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drm/i915: don't send DP "idle" pattern before "normal" on HSW PORT_A
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
09153000 419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 420
57f350b6
JB		 421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
09153000 423 return 0;
57f350b6
JB		 424 }
425
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
428 DPIO_BYTE);
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
09153000 431 return 0;
57f350b6 432 }
57f350b6 433
09153000 434 return I915_READ(DPIO_DATA);
57f350b6
JB		 435}
436
a0c4da24
JB		 437static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
438 u32 val)
439{
09153000 440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 441
a0c4da24
JB		 442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
09153000 444 return;
a0c4da24
JB		 445 }
446
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
450 DPIO_BYTE);
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 453}
454
57f350b6
JB		 455static void vlv_init_dpio(struct drm_device *dev)
456{
457 struct drm_i915_private *dev_priv = dev->dev_private;
458
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
464}
465
1b894b59
CW		 466static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
2c07245f 468{
b91ad0ec 469 struct drm_device *dev = crtc->dev;
2c07245f 470 const intel_limit_t *limit;
b91ad0ec
ZW		 471
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 473 if (intel_is_dual_link_lvds(dev)) {
b91ad0ec 474 /* LVDS dual channel */
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_dual_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_dual_lvds;
479 } else {
1b894b59 480 if (refclk == 100000)
b91ad0ec
ZW		 481 limit = &intel_limits_ironlake_single_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_single_lvds;
484 }
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 487 limit = &intel_limits_ironlake_display_port;
2c07245f 488 else
b91ad0ec 489 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 490
491 return limit;
492}
493
044c7c41
ML		 494static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
495{
496 struct drm_device *dev = crtc->dev;
044c7c41
ML		 497 const intel_limit_t *limit;
498
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 500 if (intel_is_dual_link_lvds(dev))
044c7c41 501 /* LVDS with dual channel */
e4b36699 502 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 503 else
504 /* LVDS with dual channel */
e4b36699 505 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 508 limit = &intel_limits_g4x_hdmi;
044c7c41 509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 510 limit = &intel_limits_g4x_sdvo;
0206e353 511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 512 limit = &intel_limits_g4x_display_port;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
1b894b59 519static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
523
bad720ff 524 if (HAS_PCH_SPLIT(dev))
1b894b59 525 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 526 else if (IS_G4X(dev)) {
044c7c41 527 limit = intel_g4x_limit(crtc);
f2b115e6 528 } else if (IS_PINEVIEW(dev)) {
2177832f 529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 530 limit = &intel_limits_pineview_lvds;
2177832f 531 else
f2b115e6 532 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
538 else
539 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 545 } else {
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
79e53945 548 else
e4b36699 549 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 550 }
551 return limit;
552}
553
f2b115e6
AJ		 554/* m1 is reserved as 0 in Pineview, n is a ring counter */
555static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 556{
2177832f
SL		 557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
561}
562
563static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
564{
f2b115e6
AJ		 565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
2177832f
SL		 567 return;
568 }
79e53945
JB		 569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
573}
574
79e53945
JB		 575/**
576 * Returns whether any output on the specified pipe is of the specified type
577 */
4ef69c7a 578bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 579{
4ef69c7a 580 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 581 struct intel_encoder *encoder;
582
6c2b7c12
DV		 583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
4ef69c7a
CW		 585 return true;
586
587 return false;
79e53945
JB		 588}
589
7c04d1d9 590#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 591/**
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
594 */
595
1b894b59
CW		 596static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
79e53945 599{
79e53945 600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 601 INTELPllInvalid("p1 out of range\n");
79e53945 602 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 603 INTELPllInvalid("p out of range\n");
79e53945 604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 605 INTELPllInvalid("m2 out of range\n");
79e53945 606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 607 INTELPllInvalid("m1 out of range\n");
f2b115e6 608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 609 INTELPllInvalid("m1 <= m2\n");
79e53945 610 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 611 INTELPllInvalid("m out of range\n");
79e53945 612 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 613 INTELPllInvalid("n out of range\n");
79e53945 614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 615 INTELPllInvalid("vco out of range\n");
79e53945
JB		 616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
618 */
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 620 INTELPllInvalid("dot out of range\n");
79e53945
JB		 621
622 return true;
623}
624
d4906093
ML		 625static bool
626intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
d4906093 629
79e53945
JB		 630{
631 struct drm_device *dev = crtc->dev;
79e53945 632 intel_clock_t clock;
79e53945
JB		 633 int err = target;
634
a210b028 635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 636 /*
a210b028
DV		 637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
79e53945 640 */
1974cad0 641 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
0206e353 652 memset(best_clock, 0, sizeof(*best_clock));
79e53945 653
42158660
ZY		 654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 665 int this_err;
666
2177832f 667 intel_clock(dev, refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
79e53945 670 continue;
cec2f356
SP		 671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
79e53945
JB		 674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686}
687
d4906093
ML		 688static bool
689intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
d4906093
ML		 692{
693 struct drm_device *dev = crtc->dev;
d4906093
ML		 694 intel_clock_t clock;
695 int max_n;
696 bool found;
6ba770dc
AJ		 697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 702 int lvds_reg;
703
c619eed4 704 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
1974cad0 708 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
f77f13e2 721 /* based on hardware requirement, prefer smaller n to precision */
d4906093 722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 723 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
2177832f 732 intel_clock(dev, refclk, &clock);
1b894b59
CW		 733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
d4906093 735 continue;
cec2f356
SP		 736 if (match_clock &&
737 clock.p != match_clock->p)
738 continue;
1b894b59
CW		 739
740 this_err = abs(clock.dot - target);
d4906093
ML		 741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
2c07245f
ZW		 751 return found;
752}
753
5eb08b69 754static bool
f2b115e6 755intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
5eb08b69
ZW		 758{
759 struct drm_device *dev = crtc->dev;
760 intel_clock_t clock;
4547668a 761
5eb08b69
ZW		 762 if (target < 200000) {
763 clock.n = 1;
764 clock.p1 = 2;
765 clock.p2 = 10;
766 clock.m1 = 12;
767 clock.m2 = 9;
768 } else {
769 clock.n = 2;
770 clock.p1 = 1;
771 clock.p2 = 10;
772 clock.m1 = 14;
773 clock.m2 = 8;
774 }
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
777 return true;
778}
779
a4fc5ed6
KP		 780/* DisplayPort has only two frequencies, 162MHz and 270MHz */
781static bool
782intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
a4fc5ed6 785{
5eddb70b
CW		 786 intel_clock_t clock;
787 if (target < 200000) {
788 clock.p1 = 2;
789 clock.p2 = 10;
790 clock.n = 2;
791 clock.m1 = 23;
792 clock.m2 = 8;
793 } else {
794 clock.p1 = 1;
795 clock.p2 = 10;
796 clock.n = 1;
797 clock.m1 = 14;
798 clock.m2 = 2;
799 }
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
803 clock.vco = 0;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
805 return true;
a4fc5ed6 806}
a0c4da24
JB		 807static bool
808intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811{
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
813 u32 m, n, fastclk;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
816 int dotclk, flag;
817
af447bd3 818 flag = 0;
a0c4da24
JB		 819 dotclk = target * 1000;
820 bestppm = 1000000;
821 ppm = absppm = 0;
822 fastclk = dotclk / (2*100);
823 updrate = 0;
824 minupdate = 19200;
825 fracbits = 1;
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
828
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
834 if (p2 > 10)
835 p2 = p2 - 1;
836 p = p1 * p2;
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
841 m = m1 * m2;
842 vco = updrate * m;
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
847 bestppm = 0;
848 flag = 1;
849 }
850 if (absppm < bestppm - 10) {
851 bestppm = absppm;
852 flag = 1;
853 }
854 if (flag) {
855 bestn = n;
856 bestm1 = m1;
857 bestm2 = m2;
858 bestp1 = p1;
859 bestp2 = p2;
860 flag = 0;
861 }
862 }
863 }
864 }
865 }
866 }
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
872
873 return true;
874}
a4fc5ed6 875
a5c961d1
PZ		 876enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878{
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->cpu_transcoder;
883}
884
a928d536
PZ		 885static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
886{
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
894}
895
9d0498a2
JB		 896/**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 905{
9d0498a2 906 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 907 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 908
a928d536
PZ		 909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
911 return;
912 }
913
300387c0
CW		 914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
9d0498a2 930 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
9d0498a2
JB		 934 DRM_DEBUG_KMS("vblank wait timed out\n");
935}
936
ab7ad7f6
KP		 937/*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 939 * @dev: drm device
940 * @pipe: pipe to wait for
941 *
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
945 *
ab7ad7f6
KP		 946 * On Gen4 and above:
947 * wait for the pipe register state bit to turn off
948 *
949 * Otherwise:
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
58e10eb9 952 *
9d0498a2 953 */
58e10eb9 954void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 955{
956 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 pipe);
ab7ad7f6
KP		 959
960 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 961 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 962
963 /* Wait for the Pipe State to go off */
58e10eb9
CW		 964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
284637d9 966 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 967 } else {
837ba00f 968 u32 last_line, line_mask;
58e10eb9 969 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
971
837ba00f
PZ		 972 if (IS_GEN2(dev))
973 line_mask = DSL_LINEMASK_GEN2;
974 else
975 line_mask = DSL_LINEMASK_GEN3;
976
ab7ad7f6
KP		 977 /* Wait for the display line to settle */
978 do {
837ba00f 979 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 980 mdelay(5);
837ba00f 981 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
284637d9 984 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 985 }
79e53945
JB		 986}
987
b0ea7d37
DL		 988/*
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
992 *
993 * Returns true if @port is connected, false otherwise.
994 */
995bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
997{
998 u32 bit;
999
c36346e3
DL		 1000 if (HAS_PCH_IBX(dev_priv->dev)) {
1001 switch(port->port) {
1002 case PORT_B:
1003 bit = SDE_PORTB_HOTPLUG;
1004 break;
1005 case PORT_C:
1006 bit = SDE_PORTC_HOTPLUG;
1007 break;
1008 case PORT_D:
1009 bit = SDE_PORTD_HOTPLUG;
1010 break;
1011 default:
1012 return true;
1013 }
1014 } else {
1015 switch(port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG_CPT;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG_CPT;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG_CPT;
1024 break;
1025 default:
1026 return true;
1027 }
b0ea7d37
DL		 1028 }
1029
1030 return I915_READ(SDEISR) & bit;
1031}
1032
b24e7179
JB		 1033static const char *state_string(bool enabled)
1034{
1035 return enabled ? "on" : "off";
1036}
1037
1038/* Only for pre-ILK configs */
1039static void assert_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1041{
1042 int reg;
1043 u32 val;
1044 bool cur_state;
1045
1046 reg = DPLL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & DPLL_VCO_ENABLE);
1049 WARN(cur_state != state,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1052}
1053#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
040484af
JB		 1056/* For ILK+ */
1057static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1058 struct intel_pch_pll *pll,
1059 struct intel_crtc *crtc,
1060 bool state)
040484af 1061{
040484af
JB		 1062 u32 val;
1063 bool cur_state;
1064
9d82aa17
ED		 1065 if (HAS_PCH_LPT(dev_priv->dev)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067 return;
1068 }
1069
92b27b08
CW		 1070 if (WARN (!pll,
1071 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1072 return;
ee7b9f93 1073
92b27b08
CW		 1074 val = I915_READ(pll->pll_reg);
1075 cur_state = !!(val & DPLL_VCO_ENABLE);
1076 WARN(cur_state != state,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1082 u32 pch_dpll;
1083
1084 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1085 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state, crtc->pipe, pch_dpll)) {
1089 cur_state = !!(val >> (4*crtc->pipe + 3));
1090 WARN(cur_state != state,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll->pll_reg == _PCH_DPLL_B,
1093 state_string(state),
1094 crtc->pipe,
1095 val);
1096 }
d3ccbe86 1097 }
040484af 1098}
92b27b08
CW		 1099#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
ad80a810
PZ		 1108 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 pipe);
040484af 1110
affa9354
PZ		 1111 if (HAS_DDI(dev_priv->dev)) {
1112 /* DDI does not have a specific FDI_TX register */
ad80a810 1113 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1114 val = I915_READ(reg);
ad80a810 1115 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1116 } else {
1117 reg = FDI_TX_CTL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & FDI_TX_ENABLE);
1120 }
040484af
JB		 1121 WARN(cur_state != state,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1130{
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
d63fa0dc
PZ		 1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1153 return;
1154
bf507ef7 1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1156 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1157 return;
1158
040484af
JB		 1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162}
1163
1164static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166{
1167 int reg;
1168 u32 val;
1169
1170 reg = FDI_RX_CTL(pipe);
1171 val = I915_READ(reg);
1172 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173}
1174
ea0760cf
JB		 1175static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int pp_reg, lvds_reg;
1179 u32 val;
1180 enum pipe panel_pipe = PIPE_A;
0de3b485 1181 bool locked = true;
ea0760cf
JB		 1182
1183 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184 pp_reg = PCH_PP_CONTROL;
1185 lvds_reg = PCH_LVDS;
1186 } else {
1187 pp_reg = PP_CONTROL;
1188 lvds_reg = LVDS;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197 panel_pipe = PIPE_B;
1198
1199 WARN(panel_pipe == pipe && locked,
1200 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1201 pipe_name(pipe));
ea0760cf
JB		 1202}
1203
b840d907
JB		 1204void assert_pipe(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, bool state)
b24e7179
JB		 1206{
1207 int reg;
1208 u32 val;
63d7bbe9 1209 bool cur_state;
702e7a56
PZ		 1210 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211 pipe);
b24e7179 1212
8e636784
DV		 1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215 state = true;
1216
702e7a56 1217 reg = PIPECONF(cpu_transcoder);
b24e7179 1218 val = I915_READ(reg);
63d7bbe9
JB		 1219 cur_state = !!(val & PIPECONF_ENABLE);
1220 WARN(cur_state != state,
1221 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1222 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1223}
1224
931872fc
CW		 1225static void assert_plane(struct drm_i915_private *dev_priv,
1226 enum plane plane, bool state)
b24e7179
JB		 1227{
1228 int reg;
1229 u32 val;
931872fc 1230 bool cur_state;
b24e7179
JB		 1231
1232 reg = DSPCNTR(plane);
1233 val = I915_READ(reg);
931872fc
CW		 1234 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1235 WARN(cur_state != state,
1236 "plane %c assertion failure (expected %s, current %s)\n",
1237 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1238}
1239
931872fc
CW		 1240#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1241#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1242
b24e7179
JB		 1243static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1244 enum pipe pipe)
1245{
1246 int reg, i;
1247 u32 val;
1248 int cur_pipe;
1249
19ec1358 1250 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1251 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1252 reg = DSPCNTR(pipe);
1253 val = I915_READ(reg);
1254 WARN((val & DISPLAY_PLANE_ENABLE),
1255 "plane %c assertion failure, should be disabled but not\n",
1256 plane_name(pipe));
19ec1358 1257 return;
28c05794 1258 }
19ec1358 1259
b24e7179
JB		 1260 /* Need to check both planes against the pipe */
1261 for (i = 0; i < 2; i++) {
1262 reg = DSPCNTR(i);
1263 val = I915_READ(reg);
1264 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1265 DISPPLANE_SEL_PIPE_SHIFT;
1266 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1267 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1268 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1269 }
1270}
1271
92f2584a
JB		 1272static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1273{
1274 u32 val;
1275 bool enabled;
1276
9d82aa17
ED		 1277 if (HAS_PCH_LPT(dev_priv->dev)) {
1278 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1279 return;
1280 }
1281
92f2584a
JB		 1282 val = I915_READ(PCH_DREF_CONTROL);
1283 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1284 DREF_SUPERSPREAD_SOURCE_MASK));
1285 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1286}
1287
1288static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1289 enum pipe pipe)
1290{
1291 int reg;
1292 u32 val;
1293 bool enabled;
1294
1295 reg = TRANSCONF(pipe);
1296 val = I915_READ(reg);
1297 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1298 WARN(enabled,
1299 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1300 pipe_name(pipe));
92f2584a
JB		 1301}
1302
4e634389
KP		 1303static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1305{
1306 if ((val & DP_PORT_EN) == 0)
1307 return false;
1308
1309 if (HAS_PCH_CPT(dev_priv->dev)) {
1310 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1311 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1312 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1313 return false;
1314 } else {
1315 if ((val & DP_PIPE_MASK) != (pipe << 30))
1316 return false;
1317 }
1318 return true;
1319}
1320
1519b995
KP		 1321static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, u32 val)
1323{
1324 if ((val & PORT_ENABLE) == 0)
1325 return false;
1326
1327 if (HAS_PCH_CPT(dev_priv->dev)) {
1328 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1329 return false;
1330 } else {
1331 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1332 return false;
1333 }
1334 return true;
1335}
1336
1337static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1338 enum pipe pipe, u32 val)
1339{
1340 if ((val & LVDS_PORT_EN) == 0)
1341 return false;
1342
1343 if (HAS_PCH_CPT(dev_priv->dev)) {
1344 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1345 return false;
1346 } else {
1347 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1348 return false;
1349 }
1350 return true;
1351}
1352
1353static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1354 enum pipe pipe, u32 val)
1355{
1356 if ((val & ADPA_DAC_ENABLE) == 0)
1357 return false;
1358 if (HAS_PCH_CPT(dev_priv->dev)) {
1359 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1360 return false;
1361 } else {
1362 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1363 return false;
1364 }
1365 return true;
1366}
1367
291906f1 1368static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1369 enum pipe pipe, int reg, u32 port_sel)
291906f1 1370{
47a05eca 1371 u32 val = I915_READ(reg);
4e634389 1372 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1373 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1374 reg, pipe_name(pipe));
de9a35ab 1375
75c5da27
DV		 1376 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1377 && (val & DP_PIPEB_SELECT),
de9a35ab 1378 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1379}
1380
1381static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, int reg)
1383{
47a05eca 1384 u32 val = I915_READ(reg);
b70ad586 1385 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1386 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1387 reg, pipe_name(pipe));
de9a35ab 1388
75c5da27
DV		 1389 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1390 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1391 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1392}
1393
1394static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe)
1396{
1397 int reg;
1398 u32 val;
291906f1 1399
f0575e92
KP		 1400 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1403
1404 reg = PCH_ADPA;
1405 val = I915_READ(reg);
b70ad586 1406 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1407 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1408 pipe_name(pipe));
291906f1
JB		 1409
1410 reg = PCH_LVDS;
1411 val = I915_READ(reg);
b70ad586 1412 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1413 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1414 pipe_name(pipe));
291906f1
JB		 1415
1416 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1419}
1420
63d7bbe9
JB		 1421/**
1422 * intel_enable_pll - enable a PLL
1423 * @dev_priv: i915 private structure
1424 * @pipe: pipe PLL to enable
1425 *
1426 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1427 * make sure the PLL reg is writable first though, since the panel write
1428 * protect mechanism may be enabled.
1429 *
1430 * Note! This is for pre-ILK only.
7434a255
TR		 1431 *
1432 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1433 */
1434static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1435{
1436 int reg;
1437 u32 val;
1438
1439 /* No really, not for ILK+ */
a0c4da24 1440 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1441
1442 /* PLL is protected by panel, make sure we can write it */
1443 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1444 assert_panel_unlocked(dev_priv, pipe);
1445
1446 reg = DPLL(pipe);
1447 val = I915_READ(reg);
1448 val |= DPLL_VCO_ENABLE;
1449
1450 /* We do this three times for luck */
1451 I915_WRITE(reg, val);
1452 POSTING_READ(reg);
1453 udelay(150); /* wait for warmup */
1454 I915_WRITE(reg, val);
1455 POSTING_READ(reg);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460}
1461
1462/**
1463 * intel_disable_pll - disable a PLL
1464 * @dev_priv: i915 private structure
1465 * @pipe: pipe PLL to disable
1466 *
1467 * Disable the PLL for @pipe, making sure the pipe is off first.
1468 *
1469 * Note! This is for pre-ILK only.
1470 */
1471static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1472{
1473 int reg;
1474 u32 val;
1475
1476 /* Don't disable pipe A or pipe A PLLs if needed */
1477 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1478 return;
1479
1480 /* Make sure the pipe isn't still relying on us */
1481 assert_pipe_disabled(dev_priv, pipe);
1482
1483 reg = DPLL(pipe);
1484 val = I915_READ(reg);
1485 val &= ~DPLL_VCO_ENABLE;
1486 I915_WRITE(reg, val);
1487 POSTING_READ(reg);
1488}
1489
a416edef
ED		 1490/* SBI access */
1491static void
988d6ee8
PZ		 1492intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1493 enum intel_sbi_destination destination)
a416edef 1494{
988d6ee8 1495 u32 tmp;
a416edef 1496
09153000 1497 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1498
39fb50f6 1499 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1500 100)) {
1501 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1502 return;
a416edef
ED		 1503 }
1504
988d6ee8
PZ		 1505 I915_WRITE(SBI_ADDR, (reg << 16));
1506 I915_WRITE(SBI_DATA, value);
1507
1508 if (destination == SBI_ICLK)
1509 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1510 else
1511 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1512 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1513
39fb50f6 1514 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1515 100)) {
1516 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1517 return;
a416edef 1518 }
a416edef
ED		 1519}
1520
1521static u32
988d6ee8
PZ		 1522intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1523 enum intel_sbi_destination destination)
a416edef 1524{
39fb50f6 1525 u32 value = 0;
09153000 1526 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1527
39fb50f6 1528 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1529 100)) {
1530 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1531 return 0;
a416edef
ED		 1532 }
1533
988d6ee8
PZ		 1534 I915_WRITE(SBI_ADDR, (reg << 16));
1535
1536 if (destination == SBI_ICLK)
1537 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1538 else
1539 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1540 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1541
39fb50f6 1542 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1543 100)) {
1544 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1545 return 0;
a416edef
ED		 1546 }
1547
09153000 1548 return I915_READ(SBI_DATA);
a416edef
ED		 1549}
1550
92f2584a 1551/**
b6b4e185 1552 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1553 * @dev_priv: i915 private structure
1554 * @pipe: pipe PLL to enable
1555 *
1556 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1557 * drives the transcoder clock.
1558 */
b6b4e185 1559static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1560{
ee7b9f93 1561 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1562 struct intel_pch_pll *pll;
92f2584a
JB		 1563 int reg;
1564 u32 val;
1565
48da64a8 1566 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1567 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1568 pll = intel_crtc->pch_pll;
1569 if (pll == NULL)
1570 return;
1571
1572 if (WARN_ON(pll->refcount == 0))
1573 return;
ee7b9f93
JB		 1574
1575 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1576 pll->pll_reg, pll->active, pll->on,
1577 intel_crtc->base.base.id);
92f2584a
JB		 1578
1579 /* PCH refclock must be enabled first */
1580 assert_pch_refclk_enabled(dev_priv);
1581
ee7b9f93 1582 if (pll->active++ && pll->on) {
92b27b08 1583 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1584 return;
1585 }
1586
1587 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1588
1589 reg = pll->pll_reg;
92f2584a
JB		 1590 val = I915_READ(reg);
1591 val |= DPLL_VCO_ENABLE;
1592 I915_WRITE(reg, val);
1593 POSTING_READ(reg);
1594 udelay(200);
ee7b9f93
JB		 1595
1596 pll->on = true;
92f2584a
JB		 1597}
1598
ee7b9f93 1599static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1600{
ee7b9f93
JB		 1601 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1602 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1603 int reg;
ee7b9f93 1604 u32 val;
4c609cb8 1605
92f2584a
JB		 1606 /* PCH only available on ILK+ */
1607 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1608 if (pll == NULL)
1609 return;
92f2584a 1610
48da64a8
CW		 1611 if (WARN_ON(pll->refcount == 0))
1612 return;
7a419866 1613
ee7b9f93
JB		 1614 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1615 pll->pll_reg, pll->active, pll->on,
1616 intel_crtc->base.base.id);
7a419866 1617
48da64a8 1618 if (WARN_ON(pll->active == 0)) {
92b27b08 1619 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1620 return;
1621 }
1622
ee7b9f93 1623 if (--pll->active) {
92b27b08 1624 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1625 return;
ee7b9f93
JB		 1626 }
1627
1628 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1629
1630 /* Make sure transcoder isn't still depending on us */
1631 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1632
ee7b9f93 1633 reg = pll->pll_reg;
92f2584a
JB		 1634 val = I915_READ(reg);
1635 val &= ~DPLL_VCO_ENABLE;
1636 I915_WRITE(reg, val);
1637 POSTING_READ(reg);
1638 udelay(200);
ee7b9f93
JB		 1639
1640 pll->on = false;
92f2584a
JB		 1641}
1642
b8a4f404
PZ		 1643static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1644 enum pipe pipe)
040484af 1645{
23670b32 1646 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1647 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1648 uint32_t reg, val, pipeconf_val;
040484af
JB		 1649
1650 /* PCH only available on ILK+ */
1651 BUG_ON(dev_priv->info->gen < 5);
1652
1653 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1654 assert_pch_pll_enabled(dev_priv,
1655 to_intel_crtc(crtc)->pch_pll,
1656 to_intel_crtc(crtc));
040484af
JB		 1657
1658 /* FDI must be feeding us bits for PCH ports */
1659 assert_fdi_tx_enabled(dev_priv, pipe);
1660 assert_fdi_rx_enabled(dev_priv, pipe);
1661
23670b32
DV		 1662 if (HAS_PCH_CPT(dev)) {
1663 /* Workaround: Set the timing override bit before enabling the
1664 * pch transcoder. */
1665 reg = TRANS_CHICKEN2(pipe);
1666 val = I915_READ(reg);
1667 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1668 I915_WRITE(reg, val);
59c859d6 1669 }
23670b32 1670
040484af
JB		 1671 reg = TRANSCONF(pipe);
1672 val = I915_READ(reg);
5f7f726d 1673 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1674
1675 if (HAS_PCH_IBX(dev_priv->dev)) {
1676 /*
1677 * make the BPC in transcoder be consistent with
1678 * that in pipeconf reg.
1679 */
dfd07d72
DV		 1680 val &= ~PIPECONF_BPC_MASK;
1681 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1682 }
5f7f726d
PZ		 1683
1684 val &= ~TRANS_INTERLACE_MASK;
1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1686 if (HAS_PCH_IBX(dev_priv->dev) &&
1687 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1688 val |= TRANS_LEGACY_INTERLACED_ILK;
1689 else
1690 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1691 else
1692 val |= TRANS_PROGRESSIVE;
1693
040484af
JB		 1694 I915_WRITE(reg, val | TRANS_ENABLE);
1695 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1696 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1697}
1698
8fb033d7 1699static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1700 enum transcoder cpu_transcoder)
040484af 1701{
8fb033d7 1702 u32 val, pipeconf_val;
8fb033d7
PZ		 1703
1704 /* PCH only available on ILK+ */
1705 BUG_ON(dev_priv->info->gen < 5);
1706
8fb033d7 1707 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1708 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1709 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1710
223a6fdf
PZ		 1711 /* Workaround: set timing override bit. */
1712 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1713 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1714 I915_WRITE(_TRANSA_CHICKEN2, val);
1715
25f3ef11 1716 val = TRANS_ENABLE;
937bb610 1717 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1718
9a76b1c6
PZ		 1719 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1720 PIPECONF_INTERLACED_ILK)
a35f2679 1721 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1722 else
1723 val |= TRANS_PROGRESSIVE;
1724
25f3ef11 1725 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1726 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1727 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1728}
1729
b8a4f404
PZ		 1730static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1731 enum pipe pipe)
040484af 1732{
23670b32
DV		 1733 struct drm_device *dev = dev_priv->dev;
1734 uint32_t reg, val;
040484af
JB		 1735
1736 /* FDI relies on the transcoder */
1737 assert_fdi_tx_disabled(dev_priv, pipe);
1738 assert_fdi_rx_disabled(dev_priv, pipe);
1739
291906f1
JB		 1740 /* Ports must be off as well */
1741 assert_pch_ports_disabled(dev_priv, pipe);
1742
040484af
JB		 1743 reg = TRANSCONF(pipe);
1744 val = I915_READ(reg);
1745 val &= ~TRANS_ENABLE;
1746 I915_WRITE(reg, val);
1747 /* wait for PCH transcoder off, transcoder state */
1748 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1749 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1750
1751 if (!HAS_PCH_IBX(dev)) {
1752 /* Workaround: Clear the timing override chicken bit again. */
1753 reg = TRANS_CHICKEN2(pipe);
1754 val = I915_READ(reg);
1755 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1756 I915_WRITE(reg, val);
1757 }
040484af
JB		 1758}
1759
ab4d966c 1760static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1761{
8fb033d7
PZ		 1762 u32 val;
1763
8a52fd9f 1764 val = I915_READ(_TRANSACONF);
8fb033d7 1765 val &= ~TRANS_ENABLE;
8a52fd9f 1766 I915_WRITE(_TRANSACONF, val);
8fb033d7 1767 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1768 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1769 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1770
1771 /* Workaround: clear timing override bit. */
1772 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1773 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1774 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1775}
1776
b24e7179 1777/**
309cfea8 1778 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1779 * @dev_priv: i915 private structure
1780 * @pipe: pipe to enable
040484af 1781 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1782 *
1783 * Enable @pipe, making sure that various hardware specific requirements
1784 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1785 *
1786 * @pipe should be %PIPE_A or %PIPE_B.
1787 *
1788 * Will wait until the pipe is actually running (i.e. first vblank) before
1789 * returning.
1790 */
040484af
JB		 1791static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1792 bool pch_port)
b24e7179 1793{
702e7a56
PZ		 1794 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1795 pipe);
1a240d4d 1796 enum pipe pch_transcoder;
b24e7179
JB		 1797 int reg;
1798 u32 val;
1799
681e5811 1800 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1801 pch_transcoder = TRANSCODER_A;
1802 else
1803 pch_transcoder = pipe;
1804
b24e7179
JB		 1805 /*
1806 * A pipe without a PLL won't actually be able to drive bits from
1807 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1808 * need the check.
1809 */
1810 if (!HAS_PCH_SPLIT(dev_priv->dev))
1811 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1812 else {
1813 if (pch_port) {
1814 /* if driving the PCH, we need FDI enabled */
cc391bbb 1815 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1816 assert_fdi_tx_pll_enabled(dev_priv,
1817 (enum pipe) cpu_transcoder);
040484af
JB		 1818 }
1819 /* FIXME: assert CPU port conditions for SNB+ */
1820 }
b24e7179 1821
702e7a56 1822 reg = PIPECONF(cpu_transcoder);
b24e7179 1823 val = I915_READ(reg);
00d70b15
CW		 1824 if (val & PIPECONF_ENABLE)
1825 return;
1826
1827 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1828 intel_wait_for_vblank(dev_priv->dev, pipe);
1829}
1830
1831/**
309cfea8 1832 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1833 * @dev_priv: i915 private structure
1834 * @pipe: pipe to disable
1835 *
1836 * Disable @pipe, making sure that various hardware specific requirements
1837 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1838 *
1839 * @pipe should be %PIPE_A or %PIPE_B.
1840 *
1841 * Will wait until the pipe has shut down before returning.
1842 */
1843static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1844 enum pipe pipe)
1845{
702e7a56
PZ		 1846 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1847 pipe);
b24e7179
JB		 1848 int reg;
1849 u32 val;
1850
1851 /*
1852 * Make sure planes won't keep trying to pump pixels to us,
1853 * or we might hang the display.
1854 */
1855 assert_planes_disabled(dev_priv, pipe);
1856
1857 /* Don't disable pipe A or pipe A PLLs if needed */
1858 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1859 return;
1860
702e7a56 1861 reg = PIPECONF(cpu_transcoder);
b24e7179 1862 val = I915_READ(reg);
00d70b15
CW		 1863 if ((val & PIPECONF_ENABLE) == 0)
1864 return;
1865
1866 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1867 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1868}
1869
d74362c9
KP		 1870/*
1871 * Plane regs are double buffered, going from enabled->disabled needs a
1872 * trigger in order to latch. The display address reg provides this.
1873 */
6f1d69b0 1874void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1875 enum plane plane)
1876{
14f86147
DL		 1877 if (dev_priv->info->gen >= 4)
1878 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1879 else
1880 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1881}
1882
b24e7179
JB		 1883/**
1884 * intel_enable_plane - enable a display plane on a given pipe
1885 * @dev_priv: i915 private structure
1886 * @plane: plane to enable
1887 * @pipe: pipe being fed
1888 *
1889 * Enable @plane on @pipe, making sure that @pipe is running first.
1890 */
1891static void intel_enable_plane(struct drm_i915_private *dev_priv,
1892 enum plane plane, enum pipe pipe)
1893{
1894 int reg;
1895 u32 val;
1896
1897 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1898 assert_pipe_enabled(dev_priv, pipe);
1899
1900 reg = DSPCNTR(plane);
1901 val = I915_READ(reg);
00d70b15
CW		 1902 if (val & DISPLAY_PLANE_ENABLE)
1903 return;
1904
1905 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1906 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1907 intel_wait_for_vblank(dev_priv->dev, pipe);
1908}
1909
b24e7179
JB		 1910/**
1911 * intel_disable_plane - disable a display plane
1912 * @dev_priv: i915 private structure
1913 * @plane: plane to disable
1914 * @pipe: pipe consuming the data
1915 *
1916 * Disable @plane; should be an independent operation.
1917 */
1918static void intel_disable_plane(struct drm_i915_private *dev_priv,
1919 enum plane plane, enum pipe pipe)
1920{
1921 int reg;
1922 u32 val;
1923
1924 reg = DSPCNTR(plane);
1925 val = I915_READ(reg);
00d70b15
CW		 1926 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1927 return;
1928
1929 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1930 intel_flush_display_plane(dev_priv, plane);
1931 intel_wait_for_vblank(dev_priv->dev, pipe);
1932}
1933
127bd2ac 1934int
48b956c5 1935intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1936 struct drm_i915_gem_object *obj,
919926ae 1937 struct intel_ring_buffer *pipelined)
6b95a207 1938{
ce453d81 1939 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1940 u32 alignment;
1941 int ret;
1942
05394f39 1943 switch (obj->tiling_mode) {
6b95a207 1944 case I915_TILING_NONE:
534843da
CW		 1945 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1946 alignment = 128 * 1024;
a6c45cf0 1947 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1948 alignment = 4 * 1024;
1949 else
1950 alignment = 64 * 1024;
6b95a207
KH		 1951 break;
1952 case I915_TILING_X:
1953 /* pin() will align the object as required by fence */
1954 alignment = 0;
1955 break;
1956 case I915_TILING_Y:
1957 /* FIXME: Is this true? */
1958 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1959 return -EINVAL;
1960 default:
1961 BUG();
1962 }
1963
ce453d81 1964 dev_priv->mm.interruptible = false;
2da3b9b9 1965 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1966 if (ret)
ce453d81 1967 goto err_interruptible;
6b95a207
KH		 1968
1969 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1970 * fence, whereas 965+ only requires a fence if using
1971 * framebuffer compression. For simplicity, we always install
1972 * a fence as the cost is not that onerous.
1973 */
06d98131 1974 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1975 if (ret)
1976 goto err_unpin;
1690e1eb 1977
9a5a53b3 1978 i915_gem_object_pin_fence(obj);
6b95a207 1979
ce453d81 1980 dev_priv->mm.interruptible = true;
6b95a207 1981 return 0;
48b956c5
CW		 1982
1983err_unpin:
1984 i915_gem_object_unpin(obj);
ce453d81
CW		 1985err_interruptible:
1986 dev_priv->mm.interruptible = true;
48b956c5 1987 return ret;
6b95a207
KH		 1988}
1989
1690e1eb
CW		 1990void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1991{
1992 i915_gem_object_unpin_fence(obj);
1993 i915_gem_object_unpin(obj);
1994}
1995
c2c75131
DV		 1996/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1997 * is assumed to be a power-of-two. */
5a35e99e
DL		 1998unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1999 unsigned int bpp,
2000 unsigned int pitch)
c2c75131
DV		 2001{
2002 int tile_rows, tiles;
2003
2004 tile_rows = *y / 8;
2005 *y %= 8;
2006 tiles = *x / (512/bpp);
2007 *x %= 512/bpp;
2008
2009 return tile_rows * pitch * 8 + tiles * 4096;
2010}
2011
17638cd6
JB		 2012static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2013 int x, int y)
81255565
JB		 2014{
2015 struct drm_device *dev = crtc->dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2018 struct intel_framebuffer *intel_fb;
05394f39 2019 struct drm_i915_gem_object *obj;
81255565 2020 int plane = intel_crtc->plane;
e506a0c6 2021 unsigned long linear_offset;
81255565 2022 u32 dspcntr;
5eddb70b 2023 u32 reg;
81255565
JB		 2024
2025 switch (plane) {
2026 case 0:
2027 case 1:
2028 break;
2029 default:
2030 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2031 return -EINVAL;
2032 }
2033
2034 intel_fb = to_intel_framebuffer(fb);
2035 obj = intel_fb->obj;
81255565 2036
5eddb70b
CW		 2037 reg = DSPCNTR(plane);
2038 dspcntr = I915_READ(reg);
81255565
JB		 2039 /* Mask out pixel format bits in case we change it */
2040 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2041 switch (fb->pixel_format) {
2042 case DRM_FORMAT_C8:
81255565
JB		 2043 dspcntr |= DISPPLANE_8BPP;
2044 break;
57779d06
VS		 2045 case DRM_FORMAT_XRGB1555:
2046 case DRM_FORMAT_ARGB1555:
2047 dspcntr |= DISPPLANE_BGRX555;
81255565 2048 break;
57779d06
VS		 2049 case DRM_FORMAT_RGB565:
2050 dspcntr |= DISPPLANE_BGRX565;
2051 break;
2052 case DRM_FORMAT_XRGB8888:
2053 case DRM_FORMAT_ARGB8888:
2054 dspcntr |= DISPPLANE_BGRX888;
2055 break;
2056 case DRM_FORMAT_XBGR8888:
2057 case DRM_FORMAT_ABGR8888:
2058 dspcntr |= DISPPLANE_RGBX888;
2059 break;
2060 case DRM_FORMAT_XRGB2101010:
2061 case DRM_FORMAT_ARGB2101010:
2062 dspcntr |= DISPPLANE_BGRX101010;
2063 break;
2064 case DRM_FORMAT_XBGR2101010:
2065 case DRM_FORMAT_ABGR2101010:
2066 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2067 break;
2068 default:
57779d06 2069 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2070 return -EINVAL;
2071 }
57779d06 2072
a6c45cf0 2073 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2074 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2075 dspcntr |= DISPPLANE_TILED;
2076 else
2077 dspcntr &= ~DISPPLANE_TILED;
2078 }
2079
5eddb70b 2080 I915_WRITE(reg, dspcntr);
81255565 2081
e506a0c6 2082 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2083
c2c75131
DV		 2084 if (INTEL_INFO(dev)->gen >= 4) {
2085 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2086 intel_gen4_compute_offset_xtiled(&x, &y,
2087 fb->bits_per_pixel / 8,
2088 fb->pitches[0]);
c2c75131
DV		 2089 linear_offset -= intel_crtc->dspaddr_offset;
2090 } else {
e506a0c6 2091 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2092 }
e506a0c6
DV		 2093
2094 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2095 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2096 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2097 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2098 I915_MODIFY_DISPBASE(DSPSURF(plane),
2099 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2100 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2101 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2102 } else
e506a0c6 2103 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2104 POSTING_READ(reg);
81255565 2105
17638cd6
JB		 2106 return 0;
2107}
2108
2109static int ironlake_update_plane(struct drm_crtc *crtc,
2110 struct drm_framebuffer *fb, int x, int y)
2111{
2112 struct drm_device *dev = crtc->dev;
2113 struct drm_i915_private *dev_priv = dev->dev_private;
2114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2115 struct intel_framebuffer *intel_fb;
2116 struct drm_i915_gem_object *obj;
2117 int plane = intel_crtc->plane;
e506a0c6 2118 unsigned long linear_offset;
17638cd6
JB		 2119 u32 dspcntr;
2120 u32 reg;
2121
2122 switch (plane) {
2123 case 0:
2124 case 1:
27f8227b 2125 case 2:
17638cd6
JB		 2126 break;
2127 default:
2128 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2129 return -EINVAL;
2130 }
2131
2132 intel_fb = to_intel_framebuffer(fb);
2133 obj = intel_fb->obj;
2134
2135 reg = DSPCNTR(plane);
2136 dspcntr = I915_READ(reg);
2137 /* Mask out pixel format bits in case we change it */
2138 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2139 switch (fb->pixel_format) {
2140 case DRM_FORMAT_C8:
17638cd6
JB		 2141 dspcntr |= DISPPLANE_8BPP;
2142 break;
57779d06
VS		 2143 case DRM_FORMAT_RGB565:
2144 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2145 break;
57779d06
VS		 2146 case DRM_FORMAT_XRGB8888:
2147 case DRM_FORMAT_ARGB8888:
2148 dspcntr |= DISPPLANE_BGRX888;
2149 break;
2150 case DRM_FORMAT_XBGR8888:
2151 case DRM_FORMAT_ABGR8888:
2152 dspcntr |= DISPPLANE_RGBX888;
2153 break;
2154 case DRM_FORMAT_XRGB2101010:
2155 case DRM_FORMAT_ARGB2101010:
2156 dspcntr |= DISPPLANE_BGRX101010;
2157 break;
2158 case DRM_FORMAT_XBGR2101010:
2159 case DRM_FORMAT_ABGR2101010:
2160 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2161 break;
2162 default:
57779d06 2163 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2164 return -EINVAL;
2165 }
2166
2167 if (obj->tiling_mode != I915_TILING_NONE)
2168 dspcntr |= DISPPLANE_TILED;
2169 else
2170 dspcntr &= ~DISPPLANE_TILED;
2171
2172 /* must disable */
2173 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2174
2175 I915_WRITE(reg, dspcntr);
2176
e506a0c6 2177 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2178 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2179 intel_gen4_compute_offset_xtiled(&x, &y,
2180 fb->bits_per_pixel / 8,
2181 fb->pitches[0]);
c2c75131 2182 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2183
e506a0c6
DV		 2184 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2185 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2186 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2187 I915_MODIFY_DISPBASE(DSPSURF(plane),
2188 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2189 if (IS_HASWELL(dev)) {
2190 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2191 } else {
2192 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2193 I915_WRITE(DSPLINOFF(plane), linear_offset);
2194 }
17638cd6
JB		 2195 POSTING_READ(reg);
2196
2197 return 0;
2198}
2199
2200/* Assume fb object is pinned & idle & fenced and just update base pointers */
2201static int
2202intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2203 int x, int y, enum mode_set_atomic state)
2204{
2205 struct drm_device *dev = crtc->dev;
2206 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2207
6b8e6ed0
CW		 2208 if (dev_priv->display.disable_fbc)
2209 dev_priv->display.disable_fbc(dev);
3dec0095 2210 intel_increase_pllclock(crtc);
81255565 2211
6b8e6ed0 2212 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2213}
2214
14667a4b
CW		 2215static int
2216intel_finish_fb(struct drm_framebuffer *old_fb)
2217{
2218 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2219 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2220 bool was_interruptible = dev_priv->mm.interruptible;
2221 int ret;
2222
2c10d571
DV		 2223 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2224
14667a4b 2225 wait_event(dev_priv->pending_flip_queue,
1f83fee0 2226 i915_reset_in_progress(&dev_priv->gpu_error) ||
14667a4b
CW		 2227 atomic_read(&obj->pending_flip) == 0);
2228
2229 /* Big Hammer, we also need to ensure that any pending
2230 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2231 * current scanout is retired before unpinning the old
2232 * framebuffer.
2233 *
2234 * This should only fail upon a hung GPU, in which case we
2235 * can safely continue.
2236 */
2237 dev_priv->mm.interruptible = false;
2238 ret = i915_gem_object_finish_gpu(obj);
2239 dev_priv->mm.interruptible = was_interruptible;
2240
2241 return ret;
2242}
2243
198598d0
VS		 2244static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2245{
2246 struct drm_device *dev = crtc->dev;
2247 struct drm_i915_master_private *master_priv;
2248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2249
2250 if (!dev->primary->master)
2251 return;
2252
2253 master_priv = dev->primary->master->driver_priv;
2254 if (!master_priv->sarea_priv)
2255 return;
2256
2257 switch (intel_crtc->pipe) {
2258 case 0:
2259 master_priv->sarea_priv->pipeA_x = x;
2260 master_priv->sarea_priv->pipeA_y = y;
2261 break;
2262 case 1:
2263 master_priv->sarea_priv->pipeB_x = x;
2264 master_priv->sarea_priv->pipeB_y = y;
2265 break;
2266 default:
2267 break;
2268 }
2269}
2270
5c3b82e2 2271static int
3c4fdcfb 2272intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2273 struct drm_framebuffer *fb)
79e53945
JB		 2274{
2275 struct drm_device *dev = crtc->dev;
6b8e6ed0 2276 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2278 struct drm_framebuffer *old_fb;
5c3b82e2 2279 int ret;
79e53945
JB		 2280
2281 /* no fb bound */
94352cf9 2282 if (!fb) {
a5071c2f 2283 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2284 return 0;
2285 }
2286
5826eca5
ED		 2287 if(intel_crtc->plane > dev_priv->num_pipe) {
2288 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2289 intel_crtc->plane,
2290 dev_priv->num_pipe);
5c3b82e2 2291 return -EINVAL;
79e53945
JB		 2292 }
2293
5c3b82e2 2294 mutex_lock(&dev->struct_mutex);
265db958 2295 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2296 to_intel_framebuffer(fb)->obj,
919926ae 2297 NULL);
5c3b82e2
CW		 2298 if (ret != 0) {
2299 mutex_unlock(&dev->struct_mutex);
a5071c2f 2300 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2301 return ret;
2302 }
79e53945 2303
94352cf9
DV		 2304 if (crtc->fb)
2305 intel_finish_fb(crtc->fb);
265db958 2306
94352cf9 2307 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2308 if (ret) {
94352cf9 2309 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2310 mutex_unlock(&dev->struct_mutex);
a5071c2f 2311 DRM_ERROR("failed to update base address\n");
4e6cfefc 2312 return ret;
79e53945 2313 }
3c4fdcfb 2314
94352cf9
DV		 2315 old_fb = crtc->fb;
2316 crtc->fb = fb;
6c4c86f5
DV		 2317 crtc->x = x;
2318 crtc->y = y;
94352cf9 2319
b7f1de28
CW		 2320 if (old_fb) {
2321 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2322 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2323 }
652c393a 2324
6b8e6ed0 2325 intel_update_fbc(dev);
5c3b82e2 2326 mutex_unlock(&dev->struct_mutex);
79e53945 2327
198598d0 2328 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2329
2330 return 0;
79e53945
JB		 2331}
2332
5e84e1a4
ZW		 2333static void intel_fdi_normal_train(struct drm_crtc *crtc)
2334{
2335 struct drm_device *dev = crtc->dev;
2336 struct drm_i915_private *dev_priv = dev->dev_private;
2337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2338 int pipe = intel_crtc->pipe;
2339 u32 reg, temp;
2340
2341 /* enable normal train */
2342 reg = FDI_TX_CTL(pipe);
2343 temp = I915_READ(reg);
61e499bf 2344 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2345 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2346 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2347 } else {
2348 temp &= ~FDI_LINK_TRAIN_NONE;
2349 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2350 }
5e84e1a4
ZW		 2351 I915_WRITE(reg, temp);
2352
2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
2355 if (HAS_PCH_CPT(dev)) {
2356 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2357 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2358 } else {
2359 temp &= ~FDI_LINK_TRAIN_NONE;
2360 temp |= FDI_LINK_TRAIN_NONE;
2361 }
2362 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2363
2364 /* wait one idle pattern time */
2365 POSTING_READ(reg);
2366 udelay(1000);
357555c0
JB		 2367
2368 /* IVB wants error correction enabled */
2369 if (IS_IVYBRIDGE(dev))
2370 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2371 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2372}
2373
01a415fd
DV		 2374static void ivb_modeset_global_resources(struct drm_device *dev)
2375{
2376 struct drm_i915_private *dev_priv = dev->dev_private;
2377 struct intel_crtc *pipe_B_crtc =
2378 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2379 struct intel_crtc *pipe_C_crtc =
2380 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2381 uint32_t temp;
2382
2383 /* When everything is off disable fdi C so that we could enable fdi B
2384 * with all lanes. XXX: This misses the case where a pipe is not using
2385 * any pch resources and so doesn't need any fdi lanes. */
2386 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2387 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2389
2390 temp = I915_READ(SOUTH_CHICKEN1);
2391 temp &= ~FDI_BC_BIFURCATION_SELECT;
2392 DRM_DEBUG_KMS("disabling fdi C rx\n");
2393 I915_WRITE(SOUTH_CHICKEN1, temp);
2394 }
2395}
2396
8db9d77b
ZW		 2397/* The FDI link training functions for ILK/Ibexpeak. */
2398static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2399{
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
0fc932b8 2404 int plane = intel_crtc->plane;
5eddb70b 2405 u32 reg, temp, tries;
8db9d77b 2406
0fc932b8
JB		 2407 /* FDI needs bits from pipe & plane first */
2408 assert_pipe_enabled(dev_priv, pipe);
2409 assert_plane_enabled(dev_priv, plane);
2410
e1a44743
AJ		 2411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2412 for train result */
5eddb70b
CW		 2413 reg = FDI_RX_IMR(pipe);
2414 temp = I915_READ(reg);
e1a44743
AJ		 2415 temp &= ~FDI_RX_SYMBOL_LOCK;
2416 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2417 I915_WRITE(reg, temp);
2418 I915_READ(reg);
e1a44743
AJ		 2419 udelay(150);
2420
8db9d77b 2421 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
77ffb597
AJ		 2424 temp &= ~(7 << 19);
2425 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2428 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2429
5eddb70b
CW		 2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2434 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2435
2436 POSTING_READ(reg);
8db9d77b
ZW		 2437 udelay(150);
2438
5b2adf89 2439 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2440 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2441 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2442 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2443
5eddb70b 2444 reg = FDI_RX_IIR(pipe);
e1a44743 2445 for (tries = 0; tries < 5; tries++) {
5eddb70b 2446 temp = I915_READ(reg);
8db9d77b
ZW		 2447 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2448
2449 if ((temp & FDI_RX_BIT_LOCK)) {
2450 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2452 break;
2453 }
8db9d77b 2454 }
e1a44743 2455 if (tries == 5)
5eddb70b 2456 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2457
2458 /* Train 2 */
5eddb70b
CW		 2459 reg = FDI_TX_CTL(pipe);
2460 temp = I915_READ(reg);
8db9d77b
ZW		 2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2463 I915_WRITE(reg, temp);
8db9d77b 2464
5eddb70b
CW		 2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 POSTING_READ(reg);
2472 udelay(150);
8db9d77b 2473
5eddb70b 2474 reg = FDI_RX_IIR(pipe);
e1a44743 2475 for (tries = 0; tries < 5; tries++) {
5eddb70b 2476 temp = I915_READ(reg);
8db9d77b
ZW		 2477 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2478
2479 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2480 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2481 DRM_DEBUG_KMS("FDI train 2 done.\n");
2482 break;
2483 }
8db9d77b 2484 }
e1a44743 2485 if (tries == 5)
5eddb70b 2486 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2487
2488 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2489
8db9d77b
ZW		 2490}
2491
0206e353 2492static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2493 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2494 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2495 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2496 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2497};
2498
2499/* The FDI link training functions for SNB/Cougarpoint. */
2500static void gen6_fdi_link_train(struct drm_crtc *crtc)
2501{
2502 struct drm_device *dev = crtc->dev;
2503 struct drm_i915_private *dev_priv = dev->dev_private;
2504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2505 int pipe = intel_crtc->pipe;
fa37d39e 2506 u32 reg, temp, i, retry;
8db9d77b 2507
e1a44743
AJ		 2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509 for train result */
5eddb70b
CW		 2510 reg = FDI_RX_IMR(pipe);
2511 temp = I915_READ(reg);
e1a44743
AJ		 2512 temp &= ~FDI_RX_SYMBOL_LOCK;
2513 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
e1a44743
AJ		 2517 udelay(150);
2518
8db9d77b 2519 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
77ffb597
AJ		 2522 temp &= ~(7 << 19);
2523 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_1;
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 /* SNB-B */
2528 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2529 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2530
d74cf324
DV		 2531 I915_WRITE(FDI_RX_MISC(pipe),
2532 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2533
5eddb70b
CW		 2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2539 } else {
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_1;
2542 }
5eddb70b
CW		 2543 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2544
2545 POSTING_READ(reg);
8db9d77b
ZW		 2546 udelay(150);
2547
0206e353 2548 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
8db9d77b
ZW		 2551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2553 I915_WRITE(reg, temp);
2554
2555 POSTING_READ(reg);
8db9d77b
ZW		 2556 udelay(500);
2557
fa37d39e
SP		 2558 for (retry = 0; retry < 5; retry++) {
2559 reg = FDI_RX_IIR(pipe);
2560 temp = I915_READ(reg);
2561 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562 if (temp & FDI_RX_BIT_LOCK) {
2563 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2564 DRM_DEBUG_KMS("FDI train 1 done.\n");
2565 break;
2566 }
2567 udelay(50);
8db9d77b 2568 }
fa37d39e
SP		 2569 if (retry < 5)
2570 break;
8db9d77b
ZW		 2571 }
2572 if (i == 4)
5eddb70b 2573 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2574
2575 /* Train 2 */
5eddb70b
CW		 2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
8db9d77b
ZW		 2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2580 if (IS_GEN6(dev)) {
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 /* SNB-B */
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584 }
5eddb70b 2585 I915_WRITE(reg, temp);
8db9d77b 2586
5eddb70b
CW		 2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
8db9d77b
ZW		 2589 if (HAS_PCH_CPT(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2592 } else {
2593 temp &= ~FDI_LINK_TRAIN_NONE;
2594 temp |= FDI_LINK_TRAIN_PATTERN_2;
2595 }
5eddb70b
CW		 2596 I915_WRITE(reg, temp);
2597
2598 POSTING_READ(reg);
8db9d77b
ZW		 2599 udelay(150);
2600
0206e353 2601 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
8db9d77b
ZW		 2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
8db9d77b
ZW		 2609 udelay(500);
2610
fa37d39e
SP		 2611 for (retry = 0; retry < 5; retry++) {
2612 reg = FDI_RX_IIR(pipe);
2613 temp = I915_READ(reg);
2614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2615 if (temp & FDI_RX_SYMBOL_LOCK) {
2616 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2617 DRM_DEBUG_KMS("FDI train 2 done.\n");
2618 break;
2619 }
2620 udelay(50);
8db9d77b 2621 }
fa37d39e
SP		 2622 if (retry < 5)
2623 break;
8db9d77b
ZW		 2624 }
2625 if (i == 4)
5eddb70b 2626 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2627
2628 DRM_DEBUG_KMS("FDI train done.\n");
2629}
2630
357555c0
JB		 2631/* Manual link training for Ivy Bridge A0 parts */
2632static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2633{
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
2638 u32 reg, temp, i;
2639
2640 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2641 for train result */
2642 reg = FDI_RX_IMR(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_RX_SYMBOL_LOCK;
2645 temp &= ~FDI_RX_BIT_LOCK;
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(150);
2650
01a415fd
DV		 2651 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2652 I915_READ(FDI_RX_IIR(pipe)));
2653
357555c0
JB		 2654 /* enable CPU FDI TX and PCH FDI RX */
2655 reg = FDI_TX_CTL(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~(7 << 19);
2658 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2659 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2663 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2665
d74cf324
DV		 2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2668
357555c0
JB		 2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2674 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2675 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2676
2677 POSTING_READ(reg);
2678 udelay(150);
2679
0206e353 2680 for (i = 0; i < 4; i++) {
357555c0
JB		 2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684 temp |= snb_b_fdi_train_param[i];
2685 I915_WRITE(reg, temp);
2686
2687 POSTING_READ(reg);
2688 udelay(500);
2689
2690 reg = FDI_RX_IIR(pipe);
2691 temp = I915_READ(reg);
2692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2693
2694 if (temp & FDI_RX_BIT_LOCK ||
2695 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2696 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2697 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2698 break;
2699 }
2700 }
2701 if (i == 4)
2702 DRM_ERROR("FDI train 1 fail!\n");
2703
2704 /* Train 2 */
2705 reg = FDI_TX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2711 I915_WRITE(reg, temp);
2712
2713 reg = FDI_RX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2717 I915_WRITE(reg, temp);
2718
2719 POSTING_READ(reg);
2720 udelay(150);
2721
0206e353 2722 for (i = 0; i < 4; i++) {
357555c0
JB		 2723 reg = FDI_TX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= snb_b_fdi_train_param[i];
2727 I915_WRITE(reg, temp);
2728
2729 POSTING_READ(reg);
2730 udelay(500);
2731
2732 reg = FDI_RX_IIR(pipe);
2733 temp = I915_READ(reg);
2734 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2735
2736 if (temp & FDI_RX_SYMBOL_LOCK) {
2737 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2738 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2739 break;
2740 }
2741 }
2742 if (i == 4)
2743 DRM_ERROR("FDI train 2 fail!\n");
2744
2745 DRM_DEBUG_KMS("FDI train done.\n");
2746}
2747
88cefb6c 2748static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2749{
88cefb6c 2750 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2751 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2752 int pipe = intel_crtc->pipe;
5eddb70b 2753 u32 reg, temp;
79e53945 2754
c64e311e 2755
c98e9dcf 2756 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
2759 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2760 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2761 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2762 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2763
2764 POSTING_READ(reg);
c98e9dcf
JB		 2765 udelay(200);
2766
2767 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp | FDI_PCDCLK);
2770
2771 POSTING_READ(reg);
c98e9dcf
JB		 2772 udelay(200);
2773
20749730
PZ		 2774 /* Enable CPU FDI TX PLL, always on for Ironlake */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2778 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2779
20749730
PZ		 2780 POSTING_READ(reg);
2781 udelay(100);
6be4a607 2782 }
0e23b99d
JB		 2783}
2784
88cefb6c
DV		 2785static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2786{
2787 struct drm_device *dev = intel_crtc->base.dev;
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 int pipe = intel_crtc->pipe;
2790 u32 reg, temp;
2791
2792 /* Switch from PCDclk to Rawclk */
2793 reg = FDI_RX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2796
2797 /* Disable CPU FDI TX PLL */
2798 reg = FDI_TX_CTL(pipe);
2799 temp = I915_READ(reg);
2800 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2801
2802 POSTING_READ(reg);
2803 udelay(100);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2808
2809 /* Wait for the clocks to turn off. */
2810 POSTING_READ(reg);
2811 udelay(100);
2812}
2813
0fc932b8
JB		 2814static void ironlake_fdi_disable(struct drm_crtc *crtc)
2815{
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2820 u32 reg, temp;
2821
2822 /* disable CPU FDI tx and PCH FDI rx */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2826 POSTING_READ(reg);
2827
2828 reg = FDI_RX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 temp &= ~(0x7 << 16);
dfd07d72 2831 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2832 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2833
2834 POSTING_READ(reg);
2835 udelay(100);
2836
2837 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2838 if (HAS_PCH_IBX(dev)) {
2839 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2840 }
0fc932b8
JB		 2841
2842 /* still set train pattern 1 */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1;
2847 I915_WRITE(reg, temp);
2848
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if (HAS_PCH_CPT(dev)) {
2852 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2854 } else {
2855 temp &= ~FDI_LINK_TRAIN_NONE;
2856 temp |= FDI_LINK_TRAIN_PATTERN_1;
2857 }
2858 /* BPC in FDI rx is consistent with that in PIPECONF */
2859 temp &= ~(0x07 << 16);
dfd07d72 2860 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2861 I915_WRITE(reg, temp);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865}
2866
5bb61643
CW		 2867static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2868{
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
2871 unsigned long flags;
2872 bool pending;
2873
1f83fee0 2874 if (i915_reset_in_progress(&dev_priv->gpu_error))
5bb61643
CW		 2875 return false;
2876
2877 spin_lock_irqsave(&dev->event_lock, flags);
2878 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2879 spin_unlock_irqrestore(&dev->event_lock, flags);
2880
2881 return pending;
2882}
2883
e6c3a2a6
CW		 2884static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2885{
0f91128d 2886 struct drm_device *dev = crtc->dev;
5bb61643 2887 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2888
2889 if (crtc->fb == NULL)
2890 return;
2891
2c10d571
DV		 2892 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2893
5bb61643
CW		 2894 wait_event(dev_priv->pending_flip_queue,
2895 !intel_crtc_has_pending_flip(crtc));
2896
0f91128d
CW		 2897 mutex_lock(&dev->struct_mutex);
2898 intel_finish_fb(crtc->fb);
2899 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2900}
2901
fc316cbe 2902static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2903{
2904 struct drm_device *dev = crtc->dev;
228d3e36 2905 struct intel_encoder *intel_encoder;
040484af
JB		 2906
2907 /*
2908 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2909 * must be driven by its own crtc; no sharing is possible.
2910 */
228d3e36 2911 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2912 switch (intel_encoder->type) {
040484af 2913 case INTEL_OUTPUT_EDP:
228d3e36 2914 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2915 return false;
2916 continue;
2917 }
2918 }
2919
2920 return true;
2921}
2922
fc316cbe
PZ		 2923static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2924{
2925 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2926}
2927
e615efe4
ED		 2928/* Program iCLKIP clock to the desired frequency */
2929static void lpt_program_iclkip(struct drm_crtc *crtc)
2930{
2931 struct drm_device *dev = crtc->dev;
2932 struct drm_i915_private *dev_priv = dev->dev_private;
2933 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2934 u32 temp;
2935
09153000
DV		 2936 mutex_lock(&dev_priv->dpio_lock);
2937
e615efe4
ED		 2938 /* It is necessary to ungate the pixclk gate prior to programming
2939 * the divisors, and gate it back when it is done.
2940 */
2941 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2942
2943 /* Disable SSCCTL */
2944 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2945 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2946 SBI_SSCCTL_DISABLE,
2947 SBI_ICLK);
e615efe4
ED		 2948
2949 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2950 if (crtc->mode.clock == 20000) {
2951 auxdiv = 1;
2952 divsel = 0x41;
2953 phaseinc = 0x20;
2954 } else {
2955 /* The iCLK virtual clock root frequency is in MHz,
2956 * but the crtc->mode.clock in in KHz. To get the divisors,
2957 * it is necessary to divide one by another, so we
2958 * convert the virtual clock precision to KHz here for higher
2959 * precision.
2960 */
2961 u32 iclk_virtual_root_freq = 172800 * 1000;
2962 u32 iclk_pi_range = 64;
2963 u32 desired_divisor, msb_divisor_value, pi_value;
2964
2965 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2966 msb_divisor_value = desired_divisor / iclk_pi_range;
2967 pi_value = desired_divisor % iclk_pi_range;
2968
2969 auxdiv = 0;
2970 divsel = msb_divisor_value - 2;
2971 phaseinc = pi_value;
2972 }
2973
2974 /* This should not happen with any sane values */
2975 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2976 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2977 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2978 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2979
2980 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2981 crtc->mode.clock,
2982 auxdiv,
2983 divsel,
2984 phasedir,
2985 phaseinc);
2986
2987 /* Program SSCDIVINTPHASE6 */
988d6ee8 2988 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2989 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2990 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2991 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2992 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2993 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2994 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2995 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2996
2997 /* Program SSCAUXDIV */
988d6ee8 2998 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2999 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3000 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3001 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3002
3003 /* Enable modulator and associated divider */
988d6ee8 3004 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3005 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3006 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3007
3008 /* Wait for initialization time */
3009 udelay(24);
3010
3011 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3012
3013 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3014}
3015
f67a559d
JB		 3016/*
3017 * Enable PCH resources required for PCH ports:
3018 * - PCH PLLs
3019 * - FDI training & RX/TX
3020 * - update transcoder timings
3021 * - DP transcoding bits
3022 * - transcoder
3023 */
3024static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3025{
3026 struct drm_device *dev = crtc->dev;
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029 int pipe = intel_crtc->pipe;
ee7b9f93 3030 u32 reg, temp;
2c07245f 3031
e7e164db
CW		 3032 assert_transcoder_disabled(dev_priv, pipe);
3033
cd986abb
DV		 3034 /* Write the TU size bits before fdi link training, so that error
3035 * detection works. */
3036 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3037 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3038
c98e9dcf 3039 /* For PCH output, training FDI link */
674cf967 3040 dev_priv->display.fdi_link_train(crtc);
2c07245f 3041
572deb37
DV		 3042 /* XXX: pch pll's can be enabled any time before we enable the PCH
3043 * transcoder, and we actually should do this to not upset any PCH
3044 * transcoder that already use the clock when we share it.
3045 *
3046 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3047 * unconditionally resets the pll - we need that to have the right LVDS
3048 * enable sequence. */
b6b4e185 3049 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3050
303b81e0 3051 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3052 u32 sel;
4b645f14 3053
c98e9dcf 3054 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3055 switch (pipe) {
3056 default:
3057 case 0:
3058 temp |= TRANSA_DPLL_ENABLE;
3059 sel = TRANSA_DPLLB_SEL;
3060 break;
3061 case 1:
3062 temp |= TRANSB_DPLL_ENABLE;
3063 sel = TRANSB_DPLLB_SEL;
3064 break;
3065 case 2:
3066 temp |= TRANSC_DPLL_ENABLE;
3067 sel = TRANSC_DPLLB_SEL;
3068 break;
d64311ab 3069 }
ee7b9f93
JB		 3070 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3071 temp |= sel;
3072 else
3073 temp &= ~sel;
c98e9dcf 3074 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3075 }
5eddb70b 3076
d9b6cb56
JB		 3077 /* set transcoder timing, panel must allow it */
3078 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3079 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3080 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3081 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3082
5eddb70b
CW		 3083 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3084 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3085 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3086 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3087
303b81e0 3088 intel_fdi_normal_train(crtc);
5e84e1a4 3089
c98e9dcf
JB		 3090 /* For PCH DP, enable TRANS_DP_CTL */
3091 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3092 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3093 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3094 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3095 reg = TRANS_DP_CTL(pipe);
3096 temp = I915_READ(reg);
3097 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3098 TRANS_DP_SYNC_MASK |
3099 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3100 temp |= (TRANS_DP_OUTPUT_ENABLE |
3101 TRANS_DP_ENH_FRAMING);
9325c9f0 3102 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3103
3104 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3105 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3106 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3107 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3108
3109 switch (intel_trans_dp_port_sel(crtc)) {
3110 case PCH_DP_B:
5eddb70b 3111 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3112 break;
3113 case PCH_DP_C:
5eddb70b 3114 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3115 break;
3116 case PCH_DP_D:
5eddb70b 3117 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3118 break;
3119 default:
e95d41e1 3120 BUG();
32f9d658 3121 }
2c07245f 3122
5eddb70b 3123 I915_WRITE(reg, temp);
6be4a607 3124 }
b52eb4dc 3125
b8a4f404 3126 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3127}
3128
1507e5bd
PZ		 3129static void lpt_pch_enable(struct drm_crtc *crtc)
3130{
3131 struct drm_device *dev = crtc->dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
3133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3134 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3135
daed2dbb 3136 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3137
8c52b5e8 3138 lpt_program_iclkip(crtc);
1507e5bd 3139
0540e488 3140 /* Set transcoder timing. */
daed2dbb
PZ		 3141 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3142 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3143 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3144
daed2dbb
PZ		 3145 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3146 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3147 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3148 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3149
937bb610 3150 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3151}
3152
ee7b9f93
JB		 3153static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3154{
3155 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3156
3157 if (pll == NULL)
3158 return;
3159
3160 if (pll->refcount == 0) {
3161 WARN(1, "bad PCH PLL refcount\n");
3162 return;
3163 }
3164
3165 --pll->refcount;
3166 intel_crtc->pch_pll = NULL;
3167}
3168
3169static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3170{
3171 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3172 struct intel_pch_pll *pll;
3173 int i;
3174
3175 pll = intel_crtc->pch_pll;
3176 if (pll) {
3177 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3178 intel_crtc->base.base.id, pll->pll_reg);
3179 goto prepare;
3180 }
3181
98b6bd99
DV		 3182 if (HAS_PCH_IBX(dev_priv->dev)) {
3183 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3184 i = intel_crtc->pipe;
3185 pll = &dev_priv->pch_plls[i];
3186
3187 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3188 intel_crtc->base.base.id, pll->pll_reg);
3189
3190 goto found;
3191 }
3192
ee7b9f93
JB		 3193 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3194 pll = &dev_priv->pch_plls[i];
3195
3196 /* Only want to check enabled timings first */
3197 if (pll->refcount == 0)
3198 continue;
3199
3200 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3201 fp == I915_READ(pll->fp0_reg)) {
3202 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3203 intel_crtc->base.base.id,
3204 pll->pll_reg, pll->refcount, pll->active);
3205
3206 goto found;
3207 }
3208 }
3209
3210 /* Ok no matching timings, maybe there's a free one? */
3211 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3212 pll = &dev_priv->pch_plls[i];
3213 if (pll->refcount == 0) {
3214 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3215 intel_crtc->base.base.id, pll->pll_reg);
3216 goto found;
3217 }
3218 }
3219
3220 return NULL;
3221
3222found:
3223 intel_crtc->pch_pll = pll;
3224 pll->refcount++;
3225 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3226prepare: /* separate function? */
3227 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3228
e04c7350
CW		 3229 /* Wait for the clocks to stabilize before rewriting the regs */
3230 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3231 POSTING_READ(pll->pll_reg);
3232 udelay(150);
e04c7350
CW		 3233
3234 I915_WRITE(pll->fp0_reg, fp);
3235 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3236 pll->on = false;
3237 return pll;
3238}
3239
d4270e57
JB		 3240void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3241{
3242 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3243 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3244 u32 temp;
3245
3246 temp = I915_READ(dslreg);
3247 udelay(500);
3248 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3249 if (wait_for(I915_READ(dslreg) != temp, 5))
3250 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3251 }
3252}
3253
f67a559d
JB		 3254static void ironlake_crtc_enable(struct drm_crtc *crtc)
3255{
3256 struct drm_device *dev = crtc->dev;
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3259 struct intel_encoder *encoder;
f67a559d
JB		 3260 int pipe = intel_crtc->pipe;
3261 int plane = intel_crtc->plane;
3262 u32 temp;
3263 bool is_pch_port;
3264
08a48469
DV		 3265 WARN_ON(!crtc->enabled);
3266
f67a559d
JB		 3267 if (intel_crtc->active)
3268 return;
3269
3270 intel_crtc->active = true;
3271 intel_update_watermarks(dev);
3272
3273 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3274 temp = I915_READ(PCH_LVDS);
3275 if ((temp & LVDS_PORT_EN) == 0)
3276 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3277 }
3278
fc316cbe 3279 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3280
46b6f814 3281 if (is_pch_port) {
fff367c7
DV		 3282 /* Note: FDI PLL enabling _must_ be done before we enable the
3283 * cpu pipes, hence this is separate from all the other fdi/pch
3284 * enabling. */
88cefb6c 3285 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3286 } else {
3287 assert_fdi_tx_disabled(dev_priv, pipe);
3288 assert_fdi_rx_disabled(dev_priv, pipe);
3289 }
f67a559d 3290
bf49ec8c
DV		 3291 for_each_encoder_on_crtc(dev, crtc, encoder)
3292 if (encoder->pre_enable)
3293 encoder->pre_enable(encoder);
f67a559d
JB		 3294
3295 /* Enable panel fitting for LVDS */
3296 if (dev_priv->pch_pf_size &&
547dc041
JN		 3297 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3298 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3299 /* Force use of hard-coded filter coefficients
3300 * as some pre-programmed values are broken,
3301 * e.g. x201.
3302 */
13888d78
PZ		 3303 if (IS_IVYBRIDGE(dev))
3304 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3305 PF_PIPE_SEL_IVB(pipe));
3306 else
3307 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3308 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3309 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3310 }
3311
9c54c0dd
JB		 3312 /*
3313 * On ILK+ LUT must be loaded before the pipe is running but with
3314 * clocks enabled
3315 */
3316 intel_crtc_load_lut(crtc);
3317
f67a559d
JB		 3318 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3319 intel_enable_plane(dev_priv, plane, pipe);
3320
3321 if (is_pch_port)
3322 ironlake_pch_enable(crtc);
c98e9dcf 3323
d1ebd816 3324 mutex_lock(&dev->struct_mutex);
bed4a673 3325 intel_update_fbc(dev);
d1ebd816
BW		 3326 mutex_unlock(&dev->struct_mutex);
3327
6b383a7f 3328 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3329
fa5c73b1
DV		 3330 for_each_encoder_on_crtc(dev, crtc, encoder)
3331 encoder->enable(encoder);
61b77ddd
DV		 3332
3333 if (HAS_PCH_CPT(dev))
3334 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3335
3336 /*
3337 * There seems to be a race in PCH platform hw (at least on some
3338 * outputs) where an enabled pipe still completes any pageflip right
3339 * away (as if the pipe is off) instead of waiting for vblank. As soon
3340 * as the first vblank happend, everything works as expected. Hence just
3341 * wait for one vblank before returning to avoid strange things
3342 * happening.
3343 */
3344 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3345}
3346
4f771f10
PZ		 3347static void haswell_crtc_enable(struct drm_crtc *crtc)
3348{
3349 struct drm_device *dev = crtc->dev;
3350 struct drm_i915_private *dev_priv = dev->dev_private;
3351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3352 struct intel_encoder *encoder;
3353 int pipe = intel_crtc->pipe;
3354 int plane = intel_crtc->plane;
4f771f10
PZ		 3355 bool is_pch_port;
3356
3357 WARN_ON(!crtc->enabled);
3358
3359 if (intel_crtc->active)
3360 return;
3361
3362 intel_crtc->active = true;
3363 intel_update_watermarks(dev);
3364
fc316cbe 3365 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3366
83616634 3367 if (is_pch_port)
04945641 3368 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3369
3370 for_each_encoder_on_crtc(dev, crtc, encoder)
3371 if (encoder->pre_enable)
3372 encoder->pre_enable(encoder);
3373
1f544388 3374 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3375
1f544388 3376 /* Enable panel fitting for eDP */
547dc041
JN		 3377 if (dev_priv->pch_pf_size &&
3378 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3379 /* Force use of hard-coded filter coefficients
3380 * as some pre-programmed values are broken,
3381 * e.g. x201.
3382 */
54075a7d
PZ		 3383 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3384 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3385 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3386 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3387 }
3388
3389 /*
3390 * On ILK+ LUT must be loaded before the pipe is running but with
3391 * clocks enabled
3392 */
3393 intel_crtc_load_lut(crtc);
3394
1f544388
PZ		 3395 intel_ddi_set_pipe_settings(crtc);
3396 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3397
3398 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3399 intel_enable_plane(dev_priv, plane, pipe);
3400
3401 if (is_pch_port)
1507e5bd 3402 lpt_pch_enable(crtc);
4f771f10
PZ		 3403
3404 mutex_lock(&dev->struct_mutex);
3405 intel_update_fbc(dev);
3406 mutex_unlock(&dev->struct_mutex);
3407
3408 intel_crtc_update_cursor(crtc, true);
3409
3410 for_each_encoder_on_crtc(dev, crtc, encoder)
3411 encoder->enable(encoder);
3412
4f771f10
PZ		 3413 /*
3414 * There seems to be a race in PCH platform hw (at least on some
3415 * outputs) where an enabled pipe still completes any pageflip right
3416 * away (as if the pipe is off) instead of waiting for vblank. As soon
3417 * as the first vblank happend, everything works as expected. Hence just
3418 * wait for one vblank before returning to avoid strange things
3419 * happening.
3420 */
3421 intel_wait_for_vblank(dev, intel_crtc->pipe);
3422}
3423
6be4a607
JB		 3424static void ironlake_crtc_disable(struct drm_crtc *crtc)
3425{
3426 struct drm_device *dev = crtc->dev;
3427 struct drm_i915_private *dev_priv = dev->dev_private;
3428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3429 struct intel_encoder *encoder;
6be4a607
JB		 3430 int pipe = intel_crtc->pipe;
3431 int plane = intel_crtc->plane;
5eddb70b 3432 u32 reg, temp;
b52eb4dc 3433
ef9c3aee 3434
f7abfe8b
CW		 3435 if (!intel_crtc->active)
3436 return;
3437
ea9d758d
DV		 3438 for_each_encoder_on_crtc(dev, crtc, encoder)
3439 encoder->disable(encoder);
3440
e6c3a2a6 3441 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3442 drm_vblank_off(dev, pipe);
6b383a7f 3443 intel_crtc_update_cursor(crtc, false);
5eddb70b 3444
b24e7179 3445 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3446
973d04f9
CW		 3447 if (dev_priv->cfb_plane == plane)
3448 intel_disable_fbc(dev);
2c07245f 3449
b24e7179 3450 intel_disable_pipe(dev_priv, pipe);
32f9d658 3451
6be4a607 3452 /* Disable PF */
9db4a9c7
JB		 3453 I915_WRITE(PF_CTL(pipe), 0);
3454 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3455
bf49ec8c
DV		 3456 for_each_encoder_on_crtc(dev, crtc, encoder)
3457 if (encoder->post_disable)
3458 encoder->post_disable(encoder);
2c07245f 3459
0fc932b8 3460 ironlake_fdi_disable(crtc);
249c0e64 3461
b8a4f404 3462 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3463
6be4a607
JB		 3464 if (HAS_PCH_CPT(dev)) {
3465 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3466 reg = TRANS_DP_CTL(pipe);
3467 temp = I915_READ(reg);
3468 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3469 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3470 I915_WRITE(reg, temp);
6be4a607
JB		 3471
3472 /* disable DPLL_SEL */
3473 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3474 switch (pipe) {
3475 case 0:
d64311ab 3476 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3477 break;
3478 case 1:
6be4a607 3479 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3480 break;
3481 case 2:
4b645f14 3482 /* C shares PLL A or B */
d64311ab 3483 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3484 break;
3485 default:
3486 BUG(); /* wtf */
3487 }
6be4a607 3488 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3489 }
e3421a18 3490
6be4a607 3491 /* disable PCH DPLL */
ee7b9f93 3492 intel_disable_pch_pll(intel_crtc);
8db9d77b 3493
88cefb6c 3494 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3495
f7abfe8b 3496 intel_crtc->active = false;
6b383a7f 3497 intel_update_watermarks(dev);
d1ebd816
BW		 3498
3499 mutex_lock(&dev->struct_mutex);
6b383a7f 3500 intel_update_fbc(dev);
d1ebd816 3501 mutex_unlock(&dev->struct_mutex);
6be4a607 3502}
1b3c7a47 3503
4f771f10 3504static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3505{
4f771f10
PZ		 3506 struct drm_device *dev = crtc->dev;
3507 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3509 struct intel_encoder *encoder;
3510 int pipe = intel_crtc->pipe;
3511 int plane = intel_crtc->plane;
ad80a810 3512 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3513 bool is_pch_port;
ee7b9f93 3514
4f771f10
PZ		 3515 if (!intel_crtc->active)
3516 return;
3517
83616634
PZ		 3518 is_pch_port = haswell_crtc_driving_pch(crtc);
3519
4f771f10
PZ		 3520 for_each_encoder_on_crtc(dev, crtc, encoder)
3521 encoder->disable(encoder);
3522
3523 intel_crtc_wait_for_pending_flips(crtc);
3524 drm_vblank_off(dev, pipe);
3525 intel_crtc_update_cursor(crtc, false);
3526
3527 intel_disable_plane(dev_priv, plane, pipe);
3528
3529 if (dev_priv->cfb_plane == plane)
3530 intel_disable_fbc(dev);
3531
3532 intel_disable_pipe(dev_priv, pipe);
3533
ad80a810 3534 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3535
3536 /* Disable PF */
3537 I915_WRITE(PF_CTL(pipe), 0);
3538 I915_WRITE(PF_WIN_SZ(pipe), 0);
3539
1f544388 3540 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3541
3542 for_each_encoder_on_crtc(dev, crtc, encoder)
3543 if (encoder->post_disable)
3544 encoder->post_disable(encoder);
3545
83616634 3546 if (is_pch_port) {
ab4d966c 3547 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3548 intel_ddi_fdi_disable(crtc);
83616634 3549 }
4f771f10
PZ		 3550
3551 intel_crtc->active = false;
3552 intel_update_watermarks(dev);
3553
3554 mutex_lock(&dev->struct_mutex);
3555 intel_update_fbc(dev);
3556 mutex_unlock(&dev->struct_mutex);
3557}
3558
ee7b9f93
JB		 3559static void ironlake_crtc_off(struct drm_crtc *crtc)
3560{
3561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3562 intel_put_pch_pll(intel_crtc);
3563}
3564
6441ab5f
PZ		 3565static void haswell_crtc_off(struct drm_crtc *crtc)
3566{
a5c961d1
PZ		 3567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3568
3569 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3570 * start using it. */
1a240d4d 3571 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3572
6441ab5f
PZ		 3573 intel_ddi_put_crtc_pll(crtc);
3574}
3575
02e792fb
DV		 3576static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3577{
02e792fb 3578 if (!enable && intel_crtc->overlay) {
23f09ce3 3579 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3580 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3581
23f09ce3 3582 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3583 dev_priv->mm.interruptible = false;
3584 (void) intel_overlay_switch_off(intel_crtc->overlay);
3585 dev_priv->mm.interruptible = true;
23f09ce3 3586 mutex_unlock(&dev->struct_mutex);
02e792fb 3587 }
02e792fb 3588
5dcdbcb0
CW		 3589 /* Let userspace switch the overlay on again. In most cases userspace
3590 * has to recompute where to put it anyway.
3591 */
02e792fb
DV		 3592}
3593
0b8765c6 3594static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3595{
3596 struct drm_device *dev = crtc->dev;
79e53945
JB		 3597 struct drm_i915_private *dev_priv = dev->dev_private;
3598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3599 struct intel_encoder *encoder;
79e53945 3600 int pipe = intel_crtc->pipe;
80824003 3601 int plane = intel_crtc->plane;
79e53945 3602
08a48469
DV		 3603 WARN_ON(!crtc->enabled);
3604
f7abfe8b
CW		 3605 if (intel_crtc->active)
3606 return;
3607
3608 intel_crtc->active = true;
6b383a7f
CW		 3609 intel_update_watermarks(dev);
3610
63d7bbe9 3611 intel_enable_pll(dev_priv, pipe);
040484af 3612 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3613 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3614
0b8765c6 3615 intel_crtc_load_lut(crtc);
bed4a673 3616 intel_update_fbc(dev);
79e53945 3617
0b8765c6
JB		 3618 /* Give the overlay scaler a chance to enable if it's on this pipe */
3619 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3620 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3621
fa5c73b1
DV		 3622 for_each_encoder_on_crtc(dev, crtc, encoder)
3623 encoder->enable(encoder);
0b8765c6 3624}
79e53945 3625
0b8765c6
JB		 3626static void i9xx_crtc_disable(struct drm_crtc *crtc)
3627{
3628 struct drm_device *dev = crtc->dev;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3631 struct intel_encoder *encoder;
0b8765c6
JB		 3632 int pipe = intel_crtc->pipe;
3633 int plane = intel_crtc->plane;
b690e96c 3634
ef9c3aee 3635
f7abfe8b
CW		 3636 if (!intel_crtc->active)
3637 return;
3638
ea9d758d
DV		 3639 for_each_encoder_on_crtc(dev, crtc, encoder)
3640 encoder->disable(encoder);
3641
0b8765c6 3642 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3643 intel_crtc_wait_for_pending_flips(crtc);
3644 drm_vblank_off(dev, pipe);
0b8765c6 3645 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3646 intel_crtc_update_cursor(crtc, false);
0b8765c6 3647
973d04f9
CW		 3648 if (dev_priv->cfb_plane == plane)
3649 intel_disable_fbc(dev);
79e53945 3650
b24e7179 3651 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3652 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3653 intel_disable_pll(dev_priv, pipe);
0b8765c6 3654
f7abfe8b 3655 intel_crtc->active = false;
6b383a7f
CW		 3656 intel_update_fbc(dev);
3657 intel_update_watermarks(dev);
0b8765c6
JB		 3658}
3659
ee7b9f93
JB		 3660static void i9xx_crtc_off(struct drm_crtc *crtc)
3661{
3662}
3663
976f8a20
DV		 3664static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3665 bool enabled)
2c07245f
ZW		 3666{
3667 struct drm_device *dev = crtc->dev;
3668 struct drm_i915_master_private *master_priv;
3669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3670 int pipe = intel_crtc->pipe;
79e53945
JB		 3671
3672 if (!dev->primary->master)
3673 return;
3674
3675 master_priv = dev->primary->master->driver_priv;
3676 if (!master_priv->sarea_priv)
3677 return;
3678
79e53945
JB		 3679 switch (pipe) {
3680 case 0:
3681 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3682 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3683 break;
3684 case 1:
3685 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3686 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3687 break;
3688 default:
9db4a9c7 3689 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3690 break;
3691 }
79e53945
JB		 3692}
3693
976f8a20
DV		 3694/**
3695 * Sets the power management mode of the pipe and plane.
3696 */
3697void intel_crtc_update_dpms(struct drm_crtc *crtc)
3698{
3699 struct drm_device *dev = crtc->dev;
3700 struct drm_i915_private *dev_priv = dev->dev_private;
3701 struct intel_encoder *intel_encoder;
3702 bool enable = false;
3703
3704 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3705 enable |= intel_encoder->connectors_active;
3706
3707 if (enable)
3708 dev_priv->display.crtc_enable(crtc);
3709 else
3710 dev_priv->display.crtc_disable(crtc);
3711
3712 intel_crtc_update_sarea(crtc, enable);
3713}
3714
3715static void intel_crtc_noop(struct drm_crtc *crtc)
3716{
3717}
3718
cdd59983
CW		 3719static void intel_crtc_disable(struct drm_crtc *crtc)
3720{
cdd59983 3721 struct drm_device *dev = crtc->dev;
976f8a20 3722 struct drm_connector *connector;
ee7b9f93 3723 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3725
976f8a20
DV		 3726 /* crtc should still be enabled when we disable it. */
3727 WARN_ON(!crtc->enabled);
3728
7b9f35a6 3729 intel_crtc->eld_vld = false;
976f8a20
DV		 3730 dev_priv->display.crtc_disable(crtc);
3731 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3732 dev_priv->display.off(crtc);
3733
931872fc
CW		 3734 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3735 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3736
3737 if (crtc->fb) {
3738 mutex_lock(&dev->struct_mutex);
1690e1eb 3739 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3740 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3741 crtc->fb = NULL;
3742 }
3743
3744 /* Update computed state. */
3745 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3746 if (!connector->encoder || !connector->encoder->crtc)
3747 continue;
3748
3749 if (connector->encoder->crtc != crtc)
3750 continue;
3751
3752 connector->dpms = DRM_MODE_DPMS_OFF;
3753 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3754 }
3755}
3756
a261b246 3757void intel_modeset_disable(struct drm_device *dev)
79e53945 3758{
a261b246
DV		 3759 struct drm_crtc *crtc;
3760
3761 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3762 if (crtc->enabled)
3763 intel_crtc_disable(crtc);
3764 }
79e53945
JB		 3765}
3766
1f703855 3767void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3768{
7e7d76c3
JB		 3769}
3770
ea5b213a 3771void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3772{
4ef69c7a 3773 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3774
ea5b213a
CW		 3775 drm_encoder_cleanup(encoder);
3776 kfree(intel_encoder);
7e7d76c3
JB		 3777}
3778
5ab432ef
DV		 3779/* Simple dpms helper for encodres with just one connector, no cloning and only
3780 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3781 * state of the entire output pipe. */
3782void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3783{
5ab432ef
DV		 3784 if (mode == DRM_MODE_DPMS_ON) {
3785 encoder->connectors_active = true;
3786
b2cabb0e 3787 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3788 } else {
3789 encoder->connectors_active = false;
3790
b2cabb0e 3791 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3792 }
79e53945
JB		 3793}
3794
0a91ca29
DV		 3795/* Cross check the actual hw state with our own modeset state tracking (and it's
3796 * internal consistency). */
b980514c 3797static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3798{
0a91ca29
DV		 3799 if (connector->get_hw_state(connector)) {
3800 struct intel_encoder *encoder = connector->encoder;
3801 struct drm_crtc *crtc;
3802 bool encoder_enabled;
3803 enum pipe pipe;
3804
3805 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3806 connector->base.base.id,
3807 drm_get_connector_name(&connector->base));
3808
3809 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3810 "wrong connector dpms state\n");
3811 WARN(connector->base.encoder != &encoder->base,
3812 "active connector not linked to encoder\n");
3813 WARN(!encoder->connectors_active,
3814 "encoder->connectors_active not set\n");
3815
3816 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3817 WARN(!encoder_enabled, "encoder not enabled\n");
3818 if (WARN_ON(!encoder->base.crtc))
3819 return;
3820
3821 crtc = encoder->base.crtc;
3822
3823 WARN(!crtc->enabled, "crtc not enabled\n");
3824 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3825 WARN(pipe != to_intel_crtc(crtc)->pipe,
3826 "encoder active on the wrong pipe\n");
3827 }
79e53945
JB		 3828}
3829
5ab432ef
DV		 3830/* Even simpler default implementation, if there's really no special case to
3831 * consider. */
3832void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3833{
5ab432ef 3834 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3835
5ab432ef
DV		 3836 /* All the simple cases only support two dpms states. */
3837 if (mode != DRM_MODE_DPMS_ON)
3838 mode = DRM_MODE_DPMS_OFF;
d4270e57 3839
5ab432ef
DV		 3840 if (mode == connector->dpms)
3841 return;
3842
3843 connector->dpms = mode;
3844
3845 /* Only need to change hw state when actually enabled */
3846 if (encoder->base.crtc)
3847 intel_encoder_dpms(encoder, mode);
3848 else
8af6cf88 3849 WARN_ON(encoder->connectors_active != false);
0a91ca29 3850
b980514c 3851 intel_modeset_check_state(connector->dev);
79e53945
JB		 3852}
3853
f0947c37
DV		 3854/* Simple connector->get_hw_state implementation for encoders that support only
3855 * one connector and no cloning and hence the encoder state determines the state
3856 * of the connector. */
3857bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3858{
24929352 3859 enum pipe pipe = 0;
f0947c37 3860 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3861
f0947c37 3862 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3863}
3864
79e53945 3865static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3866 const struct drm_display_mode *mode,
79e53945
JB		 3867 struct drm_display_mode *adjusted_mode)
3868{
2c07245f 3869 struct drm_device *dev = crtc->dev;
89749350 3870
bad720ff 3871 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3872 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3873 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3874 return false;
2c07245f 3875 }
89749350 3876
f9bef081
DV		 3877 /* All interlaced capable intel hw wants timings in frames. Note though
3878 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3879 * timings, so we need to be careful not to clobber these.*/
3880 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3881 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3882
44f46b42
CW		 3883 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3884 * with a hsync front porch of 0.
3885 */
3886 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3887 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3888 return false;
3889
79e53945
JB		 3890 return true;
3891}
3892
25eb05fc
JB		 3893static int valleyview_get_display_clock_speed(struct drm_device *dev)
3894{
3895 return 400000; /* FIXME */
3896}
3897
e70236a8
JB		 3898static int i945_get_display_clock_speed(struct drm_device *dev)
3899{
3900 return 400000;
3901}
79e53945 3902
e70236a8 3903static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3904{
e70236a8
JB		 3905 return 333000;
3906}
79e53945 3907
e70236a8
JB		 3908static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3909{
3910 return 200000;
3911}
79e53945 3912
e70236a8
JB		 3913static int i915gm_get_display_clock_speed(struct drm_device *dev)
3914{
3915 u16 gcfgc = 0;
79e53945 3916
e70236a8
JB		 3917 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3918
3919 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3920 return 133000;
3921 else {
3922 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3923 case GC_DISPLAY_CLOCK_333_MHZ:
3924 return 333000;
3925 default:
3926 case GC_DISPLAY_CLOCK_190_200_MHZ:
3927 return 190000;
79e53945 3928 }
e70236a8
JB		 3929 }
3930}
3931
3932static int i865_get_display_clock_speed(struct drm_device *dev)
3933{
3934 return 266000;
3935}
3936
3937static int i855_get_display_clock_speed(struct drm_device *dev)
3938{
3939 u16 hpllcc = 0;
3940 /* Assume that the hardware is in the high speed state. This
3941 * should be the default.
3942 */
3943 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3944 case GC_CLOCK_133_200:
3945 case GC_CLOCK_100_200:
3946 return 200000;
3947 case GC_CLOCK_166_250:
3948 return 250000;
3949 case GC_CLOCK_100_133:
79e53945 3950 return 133000;
e70236a8 3951 }
79e53945 3952
e70236a8
JB		 3953 /* Shouldn't happen */
3954 return 0;
3955}
79e53945 3956
e70236a8
JB		 3957static int i830_get_display_clock_speed(struct drm_device *dev)
3958{
3959 return 133000;
79e53945
JB		 3960}
3961
2c07245f 3962static void
e69d0bc1 3963intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 3964{
3965 while (*num > 0xffffff || *den > 0xffffff) {
3966 *num >>= 1;
3967 *den >>= 1;
3968 }
3969}
3970
e69d0bc1
DV		 3971void
3972intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3973 int pixel_clock, int link_clock,
3974 struct intel_link_m_n *m_n)
2c07245f 3975{
e69d0bc1 3976 m_n->tu = 64;
22ed1113
CW		 3977 m_n->gmch_m = bits_per_pixel * pixel_clock;
3978 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 3979 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 3980 m_n->link_m = pixel_clock;
3981 m_n->link_n = link_clock;
e69d0bc1 3982 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 3983}
3984
a7615030
CW		 3985static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3986{
72bbe58c
KP		 3987 if (i915_panel_use_ssc >= 0)
3988 return i915_panel_use_ssc != 0;
3989 return dev_priv->lvds_use_ssc
435793df 3990 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3991}
3992
5a354204
JB		 3993/**
3994 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3995 * @crtc: CRTC structure
3b5c78a3 3996 * @mode: requested mode
5a354204
JB		 3997 *
3998 * A pipe may be connected to one or more outputs. Based on the depth of the
3999 * attached framebuffer, choose a good color depth to use on the pipe.
4000 *
4001 * If possible, match the pipe depth to the fb depth. In some cases, this
4002 * isn't ideal, because the connected output supports a lesser or restricted
4003 * set of depths. Resolve that here:
4004 * LVDS typically supports only 6bpc, so clamp down in that case
4005 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4006 * Displays may support a restricted set as well, check EDID and clamp as
4007 * appropriate.
3b5c78a3 4008 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4009 *
4010 * RETURNS:
4011 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4012 * true if they don't match).
4013 */
4014static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4015 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4016 unsigned int *pipe_bpp,
4017 struct drm_display_mode *mode)
5a354204
JB		 4018{
4019 struct drm_device *dev = crtc->dev;
4020 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4021 struct drm_connector *connector;
6c2b7c12 4022 struct intel_encoder *intel_encoder;
5a354204
JB		 4023 unsigned int display_bpc = UINT_MAX, bpc;
4024
4025 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4026 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4027
4028 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4029 unsigned int lvds_bpc;
4030
4031 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4032 LVDS_A3_POWER_UP)
4033 lvds_bpc = 8;
4034 else
4035 lvds_bpc = 6;
4036
4037 if (lvds_bpc < display_bpc) {
82820490 4038 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4039 display_bpc = lvds_bpc;
4040 }
4041 continue;
4042 }
4043
5a354204
JB		 4044 /* Not one of the known troublemakers, check the EDID */
4045 list_for_each_entry(connector, &dev->mode_config.connector_list,
4046 head) {
6c2b7c12 4047 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4048 continue;
4049
62ac41a6
JB		 4050 /* Don't use an invalid EDID bpc value */
4051 if (connector->display_info.bpc &&
4052 connector->display_info.bpc < display_bpc) {
82820490 4053 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4054 display_bpc = connector->display_info.bpc;
4055 }
4056 }
4057
2f4f649a
JN		 4058 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4059 /* Use VBT settings if we have an eDP panel */
4060 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4061
9a30a61f 4062 if (edp_bpc && edp_bpc < display_bpc) {
2f4f649a
JN		 4063 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4064 display_bpc = edp_bpc;
4065 }
4066 continue;
4067 }
4068
5a354204
JB		 4069 /*
4070 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4071 * through, clamp it down. (Note: >12bpc will be caught below.)
4072 */
4073 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4074 if (display_bpc > 8 && display_bpc < 12) {
82820490 4075 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4076 display_bpc = 12;
4077 } else {
82820490 4078 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4079 display_bpc = 8;
4080 }
4081 }
4082 }
4083
3b5c78a3
AJ		 4084 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4085 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4086 display_bpc = 6;
4087 }
4088
5a354204
JB		 4089 /*
4090 * We could just drive the pipe at the highest bpc all the time and
4091 * enable dithering as needed, but that costs bandwidth. So choose
4092 * the minimum value that expresses the full color range of the fb but
4093 * also stays within the max display bpc discovered above.
4094 */
4095
94352cf9 4096 switch (fb->depth) {
5a354204
JB		 4097 case 8:
4098 bpc = 8; /* since we go through a colormap */
4099 break;
4100 case 15:
4101 case 16:
4102 bpc = 6; /* min is 18bpp */
4103 break;
4104 case 24:
578393cd 4105 bpc = 8;
5a354204
JB		 4106 break;
4107 case 30:
578393cd 4108 bpc = 10;
5a354204
JB		 4109 break;
4110 case 48:
578393cd 4111 bpc = 12;
5a354204
JB		 4112 break;
4113 default:
4114 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4115 bpc = min((unsigned int)8, display_bpc);
4116 break;
4117 }
4118
578393cd
KP		 4119 display_bpc = min(display_bpc, bpc);
4120
82820490
AJ		 4121 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4122 bpc, display_bpc);
5a354204 4123
578393cd 4124 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4125
4126 return display_bpc != bpc;
4127}
4128
a0c4da24
JB		 4129static int vlv_get_refclk(struct drm_crtc *crtc)
4130{
4131 struct drm_device *dev = crtc->dev;
4132 struct drm_i915_private *dev_priv = dev->dev_private;
4133 int refclk = 27000; /* for DP & HDMI */
4134
4135 return 100000; /* only one validated so far */
4136
4137 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4138 refclk = 96000;
4139 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4140 if (intel_panel_use_ssc(dev_priv))
4141 refclk = 100000;
4142 else
4143 refclk = 96000;
4144 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4145 refclk = 100000;
4146 }
4147
4148 return refclk;
4149}
4150
c65d77d8
JB		 4151static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4152{
4153 struct drm_device *dev = crtc->dev;
4154 struct drm_i915_private *dev_priv = dev->dev_private;
4155 int refclk;
4156
a0c4da24
JB		 4157 if (IS_VALLEYVIEW(dev)) {
4158 refclk = vlv_get_refclk(crtc);
4159 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4160 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4161 refclk = dev_priv->lvds_ssc_freq * 1000;
4162 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4163 refclk / 1000);
4164 } else if (!IS_GEN2(dev)) {
4165 refclk = 96000;
4166 } else {
4167 refclk = 48000;
4168 }
4169
4170 return refclk;
4171}
4172
4173static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4174 intel_clock_t *clock)
4175{
4176 /* SDVO TV has fixed PLL values depend on its clock range,
4177 this mirrors vbios setting. */
4178 if (adjusted_mode->clock >= 100000
4179 && adjusted_mode->clock < 140500) {
4180 clock->p1 = 2;
4181 clock->p2 = 10;
4182 clock->n = 3;
4183 clock->m1 = 16;
4184 clock->m2 = 8;
4185 } else if (adjusted_mode->clock >= 140500
4186 && adjusted_mode->clock <= 200000) {
4187 clock->p1 = 1;
4188 clock->p2 = 10;
4189 clock->n = 6;
4190 clock->m1 = 12;
4191 clock->m2 = 8;
4192 }
4193}
4194
a7516a05
JB		 4195static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4196 intel_clock_t *clock,
4197 intel_clock_t *reduced_clock)
4198{
4199 struct drm_device *dev = crtc->dev;
4200 struct drm_i915_private *dev_priv = dev->dev_private;
4201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4202 int pipe = intel_crtc->pipe;
4203 u32 fp, fp2 = 0;
4204
4205 if (IS_PINEVIEW(dev)) {
4206 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4207 if (reduced_clock)
4208 fp2 = (1 << reduced_clock->n) << 16 |
4209 reduced_clock->m1 << 8 | reduced_clock->m2;
4210 } else {
4211 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4212 if (reduced_clock)
4213 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4214 reduced_clock->m2;
4215 }
4216
4217 I915_WRITE(FP0(pipe), fp);
4218
4219 intel_crtc->lowfreq_avail = false;
4220 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4221 reduced_clock && i915_powersave) {
4222 I915_WRITE(FP1(pipe), fp2);
4223 intel_crtc->lowfreq_avail = true;
4224 } else {
4225 I915_WRITE(FP1(pipe), fp);
4226 }
4227}
4228
a0c4da24
JB		 4229static void vlv_update_pll(struct drm_crtc *crtc,
4230 struct drm_display_mode *mode,
4231 struct drm_display_mode *adjusted_mode,
4232 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4233 int num_connectors)
a0c4da24
JB		 4234{
4235 struct drm_device *dev = crtc->dev;
4236 struct drm_i915_private *dev_priv = dev->dev_private;
4237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4238 int pipe = intel_crtc->pipe;
4239 u32 dpll, mdiv, pdiv;
4240 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4241 bool is_sdvo;
4242 u32 temp;
a0c4da24 4243
09153000
DV		 4244 mutex_lock(&dev_priv->dpio_lock);
4245
2a8f64ca
VP		 4246 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4247 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4248
2a8f64ca
VP		 4249 dpll = DPLL_VGA_MODE_DIS;
4250 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4251 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4252 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4253
4254 I915_WRITE(DPLL(pipe), dpll);
4255 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4256
4257 bestn = clock->n;
4258 bestm1 = clock->m1;
4259 bestm2 = clock->m2;
4260 bestp1 = clock->p1;
4261 bestp2 = clock->p2;
4262
2a8f64ca
VP		 4263 /*
4264 * In Valleyview PLL and program lane counter registers are exposed
4265 * through DPIO interface
4266 */
a0c4da24
JB		 4267 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4268 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4269 mdiv |= ((bestn << DPIO_N_SHIFT));
4270 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4271 mdiv |= (1 << DPIO_K_SHIFT);
4272 mdiv |= DPIO_ENABLE_CALIBRATION;
4273 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4274
4275 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4276
2a8f64ca 4277 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4278 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4279 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4280 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4281 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4282
2a8f64ca 4283 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4284
4285 dpll |= DPLL_VCO_ENABLE;
4286 I915_WRITE(DPLL(pipe), dpll);
4287 POSTING_READ(DPLL(pipe));
4288 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4289 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4290
2a8f64ca
VP		 4291 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4292
4293 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4294 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4295
4296 I915_WRITE(DPLL(pipe), dpll);
4297
4298 /* Wait for the clocks to stabilize. */
4299 POSTING_READ(DPLL(pipe));
4300 udelay(150);
a0c4da24 4301
2a8f64ca
VP		 4302 temp = 0;
4303 if (is_sdvo) {
4304 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4305 if (temp > 1)
4306 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4307 else
4308 temp = 0;
a0c4da24 4309 }
2a8f64ca
VP		 4310 I915_WRITE(DPLL_MD(pipe), temp);
4311 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4312
2a8f64ca
VP		 4313 /* Now program lane control registers */
4314 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4315 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4316 {
4317 temp = 0x1000C4;
4318 if(pipe == 1)
4319 temp |= (1 << 21);
4320 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4321 }
4322 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4323 {
4324 temp = 0x1000C4;
4325 if(pipe == 1)
4326 temp |= (1 << 21);
4327 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4328 }
09153000
DV		 4329
4330 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4331}
4332
eb1cbe48
DV		 4333static void i9xx_update_pll(struct drm_crtc *crtc,
4334 struct drm_display_mode *mode,
4335 struct drm_display_mode *adjusted_mode,
4336 intel_clock_t *clock, intel_clock_t *reduced_clock,
4337 int num_connectors)
4338{
4339 struct drm_device *dev = crtc->dev;
4340 struct drm_i915_private *dev_priv = dev->dev_private;
4341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4342 struct intel_encoder *encoder;
eb1cbe48
DV		 4343 int pipe = intel_crtc->pipe;
4344 u32 dpll;
4345 bool is_sdvo;
4346
2a8f64ca
VP		 4347 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4348
eb1cbe48
DV		 4349 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4350 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4351
4352 dpll = DPLL_VGA_MODE_DIS;
4353
4354 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4355 dpll |= DPLLB_MODE_LVDS;
4356 else
4357 dpll |= DPLLB_MODE_DAC_SERIAL;
4358 if (is_sdvo) {
4359 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4360 if (pixel_multiplier > 1) {
4361 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4362 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4363 }
4364 dpll |= DPLL_DVO_HIGH_SPEED;
4365 }
4366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4367 dpll |= DPLL_DVO_HIGH_SPEED;
4368
4369 /* compute bitmask from p1 value */
4370 if (IS_PINEVIEW(dev))
4371 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4372 else {
4373 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4374 if (IS_G4X(dev) && reduced_clock)
4375 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4376 }
4377 switch (clock->p2) {
4378 case 5:
4379 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4380 break;
4381 case 7:
4382 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4383 break;
4384 case 10:
4385 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4386 break;
4387 case 14:
4388 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4389 break;
4390 }
4391 if (INTEL_INFO(dev)->gen >= 4)
4392 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4393
4394 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4395 dpll |= PLL_REF_INPUT_TVCLKINBC;
4396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4397 /* XXX: just matching BIOS for now */
4398 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4399 dpll |= 3;
4400 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4401 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4402 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4403 else
4404 dpll |= PLL_REF_INPUT_DREFCLK;
4405
4406 dpll |= DPLL_VCO_ENABLE;
4407 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4408 POSTING_READ(DPLL(pipe));
4409 udelay(150);
4410
dafd226c
DV		 4411 for_each_encoder_on_crtc(dev, crtc, encoder)
4412 if (encoder->pre_pll_enable)
4413 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4414
4415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4416 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4417
4418 I915_WRITE(DPLL(pipe), dpll);
4419
4420 /* Wait for the clocks to stabilize. */
4421 POSTING_READ(DPLL(pipe));
4422 udelay(150);
4423
4424 if (INTEL_INFO(dev)->gen >= 4) {
4425 u32 temp = 0;
4426 if (is_sdvo) {
4427 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4428 if (temp > 1)
4429 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4430 else
4431 temp = 0;
4432 }
4433 I915_WRITE(DPLL_MD(pipe), temp);
4434 } else {
4435 /* The pixel multiplier can only be updated once the
4436 * DPLL is enabled and the clocks are stable.
4437 *
4438 * So write it again.
4439 */
4440 I915_WRITE(DPLL(pipe), dpll);
4441 }
4442}
4443
4444static void i8xx_update_pll(struct drm_crtc *crtc,
4445 struct drm_display_mode *adjusted_mode,
2a8f64ca 4446 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4447 int num_connectors)
4448{
4449 struct drm_device *dev = crtc->dev;
4450 struct drm_i915_private *dev_priv = dev->dev_private;
4451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4452 struct intel_encoder *encoder;
eb1cbe48
DV		 4453 int pipe = intel_crtc->pipe;
4454 u32 dpll;
4455
2a8f64ca
VP		 4456 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4457
eb1cbe48
DV		 4458 dpll = DPLL_VGA_MODE_DIS;
4459
4460 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4461 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4462 } else {
4463 if (clock->p1 == 2)
4464 dpll |= PLL_P1_DIVIDE_BY_TWO;
4465 else
4466 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4467 if (clock->p2 == 4)
4468 dpll |= PLL_P2_DIVIDE_BY_4;
4469 }
4470
4471 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4472 /* XXX: just matching BIOS for now */
4473 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4474 dpll |= 3;
4475 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4476 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4477 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4478 else
4479 dpll |= PLL_REF_INPUT_DREFCLK;
4480
4481 dpll |= DPLL_VCO_ENABLE;
4482 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4483 POSTING_READ(DPLL(pipe));
4484 udelay(150);
4485
dafd226c
DV		 4486 for_each_encoder_on_crtc(dev, crtc, encoder)
4487 if (encoder->pre_pll_enable)
4488 encoder->pre_pll_enable(encoder);
eb1cbe48 4489
5b5896e4
DV		 4490 I915_WRITE(DPLL(pipe), dpll);
4491
4492 /* Wait for the clocks to stabilize. */
4493 POSTING_READ(DPLL(pipe));
4494 udelay(150);
4495
eb1cbe48
DV		 4496 /* The pixel multiplier can only be updated once the
4497 * DPLL is enabled and the clocks are stable.
4498 *
4499 * So write it again.
4500 */
4501 I915_WRITE(DPLL(pipe), dpll);
4502}
4503
b0e77b9c
PZ		 4504static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4505 struct drm_display_mode *mode,
4506 struct drm_display_mode *adjusted_mode)
4507{
4508 struct drm_device *dev = intel_crtc->base.dev;
4509 struct drm_i915_private *dev_priv = dev->dev_private;
4510 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4511 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4512 uint32_t vsyncshift;
4513
4514 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4515 /* the chip adds 2 halflines automatically */
4516 adjusted_mode->crtc_vtotal -= 1;
4517 adjusted_mode->crtc_vblank_end -= 1;
4518 vsyncshift = adjusted_mode->crtc_hsync_start
4519 - adjusted_mode->crtc_htotal / 2;
4520 } else {
4521 vsyncshift = 0;
4522 }
4523
4524 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4525 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4526
fe2b8f9d 4527 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4528 (adjusted_mode->crtc_hdisplay - 1) |
4529 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4530 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4531 (adjusted_mode->crtc_hblank_start - 1) |
4532 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4533 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4534 (adjusted_mode->crtc_hsync_start - 1) |
4535 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4536
fe2b8f9d 4537 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4538 (adjusted_mode->crtc_vdisplay - 1) |
4539 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4540 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4541 (adjusted_mode->crtc_vblank_start - 1) |
4542 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4543 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4544 (adjusted_mode->crtc_vsync_start - 1) |
4545 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4546
b5e508d4
PZ		 4547 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4548 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4549 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4550 * bits. */
4551 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4552 (pipe == PIPE_B || pipe == PIPE_C))
4553 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4554
b0e77b9c
PZ		 4555 /* pipesrc controls the size that is scaled from, which should
4556 * always be the user's requested size.
4557 */
4558 I915_WRITE(PIPESRC(pipe),
4559 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4560}
4561
f564048e
EA		 4562static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4563 struct drm_display_mode *mode,
4564 struct drm_display_mode *adjusted_mode,
4565 int x, int y,
94352cf9 4566 struct drm_framebuffer *fb)
79e53945
JB		 4567{
4568 struct drm_device *dev = crtc->dev;
4569 struct drm_i915_private *dev_priv = dev->dev_private;
4570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4571 int pipe = intel_crtc->pipe;
80824003 4572 int plane = intel_crtc->plane;
c751ce4f 4573 int refclk, num_connectors = 0;
652c393a 4574 intel_clock_t clock, reduced_clock;
b0e77b9c 4575 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4576 bool ok, has_reduced_clock = false, is_sdvo = false;
4577 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4578 struct intel_encoder *encoder;
d4906093 4579 const intel_limit_t *limit;
5c3b82e2 4580 int ret;
79e53945 4581
6c2b7c12 4582 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4583 switch (encoder->type) {
79e53945
JB		 4584 case INTEL_OUTPUT_LVDS:
4585 is_lvds = true;
4586 break;
4587 case INTEL_OUTPUT_SDVO:
7d57382e 4588 case INTEL_OUTPUT_HDMI:
79e53945 4589 is_sdvo = true;
5eddb70b 4590 if (encoder->needs_tv_clock)
e2f0ba97 4591 is_tv = true;
79e53945 4592 break;
79e53945
JB		 4593 case INTEL_OUTPUT_TVOUT:
4594 is_tv = true;
4595 break;
a4fc5ed6
KP		 4596 case INTEL_OUTPUT_DISPLAYPORT:
4597 is_dp = true;
4598 break;
79e53945 4599 }
43565a06 4600
c751ce4f 4601 num_connectors++;
79e53945
JB		 4602 }
4603
c65d77d8 4604 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4605
d4906093
ML		 4606 /*
4607 * Returns a set of divisors for the desired target clock with the given
4608 * refclk, or FALSE. The returned values represent the clock equation:
4609 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4610 */
1b894b59 4611 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4612 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4613 &clock);
79e53945
JB		 4614 if (!ok) {
4615 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4616 return -EINVAL;
79e53945
JB		 4617 }
4618
cda4b7d3 4619 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4620 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4621
ddc9003c 4622 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4623 /*
4624 * Ensure we match the reduced clock's P to the target clock.
4625 * If the clocks don't match, we can't switch the display clock
4626 * by using the FP0/FP1. In such case we will disable the LVDS
4627 * downclock feature.
4628 */
ddc9003c 4629 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4630 dev_priv->lvds_downclock,
4631 refclk,
cec2f356 4632 &clock,
5eddb70b 4633 &reduced_clock);
7026d4ac
ZW		 4634 }
4635
c65d77d8
JB		 4636 if (is_sdvo && is_tv)
4637 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4638
eb1cbe48 4639 if (IS_GEN2(dev))
2a8f64ca
VP		 4640 i8xx_update_pll(crtc, adjusted_mode, &clock,
4641 has_reduced_clock ? &reduced_clock : NULL,
4642 num_connectors);
a0c4da24 4643 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4644 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4645 has_reduced_clock ? &reduced_clock : NULL,
4646 num_connectors);
79e53945 4647 else
eb1cbe48
DV		 4648 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4649 has_reduced_clock ? &reduced_clock : NULL,
4650 num_connectors);
79e53945
JB		 4651
4652 /* setup pipeconf */
5eddb70b 4653 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4654
4655 /* Set up the display plane register */
4656 dspcntr = DISPPLANE_GAMMA_ENABLE;
4657
929c77fb
EA		 4658 if (pipe == 0)
4659 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4660 else
4661 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4662
a6c45cf0 4663 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4664 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4665 * core speed.
4666 *
4667 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4668 * pipe == 0 check?
4669 */
e70236a8
JB		 4670 if (mode->clock >
4671 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4672 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4673 else
5eddb70b 4674 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4675 }
4676
3b5c78a3 4677 /* default to 8bpc */
dfd07d72 4678 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4679 if (is_dp) {
0c96c65b 4680 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4681 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4682 PIPECONF_DITHER_EN |
4683 PIPECONF_DITHER_TYPE_SP;
4684 }
4685 }
4686
19c03924
GB		 4687 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4688 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4689 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4690 PIPECONF_ENABLE |
4691 I965_PIPECONF_ACTIVE;
4692 }
4693 }
4694
28c97730 4695 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4696 drm_mode_debug_printmodeline(mode);
4697
a7516a05
JB		 4698 if (HAS_PIPE_CXSR(dev)) {
4699 if (intel_crtc->lowfreq_avail) {
28c97730 4700 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4701 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4702 } else {
28c97730 4703 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4704 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4705 }
4706 }
4707
617cf884 4708 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4709 if (!IS_GEN2(dev) &&
b0e77b9c 4710 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4711 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4712 else
617cf884 4713 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4714
b0e77b9c 4715 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4716
4717 /* pipesrc and dspsize control the size that is scaled from,
4718 * which should always be the user's requested size.
79e53945 4719 */
929c77fb
EA		 4720 I915_WRITE(DSPSIZE(plane),
4721 ((mode->vdisplay - 1) << 16) |
4722 (mode->hdisplay - 1));
4723 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4724
f564048e
EA		 4725 I915_WRITE(PIPECONF(pipe), pipeconf);
4726 POSTING_READ(PIPECONF(pipe));
929c77fb 4727 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4728
4729 intel_wait_for_vblank(dev, pipe);
4730
f564048e
EA		 4731 I915_WRITE(DSPCNTR(plane), dspcntr);
4732 POSTING_READ(DSPCNTR(plane));
4733
94352cf9 4734 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4735
4736 intel_update_watermarks(dev);
4737
f564048e
EA		 4738 return ret;
4739}
4740
dde86e2d 4741static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4742{
4743 struct drm_i915_private *dev_priv = dev->dev_private;
4744 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4745 struct intel_encoder *encoder;
13d83a67
JB		 4746 u32 temp;
4747 bool has_lvds = false;
199e5d79
KP		 4748 bool has_cpu_edp = false;
4749 bool has_pch_edp = false;
4750 bool has_panel = false;
99eb6a01
KP		 4751 bool has_ck505 = false;
4752 bool can_ssc = false;
13d83a67
JB		 4753
4754 /* We need to take the global config into account */
199e5d79
KP		 4755 list_for_each_entry(encoder, &mode_config->encoder_list,
4756 base.head) {
4757 switch (encoder->type) {
4758 case INTEL_OUTPUT_LVDS:
4759 has_panel = true;
4760 has_lvds = true;
4761 break;
4762 case INTEL_OUTPUT_EDP:
4763 has_panel = true;
4764 if (intel_encoder_is_pch_edp(&encoder->base))
4765 has_pch_edp = true;
4766 else
4767 has_cpu_edp = true;
4768 break;
13d83a67
JB		 4769 }
4770 }
4771
99eb6a01
KP		 4772 if (HAS_PCH_IBX(dev)) {
4773 has_ck505 = dev_priv->display_clock_mode;
4774 can_ssc = has_ck505;
4775 } else {
4776 has_ck505 = false;
4777 can_ssc = true;
4778 }
4779
4780 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4781 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4782 has_ck505);
13d83a67
JB		 4783
4784 /* Ironlake: try to setup display ref clock before DPLL
4785 * enabling. This is only under driver's control after
4786 * PCH B stepping, previous chipset stepping should be
4787 * ignoring this setting.
4788 */
4789 temp = I915_READ(PCH_DREF_CONTROL);
4790 /* Always enable nonspread source */
4791 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4792
99eb6a01
KP		 4793 if (has_ck505)
4794 temp |= DREF_NONSPREAD_CK505_ENABLE;
4795 else
4796 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4797
199e5d79
KP		 4798 if (has_panel) {
4799 temp &= ~DREF_SSC_SOURCE_MASK;
4800 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4801
199e5d79 4802 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4803 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4804 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4805 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4806 } else
4807 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4808
4809 /* Get SSC going before enabling the outputs */
4810 I915_WRITE(PCH_DREF_CONTROL, temp);
4811 POSTING_READ(PCH_DREF_CONTROL);
4812 udelay(200);
4813
13d83a67
JB		 4814 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4815
4816 /* Enable CPU source on CPU attached eDP */
199e5d79 4817 if (has_cpu_edp) {
99eb6a01 4818 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4819 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4820 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4821 }
13d83a67
JB		 4822 else
4823 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4824 } else
4825 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4826
4827 I915_WRITE(PCH_DREF_CONTROL, temp);
4828 POSTING_READ(PCH_DREF_CONTROL);
4829 udelay(200);
4830 } else {
4831 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4832
4833 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4834
4835 /* Turn off CPU output */
4836 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4837
4838 I915_WRITE(PCH_DREF_CONTROL, temp);
4839 POSTING_READ(PCH_DREF_CONTROL);
4840 udelay(200);
4841
4842 /* Turn off the SSC source */
4843 temp &= ~DREF_SSC_SOURCE_MASK;
4844 temp |= DREF_SSC_SOURCE_DISABLE;
4845
4846 /* Turn off SSC1 */
4847 temp &= ~ DREF_SSC1_ENABLE;
4848
13d83a67
JB		 4849 I915_WRITE(PCH_DREF_CONTROL, temp);
4850 POSTING_READ(PCH_DREF_CONTROL);
4851 udelay(200);
4852 }
4853}
4854
dde86e2d
PZ		 4855/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4856static void lpt_init_pch_refclk(struct drm_device *dev)
4857{
4858 struct drm_i915_private *dev_priv = dev->dev_private;
4859 struct drm_mode_config *mode_config = &dev->mode_config;
4860 struct intel_encoder *encoder;
4861 bool has_vga = false;
4862 bool is_sdv = false;
4863 u32 tmp;
4864
4865 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4866 switch (encoder->type) {
4867 case INTEL_OUTPUT_ANALOG:
4868 has_vga = true;
4869 break;
4870 }
4871 }
4872
4873 if (!has_vga)
4874 return;
4875
c00db246
DV		 4876 mutex_lock(&dev_priv->dpio_lock);
4877
dde86e2d
PZ		 4878 /* XXX: Rip out SDV support once Haswell ships for real. */
4879 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4880 is_sdv = true;
4881
4882 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4883 tmp &= ~SBI_SSCCTL_DISABLE;
4884 tmp |= SBI_SSCCTL_PATHALT;
4885 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4886
4887 udelay(24);
4888
4889 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4890 tmp &= ~SBI_SSCCTL_PATHALT;
4891 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4892
4893 if (!is_sdv) {
4894 tmp = I915_READ(SOUTH_CHICKEN2);
4895 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4896 I915_WRITE(SOUTH_CHICKEN2, tmp);
4897
4898 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4899 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4900 DRM_ERROR("FDI mPHY reset assert timeout\n");
4901
4902 tmp = I915_READ(SOUTH_CHICKEN2);
4903 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4904 I915_WRITE(SOUTH_CHICKEN2, tmp);
4905
4906 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4907 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4908 100))
4909 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4910 }
4911
4912 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4913 tmp &= ~(0xFF << 24);
4914 tmp |= (0x12 << 24);
4915 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4916
4917 if (!is_sdv) {
4918 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4919 tmp &= ~(0x3 << 6);
4920 tmp |= (1 << 6) | (1 << 0);
4921 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4922 }
4923
4924 if (is_sdv) {
4925 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4926 tmp |= 0x7FFF;
4927 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4928 }
4929
4930 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4931 tmp |= (1 << 11);
4932 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4933
4934 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4935 tmp |= (1 << 11);
4936 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4937
4938 if (is_sdv) {
4939 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4940 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4941 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4942
4943 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4944 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4945 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4946
4947 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4948 tmp |= (0x3F << 8);
4949 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4950
4951 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4952 tmp |= (0x3F << 8);
4953 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4954 }
4955
4956 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4957 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4958 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4959
4960 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4961 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4962 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4963
4964 if (!is_sdv) {
4965 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4966 tmp &= ~(7 << 13);
4967 tmp |= (5 << 13);
4968 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4969
4970 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4971 tmp &= ~(7 << 13);
4972 tmp |= (5 << 13);
4973 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4974 }
4975
4976 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4977 tmp &= ~0xFF;
4978 tmp |= 0x1C;
4979 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4980
4981 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4982 tmp &= ~0xFF;
4983 tmp |= 0x1C;
4984 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
4985
4986 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
4987 tmp &= ~(0xFF << 16);
4988 tmp |= (0x1C << 16);
4989 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
4990
4991 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
4992 tmp &= ~(0xFF << 16);
4993 tmp |= (0x1C << 16);
4994 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
4995
4996 if (!is_sdv) {
4997 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
4998 tmp |= (1 << 27);
4999 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5000
5001 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5002 tmp |= (1 << 27);
5003 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5004
5005 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5006 tmp &= ~(0xF << 28);
5007 tmp |= (4 << 28);
5008 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5009
5010 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5011 tmp &= ~(0xF << 28);
5012 tmp |= (4 << 28);
5013 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5014 }
5015
5016 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5017 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5018 tmp |= SBI_DBUFF0_ENABLE;
5019 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5020
5021 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5022}
5023
5024/*
5025 * Initialize reference clocks when the driver loads
5026 */
5027void intel_init_pch_refclk(struct drm_device *dev)
5028{
5029 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5030 ironlake_init_pch_refclk(dev);
5031 else if (HAS_PCH_LPT(dev))
5032 lpt_init_pch_refclk(dev);
5033}
5034
d9d444cb
JB		 5035static int ironlake_get_refclk(struct drm_crtc *crtc)
5036{
5037 struct drm_device *dev = crtc->dev;
5038 struct drm_i915_private *dev_priv = dev->dev_private;
5039 struct intel_encoder *encoder;
d9d444cb
JB		 5040 struct intel_encoder *edp_encoder = NULL;
5041 int num_connectors = 0;
5042 bool is_lvds = false;
5043
6c2b7c12 5044 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5045 switch (encoder->type) {
5046 case INTEL_OUTPUT_LVDS:
5047 is_lvds = true;
5048 break;
5049 case INTEL_OUTPUT_EDP:
5050 edp_encoder = encoder;
5051 break;
5052 }
5053 num_connectors++;
5054 }
5055
5056 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5057 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5058 dev_priv->lvds_ssc_freq);
5059 return dev_priv->lvds_ssc_freq * 1000;
5060 }
5061
5062 return 120000;
5063}
5064
c8203565 5065static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5066 struct drm_display_mode *adjusted_mode,
c8203565 5067 bool dither)
79e53945 5068{
c8203565 5069 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5071 int pipe = intel_crtc->pipe;
c8203565
PZ		 5072 uint32_t val;
5073
5074 val = I915_READ(PIPECONF(pipe));
5075
dfd07d72 5076 val &= ~PIPECONF_BPC_MASK;
c8203565
PZ		 5077 switch (intel_crtc->bpp) {
5078 case 18:
dfd07d72 5079 val |= PIPECONF_6BPC;
c8203565
PZ		 5080 break;
5081 case 24:
dfd07d72 5082 val |= PIPECONF_8BPC;
c8203565
PZ		 5083 break;
5084 case 30:
dfd07d72 5085 val |= PIPECONF_10BPC;
c8203565
PZ		 5086 break;
5087 case 36:
dfd07d72 5088 val |= PIPECONF_12BPC;
c8203565
PZ		 5089 break;
5090 default:
cc769b62
PZ		 5091 /* Case prevented by intel_choose_pipe_bpp_dither. */
5092 BUG();
c8203565
PZ		 5093 }
5094
5095 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5096 if (dither)
5097 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5098
5099 val &= ~PIPECONF_INTERLACE_MASK;
5100 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5101 val |= PIPECONF_INTERLACED_ILK;
5102 else
5103 val |= PIPECONF_PROGRESSIVE;
5104
3685a8f3
VS		 5105 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5106 val |= PIPECONF_COLOR_RANGE_SELECT;
5107 else
5108 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5109
c8203565
PZ		 5110 I915_WRITE(PIPECONF(pipe), val);
5111 POSTING_READ(PIPECONF(pipe));
5112}
5113
ee2b0b38
PZ		 5114static void haswell_set_pipeconf(struct drm_crtc *crtc,
5115 struct drm_display_mode *adjusted_mode,
5116 bool dither)
5117{
5118 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5120 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5121 uint32_t val;
5122
702e7a56 5123 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5124
5125 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5126 if (dither)
5127 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5128
5129 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5130 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5131 val |= PIPECONF_INTERLACED_ILK;
5132 else
5133 val |= PIPECONF_PROGRESSIVE;
5134
702e7a56
PZ		 5135 I915_WRITE(PIPECONF(cpu_transcoder), val);
5136 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5137}
5138
6591c6e4
PZ		 5139static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5140 struct drm_display_mode *adjusted_mode,
5141 intel_clock_t *clock,
5142 bool *has_reduced_clock,
5143 intel_clock_t *reduced_clock)
5144{
5145 struct drm_device *dev = crtc->dev;
5146 struct drm_i915_private *dev_priv = dev->dev_private;
5147 struct intel_encoder *intel_encoder;
5148 int refclk;
d4906093 5149 const intel_limit_t *limit;
6591c6e4 5150 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5151
6591c6e4
PZ		 5152 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5153 switch (intel_encoder->type) {
79e53945
JB		 5154 case INTEL_OUTPUT_LVDS:
5155 is_lvds = true;
5156 break;
5157 case INTEL_OUTPUT_SDVO:
7d57382e 5158 case INTEL_OUTPUT_HDMI:
79e53945 5159 is_sdvo = true;
6591c6e4 5160 if (intel_encoder->needs_tv_clock)
e2f0ba97 5161 is_tv = true;
79e53945 5162 break;
79e53945
JB		 5163 case INTEL_OUTPUT_TVOUT:
5164 is_tv = true;
5165 break;
79e53945
JB		 5166 }
5167 }
5168
d9d444cb 5169 refclk = ironlake_get_refclk(crtc);
79e53945 5170
d4906093
ML		 5171 /*
5172 * Returns a set of divisors for the desired target clock with the given
5173 * refclk, or FALSE. The returned values represent the clock equation:
5174 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5175 */
1b894b59 5176 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5177 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5178 clock);
5179 if (!ret)
5180 return false;
cda4b7d3 5181
ddc9003c 5182 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5183 /*
5184 * Ensure we match the reduced clock's P to the target clock.
5185 * If the clocks don't match, we can't switch the display clock
5186 * by using the FP0/FP1. In such case we will disable the LVDS
5187 * downclock feature.
5188 */
6591c6e4
PZ		 5189 *has_reduced_clock = limit->find_pll(limit, crtc,
5190 dev_priv->lvds_downclock,
5191 refclk,
5192 clock,
5193 reduced_clock);
652c393a 5194 }
61e9653f
DV		 5195
5196 if (is_sdvo && is_tv)
6591c6e4
PZ		 5197 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5198
5199 return true;
5200}
5201
01a415fd
DV		 5202static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5203{
5204 struct drm_i915_private *dev_priv = dev->dev_private;
5205 uint32_t temp;
5206
5207 temp = I915_READ(SOUTH_CHICKEN1);
5208 if (temp & FDI_BC_BIFURCATION_SELECT)
5209 return;
5210
5211 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5212 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5213
5214 temp |= FDI_BC_BIFURCATION_SELECT;
5215 DRM_DEBUG_KMS("enabling fdi C rx\n");
5216 I915_WRITE(SOUTH_CHICKEN1, temp);
5217 POSTING_READ(SOUTH_CHICKEN1);
5218}
5219
5220static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5221{
5222 struct drm_device *dev = intel_crtc->base.dev;
5223 struct drm_i915_private *dev_priv = dev->dev_private;
5224 struct intel_crtc *pipe_B_crtc =
5225 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5226
5227 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5228 intel_crtc->pipe, intel_crtc->fdi_lanes);
5229 if (intel_crtc->fdi_lanes > 4) {
5230 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5231 intel_crtc->pipe, intel_crtc->fdi_lanes);
5232 /* Clamp lanes to avoid programming the hw with bogus values. */
5233 intel_crtc->fdi_lanes = 4;
5234
5235 return false;
5236 }
5237
5238 if (dev_priv->num_pipe == 2)
5239 return true;
5240
5241 switch (intel_crtc->pipe) {
5242 case PIPE_A:
5243 return true;
5244 case PIPE_B:
5245 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5246 intel_crtc->fdi_lanes > 2) {
5247 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5248 intel_crtc->pipe, intel_crtc->fdi_lanes);
5249 /* Clamp lanes to avoid programming the hw with bogus values. */
5250 intel_crtc->fdi_lanes = 2;
5251
5252 return false;
5253 }
5254
5255 if (intel_crtc->fdi_lanes > 2)
5256 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5257 else
5258 cpt_enable_fdi_bc_bifurcation(dev);
5259
5260 return true;
5261 case PIPE_C:
5262 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5263 if (intel_crtc->fdi_lanes > 2) {
5264 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5265 intel_crtc->pipe, intel_crtc->fdi_lanes);
5266 /* Clamp lanes to avoid programming the hw with bogus values. */
5267 intel_crtc->fdi_lanes = 2;
5268
5269 return false;
5270 }
5271 } else {
5272 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5273 return false;
5274 }
5275
5276 cpt_enable_fdi_bc_bifurcation(dev);
5277
5278 return true;
5279 default:
5280 BUG();
5281 }
5282}
5283
d4b1931c
PZ		 5284int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5285{
5286 /*
5287 * Account for spread spectrum to avoid
5288 * oversubscribing the link. Max center spread
5289 * is 2.5%; use 5% for safety's sake.
5290 */
5291 u32 bps = target_clock * bpp * 21 / 20;
5292 return bps / (link_bw * 8) + 1;
5293}
5294
f48d8f23
PZ		 5295static void ironlake_set_m_n(struct drm_crtc *crtc,
5296 struct drm_display_mode *mode,
5297 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5298{
5299 struct drm_device *dev = crtc->dev;
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5302 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5303 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5304 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5305 int target_clock, pixel_multiplier, lane, link_bw;
5306 bool is_dp = false, is_cpu_edp = false;
79e53945 5307
f48d8f23
PZ		 5308 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5309 switch (intel_encoder->type) {
a4fc5ed6
KP		 5310 case INTEL_OUTPUT_DISPLAYPORT:
5311 is_dp = true;
5312 break;
32f9d658 5313 case INTEL_OUTPUT_EDP:
e3aef172 5314 is_dp = true;
f48d8f23 5315 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5316 is_cpu_edp = true;
f48d8f23 5317 edp_encoder = intel_encoder;
32f9d658 5318 break;
79e53945 5319 }
79e53945 5320 }
61e9653f 5321
2c07245f 5322 /* FDI link */
8febb297
EA		 5323 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5324 lane = 0;
5325 /* CPU eDP doesn't require FDI link, so just set DP M/N
5326 according to current link config */
e3aef172 5327 if (is_cpu_edp) {
e3aef172 5328 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5329 } else {
8febb297
EA		 5330 /* FDI is a binary signal running at ~2.7GHz, encoding
5331 * each output octet as 10 bits. The actual frequency
5332 * is stored as a divider into a 100MHz clock, and the
5333 * mode pixel clock is stored in units of 1KHz.
5334 * Hence the bw of each lane in terms of the mode signal
5335 * is:
5336 */
5337 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5338 }
58a27471 5339
94bf2ced
DV		 5340 /* [e]DP over FDI requires target mode clock instead of link clock. */
5341 if (edp_encoder)
5342 target_clock = intel_edp_target_clock(edp_encoder, mode);
5343 else if (is_dp)
5344 target_clock = mode->clock;
5345 else
5346 target_clock = adjusted_mode->clock;
5347
d4b1931c
PZ		 5348 if (!lane)
5349 lane = ironlake_get_lanes_required(target_clock, link_bw,
5350 intel_crtc->bpp);
2c07245f 5351
8febb297
EA		 5352 intel_crtc->fdi_lanes = lane;
5353
5354 if (pixel_multiplier > 1)
5355 link_bw *= pixel_multiplier;
e69d0bc1 5356 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5357
afe2fcf5
PZ		 5358 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5359 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5360 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5361 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5362}
5363
de13a2e3
PZ		 5364static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5365 struct drm_display_mode *adjusted_mode,
5366 intel_clock_t *clock, u32 fp)
79e53945 5367{
de13a2e3 5368 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5369 struct drm_device *dev = crtc->dev;
5370 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5371 struct intel_encoder *intel_encoder;
5372 uint32_t dpll;
5373 int factor, pixel_multiplier, num_connectors = 0;
5374 bool is_lvds = false, is_sdvo = false, is_tv = false;
5375 bool is_dp = false, is_cpu_edp = false;
79e53945 5376
de13a2e3
PZ		 5377 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5378 switch (intel_encoder->type) {
79e53945
JB		 5379 case INTEL_OUTPUT_LVDS:
5380 is_lvds = true;
5381 break;
5382 case INTEL_OUTPUT_SDVO:
7d57382e 5383 case INTEL_OUTPUT_HDMI:
79e53945 5384 is_sdvo = true;
de13a2e3 5385 if (intel_encoder->needs_tv_clock)
e2f0ba97 5386 is_tv = true;
79e53945 5387 break;
79e53945
JB		 5388 case INTEL_OUTPUT_TVOUT:
5389 is_tv = true;
5390 break;
a4fc5ed6
KP		 5391 case INTEL_OUTPUT_DISPLAYPORT:
5392 is_dp = true;
5393 break;
32f9d658 5394 case INTEL_OUTPUT_EDP:
e3aef172 5395 is_dp = true;
de13a2e3 5396 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5397 is_cpu_edp = true;
32f9d658 5398 break;
79e53945 5399 }
43565a06 5400
c751ce4f 5401 num_connectors++;
79e53945 5402 }
79e53945 5403
c1858123 5404 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5405 factor = 21;
5406 if (is_lvds) {
5407 if ((intel_panel_use_ssc(dev_priv) &&
5408 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5409 intel_is_dual_link_lvds(dev))
8febb297
EA		 5410 factor = 25;
5411 } else if (is_sdvo && is_tv)
5412 factor = 20;
c1858123 5413
de13a2e3 5414 if (clock->m < factor * clock->n)
8febb297 5415 fp |= FP_CB_TUNE;
2c07245f 5416
5eddb70b 5417 dpll = 0;
2c07245f 5418
a07d6787
EA		 5419 if (is_lvds)
5420 dpll |= DPLLB_MODE_LVDS;
5421 else
5422 dpll |= DPLLB_MODE_DAC_SERIAL;
5423 if (is_sdvo) {
de13a2e3 5424 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5425 if (pixel_multiplier > 1) {
5426 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5427 }
a07d6787
EA		 5428 dpll |= DPLL_DVO_HIGH_SPEED;
5429 }
e3aef172 5430 if (is_dp && !is_cpu_edp)
a07d6787 5431 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5432
a07d6787 5433 /* compute bitmask from p1 value */
de13a2e3 5434 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5435 /* also FPA1 */
de13a2e3 5436 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5437
de13a2e3 5438 switch (clock->p2) {
a07d6787
EA		 5439 case 5:
5440 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5441 break;
5442 case 7:
5443 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5444 break;
5445 case 10:
5446 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5447 break;
5448 case 14:
5449 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5450 break;
79e53945
JB		 5451 }
5452
43565a06
KH		 5453 if (is_sdvo && is_tv)
5454 dpll |= PLL_REF_INPUT_TVCLKINBC;
5455 else if (is_tv)
79e53945 5456 /* XXX: just matching BIOS for now */
43565a06 5457 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5458 dpll |= 3;
a7615030 5459 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5460 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5461 else
5462 dpll |= PLL_REF_INPUT_DREFCLK;
5463
de13a2e3
PZ		 5464 return dpll;
5465}
5466
5467static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5468 struct drm_display_mode *mode,
5469 struct drm_display_mode *adjusted_mode,
5470 int x, int y,
5471 struct drm_framebuffer *fb)
5472{
5473 struct drm_device *dev = crtc->dev;
5474 struct drm_i915_private *dev_priv = dev->dev_private;
5475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5476 int pipe = intel_crtc->pipe;
5477 int plane = intel_crtc->plane;
5478 int num_connectors = 0;
5479 intel_clock_t clock, reduced_clock;
5480 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5481 bool ok, has_reduced_clock = false;
5482 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5483 struct intel_encoder *encoder;
de13a2e3 5484 int ret;
01a415fd 5485 bool dither, fdi_config_ok;
de13a2e3
PZ		 5486
5487 for_each_encoder_on_crtc(dev, crtc, encoder) {
5488 switch (encoder->type) {
5489 case INTEL_OUTPUT_LVDS:
5490 is_lvds = true;
5491 break;
de13a2e3
PZ		 5492 case INTEL_OUTPUT_DISPLAYPORT:
5493 is_dp = true;
5494 break;
5495 case INTEL_OUTPUT_EDP:
5496 is_dp = true;
e2f12b07 5497 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5498 is_cpu_edp = true;
5499 break;
5500 }
5501
5502 num_connectors++;
a07d6787 5503 }
79e53945 5504
5dc5298b
PZ		 5505 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5506 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5507
de13a2e3
PZ		 5508 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5509 &has_reduced_clock, &reduced_clock);
5510 if (!ok) {
5511 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5512 return -EINVAL;
79e53945
JB		 5513 }
5514
de13a2e3
PZ		 5515 /* Ensure that the cursor is valid for the new mode before changing... */
5516 intel_crtc_update_cursor(crtc, true);
5517
5518 /* determine panel color depth */
c8241969
JN		 5519 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5520 adjusted_mode);
de13a2e3
PZ		 5521 if (is_lvds && dev_priv->lvds_dither)
5522 dither = true;
5523
5524 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5525 if (has_reduced_clock)
5526 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5527 reduced_clock.m2;
5528
5529 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5530
f7cb34d4 5531 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5532 drm_mode_debug_printmodeline(mode);
5533
5dc5298b
PZ		 5534 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5535 if (!is_cpu_edp) {
ee7b9f93 5536 struct intel_pch_pll *pll;
4b645f14 5537
ee7b9f93
JB		 5538 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5539 if (pll == NULL) {
5540 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5541 pipe);
4b645f14
JB		 5542 return -EINVAL;
5543 }
ee7b9f93
JB		 5544 } else
5545 intel_put_pch_pll(intel_crtc);
79e53945 5546
2f0c2ad1 5547 if (is_dp && !is_cpu_edp)
a4fc5ed6 5548 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5549
dafd226c
DV		 5550 for_each_encoder_on_crtc(dev, crtc, encoder)
5551 if (encoder->pre_pll_enable)
5552 encoder->pre_pll_enable(encoder);
79e53945 5553
ee7b9f93
JB		 5554 if (intel_crtc->pch_pll) {
5555 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5556
32f9d658 5557 /* Wait for the clocks to stabilize. */
ee7b9f93 5558 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5559 udelay(150);
5560
8febb297
EA		 5561 /* The pixel multiplier can only be updated once the
5562 * DPLL is enabled and the clocks are stable.
5563 *
5564 * So write it again.
5565 */
ee7b9f93 5566 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5567 }
79e53945 5568
5eddb70b 5569 intel_crtc->lowfreq_avail = false;
ee7b9f93 5570 if (intel_crtc->pch_pll) {
4b645f14 5571 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5572 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5573 intel_crtc->lowfreq_avail = true;
4b645f14 5574 } else {
ee7b9f93 5575 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5576 }
5577 }
5578
b0e77b9c 5579 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5580
01a415fd
DV		 5581 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5582 * ironlake_check_fdi_lanes. */
f48d8f23 5583 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5584
01a415fd 5585 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5586
c8203565 5587 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5588
9d0498a2 5589 intel_wait_for_vblank(dev, pipe);
79e53945 5590
a1f9e77e
PZ		 5591 /* Set up the display plane register */
5592 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5593 POSTING_READ(DSPCNTR(plane));
79e53945 5594
94352cf9 5595 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5596
5597 intel_update_watermarks(dev);
5598
1f8eeabf
ED		 5599 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5600
01a415fd 5601 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5602}
5603
09b4ddf9
PZ		 5604static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5605 struct drm_display_mode *mode,
5606 struct drm_display_mode *adjusted_mode,
5607 int x, int y,
5608 struct drm_framebuffer *fb)
5609{
5610 struct drm_device *dev = crtc->dev;
5611 struct drm_i915_private *dev_priv = dev->dev_private;
5612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5613 int pipe = intel_crtc->pipe;
5614 int plane = intel_crtc->plane;
5615 int num_connectors = 0;
ed7ef439 5616 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5617 struct intel_encoder *encoder;
09b4ddf9
PZ		 5618 int ret;
5619 bool dither;
5620
5621 for_each_encoder_on_crtc(dev, crtc, encoder) {
5622 switch (encoder->type) {
09b4ddf9
PZ		 5623 case INTEL_OUTPUT_DISPLAYPORT:
5624 is_dp = true;
5625 break;
5626 case INTEL_OUTPUT_EDP:
5627 is_dp = true;
5628 if (!intel_encoder_is_pch_edp(&encoder->base))
5629 is_cpu_edp = true;
5630 break;
5631 }
5632
5633 num_connectors++;
5634 }
5635
5dc5298b
PZ		 5636 /* We are not sure yet this won't happen. */
5637 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5638 INTEL_PCH_TYPE(dev));
5639
5640 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5641 num_connectors, pipe_name(pipe));
5642
702e7a56 5643 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5644 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5645
5646 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5647
6441ab5f
PZ		 5648 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5649 return -EINVAL;
5650
09b4ddf9
PZ		 5651 /* Ensure that the cursor is valid for the new mode before changing... */
5652 intel_crtc_update_cursor(crtc, true);
5653
5654 /* determine panel color depth */
c8241969
JN		 5655 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5656 adjusted_mode);
09b4ddf9 5657
09b4ddf9
PZ		 5658 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5659 drm_mode_debug_printmodeline(mode);
5660
ed7ef439 5661 if (is_dp && !is_cpu_edp)
09b4ddf9 5662 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5663
5664 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5665
5666 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5667
1eb8dfec
PZ		 5668 if (!is_dp || is_cpu_edp)
5669 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5670
ee2b0b38 5671 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5672
09b4ddf9
PZ		 5673 /* Set up the display plane register */
5674 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5675 POSTING_READ(DSPCNTR(plane));
5676
5677 ret = intel_pipe_set_base(crtc, x, y, fb);
5678
5679 intel_update_watermarks(dev);
5680
5681 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5682
1f803ee5 5683 return ret;
79e53945
JB		 5684}
5685
f564048e
EA		 5686static int intel_crtc_mode_set(struct drm_crtc *crtc,
5687 struct drm_display_mode *mode,
5688 struct drm_display_mode *adjusted_mode,
5689 int x, int y,
94352cf9 5690 struct drm_framebuffer *fb)
f564048e
EA		 5691{
5692 struct drm_device *dev = crtc->dev;
5693 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5694 struct drm_encoder_helper_funcs *encoder_funcs;
5695 struct intel_encoder *encoder;
0b701d27
EA		 5696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5697 int pipe = intel_crtc->pipe;
f564048e
EA		 5698 int ret;
5699
cc464b2a
PZ		 5700 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5701 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5702 else
5703 intel_crtc->cpu_transcoder = pipe;
5704
0b701d27 5705 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5706
f564048e 5707 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5708 x, y, fb);
79e53945 5709 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5710
9256aa19
DV		 5711 if (ret != 0)
5712 return ret;
5713
5714 for_each_encoder_on_crtc(dev, crtc, encoder) {
5715 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5716 encoder->base.base.id,
5717 drm_get_encoder_name(&encoder->base),
5718 mode->base.id, mode->name);
5719 encoder_funcs = encoder->base.helper_private;
5720 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5721 }
5722
5723 return 0;
79e53945
JB		 5724}
5725
3a9627f4
WF		 5726static bool intel_eld_uptodate(struct drm_connector *connector,
5727 int reg_eldv, uint32_t bits_eldv,
5728 int reg_elda, uint32_t bits_elda,
5729 int reg_edid)
5730{
5731 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5732 uint8_t *eld = connector->eld;
5733 uint32_t i;
5734
5735 i = I915_READ(reg_eldv);
5736 i &= bits_eldv;
5737
5738 if (!eld[0])
5739 return !i;
5740
5741 if (!i)
5742 return false;
5743
5744 i = I915_READ(reg_elda);
5745 i &= ~bits_elda;
5746 I915_WRITE(reg_elda, i);
5747
5748 for (i = 0; i < eld[2]; i++)
5749 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5750 return false;
5751
5752 return true;
5753}
5754
e0dac65e
WF		 5755static void g4x_write_eld(struct drm_connector *connector,
5756 struct drm_crtc *crtc)
5757{
5758 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5759 uint8_t *eld = connector->eld;
5760 uint32_t eldv;
5761 uint32_t len;
5762 uint32_t i;
5763
5764 i = I915_READ(G4X_AUD_VID_DID);
5765
5766 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5767 eldv = G4X_ELDV_DEVCL_DEVBLC;
5768 else
5769 eldv = G4X_ELDV_DEVCTG;
5770
3a9627f4
WF		 5771 if (intel_eld_uptodate(connector,
5772 G4X_AUD_CNTL_ST, eldv,
5773 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5774 G4X_HDMIW_HDMIEDID))
5775 return;
5776
e0dac65e
WF		 5777 i = I915_READ(G4X_AUD_CNTL_ST);
5778 i &= ~(eldv | G4X_ELD_ADDR);
5779 len = (i >> 9) & 0x1f; /* ELD buffer size */
5780 I915_WRITE(G4X_AUD_CNTL_ST, i);
5781
5782 if (!eld[0])
5783 return;
5784
5785 len = min_t(uint8_t, eld[2], len);
5786 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5787 for (i = 0; i < len; i++)
5788 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5789
5790 i = I915_READ(G4X_AUD_CNTL_ST);
5791 i |= eldv;
5792 I915_WRITE(G4X_AUD_CNTL_ST, i);
5793}
5794
83358c85
WX		 5795static void haswell_write_eld(struct drm_connector *connector,
5796 struct drm_crtc *crtc)
5797{
5798 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5799 uint8_t *eld = connector->eld;
5800 struct drm_device *dev = crtc->dev;
7b9f35a6 5801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5802 uint32_t eldv;
5803 uint32_t i;
5804 int len;
5805 int pipe = to_intel_crtc(crtc)->pipe;
5806 int tmp;
5807
5808 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5809 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5810 int aud_config = HSW_AUD_CFG(pipe);
5811 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5812
5813
5814 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5815
5816 /* Audio output enable */
5817 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5818 tmp = I915_READ(aud_cntrl_st2);
5819 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5820 I915_WRITE(aud_cntrl_st2, tmp);
5821
5822 /* Wait for 1 vertical blank */
5823 intel_wait_for_vblank(dev, pipe);
5824
5825 /* Set ELD valid state */
5826 tmp = I915_READ(aud_cntrl_st2);
5827 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5828 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5829 I915_WRITE(aud_cntrl_st2, tmp);
5830 tmp = I915_READ(aud_cntrl_st2);
5831 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5832
5833 /* Enable HDMI mode */
5834 tmp = I915_READ(aud_config);
5835 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5836 /* clear N_programing_enable and N_value_index */
5837 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5838 I915_WRITE(aud_config, tmp);
5839
5840 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5841
5842 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5843 intel_crtc->eld_vld = true;
83358c85
WX		 5844
5845 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5846 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5847 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5848 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5849 } else
5850 I915_WRITE(aud_config, 0);
5851
5852 if (intel_eld_uptodate(connector,
5853 aud_cntrl_st2, eldv,
5854 aud_cntl_st, IBX_ELD_ADDRESS,
5855 hdmiw_hdmiedid))
5856 return;
5857
5858 i = I915_READ(aud_cntrl_st2);
5859 i &= ~eldv;
5860 I915_WRITE(aud_cntrl_st2, i);
5861
5862 if (!eld[0])
5863 return;
5864
5865 i = I915_READ(aud_cntl_st);
5866 i &= ~IBX_ELD_ADDRESS;
5867 I915_WRITE(aud_cntl_st, i);
5868 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5869 DRM_DEBUG_DRIVER("port num:%d\n", i);
5870
5871 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5872 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5873 for (i = 0; i < len; i++)
5874 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5875
5876 i = I915_READ(aud_cntrl_st2);
5877 i |= eldv;
5878 I915_WRITE(aud_cntrl_st2, i);
5879
5880}
5881
e0dac65e
WF		 5882static void ironlake_write_eld(struct drm_connector *connector,
5883 struct drm_crtc *crtc)
5884{
5885 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5886 uint8_t *eld = connector->eld;
5887 uint32_t eldv;
5888 uint32_t i;
5889 int len;
5890 int hdmiw_hdmiedid;
b6daa025 5891 int aud_config;
e0dac65e
WF		 5892 int aud_cntl_st;
5893 int aud_cntrl_st2;
9b138a83 5894 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5895
b3f33cbf 5896 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5897 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5898 aud_config = IBX_AUD_CFG(pipe);
5899 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5900 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5901 } else {
9b138a83
WX		 5902 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5903 aud_config = CPT_AUD_CFG(pipe);
5904 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5905 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5906 }
5907
9b138a83 5908 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5909
5910 i = I915_READ(aud_cntl_st);
9b138a83 5911 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5912 if (!i) {
5913 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5914 /* operate blindly on all ports */
1202b4c6
WF		 5915 eldv = IBX_ELD_VALIDB;
5916 eldv |= IBX_ELD_VALIDB << 4;
5917 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5918 } else {
5919 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5920 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5921 }
5922
3a9627f4
WF		 5923 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5924 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5925 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5926 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5927 } else
5928 I915_WRITE(aud_config, 0);
e0dac65e 5929
3a9627f4
WF		 5930 if (intel_eld_uptodate(connector,
5931 aud_cntrl_st2, eldv,
5932 aud_cntl_st, IBX_ELD_ADDRESS,
5933 hdmiw_hdmiedid))
5934 return;
5935
e0dac65e
WF		 5936 i = I915_READ(aud_cntrl_st2);
5937 i &= ~eldv;
5938 I915_WRITE(aud_cntrl_st2, i);
5939
5940 if (!eld[0])
5941 return;
5942
e0dac65e 5943 i = I915_READ(aud_cntl_st);
1202b4c6 5944 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5945 I915_WRITE(aud_cntl_st, i);
5946
5947 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5948 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5949 for (i = 0; i < len; i++)
5950 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5951
5952 i = I915_READ(aud_cntrl_st2);
5953 i |= eldv;
5954 I915_WRITE(aud_cntrl_st2, i);
5955}
5956
5957void intel_write_eld(struct drm_encoder *encoder,
5958 struct drm_display_mode *mode)
5959{
5960 struct drm_crtc *crtc = encoder->crtc;
5961 struct drm_connector *connector;
5962 struct drm_device *dev = encoder->dev;
5963 struct drm_i915_private *dev_priv = dev->dev_private;
5964
5965 connector = drm_select_eld(encoder, mode);
5966 if (!connector)
5967 return;
5968
5969 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5970 connector->base.id,
5971 drm_get_connector_name(connector),
5972 connector->encoder->base.id,
5973 drm_get_encoder_name(connector->encoder));
5974
5975 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5976
5977 if (dev_priv->display.write_eld)
5978 dev_priv->display.write_eld(connector, crtc);
5979}
5980
79e53945
JB		 5981/** Loads the palette/gamma unit for the CRTC with the prepared values */
5982void intel_crtc_load_lut(struct drm_crtc *crtc)
5983{
5984 struct drm_device *dev = crtc->dev;
5985 struct drm_i915_private *dev_priv = dev->dev_private;
5986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5987 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5988 int i;
5989
5990 /* The clocks have to be on to load the palette. */
aed3f09d 5991 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5992 return;
5993
f2b115e6 5994 /* use legacy palette for Ironlake */
bad720ff 5995 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5996 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5997
79e53945
JB		 5998 for (i = 0; i < 256; i++) {
5999 I915_WRITE(palreg + 4 * i,
6000 (intel_crtc->lut_r[i] << 16) |
6001 (intel_crtc->lut_g[i] << 8) |
6002 intel_crtc->lut_b[i]);
6003 }
6004}
6005
560b85bb
CW		 6006static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6007{
6008 struct drm_device *dev = crtc->dev;
6009 struct drm_i915_private *dev_priv = dev->dev_private;
6010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6011 bool visible = base != 0;
6012 u32 cntl;
6013
6014 if (intel_crtc->cursor_visible == visible)
6015 return;
6016
9db4a9c7 6017 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6018 if (visible) {
6019 /* On these chipsets we can only modify the base whilst
6020 * the cursor is disabled.
6021 */
9db4a9c7 6022 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6023
6024 cntl &= ~(CURSOR_FORMAT_MASK);
6025 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6026 cntl |= CURSOR_ENABLE |
6027 CURSOR_GAMMA_ENABLE |
6028 CURSOR_FORMAT_ARGB;
6029 } else
6030 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6031 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6032
6033 intel_crtc->cursor_visible = visible;
6034}
6035
6036static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6037{
6038 struct drm_device *dev = crtc->dev;
6039 struct drm_i915_private *dev_priv = dev->dev_private;
6040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6041 int pipe = intel_crtc->pipe;
6042 bool visible = base != 0;
6043
6044 if (intel_crtc->cursor_visible != visible) {
548f245b 6045 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6046 if (base) {
6047 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6048 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6049 cntl |= pipe << 28; /* Connect to correct pipe */
6050 } else {
6051 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6052 cntl |= CURSOR_MODE_DISABLE;
6053 }
9db4a9c7 6054 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6055
6056 intel_crtc->cursor_visible = visible;
6057 }
6058 /* and commit changes on next vblank */
9db4a9c7 6059 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6060}
6061
65a21cd6
JB		 6062static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6063{
6064 struct drm_device *dev = crtc->dev;
6065 struct drm_i915_private *dev_priv = dev->dev_private;
6066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6067 int pipe = intel_crtc->pipe;
6068 bool visible = base != 0;
6069
6070 if (intel_crtc->cursor_visible != visible) {
6071 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6072 if (base) {
6073 cntl &= ~CURSOR_MODE;
6074 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6075 } else {
6076 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6077 cntl |= CURSOR_MODE_DISABLE;
6078 }
6079 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6080
6081 intel_crtc->cursor_visible = visible;
6082 }
6083 /* and commit changes on next vblank */
6084 I915_WRITE(CURBASE_IVB(pipe), base);
6085}
6086
cda4b7d3 6087/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6088static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6089 bool on)
cda4b7d3
CW		 6090{
6091 struct drm_device *dev = crtc->dev;
6092 struct drm_i915_private *dev_priv = dev->dev_private;
6093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6094 int pipe = intel_crtc->pipe;
6095 int x = intel_crtc->cursor_x;
6096 int y = intel_crtc->cursor_y;
560b85bb 6097 u32 base, pos;
cda4b7d3
CW		 6098 bool visible;
6099
6100 pos = 0;
6101
6b383a7f 6102 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6103 base = intel_crtc->cursor_addr;
6104 if (x > (int) crtc->fb->width)
6105 base = 0;
6106
6107 if (y > (int) crtc->fb->height)
6108 base = 0;
6109 } else
6110 base = 0;
6111
6112 if (x < 0) {
6113 if (x + intel_crtc->cursor_width < 0)
6114 base = 0;
6115
6116 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6117 x = -x;
6118 }
6119 pos |= x << CURSOR_X_SHIFT;
6120
6121 if (y < 0) {
6122 if (y + intel_crtc->cursor_height < 0)
6123 base = 0;
6124
6125 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6126 y = -y;
6127 }
6128 pos |= y << CURSOR_Y_SHIFT;
6129
6130 visible = base != 0;
560b85bb 6131 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6132 return;
6133
0cd83aa9 6134 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6135 I915_WRITE(CURPOS_IVB(pipe), pos);
6136 ivb_update_cursor(crtc, base);
6137 } else {
6138 I915_WRITE(CURPOS(pipe), pos);
6139 if (IS_845G(dev) || IS_I865G(dev))
6140 i845_update_cursor(crtc, base);
6141 else
6142 i9xx_update_cursor(crtc, base);
6143 }
cda4b7d3
CW		 6144}
6145
79e53945 6146static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6147 struct drm_file *file,
79e53945
JB		 6148 uint32_t handle,
6149 uint32_t width, uint32_t height)
6150{
6151 struct drm_device *dev = crtc->dev;
6152 struct drm_i915_private *dev_priv = dev->dev_private;
6153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6154 struct drm_i915_gem_object *obj;
cda4b7d3 6155 uint32_t addr;
3f8bc370 6156 int ret;
79e53945 6157
79e53945
JB		 6158 /* if we want to turn off the cursor ignore width and height */
6159 if (!handle) {
28c97730 6160 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6161 addr = 0;
05394f39 6162 obj = NULL;
5004417d 6163 mutex_lock(&dev->struct_mutex);
3f8bc370 6164 goto finish;
79e53945
JB		 6165 }
6166
6167 /* Currently we only support 64x64 cursors */
6168 if (width != 64 || height != 64) {
6169 DRM_ERROR("we currently only support 64x64 cursors\n");
6170 return -EINVAL;
6171 }
6172
05394f39 6173 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6174 if (&obj->base == NULL)
79e53945
JB		 6175 return -ENOENT;
6176
05394f39 6177 if (obj->base.size < width * height * 4) {
79e53945 6178 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6179 ret = -ENOMEM;
6180 goto fail;
79e53945
JB		 6181 }
6182
71acb5eb 6183 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6184 mutex_lock(&dev->struct_mutex);
b295d1b6 6185 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6186 if (obj->tiling_mode) {
6187 DRM_ERROR("cursor cannot be tiled\n");
6188 ret = -EINVAL;
6189 goto fail_locked;
6190 }
6191
2da3b9b9 6192 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6193 if (ret) {
6194 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6195 goto fail_locked;
e7b526bb
CW		 6196 }
6197
d9e86c0e
CW		 6198 ret = i915_gem_object_put_fence(obj);
6199 if (ret) {
2da3b9b9 6200 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6201 goto fail_unpin;
6202 }
6203
05394f39 6204 addr = obj->gtt_offset;
71acb5eb 6205 } else {
6eeefaf3 6206 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6207 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6208 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6209 align);
71acb5eb
DA		 6210 if (ret) {
6211 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6212 goto fail_locked;
71acb5eb 6213 }
05394f39 6214 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6215 }
6216
a6c45cf0 6217 if (IS_GEN2(dev))
14b60391
JB		 6218 I915_WRITE(CURSIZE, (height << 12) | width);
6219
3f8bc370 6220 finish:
3f8bc370 6221 if (intel_crtc->cursor_bo) {
b295d1b6 6222 if (dev_priv->info->cursor_needs_physical) {
05394f39 6223 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6224 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6225 } else
6226 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6227 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6228 }
80824003 6229
7f9872e0 6230 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6231
6232 intel_crtc->cursor_addr = addr;
05394f39 6233 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6234 intel_crtc->cursor_width = width;
6235 intel_crtc->cursor_height = height;
6236
6b383a7f 6237 intel_crtc_update_cursor(crtc, true);
3f8bc370 6238
79e53945 6239 return 0;
e7b526bb 6240fail_unpin:
05394f39 6241 i915_gem_object_unpin(obj);
7f9872e0 6242fail_locked:
34b8686e 6243 mutex_unlock(&dev->struct_mutex);
bc9025bd 6244fail:
05394f39 6245 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6246 return ret;
79e53945
JB		 6247}
6248
6249static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6250{
79e53945 6251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6252
cda4b7d3
CW		 6253 intel_crtc->cursor_x = x;
6254 intel_crtc->cursor_y = y;
652c393a 6255
6b383a7f 6256 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6257
6258 return 0;
6259}
6260
6261/** Sets the color ramps on behalf of RandR */
6262void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6263 u16 blue, int regno)
6264{
6265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6266
6267 intel_crtc->lut_r[regno] = red >> 8;
6268 intel_crtc->lut_g[regno] = green >> 8;
6269 intel_crtc->lut_b[regno] = blue >> 8;
6270}
6271
b8c00ac5
DA		 6272void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6273 u16 *blue, int regno)
6274{
6275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6276
6277 *red = intel_crtc->lut_r[regno] << 8;
6278 *green = intel_crtc->lut_g[regno] << 8;
6279 *blue = intel_crtc->lut_b[regno] << 8;
6280}
6281
79e53945 6282static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6283 u16 *blue, uint32_t start, uint32_t size)
79e53945 6284{
7203425a 6285 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6287
7203425a 6288 for (i = start; i < end; i++) {
79e53945
JB		 6289 intel_crtc->lut_r[i] = red[i] >> 8;
6290 intel_crtc->lut_g[i] = green[i] >> 8;
6291 intel_crtc->lut_b[i] = blue[i] >> 8;
6292 }
6293
6294 intel_crtc_load_lut(crtc);
6295}
6296
6297/**
6298 * Get a pipe with a simple mode set on it for doing load-based monitor
6299 * detection.
6300 *
6301 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6302 * its requirements. The pipe will be connected to no other encoders.
79e53945 6303 *
c751ce4f 6304 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6305 * configured for it. In the future, it could choose to temporarily disable
6306 * some outputs to free up a pipe for its use.
6307 *
6308 * \return crtc, or NULL if no pipes are available.
6309 */
6310
6311/* VESA 640x480x72Hz mode to set on the pipe */
6312static struct drm_display_mode load_detect_mode = {
6313 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6314 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6315};
6316
d2dff872
CW		 6317static struct drm_framebuffer *
6318intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6319 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6320 struct drm_i915_gem_object *obj)
6321{
6322 struct intel_framebuffer *intel_fb;
6323 int ret;
6324
6325 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6326 if (!intel_fb) {
6327 drm_gem_object_unreference_unlocked(&obj->base);
6328 return ERR_PTR(-ENOMEM);
6329 }
6330
6331 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6332 if (ret) {
6333 drm_gem_object_unreference_unlocked(&obj->base);
6334 kfree(intel_fb);
6335 return ERR_PTR(ret);
6336 }
6337
6338 return &intel_fb->base;
6339}
6340
6341static u32
6342intel_framebuffer_pitch_for_width(int width, int bpp)
6343{
6344 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6345 return ALIGN(pitch, 64);
6346}
6347
6348static u32
6349intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6350{
6351 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6352 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6353}
6354
6355static struct drm_framebuffer *
6356intel_framebuffer_create_for_mode(struct drm_device *dev,
6357 struct drm_display_mode *mode,
6358 int depth, int bpp)
6359{
6360 struct drm_i915_gem_object *obj;
0fed39bd 6361 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6362
6363 obj = i915_gem_alloc_object(dev,
6364 intel_framebuffer_size_for_mode(mode, bpp));
6365 if (obj == NULL)
6366 return ERR_PTR(-ENOMEM);
6367
6368 mode_cmd.width = mode->hdisplay;
6369 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6370 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6371 bpp);
5ca0c34a 6372 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6373
6374 return intel_framebuffer_create(dev, &mode_cmd, obj);
6375}
6376
6377static struct drm_framebuffer *
6378mode_fits_in_fbdev(struct drm_device *dev,
6379 struct drm_display_mode *mode)
6380{
6381 struct drm_i915_private *dev_priv = dev->dev_private;
6382 struct drm_i915_gem_object *obj;
6383 struct drm_framebuffer *fb;
6384
6385 if (dev_priv->fbdev == NULL)
6386 return NULL;
6387
6388 obj = dev_priv->fbdev->ifb.obj;
6389 if (obj == NULL)
6390 return NULL;
6391
6392 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6393 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6394 fb->bits_per_pixel))
d2dff872
CW		 6395 return NULL;
6396
01f2c773 6397 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6398 return NULL;
6399
6400 return fb;
6401}
6402
d2434ab7 6403bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6404 struct drm_display_mode *mode,
8261b191 6405 struct intel_load_detect_pipe *old)
79e53945
JB		 6406{
6407 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6408 struct intel_encoder *intel_encoder =
6409 intel_attached_encoder(connector);
79e53945 6410 struct drm_crtc *possible_crtc;
4ef69c7a 6411 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6412 struct drm_crtc *crtc = NULL;
6413 struct drm_device *dev = encoder->dev;
94352cf9 6414 struct drm_framebuffer *fb;
79e53945
JB		 6415 int i = -1;
6416
d2dff872
CW		 6417 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6418 connector->base.id, drm_get_connector_name(connector),
6419 encoder->base.id, drm_get_encoder_name(encoder));
6420
79e53945
JB		 6421 /*
6422 * Algorithm gets a little messy:
7a5e4805 6423 *
79e53945
JB		 6424 * - if the connector already has an assigned crtc, use it (but make
6425 * sure it's on first)
7a5e4805 6426 *
79e53945
JB		 6427 * - try to find the first unused crtc that can drive this connector,
6428 * and use that if we find one
79e53945
JB		 6429 */
6430
6431 /* See if we already have a CRTC for this connector */
6432 if (encoder->crtc) {
6433 crtc = encoder->crtc;
8261b191 6434
24218aac 6435 old->dpms_mode = connector->dpms;
8261b191
CW		 6436 old->load_detect_temp = false;
6437
6438 /* Make sure the crtc and connector are running */
24218aac
DV		 6439 if (connector->dpms != DRM_MODE_DPMS_ON)
6440 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6441
7173188d 6442 return true;
79e53945
JB		 6443 }
6444
6445 /* Find an unused one (if possible) */
6446 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6447 i++;
6448 if (!(encoder->possible_crtcs & (1 << i)))
6449 continue;
6450 if (!possible_crtc->enabled) {
6451 crtc = possible_crtc;
6452 break;
6453 }
79e53945
JB		 6454 }
6455
6456 /*
6457 * If we didn't find an unused CRTC, don't use any.
6458 */
6459 if (!crtc) {
7173188d
CW		 6460 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6461 return false;
79e53945
JB		 6462 }
6463
fc303101
DV		 6464 intel_encoder->new_crtc = to_intel_crtc(crtc);
6465 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6466
6467 intel_crtc = to_intel_crtc(crtc);
24218aac 6468 old->dpms_mode = connector->dpms;
8261b191 6469 old->load_detect_temp = true;
d2dff872 6470 old->release_fb = NULL;
79e53945 6471
6492711d
CW		 6472 if (!mode)
6473 mode = &load_detect_mode;
79e53945 6474
d2dff872
CW		 6475 /* We need a framebuffer large enough to accommodate all accesses
6476 * that the plane may generate whilst we perform load detection.
6477 * We can not rely on the fbcon either being present (we get called
6478 * during its initialisation to detect all boot displays, or it may
6479 * not even exist) or that it is large enough to satisfy the
6480 * requested mode.
6481 */
94352cf9
DV		 6482 fb = mode_fits_in_fbdev(dev, mode);
6483 if (fb == NULL) {
d2dff872 6484 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6485 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6486 old->release_fb = fb;
d2dff872
CW		 6487 } else
6488 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6489 if (IS_ERR(fb)) {
d2dff872 6490 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
0e8b3d3e 6491 return false;
79e53945 6492 }
79e53945 6493
c0c36b94 6494 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6495 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6496 if (old->release_fb)
6497 old->release_fb->funcs->destroy(old->release_fb);
0e8b3d3e 6498 return false;
79e53945 6499 }
7173188d 6500
79e53945 6501 /* let the connector get through one full cycle before testing */
9d0498a2 6502 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6503 return true;
79e53945
JB		 6504}
6505
d2434ab7 6506void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6507 struct intel_load_detect_pipe *old)
79e53945 6508{
d2434ab7
DV		 6509 struct intel_encoder *intel_encoder =
6510 intel_attached_encoder(connector);
4ef69c7a 6511 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6512
d2dff872
CW		 6513 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6514 connector->base.id, drm_get_connector_name(connector),
6515 encoder->base.id, drm_get_encoder_name(encoder));
6516
8261b191 6517 if (old->load_detect_temp) {
fc303101
DV		 6518 struct drm_crtc *crtc = encoder->crtc;
6519
6520 to_intel_connector(connector)->new_encoder = NULL;
6521 intel_encoder->new_crtc = NULL;
6522 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6523
6524 if (old->release_fb)
6525 old->release_fb->funcs->destroy(old->release_fb);
6526
0622a53c 6527 return;
79e53945
JB		 6528 }
6529
c751ce4f 6530 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6531 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6532 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6533}
6534
6535/* Returns the clock of the currently programmed mode of the given pipe. */
6536static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6537{
6538 struct drm_i915_private *dev_priv = dev->dev_private;
6539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6540 int pipe = intel_crtc->pipe;
548f245b 6541 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6542 u32 fp;
6543 intel_clock_t clock;
6544
6545 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6546 fp = I915_READ(FP0(pipe));
79e53945 6547 else
39adb7a5 6548 fp = I915_READ(FP1(pipe));
79e53945
JB		 6549
6550 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6551 if (IS_PINEVIEW(dev)) {
6552 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6553 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6554 } else {
6555 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6556 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6557 }
6558
a6c45cf0 6559 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6560 if (IS_PINEVIEW(dev))
6561 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6562 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6563 else
6564 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6565 DPLL_FPA01_P1_POST_DIV_SHIFT);
6566
6567 switch (dpll & DPLL_MODE_MASK) {
6568 case DPLLB_MODE_DAC_SERIAL:
6569 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6570 5 : 10;
6571 break;
6572 case DPLLB_MODE_LVDS:
6573 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6574 7 : 14;
6575 break;
6576 default:
28c97730 6577 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6578 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6579 return 0;
6580 }
6581
6582 /* XXX: Handle the 100Mhz refclk */
2177832f 6583 intel_clock(dev, 96000, &clock);
79e53945
JB		 6584 } else {
6585 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6586
6587 if (is_lvds) {
6588 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6589 DPLL_FPA01_P1_POST_DIV_SHIFT);
6590 clock.p2 = 14;
6591
6592 if ((dpll & PLL_REF_INPUT_MASK) ==
6593 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6594 /* XXX: might not be 66MHz */
2177832f 6595 intel_clock(dev, 66000, &clock);
79e53945 6596 } else
2177832f 6597 intel_clock(dev, 48000, &clock);
79e53945
JB		 6598 } else {
6599 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6600 clock.p1 = 2;
6601 else {
6602 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6603 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6604 }
6605 if (dpll & PLL_P2_DIVIDE_BY_4)
6606 clock.p2 = 4;
6607 else
6608 clock.p2 = 2;
6609
2177832f 6610 intel_clock(dev, 48000, &clock);
79e53945
JB		 6611 }
6612 }
6613
6614 /* XXX: It would be nice to validate the clocks, but we can't reuse
6615 * i830PllIsValid() because it relies on the xf86_config connector
6616 * configuration being accurate, which it isn't necessarily.
6617 */
6618
6619 return clock.dot;
6620}
6621
6622/** Returns the currently programmed mode of the given pipe. */
6623struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6624 struct drm_crtc *crtc)
6625{
548f245b 6626 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6628 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6629 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6630 int htot = I915_READ(HTOTAL(cpu_transcoder));
6631 int hsync = I915_READ(HSYNC(cpu_transcoder));
6632 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6633 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6634
6635 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6636 if (!mode)
6637 return NULL;
6638
6639 mode->clock = intel_crtc_clock_get(dev, crtc);
6640 mode->hdisplay = (htot & 0xffff) + 1;
6641 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6642 mode->hsync_start = (hsync & 0xffff) + 1;
6643 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6644 mode->vdisplay = (vtot & 0xffff) + 1;
6645 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6646 mode->vsync_start = (vsync & 0xffff) + 1;
6647 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6648
6649 drm_mode_set_name(mode);
79e53945
JB		 6650
6651 return mode;
6652}
6653
3dec0095 6654static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6655{
6656 struct drm_device *dev = crtc->dev;
6657 drm_i915_private_t *dev_priv = dev->dev_private;
6658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6659 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6660 int dpll_reg = DPLL(pipe);
6661 int dpll;
652c393a 6662
bad720ff 6663 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6664 return;
6665
6666 if (!dev_priv->lvds_downclock_avail)
6667 return;
6668
dbdc6479 6669 dpll = I915_READ(dpll_reg);
652c393a 6670 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6671 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6672
8ac5a6d5 6673 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6674
6675 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6676 I915_WRITE(dpll_reg, dpll);
9d0498a2 6677 intel_wait_for_vblank(dev, pipe);
dbdc6479 6678
652c393a
JB		 6679 dpll = I915_READ(dpll_reg);
6680 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6681 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6682 }
652c393a
JB		 6683}
6684
6685static void intel_decrease_pllclock(struct drm_crtc *crtc)
6686{
6687 struct drm_device *dev = crtc->dev;
6688 drm_i915_private_t *dev_priv = dev->dev_private;
6689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6690
bad720ff 6691 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6692 return;
6693
6694 if (!dev_priv->lvds_downclock_avail)
6695 return;
6696
6697 /*
6698 * Since this is called by a timer, we should never get here in
6699 * the manual case.
6700 */
6701 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6702 int pipe = intel_crtc->pipe;
6703 int dpll_reg = DPLL(pipe);
6704 int dpll;
f6e5b160 6705
44d98a61 6706 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6707
8ac5a6d5 6708 assert_panel_unlocked(dev_priv, pipe);
652c393a 6709
dc257cf1 6710 dpll = I915_READ(dpll_reg);
652c393a
JB		 6711 dpll |= DISPLAY_RATE_SELECT_FPA1;
6712 I915_WRITE(dpll_reg, dpll);
9d0498a2 6713 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6714 dpll = I915_READ(dpll_reg);
6715 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6716 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6717 }
6718
6719}
6720
f047e395
CW		 6721void intel_mark_busy(struct drm_device *dev)
6722{
f047e395
CW		 6723 i915_update_gfx_val(dev->dev_private);
6724}
6725
6726void intel_mark_idle(struct drm_device *dev)
652c393a 6727{
652c393a 6728 struct drm_crtc *crtc;
652c393a
JB		 6729
6730 if (!i915_powersave)
6731 return;
6732
652c393a 6733 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6734 if (!crtc->fb)
6735 continue;
6736
725a5b54 6737 intel_decrease_pllclock(crtc);
652c393a 6738 }
652c393a
JB		 6739}
6740
725a5b54 6741void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6742{
f047e395
CW		 6743 struct drm_device *dev = obj->base.dev;
6744 struct drm_crtc *crtc;
652c393a 6745
f047e395 6746 if (!i915_powersave)
acb87dfb
CW		 6747 return;
6748
652c393a
JB		 6749 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6750 if (!crtc->fb)
6751 continue;
6752
f047e395 6753 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6754 intel_increase_pllclock(crtc);
652c393a
JB		 6755 }
6756}
6757
79e53945
JB		 6758static void intel_crtc_destroy(struct drm_crtc *crtc)
6759{
6760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6761 struct drm_device *dev = crtc->dev;
6762 struct intel_unpin_work *work;
6763 unsigned long flags;
6764
6765 spin_lock_irqsave(&dev->event_lock, flags);
6766 work = intel_crtc->unpin_work;
6767 intel_crtc->unpin_work = NULL;
6768 spin_unlock_irqrestore(&dev->event_lock, flags);
6769
6770 if (work) {
6771 cancel_work_sync(&work->work);
6772 kfree(work);
6773 }
79e53945
JB		 6774
6775 drm_crtc_cleanup(crtc);
67e77c5a 6776
79e53945
JB		 6777 kfree(intel_crtc);
6778}
6779
6b95a207
KH		 6780static void intel_unpin_work_fn(struct work_struct *__work)
6781{
6782 struct intel_unpin_work *work =
6783 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6784 struct drm_device *dev = work->crtc->dev;
6b95a207 6785
b4a98e57 6786 mutex_lock(&dev->struct_mutex);
1690e1eb 6787 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6788 drm_gem_object_unreference(&work->pending_flip_obj->base);
6789 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6790
b4a98e57
CW		 6791 intel_update_fbc(dev);
6792 mutex_unlock(&dev->struct_mutex);
6793
6794 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6795 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6796
6b95a207
KH		 6797 kfree(work);
6798}
6799
1afe3e9d 6800static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6801 struct drm_crtc *crtc)
6b95a207
KH		 6802{
6803 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6805 struct intel_unpin_work *work;
05394f39 6806 struct drm_i915_gem_object *obj;
6b95a207
KH		 6807 unsigned long flags;
6808
6809 /* Ignore early vblank irqs */
6810 if (intel_crtc == NULL)
6811 return;
6812
6813 spin_lock_irqsave(&dev->event_lock, flags);
6814 work = intel_crtc->unpin_work;
e7d841ca
CW		 6815
6816 /* Ensure we don't miss a work->pending update ... */
6817 smp_rmb();
6818
6819 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6820 spin_unlock_irqrestore(&dev->event_lock, flags);
6821 return;
6822 }
6823
e7d841ca
CW		 6824 /* and that the unpin work is consistent wrt ->pending. */
6825 smp_rmb();
6826
6b95a207 6827 intel_crtc->unpin_work = NULL;
6b95a207 6828
45a066eb
RC		 6829 if (work->event)
6830 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6831
0af7e4df
MK		 6832 drm_vblank_put(dev, intel_crtc->pipe);
6833
6b95a207
KH		 6834 spin_unlock_irqrestore(&dev->event_lock, flags);
6835
05394f39 6836 obj = work->old_fb_obj;
d9e86c0e 6837
2c10d571 6838 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6839
6840 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6841
6842 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6843}
6844
1afe3e9d
JB		 6845void intel_finish_page_flip(struct drm_device *dev, int pipe)
6846{
6847 drm_i915_private_t *dev_priv = dev->dev_private;
6848 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6849
49b14a5c 6850 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6851}
6852
6853void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6854{
6855 drm_i915_private_t *dev_priv = dev->dev_private;
6856 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6857
49b14a5c 6858 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6859}
6860
6b95a207
KH		 6861void intel_prepare_page_flip(struct drm_device *dev, int plane)
6862{
6863 drm_i915_private_t *dev_priv = dev->dev_private;
6864 struct intel_crtc *intel_crtc =
6865 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6866 unsigned long flags;
6867
e7d841ca
CW		 6868 /* NB: An MMIO update of the plane base pointer will also
6869 * generate a page-flip completion irq, i.e. every modeset
6870 * is also accompanied by a spurious intel_prepare_page_flip().
6871 */
6b95a207 6872 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 6873 if (intel_crtc->unpin_work)
6874 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 6875 spin_unlock_irqrestore(&dev->event_lock, flags);
6876}
6877
e7d841ca
CW		 6878inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6879{
6880 /* Ensure that the work item is consistent when activating it ... */
6881 smp_wmb();
6882 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6883 /* and that it is marked active as soon as the irq could fire. */
6884 smp_wmb();
6885}
6886
8c9f3aaf
JB		 6887static int intel_gen2_queue_flip(struct drm_device *dev,
6888 struct drm_crtc *crtc,
6889 struct drm_framebuffer *fb,
6890 struct drm_i915_gem_object *obj)
6891{
6892 struct drm_i915_private *dev_priv = dev->dev_private;
6893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6894 u32 flip_mask;
6d90c952 6895 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6896 int ret;
6897
6d90c952 6898 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6899 if (ret)
83d4092b 6900 goto err;
8c9f3aaf 6901
6d90c952 6902 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6903 if (ret)
83d4092b 6904 goto err_unpin;
8c9f3aaf
JB		 6905
6906 /* Can't queue multiple flips, so wait for the previous
6907 * one to finish before executing the next.
6908 */
6909 if (intel_crtc->plane)
6910 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6911 else
6912 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6913 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6914 intel_ring_emit(ring, MI_NOOP);
6915 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6916 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6917 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6918 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 6919 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 6920
6921 intel_mark_page_flip_active(intel_crtc);
6d90c952 6922 intel_ring_advance(ring);
83d4092b
CW		 6923 return 0;
6924
6925err_unpin:
6926 intel_unpin_fb_obj(obj);
6927err:
8c9f3aaf
JB		 6928 return ret;
6929}
6930
6931static int intel_gen3_queue_flip(struct drm_device *dev,
6932 struct drm_crtc *crtc,
6933 struct drm_framebuffer *fb,
6934 struct drm_i915_gem_object *obj)
6935{
6936 struct drm_i915_private *dev_priv = dev->dev_private;
6937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6938 u32 flip_mask;
6d90c952 6939 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6940 int ret;
6941
6d90c952 6942 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6943 if (ret)
83d4092b 6944 goto err;
8c9f3aaf 6945
6d90c952 6946 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6947 if (ret)
83d4092b 6948 goto err_unpin;
8c9f3aaf
JB		 6949
6950 if (intel_crtc->plane)
6951 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6952 else
6953 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6954 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6955 intel_ring_emit(ring, MI_NOOP);
6956 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6957 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6958 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6959 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6960 intel_ring_emit(ring, MI_NOOP);
6961
e7d841ca 6962 intel_mark_page_flip_active(intel_crtc);
6d90c952 6963 intel_ring_advance(ring);
83d4092b
CW		 6964 return 0;
6965
6966err_unpin:
6967 intel_unpin_fb_obj(obj);
6968err:
8c9f3aaf
JB		 6969 return ret;
6970}
6971
6972static int intel_gen4_queue_flip(struct drm_device *dev,
6973 struct drm_crtc *crtc,
6974 struct drm_framebuffer *fb,
6975 struct drm_i915_gem_object *obj)
6976{
6977 struct drm_i915_private *dev_priv = dev->dev_private;
6978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6979 uint32_t pf, pipesrc;
6d90c952 6980 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6981 int ret;
6982
6d90c952 6983 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6984 if (ret)
83d4092b 6985 goto err;
8c9f3aaf 6986
6d90c952 6987 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6988 if (ret)
83d4092b 6989 goto err_unpin;
8c9f3aaf
JB		 6990
6991 /* i965+ uses the linear or tiled offsets from the
6992 * Display Registers (which do not change across a page-flip)
6993 * so we need only reprogram the base address.
6994 */
6d90c952
DV		 6995 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6996 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6997 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6998 intel_ring_emit(ring,
6999 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7000 obj->tiling_mode);
8c9f3aaf
JB		 7001
7002 /* XXX Enabling the panel-fitter across page-flip is so far
7003 * untested on non-native modes, so ignore it for now.
7004 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7005 */
7006 pf = 0;
7007 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7008 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7009
7010 intel_mark_page_flip_active(intel_crtc);
6d90c952 7011 intel_ring_advance(ring);
83d4092b
CW		 7012 return 0;
7013
7014err_unpin:
7015 intel_unpin_fb_obj(obj);
7016err:
8c9f3aaf
JB		 7017 return ret;
7018}
7019
7020static int intel_gen6_queue_flip(struct drm_device *dev,
7021 struct drm_crtc *crtc,
7022 struct drm_framebuffer *fb,
7023 struct drm_i915_gem_object *obj)
7024{
7025 struct drm_i915_private *dev_priv = dev->dev_private;
7026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7027 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7028 uint32_t pf, pipesrc;
7029 int ret;
7030
6d90c952 7031 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7032 if (ret)
83d4092b 7033 goto err;
8c9f3aaf 7034
6d90c952 7035 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7036 if (ret)
83d4092b 7037 goto err_unpin;
8c9f3aaf 7038
6d90c952
DV		 7039 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7040 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7041 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7042 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7043
dc257cf1
DV		 7044 /* Contrary to the suggestions in the documentation,
7045 * "Enable Panel Fitter" does not seem to be required when page
7046 * flipping with a non-native mode, and worse causes a normal
7047 * modeset to fail.
7048 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7049 */
7050 pf = 0;
8c9f3aaf 7051 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7052 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7053
7054 intel_mark_page_flip_active(intel_crtc);
6d90c952 7055 intel_ring_advance(ring);
83d4092b
CW		 7056 return 0;
7057
7058err_unpin:
7059 intel_unpin_fb_obj(obj);
7060err:
8c9f3aaf
JB		 7061 return ret;
7062}
7063
7c9017e5
JB		 7064/*
7065 * On gen7 we currently use the blit ring because (in early silicon at least)
7066 * the render ring doesn't give us interrpts for page flip completion, which
7067 * means clients will hang after the first flip is queued. Fortunately the
7068 * blit ring generates interrupts properly, so use it instead.
7069 */
7070static int intel_gen7_queue_flip(struct drm_device *dev,
7071 struct drm_crtc *crtc,
7072 struct drm_framebuffer *fb,
7073 struct drm_i915_gem_object *obj)
7074{
7075 struct drm_i915_private *dev_priv = dev->dev_private;
7076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7077 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7078 uint32_t plane_bit = 0;
7c9017e5
JB		 7079 int ret;
7080
7081 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7082 if (ret)
83d4092b 7083 goto err;
7c9017e5 7084
cb05d8de
DV		 7085 switch(intel_crtc->plane) {
7086 case PLANE_A:
7087 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7088 break;
7089 case PLANE_B:
7090 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7091 break;
7092 case PLANE_C:
7093 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7094 break;
7095 default:
7096 WARN_ONCE(1, "unknown plane in flip command\n");
7097 ret = -ENODEV;
ab3951eb 7098 goto err_unpin;
cb05d8de
DV		 7099 }
7100
7c9017e5
JB		 7101 ret = intel_ring_begin(ring, 4);
7102 if (ret)
83d4092b 7103 goto err_unpin;
7c9017e5 7104
cb05d8de 7105 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7106 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7107 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7108 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7109
7110 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7111 intel_ring_advance(ring);
83d4092b
CW		 7112 return 0;
7113
7114err_unpin:
7115 intel_unpin_fb_obj(obj);
7116err:
7c9017e5
JB		 7117 return ret;
7118}
7119
8c9f3aaf
JB		 7120static int intel_default_queue_flip(struct drm_device *dev,
7121 struct drm_crtc *crtc,
7122 struct drm_framebuffer *fb,
7123 struct drm_i915_gem_object *obj)
7124{
7125 return -ENODEV;
7126}
7127
6b95a207
KH		 7128static int intel_crtc_page_flip(struct drm_crtc *crtc,
7129 struct drm_framebuffer *fb,
7130 struct drm_pending_vblank_event *event)
7131{
7132 struct drm_device *dev = crtc->dev;
7133 struct drm_i915_private *dev_priv = dev->dev_private;
7134 struct intel_framebuffer *intel_fb;
05394f39 7135 struct drm_i915_gem_object *obj;
6b95a207
KH		 7136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7137 struct intel_unpin_work *work;
8c9f3aaf 7138 unsigned long flags;
52e68630 7139 int ret;
6b95a207 7140
e6a595d2
VS		 7141 /* Can't change pixel format via MI display flips. */
7142 if (fb->pixel_format != crtc->fb->pixel_format)
7143 return -EINVAL;
7144
7145 /*
7146 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7147 * Note that pitch changes could also affect these register.
7148 */
7149 if (INTEL_INFO(dev)->gen > 3 &&
7150 (fb->offsets[0] != crtc->fb->offsets[0] ||
7151 fb->pitches[0] != crtc->fb->pitches[0]))
7152 return -EINVAL;
7153
6b95a207
KH		 7154 work = kzalloc(sizeof *work, GFP_KERNEL);
7155 if (work == NULL)
7156 return -ENOMEM;
7157
6b95a207 7158 work->event = event;
b4a98e57 7159 work->crtc = crtc;
6b95a207 7160 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7161 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7162 INIT_WORK(&work->work, intel_unpin_work_fn);
7163
7317c75e
JB		 7164 ret = drm_vblank_get(dev, intel_crtc->pipe);
7165 if (ret)
7166 goto free_work;
7167
6b95a207
KH		 7168 /* We borrow the event spin lock for protecting unpin_work */
7169 spin_lock_irqsave(&dev->event_lock, flags);
7170 if (intel_crtc->unpin_work) {
7171 spin_unlock_irqrestore(&dev->event_lock, flags);
7172 kfree(work);
7317c75e 7173 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7174
7175 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7176 return -EBUSY;
7177 }
7178 intel_crtc->unpin_work = work;
7179 spin_unlock_irqrestore(&dev->event_lock, flags);
7180
7181 intel_fb = to_intel_framebuffer(fb);
7182 obj = intel_fb->obj;
7183
b4a98e57
CW		 7184 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7185 flush_workqueue(dev_priv->wq);
7186
79158103
CW		 7187 ret = i915_mutex_lock_interruptible(dev);
7188 if (ret)
7189 goto cleanup;
6b95a207 7190
75dfca80 7191 /* Reference the objects for the scheduled work. */
05394f39
CW		 7192 drm_gem_object_reference(&work->old_fb_obj->base);
7193 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7194
7195 crtc->fb = fb;
96b099fd 7196
e1f99ce6 7197 work->pending_flip_obj = obj;
e1f99ce6 7198
4e5359cd
SF		 7199 work->enable_stall_check = true;
7200
b4a98e57 7201 atomic_inc(&intel_crtc->unpin_work_count);
e1f99ce6 7202
8c9f3aaf
JB		 7203 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7204 if (ret)
7205 goto cleanup_pending;
6b95a207 7206
7782de3b 7207 intel_disable_fbc(dev);
f047e395 7208 intel_mark_fb_busy(obj);
6b95a207
KH		 7209 mutex_unlock(&dev->struct_mutex);
7210
e5510fac
JB		 7211 trace_i915_flip_request(intel_crtc->plane, obj);
7212
6b95a207 7213 return 0;
96b099fd 7214
8c9f3aaf 7215cleanup_pending:
b4a98e57 7216 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7217 drm_gem_object_unreference(&work->old_fb_obj->base);
7218 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7219 mutex_unlock(&dev->struct_mutex);
7220
79158103 7221cleanup:
96b099fd
CW		 7222 spin_lock_irqsave(&dev->event_lock, flags);
7223 intel_crtc->unpin_work = NULL;
7224 spin_unlock_irqrestore(&dev->event_lock, flags);
7225
7317c75e
JB		 7226 drm_vblank_put(dev, intel_crtc->pipe);
7227free_work:
96b099fd
CW		 7228 kfree(work);
7229
7230 return ret;
6b95a207
KH		 7231}
7232
f6e5b160 7233static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7234 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7235 .load_lut = intel_crtc_load_lut,
976f8a20 7236 .disable = intel_crtc_noop,
f6e5b160
CW		 7237};
7238
6ed0f796 7239bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7240{
6ed0f796
DV		 7241 struct intel_encoder *other_encoder;
7242 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7243
6ed0f796
DV		 7244 if (WARN_ON(!crtc))
7245 return false;
7246
7247 list_for_each_entry(other_encoder,
7248 &crtc->dev->mode_config.encoder_list,
7249 base.head) {
7250
7251 if (&other_encoder->new_crtc->base != crtc ||
7252 encoder == other_encoder)
7253 continue;
7254 else
7255 return true;
f47166d2
CW		 7256 }
7257
6ed0f796
DV		 7258 return false;
7259}
47f1c6c9 7260
50f56119
DV		 7261static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7262 struct drm_crtc *crtc)
7263{
7264 struct drm_device *dev;
7265 struct drm_crtc *tmp;
7266 int crtc_mask = 1;
47f1c6c9 7267
50f56119 7268 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7269
50f56119 7270 dev = crtc->dev;
47f1c6c9 7271
50f56119
DV		 7272 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7273 if (tmp == crtc)
7274 break;
7275 crtc_mask <<= 1;
7276 }
47f1c6c9 7277
50f56119
DV		 7278 if (encoder->possible_crtcs & crtc_mask)
7279 return true;
7280 return false;
47f1c6c9 7281}
79e53945 7282
9a935856
DV		 7283/**
7284 * intel_modeset_update_staged_output_state
7285 *
7286 * Updates the staged output configuration state, e.g. after we've read out the
7287 * current hw state.
7288 */
7289static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7290{
9a935856
DV		 7291 struct intel_encoder *encoder;
7292 struct intel_connector *connector;
f6e5b160 7293
9a935856
DV		 7294 list_for_each_entry(connector, &dev->mode_config.connector_list,
7295 base.head) {
7296 connector->new_encoder =
7297 to_intel_encoder(connector->base.encoder);
7298 }
f6e5b160 7299
9a935856
DV		 7300 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7301 base.head) {
7302 encoder->new_crtc =
7303 to_intel_crtc(encoder->base.crtc);
7304 }
f6e5b160
CW		 7305}
7306
9a935856
DV		 7307/**
7308 * intel_modeset_commit_output_state
7309 *
7310 * This function copies the stage display pipe configuration to the real one.
7311 */
7312static void intel_modeset_commit_output_state(struct drm_device *dev)
7313{
7314 struct intel_encoder *encoder;
7315 struct intel_connector *connector;
f6e5b160 7316
9a935856
DV		 7317 list_for_each_entry(connector, &dev->mode_config.connector_list,
7318 base.head) {
7319 connector->base.encoder = &connector->new_encoder->base;
7320 }
f6e5b160 7321
9a935856
DV		 7322 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7323 base.head) {
7324 encoder->base.crtc = &encoder->new_crtc->base;
7325 }
7326}
7327
7758a113
DV		 7328static struct drm_display_mode *
7329intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7330 struct drm_display_mode *mode)
ee7b9f93 7331{
7758a113
DV		 7332 struct drm_device *dev = crtc->dev;
7333 struct drm_display_mode *adjusted_mode;
7334 struct drm_encoder_helper_funcs *encoder_funcs;
7335 struct intel_encoder *encoder;
ee7b9f93 7336
7758a113
DV		 7337 adjusted_mode = drm_mode_duplicate(dev, mode);
7338 if (!adjusted_mode)
7339 return ERR_PTR(-ENOMEM);
7340
7341 /* Pass our mode to the connectors and the CRTC to give them a chance to
7342 * adjust it according to limitations or connector properties, and also
7343 * a chance to reject the mode entirely.
47f1c6c9 7344 */
7758a113
DV		 7345 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7346 base.head) {
47f1c6c9 7347
7758a113
DV		 7348 if (&encoder->new_crtc->base != crtc)
7349 continue;
7350 encoder_funcs = encoder->base.helper_private;
7351 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7352 adjusted_mode))) {
7353 DRM_DEBUG_KMS("Encoder fixup failed\n");
7354 goto fail;
7355 }
ee7b9f93 7356 }
47f1c6c9 7357
7758a113
DV		 7358 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7359 DRM_DEBUG_KMS("CRTC fixup failed\n");
7360 goto fail;
ee7b9f93 7361 }
7758a113 7362 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7363
7758a113
DV		 7364 return adjusted_mode;
7365fail:
7366 drm_mode_destroy(dev, adjusted_mode);
7367 return ERR_PTR(-EINVAL);
ee7b9f93 7368}
47f1c6c9 7369
e2e1ed41
DV		 7370/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7371 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7372static void
7373intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7374 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7375{
7376 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7377 struct drm_device *dev = crtc->dev;
7378 struct intel_encoder *encoder;
7379 struct intel_connector *connector;
7380 struct drm_crtc *tmp_crtc;
79e53945 7381
e2e1ed41 7382 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7383
e2e1ed41
DV		 7384 /* Check which crtcs have changed outputs connected to them, these need
7385 * to be part of the prepare_pipes mask. We don't (yet) support global
7386 * modeset across multiple crtcs, so modeset_pipes will only have one
7387 * bit set at most. */
7388 list_for_each_entry(connector, &dev->mode_config.connector_list,
7389 base.head) {
7390 if (connector->base.encoder == &connector->new_encoder->base)
7391 continue;
79e53945 7392
e2e1ed41
DV		 7393 if (connector->base.encoder) {
7394 tmp_crtc = connector->base.encoder->crtc;
7395
7396 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7397 }
7398
7399 if (connector->new_encoder)
7400 *prepare_pipes |=
7401 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7402 }
7403
e2e1ed41
DV		 7404 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7405 base.head) {
7406 if (encoder->base.crtc == &encoder->new_crtc->base)
7407 continue;
7408
7409 if (encoder->base.crtc) {
7410 tmp_crtc = encoder->base.crtc;
7411
7412 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7413 }
7414
7415 if (encoder->new_crtc)
7416 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7417 }
7418
e2e1ed41
DV		 7419 /* Check for any pipes that will be fully disabled ... */
7420 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7421 base.head) {
7422 bool used = false;
22fd0fab 7423
e2e1ed41
DV		 7424 /* Don't try to disable disabled crtcs. */
7425 if (!intel_crtc->base.enabled)
7426 continue;
7e7d76c3 7427
e2e1ed41
DV		 7428 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7429 base.head) {
7430 if (encoder->new_crtc == intel_crtc)
7431 used = true;
7432 }
7433
7434 if (!used)
7435 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7436 }
7437
e2e1ed41
DV		 7438
7439 /* set_mode is also used to update properties on life display pipes. */
7440 intel_crtc = to_intel_crtc(crtc);
7441 if (crtc->enabled)
7442 *prepare_pipes |= 1 << intel_crtc->pipe;
7443
7444 /* We only support modeset on one single crtc, hence we need to do that
7445 * only for the passed in crtc iff we change anything else than just
7446 * disable crtcs.
7447 *
7448 * This is actually not true, to be fully compatible with the old crtc
7449 * helper we automatically disable _any_ output (i.e. doesn't need to be
7450 * connected to the crtc we're modesetting on) if it's disconnected.
7451 * Which is a rather nutty api (since changed the output configuration
7452 * without userspace's explicit request can lead to confusion), but
7453 * alas. Hence we currently need to modeset on all pipes we prepare. */
7454 if (*prepare_pipes)
7455 *modeset_pipes = *prepare_pipes;
7456
7457 /* ... and mask these out. */
7458 *modeset_pipes &= ~(*disable_pipes);
7459 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7460}
79e53945 7461
ea9d758d 7462static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7463{
ea9d758d 7464 struct drm_encoder *encoder;
f6e5b160 7465 struct drm_device *dev = crtc->dev;
f6e5b160 7466
ea9d758d
DV		 7467 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7468 if (encoder->crtc == crtc)
7469 return true;
7470
7471 return false;
7472}
7473
7474static void
7475intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7476{
7477 struct intel_encoder *intel_encoder;
7478 struct intel_crtc *intel_crtc;
7479 struct drm_connector *connector;
7480
7481 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7482 base.head) {
7483 if (!intel_encoder->base.crtc)
7484 continue;
7485
7486 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7487
7488 if (prepare_pipes & (1 << intel_crtc->pipe))
7489 intel_encoder->connectors_active = false;
7490 }
7491
7492 intel_modeset_commit_output_state(dev);
7493
7494 /* Update computed state. */
7495 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7496 base.head) {
7497 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7498 }
7499
7500 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7501 if (!connector->encoder || !connector->encoder->crtc)
7502 continue;
7503
7504 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7505
7506 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7507 struct drm_property *dpms_property =
7508 dev->mode_config.dpms_property;
7509
ea9d758d 7510 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7511 drm_object_property_set_value(&connector->base,
68d34720
DV		 7512 dpms_property,
7513 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7514
7515 intel_encoder = to_intel_encoder(connector->encoder);
7516 intel_encoder->connectors_active = true;
7517 }
7518 }
7519
7520}
7521
25c5b266
DV		 7522#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7523 list_for_each_entry((intel_crtc), \
7524 &(dev)->mode_config.crtc_list, \
7525 base.head) \
7526 if (mask & (1 <<(intel_crtc)->pipe)) \
7527
b980514c 7528void
8af6cf88
DV		 7529intel_modeset_check_state(struct drm_device *dev)
7530{
7531 struct intel_crtc *crtc;
7532 struct intel_encoder *encoder;
7533 struct intel_connector *connector;
7534
7535 list_for_each_entry(connector, &dev->mode_config.connector_list,
7536 base.head) {
7537 /* This also checks the encoder/connector hw state with the
7538 * ->get_hw_state callbacks. */
7539 intel_connector_check_state(connector);
7540
7541 WARN(&connector->new_encoder->base != connector->base.encoder,
7542 "connector's staged encoder doesn't match current encoder\n");
7543 }
7544
7545 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7546 base.head) {
7547 bool enabled = false;
7548 bool active = false;
7549 enum pipe pipe, tracked_pipe;
7550
7551 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7552 encoder->base.base.id,
7553 drm_get_encoder_name(&encoder->base));
7554
7555 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7556 "encoder's stage crtc doesn't match current crtc\n");
7557 WARN(encoder->connectors_active && !encoder->base.crtc,
7558 "encoder's active_connectors set, but no crtc\n");
7559
7560 list_for_each_entry(connector, &dev->mode_config.connector_list,
7561 base.head) {
7562 if (connector->base.encoder != &encoder->base)
7563 continue;
7564 enabled = true;
7565 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7566 active = true;
7567 }
7568 WARN(!!encoder->base.crtc != enabled,
7569 "encoder's enabled state mismatch "
7570 "(expected %i, found %i)\n",
7571 !!encoder->base.crtc, enabled);
7572 WARN(active && !encoder->base.crtc,
7573 "active encoder with no crtc\n");
7574
7575 WARN(encoder->connectors_active != active,
7576 "encoder's computed active state doesn't match tracked active state "
7577 "(expected %i, found %i)\n", active, encoder->connectors_active);
7578
7579 active = encoder->get_hw_state(encoder, &pipe);
7580 WARN(active != encoder->connectors_active,
7581 "encoder's hw state doesn't match sw tracking "
7582 "(expected %i, found %i)\n",
7583 encoder->connectors_active, active);
7584
7585 if (!encoder->base.crtc)
7586 continue;
7587
7588 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7589 WARN(active && pipe != tracked_pipe,
7590 "active encoder's pipe doesn't match"
7591 "(expected %i, found %i)\n",
7592 tracked_pipe, pipe);
7593
7594 }
7595
7596 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7597 base.head) {
7598 bool enabled = false;
7599 bool active = false;
7600
7601 DRM_DEBUG_KMS("[CRTC:%d]\n",
7602 crtc->base.base.id);
7603
7604 WARN(crtc->active && !crtc->base.enabled,
7605 "active crtc, but not enabled in sw tracking\n");
7606
7607 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7608 base.head) {
7609 if (encoder->base.crtc != &crtc->base)
7610 continue;
7611 enabled = true;
7612 if (encoder->connectors_active)
7613 active = true;
7614 }
7615 WARN(active != crtc->active,
7616 "crtc's computed active state doesn't match tracked active state "
7617 "(expected %i, found %i)\n", active, crtc->active);
7618 WARN(enabled != crtc->base.enabled,
7619 "crtc's computed enabled state doesn't match tracked enabled state "
7620 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7621
7622 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7623 }
7624}
7625
c0c36b94
CW		 7626int intel_set_mode(struct drm_crtc *crtc,
7627 struct drm_display_mode *mode,
7628 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7629{
7630 struct drm_device *dev = crtc->dev;
dbf2b54e 7631 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7632 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7633 struct intel_crtc *intel_crtc;
7634 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7635 int ret = 0;
a6778b3c 7636
3ac18232 7637 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7638 if (!saved_mode)
7639 return -ENOMEM;
3ac18232 7640 saved_hwmode = saved_mode + 1;
a6778b3c 7641
e2e1ed41 7642 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7643 &prepare_pipes, &disable_pipes);
7644
7645 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7646 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7647
976f8a20
DV		 7648 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7649 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7650
3ac18232
TG		 7651 *saved_hwmode = crtc->hwmode;
7652 *saved_mode = crtc->mode;
a6778b3c 7653
25c5b266
DV		 7654 /* Hack: Because we don't (yet) support global modeset on multiple
7655 * crtcs, we don't keep track of the new mode for more than one crtc.
7656 * Hence simply check whether any bit is set in modeset_pipes in all the
7657 * pieces of code that are not yet converted to deal with mutliple crtcs
7658 * changing their mode at the same time. */
7659 adjusted_mode = NULL;
7660 if (modeset_pipes) {
7661 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7662 if (IS_ERR(adjusted_mode)) {
c0c36b94 7663 ret = PTR_ERR(adjusted_mode);
3ac18232 7664 goto out;
25c5b266 7665 }
25c5b266 7666 }
a6778b3c 7667
ea9d758d
DV		 7668 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7669 if (intel_crtc->base.enabled)
7670 dev_priv->display.crtc_disable(&intel_crtc->base);
7671 }
a6778b3c 7672
6c4c86f5
DV		 7673 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7674 * to set it here already despite that we pass it down the callchain.
f6e5b160 7675 */
6c4c86f5 7676 if (modeset_pipes)
25c5b266 7677 crtc->mode = *mode;
7758a113 7678
ea9d758d
DV		 7679 /* Only after disabling all output pipelines that will be changed can we
7680 * update the the output configuration. */
7681 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7682
47fab737
DV		 7683 if (dev_priv->display.modeset_global_resources)
7684 dev_priv->display.modeset_global_resources(dev);
7685
a6778b3c
DV		 7686 /* Set up the DPLL and any encoders state that needs to adjust or depend
7687 * on the DPLL.
f6e5b160 7688 */
25c5b266 7689 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94
CW		 7690 ret = intel_crtc_mode_set(&intel_crtc->base,
7691 mode, adjusted_mode,
7692 x, y, fb);
7693 if (ret)
7694 goto done;
a6778b3c
DV		 7695 }
7696
7697 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7698 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7699 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7700
25c5b266
DV		 7701 if (modeset_pipes) {
7702 /* Store real post-adjustment hardware mode. */
7703 crtc->hwmode = *adjusted_mode;
a6778b3c 7704
25c5b266
DV		 7705 /* Calculate and store various constants which
7706 * are later needed by vblank and swap-completion
7707 * timestamping. They are derived from true hwmode.
7708 */
7709 drm_calc_timestamping_constants(crtc);
7710 }
a6778b3c
DV		 7711
7712 /* FIXME: add subpixel order */
7713done:
7714 drm_mode_destroy(dev, adjusted_mode);
c0c36b94 7715 if (ret && crtc->enabled) {
3ac18232
TG		 7716 crtc->hwmode = *saved_hwmode;
7717 crtc->mode = *saved_mode;
8af6cf88
DV		 7718 } else {
7719 intel_modeset_check_state(dev);
a6778b3c
DV		 7720 }
7721
3ac18232
TG		 7722out:
7723 kfree(saved_mode);
a6778b3c 7724 return ret;
f6e5b160
CW		 7725}
7726
c0c36b94
CW		 7727void intel_crtc_restore_mode(struct drm_crtc *crtc)
7728{
7729 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7730}
7731
25c5b266
DV		 7732#undef for_each_intel_crtc_masked
7733
d9e55608
DV		 7734static void intel_set_config_free(struct intel_set_config *config)
7735{
7736 if (!config)
7737 return;
7738
1aa4b628
DV		 7739 kfree(config->save_connector_encoders);
7740 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7741 kfree(config);
7742}
7743
85f9eb71
DV		 7744static int intel_set_config_save_state(struct drm_device *dev,
7745 struct intel_set_config *config)
7746{
85f9eb71
DV		 7747 struct drm_encoder *encoder;
7748 struct drm_connector *connector;
7749 int count;
7750
1aa4b628
DV		 7751 config->save_encoder_crtcs =
7752 kcalloc(dev->mode_config.num_encoder,
7753 sizeof(struct drm_crtc *), GFP_KERNEL);
7754 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7755 return -ENOMEM;
7756
1aa4b628
DV		 7757 config->save_connector_encoders =
7758 kcalloc(dev->mode_config.num_connector,
7759 sizeof(struct drm_encoder *), GFP_KERNEL);
7760 if (!config->save_connector_encoders)
85f9eb71
DV		 7761 return -ENOMEM;
7762
7763 /* Copy data. Note that driver private data is not affected.
7764 * Should anything bad happen only the expected state is
7765 * restored, not the drivers personal bookkeeping.
7766 */
85f9eb71
DV		 7767 count = 0;
7768 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7769 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7770 }
7771
7772 count = 0;
7773 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7774 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7775 }
7776
7777 return 0;
7778}
7779
7780static void intel_set_config_restore_state(struct drm_device *dev,
7781 struct intel_set_config *config)
7782{
9a935856
DV		 7783 struct intel_encoder *encoder;
7784 struct intel_connector *connector;
85f9eb71
DV		 7785 int count;
7786
85f9eb71 7787 count = 0;
9a935856
DV		 7788 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7789 encoder->new_crtc =
7790 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7791 }
7792
7793 count = 0;
9a935856
DV		 7794 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7795 connector->new_encoder =
7796 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7797 }
7798}
7799
5e2b584e
DV		 7800static void
7801intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7802 struct intel_set_config *config)
7803{
7804
7805 /* We should be able to check here if the fb has the same properties
7806 * and then just flip_or_move it */
7807 if (set->crtc->fb != set->fb) {
7808 /* If we have no fb then treat it as a full mode set */
7809 if (set->crtc->fb == NULL) {
7810 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7811 config->mode_changed = true;
7812 } else if (set->fb == NULL) {
7813 config->mode_changed = true;
7814 } else if (set->fb->depth != set->crtc->fb->depth) {
7815 config->mode_changed = true;
7816 } else if (set->fb->bits_per_pixel !=
7817 set->crtc->fb->bits_per_pixel) {
7818 config->mode_changed = true;
7819 } else
7820 config->fb_changed = true;
7821 }
7822
835c5873 7823 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7824 config->fb_changed = true;
7825
7826 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7827 DRM_DEBUG_KMS("modes are different, full mode set\n");
7828 drm_mode_debug_printmodeline(&set->crtc->mode);
7829 drm_mode_debug_printmodeline(set->mode);
7830 config->mode_changed = true;
7831 }
7832}
7833
2e431051 7834static int
9a935856
DV		 7835intel_modeset_stage_output_state(struct drm_device *dev,
7836 struct drm_mode_set *set,
7837 struct intel_set_config *config)
50f56119 7838{
85f9eb71 7839 struct drm_crtc *new_crtc;
9a935856
DV		 7840 struct intel_connector *connector;
7841 struct intel_encoder *encoder;
2e431051 7842 int count, ro;
50f56119 7843
9a935856
DV		 7844 /* The upper layers ensure that we either disabl a crtc or have a list
7845 * of connectors. For paranoia, double-check this. */
7846 WARN_ON(!set->fb && (set->num_connectors != 0));
7847 WARN_ON(set->fb && (set->num_connectors == 0));
7848
50f56119 7849 count = 0;
9a935856
DV		 7850 list_for_each_entry(connector, &dev->mode_config.connector_list,
7851 base.head) {
7852 /* Otherwise traverse passed in connector list and get encoders
7853 * for them. */
50f56119 7854 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7855 if (set->connectors[ro] == &connector->base) {
7856 connector->new_encoder = connector->encoder;
50f56119
DV		 7857 break;
7858 }
7859 }
7860
9a935856
DV		 7861 /* If we disable the crtc, disable all its connectors. Also, if
7862 * the connector is on the changing crtc but not on the new
7863 * connector list, disable it. */
7864 if ((!set->fb || ro == set->num_connectors) &&
7865 connector->base.encoder &&
7866 connector->base.encoder->crtc == set->crtc) {
7867 connector->new_encoder = NULL;
7868
7869 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7870 connector->base.base.id,
7871 drm_get_connector_name(&connector->base));
7872 }
7873
7874
7875 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7876 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7877 config->mode_changed = true;
50f56119
DV		 7878 }
7879 }
9a935856 7880 /* connector->new_encoder is now updated for all connectors. */
50f56119 7881
9a935856 7882 /* Update crtc of enabled connectors. */
50f56119 7883 count = 0;
9a935856
DV		 7884 list_for_each_entry(connector, &dev->mode_config.connector_list,
7885 base.head) {
7886 if (!connector->new_encoder)
50f56119
DV		 7887 continue;
7888
9a935856 7889 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7890
7891 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7892 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7893 new_crtc = set->crtc;
7894 }
7895
7896 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7897 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7898 new_crtc)) {
5e2b584e 7899 return -EINVAL;
50f56119 7900 }
9a935856
DV		 7901 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7902
7903 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7904 connector->base.base.id,
7905 drm_get_connector_name(&connector->base),
7906 new_crtc->base.id);
7907 }
7908
7909 /* Check for any encoders that needs to be disabled. */
7910 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7911 base.head) {
7912 list_for_each_entry(connector,
7913 &dev->mode_config.connector_list,
7914 base.head) {
7915 if (connector->new_encoder == encoder) {
7916 WARN_ON(!connector->new_encoder->new_crtc);
7917
7918 goto next_encoder;
7919 }
7920 }
7921 encoder->new_crtc = NULL;
7922next_encoder:
7923 /* Only now check for crtc changes so we don't miss encoders
7924 * that will be disabled. */
7925 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7926 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7927 config->mode_changed = true;
50f56119
DV		 7928 }
7929 }
9a935856 7930 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7931
2e431051
DV		 7932 return 0;
7933}
7934
7935static int intel_crtc_set_config(struct drm_mode_set *set)
7936{
7937 struct drm_device *dev;
2e431051
DV		 7938 struct drm_mode_set save_set;
7939 struct intel_set_config *config;
7940 int ret;
2e431051 7941
8d3e375e
DV		 7942 BUG_ON(!set);
7943 BUG_ON(!set->crtc);
7944 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7945
7946 if (!set->mode)
7947 set->fb = NULL;
7948
431e50f7
DV		 7949 /* The fb helper likes to play gross jokes with ->mode_set_config.
7950 * Unfortunately the crtc helper doesn't do much at all for this case,
7951 * so we have to cope with this madness until the fb helper is fixed up. */
7952 if (set->fb && set->num_connectors == 0)
7953 return 0;
7954
2e431051
DV		 7955 if (set->fb) {
7956 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7957 set->crtc->base.id, set->fb->base.id,
7958 (int)set->num_connectors, set->x, set->y);
7959 } else {
7960 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7961 }
7962
7963 dev = set->crtc->dev;
7964
7965 ret = -ENOMEM;
7966 config = kzalloc(sizeof(*config), GFP_KERNEL);
7967 if (!config)
7968 goto out_config;
7969
7970 ret = intel_set_config_save_state(dev, config);
7971 if (ret)
7972 goto out_config;
7973
7974 save_set.crtc = set->crtc;
7975 save_set.mode = &set->crtc->mode;
7976 save_set.x = set->crtc->x;
7977 save_set.y = set->crtc->y;
7978 save_set.fb = set->crtc->fb;
7979
7980 /* Compute whether we need a full modeset, only an fb base update or no
7981 * change at all. In the future we might also check whether only the
7982 * mode changed, e.g. for LVDS where we only change the panel fitter in
7983 * such cases. */
7984 intel_set_config_compute_mode_changes(set, config);
7985
9a935856 7986 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7987 if (ret)
7988 goto fail;
7989
5e2b584e 7990 if (config->mode_changed) {
87f1faa6 7991 if (set->mode) {
50f56119
DV		 7992 DRM_DEBUG_KMS("attempting to set mode from"
7993 " userspace\n");
7994 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7995 }
7996
c0c36b94
CW		 7997 ret = intel_set_mode(set->crtc, set->mode,
7998 set->x, set->y, set->fb);
7999 if (ret) {
8000 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8001 set->crtc->base.id, ret);
87f1faa6
DV		 8002 goto fail;
8003 }
5e2b584e 8004 } else if (config->fb_changed) {
4f660f49 8005 ret = intel_pipe_set_base(set->crtc,
94352cf9 8006 set->x, set->y, set->fb);
50f56119
DV		 8007 }
8008
d9e55608
DV		 8009 intel_set_config_free(config);
8010
50f56119
DV		 8011 return 0;
8012
8013fail:
85f9eb71 8014 intel_set_config_restore_state(dev, config);
50f56119
DV		 8015
8016 /* Try to restore the config */
5e2b584e 8017 if (config->mode_changed &&
c0c36b94
CW		 8018 intel_set_mode(save_set.crtc, save_set.mode,
8019 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8020 DRM_ERROR("failed to restore config after modeset failure\n");
8021
d9e55608
DV		 8022out_config:
8023 intel_set_config_free(config);
50f56119
DV		 8024 return ret;
8025}
f6e5b160
CW		 8026
8027static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8028 .cursor_set = intel_crtc_cursor_set,
8029 .cursor_move = intel_crtc_cursor_move,
8030 .gamma_set = intel_crtc_gamma_set,
50f56119 8031 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8032 .destroy = intel_crtc_destroy,
8033 .page_flip = intel_crtc_page_flip,
8034};
8035
79f689aa
PZ		 8036static void intel_cpu_pll_init(struct drm_device *dev)
8037{
affa9354 8038 if (HAS_DDI(dev))
79f689aa
PZ		 8039 intel_ddi_pll_init(dev);
8040}
8041
ee7b9f93
JB		 8042static void intel_pch_pll_init(struct drm_device *dev)
8043{
8044 drm_i915_private_t *dev_priv = dev->dev_private;
8045 int i;
8046
8047 if (dev_priv->num_pch_pll == 0) {
8048 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8049 return;
8050 }
8051
8052 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8053 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8054 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8055 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8056 }
8057}
8058
b358d0a6 8059static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8060{
22fd0fab 8061 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8062 struct intel_crtc *intel_crtc;
8063 int i;
8064
8065 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8066 if (intel_crtc == NULL)
8067 return;
8068
8069 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8070
8071 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8072 for (i = 0; i < 256; i++) {
8073 intel_crtc->lut_r[i] = i;
8074 intel_crtc->lut_g[i] = i;
8075 intel_crtc->lut_b[i] = i;
8076 }
8077
80824003
JB		 8078 /* Swap pipes & planes for FBC on pre-965 */
8079 intel_crtc->pipe = pipe;
8080 intel_crtc->plane = pipe;
a5c961d1 8081 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8082 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8083 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8084 intel_crtc->plane = !pipe;
80824003
JB		 8085 }
8086
22fd0fab
JB		 8087 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8088 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8089 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8090 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8091
5a354204 8092 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8093
79e53945 8094 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8095}
8096
08d7b3d1 8097int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8098 struct drm_file *file)
08d7b3d1 8099{
08d7b3d1 8100 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8101 struct drm_mode_object *drmmode_obj;
8102 struct intel_crtc *crtc;
08d7b3d1 8103
1cff8f6b
DV		 8104 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8105 return -ENODEV;
08d7b3d1 8106
c05422d5
DV		 8107 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8108 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8109
c05422d5 8110 if (!drmmode_obj) {
08d7b3d1
CW		 8111 DRM_ERROR("no such CRTC id\n");
8112 return -EINVAL;
8113 }
8114
c05422d5
DV		 8115 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8116 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8117
c05422d5 8118 return 0;
08d7b3d1
CW		 8119}
8120
66a9278e 8121static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8122{
66a9278e
DV		 8123 struct drm_device *dev = encoder->base.dev;
8124 struct intel_encoder *source_encoder;
79e53945 8125 int index_mask = 0;
79e53945
JB		 8126 int entry = 0;
8127
66a9278e
DV		 8128 list_for_each_entry(source_encoder,
8129 &dev->mode_config.encoder_list, base.head) {
8130
8131 if (encoder == source_encoder)
79e53945 8132 index_mask |= (1 << entry);
66a9278e
DV		 8133
8134 /* Intel hw has only one MUX where enocoders could be cloned. */
8135 if (encoder->cloneable && source_encoder->cloneable)
8136 index_mask |= (1 << entry);
8137
79e53945
JB		 8138 entry++;
8139 }
4ef69c7a 8140
79e53945
JB		 8141 return index_mask;
8142}
8143
4d302442
CW		 8144static bool has_edp_a(struct drm_device *dev)
8145{
8146 struct drm_i915_private *dev_priv = dev->dev_private;
8147
8148 if (!IS_MOBILE(dev))
8149 return false;
8150
8151 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8152 return false;
8153
8154 if (IS_GEN5(dev) &&
8155 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8156 return false;
8157
8158 return true;
8159}
8160
79e53945
JB		 8161static void intel_setup_outputs(struct drm_device *dev)
8162{
725e30ad 8163 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8164 struct intel_encoder *encoder;
cb0953d7 8165 bool dpd_is_edp = false;
f3cfcba6 8166 bool has_lvds;
79e53945 8167
f3cfcba6 8168 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8169 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8170 /* disable the panel fitter on everything but LVDS */
8171 I915_WRITE(PFIT_CONTROL, 0);
8172 }
79e53945 8173
affa9354 8174 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8175 intel_crt_init(dev);
cb0953d7 8176
affa9354 8177 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8178 int found;
8179
8180 /* Haswell uses DDI functions to detect digital outputs */
8181 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8182 /* DDI A only supports eDP */
8183 if (found)
8184 intel_ddi_init(dev, PORT_A);
8185
8186 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8187 * register */
8188 found = I915_READ(SFUSE_STRAP);
8189
8190 if (found & SFUSE_STRAP_DDIB_DETECTED)
8191 intel_ddi_init(dev, PORT_B);
8192 if (found & SFUSE_STRAP_DDIC_DETECTED)
8193 intel_ddi_init(dev, PORT_C);
8194 if (found & SFUSE_STRAP_DDID_DETECTED)
8195 intel_ddi_init(dev, PORT_D);
8196 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8197 int found;
270b3042
DV		 8198 dpd_is_edp = intel_dpd_is_edp(dev);
8199
8200 if (has_edp_a(dev))
8201 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8202
30ad48b7 8203 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8204 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8205 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8206 if (!found)
08d644ad 8207 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8208 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8209 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8210 }
8211
8212 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8213 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8214
b708a1d5 8215 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8216 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8217
5eb08b69 8218 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8219 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8220
270b3042 8221 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8222 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8223 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8224 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8225 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8226 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8227
67cfc203
VS		 8228 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8229 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8230 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8231 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d
JB		 8232 }
8233
67cfc203
VS		 8234 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8235 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
5eb08b69 8236
103a196f 8237 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8238 bool found = false;
7d57382e 8239
725e30ad 8240 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8241 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8242 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8243 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8244 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8245 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8246 }
27185ae1 8247
b01f2c3a
JB		 8248 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8249 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8250 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8251 }
725e30ad 8252 }
13520b05
KH		 8253
8254 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8255
b01f2c3a
JB		 8256 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8257 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8258 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8259 }
27185ae1
ML		 8260
8261 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8262
b01f2c3a
JB		 8263 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8264 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8265 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8266 }
8267 if (SUPPORTS_INTEGRATED_DP(dev)) {
8268 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8269 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8270 }
725e30ad 8271 }
27185ae1 8272
b01f2c3a
JB		 8273 if (SUPPORTS_INTEGRATED_DP(dev) &&
8274 (I915_READ(DP_D) & DP_DETECTED)) {
8275 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8276 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8277 }
bad720ff 8278 } else if (IS_GEN2(dev))
79e53945
JB		 8279 intel_dvo_init(dev);
8280
103a196f 8281 if (SUPPORTS_TV(dev))
79e53945
JB		 8282 intel_tv_init(dev);
8283
4ef69c7a
CW		 8284 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8285 encoder->base.possible_crtcs = encoder->crtc_mask;
8286 encoder->base.possible_clones =
66a9278e 8287 intel_encoder_clones(encoder);
79e53945 8288 }
47356eb6 8289
dde86e2d 8290 intel_init_pch_refclk(dev);
270b3042
DV		 8291
8292 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8293}
8294
8295static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8296{
8297 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8298
8299 drm_framebuffer_cleanup(fb);
05394f39 8300 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8301
8302 kfree(intel_fb);
8303}
8304
8305static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8306 struct drm_file *file,
79e53945
JB		 8307 unsigned int *handle)
8308{
8309 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8310 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8311
05394f39 8312 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8313}
8314
8315static const struct drm_framebuffer_funcs intel_fb_funcs = {
8316 .destroy = intel_user_framebuffer_destroy,
8317 .create_handle = intel_user_framebuffer_create_handle,
8318};
8319
38651674
DA		 8320int intel_framebuffer_init(struct drm_device *dev,
8321 struct intel_framebuffer *intel_fb,
308e5bcb 8322 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8323 struct drm_i915_gem_object *obj)
79e53945 8324{
79e53945
JB		 8325 int ret;
8326
05394f39 8327 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8328 return -EINVAL;
8329
308e5bcb 8330 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8331 return -EINVAL;
8332
5d7bd705
VS		 8333 /* FIXME <= Gen4 stride limits are bit unclear */
8334 if (mode_cmd->pitches[0] > 32768)
8335 return -EINVAL;
8336
8337 if (obj->tiling_mode != I915_TILING_NONE &&
8338 mode_cmd->pitches[0] != obj->stride)
8339 return -EINVAL;
8340
57779d06 8341 /* Reject formats not supported by any plane early. */
308e5bcb 8342 switch (mode_cmd->pixel_format) {
57779d06 8343 case DRM_FORMAT_C8:
04b3924d
VS		 8344 case DRM_FORMAT_RGB565:
8345 case DRM_FORMAT_XRGB8888:
8346 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8347 break;
8348 case DRM_FORMAT_XRGB1555:
8349 case DRM_FORMAT_ARGB1555:
8350 if (INTEL_INFO(dev)->gen > 3)
8351 return -EINVAL;
8352 break;
8353 case DRM_FORMAT_XBGR8888:
8354 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8355 case DRM_FORMAT_XRGB2101010:
8356 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8357 case DRM_FORMAT_XBGR2101010:
8358 case DRM_FORMAT_ABGR2101010:
8359 if (INTEL_INFO(dev)->gen < 4)
8360 return -EINVAL;
b5626747 8361 break;
04b3924d
VS		 8362 case DRM_FORMAT_YUYV:
8363 case DRM_FORMAT_UYVY:
8364 case DRM_FORMAT_YVYU:
8365 case DRM_FORMAT_VYUY:
57779d06
VS		 8366 if (INTEL_INFO(dev)->gen < 6)
8367 return -EINVAL;
57cd6508
CW		 8368 break;
8369 default:
57779d06 8370 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8371 return -EINVAL;
8372 }
8373
90f9a336
VS		 8374 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8375 if (mode_cmd->offsets[0] != 0)
8376 return -EINVAL;
8377
79e53945
JB		 8378 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8379 if (ret) {
8380 DRM_ERROR("framebuffer init failed %d\n", ret);
8381 return ret;
8382 }
8383
8384 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8385 intel_fb->obj = obj;
79e53945
JB		 8386 return 0;
8387}
8388
79e53945
JB		 8389static struct drm_framebuffer *
8390intel_user_framebuffer_create(struct drm_device *dev,
8391 struct drm_file *filp,
308e5bcb 8392 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8393{
05394f39 8394 struct drm_i915_gem_object *obj;
79e53945 8395
308e5bcb
JB		 8396 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8397 mode_cmd->handles[0]));
c8725226 8398 if (&obj->base == NULL)
cce13ff7 8399 return ERR_PTR(-ENOENT);
79e53945 8400
d2dff872 8401 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8402}
8403
79e53945 8404static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8405 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8406 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8407};
8408
e70236a8
JB		 8409/* Set up chip specific display functions */
8410static void intel_init_display(struct drm_device *dev)
8411{
8412 struct drm_i915_private *dev_priv = dev->dev_private;
8413
8414 /* We always want a DPMS function */
affa9354 8415 if (HAS_DDI(dev)) {
09b4ddf9 8416 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8417 dev_priv->display.crtc_enable = haswell_crtc_enable;
8418 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8419 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8420 dev_priv->display.update_plane = ironlake_update_plane;
8421 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8422 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8423 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8424 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8425 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8426 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8427 } else {
f564048e 8428 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8429 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8430 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8431 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8432 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8433 }
e70236a8 8434
e70236a8 8435 /* Returns the core display clock speed */
25eb05fc
JB		 8436 if (IS_VALLEYVIEW(dev))
8437 dev_priv->display.get_display_clock_speed =
8438 valleyview_get_display_clock_speed;
8439 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8440 dev_priv->display.get_display_clock_speed =
8441 i945_get_display_clock_speed;
8442 else if (IS_I915G(dev))
8443 dev_priv->display.get_display_clock_speed =
8444 i915_get_display_clock_speed;
f2b115e6 8445 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8446 dev_priv->display.get_display_clock_speed =
8447 i9xx_misc_get_display_clock_speed;
8448 else if (IS_I915GM(dev))
8449 dev_priv->display.get_display_clock_speed =
8450 i915gm_get_display_clock_speed;
8451 else if (IS_I865G(dev))
8452 dev_priv->display.get_display_clock_speed =
8453 i865_get_display_clock_speed;
f0f8a9ce 8454 else if (IS_I85X(dev))
e70236a8
JB		 8455 dev_priv->display.get_display_clock_speed =
8456 i855_get_display_clock_speed;
8457 else /* 852, 830 */
8458 dev_priv->display.get_display_clock_speed =
8459 i830_get_display_clock_speed;
8460
7f8a8569 8461 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8462 if (IS_GEN5(dev)) {
674cf967 8463 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8464 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8465 } else if (IS_GEN6(dev)) {
674cf967 8466 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8467 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8468 } else if (IS_IVYBRIDGE(dev)) {
8469 /* FIXME: detect B0+ stepping and use auto training */
8470 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8471 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8472 dev_priv->display.modeset_global_resources =
8473 ivb_modeset_global_resources;
c82e4d26
ED		 8474 } else if (IS_HASWELL(dev)) {
8475 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8476 dev_priv->display.write_eld = haswell_write_eld;
a0e63c22 8477 }
6067aaea 8478 } else if (IS_G4X(dev)) {
e0dac65e 8479 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8480 }
8c9f3aaf
JB		 8481
8482 /* Default just returns -ENODEV to indicate unsupported */
8483 dev_priv->display.queue_flip = intel_default_queue_flip;
8484
8485 switch (INTEL_INFO(dev)->gen) {
8486 case 2:
8487 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8488 break;
8489
8490 case 3:
8491 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8492 break;
8493
8494 case 4:
8495 case 5:
8496 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8497 break;
8498
8499 case 6:
8500 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8501 break;
7c9017e5
JB		 8502 case 7:
8503 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8504 break;
8c9f3aaf 8505 }
e70236a8
JB		 8506}
8507
b690e96c
JB		 8508/*
8509 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8510 * resume, or other times. This quirk makes sure that's the case for
8511 * affected systems.
8512 */
0206e353 8513static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8514{
8515 struct drm_i915_private *dev_priv = dev->dev_private;
8516
8517 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8518 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8519}
8520
435793df
KP		 8521/*
8522 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8523 */
8524static void quirk_ssc_force_disable(struct drm_device *dev)
8525{
8526 struct drm_i915_private *dev_priv = dev->dev_private;
8527 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8528 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8529}
8530
4dca20ef 8531/*
5a15ab5b
CE		 8532 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8533 * brightness value
4dca20ef
CE		 8534 */
8535static void quirk_invert_brightness(struct drm_device *dev)
8536{
8537 struct drm_i915_private *dev_priv = dev->dev_private;
8538 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8539 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8540}
8541
b690e96c
JB		 8542struct intel_quirk {
8543 int device;
8544 int subsystem_vendor;
8545 int subsystem_device;
8546 void (*hook)(struct drm_device *dev);
8547};
8548
5f85f176
EE		 8549/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8550struct intel_dmi_quirk {
8551 void (*hook)(struct drm_device *dev);
8552 const struct dmi_system_id (*dmi_id_list)[];
8553};
8554
8555static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8556{
8557 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8558 return 1;
8559}
8560
8561static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8562 {
8563 .dmi_id_list = &(const struct dmi_system_id[]) {
8564 {
8565 .callback = intel_dmi_reverse_brightness,
8566 .ident = "NCR Corporation",
8567 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8568 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8569 },
8570 },
8571 { } /* terminating entry */
8572 },
8573 .hook = quirk_invert_brightness,
8574 },
8575};
8576
c43b5634 8577static struct intel_quirk intel_quirks[] = {
b690e96c 8578 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8579 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8580
b690e96c
JB		 8581 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8582 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8583
b690e96c
JB		 8584 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8585 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8586
ccd0d36e 8587 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8588 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8589 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8590
8591 /* Lenovo U160 cannot use SSC on LVDS */
8592 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8593
8594 /* Sony Vaio Y cannot use SSC on LVDS */
8595 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8596
8597 /* Acer Aspire 5734Z must invert backlight brightness */
8598 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8599
8600 /* Acer/eMachines G725 */
8601 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8602
8603 /* Acer/eMachines e725 */
8604 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8605
8606 /* Acer/Packard Bell NCL20 */
8607 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
b690e96c
JB		 8608};
8609
8610static void intel_init_quirks(struct drm_device *dev)
8611{
8612 struct pci_dev *d = dev->pdev;
8613 int i;
8614
8615 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8616 struct intel_quirk *q = &intel_quirks[i];
8617
8618 if (d->device == q->device &&
8619 (d->subsystem_vendor == q->subsystem_vendor ||
8620 q->subsystem_vendor == PCI_ANY_ID) &&
8621 (d->subsystem_device == q->subsystem_device ||
8622 q->subsystem_device == PCI_ANY_ID))
8623 q->hook(dev);
8624 }
5f85f176
EE		 8625 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8626 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8627 intel_dmi_quirks[i].hook(dev);
8628 }
b690e96c
JB		 8629}
8630
9cce37f4
JB		 8631/* Disable the VGA plane that we never use */
8632static void i915_disable_vga(struct drm_device *dev)
8633{
8634 struct drm_i915_private *dev_priv = dev->dev_private;
8635 u8 sr1;
8636 u32 vga_reg;
8637
8638 if (HAS_PCH_SPLIT(dev))
8639 vga_reg = CPU_VGACNTRL;
8640 else
8641 vga_reg = VGACNTRL;
8642
8643 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8644 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8645 sr1 = inb(VGA_SR_DATA);
8646 outb(sr1 | 1<<5, VGA_SR_DATA);
8647 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8648 udelay(300);
8649
8650 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8651 POSTING_READ(vga_reg);
8652}
8653
f817586c
DV		 8654void intel_modeset_init_hw(struct drm_device *dev)
8655{
fa42e23c 8656 intel_init_power_well(dev);
0232e927 8657
a8f78b58
ED		 8658 intel_prepare_ddi(dev);
8659
f817586c
DV		 8660 intel_init_clock_gating(dev);
8661
79f5b2c7 8662 mutex_lock(&dev->struct_mutex);
8090c6b9 8663 intel_enable_gt_powersave(dev);
79f5b2c7 8664 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8665}
8666
79e53945
JB		 8667void intel_modeset_init(struct drm_device *dev)
8668{
652c393a 8669 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8670 int i, ret;
79e53945
JB		 8671
8672 drm_mode_config_init(dev);
8673
8674 dev->mode_config.min_width = 0;
8675 dev->mode_config.min_height = 0;
8676
019d96cb
DA		 8677 dev->mode_config.preferred_depth = 24;
8678 dev->mode_config.prefer_shadow = 1;
8679
e6ecefaa 8680 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8681
b690e96c
JB		 8682 intel_init_quirks(dev);
8683
1fa61106
ED		 8684 intel_init_pm(dev);
8685
e70236a8
JB		 8686 intel_init_display(dev);
8687
a6c45cf0
CW		 8688 if (IS_GEN2(dev)) {
8689 dev->mode_config.max_width = 2048;
8690 dev->mode_config.max_height = 2048;
8691 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8692 dev->mode_config.max_width = 4096;
8693 dev->mode_config.max_height = 4096;
79e53945 8694 } else {
a6c45cf0
CW		 8695 dev->mode_config.max_width = 8192;
8696 dev->mode_config.max_height = 8192;
79e53945 8697 }
5d4545ae 8698 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8699
28c97730 8700 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8701 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8702
a3524f1b 8703 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8704 intel_crtc_init(dev, i);
00c2064b
JB		 8705 ret = intel_plane_init(dev, i);
8706 if (ret)
8707 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8708 }
8709
79f689aa 8710 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8711 intel_pch_pll_init(dev);
8712
9cce37f4
JB		 8713 /* Just disable it once at startup */
8714 i915_disable_vga(dev);
79e53945 8715 intel_setup_outputs(dev);
11be49eb
CW		 8716
8717 /* Just in case the BIOS is doing something questionable. */
8718 intel_disable_fbc(dev);
2c7111db
CW		 8719}
8720
24929352
DV		 8721static void
8722intel_connector_break_all_links(struct intel_connector *connector)
8723{
8724 connector->base.dpms = DRM_MODE_DPMS_OFF;
8725 connector->base.encoder = NULL;
8726 connector->encoder->connectors_active = false;
8727 connector->encoder->base.crtc = NULL;
8728}
8729
7fad798e
DV		 8730static void intel_enable_pipe_a(struct drm_device *dev)
8731{
8732 struct intel_connector *connector;
8733 struct drm_connector *crt = NULL;
8734 struct intel_load_detect_pipe load_detect_temp;
8735
8736 /* We can't just switch on the pipe A, we need to set things up with a
8737 * proper mode and output configuration. As a gross hack, enable pipe A
8738 * by enabling the load detect pipe once. */
8739 list_for_each_entry(connector,
8740 &dev->mode_config.connector_list,
8741 base.head) {
8742 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8743 crt = &connector->base;
8744 break;
8745 }
8746 }
8747
8748 if (!crt)
8749 return;
8750
8751 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8752 intel_release_load_detect_pipe(crt, &load_detect_temp);
8753
652c393a 8754
7fad798e
DV		 8755}
8756
fa555837
DV		 8757static bool
8758intel_check_plane_mapping(struct intel_crtc *crtc)
8759{
8760 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8761 u32 reg, val;
8762
8763 if (dev_priv->num_pipe == 1)
8764 return true;
8765
8766 reg = DSPCNTR(!crtc->plane);
8767 val = I915_READ(reg);
8768
8769 if ((val & DISPLAY_PLANE_ENABLE) &&
8770 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8771 return false;
8772
8773 return true;
8774}
8775
24929352
DV		 8776static void intel_sanitize_crtc(struct intel_crtc *crtc)
8777{
8778 struct drm_device *dev = crtc->base.dev;
8779 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8780 u32 reg;
24929352 8781
24929352 8782 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8783 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8784 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8785
8786 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8787 * disable the crtc (and hence change the state) if it is wrong. Note
8788 * that gen4+ has a fixed plane -> pipe mapping. */
8789 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8790 struct intel_connector *connector;
8791 bool plane;
8792
24929352
DV		 8793 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8794 crtc->base.base.id);
8795
8796 /* Pipe has the wrong plane attached and the plane is active.
8797 * Temporarily change the plane mapping and disable everything
8798 * ... */
8799 plane = crtc->plane;
8800 crtc->plane = !plane;
8801 dev_priv->display.crtc_disable(&crtc->base);
8802 crtc->plane = plane;
8803
8804 /* ... and break all links. */
8805 list_for_each_entry(connector, &dev->mode_config.connector_list,
8806 base.head) {
8807 if (connector->encoder->base.crtc != &crtc->base)
8808 continue;
8809
8810 intel_connector_break_all_links(connector);
8811 }
8812
8813 WARN_ON(crtc->active);
8814 crtc->base.enabled = false;
8815 }
24929352 8816
7fad798e
DV		 8817 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8818 crtc->pipe == PIPE_A && !crtc->active) {
8819 /* BIOS forgot to enable pipe A, this mostly happens after
8820 * resume. Force-enable the pipe to fix this, the update_dpms
8821 * call below we restore the pipe to the right state, but leave
8822 * the required bits on. */
8823 intel_enable_pipe_a(dev);
8824 }
8825
24929352
DV		 8826 /* Adjust the state of the output pipe according to whether we
8827 * have active connectors/encoders. */
8828 intel_crtc_update_dpms(&crtc->base);
8829
8830 if (crtc->active != crtc->base.enabled) {
8831 struct intel_encoder *encoder;
8832
8833 /* This can happen either due to bugs in the get_hw_state
8834 * functions or because the pipe is force-enabled due to the
8835 * pipe A quirk. */
8836 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8837 crtc->base.base.id,
8838 crtc->base.enabled ? "enabled" : "disabled",
8839 crtc->active ? "enabled" : "disabled");
8840
8841 crtc->base.enabled = crtc->active;
8842
8843 /* Because we only establish the connector -> encoder ->
8844 * crtc links if something is active, this means the
8845 * crtc is now deactivated. Break the links. connector
8846 * -> encoder links are only establish when things are
8847 * actually up, hence no need to break them. */
8848 WARN_ON(crtc->active);
8849
8850 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8851 WARN_ON(encoder->connectors_active);
8852 encoder->base.crtc = NULL;
8853 }
8854 }
8855}
8856
8857static void intel_sanitize_encoder(struct intel_encoder *encoder)
8858{
8859 struct intel_connector *connector;
8860 struct drm_device *dev = encoder->base.dev;
8861
8862 /* We need to check both for a crtc link (meaning that the
8863 * encoder is active and trying to read from a pipe) and the
8864 * pipe itself being active. */
8865 bool has_active_crtc = encoder->base.crtc &&
8866 to_intel_crtc(encoder->base.crtc)->active;
8867
8868 if (encoder->connectors_active && !has_active_crtc) {
8869 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8870 encoder->base.base.id,
8871 drm_get_encoder_name(&encoder->base));
8872
8873 /* Connector is active, but has no active pipe. This is
8874 * fallout from our resume register restoring. Disable
8875 * the encoder manually again. */
8876 if (encoder->base.crtc) {
8877 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8878 encoder->base.base.id,
8879 drm_get_encoder_name(&encoder->base));
8880 encoder->disable(encoder);
8881 }
8882
8883 /* Inconsistent output/port/pipe state happens presumably due to
8884 * a bug in one of the get_hw_state functions. Or someplace else
8885 * in our code, like the register restore mess on resume. Clamp
8886 * things to off as a safer default. */
8887 list_for_each_entry(connector,
8888 &dev->mode_config.connector_list,
8889 base.head) {
8890 if (connector->encoder != encoder)
8891 continue;
8892
8893 intel_connector_break_all_links(connector);
8894 }
8895 }
8896 /* Enabled encoders without active connectors will be fixed in
8897 * the crtc fixup. */
8898}
8899
44cec740 8900void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 8901{
8902 struct drm_i915_private *dev_priv = dev->dev_private;
8903 u32 vga_reg;
8904
8905 if (HAS_PCH_SPLIT(dev))
8906 vga_reg = CPU_VGACNTRL;
8907 else
8908 vga_reg = VGACNTRL;
8909
8910 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
8911 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
8912 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8913 POSTING_READ(vga_reg);
8914 }
8915}
8916
24929352
DV		 8917/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8918 * and i915 state tracking structures. */
45e2b5f6
DV		 8919void intel_modeset_setup_hw_state(struct drm_device *dev,
8920 bool force_restore)
24929352
DV		 8921{
8922 struct drm_i915_private *dev_priv = dev->dev_private;
8923 enum pipe pipe;
8924 u32 tmp;
8925 struct intel_crtc *crtc;
8926 struct intel_encoder *encoder;
8927 struct intel_connector *connector;
8928
affa9354 8929 if (HAS_DDI(dev)) {
e28d54cb
PZ		 8930 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8931
8932 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8933 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8934 case TRANS_DDI_EDP_INPUT_A_ON:
8935 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8936 pipe = PIPE_A;
8937 break;
8938 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8939 pipe = PIPE_B;
8940 break;
8941 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8942 pipe = PIPE_C;
8943 break;
8944 }
8945
8946 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8947 crtc->cpu_transcoder = TRANSCODER_EDP;
8948
8949 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8950 pipe_name(pipe));
8951 }
8952 }
8953
24929352
DV		 8954 for_each_pipe(pipe) {
8955 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8956
702e7a56 8957 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8958 if (tmp & PIPECONF_ENABLE)
8959 crtc->active = true;
8960 else
8961 crtc->active = false;
8962
8963 crtc->base.enabled = crtc->active;
8964
8965 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8966 crtc->base.base.id,
8967 crtc->active ? "enabled" : "disabled");
8968 }
8969
affa9354 8970 if (HAS_DDI(dev))
6441ab5f
PZ		 8971 intel_ddi_setup_hw_pll_state(dev);
8972
24929352
DV		 8973 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8974 base.head) {
8975 pipe = 0;
8976
8977 if (encoder->get_hw_state(encoder, &pipe)) {
8978 encoder->base.crtc =
8979 dev_priv->pipe_to_crtc_mapping[pipe];
8980 } else {
8981 encoder->base.crtc = NULL;
8982 }
8983
8984 encoder->connectors_active = false;
8985 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8986 encoder->base.base.id,
8987 drm_get_encoder_name(&encoder->base),
8988 encoder->base.crtc ? "enabled" : "disabled",
8989 pipe);
8990 }
8991
8992 list_for_each_entry(connector, &dev->mode_config.connector_list,
8993 base.head) {
8994 if (connector->get_hw_state(connector)) {
8995 connector->base.dpms = DRM_MODE_DPMS_ON;
8996 connector->encoder->connectors_active = true;
8997 connector->base.encoder = &connector->encoder->base;
8998 } else {
8999 connector->base.dpms = DRM_MODE_DPMS_OFF;
9000 connector->base.encoder = NULL;
9001 }
9002 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9003 connector->base.base.id,
9004 drm_get_connector_name(&connector->base),
9005 connector->base.encoder ? "enabled" : "disabled");
9006 }
9007
9008 /* HW state is read out, now we need to sanitize this mess. */
9009 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9010 base.head) {
9011 intel_sanitize_encoder(encoder);
9012 }
9013
9014 for_each_pipe(pipe) {
9015 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9016 intel_sanitize_crtc(crtc);
9017 }
9a935856 9018
45e2b5f6
DV		 9019 if (force_restore) {
9020 for_each_pipe(pipe) {
c0c36b94 9021 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
45e2b5f6 9022 }
0fde901f
KM		 9023
9024 i915_redisable_vga(dev);
45e2b5f6
DV		 9025 } else {
9026 intel_modeset_update_staged_output_state(dev);
9027 }
8af6cf88
DV		 9028
9029 intel_modeset_check_state(dev);
2e938892
DV		 9030
9031 drm_mode_config_reset(dev);
2c7111db
CW		 9032}
9033
9034void intel_modeset_gem_init(struct drm_device *dev)
9035{
1833b134 9036 intel_modeset_init_hw(dev);
02e792fb
DV		 9037
9038 intel_setup_overlay(dev);
24929352 9039
45e2b5f6 9040 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9041}
9042
9043void intel_modeset_cleanup(struct drm_device *dev)
9044{
652c393a
JB		 9045 struct drm_i915_private *dev_priv = dev->dev_private;
9046 struct drm_crtc *crtc;
9047 struct intel_crtc *intel_crtc;
9048
f87ea761 9049 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9050 mutex_lock(&dev->struct_mutex);
9051
723bfd70
JB		 9052 intel_unregister_dsm_handler();
9053
9054
652c393a
JB		 9055 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9056 /* Skip inactive CRTCs */
9057 if (!crtc->fb)
9058 continue;
9059
9060 intel_crtc = to_intel_crtc(crtc);
3dec0095 9061 intel_increase_pllclock(crtc);
652c393a
JB		 9062 }
9063
973d04f9 9064 intel_disable_fbc(dev);
e70236a8 9065
8090c6b9 9066 intel_disable_gt_powersave(dev);
0cdab21f 9067
930ebb46
DV		 9068 ironlake_teardown_rc6(dev);
9069
57f350b6
JB		 9070 if (IS_VALLEYVIEW(dev))
9071 vlv_init_dpio(dev);
9072
69341a5e
KH		 9073 mutex_unlock(&dev->struct_mutex);
9074
6c0d9350
DV		 9075 /* Disable the irq before mode object teardown, for the irq might
9076 * enqueue unpin/hotplug work. */
9077 drm_irq_uninstall(dev);
9078 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9079 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9080
1630fe75
CW		 9081 /* flush any delayed tasks or pending work */
9082 flush_scheduled_work();
9083
79e53945 9084 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9085
9086 intel_cleanup_overlay(dev);
79e53945
JB		 9087}
9088
f1c79df3
ZW		 9089/*
9090 * Return which encoder is currently attached for connector.
9091 */
df0e9248 9092struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9093{
df0e9248
CW		 9094 return &intel_attached_encoder(connector)->base;
9095}
f1c79df3 9096
df0e9248
CW		 9097void intel_connector_attach_encoder(struct intel_connector *connector,
9098 struct intel_encoder *encoder)
9099{
9100 connector->encoder = encoder;
9101 drm_mode_connector_attach_encoder(&connector->base,
9102 &encoder->base);
79e53945 9103}
28d52043
DA		 9104
9105/*
9106 * set vga decode state - true == enable VGA decode
9107 */
9108int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9109{
9110 struct drm_i915_private *dev_priv = dev->dev_private;
9111 u16 gmch_ctrl;
9112
9113 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9114 if (state)
9115 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9116 else
9117 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9118 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9119 return 0;
9120}
c4a1d9e4
CW		 9121
9122#ifdef CONFIG_DEBUG_FS
9123#include <linux/seq_file.h>
9124
9125struct intel_display_error_state {
9126 struct intel_cursor_error_state {
9127 u32 control;
9128 u32 position;
9129 u32 base;
9130 u32 size;
52331309 9131 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9132
9133 struct intel_pipe_error_state {
9134 u32 conf;
9135 u32 source;
9136
9137 u32 htotal;
9138 u32 hblank;
9139 u32 hsync;
9140 u32 vtotal;
9141 u32 vblank;
9142 u32 vsync;
52331309 9143 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9144
9145 struct intel_plane_error_state {
9146 u32 control;
9147 u32 stride;
9148 u32 size;
9149 u32 pos;
9150 u32 addr;
9151 u32 surface;
9152 u32 tile_offset;
52331309 9153 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9154};
9155
9156struct intel_display_error_state *
9157intel_display_capture_error_state(struct drm_device *dev)
9158{
0206e353 9159 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9160 struct intel_display_error_state *error;
702e7a56 9161 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9162 int i;
9163
9164 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9165 if (error == NULL)
9166 return NULL;
9167
52331309 9168 for_each_pipe(i) {
702e7a56
PZ		 9169 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9170
c4a1d9e4
CW		 9171 error->cursor[i].control = I915_READ(CURCNTR(i));
9172 error->cursor[i].position = I915_READ(CURPOS(i));
9173 error->cursor[i].base = I915_READ(CURBASE(i));
9174
9175 error->plane[i].control = I915_READ(DSPCNTR(i));
9176 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9177 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9178 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9179 error->plane[i].addr = I915_READ(DSPADDR(i));
9180 if (INTEL_INFO(dev)->gen >= 4) {
9181 error->plane[i].surface = I915_READ(DSPSURF(i));
9182 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9183 }
9184
702e7a56 9185 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9186 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9187 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9188 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9189 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9190 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9191 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9192 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9193 }
9194
9195 return error;
9196}
9197
9198void
9199intel_display_print_error_state(struct seq_file *m,
9200 struct drm_device *dev,
9201 struct intel_display_error_state *error)
9202{
52331309 9203 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9204 int i;
9205
52331309
DL		 9206 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9207 for_each_pipe(i) {
c4a1d9e4
CW		 9208 seq_printf(m, "Pipe [%d]:\n", i);
9209 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9210 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9211 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9212 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9213 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9214 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9215 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9216 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9217
9218 seq_printf(m, "Plane [%d]:\n", i);
9219 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9220 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9221 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9222 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9223 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9224 if (INTEL_INFO(dev)->gen >= 4) {
9225 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9226 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9227 }
9228
9229 seq_printf(m, "Cursor [%d]:\n", i);
9230 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9231 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9232 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9233 }
9234}
9235#endif
Linux kernel - Deliverables
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