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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
6b383a7f | 88 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 89 | |
f1f644dc | 90 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
18442d08 | 92 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 93 | struct intel_crtc_state *pipe_config); |
f1f644dc | 94 | |
eb1bfe80 JB |
95 | static int intel_framebuffer_init(struct drm_device *dev, |
96 | struct intel_framebuffer *ifb, | |
97 | struct drm_mode_fb_cmd2 *mode_cmd, | |
98 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
99 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
100 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
102 | struct intel_link_m_n *m_n, |
103 | struct intel_link_m_n *m2_n2); | |
29407aab | 104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
106 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 107 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
d288f65f | 109 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 110 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
111 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
112 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
113 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
114 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
115 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
116 | int num_connectors); | |
bfd16b2a ML |
117 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
118 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
119 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 120 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
200757f5 | 121 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
e7457a9a | 122 | |
79e53945 | 123 | typedef struct { |
0206e353 | 124 | int min, max; |
79e53945 JB |
125 | } intel_range_t; |
126 | ||
127 | typedef struct { | |
0206e353 AJ |
128 | int dot_limit; |
129 | int p2_slow, p2_fast; | |
79e53945 JB |
130 | } intel_p2_t; |
131 | ||
d4906093 ML |
132 | typedef struct intel_limit intel_limit_t; |
133 | struct intel_limit { | |
0206e353 AJ |
134 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
135 | intel_p2_t p2; | |
d4906093 | 136 | }; |
79e53945 | 137 | |
bfa7df01 VS |
138 | /* returns HPLL frequency in kHz */ |
139 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
140 | { | |
141 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
142 | ||
143 | /* Obtain SKU information */ | |
144 | mutex_lock(&dev_priv->sb_lock); | |
145 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
146 | CCK_FUSE_HPLL_FREQ_MASK; | |
147 | mutex_unlock(&dev_priv->sb_lock); | |
148 | ||
149 | return vco_freq[hpll_freq] * 1000; | |
150 | } | |
151 | ||
152 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
153 | const char *name, u32 reg) | |
154 | { | |
155 | u32 val; | |
156 | int divider; | |
157 | ||
158 | if (dev_priv->hpll_freq == 0) | |
159 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
160 | ||
161 | mutex_lock(&dev_priv->sb_lock); | |
162 | val = vlv_cck_read(dev_priv, reg); | |
163 | mutex_unlock(&dev_priv->sb_lock); | |
164 | ||
165 | divider = val & CCK_FREQUENCY_VALUES; | |
166 | ||
167 | WARN((val & CCK_FREQUENCY_STATUS) != | |
168 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
169 | "%s change in progress\n", name); | |
170 | ||
171 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
172 | } | |
173 | ||
d2acd215 DV |
174 | int |
175 | intel_pch_rawclk(struct drm_device *dev) | |
176 | { | |
177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
178 | ||
179 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
180 | ||
181 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
182 | } | |
183 | ||
79e50a4f JN |
184 | /* hrawclock is 1/4 the FSB frequency */ |
185 | int intel_hrawclk(struct drm_device *dev) | |
186 | { | |
187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
188 | uint32_t clkcfg; | |
189 | ||
190 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
666a4537 | 191 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
79e50a4f JN |
192 | return 200; |
193 | ||
194 | clkcfg = I915_READ(CLKCFG); | |
195 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
196 | case CLKCFG_FSB_400: | |
197 | return 100; | |
198 | case CLKCFG_FSB_533: | |
199 | return 133; | |
200 | case CLKCFG_FSB_667: | |
201 | return 166; | |
202 | case CLKCFG_FSB_800: | |
203 | return 200; | |
204 | case CLKCFG_FSB_1067: | |
205 | return 266; | |
206 | case CLKCFG_FSB_1333: | |
207 | return 333; | |
208 | /* these two are just a guess; one of them might be right */ | |
209 | case CLKCFG_FSB_1600: | |
210 | case CLKCFG_FSB_1600_ALT: | |
211 | return 400; | |
212 | default: | |
213 | return 133; | |
214 | } | |
215 | } | |
216 | ||
bfa7df01 VS |
217 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
218 | { | |
666a4537 | 219 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
220 | return; |
221 | ||
222 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
223 | CCK_CZ_CLOCK_CONTROL); | |
224 | ||
225 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
226 | } | |
227 | ||
021357ac CW |
228 | static inline u32 /* units of 100MHz */ |
229 | intel_fdi_link_freq(struct drm_device *dev) | |
230 | { | |
8b99e68c CW |
231 | if (IS_GEN5(dev)) { |
232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
233 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
234 | } else | |
235 | return 27; | |
021357ac CW |
236 | } |
237 | ||
5d536e28 | 238 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 239 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 240 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 241 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
242 | .m = { .min = 96, .max = 140 }, |
243 | .m1 = { .min = 18, .max = 26 }, | |
244 | .m2 = { .min = 6, .max = 16 }, | |
245 | .p = { .min = 4, .max = 128 }, | |
246 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
247 | .p2 = { .dot_limit = 165000, |
248 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
249 | }; |
250 | ||
5d536e28 DV |
251 | static const intel_limit_t intel_limits_i8xx_dvo = { |
252 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 253 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 254 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
255 | .m = { .min = 96, .max = 140 }, |
256 | .m1 = { .min = 18, .max = 26 }, | |
257 | .m2 = { .min = 6, .max = 16 }, | |
258 | .p = { .min = 4, .max = 128 }, | |
259 | .p1 = { .min = 2, .max = 33 }, | |
260 | .p2 = { .dot_limit = 165000, | |
261 | .p2_slow = 4, .p2_fast = 4 }, | |
262 | }; | |
263 | ||
e4b36699 | 264 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 265 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 266 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 267 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
268 | .m = { .min = 96, .max = 140 }, |
269 | .m1 = { .min = 18, .max = 26 }, | |
270 | .m2 = { .min = 6, .max = 16 }, | |
271 | .p = { .min = 4, .max = 128 }, | |
272 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
273 | .p2 = { .dot_limit = 165000, |
274 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 275 | }; |
273e27ca | 276 | |
e4b36699 | 277 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
278 | .dot = { .min = 20000, .max = 400000 }, |
279 | .vco = { .min = 1400000, .max = 2800000 }, | |
280 | .n = { .min = 1, .max = 6 }, | |
281 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
282 | .m1 = { .min = 8, .max = 18 }, |
283 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
284 | .p = { .min = 5, .max = 80 }, |
285 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
286 | .p2 = { .dot_limit = 200000, |
287 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
288 | }; |
289 | ||
290 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
291 | .dot = { .min = 20000, .max = 400000 }, |
292 | .vco = { .min = 1400000, .max = 2800000 }, | |
293 | .n = { .min = 1, .max = 6 }, | |
294 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
295 | .m1 = { .min = 8, .max = 18 }, |
296 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
297 | .p = { .min = 7, .max = 98 }, |
298 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
299 | .p2 = { .dot_limit = 112000, |
300 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
301 | }; |
302 | ||
273e27ca | 303 | |
e4b36699 | 304 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
305 | .dot = { .min = 25000, .max = 270000 }, |
306 | .vco = { .min = 1750000, .max = 3500000}, | |
307 | .n = { .min = 1, .max = 4 }, | |
308 | .m = { .min = 104, .max = 138 }, | |
309 | .m1 = { .min = 17, .max = 23 }, | |
310 | .m2 = { .min = 5, .max = 11 }, | |
311 | .p = { .min = 10, .max = 30 }, | |
312 | .p1 = { .min = 1, .max = 3}, | |
313 | .p2 = { .dot_limit = 270000, | |
314 | .p2_slow = 10, | |
315 | .p2_fast = 10 | |
044c7c41 | 316 | }, |
e4b36699 KP |
317 | }; |
318 | ||
319 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
320 | .dot = { .min = 22000, .max = 400000 }, |
321 | .vco = { .min = 1750000, .max = 3500000}, | |
322 | .n = { .min = 1, .max = 4 }, | |
323 | .m = { .min = 104, .max = 138 }, | |
324 | .m1 = { .min = 16, .max = 23 }, | |
325 | .m2 = { .min = 5, .max = 11 }, | |
326 | .p = { .min = 5, .max = 80 }, | |
327 | .p1 = { .min = 1, .max = 8}, | |
328 | .p2 = { .dot_limit = 165000, | |
329 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
330 | }; |
331 | ||
332 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
333 | .dot = { .min = 20000, .max = 115000 }, |
334 | .vco = { .min = 1750000, .max = 3500000 }, | |
335 | .n = { .min = 1, .max = 3 }, | |
336 | .m = { .min = 104, .max = 138 }, | |
337 | .m1 = { .min = 17, .max = 23 }, | |
338 | .m2 = { .min = 5, .max = 11 }, | |
339 | .p = { .min = 28, .max = 112 }, | |
340 | .p1 = { .min = 2, .max = 8 }, | |
341 | .p2 = { .dot_limit = 0, | |
342 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 343 | }, |
e4b36699 KP |
344 | }; |
345 | ||
346 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
347 | .dot = { .min = 80000, .max = 224000 }, |
348 | .vco = { .min = 1750000, .max = 3500000 }, | |
349 | .n = { .min = 1, .max = 3 }, | |
350 | .m = { .min = 104, .max = 138 }, | |
351 | .m1 = { .min = 17, .max = 23 }, | |
352 | .m2 = { .min = 5, .max = 11 }, | |
353 | .p = { .min = 14, .max = 42 }, | |
354 | .p1 = { .min = 2, .max = 6 }, | |
355 | .p2 = { .dot_limit = 0, | |
356 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 357 | }, |
e4b36699 KP |
358 | }; |
359 | ||
f2b115e6 | 360 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
361 | .dot = { .min = 20000, .max = 400000}, |
362 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 363 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
364 | .n = { .min = 3, .max = 6 }, |
365 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 366 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
367 | .m1 = { .min = 0, .max = 0 }, |
368 | .m2 = { .min = 0, .max = 254 }, | |
369 | .p = { .min = 5, .max = 80 }, | |
370 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
371 | .p2 = { .dot_limit = 200000, |
372 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
373 | }; |
374 | ||
f2b115e6 | 375 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
376 | .dot = { .min = 20000, .max = 400000 }, |
377 | .vco = { .min = 1700000, .max = 3500000 }, | |
378 | .n = { .min = 3, .max = 6 }, | |
379 | .m = { .min = 2, .max = 256 }, | |
380 | .m1 = { .min = 0, .max = 0 }, | |
381 | .m2 = { .min = 0, .max = 254 }, | |
382 | .p = { .min = 7, .max = 112 }, | |
383 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
384 | .p2 = { .dot_limit = 112000, |
385 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
386 | }; |
387 | ||
273e27ca EA |
388 | /* Ironlake / Sandybridge |
389 | * | |
390 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
391 | * the range value for them is (actual_value - 2). | |
392 | */ | |
b91ad0ec | 393 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
394 | .dot = { .min = 25000, .max = 350000 }, |
395 | .vco = { .min = 1760000, .max = 3510000 }, | |
396 | .n = { .min = 1, .max = 5 }, | |
397 | .m = { .min = 79, .max = 127 }, | |
398 | .m1 = { .min = 12, .max = 22 }, | |
399 | .m2 = { .min = 5, .max = 9 }, | |
400 | .p = { .min = 5, .max = 80 }, | |
401 | .p1 = { .min = 1, .max = 8 }, | |
402 | .p2 = { .dot_limit = 225000, | |
403 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
404 | }; |
405 | ||
b91ad0ec | 406 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
407 | .dot = { .min = 25000, .max = 350000 }, |
408 | .vco = { .min = 1760000, .max = 3510000 }, | |
409 | .n = { .min = 1, .max = 3 }, | |
410 | .m = { .min = 79, .max = 118 }, | |
411 | .m1 = { .min = 12, .max = 22 }, | |
412 | .m2 = { .min = 5, .max = 9 }, | |
413 | .p = { .min = 28, .max = 112 }, | |
414 | .p1 = { .min = 2, .max = 8 }, | |
415 | .p2 = { .dot_limit = 225000, | |
416 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
417 | }; |
418 | ||
419 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
420 | .dot = { .min = 25000, .max = 350000 }, |
421 | .vco = { .min = 1760000, .max = 3510000 }, | |
422 | .n = { .min = 1, .max = 3 }, | |
423 | .m = { .min = 79, .max = 127 }, | |
424 | .m1 = { .min = 12, .max = 22 }, | |
425 | .m2 = { .min = 5, .max = 9 }, | |
426 | .p = { .min = 14, .max = 56 }, | |
427 | .p1 = { .min = 2, .max = 8 }, | |
428 | .p2 = { .dot_limit = 225000, | |
429 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
430 | }; |
431 | ||
273e27ca | 432 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 433 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
434 | .dot = { .min = 25000, .max = 350000 }, |
435 | .vco = { .min = 1760000, .max = 3510000 }, | |
436 | .n = { .min = 1, .max = 2 }, | |
437 | .m = { .min = 79, .max = 126 }, | |
438 | .m1 = { .min = 12, .max = 22 }, | |
439 | .m2 = { .min = 5, .max = 9 }, | |
440 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 441 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
442 | .p2 = { .dot_limit = 225000, |
443 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
444 | }; |
445 | ||
446 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
447 | .dot = { .min = 25000, .max = 350000 }, |
448 | .vco = { .min = 1760000, .max = 3510000 }, | |
449 | .n = { .min = 1, .max = 3 }, | |
450 | .m = { .min = 79, .max = 126 }, | |
451 | .m1 = { .min = 12, .max = 22 }, | |
452 | .m2 = { .min = 5, .max = 9 }, | |
453 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 454 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
455 | .p2 = { .dot_limit = 225000, |
456 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
457 | }; |
458 | ||
dc730512 | 459 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
460 | /* |
461 | * These are the data rate limits (measured in fast clocks) | |
462 | * since those are the strictest limits we have. The fast | |
463 | * clock and actual rate limits are more relaxed, so checking | |
464 | * them would make no difference. | |
465 | */ | |
466 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 467 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 468 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
469 | .m1 = { .min = 2, .max = 3 }, |
470 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 471 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 472 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
473 | }; |
474 | ||
ef9348c8 CML |
475 | static const intel_limit_t intel_limits_chv = { |
476 | /* | |
477 | * These are the data rate limits (measured in fast clocks) | |
478 | * since those are the strictest limits we have. The fast | |
479 | * clock and actual rate limits are more relaxed, so checking | |
480 | * them would make no difference. | |
481 | */ | |
482 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 483 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
484 | .n = { .min = 1, .max = 1 }, |
485 | .m1 = { .min = 2, .max = 2 }, | |
486 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
487 | .p1 = { .min = 2, .max = 4 }, | |
488 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
489 | }; | |
490 | ||
5ab7b0b7 ID |
491 | static const intel_limit_t intel_limits_bxt = { |
492 | /* FIXME: find real dot limits */ | |
493 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 494 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
495 | .n = { .min = 1, .max = 1 }, |
496 | .m1 = { .min = 2, .max = 2 }, | |
497 | /* FIXME: find real m2 limits */ | |
498 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
499 | .p1 = { .min = 2, .max = 4 }, | |
500 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
501 | }; | |
502 | ||
cdba954e ACO |
503 | static bool |
504 | needs_modeset(struct drm_crtc_state *state) | |
505 | { | |
fc596660 | 506 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
507 | } |
508 | ||
e0638cdf PZ |
509 | /** |
510 | * Returns whether any output on the specified pipe is of the specified type | |
511 | */ | |
4093561b | 512 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 513 | { |
409ee761 | 514 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
515 | struct intel_encoder *encoder; |
516 | ||
409ee761 | 517 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
518 | if (encoder->type == type) |
519 | return true; | |
520 | ||
521 | return false; | |
522 | } | |
523 | ||
d0737e1d ACO |
524 | /** |
525 | * Returns whether any output on the specified pipe will have the specified | |
526 | * type after a staged modeset is complete, i.e., the same as | |
527 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
528 | * encoder->crtc. | |
529 | */ | |
a93e255f ACO |
530 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
531 | int type) | |
d0737e1d | 532 | { |
a93e255f | 533 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 534 | struct drm_connector *connector; |
a93e255f | 535 | struct drm_connector_state *connector_state; |
d0737e1d | 536 | struct intel_encoder *encoder; |
a93e255f ACO |
537 | int i, num_connectors = 0; |
538 | ||
da3ced29 | 539 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
540 | if (connector_state->crtc != crtc_state->base.crtc) |
541 | continue; | |
542 | ||
543 | num_connectors++; | |
d0737e1d | 544 | |
a93e255f ACO |
545 | encoder = to_intel_encoder(connector_state->best_encoder); |
546 | if (encoder->type == type) | |
d0737e1d | 547 | return true; |
a93e255f ACO |
548 | } |
549 | ||
550 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
551 | |
552 | return false; | |
553 | } | |
554 | ||
a93e255f ACO |
555 | static const intel_limit_t * |
556 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 557 | { |
a93e255f | 558 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 559 | const intel_limit_t *limit; |
b91ad0ec | 560 | |
a93e255f | 561 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 562 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 563 | if (refclk == 100000) |
b91ad0ec ZW |
564 | limit = &intel_limits_ironlake_dual_lvds_100m; |
565 | else | |
566 | limit = &intel_limits_ironlake_dual_lvds; | |
567 | } else { | |
1b894b59 | 568 | if (refclk == 100000) |
b91ad0ec ZW |
569 | limit = &intel_limits_ironlake_single_lvds_100m; |
570 | else | |
571 | limit = &intel_limits_ironlake_single_lvds; | |
572 | } | |
c6bb3538 | 573 | } else |
b91ad0ec | 574 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
575 | |
576 | return limit; | |
577 | } | |
578 | ||
a93e255f ACO |
579 | static const intel_limit_t * |
580 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 581 | { |
a93e255f | 582 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
583 | const intel_limit_t *limit; |
584 | ||
a93e255f | 585 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 586 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 587 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 588 | else |
e4b36699 | 589 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
590 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
591 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 592 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 593 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 594 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 595 | } else /* The option is for other outputs */ |
e4b36699 | 596 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
597 | |
598 | return limit; | |
599 | } | |
600 | ||
a93e255f ACO |
601 | static const intel_limit_t * |
602 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 603 | { |
a93e255f | 604 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
605 | const intel_limit_t *limit; |
606 | ||
5ab7b0b7 ID |
607 | if (IS_BROXTON(dev)) |
608 | limit = &intel_limits_bxt; | |
609 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 610 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 611 | else if (IS_G4X(dev)) { |
a93e255f | 612 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 613 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 614 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 615 | limit = &intel_limits_pineview_lvds; |
2177832f | 616 | else |
f2b115e6 | 617 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
618 | } else if (IS_CHERRYVIEW(dev)) { |
619 | limit = &intel_limits_chv; | |
a0c4da24 | 620 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 621 | limit = &intel_limits_vlv; |
a6c45cf0 | 622 | } else if (!IS_GEN2(dev)) { |
a93e255f | 623 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
624 | limit = &intel_limits_i9xx_lvds; |
625 | else | |
626 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 627 | } else { |
a93e255f | 628 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 629 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 630 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 631 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
632 | else |
633 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
634 | } |
635 | return limit; | |
636 | } | |
637 | ||
dccbea3b ID |
638 | /* |
639 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
640 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
641 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
642 | * The helpers' return value is the rate of the clock that is fed to the | |
643 | * display engine's pipe which can be the above fast dot clock rate or a | |
644 | * divided-down version of it. | |
645 | */ | |
f2b115e6 | 646 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 647 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 648 | { |
2177832f SL |
649 | clock->m = clock->m2 + 2; |
650 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 651 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 652 | return 0; |
fb03ac01 VS |
653 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
654 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
655 | |
656 | return clock->dot; | |
2177832f SL |
657 | } |
658 | ||
7429e9d4 DV |
659 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
660 | { | |
661 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
662 | } | |
663 | ||
dccbea3b | 664 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 665 | { |
7429e9d4 | 666 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 667 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 668 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 669 | return 0; |
fb03ac01 VS |
670 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
671 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
672 | |
673 | return clock->dot; | |
79e53945 JB |
674 | } |
675 | ||
dccbea3b | 676 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
677 | { |
678 | clock->m = clock->m1 * clock->m2; | |
679 | clock->p = clock->p1 * clock->p2; | |
680 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 681 | return 0; |
589eca67 ID |
682 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
683 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
684 | |
685 | return clock->dot / 5; | |
589eca67 ID |
686 | } |
687 | ||
dccbea3b | 688 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
689 | { |
690 | clock->m = clock->m1 * clock->m2; | |
691 | clock->p = clock->p1 * clock->p2; | |
692 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 693 | return 0; |
ef9348c8 CML |
694 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
695 | clock->n << 22); | |
696 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
697 | |
698 | return clock->dot / 5; | |
ef9348c8 CML |
699 | } |
700 | ||
7c04d1d9 | 701 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
702 | /** |
703 | * Returns whether the given set of divisors are valid for a given refclk with | |
704 | * the given connectors. | |
705 | */ | |
706 | ||
1b894b59 CW |
707 | static bool intel_PLL_is_valid(struct drm_device *dev, |
708 | const intel_limit_t *limit, | |
709 | const intel_clock_t *clock) | |
79e53945 | 710 | { |
f01b7962 VS |
711 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
712 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 713 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 714 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 715 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 716 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 717 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 718 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 719 | |
666a4537 WB |
720 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
721 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
722 | if (clock->m1 <= clock->m2) |
723 | INTELPllInvalid("m1 <= m2\n"); | |
724 | ||
666a4537 | 725 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
726 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
727 | INTELPllInvalid("p out of range\n"); | |
728 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
729 | INTELPllInvalid("m out of range\n"); | |
730 | } | |
731 | ||
79e53945 | 732 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 733 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
734 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
735 | * connector, etc., rather than just a single range. | |
736 | */ | |
737 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 738 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
739 | |
740 | return true; | |
741 | } | |
742 | ||
3b1429d9 VS |
743 | static int |
744 | i9xx_select_p2_div(const intel_limit_t *limit, | |
745 | const struct intel_crtc_state *crtc_state, | |
746 | int target) | |
79e53945 | 747 | { |
3b1429d9 | 748 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 749 | |
a93e255f | 750 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 751 | /* |
a210b028 DV |
752 | * For LVDS just rely on its current settings for dual-channel. |
753 | * We haven't figured out how to reliably set up different | |
754 | * single/dual channel state, if we even can. | |
79e53945 | 755 | */ |
1974cad0 | 756 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 757 | return limit->p2.p2_fast; |
79e53945 | 758 | else |
3b1429d9 | 759 | return limit->p2.p2_slow; |
79e53945 JB |
760 | } else { |
761 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 762 | return limit->p2.p2_slow; |
79e53945 | 763 | else |
3b1429d9 | 764 | return limit->p2.p2_fast; |
79e53945 | 765 | } |
3b1429d9 VS |
766 | } |
767 | ||
768 | static bool | |
769 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
770 | struct intel_crtc_state *crtc_state, | |
771 | int target, int refclk, intel_clock_t *match_clock, | |
772 | intel_clock_t *best_clock) | |
773 | { | |
774 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
775 | intel_clock_t clock; | |
776 | int err = target; | |
79e53945 | 777 | |
0206e353 | 778 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 779 | |
3b1429d9 VS |
780 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
781 | ||
42158660 ZY |
782 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
783 | clock.m1++) { | |
784 | for (clock.m2 = limit->m2.min; | |
785 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 786 | if (clock.m2 >= clock.m1) |
42158660 ZY |
787 | break; |
788 | for (clock.n = limit->n.min; | |
789 | clock.n <= limit->n.max; clock.n++) { | |
790 | for (clock.p1 = limit->p1.min; | |
791 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
792 | int this_err; |
793 | ||
dccbea3b | 794 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
795 | if (!intel_PLL_is_valid(dev, limit, |
796 | &clock)) | |
797 | continue; | |
798 | if (match_clock && | |
799 | clock.p != match_clock->p) | |
800 | continue; | |
801 | ||
802 | this_err = abs(clock.dot - target); | |
803 | if (this_err < err) { | |
804 | *best_clock = clock; | |
805 | err = this_err; | |
806 | } | |
807 | } | |
808 | } | |
809 | } | |
810 | } | |
811 | ||
812 | return (err != target); | |
813 | } | |
814 | ||
815 | static bool | |
a93e255f ACO |
816 | pnv_find_best_dpll(const intel_limit_t *limit, |
817 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
818 | int target, int refclk, intel_clock_t *match_clock, |
819 | intel_clock_t *best_clock) | |
79e53945 | 820 | { |
3b1429d9 | 821 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 822 | intel_clock_t clock; |
79e53945 JB |
823 | int err = target; |
824 | ||
0206e353 | 825 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 826 | |
3b1429d9 VS |
827 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
828 | ||
42158660 ZY |
829 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
830 | clock.m1++) { | |
831 | for (clock.m2 = limit->m2.min; | |
832 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
833 | for (clock.n = limit->n.min; |
834 | clock.n <= limit->n.max; clock.n++) { | |
835 | for (clock.p1 = limit->p1.min; | |
836 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
837 | int this_err; |
838 | ||
dccbea3b | 839 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
840 | if (!intel_PLL_is_valid(dev, limit, |
841 | &clock)) | |
79e53945 | 842 | continue; |
cec2f356 SP |
843 | if (match_clock && |
844 | clock.p != match_clock->p) | |
845 | continue; | |
79e53945 JB |
846 | |
847 | this_err = abs(clock.dot - target); | |
848 | if (this_err < err) { | |
849 | *best_clock = clock; | |
850 | err = this_err; | |
851 | } | |
852 | } | |
853 | } | |
854 | } | |
855 | } | |
856 | ||
857 | return (err != target); | |
858 | } | |
859 | ||
d4906093 | 860 | static bool |
a93e255f ACO |
861 | g4x_find_best_dpll(const intel_limit_t *limit, |
862 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
863 | int target, int refclk, intel_clock_t *match_clock, |
864 | intel_clock_t *best_clock) | |
d4906093 | 865 | { |
3b1429d9 | 866 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
867 | intel_clock_t clock; |
868 | int max_n; | |
3b1429d9 | 869 | bool found = false; |
6ba770dc AJ |
870 | /* approximately equals target * 0.00585 */ |
871 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
872 | |
873 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
874 | |
875 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
876 | ||
d4906093 | 877 | max_n = limit->n.max; |
f77f13e2 | 878 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 879 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 880 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
881 | for (clock.m1 = limit->m1.max; |
882 | clock.m1 >= limit->m1.min; clock.m1--) { | |
883 | for (clock.m2 = limit->m2.max; | |
884 | clock.m2 >= limit->m2.min; clock.m2--) { | |
885 | for (clock.p1 = limit->p1.max; | |
886 | clock.p1 >= limit->p1.min; clock.p1--) { | |
887 | int this_err; | |
888 | ||
dccbea3b | 889 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
890 | if (!intel_PLL_is_valid(dev, limit, |
891 | &clock)) | |
d4906093 | 892 | continue; |
1b894b59 CW |
893 | |
894 | this_err = abs(clock.dot - target); | |
d4906093 ML |
895 | if (this_err < err_most) { |
896 | *best_clock = clock; | |
897 | err_most = this_err; | |
898 | max_n = clock.n; | |
899 | found = true; | |
900 | } | |
901 | } | |
902 | } | |
903 | } | |
904 | } | |
2c07245f ZW |
905 | return found; |
906 | } | |
907 | ||
d5dd62bd ID |
908 | /* |
909 | * Check if the calculated PLL configuration is more optimal compared to the | |
910 | * best configuration and error found so far. Return the calculated error. | |
911 | */ | |
912 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
913 | const intel_clock_t *calculated_clock, | |
914 | const intel_clock_t *best_clock, | |
915 | unsigned int best_error_ppm, | |
916 | unsigned int *error_ppm) | |
917 | { | |
9ca3ba01 ID |
918 | /* |
919 | * For CHV ignore the error and consider only the P value. | |
920 | * Prefer a bigger P value based on HW requirements. | |
921 | */ | |
922 | if (IS_CHERRYVIEW(dev)) { | |
923 | *error_ppm = 0; | |
924 | ||
925 | return calculated_clock->p > best_clock->p; | |
926 | } | |
927 | ||
24be4e46 ID |
928 | if (WARN_ON_ONCE(!target_freq)) |
929 | return false; | |
930 | ||
d5dd62bd ID |
931 | *error_ppm = div_u64(1000000ULL * |
932 | abs(target_freq - calculated_clock->dot), | |
933 | target_freq); | |
934 | /* | |
935 | * Prefer a better P value over a better (smaller) error if the error | |
936 | * is small. Ensure this preference for future configurations too by | |
937 | * setting the error to 0. | |
938 | */ | |
939 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
940 | *error_ppm = 0; | |
941 | ||
942 | return true; | |
943 | } | |
944 | ||
945 | return *error_ppm + 10 < best_error_ppm; | |
946 | } | |
947 | ||
a0c4da24 | 948 | static bool |
a93e255f ACO |
949 | vlv_find_best_dpll(const intel_limit_t *limit, |
950 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
951 | int target, int refclk, intel_clock_t *match_clock, |
952 | intel_clock_t *best_clock) | |
a0c4da24 | 953 | { |
a93e255f | 954 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 955 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 956 | intel_clock_t clock; |
69e4f900 | 957 | unsigned int bestppm = 1000000; |
27e639bf VS |
958 | /* min update 19.2 MHz */ |
959 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 960 | bool found = false; |
a0c4da24 | 961 | |
6b4bf1c4 VS |
962 | target *= 5; /* fast clock */ |
963 | ||
964 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
965 | |
966 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 967 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 968 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 969 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 970 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 971 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 972 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 973 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 974 | unsigned int ppm; |
69e4f900 | 975 | |
6b4bf1c4 VS |
976 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
977 | refclk * clock.m1); | |
978 | ||
dccbea3b | 979 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 980 | |
f01b7962 VS |
981 | if (!intel_PLL_is_valid(dev, limit, |
982 | &clock)) | |
43b0ac53 VS |
983 | continue; |
984 | ||
d5dd62bd ID |
985 | if (!vlv_PLL_is_optimal(dev, target, |
986 | &clock, | |
987 | best_clock, | |
988 | bestppm, &ppm)) | |
989 | continue; | |
6b4bf1c4 | 990 | |
d5dd62bd ID |
991 | *best_clock = clock; |
992 | bestppm = ppm; | |
993 | found = true; | |
a0c4da24 JB |
994 | } |
995 | } | |
996 | } | |
997 | } | |
a0c4da24 | 998 | |
49e497ef | 999 | return found; |
a0c4da24 | 1000 | } |
a4fc5ed6 | 1001 | |
ef9348c8 | 1002 | static bool |
a93e255f ACO |
1003 | chv_find_best_dpll(const intel_limit_t *limit, |
1004 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1005 | int target, int refclk, intel_clock_t *match_clock, |
1006 | intel_clock_t *best_clock) | |
1007 | { | |
a93e255f | 1008 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1009 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1010 | unsigned int best_error_ppm; |
ef9348c8 CML |
1011 | intel_clock_t clock; |
1012 | uint64_t m2; | |
1013 | int found = false; | |
1014 | ||
1015 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1016 | best_error_ppm = 1000000; |
ef9348c8 CML |
1017 | |
1018 | /* | |
1019 | * Based on hardware doc, the n always set to 1, and m1 always | |
1020 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1021 | * revisit this because n may not 1 anymore. | |
1022 | */ | |
1023 | clock.n = 1, clock.m1 = 2; | |
1024 | target *= 5; /* fast clock */ | |
1025 | ||
1026 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1027 | for (clock.p2 = limit->p2.p2_fast; | |
1028 | clock.p2 >= limit->p2.p2_slow; | |
1029 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1030 | unsigned int error_ppm; |
ef9348c8 CML |
1031 | |
1032 | clock.p = clock.p1 * clock.p2; | |
1033 | ||
1034 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1035 | clock.n) << 22, refclk * clock.m1); | |
1036 | ||
1037 | if (m2 > INT_MAX/clock.m1) | |
1038 | continue; | |
1039 | ||
1040 | clock.m2 = m2; | |
1041 | ||
dccbea3b | 1042 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1043 | |
1044 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1045 | continue; | |
1046 | ||
9ca3ba01 ID |
1047 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1048 | best_error_ppm, &error_ppm)) | |
1049 | continue; | |
1050 | ||
1051 | *best_clock = clock; | |
1052 | best_error_ppm = error_ppm; | |
1053 | found = true; | |
ef9348c8 CML |
1054 | } |
1055 | } | |
1056 | ||
1057 | return found; | |
1058 | } | |
1059 | ||
5ab7b0b7 ID |
1060 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1061 | intel_clock_t *best_clock) | |
1062 | { | |
1063 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1064 | ||
1065 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1066 | target_clock, refclk, NULL, best_clock); | |
1067 | } | |
1068 | ||
20ddf665 VS |
1069 | bool intel_crtc_active(struct drm_crtc *crtc) |
1070 | { | |
1071 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1072 | ||
1073 | /* Be paranoid as we can arrive here with only partial | |
1074 | * state retrieved from the hardware during setup. | |
1075 | * | |
241bfc38 | 1076 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1077 | * as Haswell has gained clock readout/fastboot support. |
1078 | * | |
66e514c1 | 1079 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1080 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1081 | * |
1082 | * FIXME: The intel_crtc->active here should be switched to | |
1083 | * crtc->state->active once we have proper CRTC states wired up | |
1084 | * for atomic. | |
20ddf665 | 1085 | */ |
c3d1f436 | 1086 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1087 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1088 | } |
1089 | ||
a5c961d1 PZ |
1090 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1091 | enum pipe pipe) | |
1092 | { | |
1093 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1094 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1095 | ||
6e3c9717 | 1096 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1097 | } |
1098 | ||
fbf49ea2 VS |
1099 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1100 | { | |
1101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1102 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1103 | u32 line1, line2; |
1104 | u32 line_mask; | |
1105 | ||
1106 | if (IS_GEN2(dev)) | |
1107 | line_mask = DSL_LINEMASK_GEN2; | |
1108 | else | |
1109 | line_mask = DSL_LINEMASK_GEN3; | |
1110 | ||
1111 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1112 | msleep(5); |
fbf49ea2 VS |
1113 | line2 = I915_READ(reg) & line_mask; |
1114 | ||
1115 | return line1 == line2; | |
1116 | } | |
1117 | ||
ab7ad7f6 KP |
1118 | /* |
1119 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1120 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1121 | * |
1122 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1123 | * spinning on the vblank interrupt status bit, since we won't actually | |
1124 | * see an interrupt when the pipe is disabled. | |
1125 | * | |
ab7ad7f6 KP |
1126 | * On Gen4 and above: |
1127 | * wait for the pipe register state bit to turn off | |
1128 | * | |
1129 | * Otherwise: | |
1130 | * wait for the display line value to settle (it usually | |
1131 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1132 | * |
9d0498a2 | 1133 | */ |
575f7ab7 | 1134 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1135 | { |
575f7ab7 | 1136 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1137 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1138 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1139 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1140 | |
1141 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1142 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1143 | |
1144 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1145 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1146 | 100)) | |
284637d9 | 1147 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1148 | } else { |
ab7ad7f6 | 1149 | /* Wait for the display line to settle */ |
fbf49ea2 | 1150 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1151 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1152 | } |
79e53945 JB |
1153 | } |
1154 | ||
b24e7179 JB |
1155 | static const char *state_string(bool enabled) |
1156 | { | |
1157 | return enabled ? "on" : "off"; | |
1158 | } | |
1159 | ||
1160 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1161 | void assert_pll(struct drm_i915_private *dev_priv, |
1162 | enum pipe pipe, bool state) | |
b24e7179 | 1163 | { |
b24e7179 JB |
1164 | u32 val; |
1165 | bool cur_state; | |
1166 | ||
649636ef | 1167 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1168 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1169 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1170 | "PLL state assertion failure (expected %s, current %s)\n", |
1171 | state_string(state), state_string(cur_state)); | |
1172 | } | |
b24e7179 | 1173 | |
23538ef1 JN |
1174 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1175 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1176 | { | |
1177 | u32 val; | |
1178 | bool cur_state; | |
1179 | ||
a580516d | 1180 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1181 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1182 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1183 | |
1184 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1185 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1186 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1187 | state_string(state), state_string(cur_state)); | |
1188 | } | |
1189 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1190 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1191 | ||
55607e8a | 1192 | struct intel_shared_dpll * |
e2b78267 DV |
1193 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1194 | { | |
1195 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1196 | ||
6e3c9717 | 1197 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1198 | return NULL; |
1199 | ||
6e3c9717 | 1200 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1201 | } |
1202 | ||
040484af | 1203 | /* For ILK+ */ |
55607e8a DV |
1204 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1205 | struct intel_shared_dpll *pll, | |
1206 | bool state) | |
040484af | 1207 | { |
040484af | 1208 | bool cur_state; |
5358901f | 1209 | struct intel_dpll_hw_state hw_state; |
040484af | 1210 | |
92b27b08 | 1211 | if (WARN (!pll, |
46edb027 | 1212 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1213 | return; |
ee7b9f93 | 1214 | |
5358901f | 1215 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1216 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1217 | "%s assertion failure (expected %s, current %s)\n", |
1218 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1219 | } |
040484af JB |
1220 | |
1221 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1222 | enum pipe pipe, bool state) | |
1223 | { | |
040484af | 1224 | bool cur_state; |
ad80a810 PZ |
1225 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1226 | pipe); | |
040484af | 1227 | |
affa9354 PZ |
1228 | if (HAS_DDI(dev_priv->dev)) { |
1229 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1230 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1231 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1232 | } else { |
649636ef | 1233 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1234 | cur_state = !!(val & FDI_TX_ENABLE); |
1235 | } | |
e2c719b7 | 1236 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1237 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1238 | state_string(state), state_string(cur_state)); | |
1239 | } | |
1240 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1241 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1242 | ||
1243 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1244 | enum pipe pipe, bool state) | |
1245 | { | |
040484af JB |
1246 | u32 val; |
1247 | bool cur_state; | |
1248 | ||
649636ef | 1249 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1250 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1251 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1252 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1253 | state_string(state), state_string(cur_state)); | |
1254 | } | |
1255 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1256 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1257 | ||
1258 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1259 | enum pipe pipe) | |
1260 | { | |
040484af JB |
1261 | u32 val; |
1262 | ||
1263 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1264 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1265 | return; |
1266 | ||
bf507ef7 | 1267 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1268 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1269 | return; |
1270 | ||
649636ef | 1271 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1272 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1273 | } |
1274 | ||
55607e8a DV |
1275 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1276 | enum pipe pipe, bool state) | |
040484af | 1277 | { |
040484af | 1278 | u32 val; |
55607e8a | 1279 | bool cur_state; |
040484af | 1280 | |
649636ef | 1281 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1282 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1283 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1284 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1285 | state_string(state), state_string(cur_state)); | |
040484af JB |
1286 | } |
1287 | ||
b680c37a DV |
1288 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1289 | enum pipe pipe) | |
ea0760cf | 1290 | { |
bedd4dba | 1291 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1292 | i915_reg_t pp_reg; |
ea0760cf JB |
1293 | u32 val; |
1294 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1295 | bool locked = true; |
ea0760cf | 1296 | |
bedd4dba JN |
1297 | if (WARN_ON(HAS_DDI(dev))) |
1298 | return; | |
1299 | ||
1300 | if (HAS_PCH_SPLIT(dev)) { | |
1301 | u32 port_sel; | |
1302 | ||
ea0760cf | 1303 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1304 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1305 | ||
1306 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1307 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1308 | panel_pipe = PIPE_B; | |
1309 | /* XXX: else fix for eDP */ | |
666a4537 | 1310 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1311 | /* presumably write lock depends on pipe, not port select */ |
1312 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1313 | panel_pipe = pipe; | |
ea0760cf JB |
1314 | } else { |
1315 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1316 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1317 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1318 | } |
1319 | ||
1320 | val = I915_READ(pp_reg); | |
1321 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1322 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1323 | locked = false; |
1324 | ||
e2c719b7 | 1325 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1326 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1327 | pipe_name(pipe)); |
ea0760cf JB |
1328 | } |
1329 | ||
93ce0ba6 JN |
1330 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1331 | enum pipe pipe, bool state) | |
1332 | { | |
1333 | struct drm_device *dev = dev_priv->dev; | |
1334 | bool cur_state; | |
1335 | ||
d9d82081 | 1336 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1337 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1338 | else |
5efb3e28 | 1339 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1340 | |
e2c719b7 | 1341 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1342 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1343 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1344 | } | |
1345 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1346 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1347 | ||
b840d907 JB |
1348 | void assert_pipe(struct drm_i915_private *dev_priv, |
1349 | enum pipe pipe, bool state) | |
b24e7179 | 1350 | { |
63d7bbe9 | 1351 | bool cur_state; |
702e7a56 PZ |
1352 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1353 | pipe); | |
b24e7179 | 1354 | |
b6b5d049 VS |
1355 | /* if we need the pipe quirk it must be always on */ |
1356 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1357 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1358 | state = true; |
1359 | ||
f458ebbc | 1360 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1361 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1362 | cur_state = false; |
1363 | } else { | |
649636ef | 1364 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 PZ |
1365 | cur_state = !!(val & PIPECONF_ENABLE); |
1366 | } | |
1367 | ||
e2c719b7 | 1368 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1369 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1370 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1371 | } |
1372 | ||
931872fc CW |
1373 | static void assert_plane(struct drm_i915_private *dev_priv, |
1374 | enum plane plane, bool state) | |
b24e7179 | 1375 | { |
b24e7179 | 1376 | u32 val; |
931872fc | 1377 | bool cur_state; |
b24e7179 | 1378 | |
649636ef | 1379 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1380 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1381 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1382 | "plane %c assertion failure (expected %s, current %s)\n", |
1383 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1384 | } |
1385 | ||
931872fc CW |
1386 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1387 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1388 | ||
b24e7179 JB |
1389 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1390 | enum pipe pipe) | |
1391 | { | |
653e1026 | 1392 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1393 | int i; |
b24e7179 | 1394 | |
653e1026 VS |
1395 | /* Primary planes are fixed to pipes on gen4+ */ |
1396 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1397 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1398 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1399 | "plane %c assertion failure, should be disabled but not\n", |
1400 | plane_name(pipe)); | |
19ec1358 | 1401 | return; |
28c05794 | 1402 | } |
19ec1358 | 1403 | |
b24e7179 | 1404 | /* Need to check both planes against the pipe */ |
055e393f | 1405 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1406 | u32 val = I915_READ(DSPCNTR(i)); |
1407 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1408 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1409 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1410 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1411 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1412 | } |
1413 | } | |
1414 | ||
19332d7a JB |
1415 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1416 | enum pipe pipe) | |
1417 | { | |
20674eef | 1418 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1419 | int sprite; |
19332d7a | 1420 | |
7feb8b88 | 1421 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1422 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1423 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1424 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1425 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1426 | sprite, pipe_name(pipe)); | |
1427 | } | |
666a4537 | 1428 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1429 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1430 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1431 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1432 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1433 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1434 | } |
1435 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1436 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1437 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1438 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1439 | plane_name(pipe), pipe_name(pipe)); |
1440 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1441 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1442 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1443 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1444 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1445 | } |
1446 | } | |
1447 | ||
08c71e5e VS |
1448 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1449 | { | |
e2c719b7 | 1450 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1451 | drm_crtc_vblank_put(crtc); |
1452 | } | |
1453 | ||
89eff4be | 1454 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1455 | { |
1456 | u32 val; | |
1457 | bool enabled; | |
1458 | ||
e2c719b7 | 1459 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1460 | |
92f2584a JB |
1461 | val = I915_READ(PCH_DREF_CONTROL); |
1462 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1463 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1464 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1465 | } |
1466 | ||
ab9412ba DV |
1467 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1468 | enum pipe pipe) | |
92f2584a | 1469 | { |
92f2584a JB |
1470 | u32 val; |
1471 | bool enabled; | |
1472 | ||
649636ef | 1473 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1474 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1475 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1476 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1477 | pipe_name(pipe)); | |
92f2584a JB |
1478 | } |
1479 | ||
4e634389 KP |
1480 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1481 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1482 | { |
1483 | if ((val & DP_PORT_EN) == 0) | |
1484 | return false; | |
1485 | ||
1486 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1487 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1488 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1489 | return false; | |
44f37d1f CML |
1490 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1491 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1492 | return false; | |
f0575e92 KP |
1493 | } else { |
1494 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1495 | return false; | |
1496 | } | |
1497 | return true; | |
1498 | } | |
1499 | ||
1519b995 KP |
1500 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1501 | enum pipe pipe, u32 val) | |
1502 | { | |
dc0fa718 | 1503 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1504 | return false; |
1505 | ||
1506 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1507 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1508 | return false; |
44f37d1f CML |
1509 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1510 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1511 | return false; | |
1519b995 | 1512 | } else { |
dc0fa718 | 1513 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1514 | return false; |
1515 | } | |
1516 | return true; | |
1517 | } | |
1518 | ||
1519 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1520 | enum pipe pipe, u32 val) | |
1521 | { | |
1522 | if ((val & LVDS_PORT_EN) == 0) | |
1523 | return false; | |
1524 | ||
1525 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1526 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1527 | return false; | |
1528 | } else { | |
1529 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1530 | return false; | |
1531 | } | |
1532 | return true; | |
1533 | } | |
1534 | ||
1535 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1536 | enum pipe pipe, u32 val) | |
1537 | { | |
1538 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1539 | return false; | |
1540 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1541 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1542 | return false; | |
1543 | } else { | |
1544 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1545 | return false; | |
1546 | } | |
1547 | return true; | |
1548 | } | |
1549 | ||
291906f1 | 1550 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1551 | enum pipe pipe, i915_reg_t reg, |
1552 | u32 port_sel) | |
291906f1 | 1553 | { |
47a05eca | 1554 | u32 val = I915_READ(reg); |
e2c719b7 | 1555 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1556 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1557 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1558 | |
e2c719b7 | 1559 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1560 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1561 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1562 | } |
1563 | ||
1564 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1565 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1566 | { |
47a05eca | 1567 | u32 val = I915_READ(reg); |
e2c719b7 | 1568 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1569 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1570 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1571 | |
e2c719b7 | 1572 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1573 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1574 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1575 | } |
1576 | ||
1577 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1578 | enum pipe pipe) | |
1579 | { | |
291906f1 | 1580 | u32 val; |
291906f1 | 1581 | |
f0575e92 KP |
1582 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1583 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1584 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1585 | |
649636ef | 1586 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1587 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1588 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1589 | pipe_name(pipe)); |
291906f1 | 1590 | |
649636ef | 1591 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1592 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1593 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1594 | pipe_name(pipe)); |
291906f1 | 1595 | |
e2debe91 PZ |
1596 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1597 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1598 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1599 | } |
1600 | ||
d288f65f | 1601 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1602 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1603 | { |
426115cf DV |
1604 | struct drm_device *dev = crtc->base.dev; |
1605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1606 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1607 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1608 | |
426115cf | 1609 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1610 | |
87442f73 | 1611 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1612 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1613 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1614 | |
426115cf DV |
1615 | I915_WRITE(reg, dpll); |
1616 | POSTING_READ(reg); | |
1617 | udelay(150); | |
1618 | ||
1619 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1620 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1621 | ||
d288f65f | 1622 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1623 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1624 | |
1625 | /* We do this three times for luck */ | |
426115cf | 1626 | I915_WRITE(reg, dpll); |
87442f73 DV |
1627 | POSTING_READ(reg); |
1628 | udelay(150); /* wait for warmup */ | |
426115cf | 1629 | I915_WRITE(reg, dpll); |
87442f73 DV |
1630 | POSTING_READ(reg); |
1631 | udelay(150); /* wait for warmup */ | |
426115cf | 1632 | I915_WRITE(reg, dpll); |
87442f73 DV |
1633 | POSTING_READ(reg); |
1634 | udelay(150); /* wait for warmup */ | |
1635 | } | |
1636 | ||
d288f65f | 1637 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1638 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1639 | { |
1640 | struct drm_device *dev = crtc->base.dev; | |
1641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1642 | int pipe = crtc->pipe; | |
1643 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1644 | u32 tmp; |
1645 | ||
1646 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1647 | ||
a580516d | 1648 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1649 | |
1650 | /* Enable back the 10bit clock to display controller */ | |
1651 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1652 | tmp |= DPIO_DCLKP_EN; | |
1653 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1654 | ||
54433e91 VS |
1655 | mutex_unlock(&dev_priv->sb_lock); |
1656 | ||
9d556c99 CML |
1657 | /* |
1658 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1659 | */ | |
1660 | udelay(1); | |
1661 | ||
1662 | /* Enable PLL */ | |
d288f65f | 1663 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1664 | |
1665 | /* Check PLL is locked */ | |
a11b0703 | 1666 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1667 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1668 | ||
a11b0703 | 1669 | /* not sure when this should be written */ |
d288f65f | 1670 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1671 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1672 | } |
1673 | ||
1c4e0274 VS |
1674 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1675 | { | |
1676 | struct intel_crtc *crtc; | |
1677 | int count = 0; | |
1678 | ||
1679 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1680 | count += crtc->base.state->active && |
409ee761 | 1681 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1682 | |
1683 | return count; | |
1684 | } | |
1685 | ||
66e3d5c0 | 1686 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1687 | { |
66e3d5c0 DV |
1688 | struct drm_device *dev = crtc->base.dev; |
1689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1690 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1691 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1692 | |
66e3d5c0 | 1693 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1694 | |
63d7bbe9 | 1695 | /* No really, not for ILK+ */ |
3d13ef2e | 1696 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1697 | |
1698 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1699 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1700 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1701 | |
1c4e0274 VS |
1702 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1703 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1704 | /* | |
1705 | * It appears to be important that we don't enable this | |
1706 | * for the current pipe before otherwise configuring the | |
1707 | * PLL. No idea how this should be handled if multiple | |
1708 | * DVO outputs are enabled simultaneosly. | |
1709 | */ | |
1710 | dpll |= DPLL_DVO_2X_MODE; | |
1711 | I915_WRITE(DPLL(!crtc->pipe), | |
1712 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1713 | } | |
66e3d5c0 | 1714 | |
c2b63374 VS |
1715 | /* |
1716 | * Apparently we need to have VGA mode enabled prior to changing | |
1717 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1718 | * dividers, even though the register value does change. | |
1719 | */ | |
1720 | I915_WRITE(reg, 0); | |
1721 | ||
8e7a65aa VS |
1722 | I915_WRITE(reg, dpll); |
1723 | ||
66e3d5c0 DV |
1724 | /* Wait for the clocks to stabilize. */ |
1725 | POSTING_READ(reg); | |
1726 | udelay(150); | |
1727 | ||
1728 | if (INTEL_INFO(dev)->gen >= 4) { | |
1729 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1730 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1731 | } else { |
1732 | /* The pixel multiplier can only be updated once the | |
1733 | * DPLL is enabled and the clocks are stable. | |
1734 | * | |
1735 | * So write it again. | |
1736 | */ | |
1737 | I915_WRITE(reg, dpll); | |
1738 | } | |
63d7bbe9 JB |
1739 | |
1740 | /* We do this three times for luck */ | |
66e3d5c0 | 1741 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1742 | POSTING_READ(reg); |
1743 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1744 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1745 | POSTING_READ(reg); |
1746 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1747 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1748 | POSTING_READ(reg); |
1749 | udelay(150); /* wait for warmup */ | |
1750 | } | |
1751 | ||
1752 | /** | |
50b44a44 | 1753 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1754 | * @dev_priv: i915 private structure |
1755 | * @pipe: pipe PLL to disable | |
1756 | * | |
1757 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1758 | * | |
1759 | * Note! This is for pre-ILK only. | |
1760 | */ | |
1c4e0274 | 1761 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1762 | { |
1c4e0274 VS |
1763 | struct drm_device *dev = crtc->base.dev; |
1764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1765 | enum pipe pipe = crtc->pipe; | |
1766 | ||
1767 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1768 | if (IS_I830(dev) && | |
409ee761 | 1769 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1770 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1771 | I915_WRITE(DPLL(PIPE_B), |
1772 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1773 | I915_WRITE(DPLL(PIPE_A), | |
1774 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1775 | } | |
1776 | ||
b6b5d049 VS |
1777 | /* Don't disable pipe or pipe PLLs if needed */ |
1778 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1779 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1780 | return; |
1781 | ||
1782 | /* Make sure the pipe isn't still relying on us */ | |
1783 | assert_pipe_disabled(dev_priv, pipe); | |
1784 | ||
b8afb911 | 1785 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1786 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1787 | } |
1788 | ||
f6071166 JB |
1789 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1790 | { | |
b8afb911 | 1791 | u32 val; |
f6071166 JB |
1792 | |
1793 | /* Make sure the pipe isn't still relying on us */ | |
1794 | assert_pipe_disabled(dev_priv, pipe); | |
1795 | ||
e5cbfbfb ID |
1796 | /* |
1797 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1798 | * The latter is needed for VGA hotplug / manual detection. | |
1799 | */ | |
b8afb911 | 1800 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1801 | if (pipe == PIPE_B) |
60bfe44f | 1802 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1803 | I915_WRITE(DPLL(pipe), val); |
1804 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1805 | |
1806 | } | |
1807 | ||
1808 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1809 | { | |
d752048d | 1810 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1811 | u32 val; |
1812 | ||
a11b0703 VS |
1813 | /* Make sure the pipe isn't still relying on us */ |
1814 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1815 | |
a11b0703 | 1816 | /* Set PLL en = 0 */ |
60bfe44f VS |
1817 | val = DPLL_SSC_REF_CLK_CHV | |
1818 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1819 | if (pipe != PIPE_A) |
1820 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1821 | I915_WRITE(DPLL(pipe), val); | |
1822 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1823 | |
a580516d | 1824 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1825 | |
1826 | /* Disable 10bit clock to display controller */ | |
1827 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1828 | val &= ~DPIO_DCLKP_EN; | |
1829 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1830 | ||
a580516d | 1831 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1832 | } |
1833 | ||
e4607fcf | 1834 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1835 | struct intel_digital_port *dport, |
1836 | unsigned int expected_mask) | |
89b667f8 JB |
1837 | { |
1838 | u32 port_mask; | |
f0f59a00 | 1839 | i915_reg_t dpll_reg; |
89b667f8 | 1840 | |
e4607fcf CML |
1841 | switch (dport->port) { |
1842 | case PORT_B: | |
89b667f8 | 1843 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1844 | dpll_reg = DPLL(0); |
e4607fcf CML |
1845 | break; |
1846 | case PORT_C: | |
89b667f8 | 1847 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1848 | dpll_reg = DPLL(0); |
9b6de0a1 | 1849 | expected_mask <<= 4; |
00fc31b7 CML |
1850 | break; |
1851 | case PORT_D: | |
1852 | port_mask = DPLL_PORTD_READY_MASK; | |
1853 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1854 | break; |
1855 | default: | |
1856 | BUG(); | |
1857 | } | |
89b667f8 | 1858 | |
9b6de0a1 VS |
1859 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1860 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1861 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1862 | } |
1863 | ||
b14b1055 DV |
1864 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1865 | { | |
1866 | struct drm_device *dev = crtc->base.dev; | |
1867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1868 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1869 | ||
be19f0ff CW |
1870 | if (WARN_ON(pll == NULL)) |
1871 | return; | |
1872 | ||
3e369b76 | 1873 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1874 | if (pll->active == 0) { |
1875 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1876 | WARN_ON(pll->on); | |
1877 | assert_shared_dpll_disabled(dev_priv, pll); | |
1878 | ||
1879 | pll->mode_set(dev_priv, pll); | |
1880 | } | |
1881 | } | |
1882 | ||
92f2584a | 1883 | /** |
85b3894f | 1884 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1885 | * @dev_priv: i915 private structure |
1886 | * @pipe: pipe PLL to enable | |
1887 | * | |
1888 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1889 | * drives the transcoder clock. | |
1890 | */ | |
85b3894f | 1891 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1892 | { |
3d13ef2e DL |
1893 | struct drm_device *dev = crtc->base.dev; |
1894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1895 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1896 | |
87a875bb | 1897 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1898 | return; |
1899 | ||
3e369b76 | 1900 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1901 | return; |
ee7b9f93 | 1902 | |
74dd6928 | 1903 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1904 | pll->name, pll->active, pll->on, |
e2b78267 | 1905 | crtc->base.base.id); |
92f2584a | 1906 | |
cdbd2316 DV |
1907 | if (pll->active++) { |
1908 | WARN_ON(!pll->on); | |
e9d6944e | 1909 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1910 | return; |
1911 | } | |
f4a091c7 | 1912 | WARN_ON(pll->on); |
ee7b9f93 | 1913 | |
bd2bb1b9 PZ |
1914 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1915 | ||
46edb027 | 1916 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1917 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1918 | pll->on = true; |
92f2584a JB |
1919 | } |
1920 | ||
f6daaec2 | 1921 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1922 | { |
3d13ef2e DL |
1923 | struct drm_device *dev = crtc->base.dev; |
1924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1925 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1926 | |
92f2584a | 1927 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1928 | if (INTEL_INFO(dev)->gen < 5) |
1929 | return; | |
1930 | ||
eddfcbcd ML |
1931 | if (pll == NULL) |
1932 | return; | |
92f2584a | 1933 | |
eddfcbcd | 1934 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1935 | return; |
7a419866 | 1936 | |
46edb027 DV |
1937 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1938 | pll->name, pll->active, pll->on, | |
e2b78267 | 1939 | crtc->base.base.id); |
7a419866 | 1940 | |
48da64a8 | 1941 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1942 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1943 | return; |
1944 | } | |
1945 | ||
e9d6944e | 1946 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1947 | WARN_ON(!pll->on); |
cdbd2316 | 1948 | if (--pll->active) |
7a419866 | 1949 | return; |
ee7b9f93 | 1950 | |
46edb027 | 1951 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1952 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1953 | pll->on = false; |
bd2bb1b9 PZ |
1954 | |
1955 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1956 | } |
1957 | ||
b8a4f404 PZ |
1958 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1959 | enum pipe pipe) | |
040484af | 1960 | { |
23670b32 | 1961 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1962 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1963 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1964 | i915_reg_t reg; |
1965 | uint32_t val, pipeconf_val; | |
040484af JB |
1966 | |
1967 | /* PCH only available on ILK+ */ | |
55522f37 | 1968 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1969 | |
1970 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1971 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1972 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1973 | |
1974 | /* FDI must be feeding us bits for PCH ports */ | |
1975 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1976 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1977 | ||
23670b32 DV |
1978 | if (HAS_PCH_CPT(dev)) { |
1979 | /* Workaround: Set the timing override bit before enabling the | |
1980 | * pch transcoder. */ | |
1981 | reg = TRANS_CHICKEN2(pipe); | |
1982 | val = I915_READ(reg); | |
1983 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1984 | I915_WRITE(reg, val); | |
59c859d6 | 1985 | } |
23670b32 | 1986 | |
ab9412ba | 1987 | reg = PCH_TRANSCONF(pipe); |
040484af | 1988 | val = I915_READ(reg); |
5f7f726d | 1989 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1990 | |
1991 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1992 | /* | |
c5de7c6f VS |
1993 | * Make the BPC in transcoder be consistent with |
1994 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1995 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1996 | */ |
dfd07d72 | 1997 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1998 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1999 | val |= PIPECONF_8BPC; | |
2000 | else | |
2001 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2002 | } |
5f7f726d PZ |
2003 | |
2004 | val &= ~TRANS_INTERLACE_MASK; | |
2005 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2006 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2007 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2008 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2009 | else | |
2010 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2011 | else |
2012 | val |= TRANS_PROGRESSIVE; | |
2013 | ||
040484af JB |
2014 | I915_WRITE(reg, val | TRANS_ENABLE); |
2015 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2016 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2017 | } |
2018 | ||
8fb033d7 | 2019 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2020 | enum transcoder cpu_transcoder) |
040484af | 2021 | { |
8fb033d7 | 2022 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2023 | |
2024 | /* PCH only available on ILK+ */ | |
55522f37 | 2025 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2026 | |
8fb033d7 | 2027 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2028 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2029 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2030 | |
223a6fdf | 2031 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2032 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2033 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2034 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2035 | |
25f3ef11 | 2036 | val = TRANS_ENABLE; |
937bb610 | 2037 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2038 | |
9a76b1c6 PZ |
2039 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2040 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2041 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2042 | else |
2043 | val |= TRANS_PROGRESSIVE; | |
2044 | ||
ab9412ba DV |
2045 | I915_WRITE(LPT_TRANSCONF, val); |
2046 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2047 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2048 | } |
2049 | ||
b8a4f404 PZ |
2050 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2051 | enum pipe pipe) | |
040484af | 2052 | { |
23670b32 | 2053 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2054 | i915_reg_t reg; |
2055 | uint32_t val; | |
040484af JB |
2056 | |
2057 | /* FDI relies on the transcoder */ | |
2058 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2059 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2060 | ||
291906f1 JB |
2061 | /* Ports must be off as well */ |
2062 | assert_pch_ports_disabled(dev_priv, pipe); | |
2063 | ||
ab9412ba | 2064 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2065 | val = I915_READ(reg); |
2066 | val &= ~TRANS_ENABLE; | |
2067 | I915_WRITE(reg, val); | |
2068 | /* wait for PCH transcoder off, transcoder state */ | |
2069 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2070 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2071 | |
c465613b | 2072 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2073 | /* Workaround: Clear the timing override chicken bit again. */ |
2074 | reg = TRANS_CHICKEN2(pipe); | |
2075 | val = I915_READ(reg); | |
2076 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2077 | I915_WRITE(reg, val); | |
2078 | } | |
040484af JB |
2079 | } |
2080 | ||
ab4d966c | 2081 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2082 | { |
8fb033d7 PZ |
2083 | u32 val; |
2084 | ||
ab9412ba | 2085 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2086 | val &= ~TRANS_ENABLE; |
ab9412ba | 2087 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2088 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2089 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2090 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2091 | |
2092 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2093 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2094 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2095 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2096 | } |
2097 | ||
b24e7179 | 2098 | /** |
309cfea8 | 2099 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2100 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2101 | * |
0372264a | 2102 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2103 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2104 | */ |
e1fdc473 | 2105 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2106 | { |
0372264a PZ |
2107 | struct drm_device *dev = crtc->base.dev; |
2108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2109 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2110 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2111 | enum pipe pch_transcoder; |
f0f59a00 | 2112 | i915_reg_t reg; |
b24e7179 JB |
2113 | u32 val; |
2114 | ||
9e2ee2dd VS |
2115 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2116 | ||
58c6eaa2 | 2117 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2118 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2119 | assert_sprites_disabled(dev_priv, pipe); |
2120 | ||
681e5811 | 2121 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2122 | pch_transcoder = TRANSCODER_A; |
2123 | else | |
2124 | pch_transcoder = pipe; | |
2125 | ||
b24e7179 JB |
2126 | /* |
2127 | * A pipe without a PLL won't actually be able to drive bits from | |
2128 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2129 | * need the check. | |
2130 | */ | |
50360403 | 2131 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2132 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2133 | assert_dsi_pll_enabled(dev_priv); |
2134 | else | |
2135 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2136 | else { |
6e3c9717 | 2137 | if (crtc->config->has_pch_encoder) { |
040484af | 2138 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2139 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2140 | assert_fdi_tx_pll_enabled(dev_priv, |
2141 | (enum pipe) cpu_transcoder); | |
040484af JB |
2142 | } |
2143 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2144 | } | |
b24e7179 | 2145 | |
702e7a56 | 2146 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2147 | val = I915_READ(reg); |
7ad25d48 | 2148 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2149 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2150 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2151 | return; |
7ad25d48 | 2152 | } |
00d70b15 CW |
2153 | |
2154 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2155 | POSTING_READ(reg); |
b24e7179 JB |
2156 | } |
2157 | ||
2158 | /** | |
309cfea8 | 2159 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2160 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2161 | * |
575f7ab7 VS |
2162 | * Disable the pipe of @crtc, making sure that various hardware |
2163 | * specific requirements are met, if applicable, e.g. plane | |
2164 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2165 | * |
2166 | * Will wait until the pipe has shut down before returning. | |
2167 | */ | |
575f7ab7 | 2168 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2169 | { |
575f7ab7 | 2170 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2171 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2172 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2173 | i915_reg_t reg; |
b24e7179 JB |
2174 | u32 val; |
2175 | ||
9e2ee2dd VS |
2176 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2177 | ||
b24e7179 JB |
2178 | /* |
2179 | * Make sure planes won't keep trying to pump pixels to us, | |
2180 | * or we might hang the display. | |
2181 | */ | |
2182 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2183 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2184 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2185 | |
702e7a56 | 2186 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2187 | val = I915_READ(reg); |
00d70b15 CW |
2188 | if ((val & PIPECONF_ENABLE) == 0) |
2189 | return; | |
2190 | ||
67adc644 VS |
2191 | /* |
2192 | * Double wide has implications for planes | |
2193 | * so best keep it disabled when not needed. | |
2194 | */ | |
6e3c9717 | 2195 | if (crtc->config->double_wide) |
67adc644 VS |
2196 | val &= ~PIPECONF_DOUBLE_WIDE; |
2197 | ||
2198 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2199 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2200 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2201 | val &= ~PIPECONF_ENABLE; |
2202 | ||
2203 | I915_WRITE(reg, val); | |
2204 | if ((val & PIPECONF_ENABLE) == 0) | |
2205 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2206 | } |
2207 | ||
693db184 CW |
2208 | static bool need_vtd_wa(struct drm_device *dev) |
2209 | { | |
2210 | #ifdef CONFIG_INTEL_IOMMU | |
2211 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2212 | return true; | |
2213 | #endif | |
2214 | return false; | |
2215 | } | |
2216 | ||
50470bb0 | 2217 | unsigned int |
6761dd31 | 2218 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
fe47ea0c | 2219 | uint64_t fb_format_modifier, unsigned int plane) |
a57ce0b2 | 2220 | { |
6761dd31 TU |
2221 | unsigned int tile_height; |
2222 | uint32_t pixel_bytes; | |
a57ce0b2 | 2223 | |
b5d0e9bf DL |
2224 | switch (fb_format_modifier) { |
2225 | case DRM_FORMAT_MOD_NONE: | |
2226 | tile_height = 1; | |
2227 | break; | |
2228 | case I915_FORMAT_MOD_X_TILED: | |
2229 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2230 | break; | |
2231 | case I915_FORMAT_MOD_Y_TILED: | |
2232 | tile_height = 32; | |
2233 | break; | |
2234 | case I915_FORMAT_MOD_Yf_TILED: | |
fe47ea0c | 2235 | pixel_bytes = drm_format_plane_cpp(pixel_format, plane); |
6761dd31 | 2236 | switch (pixel_bytes) { |
b5d0e9bf | 2237 | default: |
6761dd31 | 2238 | case 1: |
b5d0e9bf DL |
2239 | tile_height = 64; |
2240 | break; | |
6761dd31 TU |
2241 | case 2: |
2242 | case 4: | |
b5d0e9bf DL |
2243 | tile_height = 32; |
2244 | break; | |
6761dd31 | 2245 | case 8: |
b5d0e9bf DL |
2246 | tile_height = 16; |
2247 | break; | |
6761dd31 | 2248 | case 16: |
b5d0e9bf DL |
2249 | WARN_ONCE(1, |
2250 | "128-bit pixels are not supported for display!"); | |
2251 | tile_height = 16; | |
2252 | break; | |
2253 | } | |
2254 | break; | |
2255 | default: | |
2256 | MISSING_CASE(fb_format_modifier); | |
2257 | tile_height = 1; | |
2258 | break; | |
2259 | } | |
091df6cb | 2260 | |
6761dd31 TU |
2261 | return tile_height; |
2262 | } | |
2263 | ||
2264 | unsigned int | |
2265 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2266 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2267 | { | |
2268 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
fe47ea0c | 2269 | fb_format_modifier, 0)); |
a57ce0b2 JB |
2270 | } |
2271 | ||
75c82a53 | 2272 | static void |
f64b98cd TU |
2273 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2274 | const struct drm_plane_state *plane_state) | |
2275 | { | |
a6d09186 | 2276 | struct intel_rotation_info *info = &view->params.rotation_info; |
84fe03f7 | 2277 | unsigned int tile_height, tile_pitch; |
50470bb0 | 2278 | |
f64b98cd TU |
2279 | *view = i915_ggtt_view_normal; |
2280 | ||
50470bb0 | 2281 | if (!plane_state) |
75c82a53 | 2282 | return; |
50470bb0 | 2283 | |
121920fa | 2284 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
75c82a53 | 2285 | return; |
50470bb0 | 2286 | |
9abc4648 | 2287 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2288 | |
2289 | info->height = fb->height; | |
2290 | info->pixel_format = fb->pixel_format; | |
2291 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2292 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2293 | info->fb_modifier = fb->modifier[0]; |
2294 | ||
84fe03f7 | 2295 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
fe47ea0c | 2296 | fb->modifier[0], 0); |
84fe03f7 TU |
2297 | tile_pitch = PAGE_SIZE / tile_height; |
2298 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2299 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); | |
2300 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; | |
2301 | ||
89e3e142 TU |
2302 | if (info->pixel_format == DRM_FORMAT_NV12) { |
2303 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, | |
2304 | fb->modifier[0], 1); | |
2305 | tile_pitch = PAGE_SIZE / tile_height; | |
2306 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2307 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, | |
2308 | tile_height); | |
2309 | info->size_uv = info->width_pages_uv * info->height_pages_uv * | |
2310 | PAGE_SIZE; | |
2311 | } | |
f64b98cd TU |
2312 | } |
2313 | ||
4e9a86b6 VS |
2314 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2315 | { | |
2316 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2317 | return 256 * 1024; | |
985b8bb4 | 2318 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2319 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2320 | return 128 * 1024; |
2321 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2322 | return 4 * 1024; | |
2323 | else | |
44c5905e | 2324 | return 0; |
4e9a86b6 VS |
2325 | } |
2326 | ||
127bd2ac | 2327 | int |
850c4cdc TU |
2328 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2329 | struct drm_framebuffer *fb, | |
7580d774 | 2330 | const struct drm_plane_state *plane_state) |
6b95a207 | 2331 | { |
850c4cdc | 2332 | struct drm_device *dev = fb->dev; |
ce453d81 | 2333 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2334 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2335 | struct i915_ggtt_view view; |
6b95a207 KH |
2336 | u32 alignment; |
2337 | int ret; | |
2338 | ||
ebcdd39e MR |
2339 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2340 | ||
7b911adc TU |
2341 | switch (fb->modifier[0]) { |
2342 | case DRM_FORMAT_MOD_NONE: | |
4e9a86b6 | 2343 | alignment = intel_linear_alignment(dev_priv); |
6b95a207 | 2344 | break; |
7b911adc | 2345 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2346 | if (INTEL_INFO(dev)->gen >= 9) |
2347 | alignment = 256 * 1024; | |
2348 | else { | |
2349 | /* pin() will align the object as required by fence */ | |
2350 | alignment = 0; | |
2351 | } | |
6b95a207 | 2352 | break; |
7b911adc | 2353 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2354 | case I915_FORMAT_MOD_Yf_TILED: |
2355 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2356 | "Y tiling bo slipped through, driver bug!\n")) | |
2357 | return -EINVAL; | |
2358 | alignment = 1 * 1024 * 1024; | |
2359 | break; | |
6b95a207 | 2360 | default: |
7b911adc TU |
2361 | MISSING_CASE(fb->modifier[0]); |
2362 | return -EINVAL; | |
6b95a207 KH |
2363 | } |
2364 | ||
75c82a53 | 2365 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2366 | |
693db184 CW |
2367 | /* Note that the w/a also requires 64 PTE of padding following the |
2368 | * bo. We currently fill all unused PTE with the shadow page and so | |
2369 | * we should always have valid PTE following the scanout preventing | |
2370 | * the VT-d warning. | |
2371 | */ | |
2372 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2373 | alignment = 256 * 1024; | |
2374 | ||
d6dd6843 PZ |
2375 | /* |
2376 | * Global gtt pte registers are special registers which actually forward | |
2377 | * writes to a chunk of system memory. Which means that there is no risk | |
2378 | * that the register values disappear as soon as we call | |
2379 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2380 | * pin/unpin/fence and not more. | |
2381 | */ | |
2382 | intel_runtime_pm_get(dev_priv); | |
2383 | ||
7580d774 ML |
2384 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2385 | &view); | |
48b956c5 | 2386 | if (ret) |
b26a6b35 | 2387 | goto err_pm; |
6b95a207 KH |
2388 | |
2389 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2390 | * fence, whereas 965+ only requires a fence if using | |
2391 | * framebuffer compression. For simplicity, we always install | |
2392 | * a fence as the cost is not that onerous. | |
2393 | */ | |
9807216f VK |
2394 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2395 | ret = i915_gem_object_get_fence(obj); | |
2396 | if (ret == -EDEADLK) { | |
2397 | /* | |
2398 | * -EDEADLK means there are no free fences | |
2399 | * no pending flips. | |
2400 | * | |
2401 | * This is propagated to atomic, but it uses | |
2402 | * -EDEADLK to force a locking recovery, so | |
2403 | * change the returned error to -EBUSY. | |
2404 | */ | |
2405 | ret = -EBUSY; | |
2406 | goto err_unpin; | |
2407 | } else if (ret) | |
2408 | goto err_unpin; | |
1690e1eb | 2409 | |
9807216f VK |
2410 | i915_gem_object_pin_fence(obj); |
2411 | } | |
6b95a207 | 2412 | |
d6dd6843 | 2413 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2414 | return 0; |
48b956c5 CW |
2415 | |
2416 | err_unpin: | |
f64b98cd | 2417 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2418 | err_pm: |
d6dd6843 | 2419 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2420 | return ret; |
6b95a207 KH |
2421 | } |
2422 | ||
82bc3b2d TU |
2423 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2424 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2425 | { |
82bc3b2d | 2426 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2427 | struct i915_ggtt_view view; |
82bc3b2d | 2428 | |
ebcdd39e MR |
2429 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2430 | ||
75c82a53 | 2431 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2432 | |
9807216f VK |
2433 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2434 | i915_gem_object_unpin_fence(obj); | |
2435 | ||
f64b98cd | 2436 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2437 | } |
2438 | ||
c2c75131 DV |
2439 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2440 | * is assumed to be a power-of-two. */ | |
4e9a86b6 VS |
2441 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
2442 | int *x, int *y, | |
bc752862 CW |
2443 | unsigned int tiling_mode, |
2444 | unsigned int cpp, | |
2445 | unsigned int pitch) | |
c2c75131 | 2446 | { |
bc752862 CW |
2447 | if (tiling_mode != I915_TILING_NONE) { |
2448 | unsigned int tile_rows, tiles; | |
c2c75131 | 2449 | |
bc752862 CW |
2450 | tile_rows = *y / 8; |
2451 | *y %= 8; | |
c2c75131 | 2452 | |
bc752862 CW |
2453 | tiles = *x / (512/cpp); |
2454 | *x %= 512/cpp; | |
2455 | ||
2456 | return tile_rows * pitch * 8 + tiles * 4096; | |
2457 | } else { | |
4e9a86b6 | 2458 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2459 | unsigned int offset; |
2460 | ||
2461 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2462 | *y = (offset & alignment) / pitch; |
2463 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2464 | return offset & ~alignment; | |
bc752862 | 2465 | } |
c2c75131 DV |
2466 | } |
2467 | ||
b35d63fa | 2468 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2469 | { |
2470 | switch (format) { | |
2471 | case DISPPLANE_8BPP: | |
2472 | return DRM_FORMAT_C8; | |
2473 | case DISPPLANE_BGRX555: | |
2474 | return DRM_FORMAT_XRGB1555; | |
2475 | case DISPPLANE_BGRX565: | |
2476 | return DRM_FORMAT_RGB565; | |
2477 | default: | |
2478 | case DISPPLANE_BGRX888: | |
2479 | return DRM_FORMAT_XRGB8888; | |
2480 | case DISPPLANE_RGBX888: | |
2481 | return DRM_FORMAT_XBGR8888; | |
2482 | case DISPPLANE_BGRX101010: | |
2483 | return DRM_FORMAT_XRGB2101010; | |
2484 | case DISPPLANE_RGBX101010: | |
2485 | return DRM_FORMAT_XBGR2101010; | |
2486 | } | |
2487 | } | |
2488 | ||
bc8d7dff DL |
2489 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2490 | { | |
2491 | switch (format) { | |
2492 | case PLANE_CTL_FORMAT_RGB_565: | |
2493 | return DRM_FORMAT_RGB565; | |
2494 | default: | |
2495 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2496 | if (rgb_order) { | |
2497 | if (alpha) | |
2498 | return DRM_FORMAT_ABGR8888; | |
2499 | else | |
2500 | return DRM_FORMAT_XBGR8888; | |
2501 | } else { | |
2502 | if (alpha) | |
2503 | return DRM_FORMAT_ARGB8888; | |
2504 | else | |
2505 | return DRM_FORMAT_XRGB8888; | |
2506 | } | |
2507 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2508 | if (rgb_order) | |
2509 | return DRM_FORMAT_XBGR2101010; | |
2510 | else | |
2511 | return DRM_FORMAT_XRGB2101010; | |
2512 | } | |
2513 | } | |
2514 | ||
5724dbd1 | 2515 | static bool |
f6936e29 DV |
2516 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2517 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2518 | { |
2519 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2520 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2521 | struct drm_i915_gem_object *obj = NULL; |
2522 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2523 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2524 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2525 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2526 | PAGE_SIZE); | |
2527 | ||
2528 | size_aligned -= base_aligned; | |
46f297fb | 2529 | |
ff2652ea CW |
2530 | if (plane_config->size == 0) |
2531 | return false; | |
2532 | ||
3badb49f PZ |
2533 | /* If the FB is too big, just don't use it since fbdev is not very |
2534 | * important and we should probably use that space with FBC or other | |
2535 | * features. */ | |
2536 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2537 | return false; | |
2538 | ||
f37b5c2b DV |
2539 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2540 | base_aligned, | |
2541 | base_aligned, | |
2542 | size_aligned); | |
46f297fb | 2543 | if (!obj) |
484b41dd | 2544 | return false; |
46f297fb | 2545 | |
49af449b DL |
2546 | obj->tiling_mode = plane_config->tiling; |
2547 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2548 | obj->stride = fb->pitches[0]; |
46f297fb | 2549 | |
6bf129df DL |
2550 | mode_cmd.pixel_format = fb->pixel_format; |
2551 | mode_cmd.width = fb->width; | |
2552 | mode_cmd.height = fb->height; | |
2553 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2554 | mode_cmd.modifier[0] = fb->modifier[0]; |
2555 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2556 | |
2557 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2558 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2559 | &mode_cmd, obj)) { |
46f297fb JB |
2560 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2561 | goto out_unref_obj; | |
2562 | } | |
46f297fb | 2563 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2564 | |
f6936e29 | 2565 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2566 | return true; |
46f297fb JB |
2567 | |
2568 | out_unref_obj: | |
2569 | drm_gem_object_unreference(&obj->base); | |
2570 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2571 | return false; |
2572 | } | |
2573 | ||
afd65eb4 MR |
2574 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2575 | static void | |
2576 | update_state_fb(struct drm_plane *plane) | |
2577 | { | |
2578 | if (plane->fb == plane->state->fb) | |
2579 | return; | |
2580 | ||
2581 | if (plane->state->fb) | |
2582 | drm_framebuffer_unreference(plane->state->fb); | |
2583 | plane->state->fb = plane->fb; | |
2584 | if (plane->state->fb) | |
2585 | drm_framebuffer_reference(plane->state->fb); | |
2586 | } | |
2587 | ||
5724dbd1 | 2588 | static void |
f6936e29 DV |
2589 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2590 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2591 | { |
2592 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2593 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2594 | struct drm_crtc *c; |
2595 | struct intel_crtc *i; | |
2ff8fde1 | 2596 | struct drm_i915_gem_object *obj; |
88595ac9 | 2597 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2598 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2599 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2600 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
88595ac9 | 2601 | struct drm_framebuffer *fb; |
484b41dd | 2602 | |
2d14030b | 2603 | if (!plane_config->fb) |
484b41dd JB |
2604 | return; |
2605 | ||
f6936e29 | 2606 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2607 | fb = &plane_config->fb->base; |
2608 | goto valid_fb; | |
f55548b5 | 2609 | } |
484b41dd | 2610 | |
2d14030b | 2611 | kfree(plane_config->fb); |
484b41dd JB |
2612 | |
2613 | /* | |
2614 | * Failed to alloc the obj, check to see if we should share | |
2615 | * an fb with another CRTC instead | |
2616 | */ | |
70e1e0ec | 2617 | for_each_crtc(dev, c) { |
484b41dd JB |
2618 | i = to_intel_crtc(c); |
2619 | ||
2620 | if (c == &intel_crtc->base) | |
2621 | continue; | |
2622 | ||
2ff8fde1 MR |
2623 | if (!i->active) |
2624 | continue; | |
2625 | ||
88595ac9 DV |
2626 | fb = c->primary->fb; |
2627 | if (!fb) | |
484b41dd JB |
2628 | continue; |
2629 | ||
88595ac9 | 2630 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2631 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2632 | drm_framebuffer_reference(fb); |
2633 | goto valid_fb; | |
484b41dd JB |
2634 | } |
2635 | } | |
88595ac9 | 2636 | |
200757f5 MR |
2637 | /* |
2638 | * We've failed to reconstruct the BIOS FB. Current display state | |
2639 | * indicates that the primary plane is visible, but has a NULL FB, | |
2640 | * which will lead to problems later if we don't fix it up. The | |
2641 | * simplest solution is to just disable the primary plane now and | |
2642 | * pretend the BIOS never had it enabled. | |
2643 | */ | |
2644 | to_intel_plane_state(plane_state)->visible = false; | |
2645 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2646 | intel_pre_disable_primary(&intel_crtc->base); | |
2647 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2648 | ||
88595ac9 DV |
2649 | return; |
2650 | ||
2651 | valid_fb: | |
f44e2659 VS |
2652 | plane_state->src_x = 0; |
2653 | plane_state->src_y = 0; | |
be5651f2 ML |
2654 | plane_state->src_w = fb->width << 16; |
2655 | plane_state->src_h = fb->height << 16; | |
2656 | ||
f44e2659 VS |
2657 | plane_state->crtc_x = 0; |
2658 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2659 | plane_state->crtc_w = fb->width; |
2660 | plane_state->crtc_h = fb->height; | |
2661 | ||
88595ac9 DV |
2662 | obj = intel_fb_obj(fb); |
2663 | if (obj->tiling_mode != I915_TILING_NONE) | |
2664 | dev_priv->preserve_bios_swizzle = true; | |
2665 | ||
be5651f2 ML |
2666 | drm_framebuffer_reference(fb); |
2667 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2668 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2669 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2670 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2671 | } |
2672 | ||
29b9bde6 DV |
2673 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2674 | struct drm_framebuffer *fb, | |
2675 | int x, int y) | |
81255565 JB |
2676 | { |
2677 | struct drm_device *dev = crtc->dev; | |
2678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2679 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2680 | struct drm_plane *primary = crtc->primary; |
2681 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2682 | struct drm_i915_gem_object *obj; |
81255565 | 2683 | int plane = intel_crtc->plane; |
e506a0c6 | 2684 | unsigned long linear_offset; |
81255565 | 2685 | u32 dspcntr; |
f0f59a00 | 2686 | i915_reg_t reg = DSPCNTR(plane); |
48404c1e | 2687 | int pixel_size; |
f45651ba | 2688 | |
b70709a6 | 2689 | if (!visible || !fb) { |
fdd508a6 VS |
2690 | I915_WRITE(reg, 0); |
2691 | if (INTEL_INFO(dev)->gen >= 4) | |
2692 | I915_WRITE(DSPSURF(plane), 0); | |
2693 | else | |
2694 | I915_WRITE(DSPADDR(plane), 0); | |
2695 | POSTING_READ(reg); | |
2696 | return; | |
2697 | } | |
2698 | ||
c9ba6fad VS |
2699 | obj = intel_fb_obj(fb); |
2700 | if (WARN_ON(obj == NULL)) | |
2701 | return; | |
2702 | ||
2703 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2704 | ||
f45651ba VS |
2705 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2706 | ||
fdd508a6 | 2707 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2708 | |
2709 | if (INTEL_INFO(dev)->gen < 4) { | |
2710 | if (intel_crtc->pipe == PIPE_B) | |
2711 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2712 | ||
2713 | /* pipesrc and dspsize control the size that is scaled from, | |
2714 | * which should always be the user's requested size. | |
2715 | */ | |
2716 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2717 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2718 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2719 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2720 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2721 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2722 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2723 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2724 | I915_WRITE(PRIMPOS(plane), 0); |
2725 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2726 | } |
81255565 | 2727 | |
57779d06 VS |
2728 | switch (fb->pixel_format) { |
2729 | case DRM_FORMAT_C8: | |
81255565 JB |
2730 | dspcntr |= DISPPLANE_8BPP; |
2731 | break; | |
57779d06 | 2732 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2733 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2734 | break; |
57779d06 VS |
2735 | case DRM_FORMAT_RGB565: |
2736 | dspcntr |= DISPPLANE_BGRX565; | |
2737 | break; | |
2738 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2739 | dspcntr |= DISPPLANE_BGRX888; |
2740 | break; | |
2741 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2742 | dspcntr |= DISPPLANE_RGBX888; |
2743 | break; | |
2744 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2745 | dspcntr |= DISPPLANE_BGRX101010; |
2746 | break; | |
2747 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2748 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2749 | break; |
2750 | default: | |
baba133a | 2751 | BUG(); |
81255565 | 2752 | } |
57779d06 | 2753 | |
f45651ba VS |
2754 | if (INTEL_INFO(dev)->gen >= 4 && |
2755 | obj->tiling_mode != I915_TILING_NONE) | |
2756 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2757 | |
de1aa629 VS |
2758 | if (IS_G4X(dev)) |
2759 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2760 | ||
b9897127 | 2761 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2762 | |
c2c75131 DV |
2763 | if (INTEL_INFO(dev)->gen >= 4) { |
2764 | intel_crtc->dspaddr_offset = | |
4e9a86b6 VS |
2765 | intel_gen4_compute_page_offset(dev_priv, |
2766 | &x, &y, obj->tiling_mode, | |
b9897127 | 2767 | pixel_size, |
bc752862 | 2768 | fb->pitches[0]); |
c2c75131 DV |
2769 | linear_offset -= intel_crtc->dspaddr_offset; |
2770 | } else { | |
e506a0c6 | 2771 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2772 | } |
e506a0c6 | 2773 | |
8e7d688b | 2774 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2775 | dspcntr |= DISPPLANE_ROTATE_180; |
2776 | ||
6e3c9717 ACO |
2777 | x += (intel_crtc->config->pipe_src_w - 1); |
2778 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2779 | |
2780 | /* Finding the last pixel of the last line of the display | |
2781 | data and adding to linear_offset*/ | |
2782 | linear_offset += | |
6e3c9717 ACO |
2783 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2784 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2785 | } |
2786 | ||
2db3366b PZ |
2787 | intel_crtc->adjusted_x = x; |
2788 | intel_crtc->adjusted_y = y; | |
2789 | ||
48404c1e SJ |
2790 | I915_WRITE(reg, dspcntr); |
2791 | ||
01f2c773 | 2792 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2793 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2794 | I915_WRITE(DSPSURF(plane), |
2795 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2796 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2797 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2798 | } else |
f343c5f6 | 2799 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2800 | POSTING_READ(reg); |
17638cd6 JB |
2801 | } |
2802 | ||
29b9bde6 DV |
2803 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2804 | struct drm_framebuffer *fb, | |
2805 | int x, int y) | |
17638cd6 JB |
2806 | { |
2807 | struct drm_device *dev = crtc->dev; | |
2808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2809 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2810 | struct drm_plane *primary = crtc->primary; |
2811 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2812 | struct drm_i915_gem_object *obj; |
17638cd6 | 2813 | int plane = intel_crtc->plane; |
e506a0c6 | 2814 | unsigned long linear_offset; |
17638cd6 | 2815 | u32 dspcntr; |
f0f59a00 | 2816 | i915_reg_t reg = DSPCNTR(plane); |
48404c1e | 2817 | int pixel_size; |
f45651ba | 2818 | |
b70709a6 | 2819 | if (!visible || !fb) { |
fdd508a6 VS |
2820 | I915_WRITE(reg, 0); |
2821 | I915_WRITE(DSPSURF(plane), 0); | |
2822 | POSTING_READ(reg); | |
2823 | return; | |
2824 | } | |
2825 | ||
c9ba6fad VS |
2826 | obj = intel_fb_obj(fb); |
2827 | if (WARN_ON(obj == NULL)) | |
2828 | return; | |
2829 | ||
2830 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2831 | ||
f45651ba VS |
2832 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2833 | ||
fdd508a6 | 2834 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2835 | |
2836 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2837 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2838 | |
57779d06 VS |
2839 | switch (fb->pixel_format) { |
2840 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2841 | dspcntr |= DISPPLANE_8BPP; |
2842 | break; | |
57779d06 VS |
2843 | case DRM_FORMAT_RGB565: |
2844 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2845 | break; |
57779d06 | 2846 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2847 | dspcntr |= DISPPLANE_BGRX888; |
2848 | break; | |
2849 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2850 | dspcntr |= DISPPLANE_RGBX888; |
2851 | break; | |
2852 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2853 | dspcntr |= DISPPLANE_BGRX101010; |
2854 | break; | |
2855 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2856 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2857 | break; |
2858 | default: | |
baba133a | 2859 | BUG(); |
17638cd6 JB |
2860 | } |
2861 | ||
2862 | if (obj->tiling_mode != I915_TILING_NONE) | |
2863 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2864 | |
f45651ba | 2865 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2866 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2867 | |
b9897127 | 2868 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2869 | intel_crtc->dspaddr_offset = |
4e9a86b6 VS |
2870 | intel_gen4_compute_page_offset(dev_priv, |
2871 | &x, &y, obj->tiling_mode, | |
b9897127 | 2872 | pixel_size, |
bc752862 | 2873 | fb->pitches[0]); |
c2c75131 | 2874 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2875 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2876 | dspcntr |= DISPPLANE_ROTATE_180; |
2877 | ||
2878 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2879 | x += (intel_crtc->config->pipe_src_w - 1); |
2880 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2881 | |
2882 | /* Finding the last pixel of the last line of the display | |
2883 | data and adding to linear_offset*/ | |
2884 | linear_offset += | |
6e3c9717 ACO |
2885 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2886 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2887 | } |
2888 | } | |
2889 | ||
2db3366b PZ |
2890 | intel_crtc->adjusted_x = x; |
2891 | intel_crtc->adjusted_y = y; | |
2892 | ||
48404c1e | 2893 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2894 | |
01f2c773 | 2895 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2896 | I915_WRITE(DSPSURF(plane), |
2897 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2898 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2899 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2900 | } else { | |
2901 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2902 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2903 | } | |
17638cd6 | 2904 | POSTING_READ(reg); |
17638cd6 JB |
2905 | } |
2906 | ||
b321803d DL |
2907 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2908 | uint32_t pixel_format) | |
2909 | { | |
2910 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2911 | ||
2912 | /* | |
2913 | * The stride is either expressed as a multiple of 64 bytes | |
2914 | * chunks for linear buffers or in number of tiles for tiled | |
2915 | * buffers. | |
2916 | */ | |
2917 | switch (fb_modifier) { | |
2918 | case DRM_FORMAT_MOD_NONE: | |
2919 | return 64; | |
2920 | case I915_FORMAT_MOD_X_TILED: | |
2921 | if (INTEL_INFO(dev)->gen == 2) | |
2922 | return 128; | |
2923 | return 512; | |
2924 | case I915_FORMAT_MOD_Y_TILED: | |
2925 | /* No need to check for old gens and Y tiling since this is | |
2926 | * about the display engine and those will be blocked before | |
2927 | * we get here. | |
2928 | */ | |
2929 | return 128; | |
2930 | case I915_FORMAT_MOD_Yf_TILED: | |
2931 | if (bits_per_pixel == 8) | |
2932 | return 64; | |
2933 | else | |
2934 | return 128; | |
2935 | default: | |
2936 | MISSING_CASE(fb_modifier); | |
2937 | return 64; | |
2938 | } | |
2939 | } | |
2940 | ||
44eb0cb9 MK |
2941 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2942 | struct drm_i915_gem_object *obj, | |
2943 | unsigned int plane) | |
121920fa | 2944 | { |
ce7f1728 | 2945 | struct i915_ggtt_view view; |
dedf278c | 2946 | struct i915_vma *vma; |
44eb0cb9 | 2947 | u64 offset; |
121920fa | 2948 | |
ce7f1728 DV |
2949 | intel_fill_fb_ggtt_view(&view, intel_plane->base.fb, |
2950 | intel_plane->base.state); | |
121920fa | 2951 | |
ce7f1728 | 2952 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2953 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2954 | view.type)) |
dedf278c TU |
2955 | return -1; |
2956 | ||
44eb0cb9 | 2957 | offset = vma->node.start; |
dedf278c TU |
2958 | |
2959 | if (plane == 1) { | |
a6d09186 | 2960 | offset += vma->ggtt_view.params.rotation_info.uv_start_page * |
dedf278c TU |
2961 | PAGE_SIZE; |
2962 | } | |
2963 | ||
44eb0cb9 MK |
2964 | WARN_ON(upper_32_bits(offset)); |
2965 | ||
2966 | return lower_32_bits(offset); | |
121920fa TU |
2967 | } |
2968 | ||
e435d6e5 ML |
2969 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2970 | { | |
2971 | struct drm_device *dev = intel_crtc->base.dev; | |
2972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2973 | ||
2974 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2975 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2976 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2977 | } |
2978 | ||
a1b2278e CK |
2979 | /* |
2980 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2981 | */ | |
0583236e | 2982 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2983 | { |
a1b2278e CK |
2984 | struct intel_crtc_scaler_state *scaler_state; |
2985 | int i; | |
2986 | ||
a1b2278e CK |
2987 | scaler_state = &intel_crtc->config->scaler_state; |
2988 | ||
2989 | /* loop through and disable scalers that aren't in use */ | |
2990 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2991 | if (!scaler_state->scalers[i].in_use) |
2992 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2993 | } |
2994 | } | |
2995 | ||
6156a456 | 2996 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2997 | { |
6156a456 | 2998 | switch (pixel_format) { |
d161cf7a | 2999 | case DRM_FORMAT_C8: |
c34ce3d1 | 3000 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3001 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3002 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3003 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3004 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3005 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3006 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3007 | /* |
3008 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3009 | * to be already pre-multiplied. We need to add a knob (or a different | |
3010 | * DRM_FORMAT) for user-space to configure that. | |
3011 | */ | |
f75fb42a | 3012 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3013 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3014 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3015 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3016 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3017 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3018 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3019 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3020 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3021 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3022 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3023 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3024 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3025 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3026 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3027 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3028 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3029 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3030 | default: |
4249eeef | 3031 | MISSING_CASE(pixel_format); |
70d21f0e | 3032 | } |
8cfcba41 | 3033 | |
c34ce3d1 | 3034 | return 0; |
6156a456 | 3035 | } |
70d21f0e | 3036 | |
6156a456 CK |
3037 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3038 | { | |
6156a456 | 3039 | switch (fb_modifier) { |
30af77c4 | 3040 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3041 | break; |
30af77c4 | 3042 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3043 | return PLANE_CTL_TILED_X; |
b321803d | 3044 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3045 | return PLANE_CTL_TILED_Y; |
b321803d | 3046 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3047 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3048 | default: |
6156a456 | 3049 | MISSING_CASE(fb_modifier); |
70d21f0e | 3050 | } |
8cfcba41 | 3051 | |
c34ce3d1 | 3052 | return 0; |
6156a456 | 3053 | } |
70d21f0e | 3054 | |
6156a456 CK |
3055 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3056 | { | |
3b7a5119 | 3057 | switch (rotation) { |
6156a456 CK |
3058 | case BIT(DRM_ROTATE_0): |
3059 | break; | |
1e8df167 SJ |
3060 | /* |
3061 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3062 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3063 | */ | |
3b7a5119 | 3064 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3065 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3066 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3067 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3068 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3069 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3070 | default: |
3071 | MISSING_CASE(rotation); | |
3072 | } | |
3073 | ||
c34ce3d1 | 3074 | return 0; |
6156a456 CK |
3075 | } |
3076 | ||
3077 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3078 | struct drm_framebuffer *fb, | |
3079 | int x, int y) | |
3080 | { | |
3081 | struct drm_device *dev = crtc->dev; | |
3082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3083 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3084 | struct drm_plane *plane = crtc->primary; |
3085 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3086 | struct drm_i915_gem_object *obj; |
3087 | int pipe = intel_crtc->pipe; | |
3088 | u32 plane_ctl, stride_div, stride; | |
3089 | u32 tile_height, plane_offset, plane_size; | |
3090 | unsigned int rotation; | |
3091 | int x_offset, y_offset; | |
44eb0cb9 | 3092 | u32 surf_addr; |
6156a456 CK |
3093 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3094 | struct intel_plane_state *plane_state; | |
3095 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3096 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3097 | int scaler_id = -1; | |
3098 | ||
6156a456 CK |
3099 | plane_state = to_intel_plane_state(plane->state); |
3100 | ||
b70709a6 | 3101 | if (!visible || !fb) { |
6156a456 CK |
3102 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3103 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3104 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3105 | return; | |
3b7a5119 | 3106 | } |
70d21f0e | 3107 | |
6156a456 CK |
3108 | plane_ctl = PLANE_CTL_ENABLE | |
3109 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3110 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3111 | ||
3112 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3113 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3114 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3115 | ||
3116 | rotation = plane->state->rotation; | |
3117 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3118 | ||
b321803d DL |
3119 | obj = intel_fb_obj(fb); |
3120 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3121 | fb->pixel_format); | |
dedf278c | 3122 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3123 | |
a42e5a23 PZ |
3124 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3125 | ||
3126 | scaler_id = plane_state->scaler_id; | |
3127 | src_x = plane_state->src.x1 >> 16; | |
3128 | src_y = plane_state->src.y1 >> 16; | |
3129 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3130 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3131 | dst_x = plane_state->dst.x1; | |
3132 | dst_y = plane_state->dst.y1; | |
3133 | dst_w = drm_rect_width(&plane_state->dst); | |
3134 | dst_h = drm_rect_height(&plane_state->dst); | |
3135 | ||
3136 | WARN_ON(x != src_x || y != src_y); | |
6156a456 | 3137 | |
3b7a5119 SJ |
3138 | if (intel_rotation_90_or_270(rotation)) { |
3139 | /* stride = Surface height in tiles */ | |
2614f17d | 3140 | tile_height = intel_tile_height(dev, fb->pixel_format, |
fe47ea0c | 3141 | fb->modifier[0], 0); |
3b7a5119 | 3142 | stride = DIV_ROUND_UP(fb->height, tile_height); |
6156a456 | 3143 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3144 | y_offset = x; |
6156a456 | 3145 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3146 | } else { |
3147 | stride = fb->pitches[0] / stride_div; | |
3148 | x_offset = x; | |
3149 | y_offset = y; | |
6156a456 | 3150 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3151 | } |
3152 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3153 | |
2db3366b PZ |
3154 | intel_crtc->adjusted_x = x_offset; |
3155 | intel_crtc->adjusted_y = y_offset; | |
3156 | ||
70d21f0e | 3157 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3158 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3159 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3160 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3161 | |
3162 | if (scaler_id >= 0) { | |
3163 | uint32_t ps_ctrl = 0; | |
3164 | ||
3165 | WARN_ON(!dst_w || !dst_h); | |
3166 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3167 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3168 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3169 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3170 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3171 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3172 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3173 | } else { | |
3174 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3175 | } | |
3176 | ||
121920fa | 3177 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3178 | |
3179 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3180 | } | |
3181 | ||
17638cd6 JB |
3182 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3183 | static int | |
3184 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3185 | int x, int y, enum mode_set_atomic state) | |
3186 | { | |
3187 | struct drm_device *dev = crtc->dev; | |
3188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3189 | |
0e631adc PZ |
3190 | if (dev_priv->fbc.deactivate) |
3191 | dev_priv->fbc.deactivate(dev_priv); | |
81255565 | 3192 | |
29b9bde6 DV |
3193 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3194 | ||
3195 | return 0; | |
81255565 JB |
3196 | } |
3197 | ||
7514747d | 3198 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3199 | { |
96a02917 VS |
3200 | struct drm_crtc *crtc; |
3201 | ||
70e1e0ec | 3202 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3203 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3204 | enum plane plane = intel_crtc->plane; | |
3205 | ||
3206 | intel_prepare_page_flip(dev, plane); | |
3207 | intel_finish_page_flip_plane(dev, plane); | |
3208 | } | |
7514747d VS |
3209 | } |
3210 | ||
3211 | static void intel_update_primary_planes(struct drm_device *dev) | |
3212 | { | |
7514747d | 3213 | struct drm_crtc *crtc; |
96a02917 | 3214 | |
70e1e0ec | 3215 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3216 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3217 | struct intel_plane_state *plane_state; | |
96a02917 | 3218 | |
11c22da6 | 3219 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3220 | plane_state = to_intel_plane_state(plane->base.state); |
3221 | ||
f029ee82 | 3222 | if (crtc->state->active && plane_state->base.fb) |
11c22da6 ML |
3223 | plane->commit_plane(&plane->base, plane_state); |
3224 | ||
3225 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3226 | } |
3227 | } | |
3228 | ||
7514747d VS |
3229 | void intel_prepare_reset(struct drm_device *dev) |
3230 | { | |
3231 | /* no reset support for gen2 */ | |
3232 | if (IS_GEN2(dev)) | |
3233 | return; | |
3234 | ||
3235 | /* reset doesn't touch the display */ | |
3236 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3237 | return; | |
3238 | ||
3239 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3240 | /* |
3241 | * Disabling the crtcs gracefully seems nicer. Also the | |
3242 | * g33 docs say we should at least disable all the planes. | |
3243 | */ | |
6b72d486 | 3244 | intel_display_suspend(dev); |
7514747d VS |
3245 | } |
3246 | ||
3247 | void intel_finish_reset(struct drm_device *dev) | |
3248 | { | |
3249 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3250 | ||
3251 | /* | |
3252 | * Flips in the rings will be nuked by the reset, | |
3253 | * so complete all pending flips so that user space | |
3254 | * will get its events and not get stuck. | |
3255 | */ | |
3256 | intel_complete_page_flips(dev); | |
3257 | ||
3258 | /* no reset support for gen2 */ | |
3259 | if (IS_GEN2(dev)) | |
3260 | return; | |
3261 | ||
3262 | /* reset doesn't touch the display */ | |
3263 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3264 | /* | |
3265 | * Flips in the rings have been nuked by the reset, | |
3266 | * so update the base address of all primary | |
3267 | * planes to the the last fb to make sure we're | |
3268 | * showing the correct fb after a reset. | |
11c22da6 ML |
3269 | * |
3270 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3271 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3272 | */ |
3273 | intel_update_primary_planes(dev); | |
3274 | return; | |
3275 | } | |
3276 | ||
3277 | /* | |
3278 | * The display has been reset as well, | |
3279 | * so need a full re-initialization. | |
3280 | */ | |
3281 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3282 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3283 | ||
3284 | intel_modeset_init_hw(dev); | |
3285 | ||
3286 | spin_lock_irq(&dev_priv->irq_lock); | |
3287 | if (dev_priv->display.hpd_irq_setup) | |
3288 | dev_priv->display.hpd_irq_setup(dev); | |
3289 | spin_unlock_irq(&dev_priv->irq_lock); | |
3290 | ||
043e9bda | 3291 | intel_display_resume(dev); |
7514747d VS |
3292 | |
3293 | intel_hpd_init(dev_priv); | |
3294 | ||
3295 | drm_modeset_unlock_all(dev); | |
3296 | } | |
3297 | ||
7d5e3799 CW |
3298 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3299 | { | |
3300 | struct drm_device *dev = crtc->dev; | |
3301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3302 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3303 | bool pending; |
3304 | ||
3305 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3306 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3307 | return false; | |
3308 | ||
5e2d7afc | 3309 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3310 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3311 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3312 | |
3313 | return pending; | |
3314 | } | |
3315 | ||
bfd16b2a ML |
3316 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3317 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3318 | { |
3319 | struct drm_device *dev = crtc->base.dev; | |
3320 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3321 | struct intel_crtc_state *pipe_config = |
3322 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3323 | |
bfd16b2a ML |
3324 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3325 | crtc->base.mode = crtc->base.state->mode; | |
3326 | ||
3327 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3328 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3329 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3330 | |
44522d85 ML |
3331 | if (HAS_DDI(dev)) |
3332 | intel_set_pipe_csc(&crtc->base); | |
3333 | ||
e30e8f75 GP |
3334 | /* |
3335 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3336 | * that in compute_mode_changes we check the native mode (not the pfit | |
3337 | * mode) to see if we can flip rather than do a full mode set. In the | |
3338 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3339 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3340 | * sized surface. | |
e30e8f75 GP |
3341 | */ |
3342 | ||
e30e8f75 | 3343 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3344 | ((pipe_config->pipe_src_w - 1) << 16) | |
3345 | (pipe_config->pipe_src_h - 1)); | |
3346 | ||
3347 | /* on skylake this is done by detaching scalers */ | |
3348 | if (INTEL_INFO(dev)->gen >= 9) { | |
3349 | skl_detach_scalers(crtc); | |
3350 | ||
3351 | if (pipe_config->pch_pfit.enabled) | |
3352 | skylake_pfit_enable(crtc); | |
3353 | } else if (HAS_PCH_SPLIT(dev)) { | |
3354 | if (pipe_config->pch_pfit.enabled) | |
3355 | ironlake_pfit_enable(crtc); | |
3356 | else if (old_crtc_state->pch_pfit.enabled) | |
3357 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3358 | } |
e30e8f75 GP |
3359 | } |
3360 | ||
5e84e1a4 ZW |
3361 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3362 | { | |
3363 | struct drm_device *dev = crtc->dev; | |
3364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3365 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3366 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3367 | i915_reg_t reg; |
3368 | u32 temp; | |
5e84e1a4 ZW |
3369 | |
3370 | /* enable normal train */ | |
3371 | reg = FDI_TX_CTL(pipe); | |
3372 | temp = I915_READ(reg); | |
61e499bf | 3373 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3374 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3375 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3376 | } else { |
3377 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3378 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3379 | } |
5e84e1a4 ZW |
3380 | I915_WRITE(reg, temp); |
3381 | ||
3382 | reg = FDI_RX_CTL(pipe); | |
3383 | temp = I915_READ(reg); | |
3384 | if (HAS_PCH_CPT(dev)) { | |
3385 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3386 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3387 | } else { | |
3388 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3389 | temp |= FDI_LINK_TRAIN_NONE; | |
3390 | } | |
3391 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3392 | ||
3393 | /* wait one idle pattern time */ | |
3394 | POSTING_READ(reg); | |
3395 | udelay(1000); | |
357555c0 JB |
3396 | |
3397 | /* IVB wants error correction enabled */ | |
3398 | if (IS_IVYBRIDGE(dev)) | |
3399 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3400 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3401 | } |
3402 | ||
8db9d77b ZW |
3403 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3404 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3405 | { | |
3406 | struct drm_device *dev = crtc->dev; | |
3407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3408 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3409 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3410 | i915_reg_t reg; |
3411 | u32 temp, tries; | |
8db9d77b | 3412 | |
1c8562f6 | 3413 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3414 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3415 | |
e1a44743 AJ |
3416 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3417 | for train result */ | |
5eddb70b CW |
3418 | reg = FDI_RX_IMR(pipe); |
3419 | temp = I915_READ(reg); | |
e1a44743 AJ |
3420 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3421 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3422 | I915_WRITE(reg, temp); |
3423 | I915_READ(reg); | |
e1a44743 AJ |
3424 | udelay(150); |
3425 | ||
8db9d77b | 3426 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3427 | reg = FDI_TX_CTL(pipe); |
3428 | temp = I915_READ(reg); | |
627eb5a3 | 3429 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3430 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3431 | temp &= ~FDI_LINK_TRAIN_NONE; |
3432 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3433 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3434 | |
5eddb70b CW |
3435 | reg = FDI_RX_CTL(pipe); |
3436 | temp = I915_READ(reg); | |
8db9d77b ZW |
3437 | temp &= ~FDI_LINK_TRAIN_NONE; |
3438 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3439 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3440 | ||
3441 | POSTING_READ(reg); | |
8db9d77b ZW |
3442 | udelay(150); |
3443 | ||
5b2adf89 | 3444 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3445 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3446 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3447 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3448 | |
5eddb70b | 3449 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3450 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3451 | temp = I915_READ(reg); |
8db9d77b ZW |
3452 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3453 | ||
3454 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3455 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3456 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3457 | break; |
3458 | } | |
8db9d77b | 3459 | } |
e1a44743 | 3460 | if (tries == 5) |
5eddb70b | 3461 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3462 | |
3463 | /* Train 2 */ | |
5eddb70b CW |
3464 | reg = FDI_TX_CTL(pipe); |
3465 | temp = I915_READ(reg); | |
8db9d77b ZW |
3466 | temp &= ~FDI_LINK_TRAIN_NONE; |
3467 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3468 | I915_WRITE(reg, temp); |
8db9d77b | 3469 | |
5eddb70b CW |
3470 | reg = FDI_RX_CTL(pipe); |
3471 | temp = I915_READ(reg); | |
8db9d77b ZW |
3472 | temp &= ~FDI_LINK_TRAIN_NONE; |
3473 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3474 | I915_WRITE(reg, temp); |
8db9d77b | 3475 | |
5eddb70b CW |
3476 | POSTING_READ(reg); |
3477 | udelay(150); | |
8db9d77b | 3478 | |
5eddb70b | 3479 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3480 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3481 | temp = I915_READ(reg); |
8db9d77b ZW |
3482 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3483 | ||
3484 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3485 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3486 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3487 | break; | |
3488 | } | |
8db9d77b | 3489 | } |
e1a44743 | 3490 | if (tries == 5) |
5eddb70b | 3491 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3492 | |
3493 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3494 | |
8db9d77b ZW |
3495 | } |
3496 | ||
0206e353 | 3497 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3498 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3499 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3500 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3501 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3502 | }; | |
3503 | ||
3504 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3505 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3506 | { | |
3507 | struct drm_device *dev = crtc->dev; | |
3508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3509 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3510 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3511 | i915_reg_t reg; |
3512 | u32 temp, i, retry; | |
8db9d77b | 3513 | |
e1a44743 AJ |
3514 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3515 | for train result */ | |
5eddb70b CW |
3516 | reg = FDI_RX_IMR(pipe); |
3517 | temp = I915_READ(reg); | |
e1a44743 AJ |
3518 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3519 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3520 | I915_WRITE(reg, temp); |
3521 | ||
3522 | POSTING_READ(reg); | |
e1a44743 AJ |
3523 | udelay(150); |
3524 | ||
8db9d77b | 3525 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3526 | reg = FDI_TX_CTL(pipe); |
3527 | temp = I915_READ(reg); | |
627eb5a3 | 3528 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3529 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3530 | temp &= ~FDI_LINK_TRAIN_NONE; |
3531 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3532 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3533 | /* SNB-B */ | |
3534 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3535 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3536 | |
d74cf324 DV |
3537 | I915_WRITE(FDI_RX_MISC(pipe), |
3538 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3539 | ||
5eddb70b CW |
3540 | reg = FDI_RX_CTL(pipe); |
3541 | temp = I915_READ(reg); | |
8db9d77b ZW |
3542 | if (HAS_PCH_CPT(dev)) { |
3543 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3544 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3545 | } else { | |
3546 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3547 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3548 | } | |
5eddb70b CW |
3549 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3550 | ||
3551 | POSTING_READ(reg); | |
8db9d77b ZW |
3552 | udelay(150); |
3553 | ||
0206e353 | 3554 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3555 | reg = FDI_TX_CTL(pipe); |
3556 | temp = I915_READ(reg); | |
8db9d77b ZW |
3557 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3558 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3559 | I915_WRITE(reg, temp); |
3560 | ||
3561 | POSTING_READ(reg); | |
8db9d77b ZW |
3562 | udelay(500); |
3563 | ||
fa37d39e SP |
3564 | for (retry = 0; retry < 5; retry++) { |
3565 | reg = FDI_RX_IIR(pipe); | |
3566 | temp = I915_READ(reg); | |
3567 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3568 | if (temp & FDI_RX_BIT_LOCK) { | |
3569 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3570 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3571 | break; | |
3572 | } | |
3573 | udelay(50); | |
8db9d77b | 3574 | } |
fa37d39e SP |
3575 | if (retry < 5) |
3576 | break; | |
8db9d77b ZW |
3577 | } |
3578 | if (i == 4) | |
5eddb70b | 3579 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3580 | |
3581 | /* Train 2 */ | |
5eddb70b CW |
3582 | reg = FDI_TX_CTL(pipe); |
3583 | temp = I915_READ(reg); | |
8db9d77b ZW |
3584 | temp &= ~FDI_LINK_TRAIN_NONE; |
3585 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3586 | if (IS_GEN6(dev)) { | |
3587 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3588 | /* SNB-B */ | |
3589 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3590 | } | |
5eddb70b | 3591 | I915_WRITE(reg, temp); |
8db9d77b | 3592 | |
5eddb70b CW |
3593 | reg = FDI_RX_CTL(pipe); |
3594 | temp = I915_READ(reg); | |
8db9d77b ZW |
3595 | if (HAS_PCH_CPT(dev)) { |
3596 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3597 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3598 | } else { | |
3599 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3600 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3601 | } | |
5eddb70b CW |
3602 | I915_WRITE(reg, temp); |
3603 | ||
3604 | POSTING_READ(reg); | |
8db9d77b ZW |
3605 | udelay(150); |
3606 | ||
0206e353 | 3607 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3608 | reg = FDI_TX_CTL(pipe); |
3609 | temp = I915_READ(reg); | |
8db9d77b ZW |
3610 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3611 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3612 | I915_WRITE(reg, temp); |
3613 | ||
3614 | POSTING_READ(reg); | |
8db9d77b ZW |
3615 | udelay(500); |
3616 | ||
fa37d39e SP |
3617 | for (retry = 0; retry < 5; retry++) { |
3618 | reg = FDI_RX_IIR(pipe); | |
3619 | temp = I915_READ(reg); | |
3620 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3621 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3622 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3623 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3624 | break; | |
3625 | } | |
3626 | udelay(50); | |
8db9d77b | 3627 | } |
fa37d39e SP |
3628 | if (retry < 5) |
3629 | break; | |
8db9d77b ZW |
3630 | } |
3631 | if (i == 4) | |
5eddb70b | 3632 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3633 | |
3634 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3635 | } | |
3636 | ||
357555c0 JB |
3637 | /* Manual link training for Ivy Bridge A0 parts */ |
3638 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3639 | { | |
3640 | struct drm_device *dev = crtc->dev; | |
3641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3642 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3643 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3644 | i915_reg_t reg; |
3645 | u32 temp, i, j; | |
357555c0 JB |
3646 | |
3647 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3648 | for train result */ | |
3649 | reg = FDI_RX_IMR(pipe); | |
3650 | temp = I915_READ(reg); | |
3651 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3652 | temp &= ~FDI_RX_BIT_LOCK; | |
3653 | I915_WRITE(reg, temp); | |
3654 | ||
3655 | POSTING_READ(reg); | |
3656 | udelay(150); | |
3657 | ||
01a415fd DV |
3658 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3659 | I915_READ(FDI_RX_IIR(pipe))); | |
3660 | ||
139ccd3f JB |
3661 | /* Try each vswing and preemphasis setting twice before moving on */ |
3662 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3663 | /* disable first in case we need to retry */ | |
3664 | reg = FDI_TX_CTL(pipe); | |
3665 | temp = I915_READ(reg); | |
3666 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3667 | temp &= ~FDI_TX_ENABLE; | |
3668 | I915_WRITE(reg, temp); | |
357555c0 | 3669 | |
139ccd3f JB |
3670 | reg = FDI_RX_CTL(pipe); |
3671 | temp = I915_READ(reg); | |
3672 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3673 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3674 | temp &= ~FDI_RX_ENABLE; | |
3675 | I915_WRITE(reg, temp); | |
357555c0 | 3676 | |
139ccd3f | 3677 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3678 | reg = FDI_TX_CTL(pipe); |
3679 | temp = I915_READ(reg); | |
139ccd3f | 3680 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3681 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3682 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3683 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3684 | temp |= snb_b_fdi_train_param[j/2]; |
3685 | temp |= FDI_COMPOSITE_SYNC; | |
3686 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3687 | |
139ccd3f JB |
3688 | I915_WRITE(FDI_RX_MISC(pipe), |
3689 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3690 | |
139ccd3f | 3691 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3692 | temp = I915_READ(reg); |
139ccd3f JB |
3693 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3694 | temp |= FDI_COMPOSITE_SYNC; | |
3695 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3696 | |
139ccd3f JB |
3697 | POSTING_READ(reg); |
3698 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3699 | |
139ccd3f JB |
3700 | for (i = 0; i < 4; i++) { |
3701 | reg = FDI_RX_IIR(pipe); | |
3702 | temp = I915_READ(reg); | |
3703 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3704 | |
139ccd3f JB |
3705 | if (temp & FDI_RX_BIT_LOCK || |
3706 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3707 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3708 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3709 | i); | |
3710 | break; | |
3711 | } | |
3712 | udelay(1); /* should be 0.5us */ | |
3713 | } | |
3714 | if (i == 4) { | |
3715 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3716 | continue; | |
3717 | } | |
357555c0 | 3718 | |
139ccd3f | 3719 | /* Train 2 */ |
357555c0 JB |
3720 | reg = FDI_TX_CTL(pipe); |
3721 | temp = I915_READ(reg); | |
139ccd3f JB |
3722 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3723 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3724 | I915_WRITE(reg, temp); | |
3725 | ||
3726 | reg = FDI_RX_CTL(pipe); | |
3727 | temp = I915_READ(reg); | |
3728 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3729 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3730 | I915_WRITE(reg, temp); |
3731 | ||
3732 | POSTING_READ(reg); | |
139ccd3f | 3733 | udelay(2); /* should be 1.5us */ |
357555c0 | 3734 | |
139ccd3f JB |
3735 | for (i = 0; i < 4; i++) { |
3736 | reg = FDI_RX_IIR(pipe); | |
3737 | temp = I915_READ(reg); | |
3738 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3739 | |
139ccd3f JB |
3740 | if (temp & FDI_RX_SYMBOL_LOCK || |
3741 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3742 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3743 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3744 | i); | |
3745 | goto train_done; | |
3746 | } | |
3747 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3748 | } |
139ccd3f JB |
3749 | if (i == 4) |
3750 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3751 | } |
357555c0 | 3752 | |
139ccd3f | 3753 | train_done: |
357555c0 JB |
3754 | DRM_DEBUG_KMS("FDI train done.\n"); |
3755 | } | |
3756 | ||
88cefb6c | 3757 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3758 | { |
88cefb6c | 3759 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3760 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3761 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3762 | i915_reg_t reg; |
3763 | u32 temp; | |
c64e311e | 3764 | |
c98e9dcf | 3765 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3766 | reg = FDI_RX_CTL(pipe); |
3767 | temp = I915_READ(reg); | |
627eb5a3 | 3768 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3769 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3770 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3771 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3772 | ||
3773 | POSTING_READ(reg); | |
c98e9dcf JB |
3774 | udelay(200); |
3775 | ||
3776 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3777 | temp = I915_READ(reg); |
3778 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3779 | ||
3780 | POSTING_READ(reg); | |
c98e9dcf JB |
3781 | udelay(200); |
3782 | ||
20749730 PZ |
3783 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3784 | reg = FDI_TX_CTL(pipe); | |
3785 | temp = I915_READ(reg); | |
3786 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3787 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3788 | |
20749730 PZ |
3789 | POSTING_READ(reg); |
3790 | udelay(100); | |
6be4a607 | 3791 | } |
0e23b99d JB |
3792 | } |
3793 | ||
88cefb6c DV |
3794 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3795 | { | |
3796 | struct drm_device *dev = intel_crtc->base.dev; | |
3797 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3798 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3799 | i915_reg_t reg; |
3800 | u32 temp; | |
88cefb6c DV |
3801 | |
3802 | /* Switch from PCDclk to Rawclk */ | |
3803 | reg = FDI_RX_CTL(pipe); | |
3804 | temp = I915_READ(reg); | |
3805 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3806 | ||
3807 | /* Disable CPU FDI TX PLL */ | |
3808 | reg = FDI_TX_CTL(pipe); | |
3809 | temp = I915_READ(reg); | |
3810 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3811 | ||
3812 | POSTING_READ(reg); | |
3813 | udelay(100); | |
3814 | ||
3815 | reg = FDI_RX_CTL(pipe); | |
3816 | temp = I915_READ(reg); | |
3817 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3818 | ||
3819 | /* Wait for the clocks to turn off. */ | |
3820 | POSTING_READ(reg); | |
3821 | udelay(100); | |
3822 | } | |
3823 | ||
0fc932b8 JB |
3824 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3825 | { | |
3826 | struct drm_device *dev = crtc->dev; | |
3827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3828 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3829 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3830 | i915_reg_t reg; |
3831 | u32 temp; | |
0fc932b8 JB |
3832 | |
3833 | /* disable CPU FDI tx and PCH FDI rx */ | |
3834 | reg = FDI_TX_CTL(pipe); | |
3835 | temp = I915_READ(reg); | |
3836 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3837 | POSTING_READ(reg); | |
3838 | ||
3839 | reg = FDI_RX_CTL(pipe); | |
3840 | temp = I915_READ(reg); | |
3841 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3842 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3843 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3844 | ||
3845 | POSTING_READ(reg); | |
3846 | udelay(100); | |
3847 | ||
3848 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3849 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3850 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3851 | |
3852 | /* still set train pattern 1 */ | |
3853 | reg = FDI_TX_CTL(pipe); | |
3854 | temp = I915_READ(reg); | |
3855 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3856 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3857 | I915_WRITE(reg, temp); | |
3858 | ||
3859 | reg = FDI_RX_CTL(pipe); | |
3860 | temp = I915_READ(reg); | |
3861 | if (HAS_PCH_CPT(dev)) { | |
3862 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3863 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3864 | } else { | |
3865 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3866 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3867 | } | |
3868 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3869 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3870 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3871 | I915_WRITE(reg, temp); |
3872 | ||
3873 | POSTING_READ(reg); | |
3874 | udelay(100); | |
3875 | } | |
3876 | ||
5dce5b93 CW |
3877 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3878 | { | |
3879 | struct intel_crtc *crtc; | |
3880 | ||
3881 | /* Note that we don't need to be called with mode_config.lock here | |
3882 | * as our list of CRTC objects is static for the lifetime of the | |
3883 | * device and so cannot disappear as we iterate. Similarly, we can | |
3884 | * happily treat the predicates as racy, atomic checks as userspace | |
3885 | * cannot claim and pin a new fb without at least acquring the | |
3886 | * struct_mutex and so serialising with us. | |
3887 | */ | |
d3fcc808 | 3888 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3889 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3890 | continue; | |
3891 | ||
3892 | if (crtc->unpin_work) | |
3893 | intel_wait_for_vblank(dev, crtc->pipe); | |
3894 | ||
3895 | return true; | |
3896 | } | |
3897 | ||
3898 | return false; | |
3899 | } | |
3900 | ||
d6bbafa1 CW |
3901 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3902 | { | |
3903 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3904 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3905 | ||
3906 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3907 | smp_rmb(); | |
3908 | intel_crtc->unpin_work = NULL; | |
3909 | ||
3910 | if (work->event) | |
3911 | drm_send_vblank_event(intel_crtc->base.dev, | |
3912 | intel_crtc->pipe, | |
3913 | work->event); | |
3914 | ||
3915 | drm_crtc_vblank_put(&intel_crtc->base); | |
3916 | ||
3917 | wake_up_all(&dev_priv->pending_flip_queue); | |
3918 | queue_work(dev_priv->wq, &work->work); | |
3919 | ||
3920 | trace_i915_flip_complete(intel_crtc->plane, | |
3921 | work->pending_flip_obj); | |
3922 | } | |
3923 | ||
5008e874 | 3924 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3925 | { |
0f91128d | 3926 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3927 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3928 | long ret; |
e6c3a2a6 | 3929 | |
2c10d571 | 3930 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3931 | |
3932 | ret = wait_event_interruptible_timeout( | |
3933 | dev_priv->pending_flip_queue, | |
3934 | !intel_crtc_has_pending_flip(crtc), | |
3935 | 60*HZ); | |
3936 | ||
3937 | if (ret < 0) | |
3938 | return ret; | |
3939 | ||
3940 | if (ret == 0) { | |
9c787942 | 3941 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3942 | |
5e2d7afc | 3943 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3944 | if (intel_crtc->unpin_work) { |
3945 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3946 | page_flip_completed(intel_crtc); | |
3947 | } | |
5e2d7afc | 3948 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3949 | } |
5bb61643 | 3950 | |
5008e874 | 3951 | return 0; |
e6c3a2a6 CW |
3952 | } |
3953 | ||
060f02d8 VS |
3954 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3955 | { | |
3956 | u32 temp; | |
3957 | ||
3958 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3959 | ||
3960 | mutex_lock(&dev_priv->sb_lock); | |
3961 | ||
3962 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3963 | temp |= SBI_SSCCTL_DISABLE; | |
3964 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3965 | ||
3966 | mutex_unlock(&dev_priv->sb_lock); | |
3967 | } | |
3968 | ||
e615efe4 ED |
3969 | /* Program iCLKIP clock to the desired frequency */ |
3970 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3971 | { | |
3972 | struct drm_device *dev = crtc->dev; | |
3973 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3974 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3975 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3976 | u32 temp; | |
3977 | ||
060f02d8 | 3978 | lpt_disable_iclkip(dev_priv); |
e615efe4 ED |
3979 | |
3980 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3981 | if (clock == 20000) { |
e615efe4 ED |
3982 | auxdiv = 1; |
3983 | divsel = 0x41; | |
3984 | phaseinc = 0x20; | |
3985 | } else { | |
3986 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3987 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3988 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3989 | * convert the virtual clock precision to KHz here for higher |
3990 | * precision. | |
3991 | */ | |
3992 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3993 | u32 iclk_pi_range = 64; | |
3994 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3995 | ||
a2572f5c | 3996 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
e615efe4 ED |
3997 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3998 | pi_value = desired_divisor % iclk_pi_range; | |
3999 | ||
4000 | auxdiv = 0; | |
4001 | divsel = msb_divisor_value - 2; | |
4002 | phaseinc = pi_value; | |
4003 | } | |
4004 | ||
4005 | /* This should not happen with any sane values */ | |
4006 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4007 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4008 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4009 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4010 | ||
4011 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4012 | clock, |
e615efe4 ED |
4013 | auxdiv, |
4014 | divsel, | |
4015 | phasedir, | |
4016 | phaseinc); | |
4017 | ||
060f02d8 VS |
4018 | mutex_lock(&dev_priv->sb_lock); |
4019 | ||
e615efe4 | 4020 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4021 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4022 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4023 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4024 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4025 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4026 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4027 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4028 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4029 | |
4030 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4031 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4032 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4033 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4034 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4035 | |
4036 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4037 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4038 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4039 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4040 | |
060f02d8 VS |
4041 | mutex_unlock(&dev_priv->sb_lock); |
4042 | ||
e615efe4 ED |
4043 | /* Wait for initialization time */ |
4044 | udelay(24); | |
4045 | ||
4046 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4047 | } | |
4048 | ||
275f01b2 DV |
4049 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4050 | enum pipe pch_transcoder) | |
4051 | { | |
4052 | struct drm_device *dev = crtc->base.dev; | |
4053 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4054 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4055 | |
4056 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4057 | I915_READ(HTOTAL(cpu_transcoder))); | |
4058 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4059 | I915_READ(HBLANK(cpu_transcoder))); | |
4060 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4061 | I915_READ(HSYNC(cpu_transcoder))); | |
4062 | ||
4063 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4064 | I915_READ(VTOTAL(cpu_transcoder))); | |
4065 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4066 | I915_READ(VBLANK(cpu_transcoder))); | |
4067 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4068 | I915_READ(VSYNC(cpu_transcoder))); | |
4069 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4070 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4071 | } | |
4072 | ||
003632d9 | 4073 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4074 | { |
4075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4076 | uint32_t temp; | |
4077 | ||
4078 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4079 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4080 | return; |
4081 | ||
4082 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4083 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4084 | ||
003632d9 ACO |
4085 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4086 | if (enable) | |
4087 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4088 | ||
4089 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4090 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4091 | POSTING_READ(SOUTH_CHICKEN1); | |
4092 | } | |
4093 | ||
4094 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4095 | { | |
4096 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4097 | |
4098 | switch (intel_crtc->pipe) { | |
4099 | case PIPE_A: | |
4100 | break; | |
4101 | case PIPE_B: | |
6e3c9717 | 4102 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4103 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4104 | else |
003632d9 | 4105 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4106 | |
4107 | break; | |
4108 | case PIPE_C: | |
003632d9 | 4109 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4110 | |
4111 | break; | |
4112 | default: | |
4113 | BUG(); | |
4114 | } | |
4115 | } | |
4116 | ||
c48b5305 VS |
4117 | /* Return which DP Port should be selected for Transcoder DP control */ |
4118 | static enum port | |
4119 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4120 | { | |
4121 | struct drm_device *dev = crtc->dev; | |
4122 | struct intel_encoder *encoder; | |
4123 | ||
4124 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4125 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4126 | encoder->type == INTEL_OUTPUT_EDP) | |
4127 | return enc_to_dig_port(&encoder->base)->port; | |
4128 | } | |
4129 | ||
4130 | return -1; | |
4131 | } | |
4132 | ||
f67a559d JB |
4133 | /* |
4134 | * Enable PCH resources required for PCH ports: | |
4135 | * - PCH PLLs | |
4136 | * - FDI training & RX/TX | |
4137 | * - update transcoder timings | |
4138 | * - DP transcoding bits | |
4139 | * - transcoder | |
4140 | */ | |
4141 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4142 | { |
4143 | struct drm_device *dev = crtc->dev; | |
4144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4146 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4147 | u32 temp; |
2c07245f | 4148 | |
ab9412ba | 4149 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4150 | |
1fbc0d78 DV |
4151 | if (IS_IVYBRIDGE(dev)) |
4152 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4153 | ||
cd986abb DV |
4154 | /* Write the TU size bits before fdi link training, so that error |
4155 | * detection works. */ | |
4156 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4157 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4158 | ||
3860b2ec VS |
4159 | /* |
4160 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4161 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4162 | */ | |
4163 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4164 | ||
c98e9dcf | 4165 | /* For PCH output, training FDI link */ |
674cf967 | 4166 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4167 | |
3ad8a208 DV |
4168 | /* We need to program the right clock selection before writing the pixel |
4169 | * mutliplier into the DPLL. */ | |
303b81e0 | 4170 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4171 | u32 sel; |
4b645f14 | 4172 | |
c98e9dcf | 4173 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4174 | temp |= TRANS_DPLL_ENABLE(pipe); |
4175 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4176 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4177 | temp |= sel; |
4178 | else | |
4179 | temp &= ~sel; | |
c98e9dcf | 4180 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4181 | } |
5eddb70b | 4182 | |
3ad8a208 DV |
4183 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4184 | * transcoder, and we actually should do this to not upset any PCH | |
4185 | * transcoder that already use the clock when we share it. | |
4186 | * | |
4187 | * Note that enable_shared_dpll tries to do the right thing, but | |
4188 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4189 | * the right LVDS enable sequence. */ | |
85b3894f | 4190 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4191 | |
d9b6cb56 JB |
4192 | /* set transcoder timing, panel must allow it */ |
4193 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4194 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4195 | |
303b81e0 | 4196 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4197 | |
3860b2ec VS |
4198 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4199 | ||
c98e9dcf | 4200 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4201 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4202 | const struct drm_display_mode *adjusted_mode = |
4203 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4204 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4205 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4206 | temp = I915_READ(reg); |
4207 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4208 | TRANS_DP_SYNC_MASK | |
4209 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4210 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4211 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4212 | |
9c4edaee | 4213 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4214 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4215 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4216 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4217 | |
4218 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4219 | case PORT_B: |
5eddb70b | 4220 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4221 | break; |
c48b5305 | 4222 | case PORT_C: |
5eddb70b | 4223 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4224 | break; |
c48b5305 | 4225 | case PORT_D: |
5eddb70b | 4226 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4227 | break; |
4228 | default: | |
e95d41e1 | 4229 | BUG(); |
32f9d658 | 4230 | } |
2c07245f | 4231 | |
5eddb70b | 4232 | I915_WRITE(reg, temp); |
6be4a607 | 4233 | } |
b52eb4dc | 4234 | |
b8a4f404 | 4235 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4236 | } |
4237 | ||
1507e5bd PZ |
4238 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4239 | { | |
4240 | struct drm_device *dev = crtc->dev; | |
4241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4242 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4243 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4244 | |
ab9412ba | 4245 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4246 | |
8c52b5e8 | 4247 | lpt_program_iclkip(crtc); |
1507e5bd | 4248 | |
0540e488 | 4249 | /* Set transcoder timing. */ |
275f01b2 | 4250 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4251 | |
937bb610 | 4252 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4253 | } |
4254 | ||
190f68c5 ACO |
4255 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4256 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4257 | { |
e2b78267 | 4258 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4259 | struct intel_shared_dpll *pll; |
de419ab6 | 4260 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4261 | enum intel_dpll_id i; |
00490c22 | 4262 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4263 | |
de419ab6 ML |
4264 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4265 | ||
98b6bd99 DV |
4266 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4267 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4268 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4269 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4270 | |
46edb027 DV |
4271 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4272 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4273 | |
de419ab6 | 4274 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4275 | |
98b6bd99 DV |
4276 | goto found; |
4277 | } | |
4278 | ||
bcddf610 S |
4279 | if (IS_BROXTON(dev_priv->dev)) { |
4280 | /* PLL is attached to port in bxt */ | |
4281 | struct intel_encoder *encoder; | |
4282 | struct intel_digital_port *intel_dig_port; | |
4283 | ||
4284 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4285 | if (WARN_ON(!encoder)) | |
4286 | return NULL; | |
4287 | ||
4288 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4289 | /* 1:1 mapping between ports and PLLs */ | |
4290 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4291 | pll = &dev_priv->shared_dplls[i]; | |
4292 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4293 | crtc->base.base.id, pll->name); | |
de419ab6 | 4294 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4295 | |
4296 | goto found; | |
00490c22 ML |
4297 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4298 | /* Do not consider SPLL */ | |
4299 | max = 2; | |
bcddf610 | 4300 | |
00490c22 | 4301 | for (i = 0; i < max; i++) { |
e72f9fbf | 4302 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4303 | |
4304 | /* Only want to check enabled timings first */ | |
de419ab6 | 4305 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4306 | continue; |
4307 | ||
190f68c5 | 4308 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4309 | &shared_dpll[i].hw_state, |
4310 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4311 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4312 | crtc->base.base.id, pll->name, |
de419ab6 | 4313 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4314 | pll->active); |
ee7b9f93 JB |
4315 | goto found; |
4316 | } | |
4317 | } | |
4318 | ||
4319 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4320 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4321 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4322 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4323 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4324 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4325 | goto found; |
4326 | } | |
4327 | } | |
4328 | ||
4329 | return NULL; | |
4330 | ||
4331 | found: | |
de419ab6 ML |
4332 | if (shared_dpll[i].crtc_mask == 0) |
4333 | shared_dpll[i].hw_state = | |
4334 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4335 | |
190f68c5 | 4336 | crtc_state->shared_dpll = i; |
46edb027 DV |
4337 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4338 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4339 | |
de419ab6 | 4340 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4341 | |
ee7b9f93 JB |
4342 | return pll; |
4343 | } | |
4344 | ||
de419ab6 | 4345 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4346 | { |
de419ab6 ML |
4347 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4348 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4349 | struct intel_shared_dpll *pll; |
4350 | enum intel_dpll_id i; | |
4351 | ||
de419ab6 ML |
4352 | if (!to_intel_atomic_state(state)->dpll_set) |
4353 | return; | |
8bd31e67 | 4354 | |
de419ab6 | 4355 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4356 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4357 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4358 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4359 | } |
4360 | } | |
4361 | ||
a1520318 | 4362 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4363 | { |
4364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4365 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4366 | u32 temp; |
4367 | ||
4368 | temp = I915_READ(dslreg); | |
4369 | udelay(500); | |
4370 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4371 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4372 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4373 | } |
4374 | } | |
4375 | ||
86adf9d7 ML |
4376 | static int |
4377 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4378 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4379 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4380 | { |
86adf9d7 ML |
4381 | struct intel_crtc_scaler_state *scaler_state = |
4382 | &crtc_state->scaler_state; | |
4383 | struct intel_crtc *intel_crtc = | |
4384 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4385 | int need_scaling; |
6156a456 CK |
4386 | |
4387 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4388 | (src_h != dst_w || src_w != dst_h): | |
4389 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4390 | |
4391 | /* | |
4392 | * if plane is being disabled or scaler is no more required or force detach | |
4393 | * - free scaler binded to this plane/crtc | |
4394 | * - in order to do this, update crtc->scaler_usage | |
4395 | * | |
4396 | * Here scaler state in crtc_state is set free so that | |
4397 | * scaler can be assigned to other user. Actual register | |
4398 | * update to free the scaler is done in plane/panel-fit programming. | |
4399 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4400 | */ | |
86adf9d7 | 4401 | if (force_detach || !need_scaling) { |
a1b2278e | 4402 | if (*scaler_id >= 0) { |
86adf9d7 | 4403 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4404 | scaler_state->scalers[*scaler_id].in_use = 0; |
4405 | ||
86adf9d7 ML |
4406 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4407 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4408 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4409 | scaler_state->scaler_users); |
4410 | *scaler_id = -1; | |
4411 | } | |
4412 | return 0; | |
4413 | } | |
4414 | ||
4415 | /* range checks */ | |
4416 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4417 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4418 | ||
4419 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4420 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4421 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4422 | "size is out of scaler range\n", |
86adf9d7 | 4423 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4424 | return -EINVAL; |
4425 | } | |
4426 | ||
86adf9d7 ML |
4427 | /* mark this plane as a scaler user in crtc_state */ |
4428 | scaler_state->scaler_users |= (1 << scaler_user); | |
4429 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4430 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4431 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4432 | scaler_state->scaler_users); | |
4433 | ||
4434 | return 0; | |
4435 | } | |
4436 | ||
4437 | /** | |
4438 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4439 | * | |
4440 | * @state: crtc's scaler state | |
86adf9d7 ML |
4441 | * |
4442 | * Return | |
4443 | * 0 - scaler_usage updated successfully | |
4444 | * error - requested scaling cannot be supported or other error condition | |
4445 | */ | |
e435d6e5 | 4446 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4447 | { |
4448 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4449 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4450 | |
4451 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4452 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4453 | ||
e435d6e5 | 4454 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
86adf9d7 ML |
4455 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
4456 | state->pipe_src_w, state->pipe_src_h, | |
aad941d5 | 4457 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4458 | } |
4459 | ||
4460 | /** | |
4461 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4462 | * | |
4463 | * @state: crtc's scaler state | |
86adf9d7 ML |
4464 | * @plane_state: atomic plane state to update |
4465 | * | |
4466 | * Return | |
4467 | * 0 - scaler_usage updated successfully | |
4468 | * error - requested scaling cannot be supported or other error condition | |
4469 | */ | |
da20eabd ML |
4470 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4471 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4472 | { |
4473 | ||
4474 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4475 | struct intel_plane *intel_plane = |
4476 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4477 | struct drm_framebuffer *fb = plane_state->base.fb; |
4478 | int ret; | |
4479 | ||
4480 | bool force_detach = !fb || !plane_state->visible; | |
4481 | ||
4482 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4483 | intel_plane->base.base.id, intel_crtc->pipe, | |
4484 | drm_plane_index(&intel_plane->base)); | |
4485 | ||
4486 | ret = skl_update_scaler(crtc_state, force_detach, | |
4487 | drm_plane_index(&intel_plane->base), | |
4488 | &plane_state->scaler_id, | |
4489 | plane_state->base.rotation, | |
4490 | drm_rect_width(&plane_state->src) >> 16, | |
4491 | drm_rect_height(&plane_state->src) >> 16, | |
4492 | drm_rect_width(&plane_state->dst), | |
4493 | drm_rect_height(&plane_state->dst)); | |
4494 | ||
4495 | if (ret || plane_state->scaler_id < 0) | |
4496 | return ret; | |
4497 | ||
a1b2278e | 4498 | /* check colorkey */ |
818ed961 | 4499 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4500 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4501 | intel_plane->base.base.id); |
a1b2278e CK |
4502 | return -EINVAL; |
4503 | } | |
4504 | ||
4505 | /* Check src format */ | |
86adf9d7 ML |
4506 | switch (fb->pixel_format) { |
4507 | case DRM_FORMAT_RGB565: | |
4508 | case DRM_FORMAT_XBGR8888: | |
4509 | case DRM_FORMAT_XRGB8888: | |
4510 | case DRM_FORMAT_ABGR8888: | |
4511 | case DRM_FORMAT_ARGB8888: | |
4512 | case DRM_FORMAT_XRGB2101010: | |
4513 | case DRM_FORMAT_XBGR2101010: | |
4514 | case DRM_FORMAT_YUYV: | |
4515 | case DRM_FORMAT_YVYU: | |
4516 | case DRM_FORMAT_UYVY: | |
4517 | case DRM_FORMAT_VYUY: | |
4518 | break; | |
4519 | default: | |
4520 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4521 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4522 | return -EINVAL; | |
a1b2278e CK |
4523 | } |
4524 | ||
a1b2278e CK |
4525 | return 0; |
4526 | } | |
4527 | ||
e435d6e5 ML |
4528 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4529 | { | |
4530 | int i; | |
4531 | ||
4532 | for (i = 0; i < crtc->num_scalers; i++) | |
4533 | skl_detach_scaler(crtc, i); | |
4534 | } | |
4535 | ||
4536 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4537 | { |
4538 | struct drm_device *dev = crtc->base.dev; | |
4539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4540 | int pipe = crtc->pipe; | |
a1b2278e CK |
4541 | struct intel_crtc_scaler_state *scaler_state = |
4542 | &crtc->config->scaler_state; | |
4543 | ||
4544 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4545 | ||
6e3c9717 | 4546 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4547 | int id; |
4548 | ||
4549 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4550 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4551 | return; | |
4552 | } | |
4553 | ||
4554 | id = scaler_state->scaler_id; | |
4555 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4556 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4557 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4558 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4559 | ||
4560 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4561 | } |
4562 | } | |
4563 | ||
b074cec8 JB |
4564 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4565 | { | |
4566 | struct drm_device *dev = crtc->base.dev; | |
4567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4568 | int pipe = crtc->pipe; | |
4569 | ||
6e3c9717 | 4570 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4571 | /* Force use of hard-coded filter coefficients |
4572 | * as some pre-programmed values are broken, | |
4573 | * e.g. x201. | |
4574 | */ | |
4575 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4576 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4577 | PF_PIPE_SEL_IVB(pipe)); | |
4578 | else | |
4579 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4580 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4581 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4582 | } |
4583 | } | |
4584 | ||
20bc8673 | 4585 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4586 | { |
cea165c3 VS |
4587 | struct drm_device *dev = crtc->base.dev; |
4588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4589 | |
6e3c9717 | 4590 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4591 | return; |
4592 | ||
cea165c3 VS |
4593 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4594 | intel_wait_for_vblank(dev, crtc->pipe); | |
4595 | ||
d77e4531 | 4596 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4597 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4598 | mutex_lock(&dev_priv->rps.hw_lock); |
4599 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4600 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4601 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4602 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4603 | * mailbox." Moreover, the mailbox may return a bogus state, |
4604 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4605 | */ |
4606 | } else { | |
4607 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4608 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4609 | * is essentially intel_wait_for_vblank. If we don't have this | |
4610 | * and don't wait for vblanks until the end of crtc_enable, then | |
4611 | * the HW state readout code will complain that the expected | |
4612 | * IPS_CTL value is not the one we read. */ | |
4613 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4614 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4615 | } | |
d77e4531 PZ |
4616 | } |
4617 | ||
20bc8673 | 4618 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4619 | { |
4620 | struct drm_device *dev = crtc->base.dev; | |
4621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4622 | ||
6e3c9717 | 4623 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4624 | return; |
4625 | ||
4626 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4627 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4628 | mutex_lock(&dev_priv->rps.hw_lock); |
4629 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4630 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4631 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4632 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4633 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4634 | } else { |
2a114cc1 | 4635 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4636 | POSTING_READ(IPS_CTL); |
4637 | } | |
d77e4531 PZ |
4638 | |
4639 | /* We need to wait for a vblank before we can disable the plane. */ | |
4640 | intel_wait_for_vblank(dev, crtc->pipe); | |
4641 | } | |
4642 | ||
4643 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4644 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4645 | { | |
4646 | struct drm_device *dev = crtc->dev; | |
4647 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4648 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4649 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4650 | int i; |
4651 | bool reenable_ips = false; | |
4652 | ||
4653 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4654 | if (!crtc->state->active) |
d77e4531 PZ |
4655 | return; |
4656 | ||
50360403 | 4657 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4658 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4659 | assert_dsi_pll_enabled(dev_priv); |
4660 | else | |
4661 | assert_pll_enabled(dev_priv, pipe); | |
4662 | } | |
4663 | ||
d77e4531 PZ |
4664 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4665 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4666 | */ | |
6e3c9717 | 4667 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4668 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4669 | GAMMA_MODE_MODE_SPLIT)) { | |
4670 | hsw_disable_ips(intel_crtc); | |
4671 | reenable_ips = true; | |
4672 | } | |
4673 | ||
4674 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4675 | i915_reg_t palreg; |
f65a9c5b VS |
4676 | |
4677 | if (HAS_GMCH_DISPLAY(dev)) | |
4678 | palreg = PALETTE(pipe, i); | |
4679 | else | |
4680 | palreg = LGC_PALETTE(pipe, i); | |
4681 | ||
4682 | I915_WRITE(palreg, | |
d77e4531 PZ |
4683 | (intel_crtc->lut_r[i] << 16) | |
4684 | (intel_crtc->lut_g[i] << 8) | | |
4685 | intel_crtc->lut_b[i]); | |
4686 | } | |
4687 | ||
4688 | if (reenable_ips) | |
4689 | hsw_enable_ips(intel_crtc); | |
4690 | } | |
4691 | ||
7cac945f | 4692 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4693 | { |
7cac945f | 4694 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4695 | struct drm_device *dev = intel_crtc->base.dev; |
4696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4697 | ||
4698 | mutex_lock(&dev->struct_mutex); | |
4699 | dev_priv->mm.interruptible = false; | |
4700 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4701 | dev_priv->mm.interruptible = true; | |
4702 | mutex_unlock(&dev->struct_mutex); | |
4703 | } | |
4704 | ||
4705 | /* Let userspace switch the overlay on again. In most cases userspace | |
4706 | * has to recompute where to put it anyway. | |
4707 | */ | |
4708 | } | |
4709 | ||
87d4300a ML |
4710 | /** |
4711 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4712 | * @crtc: the CRTC whose primary plane was just enabled | |
4713 | * | |
4714 | * Performs potentially sleeping operations that must be done after the primary | |
4715 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4716 | * called due to an explicit primary plane update, or due to an implicit | |
4717 | * re-enable that is caused when a sprite plane is updated to no longer | |
4718 | * completely hide the primary plane. | |
4719 | */ | |
4720 | static void | |
4721 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4722 | { |
4723 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4724 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4725 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4726 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4727 | |
87d4300a ML |
4728 | /* |
4729 | * FIXME IPS should be fine as long as one plane is | |
4730 | * enabled, but in practice it seems to have problems | |
4731 | * when going from primary only to sprite only and vice | |
4732 | * versa. | |
4733 | */ | |
a5c4d7bc VS |
4734 | hsw_enable_ips(intel_crtc); |
4735 | ||
f99d7069 | 4736 | /* |
87d4300a ML |
4737 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4738 | * So don't enable underrun reporting before at least some planes | |
4739 | * are enabled. | |
4740 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4741 | * but leave the pipe running. | |
f99d7069 | 4742 | */ |
87d4300a ML |
4743 | if (IS_GEN2(dev)) |
4744 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4745 | ||
aca7b684 VS |
4746 | /* Underruns don't always raise interrupts, so check manually. */ |
4747 | intel_check_cpu_fifo_underruns(dev_priv); | |
4748 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4749 | } |
4750 | ||
87d4300a ML |
4751 | /** |
4752 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4753 | * @crtc: the CRTC whose primary plane is to be disabled | |
4754 | * | |
4755 | * Performs potentially sleeping operations that must be done before the | |
4756 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4757 | * be called due to an explicit primary plane update, or due to an implicit | |
4758 | * disable that is caused when a sprite plane completely hides the primary | |
4759 | * plane. | |
4760 | */ | |
4761 | static void | |
4762 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4763 | { |
4764 | struct drm_device *dev = crtc->dev; | |
4765 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4766 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4767 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4768 | |
87d4300a ML |
4769 | /* |
4770 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4771 | * So diasble underrun reporting before all the planes get disabled. | |
4772 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4773 | * but leave the pipe running. | |
4774 | */ | |
4775 | if (IS_GEN2(dev)) | |
4776 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4777 | |
87d4300a ML |
4778 | /* |
4779 | * Vblank time updates from the shadow to live plane control register | |
4780 | * are blocked if the memory self-refresh mode is active at that | |
4781 | * moment. So to make sure the plane gets truly disabled, disable | |
4782 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4783 | * will be checked/applied by the HW only at the next frame start | |
4784 | * event which is after the vblank start event, so we need to have a | |
4785 | * wait-for-vblank between disabling the plane and the pipe. | |
4786 | */ | |
262cd2e1 | 4787 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4788 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4789 | dev_priv->wm.vlv.cxsr = false; |
4790 | intel_wait_for_vblank(dev, pipe); | |
4791 | } | |
87d4300a | 4792 | |
87d4300a ML |
4793 | /* |
4794 | * FIXME IPS should be fine as long as one plane is | |
4795 | * enabled, but in practice it seems to have problems | |
4796 | * when going from primary only to sprite only and vice | |
4797 | * versa. | |
4798 | */ | |
a5c4d7bc | 4799 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4800 | } |
4801 | ||
ac21b225 ML |
4802 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4803 | { | |
4804 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4805 | struct intel_crtc_state *pipe_config = |
4806 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4807 | struct drm_device *dev = crtc->base.dev; |
ac21b225 ML |
4808 | |
4809 | if (atomic->wait_vblank) | |
4810 | intel_wait_for_vblank(dev, crtc->pipe); | |
4811 | ||
4812 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4813 | ||
ab1d3a0e | 4814 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4815 | |
b9001114 | 4816 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4817 | intel_update_watermarks(&crtc->base); |
4818 | ||
c80ac854 | 4819 | if (atomic->update_fbc) |
754d1133 | 4820 | intel_fbc_update(crtc); |
ac21b225 ML |
4821 | |
4822 | if (atomic->post_enable_primary) | |
4823 | intel_post_enable_primary(&crtc->base); | |
4824 | ||
ac21b225 ML |
4825 | memset(atomic, 0, sizeof(*atomic)); |
4826 | } | |
4827 | ||
4828 | static void intel_pre_plane_update(struct intel_crtc *crtc) | |
4829 | { | |
4830 | struct drm_device *dev = crtc->base.dev; | |
eddfcbcd | 4831 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4832 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4833 | struct intel_crtc_state *pipe_config = |
4834 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4835 | |
c80ac854 | 4836 | if (atomic->disable_fbc) |
d029bcad | 4837 | intel_fbc_deactivate(crtc); |
ac21b225 | 4838 | |
066cf55b RV |
4839 | if (crtc->atomic.disable_ips) |
4840 | hsw_disable_ips(crtc); | |
4841 | ||
ac21b225 ML |
4842 | if (atomic->pre_disable_primary) |
4843 | intel_pre_disable_primary(&crtc->base); | |
852eb00d | 4844 | |
ab1d3a0e | 4845 | if (pipe_config->disable_cxsr) { |
852eb00d VS |
4846 | crtc->wm.cxsr_allowed = false; |
4847 | intel_set_memory_cxsr(dev_priv, false); | |
4848 | } | |
92826fcd ML |
4849 | |
4850 | if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed) | |
4851 | intel_update_watermarks(&crtc->base); | |
ac21b225 ML |
4852 | } |
4853 | ||
d032ffa0 | 4854 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4855 | { |
4856 | struct drm_device *dev = crtc->dev; | |
4857 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4858 | struct drm_plane *p; |
87d4300a ML |
4859 | int pipe = intel_crtc->pipe; |
4860 | ||
7cac945f | 4861 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4862 | |
d032ffa0 ML |
4863 | drm_for_each_plane_mask(p, dev, plane_mask) |
4864 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4865 | |
f99d7069 DV |
4866 | /* |
4867 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4868 | * to compute the mask of flip planes precisely. For the time being | |
4869 | * consider this a flip to a NULL plane. | |
4870 | */ | |
4871 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4872 | } |
4873 | ||
f67a559d JB |
4874 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4875 | { | |
4876 | struct drm_device *dev = crtc->dev; | |
4877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4878 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4879 | struct intel_encoder *encoder; |
f67a559d | 4880 | int pipe = intel_crtc->pipe; |
f67a559d | 4881 | |
53d9f4e9 | 4882 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4883 | return; |
4884 | ||
81b088ca VS |
4885 | if (intel_crtc->config->has_pch_encoder) |
4886 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4887 | ||
6e3c9717 | 4888 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4889 | intel_prepare_shared_dpll(intel_crtc); |
4890 | ||
6e3c9717 | 4891 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4892 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4893 | |
4894 | intel_set_pipe_timings(intel_crtc); | |
4895 | ||
6e3c9717 | 4896 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4897 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4898 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4899 | } |
4900 | ||
4901 | ironlake_set_pipeconf(crtc); | |
4902 | ||
f67a559d | 4903 | intel_crtc->active = true; |
8664281b | 4904 | |
a72e4c9f | 4905 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4906 | |
f6736a1a | 4907 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4908 | if (encoder->pre_enable) |
4909 | encoder->pre_enable(encoder); | |
f67a559d | 4910 | |
6e3c9717 | 4911 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4912 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4913 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4914 | * enabling. */ | |
88cefb6c | 4915 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4916 | } else { |
4917 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4918 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4919 | } | |
f67a559d | 4920 | |
b074cec8 | 4921 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4922 | |
9c54c0dd JB |
4923 | /* |
4924 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4925 | * clocks enabled | |
4926 | */ | |
4927 | intel_crtc_load_lut(crtc); | |
4928 | ||
f37fcc2a | 4929 | intel_update_watermarks(crtc); |
e1fdc473 | 4930 | intel_enable_pipe(intel_crtc); |
f67a559d | 4931 | |
6e3c9717 | 4932 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4933 | ironlake_pch_enable(crtc); |
c98e9dcf | 4934 | |
f9b61ff6 DV |
4935 | assert_vblank_disabled(crtc); |
4936 | drm_crtc_vblank_on(crtc); | |
4937 | ||
fa5c73b1 DV |
4938 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4939 | encoder->enable(encoder); | |
61b77ddd DV |
4940 | |
4941 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4942 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4943 | |
4944 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4945 | if (intel_crtc->config->has_pch_encoder) | |
4946 | intel_wait_for_vblank(dev, pipe); | |
4947 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
d029bcad PZ |
4948 | |
4949 | intel_fbc_enable(intel_crtc); | |
6be4a607 JB |
4950 | } |
4951 | ||
42db64ef PZ |
4952 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4953 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4954 | { | |
f5adf94e | 4955 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4956 | } |
4957 | ||
4f771f10 PZ |
4958 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4959 | { | |
4960 | struct drm_device *dev = crtc->dev; | |
4961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4962 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4963 | struct intel_encoder *encoder; | |
99d736a2 ML |
4964 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4965 | struct intel_crtc_state *pipe_config = | |
4966 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4967 | |
53d9f4e9 | 4968 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4969 | return; |
4970 | ||
81b088ca VS |
4971 | if (intel_crtc->config->has_pch_encoder) |
4972 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4973 | false); | |
4974 | ||
df8ad70c DV |
4975 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4976 | intel_enable_shared_dpll(intel_crtc); | |
4977 | ||
6e3c9717 | 4978 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4979 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4980 | |
4981 | intel_set_pipe_timings(intel_crtc); | |
4982 | ||
6e3c9717 ACO |
4983 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4984 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4985 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4986 | } |
4987 | ||
6e3c9717 | 4988 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4989 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4990 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4991 | } |
4992 | ||
4993 | haswell_set_pipeconf(crtc); | |
4994 | ||
4995 | intel_set_pipe_csc(crtc); | |
4996 | ||
4f771f10 | 4997 | intel_crtc->active = true; |
8664281b | 4998 | |
6b698516 DV |
4999 | if (intel_crtc->config->has_pch_encoder) |
5000 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5001 | else | |
5002 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5003 | ||
7d4aefd0 | 5004 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
5005 | if (encoder->pre_enable) |
5006 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5007 | } |
4f771f10 | 5008 | |
d2d65408 | 5009 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5010 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5011 | |
a65347ba | 5012 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5013 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5014 | |
1c132b44 | 5015 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5016 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5017 | else |
1c132b44 | 5018 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5019 | |
5020 | /* | |
5021 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5022 | * clocks enabled | |
5023 | */ | |
5024 | intel_crtc_load_lut(crtc); | |
5025 | ||
1f544388 | 5026 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5027 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5028 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5029 | |
f37fcc2a | 5030 | intel_update_watermarks(crtc); |
e1fdc473 | 5031 | intel_enable_pipe(intel_crtc); |
42db64ef | 5032 | |
6e3c9717 | 5033 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5034 | lpt_pch_enable(crtc); |
4f771f10 | 5035 | |
a65347ba | 5036 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5037 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5038 | ||
f9b61ff6 DV |
5039 | assert_vblank_disabled(crtc); |
5040 | drm_crtc_vblank_on(crtc); | |
5041 | ||
8807e55b | 5042 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5043 | encoder->enable(encoder); |
8807e55b JN |
5044 | intel_opregion_notify_encoder(encoder, true); |
5045 | } | |
4f771f10 | 5046 | |
6b698516 DV |
5047 | if (intel_crtc->config->has_pch_encoder) { |
5048 | intel_wait_for_vblank(dev, pipe); | |
5049 | intel_wait_for_vblank(dev, pipe); | |
5050 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5051 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5052 | true); | |
6b698516 | 5053 | } |
d2d65408 | 5054 | |
e4916946 PZ |
5055 | /* If we change the relative order between pipe/planes enabling, we need |
5056 | * to change the workaround. */ | |
99d736a2 ML |
5057 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5058 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5059 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5060 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5061 | } | |
d029bcad PZ |
5062 | |
5063 | intel_fbc_enable(intel_crtc); | |
4f771f10 PZ |
5064 | } |
5065 | ||
bfd16b2a | 5066 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5067 | { |
5068 | struct drm_device *dev = crtc->base.dev; | |
5069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5070 | int pipe = crtc->pipe; | |
5071 | ||
5072 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5073 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5074 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5075 | I915_WRITE(PF_CTL(pipe), 0); |
5076 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5077 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5078 | } | |
5079 | } | |
5080 | ||
6be4a607 JB |
5081 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5082 | { | |
5083 | struct drm_device *dev = crtc->dev; | |
5084 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5085 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5086 | struct intel_encoder *encoder; |
6be4a607 | 5087 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5088 | |
37ca8d4c VS |
5089 | if (intel_crtc->config->has_pch_encoder) |
5090 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5091 | ||
ea9d758d DV |
5092 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5093 | encoder->disable(encoder); | |
5094 | ||
f9b61ff6 DV |
5095 | drm_crtc_vblank_off(crtc); |
5096 | assert_vblank_disabled(crtc); | |
5097 | ||
3860b2ec VS |
5098 | /* |
5099 | * Sometimes spurious CPU pipe underruns happen when the | |
5100 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5101 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5102 | */ | |
5103 | if (intel_crtc->config->has_pch_encoder) | |
5104 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5105 | ||
575f7ab7 | 5106 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5107 | |
bfd16b2a | 5108 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5109 | |
3860b2ec | 5110 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5111 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5112 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5113 | } | |
5a74f70a | 5114 | |
bf49ec8c DV |
5115 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5116 | if (encoder->post_disable) | |
5117 | encoder->post_disable(encoder); | |
2c07245f | 5118 | |
6e3c9717 | 5119 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5120 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5121 | |
d925c59a | 5122 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5123 | i915_reg_t reg; |
5124 | u32 temp; | |
5125 | ||
d925c59a DV |
5126 | /* disable TRANS_DP_CTL */ |
5127 | reg = TRANS_DP_CTL(pipe); | |
5128 | temp = I915_READ(reg); | |
5129 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5130 | TRANS_DP_PORT_SEL_MASK); | |
5131 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5132 | I915_WRITE(reg, temp); | |
5133 | ||
5134 | /* disable DPLL_SEL */ | |
5135 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5136 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5137 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5138 | } |
e3421a18 | 5139 | |
d925c59a DV |
5140 | ironlake_fdi_pll_disable(intel_crtc); |
5141 | } | |
81b088ca VS |
5142 | |
5143 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
d029bcad PZ |
5144 | |
5145 | intel_fbc_disable_crtc(intel_crtc); | |
6be4a607 | 5146 | } |
1b3c7a47 | 5147 | |
4f771f10 | 5148 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5149 | { |
4f771f10 PZ |
5150 | struct drm_device *dev = crtc->dev; |
5151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5152 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5153 | struct intel_encoder *encoder; |
6e3c9717 | 5154 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5155 | |
d2d65408 VS |
5156 | if (intel_crtc->config->has_pch_encoder) |
5157 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5158 | false); | |
5159 | ||
8807e55b JN |
5160 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5161 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5162 | encoder->disable(encoder); |
8807e55b | 5163 | } |
4f771f10 | 5164 | |
f9b61ff6 DV |
5165 | drm_crtc_vblank_off(crtc); |
5166 | assert_vblank_disabled(crtc); | |
5167 | ||
575f7ab7 | 5168 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5169 | |
6e3c9717 | 5170 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5171 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5172 | ||
a65347ba | 5173 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5174 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5175 | |
1c132b44 | 5176 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5177 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5178 | else |
bfd16b2a | 5179 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5180 | |
a65347ba | 5181 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5182 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5183 | |
97b040aa ID |
5184 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5185 | if (encoder->post_disable) | |
5186 | encoder->post_disable(encoder); | |
81b088ca | 5187 | |
92966a37 VS |
5188 | if (intel_crtc->config->has_pch_encoder) { |
5189 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5190 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5191 | intel_ddi_fdi_disable(crtc); |
5192 | ||
81b088ca VS |
5193 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5194 | true); | |
92966a37 | 5195 | } |
d029bcad PZ |
5196 | |
5197 | intel_fbc_disable_crtc(intel_crtc); | |
4f771f10 PZ |
5198 | } |
5199 | ||
2dd24552 JB |
5200 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5201 | { | |
5202 | struct drm_device *dev = crtc->base.dev; | |
5203 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5204 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5205 | |
681a8504 | 5206 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5207 | return; |
5208 | ||
2dd24552 | 5209 | /* |
c0b03411 DV |
5210 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5211 | * according to register description and PRM. | |
2dd24552 | 5212 | */ |
c0b03411 DV |
5213 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5214 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5215 | |
b074cec8 JB |
5216 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5217 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5218 | |
5219 | /* Border color in case we don't scale up to the full screen. Black by | |
5220 | * default, change to something else for debugging. */ | |
5221 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5222 | } |
5223 | ||
d05410f9 DA |
5224 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5225 | { | |
5226 | switch (port) { | |
5227 | case PORT_A: | |
6331a704 | 5228 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5229 | case PORT_B: |
6331a704 | 5230 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5231 | case PORT_C: |
6331a704 | 5232 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5233 | case PORT_D: |
6331a704 | 5234 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5235 | case PORT_E: |
6331a704 | 5236 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5237 | default: |
b9fec167 | 5238 | MISSING_CASE(port); |
d05410f9 DA |
5239 | return POWER_DOMAIN_PORT_OTHER; |
5240 | } | |
5241 | } | |
5242 | ||
25f78f58 VS |
5243 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5244 | { | |
5245 | switch (port) { | |
5246 | case PORT_A: | |
5247 | return POWER_DOMAIN_AUX_A; | |
5248 | case PORT_B: | |
5249 | return POWER_DOMAIN_AUX_B; | |
5250 | case PORT_C: | |
5251 | return POWER_DOMAIN_AUX_C; | |
5252 | case PORT_D: | |
5253 | return POWER_DOMAIN_AUX_D; | |
5254 | case PORT_E: | |
5255 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5256 | return POWER_DOMAIN_AUX_D; | |
5257 | default: | |
b9fec167 | 5258 | MISSING_CASE(port); |
25f78f58 VS |
5259 | return POWER_DOMAIN_AUX_A; |
5260 | } | |
5261 | } | |
5262 | ||
319be8ae ID |
5263 | enum intel_display_power_domain |
5264 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5265 | { | |
5266 | struct drm_device *dev = intel_encoder->base.dev; | |
5267 | struct intel_digital_port *intel_dig_port; | |
5268 | ||
5269 | switch (intel_encoder->type) { | |
5270 | case INTEL_OUTPUT_UNKNOWN: | |
5271 | /* Only DDI platforms should ever use this output type */ | |
5272 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5273 | case INTEL_OUTPUT_DISPLAYPORT: | |
5274 | case INTEL_OUTPUT_HDMI: | |
5275 | case INTEL_OUTPUT_EDP: | |
5276 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5277 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5278 | case INTEL_OUTPUT_DP_MST: |
5279 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5280 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5281 | case INTEL_OUTPUT_ANALOG: |
5282 | return POWER_DOMAIN_PORT_CRT; | |
5283 | case INTEL_OUTPUT_DSI: | |
5284 | return POWER_DOMAIN_PORT_DSI; | |
5285 | default: | |
5286 | return POWER_DOMAIN_PORT_OTHER; | |
5287 | } | |
5288 | } | |
5289 | ||
25f78f58 VS |
5290 | enum intel_display_power_domain |
5291 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5292 | { | |
5293 | struct drm_device *dev = intel_encoder->base.dev; | |
5294 | struct intel_digital_port *intel_dig_port; | |
5295 | ||
5296 | switch (intel_encoder->type) { | |
5297 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5298 | case INTEL_OUTPUT_HDMI: |
5299 | /* | |
5300 | * Only DDI platforms should ever use these output types. | |
5301 | * We can get here after the HDMI detect code has already set | |
5302 | * the type of the shared encoder. Since we can't be sure | |
5303 | * what's the status of the given connectors, play safe and | |
5304 | * run the DP detection too. | |
5305 | */ | |
25f78f58 VS |
5306 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5307 | case INTEL_OUTPUT_DISPLAYPORT: | |
5308 | case INTEL_OUTPUT_EDP: | |
5309 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5310 | return port_to_aux_power_domain(intel_dig_port->port); | |
5311 | case INTEL_OUTPUT_DP_MST: | |
5312 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5313 | return port_to_aux_power_domain(intel_dig_port->port); | |
5314 | default: | |
b9fec167 | 5315 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5316 | return POWER_DOMAIN_AUX_A; |
5317 | } | |
5318 | } | |
5319 | ||
319be8ae | 5320 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5321 | { |
319be8ae ID |
5322 | struct drm_device *dev = crtc->dev; |
5323 | struct intel_encoder *intel_encoder; | |
5324 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5325 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5326 | unsigned long mask; |
1a70a728 | 5327 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
77d22dca | 5328 | |
292b990e ML |
5329 | if (!crtc->state->active) |
5330 | return 0; | |
5331 | ||
77d22dca ID |
5332 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5333 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5334 | if (intel_crtc->config->pch_pfit.enabled || |
5335 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5336 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5337 | ||
319be8ae ID |
5338 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5339 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5340 | ||
77d22dca ID |
5341 | return mask; |
5342 | } | |
5343 | ||
292b990e | 5344 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5345 | { |
292b990e ML |
5346 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5347 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5348 | enum intel_display_power_domain domain; | |
5349 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5350 | |
292b990e ML |
5351 | old_domains = intel_crtc->enabled_power_domains; |
5352 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5353 | |
292b990e ML |
5354 | domains = new_domains & ~old_domains; |
5355 | ||
5356 | for_each_power_domain(domain, domains) | |
5357 | intel_display_power_get(dev_priv, domain); | |
5358 | ||
5359 | return old_domains & ~new_domains; | |
5360 | } | |
5361 | ||
5362 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5363 | unsigned long domains) | |
5364 | { | |
5365 | enum intel_display_power_domain domain; | |
5366 | ||
5367 | for_each_power_domain(domain, domains) | |
5368 | intel_display_power_put(dev_priv, domain); | |
5369 | } | |
77d22dca | 5370 | |
292b990e ML |
5371 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5372 | { | |
5373 | struct drm_device *dev = state->dev; | |
5374 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5375 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5376 | struct drm_crtc_state *crtc_state; | |
5377 | struct drm_crtc *crtc; | |
5378 | int i; | |
77d22dca | 5379 | |
292b990e ML |
5380 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5381 | if (needs_modeset(crtc->state)) | |
5382 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5383 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5384 | } |
5385 | ||
27c329ed ML |
5386 | if (dev_priv->display.modeset_commit_cdclk) { |
5387 | unsigned int cdclk = to_intel_atomic_state(state)->cdclk; | |
5388 | ||
5389 | if (cdclk != dev_priv->cdclk_freq && | |
5390 | !WARN_ON(!state->allow_modeset)) | |
5391 | dev_priv->display.modeset_commit_cdclk(state); | |
5392 | } | |
50f6e502 | 5393 | |
292b990e ML |
5394 | for (i = 0; i < I915_MAX_PIPES; i++) |
5395 | if (put_domains[i]) | |
5396 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5397 | } |
5398 | ||
adafdc6f MK |
5399 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5400 | { | |
5401 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5402 | ||
5403 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5404 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5405 | return max_cdclk_freq; | |
5406 | else if (IS_CHERRYVIEW(dev_priv)) | |
5407 | return max_cdclk_freq*95/100; | |
5408 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5409 | return 2*max_cdclk_freq*90/100; | |
5410 | else | |
5411 | return max_cdclk_freq*90/100; | |
5412 | } | |
5413 | ||
560a7ae4 DL |
5414 | static void intel_update_max_cdclk(struct drm_device *dev) |
5415 | { | |
5416 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5417 | ||
ef11bdb3 | 5418 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5419 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5420 | ||
5421 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5422 | dev_priv->max_cdclk_freq = 675000; | |
5423 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5424 | dev_priv->max_cdclk_freq = 540000; | |
5425 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5426 | dev_priv->max_cdclk_freq = 450000; | |
5427 | else | |
5428 | dev_priv->max_cdclk_freq = 337500; | |
5429 | } else if (IS_BROADWELL(dev)) { | |
5430 | /* | |
5431 | * FIXME with extra cooling we can allow | |
5432 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5433 | * How can we know if extra cooling is | |
5434 | * available? PCI ID, VTB, something else? | |
5435 | */ | |
5436 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5437 | dev_priv->max_cdclk_freq = 450000; | |
5438 | else if (IS_BDW_ULX(dev)) | |
5439 | dev_priv->max_cdclk_freq = 450000; | |
5440 | else if (IS_BDW_ULT(dev)) | |
5441 | dev_priv->max_cdclk_freq = 540000; | |
5442 | else | |
5443 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5444 | } else if (IS_CHERRYVIEW(dev)) { |
5445 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5446 | } else if (IS_VALLEYVIEW(dev)) { |
5447 | dev_priv->max_cdclk_freq = 400000; | |
5448 | } else { | |
5449 | /* otherwise assume cdclk is fixed */ | |
5450 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5451 | } | |
5452 | ||
adafdc6f MK |
5453 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5454 | ||
560a7ae4 DL |
5455 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5456 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5457 | |
5458 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5459 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5460 | } |
5461 | ||
5462 | static void intel_update_cdclk(struct drm_device *dev) | |
5463 | { | |
5464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5465 | ||
5466 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5467 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5468 | dev_priv->cdclk_freq); | |
5469 | ||
5470 | /* | |
5471 | * Program the gmbus_freq based on the cdclk frequency. | |
5472 | * BSpec erroneously claims we should aim for 4MHz, but | |
5473 | * in fact 1MHz is the correct frequency. | |
5474 | */ | |
666a4537 | 5475 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5476 | /* |
5477 | * Program the gmbus_freq based on the cdclk frequency. | |
5478 | * BSpec erroneously claims we should aim for 4MHz, but | |
5479 | * in fact 1MHz is the correct frequency. | |
5480 | */ | |
5481 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5482 | } | |
5483 | ||
5484 | if (dev_priv->max_cdclk_freq == 0) | |
5485 | intel_update_max_cdclk(dev); | |
5486 | } | |
5487 | ||
70d0c574 | 5488 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5489 | { |
5490 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5491 | uint32_t divider; | |
5492 | uint32_t ratio; | |
5493 | uint32_t current_freq; | |
5494 | int ret; | |
5495 | ||
5496 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5497 | switch (frequency) { | |
5498 | case 144000: | |
5499 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5500 | ratio = BXT_DE_PLL_RATIO(60); | |
5501 | break; | |
5502 | case 288000: | |
5503 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5504 | ratio = BXT_DE_PLL_RATIO(60); | |
5505 | break; | |
5506 | case 384000: | |
5507 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5508 | ratio = BXT_DE_PLL_RATIO(60); | |
5509 | break; | |
5510 | case 576000: | |
5511 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5512 | ratio = BXT_DE_PLL_RATIO(60); | |
5513 | break; | |
5514 | case 624000: | |
5515 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5516 | ratio = BXT_DE_PLL_RATIO(65); | |
5517 | break; | |
5518 | case 19200: | |
5519 | /* | |
5520 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5521 | * to suppress GCC warning. | |
5522 | */ | |
5523 | ratio = 0; | |
5524 | divider = 0; | |
5525 | break; | |
5526 | default: | |
5527 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5528 | ||
5529 | return; | |
5530 | } | |
5531 | ||
5532 | mutex_lock(&dev_priv->rps.hw_lock); | |
5533 | /* Inform power controller of upcoming frequency change */ | |
5534 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5535 | 0x80000000); | |
5536 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5537 | ||
5538 | if (ret) { | |
5539 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5540 | ret, frequency); | |
5541 | return; | |
5542 | } | |
5543 | ||
5544 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5545 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5546 | current_freq = current_freq * 500 + 1000; | |
5547 | ||
5548 | /* | |
5549 | * DE PLL has to be disabled when | |
5550 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5551 | * - before setting to 624MHz (PLL needs toggling) | |
5552 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5553 | */ | |
5554 | if (frequency == 19200 || frequency == 624000 || | |
5555 | current_freq == 624000) { | |
5556 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5557 | /* Timeout 200us */ | |
5558 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5559 | 1)) | |
5560 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5561 | } | |
5562 | ||
5563 | if (frequency != 19200) { | |
5564 | uint32_t val; | |
5565 | ||
5566 | val = I915_READ(BXT_DE_PLL_CTL); | |
5567 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5568 | val |= ratio; | |
5569 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5570 | ||
5571 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5572 | /* Timeout 200us */ | |
5573 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5574 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5575 | ||
5576 | val = I915_READ(CDCLK_CTL); | |
5577 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5578 | val |= divider; | |
5579 | /* | |
5580 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5581 | * enable otherwise. | |
5582 | */ | |
5583 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5584 | if (frequency >= 500000) | |
5585 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5586 | ||
5587 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5588 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5589 | val |= (frequency - 1000) / 500; | |
5590 | I915_WRITE(CDCLK_CTL, val); | |
5591 | } | |
5592 | ||
5593 | mutex_lock(&dev_priv->rps.hw_lock); | |
5594 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5595 | DIV_ROUND_UP(frequency, 25000)); | |
5596 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5597 | ||
5598 | if (ret) { | |
5599 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5600 | ret, frequency); | |
5601 | return; | |
5602 | } | |
5603 | ||
a47871bd | 5604 | intel_update_cdclk(dev); |
f8437dd1 VK |
5605 | } |
5606 | ||
5607 | void broxton_init_cdclk(struct drm_device *dev) | |
5608 | { | |
5609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5610 | uint32_t val; | |
5611 | ||
5612 | /* | |
5613 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5614 | * or else the reset will hang because there is no PCH to respond. | |
5615 | * Move the handshake programming to initialization sequence. | |
5616 | * Previously was left up to BIOS. | |
5617 | */ | |
5618 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5619 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5620 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5621 | ||
5622 | /* Enable PG1 for cdclk */ | |
5623 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5624 | ||
5625 | /* check if cd clock is enabled */ | |
5626 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5627 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5628 | return; | |
5629 | } | |
5630 | ||
5631 | /* | |
5632 | * FIXME: | |
5633 | * - The initial CDCLK needs to be read from VBT. | |
5634 | * Need to make this change after VBT has changes for BXT. | |
5635 | * - check if setting the max (or any) cdclk freq is really necessary | |
5636 | * here, it belongs to modeset time | |
5637 | */ | |
5638 | broxton_set_cdclk(dev, 624000); | |
5639 | ||
5640 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5641 | POSTING_READ(DBUF_CTL); |
5642 | ||
f8437dd1 VK |
5643 | udelay(10); |
5644 | ||
5645 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5646 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5647 | } | |
5648 | ||
5649 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5650 | { | |
5651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5652 | ||
5653 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5654 | POSTING_READ(DBUF_CTL); |
5655 | ||
f8437dd1 VK |
5656 | udelay(10); |
5657 | ||
5658 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5659 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5660 | ||
5661 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5662 | broxton_set_cdclk(dev, 19200); | |
5663 | ||
5664 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5665 | } | |
5666 | ||
5d96d8af DL |
5667 | static const struct skl_cdclk_entry { |
5668 | unsigned int freq; | |
5669 | unsigned int vco; | |
5670 | } skl_cdclk_frequencies[] = { | |
5671 | { .freq = 308570, .vco = 8640 }, | |
5672 | { .freq = 337500, .vco = 8100 }, | |
5673 | { .freq = 432000, .vco = 8640 }, | |
5674 | { .freq = 450000, .vco = 8100 }, | |
5675 | { .freq = 540000, .vco = 8100 }, | |
5676 | { .freq = 617140, .vco = 8640 }, | |
5677 | { .freq = 675000, .vco = 8100 }, | |
5678 | }; | |
5679 | ||
5680 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5681 | { | |
5682 | return (freq - 1000) / 500; | |
5683 | } | |
5684 | ||
5685 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5686 | { | |
5687 | unsigned int i; | |
5688 | ||
5689 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5690 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5691 | ||
5692 | if (e->freq == freq) | |
5693 | return e->vco; | |
5694 | } | |
5695 | ||
5696 | return 8100; | |
5697 | } | |
5698 | ||
5699 | static void | |
5700 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5701 | { | |
5702 | unsigned int min_freq; | |
5703 | u32 val; | |
5704 | ||
5705 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5706 | val = I915_READ(CDCLK_CTL); | |
5707 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5708 | val |= CDCLK_FREQ_337_308; | |
5709 | ||
5710 | if (required_vco == 8640) | |
5711 | min_freq = 308570; | |
5712 | else | |
5713 | min_freq = 337500; | |
5714 | ||
5715 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5716 | ||
5717 | I915_WRITE(CDCLK_CTL, val); | |
5718 | POSTING_READ(CDCLK_CTL); | |
5719 | ||
5720 | /* | |
5721 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5722 | * taking into account the VCO required to operate the eDP panel at the | |
5723 | * desired frequency. The usual DP link rates operate with a VCO of | |
5724 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5725 | * The modeset code is responsible for the selection of the exact link | |
5726 | * rate later on, with the constraint of choosing a frequency that | |
5727 | * works with required_vco. | |
5728 | */ | |
5729 | val = I915_READ(DPLL_CTRL1); | |
5730 | ||
5731 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5732 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5733 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5734 | if (required_vco == 8640) | |
5735 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5736 | SKL_DPLL0); | |
5737 | else | |
5738 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5739 | SKL_DPLL0); | |
5740 | ||
5741 | I915_WRITE(DPLL_CTRL1, val); | |
5742 | POSTING_READ(DPLL_CTRL1); | |
5743 | ||
5744 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5745 | ||
5746 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5747 | DRM_ERROR("DPLL0 not locked\n"); | |
5748 | } | |
5749 | ||
5750 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5751 | { | |
5752 | int ret; | |
5753 | u32 val; | |
5754 | ||
5755 | /* inform PCU we want to change CDCLK */ | |
5756 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5757 | mutex_lock(&dev_priv->rps.hw_lock); | |
5758 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5759 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5760 | ||
5761 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5762 | } | |
5763 | ||
5764 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5765 | { | |
5766 | unsigned int i; | |
5767 | ||
5768 | for (i = 0; i < 15; i++) { | |
5769 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5770 | return true; | |
5771 | udelay(10); | |
5772 | } | |
5773 | ||
5774 | return false; | |
5775 | } | |
5776 | ||
5777 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5778 | { | |
560a7ae4 | 5779 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5780 | u32 freq_select, pcu_ack; |
5781 | ||
5782 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5783 | ||
5784 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5785 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5786 | return; | |
5787 | } | |
5788 | ||
5789 | /* set CDCLK_CTL */ | |
5790 | switch(freq) { | |
5791 | case 450000: | |
5792 | case 432000: | |
5793 | freq_select = CDCLK_FREQ_450_432; | |
5794 | pcu_ack = 1; | |
5795 | break; | |
5796 | case 540000: | |
5797 | freq_select = CDCLK_FREQ_540; | |
5798 | pcu_ack = 2; | |
5799 | break; | |
5800 | case 308570: | |
5801 | case 337500: | |
5802 | default: | |
5803 | freq_select = CDCLK_FREQ_337_308; | |
5804 | pcu_ack = 0; | |
5805 | break; | |
5806 | case 617140: | |
5807 | case 675000: | |
5808 | freq_select = CDCLK_FREQ_675_617; | |
5809 | pcu_ack = 3; | |
5810 | break; | |
5811 | } | |
5812 | ||
5813 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5814 | POSTING_READ(CDCLK_CTL); | |
5815 | ||
5816 | /* inform PCU of the change */ | |
5817 | mutex_lock(&dev_priv->rps.hw_lock); | |
5818 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5819 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5820 | |
5821 | intel_update_cdclk(dev); | |
5d96d8af DL |
5822 | } |
5823 | ||
5824 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5825 | { | |
5826 | /* disable DBUF power */ | |
5827 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5828 | POSTING_READ(DBUF_CTL); | |
5829 | ||
5830 | udelay(10); | |
5831 | ||
5832 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5833 | DRM_ERROR("DBuf power disable timeout\n"); | |
5834 | ||
ab96c1ee ID |
5835 | /* disable DPLL0 */ |
5836 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5837 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5838 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5839 | } |
5840 | ||
5841 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5842 | { | |
5d96d8af DL |
5843 | unsigned int required_vco; |
5844 | ||
39d9b85a GW |
5845 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5846 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5847 | /* enable DPLL0 */ | |
5848 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5849 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5850 | } |
5851 | ||
5d96d8af DL |
5852 | /* set CDCLK to the frequency the BIOS chose */ |
5853 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5854 | ||
5855 | /* enable DBUF power */ | |
5856 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5857 | POSTING_READ(DBUF_CTL); | |
5858 | ||
5859 | udelay(10); | |
5860 | ||
5861 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5862 | DRM_ERROR("DBuf power enable timeout\n"); | |
5863 | } | |
5864 | ||
c73666f3 SK |
5865 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5866 | { | |
5867 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5868 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5869 | int freq = dev_priv->skl_boot_cdclk; | |
5870 | ||
f1b391a5 SK |
5871 | /* |
5872 | * check if the pre-os intialized the display | |
5873 | * There is SWF18 scratchpad register defined which is set by the | |
5874 | * pre-os which can be used by the OS drivers to check the status | |
5875 | */ | |
5876 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5877 | goto sanitize; | |
5878 | ||
c73666f3 SK |
5879 | /* Is PLL enabled and locked ? */ |
5880 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5881 | goto sanitize; | |
5882 | ||
5883 | /* DPLL okay; verify the cdclock | |
5884 | * | |
5885 | * Noticed in some instances that the freq selection is correct but | |
5886 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5887 | * enable display. Verify the same as well. | |
5888 | */ | |
5889 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5890 | /* All well; nothing to sanitize */ | |
5891 | return false; | |
5892 | sanitize: | |
5893 | /* | |
5894 | * As of now initialize with max cdclk till | |
5895 | * we get dynamic cdclk support | |
5896 | * */ | |
5897 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5898 | skl_init_cdclk(dev_priv); | |
5899 | ||
5900 | /* we did have to sanitize */ | |
5901 | return true; | |
5902 | } | |
5903 | ||
30a970c6 JB |
5904 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5905 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5906 | { | |
5907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5908 | u32 val, cmd; | |
5909 | ||
164dfd28 VK |
5910 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5911 | != dev_priv->cdclk_freq); | |
d60c4473 | 5912 | |
dfcab17e | 5913 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5914 | cmd = 2; |
dfcab17e | 5915 | else if (cdclk == 266667) |
30a970c6 JB |
5916 | cmd = 1; |
5917 | else | |
5918 | cmd = 0; | |
5919 | ||
5920 | mutex_lock(&dev_priv->rps.hw_lock); | |
5921 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5922 | val &= ~DSPFREQGUAR_MASK; | |
5923 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5924 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5925 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5926 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5927 | 50)) { | |
5928 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5929 | } | |
5930 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5931 | ||
54433e91 VS |
5932 | mutex_lock(&dev_priv->sb_lock); |
5933 | ||
dfcab17e | 5934 | if (cdclk == 400000) { |
6bcda4f0 | 5935 | u32 divider; |
30a970c6 | 5936 | |
6bcda4f0 | 5937 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5938 | |
30a970c6 JB |
5939 | /* adjust cdclk divider */ |
5940 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5941 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5942 | val |= divider; |
5943 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5944 | |
5945 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5946 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5947 | 50)) |
5948 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5949 | } |
5950 | ||
30a970c6 JB |
5951 | /* adjust self-refresh exit latency value */ |
5952 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5953 | val &= ~0x7f; | |
5954 | ||
5955 | /* | |
5956 | * For high bandwidth configs, we set a higher latency in the bunit | |
5957 | * so that the core display fetch happens in time to avoid underruns. | |
5958 | */ | |
dfcab17e | 5959 | if (cdclk == 400000) |
30a970c6 JB |
5960 | val |= 4500 / 250; /* 4.5 usec */ |
5961 | else | |
5962 | val |= 3000 / 250; /* 3.0 usec */ | |
5963 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5964 | |
a580516d | 5965 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5966 | |
b6283055 | 5967 | intel_update_cdclk(dev); |
30a970c6 JB |
5968 | } |
5969 | ||
383c5a6a VS |
5970 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5971 | { | |
5972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5973 | u32 val, cmd; | |
5974 | ||
164dfd28 VK |
5975 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5976 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5977 | |
5978 | switch (cdclk) { | |
383c5a6a VS |
5979 | case 333333: |
5980 | case 320000: | |
383c5a6a | 5981 | case 266667: |
383c5a6a | 5982 | case 200000: |
383c5a6a VS |
5983 | break; |
5984 | default: | |
5f77eeb0 | 5985 | MISSING_CASE(cdclk); |
383c5a6a VS |
5986 | return; |
5987 | } | |
5988 | ||
9d0d3fda VS |
5989 | /* |
5990 | * Specs are full of misinformation, but testing on actual | |
5991 | * hardware has shown that we just need to write the desired | |
5992 | * CCK divider into the Punit register. | |
5993 | */ | |
5994 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5995 | ||
383c5a6a VS |
5996 | mutex_lock(&dev_priv->rps.hw_lock); |
5997 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5998 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5999 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6000 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6001 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6002 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6003 | 50)) { | |
6004 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6005 | } | |
6006 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6007 | ||
b6283055 | 6008 | intel_update_cdclk(dev); |
383c5a6a VS |
6009 | } |
6010 | ||
30a970c6 JB |
6011 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6012 | int max_pixclk) | |
6013 | { | |
6bcda4f0 | 6014 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6015 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6016 | |
30a970c6 JB |
6017 | /* |
6018 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6019 | * 200MHz | |
6020 | * 267MHz | |
29dc7ef3 | 6021 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6022 | * 400MHz (VLV only) |
6023 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6024 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6025 | * |
6026 | * We seem to get an unstable or solid color picture at 200MHz. | |
6027 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6028 | * are off. | |
30a970c6 | 6029 | */ |
6cca3195 VS |
6030 | if (!IS_CHERRYVIEW(dev_priv) && |
6031 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6032 | return 400000; |
6cca3195 | 6033 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6034 | return freq_320; |
e37c67a1 | 6035 | else if (max_pixclk > 0) |
dfcab17e | 6036 | return 266667; |
e37c67a1 VS |
6037 | else |
6038 | return 200000; | |
30a970c6 JB |
6039 | } |
6040 | ||
f8437dd1 VK |
6041 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6042 | int max_pixclk) | |
6043 | { | |
6044 | /* | |
6045 | * FIXME: | |
6046 | * - remove the guardband, it's not needed on BXT | |
6047 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6048 | */ | |
6049 | if (max_pixclk > 576000*9/10) | |
6050 | return 624000; | |
6051 | else if (max_pixclk > 384000*9/10) | |
6052 | return 576000; | |
6053 | else if (max_pixclk > 288000*9/10) | |
6054 | return 384000; | |
6055 | else if (max_pixclk > 144000*9/10) | |
6056 | return 288000; | |
6057 | else | |
6058 | return 144000; | |
6059 | } | |
6060 | ||
a821fc46 ACO |
6061 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
6062 | * that's non-NULL, look at current state otherwise. */ | |
6063 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
6064 | struct drm_atomic_state *state) | |
30a970c6 | 6065 | { |
30a970c6 | 6066 | struct intel_crtc *intel_crtc; |
304603f4 | 6067 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
6068 | int max_pixclk = 0; |
6069 | ||
d3fcc808 | 6070 | for_each_intel_crtc(dev, intel_crtc) { |
27c329ed | 6071 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
304603f4 ACO |
6072 | if (IS_ERR(crtc_state)) |
6073 | return PTR_ERR(crtc_state); | |
6074 | ||
6075 | if (!crtc_state->base.enable) | |
6076 | continue; | |
6077 | ||
6078 | max_pixclk = max(max_pixclk, | |
6079 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
6080 | } |
6081 | ||
6082 | return max_pixclk; | |
6083 | } | |
6084 | ||
27c329ed | 6085 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6086 | { |
27c329ed ML |
6087 | struct drm_device *dev = state->dev; |
6088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6089 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
30a970c6 | 6090 | |
304603f4 ACO |
6091 | if (max_pixclk < 0) |
6092 | return max_pixclk; | |
30a970c6 | 6093 | |
27c329ed ML |
6094 | to_intel_atomic_state(state)->cdclk = |
6095 | valleyview_calc_cdclk(dev_priv, max_pixclk); | |
0a9ab303 | 6096 | |
27c329ed ML |
6097 | return 0; |
6098 | } | |
304603f4 | 6099 | |
27c329ed ML |
6100 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6101 | { | |
6102 | struct drm_device *dev = state->dev; | |
6103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6104 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
85a96e7a | 6105 | |
27c329ed ML |
6106 | if (max_pixclk < 0) |
6107 | return max_pixclk; | |
85a96e7a | 6108 | |
27c329ed ML |
6109 | to_intel_atomic_state(state)->cdclk = |
6110 | broxton_calc_cdclk(dev_priv, max_pixclk); | |
85a96e7a | 6111 | |
27c329ed | 6112 | return 0; |
30a970c6 JB |
6113 | } |
6114 | ||
1e69cd74 VS |
6115 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6116 | { | |
6117 | unsigned int credits, default_credits; | |
6118 | ||
6119 | if (IS_CHERRYVIEW(dev_priv)) | |
6120 | default_credits = PFI_CREDIT(12); | |
6121 | else | |
6122 | default_credits = PFI_CREDIT(8); | |
6123 | ||
bfa7df01 | 6124 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6125 | /* CHV suggested value is 31 or 63 */ |
6126 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6127 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6128 | else |
6129 | credits = PFI_CREDIT(15); | |
6130 | } else { | |
6131 | credits = default_credits; | |
6132 | } | |
6133 | ||
6134 | /* | |
6135 | * WA - write default credits before re-programming | |
6136 | * FIXME: should we also set the resend bit here? | |
6137 | */ | |
6138 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6139 | default_credits); | |
6140 | ||
6141 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6142 | credits | PFI_CREDIT_RESEND); | |
6143 | ||
6144 | /* | |
6145 | * FIXME is this guaranteed to clear | |
6146 | * immediately or should we poll for it? | |
6147 | */ | |
6148 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6149 | } | |
6150 | ||
27c329ed | 6151 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6152 | { |
a821fc46 | 6153 | struct drm_device *dev = old_state->dev; |
27c329ed | 6154 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
30a970c6 | 6155 | struct drm_i915_private *dev_priv = dev->dev_private; |
30a970c6 | 6156 | |
27c329ed ML |
6157 | /* |
6158 | * FIXME: We can end up here with all power domains off, yet | |
6159 | * with a CDCLK frequency other than the minimum. To account | |
6160 | * for this take the PIPE-A power domain, which covers the HW | |
6161 | * blocks needed for the following programming. This can be | |
6162 | * removed once it's guaranteed that we get here either with | |
6163 | * the minimum CDCLK set, or the required power domains | |
6164 | * enabled. | |
6165 | */ | |
6166 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6167 | |
27c329ed ML |
6168 | if (IS_CHERRYVIEW(dev)) |
6169 | cherryview_set_cdclk(dev, req_cdclk); | |
6170 | else | |
6171 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6172 | |
27c329ed | 6173 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6174 | |
27c329ed | 6175 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6176 | } |
6177 | ||
89b667f8 JB |
6178 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6179 | { | |
6180 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6181 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6182 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6183 | struct intel_encoder *encoder; | |
6184 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6185 | |
53d9f4e9 | 6186 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6187 | return; |
6188 | ||
6e3c9717 | 6189 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6190 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6191 | |
6192 | intel_set_pipe_timings(intel_crtc); | |
6193 | ||
c14b0485 VS |
6194 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6196 | ||
6197 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6198 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6199 | } | |
6200 | ||
5b18e57c DV |
6201 | i9xx_set_pipeconf(intel_crtc); |
6202 | ||
89b667f8 | 6203 | intel_crtc->active = true; |
89b667f8 | 6204 | |
a72e4c9f | 6205 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6206 | |
89b667f8 JB |
6207 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6208 | if (encoder->pre_pll_enable) | |
6209 | encoder->pre_pll_enable(encoder); | |
6210 | ||
a65347ba | 6211 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6212 | if (IS_CHERRYVIEW(dev)) { |
6213 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6214 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6215 | } else { |
6216 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6217 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6218 | } |
9d556c99 | 6219 | } |
89b667f8 JB |
6220 | |
6221 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6222 | if (encoder->pre_enable) | |
6223 | encoder->pre_enable(encoder); | |
6224 | ||
2dd24552 JB |
6225 | i9xx_pfit_enable(intel_crtc); |
6226 | ||
63cbb074 VS |
6227 | intel_crtc_load_lut(crtc); |
6228 | ||
e1fdc473 | 6229 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6230 | |
4b3a9526 VS |
6231 | assert_vblank_disabled(crtc); |
6232 | drm_crtc_vblank_on(crtc); | |
6233 | ||
f9b61ff6 DV |
6234 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6235 | encoder->enable(encoder); | |
89b667f8 JB |
6236 | } |
6237 | ||
f13c2ef3 DV |
6238 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6239 | { | |
6240 | struct drm_device *dev = crtc->base.dev; | |
6241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6242 | ||
6e3c9717 ACO |
6243 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6244 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6245 | } |
6246 | ||
0b8765c6 | 6247 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6248 | { |
6249 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6250 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6251 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6252 | struct intel_encoder *encoder; |
79e53945 | 6253 | int pipe = intel_crtc->pipe; |
79e53945 | 6254 | |
53d9f4e9 | 6255 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6256 | return; |
6257 | ||
f13c2ef3 DV |
6258 | i9xx_set_pll_dividers(intel_crtc); |
6259 | ||
6e3c9717 | 6260 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6261 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6262 | |
6263 | intel_set_pipe_timings(intel_crtc); | |
6264 | ||
5b18e57c DV |
6265 | i9xx_set_pipeconf(intel_crtc); |
6266 | ||
f7abfe8b | 6267 | intel_crtc->active = true; |
6b383a7f | 6268 | |
4a3436e8 | 6269 | if (!IS_GEN2(dev)) |
a72e4c9f | 6270 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6271 | |
9d6d9f19 MK |
6272 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6273 | if (encoder->pre_enable) | |
6274 | encoder->pre_enable(encoder); | |
6275 | ||
f6736a1a DV |
6276 | i9xx_enable_pll(intel_crtc); |
6277 | ||
2dd24552 JB |
6278 | i9xx_pfit_enable(intel_crtc); |
6279 | ||
63cbb074 VS |
6280 | intel_crtc_load_lut(crtc); |
6281 | ||
f37fcc2a | 6282 | intel_update_watermarks(crtc); |
e1fdc473 | 6283 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6284 | |
4b3a9526 VS |
6285 | assert_vblank_disabled(crtc); |
6286 | drm_crtc_vblank_on(crtc); | |
6287 | ||
f9b61ff6 DV |
6288 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6289 | encoder->enable(encoder); | |
d029bcad PZ |
6290 | |
6291 | intel_fbc_enable(intel_crtc); | |
0b8765c6 | 6292 | } |
79e53945 | 6293 | |
87476d63 DV |
6294 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6295 | { | |
6296 | struct drm_device *dev = crtc->base.dev; | |
6297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6298 | |
6e3c9717 | 6299 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6300 | return; |
87476d63 | 6301 | |
328d8e82 | 6302 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6303 | |
328d8e82 DV |
6304 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6305 | I915_READ(PFIT_CONTROL)); | |
6306 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6307 | } |
6308 | ||
0b8765c6 JB |
6309 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6310 | { | |
6311 | struct drm_device *dev = crtc->dev; | |
6312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6314 | struct intel_encoder *encoder; |
0b8765c6 | 6315 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6316 | |
6304cd91 VS |
6317 | /* |
6318 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6319 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6320 | * We also need to wait on all gmch platforms because of the |
6321 | * self-refresh mode constraint explained above. | |
6304cd91 | 6322 | */ |
564ed191 | 6323 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6324 | |
4b3a9526 VS |
6325 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6326 | encoder->disable(encoder); | |
6327 | ||
f9b61ff6 DV |
6328 | drm_crtc_vblank_off(crtc); |
6329 | assert_vblank_disabled(crtc); | |
6330 | ||
575f7ab7 | 6331 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6332 | |
87476d63 | 6333 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6334 | |
89b667f8 JB |
6335 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6336 | if (encoder->post_disable) | |
6337 | encoder->post_disable(encoder); | |
6338 | ||
a65347ba | 6339 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6340 | if (IS_CHERRYVIEW(dev)) |
6341 | chv_disable_pll(dev_priv, pipe); | |
6342 | else if (IS_VALLEYVIEW(dev)) | |
6343 | vlv_disable_pll(dev_priv, pipe); | |
6344 | else | |
1c4e0274 | 6345 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6346 | } |
0b8765c6 | 6347 | |
d6db995f VS |
6348 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6349 | if (encoder->post_pll_disable) | |
6350 | encoder->post_pll_disable(encoder); | |
6351 | ||
4a3436e8 | 6352 | if (!IS_GEN2(dev)) |
a72e4c9f | 6353 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
d029bcad PZ |
6354 | |
6355 | intel_fbc_disable_crtc(intel_crtc); | |
0b8765c6 JB |
6356 | } |
6357 | ||
b17d48e2 ML |
6358 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6359 | { | |
6360 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6361 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6362 | enum intel_display_power_domain domain; | |
6363 | unsigned long domains; | |
6364 | ||
6365 | if (!intel_crtc->active) | |
6366 | return; | |
6367 | ||
a539205a | 6368 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6369 | WARN_ON(intel_crtc->unpin_work); |
6370 | ||
a539205a | 6371 | intel_pre_disable_primary(crtc); |
54a41961 ML |
6372 | |
6373 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6374 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6375 | } |
6376 | ||
b17d48e2 | 6377 | dev_priv->display.crtc_disable(crtc); |
37d9078b MR |
6378 | intel_crtc->active = false; |
6379 | intel_update_watermarks(crtc); | |
1f7457b1 | 6380 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6381 | |
6382 | domains = intel_crtc->enabled_power_domains; | |
6383 | for_each_power_domain(domain, domains) | |
6384 | intel_display_power_put(dev_priv, domain); | |
6385 | intel_crtc->enabled_power_domains = 0; | |
6386 | } | |
6387 | ||
6b72d486 ML |
6388 | /* |
6389 | * turn all crtc's off, but do not adjust state | |
6390 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6391 | */ | |
70e0bd74 | 6392 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6393 | { |
70e0bd74 ML |
6394 | struct drm_mode_config *config = &dev->mode_config; |
6395 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6396 | struct drm_atomic_state *state; | |
6b72d486 | 6397 | struct drm_crtc *crtc; |
70e0bd74 ML |
6398 | unsigned crtc_mask = 0; |
6399 | int ret = 0; | |
6400 | ||
6401 | if (WARN_ON(!ctx)) | |
6402 | return 0; | |
6403 | ||
6404 | lockdep_assert_held(&ctx->ww_ctx); | |
6405 | state = drm_atomic_state_alloc(dev); | |
6406 | if (WARN_ON(!state)) | |
6407 | return -ENOMEM; | |
6408 | ||
6409 | state->acquire_ctx = ctx; | |
6410 | state->allow_modeset = true; | |
6411 | ||
6412 | for_each_crtc(dev, crtc) { | |
6413 | struct drm_crtc_state *crtc_state = | |
6414 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6415 | |
70e0bd74 ML |
6416 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6417 | if (ret) | |
6418 | goto free; | |
6419 | ||
6420 | if (!crtc_state->active) | |
6421 | continue; | |
6422 | ||
6423 | crtc_state->active = false; | |
6424 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6425 | } | |
6426 | ||
6427 | if (crtc_mask) { | |
74c090b1 | 6428 | ret = drm_atomic_commit(state); |
70e0bd74 ML |
6429 | |
6430 | if (!ret) { | |
6431 | for_each_crtc(dev, crtc) | |
6432 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6433 | crtc->state->active = true; | |
6434 | ||
6435 | return ret; | |
6436 | } | |
6437 | } | |
6438 | ||
6439 | free: | |
6440 | if (ret) | |
6441 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6442 | drm_atomic_state_free(state); | |
6443 | return ret; | |
ee7b9f93 JB |
6444 | } |
6445 | ||
ea5b213a | 6446 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6447 | { |
4ef69c7a | 6448 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6449 | |
ea5b213a CW |
6450 | drm_encoder_cleanup(encoder); |
6451 | kfree(intel_encoder); | |
7e7d76c3 JB |
6452 | } |
6453 | ||
0a91ca29 DV |
6454 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6455 | * internal consistency). */ | |
b980514c | 6456 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6457 | { |
35dd3c64 ML |
6458 | struct drm_crtc *crtc = connector->base.state->crtc; |
6459 | ||
6460 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6461 | connector->base.base.id, | |
6462 | connector->base.name); | |
6463 | ||
0a91ca29 | 6464 | if (connector->get_hw_state(connector)) { |
e85376cb | 6465 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6466 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6467 | |
35dd3c64 ML |
6468 | I915_STATE_WARN(!crtc, |
6469 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6470 | |
35dd3c64 ML |
6471 | if (!crtc) |
6472 | return; | |
6473 | ||
6474 | I915_STATE_WARN(!crtc->state->active, | |
6475 | "connector is active, but attached crtc isn't\n"); | |
6476 | ||
e85376cb | 6477 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6478 | return; |
6479 | ||
e85376cb | 6480 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6481 | "atomic encoder doesn't match attached encoder\n"); |
6482 | ||
e85376cb | 6483 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6484 | "attached encoder crtc differs from connector crtc\n"); |
6485 | } else { | |
4d688a2a ML |
6486 | I915_STATE_WARN(crtc && crtc->state->active, |
6487 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6488 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6489 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6490 | } |
79e53945 JB |
6491 | } |
6492 | ||
08d9bc92 ACO |
6493 | int intel_connector_init(struct intel_connector *connector) |
6494 | { | |
6495 | struct drm_connector_state *connector_state; | |
6496 | ||
6497 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6498 | if (!connector_state) | |
6499 | return -ENOMEM; | |
6500 | ||
6501 | connector->base.state = connector_state; | |
6502 | return 0; | |
6503 | } | |
6504 | ||
6505 | struct intel_connector *intel_connector_alloc(void) | |
6506 | { | |
6507 | struct intel_connector *connector; | |
6508 | ||
6509 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6510 | if (!connector) | |
6511 | return NULL; | |
6512 | ||
6513 | if (intel_connector_init(connector) < 0) { | |
6514 | kfree(connector); | |
6515 | return NULL; | |
6516 | } | |
6517 | ||
6518 | return connector; | |
6519 | } | |
6520 | ||
f0947c37 DV |
6521 | /* Simple connector->get_hw_state implementation for encoders that support only |
6522 | * one connector and no cloning and hence the encoder state determines the state | |
6523 | * of the connector. */ | |
6524 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6525 | { |
24929352 | 6526 | enum pipe pipe = 0; |
f0947c37 | 6527 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6528 | |
f0947c37 | 6529 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6530 | } |
6531 | ||
6d293983 | 6532 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6533 | { |
6d293983 ACO |
6534 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6535 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6536 | |
6537 | return 0; | |
6538 | } | |
6539 | ||
6d293983 | 6540 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6541 | struct intel_crtc_state *pipe_config) |
1857e1da | 6542 | { |
6d293983 ACO |
6543 | struct drm_atomic_state *state = pipe_config->base.state; |
6544 | struct intel_crtc *other_crtc; | |
6545 | struct intel_crtc_state *other_crtc_state; | |
6546 | ||
1857e1da DV |
6547 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6548 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6549 | if (pipe_config->fdi_lanes > 4) { | |
6550 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6551 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6552 | return -EINVAL; |
1857e1da DV |
6553 | } |
6554 | ||
bafb6553 | 6555 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6556 | if (pipe_config->fdi_lanes > 2) { |
6557 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6558 | pipe_config->fdi_lanes); | |
6d293983 | 6559 | return -EINVAL; |
1857e1da | 6560 | } else { |
6d293983 | 6561 | return 0; |
1857e1da DV |
6562 | } |
6563 | } | |
6564 | ||
6565 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6566 | return 0; |
1857e1da DV |
6567 | |
6568 | /* Ivybridge 3 pipe is really complicated */ | |
6569 | switch (pipe) { | |
6570 | case PIPE_A: | |
6d293983 | 6571 | return 0; |
1857e1da | 6572 | case PIPE_B: |
6d293983 ACO |
6573 | if (pipe_config->fdi_lanes <= 2) |
6574 | return 0; | |
6575 | ||
6576 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6577 | other_crtc_state = | |
6578 | intel_atomic_get_crtc_state(state, other_crtc); | |
6579 | if (IS_ERR(other_crtc_state)) | |
6580 | return PTR_ERR(other_crtc_state); | |
6581 | ||
6582 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6583 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6584 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6585 | return -EINVAL; |
1857e1da | 6586 | } |
6d293983 | 6587 | return 0; |
1857e1da | 6588 | case PIPE_C: |
251cc67c VS |
6589 | if (pipe_config->fdi_lanes > 2) { |
6590 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6591 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6592 | return -EINVAL; |
251cc67c | 6593 | } |
6d293983 ACO |
6594 | |
6595 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6596 | other_crtc_state = | |
6597 | intel_atomic_get_crtc_state(state, other_crtc); | |
6598 | if (IS_ERR(other_crtc_state)) | |
6599 | return PTR_ERR(other_crtc_state); | |
6600 | ||
6601 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6602 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6603 | return -EINVAL; |
1857e1da | 6604 | } |
6d293983 | 6605 | return 0; |
1857e1da DV |
6606 | default: |
6607 | BUG(); | |
6608 | } | |
6609 | } | |
6610 | ||
e29c22c0 DV |
6611 | #define RETRY 1 |
6612 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6613 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6614 | { |
1857e1da | 6615 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6616 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6617 | int lane, link_bw, fdi_dotclock, ret; |
6618 | bool needs_recompute = false; | |
877d48d5 | 6619 | |
e29c22c0 | 6620 | retry: |
877d48d5 DV |
6621 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6622 | * each output octet as 10 bits. The actual frequency | |
6623 | * is stored as a divider into a 100MHz clock, and the | |
6624 | * mode pixel clock is stored in units of 1KHz. | |
6625 | * Hence the bw of each lane in terms of the mode signal | |
6626 | * is: | |
6627 | */ | |
6628 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6629 | ||
241bfc38 | 6630 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6631 | |
2bd89a07 | 6632 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6633 | pipe_config->pipe_bpp); |
6634 | ||
6635 | pipe_config->fdi_lanes = lane; | |
6636 | ||
2bd89a07 | 6637 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6638 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6639 | |
6d293983 ACO |
6640 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6641 | intel_crtc->pipe, pipe_config); | |
6642 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6643 | pipe_config->pipe_bpp -= 2*3; |
6644 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6645 | pipe_config->pipe_bpp); | |
6646 | needs_recompute = true; | |
6647 | pipe_config->bw_constrained = true; | |
6648 | ||
6649 | goto retry; | |
6650 | } | |
6651 | ||
6652 | if (needs_recompute) | |
6653 | return RETRY; | |
6654 | ||
6d293983 | 6655 | return ret; |
877d48d5 DV |
6656 | } |
6657 | ||
8cfb3407 VS |
6658 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6659 | struct intel_crtc_state *pipe_config) | |
6660 | { | |
6661 | if (pipe_config->pipe_bpp > 24) | |
6662 | return false; | |
6663 | ||
6664 | /* HSW can handle pixel rate up to cdclk? */ | |
6665 | if (IS_HASWELL(dev_priv->dev)) | |
6666 | return true; | |
6667 | ||
6668 | /* | |
b432e5cf VS |
6669 | * We compare against max which means we must take |
6670 | * the increased cdclk requirement into account when | |
6671 | * calculating the new cdclk. | |
6672 | * | |
6673 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6674 | */ |
6675 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6676 | dev_priv->max_cdclk_freq * 95 / 100; | |
6677 | } | |
6678 | ||
42db64ef | 6679 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6680 | struct intel_crtc_state *pipe_config) |
42db64ef | 6681 | { |
8cfb3407 VS |
6682 | struct drm_device *dev = crtc->base.dev; |
6683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6684 | ||
d330a953 | 6685 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6686 | hsw_crtc_supports_ips(crtc) && |
6687 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6688 | } |
6689 | ||
39acb4aa VS |
6690 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6691 | { | |
6692 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6693 | ||
6694 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6695 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6696 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6697 | } | |
6698 | ||
a43f6e0f | 6699 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6700 | struct intel_crtc_state *pipe_config) |
79e53945 | 6701 | { |
a43f6e0f | 6702 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6703 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6704 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6705 | |
ad3a4479 | 6706 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6707 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6708 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6709 | |
6710 | /* | |
39acb4aa | 6711 | * Enable double wide mode when the dot clock |
cf532bb2 | 6712 | * is > 90% of the (display) core speed. |
cf532bb2 | 6713 | */ |
39acb4aa VS |
6714 | if (intel_crtc_supports_double_wide(crtc) && |
6715 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6716 | clock_limit *= 2; |
cf532bb2 | 6717 | pipe_config->double_wide = true; |
ad3a4479 VS |
6718 | } |
6719 | ||
39acb4aa VS |
6720 | if (adjusted_mode->crtc_clock > clock_limit) { |
6721 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6722 | adjusted_mode->crtc_clock, clock_limit, | |
6723 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6724 | return -EINVAL; |
39acb4aa | 6725 | } |
2c07245f | 6726 | } |
89749350 | 6727 | |
1d1d0e27 VS |
6728 | /* |
6729 | * Pipe horizontal size must be even in: | |
6730 | * - DVO ganged mode | |
6731 | * - LVDS dual channel mode | |
6732 | * - Double wide pipe | |
6733 | */ | |
a93e255f | 6734 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6735 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6736 | pipe_config->pipe_src_w &= ~1; | |
6737 | ||
8693a824 DL |
6738 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6739 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6740 | */ |
6741 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6742 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6743 | return -EINVAL; |
44f46b42 | 6744 | |
f5adf94e | 6745 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6746 | hsw_compute_ips_config(crtc, pipe_config); |
6747 | ||
877d48d5 | 6748 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6749 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6750 | |
cf5a15be | 6751 | return 0; |
79e53945 JB |
6752 | } |
6753 | ||
1652d19e VS |
6754 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6755 | { | |
6756 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6757 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6758 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6759 | uint32_t linkrate; | |
6760 | ||
414355a7 | 6761 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6762 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6763 | |
6764 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6765 | return 540000; | |
6766 | ||
6767 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6768 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6769 | |
71cd8423 DL |
6770 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6771 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6772 | /* vco 8640 */ |
6773 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6774 | case CDCLK_FREQ_450_432: | |
6775 | return 432000; | |
6776 | case CDCLK_FREQ_337_308: | |
6777 | return 308570; | |
6778 | case CDCLK_FREQ_675_617: | |
6779 | return 617140; | |
6780 | default: | |
6781 | WARN(1, "Unknown cd freq selection\n"); | |
6782 | } | |
6783 | } else { | |
6784 | /* vco 8100 */ | |
6785 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6786 | case CDCLK_FREQ_450_432: | |
6787 | return 450000; | |
6788 | case CDCLK_FREQ_337_308: | |
6789 | return 337500; | |
6790 | case CDCLK_FREQ_675_617: | |
6791 | return 675000; | |
6792 | default: | |
6793 | WARN(1, "Unknown cd freq selection\n"); | |
6794 | } | |
6795 | } | |
6796 | ||
6797 | /* error case, do as if DPLL0 isn't enabled */ | |
6798 | return 24000; | |
6799 | } | |
6800 | ||
acd3f3d3 BP |
6801 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6802 | { | |
6803 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6804 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6805 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6806 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6807 | int cdclk; | |
6808 | ||
6809 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6810 | return 19200; | |
6811 | ||
6812 | cdclk = 19200 * pll_ratio / 2; | |
6813 | ||
6814 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6815 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6816 | return cdclk; /* 576MHz or 624MHz */ | |
6817 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6818 | return cdclk * 2 / 3; /* 384MHz */ | |
6819 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6820 | return cdclk / 2; /* 288MHz */ | |
6821 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6822 | return cdclk / 4; /* 144MHz */ | |
6823 | } | |
6824 | ||
6825 | /* error case, do as if DE PLL isn't enabled */ | |
6826 | return 19200; | |
6827 | } | |
6828 | ||
1652d19e VS |
6829 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6830 | { | |
6831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6832 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6833 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6834 | ||
6835 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6836 | return 800000; | |
6837 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6838 | return 450000; | |
6839 | else if (freq == LCPLL_CLK_FREQ_450) | |
6840 | return 450000; | |
6841 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6842 | return 540000; | |
6843 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6844 | return 337500; | |
6845 | else | |
6846 | return 675000; | |
6847 | } | |
6848 | ||
6849 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6850 | { | |
6851 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6852 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6853 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6854 | ||
6855 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6856 | return 800000; | |
6857 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6858 | return 450000; | |
6859 | else if (freq == LCPLL_CLK_FREQ_450) | |
6860 | return 450000; | |
6861 | else if (IS_HSW_ULT(dev)) | |
6862 | return 337500; | |
6863 | else | |
6864 | return 540000; | |
79e53945 JB |
6865 | } |
6866 | ||
25eb05fc JB |
6867 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6868 | { | |
bfa7df01 VS |
6869 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6870 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6871 | } |
6872 | ||
b37a6434 VS |
6873 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6874 | { | |
6875 | return 450000; | |
6876 | } | |
6877 | ||
e70236a8 JB |
6878 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6879 | { | |
6880 | return 400000; | |
6881 | } | |
79e53945 | 6882 | |
e70236a8 | 6883 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6884 | { |
e907f170 | 6885 | return 333333; |
e70236a8 | 6886 | } |
79e53945 | 6887 | |
e70236a8 JB |
6888 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6889 | { | |
6890 | return 200000; | |
6891 | } | |
79e53945 | 6892 | |
257a7ffc DV |
6893 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6894 | { | |
6895 | u16 gcfgc = 0; | |
6896 | ||
6897 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6898 | ||
6899 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6900 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6901 | return 266667; |
257a7ffc | 6902 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6903 | return 333333; |
257a7ffc | 6904 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6905 | return 444444; |
257a7ffc DV |
6906 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6907 | return 200000; | |
6908 | default: | |
6909 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6910 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6911 | return 133333; |
257a7ffc | 6912 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6913 | return 166667; |
257a7ffc DV |
6914 | } |
6915 | } | |
6916 | ||
e70236a8 JB |
6917 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6918 | { | |
6919 | u16 gcfgc = 0; | |
79e53945 | 6920 | |
e70236a8 JB |
6921 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6922 | ||
6923 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6924 | return 133333; |
e70236a8 JB |
6925 | else { |
6926 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6927 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6928 | return 333333; |
e70236a8 JB |
6929 | default: |
6930 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6931 | return 190000; | |
79e53945 | 6932 | } |
e70236a8 JB |
6933 | } |
6934 | } | |
6935 | ||
6936 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6937 | { | |
e907f170 | 6938 | return 266667; |
e70236a8 JB |
6939 | } |
6940 | ||
1b1d2716 | 6941 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6942 | { |
6943 | u16 hpllcc = 0; | |
1b1d2716 | 6944 | |
65cd2b3f VS |
6945 | /* |
6946 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6947 | * encoding is different :( | |
6948 | * FIXME is this the right way to detect 852GM/852GMV? | |
6949 | */ | |
6950 | if (dev->pdev->revision == 0x1) | |
6951 | return 133333; | |
6952 | ||
1b1d2716 VS |
6953 | pci_bus_read_config_word(dev->pdev->bus, |
6954 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6955 | ||
e70236a8 JB |
6956 | /* Assume that the hardware is in the high speed state. This |
6957 | * should be the default. | |
6958 | */ | |
6959 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6960 | case GC_CLOCK_133_200: | |
1b1d2716 | 6961 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6962 | case GC_CLOCK_100_200: |
6963 | return 200000; | |
6964 | case GC_CLOCK_166_250: | |
6965 | return 250000; | |
6966 | case GC_CLOCK_100_133: | |
e907f170 | 6967 | return 133333; |
1b1d2716 VS |
6968 | case GC_CLOCK_133_266: |
6969 | case GC_CLOCK_133_266_2: | |
6970 | case GC_CLOCK_166_266: | |
6971 | return 266667; | |
e70236a8 | 6972 | } |
79e53945 | 6973 | |
e70236a8 JB |
6974 | /* Shouldn't happen */ |
6975 | return 0; | |
6976 | } | |
79e53945 | 6977 | |
e70236a8 JB |
6978 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6979 | { | |
e907f170 | 6980 | return 133333; |
79e53945 JB |
6981 | } |
6982 | ||
34edce2f VS |
6983 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6984 | { | |
6985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6986 | static const unsigned int blb_vco[8] = { | |
6987 | [0] = 3200000, | |
6988 | [1] = 4000000, | |
6989 | [2] = 5333333, | |
6990 | [3] = 4800000, | |
6991 | [4] = 6400000, | |
6992 | }; | |
6993 | static const unsigned int pnv_vco[8] = { | |
6994 | [0] = 3200000, | |
6995 | [1] = 4000000, | |
6996 | [2] = 5333333, | |
6997 | [3] = 4800000, | |
6998 | [4] = 2666667, | |
6999 | }; | |
7000 | static const unsigned int cl_vco[8] = { | |
7001 | [0] = 3200000, | |
7002 | [1] = 4000000, | |
7003 | [2] = 5333333, | |
7004 | [3] = 6400000, | |
7005 | [4] = 3333333, | |
7006 | [5] = 3566667, | |
7007 | [6] = 4266667, | |
7008 | }; | |
7009 | static const unsigned int elk_vco[8] = { | |
7010 | [0] = 3200000, | |
7011 | [1] = 4000000, | |
7012 | [2] = 5333333, | |
7013 | [3] = 4800000, | |
7014 | }; | |
7015 | static const unsigned int ctg_vco[8] = { | |
7016 | [0] = 3200000, | |
7017 | [1] = 4000000, | |
7018 | [2] = 5333333, | |
7019 | [3] = 6400000, | |
7020 | [4] = 2666667, | |
7021 | [5] = 4266667, | |
7022 | }; | |
7023 | const unsigned int *vco_table; | |
7024 | unsigned int vco; | |
7025 | uint8_t tmp = 0; | |
7026 | ||
7027 | /* FIXME other chipsets? */ | |
7028 | if (IS_GM45(dev)) | |
7029 | vco_table = ctg_vco; | |
7030 | else if (IS_G4X(dev)) | |
7031 | vco_table = elk_vco; | |
7032 | else if (IS_CRESTLINE(dev)) | |
7033 | vco_table = cl_vco; | |
7034 | else if (IS_PINEVIEW(dev)) | |
7035 | vco_table = pnv_vco; | |
7036 | else if (IS_G33(dev)) | |
7037 | vco_table = blb_vco; | |
7038 | else | |
7039 | return 0; | |
7040 | ||
7041 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7042 | ||
7043 | vco = vco_table[tmp & 0x7]; | |
7044 | if (vco == 0) | |
7045 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7046 | else | |
7047 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7048 | ||
7049 | return vco; | |
7050 | } | |
7051 | ||
7052 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7053 | { | |
7054 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7055 | uint16_t tmp = 0; | |
7056 | ||
7057 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7058 | ||
7059 | cdclk_sel = (tmp >> 12) & 0x1; | |
7060 | ||
7061 | switch (vco) { | |
7062 | case 2666667: | |
7063 | case 4000000: | |
7064 | case 5333333: | |
7065 | return cdclk_sel ? 333333 : 222222; | |
7066 | case 3200000: | |
7067 | return cdclk_sel ? 320000 : 228571; | |
7068 | default: | |
7069 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7070 | return 222222; | |
7071 | } | |
7072 | } | |
7073 | ||
7074 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7075 | { | |
7076 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7077 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7078 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7079 | const uint8_t *div_table; | |
7080 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7081 | uint16_t tmp = 0; | |
7082 | ||
7083 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7084 | ||
7085 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7086 | ||
7087 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7088 | goto fail; | |
7089 | ||
7090 | switch (vco) { | |
7091 | case 3200000: | |
7092 | div_table = div_3200; | |
7093 | break; | |
7094 | case 4000000: | |
7095 | div_table = div_4000; | |
7096 | break; | |
7097 | case 5333333: | |
7098 | div_table = div_5333; | |
7099 | break; | |
7100 | default: | |
7101 | goto fail; | |
7102 | } | |
7103 | ||
7104 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7105 | ||
caf4e252 | 7106 | fail: |
34edce2f VS |
7107 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7108 | return 200000; | |
7109 | } | |
7110 | ||
7111 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7112 | { | |
7113 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7114 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7115 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7116 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7117 | const uint8_t *div_table; | |
7118 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7119 | uint16_t tmp = 0; | |
7120 | ||
7121 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7122 | ||
7123 | cdclk_sel = (tmp >> 4) & 0x7; | |
7124 | ||
7125 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7126 | goto fail; | |
7127 | ||
7128 | switch (vco) { | |
7129 | case 3200000: | |
7130 | div_table = div_3200; | |
7131 | break; | |
7132 | case 4000000: | |
7133 | div_table = div_4000; | |
7134 | break; | |
7135 | case 4800000: | |
7136 | div_table = div_4800; | |
7137 | break; | |
7138 | case 5333333: | |
7139 | div_table = div_5333; | |
7140 | break; | |
7141 | default: | |
7142 | goto fail; | |
7143 | } | |
7144 | ||
7145 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7146 | ||
caf4e252 | 7147 | fail: |
34edce2f VS |
7148 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7149 | return 190476; | |
7150 | } | |
7151 | ||
2c07245f | 7152 | static void |
a65851af | 7153 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7154 | { |
a65851af VS |
7155 | while (*num > DATA_LINK_M_N_MASK || |
7156 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7157 | *num >>= 1; |
7158 | *den >>= 1; | |
7159 | } | |
7160 | } | |
7161 | ||
a65851af VS |
7162 | static void compute_m_n(unsigned int m, unsigned int n, |
7163 | uint32_t *ret_m, uint32_t *ret_n) | |
7164 | { | |
7165 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7166 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7167 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7168 | } | |
7169 | ||
e69d0bc1 DV |
7170 | void |
7171 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7172 | int pixel_clock, int link_clock, | |
7173 | struct intel_link_m_n *m_n) | |
2c07245f | 7174 | { |
e69d0bc1 | 7175 | m_n->tu = 64; |
a65851af VS |
7176 | |
7177 | compute_m_n(bits_per_pixel * pixel_clock, | |
7178 | link_clock * nlanes * 8, | |
7179 | &m_n->gmch_m, &m_n->gmch_n); | |
7180 | ||
7181 | compute_m_n(pixel_clock, link_clock, | |
7182 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7183 | } |
7184 | ||
a7615030 CW |
7185 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7186 | { | |
d330a953 JN |
7187 | if (i915.panel_use_ssc >= 0) |
7188 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7189 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7190 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7191 | } |
7192 | ||
a93e255f ACO |
7193 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7194 | int num_connectors) | |
c65d77d8 | 7195 | { |
a93e255f | 7196 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7197 | struct drm_i915_private *dev_priv = dev->dev_private; |
7198 | int refclk; | |
7199 | ||
a93e255f ACO |
7200 | WARN_ON(!crtc_state->base.state); |
7201 | ||
666a4537 | 7202 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7203 | refclk = 100000; |
a93e255f | 7204 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7205 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7206 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7207 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7208 | } else if (!IS_GEN2(dev)) { |
7209 | refclk = 96000; | |
7210 | } else { | |
7211 | refclk = 48000; | |
7212 | } | |
7213 | ||
7214 | return refclk; | |
7215 | } | |
7216 | ||
7429e9d4 | 7217 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7218 | { |
7df00d7a | 7219 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7220 | } |
f47709a9 | 7221 | |
7429e9d4 DV |
7222 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7223 | { | |
7224 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7225 | } |
7226 | ||
f47709a9 | 7227 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7228 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7229 | intel_clock_t *reduced_clock) |
7230 | { | |
f47709a9 | 7231 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7232 | u32 fp, fp2 = 0; |
7233 | ||
7234 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7235 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7236 | if (reduced_clock) |
7429e9d4 | 7237 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7238 | } else { |
190f68c5 | 7239 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7240 | if (reduced_clock) |
7429e9d4 | 7241 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7242 | } |
7243 | ||
190f68c5 | 7244 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7245 | |
f47709a9 | 7246 | crtc->lowfreq_avail = false; |
a93e255f | 7247 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7248 | reduced_clock) { |
190f68c5 | 7249 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7250 | crtc->lowfreq_avail = true; |
a7516a05 | 7251 | } else { |
190f68c5 | 7252 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7253 | } |
7254 | } | |
7255 | ||
5e69f97f CML |
7256 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7257 | pipe) | |
89b667f8 JB |
7258 | { |
7259 | u32 reg_val; | |
7260 | ||
7261 | /* | |
7262 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7263 | * and set it to a reasonable value instead. | |
7264 | */ | |
ab3c759a | 7265 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7266 | reg_val &= 0xffffff00; |
7267 | reg_val |= 0x00000030; | |
ab3c759a | 7268 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7269 | |
ab3c759a | 7270 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7271 | reg_val &= 0x8cffffff; |
7272 | reg_val = 0x8c000000; | |
ab3c759a | 7273 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7274 | |
ab3c759a | 7275 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7276 | reg_val &= 0xffffff00; |
ab3c759a | 7277 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7278 | |
ab3c759a | 7279 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7280 | reg_val &= 0x00ffffff; |
7281 | reg_val |= 0xb0000000; | |
ab3c759a | 7282 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7283 | } |
7284 | ||
b551842d DV |
7285 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7286 | struct intel_link_m_n *m_n) | |
7287 | { | |
7288 | struct drm_device *dev = crtc->base.dev; | |
7289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7290 | int pipe = crtc->pipe; | |
7291 | ||
e3b95f1e DV |
7292 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7293 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7294 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7295 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7296 | } |
7297 | ||
7298 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7299 | struct intel_link_m_n *m_n, |
7300 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7301 | { |
7302 | struct drm_device *dev = crtc->base.dev; | |
7303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7304 | int pipe = crtc->pipe; | |
6e3c9717 | 7305 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7306 | |
7307 | if (INTEL_INFO(dev)->gen >= 5) { | |
7308 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7309 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7310 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7311 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7312 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7313 | * for gen < 8) and if DRRS is supported (to make sure the | |
7314 | * registers are not unnecessarily accessed). | |
7315 | */ | |
44395bfe | 7316 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7317 | crtc->config->has_drrs) { |
f769cd24 VK |
7318 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7319 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7320 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7321 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7322 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7323 | } | |
b551842d | 7324 | } else { |
e3b95f1e DV |
7325 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7326 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7327 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7328 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7329 | } |
7330 | } | |
7331 | ||
fe3cd48d | 7332 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7333 | { |
fe3cd48d R |
7334 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7335 | ||
7336 | if (m_n == M1_N1) { | |
7337 | dp_m_n = &crtc->config->dp_m_n; | |
7338 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7339 | } else if (m_n == M2_N2) { | |
7340 | ||
7341 | /* | |
7342 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7343 | * needs to be programmed into M1_N1. | |
7344 | */ | |
7345 | dp_m_n = &crtc->config->dp_m2_n2; | |
7346 | } else { | |
7347 | DRM_ERROR("Unsupported divider value\n"); | |
7348 | return; | |
7349 | } | |
7350 | ||
6e3c9717 ACO |
7351 | if (crtc->config->has_pch_encoder) |
7352 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7353 | else |
fe3cd48d | 7354 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7355 | } |
7356 | ||
251ac862 DV |
7357 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7358 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7359 | { |
7360 | u32 dpll, dpll_md; | |
7361 | ||
7362 | /* | |
7363 | * Enable DPIO clock input. We should never disable the reference | |
7364 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7365 | * on it. | |
7366 | */ | |
60bfe44f VS |
7367 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7368 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7369 | /* We should never disable this, set it here for state tracking */ |
7370 | if (crtc->pipe == PIPE_B) | |
7371 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7372 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7373 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7374 | |
d288f65f | 7375 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7376 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7377 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7378 | } |
7379 | ||
d288f65f | 7380 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7381 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7382 | { |
f47709a9 | 7383 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7384 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7385 | int pipe = crtc->pipe; |
bdd4b6a6 | 7386 | u32 mdiv; |
a0c4da24 | 7387 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7388 | u32 coreclk, reg_val; |
a0c4da24 | 7389 | |
a580516d | 7390 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7391 | |
d288f65f VS |
7392 | bestn = pipe_config->dpll.n; |
7393 | bestm1 = pipe_config->dpll.m1; | |
7394 | bestm2 = pipe_config->dpll.m2; | |
7395 | bestp1 = pipe_config->dpll.p1; | |
7396 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7397 | |
89b667f8 JB |
7398 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7399 | ||
7400 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7401 | if (pipe == PIPE_B) |
5e69f97f | 7402 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7403 | |
7404 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7405 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7406 | |
7407 | /* Disable target IRef on PLL */ | |
ab3c759a | 7408 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7409 | reg_val &= 0x00ffffff; |
ab3c759a | 7410 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7411 | |
7412 | /* Disable fast lock */ | |
ab3c759a | 7413 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7414 | |
7415 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7416 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7417 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7418 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7419 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7420 | |
7421 | /* | |
7422 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7423 | * but we don't support that). | |
7424 | * Note: don't use the DAC post divider as it seems unstable. | |
7425 | */ | |
7426 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7427 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7428 | |
a0c4da24 | 7429 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7430 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7431 | |
89b667f8 | 7432 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7433 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7434 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7435 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7436 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7437 | 0x009f0003); |
89b667f8 | 7438 | else |
ab3c759a | 7439 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7440 | 0x00d0000f); |
7441 | ||
681a8504 | 7442 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7443 | /* Use SSC source */ |
bdd4b6a6 | 7444 | if (pipe == PIPE_A) |
ab3c759a | 7445 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7446 | 0x0df40000); |
7447 | else | |
ab3c759a | 7448 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7449 | 0x0df70000); |
7450 | } else { /* HDMI or VGA */ | |
7451 | /* Use bend source */ | |
bdd4b6a6 | 7452 | if (pipe == PIPE_A) |
ab3c759a | 7453 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7454 | 0x0df70000); |
7455 | else | |
ab3c759a | 7456 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7457 | 0x0df40000); |
7458 | } | |
a0c4da24 | 7459 | |
ab3c759a | 7460 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7461 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7462 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7463 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7464 | coreclk |= 0x01000000; |
ab3c759a | 7465 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7466 | |
ab3c759a | 7467 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7468 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7469 | } |
7470 | ||
251ac862 DV |
7471 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7472 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7473 | { |
60bfe44f VS |
7474 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7475 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7476 | DPLL_VCO_ENABLE; |
7477 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7478 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7479 | |
d288f65f VS |
7480 | pipe_config->dpll_hw_state.dpll_md = |
7481 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7482 | } |
7483 | ||
d288f65f | 7484 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7485 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7486 | { |
7487 | struct drm_device *dev = crtc->base.dev; | |
7488 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7489 | int pipe = crtc->pipe; | |
f0f59a00 | 7490 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7491 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7492 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7493 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7494 | u32 dpio_val; |
9cbe40c1 | 7495 | int vco; |
9d556c99 | 7496 | |
d288f65f VS |
7497 | bestn = pipe_config->dpll.n; |
7498 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7499 | bestm1 = pipe_config->dpll.m1; | |
7500 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7501 | bestp1 = pipe_config->dpll.p1; | |
7502 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7503 | vco = pipe_config->dpll.vco; |
a945ce7e | 7504 | dpio_val = 0; |
9cbe40c1 | 7505 | loopfilter = 0; |
9d556c99 CML |
7506 | |
7507 | /* | |
7508 | * Enable Refclk and SSC | |
7509 | */ | |
a11b0703 | 7510 | I915_WRITE(dpll_reg, |
d288f65f | 7511 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7512 | |
a580516d | 7513 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7514 | |
9d556c99 CML |
7515 | /* p1 and p2 divider */ |
7516 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7517 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7518 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7519 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7520 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7521 | ||
7522 | /* Feedback post-divider - m2 */ | |
7523 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7524 | ||
7525 | /* Feedback refclk divider - n and m1 */ | |
7526 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7527 | DPIO_CHV_M1_DIV_BY_2 | | |
7528 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7529 | ||
7530 | /* M2 fraction division */ | |
25a25dfc | 7531 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7532 | |
7533 | /* M2 fraction division enable */ | |
a945ce7e VP |
7534 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7535 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7536 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7537 | if (bestm2_frac) | |
7538 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7539 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7540 | |
de3a0fde VP |
7541 | /* Program digital lock detect threshold */ |
7542 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7543 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7544 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7545 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7546 | if (!bestm2_frac) | |
7547 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7548 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7549 | ||
9d556c99 | 7550 | /* Loop filter */ |
9cbe40c1 VP |
7551 | if (vco == 5400000) { |
7552 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7553 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7554 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7555 | tribuf_calcntr = 0x9; | |
7556 | } else if (vco <= 6200000) { | |
7557 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7558 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7559 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7560 | tribuf_calcntr = 0x9; | |
7561 | } else if (vco <= 6480000) { | |
7562 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7563 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7564 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7565 | tribuf_calcntr = 0x8; | |
7566 | } else { | |
7567 | /* Not supported. Apply the same limits as in the max case */ | |
7568 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7569 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7570 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7571 | tribuf_calcntr = 0; | |
7572 | } | |
9d556c99 CML |
7573 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7574 | ||
968040b2 | 7575 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7576 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7577 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7578 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7579 | ||
9d556c99 CML |
7580 | /* AFC Recal */ |
7581 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7582 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7583 | DPIO_AFC_RECAL); | |
7584 | ||
a580516d | 7585 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7586 | } |
7587 | ||
d288f65f VS |
7588 | /** |
7589 | * vlv_force_pll_on - forcibly enable just the PLL | |
7590 | * @dev_priv: i915 private structure | |
7591 | * @pipe: pipe PLL to enable | |
7592 | * @dpll: PLL configuration | |
7593 | * | |
7594 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7595 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7596 | * be enabled. | |
7597 | */ | |
7598 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7599 | const struct dpll *dpll) | |
7600 | { | |
7601 | struct intel_crtc *crtc = | |
7602 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7603 | struct intel_crtc_state pipe_config = { |
a93e255f | 7604 | .base.crtc = &crtc->base, |
d288f65f VS |
7605 | .pixel_multiplier = 1, |
7606 | .dpll = *dpll, | |
7607 | }; | |
7608 | ||
7609 | if (IS_CHERRYVIEW(dev)) { | |
251ac862 | 7610 | chv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7611 | chv_prepare_pll(crtc, &pipe_config); |
7612 | chv_enable_pll(crtc, &pipe_config); | |
7613 | } else { | |
251ac862 | 7614 | vlv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7615 | vlv_prepare_pll(crtc, &pipe_config); |
7616 | vlv_enable_pll(crtc, &pipe_config); | |
7617 | } | |
7618 | } | |
7619 | ||
7620 | /** | |
7621 | * vlv_force_pll_off - forcibly disable just the PLL | |
7622 | * @dev_priv: i915 private structure | |
7623 | * @pipe: pipe PLL to disable | |
7624 | * | |
7625 | * Disable the PLL for @pipe. To be used in cases where we need | |
7626 | * the PLL enabled even when @pipe is not going to be enabled. | |
7627 | */ | |
7628 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7629 | { | |
7630 | if (IS_CHERRYVIEW(dev)) | |
7631 | chv_disable_pll(to_i915(dev), pipe); | |
7632 | else | |
7633 | vlv_disable_pll(to_i915(dev), pipe); | |
7634 | } | |
7635 | ||
251ac862 DV |
7636 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7637 | struct intel_crtc_state *crtc_state, | |
7638 | intel_clock_t *reduced_clock, | |
7639 | int num_connectors) | |
eb1cbe48 | 7640 | { |
f47709a9 | 7641 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7642 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7643 | u32 dpll; |
7644 | bool is_sdvo; | |
190f68c5 | 7645 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7646 | |
190f68c5 | 7647 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7648 | |
a93e255f ACO |
7649 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7650 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7651 | |
7652 | dpll = DPLL_VGA_MODE_DIS; | |
7653 | ||
a93e255f | 7654 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7655 | dpll |= DPLLB_MODE_LVDS; |
7656 | else | |
7657 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7658 | |
ef1b460d | 7659 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7660 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7661 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7662 | } |
198a037f DV |
7663 | |
7664 | if (is_sdvo) | |
4a33e48d | 7665 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7666 | |
190f68c5 | 7667 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7668 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7669 | |
7670 | /* compute bitmask from p1 value */ | |
7671 | if (IS_PINEVIEW(dev)) | |
7672 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7673 | else { | |
7674 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7675 | if (IS_G4X(dev) && reduced_clock) | |
7676 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7677 | } | |
7678 | switch (clock->p2) { | |
7679 | case 5: | |
7680 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7681 | break; | |
7682 | case 7: | |
7683 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7684 | break; | |
7685 | case 10: | |
7686 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7687 | break; | |
7688 | case 14: | |
7689 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7690 | break; | |
7691 | } | |
7692 | if (INTEL_INFO(dev)->gen >= 4) | |
7693 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7694 | ||
190f68c5 | 7695 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7696 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7697 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7698 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7699 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7700 | else | |
7701 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7702 | ||
7703 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7704 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7705 | |
eb1cbe48 | 7706 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7707 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7708 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7709 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7710 | } |
7711 | } | |
7712 | ||
251ac862 DV |
7713 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7714 | struct intel_crtc_state *crtc_state, | |
7715 | intel_clock_t *reduced_clock, | |
7716 | int num_connectors) | |
eb1cbe48 | 7717 | { |
f47709a9 | 7718 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7719 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7720 | u32 dpll; |
190f68c5 | 7721 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7722 | |
190f68c5 | 7723 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7724 | |
eb1cbe48 DV |
7725 | dpll = DPLL_VGA_MODE_DIS; |
7726 | ||
a93e255f | 7727 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7728 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7729 | } else { | |
7730 | if (clock->p1 == 2) | |
7731 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7732 | else | |
7733 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7734 | if (clock->p2 == 4) | |
7735 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7736 | } | |
7737 | ||
a93e255f | 7738 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7739 | dpll |= DPLL_DVO_2X_MODE; |
7740 | ||
a93e255f | 7741 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7742 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7743 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7744 | else | |
7745 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7746 | ||
7747 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7748 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7749 | } |
7750 | ||
8a654f3b | 7751 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7752 | { |
7753 | struct drm_device *dev = intel_crtc->base.dev; | |
7754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7755 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7756 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7757 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7758 | uint32_t crtc_vtotal, crtc_vblank_end; |
7759 | int vsyncshift = 0; | |
4d8a62ea DV |
7760 | |
7761 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7762 | * the hw state checker will get angry at the mismatch. */ | |
7763 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7764 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7765 | |
609aeaca | 7766 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7767 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7768 | crtc_vtotal -= 1; |
7769 | crtc_vblank_end -= 1; | |
609aeaca | 7770 | |
409ee761 | 7771 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7772 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7773 | else | |
7774 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7775 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7776 | if (vsyncshift < 0) |
7777 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7778 | } |
7779 | ||
7780 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7781 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7782 | |
fe2b8f9d | 7783 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7784 | (adjusted_mode->crtc_hdisplay - 1) | |
7785 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7786 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7787 | (adjusted_mode->crtc_hblank_start - 1) | |
7788 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7789 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7790 | (adjusted_mode->crtc_hsync_start - 1) | |
7791 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7792 | ||
fe2b8f9d | 7793 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7794 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7795 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7796 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7797 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7798 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7799 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7800 | (adjusted_mode->crtc_vsync_start - 1) | |
7801 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7802 | ||
b5e508d4 PZ |
7803 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7804 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7805 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7806 | * bits. */ | |
7807 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7808 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7809 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7810 | ||
b0e77b9c PZ |
7811 | /* pipesrc controls the size that is scaled from, which should |
7812 | * always be the user's requested size. | |
7813 | */ | |
7814 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7815 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7816 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7817 | } |
7818 | ||
1bd1bd80 | 7819 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7820 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7821 | { |
7822 | struct drm_device *dev = crtc->base.dev; | |
7823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7824 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7825 | uint32_t tmp; | |
7826 | ||
7827 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7828 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7829 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7830 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7831 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7832 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7833 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7834 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7835 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7836 | |
7837 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7838 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7839 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7840 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7841 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7842 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7843 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7844 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7845 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7846 | |
7847 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7848 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7849 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7850 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7851 | } |
7852 | ||
7853 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7854 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7855 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7856 | ||
2d112de7 ACO |
7857 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7858 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7859 | } |
7860 | ||
f6a83288 | 7861 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7862 | struct intel_crtc_state *pipe_config) |
babea61d | 7863 | { |
2d112de7 ACO |
7864 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7865 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7866 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7867 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7868 | |
2d112de7 ACO |
7869 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7870 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7871 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7872 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7873 | |
2d112de7 | 7874 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7875 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7876 | |
2d112de7 ACO |
7877 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7878 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7879 | |
7880 | mode->hsync = drm_mode_hsync(mode); | |
7881 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7882 | drm_mode_set_name(mode); | |
babea61d JB |
7883 | } |
7884 | ||
84b046f3 DV |
7885 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7886 | { | |
7887 | struct drm_device *dev = intel_crtc->base.dev; | |
7888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7889 | uint32_t pipeconf; | |
7890 | ||
9f11a9e4 | 7891 | pipeconf = 0; |
84b046f3 | 7892 | |
b6b5d049 VS |
7893 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7894 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7895 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7896 | |
6e3c9717 | 7897 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7898 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7899 | |
ff9ce46e | 7900 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7901 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7902 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7903 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7904 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7905 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7906 | |
6e3c9717 | 7907 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7908 | case 18: |
7909 | pipeconf |= PIPECONF_6BPC; | |
7910 | break; | |
7911 | case 24: | |
7912 | pipeconf |= PIPECONF_8BPC; | |
7913 | break; | |
7914 | case 30: | |
7915 | pipeconf |= PIPECONF_10BPC; | |
7916 | break; | |
7917 | default: | |
7918 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7919 | BUG(); | |
84b046f3 DV |
7920 | } |
7921 | } | |
7922 | ||
7923 | if (HAS_PIPE_CXSR(dev)) { | |
7924 | if (intel_crtc->lowfreq_avail) { | |
7925 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7926 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7927 | } else { | |
7928 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7929 | } |
7930 | } | |
7931 | ||
6e3c9717 | 7932 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7933 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7934 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7935 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7936 | else | |
7937 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7938 | } else | |
84b046f3 DV |
7939 | pipeconf |= PIPECONF_PROGRESSIVE; |
7940 | ||
666a4537 WB |
7941 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7942 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7943 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7944 | |
84b046f3 DV |
7945 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7946 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7947 | } | |
7948 | ||
190f68c5 ACO |
7949 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7950 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7951 | { |
c7653199 | 7952 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7953 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7954 | int refclk, num_connectors = 0; |
c329a4ec DV |
7955 | intel_clock_t clock; |
7956 | bool ok; | |
d4906093 | 7957 | const intel_limit_t *limit; |
55bb9992 | 7958 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7959 | struct drm_connector *connector; |
55bb9992 ACO |
7960 | struct drm_connector_state *connector_state; |
7961 | int i; | |
79e53945 | 7962 | |
dd3cd74a ACO |
7963 | memset(&crtc_state->dpll_hw_state, 0, |
7964 | sizeof(crtc_state->dpll_hw_state)); | |
7965 | ||
a65347ba JN |
7966 | if (crtc_state->has_dsi_encoder) |
7967 | return 0; | |
43565a06 | 7968 | |
a65347ba JN |
7969 | for_each_connector_in_state(state, connector, connector_state, i) { |
7970 | if (connector_state->crtc == &crtc->base) | |
7971 | num_connectors++; | |
79e53945 JB |
7972 | } |
7973 | ||
190f68c5 | 7974 | if (!crtc_state->clock_set) { |
a93e255f | 7975 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7976 | |
e9fd1c02 JN |
7977 | /* |
7978 | * Returns a set of divisors for the desired target clock with | |
7979 | * the given refclk, or FALSE. The returned values represent | |
7980 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7981 | * 2) / p1 / p2. | |
7982 | */ | |
a93e255f ACO |
7983 | limit = intel_limit(crtc_state, refclk); |
7984 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7985 | crtc_state->port_clock, |
e9fd1c02 | 7986 | refclk, NULL, &clock); |
f2335330 | 7987 | if (!ok) { |
e9fd1c02 JN |
7988 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7989 | return -EINVAL; | |
7990 | } | |
79e53945 | 7991 | |
f2335330 | 7992 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7993 | crtc_state->dpll.n = clock.n; |
7994 | crtc_state->dpll.m1 = clock.m1; | |
7995 | crtc_state->dpll.m2 = clock.m2; | |
7996 | crtc_state->dpll.p1 = clock.p1; | |
7997 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7998 | } |
7026d4ac | 7999 | |
e9fd1c02 | 8000 | if (IS_GEN2(dev)) { |
c329a4ec | 8001 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8002 | num_connectors); |
9d556c99 | 8003 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 8004 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8005 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 8006 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8007 | } else { |
c329a4ec | 8008 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8009 | num_connectors); |
e9fd1c02 | 8010 | } |
79e53945 | 8011 | |
c8f7a0db | 8012 | return 0; |
f564048e EA |
8013 | } |
8014 | ||
2fa2fe9a | 8015 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8016 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8017 | { |
8018 | struct drm_device *dev = crtc->base.dev; | |
8019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8020 | uint32_t tmp; | |
8021 | ||
dc9e7dec VS |
8022 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8023 | return; | |
8024 | ||
2fa2fe9a | 8025 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8026 | if (!(tmp & PFIT_ENABLE)) |
8027 | return; | |
2fa2fe9a | 8028 | |
06922821 | 8029 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8030 | if (INTEL_INFO(dev)->gen < 4) { |
8031 | if (crtc->pipe != PIPE_B) | |
8032 | return; | |
2fa2fe9a DV |
8033 | } else { |
8034 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8035 | return; | |
8036 | } | |
8037 | ||
06922821 | 8038 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8039 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8040 | if (INTEL_INFO(dev)->gen < 5) | |
8041 | pipe_config->gmch_pfit.lvds_border_bits = | |
8042 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8043 | } | |
8044 | ||
acbec814 | 8045 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8046 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8047 | { |
8048 | struct drm_device *dev = crtc->base.dev; | |
8049 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8050 | int pipe = pipe_config->cpu_transcoder; | |
8051 | intel_clock_t clock; | |
8052 | u32 mdiv; | |
662c6ecb | 8053 | int refclk = 100000; |
acbec814 | 8054 | |
f573de5a SK |
8055 | /* In case of MIPI DPLL will not even be used */ |
8056 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8057 | return; | |
8058 | ||
a580516d | 8059 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8060 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8061 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8062 | |
8063 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8064 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8065 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8066 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8067 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8068 | ||
dccbea3b | 8069 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8070 | } |
8071 | ||
5724dbd1 DL |
8072 | static void |
8073 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8074 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8075 | { |
8076 | struct drm_device *dev = crtc->base.dev; | |
8077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8078 | u32 val, base, offset; | |
8079 | int pipe = crtc->pipe, plane = crtc->plane; | |
8080 | int fourcc, pixel_format; | |
6761dd31 | 8081 | unsigned int aligned_height; |
b113d5ee | 8082 | struct drm_framebuffer *fb; |
1b842c89 | 8083 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8084 | |
42a7b088 DL |
8085 | val = I915_READ(DSPCNTR(plane)); |
8086 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8087 | return; | |
8088 | ||
d9806c9f | 8089 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8090 | if (!intel_fb) { |
1ad292b5 JB |
8091 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8092 | return; | |
8093 | } | |
8094 | ||
1b842c89 DL |
8095 | fb = &intel_fb->base; |
8096 | ||
18c5247e DV |
8097 | if (INTEL_INFO(dev)->gen >= 4) { |
8098 | if (val & DISPPLANE_TILED) { | |
49af449b | 8099 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8100 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8101 | } | |
8102 | } | |
1ad292b5 JB |
8103 | |
8104 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8105 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8106 | fb->pixel_format = fourcc; |
8107 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8108 | |
8109 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8110 | if (plane_config->tiling) |
1ad292b5 JB |
8111 | offset = I915_READ(DSPTILEOFF(plane)); |
8112 | else | |
8113 | offset = I915_READ(DSPLINOFF(plane)); | |
8114 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8115 | } else { | |
8116 | base = I915_READ(DSPADDR(plane)); | |
8117 | } | |
8118 | plane_config->base = base; | |
8119 | ||
8120 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8121 | fb->width = ((val >> 16) & 0xfff) + 1; |
8122 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8123 | |
8124 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8125 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8126 | |
b113d5ee | 8127 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8128 | fb->pixel_format, |
8129 | fb->modifier[0]); | |
1ad292b5 | 8130 | |
f37b5c2b | 8131 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8132 | |
2844a921 DL |
8133 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8134 | pipe_name(pipe), plane, fb->width, fb->height, | |
8135 | fb->bits_per_pixel, base, fb->pitches[0], | |
8136 | plane_config->size); | |
1ad292b5 | 8137 | |
2d14030b | 8138 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8139 | } |
8140 | ||
70b23a98 | 8141 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8142 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8143 | { |
8144 | struct drm_device *dev = crtc->base.dev; | |
8145 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8146 | int pipe = pipe_config->cpu_transcoder; | |
8147 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8148 | intel_clock_t clock; | |
0d7b6b11 | 8149 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8150 | int refclk = 100000; |
8151 | ||
a580516d | 8152 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8153 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8154 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8155 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8156 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8157 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8158 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8159 | |
8160 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8161 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8162 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8163 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8164 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8165 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8166 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8167 | ||
dccbea3b | 8168 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8169 | } |
8170 | ||
0e8ffe1b | 8171 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8172 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8173 | { |
8174 | struct drm_device *dev = crtc->base.dev; | |
8175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8176 | uint32_t tmp; | |
8177 | ||
f458ebbc DV |
8178 | if (!intel_display_power_is_enabled(dev_priv, |
8179 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8180 | return false; |
8181 | ||
e143a21c | 8182 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8183 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8184 | |
0e8ffe1b DV |
8185 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8186 | if (!(tmp & PIPECONF_ENABLE)) | |
8187 | return false; | |
8188 | ||
666a4537 | 8189 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8190 | switch (tmp & PIPECONF_BPC_MASK) { |
8191 | case PIPECONF_6BPC: | |
8192 | pipe_config->pipe_bpp = 18; | |
8193 | break; | |
8194 | case PIPECONF_8BPC: | |
8195 | pipe_config->pipe_bpp = 24; | |
8196 | break; | |
8197 | case PIPECONF_10BPC: | |
8198 | pipe_config->pipe_bpp = 30; | |
8199 | break; | |
8200 | default: | |
8201 | break; | |
8202 | } | |
8203 | } | |
8204 | ||
666a4537 WB |
8205 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8206 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8207 | pipe_config->limited_color_range = true; |
8208 | ||
282740f7 VS |
8209 | if (INTEL_INFO(dev)->gen < 4) |
8210 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8211 | ||
1bd1bd80 DV |
8212 | intel_get_pipe_timings(crtc, pipe_config); |
8213 | ||
2fa2fe9a DV |
8214 | i9xx_get_pfit_config(crtc, pipe_config); |
8215 | ||
6c49f241 DV |
8216 | if (INTEL_INFO(dev)->gen >= 4) { |
8217 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8218 | pipe_config->pixel_multiplier = | |
8219 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8220 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8221 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8222 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8223 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8224 | pipe_config->pixel_multiplier = | |
8225 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8226 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8227 | } else { | |
8228 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8229 | * port and will be fixed up in the encoder->get_config | |
8230 | * function. */ | |
8231 | pipe_config->pixel_multiplier = 1; | |
8232 | } | |
8bcc2795 | 8233 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8234 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8235 | /* |
8236 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8237 | * on 830. Filter it out here so that we don't | |
8238 | * report errors due to that. | |
8239 | */ | |
8240 | if (IS_I830(dev)) | |
8241 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8242 | ||
8bcc2795 DV |
8243 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8244 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8245 | } else { |
8246 | /* Mask out read-only status bits. */ | |
8247 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8248 | DPLL_PORTC_READY_MASK | | |
8249 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8250 | } |
6c49f241 | 8251 | |
70b23a98 VS |
8252 | if (IS_CHERRYVIEW(dev)) |
8253 | chv_crtc_clock_get(crtc, pipe_config); | |
8254 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8255 | vlv_crtc_clock_get(crtc, pipe_config); |
8256 | else | |
8257 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8258 | |
0f64614d VS |
8259 | /* |
8260 | * Normally the dotclock is filled in by the encoder .get_config() | |
8261 | * but in case the pipe is enabled w/o any ports we need a sane | |
8262 | * default. | |
8263 | */ | |
8264 | pipe_config->base.adjusted_mode.crtc_clock = | |
8265 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8266 | ||
0e8ffe1b DV |
8267 | return true; |
8268 | } | |
8269 | ||
dde86e2d | 8270 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8271 | { |
8272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8273 | struct intel_encoder *encoder; |
74cfd7ac | 8274 | u32 val, final; |
13d83a67 | 8275 | bool has_lvds = false; |
199e5d79 | 8276 | bool has_cpu_edp = false; |
199e5d79 | 8277 | bool has_panel = false; |
99eb6a01 KP |
8278 | bool has_ck505 = false; |
8279 | bool can_ssc = false; | |
13d83a67 JB |
8280 | |
8281 | /* We need to take the global config into account */ | |
b2784e15 | 8282 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8283 | switch (encoder->type) { |
8284 | case INTEL_OUTPUT_LVDS: | |
8285 | has_panel = true; | |
8286 | has_lvds = true; | |
8287 | break; | |
8288 | case INTEL_OUTPUT_EDP: | |
8289 | has_panel = true; | |
2de6905f | 8290 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8291 | has_cpu_edp = true; |
8292 | break; | |
6847d71b PZ |
8293 | default: |
8294 | break; | |
13d83a67 JB |
8295 | } |
8296 | } | |
8297 | ||
99eb6a01 | 8298 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8299 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8300 | can_ssc = has_ck505; |
8301 | } else { | |
8302 | has_ck505 = false; | |
8303 | can_ssc = true; | |
8304 | } | |
8305 | ||
2de6905f ID |
8306 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8307 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8308 | |
8309 | /* Ironlake: try to setup display ref clock before DPLL | |
8310 | * enabling. This is only under driver's control after | |
8311 | * PCH B stepping, previous chipset stepping should be | |
8312 | * ignoring this setting. | |
8313 | */ | |
74cfd7ac CW |
8314 | val = I915_READ(PCH_DREF_CONTROL); |
8315 | ||
8316 | /* As we must carefully and slowly disable/enable each source in turn, | |
8317 | * compute the final state we want first and check if we need to | |
8318 | * make any changes at all. | |
8319 | */ | |
8320 | final = val; | |
8321 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8322 | if (has_ck505) | |
8323 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8324 | else | |
8325 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8326 | ||
8327 | final &= ~DREF_SSC_SOURCE_MASK; | |
8328 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8329 | final &= ~DREF_SSC1_ENABLE; | |
8330 | ||
8331 | if (has_panel) { | |
8332 | final |= DREF_SSC_SOURCE_ENABLE; | |
8333 | ||
8334 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8335 | final |= DREF_SSC1_ENABLE; | |
8336 | ||
8337 | if (has_cpu_edp) { | |
8338 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8339 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8340 | else | |
8341 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8342 | } else | |
8343 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8344 | } else { | |
8345 | final |= DREF_SSC_SOURCE_DISABLE; | |
8346 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8347 | } | |
8348 | ||
8349 | if (final == val) | |
8350 | return; | |
8351 | ||
13d83a67 | 8352 | /* Always enable nonspread source */ |
74cfd7ac | 8353 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8354 | |
99eb6a01 | 8355 | if (has_ck505) |
74cfd7ac | 8356 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8357 | else |
74cfd7ac | 8358 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8359 | |
199e5d79 | 8360 | if (has_panel) { |
74cfd7ac CW |
8361 | val &= ~DREF_SSC_SOURCE_MASK; |
8362 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8363 | |
199e5d79 | 8364 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8365 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8366 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8367 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8368 | } else |
74cfd7ac | 8369 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8370 | |
8371 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8372 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8373 | POSTING_READ(PCH_DREF_CONTROL); |
8374 | udelay(200); | |
8375 | ||
74cfd7ac | 8376 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8377 | |
8378 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8379 | if (has_cpu_edp) { |
99eb6a01 | 8380 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8381 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8382 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8383 | } else |
74cfd7ac | 8384 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8385 | } else |
74cfd7ac | 8386 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8387 | |
74cfd7ac | 8388 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8389 | POSTING_READ(PCH_DREF_CONTROL); |
8390 | udelay(200); | |
8391 | } else { | |
8392 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8393 | ||
74cfd7ac | 8394 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8395 | |
8396 | /* Turn off CPU output */ | |
74cfd7ac | 8397 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8398 | |
74cfd7ac | 8399 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8400 | POSTING_READ(PCH_DREF_CONTROL); |
8401 | udelay(200); | |
8402 | ||
8403 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8404 | val &= ~DREF_SSC_SOURCE_MASK; |
8405 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8406 | |
8407 | /* Turn off SSC1 */ | |
74cfd7ac | 8408 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8409 | |
74cfd7ac | 8410 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8411 | POSTING_READ(PCH_DREF_CONTROL); |
8412 | udelay(200); | |
8413 | } | |
74cfd7ac CW |
8414 | |
8415 | BUG_ON(val != final); | |
13d83a67 JB |
8416 | } |
8417 | ||
f31f2d55 | 8418 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8419 | { |
f31f2d55 | 8420 | uint32_t tmp; |
dde86e2d | 8421 | |
0ff066a9 PZ |
8422 | tmp = I915_READ(SOUTH_CHICKEN2); |
8423 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8424 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8425 | |
0ff066a9 PZ |
8426 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8427 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8428 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8429 | |
0ff066a9 PZ |
8430 | tmp = I915_READ(SOUTH_CHICKEN2); |
8431 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8432 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8433 | |
0ff066a9 PZ |
8434 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8435 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8436 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8437 | } |
8438 | ||
8439 | /* WaMPhyProgramming:hsw */ | |
8440 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8441 | { | |
8442 | uint32_t tmp; | |
dde86e2d PZ |
8443 | |
8444 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8445 | tmp &= ~(0xFF << 24); | |
8446 | tmp |= (0x12 << 24); | |
8447 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8448 | ||
dde86e2d PZ |
8449 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8450 | tmp |= (1 << 11); | |
8451 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8452 | ||
8453 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8454 | tmp |= (1 << 11); | |
8455 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8456 | ||
dde86e2d PZ |
8457 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8458 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8459 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8460 | ||
8461 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8462 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8463 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8464 | ||
0ff066a9 PZ |
8465 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8466 | tmp &= ~(7 << 13); | |
8467 | tmp |= (5 << 13); | |
8468 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8469 | |
0ff066a9 PZ |
8470 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8471 | tmp &= ~(7 << 13); | |
8472 | tmp |= (5 << 13); | |
8473 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8474 | |
8475 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8476 | tmp &= ~0xFF; | |
8477 | tmp |= 0x1C; | |
8478 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8479 | ||
8480 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8481 | tmp &= ~0xFF; | |
8482 | tmp |= 0x1C; | |
8483 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8484 | ||
8485 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8486 | tmp &= ~(0xFF << 16); | |
8487 | tmp |= (0x1C << 16); | |
8488 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8489 | ||
8490 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8491 | tmp &= ~(0xFF << 16); | |
8492 | tmp |= (0x1C << 16); | |
8493 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8494 | ||
0ff066a9 PZ |
8495 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8496 | tmp |= (1 << 27); | |
8497 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8498 | |
0ff066a9 PZ |
8499 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8500 | tmp |= (1 << 27); | |
8501 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8502 | |
0ff066a9 PZ |
8503 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8504 | tmp &= ~(0xF << 28); | |
8505 | tmp |= (4 << 28); | |
8506 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8507 | |
0ff066a9 PZ |
8508 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8509 | tmp &= ~(0xF << 28); | |
8510 | tmp |= (4 << 28); | |
8511 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8512 | } |
8513 | ||
2fa86a1f PZ |
8514 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8515 | * Programming" based on the parameters passed: | |
8516 | * - Sequence to enable CLKOUT_DP | |
8517 | * - Sequence to enable CLKOUT_DP without spread | |
8518 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8519 | */ | |
8520 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8521 | bool with_fdi) | |
f31f2d55 PZ |
8522 | { |
8523 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8524 | uint32_t reg, tmp; |
8525 | ||
8526 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8527 | with_spread = true; | |
c2699524 | 8528 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8529 | with_fdi = false; |
f31f2d55 | 8530 | |
a580516d | 8531 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8532 | |
8533 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8534 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8535 | tmp |= SBI_SSCCTL_PATHALT; | |
8536 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8537 | ||
8538 | udelay(24); | |
8539 | ||
2fa86a1f PZ |
8540 | if (with_spread) { |
8541 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8542 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8543 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8544 | |
2fa86a1f PZ |
8545 | if (with_fdi) { |
8546 | lpt_reset_fdi_mphy(dev_priv); | |
8547 | lpt_program_fdi_mphy(dev_priv); | |
8548 | } | |
8549 | } | |
dde86e2d | 8550 | |
c2699524 | 8551 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8552 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8553 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8554 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8555 | |
a580516d | 8556 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8557 | } |
8558 | ||
47701c3b PZ |
8559 | /* Sequence to disable CLKOUT_DP */ |
8560 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8561 | { | |
8562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8563 | uint32_t reg, tmp; | |
8564 | ||
a580516d | 8565 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8566 | |
c2699524 | 8567 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8568 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8569 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8570 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8571 | ||
8572 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8573 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8574 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8575 | tmp |= SBI_SSCCTL_PATHALT; | |
8576 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8577 | udelay(32); | |
8578 | } | |
8579 | tmp |= SBI_SSCCTL_DISABLE; | |
8580 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8581 | } | |
8582 | ||
a580516d | 8583 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8584 | } |
8585 | ||
f7be2c21 VS |
8586 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8587 | ||
8588 | static const uint16_t sscdivintphase[] = { | |
8589 | [BEND_IDX( 50)] = 0x3B23, | |
8590 | [BEND_IDX( 45)] = 0x3B23, | |
8591 | [BEND_IDX( 40)] = 0x3C23, | |
8592 | [BEND_IDX( 35)] = 0x3C23, | |
8593 | [BEND_IDX( 30)] = 0x3D23, | |
8594 | [BEND_IDX( 25)] = 0x3D23, | |
8595 | [BEND_IDX( 20)] = 0x3E23, | |
8596 | [BEND_IDX( 15)] = 0x3E23, | |
8597 | [BEND_IDX( 10)] = 0x3F23, | |
8598 | [BEND_IDX( 5)] = 0x3F23, | |
8599 | [BEND_IDX( 0)] = 0x0025, | |
8600 | [BEND_IDX( -5)] = 0x0025, | |
8601 | [BEND_IDX(-10)] = 0x0125, | |
8602 | [BEND_IDX(-15)] = 0x0125, | |
8603 | [BEND_IDX(-20)] = 0x0225, | |
8604 | [BEND_IDX(-25)] = 0x0225, | |
8605 | [BEND_IDX(-30)] = 0x0325, | |
8606 | [BEND_IDX(-35)] = 0x0325, | |
8607 | [BEND_IDX(-40)] = 0x0425, | |
8608 | [BEND_IDX(-45)] = 0x0425, | |
8609 | [BEND_IDX(-50)] = 0x0525, | |
8610 | }; | |
8611 | ||
8612 | /* | |
8613 | * Bend CLKOUT_DP | |
8614 | * steps -50 to 50 inclusive, in steps of 5 | |
8615 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8616 | * change in clock period = -(steps / 10) * 5.787 ps | |
8617 | */ | |
8618 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8619 | { | |
8620 | uint32_t tmp; | |
8621 | int idx = BEND_IDX(steps); | |
8622 | ||
8623 | if (WARN_ON(steps % 5 != 0)) | |
8624 | return; | |
8625 | ||
8626 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8627 | return; | |
8628 | ||
8629 | mutex_lock(&dev_priv->sb_lock); | |
8630 | ||
8631 | if (steps % 10 != 0) | |
8632 | tmp = 0xAAAAAAAB; | |
8633 | else | |
8634 | tmp = 0x00000000; | |
8635 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8636 | ||
8637 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8638 | tmp &= 0xffff0000; | |
8639 | tmp |= sscdivintphase[idx]; | |
8640 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8641 | ||
8642 | mutex_unlock(&dev_priv->sb_lock); | |
8643 | } | |
8644 | ||
8645 | #undef BEND_IDX | |
8646 | ||
bf8fa3d3 PZ |
8647 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8648 | { | |
bf8fa3d3 PZ |
8649 | struct intel_encoder *encoder; |
8650 | bool has_vga = false; | |
8651 | ||
b2784e15 | 8652 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8653 | switch (encoder->type) { |
8654 | case INTEL_OUTPUT_ANALOG: | |
8655 | has_vga = true; | |
8656 | break; | |
6847d71b PZ |
8657 | default: |
8658 | break; | |
bf8fa3d3 PZ |
8659 | } |
8660 | } | |
8661 | ||
f7be2c21 VS |
8662 | if (has_vga) { |
8663 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8664 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8665 | } else { |
47701c3b | 8666 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8667 | } |
bf8fa3d3 PZ |
8668 | } |
8669 | ||
dde86e2d PZ |
8670 | /* |
8671 | * Initialize reference clocks when the driver loads | |
8672 | */ | |
8673 | void intel_init_pch_refclk(struct drm_device *dev) | |
8674 | { | |
8675 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8676 | ironlake_init_pch_refclk(dev); | |
8677 | else if (HAS_PCH_LPT(dev)) | |
8678 | lpt_init_pch_refclk(dev); | |
8679 | } | |
8680 | ||
55bb9992 | 8681 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8682 | { |
55bb9992 | 8683 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8684 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8685 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8686 | struct drm_connector *connector; |
55bb9992 | 8687 | struct drm_connector_state *connector_state; |
d9d444cb | 8688 | struct intel_encoder *encoder; |
55bb9992 | 8689 | int num_connectors = 0, i; |
d9d444cb JB |
8690 | bool is_lvds = false; |
8691 | ||
da3ced29 | 8692 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8693 | if (connector_state->crtc != crtc_state->base.crtc) |
8694 | continue; | |
8695 | ||
8696 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8697 | ||
d9d444cb JB |
8698 | switch (encoder->type) { |
8699 | case INTEL_OUTPUT_LVDS: | |
8700 | is_lvds = true; | |
8701 | break; | |
6847d71b PZ |
8702 | default: |
8703 | break; | |
d9d444cb JB |
8704 | } |
8705 | num_connectors++; | |
8706 | } | |
8707 | ||
8708 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8709 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8710 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8711 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8712 | } |
8713 | ||
8714 | return 120000; | |
8715 | } | |
8716 | ||
6ff93609 | 8717 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8718 | { |
c8203565 | 8719 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8720 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8721 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8722 | uint32_t val; |
8723 | ||
78114071 | 8724 | val = 0; |
c8203565 | 8725 | |
6e3c9717 | 8726 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8727 | case 18: |
dfd07d72 | 8728 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8729 | break; |
8730 | case 24: | |
dfd07d72 | 8731 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8732 | break; |
8733 | case 30: | |
dfd07d72 | 8734 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8735 | break; |
8736 | case 36: | |
dfd07d72 | 8737 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8738 | break; |
8739 | default: | |
cc769b62 PZ |
8740 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8741 | BUG(); | |
c8203565 PZ |
8742 | } |
8743 | ||
6e3c9717 | 8744 | if (intel_crtc->config->dither) |
c8203565 PZ |
8745 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8746 | ||
6e3c9717 | 8747 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8748 | val |= PIPECONF_INTERLACED_ILK; |
8749 | else | |
8750 | val |= PIPECONF_PROGRESSIVE; | |
8751 | ||
6e3c9717 | 8752 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8753 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8754 | |
c8203565 PZ |
8755 | I915_WRITE(PIPECONF(pipe), val); |
8756 | POSTING_READ(PIPECONF(pipe)); | |
8757 | } | |
8758 | ||
86d3efce VS |
8759 | /* |
8760 | * Set up the pipe CSC unit. | |
8761 | * | |
8762 | * Currently only full range RGB to limited range RGB conversion | |
8763 | * is supported, but eventually this should handle various | |
8764 | * RGB<->YCbCr scenarios as well. | |
8765 | */ | |
50f3b016 | 8766 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8767 | { |
8768 | struct drm_device *dev = crtc->dev; | |
8769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8770 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8771 | int pipe = intel_crtc->pipe; | |
8772 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8773 | ||
8774 | /* | |
8775 | * TODO: Check what kind of values actually come out of the pipe | |
8776 | * with these coeff/postoff values and adjust to get the best | |
8777 | * accuracy. Perhaps we even need to take the bpc value into | |
8778 | * consideration. | |
8779 | */ | |
8780 | ||
6e3c9717 | 8781 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8782 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8783 | ||
8784 | /* | |
8785 | * GY/GU and RY/RU should be the other way around according | |
8786 | * to BSpec, but reality doesn't agree. Just set them up in | |
8787 | * a way that results in the correct picture. | |
8788 | */ | |
8789 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8790 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8791 | ||
8792 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8793 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8794 | ||
8795 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8796 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8797 | ||
8798 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8799 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8800 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8801 | ||
8802 | if (INTEL_INFO(dev)->gen > 6) { | |
8803 | uint16_t postoff = 0; | |
8804 | ||
6e3c9717 | 8805 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8806 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8807 | |
8808 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8809 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8810 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8811 | ||
8812 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8813 | } else { | |
8814 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8815 | ||
6e3c9717 | 8816 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8817 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8818 | ||
8819 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8820 | } | |
8821 | } | |
8822 | ||
6ff93609 | 8823 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8824 | { |
756f85cf PZ |
8825 | struct drm_device *dev = crtc->dev; |
8826 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8827 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8828 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8829 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8830 | uint32_t val; |
8831 | ||
3eff4faa | 8832 | val = 0; |
ee2b0b38 | 8833 | |
6e3c9717 | 8834 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8835 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8836 | ||
6e3c9717 | 8837 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8838 | val |= PIPECONF_INTERLACED_ILK; |
8839 | else | |
8840 | val |= PIPECONF_PROGRESSIVE; | |
8841 | ||
702e7a56 PZ |
8842 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8843 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8844 | |
8845 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8846 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8847 | |
3cdf122c | 8848 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8849 | val = 0; |
8850 | ||
6e3c9717 | 8851 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8852 | case 18: |
8853 | val |= PIPEMISC_DITHER_6_BPC; | |
8854 | break; | |
8855 | case 24: | |
8856 | val |= PIPEMISC_DITHER_8_BPC; | |
8857 | break; | |
8858 | case 30: | |
8859 | val |= PIPEMISC_DITHER_10_BPC; | |
8860 | break; | |
8861 | case 36: | |
8862 | val |= PIPEMISC_DITHER_12_BPC; | |
8863 | break; | |
8864 | default: | |
8865 | /* Case prevented by pipe_config_set_bpp. */ | |
8866 | BUG(); | |
8867 | } | |
8868 | ||
6e3c9717 | 8869 | if (intel_crtc->config->dither) |
756f85cf PZ |
8870 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8871 | ||
8872 | I915_WRITE(PIPEMISC(pipe), val); | |
8873 | } | |
ee2b0b38 PZ |
8874 | } |
8875 | ||
6591c6e4 | 8876 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8877 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8878 | intel_clock_t *clock, |
8879 | bool *has_reduced_clock, | |
8880 | intel_clock_t *reduced_clock) | |
8881 | { | |
8882 | struct drm_device *dev = crtc->dev; | |
8883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8884 | int refclk; |
d4906093 | 8885 | const intel_limit_t *limit; |
c329a4ec | 8886 | bool ret; |
79e53945 | 8887 | |
55bb9992 | 8888 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8889 | |
d4906093 ML |
8890 | /* |
8891 | * Returns a set of divisors for the desired target clock with the given | |
8892 | * refclk, or FALSE. The returned values represent the clock equation: | |
8893 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8894 | */ | |
a93e255f ACO |
8895 | limit = intel_limit(crtc_state, refclk); |
8896 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8897 | crtc_state->port_clock, |
ee9300bb | 8898 | refclk, NULL, clock); |
6591c6e4 PZ |
8899 | if (!ret) |
8900 | return false; | |
cda4b7d3 | 8901 | |
6591c6e4 PZ |
8902 | return true; |
8903 | } | |
8904 | ||
d4b1931c PZ |
8905 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8906 | { | |
8907 | /* | |
8908 | * Account for spread spectrum to avoid | |
8909 | * oversubscribing the link. Max center spread | |
8910 | * is 2.5%; use 5% for safety's sake. | |
8911 | */ | |
8912 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8913 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8914 | } |
8915 | ||
7429e9d4 | 8916 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8917 | { |
7429e9d4 | 8918 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8919 | } |
8920 | ||
de13a2e3 | 8921 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8922 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8923 | u32 *fp, |
9a7c7890 | 8924 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8925 | { |
de13a2e3 | 8926 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8927 | struct drm_device *dev = crtc->dev; |
8928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8929 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8930 | struct drm_connector *connector; |
55bb9992 ACO |
8931 | struct drm_connector_state *connector_state; |
8932 | struct intel_encoder *encoder; | |
de13a2e3 | 8933 | uint32_t dpll; |
55bb9992 | 8934 | int factor, num_connectors = 0, i; |
09ede541 | 8935 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8936 | |
da3ced29 | 8937 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8938 | if (connector_state->crtc != crtc_state->base.crtc) |
8939 | continue; | |
8940 | ||
8941 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8942 | ||
8943 | switch (encoder->type) { | |
79e53945 JB |
8944 | case INTEL_OUTPUT_LVDS: |
8945 | is_lvds = true; | |
8946 | break; | |
8947 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8948 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8949 | is_sdvo = true; |
79e53945 | 8950 | break; |
6847d71b PZ |
8951 | default: |
8952 | break; | |
79e53945 | 8953 | } |
43565a06 | 8954 | |
c751ce4f | 8955 | num_connectors++; |
79e53945 | 8956 | } |
79e53945 | 8957 | |
c1858123 | 8958 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8959 | factor = 21; |
8960 | if (is_lvds) { | |
8961 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8962 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8963 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8964 | factor = 25; |
190f68c5 | 8965 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8966 | factor = 20; |
c1858123 | 8967 | |
190f68c5 | 8968 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8969 | *fp |= FP_CB_TUNE; |
2c07245f | 8970 | |
9a7c7890 DV |
8971 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8972 | *fp2 |= FP_CB_TUNE; | |
8973 | ||
5eddb70b | 8974 | dpll = 0; |
2c07245f | 8975 | |
a07d6787 EA |
8976 | if (is_lvds) |
8977 | dpll |= DPLLB_MODE_LVDS; | |
8978 | else | |
8979 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8980 | |
190f68c5 | 8981 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8982 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8983 | |
8984 | if (is_sdvo) | |
4a33e48d | 8985 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8986 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8987 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8988 | |
a07d6787 | 8989 | /* compute bitmask from p1 value */ |
190f68c5 | 8990 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8991 | /* also FPA1 */ |
190f68c5 | 8992 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8993 | |
190f68c5 | 8994 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8995 | case 5: |
8996 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8997 | break; | |
8998 | case 7: | |
8999 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9000 | break; | |
9001 | case 10: | |
9002 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9003 | break; | |
9004 | case 14: | |
9005 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9006 | break; | |
79e53945 JB |
9007 | } |
9008 | ||
b4c09f3b | 9009 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 9010 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9011 | else |
9012 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9013 | ||
959e16d6 | 9014 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
9015 | } |
9016 | ||
190f68c5 ACO |
9017 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9018 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9019 | { |
c7653199 | 9020 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 9021 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 9022 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 9023 | bool ok, has_reduced_clock = false; |
8b47047b | 9024 | bool is_lvds = false; |
e2b78267 | 9025 | struct intel_shared_dpll *pll; |
de13a2e3 | 9026 | |
dd3cd74a ACO |
9027 | memset(&crtc_state->dpll_hw_state, 0, |
9028 | sizeof(crtc_state->dpll_hw_state)); | |
9029 | ||
7905df29 | 9030 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 9031 | |
5dc5298b PZ |
9032 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
9033 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 9034 | |
190f68c5 | 9035 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 9036 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 9037 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
9038 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9039 | return -EINVAL; | |
79e53945 | 9040 | } |
f47709a9 | 9041 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9042 | if (!crtc_state->clock_set) { |
9043 | crtc_state->dpll.n = clock.n; | |
9044 | crtc_state->dpll.m1 = clock.m1; | |
9045 | crtc_state->dpll.m2 = clock.m2; | |
9046 | crtc_state->dpll.p1 = clock.p1; | |
9047 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9048 | } |
79e53945 | 9049 | |
5dc5298b | 9050 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9051 | if (crtc_state->has_pch_encoder) { |
9052 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9053 | if (has_reduced_clock) |
7429e9d4 | 9054 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9055 | |
190f68c5 | 9056 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9057 | &fp, &reduced_clock, |
9058 | has_reduced_clock ? &fp2 : NULL); | |
9059 | ||
190f68c5 ACO |
9060 | crtc_state->dpll_hw_state.dpll = dpll; |
9061 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9062 | if (has_reduced_clock) |
190f68c5 | 9063 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9064 | else |
190f68c5 | 9065 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9066 | |
190f68c5 | 9067 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9068 | if (pll == NULL) { |
84f44ce7 | 9069 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9070 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9071 | return -EINVAL; |
9072 | } | |
3fb37703 | 9073 | } |
79e53945 | 9074 | |
ab585dea | 9075 | if (is_lvds && has_reduced_clock) |
c7653199 | 9076 | crtc->lowfreq_avail = true; |
bcd644e0 | 9077 | else |
c7653199 | 9078 | crtc->lowfreq_avail = false; |
e2b78267 | 9079 | |
c8f7a0db | 9080 | return 0; |
79e53945 JB |
9081 | } |
9082 | ||
eb14cb74 VS |
9083 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9084 | struct intel_link_m_n *m_n) | |
9085 | { | |
9086 | struct drm_device *dev = crtc->base.dev; | |
9087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9088 | enum pipe pipe = crtc->pipe; | |
9089 | ||
9090 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9091 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9092 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9093 | & ~TU_SIZE_MASK; | |
9094 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9095 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9096 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9097 | } | |
9098 | ||
9099 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9100 | enum transcoder transcoder, | |
b95af8be VK |
9101 | struct intel_link_m_n *m_n, |
9102 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9103 | { |
9104 | struct drm_device *dev = crtc->base.dev; | |
9105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9106 | enum pipe pipe = crtc->pipe; |
72419203 | 9107 | |
eb14cb74 VS |
9108 | if (INTEL_INFO(dev)->gen >= 5) { |
9109 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9110 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9111 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9112 | & ~TU_SIZE_MASK; | |
9113 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9114 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9115 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9116 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9117 | * gen < 8) and if DRRS is supported (to make sure the | |
9118 | * registers are not unnecessarily read). | |
9119 | */ | |
9120 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9121 | crtc->config->has_drrs) { |
b95af8be VK |
9122 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9123 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9124 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9125 | & ~TU_SIZE_MASK; | |
9126 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9127 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9128 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9129 | } | |
eb14cb74 VS |
9130 | } else { |
9131 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9132 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9133 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9134 | & ~TU_SIZE_MASK; | |
9135 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9136 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9137 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9138 | } | |
9139 | } | |
9140 | ||
9141 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9142 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9143 | { |
681a8504 | 9144 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9145 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9146 | else | |
9147 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9148 | &pipe_config->dp_m_n, |
9149 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9150 | } |
72419203 | 9151 | |
eb14cb74 | 9152 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9153 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9154 | { |
9155 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9156 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9157 | } |
9158 | ||
bd2e244f | 9159 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9160 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9161 | { |
9162 | struct drm_device *dev = crtc->base.dev; | |
9163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9164 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9165 | uint32_t ps_ctrl = 0; | |
9166 | int id = -1; | |
9167 | int i; | |
bd2e244f | 9168 | |
a1b2278e CK |
9169 | /* find scaler attached to this pipe */ |
9170 | for (i = 0; i < crtc->num_scalers; i++) { | |
9171 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9172 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9173 | id = i; | |
9174 | pipe_config->pch_pfit.enabled = true; | |
9175 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9176 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9177 | break; | |
9178 | } | |
9179 | } | |
bd2e244f | 9180 | |
a1b2278e CK |
9181 | scaler_state->scaler_id = id; |
9182 | if (id >= 0) { | |
9183 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9184 | } else { | |
9185 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9186 | } |
9187 | } | |
9188 | ||
5724dbd1 DL |
9189 | static void |
9190 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9191 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9192 | { |
9193 | struct drm_device *dev = crtc->base.dev; | |
9194 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9195 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9196 | int pipe = crtc->pipe; |
9197 | int fourcc, pixel_format; | |
6761dd31 | 9198 | unsigned int aligned_height; |
bc8d7dff | 9199 | struct drm_framebuffer *fb; |
1b842c89 | 9200 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9201 | |
d9806c9f | 9202 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9203 | if (!intel_fb) { |
bc8d7dff DL |
9204 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9205 | return; | |
9206 | } | |
9207 | ||
1b842c89 DL |
9208 | fb = &intel_fb->base; |
9209 | ||
bc8d7dff | 9210 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9211 | if (!(val & PLANE_CTL_ENABLE)) |
9212 | goto error; | |
9213 | ||
bc8d7dff DL |
9214 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9215 | fourcc = skl_format_to_fourcc(pixel_format, | |
9216 | val & PLANE_CTL_ORDER_RGBX, | |
9217 | val & PLANE_CTL_ALPHA_MASK); | |
9218 | fb->pixel_format = fourcc; | |
9219 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9220 | ||
40f46283 DL |
9221 | tiling = val & PLANE_CTL_TILED_MASK; |
9222 | switch (tiling) { | |
9223 | case PLANE_CTL_TILED_LINEAR: | |
9224 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9225 | break; | |
9226 | case PLANE_CTL_TILED_X: | |
9227 | plane_config->tiling = I915_TILING_X; | |
9228 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9229 | break; | |
9230 | case PLANE_CTL_TILED_Y: | |
9231 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9232 | break; | |
9233 | case PLANE_CTL_TILED_YF: | |
9234 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9235 | break; | |
9236 | default: | |
9237 | MISSING_CASE(tiling); | |
9238 | goto error; | |
9239 | } | |
9240 | ||
bc8d7dff DL |
9241 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9242 | plane_config->base = base; | |
9243 | ||
9244 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9245 | ||
9246 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9247 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9248 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9249 | ||
9250 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
9251 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9252 | fb->pixel_format); | |
bc8d7dff DL |
9253 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9254 | ||
9255 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9256 | fb->pixel_format, |
9257 | fb->modifier[0]); | |
bc8d7dff | 9258 | |
f37b5c2b | 9259 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9260 | |
9261 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9262 | pipe_name(pipe), fb->width, fb->height, | |
9263 | fb->bits_per_pixel, base, fb->pitches[0], | |
9264 | plane_config->size); | |
9265 | ||
2d14030b | 9266 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9267 | return; |
9268 | ||
9269 | error: | |
9270 | kfree(fb); | |
9271 | } | |
9272 | ||
2fa2fe9a | 9273 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9274 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9275 | { |
9276 | struct drm_device *dev = crtc->base.dev; | |
9277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9278 | uint32_t tmp; | |
9279 | ||
9280 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9281 | ||
9282 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9283 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9284 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9285 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9286 | |
9287 | /* We currently do not free assignements of panel fitters on | |
9288 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9289 | * differentiates them) so just WARN about this case for now. */ | |
9290 | if (IS_GEN7(dev)) { | |
9291 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9292 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9293 | } | |
2fa2fe9a | 9294 | } |
79e53945 JB |
9295 | } |
9296 | ||
5724dbd1 DL |
9297 | static void |
9298 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9299 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9300 | { |
9301 | struct drm_device *dev = crtc->base.dev; | |
9302 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9303 | u32 val, base, offset; | |
aeee5a49 | 9304 | int pipe = crtc->pipe; |
4c6baa59 | 9305 | int fourcc, pixel_format; |
6761dd31 | 9306 | unsigned int aligned_height; |
b113d5ee | 9307 | struct drm_framebuffer *fb; |
1b842c89 | 9308 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9309 | |
42a7b088 DL |
9310 | val = I915_READ(DSPCNTR(pipe)); |
9311 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9312 | return; | |
9313 | ||
d9806c9f | 9314 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9315 | if (!intel_fb) { |
4c6baa59 JB |
9316 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9317 | return; | |
9318 | } | |
9319 | ||
1b842c89 DL |
9320 | fb = &intel_fb->base; |
9321 | ||
18c5247e DV |
9322 | if (INTEL_INFO(dev)->gen >= 4) { |
9323 | if (val & DISPPLANE_TILED) { | |
49af449b | 9324 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9325 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9326 | } | |
9327 | } | |
4c6baa59 JB |
9328 | |
9329 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9330 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9331 | fb->pixel_format = fourcc; |
9332 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9333 | |
aeee5a49 | 9334 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9335 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9336 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9337 | } else { |
49af449b | 9338 | if (plane_config->tiling) |
aeee5a49 | 9339 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9340 | else |
aeee5a49 | 9341 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9342 | } |
9343 | plane_config->base = base; | |
9344 | ||
9345 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9346 | fb->width = ((val >> 16) & 0xfff) + 1; |
9347 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9348 | |
9349 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9350 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9351 | |
b113d5ee | 9352 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9353 | fb->pixel_format, |
9354 | fb->modifier[0]); | |
4c6baa59 | 9355 | |
f37b5c2b | 9356 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9357 | |
2844a921 DL |
9358 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9359 | pipe_name(pipe), fb->width, fb->height, | |
9360 | fb->bits_per_pixel, base, fb->pitches[0], | |
9361 | plane_config->size); | |
b113d5ee | 9362 | |
2d14030b | 9363 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9364 | } |
9365 | ||
0e8ffe1b | 9366 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9367 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9368 | { |
9369 | struct drm_device *dev = crtc->base.dev; | |
9370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9371 | uint32_t tmp; | |
9372 | ||
f458ebbc DV |
9373 | if (!intel_display_power_is_enabled(dev_priv, |
9374 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9375 | return false; |
9376 | ||
e143a21c | 9377 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9378 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9379 | |
0e8ffe1b DV |
9380 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9381 | if (!(tmp & PIPECONF_ENABLE)) | |
9382 | return false; | |
9383 | ||
42571aef VS |
9384 | switch (tmp & PIPECONF_BPC_MASK) { |
9385 | case PIPECONF_6BPC: | |
9386 | pipe_config->pipe_bpp = 18; | |
9387 | break; | |
9388 | case PIPECONF_8BPC: | |
9389 | pipe_config->pipe_bpp = 24; | |
9390 | break; | |
9391 | case PIPECONF_10BPC: | |
9392 | pipe_config->pipe_bpp = 30; | |
9393 | break; | |
9394 | case PIPECONF_12BPC: | |
9395 | pipe_config->pipe_bpp = 36; | |
9396 | break; | |
9397 | default: | |
9398 | break; | |
9399 | } | |
9400 | ||
b5a9fa09 DV |
9401 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9402 | pipe_config->limited_color_range = true; | |
9403 | ||
ab9412ba | 9404 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9405 | struct intel_shared_dpll *pll; |
9406 | ||
88adfff1 DV |
9407 | pipe_config->has_pch_encoder = true; |
9408 | ||
627eb5a3 DV |
9409 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9410 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9411 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9412 | |
9413 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9414 | |
c0d43d62 | 9415 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9416 | pipe_config->shared_dpll = |
9417 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9418 | } else { |
9419 | tmp = I915_READ(PCH_DPLL_SEL); | |
9420 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9421 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9422 | else | |
9423 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9424 | } | |
66e985c0 DV |
9425 | |
9426 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9427 | ||
9428 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9429 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9430 | |
9431 | tmp = pipe_config->dpll_hw_state.dpll; | |
9432 | pipe_config->pixel_multiplier = | |
9433 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9434 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9435 | |
9436 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9437 | } else { |
9438 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9439 | } |
9440 | ||
1bd1bd80 DV |
9441 | intel_get_pipe_timings(crtc, pipe_config); |
9442 | ||
2fa2fe9a DV |
9443 | ironlake_get_pfit_config(crtc, pipe_config); |
9444 | ||
0e8ffe1b DV |
9445 | return true; |
9446 | } | |
9447 | ||
be256dc7 PZ |
9448 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9449 | { | |
9450 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9451 | struct intel_crtc *crtc; |
be256dc7 | 9452 | |
d3fcc808 | 9453 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9454 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9455 | pipe_name(crtc->pipe)); |
9456 | ||
e2c719b7 RC |
9457 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9458 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9459 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9460 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9461 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9462 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9463 | "CPU PWM1 enabled\n"); |
c5107b87 | 9464 | if (IS_HASWELL(dev)) |
e2c719b7 | 9465 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9466 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9467 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9468 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9469 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9470 | "Utility pin enabled\n"); |
e2c719b7 | 9471 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9472 | |
9926ada1 PZ |
9473 | /* |
9474 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9475 | * interrupts remain enabled. We used to check for that, but since it's | |
9476 | * gen-specific and since we only disable LCPLL after we fully disable | |
9477 | * the interrupts, the check below should be enough. | |
9478 | */ | |
e2c719b7 | 9479 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9480 | } |
9481 | ||
9ccd5aeb PZ |
9482 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9483 | { | |
9484 | struct drm_device *dev = dev_priv->dev; | |
9485 | ||
9486 | if (IS_HASWELL(dev)) | |
9487 | return I915_READ(D_COMP_HSW); | |
9488 | else | |
9489 | return I915_READ(D_COMP_BDW); | |
9490 | } | |
9491 | ||
3c4c9b81 PZ |
9492 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9493 | { | |
9494 | struct drm_device *dev = dev_priv->dev; | |
9495 | ||
9496 | if (IS_HASWELL(dev)) { | |
9497 | mutex_lock(&dev_priv->rps.hw_lock); | |
9498 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9499 | val)) | |
f475dadf | 9500 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9501 | mutex_unlock(&dev_priv->rps.hw_lock); |
9502 | } else { | |
9ccd5aeb PZ |
9503 | I915_WRITE(D_COMP_BDW, val); |
9504 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9505 | } |
be256dc7 PZ |
9506 | } |
9507 | ||
9508 | /* | |
9509 | * This function implements pieces of two sequences from BSpec: | |
9510 | * - Sequence for display software to disable LCPLL | |
9511 | * - Sequence for display software to allow package C8+ | |
9512 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9513 | * register. Callers should take care of disabling all the display engine | |
9514 | * functions, doing the mode unset, fixing interrupts, etc. | |
9515 | */ | |
6ff58d53 PZ |
9516 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9517 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9518 | { |
9519 | uint32_t val; | |
9520 | ||
9521 | assert_can_disable_lcpll(dev_priv); | |
9522 | ||
9523 | val = I915_READ(LCPLL_CTL); | |
9524 | ||
9525 | if (switch_to_fclk) { | |
9526 | val |= LCPLL_CD_SOURCE_FCLK; | |
9527 | I915_WRITE(LCPLL_CTL, val); | |
9528 | ||
9529 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9530 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9531 | DRM_ERROR("Switching to FCLK failed\n"); | |
9532 | ||
9533 | val = I915_READ(LCPLL_CTL); | |
9534 | } | |
9535 | ||
9536 | val |= LCPLL_PLL_DISABLE; | |
9537 | I915_WRITE(LCPLL_CTL, val); | |
9538 | POSTING_READ(LCPLL_CTL); | |
9539 | ||
9540 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9541 | DRM_ERROR("LCPLL still locked\n"); | |
9542 | ||
9ccd5aeb | 9543 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9544 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9545 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9546 | ndelay(100); |
9547 | ||
9ccd5aeb PZ |
9548 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9549 | 1)) | |
be256dc7 PZ |
9550 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9551 | ||
9552 | if (allow_power_down) { | |
9553 | val = I915_READ(LCPLL_CTL); | |
9554 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9555 | I915_WRITE(LCPLL_CTL, val); | |
9556 | POSTING_READ(LCPLL_CTL); | |
9557 | } | |
9558 | } | |
9559 | ||
9560 | /* | |
9561 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9562 | * source. | |
9563 | */ | |
6ff58d53 | 9564 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9565 | { |
9566 | uint32_t val; | |
9567 | ||
9568 | val = I915_READ(LCPLL_CTL); | |
9569 | ||
9570 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9571 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9572 | return; | |
9573 | ||
a8a8bd54 PZ |
9574 | /* |
9575 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9576 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9577 | */ |
59bad947 | 9578 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9579 | |
be256dc7 PZ |
9580 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9581 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9582 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9583 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9584 | } |
9585 | ||
9ccd5aeb | 9586 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9587 | val |= D_COMP_COMP_FORCE; |
9588 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9589 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9590 | |
9591 | val = I915_READ(LCPLL_CTL); | |
9592 | val &= ~LCPLL_PLL_DISABLE; | |
9593 | I915_WRITE(LCPLL_CTL, val); | |
9594 | ||
9595 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9596 | DRM_ERROR("LCPLL not locked yet\n"); | |
9597 | ||
9598 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9599 | val = I915_READ(LCPLL_CTL); | |
9600 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9601 | I915_WRITE(LCPLL_CTL, val); | |
9602 | ||
9603 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9604 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9605 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9606 | } | |
215733fa | 9607 | |
59bad947 | 9608 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9609 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9610 | } |
9611 | ||
765dab67 PZ |
9612 | /* |
9613 | * Package states C8 and deeper are really deep PC states that can only be | |
9614 | * reached when all the devices on the system allow it, so even if the graphics | |
9615 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9616 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9617 | * | |
9618 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9619 | * well is disabled and most interrupts are disabled, and these are also | |
9620 | * requirements for runtime PM. When these conditions are met, we manually do | |
9621 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9622 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9623 | * hang the machine. | |
9624 | * | |
9625 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9626 | * the state of some registers, so when we come back from PC8+ we need to | |
9627 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9628 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9629 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9630 | * because of the runtime PM support). | |
9631 | * | |
9632 | * For more, read "Display Sequences for Package C8" on the hardware | |
9633 | * documentation. | |
9634 | */ | |
a14cb6fc | 9635 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9636 | { |
c67a470b PZ |
9637 | struct drm_device *dev = dev_priv->dev; |
9638 | uint32_t val; | |
9639 | ||
c67a470b PZ |
9640 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9641 | ||
c2699524 | 9642 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9643 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9644 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9645 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9646 | } | |
9647 | ||
9648 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9649 | hsw_disable_lcpll(dev_priv, true, true); |
9650 | } | |
9651 | ||
a14cb6fc | 9652 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9653 | { |
9654 | struct drm_device *dev = dev_priv->dev; | |
9655 | uint32_t val; | |
9656 | ||
c67a470b PZ |
9657 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9658 | ||
9659 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9660 | lpt_init_pch_refclk(dev); |
9661 | ||
c2699524 | 9662 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9663 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9664 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9665 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9666 | } | |
9667 | ||
9668 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9669 | } |
9670 | ||
27c329ed | 9671 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9672 | { |
a821fc46 | 9673 | struct drm_device *dev = old_state->dev; |
27c329ed | 9674 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
f8437dd1 | 9675 | |
27c329ed | 9676 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9677 | } |
9678 | ||
b432e5cf | 9679 | /* compute the max rate for new configuration */ |
27c329ed | 9680 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9681 | { |
b432e5cf | 9682 | struct intel_crtc *intel_crtc; |
27c329ed | 9683 | struct intel_crtc_state *crtc_state; |
b432e5cf | 9684 | int max_pixel_rate = 0; |
b432e5cf | 9685 | |
27c329ed ML |
9686 | for_each_intel_crtc(state->dev, intel_crtc) { |
9687 | int pixel_rate; | |
9688 | ||
9689 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
9690 | if (IS_ERR(crtc_state)) | |
9691 | return PTR_ERR(crtc_state); | |
9692 | ||
9693 | if (!crtc_state->base.enable) | |
b432e5cf VS |
9694 | continue; |
9695 | ||
27c329ed | 9696 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9697 | |
9698 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
27c329ed | 9699 | if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled) |
b432e5cf VS |
9700 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9701 | ||
9702 | max_pixel_rate = max(max_pixel_rate, pixel_rate); | |
9703 | } | |
9704 | ||
9705 | return max_pixel_rate; | |
9706 | } | |
9707 | ||
9708 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9709 | { | |
9710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9711 | uint32_t val, data; | |
9712 | int ret; | |
9713 | ||
9714 | if (WARN((I915_READ(LCPLL_CTL) & | |
9715 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9716 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9717 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9718 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9719 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9720 | return; | |
9721 | ||
9722 | mutex_lock(&dev_priv->rps.hw_lock); | |
9723 | ret = sandybridge_pcode_write(dev_priv, | |
9724 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9725 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9726 | if (ret) { | |
9727 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9728 | return; | |
9729 | } | |
9730 | ||
9731 | val = I915_READ(LCPLL_CTL); | |
9732 | val |= LCPLL_CD_SOURCE_FCLK; | |
9733 | I915_WRITE(LCPLL_CTL, val); | |
9734 | ||
9735 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9736 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9737 | DRM_ERROR("Switching to FCLK failed\n"); | |
9738 | ||
9739 | val = I915_READ(LCPLL_CTL); | |
9740 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9741 | ||
9742 | switch (cdclk) { | |
9743 | case 450000: | |
9744 | val |= LCPLL_CLK_FREQ_450; | |
9745 | data = 0; | |
9746 | break; | |
9747 | case 540000: | |
9748 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9749 | data = 1; | |
9750 | break; | |
9751 | case 337500: | |
9752 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9753 | data = 2; | |
9754 | break; | |
9755 | case 675000: | |
9756 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9757 | data = 3; | |
9758 | break; | |
9759 | default: | |
9760 | WARN(1, "invalid cdclk frequency\n"); | |
9761 | return; | |
9762 | } | |
9763 | ||
9764 | I915_WRITE(LCPLL_CTL, val); | |
9765 | ||
9766 | val = I915_READ(LCPLL_CTL); | |
9767 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9768 | I915_WRITE(LCPLL_CTL, val); | |
9769 | ||
9770 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9771 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9772 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9773 | ||
9774 | mutex_lock(&dev_priv->rps.hw_lock); | |
9775 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9776 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9777 | ||
9778 | intel_update_cdclk(dev); | |
9779 | ||
9780 | WARN(cdclk != dev_priv->cdclk_freq, | |
9781 | "cdclk requested %d kHz but got %d kHz\n", | |
9782 | cdclk, dev_priv->cdclk_freq); | |
9783 | } | |
9784 | ||
27c329ed | 9785 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9786 | { |
27c329ed ML |
9787 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
9788 | int max_pixclk = ilk_max_pixel_rate(state); | |
b432e5cf VS |
9789 | int cdclk; |
9790 | ||
9791 | /* | |
9792 | * FIXME should also account for plane ratio | |
9793 | * once 64bpp pixel formats are supported. | |
9794 | */ | |
27c329ed | 9795 | if (max_pixclk > 540000) |
b432e5cf | 9796 | cdclk = 675000; |
27c329ed | 9797 | else if (max_pixclk > 450000) |
b432e5cf | 9798 | cdclk = 540000; |
27c329ed | 9799 | else if (max_pixclk > 337500) |
b432e5cf VS |
9800 | cdclk = 450000; |
9801 | else | |
9802 | cdclk = 337500; | |
9803 | ||
b432e5cf | 9804 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9805 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9806 | cdclk, dev_priv->max_cdclk_freq); | |
9807 | return -EINVAL; | |
b432e5cf VS |
9808 | } |
9809 | ||
27c329ed | 9810 | to_intel_atomic_state(state)->cdclk = cdclk; |
b432e5cf VS |
9811 | |
9812 | return 0; | |
9813 | } | |
9814 | ||
27c329ed | 9815 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9816 | { |
27c329ed ML |
9817 | struct drm_device *dev = old_state->dev; |
9818 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; | |
b432e5cf | 9819 | |
27c329ed | 9820 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9821 | } |
9822 | ||
190f68c5 ACO |
9823 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9824 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9825 | { |
190f68c5 | 9826 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9827 | return -EINVAL; |
716c2e55 | 9828 | |
c7653199 | 9829 | crtc->lowfreq_avail = false; |
644cef34 | 9830 | |
c8f7a0db | 9831 | return 0; |
79e53945 JB |
9832 | } |
9833 | ||
3760b59c S |
9834 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9835 | enum port port, | |
9836 | struct intel_crtc_state *pipe_config) | |
9837 | { | |
9838 | switch (port) { | |
9839 | case PORT_A: | |
9840 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9841 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9842 | break; | |
9843 | case PORT_B: | |
9844 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9845 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9846 | break; | |
9847 | case PORT_C: | |
9848 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9849 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9850 | break; | |
9851 | default: | |
9852 | DRM_ERROR("Incorrect port type\n"); | |
9853 | } | |
9854 | } | |
9855 | ||
96b7dfb7 S |
9856 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9857 | enum port port, | |
5cec258b | 9858 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9859 | { |
3148ade7 | 9860 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9861 | |
9862 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9863 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9864 | ||
9865 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9866 | case SKL_DPLL0: |
9867 | /* | |
9868 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9869 | * of the shared DPLL framework and thus needs to be read out | |
9870 | * separately | |
9871 | */ | |
9872 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9873 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9874 | break; | |
96b7dfb7 S |
9875 | case SKL_DPLL1: |
9876 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9877 | break; | |
9878 | case SKL_DPLL2: | |
9879 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9880 | break; | |
9881 | case SKL_DPLL3: | |
9882 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9883 | break; | |
96b7dfb7 S |
9884 | } |
9885 | } | |
9886 | ||
7d2c8175 DL |
9887 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9888 | enum port port, | |
5cec258b | 9889 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9890 | { |
9891 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9892 | ||
9893 | switch (pipe_config->ddi_pll_sel) { | |
9894 | case PORT_CLK_SEL_WRPLL1: | |
9895 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9896 | break; | |
9897 | case PORT_CLK_SEL_WRPLL2: | |
9898 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9899 | break; | |
00490c22 ML |
9900 | case PORT_CLK_SEL_SPLL: |
9901 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 9902 | break; |
7d2c8175 DL |
9903 | } |
9904 | } | |
9905 | ||
26804afd | 9906 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9907 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9908 | { |
9909 | struct drm_device *dev = crtc->base.dev; | |
9910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9911 | struct intel_shared_dpll *pll; |
26804afd DV |
9912 | enum port port; |
9913 | uint32_t tmp; | |
9914 | ||
9915 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9916 | ||
9917 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9918 | ||
ef11bdb3 | 9919 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9920 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9921 | else if (IS_BROXTON(dev)) |
9922 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9923 | else |
9924 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9925 | |
d452c5b6 DV |
9926 | if (pipe_config->shared_dpll >= 0) { |
9927 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9928 | ||
9929 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9930 | &pipe_config->dpll_hw_state)); | |
9931 | } | |
9932 | ||
26804afd DV |
9933 | /* |
9934 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9935 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9936 | * the PCH transcoder is on. | |
9937 | */ | |
ca370455 DL |
9938 | if (INTEL_INFO(dev)->gen < 9 && |
9939 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9940 | pipe_config->has_pch_encoder = true; |
9941 | ||
9942 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9943 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9944 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9945 | ||
9946 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9947 | } | |
9948 | } | |
9949 | ||
0e8ffe1b | 9950 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9951 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9952 | { |
9953 | struct drm_device *dev = crtc->base.dev; | |
9954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9955 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9956 | uint32_t tmp; |
9957 | ||
f458ebbc | 9958 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9959 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9960 | return false; | |
9961 | ||
e143a21c | 9962 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9963 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9964 | ||
eccb140b DV |
9965 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9966 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9967 | enum pipe trans_edp_pipe; | |
9968 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9969 | default: | |
9970 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9971 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9972 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9973 | trans_edp_pipe = PIPE_A; | |
9974 | break; | |
9975 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9976 | trans_edp_pipe = PIPE_B; | |
9977 | break; | |
9978 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9979 | trans_edp_pipe = PIPE_C; | |
9980 | break; | |
9981 | } | |
9982 | ||
9983 | if (trans_edp_pipe == crtc->pipe) | |
9984 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9985 | } | |
9986 | ||
f458ebbc | 9987 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9988 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9989 | return false; |
9990 | ||
eccb140b | 9991 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9992 | if (!(tmp & PIPECONF_ENABLE)) |
9993 | return false; | |
9994 | ||
26804afd | 9995 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9996 | |
1bd1bd80 DV |
9997 | intel_get_pipe_timings(crtc, pipe_config); |
9998 | ||
a1b2278e CK |
9999 | if (INTEL_INFO(dev)->gen >= 9) { |
10000 | skl_init_scalers(dev, crtc, pipe_config); | |
10001 | } | |
10002 | ||
2fa2fe9a | 10003 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
10004 | |
10005 | if (INTEL_INFO(dev)->gen >= 9) { | |
10006 | pipe_config->scaler_state.scaler_id = -1; | |
10007 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10008 | } | |
10009 | ||
bd2e244f | 10010 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 10011 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10012 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10013 | else |
1c132b44 | 10014 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10015 | } |
88adfff1 | 10016 | |
e59150dc JB |
10017 | if (IS_HASWELL(dev)) |
10018 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10019 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10020 | |
ebb69c95 CT |
10021 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10022 | pipe_config->pixel_multiplier = | |
10023 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10024 | } else { | |
10025 | pipe_config->pixel_multiplier = 1; | |
10026 | } | |
6c49f241 | 10027 | |
0e8ffe1b DV |
10028 | return true; |
10029 | } | |
10030 | ||
663f3122 | 10031 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
560b85bb CW |
10032 | { |
10033 | struct drm_device *dev = crtc->dev; | |
10034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10035 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10036 | uint32_t cntl = 0, size = 0; |
560b85bb | 10037 | |
663f3122 | 10038 | if (on) { |
3dd512fb MR |
10039 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
10040 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
10041 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10042 | ||
10043 | switch (stride) { | |
10044 | default: | |
10045 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10046 | width, stride); | |
10047 | stride = 256; | |
10048 | /* fallthrough */ | |
10049 | case 256: | |
10050 | case 512: | |
10051 | case 1024: | |
10052 | case 2048: | |
10053 | break; | |
4b0e333e CW |
10054 | } |
10055 | ||
dc41c154 VS |
10056 | cntl |= CURSOR_ENABLE | |
10057 | CURSOR_GAMMA_ENABLE | | |
10058 | CURSOR_FORMAT_ARGB | | |
10059 | CURSOR_STRIDE(stride); | |
10060 | ||
10061 | size = (height << 12) | width; | |
4b0e333e | 10062 | } |
560b85bb | 10063 | |
dc41c154 VS |
10064 | if (intel_crtc->cursor_cntl != 0 && |
10065 | (intel_crtc->cursor_base != base || | |
10066 | intel_crtc->cursor_size != size || | |
10067 | intel_crtc->cursor_cntl != cntl)) { | |
10068 | /* On these chipsets we can only modify the base/size/stride | |
10069 | * whilst the cursor is disabled. | |
10070 | */ | |
0b87c24e VS |
10071 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10072 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10073 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10074 | } |
560b85bb | 10075 | |
99d1f387 | 10076 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10077 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10078 | intel_crtc->cursor_base = base; |
10079 | } | |
4726e0b0 | 10080 | |
dc41c154 VS |
10081 | if (intel_crtc->cursor_size != size) { |
10082 | I915_WRITE(CURSIZE, size); | |
10083 | intel_crtc->cursor_size = size; | |
4b0e333e | 10084 | } |
560b85bb | 10085 | |
4b0e333e | 10086 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10087 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10088 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10089 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10090 | } |
560b85bb CW |
10091 | } |
10092 | ||
663f3122 | 10093 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
65a21cd6 JB |
10094 | { |
10095 | struct drm_device *dev = crtc->dev; | |
10096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10097 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10098 | int pipe = intel_crtc->pipe; | |
663f3122 | 10099 | uint32_t cntl = 0; |
4b0e333e | 10100 | |
663f3122 | 10101 | if (on) { |
4b0e333e | 10102 | cntl = MCURSOR_GAMMA_ENABLE; |
3dd512fb | 10103 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
10104 | case 64: |
10105 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10106 | break; | |
10107 | case 128: | |
10108 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10109 | break; | |
10110 | case 256: | |
10111 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10112 | break; | |
10113 | default: | |
3dd512fb | 10114 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 10115 | return; |
65a21cd6 | 10116 | } |
4b0e333e | 10117 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10118 | |
fc6f93bc | 10119 | if (HAS_DDI(dev)) |
47bf17a7 | 10120 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
4b0e333e | 10121 | } |
65a21cd6 | 10122 | |
8e7d688b | 10123 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
10124 | cntl |= CURSOR_ROTATE_180; |
10125 | ||
4b0e333e CW |
10126 | if (intel_crtc->cursor_cntl != cntl) { |
10127 | I915_WRITE(CURCNTR(pipe), cntl); | |
10128 | POSTING_READ(CURCNTR(pipe)); | |
10129 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10130 | } |
4b0e333e | 10131 | |
65a21cd6 | 10132 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10133 | I915_WRITE(CURBASE(pipe), base); |
10134 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10135 | |
10136 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10137 | } |
10138 | ||
cda4b7d3 | 10139 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
10140 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
10141 | bool on) | |
cda4b7d3 CW |
10142 | { |
10143 | struct drm_device *dev = crtc->dev; | |
10144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10145 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10146 | int pipe = intel_crtc->pipe; | |
9b4101be ML |
10147 | struct drm_plane_state *cursor_state = crtc->cursor->state; |
10148 | int x = cursor_state->crtc_x; | |
10149 | int y = cursor_state->crtc_y; | |
d6e4db15 | 10150 | u32 base = 0, pos = 0; |
cda4b7d3 | 10151 | |
663f3122 | 10152 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 10153 | |
6e3c9717 | 10154 | if (x >= intel_crtc->config->pipe_src_w) |
663f3122 | 10155 | on = false; |
d6e4db15 | 10156 | |
6e3c9717 | 10157 | if (y >= intel_crtc->config->pipe_src_h) |
663f3122 | 10158 | on = false; |
cda4b7d3 CW |
10159 | |
10160 | if (x < 0) { | |
9b4101be | 10161 | if (x + cursor_state->crtc_w <= 0) |
663f3122 | 10162 | on = false; |
cda4b7d3 CW |
10163 | |
10164 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10165 | x = -x; | |
10166 | } | |
10167 | pos |= x << CURSOR_X_SHIFT; | |
10168 | ||
10169 | if (y < 0) { | |
9b4101be | 10170 | if (y + cursor_state->crtc_h <= 0) |
663f3122 | 10171 | on = false; |
cda4b7d3 CW |
10172 | |
10173 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10174 | y = -y; | |
10175 | } | |
10176 | pos |= y << CURSOR_Y_SHIFT; | |
10177 | ||
5efb3e28 VS |
10178 | I915_WRITE(CURPOS(pipe), pos); |
10179 | ||
4398ad45 VS |
10180 | /* ILK+ do this automagically */ |
10181 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 10182 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
9b4101be ML |
10183 | base += (cursor_state->crtc_h * |
10184 | cursor_state->crtc_w - 1) * 4; | |
4398ad45 VS |
10185 | } |
10186 | ||
8ac54669 | 10187 | if (IS_845G(dev) || IS_I865G(dev)) |
663f3122 | 10188 | i845_update_cursor(crtc, base, on); |
5efb3e28 | 10189 | else |
663f3122 | 10190 | i9xx_update_cursor(crtc, base, on); |
cda4b7d3 CW |
10191 | } |
10192 | ||
dc41c154 VS |
10193 | static bool cursor_size_ok(struct drm_device *dev, |
10194 | uint32_t width, uint32_t height) | |
10195 | { | |
10196 | if (width == 0 || height == 0) | |
10197 | return false; | |
10198 | ||
10199 | /* | |
10200 | * 845g/865g are special in that they are only limited by | |
10201 | * the width of their cursors, the height is arbitrary up to | |
10202 | * the precision of the register. Everything else requires | |
10203 | * square cursors, limited to a few power-of-two sizes. | |
10204 | */ | |
10205 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10206 | if ((width & 63) != 0) | |
10207 | return false; | |
10208 | ||
10209 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10210 | return false; | |
10211 | ||
10212 | if (height > 1023) | |
10213 | return false; | |
10214 | } else { | |
10215 | switch (width | height) { | |
10216 | case 256: | |
10217 | case 128: | |
10218 | if (IS_GEN2(dev)) | |
10219 | return false; | |
10220 | case 64: | |
10221 | break; | |
10222 | default: | |
10223 | return false; | |
10224 | } | |
10225 | } | |
10226 | ||
10227 | return true; | |
10228 | } | |
10229 | ||
79e53945 | 10230 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10231 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10232 | { |
7203425a | 10233 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10234 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10235 | |
7203425a | 10236 | for (i = start; i < end; i++) { |
79e53945 JB |
10237 | intel_crtc->lut_r[i] = red[i] >> 8; |
10238 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10239 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10240 | } | |
10241 | ||
10242 | intel_crtc_load_lut(crtc); | |
10243 | } | |
10244 | ||
79e53945 JB |
10245 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10246 | static struct drm_display_mode load_detect_mode = { | |
10247 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10248 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10249 | }; | |
10250 | ||
a8bb6818 DV |
10251 | struct drm_framebuffer * |
10252 | __intel_framebuffer_create(struct drm_device *dev, | |
10253 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10254 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10255 | { |
10256 | struct intel_framebuffer *intel_fb; | |
10257 | int ret; | |
10258 | ||
10259 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10260 | if (!intel_fb) |
d2dff872 | 10261 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10262 | |
10263 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10264 | if (ret) |
10265 | goto err; | |
d2dff872 CW |
10266 | |
10267 | return &intel_fb->base; | |
dcb1394e | 10268 | |
dd4916c5 | 10269 | err: |
dd4916c5 | 10270 | kfree(intel_fb); |
dd4916c5 | 10271 | return ERR_PTR(ret); |
d2dff872 CW |
10272 | } |
10273 | ||
b5ea642a | 10274 | static struct drm_framebuffer * |
a8bb6818 DV |
10275 | intel_framebuffer_create(struct drm_device *dev, |
10276 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10277 | struct drm_i915_gem_object *obj) | |
10278 | { | |
10279 | struct drm_framebuffer *fb; | |
10280 | int ret; | |
10281 | ||
10282 | ret = i915_mutex_lock_interruptible(dev); | |
10283 | if (ret) | |
10284 | return ERR_PTR(ret); | |
10285 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10286 | mutex_unlock(&dev->struct_mutex); | |
10287 | ||
10288 | return fb; | |
10289 | } | |
10290 | ||
d2dff872 CW |
10291 | static u32 |
10292 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10293 | { | |
10294 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10295 | return ALIGN(pitch, 64); | |
10296 | } | |
10297 | ||
10298 | static u32 | |
10299 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10300 | { | |
10301 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10302 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10303 | } |
10304 | ||
10305 | static struct drm_framebuffer * | |
10306 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10307 | struct drm_display_mode *mode, | |
10308 | int depth, int bpp) | |
10309 | { | |
dcb1394e | 10310 | struct drm_framebuffer *fb; |
d2dff872 | 10311 | struct drm_i915_gem_object *obj; |
0fed39bd | 10312 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10313 | |
10314 | obj = i915_gem_alloc_object(dev, | |
10315 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10316 | if (obj == NULL) | |
10317 | return ERR_PTR(-ENOMEM); | |
10318 | ||
10319 | mode_cmd.width = mode->hdisplay; | |
10320 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10321 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10322 | bpp); | |
5ca0c34a | 10323 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10324 | |
dcb1394e LW |
10325 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10326 | if (IS_ERR(fb)) | |
10327 | drm_gem_object_unreference_unlocked(&obj->base); | |
10328 | ||
10329 | return fb; | |
d2dff872 CW |
10330 | } |
10331 | ||
10332 | static struct drm_framebuffer * | |
10333 | mode_fits_in_fbdev(struct drm_device *dev, | |
10334 | struct drm_display_mode *mode) | |
10335 | { | |
0695726e | 10336 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10337 | struct drm_i915_private *dev_priv = dev->dev_private; |
10338 | struct drm_i915_gem_object *obj; | |
10339 | struct drm_framebuffer *fb; | |
10340 | ||
4c0e5528 | 10341 | if (!dev_priv->fbdev) |
d2dff872 CW |
10342 | return NULL; |
10343 | ||
4c0e5528 | 10344 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10345 | return NULL; |
10346 | ||
4c0e5528 DV |
10347 | obj = dev_priv->fbdev->fb->obj; |
10348 | BUG_ON(!obj); | |
10349 | ||
8bcd4553 | 10350 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10351 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10352 | fb->bits_per_pixel)) | |
d2dff872 CW |
10353 | return NULL; |
10354 | ||
01f2c773 | 10355 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10356 | return NULL; |
10357 | ||
10358 | return fb; | |
4520f53a DV |
10359 | #else |
10360 | return NULL; | |
10361 | #endif | |
d2dff872 CW |
10362 | } |
10363 | ||
d3a40d1b ACO |
10364 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10365 | struct drm_crtc *crtc, | |
10366 | struct drm_display_mode *mode, | |
10367 | struct drm_framebuffer *fb, | |
10368 | int x, int y) | |
10369 | { | |
10370 | struct drm_plane_state *plane_state; | |
10371 | int hdisplay, vdisplay; | |
10372 | int ret; | |
10373 | ||
10374 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10375 | if (IS_ERR(plane_state)) | |
10376 | return PTR_ERR(plane_state); | |
10377 | ||
10378 | if (mode) | |
10379 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10380 | else | |
10381 | hdisplay = vdisplay = 0; | |
10382 | ||
10383 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10384 | if (ret) | |
10385 | return ret; | |
10386 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10387 | plane_state->crtc_x = 0; | |
10388 | plane_state->crtc_y = 0; | |
10389 | plane_state->crtc_w = hdisplay; | |
10390 | plane_state->crtc_h = vdisplay; | |
10391 | plane_state->src_x = x << 16; | |
10392 | plane_state->src_y = y << 16; | |
10393 | plane_state->src_w = hdisplay << 16; | |
10394 | plane_state->src_h = vdisplay << 16; | |
10395 | ||
10396 | return 0; | |
10397 | } | |
10398 | ||
d2434ab7 | 10399 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10400 | struct drm_display_mode *mode, |
51fd371b RC |
10401 | struct intel_load_detect_pipe *old, |
10402 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10403 | { |
10404 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10405 | struct intel_encoder *intel_encoder = |
10406 | intel_attached_encoder(connector); | |
79e53945 | 10407 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10408 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10409 | struct drm_crtc *crtc = NULL; |
10410 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10411 | struct drm_framebuffer *fb; |
51fd371b | 10412 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10413 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10414 | struct drm_connector_state *connector_state; |
4be07317 | 10415 | struct intel_crtc_state *crtc_state; |
51fd371b | 10416 | int ret, i = -1; |
79e53945 | 10417 | |
d2dff872 | 10418 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10419 | connector->base.id, connector->name, |
8e329a03 | 10420 | encoder->base.id, encoder->name); |
d2dff872 | 10421 | |
51fd371b RC |
10422 | retry: |
10423 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10424 | if (ret) | |
ad3c558f | 10425 | goto fail; |
6e9f798d | 10426 | |
79e53945 JB |
10427 | /* |
10428 | * Algorithm gets a little messy: | |
7a5e4805 | 10429 | * |
79e53945 JB |
10430 | * - if the connector already has an assigned crtc, use it (but make |
10431 | * sure it's on first) | |
7a5e4805 | 10432 | * |
79e53945 JB |
10433 | * - try to find the first unused crtc that can drive this connector, |
10434 | * and use that if we find one | |
79e53945 JB |
10435 | */ |
10436 | ||
10437 | /* See if we already have a CRTC for this connector */ | |
10438 | if (encoder->crtc) { | |
10439 | crtc = encoder->crtc; | |
8261b191 | 10440 | |
51fd371b | 10441 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10442 | if (ret) |
ad3c558f | 10443 | goto fail; |
4d02e2de | 10444 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10445 | if (ret) |
ad3c558f | 10446 | goto fail; |
7b24056b | 10447 | |
24218aac | 10448 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10449 | old->load_detect_temp = false; |
10450 | ||
10451 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10452 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10453 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10454 | |
7173188d | 10455 | return true; |
79e53945 JB |
10456 | } |
10457 | ||
10458 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10459 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10460 | i++; |
10461 | if (!(encoder->possible_crtcs & (1 << i))) | |
10462 | continue; | |
83d65738 | 10463 | if (possible_crtc->state->enable) |
a459249c | 10464 | continue; |
a459249c VS |
10465 | |
10466 | crtc = possible_crtc; | |
10467 | break; | |
79e53945 JB |
10468 | } |
10469 | ||
10470 | /* | |
10471 | * If we didn't find an unused CRTC, don't use any. | |
10472 | */ | |
10473 | if (!crtc) { | |
7173188d | 10474 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10475 | goto fail; |
79e53945 JB |
10476 | } |
10477 | ||
51fd371b RC |
10478 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10479 | if (ret) | |
ad3c558f | 10480 | goto fail; |
4d02e2de DV |
10481 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10482 | if (ret) | |
ad3c558f | 10483 | goto fail; |
79e53945 JB |
10484 | |
10485 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10486 | old->dpms_mode = connector->dpms; |
8261b191 | 10487 | old->load_detect_temp = true; |
d2dff872 | 10488 | old->release_fb = NULL; |
79e53945 | 10489 | |
83a57153 ACO |
10490 | state = drm_atomic_state_alloc(dev); |
10491 | if (!state) | |
10492 | return false; | |
10493 | ||
10494 | state->acquire_ctx = ctx; | |
10495 | ||
944b0c76 ACO |
10496 | connector_state = drm_atomic_get_connector_state(state, connector); |
10497 | if (IS_ERR(connector_state)) { | |
10498 | ret = PTR_ERR(connector_state); | |
10499 | goto fail; | |
10500 | } | |
10501 | ||
10502 | connector_state->crtc = crtc; | |
10503 | connector_state->best_encoder = &intel_encoder->base; | |
10504 | ||
4be07317 ACO |
10505 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10506 | if (IS_ERR(crtc_state)) { | |
10507 | ret = PTR_ERR(crtc_state); | |
10508 | goto fail; | |
10509 | } | |
10510 | ||
49d6fa21 | 10511 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10512 | |
6492711d CW |
10513 | if (!mode) |
10514 | mode = &load_detect_mode; | |
79e53945 | 10515 | |
d2dff872 CW |
10516 | /* We need a framebuffer large enough to accommodate all accesses |
10517 | * that the plane may generate whilst we perform load detection. | |
10518 | * We can not rely on the fbcon either being present (we get called | |
10519 | * during its initialisation to detect all boot displays, or it may | |
10520 | * not even exist) or that it is large enough to satisfy the | |
10521 | * requested mode. | |
10522 | */ | |
94352cf9 DV |
10523 | fb = mode_fits_in_fbdev(dev, mode); |
10524 | if (fb == NULL) { | |
d2dff872 | 10525 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10526 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10527 | old->release_fb = fb; | |
d2dff872 CW |
10528 | } else |
10529 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10530 | if (IS_ERR(fb)) { |
d2dff872 | 10531 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10532 | goto fail; |
79e53945 | 10533 | } |
79e53945 | 10534 | |
d3a40d1b ACO |
10535 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10536 | if (ret) | |
10537 | goto fail; | |
10538 | ||
8c7b5ccb ACO |
10539 | drm_mode_copy(&crtc_state->base.mode, mode); |
10540 | ||
74c090b1 | 10541 | if (drm_atomic_commit(state)) { |
6492711d | 10542 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10543 | if (old->release_fb) |
10544 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10545 | goto fail; |
79e53945 | 10546 | } |
9128b040 | 10547 | crtc->primary->crtc = crtc; |
7173188d | 10548 | |
79e53945 | 10549 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10550 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10551 | return true; |
412b61d8 | 10552 | |
ad3c558f | 10553 | fail: |
e5d958ef ACO |
10554 | drm_atomic_state_free(state); |
10555 | state = NULL; | |
83a57153 | 10556 | |
51fd371b RC |
10557 | if (ret == -EDEADLK) { |
10558 | drm_modeset_backoff(ctx); | |
10559 | goto retry; | |
10560 | } | |
10561 | ||
412b61d8 | 10562 | return false; |
79e53945 JB |
10563 | } |
10564 | ||
d2434ab7 | 10565 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10566 | struct intel_load_detect_pipe *old, |
10567 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10568 | { |
83a57153 | 10569 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10570 | struct intel_encoder *intel_encoder = |
10571 | intel_attached_encoder(connector); | |
4ef69c7a | 10572 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10573 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10574 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10575 | struct drm_atomic_state *state; |
944b0c76 | 10576 | struct drm_connector_state *connector_state; |
4be07317 | 10577 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10578 | int ret; |
79e53945 | 10579 | |
d2dff872 | 10580 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10581 | connector->base.id, connector->name, |
8e329a03 | 10582 | encoder->base.id, encoder->name); |
d2dff872 | 10583 | |
8261b191 | 10584 | if (old->load_detect_temp) { |
83a57153 | 10585 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10586 | if (!state) |
10587 | goto fail; | |
83a57153 ACO |
10588 | |
10589 | state->acquire_ctx = ctx; | |
10590 | ||
944b0c76 ACO |
10591 | connector_state = drm_atomic_get_connector_state(state, connector); |
10592 | if (IS_ERR(connector_state)) | |
10593 | goto fail; | |
10594 | ||
4be07317 ACO |
10595 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10596 | if (IS_ERR(crtc_state)) | |
10597 | goto fail; | |
10598 | ||
944b0c76 ACO |
10599 | connector_state->best_encoder = NULL; |
10600 | connector_state->crtc = NULL; | |
10601 | ||
49d6fa21 | 10602 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10603 | |
d3a40d1b ACO |
10604 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10605 | 0, 0); | |
10606 | if (ret) | |
10607 | goto fail; | |
10608 | ||
74c090b1 | 10609 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10610 | if (ret) |
10611 | goto fail; | |
d2dff872 | 10612 | |
36206361 DV |
10613 | if (old->release_fb) { |
10614 | drm_framebuffer_unregister_private(old->release_fb); | |
10615 | drm_framebuffer_unreference(old->release_fb); | |
10616 | } | |
d2dff872 | 10617 | |
0622a53c | 10618 | return; |
79e53945 JB |
10619 | } |
10620 | ||
c751ce4f | 10621 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10622 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10623 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10624 | |
10625 | return; | |
10626 | fail: | |
10627 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10628 | drm_atomic_state_free(state); | |
79e53945 JB |
10629 | } |
10630 | ||
da4a1efa | 10631 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10632 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10633 | { |
10634 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10635 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10636 | ||
10637 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10638 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10639 | else if (HAS_PCH_SPLIT(dev)) |
10640 | return 120000; | |
10641 | else if (!IS_GEN2(dev)) | |
10642 | return 96000; | |
10643 | else | |
10644 | return 48000; | |
10645 | } | |
10646 | ||
79e53945 | 10647 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10648 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10649 | struct intel_crtc_state *pipe_config) |
79e53945 | 10650 | { |
f1f644dc | 10651 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10652 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10653 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10654 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10655 | u32 fp; |
10656 | intel_clock_t clock; | |
dccbea3b | 10657 | int port_clock; |
da4a1efa | 10658 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10659 | |
10660 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10661 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10662 | else |
293623f7 | 10663 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10664 | |
10665 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10666 | if (IS_PINEVIEW(dev)) { |
10667 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10668 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10669 | } else { |
10670 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10671 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10672 | } | |
10673 | ||
a6c45cf0 | 10674 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10675 | if (IS_PINEVIEW(dev)) |
10676 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10677 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10678 | else |
10679 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10680 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10681 | ||
10682 | switch (dpll & DPLL_MODE_MASK) { | |
10683 | case DPLLB_MODE_DAC_SERIAL: | |
10684 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10685 | 5 : 10; | |
10686 | break; | |
10687 | case DPLLB_MODE_LVDS: | |
10688 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10689 | 7 : 14; | |
10690 | break; | |
10691 | default: | |
28c97730 | 10692 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10693 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10694 | return; |
79e53945 JB |
10695 | } |
10696 | ||
ac58c3f0 | 10697 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10698 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10699 | else |
dccbea3b | 10700 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10701 | } else { |
0fb58223 | 10702 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10703 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10704 | |
10705 | if (is_lvds) { | |
10706 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10707 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10708 | |
10709 | if (lvds & LVDS_CLKB_POWER_UP) | |
10710 | clock.p2 = 7; | |
10711 | else | |
10712 | clock.p2 = 14; | |
79e53945 JB |
10713 | } else { |
10714 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10715 | clock.p1 = 2; | |
10716 | else { | |
10717 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10718 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10719 | } | |
10720 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10721 | clock.p2 = 4; | |
10722 | else | |
10723 | clock.p2 = 2; | |
79e53945 | 10724 | } |
da4a1efa | 10725 | |
dccbea3b | 10726 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10727 | } |
10728 | ||
18442d08 VS |
10729 | /* |
10730 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10731 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10732 | * encoder's get_config() function. |
10733 | */ | |
dccbea3b | 10734 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10735 | } |
10736 | ||
6878da05 VS |
10737 | int intel_dotclock_calculate(int link_freq, |
10738 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10739 | { |
f1f644dc JB |
10740 | /* |
10741 | * The calculation for the data clock is: | |
1041a02f | 10742 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10743 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10744 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10745 | * |
10746 | * and the link clock is simpler: | |
1041a02f | 10747 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10748 | */ |
10749 | ||
6878da05 VS |
10750 | if (!m_n->link_n) |
10751 | return 0; | |
f1f644dc | 10752 | |
6878da05 VS |
10753 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10754 | } | |
f1f644dc | 10755 | |
18442d08 | 10756 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10757 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10758 | { |
10759 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10760 | |
18442d08 VS |
10761 | /* read out port_clock from the DPLL */ |
10762 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10763 | |
f1f644dc | 10764 | /* |
18442d08 | 10765 | * This value does not include pixel_multiplier. |
241bfc38 | 10766 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10767 | * agree once we know their relationship in the encoder's |
10768 | * get_config() function. | |
79e53945 | 10769 | */ |
2d112de7 | 10770 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10771 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10772 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10773 | } |
10774 | ||
10775 | /** Returns the currently programmed mode of the given pipe. */ | |
10776 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10777 | struct drm_crtc *crtc) | |
10778 | { | |
548f245b | 10779 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10780 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10781 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10782 | struct drm_display_mode *mode; |
5cec258b | 10783 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10784 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10785 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10786 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10787 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10788 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10789 | |
10790 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10791 | if (!mode) | |
10792 | return NULL; | |
10793 | ||
f1f644dc JB |
10794 | /* |
10795 | * Construct a pipe_config sufficient for getting the clock info | |
10796 | * back out of crtc_clock_get. | |
10797 | * | |
10798 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10799 | * to use a real value here instead. | |
10800 | */ | |
293623f7 | 10801 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10802 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10803 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10804 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10805 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10806 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10807 | ||
773ae034 | 10808 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10809 | mode->hdisplay = (htot & 0xffff) + 1; |
10810 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10811 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10812 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10813 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10814 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10815 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10816 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10817 | ||
10818 | drm_mode_set_name(mode); | |
79e53945 JB |
10819 | |
10820 | return mode; | |
10821 | } | |
10822 | ||
f047e395 CW |
10823 | void intel_mark_busy(struct drm_device *dev) |
10824 | { | |
c67a470b PZ |
10825 | struct drm_i915_private *dev_priv = dev->dev_private; |
10826 | ||
f62a0076 CW |
10827 | if (dev_priv->mm.busy) |
10828 | return; | |
10829 | ||
43694d69 | 10830 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10831 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10832 | if (INTEL_INFO(dev)->gen >= 6) |
10833 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10834 | dev_priv->mm.busy = true; |
f047e395 CW |
10835 | } |
10836 | ||
10837 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10838 | { |
c67a470b | 10839 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10840 | |
f62a0076 CW |
10841 | if (!dev_priv->mm.busy) |
10842 | return; | |
10843 | ||
10844 | dev_priv->mm.busy = false; | |
10845 | ||
3d13ef2e | 10846 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10847 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10848 | |
43694d69 | 10849 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10850 | } |
10851 | ||
79e53945 JB |
10852 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10853 | { | |
10854 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10855 | struct drm_device *dev = crtc->dev; |
10856 | struct intel_unpin_work *work; | |
67e77c5a | 10857 | |
5e2d7afc | 10858 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10859 | work = intel_crtc->unpin_work; |
10860 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10861 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10862 | |
10863 | if (work) { | |
10864 | cancel_work_sync(&work->work); | |
10865 | kfree(work); | |
10866 | } | |
79e53945 JB |
10867 | |
10868 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10869 | |
79e53945 JB |
10870 | kfree(intel_crtc); |
10871 | } | |
10872 | ||
6b95a207 KH |
10873 | static void intel_unpin_work_fn(struct work_struct *__work) |
10874 | { | |
10875 | struct intel_unpin_work *work = | |
10876 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10877 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10878 | struct drm_device *dev = crtc->base.dev; | |
10879 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10880 | |
b4a98e57 | 10881 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10882 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10883 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10884 | |
f06cc1b9 | 10885 | if (work->flip_queued_req) |
146d84f0 | 10886 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10887 | mutex_unlock(&dev->struct_mutex); |
10888 | ||
a9ff8714 | 10889 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
89ed88ba | 10890 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10891 | |
a9ff8714 VS |
10892 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10893 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10894 | |
6b95a207 KH |
10895 | kfree(work); |
10896 | } | |
10897 | ||
1afe3e9d | 10898 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10899 | struct drm_crtc *crtc) |
6b95a207 | 10900 | { |
6b95a207 KH |
10901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10902 | struct intel_unpin_work *work; | |
6b95a207 KH |
10903 | unsigned long flags; |
10904 | ||
10905 | /* Ignore early vblank irqs */ | |
10906 | if (intel_crtc == NULL) | |
10907 | return; | |
10908 | ||
f326038a DV |
10909 | /* |
10910 | * This is called both by irq handlers and the reset code (to complete | |
10911 | * lost pageflips) so needs the full irqsave spinlocks. | |
10912 | */ | |
6b95a207 KH |
10913 | spin_lock_irqsave(&dev->event_lock, flags); |
10914 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10915 | |
10916 | /* Ensure we don't miss a work->pending update ... */ | |
10917 | smp_rmb(); | |
10918 | ||
10919 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10920 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10921 | return; | |
10922 | } | |
10923 | ||
d6bbafa1 | 10924 | page_flip_completed(intel_crtc); |
0af7e4df | 10925 | |
6b95a207 | 10926 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10927 | } |
10928 | ||
1afe3e9d JB |
10929 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10930 | { | |
fbee40df | 10931 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10932 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10933 | ||
49b14a5c | 10934 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10935 | } |
10936 | ||
10937 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10938 | { | |
fbee40df | 10939 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10940 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10941 | ||
49b14a5c | 10942 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10943 | } |
10944 | ||
75f7f3ec VS |
10945 | /* Is 'a' after or equal to 'b'? */ |
10946 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10947 | { | |
10948 | return !((a - b) & 0x80000000); | |
10949 | } | |
10950 | ||
10951 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10952 | { | |
10953 | struct drm_device *dev = crtc->base.dev; | |
10954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10955 | ||
bdfa7542 VS |
10956 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10957 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10958 | return true; | |
10959 | ||
75f7f3ec VS |
10960 | /* |
10961 | * The relevant registers doen't exist on pre-ctg. | |
10962 | * As the flip done interrupt doesn't trigger for mmio | |
10963 | * flips on gmch platforms, a flip count check isn't | |
10964 | * really needed there. But since ctg has the registers, | |
10965 | * include it in the check anyway. | |
10966 | */ | |
10967 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10968 | return true; | |
10969 | ||
10970 | /* | |
10971 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10972 | * used the same base address. In that case the mmio flip might | |
10973 | * have completed, but the CS hasn't even executed the flip yet. | |
10974 | * | |
10975 | * A flip count check isn't enough as the CS might have updated | |
10976 | * the base address just after start of vblank, but before we | |
10977 | * managed to process the interrupt. This means we'd complete the | |
10978 | * CS flip too soon. | |
10979 | * | |
10980 | * Combining both checks should get us a good enough result. It may | |
10981 | * still happen that the CS flip has been executed, but has not | |
10982 | * yet actually completed. But in case the base address is the same | |
10983 | * anyway, we don't really care. | |
10984 | */ | |
10985 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10986 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10987 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
10988 | crtc->unpin_work->flip_count); |
10989 | } | |
10990 | ||
6b95a207 KH |
10991 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10992 | { | |
fbee40df | 10993 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10994 | struct intel_crtc *intel_crtc = |
10995 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10996 | unsigned long flags; | |
10997 | ||
f326038a DV |
10998 | |
10999 | /* | |
11000 | * This is called both by irq handlers and the reset code (to complete | |
11001 | * lost pageflips) so needs the full irqsave spinlocks. | |
11002 | * | |
11003 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
11004 | * generate a page-flip completion irq, i.e. every modeset |
11005 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
11006 | */ | |
6b95a207 | 11007 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 11008 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 11009 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
11010 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11011 | } | |
11012 | ||
6042639c | 11013 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
11014 | { |
11015 | /* Ensure that the work item is consistent when activating it ... */ | |
11016 | smp_wmb(); | |
6042639c | 11017 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11018 | /* and that it is marked active as soon as the irq could fire. */ |
11019 | smp_wmb(); | |
11020 | } | |
11021 | ||
8c9f3aaf JB |
11022 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11023 | struct drm_crtc *crtc, | |
11024 | struct drm_framebuffer *fb, | |
ed8d1975 | 11025 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11026 | struct drm_i915_gem_request *req, |
ed8d1975 | 11027 | uint32_t flags) |
8c9f3aaf | 11028 | { |
6258fbe2 | 11029 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11030 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11031 | u32 flip_mask; |
11032 | int ret; | |
11033 | ||
5fb9de1a | 11034 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11035 | if (ret) |
4fa62c89 | 11036 | return ret; |
8c9f3aaf JB |
11037 | |
11038 | /* Can't queue multiple flips, so wait for the previous | |
11039 | * one to finish before executing the next. | |
11040 | */ | |
11041 | if (intel_crtc->plane) | |
11042 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11043 | else | |
11044 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11045 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11046 | intel_ring_emit(ring, MI_NOOP); | |
11047 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11048 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11049 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11050 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11051 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11052 | |
6042639c | 11053 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11054 | return 0; |
8c9f3aaf JB |
11055 | } |
11056 | ||
11057 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11058 | struct drm_crtc *crtc, | |
11059 | struct drm_framebuffer *fb, | |
ed8d1975 | 11060 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11061 | struct drm_i915_gem_request *req, |
ed8d1975 | 11062 | uint32_t flags) |
8c9f3aaf | 11063 | { |
6258fbe2 | 11064 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11065 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11066 | u32 flip_mask; |
11067 | int ret; | |
11068 | ||
5fb9de1a | 11069 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11070 | if (ret) |
4fa62c89 | 11071 | return ret; |
8c9f3aaf JB |
11072 | |
11073 | if (intel_crtc->plane) | |
11074 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11075 | else | |
11076 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11077 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11078 | intel_ring_emit(ring, MI_NOOP); | |
11079 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11080 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11081 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11082 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11083 | intel_ring_emit(ring, MI_NOOP); |
11084 | ||
6042639c | 11085 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11086 | return 0; |
8c9f3aaf JB |
11087 | } |
11088 | ||
11089 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11090 | struct drm_crtc *crtc, | |
11091 | struct drm_framebuffer *fb, | |
ed8d1975 | 11092 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11093 | struct drm_i915_gem_request *req, |
ed8d1975 | 11094 | uint32_t flags) |
8c9f3aaf | 11095 | { |
6258fbe2 | 11096 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11097 | struct drm_i915_private *dev_priv = dev->dev_private; |
11098 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11099 | uint32_t pf, pipesrc; | |
11100 | int ret; | |
11101 | ||
5fb9de1a | 11102 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11103 | if (ret) |
4fa62c89 | 11104 | return ret; |
8c9f3aaf JB |
11105 | |
11106 | /* i965+ uses the linear or tiled offsets from the | |
11107 | * Display Registers (which do not change across a page-flip) | |
11108 | * so we need only reprogram the base address. | |
11109 | */ | |
6d90c952 DV |
11110 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11111 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11112 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11113 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11114 | obj->tiling_mode); |
8c9f3aaf JB |
11115 | |
11116 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11117 | * untested on non-native modes, so ignore it for now. | |
11118 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11119 | */ | |
11120 | pf = 0; | |
11121 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11122 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11123 | |
6042639c | 11124 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11125 | return 0; |
8c9f3aaf JB |
11126 | } |
11127 | ||
11128 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11129 | struct drm_crtc *crtc, | |
11130 | struct drm_framebuffer *fb, | |
ed8d1975 | 11131 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11132 | struct drm_i915_gem_request *req, |
ed8d1975 | 11133 | uint32_t flags) |
8c9f3aaf | 11134 | { |
6258fbe2 | 11135 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11136 | struct drm_i915_private *dev_priv = dev->dev_private; |
11137 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11138 | uint32_t pf, pipesrc; | |
11139 | int ret; | |
11140 | ||
5fb9de1a | 11141 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11142 | if (ret) |
4fa62c89 | 11143 | return ret; |
8c9f3aaf | 11144 | |
6d90c952 DV |
11145 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11146 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11147 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11148 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11149 | |
dc257cf1 DV |
11150 | /* Contrary to the suggestions in the documentation, |
11151 | * "Enable Panel Fitter" does not seem to be required when page | |
11152 | * flipping with a non-native mode, and worse causes a normal | |
11153 | * modeset to fail. | |
11154 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11155 | */ | |
11156 | pf = 0; | |
8c9f3aaf | 11157 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11158 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11159 | |
6042639c | 11160 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11161 | return 0; |
8c9f3aaf JB |
11162 | } |
11163 | ||
7c9017e5 JB |
11164 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11165 | struct drm_crtc *crtc, | |
11166 | struct drm_framebuffer *fb, | |
ed8d1975 | 11167 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11168 | struct drm_i915_gem_request *req, |
ed8d1975 | 11169 | uint32_t flags) |
7c9017e5 | 11170 | { |
6258fbe2 | 11171 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11173 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11174 | int len, ret; |
11175 | ||
eba905b2 | 11176 | switch (intel_crtc->plane) { |
cb05d8de DV |
11177 | case PLANE_A: |
11178 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11179 | break; | |
11180 | case PLANE_B: | |
11181 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11182 | break; | |
11183 | case PLANE_C: | |
11184 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11185 | break; | |
11186 | default: | |
11187 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11188 | return -ENODEV; |
cb05d8de DV |
11189 | } |
11190 | ||
ffe74d75 | 11191 | len = 4; |
f476828a | 11192 | if (ring->id == RCS) { |
ffe74d75 | 11193 | len += 6; |
f476828a DL |
11194 | /* |
11195 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11196 | * 48bits addresses, and we need a NOOP for the batch size to | |
11197 | * stay even. | |
11198 | */ | |
11199 | if (IS_GEN8(dev)) | |
11200 | len += 2; | |
11201 | } | |
ffe74d75 | 11202 | |
f66fab8e VS |
11203 | /* |
11204 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11205 | * "The full packet must be contained within the same cache line." | |
11206 | * | |
11207 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11208 | * cacheline, if we ever start emitting more commands before | |
11209 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11210 | * then do the cacheline alignment, and finally emit the | |
11211 | * MI_DISPLAY_FLIP. | |
11212 | */ | |
bba09b12 | 11213 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11214 | if (ret) |
4fa62c89 | 11215 | return ret; |
f66fab8e | 11216 | |
5fb9de1a | 11217 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11218 | if (ret) |
4fa62c89 | 11219 | return ret; |
7c9017e5 | 11220 | |
ffe74d75 CW |
11221 | /* Unmask the flip-done completion message. Note that the bspec says that |
11222 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11223 | * more than one flip event at any time (or ensure that one flip message | |
11224 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11225 | * Experimentation says that BCS works despite DERRMR masking all | |
11226 | * flip-done completion events and that unmasking all planes at once | |
11227 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11228 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11229 | */ | |
11230 | if (ring->id == RCS) { | |
11231 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11232 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11233 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11234 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11235 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11236 | if (IS_GEN8(dev)) |
f1afe24f | 11237 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11238 | MI_SRM_LRM_GLOBAL_GTT); |
11239 | else | |
f1afe24f | 11240 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11241 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11242 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11243 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11244 | if (IS_GEN8(dev)) { |
11245 | intel_ring_emit(ring, 0); | |
11246 | intel_ring_emit(ring, MI_NOOP); | |
11247 | } | |
ffe74d75 CW |
11248 | } |
11249 | ||
cb05d8de | 11250 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11251 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11252 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11253 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11254 | |
6042639c | 11255 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11256 | return 0; |
7c9017e5 JB |
11257 | } |
11258 | ||
84c33a64 SG |
11259 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11260 | struct drm_i915_gem_object *obj) | |
11261 | { | |
11262 | /* | |
11263 | * This is not being used for older platforms, because | |
11264 | * non-availability of flip done interrupt forces us to use | |
11265 | * CS flips. Older platforms derive flip done using some clever | |
11266 | * tricks involving the flip_pending status bits and vblank irqs. | |
11267 | * So using MMIO flips there would disrupt this mechanism. | |
11268 | */ | |
11269 | ||
8e09bf83 CW |
11270 | if (ring == NULL) |
11271 | return true; | |
11272 | ||
84c33a64 SG |
11273 | if (INTEL_INFO(ring->dev)->gen < 5) |
11274 | return false; | |
11275 | ||
11276 | if (i915.use_mmio_flip < 0) | |
11277 | return false; | |
11278 | else if (i915.use_mmio_flip > 0) | |
11279 | return true; | |
14bf993e OM |
11280 | else if (i915.enable_execlists) |
11281 | return true; | |
fd8e058a AG |
11282 | else if (obj->base.dma_buf && |
11283 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11284 | false)) | |
11285 | return true; | |
84c33a64 | 11286 | else |
b4716185 | 11287 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11288 | } |
11289 | ||
6042639c | 11290 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11291 | unsigned int rotation, |
6042639c | 11292 | struct intel_unpin_work *work) |
ff944564 DL |
11293 | { |
11294 | struct drm_device *dev = intel_crtc->base.dev; | |
11295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11296 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11297 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11298 | u32 ctl, stride, tile_height; |
ff944564 DL |
11299 | |
11300 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11301 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11302 | switch (fb->modifier[0]) { |
11303 | case DRM_FORMAT_MOD_NONE: | |
11304 | break; | |
11305 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11306 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11307 | break; |
11308 | case I915_FORMAT_MOD_Y_TILED: | |
11309 | ctl |= PLANE_CTL_TILED_Y; | |
11310 | break; | |
11311 | case I915_FORMAT_MOD_Yf_TILED: | |
11312 | ctl |= PLANE_CTL_TILED_YF; | |
11313 | break; | |
11314 | default: | |
11315 | MISSING_CASE(fb->modifier[0]); | |
11316 | } | |
ff944564 DL |
11317 | |
11318 | /* | |
11319 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11320 | * linear buffers or in number of tiles for tiled buffers. | |
11321 | */ | |
86efe24a TU |
11322 | if (intel_rotation_90_or_270(rotation)) { |
11323 | /* stride = Surface height in tiles */ | |
11324 | tile_height = intel_tile_height(dev, fb->pixel_format, | |
11325 | fb->modifier[0], 0); | |
11326 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
11327 | } else { | |
11328 | stride = fb->pitches[0] / | |
11329 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
11330 | fb->pixel_format); | |
11331 | } | |
ff944564 DL |
11332 | |
11333 | /* | |
11334 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11335 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11336 | */ | |
11337 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11338 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11339 | ||
6042639c | 11340 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11341 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11342 | } | |
11343 | ||
6042639c CW |
11344 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11345 | struct intel_unpin_work *work) | |
84c33a64 SG |
11346 | { |
11347 | struct drm_device *dev = intel_crtc->base.dev; | |
11348 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11349 | struct intel_framebuffer *intel_fb = | |
11350 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11351 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11352 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11353 | u32 dspcntr; |
84c33a64 | 11354 | |
84c33a64 SG |
11355 | dspcntr = I915_READ(reg); |
11356 | ||
c5d97472 DL |
11357 | if (obj->tiling_mode != I915_TILING_NONE) |
11358 | dspcntr |= DISPPLANE_TILED; | |
11359 | else | |
11360 | dspcntr &= ~DISPPLANE_TILED; | |
11361 | ||
84c33a64 SG |
11362 | I915_WRITE(reg, dspcntr); |
11363 | ||
6042639c | 11364 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11365 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11366 | } |
11367 | ||
11368 | /* | |
11369 | * XXX: This is the temporary way to update the plane registers until we get | |
11370 | * around to using the usual plane update functions for MMIO flips | |
11371 | */ | |
6042639c | 11372 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11373 | { |
6042639c CW |
11374 | struct intel_crtc *crtc = mmio_flip->crtc; |
11375 | struct intel_unpin_work *work; | |
11376 | ||
11377 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11378 | work = crtc->unpin_work; | |
11379 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11380 | if (work == NULL) | |
11381 | return; | |
ff944564 | 11382 | |
6042639c | 11383 | intel_mark_page_flip_active(work); |
ff944564 | 11384 | |
6042639c | 11385 | intel_pipe_update_start(crtc); |
ff944564 | 11386 | |
6042639c | 11387 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11388 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11389 | else |
11390 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11391 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11392 | |
6042639c | 11393 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11394 | } |
11395 | ||
9362c7c5 | 11396 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11397 | { |
b2cfe0ab CW |
11398 | struct intel_mmio_flip *mmio_flip = |
11399 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11400 | struct intel_framebuffer *intel_fb = |
11401 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11402 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11403 | |
6042639c | 11404 | if (mmio_flip->req) { |
eed29a5b | 11405 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11406 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11407 | false, NULL, |
11408 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11409 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11410 | } | |
84c33a64 | 11411 | |
fd8e058a AG |
11412 | /* For framebuffer backed by dmabuf, wait for fence */ |
11413 | if (obj->base.dma_buf) | |
11414 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11415 | false, false, | |
11416 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11417 | ||
6042639c | 11418 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11419 | kfree(mmio_flip); |
84c33a64 SG |
11420 | } |
11421 | ||
11422 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11423 | struct drm_crtc *crtc, | |
86efe24a | 11424 | struct drm_i915_gem_object *obj) |
84c33a64 | 11425 | { |
b2cfe0ab CW |
11426 | struct intel_mmio_flip *mmio_flip; |
11427 | ||
11428 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11429 | if (mmio_flip == NULL) | |
11430 | return -ENOMEM; | |
84c33a64 | 11431 | |
bcafc4e3 | 11432 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11433 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11434 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11435 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11436 | |
b2cfe0ab CW |
11437 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11438 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11439 | |
84c33a64 SG |
11440 | return 0; |
11441 | } | |
11442 | ||
8c9f3aaf JB |
11443 | static int intel_default_queue_flip(struct drm_device *dev, |
11444 | struct drm_crtc *crtc, | |
11445 | struct drm_framebuffer *fb, | |
ed8d1975 | 11446 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11447 | struct drm_i915_gem_request *req, |
ed8d1975 | 11448 | uint32_t flags) |
8c9f3aaf JB |
11449 | { |
11450 | return -ENODEV; | |
11451 | } | |
11452 | ||
d6bbafa1 CW |
11453 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11454 | struct drm_crtc *crtc) | |
11455 | { | |
11456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11458 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11459 | u32 addr; | |
11460 | ||
11461 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11462 | return true; | |
11463 | ||
908565c2 CW |
11464 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11465 | return false; | |
11466 | ||
d6bbafa1 CW |
11467 | if (!work->enable_stall_check) |
11468 | return false; | |
11469 | ||
11470 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11471 | if (work->flip_queued_req && |
11472 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11473 | return false; |
11474 | ||
1e3feefd | 11475 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11476 | } |
11477 | ||
1e3feefd | 11478 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11479 | return false; |
11480 | ||
11481 | /* Potential stall - if we see that the flip has happened, | |
11482 | * assume a missed interrupt. */ | |
11483 | if (INTEL_INFO(dev)->gen >= 4) | |
11484 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11485 | else | |
11486 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11487 | ||
11488 | /* There is a potential issue here with a false positive after a flip | |
11489 | * to the same address. We could address this by checking for a | |
11490 | * non-incrementing frame counter. | |
11491 | */ | |
11492 | return addr == work->gtt_offset; | |
11493 | } | |
11494 | ||
11495 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11496 | { | |
11497 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11498 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11499 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11500 | struct intel_unpin_work *work; |
f326038a | 11501 | |
6c51d46f | 11502 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11503 | |
11504 | if (crtc == NULL) | |
11505 | return; | |
11506 | ||
f326038a | 11507 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11508 | work = intel_crtc->unpin_work; |
11509 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11510 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11511 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11512 | page_flip_completed(intel_crtc); |
6ad790c0 | 11513 | work = NULL; |
d6bbafa1 | 11514 | } |
6ad790c0 CW |
11515 | if (work != NULL && |
11516 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11517 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11518 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11519 | } |
11520 | ||
6b95a207 KH |
11521 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11522 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11523 | struct drm_pending_vblank_event *event, |
11524 | uint32_t page_flip_flags) | |
6b95a207 KH |
11525 | { |
11526 | struct drm_device *dev = crtc->dev; | |
11527 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11528 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11529 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11530 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11531 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11532 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11533 | struct intel_unpin_work *work; |
a4872ba6 | 11534 | struct intel_engine_cs *ring; |
cf5d8a46 | 11535 | bool mmio_flip; |
91af127f | 11536 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11537 | int ret; |
6b95a207 | 11538 | |
2ff8fde1 MR |
11539 | /* |
11540 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11541 | * check to be safe. In the future we may enable pageflipping from | |
11542 | * a disabled primary plane. | |
11543 | */ | |
11544 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11545 | return -EBUSY; | |
11546 | ||
e6a595d2 | 11547 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11548 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11549 | return -EINVAL; |
11550 | ||
11551 | /* | |
11552 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11553 | * Note that pitch changes could also affect these register. | |
11554 | */ | |
11555 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11556 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11557 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11558 | return -EINVAL; |
11559 | ||
f900db47 CW |
11560 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11561 | goto out_hang; | |
11562 | ||
b14c5679 | 11563 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11564 | if (work == NULL) |
11565 | return -ENOMEM; | |
11566 | ||
6b95a207 | 11567 | work->event = event; |
b4a98e57 | 11568 | work->crtc = crtc; |
ab8d6675 | 11569 | work->old_fb = old_fb; |
6b95a207 KH |
11570 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11571 | ||
87b6b101 | 11572 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11573 | if (ret) |
11574 | goto free_work; | |
11575 | ||
6b95a207 | 11576 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11577 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11578 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11579 | /* Before declaring the flip queue wedged, check if |
11580 | * the hardware completed the operation behind our backs. | |
11581 | */ | |
11582 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11583 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11584 | page_flip_completed(intel_crtc); | |
11585 | } else { | |
11586 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11587 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11588 | |
d6bbafa1 CW |
11589 | drm_crtc_vblank_put(crtc); |
11590 | kfree(work); | |
11591 | return -EBUSY; | |
11592 | } | |
6b95a207 KH |
11593 | } |
11594 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11595 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11596 | |
b4a98e57 CW |
11597 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11598 | flush_workqueue(dev_priv->wq); | |
11599 | ||
75dfca80 | 11600 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11601 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11602 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11603 | |
f4510a27 | 11604 | crtc->primary->fb = fb; |
afd65eb4 | 11605 | update_state_fb(crtc->primary); |
1ed1f968 | 11606 | |
e1f99ce6 | 11607 | work->pending_flip_obj = obj; |
e1f99ce6 | 11608 | |
89ed88ba CW |
11609 | ret = i915_mutex_lock_interruptible(dev); |
11610 | if (ret) | |
11611 | goto cleanup; | |
11612 | ||
b4a98e57 | 11613 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11614 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11615 | |
75f7f3ec | 11616 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11617 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11618 | |
666a4537 | 11619 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11620 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11621 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11622 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11623 | ring = NULL; | |
48bf5b2d | 11624 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11625 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11626 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11627 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11628 | if (ring == NULL || ring->id != RCS) |
11629 | ring = &dev_priv->ring[BCS]; | |
11630 | } else { | |
11631 | ring = &dev_priv->ring[RCS]; | |
11632 | } | |
11633 | ||
cf5d8a46 CW |
11634 | mmio_flip = use_mmio_flip(ring, obj); |
11635 | ||
11636 | /* When using CS flips, we want to emit semaphores between rings. | |
11637 | * However, when using mmio flips we will create a task to do the | |
11638 | * synchronisation, so all we want here is to pin the framebuffer | |
11639 | * into the display plane and skip any waits. | |
11640 | */ | |
7580d774 ML |
11641 | if (!mmio_flip) { |
11642 | ret = i915_gem_object_sync(obj, ring, &request); | |
11643 | if (ret) | |
11644 | goto cleanup_pending; | |
11645 | } | |
11646 | ||
82bc3b2d | 11647 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
7580d774 | 11648 | crtc->primary->state); |
8c9f3aaf JB |
11649 | if (ret) |
11650 | goto cleanup_pending; | |
6b95a207 | 11651 | |
dedf278c TU |
11652 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11653 | obj, 0); | |
11654 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11655 | |
cf5d8a46 | 11656 | if (mmio_flip) { |
86efe24a | 11657 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11658 | if (ret) |
11659 | goto cleanup_unpin; | |
11660 | ||
f06cc1b9 JH |
11661 | i915_gem_request_assign(&work->flip_queued_req, |
11662 | obj->last_write_req); | |
d6bbafa1 | 11663 | } else { |
6258fbe2 JH |
11664 | if (!request) { |
11665 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); | |
11666 | if (ret) | |
11667 | goto cleanup_unpin; | |
11668 | } | |
11669 | ||
11670 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11671 | page_flip_flags); |
11672 | if (ret) | |
11673 | goto cleanup_unpin; | |
11674 | ||
6258fbe2 | 11675 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11676 | } |
11677 | ||
91af127f | 11678 | if (request) |
75289874 | 11679 | i915_add_request_no_flush(request); |
91af127f | 11680 | |
1e3feefd | 11681 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11682 | work->enable_stall_check = true; |
4fa62c89 | 11683 | |
ab8d6675 | 11684 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11685 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11686 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11687 | |
d029bcad | 11688 | intel_fbc_deactivate(intel_crtc); |
a9ff8714 VS |
11689 | intel_frontbuffer_flip_prepare(dev, |
11690 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11691 | |
e5510fac JB |
11692 | trace_i915_flip_request(intel_crtc->plane, obj); |
11693 | ||
6b95a207 | 11694 | return 0; |
96b099fd | 11695 | |
4fa62c89 | 11696 | cleanup_unpin: |
82bc3b2d | 11697 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11698 | cleanup_pending: |
91af127f JH |
11699 | if (request) |
11700 | i915_gem_request_cancel(request); | |
b4a98e57 | 11701 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11702 | mutex_unlock(&dev->struct_mutex); |
11703 | cleanup: | |
f4510a27 | 11704 | crtc->primary->fb = old_fb; |
afd65eb4 | 11705 | update_state_fb(crtc->primary); |
89ed88ba CW |
11706 | |
11707 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11708 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11709 | |
5e2d7afc | 11710 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11711 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11712 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11713 | |
87b6b101 | 11714 | drm_crtc_vblank_put(crtc); |
7317c75e | 11715 | free_work: |
96b099fd CW |
11716 | kfree(work); |
11717 | ||
f900db47 | 11718 | if (ret == -EIO) { |
02e0efb5 ML |
11719 | struct drm_atomic_state *state; |
11720 | struct drm_plane_state *plane_state; | |
11721 | ||
f900db47 | 11722 | out_hang: |
02e0efb5 ML |
11723 | state = drm_atomic_state_alloc(dev); |
11724 | if (!state) | |
11725 | return -ENOMEM; | |
11726 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11727 | ||
11728 | retry: | |
11729 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11730 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11731 | if (!ret) { | |
11732 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11733 | ||
11734 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11735 | if (!ret) | |
11736 | ret = drm_atomic_commit(state); | |
11737 | } | |
11738 | ||
11739 | if (ret == -EDEADLK) { | |
11740 | drm_modeset_backoff(state->acquire_ctx); | |
11741 | drm_atomic_state_clear(state); | |
11742 | goto retry; | |
11743 | } | |
11744 | ||
11745 | if (ret) | |
11746 | drm_atomic_state_free(state); | |
11747 | ||
f0d3dad3 | 11748 | if (ret == 0 && event) { |
5e2d7afc | 11749 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11750 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11751 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11752 | } |
f900db47 | 11753 | } |
96b099fd | 11754 | return ret; |
6b95a207 KH |
11755 | } |
11756 | ||
da20eabd ML |
11757 | |
11758 | /** | |
11759 | * intel_wm_need_update - Check whether watermarks need updating | |
11760 | * @plane: drm plane | |
11761 | * @state: new plane state | |
11762 | * | |
11763 | * Check current plane state versus the new one to determine whether | |
11764 | * watermarks need to be recalculated. | |
11765 | * | |
11766 | * Returns true or false. | |
11767 | */ | |
11768 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11769 | struct drm_plane_state *state) | |
11770 | { | |
d21fbe87 MR |
11771 | struct intel_plane_state *new = to_intel_plane_state(state); |
11772 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11773 | ||
11774 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11775 | if (new->visible != cur->visible) |
11776 | return true; | |
11777 | ||
11778 | if (!cur->base.fb || !new->base.fb) | |
11779 | return false; | |
11780 | ||
11781 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11782 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11783 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11784 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11785 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11786 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11787 | return true; |
7809e5ae | 11788 | |
2791a16c | 11789 | return false; |
7809e5ae MR |
11790 | } |
11791 | ||
d21fbe87 MR |
11792 | static bool needs_scaling(struct intel_plane_state *state) |
11793 | { | |
11794 | int src_w = drm_rect_width(&state->src) >> 16; | |
11795 | int src_h = drm_rect_height(&state->src) >> 16; | |
11796 | int dst_w = drm_rect_width(&state->dst); | |
11797 | int dst_h = drm_rect_height(&state->dst); | |
11798 | ||
11799 | return (src_w != dst_w || src_h != dst_h); | |
11800 | } | |
11801 | ||
da20eabd ML |
11802 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11803 | struct drm_plane_state *plane_state) | |
11804 | { | |
ab1d3a0e | 11805 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11806 | struct drm_crtc *crtc = crtc_state->crtc; |
11807 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11808 | struct drm_plane *plane = plane_state->plane; | |
11809 | struct drm_device *dev = crtc->dev; | |
11810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11811 | struct intel_plane_state *old_plane_state = | |
11812 | to_intel_plane_state(plane->state); | |
11813 | int idx = intel_crtc->base.base.id, ret; | |
11814 | int i = drm_plane_index(plane); | |
11815 | bool mode_changed = needs_modeset(crtc_state); | |
11816 | bool was_crtc_enabled = crtc->state->active; | |
11817 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11818 | bool turn_off, turn_on, visible, was_visible; |
11819 | struct drm_framebuffer *fb = plane_state->fb; | |
11820 | ||
11821 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11822 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11823 | ret = skl_update_scaler_plane( | |
11824 | to_intel_crtc_state(crtc_state), | |
11825 | to_intel_plane_state(plane_state)); | |
11826 | if (ret) | |
11827 | return ret; | |
11828 | } | |
11829 | ||
da20eabd ML |
11830 | was_visible = old_plane_state->visible; |
11831 | visible = to_intel_plane_state(plane_state)->visible; | |
11832 | ||
11833 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11834 | was_visible = false; | |
11835 | ||
11836 | if (!is_crtc_enabled && WARN_ON(visible)) | |
11837 | visible = false; | |
11838 | ||
11839 | if (!was_visible && !visible) | |
11840 | return 0; | |
11841 | ||
11842 | turn_off = was_visible && (!visible || mode_changed); | |
11843 | turn_on = visible && (!was_visible || mode_changed); | |
11844 | ||
11845 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11846 | plane->base.id, fb ? fb->base.id : -1); | |
11847 | ||
11848 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11849 | plane->base.id, was_visible, visible, | |
11850 | turn_off, turn_on, mode_changed); | |
11851 | ||
92826fcd ML |
11852 | if (turn_on || turn_off) { |
11853 | pipe_config->wm_changed = true; | |
11854 | ||
852eb00d VS |
11855 | /* must disable cxsr around plane enable/disable */ |
11856 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11857 | if (is_crtc_enabled) | |
11858 | intel_crtc->atomic.wait_vblank = true; | |
ab1d3a0e | 11859 | pipe_config->disable_cxsr = true; |
852eb00d VS |
11860 | } |
11861 | } else if (intel_wm_need_update(plane, plane_state)) { | |
92826fcd | 11862 | pipe_config->wm_changed = true; |
852eb00d | 11863 | } |
da20eabd | 11864 | |
8be6ca85 | 11865 | if (visible || was_visible) |
a9ff8714 VS |
11866 | intel_crtc->atomic.fb_bits |= |
11867 | to_intel_plane(plane)->frontbuffer_bit; | |
11868 | ||
da20eabd ML |
11869 | switch (plane->type) { |
11870 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd ML |
11871 | intel_crtc->atomic.pre_disable_primary = turn_off; |
11872 | intel_crtc->atomic.post_enable_primary = turn_on; | |
11873 | ||
066cf55b RV |
11874 | if (turn_off) { |
11875 | /* | |
11876 | * FIXME: Actually if we will still have any other | |
11877 | * plane enabled on the pipe we could let IPS enabled | |
11878 | * still, but for now lets consider that when we make | |
11879 | * primary invisible by setting DSPCNTR to 0 on | |
11880 | * update_primary_plane function IPS needs to be | |
11881 | * disable. | |
11882 | */ | |
11883 | intel_crtc->atomic.disable_ips = true; | |
11884 | ||
da20eabd | 11885 | intel_crtc->atomic.disable_fbc = true; |
066cf55b | 11886 | } |
da20eabd ML |
11887 | |
11888 | /* | |
11889 | * FBC does not work on some platforms for rotated | |
11890 | * planes, so disable it when rotation is not 0 and | |
11891 | * update it when rotation is set back to 0. | |
11892 | * | |
11893 | * FIXME: This is redundant with the fbc update done in | |
11894 | * the primary plane enable function except that that | |
11895 | * one is done too late. We eventually need to unify | |
11896 | * this. | |
11897 | */ | |
11898 | ||
11899 | if (visible && | |
11900 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11901 | dev_priv->fbc.crtc == intel_crtc && | |
11902 | plane_state->rotation != BIT(DRM_ROTATE_0)) | |
11903 | intel_crtc->atomic.disable_fbc = true; | |
11904 | ||
11905 | /* | |
11906 | * BDW signals flip done immediately if the plane | |
11907 | * is disabled, even if the plane enable is already | |
11908 | * armed to occur at the next vblank :( | |
11909 | */ | |
11910 | if (turn_on && IS_BROADWELL(dev)) | |
11911 | intel_crtc->atomic.wait_vblank = true; | |
11912 | ||
11913 | intel_crtc->atomic.update_fbc |= visible || mode_changed; | |
11914 | break; | |
11915 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11916 | break; |
11917 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
11918 | /* |
11919 | * WaCxSRDisabledForSpriteScaling:ivb | |
11920 | * | |
11921 | * cstate->update_wm was already set above, so this flag will | |
11922 | * take effect when we commit and program watermarks. | |
11923 | */ | |
11924 | if (IS_IVYBRIDGE(dev) && | |
11925 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11926 | !needs_scaling(old_plane_state)) { | |
11927 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; | |
11928 | } else if (turn_off && !mode_changed) { | |
da20eabd ML |
11929 | intel_crtc->atomic.wait_vblank = true; |
11930 | intel_crtc->atomic.update_sprite_watermarks |= | |
11931 | 1 << i; | |
11932 | } | |
d21fbe87 MR |
11933 | |
11934 | break; | |
da20eabd ML |
11935 | } |
11936 | return 0; | |
11937 | } | |
11938 | ||
6d3a1ce7 ML |
11939 | static bool encoders_cloneable(const struct intel_encoder *a, |
11940 | const struct intel_encoder *b) | |
11941 | { | |
11942 | /* masks could be asymmetric, so check both ways */ | |
11943 | return a == b || (a->cloneable & (1 << b->type) && | |
11944 | b->cloneable & (1 << a->type)); | |
11945 | } | |
11946 | ||
11947 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11948 | struct intel_crtc *crtc, | |
11949 | struct intel_encoder *encoder) | |
11950 | { | |
11951 | struct intel_encoder *source_encoder; | |
11952 | struct drm_connector *connector; | |
11953 | struct drm_connector_state *connector_state; | |
11954 | int i; | |
11955 | ||
11956 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11957 | if (connector_state->crtc != &crtc->base) | |
11958 | continue; | |
11959 | ||
11960 | source_encoder = | |
11961 | to_intel_encoder(connector_state->best_encoder); | |
11962 | if (!encoders_cloneable(encoder, source_encoder)) | |
11963 | return false; | |
11964 | } | |
11965 | ||
11966 | return true; | |
11967 | } | |
11968 | ||
11969 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11970 | struct intel_crtc *crtc) | |
11971 | { | |
11972 | struct intel_encoder *encoder; | |
11973 | struct drm_connector *connector; | |
11974 | struct drm_connector_state *connector_state; | |
11975 | int i; | |
11976 | ||
11977 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11978 | if (connector_state->crtc != &crtc->base) | |
11979 | continue; | |
11980 | ||
11981 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11982 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11983 | return false; | |
11984 | } | |
11985 | ||
11986 | return true; | |
11987 | } | |
11988 | ||
11989 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11990 | struct drm_crtc_state *crtc_state) | |
11991 | { | |
cf5a15be | 11992 | struct drm_device *dev = crtc->dev; |
ad421372 | 11993 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11994 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11995 | struct intel_crtc_state *pipe_config = |
11996 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11997 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11998 | int ret; |
6d3a1ce7 ML |
11999 | bool mode_changed = needs_modeset(crtc_state); |
12000 | ||
12001 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
12002 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12003 | return -EINVAL; | |
12004 | } | |
12005 | ||
852eb00d | 12006 | if (mode_changed && !crtc_state->active) |
92826fcd | 12007 | pipe_config->wm_changed = true; |
eddfcbcd | 12008 | |
ad421372 ML |
12009 | if (mode_changed && crtc_state->enable && |
12010 | dev_priv->display.crtc_compute_clock && | |
12011 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
12012 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
12013 | pipe_config); | |
12014 | if (ret) | |
12015 | return ret; | |
12016 | } | |
12017 | ||
e435d6e5 | 12018 | ret = 0; |
86c8bbbe MR |
12019 | if (dev_priv->display.compute_pipe_wm) { |
12020 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
12021 | if (ret) | |
12022 | return ret; | |
12023 | } | |
12024 | ||
e435d6e5 ML |
12025 | if (INTEL_INFO(dev)->gen >= 9) { |
12026 | if (mode_changed) | |
12027 | ret = skl_update_scaler_crtc(pipe_config); | |
12028 | ||
12029 | if (!ret) | |
12030 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12031 | pipe_config); | |
12032 | } | |
12033 | ||
12034 | return ret; | |
6d3a1ce7 ML |
12035 | } |
12036 | ||
65b38e0d | 12037 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
12038 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
12039 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
12040 | .atomic_begin = intel_begin_crtc_commit, |
12041 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12042 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12043 | }; |
12044 | ||
d29b2f9d ACO |
12045 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12046 | { | |
12047 | struct intel_connector *connector; | |
12048 | ||
12049 | for_each_intel_connector(dev, connector) { | |
12050 | if (connector->base.encoder) { | |
12051 | connector->base.state->best_encoder = | |
12052 | connector->base.encoder; | |
12053 | connector->base.state->crtc = | |
12054 | connector->base.encoder->crtc; | |
12055 | } else { | |
12056 | connector->base.state->best_encoder = NULL; | |
12057 | connector->base.state->crtc = NULL; | |
12058 | } | |
12059 | } | |
12060 | } | |
12061 | ||
050f7aeb | 12062 | static void |
eba905b2 | 12063 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12064 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12065 | { |
12066 | int bpp = pipe_config->pipe_bpp; | |
12067 | ||
12068 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12069 | connector->base.base.id, | |
c23cc417 | 12070 | connector->base.name); |
050f7aeb DV |
12071 | |
12072 | /* Don't use an invalid EDID bpc value */ | |
12073 | if (connector->base.display_info.bpc && | |
12074 | connector->base.display_info.bpc * 3 < bpp) { | |
12075 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12076 | bpp, connector->base.display_info.bpc*3); | |
12077 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12078 | } | |
12079 | ||
12080 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
12081 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
12082 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
12083 | bpp); | |
12084 | pipe_config->pipe_bpp = 24; | |
12085 | } | |
12086 | } | |
12087 | ||
4e53c2e0 | 12088 | static int |
050f7aeb | 12089 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12090 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12091 | { |
050f7aeb | 12092 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12093 | struct drm_atomic_state *state; |
da3ced29 ACO |
12094 | struct drm_connector *connector; |
12095 | struct drm_connector_state *connector_state; | |
1486017f | 12096 | int bpp, i; |
4e53c2e0 | 12097 | |
666a4537 | 12098 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12099 | bpp = 10*3; |
d328c9d7 DV |
12100 | else if (INTEL_INFO(dev)->gen >= 5) |
12101 | bpp = 12*3; | |
12102 | else | |
12103 | bpp = 8*3; | |
12104 | ||
4e53c2e0 | 12105 | |
4e53c2e0 DV |
12106 | pipe_config->pipe_bpp = bpp; |
12107 | ||
1486017f ACO |
12108 | state = pipe_config->base.state; |
12109 | ||
4e53c2e0 | 12110 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12111 | for_each_connector_in_state(state, connector, connector_state, i) { |
12112 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12113 | continue; |
12114 | ||
da3ced29 ACO |
12115 | connected_sink_compute_bpp(to_intel_connector(connector), |
12116 | pipe_config); | |
4e53c2e0 DV |
12117 | } |
12118 | ||
12119 | return bpp; | |
12120 | } | |
12121 | ||
644db711 DV |
12122 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12123 | { | |
12124 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12125 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12126 | mode->crtc_clock, |
644db711 DV |
12127 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12128 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12129 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12130 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12131 | } | |
12132 | ||
c0b03411 | 12133 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12134 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12135 | const char *context) |
12136 | { | |
6a60cd87 CK |
12137 | struct drm_device *dev = crtc->base.dev; |
12138 | struct drm_plane *plane; | |
12139 | struct intel_plane *intel_plane; | |
12140 | struct intel_plane_state *state; | |
12141 | struct drm_framebuffer *fb; | |
12142 | ||
12143 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12144 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12145 | |
12146 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12147 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12148 | pipe_config->pipe_bpp, pipe_config->dither); | |
12149 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12150 | pipe_config->has_pch_encoder, | |
12151 | pipe_config->fdi_lanes, | |
12152 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12153 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12154 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12155 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12156 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12157 | pipe_config->lane_count, |
eb14cb74 VS |
12158 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12159 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12160 | pipe_config->dp_m_n.tu); | |
b95af8be | 12161 | |
90a6b7b0 | 12162 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12163 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12164 | pipe_config->lane_count, |
b95af8be VK |
12165 | pipe_config->dp_m2_n2.gmch_m, |
12166 | pipe_config->dp_m2_n2.gmch_n, | |
12167 | pipe_config->dp_m2_n2.link_m, | |
12168 | pipe_config->dp_m2_n2.link_n, | |
12169 | pipe_config->dp_m2_n2.tu); | |
12170 | ||
55072d19 DV |
12171 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12172 | pipe_config->has_audio, | |
12173 | pipe_config->has_infoframe); | |
12174 | ||
c0b03411 | 12175 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12176 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12177 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12178 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12179 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12180 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12181 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12182 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12183 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12184 | crtc->num_scalers, | |
12185 | pipe_config->scaler_state.scaler_users, | |
12186 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12187 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12188 | pipe_config->gmch_pfit.control, | |
12189 | pipe_config->gmch_pfit.pgm_ratios, | |
12190 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12191 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12192 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12193 | pipe_config->pch_pfit.size, |
12194 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12195 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12196 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12197 | |
415ff0f6 | 12198 | if (IS_BROXTON(dev)) { |
05712c15 | 12199 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12200 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12201 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12202 | pipe_config->ddi_pll_sel, |
12203 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12204 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12205 | pipe_config->dpll_hw_state.pll0, |
12206 | pipe_config->dpll_hw_state.pll1, | |
12207 | pipe_config->dpll_hw_state.pll2, | |
12208 | pipe_config->dpll_hw_state.pll3, | |
12209 | pipe_config->dpll_hw_state.pll6, | |
12210 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12211 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12212 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12213 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12214 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12215 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12216 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12217 | pipe_config->ddi_pll_sel, | |
12218 | pipe_config->dpll_hw_state.ctrl1, | |
12219 | pipe_config->dpll_hw_state.cfgcr1, | |
12220 | pipe_config->dpll_hw_state.cfgcr2); | |
12221 | } else if (HAS_DDI(dev)) { | |
00490c22 | 12222 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12223 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12224 | pipe_config->dpll_hw_state.wrpll, |
12225 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12226 | } else { |
12227 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12228 | "fp0: 0x%x, fp1: 0x%x\n", | |
12229 | pipe_config->dpll_hw_state.dpll, | |
12230 | pipe_config->dpll_hw_state.dpll_md, | |
12231 | pipe_config->dpll_hw_state.fp0, | |
12232 | pipe_config->dpll_hw_state.fp1); | |
12233 | } | |
12234 | ||
6a60cd87 CK |
12235 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12236 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12237 | intel_plane = to_intel_plane(plane); | |
12238 | if (intel_plane->pipe != crtc->pipe) | |
12239 | continue; | |
12240 | ||
12241 | state = to_intel_plane_state(plane->state); | |
12242 | fb = state->base.fb; | |
12243 | if (!fb) { | |
12244 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12245 | "disabled, scaler_id = %d\n", | |
12246 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12247 | plane->base.id, intel_plane->pipe, | |
12248 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12249 | drm_plane_index(plane), state->scaler_id); | |
12250 | continue; | |
12251 | } | |
12252 | ||
12253 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12254 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12255 | plane->base.id, intel_plane->pipe, | |
12256 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12257 | drm_plane_index(plane)); | |
12258 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12259 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12260 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12261 | state->scaler_id, | |
12262 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12263 | drm_rect_width(&state->src) >> 16, | |
12264 | drm_rect_height(&state->src) >> 16, | |
12265 | state->dst.x1, state->dst.y1, | |
12266 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12267 | } | |
c0b03411 DV |
12268 | } |
12269 | ||
5448a00d | 12270 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12271 | { |
5448a00d ACO |
12272 | struct drm_device *dev = state->dev; |
12273 | struct intel_encoder *encoder; | |
da3ced29 | 12274 | struct drm_connector *connector; |
5448a00d | 12275 | struct drm_connector_state *connector_state; |
00f0b378 | 12276 | unsigned int used_ports = 0; |
5448a00d | 12277 | int i; |
00f0b378 VS |
12278 | |
12279 | /* | |
12280 | * Walk the connector list instead of the encoder | |
12281 | * list to detect the problem on ddi platforms | |
12282 | * where there's just one encoder per digital port. | |
12283 | */ | |
da3ced29 | 12284 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 12285 | if (!connector_state->best_encoder) |
00f0b378 VS |
12286 | continue; |
12287 | ||
5448a00d ACO |
12288 | encoder = to_intel_encoder(connector_state->best_encoder); |
12289 | ||
12290 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12291 | |
12292 | switch (encoder->type) { | |
12293 | unsigned int port_mask; | |
12294 | case INTEL_OUTPUT_UNKNOWN: | |
12295 | if (WARN_ON(!HAS_DDI(dev))) | |
12296 | break; | |
12297 | case INTEL_OUTPUT_DISPLAYPORT: | |
12298 | case INTEL_OUTPUT_HDMI: | |
12299 | case INTEL_OUTPUT_EDP: | |
12300 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12301 | ||
12302 | /* the same port mustn't appear more than once */ | |
12303 | if (used_ports & port_mask) | |
12304 | return false; | |
12305 | ||
12306 | used_ports |= port_mask; | |
12307 | default: | |
12308 | break; | |
12309 | } | |
12310 | } | |
12311 | ||
12312 | return true; | |
12313 | } | |
12314 | ||
83a57153 ACO |
12315 | static void |
12316 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12317 | { | |
12318 | struct drm_crtc_state tmp_state; | |
663a3640 | 12319 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12320 | struct intel_dpll_hw_state dpll_hw_state; |
12321 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12322 | uint32_t ddi_pll_sel; |
c4e2d043 | 12323 | bool force_thru; |
83a57153 | 12324 | |
7546a384 ACO |
12325 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12326 | * kzalloc'd. Code that depends on any field being zero should be | |
12327 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12328 | * only fields that are know to not cause problems are preserved. */ | |
12329 | ||
83a57153 | 12330 | tmp_state = crtc_state->base; |
663a3640 | 12331 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12332 | shared_dpll = crtc_state->shared_dpll; |
12333 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12334 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12335 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12336 | |
83a57153 | 12337 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12338 | |
83a57153 | 12339 | crtc_state->base = tmp_state; |
663a3640 | 12340 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12341 | crtc_state->shared_dpll = shared_dpll; |
12342 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12343 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12344 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12345 | } |
12346 | ||
548ee15b | 12347 | static int |
b8cecdf5 | 12348 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12349 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12350 | { |
b359283a | 12351 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12352 | struct intel_encoder *encoder; |
da3ced29 | 12353 | struct drm_connector *connector; |
0b901879 | 12354 | struct drm_connector_state *connector_state; |
d328c9d7 | 12355 | int base_bpp, ret = -EINVAL; |
0b901879 | 12356 | int i; |
e29c22c0 | 12357 | bool retry = true; |
ee7b9f93 | 12358 | |
83a57153 | 12359 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12360 | |
e143a21c DV |
12361 | pipe_config->cpu_transcoder = |
12362 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12363 | |
2960bc9c ID |
12364 | /* |
12365 | * Sanitize sync polarity flags based on requested ones. If neither | |
12366 | * positive or negative polarity is requested, treat this as meaning | |
12367 | * negative polarity. | |
12368 | */ | |
2d112de7 | 12369 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12370 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12371 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12372 | |
2d112de7 | 12373 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12374 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12375 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12376 | |
d328c9d7 DV |
12377 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12378 | pipe_config); | |
12379 | if (base_bpp < 0) | |
4e53c2e0 DV |
12380 | goto fail; |
12381 | ||
e41a56be VS |
12382 | /* |
12383 | * Determine the real pipe dimensions. Note that stereo modes can | |
12384 | * increase the actual pipe size due to the frame doubling and | |
12385 | * insertion of additional space for blanks between the frame. This | |
12386 | * is stored in the crtc timings. We use the requested mode to do this | |
12387 | * computation to clearly distinguish it from the adjusted mode, which | |
12388 | * can be changed by the connectors in the below retry loop. | |
12389 | */ | |
2d112de7 | 12390 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12391 | &pipe_config->pipe_src_w, |
12392 | &pipe_config->pipe_src_h); | |
e41a56be | 12393 | |
e29c22c0 | 12394 | encoder_retry: |
ef1b460d | 12395 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12396 | pipe_config->port_clock = 0; |
ef1b460d | 12397 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12398 | |
135c81b8 | 12399 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12400 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12401 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12402 | |
7758a113 DV |
12403 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12404 | * adjust it according to limitations or connector properties, and also | |
12405 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12406 | */ |
da3ced29 | 12407 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12408 | if (connector_state->crtc != crtc) |
7758a113 | 12409 | continue; |
7ae89233 | 12410 | |
0b901879 ACO |
12411 | encoder = to_intel_encoder(connector_state->best_encoder); |
12412 | ||
efea6e8e DV |
12413 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12414 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12415 | goto fail; |
12416 | } | |
ee7b9f93 | 12417 | } |
47f1c6c9 | 12418 | |
ff9a6750 DV |
12419 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12420 | * done afterwards in case the encoder adjusts the mode. */ | |
12421 | if (!pipe_config->port_clock) | |
2d112de7 | 12422 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12423 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12424 | |
a43f6e0f | 12425 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12426 | if (ret < 0) { |
7758a113 DV |
12427 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12428 | goto fail; | |
ee7b9f93 | 12429 | } |
e29c22c0 DV |
12430 | |
12431 | if (ret == RETRY) { | |
12432 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12433 | ret = -EINVAL; | |
12434 | goto fail; | |
12435 | } | |
12436 | ||
12437 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12438 | retry = false; | |
12439 | goto encoder_retry; | |
12440 | } | |
12441 | ||
e8fa4270 DV |
12442 | /* Dithering seems to not pass-through bits correctly when it should, so |
12443 | * only enable it on 6bpc panels. */ | |
12444 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12445 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12446 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12447 | |
7758a113 | 12448 | fail: |
548ee15b | 12449 | return ret; |
ee7b9f93 | 12450 | } |
47f1c6c9 | 12451 | |
ea9d758d | 12452 | static void |
4740b0f2 | 12453 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12454 | { |
0a9ab303 ACO |
12455 | struct drm_crtc *crtc; |
12456 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12457 | int i; |
ea9d758d | 12458 | |
7668851f | 12459 | /* Double check state. */ |
8a75d157 | 12460 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12461 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12462 | |
12463 | /* Update hwmode for vblank functions */ | |
12464 | if (crtc->state->active) | |
12465 | crtc->hwmode = crtc->state->adjusted_mode; | |
12466 | else | |
12467 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12468 | |
12469 | /* | |
12470 | * Update legacy state to satisfy fbc code. This can | |
12471 | * be removed when fbc uses the atomic state. | |
12472 | */ | |
12473 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12474 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12475 | ||
12476 | crtc->primary->fb = plane_state->fb; | |
12477 | crtc->x = plane_state->src_x >> 16; | |
12478 | crtc->y = plane_state->src_y >> 16; | |
12479 | } | |
ea9d758d | 12480 | } |
ea9d758d DV |
12481 | } |
12482 | ||
3bd26263 | 12483 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12484 | { |
3bd26263 | 12485 | int diff; |
f1f644dc JB |
12486 | |
12487 | if (clock1 == clock2) | |
12488 | return true; | |
12489 | ||
12490 | if (!clock1 || !clock2) | |
12491 | return false; | |
12492 | ||
12493 | diff = abs(clock1 - clock2); | |
12494 | ||
12495 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12496 | return true; | |
12497 | ||
12498 | return false; | |
12499 | } | |
12500 | ||
25c5b266 DV |
12501 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12502 | list_for_each_entry((intel_crtc), \ | |
12503 | &(dev)->mode_config.crtc_list, \ | |
12504 | base.head) \ | |
95150bdf | 12505 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12506 | |
cfb23ed6 ML |
12507 | static bool |
12508 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12509 | unsigned int m2, unsigned int n2, | |
12510 | bool exact) | |
12511 | { | |
12512 | if (m == m2 && n == n2) | |
12513 | return true; | |
12514 | ||
12515 | if (exact || !m || !n || !m2 || !n2) | |
12516 | return false; | |
12517 | ||
12518 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12519 | ||
12520 | if (m > m2) { | |
12521 | while (m > m2) { | |
12522 | m2 <<= 1; | |
12523 | n2 <<= 1; | |
12524 | } | |
12525 | } else if (m < m2) { | |
12526 | while (m < m2) { | |
12527 | m <<= 1; | |
12528 | n <<= 1; | |
12529 | } | |
12530 | } | |
12531 | ||
12532 | return m == m2 && n == n2; | |
12533 | } | |
12534 | ||
12535 | static bool | |
12536 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12537 | struct intel_link_m_n *m2_n2, | |
12538 | bool adjust) | |
12539 | { | |
12540 | if (m_n->tu == m2_n2->tu && | |
12541 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12542 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12543 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12544 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12545 | if (adjust) | |
12546 | *m2_n2 = *m_n; | |
12547 | ||
12548 | return true; | |
12549 | } | |
12550 | ||
12551 | return false; | |
12552 | } | |
12553 | ||
0e8ffe1b | 12554 | static bool |
2fa2fe9a | 12555 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12556 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12557 | struct intel_crtc_state *pipe_config, |
12558 | bool adjust) | |
0e8ffe1b | 12559 | { |
cfb23ed6 ML |
12560 | bool ret = true; |
12561 | ||
12562 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12563 | do { \ | |
12564 | if (!adjust) \ | |
12565 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12566 | else \ | |
12567 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12568 | } while (0) | |
12569 | ||
66e985c0 DV |
12570 | #define PIPE_CONF_CHECK_X(name) \ |
12571 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12572 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12573 | "(expected 0x%08x, found 0x%08x)\n", \ |
12574 | current_config->name, \ | |
12575 | pipe_config->name); \ | |
cfb23ed6 | 12576 | ret = false; \ |
66e985c0 DV |
12577 | } |
12578 | ||
08a24034 DV |
12579 | #define PIPE_CONF_CHECK_I(name) \ |
12580 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12581 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12582 | "(expected %i, found %i)\n", \ |
12583 | current_config->name, \ | |
12584 | pipe_config->name); \ | |
cfb23ed6 ML |
12585 | ret = false; \ |
12586 | } | |
12587 | ||
12588 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12589 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12590 | &pipe_config->name,\ | |
12591 | adjust)) { \ | |
12592 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12593 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12594 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12595 | current_config->name.tu, \ | |
12596 | current_config->name.gmch_m, \ | |
12597 | current_config->name.gmch_n, \ | |
12598 | current_config->name.link_m, \ | |
12599 | current_config->name.link_n, \ | |
12600 | pipe_config->name.tu, \ | |
12601 | pipe_config->name.gmch_m, \ | |
12602 | pipe_config->name.gmch_n, \ | |
12603 | pipe_config->name.link_m, \ | |
12604 | pipe_config->name.link_n); \ | |
12605 | ret = false; \ | |
12606 | } | |
12607 | ||
12608 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12609 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12610 | &pipe_config->name, adjust) && \ | |
12611 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12612 | &pipe_config->name, adjust)) { \ | |
12613 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12614 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12615 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12616 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12617 | current_config->name.tu, \ | |
12618 | current_config->name.gmch_m, \ | |
12619 | current_config->name.gmch_n, \ | |
12620 | current_config->name.link_m, \ | |
12621 | current_config->name.link_n, \ | |
12622 | current_config->alt_name.tu, \ | |
12623 | current_config->alt_name.gmch_m, \ | |
12624 | current_config->alt_name.gmch_n, \ | |
12625 | current_config->alt_name.link_m, \ | |
12626 | current_config->alt_name.link_n, \ | |
12627 | pipe_config->name.tu, \ | |
12628 | pipe_config->name.gmch_m, \ | |
12629 | pipe_config->name.gmch_n, \ | |
12630 | pipe_config->name.link_m, \ | |
12631 | pipe_config->name.link_n); \ | |
12632 | ret = false; \ | |
88adfff1 DV |
12633 | } |
12634 | ||
b95af8be VK |
12635 | /* This is required for BDW+ where there is only one set of registers for |
12636 | * switching between high and low RR. | |
12637 | * This macro can be used whenever a comparison has to be made between one | |
12638 | * hw state and multiple sw state variables. | |
12639 | */ | |
12640 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12641 | if ((current_config->name != pipe_config->name) && \ | |
12642 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12643 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12644 | "(expected %i or %i, found %i)\n", \ |
12645 | current_config->name, \ | |
12646 | current_config->alt_name, \ | |
12647 | pipe_config->name); \ | |
cfb23ed6 | 12648 | ret = false; \ |
b95af8be VK |
12649 | } |
12650 | ||
1bd1bd80 DV |
12651 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12652 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12653 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12654 | "(expected %i, found %i)\n", \ |
12655 | current_config->name & (mask), \ | |
12656 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12657 | ret = false; \ |
1bd1bd80 DV |
12658 | } |
12659 | ||
5e550656 VS |
12660 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12661 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12662 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12663 | "(expected %i, found %i)\n", \ |
12664 | current_config->name, \ | |
12665 | pipe_config->name); \ | |
cfb23ed6 | 12666 | ret = false; \ |
5e550656 VS |
12667 | } |
12668 | ||
bb760063 DV |
12669 | #define PIPE_CONF_QUIRK(quirk) \ |
12670 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12671 | ||
eccb140b DV |
12672 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12673 | ||
08a24034 DV |
12674 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12675 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12676 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12677 | |
eb14cb74 | 12678 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12679 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12680 | |
12681 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12682 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12683 | ||
cfb23ed6 ML |
12684 | if (current_config->has_drrs) |
12685 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12686 | } else | |
12687 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12688 | |
a65347ba JN |
12689 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12690 | ||
2d112de7 ACO |
12691 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12692 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12693 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12694 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12695 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12696 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12697 | |
2d112de7 ACO |
12698 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12699 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12700 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12701 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12702 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12703 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12704 | |
c93f54cf | 12705 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12706 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12707 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12708 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12709 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12710 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12711 | |
9ed109a7 DV |
12712 | PIPE_CONF_CHECK_I(has_audio); |
12713 | ||
2d112de7 | 12714 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12715 | DRM_MODE_FLAG_INTERLACE); |
12716 | ||
bb760063 | 12717 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12718 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12719 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12720 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12721 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12722 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12723 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12724 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12725 | DRM_MODE_FLAG_NVSYNC); |
12726 | } | |
045ac3b5 | 12727 | |
333b8ca8 | 12728 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12729 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12730 | if (INTEL_INFO(dev)->gen < 4) | |
12731 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12732 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12733 | |
bfd16b2a ML |
12734 | if (!adjust) { |
12735 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12736 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12737 | ||
12738 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12739 | if (current_config->pch_pfit.enabled) { | |
12740 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12741 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12742 | } | |
2fa2fe9a | 12743 | |
7aefe2b5 ML |
12744 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12745 | } | |
a1b2278e | 12746 | |
e59150dc JB |
12747 | /* BDW+ don't expose a synchronous way to read the state */ |
12748 | if (IS_HASWELL(dev)) | |
12749 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12750 | |
282740f7 VS |
12751 | PIPE_CONF_CHECK_I(double_wide); |
12752 | ||
26804afd DV |
12753 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12754 | ||
c0d43d62 | 12755 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12756 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12757 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12758 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12759 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12760 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12761 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12762 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12763 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12764 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12765 | |
42571aef VS |
12766 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12767 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12768 | ||
2d112de7 | 12769 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12770 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12771 | |
66e985c0 | 12772 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12773 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12774 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12775 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12776 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12777 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12778 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12779 | |
cfb23ed6 | 12780 | return ret; |
0e8ffe1b DV |
12781 | } |
12782 | ||
08db6652 DL |
12783 | static void check_wm_state(struct drm_device *dev) |
12784 | { | |
12785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12786 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12787 | struct intel_crtc *intel_crtc; | |
12788 | int plane; | |
12789 | ||
12790 | if (INTEL_INFO(dev)->gen < 9) | |
12791 | return; | |
12792 | ||
12793 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12794 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12795 | ||
12796 | for_each_intel_crtc(dev, intel_crtc) { | |
12797 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12798 | const enum pipe pipe = intel_crtc->pipe; | |
12799 | ||
12800 | if (!intel_crtc->active) | |
12801 | continue; | |
12802 | ||
12803 | /* planes */ | |
dd740780 | 12804 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12805 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12806 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12807 | ||
12808 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12809 | continue; | |
12810 | ||
12811 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12812 | "(expected (%u,%u), found (%u,%u))\n", | |
12813 | pipe_name(pipe), plane + 1, | |
12814 | sw_entry->start, sw_entry->end, | |
12815 | hw_entry->start, hw_entry->end); | |
12816 | } | |
12817 | ||
12818 | /* cursor */ | |
4969d33e MR |
12819 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12820 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12821 | |
12822 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12823 | continue; | |
12824 | ||
12825 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12826 | "(expected (%u,%u), found (%u,%u))\n", | |
12827 | pipe_name(pipe), | |
12828 | sw_entry->start, sw_entry->end, | |
12829 | hw_entry->start, hw_entry->end); | |
12830 | } | |
12831 | } | |
12832 | ||
91d1b4bd | 12833 | static void |
35dd3c64 ML |
12834 | check_connector_state(struct drm_device *dev, |
12835 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12836 | { |
35dd3c64 ML |
12837 | struct drm_connector_state *old_conn_state; |
12838 | struct drm_connector *connector; | |
12839 | int i; | |
8af6cf88 | 12840 | |
35dd3c64 ML |
12841 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12842 | struct drm_encoder *encoder = connector->encoder; | |
12843 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12844 | |
8af6cf88 DV |
12845 | /* This also checks the encoder/connector hw state with the |
12846 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12847 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12848 | |
ad3c558f | 12849 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12850 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12851 | } |
91d1b4bd DV |
12852 | } |
12853 | ||
12854 | static void | |
12855 | check_encoder_state(struct drm_device *dev) | |
12856 | { | |
12857 | struct intel_encoder *encoder; | |
12858 | struct intel_connector *connector; | |
8af6cf88 | 12859 | |
b2784e15 | 12860 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12861 | bool enabled = false; |
4d20cd86 | 12862 | enum pipe pipe; |
8af6cf88 DV |
12863 | |
12864 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12865 | encoder->base.base.id, | |
8e329a03 | 12866 | encoder->base.name); |
8af6cf88 | 12867 | |
3a3371ff | 12868 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12869 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12870 | continue; |
12871 | enabled = true; | |
ad3c558f ML |
12872 | |
12873 | I915_STATE_WARN(connector->base.state->crtc != | |
12874 | encoder->base.crtc, | |
12875 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12876 | } |
0e32b39c | 12877 | |
e2c719b7 | 12878 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12879 | "encoder's enabled state mismatch " |
12880 | "(expected %i, found %i)\n", | |
12881 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12882 | |
12883 | if (!encoder->base.crtc) { | |
4d20cd86 | 12884 | bool active; |
7c60d198 | 12885 | |
4d20cd86 ML |
12886 | active = encoder->get_hw_state(encoder, &pipe); |
12887 | I915_STATE_WARN(active, | |
12888 | "encoder detached but still enabled on pipe %c.\n", | |
12889 | pipe_name(pipe)); | |
7c60d198 | 12890 | } |
8af6cf88 | 12891 | } |
91d1b4bd DV |
12892 | } |
12893 | ||
12894 | static void | |
4d20cd86 | 12895 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12896 | { |
fbee40df | 12897 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12898 | struct intel_encoder *encoder; |
4d20cd86 ML |
12899 | struct drm_crtc_state *old_crtc_state; |
12900 | struct drm_crtc *crtc; | |
12901 | int i; | |
8af6cf88 | 12902 | |
4d20cd86 ML |
12903 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12904 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12905 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12906 | bool active; |
8af6cf88 | 12907 | |
bfd16b2a ML |
12908 | if (!needs_modeset(crtc->state) && |
12909 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12910 | continue; |
045ac3b5 | 12911 | |
4d20cd86 ML |
12912 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12913 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12914 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12915 | pipe_config->base.crtc = crtc; | |
12916 | pipe_config->base.state = old_state; | |
8af6cf88 | 12917 | |
4d20cd86 ML |
12918 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12919 | crtc->base.id); | |
8af6cf88 | 12920 | |
4d20cd86 ML |
12921 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12922 | pipe_config); | |
d62cf62a | 12923 | |
b6b5d049 | 12924 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12925 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12926 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12927 | active = crtc->state->active; | |
6c49f241 | 12928 | |
4d20cd86 | 12929 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12930 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12931 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12932 | |
4d20cd86 | 12933 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12934 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12935 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12936 | ||
12937 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12938 | enum pipe pipe; | |
12939 | ||
12940 | active = encoder->get_hw_state(encoder, &pipe); | |
12941 | I915_STATE_WARN(active != crtc->state->active, | |
12942 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12943 | encoder->base.base.id, active, crtc->state->active); | |
12944 | ||
12945 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12946 | "Encoder connected to wrong pipe %c\n", | |
12947 | pipe_name(pipe)); | |
12948 | ||
12949 | if (active) | |
12950 | encoder->get_config(encoder, pipe_config); | |
12951 | } | |
53d9f4e9 | 12952 | |
4d20cd86 | 12953 | if (!crtc->state->active) |
cfb23ed6 ML |
12954 | continue; |
12955 | ||
4d20cd86 ML |
12956 | sw_config = to_intel_crtc_state(crtc->state); |
12957 | if (!intel_pipe_config_compare(dev, sw_config, | |
12958 | pipe_config, false)) { | |
e2c719b7 | 12959 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12960 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12961 | "[hw state]"); |
4d20cd86 | 12962 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12963 | "[sw state]"); |
12964 | } | |
8af6cf88 DV |
12965 | } |
12966 | } | |
12967 | ||
91d1b4bd DV |
12968 | static void |
12969 | check_shared_dpll_state(struct drm_device *dev) | |
12970 | { | |
fbee40df | 12971 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12972 | struct intel_crtc *crtc; |
12973 | struct intel_dpll_hw_state dpll_hw_state; | |
12974 | int i; | |
5358901f DV |
12975 | |
12976 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12977 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12978 | int enabled_crtcs = 0, active_crtcs = 0; | |
12979 | bool active; | |
12980 | ||
12981 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12982 | ||
12983 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12984 | ||
12985 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12986 | ||
e2c719b7 | 12987 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12988 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12989 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12990 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12991 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12992 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12993 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12994 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12995 | "pll on state mismatch (expected %i, found %i)\n", |
12996 | pll->on, active); | |
12997 | ||
d3fcc808 | 12998 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12999 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
13000 | enabled_crtcs++; |
13001 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
13002 | active_crtcs++; | |
13003 | } | |
e2c719b7 | 13004 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
13005 | "pll active crtcs mismatch (expected %i, found %i)\n", |
13006 | pll->active, active_crtcs); | |
e2c719b7 | 13007 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 13008 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 13009 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 13010 | |
e2c719b7 | 13011 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
13012 | sizeof(dpll_hw_state)), |
13013 | "pll hw state mismatch\n"); | |
5358901f | 13014 | } |
8af6cf88 DV |
13015 | } |
13016 | ||
ee165b1a ML |
13017 | static void |
13018 | intel_modeset_check_state(struct drm_device *dev, | |
13019 | struct drm_atomic_state *old_state) | |
91d1b4bd | 13020 | { |
08db6652 | 13021 | check_wm_state(dev); |
35dd3c64 | 13022 | check_connector_state(dev, old_state); |
91d1b4bd | 13023 | check_encoder_state(dev); |
4d20cd86 | 13024 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
13025 | check_shared_dpll_state(dev); |
13026 | } | |
13027 | ||
5cec258b | 13028 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
13029 | int dotclock) |
13030 | { | |
13031 | /* | |
13032 | * FDI already provided one idea for the dotclock. | |
13033 | * Yell if the encoder disagrees. | |
13034 | */ | |
2d112de7 | 13035 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 13036 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 13037 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
13038 | } |
13039 | ||
80715b2f VS |
13040 | static void update_scanline_offset(struct intel_crtc *crtc) |
13041 | { | |
13042 | struct drm_device *dev = crtc->base.dev; | |
13043 | ||
13044 | /* | |
13045 | * The scanline counter increments at the leading edge of hsync. | |
13046 | * | |
13047 | * On most platforms it starts counting from vtotal-1 on the | |
13048 | * first active line. That means the scanline counter value is | |
13049 | * always one less than what we would expect. Ie. just after | |
13050 | * start of vblank, which also occurs at start of hsync (on the | |
13051 | * last active line), the scanline counter will read vblank_start-1. | |
13052 | * | |
13053 | * On gen2 the scanline counter starts counting from 1 instead | |
13054 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13055 | * to keep the value positive), instead of adding one. | |
13056 | * | |
13057 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13058 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13059 | * there's an extra 1 line difference. So we need to add two instead of | |
13060 | * one to the value. | |
13061 | */ | |
13062 | if (IS_GEN2(dev)) { | |
124abe07 | 13063 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13064 | int vtotal; |
13065 | ||
124abe07 VS |
13066 | vtotal = adjusted_mode->crtc_vtotal; |
13067 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13068 | vtotal /= 2; |
13069 | ||
13070 | crtc->scanline_offset = vtotal - 1; | |
13071 | } else if (HAS_DDI(dev) && | |
409ee761 | 13072 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13073 | crtc->scanline_offset = 2; |
13074 | } else | |
13075 | crtc->scanline_offset = 1; | |
13076 | } | |
13077 | ||
ad421372 | 13078 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13079 | { |
225da59b | 13080 | struct drm_device *dev = state->dev; |
ed6739ef | 13081 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13082 | struct intel_shared_dpll_config *shared_dpll = NULL; |
ed6739ef | 13083 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
13084 | struct intel_crtc_state *intel_crtc_state; |
13085 | struct drm_crtc *crtc; | |
13086 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13087 | int i; |
ed6739ef ACO |
13088 | |
13089 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13090 | return; |
ed6739ef | 13091 | |
0a9ab303 | 13092 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
ad421372 ML |
13093 | int dpll; |
13094 | ||
0a9ab303 | 13095 | intel_crtc = to_intel_crtc(crtc); |
4978cc93 | 13096 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
ad421372 | 13097 | dpll = intel_crtc_state->shared_dpll; |
0a9ab303 | 13098 | |
ad421372 | 13099 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
225da59b ACO |
13100 | continue; |
13101 | ||
ad421372 | 13102 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
0a9ab303 | 13103 | |
ad421372 ML |
13104 | if (!shared_dpll) |
13105 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13106 | |
ad421372 ML |
13107 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
13108 | } | |
ed6739ef ACO |
13109 | } |
13110 | ||
99d736a2 ML |
13111 | /* |
13112 | * This implements the workaround described in the "notes" section of the mode | |
13113 | * set sequence documentation. When going from no pipes or single pipe to | |
13114 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13115 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13116 | */ | |
13117 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13118 | { | |
13119 | struct drm_crtc_state *crtc_state; | |
13120 | struct intel_crtc *intel_crtc; | |
13121 | struct drm_crtc *crtc; | |
13122 | struct intel_crtc_state *first_crtc_state = NULL; | |
13123 | struct intel_crtc_state *other_crtc_state = NULL; | |
13124 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13125 | int i; | |
13126 | ||
13127 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13128 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13129 | intel_crtc = to_intel_crtc(crtc); | |
13130 | ||
13131 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13132 | continue; | |
13133 | ||
13134 | if (first_crtc_state) { | |
13135 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13136 | break; | |
13137 | } else { | |
13138 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13139 | first_pipe = intel_crtc->pipe; | |
13140 | } | |
13141 | } | |
13142 | ||
13143 | /* No workaround needed? */ | |
13144 | if (!first_crtc_state) | |
13145 | return 0; | |
13146 | ||
13147 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13148 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13149 | struct intel_crtc_state *pipe_config; | |
13150 | ||
13151 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13152 | if (IS_ERR(pipe_config)) | |
13153 | return PTR_ERR(pipe_config); | |
13154 | ||
13155 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13156 | ||
13157 | if (!pipe_config->base.active || | |
13158 | needs_modeset(&pipe_config->base)) | |
13159 | continue; | |
13160 | ||
13161 | /* 2 or more enabled crtcs means no need for w/a */ | |
13162 | if (enabled_pipe != INVALID_PIPE) | |
13163 | return 0; | |
13164 | ||
13165 | enabled_pipe = intel_crtc->pipe; | |
13166 | } | |
13167 | ||
13168 | if (enabled_pipe != INVALID_PIPE) | |
13169 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13170 | else if (other_crtc_state) | |
13171 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13172 | ||
13173 | return 0; | |
13174 | } | |
13175 | ||
27c329ed ML |
13176 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13177 | { | |
13178 | struct drm_crtc *crtc; | |
13179 | struct drm_crtc_state *crtc_state; | |
13180 | int ret = 0; | |
13181 | ||
13182 | /* add all active pipes to the state */ | |
13183 | for_each_crtc(state->dev, crtc) { | |
13184 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13185 | if (IS_ERR(crtc_state)) | |
13186 | return PTR_ERR(crtc_state); | |
13187 | ||
13188 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13189 | continue; | |
13190 | ||
13191 | crtc_state->mode_changed = true; | |
13192 | ||
13193 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13194 | if (ret) | |
13195 | break; | |
13196 | ||
13197 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13198 | if (ret) | |
13199 | break; | |
13200 | } | |
13201 | ||
13202 | return ret; | |
13203 | } | |
13204 | ||
c347a676 | 13205 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd ACO |
13206 | { |
13207 | struct drm_device *dev = state->dev; | |
27c329ed | 13208 | struct drm_i915_private *dev_priv = dev->dev_private; |
054518dd ACO |
13209 | int ret; |
13210 | ||
b359283a ML |
13211 | if (!check_digital_port_conflicts(state)) { |
13212 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13213 | return -EINVAL; | |
13214 | } | |
13215 | ||
054518dd ACO |
13216 | /* |
13217 | * See if the config requires any additional preparation, e.g. | |
13218 | * to adjust global state with pipes off. We need to do this | |
13219 | * here so we can get the modeset_pipe updated config for the new | |
13220 | * mode set on this crtc. For other crtcs we need to use the | |
13221 | * adjusted_mode bits in the crtc directly. | |
13222 | */ | |
27c329ed ML |
13223 | if (dev_priv->display.modeset_calc_cdclk) { |
13224 | unsigned int cdclk; | |
b432e5cf | 13225 | |
27c329ed ML |
13226 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13227 | ||
13228 | cdclk = to_intel_atomic_state(state)->cdclk; | |
13229 | if (!ret && cdclk != dev_priv->cdclk_freq) | |
13230 | ret = intel_modeset_all_pipes(state); | |
13231 | ||
13232 | if (ret < 0) | |
054518dd | 13233 | return ret; |
27c329ed ML |
13234 | } else |
13235 | to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq; | |
054518dd | 13236 | |
ad421372 | 13237 | intel_modeset_clear_plls(state); |
054518dd | 13238 | |
99d736a2 | 13239 | if (IS_HASWELL(dev)) |
ad421372 | 13240 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13241 | |
ad421372 | 13242 | return 0; |
c347a676 ACO |
13243 | } |
13244 | ||
aa363136 MR |
13245 | /* |
13246 | * Handle calculation of various watermark data at the end of the atomic check | |
13247 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13248 | * handlers to ensure that all derived state has been updated. | |
13249 | */ | |
13250 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13251 | { | |
13252 | struct drm_device *dev = state->dev; | |
13253 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13254 | struct drm_crtc *crtc; | |
13255 | struct drm_crtc_state *cstate; | |
13256 | struct drm_plane *plane; | |
13257 | struct drm_plane_state *pstate; | |
13258 | ||
13259 | /* | |
13260 | * Calculate watermark configuration details now that derived | |
13261 | * plane/crtc state is all properly updated. | |
13262 | */ | |
13263 | drm_for_each_crtc(crtc, dev) { | |
13264 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13265 | crtc->state; | |
13266 | ||
13267 | if (cstate->active) | |
13268 | intel_state->wm_config.num_pipes_active++; | |
13269 | } | |
13270 | drm_for_each_legacy_plane(plane, dev) { | |
13271 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13272 | plane->state; | |
13273 | ||
13274 | if (!to_intel_plane_state(pstate)->visible) | |
13275 | continue; | |
13276 | ||
13277 | intel_state->wm_config.sprites_enabled = true; | |
13278 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13279 | pstate->crtc_h != pstate->src_h >> 16) | |
13280 | intel_state->wm_config.sprites_scaled = true; | |
13281 | } | |
13282 | } | |
13283 | ||
74c090b1 ML |
13284 | /** |
13285 | * intel_atomic_check - validate state object | |
13286 | * @dev: drm device | |
13287 | * @state: state to validate | |
13288 | */ | |
13289 | static int intel_atomic_check(struct drm_device *dev, | |
13290 | struct drm_atomic_state *state) | |
c347a676 | 13291 | { |
aa363136 | 13292 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13293 | struct drm_crtc *crtc; |
13294 | struct drm_crtc_state *crtc_state; | |
13295 | int ret, i; | |
61333b60 | 13296 | bool any_ms = false; |
c347a676 | 13297 | |
74c090b1 | 13298 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13299 | if (ret) |
13300 | return ret; | |
13301 | ||
c347a676 | 13302 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13303 | struct intel_crtc_state *pipe_config = |
13304 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13305 | |
ba8af3e5 ML |
13306 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13307 | sizeof(struct intel_crtc_atomic_commit)); | |
13308 | ||
1ed51de9 DV |
13309 | /* Catch I915_MODE_FLAG_INHERITED */ |
13310 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13311 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13312 | |
61333b60 ML |
13313 | if (!crtc_state->enable) { |
13314 | if (needs_modeset(crtc_state)) | |
13315 | any_ms = true; | |
c347a676 | 13316 | continue; |
61333b60 | 13317 | } |
c347a676 | 13318 | |
26495481 | 13319 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13320 | continue; |
13321 | ||
26495481 DV |
13322 | /* FIXME: For only active_changed we shouldn't need to do any |
13323 | * state recomputation at all. */ | |
13324 | ||
1ed51de9 DV |
13325 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13326 | if (ret) | |
13327 | return ret; | |
b359283a | 13328 | |
cfb23ed6 | 13329 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13330 | if (ret) |
13331 | return ret; | |
13332 | ||
73831236 JN |
13333 | if (i915.fastboot && |
13334 | intel_pipe_config_compare(state->dev, | |
cfb23ed6 | 13335 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13336 | pipe_config, true)) { |
26495481 | 13337 | crtc_state->mode_changed = false; |
bfd16b2a | 13338 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13339 | } |
13340 | ||
13341 | if (needs_modeset(crtc_state)) { | |
13342 | any_ms = true; | |
cfb23ed6 ML |
13343 | |
13344 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13345 | if (ret) | |
13346 | return ret; | |
13347 | } | |
61333b60 | 13348 | |
26495481 DV |
13349 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13350 | needs_modeset(crtc_state) ? | |
13351 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13352 | } |
13353 | ||
61333b60 ML |
13354 | if (any_ms) { |
13355 | ret = intel_modeset_checks(state); | |
13356 | ||
13357 | if (ret) | |
13358 | return ret; | |
27c329ed | 13359 | } else |
aa363136 | 13360 | intel_state->cdclk = to_i915(state->dev)->cdclk_freq; |
76305b1a | 13361 | |
aa363136 MR |
13362 | ret = drm_atomic_helper_check_planes(state->dev, state); |
13363 | if (ret) | |
13364 | return ret; | |
13365 | ||
13366 | calc_watermark_data(state); | |
13367 | ||
13368 | return 0; | |
054518dd ACO |
13369 | } |
13370 | ||
5008e874 ML |
13371 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13372 | struct drm_atomic_state *state, | |
13373 | bool async) | |
13374 | { | |
7580d774 ML |
13375 | struct drm_i915_private *dev_priv = dev->dev_private; |
13376 | struct drm_plane_state *plane_state; | |
5008e874 | 13377 | struct drm_crtc_state *crtc_state; |
7580d774 | 13378 | struct drm_plane *plane; |
5008e874 ML |
13379 | struct drm_crtc *crtc; |
13380 | int i, ret; | |
13381 | ||
13382 | if (async) { | |
13383 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13384 | return -EINVAL; | |
13385 | } | |
13386 | ||
13387 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13388 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13389 | if (ret) | |
13390 | return ret; | |
7580d774 ML |
13391 | |
13392 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13393 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13394 | } |
13395 | ||
f935675f ML |
13396 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13397 | if (ret) | |
13398 | return ret; | |
13399 | ||
5008e874 | 13400 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13401 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13402 | u32 reset_counter; | |
13403 | ||
13404 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13405 | mutex_unlock(&dev->struct_mutex); | |
13406 | ||
13407 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13408 | struct intel_plane_state *intel_plane_state = | |
13409 | to_intel_plane_state(plane_state); | |
13410 | ||
13411 | if (!intel_plane_state->wait_req) | |
13412 | continue; | |
13413 | ||
13414 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13415 | reset_counter, true, | |
13416 | NULL, NULL); | |
13417 | ||
13418 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13419 | if (ret == -EIO) | |
13420 | ret = 0; | |
13421 | ||
13422 | if (ret) | |
13423 | break; | |
13424 | } | |
13425 | ||
13426 | if (!ret) | |
13427 | return 0; | |
13428 | ||
13429 | mutex_lock(&dev->struct_mutex); | |
13430 | drm_atomic_helper_cleanup_planes(dev, state); | |
13431 | } | |
5008e874 | 13432 | |
f935675f | 13433 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13434 | return ret; |
13435 | } | |
13436 | ||
74c090b1 ML |
13437 | /** |
13438 | * intel_atomic_commit - commit validated state object | |
13439 | * @dev: DRM device | |
13440 | * @state: the top-level driver state object | |
13441 | * @async: asynchronous commit | |
13442 | * | |
13443 | * This function commits a top-level state object that has been validated | |
13444 | * with drm_atomic_helper_check(). | |
13445 | * | |
13446 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13447 | * we can only handle plane-related operations and do not yet support | |
13448 | * asynchronous commit. | |
13449 | * | |
13450 | * RETURNS | |
13451 | * Zero for success or -errno. | |
13452 | */ | |
13453 | static int intel_atomic_commit(struct drm_device *dev, | |
13454 | struct drm_atomic_state *state, | |
13455 | bool async) | |
a6778b3c | 13456 | { |
fbee40df | 13457 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13458 | struct drm_crtc_state *crtc_state; |
7580d774 | 13459 | struct drm_crtc *crtc; |
c0c36b94 | 13460 | int ret = 0; |
0a9ab303 | 13461 | int i; |
61333b60 | 13462 | bool any_ms = false; |
a6778b3c | 13463 | |
5008e874 | 13464 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13465 | if (ret) { |
13466 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13467 | return ret; |
7580d774 | 13468 | } |
d4afb8cc | 13469 | |
1c5e19f8 | 13470 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13471 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13472 | |
0a9ab303 | 13473 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13474 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13475 | ||
61333b60 ML |
13476 | if (!needs_modeset(crtc->state)) |
13477 | continue; | |
13478 | ||
13479 | any_ms = true; | |
a539205a | 13480 | intel_pre_plane_update(intel_crtc); |
460da916 | 13481 | |
a539205a ML |
13482 | if (crtc_state->active) { |
13483 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13484 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd ML |
13485 | intel_crtc->active = false; |
13486 | intel_disable_shared_dpll(intel_crtc); | |
9bbc8258 VS |
13487 | |
13488 | /* | |
13489 | * Underruns don't always raise | |
13490 | * interrupts, so check manually. | |
13491 | */ | |
13492 | intel_check_cpu_fifo_underruns(dev_priv); | |
13493 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13494 | |
13495 | if (!crtc->state->active) | |
13496 | intel_update_watermarks(crtc); | |
a539205a | 13497 | } |
b8cecdf5 | 13498 | } |
7758a113 | 13499 | |
ea9d758d DV |
13500 | /* Only after disabling all output pipelines that will be changed can we |
13501 | * update the the output configuration. */ | |
4740b0f2 | 13502 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13503 | |
4740b0f2 ML |
13504 | if (any_ms) { |
13505 | intel_shared_dpll_commit(state); | |
13506 | ||
13507 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13508 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13509 | } |
47fab737 | 13510 | |
a6778b3c | 13511 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13512 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13513 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13514 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13515 | bool update_pipe = !modeset && |
13516 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13517 | unsigned long put_domains = 0; | |
f6ac4b2a | 13518 | |
9f836f90 PJ |
13519 | if (modeset) |
13520 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
13521 | ||
f6ac4b2a | 13522 | if (modeset && crtc->state->active) { |
a539205a ML |
13523 | update_scanline_offset(to_intel_crtc(crtc)); |
13524 | dev_priv->display.crtc_enable(crtc); | |
13525 | } | |
80715b2f | 13526 | |
bfd16b2a ML |
13527 | if (update_pipe) { |
13528 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13529 | ||
13530 | /* make sure intel_modeset_check_state runs */ | |
13531 | any_ms = true; | |
13532 | } | |
13533 | ||
f6ac4b2a ML |
13534 | if (!modeset) |
13535 | intel_pre_plane_update(intel_crtc); | |
13536 | ||
6173ee28 ML |
13537 | if (crtc->state->active && |
13538 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13539 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13540 | |
13541 | if (put_domains) | |
13542 | modeset_put_power_domains(dev_priv, put_domains); | |
13543 | ||
f6ac4b2a | 13544 | intel_post_plane_update(intel_crtc); |
9f836f90 PJ |
13545 | |
13546 | if (modeset) | |
13547 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
80715b2f | 13548 | } |
a6778b3c | 13549 | |
a6778b3c | 13550 | /* FIXME: add subpixel order */ |
83a57153 | 13551 | |
74c090b1 | 13552 | drm_atomic_helper_wait_for_vblanks(dev, state); |
f935675f ML |
13553 | |
13554 | mutex_lock(&dev->struct_mutex); | |
d4afb8cc | 13555 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13556 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13557 | |
74c090b1 | 13558 | if (any_ms) |
ee165b1a ML |
13559 | intel_modeset_check_state(dev, state); |
13560 | ||
13561 | drm_atomic_state_free(state); | |
f30da187 | 13562 | |
74c090b1 | 13563 | return 0; |
7f27126e JB |
13564 | } |
13565 | ||
c0c36b94 CW |
13566 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13567 | { | |
83a57153 ACO |
13568 | struct drm_device *dev = crtc->dev; |
13569 | struct drm_atomic_state *state; | |
e694eb02 | 13570 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13571 | int ret; |
83a57153 ACO |
13572 | |
13573 | state = drm_atomic_state_alloc(dev); | |
13574 | if (!state) { | |
e694eb02 | 13575 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13576 | crtc->base.id); |
13577 | return; | |
13578 | } | |
13579 | ||
e694eb02 | 13580 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13581 | |
e694eb02 ML |
13582 | retry: |
13583 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13584 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13585 | if (!ret) { | |
13586 | if (!crtc_state->active) | |
13587 | goto out; | |
83a57153 | 13588 | |
e694eb02 | 13589 | crtc_state->mode_changed = true; |
74c090b1 | 13590 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13591 | } |
13592 | ||
e694eb02 ML |
13593 | if (ret == -EDEADLK) { |
13594 | drm_atomic_state_clear(state); | |
13595 | drm_modeset_backoff(state->acquire_ctx); | |
13596 | goto retry; | |
4ed9fb37 | 13597 | } |
4be07317 | 13598 | |
2bfb4627 | 13599 | if (ret) |
e694eb02 | 13600 | out: |
2bfb4627 | 13601 | drm_atomic_state_free(state); |
c0c36b94 CW |
13602 | } |
13603 | ||
25c5b266 DV |
13604 | #undef for_each_intel_crtc_masked |
13605 | ||
f6e5b160 | 13606 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13607 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13608 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13609 | .destroy = intel_crtc_destroy, |
13610 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13611 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13612 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13613 | }; |
13614 | ||
5358901f DV |
13615 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13616 | struct intel_shared_dpll *pll, | |
13617 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13618 | { |
5358901f | 13619 | uint32_t val; |
ee7b9f93 | 13620 | |
f458ebbc | 13621 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13622 | return false; |
13623 | ||
5358901f | 13624 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13625 | hw_state->dpll = val; |
13626 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13627 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13628 | |
13629 | return val & DPLL_VCO_ENABLE; | |
13630 | } | |
13631 | ||
15bdd4cf DV |
13632 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13633 | struct intel_shared_dpll *pll) | |
13634 | { | |
3e369b76 ACO |
13635 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13636 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13637 | } |
13638 | ||
e7b903d2 DV |
13639 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13640 | struct intel_shared_dpll *pll) | |
13641 | { | |
e7b903d2 | 13642 | /* PCH refclock must be enabled first */ |
89eff4be | 13643 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13644 | |
3e369b76 | 13645 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13646 | |
13647 | /* Wait for the clocks to stabilize. */ | |
13648 | POSTING_READ(PCH_DPLL(pll->id)); | |
13649 | udelay(150); | |
13650 | ||
13651 | /* The pixel multiplier can only be updated once the | |
13652 | * DPLL is enabled and the clocks are stable. | |
13653 | * | |
13654 | * So write it again. | |
13655 | */ | |
3e369b76 | 13656 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13657 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13658 | udelay(200); |
13659 | } | |
13660 | ||
13661 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13662 | struct intel_shared_dpll *pll) | |
13663 | { | |
13664 | struct drm_device *dev = dev_priv->dev; | |
13665 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13666 | |
13667 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13668 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13669 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13670 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13671 | } |
13672 | ||
15bdd4cf DV |
13673 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13674 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13675 | udelay(200); |
13676 | } | |
13677 | ||
46edb027 DV |
13678 | static char *ibx_pch_dpll_names[] = { |
13679 | "PCH DPLL A", | |
13680 | "PCH DPLL B", | |
13681 | }; | |
13682 | ||
7c74ade1 | 13683 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13684 | { |
e7b903d2 | 13685 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13686 | int i; |
13687 | ||
7c74ade1 | 13688 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13689 | |
e72f9fbf | 13690 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13691 | dev_priv->shared_dplls[i].id = i; |
13692 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13693 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13694 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13695 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13696 | dev_priv->shared_dplls[i].get_hw_state = |
13697 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13698 | } |
13699 | } | |
13700 | ||
7c74ade1 DV |
13701 | static void intel_shared_dpll_init(struct drm_device *dev) |
13702 | { | |
e7b903d2 | 13703 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13704 | |
9cd86933 DV |
13705 | if (HAS_DDI(dev)) |
13706 | intel_ddi_pll_init(dev); | |
13707 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13708 | ibx_pch_dpll_init(dev); |
13709 | else | |
13710 | dev_priv->num_shared_dpll = 0; | |
13711 | ||
13712 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13713 | } |
13714 | ||
6beb8c23 MR |
13715 | /** |
13716 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13717 | * @plane: drm plane to prepare for | |
13718 | * @fb: framebuffer to prepare for presentation | |
13719 | * | |
13720 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13721 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13722 | * bits. Some older platforms need special physical address handling for | |
13723 | * cursor planes. | |
13724 | * | |
f935675f ML |
13725 | * Must be called with struct_mutex held. |
13726 | * | |
6beb8c23 MR |
13727 | * Returns 0 on success, negative error code on failure. |
13728 | */ | |
13729 | int | |
13730 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13731 | const struct drm_plane_state *new_state) |
465c120c MR |
13732 | { |
13733 | struct drm_device *dev = plane->dev; | |
844f9111 | 13734 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13735 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13736 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13737 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13738 | int ret = 0; |
465c120c | 13739 | |
1ee49399 | 13740 | if (!obj && !old_obj) |
465c120c MR |
13741 | return 0; |
13742 | ||
5008e874 ML |
13743 | if (old_obj) { |
13744 | struct drm_crtc_state *crtc_state = | |
13745 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13746 | ||
13747 | /* Big Hammer, we also need to ensure that any pending | |
13748 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13749 | * current scanout is retired before unpinning the old | |
13750 | * framebuffer. Note that we rely on userspace rendering | |
13751 | * into the buffer attached to the pipe they are waiting | |
13752 | * on. If not, userspace generates a GPU hang with IPEHR | |
13753 | * point to the MI_WAIT_FOR_EVENT. | |
13754 | * | |
13755 | * This should only fail upon a hung GPU, in which case we | |
13756 | * can safely continue. | |
13757 | */ | |
13758 | if (needs_modeset(crtc_state)) | |
13759 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13760 | ||
13761 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13762 | if (ret && ret != -EIO) | |
f935675f | 13763 | return ret; |
5008e874 ML |
13764 | } |
13765 | ||
3c28ff22 AG |
13766 | /* For framebuffer backed by dmabuf, wait for fence */ |
13767 | if (obj && obj->base.dma_buf) { | |
13768 | ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13769 | false, true, | |
13770 | MAX_SCHEDULE_TIMEOUT); | |
13771 | if (ret == -ERESTARTSYS) | |
13772 | return ret; | |
13773 | ||
13774 | WARN_ON(ret < 0); | |
13775 | } | |
13776 | ||
1ee49399 ML |
13777 | if (!obj) { |
13778 | ret = 0; | |
13779 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13780 | INTEL_INFO(dev)->cursor_needs_physical) { |
13781 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13782 | ret = i915_gem_object_attach_phys(obj, align); | |
13783 | if (ret) | |
13784 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13785 | } else { | |
7580d774 | 13786 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
6beb8c23 | 13787 | } |
465c120c | 13788 | |
7580d774 ML |
13789 | if (ret == 0) { |
13790 | if (obj) { | |
13791 | struct intel_plane_state *plane_state = | |
13792 | to_intel_plane_state(new_state); | |
13793 | ||
13794 | i915_gem_request_assign(&plane_state->wait_req, | |
13795 | obj->last_write_req); | |
13796 | } | |
13797 | ||
a9ff8714 | 13798 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13799 | } |
fdd508a6 | 13800 | |
6beb8c23 MR |
13801 | return ret; |
13802 | } | |
13803 | ||
38f3ce3a MR |
13804 | /** |
13805 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13806 | * @plane: drm plane to clean up for | |
13807 | * @fb: old framebuffer that was on plane | |
13808 | * | |
13809 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13810 | * |
13811 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13812 | */ |
13813 | void | |
13814 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13815 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13816 | { |
13817 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13818 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13819 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13820 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13821 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13822 | |
7580d774 ML |
13823 | old_intel_state = to_intel_plane_state(old_state); |
13824 | ||
1ee49399 | 13825 | if (!obj && !old_obj) |
38f3ce3a MR |
13826 | return; |
13827 | ||
1ee49399 ML |
13828 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13829 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
844f9111 | 13830 | intel_unpin_fb_obj(old_state->fb, old_state); |
1ee49399 ML |
13831 | |
13832 | /* prepare_fb aborted? */ | |
13833 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13834 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13835 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13836 | |
13837 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13838 | ||
465c120c MR |
13839 | } |
13840 | ||
6156a456 CK |
13841 | int |
13842 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13843 | { | |
13844 | int max_scale; | |
13845 | struct drm_device *dev; | |
13846 | struct drm_i915_private *dev_priv; | |
13847 | int crtc_clock, cdclk; | |
13848 | ||
13849 | if (!intel_crtc || !crtc_state) | |
13850 | return DRM_PLANE_HELPER_NO_SCALING; | |
13851 | ||
13852 | dev = intel_crtc->base.dev; | |
13853 | dev_priv = dev->dev_private; | |
13854 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13855 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13856 | |
54bf1ce6 | 13857 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13858 | return DRM_PLANE_HELPER_NO_SCALING; |
13859 | ||
13860 | /* | |
13861 | * skl max scale is lower of: | |
13862 | * close to 3 but not 3, -1 is for that purpose | |
13863 | * or | |
13864 | * cdclk/crtc_clock | |
13865 | */ | |
13866 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13867 | ||
13868 | return max_scale; | |
13869 | } | |
13870 | ||
465c120c | 13871 | static int |
3c692a41 | 13872 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13873 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13874 | struct intel_plane_state *state) |
13875 | { | |
2b875c22 MR |
13876 | struct drm_crtc *crtc = state->base.crtc; |
13877 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13878 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13879 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13880 | bool can_position = false; | |
465c120c | 13881 | |
061e4b8d ML |
13882 | /* use scaler when colorkey is not required */ |
13883 | if (INTEL_INFO(plane->dev)->gen >= 9 && | |
818ed961 | 13884 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
061e4b8d ML |
13885 | min_scale = 1; |
13886 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
d8106366 | 13887 | can_position = true; |
6156a456 | 13888 | } |
d8106366 | 13889 | |
061e4b8d ML |
13890 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13891 | &state->dst, &state->clip, | |
da20eabd ML |
13892 | min_scale, max_scale, |
13893 | can_position, true, | |
13894 | &state->visible); | |
14af293f GP |
13895 | } |
13896 | ||
13897 | static void | |
13898 | intel_commit_primary_plane(struct drm_plane *plane, | |
13899 | struct intel_plane_state *state) | |
13900 | { | |
2b875c22 MR |
13901 | struct drm_crtc *crtc = state->base.crtc; |
13902 | struct drm_framebuffer *fb = state->base.fb; | |
13903 | struct drm_device *dev = plane->dev; | |
14af293f | 13904 | struct drm_i915_private *dev_priv = dev->dev_private; |
14af293f | 13905 | |
ea2c67bb | 13906 | crtc = crtc ? crtc : plane->crtc; |
ccc759dc | 13907 | |
d4b08630 ML |
13908 | dev_priv->display.update_primary_plane(crtc, fb, |
13909 | state->src.x1 >> 16, | |
13910 | state->src.y1 >> 16); | |
465c120c MR |
13911 | } |
13912 | ||
a8ad0d8e ML |
13913 | static void |
13914 | intel_disable_primary_plane(struct drm_plane *plane, | |
7fabf5ef | 13915 | struct drm_crtc *crtc) |
a8ad0d8e ML |
13916 | { |
13917 | struct drm_device *dev = plane->dev; | |
13918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13919 | ||
a8ad0d8e ML |
13920 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13921 | } | |
13922 | ||
613d2b27 ML |
13923 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13924 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13925 | { |
32b7eeec | 13926 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13927 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13928 | struct intel_crtc_state *old_intel_state = |
13929 | to_intel_crtc_state(old_crtc_state); | |
13930 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13931 | |
c34c9ee4 | 13932 | /* Perform vblank evasion around commit operation */ |
62852622 | 13933 | intel_pipe_update_start(intel_crtc); |
0583236e | 13934 | |
bfd16b2a ML |
13935 | if (modeset) |
13936 | return; | |
13937 | ||
13938 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13939 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13940 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13941 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13942 | } |
13943 | ||
613d2b27 ML |
13944 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13945 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13946 | { |
32b7eeec | 13947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13948 | |
62852622 | 13949 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13950 | } |
13951 | ||
cf4c7c12 | 13952 | /** |
4a3b8769 MR |
13953 | * intel_plane_destroy - destroy a plane |
13954 | * @plane: plane to destroy | |
cf4c7c12 | 13955 | * |
4a3b8769 MR |
13956 | * Common destruction function for all types of planes (primary, cursor, |
13957 | * sprite). | |
cf4c7c12 | 13958 | */ |
4a3b8769 | 13959 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13960 | { |
13961 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13962 | drm_plane_cleanup(plane); | |
13963 | kfree(intel_plane); | |
13964 | } | |
13965 | ||
65a3fea0 | 13966 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13967 | .update_plane = drm_atomic_helper_update_plane, |
13968 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13969 | .destroy = intel_plane_destroy, |
c196e1d6 | 13970 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13971 | .atomic_get_property = intel_plane_atomic_get_property, |
13972 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13973 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13974 | .atomic_destroy_state = intel_plane_destroy_state, | |
13975 | ||
465c120c MR |
13976 | }; |
13977 | ||
13978 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13979 | int pipe) | |
13980 | { | |
13981 | struct intel_plane *primary; | |
8e7d688b | 13982 | struct intel_plane_state *state; |
465c120c | 13983 | const uint32_t *intel_primary_formats; |
45e3743a | 13984 | unsigned int num_formats; |
465c120c MR |
13985 | |
13986 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13987 | if (primary == NULL) | |
13988 | return NULL; | |
13989 | ||
8e7d688b MR |
13990 | state = intel_create_plane_state(&primary->base); |
13991 | if (!state) { | |
ea2c67bb MR |
13992 | kfree(primary); |
13993 | return NULL; | |
13994 | } | |
8e7d688b | 13995 | primary->base.state = &state->base; |
ea2c67bb | 13996 | |
465c120c MR |
13997 | primary->can_scale = false; |
13998 | primary->max_downscale = 1; | |
6156a456 CK |
13999 | if (INTEL_INFO(dev)->gen >= 9) { |
14000 | primary->can_scale = true; | |
af99ceda | 14001 | state->scaler_id = -1; |
6156a456 | 14002 | } |
465c120c MR |
14003 | primary->pipe = pipe; |
14004 | primary->plane = pipe; | |
a9ff8714 | 14005 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 MR |
14006 | primary->check_plane = intel_check_primary_plane; |
14007 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 14008 | primary->disable_plane = intel_disable_primary_plane; |
465c120c MR |
14009 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14010 | primary->plane = !pipe; | |
14011 | ||
6c0fd451 DL |
14012 | if (INTEL_INFO(dev)->gen >= 9) { |
14013 | intel_primary_formats = skl_primary_formats; | |
14014 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
14015 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
14016 | intel_primary_formats = i965_primary_formats; |
14017 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
14018 | } else { |
14019 | intel_primary_formats = i8xx_primary_formats; | |
14020 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
14021 | } |
14022 | ||
14023 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14024 | &intel_plane_funcs, |
465c120c MR |
14025 | intel_primary_formats, num_formats, |
14026 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 14027 | |
3b7a5119 SJ |
14028 | if (INTEL_INFO(dev)->gen >= 4) |
14029 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14030 | |
ea2c67bb MR |
14031 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14032 | ||
465c120c MR |
14033 | return &primary->base; |
14034 | } | |
14035 | ||
3b7a5119 SJ |
14036 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14037 | { | |
14038 | if (!dev->mode_config.rotation_property) { | |
14039 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14040 | BIT(DRM_ROTATE_180); | |
14041 | ||
14042 | if (INTEL_INFO(dev)->gen >= 9) | |
14043 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14044 | ||
14045 | dev->mode_config.rotation_property = | |
14046 | drm_mode_create_rotation_property(dev, flags); | |
14047 | } | |
14048 | if (dev->mode_config.rotation_property) | |
14049 | drm_object_attach_property(&plane->base.base, | |
14050 | dev->mode_config.rotation_property, | |
14051 | plane->base.state->rotation); | |
14052 | } | |
14053 | ||
3d7d6510 | 14054 | static int |
852e787c | 14055 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14056 | struct intel_crtc_state *crtc_state, |
852e787c | 14057 | struct intel_plane_state *state) |
3d7d6510 | 14058 | { |
061e4b8d | 14059 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14060 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14061 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14062 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14063 | unsigned stride; |
14064 | int ret; | |
3d7d6510 | 14065 | |
061e4b8d ML |
14066 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14067 | &state->dst, &state->clip, | |
3d7d6510 MR |
14068 | DRM_PLANE_HELPER_NO_SCALING, |
14069 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14070 | true, true, &state->visible); |
757f9a3e GP |
14071 | if (ret) |
14072 | return ret; | |
14073 | ||
757f9a3e GP |
14074 | /* if we want to turn off the cursor ignore width and height */ |
14075 | if (!obj) | |
da20eabd | 14076 | return 0; |
757f9a3e | 14077 | |
757f9a3e | 14078 | /* Check for which cursor types we support */ |
061e4b8d | 14079 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14080 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14081 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14082 | return -EINVAL; |
14083 | } | |
14084 | ||
ea2c67bb MR |
14085 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14086 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14087 | DRM_DEBUG_KMS("buffer is too small\n"); |
14088 | return -ENOMEM; | |
14089 | } | |
14090 | ||
3a656b54 | 14091 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14092 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14093 | return -EINVAL; |
32b7eeec MR |
14094 | } |
14095 | ||
b29ec92c VS |
14096 | /* |
14097 | * There's something wrong with the cursor on CHV pipe C. | |
14098 | * If it straddles the left edge of the screen then | |
14099 | * moving it away from the edge or disabling it often | |
14100 | * results in a pipe underrun, and often that can lead to | |
14101 | * dead pipe (constant underrun reported, and it scans | |
14102 | * out just a solid color). To recover from that, the | |
14103 | * display power well must be turned off and on again. | |
14104 | * Refuse the put the cursor into that compromised position. | |
14105 | */ | |
14106 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14107 | state->visible && state->base.crtc_x < 0) { | |
14108 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14109 | return -EINVAL; | |
14110 | } | |
14111 | ||
da20eabd | 14112 | return 0; |
852e787c | 14113 | } |
3d7d6510 | 14114 | |
a8ad0d8e ML |
14115 | static void |
14116 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14117 | struct drm_crtc *crtc) |
a8ad0d8e | 14118 | { |
a8ad0d8e ML |
14119 | intel_crtc_update_cursor(crtc, false); |
14120 | } | |
14121 | ||
f4a2cf29 | 14122 | static void |
852e787c GP |
14123 | intel_commit_cursor_plane(struct drm_plane *plane, |
14124 | struct intel_plane_state *state) | |
14125 | { | |
2b875c22 | 14126 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
14127 | struct drm_device *dev = plane->dev; |
14128 | struct intel_crtc *intel_crtc; | |
2b875c22 | 14129 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14130 | uint32_t addr; |
852e787c | 14131 | |
ea2c67bb MR |
14132 | crtc = crtc ? crtc : plane->crtc; |
14133 | intel_crtc = to_intel_crtc(crtc); | |
14134 | ||
f4a2cf29 | 14135 | if (!obj) |
a912f12f | 14136 | addr = 0; |
f4a2cf29 | 14137 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14138 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14139 | else |
a912f12f | 14140 | addr = obj->phys_handle->busaddr; |
852e787c | 14141 | |
a912f12f | 14142 | intel_crtc->cursor_addr = addr; |
852e787c | 14143 | |
62852622 | 14144 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
14145 | } |
14146 | ||
3d7d6510 MR |
14147 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14148 | int pipe) | |
14149 | { | |
14150 | struct intel_plane *cursor; | |
8e7d688b | 14151 | struct intel_plane_state *state; |
3d7d6510 MR |
14152 | |
14153 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14154 | if (cursor == NULL) | |
14155 | return NULL; | |
14156 | ||
8e7d688b MR |
14157 | state = intel_create_plane_state(&cursor->base); |
14158 | if (!state) { | |
ea2c67bb MR |
14159 | kfree(cursor); |
14160 | return NULL; | |
14161 | } | |
8e7d688b | 14162 | cursor->base.state = &state->base; |
ea2c67bb | 14163 | |
3d7d6510 MR |
14164 | cursor->can_scale = false; |
14165 | cursor->max_downscale = 1; | |
14166 | cursor->pipe = pipe; | |
14167 | cursor->plane = pipe; | |
a9ff8714 | 14168 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 MR |
14169 | cursor->check_plane = intel_check_cursor_plane; |
14170 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 14171 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14172 | |
14173 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14174 | &intel_plane_funcs, |
3d7d6510 MR |
14175 | intel_cursor_formats, |
14176 | ARRAY_SIZE(intel_cursor_formats), | |
14177 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
14178 | |
14179 | if (INTEL_INFO(dev)->gen >= 4) { | |
14180 | if (!dev->mode_config.rotation_property) | |
14181 | dev->mode_config.rotation_property = | |
14182 | drm_mode_create_rotation_property(dev, | |
14183 | BIT(DRM_ROTATE_0) | | |
14184 | BIT(DRM_ROTATE_180)); | |
14185 | if (dev->mode_config.rotation_property) | |
14186 | drm_object_attach_property(&cursor->base.base, | |
14187 | dev->mode_config.rotation_property, | |
8e7d688b | 14188 | state->base.rotation); |
4398ad45 VS |
14189 | } |
14190 | ||
af99ceda CK |
14191 | if (INTEL_INFO(dev)->gen >=9) |
14192 | state->scaler_id = -1; | |
14193 | ||
ea2c67bb MR |
14194 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14195 | ||
3d7d6510 MR |
14196 | return &cursor->base; |
14197 | } | |
14198 | ||
549e2bfb CK |
14199 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14200 | struct intel_crtc_state *crtc_state) | |
14201 | { | |
14202 | int i; | |
14203 | struct intel_scaler *intel_scaler; | |
14204 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14205 | ||
14206 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14207 | intel_scaler = &scaler_state->scalers[i]; | |
14208 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14209 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14210 | } | |
14211 | ||
14212 | scaler_state->scaler_id = -1; | |
14213 | } | |
14214 | ||
b358d0a6 | 14215 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14216 | { |
fbee40df | 14217 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14218 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14219 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14220 | struct drm_plane *primary = NULL; |
14221 | struct drm_plane *cursor = NULL; | |
465c120c | 14222 | int i, ret; |
79e53945 | 14223 | |
955382f3 | 14224 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14225 | if (intel_crtc == NULL) |
14226 | return; | |
14227 | ||
f5de6e07 ACO |
14228 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14229 | if (!crtc_state) | |
14230 | goto fail; | |
550acefd ACO |
14231 | intel_crtc->config = crtc_state; |
14232 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14233 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14234 | |
549e2bfb CK |
14235 | /* initialize shared scalers */ |
14236 | if (INTEL_INFO(dev)->gen >= 9) { | |
14237 | if (pipe == PIPE_C) | |
14238 | intel_crtc->num_scalers = 1; | |
14239 | else | |
14240 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14241 | ||
14242 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14243 | } | |
14244 | ||
465c120c | 14245 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14246 | if (!primary) |
14247 | goto fail; | |
14248 | ||
14249 | cursor = intel_cursor_plane_create(dev, pipe); | |
14250 | if (!cursor) | |
14251 | goto fail; | |
14252 | ||
465c120c | 14253 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
14254 | cursor, &intel_crtc_funcs); |
14255 | if (ret) | |
14256 | goto fail; | |
79e53945 JB |
14257 | |
14258 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14259 | for (i = 0; i < 256; i++) { |
14260 | intel_crtc->lut_r[i] = i; | |
14261 | intel_crtc->lut_g[i] = i; | |
14262 | intel_crtc->lut_b[i] = i; | |
14263 | } | |
14264 | ||
1f1c2e24 VS |
14265 | /* |
14266 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14267 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14268 | */ |
80824003 JB |
14269 | intel_crtc->pipe = pipe; |
14270 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14271 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14272 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14273 | intel_crtc->plane = !pipe; |
80824003 JB |
14274 | } |
14275 | ||
4b0e333e CW |
14276 | intel_crtc->cursor_base = ~0; |
14277 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14278 | intel_crtc->cursor_size = ~0; |
8d7849db | 14279 | |
852eb00d VS |
14280 | intel_crtc->wm.cxsr_allowed = true; |
14281 | ||
22fd0fab JB |
14282 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14283 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14284 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14285 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14286 | ||
79e53945 | 14287 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14288 | |
14289 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14290 | return; |
14291 | ||
14292 | fail: | |
14293 | if (primary) | |
14294 | drm_plane_cleanup(primary); | |
14295 | if (cursor) | |
14296 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14297 | kfree(crtc_state); |
3d7d6510 | 14298 | kfree(intel_crtc); |
79e53945 JB |
14299 | } |
14300 | ||
752aa88a JB |
14301 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14302 | { | |
14303 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14304 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14305 | |
51fd371b | 14306 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14307 | |
d3babd3f | 14308 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14309 | return INVALID_PIPE; |
14310 | ||
14311 | return to_intel_crtc(encoder->crtc)->pipe; | |
14312 | } | |
14313 | ||
08d7b3d1 | 14314 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14315 | struct drm_file *file) |
08d7b3d1 | 14316 | { |
08d7b3d1 | 14317 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14318 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14319 | struct intel_crtc *crtc; |
08d7b3d1 | 14320 | |
7707e653 | 14321 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14322 | |
7707e653 | 14323 | if (!drmmode_crtc) { |
08d7b3d1 | 14324 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14325 | return -ENOENT; |
08d7b3d1 CW |
14326 | } |
14327 | ||
7707e653 | 14328 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14329 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14330 | |
c05422d5 | 14331 | return 0; |
08d7b3d1 CW |
14332 | } |
14333 | ||
66a9278e | 14334 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14335 | { |
66a9278e DV |
14336 | struct drm_device *dev = encoder->base.dev; |
14337 | struct intel_encoder *source_encoder; | |
79e53945 | 14338 | int index_mask = 0; |
79e53945 JB |
14339 | int entry = 0; |
14340 | ||
b2784e15 | 14341 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14342 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14343 | index_mask |= (1 << entry); |
14344 | ||
79e53945 JB |
14345 | entry++; |
14346 | } | |
4ef69c7a | 14347 | |
79e53945 JB |
14348 | return index_mask; |
14349 | } | |
14350 | ||
4d302442 CW |
14351 | static bool has_edp_a(struct drm_device *dev) |
14352 | { | |
14353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14354 | ||
14355 | if (!IS_MOBILE(dev)) | |
14356 | return false; | |
14357 | ||
14358 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14359 | return false; | |
14360 | ||
e3589908 | 14361 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14362 | return false; |
14363 | ||
14364 | return true; | |
14365 | } | |
14366 | ||
84b4e042 JB |
14367 | static bool intel_crt_present(struct drm_device *dev) |
14368 | { | |
14369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14370 | ||
884497ed DL |
14371 | if (INTEL_INFO(dev)->gen >= 9) |
14372 | return false; | |
14373 | ||
cf404ce4 | 14374 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14375 | return false; |
14376 | ||
14377 | if (IS_CHERRYVIEW(dev)) | |
14378 | return false; | |
14379 | ||
65e472e4 VS |
14380 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14381 | return false; | |
14382 | ||
70ac54d0 VS |
14383 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14384 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14385 | return false; | |
14386 | ||
e4abb733 | 14387 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14388 | return false; |
14389 | ||
14390 | return true; | |
14391 | } | |
14392 | ||
79e53945 JB |
14393 | static void intel_setup_outputs(struct drm_device *dev) |
14394 | { | |
725e30ad | 14395 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14396 | struct intel_encoder *encoder; |
cb0953d7 | 14397 | bool dpd_is_edp = false; |
79e53945 | 14398 | |
c9093354 | 14399 | intel_lvds_init(dev); |
79e53945 | 14400 | |
84b4e042 | 14401 | if (intel_crt_present(dev)) |
79935fca | 14402 | intel_crt_init(dev); |
cb0953d7 | 14403 | |
c776eb2e VK |
14404 | if (IS_BROXTON(dev)) { |
14405 | /* | |
14406 | * FIXME: Broxton doesn't support port detection via the | |
14407 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14408 | * detect the ports. | |
14409 | */ | |
14410 | intel_ddi_init(dev, PORT_A); | |
14411 | intel_ddi_init(dev, PORT_B); | |
14412 | intel_ddi_init(dev, PORT_C); | |
14413 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14414 | int found; |
14415 | ||
de31facd JB |
14416 | /* |
14417 | * Haswell uses DDI functions to detect digital outputs. | |
14418 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14419 | * it's there. | |
14420 | */ | |
77179400 | 14421 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14422 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14423 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14424 | intel_ddi_init(dev, PORT_A); |
14425 | ||
14426 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14427 | * register */ | |
14428 | found = I915_READ(SFUSE_STRAP); | |
14429 | ||
14430 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14431 | intel_ddi_init(dev, PORT_B); | |
14432 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14433 | intel_ddi_init(dev, PORT_C); | |
14434 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14435 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14436 | /* |
14437 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14438 | */ | |
ef11bdb3 | 14439 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14440 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14441 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14442 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14443 | intel_ddi_init(dev, PORT_E); | |
14444 | ||
0e72a5b5 | 14445 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14446 | int found; |
5d8a7752 | 14447 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14448 | |
14449 | if (has_edp_a(dev)) | |
14450 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14451 | |
dc0fa718 | 14452 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14453 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14454 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14455 | if (!found) |
e2debe91 | 14456 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14457 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14458 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14459 | } |
14460 | ||
dc0fa718 | 14461 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14462 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14463 | |
dc0fa718 | 14464 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14465 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14466 | |
5eb08b69 | 14467 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14468 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14469 | |
270b3042 | 14470 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14471 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14472 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14473 | /* |
14474 | * The DP_DETECTED bit is the latched state of the DDC | |
14475 | * SDA pin at boot. However since eDP doesn't require DDC | |
14476 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14477 | * eDP ports may have been muxed to an alternate function. | |
14478 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14479 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14480 | * detect eDP ports. | |
14481 | */ | |
e66eb81d | 14482 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14483 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14484 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14485 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14486 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14487 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14488 | |
e66eb81d | 14489 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14490 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14491 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14492 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14493 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14494 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14495 | |
9418c1f1 | 14496 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14497 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14498 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14499 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14500 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14501 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14502 | } |
14503 | ||
3cfca973 | 14504 | intel_dsi_init(dev); |
09da55dc | 14505 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14506 | bool found = false; |
7d57382e | 14507 | |
e2debe91 | 14508 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14509 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14510 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14511 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14512 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14513 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14514 | } |
27185ae1 | 14515 | |
3fec3d2f | 14516 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14517 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14518 | } |
13520b05 KH |
14519 | |
14520 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14521 | |
e2debe91 | 14522 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14523 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14524 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14525 | } |
27185ae1 | 14526 | |
e2debe91 | 14527 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14528 | |
3fec3d2f | 14529 | if (IS_G4X(dev)) { |
b01f2c3a | 14530 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14531 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14532 | } |
3fec3d2f | 14533 | if (IS_G4X(dev)) |
ab9d7c30 | 14534 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14535 | } |
27185ae1 | 14536 | |
3fec3d2f | 14537 | if (IS_G4X(dev) && |
e7281eab | 14538 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14539 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14540 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14541 | intel_dvo_init(dev); |
14542 | ||
103a196f | 14543 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14544 | intel_tv_init(dev); |
14545 | ||
0bc12bcb | 14546 | intel_psr_init(dev); |
7c8f8a70 | 14547 | |
b2784e15 | 14548 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14549 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14550 | encoder->base.possible_clones = | |
66a9278e | 14551 | intel_encoder_clones(encoder); |
79e53945 | 14552 | } |
47356eb6 | 14553 | |
dde86e2d | 14554 | intel_init_pch_refclk(dev); |
270b3042 DV |
14555 | |
14556 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14557 | } |
14558 | ||
14559 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14560 | { | |
60a5ca01 | 14561 | struct drm_device *dev = fb->dev; |
79e53945 | 14562 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14563 | |
ef2d633e | 14564 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14565 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14566 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14567 | drm_gem_object_unreference(&intel_fb->obj->base); |
14568 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14569 | kfree(intel_fb); |
14570 | } | |
14571 | ||
14572 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14573 | struct drm_file *file, |
79e53945 JB |
14574 | unsigned int *handle) |
14575 | { | |
14576 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14577 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14578 | |
cc917ab4 CW |
14579 | if (obj->userptr.mm) { |
14580 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14581 | return -EINVAL; | |
14582 | } | |
14583 | ||
05394f39 | 14584 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14585 | } |
14586 | ||
86c98588 RV |
14587 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14588 | struct drm_file *file, | |
14589 | unsigned flags, unsigned color, | |
14590 | struct drm_clip_rect *clips, | |
14591 | unsigned num_clips) | |
14592 | { | |
14593 | struct drm_device *dev = fb->dev; | |
14594 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14595 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14596 | ||
14597 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14598 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14599 | mutex_unlock(&dev->struct_mutex); |
14600 | ||
14601 | return 0; | |
14602 | } | |
14603 | ||
79e53945 JB |
14604 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14605 | .destroy = intel_user_framebuffer_destroy, | |
14606 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14607 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14608 | }; |
14609 | ||
b321803d DL |
14610 | static |
14611 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14612 | uint32_t pixel_format) | |
14613 | { | |
14614 | u32 gen = INTEL_INFO(dev)->gen; | |
14615 | ||
14616 | if (gen >= 9) { | |
14617 | /* "The stride in bytes must not exceed the of the size of 8K | |
14618 | * pixels and 32K bytes." | |
14619 | */ | |
14620 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
666a4537 | 14621 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14622 | return 32*1024; |
14623 | } else if (gen >= 4) { | |
14624 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14625 | return 16*1024; | |
14626 | else | |
14627 | return 32*1024; | |
14628 | } else if (gen >= 3) { | |
14629 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14630 | return 8*1024; | |
14631 | else | |
14632 | return 16*1024; | |
14633 | } else { | |
14634 | /* XXX DSPC is limited to 4k tiled */ | |
14635 | return 8*1024; | |
14636 | } | |
14637 | } | |
14638 | ||
b5ea642a DV |
14639 | static int intel_framebuffer_init(struct drm_device *dev, |
14640 | struct intel_framebuffer *intel_fb, | |
14641 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14642 | struct drm_i915_gem_object *obj) | |
79e53945 | 14643 | { |
6761dd31 | 14644 | unsigned int aligned_height; |
79e53945 | 14645 | int ret; |
b321803d | 14646 | u32 pitch_limit, stride_alignment; |
79e53945 | 14647 | |
dd4916c5 DV |
14648 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14649 | ||
2a80eada DV |
14650 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14651 | /* Enforce that fb modifier and tiling mode match, but only for | |
14652 | * X-tiled. This is needed for FBC. */ | |
14653 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14654 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14655 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14656 | return -EINVAL; | |
14657 | } | |
14658 | } else { | |
14659 | if (obj->tiling_mode == I915_TILING_X) | |
14660 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14661 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14662 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14663 | return -EINVAL; | |
14664 | } | |
14665 | } | |
14666 | ||
9a8f0a12 TU |
14667 | /* Passed in modifier sanity checking. */ |
14668 | switch (mode_cmd->modifier[0]) { | |
14669 | case I915_FORMAT_MOD_Y_TILED: | |
14670 | case I915_FORMAT_MOD_Yf_TILED: | |
14671 | if (INTEL_INFO(dev)->gen < 9) { | |
14672 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14673 | mode_cmd->modifier[0]); | |
14674 | return -EINVAL; | |
14675 | } | |
14676 | case DRM_FORMAT_MOD_NONE: | |
14677 | case I915_FORMAT_MOD_X_TILED: | |
14678 | break; | |
14679 | default: | |
c0f40428 JB |
14680 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14681 | mode_cmd->modifier[0]); | |
57cd6508 | 14682 | return -EINVAL; |
c16ed4be | 14683 | } |
57cd6508 | 14684 | |
b321803d DL |
14685 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14686 | mode_cmd->pixel_format); | |
14687 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14688 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14689 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14690 | return -EINVAL; |
c16ed4be | 14691 | } |
57cd6508 | 14692 | |
b321803d DL |
14693 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14694 | mode_cmd->pixel_format); | |
a35cdaa0 | 14695 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14696 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14697 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14698 | "tiled" : "linear", |
a35cdaa0 | 14699 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14700 | return -EINVAL; |
c16ed4be | 14701 | } |
5d7bd705 | 14702 | |
2a80eada | 14703 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14704 | mode_cmd->pitches[0] != obj->stride) { |
14705 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14706 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14707 | return -EINVAL; |
c16ed4be | 14708 | } |
5d7bd705 | 14709 | |
57779d06 | 14710 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14711 | switch (mode_cmd->pixel_format) { |
57779d06 | 14712 | case DRM_FORMAT_C8: |
04b3924d VS |
14713 | case DRM_FORMAT_RGB565: |
14714 | case DRM_FORMAT_XRGB8888: | |
14715 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14716 | break; |
14717 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14718 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14719 | DRM_DEBUG("unsupported pixel format: %s\n", |
14720 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14721 | return -EINVAL; |
c16ed4be | 14722 | } |
57779d06 | 14723 | break; |
57779d06 | 14724 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14725 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14726 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14727 | DRM_DEBUG("unsupported pixel format: %s\n", |
14728 | drm_get_format_name(mode_cmd->pixel_format)); | |
14729 | return -EINVAL; | |
14730 | } | |
14731 | break; | |
14732 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14733 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14734 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14735 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14736 | DRM_DEBUG("unsupported pixel format: %s\n", |
14737 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14738 | return -EINVAL; |
c16ed4be | 14739 | } |
b5626747 | 14740 | break; |
7531208b | 14741 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14742 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14743 | DRM_DEBUG("unsupported pixel format: %s\n", |
14744 | drm_get_format_name(mode_cmd->pixel_format)); | |
14745 | return -EINVAL; | |
14746 | } | |
14747 | break; | |
04b3924d VS |
14748 | case DRM_FORMAT_YUYV: |
14749 | case DRM_FORMAT_UYVY: | |
14750 | case DRM_FORMAT_YVYU: | |
14751 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14752 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14753 | DRM_DEBUG("unsupported pixel format: %s\n", |
14754 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14755 | return -EINVAL; |
c16ed4be | 14756 | } |
57cd6508 CW |
14757 | break; |
14758 | default: | |
4ee62c76 VS |
14759 | DRM_DEBUG("unsupported pixel format: %s\n", |
14760 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14761 | return -EINVAL; |
14762 | } | |
14763 | ||
90f9a336 VS |
14764 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14765 | if (mode_cmd->offsets[0] != 0) | |
14766 | return -EINVAL; | |
14767 | ||
ec2c981e | 14768 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14769 | mode_cmd->pixel_format, |
14770 | mode_cmd->modifier[0]); | |
53155c0a DV |
14771 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14772 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14773 | return -EINVAL; | |
14774 | ||
c7d73f6a DV |
14775 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14776 | intel_fb->obj = obj; | |
80075d49 | 14777 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14778 | |
79e53945 JB |
14779 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14780 | if (ret) { | |
14781 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14782 | return ret; | |
14783 | } | |
14784 | ||
79e53945 JB |
14785 | return 0; |
14786 | } | |
14787 | ||
79e53945 JB |
14788 | static struct drm_framebuffer * |
14789 | intel_user_framebuffer_create(struct drm_device *dev, | |
14790 | struct drm_file *filp, | |
1eb83451 | 14791 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14792 | { |
dcb1394e | 14793 | struct drm_framebuffer *fb; |
05394f39 | 14794 | struct drm_i915_gem_object *obj; |
76dc3769 | 14795 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14796 | |
308e5bcb | 14797 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14798 | mode_cmd.handles[0])); |
c8725226 | 14799 | if (&obj->base == NULL) |
cce13ff7 | 14800 | return ERR_PTR(-ENOENT); |
79e53945 | 14801 | |
92907cbb | 14802 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14803 | if (IS_ERR(fb)) |
14804 | drm_gem_object_unreference_unlocked(&obj->base); | |
14805 | ||
14806 | return fb; | |
79e53945 JB |
14807 | } |
14808 | ||
0695726e | 14809 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14810 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14811 | { |
14812 | } | |
14813 | #endif | |
14814 | ||
79e53945 | 14815 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14816 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14817 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14818 | .atomic_check = intel_atomic_check, |
14819 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14820 | .atomic_state_alloc = intel_atomic_state_alloc, |
14821 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14822 | }; |
14823 | ||
e70236a8 JB |
14824 | /* Set up chip specific display functions */ |
14825 | static void intel_init_display(struct drm_device *dev) | |
14826 | { | |
14827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14828 | ||
ee9300bb DV |
14829 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14830 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14831 | else if (IS_CHERRYVIEW(dev)) |
14832 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14833 | else if (IS_VALLEYVIEW(dev)) |
14834 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14835 | else if (IS_PINEVIEW(dev)) | |
14836 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14837 | else | |
14838 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14839 | ||
bc8d7dff DL |
14840 | if (INTEL_INFO(dev)->gen >= 9) { |
14841 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14842 | dev_priv->display.get_initial_plane_config = |
14843 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14844 | dev_priv->display.crtc_compute_clock = |
14845 | haswell_crtc_compute_clock; | |
14846 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14847 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14848 | dev_priv->display.update_primary_plane = |
14849 | skylake_update_primary_plane; | |
14850 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14851 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14852 | dev_priv->display.get_initial_plane_config = |
14853 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14854 | dev_priv->display.crtc_compute_clock = |
14855 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14856 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14857 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14858 | dev_priv->display.update_primary_plane = |
14859 | ironlake_update_primary_plane; | |
09b4ddf9 | 14860 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14861 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14862 | dev_priv->display.get_initial_plane_config = |
14863 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14864 | dev_priv->display.crtc_compute_clock = |
14865 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14866 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14867 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
262ca2b0 MR |
14868 | dev_priv->display.update_primary_plane = |
14869 | ironlake_update_primary_plane; | |
666a4537 | 14870 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 14871 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14872 | dev_priv->display.get_initial_plane_config = |
14873 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14874 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14875 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14876 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14877 | dev_priv->display.update_primary_plane = |
14878 | i9xx_update_primary_plane; | |
f564048e | 14879 | } else { |
0e8ffe1b | 14880 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14881 | dev_priv->display.get_initial_plane_config = |
14882 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14883 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14884 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14885 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14886 | dev_priv->display.update_primary_plane = |
14887 | i9xx_update_primary_plane; | |
f564048e | 14888 | } |
e70236a8 | 14889 | |
e70236a8 | 14890 | /* Returns the core display clock speed */ |
ef11bdb3 | 14891 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
14892 | dev_priv->display.get_display_clock_speed = |
14893 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14894 | else if (IS_BROXTON(dev)) |
14895 | dev_priv->display.get_display_clock_speed = | |
14896 | broxton_get_display_clock_speed; | |
1652d19e VS |
14897 | else if (IS_BROADWELL(dev)) |
14898 | dev_priv->display.get_display_clock_speed = | |
14899 | broadwell_get_display_clock_speed; | |
14900 | else if (IS_HASWELL(dev)) | |
14901 | dev_priv->display.get_display_clock_speed = | |
14902 | haswell_get_display_clock_speed; | |
666a4537 | 14903 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
14904 | dev_priv->display.get_display_clock_speed = |
14905 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14906 | else if (IS_GEN5(dev)) |
14907 | dev_priv->display.get_display_clock_speed = | |
14908 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14909 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14910 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14911 | dev_priv->display.get_display_clock_speed = |
14912 | i945_get_display_clock_speed; | |
34edce2f VS |
14913 | else if (IS_GM45(dev)) |
14914 | dev_priv->display.get_display_clock_speed = | |
14915 | gm45_get_display_clock_speed; | |
14916 | else if (IS_CRESTLINE(dev)) | |
14917 | dev_priv->display.get_display_clock_speed = | |
14918 | i965gm_get_display_clock_speed; | |
14919 | else if (IS_PINEVIEW(dev)) | |
14920 | dev_priv->display.get_display_clock_speed = | |
14921 | pnv_get_display_clock_speed; | |
14922 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14923 | dev_priv->display.get_display_clock_speed = | |
14924 | g33_get_display_clock_speed; | |
e70236a8 JB |
14925 | else if (IS_I915G(dev)) |
14926 | dev_priv->display.get_display_clock_speed = | |
14927 | i915_get_display_clock_speed; | |
257a7ffc | 14928 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14929 | dev_priv->display.get_display_clock_speed = |
14930 | i9xx_misc_get_display_clock_speed; | |
14931 | else if (IS_I915GM(dev)) | |
14932 | dev_priv->display.get_display_clock_speed = | |
14933 | i915gm_get_display_clock_speed; | |
14934 | else if (IS_I865G(dev)) | |
14935 | dev_priv->display.get_display_clock_speed = | |
14936 | i865_get_display_clock_speed; | |
f0f8a9ce | 14937 | else if (IS_I85X(dev)) |
e70236a8 | 14938 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14939 | i85x_get_display_clock_speed; |
623e01e5 VS |
14940 | else { /* 830 */ |
14941 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14942 | dev_priv->display.get_display_clock_speed = |
14943 | i830_get_display_clock_speed; | |
623e01e5 | 14944 | } |
e70236a8 | 14945 | |
7c10a2b5 | 14946 | if (IS_GEN5(dev)) { |
3bb11b53 | 14947 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14948 | } else if (IS_GEN6(dev)) { |
14949 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14950 | } else if (IS_IVYBRIDGE(dev)) { |
14951 | /* FIXME: detect B0+ stepping and use auto training */ | |
14952 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14953 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14954 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
14955 | if (IS_BROADWELL(dev)) { |
14956 | dev_priv->display.modeset_commit_cdclk = | |
14957 | broadwell_modeset_commit_cdclk; | |
14958 | dev_priv->display.modeset_calc_cdclk = | |
14959 | broadwell_modeset_calc_cdclk; | |
14960 | } | |
666a4537 | 14961 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
14962 | dev_priv->display.modeset_commit_cdclk = |
14963 | valleyview_modeset_commit_cdclk; | |
14964 | dev_priv->display.modeset_calc_cdclk = | |
14965 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 14966 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
14967 | dev_priv->display.modeset_commit_cdclk = |
14968 | broxton_modeset_commit_cdclk; | |
14969 | dev_priv->display.modeset_calc_cdclk = | |
14970 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14971 | } |
8c9f3aaf | 14972 | |
8c9f3aaf JB |
14973 | switch (INTEL_INFO(dev)->gen) { |
14974 | case 2: | |
14975 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14976 | break; | |
14977 | ||
14978 | case 3: | |
14979 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14980 | break; | |
14981 | ||
14982 | case 4: | |
14983 | case 5: | |
14984 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14985 | break; | |
14986 | ||
14987 | case 6: | |
14988 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14989 | break; | |
7c9017e5 | 14990 | case 7: |
4e0bbc31 | 14991 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14992 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14993 | break; | |
830c81db | 14994 | case 9: |
ba343e02 TU |
14995 | /* Drop through - unsupported since execlist only. */ |
14996 | default: | |
14997 | /* Default just returns -ENODEV to indicate unsupported */ | |
14998 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14999 | } |
7bd688cd | 15000 | |
e39b999a | 15001 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
15002 | } |
15003 | ||
b690e96c JB |
15004 | /* |
15005 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15006 | * resume, or other times. This quirk makes sure that's the case for | |
15007 | * affected systems. | |
15008 | */ | |
0206e353 | 15009 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15010 | { |
15011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15012 | ||
15013 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15014 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15015 | } |
15016 | ||
b6b5d049 VS |
15017 | static void quirk_pipeb_force(struct drm_device *dev) |
15018 | { | |
15019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15020 | ||
15021 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15022 | DRM_INFO("applying pipe b force quirk\n"); | |
15023 | } | |
15024 | ||
435793df KP |
15025 | /* |
15026 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15027 | */ | |
15028 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15029 | { | |
15030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15031 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15032 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15033 | } |
15034 | ||
4dca20ef | 15035 | /* |
5a15ab5b CE |
15036 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15037 | * brightness value | |
4dca20ef CE |
15038 | */ |
15039 | static void quirk_invert_brightness(struct drm_device *dev) | |
15040 | { | |
15041 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15042 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15043 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15044 | } |
15045 | ||
9c72cc6f SD |
15046 | /* Some VBT's incorrectly indicate no backlight is present */ |
15047 | static void quirk_backlight_present(struct drm_device *dev) | |
15048 | { | |
15049 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15050 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15051 | DRM_INFO("applying backlight present quirk\n"); | |
15052 | } | |
15053 | ||
b690e96c JB |
15054 | struct intel_quirk { |
15055 | int device; | |
15056 | int subsystem_vendor; | |
15057 | int subsystem_device; | |
15058 | void (*hook)(struct drm_device *dev); | |
15059 | }; | |
15060 | ||
5f85f176 EE |
15061 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15062 | struct intel_dmi_quirk { | |
15063 | void (*hook)(struct drm_device *dev); | |
15064 | const struct dmi_system_id (*dmi_id_list)[]; | |
15065 | }; | |
15066 | ||
15067 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15068 | { | |
15069 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15070 | return 1; | |
15071 | } | |
15072 | ||
15073 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15074 | { | |
15075 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15076 | { | |
15077 | .callback = intel_dmi_reverse_brightness, | |
15078 | .ident = "NCR Corporation", | |
15079 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15080 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15081 | }, | |
15082 | }, | |
15083 | { } /* terminating entry */ | |
15084 | }, | |
15085 | .hook = quirk_invert_brightness, | |
15086 | }, | |
15087 | }; | |
15088 | ||
c43b5634 | 15089 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15090 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15091 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15092 | ||
b690e96c JB |
15093 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15094 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15095 | ||
5f080c0f VS |
15096 | /* 830 needs to leave pipe A & dpll A up */ |
15097 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15098 | ||
b6b5d049 VS |
15099 | /* 830 needs to leave pipe B & dpll B up */ |
15100 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15101 | ||
435793df KP |
15102 | /* Lenovo U160 cannot use SSC on LVDS */ |
15103 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15104 | |
15105 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15106 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15107 | |
be505f64 AH |
15108 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15109 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15110 | ||
15111 | /* Acer/eMachines G725 */ | |
15112 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15113 | ||
15114 | /* Acer/eMachines e725 */ | |
15115 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15116 | ||
15117 | /* Acer/Packard Bell NCL20 */ | |
15118 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15119 | ||
15120 | /* Acer Aspire 4736Z */ | |
15121 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15122 | |
15123 | /* Acer Aspire 5336 */ | |
15124 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15125 | |
15126 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15127 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15128 | |
dfb3d47b SD |
15129 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15130 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15131 | ||
b2a9601c | 15132 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15133 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15134 | ||
1b9448b0 JN |
15135 | /* Apple Macbook 4,1 */ |
15136 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15137 | ||
d4967d8c SD |
15138 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15139 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15140 | |
15141 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15142 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15143 | |
15144 | /* Dell Chromebook 11 */ | |
15145 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15146 | |
15147 | /* Dell Chromebook 11 (2015 version) */ | |
15148 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15149 | }; |
15150 | ||
15151 | static void intel_init_quirks(struct drm_device *dev) | |
15152 | { | |
15153 | struct pci_dev *d = dev->pdev; | |
15154 | int i; | |
15155 | ||
15156 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15157 | struct intel_quirk *q = &intel_quirks[i]; | |
15158 | ||
15159 | if (d->device == q->device && | |
15160 | (d->subsystem_vendor == q->subsystem_vendor || | |
15161 | q->subsystem_vendor == PCI_ANY_ID) && | |
15162 | (d->subsystem_device == q->subsystem_device || | |
15163 | q->subsystem_device == PCI_ANY_ID)) | |
15164 | q->hook(dev); | |
15165 | } | |
5f85f176 EE |
15166 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15167 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15168 | intel_dmi_quirks[i].hook(dev); | |
15169 | } | |
b690e96c JB |
15170 | } |
15171 | ||
9cce37f4 JB |
15172 | /* Disable the VGA plane that we never use */ |
15173 | static void i915_disable_vga(struct drm_device *dev) | |
15174 | { | |
15175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15176 | u8 sr1; | |
f0f59a00 | 15177 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15178 | |
2b37c616 | 15179 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15180 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15181 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15182 | sr1 = inb(VGA_SR_DATA); |
15183 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15184 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15185 | udelay(300); | |
15186 | ||
01f5a626 | 15187 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15188 | POSTING_READ(vga_reg); |
15189 | } | |
15190 | ||
f817586c DV |
15191 | void intel_modeset_init_hw(struct drm_device *dev) |
15192 | { | |
b6283055 | 15193 | intel_update_cdclk(dev); |
a8f78b58 | 15194 | intel_prepare_ddi(dev); |
f817586c | 15195 | intel_init_clock_gating(dev); |
8090c6b9 | 15196 | intel_enable_gt_powersave(dev); |
f817586c DV |
15197 | } |
15198 | ||
79e53945 JB |
15199 | void intel_modeset_init(struct drm_device *dev) |
15200 | { | |
652c393a | 15201 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15202 | int sprite, ret; |
8cc87b75 | 15203 | enum pipe pipe; |
46f297fb | 15204 | struct intel_crtc *crtc; |
79e53945 JB |
15205 | |
15206 | drm_mode_config_init(dev); | |
15207 | ||
15208 | dev->mode_config.min_width = 0; | |
15209 | dev->mode_config.min_height = 0; | |
15210 | ||
019d96cb DA |
15211 | dev->mode_config.preferred_depth = 24; |
15212 | dev->mode_config.prefer_shadow = 1; | |
15213 | ||
25bab385 TU |
15214 | dev->mode_config.allow_fb_modifiers = true; |
15215 | ||
e6ecefaa | 15216 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15217 | |
b690e96c JB |
15218 | intel_init_quirks(dev); |
15219 | ||
1fa61106 ED |
15220 | intel_init_pm(dev); |
15221 | ||
e3c74757 BW |
15222 | if (INTEL_INFO(dev)->num_pipes == 0) |
15223 | return; | |
15224 | ||
69f92f67 LW |
15225 | /* |
15226 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15227 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15228 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15229 | * indicates as much. | |
15230 | */ | |
15231 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15232 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15233 | DREF_SSC1_ENABLE); | |
15234 | ||
15235 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15236 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15237 | bios_lvds_use_ssc ? "en" : "dis", | |
15238 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15239 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15240 | } | |
15241 | } | |
15242 | ||
e70236a8 | 15243 | intel_init_display(dev); |
7c10a2b5 | 15244 | intel_init_audio(dev); |
e70236a8 | 15245 | |
a6c45cf0 CW |
15246 | if (IS_GEN2(dev)) { |
15247 | dev->mode_config.max_width = 2048; | |
15248 | dev->mode_config.max_height = 2048; | |
15249 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15250 | dev->mode_config.max_width = 4096; |
15251 | dev->mode_config.max_height = 4096; | |
79e53945 | 15252 | } else { |
a6c45cf0 CW |
15253 | dev->mode_config.max_width = 8192; |
15254 | dev->mode_config.max_height = 8192; | |
79e53945 | 15255 | } |
068be561 | 15256 | |
dc41c154 VS |
15257 | if (IS_845G(dev) || IS_I865G(dev)) { |
15258 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15259 | dev->mode_config.cursor_height = 1023; | |
15260 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15261 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15262 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15263 | } else { | |
15264 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15265 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15266 | } | |
15267 | ||
5d4545ae | 15268 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15269 | |
28c97730 | 15270 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15271 | INTEL_INFO(dev)->num_pipes, |
15272 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15273 | |
055e393f | 15274 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15275 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15276 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15277 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15278 | if (ret) |
06da8da2 | 15279 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15280 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15281 | } |
79e53945 JB |
15282 | } |
15283 | ||
bfa7df01 VS |
15284 | intel_update_czclk(dev_priv); |
15285 | intel_update_cdclk(dev); | |
15286 | ||
e72f9fbf | 15287 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15288 | |
9cce37f4 JB |
15289 | /* Just disable it once at startup */ |
15290 | i915_disable_vga(dev); | |
79e53945 | 15291 | intel_setup_outputs(dev); |
11be49eb | 15292 | |
6e9f798d | 15293 | drm_modeset_lock_all(dev); |
043e9bda | 15294 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15295 | drm_modeset_unlock_all(dev); |
46f297fb | 15296 | |
d3fcc808 | 15297 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15298 | struct intel_initial_plane_config plane_config = {}; |
15299 | ||
46f297fb JB |
15300 | if (!crtc->active) |
15301 | continue; | |
15302 | ||
46f297fb | 15303 | /* |
46f297fb JB |
15304 | * Note that reserving the BIOS fb up front prevents us |
15305 | * from stuffing other stolen allocations like the ring | |
15306 | * on top. This prevents some ugliness at boot time, and | |
15307 | * can even allow for smooth boot transitions if the BIOS | |
15308 | * fb is large enough for the active pipe configuration. | |
15309 | */ | |
eeebeac5 ML |
15310 | dev_priv->display.get_initial_plane_config(crtc, |
15311 | &plane_config); | |
15312 | ||
15313 | /* | |
15314 | * If the fb is shared between multiple heads, we'll | |
15315 | * just get the first one. | |
15316 | */ | |
15317 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15318 | } |
2c7111db CW |
15319 | } |
15320 | ||
7fad798e DV |
15321 | static void intel_enable_pipe_a(struct drm_device *dev) |
15322 | { | |
15323 | struct intel_connector *connector; | |
15324 | struct drm_connector *crt = NULL; | |
15325 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15326 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15327 | |
15328 | /* We can't just switch on the pipe A, we need to set things up with a | |
15329 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15330 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15331 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15332 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15333 | crt = &connector->base; | |
15334 | break; | |
15335 | } | |
15336 | } | |
15337 | ||
15338 | if (!crt) | |
15339 | return; | |
15340 | ||
208bf9fd | 15341 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15342 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15343 | } |
15344 | ||
fa555837 DV |
15345 | static bool |
15346 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15347 | { | |
7eb552ae BW |
15348 | struct drm_device *dev = crtc->base.dev; |
15349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15350 | u32 val; |
fa555837 | 15351 | |
7eb552ae | 15352 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15353 | return true; |
15354 | ||
649636ef | 15355 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15356 | |
15357 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15358 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15359 | return false; | |
15360 | ||
15361 | return true; | |
15362 | } | |
15363 | ||
02e93c35 VS |
15364 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15365 | { | |
15366 | struct drm_device *dev = crtc->base.dev; | |
15367 | struct intel_encoder *encoder; | |
15368 | ||
15369 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15370 | return true; | |
15371 | ||
15372 | return false; | |
15373 | } | |
15374 | ||
24929352 DV |
15375 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15376 | { | |
15377 | struct drm_device *dev = crtc->base.dev; | |
15378 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15379 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15380 | |
24929352 | 15381 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15382 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15383 | ||
d3eaf884 | 15384 | /* restore vblank interrupts to correct state */ |
9625604c | 15385 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15386 | if (crtc->active) { |
f9cd7b88 VS |
15387 | struct intel_plane *plane; |
15388 | ||
9625604c | 15389 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15390 | |
15391 | /* Disable everything but the primary plane */ | |
15392 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15393 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15394 | continue; | |
15395 | ||
15396 | plane->disable_plane(&plane->base, &crtc->base); | |
15397 | } | |
9625604c | 15398 | } |
d3eaf884 | 15399 | |
24929352 | 15400 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15401 | * disable the crtc (and hence change the state) if it is wrong. Note |
15402 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15403 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15404 | bool plane; |
15405 | ||
24929352 DV |
15406 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15407 | crtc->base.base.id); | |
15408 | ||
15409 | /* Pipe has the wrong plane attached and the plane is active. | |
15410 | * Temporarily change the plane mapping and disable everything | |
15411 | * ... */ | |
15412 | plane = crtc->plane; | |
b70709a6 | 15413 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15414 | crtc->plane = !plane; |
b17d48e2 | 15415 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15416 | crtc->plane = plane; |
24929352 | 15417 | } |
24929352 | 15418 | |
7fad798e DV |
15419 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15420 | crtc->pipe == PIPE_A && !crtc->active) { | |
15421 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15422 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15423 | * call below we restore the pipe to the right state, but leave | |
15424 | * the required bits on. */ | |
15425 | intel_enable_pipe_a(dev); | |
15426 | } | |
15427 | ||
24929352 DV |
15428 | /* Adjust the state of the output pipe according to whether we |
15429 | * have active connectors/encoders. */ | |
02e93c35 | 15430 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15431 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15432 | |
53d9f4e9 | 15433 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15434 | struct intel_encoder *encoder; |
24929352 DV |
15435 | |
15436 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15437 | * functions or because of calls to intel_crtc_disable_noatomic, |
15438 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15439 | * pipe A quirk. */ |
15440 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15441 | crtc->base.base.id, | |
83d65738 | 15442 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15443 | crtc->active ? "enabled" : "disabled"); |
15444 | ||
4be40c98 | 15445 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15446 | crtc->base.state->active = crtc->active; |
24929352 DV |
15447 | crtc->base.enabled = crtc->active; |
15448 | ||
15449 | /* Because we only establish the connector -> encoder -> | |
15450 | * crtc links if something is active, this means the | |
15451 | * crtc is now deactivated. Break the links. connector | |
15452 | * -> encoder links are only establish when things are | |
15453 | * actually up, hence no need to break them. */ | |
15454 | WARN_ON(crtc->active); | |
15455 | ||
2d406bb0 | 15456 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15457 | encoder->base.crtc = NULL; |
24929352 | 15458 | } |
c5ab3bc0 | 15459 | |
a3ed6aad | 15460 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15461 | /* |
15462 | * We start out with underrun reporting disabled to avoid races. | |
15463 | * For correct bookkeeping mark this on active crtcs. | |
15464 | * | |
c5ab3bc0 DV |
15465 | * Also on gmch platforms we dont have any hardware bits to |
15466 | * disable the underrun reporting. Which means we need to start | |
15467 | * out with underrun reporting disabled also on inactive pipes, | |
15468 | * since otherwise we'll complain about the garbage we read when | |
15469 | * e.g. coming up after runtime pm. | |
15470 | * | |
4cc31489 DV |
15471 | * No protection against concurrent access is required - at |
15472 | * worst a fifo underrun happens which also sets this to false. | |
15473 | */ | |
15474 | crtc->cpu_fifo_underrun_disabled = true; | |
15475 | crtc->pch_fifo_underrun_disabled = true; | |
15476 | } | |
24929352 DV |
15477 | } |
15478 | ||
15479 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15480 | { | |
15481 | struct intel_connector *connector; | |
15482 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15483 | bool active = false; |
24929352 DV |
15484 | |
15485 | /* We need to check both for a crtc link (meaning that the | |
15486 | * encoder is active and trying to read from a pipe) and the | |
15487 | * pipe itself being active. */ | |
15488 | bool has_active_crtc = encoder->base.crtc && | |
15489 | to_intel_crtc(encoder->base.crtc)->active; | |
15490 | ||
873ffe69 ML |
15491 | for_each_intel_connector(dev, connector) { |
15492 | if (connector->base.encoder != &encoder->base) | |
15493 | continue; | |
15494 | ||
15495 | active = true; | |
15496 | break; | |
15497 | } | |
15498 | ||
15499 | if (active && !has_active_crtc) { | |
24929352 DV |
15500 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15501 | encoder->base.base.id, | |
8e329a03 | 15502 | encoder->base.name); |
24929352 DV |
15503 | |
15504 | /* Connector is active, but has no active pipe. This is | |
15505 | * fallout from our resume register restoring. Disable | |
15506 | * the encoder manually again. */ | |
15507 | if (encoder->base.crtc) { | |
15508 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15509 | encoder->base.base.id, | |
8e329a03 | 15510 | encoder->base.name); |
24929352 | 15511 | encoder->disable(encoder); |
a62d1497 VS |
15512 | if (encoder->post_disable) |
15513 | encoder->post_disable(encoder); | |
24929352 | 15514 | } |
7f1950fb | 15515 | encoder->base.crtc = NULL; |
24929352 DV |
15516 | |
15517 | /* Inconsistent output/port/pipe state happens presumably due to | |
15518 | * a bug in one of the get_hw_state functions. Or someplace else | |
15519 | * in our code, like the register restore mess on resume. Clamp | |
15520 | * things to off as a safer default. */ | |
3a3371ff | 15521 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15522 | if (connector->encoder != encoder) |
15523 | continue; | |
7f1950fb EE |
15524 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15525 | connector->base.encoder = NULL; | |
24929352 DV |
15526 | } |
15527 | } | |
15528 | /* Enabled encoders without active connectors will be fixed in | |
15529 | * the crtc fixup. */ | |
15530 | } | |
15531 | ||
04098753 | 15532 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15533 | { |
15534 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15535 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15536 | |
04098753 ID |
15537 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15538 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15539 | i915_disable_vga(dev); | |
15540 | } | |
15541 | } | |
15542 | ||
15543 | void i915_redisable_vga(struct drm_device *dev) | |
15544 | { | |
15545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15546 | ||
8dc8a27c PZ |
15547 | /* This function can be called both from intel_modeset_setup_hw_state or |
15548 | * at a very early point in our resume sequence, where the power well | |
15549 | * structures are not yet restored. Since this function is at a very | |
15550 | * paranoid "someone might have enabled VGA while we were not looking" | |
15551 | * level, just check if the power well is enabled instead of trying to | |
15552 | * follow the "don't touch the power well if we don't need it" policy | |
15553 | * the rest of the driver uses. */ | |
f458ebbc | 15554 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15555 | return; |
15556 | ||
04098753 | 15557 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15558 | } |
15559 | ||
f9cd7b88 | 15560 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15561 | { |
f9cd7b88 | 15562 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15563 | |
f9cd7b88 | 15564 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15565 | } |
15566 | ||
f9cd7b88 VS |
15567 | /* FIXME read out full plane state for all planes */ |
15568 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15569 | { |
b26d3ea3 | 15570 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15571 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15572 | to_intel_plane_state(primary->state); |
d032ffa0 | 15573 | |
19b8d387 | 15574 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15575 | primary_get_hw_state(to_intel_plane(primary)); |
15576 | ||
15577 | if (plane_state->visible) | |
15578 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15579 | } |
15580 | ||
30e984df | 15581 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15582 | { |
15583 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15584 | enum pipe pipe; | |
24929352 DV |
15585 | struct intel_crtc *crtc; |
15586 | struct intel_encoder *encoder; | |
15587 | struct intel_connector *connector; | |
5358901f | 15588 | int i; |
24929352 | 15589 | |
d3fcc808 | 15590 | for_each_intel_crtc(dev, crtc) { |
b06f8b0d | 15591 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state); |
6e3c9717 | 15592 | memset(crtc->config, 0, sizeof(*crtc->config)); |
f7217905 | 15593 | crtc->config->base.crtc = &crtc->base; |
3b117c8f | 15594 | |
0e8ffe1b | 15595 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 15596 | crtc->config); |
24929352 | 15597 | |
49d6fa21 | 15598 | crtc->base.state->active = crtc->active; |
24929352 | 15599 | crtc->base.enabled = crtc->active; |
b70709a6 | 15600 | |
f9cd7b88 | 15601 | readout_plane_state(crtc); |
24929352 DV |
15602 | |
15603 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15604 | crtc->base.base.id, | |
15605 | crtc->active ? "enabled" : "disabled"); | |
15606 | } | |
15607 | ||
5358901f DV |
15608 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15609 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15610 | ||
3e369b76 ACO |
15611 | pll->on = pll->get_hw_state(dev_priv, pll, |
15612 | &pll->config.hw_state); | |
5358901f | 15613 | pll->active = 0; |
3e369b76 | 15614 | pll->config.crtc_mask = 0; |
d3fcc808 | 15615 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15616 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15617 | pll->active++; |
3e369b76 | 15618 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15619 | } |
5358901f | 15620 | } |
5358901f | 15621 | |
1e6f2ddc | 15622 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15623 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15624 | |
3e369b76 | 15625 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15626 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15627 | } |
15628 | ||
b2784e15 | 15629 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15630 | pipe = 0; |
15631 | ||
15632 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15633 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15634 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15635 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15636 | } else { |
15637 | encoder->base.crtc = NULL; | |
15638 | } | |
15639 | ||
6f2bcceb | 15640 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15641 | encoder->base.base.id, |
8e329a03 | 15642 | encoder->base.name, |
24929352 | 15643 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15644 | pipe_name(pipe)); |
24929352 DV |
15645 | } |
15646 | ||
3a3371ff | 15647 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15648 | if (connector->get_hw_state(connector)) { |
15649 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
24929352 DV |
15650 | connector->base.encoder = &connector->encoder->base; |
15651 | } else { | |
15652 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15653 | connector->base.encoder = NULL; | |
15654 | } | |
15655 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15656 | connector->base.base.id, | |
c23cc417 | 15657 | connector->base.name, |
24929352 DV |
15658 | connector->base.encoder ? "enabled" : "disabled"); |
15659 | } | |
7f4c6284 VS |
15660 | |
15661 | for_each_intel_crtc(dev, crtc) { | |
15662 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15663 | ||
15664 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15665 | if (crtc->base.state->active) { | |
15666 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15667 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15668 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15669 | ||
15670 | /* | |
15671 | * The initial mode needs to be set in order to keep | |
15672 | * the atomic core happy. It wants a valid mode if the | |
15673 | * crtc's enabled, so we do the above call. | |
15674 | * | |
15675 | * At this point some state updated by the connectors | |
15676 | * in their ->detect() callback has not run yet, so | |
15677 | * no recalculation can be done yet. | |
15678 | * | |
15679 | * Even if we could do a recalculation and modeset | |
15680 | * right now it would cause a double modeset if | |
15681 | * fbdev or userspace chooses a different initial mode. | |
15682 | * | |
15683 | * If that happens, someone indicated they wanted a | |
15684 | * mode change, which means it's safe to do a full | |
15685 | * recalculation. | |
15686 | */ | |
15687 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15688 | |
15689 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15690 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15691 | } |
15692 | } | |
30e984df DV |
15693 | } |
15694 | ||
043e9bda ML |
15695 | /* Scan out the current hw modeset state, |
15696 | * and sanitizes it to the current state | |
15697 | */ | |
15698 | static void | |
15699 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15700 | { |
15701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15702 | enum pipe pipe; | |
30e984df DV |
15703 | struct intel_crtc *crtc; |
15704 | struct intel_encoder *encoder; | |
35c95375 | 15705 | int i; |
30e984df DV |
15706 | |
15707 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15708 | |
15709 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15710 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15711 | intel_sanitize_encoder(encoder); |
15712 | } | |
15713 | ||
055e393f | 15714 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15715 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15716 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15717 | intel_dump_pipe_config(crtc, crtc->config, |
15718 | "[setup_hw_state]"); | |
24929352 | 15719 | } |
9a935856 | 15720 | |
d29b2f9d ACO |
15721 | intel_modeset_update_connector_atomic_state(dev); |
15722 | ||
35c95375 DV |
15723 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15724 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15725 | ||
15726 | if (!pll->on || pll->active) | |
15727 | continue; | |
15728 | ||
15729 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15730 | ||
15731 | pll->disable(dev_priv, pll); | |
15732 | pll->on = false; | |
15733 | } | |
15734 | ||
666a4537 | 15735 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15736 | vlv_wm_get_hw_state(dev); |
15737 | else if (IS_GEN9(dev)) | |
3078999f PB |
15738 | skl_wm_get_hw_state(dev); |
15739 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15740 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15741 | |
15742 | for_each_intel_crtc(dev, crtc) { | |
15743 | unsigned long put_domains; | |
15744 | ||
15745 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15746 | if (WARN_ON(put_domains)) | |
15747 | modeset_put_power_domains(dev_priv, put_domains); | |
15748 | } | |
15749 | intel_display_set_init_power(dev_priv, false); | |
043e9bda | 15750 | } |
7d0bc1ea | 15751 | |
043e9bda ML |
15752 | void intel_display_resume(struct drm_device *dev) |
15753 | { | |
15754 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15755 | struct intel_connector *conn; | |
15756 | struct intel_plane *plane; | |
15757 | struct drm_crtc *crtc; | |
15758 | int ret; | |
f30da187 | 15759 | |
043e9bda ML |
15760 | if (!state) |
15761 | return; | |
15762 | ||
15763 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15764 | ||
15765 | /* preserve complete old state, including dpll */ | |
15766 | intel_atomic_get_shared_dpll_state(state); | |
15767 | ||
15768 | for_each_crtc(dev, crtc) { | |
15769 | struct drm_crtc_state *crtc_state = | |
15770 | drm_atomic_get_crtc_state(state, crtc); | |
15771 | ||
15772 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
15773 | if (ret) | |
15774 | goto err; | |
15775 | ||
15776 | /* force a restore */ | |
15777 | crtc_state->mode_changed = true; | |
45e2b5f6 | 15778 | } |
8af6cf88 | 15779 | |
043e9bda ML |
15780 | for_each_intel_plane(dev, plane) { |
15781 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
15782 | if (ret) | |
15783 | goto err; | |
15784 | } | |
15785 | ||
15786 | for_each_intel_connector(dev, conn) { | |
15787 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
15788 | if (ret) | |
15789 | goto err; | |
15790 | } | |
15791 | ||
15792 | intel_modeset_setup_hw_state(dev); | |
15793 | ||
15794 | i915_redisable_vga(dev); | |
74c090b1 | 15795 | ret = drm_atomic_commit(state); |
043e9bda ML |
15796 | if (!ret) |
15797 | return; | |
15798 | ||
15799 | err: | |
15800 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15801 | drm_atomic_state_free(state); | |
2c7111db CW |
15802 | } |
15803 | ||
15804 | void intel_modeset_gem_init(struct drm_device *dev) | |
15805 | { | |
484b41dd | 15806 | struct drm_crtc *c; |
2ff8fde1 | 15807 | struct drm_i915_gem_object *obj; |
e0d6149b | 15808 | int ret; |
484b41dd | 15809 | |
ae48434c ID |
15810 | mutex_lock(&dev->struct_mutex); |
15811 | intel_init_gt_powersave(dev); | |
15812 | mutex_unlock(&dev->struct_mutex); | |
15813 | ||
1833b134 | 15814 | intel_modeset_init_hw(dev); |
02e792fb DV |
15815 | |
15816 | intel_setup_overlay(dev); | |
484b41dd JB |
15817 | |
15818 | /* | |
15819 | * Make sure any fbs we allocated at startup are properly | |
15820 | * pinned & fenced. When we do the allocation it's too early | |
15821 | * for this. | |
15822 | */ | |
70e1e0ec | 15823 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15824 | obj = intel_fb_obj(c->primary->fb); |
15825 | if (obj == NULL) | |
484b41dd JB |
15826 | continue; |
15827 | ||
e0d6149b TU |
15828 | mutex_lock(&dev->struct_mutex); |
15829 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15830 | c->primary->fb, | |
7580d774 | 15831 | c->primary->state); |
e0d6149b TU |
15832 | mutex_unlock(&dev->struct_mutex); |
15833 | if (ret) { | |
484b41dd JB |
15834 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15835 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15836 | drm_framebuffer_unreference(c->primary->fb); |
15837 | c->primary->fb = NULL; | |
36750f28 | 15838 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15839 | update_state_fb(c->primary); |
36750f28 | 15840 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15841 | } |
15842 | } | |
0962c3c9 VS |
15843 | |
15844 | intel_backlight_register(dev); | |
79e53945 JB |
15845 | } |
15846 | ||
4932e2c3 ID |
15847 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15848 | { | |
15849 | struct drm_connector *connector = &intel_connector->base; | |
15850 | ||
15851 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15852 | drm_connector_unregister(connector); |
4932e2c3 ID |
15853 | } |
15854 | ||
79e53945 JB |
15855 | void intel_modeset_cleanup(struct drm_device *dev) |
15856 | { | |
652c393a | 15857 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 15858 | struct intel_connector *connector; |
652c393a | 15859 | |
2eb5252e ID |
15860 | intel_disable_gt_powersave(dev); |
15861 | ||
0962c3c9 VS |
15862 | intel_backlight_unregister(dev); |
15863 | ||
fd0c0642 DV |
15864 | /* |
15865 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15866 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15867 | * experience fancy races otherwise. |
15868 | */ | |
2aeb7d3a | 15869 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15870 | |
fd0c0642 DV |
15871 | /* |
15872 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15873 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15874 | */ | |
f87ea761 | 15875 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15876 | |
723bfd70 JB |
15877 | intel_unregister_dsm_handler(); |
15878 | ||
7733b49b | 15879 | intel_fbc_disable(dev_priv); |
69341a5e | 15880 | |
1630fe75 CW |
15881 | /* flush any delayed tasks or pending work */ |
15882 | flush_scheduled_work(); | |
15883 | ||
db31af1d | 15884 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
15885 | for_each_intel_connector(dev, connector) |
15886 | connector->unregister(connector); | |
d9255d57 | 15887 | |
79e53945 | 15888 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15889 | |
15890 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15891 | |
15892 | mutex_lock(&dev->struct_mutex); | |
15893 | intel_cleanup_gt_powersave(dev); | |
15894 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15895 | } |
15896 | ||
f1c79df3 ZW |
15897 | /* |
15898 | * Return which encoder is currently attached for connector. | |
15899 | */ | |
df0e9248 | 15900 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15901 | { |
df0e9248 CW |
15902 | return &intel_attached_encoder(connector)->base; |
15903 | } | |
f1c79df3 | 15904 | |
df0e9248 CW |
15905 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15906 | struct intel_encoder *encoder) | |
15907 | { | |
15908 | connector->encoder = encoder; | |
15909 | drm_mode_connector_attach_encoder(&connector->base, | |
15910 | &encoder->base); | |
79e53945 | 15911 | } |
28d52043 DA |
15912 | |
15913 | /* | |
15914 | * set vga decode state - true == enable VGA decode | |
15915 | */ | |
15916 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15917 | { | |
15918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15919 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15920 | u16 gmch_ctrl; |
15921 | ||
75fa041d CW |
15922 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15923 | DRM_ERROR("failed to read control word\n"); | |
15924 | return -EIO; | |
15925 | } | |
15926 | ||
c0cc8a55 CW |
15927 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15928 | return 0; | |
15929 | ||
28d52043 DA |
15930 | if (state) |
15931 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15932 | else | |
15933 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15934 | |
15935 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15936 | DRM_ERROR("failed to write control word\n"); | |
15937 | return -EIO; | |
15938 | } | |
15939 | ||
28d52043 DA |
15940 | return 0; |
15941 | } | |
c4a1d9e4 | 15942 | |
c4a1d9e4 | 15943 | struct intel_display_error_state { |
ff57f1b0 PZ |
15944 | |
15945 | u32 power_well_driver; | |
15946 | ||
63b66e5b CW |
15947 | int num_transcoders; |
15948 | ||
c4a1d9e4 CW |
15949 | struct intel_cursor_error_state { |
15950 | u32 control; | |
15951 | u32 position; | |
15952 | u32 base; | |
15953 | u32 size; | |
52331309 | 15954 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15955 | |
15956 | struct intel_pipe_error_state { | |
ddf9c536 | 15957 | bool power_domain_on; |
c4a1d9e4 | 15958 | u32 source; |
f301b1e1 | 15959 | u32 stat; |
52331309 | 15960 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15961 | |
15962 | struct intel_plane_error_state { | |
15963 | u32 control; | |
15964 | u32 stride; | |
15965 | u32 size; | |
15966 | u32 pos; | |
15967 | u32 addr; | |
15968 | u32 surface; | |
15969 | u32 tile_offset; | |
52331309 | 15970 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15971 | |
15972 | struct intel_transcoder_error_state { | |
ddf9c536 | 15973 | bool power_domain_on; |
63b66e5b CW |
15974 | enum transcoder cpu_transcoder; |
15975 | ||
15976 | u32 conf; | |
15977 | ||
15978 | u32 htotal; | |
15979 | u32 hblank; | |
15980 | u32 hsync; | |
15981 | u32 vtotal; | |
15982 | u32 vblank; | |
15983 | u32 vsync; | |
15984 | } transcoder[4]; | |
c4a1d9e4 CW |
15985 | }; |
15986 | ||
15987 | struct intel_display_error_state * | |
15988 | intel_display_capture_error_state(struct drm_device *dev) | |
15989 | { | |
fbee40df | 15990 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15991 | struct intel_display_error_state *error; |
63b66e5b CW |
15992 | int transcoders[] = { |
15993 | TRANSCODER_A, | |
15994 | TRANSCODER_B, | |
15995 | TRANSCODER_C, | |
15996 | TRANSCODER_EDP, | |
15997 | }; | |
c4a1d9e4 CW |
15998 | int i; |
15999 | ||
63b66e5b CW |
16000 | if (INTEL_INFO(dev)->num_pipes == 0) |
16001 | return NULL; | |
16002 | ||
9d1cb914 | 16003 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16004 | if (error == NULL) |
16005 | return NULL; | |
16006 | ||
190be112 | 16007 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16008 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16009 | ||
055e393f | 16010 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16011 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16012 | __intel_display_power_is_enabled(dev_priv, |
16013 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16014 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16015 | continue; |
16016 | ||
5efb3e28 VS |
16017 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16018 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16019 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16020 | |
16021 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16022 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16023 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16024 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16025 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16026 | } | |
ca291363 PZ |
16027 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16028 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16029 | if (INTEL_INFO(dev)->gen >= 4) { |
16030 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16031 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16032 | } | |
16033 | ||
c4a1d9e4 | 16034 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16035 | |
3abfce77 | 16036 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16037 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16038 | } |
16039 | ||
16040 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16041 | if (HAS_DDI(dev_priv->dev)) | |
16042 | error->num_transcoders++; /* Account for eDP. */ | |
16043 | ||
16044 | for (i = 0; i < error->num_transcoders; i++) { | |
16045 | enum transcoder cpu_transcoder = transcoders[i]; | |
16046 | ||
ddf9c536 | 16047 | error->transcoder[i].power_domain_on = |
f458ebbc | 16048 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16049 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16050 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16051 | continue; |
16052 | ||
63b66e5b CW |
16053 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16054 | ||
16055 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16056 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16057 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16058 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16059 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16060 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16061 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16062 | } |
16063 | ||
16064 | return error; | |
16065 | } | |
16066 | ||
edc3d884 MK |
16067 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16068 | ||
c4a1d9e4 | 16069 | void |
edc3d884 | 16070 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16071 | struct drm_device *dev, |
16072 | struct intel_display_error_state *error) | |
16073 | { | |
055e393f | 16074 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16075 | int i; |
16076 | ||
63b66e5b CW |
16077 | if (!error) |
16078 | return; | |
16079 | ||
edc3d884 | 16080 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16081 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16082 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16083 | error->power_well_driver); |
055e393f | 16084 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16085 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
16086 | err_printf(m, " Power: %s\n", |
16087 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 16088 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16089 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16090 | |
16091 | err_printf(m, "Plane [%d]:\n", i); | |
16092 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16093 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16094 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16095 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16096 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16097 | } |
4b71a570 | 16098 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16099 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16100 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16101 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16102 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16103 | } |
16104 | ||
edc3d884 MK |
16105 | err_printf(m, "Cursor [%d]:\n", i); |
16106 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16107 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16108 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16109 | } |
63b66e5b CW |
16110 | |
16111 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16112 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16113 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
16114 | err_printf(m, " Power: %s\n", |
16115 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
16116 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16117 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16118 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16119 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16120 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16121 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16122 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16123 | } | |
c4a1d9e4 | 16124 | } |
e2fcdaa9 VS |
16125 | |
16126 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
16127 | { | |
16128 | struct intel_crtc *crtc; | |
16129 | ||
16130 | for_each_intel_crtc(dev, crtc) { | |
16131 | struct intel_unpin_work *work; | |
e2fcdaa9 | 16132 | |
5e2d7afc | 16133 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16134 | |
16135 | work = crtc->unpin_work; | |
16136 | ||
16137 | if (work && work->event && | |
16138 | work->event->base.file_priv == file) { | |
16139 | kfree(work->event); | |
16140 | work->event = NULL; | |
16141 | } | |
16142 | ||
5e2d7afc | 16143 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16144 | } |
16145 | } |