projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Fix port_clock and adjusted_mode.clock readout all over
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
18442d08
VS		 50static void ironlake_pch_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
f1f644dc 52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
a0c4da24 401 else
65ce4bf5 402 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
406 else
407 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 408 } else {
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 410 limit = &intel_limits_i8xx_lvds;
5d536e28 411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 412 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 413 else
414 limit = &intel_limits_i8xx_dac;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
f3f08572 675 u32 updrate, minupdate, p;
a0c4da24
JB		 676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
a0c4da24
JB		 686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
688
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
694 if (p2 > 10)
695 p2 = p2 - 1;
696 p = p1 * p2;
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
701 m = m1 * m2;
702 vco = updrate * m;
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
707 bestppm = 0;
708 flag = 1;
709 }
710 if (absppm < bestppm - 10) {
711 bestppm = absppm;
712 flag = 1;
713 }
714 if (flag) {
715 bestn = n;
716 bestm1 = m1;
717 bestm2 = m2;
718 bestp1 = p1;
719 bestp2 = p2;
720 flag = 0;
721 }
722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
a5c961d1
PZ		 736enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
737 enum pipe pipe)
738{
739 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
741
3b117c8f 742 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 743}
744
a928d536
PZ		 745static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
746{
747 struct drm_i915_private *dev_priv = dev->dev_private;
748 u32 frame, frame_reg = PIPEFRAME(pipe);
749
750 frame = I915_READ(frame_reg);
751
752 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
753 DRM_DEBUG_KMS("vblank wait timed out\n");
754}
755
9d0498a2
JB		 756/**
757 * intel_wait_for_vblank - wait for vblank on a given pipe
758 * @dev: drm device
759 * @pipe: pipe to wait for
760 *
761 * Wait for vblank to occur on a given pipe. Needed for various bits of
762 * mode setting code.
763 */
764void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 765{
9d0498a2 766 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 767 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 768
a928d536
PZ		 769 if (INTEL_INFO(dev)->gen >= 5) {
770 ironlake_wait_for_vblank(dev, pipe);
771 return;
772 }
773
300387c0
CW		 774 /* Clear existing vblank status. Note this will clear any other
775 * sticky status fields as well.
776 *
777 * This races with i915_driver_irq_handler() with the result
778 * that either function could miss a vblank event. Here it is not
779 * fatal, as we will either wait upon the next vblank interrupt or
780 * timeout. Generally speaking intel_wait_for_vblank() is only
781 * called during modeset at which time the GPU should be idle and
782 * should *not* be performing page flips and thus not waiting on
783 * vblanks...
784 * Currently, the result of us stealing a vblank from the irq
785 * handler is that a single frame will be skipped during swapbuffers.
786 */
787 I915_WRITE(pipestat_reg,
788 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
789
9d0498a2 790 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 791 if (wait_for(I915_READ(pipestat_reg) &
792 PIPE_VBLANK_INTERRUPT_STATUS,
793 50))
9d0498a2
JB		 794 DRM_DEBUG_KMS("vblank wait timed out\n");
795}
796
ab7ad7f6
KP		 797/*
798 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 799 * @dev: drm device
800 * @pipe: pipe to wait for
801 *
802 * After disabling a pipe, we can't wait for vblank in the usual way,
803 * spinning on the vblank interrupt status bit, since we won't actually
804 * see an interrupt when the pipe is disabled.
805 *
ab7ad7f6
KP		 806 * On Gen4 and above:
807 * wait for the pipe register state bit to turn off
808 *
809 * Otherwise:
810 * wait for the display line value to settle (it usually
811 * ends up stopping at the start of the next frame).
58e10eb9 812 *
9d0498a2 813 */
58e10eb9 814void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 815{
816 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
818 pipe);
ab7ad7f6
KP		 819
820 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 821 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 822
823 /* Wait for the Pipe State to go off */
58e10eb9
CW		 824 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
825 100))
284637d9 826 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 827 } else {
837ba00f 828 u32 last_line, line_mask;
58e10eb9 829 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 830 unsigned long timeout = jiffies + msecs_to_jiffies(100);
831
837ba00f
PZ		 832 if (IS_GEN2(dev))
833 line_mask = DSL_LINEMASK_GEN2;
834 else
835 line_mask = DSL_LINEMASK_GEN3;
836
ab7ad7f6
KP		 837 /* Wait for the display line to settle */
838 do {
837ba00f 839 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 840 mdelay(5);
837ba00f 841 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 842 time_after(timeout, jiffies));
843 if (time_after(jiffies, timeout))
284637d9 844 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 845 }
79e53945
JB		 846}
847
b0ea7d37
DL		 848/*
849 * ibx_digital_port_connected - is the specified port connected?
850 * @dev_priv: i915 private structure
851 * @port: the port to test
852 *
853 * Returns true if @port is connected, false otherwise.
854 */
855bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
856 struct intel_digital_port *port)
857{
858 u32 bit;
859
c36346e3
DL		 860 if (HAS_PCH_IBX(dev_priv->dev)) {
861 switch(port->port) {
862 case PORT_B:
863 bit = SDE_PORTB_HOTPLUG;
864 break;
865 case PORT_C:
866 bit = SDE_PORTC_HOTPLUG;
867 break;
868 case PORT_D:
869 bit = SDE_PORTD_HOTPLUG;
870 break;
871 default:
872 return true;
873 }
874 } else {
875 switch(port->port) {
876 case PORT_B:
877 bit = SDE_PORTB_HOTPLUG_CPT;
878 break;
879 case PORT_C:
880 bit = SDE_PORTC_HOTPLUG_CPT;
881 break;
882 case PORT_D:
883 bit = SDE_PORTD_HOTPLUG_CPT;
884 break;
885 default:
886 return true;
887 }
b0ea7d37
DL		 888 }
889
890 return I915_READ(SDEISR) & bit;
891}
892
b24e7179
JB		 893static const char *state_string(bool enabled)
894{
895 return enabled ? "on" : "off";
896}
897
898/* Only for pre-ILK configs */
55607e8a
DV		 899void assert_pll(struct drm_i915_private *dev_priv,
900 enum pipe pipe, bool state)
b24e7179
JB		 901{
902 int reg;
903 u32 val;
904 bool cur_state;
905
906 reg = DPLL(pipe);
907 val = I915_READ(reg);
908 cur_state = !!(val & DPLL_VCO_ENABLE);
909 WARN(cur_state != state,
910 "PLL state assertion failure (expected %s, current %s)\n",
911 state_string(state), state_string(cur_state));
912}
b24e7179 913
23538ef1
JN		 914/* XXX: the dsi pll is shared between MIPI DSI ports */
915static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
916{
917 u32 val;
918 bool cur_state;
919
920 mutex_lock(&dev_priv->dpio_lock);
921 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
922 mutex_unlock(&dev_priv->dpio_lock);
923
924 cur_state = val & DSI_PLL_VCO_EN;
925 WARN(cur_state != state,
926 "DSI PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state), state_string(cur_state));
928}
929#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
930#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
931
55607e8a 932struct intel_shared_dpll *
e2b78267
DV		 933intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
934{
935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
936
a43f6e0f 937 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 938 return NULL;
939
a43f6e0f 940 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 941}
942
040484af 943/* For ILK+ */
55607e8a
DV		 944void assert_shared_dpll(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll,
946 bool state)
040484af 947{
040484af 948 bool cur_state;
5358901f 949 struct intel_dpll_hw_state hw_state;
040484af 950
9d82aa17
ED		 951 if (HAS_PCH_LPT(dev_priv->dev)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
953 return;
954 }
955
92b27b08 956 if (WARN (!pll,
46edb027 957 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 958 return;
ee7b9f93 959
5358901f 960 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 961 WARN(cur_state != state,
5358901f
DV		 962 "%s assertion failure (expected %s, current %s)\n",
963 pll->name, state_string(state), state_string(cur_state));
040484af 964}
040484af
JB		 965
966static void assert_fdi_tx(struct drm_i915_private *dev_priv,
967 enum pipe pipe, bool state)
968{
969 int reg;
970 u32 val;
971 bool cur_state;
ad80a810
PZ		 972 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
973 pipe);
040484af 974
affa9354
PZ		 975 if (HAS_DDI(dev_priv->dev)) {
976 /* DDI does not have a specific FDI_TX register */
ad80a810 977 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 978 val = I915_READ(reg);
ad80a810 979 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 980 } else {
981 reg = FDI_TX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_TX_ENABLE);
984 }
040484af
JB		 985 WARN(cur_state != state,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
991
992static void assert_fdi_rx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994{
995 int reg;
996 u32 val;
997 bool cur_state;
998
d63fa0dc
PZ		 999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1008
1009static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv->info->gen == 5)
1017 return;
1018
bf507ef7 1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1020 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1021 return;
1022
040484af
JB		 1023 reg = FDI_TX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026}
1027
55607e8a
DV		 1028void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
040484af
JB		 1030{
1031 int reg;
1032 u32 val;
55607e8a 1033 bool cur_state;
040484af
JB		 1034
1035 reg = FDI_RX_CTL(pipe);
1036 val = I915_READ(reg);
55607e8a
DV		 1037 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038 WARN(cur_state != state,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
040484af
JB		 1041}
1042
ea0760cf
JB		 1043static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1044 enum pipe pipe)
1045{
1046 int pp_reg, lvds_reg;
1047 u32 val;
1048 enum pipe panel_pipe = PIPE_A;
0de3b485 1049 bool locked = true;
ea0760cf
JB		 1050
1051 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052 pp_reg = PCH_PP_CONTROL;
1053 lvds_reg = PCH_LVDS;
1054 } else {
1055 pp_reg = PP_CONTROL;
1056 lvds_reg = LVDS;
1057 }
1058
1059 val = I915_READ(pp_reg);
1060 if (!(val & PANEL_POWER_ON) ||
1061 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1062 locked = false;
1063
1064 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065 panel_pipe = PIPE_B;
1066
1067 WARN(panel_pipe == pipe && locked,
1068 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1069 pipe_name(pipe));
ea0760cf
JB		 1070}
1071
93ce0ba6
JN		 1072static void assert_cursor(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool state)
1074{
1075 struct drm_device *dev = dev_priv->dev;
1076 bool cur_state;
1077
1078 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1079 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1080 else if (IS_845G(dev) || IS_I865G(dev))
1081 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1082 else
1083 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1084
1085 WARN(cur_state != state,
1086 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1087 pipe_name(pipe), state_string(state), state_string(cur_state));
1088}
1089#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1090#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1091
b840d907
JB		 1092void assert_pipe(struct drm_i915_private *dev_priv,
1093 enum pipe pipe, bool state)
b24e7179
JB		 1094{
1095 int reg;
1096 u32 val;
63d7bbe9 1097 bool cur_state;
702e7a56
PZ		 1098 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1099 pipe);
b24e7179 1100
8e636784
DV		 1101 /* if we need the pipe A quirk it must be always on */
1102 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1103 state = true;
1104
b97186f0
PZ		 1105 if (!intel_display_power_enabled(dev_priv->dev,
1106 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1107 cur_state = false;
1108 } else {
1109 reg = PIPECONF(cpu_transcoder);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPECONF_ENABLE);
1112 }
1113
63d7bbe9
JB		 1114 WARN(cur_state != state,
1115 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1116 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1117}
1118
931872fc
CW		 1119static void assert_plane(struct drm_i915_private *dev_priv,
1120 enum plane plane, bool state)
b24e7179
JB		 1121{
1122 int reg;
1123 u32 val;
931872fc 1124 bool cur_state;
b24e7179
JB		 1125
1126 reg = DSPCNTR(plane);
1127 val = I915_READ(reg);
931872fc
CW		 1128 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1129 WARN(cur_state != state,
1130 "plane %c assertion failure (expected %s, current %s)\n",
1131 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1132}
1133
931872fc
CW		 1134#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1135#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1136
b24e7179
JB		 1137static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1138 enum pipe pipe)
1139{
653e1026 1140 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1141 int reg, i;
1142 u32 val;
1143 int cur_pipe;
1144
653e1026
VS		 1145 /* Primary planes are fixed to pipes on gen4+ */
1146 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1147 reg = DSPCNTR(pipe);
1148 val = I915_READ(reg);
1149 WARN((val & DISPLAY_PLANE_ENABLE),
1150 "plane %c assertion failure, should be disabled but not\n",
1151 plane_name(pipe));
19ec1358 1152 return;
28c05794 1153 }
19ec1358 1154
b24e7179 1155 /* Need to check both planes against the pipe */
08e2a7de 1156 for_each_pipe(i) {
b24e7179
JB		 1157 reg = DSPCNTR(i);
1158 val = I915_READ(reg);
1159 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1160 DISPPLANE_SEL_PIPE_SHIFT;
1161 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1162 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1163 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1164 }
1165}
1166
19332d7a
JB		 1167static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1168 enum pipe pipe)
1169{
20674eef 1170 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1171 int reg, i;
1172 u32 val;
1173
20674eef
VS		 1174 if (IS_VALLEYVIEW(dev)) {
1175 for (i = 0; i < dev_priv->num_plane; i++) {
1176 reg = SPCNTR(pipe, i);
1177 val = I915_READ(reg);
1178 WARN((val & SP_ENABLE),
1179 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1180 sprite_name(pipe, i), pipe_name(pipe));
1181 }
1182 } else if (INTEL_INFO(dev)->gen >= 7) {
1183 reg = SPRCTL(pipe);
19332d7a 1184 val = I915_READ(reg);
20674eef 1185 WARN((val & SPRITE_ENABLE),
06da8da2 1186 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1187 plane_name(pipe), pipe_name(pipe));
1188 } else if (INTEL_INFO(dev)->gen >= 5) {
1189 reg = DVSCNTR(pipe);
19332d7a 1190 val = I915_READ(reg);
20674eef 1191 WARN((val & DVS_ENABLE),
06da8da2 1192 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1193 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1194 }
1195}
1196
92f2584a
JB		 1197static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1198{
1199 u32 val;
1200 bool enabled;
1201
9d82aa17
ED		 1202 if (HAS_PCH_LPT(dev_priv->dev)) {
1203 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1204 return;
1205 }
1206
92f2584a
JB		 1207 val = I915_READ(PCH_DREF_CONTROL);
1208 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1209 DREF_SUPERSPREAD_SOURCE_MASK));
1210 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1211}
1212
ab9412ba
DV		 1213static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1214 enum pipe pipe)
92f2584a
JB		 1215{
1216 int reg;
1217 u32 val;
1218 bool enabled;
1219
ab9412ba 1220 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1221 val = I915_READ(reg);
1222 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1223 WARN(enabled,
1224 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1225 pipe_name(pipe));
92f2584a
JB		 1226}
1227
4e634389
KP		 1228static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1229 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1230{
1231 if ((val & DP_PORT_EN) == 0)
1232 return false;
1233
1234 if (HAS_PCH_CPT(dev_priv->dev)) {
1235 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1236 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1237 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1238 return false;
1239 } else {
1240 if ((val & DP_PIPE_MASK) != (pipe << 30))
1241 return false;
1242 }
1243 return true;
1244}
1245
1519b995
KP		 1246static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, u32 val)
1248{
dc0fa718 1249 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1250 return false;
1251
1252 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1253 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1254 return false;
1255 } else {
dc0fa718 1256 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1257 return false;
1258 }
1259 return true;
1260}
1261
1262static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe, u32 val)
1264{
1265 if ((val & LVDS_PORT_EN) == 0)
1266 return false;
1267
1268 if (HAS_PCH_CPT(dev_priv->dev)) {
1269 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1270 return false;
1271 } else {
1272 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1273 return false;
1274 }
1275 return true;
1276}
1277
1278static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe, u32 val)
1280{
1281 if ((val & ADPA_DAC_ENABLE) == 0)
1282 return false;
1283 if (HAS_PCH_CPT(dev_priv->dev)) {
1284 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1285 return false;
1286 } else {
1287 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1288 return false;
1289 }
1290 return true;
1291}
1292
291906f1 1293static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1294 enum pipe pipe, int reg, u32 port_sel)
291906f1 1295{
47a05eca 1296 u32 val = I915_READ(reg);
4e634389 1297 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1298 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1299 reg, pipe_name(pipe));
de9a35ab 1300
75c5da27
DV		 1301 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1302 && (val & DP_PIPEB_SELECT),
de9a35ab 1303 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1304}
1305
1306static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, int reg)
1308{
47a05eca 1309 u32 val = I915_READ(reg);
b70ad586 1310 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1311 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1312 reg, pipe_name(pipe));
de9a35ab 1313
dc0fa718 1314 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1315 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1316 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1317}
1318
1319static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1320 enum pipe pipe)
1321{
1322 int reg;
1323 u32 val;
291906f1 1324
f0575e92
KP		 1325 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1326 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1327 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1328
1329 reg = PCH_ADPA;
1330 val = I915_READ(reg);
b70ad586 1331 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1332 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1333 pipe_name(pipe));
291906f1
JB		 1334
1335 reg = PCH_LVDS;
1336 val = I915_READ(reg);
b70ad586 1337 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1338 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1339 pipe_name(pipe));
291906f1 1340
e2debe91
PZ		 1341 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1342 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1343 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1344}
1345
426115cf 1346static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1347{
426115cf
DV		 1348 struct drm_device *dev = crtc->base.dev;
1349 struct drm_i915_private *dev_priv = dev->dev_private;
1350 int reg = DPLL(crtc->pipe);
1351 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1352
426115cf 1353 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1354
1355 /* No really, not for ILK+ */
1356 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1357
1358 /* PLL is protected by panel, make sure we can write it */
1359 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1360 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1361
426115cf
DV		 1362 I915_WRITE(reg, dpll);
1363 POSTING_READ(reg);
1364 udelay(150);
1365
1366 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1367 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1368
1369 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1370 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1371
1372 /* We do this three times for luck */
426115cf 1373 I915_WRITE(reg, dpll);
87442f73
DV		 1374 POSTING_READ(reg);
1375 udelay(150); /* wait for warmup */
426115cf 1376 I915_WRITE(reg, dpll);
87442f73
DV		 1377 POSTING_READ(reg);
1378 udelay(150); /* wait for warmup */
426115cf 1379 I915_WRITE(reg, dpll);
87442f73
DV		 1380 POSTING_READ(reg);
1381 udelay(150); /* wait for warmup */
1382}
1383
66e3d5c0 1384static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1385{
66e3d5c0
DV		 1386 struct drm_device *dev = crtc->base.dev;
1387 struct drm_i915_private *dev_priv = dev->dev_private;
1388 int reg = DPLL(crtc->pipe);
1389 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1390
66e3d5c0 1391 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1392
63d7bbe9 1393 /* No really, not for ILK+ */
87442f73 1394 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1395
1396 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1397 if (IS_MOBILE(dev) && !IS_I830(dev))
1398 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1399
66e3d5c0
DV		 1400 I915_WRITE(reg, dpll);
1401
1402 /* Wait for the clocks to stabilize. */
1403 POSTING_READ(reg);
1404 udelay(150);
1405
1406 if (INTEL_INFO(dev)->gen >= 4) {
1407 I915_WRITE(DPLL_MD(crtc->pipe),
1408 crtc->config.dpll_hw_state.dpll_md);
1409 } else {
1410 /* The pixel multiplier can only be updated once the
1411 * DPLL is enabled and the clocks are stable.
1412 *
1413 * So write it again.
1414 */
1415 I915_WRITE(reg, dpll);
1416 }
63d7bbe9
JB		 1417
1418 /* We do this three times for luck */
66e3d5c0 1419 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1420 POSTING_READ(reg);
1421 udelay(150); /* wait for warmup */
66e3d5c0 1422 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1423 POSTING_READ(reg);
1424 udelay(150); /* wait for warmup */
66e3d5c0 1425 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1426 POSTING_READ(reg);
1427 udelay(150); /* wait for warmup */
1428}
1429
1430/**
50b44a44 1431 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1432 * @dev_priv: i915 private structure
1433 * @pipe: pipe PLL to disable
1434 *
1435 * Disable the PLL for @pipe, making sure the pipe is off first.
1436 *
1437 * Note! This is for pre-ILK only.
1438 */
50b44a44 1439static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1440{
63d7bbe9
JB		 1441 /* Don't disable pipe A or pipe A PLLs if needed */
1442 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1443 return;
1444
1445 /* Make sure the pipe isn't still relying on us */
1446 assert_pipe_disabled(dev_priv, pipe);
1447
50b44a44
DV		 1448 I915_WRITE(DPLL(pipe), 0);
1449 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1450}
1451
89b667f8
JB		 1452void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1453{
1454 u32 port_mask;
1455
1456 if (!port)
1457 port_mask = DPLL_PORTB_READY_MASK;
1458 else
1459 port_mask = DPLL_PORTC_READY_MASK;
1460
1461 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1462 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1463 'B' + port, I915_READ(DPLL(0)));
1464}
1465
92f2584a 1466/**
e72f9fbf 1467 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1468 * @dev_priv: i915 private structure
1469 * @pipe: pipe PLL to enable
1470 *
1471 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1472 * drives the transcoder clock.
1473 */
e2b78267 1474static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1475{
e2b78267
DV		 1476 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1477 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1478
48da64a8 1479 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1480 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1481 if (WARN_ON(pll == NULL))
48da64a8
CW		 1482 return;
1483
1484 if (WARN_ON(pll->refcount == 0))
1485 return;
ee7b9f93 1486
46edb027
DV		 1487 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1488 pll->name, pll->active, pll->on,
e2b78267 1489 crtc->base.base.id);
92f2584a 1490
cdbd2316
DV		 1491 if (pll->active++) {
1492 WARN_ON(!pll->on);
e9d6944e 1493 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1494 return;
1495 }
f4a091c7 1496 WARN_ON(pll->on);
ee7b9f93 1497
46edb027 1498 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1499 pll->enable(dev_priv, pll);
ee7b9f93 1500 pll->on = true;
92f2584a
JB		 1501}
1502
e2b78267 1503static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1504{
e2b78267
DV		 1505 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1506 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1507
92f2584a
JB		 1508 /* PCH only available on ILK+ */
1509 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1510 if (WARN_ON(pll == NULL))
ee7b9f93 1511 return;
92f2584a 1512
48da64a8
CW		 1513 if (WARN_ON(pll->refcount == 0))
1514 return;
7a419866 1515
46edb027
DV		 1516 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1517 pll->name, pll->active, pll->on,
e2b78267 1518 crtc->base.base.id);
7a419866 1519
48da64a8 1520 if (WARN_ON(pll->active == 0)) {
e9d6944e 1521 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1522 return;
1523 }
1524
e9d6944e 1525 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1526 WARN_ON(!pll->on);
cdbd2316 1527 if (--pll->active)
7a419866 1528 return;
ee7b9f93 1529
46edb027 1530 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1531 pll->disable(dev_priv, pll);
ee7b9f93 1532 pll->on = false;
92f2584a
JB		 1533}
1534
b8a4f404
PZ		 1535static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1536 enum pipe pipe)
040484af 1537{
23670b32 1538 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1539 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1541 uint32_t reg, val, pipeconf_val;
040484af
JB		 1542
1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
1545
1546 /* Make sure PCH DPLL is enabled */
e72f9fbf 1547 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1548 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1549
1550 /* FDI must be feeding us bits for PCH ports */
1551 assert_fdi_tx_enabled(dev_priv, pipe);
1552 assert_fdi_rx_enabled(dev_priv, pipe);
1553
23670b32
DV		 1554 if (HAS_PCH_CPT(dev)) {
1555 /* Workaround: Set the timing override bit before enabling the
1556 * pch transcoder. */
1557 reg = TRANS_CHICKEN2(pipe);
1558 val = I915_READ(reg);
1559 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1560 I915_WRITE(reg, val);
59c859d6 1561 }
23670b32 1562
ab9412ba 1563 reg = PCH_TRANSCONF(pipe);
040484af 1564 val = I915_READ(reg);
5f7f726d 1565 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1566
1567 if (HAS_PCH_IBX(dev_priv->dev)) {
1568 /*
1569 * make the BPC in transcoder be consistent with
1570 * that in pipeconf reg.
1571 */
dfd07d72
DV		 1572 val &= ~PIPECONF_BPC_MASK;
1573 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1574 }
5f7f726d
PZ		 1575
1576 val &= ~TRANS_INTERLACE_MASK;
1577 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1578 if (HAS_PCH_IBX(dev_priv->dev) &&
1579 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1580 val |= TRANS_LEGACY_INTERLACED_ILK;
1581 else
1582 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1583 else
1584 val |= TRANS_PROGRESSIVE;
1585
040484af
JB		 1586 I915_WRITE(reg, val | TRANS_ENABLE);
1587 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1588 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1589}
1590
8fb033d7 1591static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1592 enum transcoder cpu_transcoder)
040484af 1593{
8fb033d7 1594 u32 val, pipeconf_val;
8fb033d7
PZ		 1595
1596 /* PCH only available on ILK+ */
1597 BUG_ON(dev_priv->info->gen < 5);
1598
8fb033d7 1599 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1600 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1601 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1602
223a6fdf
PZ		 1603 /* Workaround: set timing override bit. */
1604 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1605 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1606 I915_WRITE(_TRANSA_CHICKEN2, val);
1607
25f3ef11 1608 val = TRANS_ENABLE;
937bb610 1609 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1610
9a76b1c6
PZ		 1611 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1612 PIPECONF_INTERLACED_ILK)
a35f2679 1613 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1614 else
1615 val |= TRANS_PROGRESSIVE;
1616
ab9412ba
DV		 1617 I915_WRITE(LPT_TRANSCONF, val);
1618 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1619 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1620}
1621
b8a4f404
PZ		 1622static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1623 enum pipe pipe)
040484af 1624{
23670b32
DV		 1625 struct drm_device *dev = dev_priv->dev;
1626 uint32_t reg, val;
040484af
JB		 1627
1628 /* FDI relies on the transcoder */
1629 assert_fdi_tx_disabled(dev_priv, pipe);
1630 assert_fdi_rx_disabled(dev_priv, pipe);
1631
291906f1
JB		 1632 /* Ports must be off as well */
1633 assert_pch_ports_disabled(dev_priv, pipe);
1634
ab9412ba 1635 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1636 val = I915_READ(reg);
1637 val &= ~TRANS_ENABLE;
1638 I915_WRITE(reg, val);
1639 /* wait for PCH transcoder off, transcoder state */
1640 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1641 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1642
1643 if (!HAS_PCH_IBX(dev)) {
1644 /* Workaround: Clear the timing override chicken bit again. */
1645 reg = TRANS_CHICKEN2(pipe);
1646 val = I915_READ(reg);
1647 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1648 I915_WRITE(reg, val);
1649 }
040484af
JB		 1650}
1651
ab4d966c 1652static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1653{
8fb033d7
PZ		 1654 u32 val;
1655
ab9412ba 1656 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1657 val &= ~TRANS_ENABLE;
ab9412ba 1658 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1659 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1660 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1661 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1662
1663 /* Workaround: clear timing override bit. */
1664 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1665 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1666 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1667}
1668
b24e7179 1669/**
309cfea8 1670 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1671 * @dev_priv: i915 private structure
1672 * @pipe: pipe to enable
040484af 1673 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1674 *
1675 * Enable @pipe, making sure that various hardware specific requirements
1676 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1677 *
1678 * @pipe should be %PIPE_A or %PIPE_B.
1679 *
1680 * Will wait until the pipe is actually running (i.e. first vblank) before
1681 * returning.
1682 */
040484af 1683static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1684 bool pch_port, bool dsi)
b24e7179 1685{
702e7a56
PZ		 1686 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1687 pipe);
1a240d4d 1688 enum pipe pch_transcoder;
b24e7179
JB		 1689 int reg;
1690 u32 val;
1691
58c6eaa2 1692 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1693 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1694 assert_sprites_disabled(dev_priv, pipe);
1695
681e5811 1696 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1697 pch_transcoder = TRANSCODER_A;
1698 else
1699 pch_transcoder = pipe;
1700
b24e7179
JB		 1701 /*
1702 * A pipe without a PLL won't actually be able to drive bits from
1703 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1704 * need the check.
1705 */
1706 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1707 if (dsi)
1708 assert_dsi_pll_enabled(dev_priv);
1709 else
1710 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1711 else {
1712 if (pch_port) {
1713 /* if driving the PCH, we need FDI enabled */
cc391bbb 1714 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1715 assert_fdi_tx_pll_enabled(dev_priv,
1716 (enum pipe) cpu_transcoder);
040484af
JB		 1717 }
1718 /* FIXME: assert CPU port conditions for SNB+ */
1719 }
b24e7179 1720
702e7a56 1721 reg = PIPECONF(cpu_transcoder);
b24e7179 1722 val = I915_READ(reg);
00d70b15
CW		 1723 if (val & PIPECONF_ENABLE)
1724 return;
1725
1726 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1727 intel_wait_for_vblank(dev_priv->dev, pipe);
1728}
1729
1730/**
309cfea8 1731 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe to disable
1734 *
1735 * Disable @pipe, making sure that various hardware specific requirements
1736 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1737 *
1738 * @pipe should be %PIPE_A or %PIPE_B.
1739 *
1740 * Will wait until the pipe has shut down before returning.
1741 */
1742static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1743 enum pipe pipe)
1744{
702e7a56
PZ		 1745 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1746 pipe);
b24e7179
JB		 1747 int reg;
1748 u32 val;
1749
1750 /*
1751 * Make sure planes won't keep trying to pump pixels to us,
1752 * or we might hang the display.
1753 */
1754 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1755 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1756 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1757
1758 /* Don't disable pipe A or pipe A PLLs if needed */
1759 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1760 return;
1761
702e7a56 1762 reg = PIPECONF(cpu_transcoder);
b24e7179 1763 val = I915_READ(reg);
00d70b15
CW		 1764 if ((val & PIPECONF_ENABLE) == 0)
1765 return;
1766
1767 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1768 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1769}
1770
d74362c9
KP		 1771/*
1772 * Plane regs are double buffered, going from enabled->disabled needs a
1773 * trigger in order to latch. The display address reg provides this.
1774 */
6f1d69b0 1775void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1776 enum plane plane)
1777{
14f86147
DL		 1778 if (dev_priv->info->gen >= 4)
1779 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1780 else
1781 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1782}
1783
b24e7179
JB		 1784/**
1785 * intel_enable_plane - enable a display plane on a given pipe
1786 * @dev_priv: i915 private structure
1787 * @plane: plane to enable
1788 * @pipe: pipe being fed
1789 *
1790 * Enable @plane on @pipe, making sure that @pipe is running first.
1791 */
1792static void intel_enable_plane(struct drm_i915_private *dev_priv,
1793 enum plane plane, enum pipe pipe)
1794{
1795 int reg;
1796 u32 val;
1797
1798 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1799 assert_pipe_enabled(dev_priv, pipe);
1800
1801 reg = DSPCNTR(plane);
1802 val = I915_READ(reg);
00d70b15
CW		 1803 if (val & DISPLAY_PLANE_ENABLE)
1804 return;
1805
1806 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1807 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1808 intel_wait_for_vblank(dev_priv->dev, pipe);
1809}
1810
b24e7179
JB		 1811/**
1812 * intel_disable_plane - disable a display plane
1813 * @dev_priv: i915 private structure
1814 * @plane: plane to disable
1815 * @pipe: pipe consuming the data
1816 *
1817 * Disable @plane; should be an independent operation.
1818 */
1819static void intel_disable_plane(struct drm_i915_private *dev_priv,
1820 enum plane plane, enum pipe pipe)
1821{
1822 int reg;
1823 u32 val;
1824
1825 reg = DSPCNTR(plane);
1826 val = I915_READ(reg);
00d70b15
CW		 1827 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1828 return;
1829
1830 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1831 intel_flush_display_plane(dev_priv, plane);
1832 intel_wait_for_vblank(dev_priv->dev, pipe);
1833}
1834
693db184
CW		 1835static bool need_vtd_wa(struct drm_device *dev)
1836{
1837#ifdef CONFIG_INTEL_IOMMU
1838 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1839 return true;
1840#endif
1841 return false;
1842}
1843
127bd2ac 1844int
48b956c5 1845intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1846 struct drm_i915_gem_object *obj,
919926ae 1847 struct intel_ring_buffer *pipelined)
6b95a207 1848{
ce453d81 1849 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1850 u32 alignment;
1851 int ret;
1852
05394f39 1853 switch (obj->tiling_mode) {
6b95a207 1854 case I915_TILING_NONE:
534843da
CW		 1855 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1856 alignment = 128 * 1024;
a6c45cf0 1857 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1858 alignment = 4 * 1024;
1859 else
1860 alignment = 64 * 1024;
6b95a207
KH		 1861 break;
1862 case I915_TILING_X:
1863 /* pin() will align the object as required by fence */
1864 alignment = 0;
1865 break;
1866 case I915_TILING_Y:
8bb6e959
DV		 1867 /* Despite that we check this in framebuffer_init userspace can
1868 * screw us over and change the tiling after the fact. Only
1869 * pinned buffers can't change their tiling. */
1870 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1871 return -EINVAL;
1872 default:
1873 BUG();
1874 }
1875
693db184
CW		 1876 /* Note that the w/a also requires 64 PTE of padding following the
1877 * bo. We currently fill all unused PTE with the shadow page and so
1878 * we should always have valid PTE following the scanout preventing
1879 * the VT-d warning.
1880 */
1881 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1882 alignment = 256 * 1024;
1883
ce453d81 1884 dev_priv->mm.interruptible = false;
2da3b9b9 1885 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1886 if (ret)
ce453d81 1887 goto err_interruptible;
6b95a207
KH		 1888
1889 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1890 * fence, whereas 965+ only requires a fence if using
1891 * framebuffer compression. For simplicity, we always install
1892 * a fence as the cost is not that onerous.
1893 */
06d98131 1894 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1895 if (ret)
1896 goto err_unpin;
1690e1eb 1897
9a5a53b3 1898 i915_gem_object_pin_fence(obj);
6b95a207 1899
ce453d81 1900 dev_priv->mm.interruptible = true;
6b95a207 1901 return 0;
48b956c5
CW		 1902
1903err_unpin:
cc98b413 1904 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1905err_interruptible:
1906 dev_priv->mm.interruptible = true;
48b956c5 1907 return ret;
6b95a207
KH		 1908}
1909
1690e1eb
CW		 1910void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1911{
1912 i915_gem_object_unpin_fence(obj);
cc98b413 1913 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1914}
1915
c2c75131
DV		 1916/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1917 * is assumed to be a power-of-two. */
bc752862
CW		 1918unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1919 unsigned int tiling_mode,
1920 unsigned int cpp,
1921 unsigned int pitch)
c2c75131 1922{
bc752862
CW		 1923 if (tiling_mode != I915_TILING_NONE) {
1924 unsigned int tile_rows, tiles;
c2c75131 1925
bc752862
CW		 1926 tile_rows = *y / 8;
1927 *y %= 8;
c2c75131 1928
bc752862
CW		 1929 tiles = *x / (512/cpp);
1930 *x %= 512/cpp;
1931
1932 return tile_rows * pitch * 8 + tiles * 4096;
1933 } else {
1934 unsigned int offset;
1935
1936 offset = *y * pitch + *x * cpp;
1937 *y = 0;
1938 *x = (offset & 4095) / cpp;
1939 return offset & -4096;
1940 }
c2c75131
DV		 1941}
1942
17638cd6
JB		 1943static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1944 int x, int y)
81255565
JB		 1945{
1946 struct drm_device *dev = crtc->dev;
1947 struct drm_i915_private *dev_priv = dev->dev_private;
1948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1949 struct intel_framebuffer *intel_fb;
05394f39 1950 struct drm_i915_gem_object *obj;
81255565 1951 int plane = intel_crtc->plane;
e506a0c6 1952 unsigned long linear_offset;
81255565 1953 u32 dspcntr;
5eddb70b 1954 u32 reg;
81255565
JB		 1955
1956 switch (plane) {
1957 case 0:
1958 case 1:
1959 break;
1960 default:
84f44ce7 1961 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1962 return -EINVAL;
1963 }
1964
1965 intel_fb = to_intel_framebuffer(fb);
1966 obj = intel_fb->obj;
81255565 1967
5eddb70b
CW		 1968 reg = DSPCNTR(plane);
1969 dspcntr = I915_READ(reg);
81255565
JB		 1970 /* Mask out pixel format bits in case we change it */
1971 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1972 switch (fb->pixel_format) {
1973 case DRM_FORMAT_C8:
81255565
JB		 1974 dspcntr |= DISPPLANE_8BPP;
1975 break;
57779d06
VS		 1976 case DRM_FORMAT_XRGB1555:
1977 case DRM_FORMAT_ARGB1555:
1978 dspcntr |= DISPPLANE_BGRX555;
81255565 1979 break;
57779d06
VS		 1980 case DRM_FORMAT_RGB565:
1981 dspcntr |= DISPPLANE_BGRX565;
1982 break;
1983 case DRM_FORMAT_XRGB8888:
1984 case DRM_FORMAT_ARGB8888:
1985 dspcntr |= DISPPLANE_BGRX888;
1986 break;
1987 case DRM_FORMAT_XBGR8888:
1988 case DRM_FORMAT_ABGR8888:
1989 dspcntr |= DISPPLANE_RGBX888;
1990 break;
1991 case DRM_FORMAT_XRGB2101010:
1992 case DRM_FORMAT_ARGB2101010:
1993 dspcntr |= DISPPLANE_BGRX101010;
1994 break;
1995 case DRM_FORMAT_XBGR2101010:
1996 case DRM_FORMAT_ABGR2101010:
1997 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1998 break;
1999 default:
baba133a 2000 BUG();
81255565 2001 }
57779d06 2002
a6c45cf0 2003 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2004 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2005 dspcntr |= DISPPLANE_TILED;
2006 else
2007 dspcntr &= ~DISPPLANE_TILED;
2008 }
2009
de1aa629
VS		 2010 if (IS_G4X(dev))
2011 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2012
5eddb70b 2013 I915_WRITE(reg, dspcntr);
81255565 2014
e506a0c6 2015 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2016
c2c75131
DV		 2017 if (INTEL_INFO(dev)->gen >= 4) {
2018 intel_crtc->dspaddr_offset =
bc752862
CW		 2019 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2020 fb->bits_per_pixel / 8,
2021 fb->pitches[0]);
c2c75131
DV		 2022 linear_offset -= intel_crtc->dspaddr_offset;
2023 } else {
e506a0c6 2024 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2025 }
e506a0c6 2026
f343c5f6
BW		 2027 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2028 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2029 fb->pitches[0]);
01f2c773 2030 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2031 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2032 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2033 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2034 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2035 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2036 } else
f343c5f6 2037 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2038 POSTING_READ(reg);
81255565 2039
17638cd6
JB		 2040 return 0;
2041}
2042
2043static int ironlake_update_plane(struct drm_crtc *crtc,
2044 struct drm_framebuffer *fb, int x, int y)
2045{
2046 struct drm_device *dev = crtc->dev;
2047 struct drm_i915_private *dev_priv = dev->dev_private;
2048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2049 struct intel_framebuffer *intel_fb;
2050 struct drm_i915_gem_object *obj;
2051 int plane = intel_crtc->plane;
e506a0c6 2052 unsigned long linear_offset;
17638cd6
JB		 2053 u32 dspcntr;
2054 u32 reg;
2055
2056 switch (plane) {
2057 case 0:
2058 case 1:
27f8227b 2059 case 2:
17638cd6
JB		 2060 break;
2061 default:
84f44ce7 2062 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2063 return -EINVAL;
2064 }
2065
2066 intel_fb = to_intel_framebuffer(fb);
2067 obj = intel_fb->obj;
2068
2069 reg = DSPCNTR(plane);
2070 dspcntr = I915_READ(reg);
2071 /* Mask out pixel format bits in case we change it */
2072 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2073 switch (fb->pixel_format) {
2074 case DRM_FORMAT_C8:
17638cd6
JB		 2075 dspcntr |= DISPPLANE_8BPP;
2076 break;
57779d06
VS		 2077 case DRM_FORMAT_RGB565:
2078 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2079 break;
57779d06
VS		 2080 case DRM_FORMAT_XRGB8888:
2081 case DRM_FORMAT_ARGB8888:
2082 dspcntr |= DISPPLANE_BGRX888;
2083 break;
2084 case DRM_FORMAT_XBGR8888:
2085 case DRM_FORMAT_ABGR8888:
2086 dspcntr |= DISPPLANE_RGBX888;
2087 break;
2088 case DRM_FORMAT_XRGB2101010:
2089 case DRM_FORMAT_ARGB2101010:
2090 dspcntr |= DISPPLANE_BGRX101010;
2091 break;
2092 case DRM_FORMAT_XBGR2101010:
2093 case DRM_FORMAT_ABGR2101010:
2094 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2095 break;
2096 default:
baba133a 2097 BUG();
17638cd6
JB		 2098 }
2099
2100 if (obj->tiling_mode != I915_TILING_NONE)
2101 dspcntr |= DISPPLANE_TILED;
2102 else
2103 dspcntr &= ~DISPPLANE_TILED;
2104
1f5d76db
PZ		 2105 if (IS_HASWELL(dev))
2106 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2107 else
2108 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2109
2110 I915_WRITE(reg, dspcntr);
2111
e506a0c6 2112 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2113 intel_crtc->dspaddr_offset =
bc752862
CW		 2114 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2115 fb->bits_per_pixel / 8,
2116 fb->pitches[0]);
c2c75131 2117 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2118
f343c5f6
BW		 2119 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2120 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2121 fb->pitches[0]);
01f2c773 2122 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2123 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2124 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2125 if (IS_HASWELL(dev)) {
2126 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2127 } else {
2128 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2129 I915_WRITE(DSPLINOFF(plane), linear_offset);
2130 }
17638cd6
JB		 2131 POSTING_READ(reg);
2132
2133 return 0;
2134}
2135
2136/* Assume fb object is pinned & idle & fenced and just update base pointers */
2137static int
2138intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2139 int x, int y, enum mode_set_atomic state)
2140{
2141 struct drm_device *dev = crtc->dev;
2142 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2143
6b8e6ed0
CW		 2144 if (dev_priv->display.disable_fbc)
2145 dev_priv->display.disable_fbc(dev);
3dec0095 2146 intel_increase_pllclock(crtc);
81255565 2147
6b8e6ed0 2148 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2149}
2150
96a02917
VS		 2151void intel_display_handle_reset(struct drm_device *dev)
2152{
2153 struct drm_i915_private *dev_priv = dev->dev_private;
2154 struct drm_crtc *crtc;
2155
2156 /*
2157 * Flips in the rings have been nuked by the reset,
2158 * so complete all pending flips so that user space
2159 * will get its events and not get stuck.
2160 *
2161 * Also update the base address of all primary
2162 * planes to the the last fb to make sure we're
2163 * showing the correct fb after a reset.
2164 *
2165 * Need to make two loops over the crtcs so that we
2166 * don't try to grab a crtc mutex before the
2167 * pending_flip_queue really got woken up.
2168 */
2169
2170 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2172 enum plane plane = intel_crtc->plane;
2173
2174 intel_prepare_page_flip(dev, plane);
2175 intel_finish_page_flip_plane(dev, plane);
2176 }
2177
2178 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2180
2181 mutex_lock(&crtc->mutex);
2182 if (intel_crtc->active)
2183 dev_priv->display.update_plane(crtc, crtc->fb,
2184 crtc->x, crtc->y);
2185 mutex_unlock(&crtc->mutex);
2186 }
2187}
2188
14667a4b
CW		 2189static int
2190intel_finish_fb(struct drm_framebuffer *old_fb)
2191{
2192 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2193 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2194 bool was_interruptible = dev_priv->mm.interruptible;
2195 int ret;
2196
14667a4b
CW		 2197 /* Big Hammer, we also need to ensure that any pending
2198 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2199 * current scanout is retired before unpinning the old
2200 * framebuffer.
2201 *
2202 * This should only fail upon a hung GPU, in which case we
2203 * can safely continue.
2204 */
2205 dev_priv->mm.interruptible = false;
2206 ret = i915_gem_object_finish_gpu(obj);
2207 dev_priv->mm.interruptible = was_interruptible;
2208
2209 return ret;
2210}
2211
198598d0
VS		 2212static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2213{
2214 struct drm_device *dev = crtc->dev;
2215 struct drm_i915_master_private *master_priv;
2216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2217
2218 if (!dev->primary->master)
2219 return;
2220
2221 master_priv = dev->primary->master->driver_priv;
2222 if (!master_priv->sarea_priv)
2223 return;
2224
2225 switch (intel_crtc->pipe) {
2226 case 0:
2227 master_priv->sarea_priv->pipeA_x = x;
2228 master_priv->sarea_priv->pipeA_y = y;
2229 break;
2230 case 1:
2231 master_priv->sarea_priv->pipeB_x = x;
2232 master_priv->sarea_priv->pipeB_y = y;
2233 break;
2234 default:
2235 break;
2236 }
2237}
2238
5c3b82e2 2239static int
3c4fdcfb 2240intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2241 struct drm_framebuffer *fb)
79e53945
JB		 2242{
2243 struct drm_device *dev = crtc->dev;
6b8e6ed0 2244 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2246 struct drm_framebuffer *old_fb;
5c3b82e2 2247 int ret;
79e53945
JB		 2248
2249 /* no fb bound */
94352cf9 2250 if (!fb) {
a5071c2f 2251 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2252 return 0;
2253 }
2254
7eb552ae 2255 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2256 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2257 plane_name(intel_crtc->plane),
2258 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2259 return -EINVAL;
79e53945
JB		 2260 }
2261
5c3b82e2 2262 mutex_lock(&dev->struct_mutex);
265db958 2263 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2264 to_intel_framebuffer(fb)->obj,
919926ae 2265 NULL);
5c3b82e2
CW		 2266 if (ret != 0) {
2267 mutex_unlock(&dev->struct_mutex);
a5071c2f 2268 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2269 return ret;
2270 }
79e53945 2271
4d6a3e63
JB		 2272 /* Update pipe size and adjust fitter if needed */
2273 if (i915_fastboot) {
2274 I915_WRITE(PIPESRC(intel_crtc->pipe),
2275 ((crtc->mode.hdisplay - 1) << 16) |
2276 (crtc->mode.vdisplay - 1));
2277 if (!intel_crtc->config.pch_pfit.size &&
2278 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2279 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2280 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2281 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2282 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2283 }
2284 }
2285
94352cf9 2286 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2287 if (ret) {
94352cf9 2288 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2289 mutex_unlock(&dev->struct_mutex);
a5071c2f 2290 DRM_ERROR("failed to update base address\n");
4e6cfefc 2291 return ret;
79e53945 2292 }
3c4fdcfb 2293
94352cf9
DV		 2294 old_fb = crtc->fb;
2295 crtc->fb = fb;
6c4c86f5
DV		 2296 crtc->x = x;
2297 crtc->y = y;
94352cf9 2298
b7f1de28 2299 if (old_fb) {
d7697eea
DV		 2300 if (intel_crtc->active && old_fb != fb)
2301 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2302 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2303 }
652c393a 2304
6b8e6ed0 2305 intel_update_fbc(dev);
4906557e 2306 intel_edp_psr_update(dev);
5c3b82e2 2307 mutex_unlock(&dev->struct_mutex);
79e53945 2308
198598d0 2309 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2310
2311 return 0;
79e53945
JB		 2312}
2313
5e84e1a4
ZW		 2314static void intel_fdi_normal_train(struct drm_crtc *crtc)
2315{
2316 struct drm_device *dev = crtc->dev;
2317 struct drm_i915_private *dev_priv = dev->dev_private;
2318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2319 int pipe = intel_crtc->pipe;
2320 u32 reg, temp;
2321
2322 /* enable normal train */
2323 reg = FDI_TX_CTL(pipe);
2324 temp = I915_READ(reg);
61e499bf 2325 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2326 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2327 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2328 } else {
2329 temp &= ~FDI_LINK_TRAIN_NONE;
2330 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2331 }
5e84e1a4
ZW		 2332 I915_WRITE(reg, temp);
2333
2334 reg = FDI_RX_CTL(pipe);
2335 temp = I915_READ(reg);
2336 if (HAS_PCH_CPT(dev)) {
2337 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2338 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2339 } else {
2340 temp &= ~FDI_LINK_TRAIN_NONE;
2341 temp |= FDI_LINK_TRAIN_NONE;
2342 }
2343 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2344
2345 /* wait one idle pattern time */
2346 POSTING_READ(reg);
2347 udelay(1000);
357555c0
JB		 2348
2349 /* IVB wants error correction enabled */
2350 if (IS_IVYBRIDGE(dev))
2351 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2352 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2353}
2354
1e833f40
DV		 2355static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2356{
2357 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2358}
2359
01a415fd
DV		 2360static void ivb_modeset_global_resources(struct drm_device *dev)
2361{
2362 struct drm_i915_private *dev_priv = dev->dev_private;
2363 struct intel_crtc *pipe_B_crtc =
2364 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2365 struct intel_crtc *pipe_C_crtc =
2366 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2367 uint32_t temp;
2368
1e833f40
DV		 2369 /*
2370 * When everything is off disable fdi C so that we could enable fdi B
2371 * with all lanes. Note that we don't care about enabled pipes without
2372 * an enabled pch encoder.
2373 */
2374 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2375 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2376 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2377 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2378
2379 temp = I915_READ(SOUTH_CHICKEN1);
2380 temp &= ~FDI_BC_BIFURCATION_SELECT;
2381 DRM_DEBUG_KMS("disabling fdi C rx\n");
2382 I915_WRITE(SOUTH_CHICKEN1, temp);
2383 }
2384}
2385
8db9d77b
ZW		 2386/* The FDI link training functions for ILK/Ibexpeak. */
2387static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2388{
2389 struct drm_device *dev = crtc->dev;
2390 struct drm_i915_private *dev_priv = dev->dev_private;
2391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2392 int pipe = intel_crtc->pipe;
0fc932b8 2393 int plane = intel_crtc->plane;
5eddb70b 2394 u32 reg, temp, tries;
8db9d77b 2395
0fc932b8
JB		 2396 /* FDI needs bits from pipe & plane first */
2397 assert_pipe_enabled(dev_priv, pipe);
2398 assert_plane_enabled(dev_priv, plane);
2399
e1a44743
AJ		 2400 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2401 for train result */
5eddb70b
CW		 2402 reg = FDI_RX_IMR(pipe);
2403 temp = I915_READ(reg);
e1a44743
AJ		 2404 temp &= ~FDI_RX_SYMBOL_LOCK;
2405 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2406 I915_WRITE(reg, temp);
2407 I915_READ(reg);
e1a44743
AJ		 2408 udelay(150);
2409
8db9d77b 2410 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2411 reg = FDI_TX_CTL(pipe);
2412 temp = I915_READ(reg);
627eb5a3
DV		 2413 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2414 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2415 temp &= ~FDI_LINK_TRAIN_NONE;
2416 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2417 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2418
5eddb70b
CW		 2419 reg = FDI_RX_CTL(pipe);
2420 temp = I915_READ(reg);
8db9d77b
ZW		 2421 temp &= ~FDI_LINK_TRAIN_NONE;
2422 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2423 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2424
2425 POSTING_READ(reg);
8db9d77b
ZW		 2426 udelay(150);
2427
5b2adf89 2428 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2429 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2430 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2431 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2432
5eddb70b 2433 reg = FDI_RX_IIR(pipe);
e1a44743 2434 for (tries = 0; tries < 5; tries++) {
5eddb70b 2435 temp = I915_READ(reg);
8db9d77b
ZW		 2436 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2437
2438 if ((temp & FDI_RX_BIT_LOCK)) {
2439 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2440 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2441 break;
2442 }
8db9d77b 2443 }
e1a44743 2444 if (tries == 5)
5eddb70b 2445 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2446
2447 /* Train 2 */
5eddb70b
CW		 2448 reg = FDI_TX_CTL(pipe);
2449 temp = I915_READ(reg);
8db9d77b
ZW		 2450 temp &= ~FDI_LINK_TRAIN_NONE;
2451 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2452 I915_WRITE(reg, temp);
8db9d77b 2453
5eddb70b
CW		 2454 reg = FDI_RX_CTL(pipe);
2455 temp = I915_READ(reg);
8db9d77b
ZW		 2456 temp &= ~FDI_LINK_TRAIN_NONE;
2457 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2458 I915_WRITE(reg, temp);
8db9d77b 2459
5eddb70b
CW		 2460 POSTING_READ(reg);
2461 udelay(150);
8db9d77b 2462
5eddb70b 2463 reg = FDI_RX_IIR(pipe);
e1a44743 2464 for (tries = 0; tries < 5; tries++) {
5eddb70b 2465 temp = I915_READ(reg);
8db9d77b
ZW		 2466 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2467
2468 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2469 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2470 DRM_DEBUG_KMS("FDI train 2 done.\n");
2471 break;
2472 }
8db9d77b 2473 }
e1a44743 2474 if (tries == 5)
5eddb70b 2475 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2476
2477 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2478
8db9d77b
ZW		 2479}
2480
0206e353 2481static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2482 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2483 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2484 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2485 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2486};
2487
2488/* The FDI link training functions for SNB/Cougarpoint. */
2489static void gen6_fdi_link_train(struct drm_crtc *crtc)
2490{
2491 struct drm_device *dev = crtc->dev;
2492 struct drm_i915_private *dev_priv = dev->dev_private;
2493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2494 int pipe = intel_crtc->pipe;
fa37d39e 2495 u32 reg, temp, i, retry;
8db9d77b 2496
e1a44743
AJ		 2497 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2498 for train result */
5eddb70b
CW		 2499 reg = FDI_RX_IMR(pipe);
2500 temp = I915_READ(reg);
e1a44743
AJ		 2501 temp &= ~FDI_RX_SYMBOL_LOCK;
2502 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2503 I915_WRITE(reg, temp);
2504
2505 POSTING_READ(reg);
e1a44743
AJ		 2506 udelay(150);
2507
8db9d77b 2508 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2509 reg = FDI_TX_CTL(pipe);
2510 temp = I915_READ(reg);
627eb5a3
DV		 2511 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2512 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_1;
2515 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516 /* SNB-B */
2517 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2518 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2519
d74cf324
DV		 2520 I915_WRITE(FDI_RX_MISC(pipe),
2521 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2522
5eddb70b
CW		 2523 reg = FDI_RX_CTL(pipe);
2524 temp = I915_READ(reg);
8db9d77b
ZW		 2525 if (HAS_PCH_CPT(dev)) {
2526 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2527 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2528 } else {
2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_1;
2531 }
5eddb70b
CW		 2532 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2533
2534 POSTING_READ(reg);
8db9d77b
ZW		 2535 udelay(150);
2536
0206e353 2537 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2538 reg = FDI_TX_CTL(pipe);
2539 temp = I915_READ(reg);
8db9d77b
ZW		 2540 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2541 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2542 I915_WRITE(reg, temp);
2543
2544 POSTING_READ(reg);
8db9d77b
ZW		 2545 udelay(500);
2546
fa37d39e
SP		 2547 for (retry = 0; retry < 5; retry++) {
2548 reg = FDI_RX_IIR(pipe);
2549 temp = I915_READ(reg);
2550 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2551 if (temp & FDI_RX_BIT_LOCK) {
2552 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2553 DRM_DEBUG_KMS("FDI train 1 done.\n");
2554 break;
2555 }
2556 udelay(50);
8db9d77b 2557 }
fa37d39e
SP		 2558 if (retry < 5)
2559 break;
8db9d77b
ZW		 2560 }
2561 if (i == 4)
5eddb70b 2562 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2563
2564 /* Train 2 */
5eddb70b
CW		 2565 reg = FDI_TX_CTL(pipe);
2566 temp = I915_READ(reg);
8db9d77b
ZW		 2567 temp &= ~FDI_LINK_TRAIN_NONE;
2568 temp |= FDI_LINK_TRAIN_PATTERN_2;
2569 if (IS_GEN6(dev)) {
2570 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2571 /* SNB-B */
2572 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2573 }
5eddb70b 2574 I915_WRITE(reg, temp);
8db9d77b 2575
5eddb70b
CW		 2576 reg = FDI_RX_CTL(pipe);
2577 temp = I915_READ(reg);
8db9d77b
ZW		 2578 if (HAS_PCH_CPT(dev)) {
2579 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2580 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2581 } else {
2582 temp &= ~FDI_LINK_TRAIN_NONE;
2583 temp |= FDI_LINK_TRAIN_PATTERN_2;
2584 }
5eddb70b
CW		 2585 I915_WRITE(reg, temp);
2586
2587 POSTING_READ(reg);
8db9d77b
ZW		 2588 udelay(150);
2589
0206e353 2590 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2591 reg = FDI_TX_CTL(pipe);
2592 temp = I915_READ(reg);
8db9d77b
ZW		 2593 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2594 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2595 I915_WRITE(reg, temp);
2596
2597 POSTING_READ(reg);
8db9d77b
ZW		 2598 udelay(500);
2599
fa37d39e
SP		 2600 for (retry = 0; retry < 5; retry++) {
2601 reg = FDI_RX_IIR(pipe);
2602 temp = I915_READ(reg);
2603 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2604 if (temp & FDI_RX_SYMBOL_LOCK) {
2605 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2606 DRM_DEBUG_KMS("FDI train 2 done.\n");
2607 break;
2608 }
2609 udelay(50);
8db9d77b 2610 }
fa37d39e
SP		 2611 if (retry < 5)
2612 break;
8db9d77b
ZW		 2613 }
2614 if (i == 4)
5eddb70b 2615 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2616
2617 DRM_DEBUG_KMS("FDI train done.\n");
2618}
2619
357555c0
JB		 2620/* Manual link training for Ivy Bridge A0 parts */
2621static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2622{
2623 struct drm_device *dev = crtc->dev;
2624 struct drm_i915_private *dev_priv = dev->dev_private;
2625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2626 int pipe = intel_crtc->pipe;
139ccd3f 2627 u32 reg, temp, i, j;
357555c0
JB		 2628
2629 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2630 for train result */
2631 reg = FDI_RX_IMR(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_RX_SYMBOL_LOCK;
2634 temp &= ~FDI_RX_BIT_LOCK;
2635 I915_WRITE(reg, temp);
2636
2637 POSTING_READ(reg);
2638 udelay(150);
2639
01a415fd
DV		 2640 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2641 I915_READ(FDI_RX_IIR(pipe)));
2642
139ccd3f
JB		 2643 /* Try each vswing and preemphasis setting twice before moving on */
2644 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2645 /* disable first in case we need to retry */
2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2649 temp &= ~FDI_TX_ENABLE;
2650 I915_WRITE(reg, temp);
357555c0 2651
139ccd3f
JB		 2652 reg = FDI_RX_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~FDI_LINK_TRAIN_AUTO;
2655 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2656 temp &= ~FDI_RX_ENABLE;
2657 I915_WRITE(reg, temp);
357555c0 2658
139ccd3f 2659 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2660 reg = FDI_TX_CTL(pipe);
2661 temp = I915_READ(reg);
139ccd3f
JB		 2662 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2663 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2664 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2666 temp |= snb_b_fdi_train_param[j/2];
2667 temp |= FDI_COMPOSITE_SYNC;
2668 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2669
139ccd3f
JB		 2670 I915_WRITE(FDI_RX_MISC(pipe),
2671 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2672
139ccd3f 2673 reg = FDI_RX_CTL(pipe);
357555c0 2674 temp = I915_READ(reg);
139ccd3f
JB		 2675 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2676 temp |= FDI_COMPOSITE_SYNC;
2677 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2678
139ccd3f
JB		 2679 POSTING_READ(reg);
2680 udelay(1); /* should be 0.5us */
357555c0 2681
139ccd3f
JB		 2682 for (i = 0; i < 4; i++) {
2683 reg = FDI_RX_IIR(pipe);
2684 temp = I915_READ(reg);
2685 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2686
139ccd3f
JB		 2687 if (temp & FDI_RX_BIT_LOCK ||
2688 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2689 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2690 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2691 i);
2692 break;
2693 }
2694 udelay(1); /* should be 0.5us */
2695 }
2696 if (i == 4) {
2697 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2698 continue;
2699 }
357555c0 2700
139ccd3f 2701 /* Train 2 */
357555c0
JB		 2702 reg = FDI_TX_CTL(pipe);
2703 temp = I915_READ(reg);
139ccd3f
JB		 2704 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2705 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2706 I915_WRITE(reg, temp);
2707
2708 reg = FDI_RX_CTL(pipe);
2709 temp = I915_READ(reg);
2710 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2711 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2712 I915_WRITE(reg, temp);
2713
2714 POSTING_READ(reg);
139ccd3f 2715 udelay(2); /* should be 1.5us */
357555c0 2716
139ccd3f
JB		 2717 for (i = 0; i < 4; i++) {
2718 reg = FDI_RX_IIR(pipe);
2719 temp = I915_READ(reg);
2720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2721
139ccd3f
JB		 2722 if (temp & FDI_RX_SYMBOL_LOCK ||
2723 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2724 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2725 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2726 i);
2727 goto train_done;
2728 }
2729 udelay(2); /* should be 1.5us */
357555c0 2730 }
139ccd3f
JB		 2731 if (i == 4)
2732 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2733 }
357555c0 2734
139ccd3f 2735train_done:
357555c0
JB		 2736 DRM_DEBUG_KMS("FDI train done.\n");
2737}
2738
88cefb6c 2739static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2740{
88cefb6c 2741 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2742 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2743 int pipe = intel_crtc->pipe;
5eddb70b 2744 u32 reg, temp;
79e53945 2745
c64e311e 2746
c98e9dcf 2747 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2748 reg = FDI_RX_CTL(pipe);
2749 temp = I915_READ(reg);
627eb5a3
DV		 2750 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2751 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2752 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2753 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2754
2755 POSTING_READ(reg);
c98e9dcf
JB		 2756 udelay(200);
2757
2758 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2759 temp = I915_READ(reg);
2760 I915_WRITE(reg, temp | FDI_PCDCLK);
2761
2762 POSTING_READ(reg);
c98e9dcf
JB		 2763 udelay(200);
2764
20749730
PZ		 2765 /* Enable CPU FDI TX PLL, always on for Ironlake */
2766 reg = FDI_TX_CTL(pipe);
2767 temp = I915_READ(reg);
2768 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2769 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2770
20749730
PZ		 2771 POSTING_READ(reg);
2772 udelay(100);
6be4a607 2773 }
0e23b99d
JB		 2774}
2775
88cefb6c
DV		 2776static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2777{
2778 struct drm_device *dev = intel_crtc->base.dev;
2779 struct drm_i915_private *dev_priv = dev->dev_private;
2780 int pipe = intel_crtc->pipe;
2781 u32 reg, temp;
2782
2783 /* Switch from PCDclk to Rawclk */
2784 reg = FDI_RX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2787
2788 /* Disable CPU FDI TX PLL */
2789 reg = FDI_TX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2792
2793 POSTING_READ(reg);
2794 udelay(100);
2795
2796 reg = FDI_RX_CTL(pipe);
2797 temp = I915_READ(reg);
2798 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2799
2800 /* Wait for the clocks to turn off. */
2801 POSTING_READ(reg);
2802 udelay(100);
2803}
2804
0fc932b8
JB		 2805static void ironlake_fdi_disable(struct drm_crtc *crtc)
2806{
2807 struct drm_device *dev = crtc->dev;
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2810 int pipe = intel_crtc->pipe;
2811 u32 reg, temp;
2812
2813 /* disable CPU FDI tx and PCH FDI rx */
2814 reg = FDI_TX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2817 POSTING_READ(reg);
2818
2819 reg = FDI_RX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 temp &= ~(0x7 << 16);
dfd07d72 2822 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2823 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2824
2825 POSTING_READ(reg);
2826 udelay(100);
2827
2828 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2829 if (HAS_PCH_IBX(dev)) {
2830 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2831 }
0fc932b8
JB		 2832
2833 /* still set train pattern 1 */
2834 reg = FDI_TX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~FDI_LINK_TRAIN_NONE;
2837 temp |= FDI_LINK_TRAIN_PATTERN_1;
2838 I915_WRITE(reg, temp);
2839
2840 reg = FDI_RX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 if (HAS_PCH_CPT(dev)) {
2843 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2845 } else {
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848 }
2849 /* BPC in FDI rx is consistent with that in PIPECONF */
2850 temp &= ~(0x07 << 16);
dfd07d72 2851 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2852 I915_WRITE(reg, temp);
2853
2854 POSTING_READ(reg);
2855 udelay(100);
2856}
2857
5bb61643
CW		 2858static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2859{
2860 struct drm_device *dev = crtc->dev;
2861 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2863 unsigned long flags;
2864 bool pending;
2865
10d83730
VS		 2866 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2867 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2868 return false;
2869
2870 spin_lock_irqsave(&dev->event_lock, flags);
2871 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2872 spin_unlock_irqrestore(&dev->event_lock, flags);
2873
2874 return pending;
2875}
2876
e6c3a2a6
CW		 2877static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2878{
0f91128d 2879 struct drm_device *dev = crtc->dev;
5bb61643 2880 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2881
2882 if (crtc->fb == NULL)
2883 return;
2884
2c10d571
DV		 2885 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2886
5bb61643
CW		 2887 wait_event(dev_priv->pending_flip_queue,
2888 !intel_crtc_has_pending_flip(crtc));
2889
0f91128d
CW		 2890 mutex_lock(&dev->struct_mutex);
2891 intel_finish_fb(crtc->fb);
2892 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2893}
2894
e615efe4
ED		 2895/* Program iCLKIP clock to the desired frequency */
2896static void lpt_program_iclkip(struct drm_crtc *crtc)
2897{
2898 struct drm_device *dev = crtc->dev;
2899 struct drm_i915_private *dev_priv = dev->dev_private;
2900 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2901 u32 temp;
2902
09153000
DV		 2903 mutex_lock(&dev_priv->dpio_lock);
2904
e615efe4
ED		 2905 /* It is necessary to ungate the pixclk gate prior to programming
2906 * the divisors, and gate it back when it is done.
2907 */
2908 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2909
2910 /* Disable SSCCTL */
2911 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2912 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2913 SBI_SSCCTL_DISABLE,
2914 SBI_ICLK);
e615efe4
ED		 2915
2916 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2917 if (crtc->mode.clock == 20000) {
2918 auxdiv = 1;
2919 divsel = 0x41;
2920 phaseinc = 0x20;
2921 } else {
2922 /* The iCLK virtual clock root frequency is in MHz,
2923 * but the crtc->mode.clock in in KHz. To get the divisors,
2924 * it is necessary to divide one by another, so we
2925 * convert the virtual clock precision to KHz here for higher
2926 * precision.
2927 */
2928 u32 iclk_virtual_root_freq = 172800 * 1000;
2929 u32 iclk_pi_range = 64;
2930 u32 desired_divisor, msb_divisor_value, pi_value;
2931
2932 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2933 msb_divisor_value = desired_divisor / iclk_pi_range;
2934 pi_value = desired_divisor % iclk_pi_range;
2935
2936 auxdiv = 0;
2937 divsel = msb_divisor_value - 2;
2938 phaseinc = pi_value;
2939 }
2940
2941 /* This should not happen with any sane values */
2942 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2943 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2944 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2945 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2946
2947 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2948 crtc->mode.clock,
2949 auxdiv,
2950 divsel,
2951 phasedir,
2952 phaseinc);
2953
2954 /* Program SSCDIVINTPHASE6 */
988d6ee8 2955 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2956 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2957 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2958 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2959 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2960 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2961 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2962 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2963
2964 /* Program SSCAUXDIV */
988d6ee8 2965 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2966 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2967 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2968 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2969
2970 /* Enable modulator and associated divider */
988d6ee8 2971 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2972 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2973 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2974
2975 /* Wait for initialization time */
2976 udelay(24);
2977
2978 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2979
2980 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2981}
2982
275f01b2
DV		 2983static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2984 enum pipe pch_transcoder)
2985{
2986 struct drm_device *dev = crtc->base.dev;
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2989
2990 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2991 I915_READ(HTOTAL(cpu_transcoder)));
2992 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2993 I915_READ(HBLANK(cpu_transcoder)));
2994 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2995 I915_READ(HSYNC(cpu_transcoder)));
2996
2997 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2998 I915_READ(VTOTAL(cpu_transcoder)));
2999 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3000 I915_READ(VBLANK(cpu_transcoder)));
3001 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3002 I915_READ(VSYNC(cpu_transcoder)));
3003 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3004 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3005}
3006
f67a559d
JB		 3007/*
3008 * Enable PCH resources required for PCH ports:
3009 * - PCH PLLs
3010 * - FDI training & RX/TX
3011 * - update transcoder timings
3012 * - DP transcoding bits
3013 * - transcoder
3014 */
3015static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3016{
3017 struct drm_device *dev = crtc->dev;
3018 struct drm_i915_private *dev_priv = dev->dev_private;
3019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3020 int pipe = intel_crtc->pipe;
ee7b9f93 3021 u32 reg, temp;
2c07245f 3022
ab9412ba 3023 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3024
cd986abb
DV		 3025 /* Write the TU size bits before fdi link training, so that error
3026 * detection works. */
3027 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3028 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3029
c98e9dcf 3030 /* For PCH output, training FDI link */
674cf967 3031 dev_priv->display.fdi_link_train(crtc);
2c07245f 3032
3ad8a208
DV		 3033 /* We need to program the right clock selection before writing the pixel
3034 * mutliplier into the DPLL. */
303b81e0 3035 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3036 u32 sel;
4b645f14 3037
c98e9dcf 3038 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3039 temp |= TRANS_DPLL_ENABLE(pipe);
3040 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3041 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3042 temp |= sel;
3043 else
3044 temp &= ~sel;
c98e9dcf 3045 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3046 }
5eddb70b 3047
3ad8a208
DV		 3048 /* XXX: pch pll's can be enabled any time before we enable the PCH
3049 * transcoder, and we actually should do this to not upset any PCH
3050 * transcoder that already use the clock when we share it.
3051 *
3052 * Note that enable_shared_dpll tries to do the right thing, but
3053 * get_shared_dpll unconditionally resets the pll - we need that to have
3054 * the right LVDS enable sequence. */
3055 ironlake_enable_shared_dpll(intel_crtc);
3056
d9b6cb56
JB		 3057 /* set transcoder timing, panel must allow it */
3058 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3059 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3060
303b81e0 3061 intel_fdi_normal_train(crtc);
5e84e1a4 3062
c98e9dcf
JB		 3063 /* For PCH DP, enable TRANS_DP_CTL */
3064 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3065 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3066 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3067 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3068 reg = TRANS_DP_CTL(pipe);
3069 temp = I915_READ(reg);
3070 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3071 TRANS_DP_SYNC_MASK |
3072 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3073 temp |= (TRANS_DP_OUTPUT_ENABLE |
3074 TRANS_DP_ENH_FRAMING);
9325c9f0 3075 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3076
3077 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3078 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3079 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3080 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3081
3082 switch (intel_trans_dp_port_sel(crtc)) {
3083 case PCH_DP_B:
5eddb70b 3084 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3085 break;
3086 case PCH_DP_C:
5eddb70b 3087 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3088 break;
3089 case PCH_DP_D:
5eddb70b 3090 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3091 break;
3092 default:
e95d41e1 3093 BUG();
32f9d658 3094 }
2c07245f 3095
5eddb70b 3096 I915_WRITE(reg, temp);
6be4a607 3097 }
b52eb4dc 3098
b8a4f404 3099 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3100}
3101
1507e5bd
PZ		 3102static void lpt_pch_enable(struct drm_crtc *crtc)
3103{
3104 struct drm_device *dev = crtc->dev;
3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3107 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3108
ab9412ba 3109 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3110
8c52b5e8 3111 lpt_program_iclkip(crtc);
1507e5bd 3112
0540e488 3113 /* Set transcoder timing. */
275f01b2 3114 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3115
937bb610 3116 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3117}
3118
e2b78267 3119static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3120{
e2b78267 3121 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3122
3123 if (pll == NULL)
3124 return;
3125
3126 if (pll->refcount == 0) {
46edb027 3127 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3128 return;
3129 }
3130
f4a091c7
DV		 3131 if (--pll->refcount == 0) {
3132 WARN_ON(pll->on);
3133 WARN_ON(pll->active);
3134 }
3135
a43f6e0f 3136 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3137}
3138
b89a1d39 3139static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3140{
e2b78267
DV		 3141 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3142 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3143 enum intel_dpll_id i;
ee7b9f93 3144
ee7b9f93 3145 if (pll) {
46edb027
DV		 3146 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3147 crtc->base.base.id, pll->name);
e2b78267 3148 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3149 }
3150
98b6bd99
DV		 3151 if (HAS_PCH_IBX(dev_priv->dev)) {
3152 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3153 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3154 pll = &dev_priv->shared_dplls[i];
98b6bd99 3155
46edb027
DV		 3156 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3157 crtc->base.base.id, pll->name);
98b6bd99
DV		 3158
3159 goto found;
3160 }
3161
e72f9fbf
DV		 3162 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3163 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3164
3165 /* Only want to check enabled timings first */
3166 if (pll->refcount == 0)
3167 continue;
3168
b89a1d39
DV		 3169 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3170 sizeof(pll->hw_state)) == 0) {
46edb027 3171 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3172 crtc->base.base.id,
46edb027 3173 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3174
3175 goto found;
3176 }
3177 }
3178
3179 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3182 if (pll->refcount == 0) {
46edb027
DV		 3183 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3184 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3185 goto found;
3186 }
3187 }
3188
3189 return NULL;
3190
3191found:
a43f6e0f 3192 crtc->config.shared_dpll = i;
46edb027
DV		 3193 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3194 pipe_name(crtc->pipe));
ee7b9f93 3195
cdbd2316 3196 if (pll->active == 0) {
66e985c0
DV		 3197 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3198 sizeof(pll->hw_state));
3199
46edb027 3200 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3201 WARN_ON(pll->on);
e9d6944e 3202 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3203
15bdd4cf 3204 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3205 }
3206 pll->refcount++;
e04c7350 3207
ee7b9f93
JB		 3208 return pll;
3209}
3210
a1520318 3211static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3212{
3213 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3214 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3215 u32 temp;
3216
3217 temp = I915_READ(dslreg);
3218 udelay(500);
3219 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3220 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3221 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3222 }
3223}
3224
b074cec8
JB		 3225static void ironlake_pfit_enable(struct intel_crtc *crtc)
3226{
3227 struct drm_device *dev = crtc->base.dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 int pipe = crtc->pipe;
3230
0ef37f3f 3231 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3232 /* Force use of hard-coded filter coefficients
3233 * as some pre-programmed values are broken,
3234 * e.g. x201.
3235 */
3236 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3237 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3238 PF_PIPE_SEL_IVB(pipe));
3239 else
3240 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3241 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3242 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3243 }
3244}
3245
bb53d4ae
VS		 3246static void intel_enable_planes(struct drm_crtc *crtc)
3247{
3248 struct drm_device *dev = crtc->dev;
3249 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3250 struct intel_plane *intel_plane;
3251
3252 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3253 if (intel_plane->pipe == pipe)
3254 intel_plane_restore(&intel_plane->base);
3255}
3256
3257static void intel_disable_planes(struct drm_crtc *crtc)
3258{
3259 struct drm_device *dev = crtc->dev;
3260 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3261 struct intel_plane *intel_plane;
3262
3263 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3264 if (intel_plane->pipe == pipe)
3265 intel_plane_disable(&intel_plane->base);
3266}
3267
f67a559d
JB		 3268static void ironlake_crtc_enable(struct drm_crtc *crtc)
3269{
3270 struct drm_device *dev = crtc->dev;
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3273 struct intel_encoder *encoder;
f67a559d
JB		 3274 int pipe = intel_crtc->pipe;
3275 int plane = intel_crtc->plane;
f67a559d 3276
08a48469
DV		 3277 WARN_ON(!crtc->enabled);
3278
f67a559d
JB		 3279 if (intel_crtc->active)
3280 return;
3281
3282 intel_crtc->active = true;
8664281b
PZ		 3283
3284 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3285 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3286
f6736a1a 3287 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3288 if (encoder->pre_enable)
3289 encoder->pre_enable(encoder);
f67a559d 3290
5bfe2ac0 3291 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3292 /* Note: FDI PLL enabling _must_ be done before we enable the
3293 * cpu pipes, hence this is separate from all the other fdi/pch
3294 * enabling. */
88cefb6c 3295 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3296 } else {
3297 assert_fdi_tx_disabled(dev_priv, pipe);
3298 assert_fdi_rx_disabled(dev_priv, pipe);
3299 }
f67a559d 3300
b074cec8 3301 ironlake_pfit_enable(intel_crtc);
f67a559d 3302
9c54c0dd
JB		 3303 /*
3304 * On ILK+ LUT must be loaded before the pipe is running but with
3305 * clocks enabled
3306 */
3307 intel_crtc_load_lut(crtc);
3308
f37fcc2a 3309 intel_update_watermarks(crtc);
5bfe2ac0 3310 intel_enable_pipe(dev_priv, pipe,
23538ef1 3311 intel_crtc->config.has_pch_encoder, false);
f67a559d 3312 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3313 intel_enable_planes(crtc);
5c38d48c 3314 intel_crtc_update_cursor(crtc, true);
f67a559d 3315
5bfe2ac0 3316 if (intel_crtc->config.has_pch_encoder)
f67a559d 3317 ironlake_pch_enable(crtc);
c98e9dcf 3318
d1ebd816 3319 mutex_lock(&dev->struct_mutex);
bed4a673 3320 intel_update_fbc(dev);
d1ebd816
BW		 3321 mutex_unlock(&dev->struct_mutex);
3322
fa5c73b1
DV		 3323 for_each_encoder_on_crtc(dev, crtc, encoder)
3324 encoder->enable(encoder);
61b77ddd
DV		 3325
3326 if (HAS_PCH_CPT(dev))
a1520318 3327 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3328
3329 /*
3330 * There seems to be a race in PCH platform hw (at least on some
3331 * outputs) where an enabled pipe still completes any pageflip right
3332 * away (as if the pipe is off) instead of waiting for vblank. As soon
3333 * as the first vblank happend, everything works as expected. Hence just
3334 * wait for one vblank before returning to avoid strange things
3335 * happening.
3336 */
3337 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3338}
3339
42db64ef
PZ		 3340/* IPS only exists on ULT machines and is tied to pipe A. */
3341static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3342{
f5adf94e 3343 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3344}
3345
3346static void hsw_enable_ips(struct intel_crtc *crtc)
3347{
3348 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3349
3350 if (!crtc->config.ips_enabled)
3351 return;
3352
3353 /* We can only enable IPS after we enable a plane and wait for a vblank.
3354 * We guarantee that the plane is enabled by calling intel_enable_ips
3355 * only after intel_enable_plane. And intel_enable_plane already waits
3356 * for a vblank, so all we need to do here is to enable the IPS bit. */
3357 assert_plane_enabled(dev_priv, crtc->plane);
3358 I915_WRITE(IPS_CTL, IPS_ENABLE);
3359}
3360
3361static void hsw_disable_ips(struct intel_crtc *crtc)
3362{
3363 struct drm_device *dev = crtc->base.dev;
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365
3366 if (!crtc->config.ips_enabled)
3367 return;
3368
3369 assert_plane_enabled(dev_priv, crtc->plane);
3370 I915_WRITE(IPS_CTL, 0);
3371
3372 /* We need to wait for a vblank before we can disable the plane. */
3373 intel_wait_for_vblank(dev, crtc->pipe);
3374}
3375
4f771f10
PZ		 3376static void haswell_crtc_enable(struct drm_crtc *crtc)
3377{
3378 struct drm_device *dev = crtc->dev;
3379 struct drm_i915_private *dev_priv = dev->dev_private;
3380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3381 struct intel_encoder *encoder;
3382 int pipe = intel_crtc->pipe;
3383 int plane = intel_crtc->plane;
4f771f10
PZ		 3384
3385 WARN_ON(!crtc->enabled);
3386
3387 if (intel_crtc->active)
3388 return;
3389
3390 intel_crtc->active = true;
8664281b
PZ		 3391
3392 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3393 if (intel_crtc->config.has_pch_encoder)
3394 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3395
5bfe2ac0 3396 if (intel_crtc->config.has_pch_encoder)
04945641 3397 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3398
3399 for_each_encoder_on_crtc(dev, crtc, encoder)
3400 if (encoder->pre_enable)
3401 encoder->pre_enable(encoder);
3402
1f544388 3403 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3404
b074cec8 3405 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3406
3407 /*
3408 * On ILK+ LUT must be loaded before the pipe is running but with
3409 * clocks enabled
3410 */
3411 intel_crtc_load_lut(crtc);
3412
1f544388 3413 intel_ddi_set_pipe_settings(crtc);
8228c251 3414 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3415
f37fcc2a 3416 intel_update_watermarks(crtc);
5bfe2ac0 3417 intel_enable_pipe(dev_priv, pipe,
23538ef1 3418 intel_crtc->config.has_pch_encoder, false);
4f771f10 3419 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3420 intel_enable_planes(crtc);
5c38d48c 3421 intel_crtc_update_cursor(crtc, true);
4f771f10 3422
42db64ef
PZ		 3423 hsw_enable_ips(intel_crtc);
3424
5bfe2ac0 3425 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3426 lpt_pch_enable(crtc);
4f771f10
PZ		 3427
3428 mutex_lock(&dev->struct_mutex);
3429 intel_update_fbc(dev);
3430 mutex_unlock(&dev->struct_mutex);
3431
8807e55b 3432 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3433 encoder->enable(encoder);
8807e55b
JN		 3434 intel_opregion_notify_encoder(encoder, true);
3435 }
4f771f10 3436
4f771f10
PZ		 3437 /*
3438 * There seems to be a race in PCH platform hw (at least on some
3439 * outputs) where an enabled pipe still completes any pageflip right
3440 * away (as if the pipe is off) instead of waiting for vblank. As soon
3441 * as the first vblank happend, everything works as expected. Hence just
3442 * wait for one vblank before returning to avoid strange things
3443 * happening.
3444 */
3445 intel_wait_for_vblank(dev, intel_crtc->pipe);
3446}
3447
3f8dce3a
DV		 3448static void ironlake_pfit_disable(struct intel_crtc *crtc)
3449{
3450 struct drm_device *dev = crtc->base.dev;
3451 struct drm_i915_private *dev_priv = dev->dev_private;
3452 int pipe = crtc->pipe;
3453
3454 /* To avoid upsetting the power well on haswell only disable the pfit if
3455 * it's in use. The hw state code will make sure we get this right. */
3456 if (crtc->config.pch_pfit.size) {
3457 I915_WRITE(PF_CTL(pipe), 0);
3458 I915_WRITE(PF_WIN_POS(pipe), 0);
3459 I915_WRITE(PF_WIN_SZ(pipe), 0);
3460 }
3461}
3462
6be4a607
JB		 3463static void ironlake_crtc_disable(struct drm_crtc *crtc)
3464{
3465 struct drm_device *dev = crtc->dev;
3466 struct drm_i915_private *dev_priv = dev->dev_private;
3467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3468 struct intel_encoder *encoder;
6be4a607
JB		 3469 int pipe = intel_crtc->pipe;
3470 int plane = intel_crtc->plane;
5eddb70b 3471 u32 reg, temp;
b52eb4dc 3472
ef9c3aee 3473
f7abfe8b
CW		 3474 if (!intel_crtc->active)
3475 return;
3476
ea9d758d
DV		 3477 for_each_encoder_on_crtc(dev, crtc, encoder)
3478 encoder->disable(encoder);
3479
e6c3a2a6 3480 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3481 drm_vblank_off(dev, pipe);
913d8d11 3482
5c3fe8b0 3483 if (dev_priv->fbc.plane == plane)
973d04f9 3484 intel_disable_fbc(dev);
2c07245f 3485
0d5b8c61 3486 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3487 intel_disable_planes(crtc);
0d5b8c61
VS		 3488 intel_disable_plane(dev_priv, plane, pipe);
3489
d925c59a
DV		 3490 if (intel_crtc->config.has_pch_encoder)
3491 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3492
b24e7179 3493 intel_disable_pipe(dev_priv, pipe);
32f9d658 3494
3f8dce3a 3495 ironlake_pfit_disable(intel_crtc);
2c07245f 3496
bf49ec8c
DV		 3497 for_each_encoder_on_crtc(dev, crtc, encoder)
3498 if (encoder->post_disable)
3499 encoder->post_disable(encoder);
2c07245f 3500
d925c59a
DV		 3501 if (intel_crtc->config.has_pch_encoder) {
3502 ironlake_fdi_disable(crtc);
913d8d11 3503
d925c59a
DV		 3504 ironlake_disable_pch_transcoder(dev_priv, pipe);
3505 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3506
d925c59a
DV		 3507 if (HAS_PCH_CPT(dev)) {
3508 /* disable TRANS_DP_CTL */
3509 reg = TRANS_DP_CTL(pipe);
3510 temp = I915_READ(reg);
3511 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3512 TRANS_DP_PORT_SEL_MASK);
3513 temp |= TRANS_DP_PORT_SEL_NONE;
3514 I915_WRITE(reg, temp);
3515
3516 /* disable DPLL_SEL */
3517 temp = I915_READ(PCH_DPLL_SEL);
11887397 3518 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3519 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3520 }
e3421a18 3521
d925c59a 3522 /* disable PCH DPLL */
e72f9fbf 3523 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3524
d925c59a
DV		 3525 ironlake_fdi_pll_disable(intel_crtc);
3526 }
6b383a7f 3527
f7abfe8b 3528 intel_crtc->active = false;
46ba614c 3529 intel_update_watermarks(crtc);
d1ebd816
BW		 3530
3531 mutex_lock(&dev->struct_mutex);
6b383a7f 3532 intel_update_fbc(dev);
d1ebd816 3533 mutex_unlock(&dev->struct_mutex);
6be4a607 3534}
1b3c7a47 3535
4f771f10 3536static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3537{
4f771f10
PZ		 3538 struct drm_device *dev = crtc->dev;
3539 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3541 struct intel_encoder *encoder;
3542 int pipe = intel_crtc->pipe;
3543 int plane = intel_crtc->plane;
3b117c8f 3544 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3545
4f771f10
PZ		 3546 if (!intel_crtc->active)
3547 return;
3548
8807e55b
JN		 3549 for_each_encoder_on_crtc(dev, crtc, encoder) {
3550 intel_opregion_notify_encoder(encoder, false);
4f771f10 3551 encoder->disable(encoder);
8807e55b 3552 }
4f771f10
PZ		 3553
3554 intel_crtc_wait_for_pending_flips(crtc);
3555 drm_vblank_off(dev, pipe);
4f771f10 3556
891348b2 3557 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3558 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3559 intel_disable_fbc(dev);
3560
42db64ef
PZ		 3561 hsw_disable_ips(intel_crtc);
3562
0d5b8c61 3563 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3564 intel_disable_planes(crtc);
891348b2
RV		 3565 intel_disable_plane(dev_priv, plane, pipe);
3566
8664281b
PZ		 3567 if (intel_crtc->config.has_pch_encoder)
3568 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3569 intel_disable_pipe(dev_priv, pipe);
3570
ad80a810 3571 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3572
3f8dce3a 3573 ironlake_pfit_disable(intel_crtc);
4f771f10 3574
1f544388 3575 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3576
3577 for_each_encoder_on_crtc(dev, crtc, encoder)
3578 if (encoder->post_disable)
3579 encoder->post_disable(encoder);
3580
88adfff1 3581 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3582 lpt_disable_pch_transcoder(dev_priv);
8664281b 3583 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3584 intel_ddi_fdi_disable(crtc);
83616634 3585 }
4f771f10
PZ		 3586
3587 intel_crtc->active = false;
46ba614c 3588 intel_update_watermarks(crtc);
4f771f10
PZ		 3589
3590 mutex_lock(&dev->struct_mutex);
3591 intel_update_fbc(dev);
3592 mutex_unlock(&dev->struct_mutex);
3593}
3594
ee7b9f93
JB		 3595static void ironlake_crtc_off(struct drm_crtc *crtc)
3596{
3597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3598 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3599}
3600
6441ab5f
PZ		 3601static void haswell_crtc_off(struct drm_crtc *crtc)
3602{
3603 intel_ddi_put_crtc_pll(crtc);
3604}
3605
02e792fb
DV		 3606static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3607{
02e792fb 3608 if (!enable && intel_crtc->overlay) {
23f09ce3 3609 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3610 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3611
23f09ce3 3612 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3613 dev_priv->mm.interruptible = false;
3614 (void) intel_overlay_switch_off(intel_crtc->overlay);
3615 dev_priv->mm.interruptible = true;
23f09ce3 3616 mutex_unlock(&dev->struct_mutex);
02e792fb 3617 }
02e792fb 3618
5dcdbcb0
CW		 3619 /* Let userspace switch the overlay on again. In most cases userspace
3620 * has to recompute where to put it anyway.
3621 */
02e792fb
DV		 3622}
3623
61bc95c1
EE		 3624/**
3625 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3626 * cursor plane briefly if not already running after enabling the display
3627 * plane.
3628 * This workaround avoids occasional blank screens when self refresh is
3629 * enabled.
3630 */
3631static void
3632g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3633{
3634 u32 cntl = I915_READ(CURCNTR(pipe));
3635
3636 if ((cntl & CURSOR_MODE) == 0) {
3637 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3638
3639 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3640 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3641 intel_wait_for_vblank(dev_priv->dev, pipe);
3642 I915_WRITE(CURCNTR(pipe), cntl);
3643 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3644 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3645 }
3646}
3647
2dd24552
JB		 3648static void i9xx_pfit_enable(struct intel_crtc *crtc)
3649{
3650 struct drm_device *dev = crtc->base.dev;
3651 struct drm_i915_private *dev_priv = dev->dev_private;
3652 struct intel_crtc_config *pipe_config = &crtc->config;
3653
328d8e82 3654 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3655 return;
3656
2dd24552 3657 /*
c0b03411
DV		 3658 * The panel fitter should only be adjusted whilst the pipe is disabled,
3659 * according to register description and PRM.
2dd24552 3660 */
c0b03411
DV		 3661 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3662 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3663
b074cec8
JB		 3664 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3665 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3666
3667 /* Border color in case we don't scale up to the full screen. Black by
3668 * default, change to something else for debugging. */
3669 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3670}
3671
89b667f8
JB		 3672static void valleyview_crtc_enable(struct drm_crtc *crtc)
3673{
3674 struct drm_device *dev = crtc->dev;
3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3677 struct intel_encoder *encoder;
3678 int pipe = intel_crtc->pipe;
3679 int plane = intel_crtc->plane;
23538ef1 3680 bool is_dsi;
89b667f8
JB		 3681
3682 WARN_ON(!crtc->enabled);
3683
3684 if (intel_crtc->active)
3685 return;
3686
3687 intel_crtc->active = true;
89b667f8 3688
89b667f8
JB		 3689 for_each_encoder_on_crtc(dev, crtc, encoder)
3690 if (encoder->pre_pll_enable)
3691 encoder->pre_pll_enable(encoder);
3692
23538ef1
JN		 3693 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3694
e9fd1c02
JN		 3695 if (!is_dsi)
3696 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3697
3698 for_each_encoder_on_crtc(dev, crtc, encoder)
3699 if (encoder->pre_enable)
3700 encoder->pre_enable(encoder);
3701
2dd24552
JB		 3702 i9xx_pfit_enable(intel_crtc);
3703
63cbb074
VS		 3704 intel_crtc_load_lut(crtc);
3705
f37fcc2a 3706 intel_update_watermarks(crtc);
23538ef1 3707 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3708 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3709 intel_enable_planes(crtc);
5c38d48c 3710 intel_crtc_update_cursor(crtc, true);
89b667f8 3711
89b667f8 3712 intel_update_fbc(dev);
5004945f
JN		 3713
3714 for_each_encoder_on_crtc(dev, crtc, encoder)
3715 encoder->enable(encoder);
89b667f8
JB		 3716}
3717
0b8765c6 3718static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3719{
3720 struct drm_device *dev = crtc->dev;
79e53945
JB		 3721 struct drm_i915_private *dev_priv = dev->dev_private;
3722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3723 struct intel_encoder *encoder;
79e53945 3724 int pipe = intel_crtc->pipe;
80824003 3725 int plane = intel_crtc->plane;
79e53945 3726
08a48469
DV		 3727 WARN_ON(!crtc->enabled);
3728
f7abfe8b
CW		 3729 if (intel_crtc->active)
3730 return;
3731
3732 intel_crtc->active = true;
6b383a7f 3733
9d6d9f19
MK		 3734 for_each_encoder_on_crtc(dev, crtc, encoder)
3735 if (encoder->pre_enable)
3736 encoder->pre_enable(encoder);
3737
f6736a1a
DV		 3738 i9xx_enable_pll(intel_crtc);
3739
2dd24552
JB		 3740 i9xx_pfit_enable(intel_crtc);
3741
63cbb074
VS		 3742 intel_crtc_load_lut(crtc);
3743
f37fcc2a 3744 intel_update_watermarks(crtc);
23538ef1 3745 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3746 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3747 intel_enable_planes(crtc);
22e407d7 3748 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3749 if (IS_G4X(dev))
3750 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3751 intel_crtc_update_cursor(crtc, true);
79e53945 3752
0b8765c6
JB		 3753 /* Give the overlay scaler a chance to enable if it's on this pipe */
3754 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3755
f440eb13 3756 intel_update_fbc(dev);
ef9c3aee 3757
fa5c73b1
DV		 3758 for_each_encoder_on_crtc(dev, crtc, encoder)
3759 encoder->enable(encoder);
0b8765c6 3760}
79e53945 3761
87476d63
DV		 3762static void i9xx_pfit_disable(struct intel_crtc *crtc)
3763{
3764 struct drm_device *dev = crtc->base.dev;
3765 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3766
328d8e82
DV		 3767 if (!crtc->config.gmch_pfit.control)
3768 return;
87476d63 3769
328d8e82 3770 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3771
328d8e82
DV		 3772 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3773 I915_READ(PFIT_CONTROL));
3774 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3775}
3776
0b8765c6
JB		 3777static void i9xx_crtc_disable(struct drm_crtc *crtc)
3778{
3779 struct drm_device *dev = crtc->dev;
3780 struct drm_i915_private *dev_priv = dev->dev_private;
3781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3782 struct intel_encoder *encoder;
0b8765c6
JB		 3783 int pipe = intel_crtc->pipe;
3784 int plane = intel_crtc->plane;
ef9c3aee 3785
f7abfe8b
CW		 3786 if (!intel_crtc->active)
3787 return;
3788
ea9d758d
DV		 3789 for_each_encoder_on_crtc(dev, crtc, encoder)
3790 encoder->disable(encoder);
3791
0b8765c6 3792 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3793 intel_crtc_wait_for_pending_flips(crtc);
3794 drm_vblank_off(dev, pipe);
0b8765c6 3795
5c3fe8b0 3796 if (dev_priv->fbc.plane == plane)
973d04f9 3797 intel_disable_fbc(dev);
79e53945 3798
0d5b8c61
VS		 3799 intel_crtc_dpms_overlay(intel_crtc, false);
3800 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3801 intel_disable_planes(crtc);
b24e7179 3802 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3803
b24e7179 3804 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3805
87476d63 3806 i9xx_pfit_disable(intel_crtc);
24a1f16d 3807
89b667f8
JB		 3808 for_each_encoder_on_crtc(dev, crtc, encoder)
3809 if (encoder->post_disable)
3810 encoder->post_disable(encoder);
3811
e9fd1c02
JN		 3812 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3813 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3814
f7abfe8b 3815 intel_crtc->active = false;
46ba614c 3816 intel_update_watermarks(crtc);
f37fcc2a
VS		 3817
3818 intel_update_fbc(dev);
0b8765c6
JB		 3819}
3820
ee7b9f93
JB		 3821static void i9xx_crtc_off(struct drm_crtc *crtc)
3822{
3823}
3824
976f8a20
DV		 3825static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3826 bool enabled)
2c07245f
ZW		 3827{
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_i915_master_private *master_priv;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831 int pipe = intel_crtc->pipe;
79e53945
JB		 3832
3833 if (!dev->primary->master)
3834 return;
3835
3836 master_priv = dev->primary->master->driver_priv;
3837 if (!master_priv->sarea_priv)
3838 return;
3839
79e53945
JB		 3840 switch (pipe) {
3841 case 0:
3842 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3843 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3844 break;
3845 case 1:
3846 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3847 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3848 break;
3849 default:
9db4a9c7 3850 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3851 break;
3852 }
79e53945
JB		 3853}
3854
976f8a20
DV		 3855/**
3856 * Sets the power management mode of the pipe and plane.
3857 */
3858void intel_crtc_update_dpms(struct drm_crtc *crtc)
3859{
3860 struct drm_device *dev = crtc->dev;
3861 struct drm_i915_private *dev_priv = dev->dev_private;
3862 struct intel_encoder *intel_encoder;
3863 bool enable = false;
3864
3865 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3866 enable |= intel_encoder->connectors_active;
3867
3868 if (enable)
3869 dev_priv->display.crtc_enable(crtc);
3870 else
3871 dev_priv->display.crtc_disable(crtc);
3872
3873 intel_crtc_update_sarea(crtc, enable);
3874}
3875
cdd59983
CW		 3876static void intel_crtc_disable(struct drm_crtc *crtc)
3877{
cdd59983 3878 struct drm_device *dev = crtc->dev;
976f8a20 3879 struct drm_connector *connector;
ee7b9f93 3880 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3882
976f8a20
DV		 3883 /* crtc should still be enabled when we disable it. */
3884 WARN_ON(!crtc->enabled);
3885
3886 dev_priv->display.crtc_disable(crtc);
c77bf565 3887 intel_crtc->eld_vld = false;
976f8a20 3888 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3889 dev_priv->display.off(crtc);
3890
931872fc 3891 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3892 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3893 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3894
3895 if (crtc->fb) {
3896 mutex_lock(&dev->struct_mutex);
1690e1eb 3897 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3898 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3899 crtc->fb = NULL;
3900 }
3901
3902 /* Update computed state. */
3903 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3904 if (!connector->encoder || !connector->encoder->crtc)
3905 continue;
3906
3907 if (connector->encoder->crtc != crtc)
3908 continue;
3909
3910 connector->dpms = DRM_MODE_DPMS_OFF;
3911 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3912 }
3913}
3914
ea5b213a 3915void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3916{
4ef69c7a 3917 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3918
ea5b213a
CW		 3919 drm_encoder_cleanup(encoder);
3920 kfree(intel_encoder);
7e7d76c3
JB		 3921}
3922
9237329d 3923/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3924 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3925 * state of the entire output pipe. */
9237329d 3926static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3927{
5ab432ef
DV		 3928 if (mode == DRM_MODE_DPMS_ON) {
3929 encoder->connectors_active = true;
3930
b2cabb0e 3931 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3932 } else {
3933 encoder->connectors_active = false;
3934
b2cabb0e 3935 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3936 }
79e53945
JB		 3937}
3938
0a91ca29
DV		 3939/* Cross check the actual hw state with our own modeset state tracking (and it's
3940 * internal consistency). */
b980514c 3941static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3942{
0a91ca29
DV		 3943 if (connector->get_hw_state(connector)) {
3944 struct intel_encoder *encoder = connector->encoder;
3945 struct drm_crtc *crtc;
3946 bool encoder_enabled;
3947 enum pipe pipe;
3948
3949 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3950 connector->base.base.id,
3951 drm_get_connector_name(&connector->base));
3952
3953 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3954 "wrong connector dpms state\n");
3955 WARN(connector->base.encoder != &encoder->base,
3956 "active connector not linked to encoder\n");
3957 WARN(!encoder->connectors_active,
3958 "encoder->connectors_active not set\n");
3959
3960 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3961 WARN(!encoder_enabled, "encoder not enabled\n");
3962 if (WARN_ON(!encoder->base.crtc))
3963 return;
3964
3965 crtc = encoder->base.crtc;
3966
3967 WARN(!crtc->enabled, "crtc not enabled\n");
3968 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3969 WARN(pipe != to_intel_crtc(crtc)->pipe,
3970 "encoder active on the wrong pipe\n");
3971 }
79e53945
JB		 3972}
3973
5ab432ef
DV		 3974/* Even simpler default implementation, if there's really no special case to
3975 * consider. */
3976void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3977{
5ab432ef 3978 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3979
5ab432ef
DV		 3980 /* All the simple cases only support two dpms states. */
3981 if (mode != DRM_MODE_DPMS_ON)
3982 mode = DRM_MODE_DPMS_OFF;
d4270e57 3983
5ab432ef
DV		 3984 if (mode == connector->dpms)
3985 return;
3986
3987 connector->dpms = mode;
3988
3989 /* Only need to change hw state when actually enabled */
3990 if (encoder->base.crtc)
3991 intel_encoder_dpms(encoder, mode);
3992 else
8af6cf88 3993 WARN_ON(encoder->connectors_active != false);
0a91ca29 3994
b980514c 3995 intel_modeset_check_state(connector->dev);
79e53945
JB		 3996}
3997
f0947c37
DV		 3998/* Simple connector->get_hw_state implementation for encoders that support only
3999 * one connector and no cloning and hence the encoder state determines the state
4000 * of the connector. */
4001bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4002{
24929352 4003 enum pipe pipe = 0;
f0947c37 4004 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4005
f0947c37 4006 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4007}
4008
1857e1da
DV		 4009static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4010 struct intel_crtc_config *pipe_config)
4011{
4012 struct drm_i915_private *dev_priv = dev->dev_private;
4013 struct intel_crtc *pipe_B_crtc =
4014 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4015
4016 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4017 pipe_name(pipe), pipe_config->fdi_lanes);
4018 if (pipe_config->fdi_lanes > 4) {
4019 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4020 pipe_name(pipe), pipe_config->fdi_lanes);
4021 return false;
4022 }
4023
4024 if (IS_HASWELL(dev)) {
4025 if (pipe_config->fdi_lanes > 2) {
4026 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4027 pipe_config->fdi_lanes);
4028 return false;
4029 } else {
4030 return true;
4031 }
4032 }
4033
4034 if (INTEL_INFO(dev)->num_pipes == 2)
4035 return true;
4036
4037 /* Ivybridge 3 pipe is really complicated */
4038 switch (pipe) {
4039 case PIPE_A:
4040 return true;
4041 case PIPE_B:
4042 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4043 pipe_config->fdi_lanes > 2) {
4044 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4045 pipe_name(pipe), pipe_config->fdi_lanes);
4046 return false;
4047 }
4048 return true;
4049 case PIPE_C:
1e833f40 4050 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4051 pipe_B_crtc->config.fdi_lanes <= 2) {
4052 if (pipe_config->fdi_lanes > 2) {
4053 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4054 pipe_name(pipe), pipe_config->fdi_lanes);
4055 return false;
4056 }
4057 } else {
4058 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4059 return false;
4060 }
4061 return true;
4062 default:
4063 BUG();
4064 }
4065}
4066
e29c22c0
DV		 4067#define RETRY 1
4068static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4069 struct intel_crtc_config *pipe_config)
877d48d5 4070{
1857e1da 4071 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4072 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4073 int lane, link_bw, fdi_dotclock;
e29c22c0 4074 bool setup_ok, needs_recompute = false;
877d48d5 4075
e29c22c0 4076retry:
877d48d5
DV		 4077 /* FDI is a binary signal running at ~2.7GHz, encoding
4078 * each output octet as 10 bits. The actual frequency
4079 * is stored as a divider into a 100MHz clock, and the
4080 * mode pixel clock is stored in units of 1KHz.
4081 * Hence the bw of each lane in terms of the mode signal
4082 * is:
4083 */
4084 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4085
ff9a6750 4086 fdi_dotclock = adjusted_mode->clock;
877d48d5 4087
2bd89a07 4088 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4089 pipe_config->pipe_bpp);
4090
4091 pipe_config->fdi_lanes = lane;
4092
2bd89a07 4093 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4094 link_bw, &pipe_config->fdi_m_n);
1857e1da 4095
e29c22c0
DV		 4096 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4097 intel_crtc->pipe, pipe_config);
4098 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4099 pipe_config->pipe_bpp -= 2*3;
4100 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4101 pipe_config->pipe_bpp);
4102 needs_recompute = true;
4103 pipe_config->bw_constrained = true;
4104
4105 goto retry;
4106 }
4107
4108 if (needs_recompute)
4109 return RETRY;
4110
4111 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4112}
4113
42db64ef
PZ		 4114static void hsw_compute_ips_config(struct intel_crtc *crtc,
4115 struct intel_crtc_config *pipe_config)
4116{
3c4ca58c
PZ		 4117 pipe_config->ips_enabled = i915_enable_ips &&
4118 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4119 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4120}
4121
a43f6e0f 4122static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4123 struct intel_crtc_config *pipe_config)
79e53945 4124{
a43f6e0f 4125 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4126 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4127
8693a824
DL		 4128 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4129 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4130 */
4131 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4132 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4133 return -EINVAL;
44f46b42 4134
bd080ee5 4135 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4136 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4137 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4138 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4139 * for lvds. */
4140 pipe_config->pipe_bpp = 8*3;
4141 }
4142
f5adf94e 4143 if (HAS_IPS(dev))
a43f6e0f
DV		 4144 hsw_compute_ips_config(crtc, pipe_config);
4145
4146 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4147 * clock survives for now. */
4148 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4149 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4150
877d48d5 4151 if (pipe_config->has_pch_encoder)
a43f6e0f 4152 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4153
e29c22c0 4154 return 0;
79e53945
JB		 4155}
4156
25eb05fc
JB		 4157static int valleyview_get_display_clock_speed(struct drm_device *dev)
4158{
4159 return 400000; /* FIXME */
4160}
4161
e70236a8
JB		 4162static int i945_get_display_clock_speed(struct drm_device *dev)
4163{
4164 return 400000;
4165}
79e53945 4166
e70236a8 4167static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4168{
e70236a8
JB		 4169 return 333000;
4170}
79e53945 4171
e70236a8
JB		 4172static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4173{
4174 return 200000;
4175}
79e53945 4176
257a7ffc
DV		 4177static int pnv_get_display_clock_speed(struct drm_device *dev)
4178{
4179 u16 gcfgc = 0;
4180
4181 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4182
4183 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4184 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4185 return 267000;
4186 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4187 return 333000;
4188 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4189 return 444000;
4190 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4191 return 200000;
4192 default:
4193 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4194 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4195 return 133000;
4196 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4197 return 167000;
4198 }
4199}
4200
e70236a8
JB		 4201static int i915gm_get_display_clock_speed(struct drm_device *dev)
4202{
4203 u16 gcfgc = 0;
79e53945 4204
e70236a8
JB		 4205 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4206
4207 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4208 return 133000;
4209 else {
4210 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4211 case GC_DISPLAY_CLOCK_333_MHZ:
4212 return 333000;
4213 default:
4214 case GC_DISPLAY_CLOCK_190_200_MHZ:
4215 return 190000;
79e53945 4216 }
e70236a8
JB		 4217 }
4218}
4219
4220static int i865_get_display_clock_speed(struct drm_device *dev)
4221{
4222 return 266000;
4223}
4224
4225static int i855_get_display_clock_speed(struct drm_device *dev)
4226{
4227 u16 hpllcc = 0;
4228 /* Assume that the hardware is in the high speed state. This
4229 * should be the default.
4230 */
4231 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4232 case GC_CLOCK_133_200:
4233 case GC_CLOCK_100_200:
4234 return 200000;
4235 case GC_CLOCK_166_250:
4236 return 250000;
4237 case GC_CLOCK_100_133:
79e53945 4238 return 133000;
e70236a8 4239 }
79e53945 4240
e70236a8
JB		 4241 /* Shouldn't happen */
4242 return 0;
4243}
79e53945 4244
e70236a8
JB		 4245static int i830_get_display_clock_speed(struct drm_device *dev)
4246{
4247 return 133000;
79e53945
JB		 4248}
4249
2c07245f 4250static void
a65851af 4251intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4252{
a65851af
VS		 4253 while (*num > DATA_LINK_M_N_MASK ||
4254 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4255 *num >>= 1;
4256 *den >>= 1;
4257 }
4258}
4259
a65851af
VS		 4260static void compute_m_n(unsigned int m, unsigned int n,
4261 uint32_t *ret_m, uint32_t *ret_n)
4262{
4263 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4264 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4265 intel_reduce_m_n_ratio(ret_m, ret_n);
4266}
4267
e69d0bc1
DV		 4268void
4269intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4270 int pixel_clock, int link_clock,
4271 struct intel_link_m_n *m_n)
2c07245f 4272{
e69d0bc1 4273 m_n->tu = 64;
a65851af
VS		 4274
4275 compute_m_n(bits_per_pixel * pixel_clock,
4276 link_clock * nlanes * 8,
4277 &m_n->gmch_m, &m_n->gmch_n);
4278
4279 compute_m_n(pixel_clock, link_clock,
4280 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4281}
4282
a7615030
CW		 4283static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4284{
72bbe58c
KP		 4285 if (i915_panel_use_ssc >= 0)
4286 return i915_panel_use_ssc != 0;
41aa3448 4287 return dev_priv->vbt.lvds_use_ssc
435793df 4288 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4289}
4290
a0c4da24
JB		 4291static int vlv_get_refclk(struct drm_crtc *crtc)
4292{
4293 struct drm_device *dev = crtc->dev;
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 int refclk = 27000; /* for DP & HDMI */
4296
4297 return 100000; /* only one validated so far */
4298
4299 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4300 refclk = 96000;
4301 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4302 if (intel_panel_use_ssc(dev_priv))
4303 refclk = 100000;
4304 else
4305 refclk = 96000;
4306 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4307 refclk = 100000;
4308 }
4309
4310 return refclk;
4311}
4312
c65d77d8
JB		 4313static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4314{
4315 struct drm_device *dev = crtc->dev;
4316 struct drm_i915_private *dev_priv = dev->dev_private;
4317 int refclk;
4318
a0c4da24
JB		 4319 if (IS_VALLEYVIEW(dev)) {
4320 refclk = vlv_get_refclk(crtc);
4321 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4322 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4323 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4324 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4325 refclk / 1000);
4326 } else if (!IS_GEN2(dev)) {
4327 refclk = 96000;
4328 } else {
4329 refclk = 48000;
4330 }
4331
4332 return refclk;
4333}
4334
7429e9d4 4335static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4336{
7df00d7a 4337 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4338}
f47709a9 4339
7429e9d4
DV		 4340static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4341{
4342 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4343}
4344
f47709a9 4345static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4346 intel_clock_t *reduced_clock)
4347{
f47709a9 4348 struct drm_device *dev = crtc->base.dev;
a7516a05 4349 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4350 int pipe = crtc->pipe;
a7516a05
JB		 4351 u32 fp, fp2 = 0;
4352
4353 if (IS_PINEVIEW(dev)) {
7429e9d4 4354 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4355 if (reduced_clock)
7429e9d4 4356 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4357 } else {
7429e9d4 4358 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4359 if (reduced_clock)
7429e9d4 4360 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4361 }
4362
4363 I915_WRITE(FP0(pipe), fp);
8bcc2795 4364 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4365
f47709a9
DV		 4366 crtc->lowfreq_avail = false;
4367 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4368 reduced_clock && i915_powersave) {
4369 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4370 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4371 crtc->lowfreq_avail = true;
a7516a05
JB		 4372 } else {
4373 I915_WRITE(FP1(pipe), fp);
8bcc2795 4374 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4375 }
4376}
4377
5e69f97f
CML		 4378static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4379 pipe)
89b667f8
JB		 4380{
4381 u32 reg_val;
4382
4383 /*
4384 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4385 * and set it to a reasonable value instead.
4386 */
5e69f97f 4387 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4388 reg_val &= 0xffffff00;
4389 reg_val |= 0x00000030;
5e69f97f 4390 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4391
5e69f97f 4392 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4393 reg_val &= 0x8cffffff;
4394 reg_val = 0x8c000000;
5e69f97f 4395 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4396
5e69f97f 4397 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4398 reg_val &= 0xffffff00;
5e69f97f 4399 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4400
5e69f97f 4401 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4402 reg_val &= 0x00ffffff;
4403 reg_val |= 0xb0000000;
5e69f97f 4404 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4405}
4406
b551842d
DV		 4407static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4408 struct intel_link_m_n *m_n)
4409{
4410 struct drm_device *dev = crtc->base.dev;
4411 struct drm_i915_private *dev_priv = dev->dev_private;
4412 int pipe = crtc->pipe;
4413
e3b95f1e
DV		 4414 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4415 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4416 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4417 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4418}
4419
4420static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4421 struct intel_link_m_n *m_n)
4422{
4423 struct drm_device *dev = crtc->base.dev;
4424 struct drm_i915_private *dev_priv = dev->dev_private;
4425 int pipe = crtc->pipe;
4426 enum transcoder transcoder = crtc->config.cpu_transcoder;
4427
4428 if (INTEL_INFO(dev)->gen >= 5) {
4429 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4430 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4431 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4432 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4433 } else {
e3b95f1e
DV		 4434 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4435 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4436 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4437 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4438 }
4439}
4440
03afc4a2
DV		 4441static void intel_dp_set_m_n(struct intel_crtc *crtc)
4442{
4443 if (crtc->config.has_pch_encoder)
4444 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4445 else
4446 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4447}
4448
f47709a9 4449static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4450{
f47709a9 4451 struct drm_device *dev = crtc->base.dev;
a0c4da24 4452 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4453 int pipe = crtc->pipe;
89b667f8 4454 u32 dpll, mdiv;
a0c4da24 4455 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4456 u32 coreclk, reg_val, dpll_md;
a0c4da24 4457
09153000
DV		 4458 mutex_lock(&dev_priv->dpio_lock);
4459
f47709a9
DV		 4460 bestn = crtc->config.dpll.n;
4461 bestm1 = crtc->config.dpll.m1;
4462 bestm2 = crtc->config.dpll.m2;
4463 bestp1 = crtc->config.dpll.p1;
4464 bestp2 = crtc->config.dpll.p2;
a0c4da24 4465
89b667f8
JB		 4466 /* See eDP HDMI DPIO driver vbios notes doc */
4467
4468 /* PLL B needs special handling */
4469 if (pipe)
5e69f97f 4470 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4471
4472 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4473 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4474
4475 /* Disable target IRef on PLL */
5e69f97f 4476 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4477 reg_val &= 0x00ffffff;
5e69f97f 4478 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4479
4480 /* Disable fast lock */
5e69f97f 4481 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4482
4483 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4484 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4485 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4486 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4487 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4488
4489 /*
4490 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4491 * but we don't support that).
4492 * Note: don't use the DAC post divider as it seems unstable.
4493 */
4494 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4495 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4496
a0c4da24 4497 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4498 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4499
89b667f8 4500 /* Set HBR and RBR LPF coefficients */
ff9a6750 4501 if (crtc->config.port_clock == 162000 ||
99750bd4 4502 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4503 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4504 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4505 0x009f0003);
89b667f8 4506 else
5e69f97f 4507 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4508 0x00d0000f);
4509
4510 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4511 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4512 /* Use SSC source */
4513 if (!pipe)
5e69f97f 4514 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4515 0x0df40000);
4516 else
5e69f97f 4517 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4518 0x0df70000);
4519 } else { /* HDMI or VGA */
4520 /* Use bend source */
4521 if (!pipe)
5e69f97f 4522 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4523 0x0df70000);
4524 else
5e69f97f 4525 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4526 0x0df40000);
4527 }
a0c4da24 4528
5e69f97f 4529 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4530 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4531 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4532 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4533 coreclk |= 0x01000000;
5e69f97f 4534 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4535
5e69f97f 4536 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4537
89b667f8
JB		 4538 /* Enable DPIO clock input */
4539 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4540 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4541 if (pipe)
4542 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4543
4544 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4545 crtc->config.dpll_hw_state.dpll = dpll;
4546
ef1b460d
DV		 4547 dpll_md = (crtc->config.pixel_multiplier - 1)
4548 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4549 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4550
89b667f8
JB		 4551 if (crtc->config.has_dp_encoder)
4552 intel_dp_set_m_n(crtc);
09153000
DV		 4553
4554 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4555}
4556
f47709a9
DV		 4557static void i9xx_update_pll(struct intel_crtc *crtc,
4558 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4559 int num_connectors)
4560{
f47709a9 4561 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4562 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4563 u32 dpll;
4564 bool is_sdvo;
f47709a9 4565 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4566
f47709a9 4567 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4568
f47709a9
DV		 4569 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4570 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4571
4572 dpll = DPLL_VGA_MODE_DIS;
4573
f47709a9 4574 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4575 dpll |= DPLLB_MODE_LVDS;
4576 else
4577 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4578
ef1b460d 4579 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4580 dpll |= (crtc->config.pixel_multiplier - 1)
4581 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4582 }
198a037f
DV		 4583
4584 if (is_sdvo)
4a33e48d 4585 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4586
f47709a9 4587 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4588 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4589
4590 /* compute bitmask from p1 value */
4591 if (IS_PINEVIEW(dev))
4592 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4593 else {
4594 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4595 if (IS_G4X(dev) && reduced_clock)
4596 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4597 }
4598 switch (clock->p2) {
4599 case 5:
4600 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4601 break;
4602 case 7:
4603 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4604 break;
4605 case 10:
4606 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4607 break;
4608 case 14:
4609 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4610 break;
4611 }
4612 if (INTEL_INFO(dev)->gen >= 4)
4613 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4614
09ede541 4615 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4616 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4617 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4618 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4619 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4620 else
4621 dpll |= PLL_REF_INPUT_DREFCLK;
4622
4623 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4624 crtc->config.dpll_hw_state.dpll = dpll;
4625
eb1cbe48 4626 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4627 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4628 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4629 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4630 }
66e3d5c0
DV		 4631
4632 if (crtc->config.has_dp_encoder)
4633 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4634}
4635
f47709a9 4636static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4637 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4638 int num_connectors)
4639{
f47709a9 4640 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4641 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4642 u32 dpll;
f47709a9 4643 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4644
f47709a9 4645 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4646
eb1cbe48
DV		 4647 dpll = DPLL_VGA_MODE_DIS;
4648
f47709a9 4649 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4650 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4651 } else {
4652 if (clock->p1 == 2)
4653 dpll |= PLL_P1_DIVIDE_BY_TWO;
4654 else
4655 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4656 if (clock->p2 == 4)
4657 dpll |= PLL_P2_DIVIDE_BY_4;
4658 }
4659
4a33e48d
DV		 4660 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4661 dpll |= DPLL_DVO_2X_MODE;
4662
f47709a9 4663 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4664 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4665 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4666 else
4667 dpll |= PLL_REF_INPUT_DREFCLK;
4668
4669 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4670 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4671}
4672
8a654f3b 4673static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4674{
4675 struct drm_device *dev = intel_crtc->base.dev;
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4678 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4679 struct drm_display_mode *adjusted_mode =
4680 &intel_crtc->config.adjusted_mode;
4681 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4682 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4683
4684 /* We need to be careful not to changed the adjusted mode, for otherwise
4685 * the hw state checker will get angry at the mismatch. */
4686 crtc_vtotal = adjusted_mode->crtc_vtotal;
4687 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4688
4689 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4690 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4691 crtc_vtotal -= 1;
4692 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4693 vsyncshift = adjusted_mode->crtc_hsync_start
4694 - adjusted_mode->crtc_htotal / 2;
4695 } else {
4696 vsyncshift = 0;
4697 }
4698
4699 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4700 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4701
fe2b8f9d 4702 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4703 (adjusted_mode->crtc_hdisplay - 1) |
4704 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4705 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4706 (adjusted_mode->crtc_hblank_start - 1) |
4707 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4708 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4709 (adjusted_mode->crtc_hsync_start - 1) |
4710 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4711
fe2b8f9d 4712 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4713 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4714 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4715 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4716 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4717 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4718 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4719 (adjusted_mode->crtc_vsync_start - 1) |
4720 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4721
b5e508d4
PZ		 4722 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4723 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4724 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4725 * bits. */
4726 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4727 (pipe == PIPE_B || pipe == PIPE_C))
4728 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4729
b0e77b9c
PZ		 4730 /* pipesrc controls the size that is scaled from, which should
4731 * always be the user's requested size.
4732 */
4733 I915_WRITE(PIPESRC(pipe),
4734 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4735}
4736
1bd1bd80
DV		 4737static void intel_get_pipe_timings(struct intel_crtc *crtc,
4738 struct intel_crtc_config *pipe_config)
4739{
4740 struct drm_device *dev = crtc->base.dev;
4741 struct drm_i915_private *dev_priv = dev->dev_private;
4742 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4743 uint32_t tmp;
4744
4745 tmp = I915_READ(HTOTAL(cpu_transcoder));
4746 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4747 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4748 tmp = I915_READ(HBLANK(cpu_transcoder));
4749 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4750 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4751 tmp = I915_READ(HSYNC(cpu_transcoder));
4752 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4753 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4754
4755 tmp = I915_READ(VTOTAL(cpu_transcoder));
4756 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4757 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4758 tmp = I915_READ(VBLANK(cpu_transcoder));
4759 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4760 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4761 tmp = I915_READ(VSYNC(cpu_transcoder));
4762 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4763 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4764
4765 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4766 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4767 pipe_config->adjusted_mode.crtc_vtotal += 1;
4768 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4769 }
4770
4771 tmp = I915_READ(PIPESRC(crtc->pipe));
4772 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4773 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4774}
4775
babea61d
JB		 4776static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4777 struct intel_crtc_config *pipe_config)
4778{
4779 struct drm_crtc *crtc = &intel_crtc->base;
4780
4781 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4782 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4783 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4784 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4785
4786 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4787 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4788 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4789 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4790
4791 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4792
4793 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4794 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4795}
4796
84b046f3
DV		 4797static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4798{
4799 struct drm_device *dev = intel_crtc->base.dev;
4800 struct drm_i915_private *dev_priv = dev->dev_private;
4801 uint32_t pipeconf;
4802
9f11a9e4 4803 pipeconf = 0;
84b046f3
DV		 4804
4805 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4806 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4807 * core speed.
4808 *
4809 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4810 * pipe == 0 check?
4811 */
4812 if (intel_crtc->config.requested_mode.clock >
4813 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4814 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4815 }
4816
ff9ce46e
DV		 4817 /* only g4x and later have fancy bpc/dither controls */
4818 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4819 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4820 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4821 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4822 PIPECONF_DITHER_TYPE_SP;
84b046f3 4823
ff9ce46e
DV		 4824 switch (intel_crtc->config.pipe_bpp) {
4825 case 18:
4826 pipeconf |= PIPECONF_6BPC;
4827 break;
4828 case 24:
4829 pipeconf |= PIPECONF_8BPC;
4830 break;
4831 case 30:
4832 pipeconf |= PIPECONF_10BPC;
4833 break;
4834 default:
4835 /* Case prevented by intel_choose_pipe_bpp_dither. */
4836 BUG();
84b046f3
DV		 4837 }
4838 }
4839
4840 if (HAS_PIPE_CXSR(dev)) {
4841 if (intel_crtc->lowfreq_avail) {
4842 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4843 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4844 } else {
4845 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4846 }
4847 }
4848
84b046f3
DV		 4849 if (!IS_GEN2(dev) &&
4850 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4851 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4852 else
4853 pipeconf |= PIPECONF_PROGRESSIVE;
4854
9f11a9e4
DV		 4855 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4856 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4857
84b046f3
DV		 4858 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4859 POSTING_READ(PIPECONF(intel_crtc->pipe));
4860}
4861
f564048e 4862static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4863 int x, int y,
94352cf9 4864 struct drm_framebuffer *fb)
79e53945
JB		 4865{
4866 struct drm_device *dev = crtc->dev;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
4868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4869 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4870 int pipe = intel_crtc->pipe;
80824003 4871 int plane = intel_crtc->plane;
c751ce4f 4872 int refclk, num_connectors = 0;
652c393a 4873 intel_clock_t clock, reduced_clock;
84b046f3 4874 u32 dspcntr;
a16af721 4875 bool ok, has_reduced_clock = false;
e9fd1c02 4876 bool is_lvds = false, is_dsi = false;
5eddb70b 4877 struct intel_encoder *encoder;
d4906093 4878 const intel_limit_t *limit;
5c3b82e2 4879 int ret;
79e53945 4880
6c2b7c12 4881 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4882 switch (encoder->type) {
79e53945
JB		 4883 case INTEL_OUTPUT_LVDS:
4884 is_lvds = true;
4885 break;
e9fd1c02
JN		 4886 case INTEL_OUTPUT_DSI:
4887 is_dsi = true;
4888 break;
79e53945 4889 }
43565a06 4890
c751ce4f 4891 num_connectors++;
79e53945
JB		 4892 }
4893
c65d77d8 4894 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4895
65ce4bf5 4896 if (!is_dsi && !intel_crtc->config.clock_set) {
e9fd1c02
JN		 4897 /*
4898 * Returns a set of divisors for the desired target clock with
4899 * the given refclk, or FALSE. The returned values represent
4900 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4901 * 2) / p1 / p2.
4902 */
4903 limit = intel_limit(crtc, refclk);
4904 ok = dev_priv->display.find_dpll(limit, crtc,
4905 intel_crtc->config.port_clock,
4906 refclk, NULL, &clock);
4907 if (!ok && !intel_crtc->config.clock_set) {
4908 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4909 return -EINVAL;
4910 }
79e53945
JB		 4911 }
4912
cda4b7d3 4913 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4914 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4915
e9fd1c02 4916 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4917 /*
4918 * Ensure we match the reduced clock's P to the target clock.
4919 * If the clocks don't match, we can't switch the display clock
4920 * by using the FP0/FP1. In such case we will disable the LVDS
4921 * downclock feature.
4922 */
65ce4bf5 4923 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4924 has_reduced_clock =
4925 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4926 dev_priv->lvds_downclock,
ee9300bb 4927 refclk, &clock,
5eddb70b 4928 &reduced_clock);
7026d4ac 4929 }
f47709a9
DV		 4930 /* Compat-code for transition, will disappear. */
4931 if (!intel_crtc->config.clock_set) {
4932 intel_crtc->config.dpll.n = clock.n;
4933 intel_crtc->config.dpll.m1 = clock.m1;
4934 intel_crtc->config.dpll.m2 = clock.m2;
4935 intel_crtc->config.dpll.p1 = clock.p1;
4936 intel_crtc->config.dpll.p2 = clock.p2;
4937 }
7026d4ac 4938
e9fd1c02 4939 if (IS_GEN2(dev)) {
8a654f3b 4940 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4941 has_reduced_clock ? &reduced_clock : NULL,
4942 num_connectors);
e9fd1c02
JN		 4943 } else if (IS_VALLEYVIEW(dev)) {
4944 if (!is_dsi)
4945 vlv_update_pll(intel_crtc);
4946 } else {
f47709a9 4947 i9xx_update_pll(intel_crtc,
eb1cbe48 4948 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4949 num_connectors);
e9fd1c02 4950 }
79e53945 4951
79e53945
JB		 4952 /* Set up the display plane register */
4953 dspcntr = DISPPLANE_GAMMA_ENABLE;
4954
da6ecc5d
JB		 4955 if (!IS_VALLEYVIEW(dev)) {
4956 if (pipe == 0)
4957 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4958 else
4959 dspcntr |= DISPPLANE_SEL_PIPE_B;
4960 }
79e53945 4961
8a654f3b 4962 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4963
4964 /* pipesrc and dspsize control the size that is scaled from,
4965 * which should always be the user's requested size.
79e53945 4966 */
929c77fb
EA		 4967 I915_WRITE(DSPSIZE(plane),
4968 ((mode->vdisplay - 1) << 16) |
4969 (mode->hdisplay - 1));
4970 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4971
84b046f3
DV		 4972 i9xx_set_pipeconf(intel_crtc);
4973
f564048e
EA		 4974 I915_WRITE(DSPCNTR(plane), dspcntr);
4975 POSTING_READ(DSPCNTR(plane));
4976
94352cf9 4977 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 4978
f564048e
EA		 4979 return ret;
4980}
4981
2fa2fe9a
DV		 4982static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4983 struct intel_crtc_config *pipe_config)
4984{
4985 struct drm_device *dev = crtc->base.dev;
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987 uint32_t tmp;
4988
4989 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4990 if (!(tmp & PFIT_ENABLE))
4991 return;
2fa2fe9a 4992
06922821 4993 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 4994 if (INTEL_INFO(dev)->gen < 4) {
4995 if (crtc->pipe != PIPE_B)
4996 return;
2fa2fe9a
DV		 4997 } else {
4998 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4999 return;
5000 }
5001
06922821 5002 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5003 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5004 if (INTEL_INFO(dev)->gen < 5)
5005 pipe_config->gmch_pfit.lvds_border_bits =
5006 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5007}
5008
0e8ffe1b
DV		 5009static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5010 struct intel_crtc_config *pipe_config)
5011{
5012 struct drm_device *dev = crtc->base.dev;
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014 uint32_t tmp;
5015
e143a21c 5016 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5017 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5018
0e8ffe1b
DV		 5019 tmp = I915_READ(PIPECONF(crtc->pipe));
5020 if (!(tmp & PIPECONF_ENABLE))
5021 return false;
5022
42571aef
VS		 5023 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5024 switch (tmp & PIPECONF_BPC_MASK) {
5025 case PIPECONF_6BPC:
5026 pipe_config->pipe_bpp = 18;
5027 break;
5028 case PIPECONF_8BPC:
5029 pipe_config->pipe_bpp = 24;
5030 break;
5031 case PIPECONF_10BPC:
5032 pipe_config->pipe_bpp = 30;
5033 break;
5034 default:
5035 break;
5036 }
5037 }
5038
1bd1bd80
DV		 5039 intel_get_pipe_timings(crtc, pipe_config);
5040
2fa2fe9a
DV		 5041 i9xx_get_pfit_config(crtc, pipe_config);
5042
6c49f241
DV		 5043 if (INTEL_INFO(dev)->gen >= 4) {
5044 tmp = I915_READ(DPLL_MD(crtc->pipe));
5045 pipe_config->pixel_multiplier =
5046 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5047 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5048 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5049 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5050 tmp = I915_READ(DPLL(crtc->pipe));
5051 pipe_config->pixel_multiplier =
5052 ((tmp & SDVO_MULTIPLIER_MASK)
5053 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5054 } else {
5055 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5056 * port and will be fixed up in the encoder->get_config
5057 * function. */
5058 pipe_config->pixel_multiplier = 1;
5059 }
8bcc2795
DV		 5060 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5061 if (!IS_VALLEYVIEW(dev)) {
5062 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5063 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5064 } else {
5065 /* Mask out read-only status bits. */
5066 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5067 DPLL_PORTC_READY_MASK |
5068 DPLL_PORTB_READY_MASK);
8bcc2795 5069 }
6c49f241 5070
18442d08
VS		 5071 i9xx_crtc_clock_get(crtc, pipe_config);
5072
0e8ffe1b
DV		 5073 return true;
5074}
5075
dde86e2d 5076static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5077{
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5080 struct intel_encoder *encoder;
74cfd7ac 5081 u32 val, final;
13d83a67 5082 bool has_lvds = false;
199e5d79 5083 bool has_cpu_edp = false;
199e5d79 5084 bool has_panel = false;
99eb6a01
KP		 5085 bool has_ck505 = false;
5086 bool can_ssc = false;
13d83a67
JB		 5087
5088 /* We need to take the global config into account */
199e5d79
KP		 5089 list_for_each_entry(encoder, &mode_config->encoder_list,
5090 base.head) {
5091 switch (encoder->type) {
5092 case INTEL_OUTPUT_LVDS:
5093 has_panel = true;
5094 has_lvds = true;
5095 break;
5096 case INTEL_OUTPUT_EDP:
5097 has_panel = true;
2de6905f 5098 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5099 has_cpu_edp = true;
5100 break;
13d83a67
JB		 5101 }
5102 }
5103
99eb6a01 5104 if (HAS_PCH_IBX(dev)) {
41aa3448 5105 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5106 can_ssc = has_ck505;
5107 } else {
5108 has_ck505 = false;
5109 can_ssc = true;
5110 }
5111
2de6905f
ID		 5112 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5113 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5114
5115 /* Ironlake: try to setup display ref clock before DPLL
5116 * enabling. This is only under driver's control after
5117 * PCH B stepping, previous chipset stepping should be
5118 * ignoring this setting.
5119 */
74cfd7ac
CW		 5120 val = I915_READ(PCH_DREF_CONTROL);
5121
5122 /* As we must carefully and slowly disable/enable each source in turn,
5123 * compute the final state we want first and check if we need to
5124 * make any changes at all.
5125 */
5126 final = val;
5127 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5128 if (has_ck505)
5129 final |= DREF_NONSPREAD_CK505_ENABLE;
5130 else
5131 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5132
5133 final &= ~DREF_SSC_SOURCE_MASK;
5134 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5135 final &= ~DREF_SSC1_ENABLE;
5136
5137 if (has_panel) {
5138 final |= DREF_SSC_SOURCE_ENABLE;
5139
5140 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5141 final |= DREF_SSC1_ENABLE;
5142
5143 if (has_cpu_edp) {
5144 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5145 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5146 else
5147 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5148 } else
5149 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5150 } else {
5151 final |= DREF_SSC_SOURCE_DISABLE;
5152 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5153 }
5154
5155 if (final == val)
5156 return;
5157
13d83a67 5158 /* Always enable nonspread source */
74cfd7ac 5159 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5160
99eb6a01 5161 if (has_ck505)
74cfd7ac 5162 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5163 else
74cfd7ac 5164 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5165
199e5d79 5166 if (has_panel) {
74cfd7ac
CW		 5167 val &= ~DREF_SSC_SOURCE_MASK;
5168 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5169
199e5d79 5170 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5171 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5172 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5173 val |= DREF_SSC1_ENABLE;
e77166b5 5174 } else
74cfd7ac 5175 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5176
5177 /* Get SSC going before enabling the outputs */
74cfd7ac 5178 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5179 POSTING_READ(PCH_DREF_CONTROL);
5180 udelay(200);
5181
74cfd7ac 5182 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5183
5184 /* Enable CPU source on CPU attached eDP */
199e5d79 5185 if (has_cpu_edp) {
99eb6a01 5186 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5187 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5188 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5189 }
13d83a67 5190 else
74cfd7ac 5191 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5192 } else
74cfd7ac 5193 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5194
74cfd7ac 5195 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5196 POSTING_READ(PCH_DREF_CONTROL);
5197 udelay(200);
5198 } else {
5199 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5200
74cfd7ac 5201 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5202
5203 /* Turn off CPU output */
74cfd7ac 5204 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5205
74cfd7ac 5206 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5207 POSTING_READ(PCH_DREF_CONTROL);
5208 udelay(200);
5209
5210 /* Turn off the SSC source */
74cfd7ac
CW		 5211 val &= ~DREF_SSC_SOURCE_MASK;
5212 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5213
5214 /* Turn off SSC1 */
74cfd7ac 5215 val &= ~DREF_SSC1_ENABLE;
199e5d79 5216
74cfd7ac 5217 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5218 POSTING_READ(PCH_DREF_CONTROL);
5219 udelay(200);
5220 }
74cfd7ac
CW		 5221
5222 BUG_ON(val != final);
13d83a67
JB		 5223}
5224
f31f2d55 5225static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5226{
f31f2d55 5227 uint32_t tmp;
dde86e2d 5228
0ff066a9
PZ		 5229 tmp = I915_READ(SOUTH_CHICKEN2);
5230 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5231 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5232
0ff066a9
PZ		 5233 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5234 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5235 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5236
0ff066a9
PZ		 5237 tmp = I915_READ(SOUTH_CHICKEN2);
5238 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5239 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5240
0ff066a9
PZ		 5241 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5242 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5243 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5244}
5245
5246/* WaMPhyProgramming:hsw */
5247static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5248{
5249 uint32_t tmp;
dde86e2d
PZ		 5250
5251 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5252 tmp &= ~(0xFF << 24);
5253 tmp |= (0x12 << 24);
5254 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5255
dde86e2d
PZ		 5256 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5257 tmp |= (1 << 11);
5258 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5259
5260 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5261 tmp |= (1 << 11);
5262 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5263
dde86e2d
PZ		 5264 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5265 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5266 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5267
5268 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5269 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5270 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5271
0ff066a9
PZ		 5272 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5273 tmp &= ~(7 << 13);
5274 tmp |= (5 << 13);
5275 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5276
0ff066a9
PZ		 5277 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5278 tmp &= ~(7 << 13);
5279 tmp |= (5 << 13);
5280 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5281
5282 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5283 tmp &= ~0xFF;
5284 tmp |= 0x1C;
5285 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5286
5287 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5288 tmp &= ~0xFF;
5289 tmp |= 0x1C;
5290 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5291
5292 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5293 tmp &= ~(0xFF << 16);
5294 tmp |= (0x1C << 16);
5295 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5296
5297 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5298 tmp &= ~(0xFF << 16);
5299 tmp |= (0x1C << 16);
5300 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5301
0ff066a9
PZ		 5302 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5303 tmp |= (1 << 27);
5304 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5305
0ff066a9
PZ		 5306 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5307 tmp |= (1 << 27);
5308 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5309
0ff066a9
PZ		 5310 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5311 tmp &= ~(0xF << 28);
5312 tmp |= (4 << 28);
5313 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5314
0ff066a9
PZ		 5315 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5316 tmp &= ~(0xF << 28);
5317 tmp |= (4 << 28);
5318 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5319}
5320
2fa86a1f
PZ		 5321/* Implements 3 different sequences from BSpec chapter "Display iCLK
5322 * Programming" based on the parameters passed:
5323 * - Sequence to enable CLKOUT_DP
5324 * - Sequence to enable CLKOUT_DP without spread
5325 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5326 */
5327static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5328 bool with_fdi)
f31f2d55
PZ		 5329{
5330 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5331 uint32_t reg, tmp;
5332
5333 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5334 with_spread = true;
5335 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5336 with_fdi, "LP PCH doesn't have FDI\n"))
5337 with_fdi = false;
f31f2d55
PZ		 5338
5339 mutex_lock(&dev_priv->dpio_lock);
5340
5341 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5342 tmp &= ~SBI_SSCCTL_DISABLE;
5343 tmp |= SBI_SSCCTL_PATHALT;
5344 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5345
5346 udelay(24);
5347
2fa86a1f
PZ		 5348 if (with_spread) {
5349 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5350 tmp &= ~SBI_SSCCTL_PATHALT;
5351 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5352
2fa86a1f
PZ		 5353 if (with_fdi) {
5354 lpt_reset_fdi_mphy(dev_priv);
5355 lpt_program_fdi_mphy(dev_priv);
5356 }
5357 }
dde86e2d 5358
2fa86a1f
PZ		 5359 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5360 SBI_GEN0 : SBI_DBUFF0;
5361 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5362 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5363 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5364
5365 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5366}
5367
47701c3b
PZ		 5368/* Sequence to disable CLKOUT_DP */
5369static void lpt_disable_clkout_dp(struct drm_device *dev)
5370{
5371 struct drm_i915_private *dev_priv = dev->dev_private;
5372 uint32_t reg, tmp;
5373
5374 mutex_lock(&dev_priv->dpio_lock);
5375
5376 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5377 SBI_GEN0 : SBI_DBUFF0;
5378 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5379 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5380 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5381
5382 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5383 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5384 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5385 tmp |= SBI_SSCCTL_PATHALT;
5386 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5387 udelay(32);
5388 }
5389 tmp |= SBI_SSCCTL_DISABLE;
5390 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5391 }
5392
5393 mutex_unlock(&dev_priv->dpio_lock);
5394}
5395
bf8fa3d3
PZ		 5396static void lpt_init_pch_refclk(struct drm_device *dev)
5397{
5398 struct drm_mode_config *mode_config = &dev->mode_config;
5399 struct intel_encoder *encoder;
5400 bool has_vga = false;
5401
5402 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5403 switch (encoder->type) {
5404 case INTEL_OUTPUT_ANALOG:
5405 has_vga = true;
5406 break;
5407 }
5408 }
5409
47701c3b
PZ		 5410 if (has_vga)
5411 lpt_enable_clkout_dp(dev, true, true);
5412 else
5413 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5414}
5415
dde86e2d
PZ		 5416/*
5417 * Initialize reference clocks when the driver loads
5418 */
5419void intel_init_pch_refclk(struct drm_device *dev)
5420{
5421 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5422 ironlake_init_pch_refclk(dev);
5423 else if (HAS_PCH_LPT(dev))
5424 lpt_init_pch_refclk(dev);
5425}
5426
d9d444cb
JB		 5427static int ironlake_get_refclk(struct drm_crtc *crtc)
5428{
5429 struct drm_device *dev = crtc->dev;
5430 struct drm_i915_private *dev_priv = dev->dev_private;
5431 struct intel_encoder *encoder;
d9d444cb
JB		 5432 int num_connectors = 0;
5433 bool is_lvds = false;
5434
6c2b7c12 5435 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5436 switch (encoder->type) {
5437 case INTEL_OUTPUT_LVDS:
5438 is_lvds = true;
5439 break;
d9d444cb
JB		 5440 }
5441 num_connectors++;
5442 }
5443
5444 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5445 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5446 dev_priv->vbt.lvds_ssc_freq);
5447 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5448 }
5449
5450 return 120000;
5451}
5452
6ff93609 5453static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5454{
c8203565 5455 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5457 int pipe = intel_crtc->pipe;
c8203565
PZ		 5458 uint32_t val;
5459
78114071 5460 val = 0;
c8203565 5461
965e0c48 5462 switch (intel_crtc->config.pipe_bpp) {
c8203565 5463 case 18:
dfd07d72 5464 val |= PIPECONF_6BPC;
c8203565
PZ		 5465 break;
5466 case 24:
dfd07d72 5467 val |= PIPECONF_8BPC;
c8203565
PZ		 5468 break;
5469 case 30:
dfd07d72 5470 val |= PIPECONF_10BPC;
c8203565
PZ		 5471 break;
5472 case 36:
dfd07d72 5473 val |= PIPECONF_12BPC;
c8203565
PZ		 5474 break;
5475 default:
cc769b62
PZ		 5476 /* Case prevented by intel_choose_pipe_bpp_dither. */
5477 BUG();
c8203565
PZ		 5478 }
5479
d8b32247 5480 if (intel_crtc->config.dither)
c8203565
PZ		 5481 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5482
6ff93609 5483 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5484 val |= PIPECONF_INTERLACED_ILK;
5485 else
5486 val |= PIPECONF_PROGRESSIVE;
5487
50f3b016 5488 if (intel_crtc->config.limited_color_range)
3685a8f3 5489 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5490
c8203565
PZ		 5491 I915_WRITE(PIPECONF(pipe), val);
5492 POSTING_READ(PIPECONF(pipe));
5493}
5494
86d3efce
VS		 5495/*
5496 * Set up the pipe CSC unit.
5497 *
5498 * Currently only full range RGB to limited range RGB conversion
5499 * is supported, but eventually this should handle various
5500 * RGB<->YCbCr scenarios as well.
5501 */
50f3b016 5502static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5503{
5504 struct drm_device *dev = crtc->dev;
5505 struct drm_i915_private *dev_priv = dev->dev_private;
5506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5507 int pipe = intel_crtc->pipe;
5508 uint16_t coeff = 0x7800; /* 1.0 */
5509
5510 /*
5511 * TODO: Check what kind of values actually come out of the pipe
5512 * with these coeff/postoff values and adjust to get the best
5513 * accuracy. Perhaps we even need to take the bpc value into
5514 * consideration.
5515 */
5516
50f3b016 5517 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5518 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5519
5520 /*
5521 * GY/GU and RY/RU should be the other way around according
5522 * to BSpec, but reality doesn't agree. Just set them up in
5523 * a way that results in the correct picture.
5524 */
5525 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5526 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5527
5528 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5529 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5530
5531 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5532 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5533
5534 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5535 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5536 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5537
5538 if (INTEL_INFO(dev)->gen > 6) {
5539 uint16_t postoff = 0;
5540
50f3b016 5541 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5542 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5543
5544 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5545 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5546 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5547
5548 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5549 } else {
5550 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5551
50f3b016 5552 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5553 mode |= CSC_BLACK_SCREEN_OFFSET;
5554
5555 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5556 }
5557}
5558
6ff93609 5559static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5560{
5561 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5563 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5564 uint32_t val;
5565
3eff4faa 5566 val = 0;
ee2b0b38 5567
d8b32247 5568 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5569 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5570
6ff93609 5571 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5572 val |= PIPECONF_INTERLACED_ILK;
5573 else
5574 val |= PIPECONF_PROGRESSIVE;
5575
702e7a56
PZ		 5576 I915_WRITE(PIPECONF(cpu_transcoder), val);
5577 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5578
5579 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5580 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5581}
5582
6591c6e4 5583static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5584 intel_clock_t *clock,
5585 bool *has_reduced_clock,
5586 intel_clock_t *reduced_clock)
5587{
5588 struct drm_device *dev = crtc->dev;
5589 struct drm_i915_private *dev_priv = dev->dev_private;
5590 struct intel_encoder *intel_encoder;
5591 int refclk;
d4906093 5592 const intel_limit_t *limit;
a16af721 5593 bool ret, is_lvds = false;
79e53945 5594
6591c6e4
PZ		 5595 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5596 switch (intel_encoder->type) {
79e53945
JB		 5597 case INTEL_OUTPUT_LVDS:
5598 is_lvds = true;
5599 break;
79e53945
JB		 5600 }
5601 }
5602
d9d444cb 5603 refclk = ironlake_get_refclk(crtc);
79e53945 5604
d4906093
ML		 5605 /*
5606 * Returns a set of divisors for the desired target clock with the given
5607 * refclk, or FALSE. The returned values represent the clock equation:
5608 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5609 */
1b894b59 5610 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5611 ret = dev_priv->display.find_dpll(limit, crtc,
5612 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5613 refclk, NULL, clock);
6591c6e4
PZ		 5614 if (!ret)
5615 return false;
cda4b7d3 5616
ddc9003c 5617 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5618 /*
5619 * Ensure we match the reduced clock's P to the target clock.
5620 * If the clocks don't match, we can't switch the display clock
5621 * by using the FP0/FP1. In such case we will disable the LVDS
5622 * downclock feature.
5623 */
ee9300bb
DV		 5624 *has_reduced_clock =
5625 dev_priv->display.find_dpll(limit, crtc,
5626 dev_priv->lvds_downclock,
5627 refclk, clock,
5628 reduced_clock);
652c393a 5629 }
61e9653f 5630
6591c6e4
PZ		 5631 return true;
5632}
5633
01a415fd
DV		 5634static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5635{
5636 struct drm_i915_private *dev_priv = dev->dev_private;
5637 uint32_t temp;
5638
5639 temp = I915_READ(SOUTH_CHICKEN1);
5640 if (temp & FDI_BC_BIFURCATION_SELECT)
5641 return;
5642
5643 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5644 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5645
5646 temp |= FDI_BC_BIFURCATION_SELECT;
5647 DRM_DEBUG_KMS("enabling fdi C rx\n");
5648 I915_WRITE(SOUTH_CHICKEN1, temp);
5649 POSTING_READ(SOUTH_CHICKEN1);
5650}
5651
ebfd86fd 5652static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5653{
5654 struct drm_device *dev = intel_crtc->base.dev;
5655 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5656
5657 switch (intel_crtc->pipe) {
5658 case PIPE_A:
ebfd86fd 5659 break;
01a415fd 5660 case PIPE_B:
ebfd86fd 5661 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5662 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5663 else
5664 cpt_enable_fdi_bc_bifurcation(dev);
5665
ebfd86fd 5666 break;
01a415fd 5667 case PIPE_C:
01a415fd
DV		 5668 cpt_enable_fdi_bc_bifurcation(dev);
5669
ebfd86fd 5670 break;
01a415fd
DV		 5671 default:
5672 BUG();
5673 }
5674}
5675
d4b1931c
PZ		 5676int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5677{
5678 /*
5679 * Account for spread spectrum to avoid
5680 * oversubscribing the link. Max center spread
5681 * is 2.5%; use 5% for safety's sake.
5682 */
5683 u32 bps = target_clock * bpp * 21 / 20;
5684 return bps / (link_bw * 8) + 1;
5685}
5686
7429e9d4 5687static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5688{
7429e9d4 5689 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5690}
5691
de13a2e3 5692static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5693 u32 *fp,
9a7c7890 5694 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5695{
de13a2e3 5696 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5697 struct drm_device *dev = crtc->dev;
5698 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5699 struct intel_encoder *intel_encoder;
5700 uint32_t dpll;
6cc5f341 5701 int factor, num_connectors = 0;
09ede541 5702 bool is_lvds = false, is_sdvo = false;
79e53945 5703
de13a2e3
PZ		 5704 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5705 switch (intel_encoder->type) {
79e53945
JB		 5706 case INTEL_OUTPUT_LVDS:
5707 is_lvds = true;
5708 break;
5709 case INTEL_OUTPUT_SDVO:
7d57382e 5710 case INTEL_OUTPUT_HDMI:
79e53945 5711 is_sdvo = true;
79e53945 5712 break;
79e53945 5713 }
43565a06 5714
c751ce4f 5715 num_connectors++;
79e53945 5716 }
79e53945 5717
c1858123 5718 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5719 factor = 21;
5720 if (is_lvds) {
5721 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5722 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5723 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5724 factor = 25;
09ede541 5725 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5726 factor = 20;
c1858123 5727
7429e9d4 5728 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5729 *fp |= FP_CB_TUNE;
2c07245f 5730
9a7c7890
DV		 5731 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5732 *fp2 |= FP_CB_TUNE;
5733
5eddb70b 5734 dpll = 0;
2c07245f 5735
a07d6787
EA		 5736 if (is_lvds)
5737 dpll |= DPLLB_MODE_LVDS;
5738 else
5739 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5740
ef1b460d
DV		 5741 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5742 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5743
5744 if (is_sdvo)
4a33e48d 5745 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5746 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5747 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5748
a07d6787 5749 /* compute bitmask from p1 value */
7429e9d4 5750 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5751 /* also FPA1 */
7429e9d4 5752 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5753
7429e9d4 5754 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5755 case 5:
5756 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5757 break;
5758 case 7:
5759 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5760 break;
5761 case 10:
5762 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5763 break;
5764 case 14:
5765 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5766 break;
79e53945
JB		 5767 }
5768
b4c09f3b 5769 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5770 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5771 else
5772 dpll |= PLL_REF_INPUT_DREFCLK;
5773
959e16d6 5774 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5775}
5776
5777static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5778 int x, int y,
5779 struct drm_framebuffer *fb)
5780{
5781 struct drm_device *dev = crtc->dev;
5782 struct drm_i915_private *dev_priv = dev->dev_private;
5783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5784 int pipe = intel_crtc->pipe;
5785 int plane = intel_crtc->plane;
5786 int num_connectors = 0;
5787 intel_clock_t clock, reduced_clock;
cbbab5bd 5788 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5789 bool ok, has_reduced_clock = false;
8b47047b 5790 bool is_lvds = false;
de13a2e3 5791 struct intel_encoder *encoder;
e2b78267 5792 struct intel_shared_dpll *pll;
de13a2e3 5793 int ret;
de13a2e3
PZ		 5794
5795 for_each_encoder_on_crtc(dev, crtc, encoder) {
5796 switch (encoder->type) {
5797 case INTEL_OUTPUT_LVDS:
5798 is_lvds = true;
5799 break;
de13a2e3
PZ		 5800 }
5801
5802 num_connectors++;
a07d6787 5803 }
79e53945 5804
5dc5298b
PZ		 5805 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5806 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5807
ff9a6750 5808 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5809 &has_reduced_clock, &reduced_clock);
ee9300bb 5810 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5811 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5812 return -EINVAL;
79e53945 5813 }
f47709a9
DV		 5814 /* Compat-code for transition, will disappear. */
5815 if (!intel_crtc->config.clock_set) {
5816 intel_crtc->config.dpll.n = clock.n;
5817 intel_crtc->config.dpll.m1 = clock.m1;
5818 intel_crtc->config.dpll.m2 = clock.m2;
5819 intel_crtc->config.dpll.p1 = clock.p1;
5820 intel_crtc->config.dpll.p2 = clock.p2;
5821 }
79e53945 5822
de13a2e3
PZ		 5823 /* Ensure that the cursor is valid for the new mode before changing... */
5824 intel_crtc_update_cursor(crtc, true);
5825
5dc5298b 5826 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5827 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5828 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5829 if (has_reduced_clock)
7429e9d4 5830 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5831
7429e9d4 5832 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5833 &fp, &reduced_clock,
5834 has_reduced_clock ? &fp2 : NULL);
5835
959e16d6 5836 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5837 intel_crtc->config.dpll_hw_state.fp0 = fp;
5838 if (has_reduced_clock)
5839 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5840 else
5841 intel_crtc->config.dpll_hw_state.fp1 = fp;
5842
b89a1d39 5843 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5844 if (pll == NULL) {
84f44ce7
VS		 5845 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5846 pipe_name(pipe));
4b645f14
JB		 5847 return -EINVAL;
5848 }
ee7b9f93 5849 } else
e72f9fbf 5850 intel_put_shared_dpll(intel_crtc);
79e53945 5851
03afc4a2
DV		 5852 if (intel_crtc->config.has_dp_encoder)
5853 intel_dp_set_m_n(intel_crtc);
79e53945 5854
bcd644e0
DV		 5855 if (is_lvds && has_reduced_clock && i915_powersave)
5856 intel_crtc->lowfreq_avail = true;
5857 else
5858 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5859
5860 if (intel_crtc->config.has_pch_encoder) {
5861 pll = intel_crtc_to_shared_dpll(intel_crtc);
5862
652c393a
JB		 5863 }
5864
8a654f3b 5865 intel_set_pipe_timings(intel_crtc);
5eddb70b 5866
ca3a0ff8 5867 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5868 intel_cpu_transcoder_set_m_n(intel_crtc,
5869 &intel_crtc->config.fdi_m_n);
5870 }
2c07245f 5871
ebfd86fd
DV		 5872 if (IS_IVYBRIDGE(dev))
5873 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5874
6ff93609 5875 ironlake_set_pipeconf(crtc);
79e53945 5876
a1f9e77e
PZ		 5877 /* Set up the display plane register */
5878 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5879 POSTING_READ(DSPCNTR(plane));
79e53945 5880
94352cf9 5881 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5882
1857e1da 5883 return ret;
79e53945
JB		 5884}
5885
eb14cb74
VS		 5886static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5887 struct intel_link_m_n *m_n)
5888{
5889 struct drm_device *dev = crtc->base.dev;
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891 enum pipe pipe = crtc->pipe;
5892
5893 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5894 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5895 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5896 & ~TU_SIZE_MASK;
5897 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5898 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5899 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5900}
5901
5902static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5903 enum transcoder transcoder,
5904 struct intel_link_m_n *m_n)
72419203
DV		 5905{
5906 struct drm_device *dev = crtc->base.dev;
5907 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74
VS		 5908 enum pipe pipe = crtc->pipe;
5909
5910 if (INTEL_INFO(dev)->gen >= 5) {
5911 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5912 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5913 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5914 & ~TU_SIZE_MASK;
5915 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5916 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5917 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5918 } else {
5919 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5920 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5921 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5922 & ~TU_SIZE_MASK;
5923 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5924 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5925 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5926 }
5927}
5928
5929void intel_dp_get_m_n(struct intel_crtc *crtc,
5930 struct intel_crtc_config *pipe_config)
5931{
5932 if (crtc->config.has_pch_encoder)
5933 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5934 else
5935 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5936 &pipe_config->dp_m_n);
5937}
72419203 5938
eb14cb74
VS		 5939static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5940 struct intel_crtc_config *pipe_config)
5941{
5942 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5943 &pipe_config->fdi_m_n);
72419203
DV		 5944}
5945
2fa2fe9a
DV		 5946static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5947 struct intel_crtc_config *pipe_config)
5948{
5949 struct drm_device *dev = crtc->base.dev;
5950 struct drm_i915_private *dev_priv = dev->dev_private;
5951 uint32_t tmp;
5952
5953 tmp = I915_READ(PF_CTL(crtc->pipe));
5954
5955 if (tmp & PF_ENABLE) {
5956 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5957 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5958
5959 /* We currently do not free assignements of panel fitters on
5960 * ivb/hsw (since we don't use the higher upscaling modes which
5961 * differentiates them) so just WARN about this case for now. */
5962 if (IS_GEN7(dev)) {
5963 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5964 PF_PIPE_SEL_IVB(crtc->pipe));
5965 }
2fa2fe9a 5966 }
79e53945
JB		 5967}
5968
0e8ffe1b
DV		 5969static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5970 struct intel_crtc_config *pipe_config)
5971{
5972 struct drm_device *dev = crtc->base.dev;
5973 struct drm_i915_private *dev_priv = dev->dev_private;
5974 uint32_t tmp;
5975
e143a21c 5976 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5977 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5978
0e8ffe1b
DV		 5979 tmp = I915_READ(PIPECONF(crtc->pipe));
5980 if (!(tmp & PIPECONF_ENABLE))
5981 return false;
5982
42571aef
VS		 5983 switch (tmp & PIPECONF_BPC_MASK) {
5984 case PIPECONF_6BPC:
5985 pipe_config->pipe_bpp = 18;
5986 break;
5987 case PIPECONF_8BPC:
5988 pipe_config->pipe_bpp = 24;
5989 break;
5990 case PIPECONF_10BPC:
5991 pipe_config->pipe_bpp = 30;
5992 break;
5993 case PIPECONF_12BPC:
5994 pipe_config->pipe_bpp = 36;
5995 break;
5996 default:
5997 break;
5998 }
5999
ab9412ba 6000 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6001 struct intel_shared_dpll *pll;
6002
88adfff1
DV		 6003 pipe_config->has_pch_encoder = true;
6004
627eb5a3
DV		 6005 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6006 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6007 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6008
6009 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6010
c0d43d62 6011 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6012 pipe_config->shared_dpll =
6013 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6014 } else {
6015 tmp = I915_READ(PCH_DPLL_SEL);
6016 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6017 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6018 else
6019 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6020 }
66e985c0
DV		 6021
6022 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6023
6024 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6025 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6026
6027 tmp = pipe_config->dpll_hw_state.dpll;
6028 pipe_config->pixel_multiplier =
6029 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6030 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6031
6032 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6033 } else {
6034 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6035 }
6036
1bd1bd80
DV		 6037 intel_get_pipe_timings(crtc, pipe_config);
6038
2fa2fe9a
DV		 6039 ironlake_get_pfit_config(crtc, pipe_config);
6040
0e8ffe1b
DV		 6041 return true;
6042}
6043
be256dc7
PZ		 6044static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6045{
6046 struct drm_device *dev = dev_priv->dev;
6047 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6048 struct intel_crtc *crtc;
6049 unsigned long irqflags;
bd633a7c 6050 uint32_t val;
be256dc7
PZ		 6051
6052 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6053 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6054 pipe_name(crtc->pipe));
6055
6056 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6057 WARN(plls->spll_refcount, "SPLL enabled\n");
6058 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6059 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6060 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6061 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6062 "CPU PWM1 enabled\n");
6063 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6064 "CPU PWM2 enabled\n");
6065 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6066 "PCH PWM1 enabled\n");
6067 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6068 "Utility pin enabled\n");
6069 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6070
6071 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6072 val = I915_READ(DEIMR);
6073 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6074 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6075 val = I915_READ(SDEIMR);
bd633a7c 6076 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6077 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6078 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6079}
6080
6081/*
6082 * This function implements pieces of two sequences from BSpec:
6083 * - Sequence for display software to disable LCPLL
6084 * - Sequence for display software to allow package C8+
6085 * The steps implemented here are just the steps that actually touch the LCPLL
6086 * register. Callers should take care of disabling all the display engine
6087 * functions, doing the mode unset, fixing interrupts, etc.
6088 */
6089void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6090 bool switch_to_fclk, bool allow_power_down)
6091{
6092 uint32_t val;
6093
6094 assert_can_disable_lcpll(dev_priv);
6095
6096 val = I915_READ(LCPLL_CTL);
6097
6098 if (switch_to_fclk) {
6099 val |= LCPLL_CD_SOURCE_FCLK;
6100 I915_WRITE(LCPLL_CTL, val);
6101
6102 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6103 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6104 DRM_ERROR("Switching to FCLK failed\n");
6105
6106 val = I915_READ(LCPLL_CTL);
6107 }
6108
6109 val |= LCPLL_PLL_DISABLE;
6110 I915_WRITE(LCPLL_CTL, val);
6111 POSTING_READ(LCPLL_CTL);
6112
6113 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6114 DRM_ERROR("LCPLL still locked\n");
6115
6116 val = I915_READ(D_COMP);
6117 val |= D_COMP_COMP_DISABLE;
6118 I915_WRITE(D_COMP, val);
6119 POSTING_READ(D_COMP);
6120 ndelay(100);
6121
6122 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6123 DRM_ERROR("D_COMP RCOMP still in progress\n");
6124
6125 if (allow_power_down) {
6126 val = I915_READ(LCPLL_CTL);
6127 val |= LCPLL_POWER_DOWN_ALLOW;
6128 I915_WRITE(LCPLL_CTL, val);
6129 POSTING_READ(LCPLL_CTL);
6130 }
6131}
6132
6133/*
6134 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6135 * source.
6136 */
6137void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6138{
6139 uint32_t val;
6140
6141 val = I915_READ(LCPLL_CTL);
6142
6143 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6144 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6145 return;
6146
215733fa
PZ		 6147 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6148 * we'll hang the machine! */
6149 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6150
be256dc7
PZ		 6151 if (val & LCPLL_POWER_DOWN_ALLOW) {
6152 val &= ~LCPLL_POWER_DOWN_ALLOW;
6153 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6154 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6155 }
6156
6157 val = I915_READ(D_COMP);
6158 val |= D_COMP_COMP_FORCE;
6159 val &= ~D_COMP_COMP_DISABLE;
6160 I915_WRITE(D_COMP, val);
35d8f2eb 6161 POSTING_READ(D_COMP);
be256dc7
PZ		 6162
6163 val = I915_READ(LCPLL_CTL);
6164 val &= ~LCPLL_PLL_DISABLE;
6165 I915_WRITE(LCPLL_CTL, val);
6166
6167 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6168 DRM_ERROR("LCPLL not locked yet\n");
6169
6170 if (val & LCPLL_CD_SOURCE_FCLK) {
6171 val = I915_READ(LCPLL_CTL);
6172 val &= ~LCPLL_CD_SOURCE_FCLK;
6173 I915_WRITE(LCPLL_CTL, val);
6174
6175 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6176 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6177 DRM_ERROR("Switching back to LCPLL failed\n");
6178 }
215733fa
PZ		 6179
6180 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6181}
6182
c67a470b
PZ		 6183void hsw_enable_pc8_work(struct work_struct *__work)
6184{
6185 struct drm_i915_private *dev_priv =
6186 container_of(to_delayed_work(__work), struct drm_i915_private,
6187 pc8.enable_work);
6188 struct drm_device *dev = dev_priv->dev;
6189 uint32_t val;
6190
6191 if (dev_priv->pc8.enabled)
6192 return;
6193
6194 DRM_DEBUG_KMS("Enabling package C8+\n");
6195
6196 dev_priv->pc8.enabled = true;
6197
6198 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6199 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6200 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6201 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6202 }
6203
6204 lpt_disable_clkout_dp(dev);
6205 hsw_pc8_disable_interrupts(dev);
6206 hsw_disable_lcpll(dev_priv, true, true);
6207}
6208
6209static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6210{
6211 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6212 WARN(dev_priv->pc8.disable_count < 1,
6213 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6214
6215 dev_priv->pc8.disable_count--;
6216 if (dev_priv->pc8.disable_count != 0)
6217 return;
6218
6219 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6220 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6221}
6222
6223static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6224{
6225 struct drm_device *dev = dev_priv->dev;
6226 uint32_t val;
6227
6228 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6229 WARN(dev_priv->pc8.disable_count < 0,
6230 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6231
6232 dev_priv->pc8.disable_count++;
6233 if (dev_priv->pc8.disable_count != 1)
6234 return;
6235
6236 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6237 if (!dev_priv->pc8.enabled)
6238 return;
6239
6240 DRM_DEBUG_KMS("Disabling package C8+\n");
6241
6242 hsw_restore_lcpll(dev_priv);
6243 hsw_pc8_restore_interrupts(dev);
6244 lpt_init_pch_refclk(dev);
6245
6246 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6247 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6248 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6249 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6250 }
6251
6252 intel_prepare_ddi(dev);
6253 i915_gem_init_swizzling(dev);
6254 mutex_lock(&dev_priv->rps.hw_lock);
6255 gen6_update_ring_freq(dev);
6256 mutex_unlock(&dev_priv->rps.hw_lock);
6257 dev_priv->pc8.enabled = false;
6258}
6259
6260void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6261{
6262 mutex_lock(&dev_priv->pc8.lock);
6263 __hsw_enable_package_c8(dev_priv);
6264 mutex_unlock(&dev_priv->pc8.lock);
6265}
6266
6267void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6268{
6269 mutex_lock(&dev_priv->pc8.lock);
6270 __hsw_disable_package_c8(dev_priv);
6271 mutex_unlock(&dev_priv->pc8.lock);
6272}
6273
6274static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6275{
6276 struct drm_device *dev = dev_priv->dev;
6277 struct intel_crtc *crtc;
6278 uint32_t val;
6279
6280 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6281 if (crtc->base.enabled)
6282 return false;
6283
6284 /* This case is still possible since we have the i915.disable_power_well
6285 * parameter and also the KVMr or something else might be requesting the
6286 * power well. */
6287 val = I915_READ(HSW_PWR_WELL_DRIVER);
6288 if (val != 0) {
6289 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6290 return false;
6291 }
6292
6293 return true;
6294}
6295
6296/* Since we're called from modeset_global_resources there's no way to
6297 * symmetrically increase and decrease the refcount, so we use
6298 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6299 * or not.
6300 */
6301static void hsw_update_package_c8(struct drm_device *dev)
6302{
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 bool allow;
6305
6306 if (!i915_enable_pc8)
6307 return;
6308
6309 mutex_lock(&dev_priv->pc8.lock);
6310
6311 allow = hsw_can_enable_package_c8(dev_priv);
6312
6313 if (allow == dev_priv->pc8.requirements_met)
6314 goto done;
6315
6316 dev_priv->pc8.requirements_met = allow;
6317
6318 if (allow)
6319 __hsw_enable_package_c8(dev_priv);
6320 else
6321 __hsw_disable_package_c8(dev_priv);
6322
6323done:
6324 mutex_unlock(&dev_priv->pc8.lock);
6325}
6326
6327static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6328{
6329 if (!dev_priv->pc8.gpu_idle) {
6330 dev_priv->pc8.gpu_idle = true;
6331 hsw_enable_package_c8(dev_priv);
6332 }
6333}
6334
6335static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6336{
6337 if (dev_priv->pc8.gpu_idle) {
6338 dev_priv->pc8.gpu_idle = false;
6339 hsw_disable_package_c8(dev_priv);
6340 }
be256dc7
PZ		 6341}
6342
d6dd9eb1
DV		 6343static void haswell_modeset_global_resources(struct drm_device *dev)
6344{
d6dd9eb1
DV		 6345 bool enable = false;
6346 struct intel_crtc *crtc;
d6dd9eb1
DV		 6347
6348 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6349 if (!crtc->base.enabled)
6350 continue;
d6dd9eb1 6351
e7a639c4
DV		 6352 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6353 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6354 enable = true;
6355 }
6356
d6dd9eb1 6357 intel_set_power_well(dev, enable);
c67a470b
PZ		 6358
6359 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6360}
6361
09b4ddf9 6362static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6363 int x, int y,
6364 struct drm_framebuffer *fb)
6365{
6366 struct drm_device *dev = crtc->dev;
6367 struct drm_i915_private *dev_priv = dev->dev_private;
6368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6369 int plane = intel_crtc->plane;
09b4ddf9 6370 int ret;
09b4ddf9 6371
ff9a6750 6372 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6373 return -EINVAL;
6374
09b4ddf9
PZ		 6375 /* Ensure that the cursor is valid for the new mode before changing... */
6376 intel_crtc_update_cursor(crtc, true);
6377
03afc4a2
DV		 6378 if (intel_crtc->config.has_dp_encoder)
6379 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6380
6381 intel_crtc->lowfreq_avail = false;
09b4ddf9 6382
8a654f3b 6383 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6384
ca3a0ff8 6385 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6386 intel_cpu_transcoder_set_m_n(intel_crtc,
6387 &intel_crtc->config.fdi_m_n);
6388 }
09b4ddf9 6389
6ff93609 6390 haswell_set_pipeconf(crtc);
09b4ddf9 6391
50f3b016 6392 intel_set_pipe_csc(crtc);
86d3efce 6393
09b4ddf9 6394 /* Set up the display plane register */
86d3efce 6395 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6396 POSTING_READ(DSPCNTR(plane));
6397
6398 ret = intel_pipe_set_base(crtc, x, y, fb);
6399
1f803ee5 6400 return ret;
79e53945
JB		 6401}
6402
0e8ffe1b
DV		 6403static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6404 struct intel_crtc_config *pipe_config)
6405{
6406 struct drm_device *dev = crtc->base.dev;
6407 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6408 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6409 uint32_t tmp;
6410
e143a21c 6411 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6412 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6413
eccb140b
DV		 6414 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6415 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6416 enum pipe trans_edp_pipe;
6417 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6418 default:
6419 WARN(1, "unknown pipe linked to edp transcoder\n");
6420 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6421 case TRANS_DDI_EDP_INPUT_A_ON:
6422 trans_edp_pipe = PIPE_A;
6423 break;
6424 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6425 trans_edp_pipe = PIPE_B;
6426 break;
6427 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6428 trans_edp_pipe = PIPE_C;
6429 break;
6430 }
6431
6432 if (trans_edp_pipe == crtc->pipe)
6433 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6434 }
6435
b97186f0 6436 if (!intel_display_power_enabled(dev,
eccb140b 6437 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6438 return false;
6439
eccb140b 6440 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6441 if (!(tmp & PIPECONF_ENABLE))
6442 return false;
6443
88adfff1 6444 /*
f196e6be 6445 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6446 * DDI E. So just check whether this pipe is wired to DDI E and whether
6447 * the PCH transcoder is on.
6448 */
eccb140b 6449 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6450 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6451 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6452 pipe_config->has_pch_encoder = true;
6453
627eb5a3
DV		 6454 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6455 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6456 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6457
6458 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6459 }
6460
1bd1bd80
DV		 6461 intel_get_pipe_timings(crtc, pipe_config);
6462
2fa2fe9a
DV		 6463 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6464 if (intel_display_power_enabled(dev, pfit_domain))
6465 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6466
42db64ef
PZ		 6467 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6468 (I915_READ(IPS_CTL) & IPS_ENABLE);
6469
6c49f241
DV		 6470 pipe_config->pixel_multiplier = 1;
6471
0e8ffe1b
DV		 6472 return true;
6473}
6474
f564048e 6475static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6476 int x, int y,
94352cf9 6477 struct drm_framebuffer *fb)
f564048e
EA		 6478{
6479 struct drm_device *dev = crtc->dev;
6480 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6481 struct intel_encoder *encoder;
0b701d27 6482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6483 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6484 int pipe = intel_crtc->pipe;
f564048e
EA		 6485 int ret;
6486
0b701d27 6487 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6488
b8cecdf5
DV		 6489 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6490
79e53945 6491 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6492
9256aa19
DV		 6493 if (ret != 0)
6494 return ret;
6495
6496 for_each_encoder_on_crtc(dev, crtc, encoder) {
6497 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6498 encoder->base.base.id,
6499 drm_get_encoder_name(&encoder->base),
6500 mode->base.id, mode->name);
36f2d1f1 6501 encoder->mode_set(encoder);
9256aa19
DV		 6502 }
6503
6504 return 0;
79e53945
JB		 6505}
6506
3a9627f4
WF		 6507static bool intel_eld_uptodate(struct drm_connector *connector,
6508 int reg_eldv, uint32_t bits_eldv,
6509 int reg_elda, uint32_t bits_elda,
6510 int reg_edid)
6511{
6512 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6513 uint8_t *eld = connector->eld;
6514 uint32_t i;
6515
6516 i = I915_READ(reg_eldv);
6517 i &= bits_eldv;
6518
6519 if (!eld[0])
6520 return !i;
6521
6522 if (!i)
6523 return false;
6524
6525 i = I915_READ(reg_elda);
6526 i &= ~bits_elda;
6527 I915_WRITE(reg_elda, i);
6528
6529 for (i = 0; i < eld[2]; i++)
6530 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6531 return false;
6532
6533 return true;
6534}
6535
e0dac65e
WF		 6536static void g4x_write_eld(struct drm_connector *connector,
6537 struct drm_crtc *crtc)
6538{
6539 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6540 uint8_t *eld = connector->eld;
6541 uint32_t eldv;
6542 uint32_t len;
6543 uint32_t i;
6544
6545 i = I915_READ(G4X_AUD_VID_DID);
6546
6547 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6548 eldv = G4X_ELDV_DEVCL_DEVBLC;
6549 else
6550 eldv = G4X_ELDV_DEVCTG;
6551
3a9627f4
WF		 6552 if (intel_eld_uptodate(connector,
6553 G4X_AUD_CNTL_ST, eldv,
6554 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6555 G4X_HDMIW_HDMIEDID))
6556 return;
6557
e0dac65e
WF		 6558 i = I915_READ(G4X_AUD_CNTL_ST);
6559 i &= ~(eldv | G4X_ELD_ADDR);
6560 len = (i >> 9) & 0x1f; /* ELD buffer size */
6561 I915_WRITE(G4X_AUD_CNTL_ST, i);
6562
6563 if (!eld[0])
6564 return;
6565
6566 len = min_t(uint8_t, eld[2], len);
6567 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6568 for (i = 0; i < len; i++)
6569 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6570
6571 i = I915_READ(G4X_AUD_CNTL_ST);
6572 i |= eldv;
6573 I915_WRITE(G4X_AUD_CNTL_ST, i);
6574}
6575
83358c85
WX		 6576static void haswell_write_eld(struct drm_connector *connector,
6577 struct drm_crtc *crtc)
6578{
6579 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6580 uint8_t *eld = connector->eld;
6581 struct drm_device *dev = crtc->dev;
7b9f35a6 6582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6583 uint32_t eldv;
6584 uint32_t i;
6585 int len;
6586 int pipe = to_intel_crtc(crtc)->pipe;
6587 int tmp;
6588
6589 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6590 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6591 int aud_config = HSW_AUD_CFG(pipe);
6592 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6593
6594
6595 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6596
6597 /* Audio output enable */
6598 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6599 tmp = I915_READ(aud_cntrl_st2);
6600 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6601 I915_WRITE(aud_cntrl_st2, tmp);
6602
6603 /* Wait for 1 vertical blank */
6604 intel_wait_for_vblank(dev, pipe);
6605
6606 /* Set ELD valid state */
6607 tmp = I915_READ(aud_cntrl_st2);
6608 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6609 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6610 I915_WRITE(aud_cntrl_st2, tmp);
6611 tmp = I915_READ(aud_cntrl_st2);
6612 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6613
6614 /* Enable HDMI mode */
6615 tmp = I915_READ(aud_config);
6616 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6617 /* clear N_programing_enable and N_value_index */
6618 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6619 I915_WRITE(aud_config, tmp);
6620
6621 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6622
6623 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6624 intel_crtc->eld_vld = true;
83358c85
WX		 6625
6626 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6627 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6628 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6629 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6630 } else
6631 I915_WRITE(aud_config, 0);
6632
6633 if (intel_eld_uptodate(connector,
6634 aud_cntrl_st2, eldv,
6635 aud_cntl_st, IBX_ELD_ADDRESS,
6636 hdmiw_hdmiedid))
6637 return;
6638
6639 i = I915_READ(aud_cntrl_st2);
6640 i &= ~eldv;
6641 I915_WRITE(aud_cntrl_st2, i);
6642
6643 if (!eld[0])
6644 return;
6645
6646 i = I915_READ(aud_cntl_st);
6647 i &= ~IBX_ELD_ADDRESS;
6648 I915_WRITE(aud_cntl_st, i);
6649 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6650 DRM_DEBUG_DRIVER("port num:%d\n", i);
6651
6652 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6653 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6654 for (i = 0; i < len; i++)
6655 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6656
6657 i = I915_READ(aud_cntrl_st2);
6658 i |= eldv;
6659 I915_WRITE(aud_cntrl_st2, i);
6660
6661}
6662
e0dac65e
WF		 6663static void ironlake_write_eld(struct drm_connector *connector,
6664 struct drm_crtc *crtc)
6665{
6666 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6667 uint8_t *eld = connector->eld;
6668 uint32_t eldv;
6669 uint32_t i;
6670 int len;
6671 int hdmiw_hdmiedid;
b6daa025 6672 int aud_config;
e0dac65e
WF		 6673 int aud_cntl_st;
6674 int aud_cntrl_st2;
9b138a83 6675 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6676
b3f33cbf 6677 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6678 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6679 aud_config = IBX_AUD_CFG(pipe);
6680 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6681 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6682 } else {
9b138a83
WX		 6683 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6684 aud_config = CPT_AUD_CFG(pipe);
6685 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6686 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6687 }
6688
9b138a83 6689 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6690
6691 i = I915_READ(aud_cntl_st);
9b138a83 6692 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6693 if (!i) {
6694 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6695 /* operate blindly on all ports */
1202b4c6
WF		 6696 eldv = IBX_ELD_VALIDB;
6697 eldv |= IBX_ELD_VALIDB << 4;
6698 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6699 } else {
2582a850 6700 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6701 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6702 }
6703
3a9627f4
WF		 6704 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6705 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6706 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6707 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6708 } else
6709 I915_WRITE(aud_config, 0);
e0dac65e 6710
3a9627f4
WF		 6711 if (intel_eld_uptodate(connector,
6712 aud_cntrl_st2, eldv,
6713 aud_cntl_st, IBX_ELD_ADDRESS,
6714 hdmiw_hdmiedid))
6715 return;
6716
e0dac65e
WF		 6717 i = I915_READ(aud_cntrl_st2);
6718 i &= ~eldv;
6719 I915_WRITE(aud_cntrl_st2, i);
6720
6721 if (!eld[0])
6722 return;
6723
e0dac65e 6724 i = I915_READ(aud_cntl_st);
1202b4c6 6725 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6726 I915_WRITE(aud_cntl_st, i);
6727
6728 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6729 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6730 for (i = 0; i < len; i++)
6731 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6732
6733 i = I915_READ(aud_cntrl_st2);
6734 i |= eldv;
6735 I915_WRITE(aud_cntrl_st2, i);
6736}
6737
6738void intel_write_eld(struct drm_encoder *encoder,
6739 struct drm_display_mode *mode)
6740{
6741 struct drm_crtc *crtc = encoder->crtc;
6742 struct drm_connector *connector;
6743 struct drm_device *dev = encoder->dev;
6744 struct drm_i915_private *dev_priv = dev->dev_private;
6745
6746 connector = drm_select_eld(encoder, mode);
6747 if (!connector)
6748 return;
6749
6750 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6751 connector->base.id,
6752 drm_get_connector_name(connector),
6753 connector->encoder->base.id,
6754 drm_get_encoder_name(connector->encoder));
6755
6756 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6757
6758 if (dev_priv->display.write_eld)
6759 dev_priv->display.write_eld(connector, crtc);
6760}
6761
79e53945
JB		 6762/** Loads the palette/gamma unit for the CRTC with the prepared values */
6763void intel_crtc_load_lut(struct drm_crtc *crtc)
6764{
6765 struct drm_device *dev = crtc->dev;
6766 struct drm_i915_private *dev_priv = dev->dev_private;
6767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6768 enum pipe pipe = intel_crtc->pipe;
6769 int palreg = PALETTE(pipe);
79e53945 6770 int i;
42db64ef 6771 bool reenable_ips = false;
79e53945
JB		 6772
6773 /* The clocks have to be on to load the palette. */
aed3f09d 6774 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6775 return;
6776
23538ef1
JN		 6777 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6778 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6779 assert_dsi_pll_enabled(dev_priv);
6780 else
6781 assert_pll_enabled(dev_priv, pipe);
6782 }
14420bd0 6783
f2b115e6 6784 /* use legacy palette for Ironlake */
bad720ff 6785 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6786 palreg = LGC_PALETTE(pipe);
6787
6788 /* Workaround : Do not read or write the pipe palette/gamma data while
6789 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6790 */
6791 if (intel_crtc->config.ips_enabled &&
6792 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6793 GAMMA_MODE_MODE_SPLIT)) {
6794 hsw_disable_ips(intel_crtc);
6795 reenable_ips = true;
6796 }
2c07245f 6797
79e53945
JB		 6798 for (i = 0; i < 256; i++) {
6799 I915_WRITE(palreg + 4 * i,
6800 (intel_crtc->lut_r[i] << 16) |
6801 (intel_crtc->lut_g[i] << 8) |
6802 intel_crtc->lut_b[i]);
6803 }
42db64ef
PZ		 6804
6805 if (reenable_ips)
6806 hsw_enable_ips(intel_crtc);
79e53945
JB		 6807}
6808
560b85bb
CW		 6809static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6810{
6811 struct drm_device *dev = crtc->dev;
6812 struct drm_i915_private *dev_priv = dev->dev_private;
6813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6814 bool visible = base != 0;
6815 u32 cntl;
6816
6817 if (intel_crtc->cursor_visible == visible)
6818 return;
6819
9db4a9c7 6820 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6821 if (visible) {
6822 /* On these chipsets we can only modify the base whilst
6823 * the cursor is disabled.
6824 */
9db4a9c7 6825 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6826
6827 cntl &= ~(CURSOR_FORMAT_MASK);
6828 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6829 cntl |= CURSOR_ENABLE |
6830 CURSOR_GAMMA_ENABLE |
6831 CURSOR_FORMAT_ARGB;
6832 } else
6833 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6834 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6835
6836 intel_crtc->cursor_visible = visible;
6837}
6838
6839static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6840{
6841 struct drm_device *dev = crtc->dev;
6842 struct drm_i915_private *dev_priv = dev->dev_private;
6843 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6844 int pipe = intel_crtc->pipe;
6845 bool visible = base != 0;
6846
6847 if (intel_crtc->cursor_visible != visible) {
548f245b 6848 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6849 if (base) {
6850 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6851 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6852 cntl |= pipe << 28; /* Connect to correct pipe */
6853 } else {
6854 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6855 cntl |= CURSOR_MODE_DISABLE;
6856 }
9db4a9c7 6857 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6858
6859 intel_crtc->cursor_visible = visible;
6860 }
6861 /* and commit changes on next vblank */
9db4a9c7 6862 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6863}
6864
65a21cd6
JB		 6865static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6866{
6867 struct drm_device *dev = crtc->dev;
6868 struct drm_i915_private *dev_priv = dev->dev_private;
6869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6870 int pipe = intel_crtc->pipe;
6871 bool visible = base != 0;
6872
6873 if (intel_crtc->cursor_visible != visible) {
6874 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6875 if (base) {
6876 cntl &= ~CURSOR_MODE;
6877 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6878 } else {
6879 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6880 cntl |= CURSOR_MODE_DISABLE;
6881 }
1f5d76db 6882 if (IS_HASWELL(dev)) {
86d3efce 6883 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6884 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6885 }
65a21cd6
JB		 6886 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6887
6888 intel_crtc->cursor_visible = visible;
6889 }
6890 /* and commit changes on next vblank */
6891 I915_WRITE(CURBASE_IVB(pipe), base);
6892}
6893
cda4b7d3 6894/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6895static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6896 bool on)
cda4b7d3
CW		 6897{
6898 struct drm_device *dev = crtc->dev;
6899 struct drm_i915_private *dev_priv = dev->dev_private;
6900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6901 int pipe = intel_crtc->pipe;
6902 int x = intel_crtc->cursor_x;
6903 int y = intel_crtc->cursor_y;
560b85bb 6904 u32 base, pos;
cda4b7d3
CW		 6905 bool visible;
6906
6907 pos = 0;
6908
6b383a7f 6909 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6910 base = intel_crtc->cursor_addr;
6911 if (x > (int) crtc->fb->width)
6912 base = 0;
6913
6914 if (y > (int) crtc->fb->height)
6915 base = 0;
6916 } else
6917 base = 0;
6918
6919 if (x < 0) {
6920 if (x + intel_crtc->cursor_width < 0)
6921 base = 0;
6922
6923 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6924 x = -x;
6925 }
6926 pos |= x << CURSOR_X_SHIFT;
6927
6928 if (y < 0) {
6929 if (y + intel_crtc->cursor_height < 0)
6930 base = 0;
6931
6932 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6933 y = -y;
6934 }
6935 pos |= y << CURSOR_Y_SHIFT;
6936
6937 visible = base != 0;
560b85bb 6938 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6939 return;
6940
0cd83aa9 6941 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6942 I915_WRITE(CURPOS_IVB(pipe), pos);
6943 ivb_update_cursor(crtc, base);
6944 } else {
6945 I915_WRITE(CURPOS(pipe), pos);
6946 if (IS_845G(dev) || IS_I865G(dev))
6947 i845_update_cursor(crtc, base);
6948 else
6949 i9xx_update_cursor(crtc, base);
6950 }
cda4b7d3
CW		 6951}
6952
79e53945 6953static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6954 struct drm_file *file,
79e53945
JB		 6955 uint32_t handle,
6956 uint32_t width, uint32_t height)
6957{
6958 struct drm_device *dev = crtc->dev;
6959 struct drm_i915_private *dev_priv = dev->dev_private;
6960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6961 struct drm_i915_gem_object *obj;
cda4b7d3 6962 uint32_t addr;
3f8bc370 6963 int ret;
79e53945 6964
79e53945
JB		 6965 /* if we want to turn off the cursor ignore width and height */
6966 if (!handle) {
28c97730 6967 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6968 addr = 0;
05394f39 6969 obj = NULL;
5004417d 6970 mutex_lock(&dev->struct_mutex);
3f8bc370 6971 goto finish;
79e53945
JB		 6972 }
6973
6974 /* Currently we only support 64x64 cursors */
6975 if (width != 64 || height != 64) {
6976 DRM_ERROR("we currently only support 64x64 cursors\n");
6977 return -EINVAL;
6978 }
6979
05394f39 6980 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6981 if (&obj->base == NULL)
79e53945
JB		 6982 return -ENOENT;
6983
05394f39 6984 if (obj->base.size < width * height * 4) {
79e53945 6985 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6986 ret = -ENOMEM;
6987 goto fail;
79e53945
JB		 6988 }
6989
71acb5eb 6990 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6991 mutex_lock(&dev->struct_mutex);
b295d1b6 6992 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6993 unsigned alignment;
6994
d9e86c0e
CW		 6995 if (obj->tiling_mode) {
6996 DRM_ERROR("cursor cannot be tiled\n");
6997 ret = -EINVAL;
6998 goto fail_locked;
6999 }
7000
693db184
CW		 7001 /* Note that the w/a also requires 2 PTE of padding following
7002 * the bo. We currently fill all unused PTE with the shadow
7003 * page and so we should always have valid PTE following the
7004 * cursor preventing the VT-d warning.
7005 */
7006 alignment = 0;
7007 if (need_vtd_wa(dev))
7008 alignment = 64*1024;
7009
7010 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7011 if (ret) {
7012 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7013 goto fail_locked;
e7b526bb
CW		 7014 }
7015
d9e86c0e
CW		 7016 ret = i915_gem_object_put_fence(obj);
7017 if (ret) {
2da3b9b9 7018 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7019 goto fail_unpin;
7020 }
7021
f343c5f6 7022 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7023 } else {
6eeefaf3 7024 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7025 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7026 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7027 align);
71acb5eb
DA		 7028 if (ret) {
7029 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7030 goto fail_locked;
71acb5eb 7031 }
05394f39 7032 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7033 }
7034
a6c45cf0 7035 if (IS_GEN2(dev))
14b60391
JB		 7036 I915_WRITE(CURSIZE, (height << 12) | width);
7037
3f8bc370 7038 finish:
3f8bc370 7039 if (intel_crtc->cursor_bo) {
b295d1b6 7040 if (dev_priv->info->cursor_needs_physical) {
05394f39 7041 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7042 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7043 } else
cc98b413 7044 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7045 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7046 }
80824003 7047
7f9872e0 7048 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7049
7050 intel_crtc->cursor_addr = addr;
05394f39 7051 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7052 intel_crtc->cursor_width = width;
7053 intel_crtc->cursor_height = height;
7054
40ccc72b 7055 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7056
79e53945 7057 return 0;
e7b526bb 7058fail_unpin:
cc98b413 7059 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7060fail_locked:
34b8686e 7061 mutex_unlock(&dev->struct_mutex);
bc9025bd 7062fail:
05394f39 7063 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7064 return ret;
79e53945
JB		 7065}
7066
7067static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7068{
79e53945 7069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7070
cda4b7d3
CW		 7071 intel_crtc->cursor_x = x;
7072 intel_crtc->cursor_y = y;
652c393a 7073
40ccc72b 7074 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7075
7076 return 0;
7077}
7078
7079/** Sets the color ramps on behalf of RandR */
7080void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7081 u16 blue, int regno)
7082{
7083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7084
7085 intel_crtc->lut_r[regno] = red >> 8;
7086 intel_crtc->lut_g[regno] = green >> 8;
7087 intel_crtc->lut_b[regno] = blue >> 8;
7088}
7089
b8c00ac5
DA		 7090void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7091 u16 *blue, int regno)
7092{
7093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7094
7095 *red = intel_crtc->lut_r[regno] << 8;
7096 *green = intel_crtc->lut_g[regno] << 8;
7097 *blue = intel_crtc->lut_b[regno] << 8;
7098}
7099
79e53945 7100static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7101 u16 *blue, uint32_t start, uint32_t size)
79e53945 7102{
7203425a 7103 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7105
7203425a 7106 for (i = start; i < end; i++) {
79e53945
JB		 7107 intel_crtc->lut_r[i] = red[i] >> 8;
7108 intel_crtc->lut_g[i] = green[i] >> 8;
7109 intel_crtc->lut_b[i] = blue[i] >> 8;
7110 }
7111
7112 intel_crtc_load_lut(crtc);
7113}
7114
79e53945
JB		 7115/* VESA 640x480x72Hz mode to set on the pipe */
7116static struct drm_display_mode load_detect_mode = {
7117 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7118 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7119};
7120
d2dff872
CW		 7121static struct drm_framebuffer *
7122intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7123 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7124 struct drm_i915_gem_object *obj)
7125{
7126 struct intel_framebuffer *intel_fb;
7127 int ret;
7128
7129 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7130 if (!intel_fb) {
7131 drm_gem_object_unreference_unlocked(&obj->base);
7132 return ERR_PTR(-ENOMEM);
7133 }
7134
7135 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7136 if (ret) {
7137 drm_gem_object_unreference_unlocked(&obj->base);
7138 kfree(intel_fb);
7139 return ERR_PTR(ret);
7140 }
7141
7142 return &intel_fb->base;
7143}
7144
7145static u32
7146intel_framebuffer_pitch_for_width(int width, int bpp)
7147{
7148 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7149 return ALIGN(pitch, 64);
7150}
7151
7152static u32
7153intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7154{
7155 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7156 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7157}
7158
7159static struct drm_framebuffer *
7160intel_framebuffer_create_for_mode(struct drm_device *dev,
7161 struct drm_display_mode *mode,
7162 int depth, int bpp)
7163{
7164 struct drm_i915_gem_object *obj;
0fed39bd 7165 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7166
7167 obj = i915_gem_alloc_object(dev,
7168 intel_framebuffer_size_for_mode(mode, bpp));
7169 if (obj == NULL)
7170 return ERR_PTR(-ENOMEM);
7171
7172 mode_cmd.width = mode->hdisplay;
7173 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7174 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7175 bpp);
5ca0c34a 7176 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7177
7178 return intel_framebuffer_create(dev, &mode_cmd, obj);
7179}
7180
7181static struct drm_framebuffer *
7182mode_fits_in_fbdev(struct drm_device *dev,
7183 struct drm_display_mode *mode)
7184{
7185 struct drm_i915_private *dev_priv = dev->dev_private;
7186 struct drm_i915_gem_object *obj;
7187 struct drm_framebuffer *fb;
7188
7189 if (dev_priv->fbdev == NULL)
7190 return NULL;
7191
7192 obj = dev_priv->fbdev->ifb.obj;
7193 if (obj == NULL)
7194 return NULL;
7195
7196 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7197 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7198 fb->bits_per_pixel))
d2dff872
CW		 7199 return NULL;
7200
01f2c773 7201 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7202 return NULL;
7203
7204 return fb;
7205}
7206
d2434ab7 7207bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7208 struct drm_display_mode *mode,
8261b191 7209 struct intel_load_detect_pipe *old)
79e53945
JB		 7210{
7211 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7212 struct intel_encoder *intel_encoder =
7213 intel_attached_encoder(connector);
79e53945 7214 struct drm_crtc *possible_crtc;
4ef69c7a 7215 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7216 struct drm_crtc *crtc = NULL;
7217 struct drm_device *dev = encoder->dev;
94352cf9 7218 struct drm_framebuffer *fb;
79e53945
JB		 7219 int i = -1;
7220
d2dff872
CW		 7221 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7222 connector->base.id, drm_get_connector_name(connector),
7223 encoder->base.id, drm_get_encoder_name(encoder));
7224
79e53945
JB		 7225 /*
7226 * Algorithm gets a little messy:
7a5e4805 7227 *
79e53945
JB		 7228 * - if the connector already has an assigned crtc, use it (but make
7229 * sure it's on first)
7a5e4805 7230 *
79e53945
JB		 7231 * - try to find the first unused crtc that can drive this connector,
7232 * and use that if we find one
79e53945
JB		 7233 */
7234
7235 /* See if we already have a CRTC for this connector */
7236 if (encoder->crtc) {
7237 crtc = encoder->crtc;
8261b191 7238
7b24056b
DV		 7239 mutex_lock(&crtc->mutex);
7240
24218aac 7241 old->dpms_mode = connector->dpms;
8261b191
CW		 7242 old->load_detect_temp = false;
7243
7244 /* Make sure the crtc and connector are running */
24218aac
DV		 7245 if (connector->dpms != DRM_MODE_DPMS_ON)
7246 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7247
7173188d 7248 return true;
79e53945
JB		 7249 }
7250
7251 /* Find an unused one (if possible) */
7252 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7253 i++;
7254 if (!(encoder->possible_crtcs & (1 << i)))
7255 continue;
7256 if (!possible_crtc->enabled) {
7257 crtc = possible_crtc;
7258 break;
7259 }
79e53945
JB		 7260 }
7261
7262 /*
7263 * If we didn't find an unused CRTC, don't use any.
7264 */
7265 if (!crtc) {
7173188d
CW		 7266 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7267 return false;
79e53945
JB		 7268 }
7269
7b24056b 7270 mutex_lock(&crtc->mutex);
fc303101
DV		 7271 intel_encoder->new_crtc = to_intel_crtc(crtc);
7272 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7273
7274 intel_crtc = to_intel_crtc(crtc);
24218aac 7275 old->dpms_mode = connector->dpms;
8261b191 7276 old->load_detect_temp = true;
d2dff872 7277 old->release_fb = NULL;
79e53945 7278
6492711d
CW		 7279 if (!mode)
7280 mode = &load_detect_mode;
79e53945 7281
d2dff872
CW		 7282 /* We need a framebuffer large enough to accommodate all accesses
7283 * that the plane may generate whilst we perform load detection.
7284 * We can not rely on the fbcon either being present (we get called
7285 * during its initialisation to detect all boot displays, or it may
7286 * not even exist) or that it is large enough to satisfy the
7287 * requested mode.
7288 */
94352cf9
DV		 7289 fb = mode_fits_in_fbdev(dev, mode);
7290 if (fb == NULL) {
d2dff872 7291 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7292 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7293 old->release_fb = fb;
d2dff872
CW		 7294 } else
7295 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7296 if (IS_ERR(fb)) {
d2dff872 7297 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7298 mutex_unlock(&crtc->mutex);
0e8b3d3e 7299 return false;
79e53945 7300 }
79e53945 7301
c0c36b94 7302 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7303 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7304 if (old->release_fb)
7305 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7306 mutex_unlock(&crtc->mutex);
0e8b3d3e 7307 return false;
79e53945 7308 }
7173188d 7309
79e53945 7310 /* let the connector get through one full cycle before testing */
9d0498a2 7311 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7312 return true;
79e53945
JB		 7313}
7314
d2434ab7 7315void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7316 struct intel_load_detect_pipe *old)
79e53945 7317{
d2434ab7
DV		 7318 struct intel_encoder *intel_encoder =
7319 intel_attached_encoder(connector);
4ef69c7a 7320 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7321 struct drm_crtc *crtc = encoder->crtc;
79e53945 7322
d2dff872
CW		 7323 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7324 connector->base.id, drm_get_connector_name(connector),
7325 encoder->base.id, drm_get_encoder_name(encoder));
7326
8261b191 7327 if (old->load_detect_temp) {
fc303101
DV		 7328 to_intel_connector(connector)->new_encoder = NULL;
7329 intel_encoder->new_crtc = NULL;
7330 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7331
36206361
DV		 7332 if (old->release_fb) {
7333 drm_framebuffer_unregister_private(old->release_fb);
7334 drm_framebuffer_unreference(old->release_fb);
7335 }
d2dff872 7336
67c96400 7337 mutex_unlock(&crtc->mutex);
0622a53c 7338 return;
79e53945
JB		 7339 }
7340
c751ce4f 7341 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7342 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7343 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7344
7345 mutex_unlock(&crtc->mutex);
79e53945
JB		 7346}
7347
da4a1efa
VS		 7348static int i9xx_pll_refclk(struct drm_device *dev,
7349 const struct intel_crtc_config *pipe_config)
7350{
7351 struct drm_i915_private *dev_priv = dev->dev_private;
7352 u32 dpll = pipe_config->dpll_hw_state.dpll;
7353
7354 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7355 return dev_priv->vbt.lvds_ssc_freq * 1000;
7356 else if (HAS_PCH_SPLIT(dev))
7357 return 120000;
7358 else if (!IS_GEN2(dev))
7359 return 96000;
7360 else
7361 return 48000;
7362}
7363
79e53945 7364/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7365static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7366 struct intel_crtc_config *pipe_config)
79e53945 7367{
f1f644dc 7368 struct drm_device *dev = crtc->base.dev;
79e53945 7369 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7370 int pipe = pipe_config->cpu_transcoder;
293623f7 7371 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7372 u32 fp;
7373 intel_clock_t clock;
da4a1efa 7374 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7375
7376 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7377 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7378 else
293623f7 7379 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7380
7381 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7382 if (IS_PINEVIEW(dev)) {
7383 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7384 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7385 } else {
7386 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7387 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7388 }
7389
a6c45cf0 7390 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7391 if (IS_PINEVIEW(dev))
7392 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7393 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7394 else
7395 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7396 DPLL_FPA01_P1_POST_DIV_SHIFT);
7397
7398 switch (dpll & DPLL_MODE_MASK) {
7399 case DPLLB_MODE_DAC_SERIAL:
7400 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7401 5 : 10;
7402 break;
7403 case DPLLB_MODE_LVDS:
7404 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7405 7 : 14;
7406 break;
7407 default:
28c97730 7408 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7409 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7410 return;
79e53945
JB		 7411 }
7412
ac58c3f0 7413 if (IS_PINEVIEW(dev))
da4a1efa 7414 pineview_clock(refclk, &clock);
ac58c3f0 7415 else
da4a1efa 7416 i9xx_clock(refclk, &clock);
79e53945
JB		 7417 } else {
7418 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7419
7420 if (is_lvds) {
7421 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7422 DPLL_FPA01_P1_POST_DIV_SHIFT);
7423 clock.p2 = 14;
79e53945
JB		 7424 } else {
7425 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7426 clock.p1 = 2;
7427 else {
7428 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7429 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7430 }
7431 if (dpll & PLL_P2_DIVIDE_BY_4)
7432 clock.p2 = 4;
7433 else
7434 clock.p2 = 2;
79e53945 7435 }
da4a1efa
VS		 7436
7437 i9xx_clock(refclk, &clock);
79e53945
JB		 7438 }
7439
18442d08
VS		 7440 /*
7441 * This value includes pixel_multiplier. We will use
7442 * port_clock to compute adjusted_mode.clock in the
7443 * encoder's get_config() function.
7444 */
7445 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7446}
7447
6878da05
VS		 7448int intel_dotclock_calculate(int link_freq,
7449 const struct intel_link_m_n *m_n)
f1f644dc 7450{
f1f644dc
JB		 7451 /*
7452 * The calculation for the data clock is:
1041a02f 7453 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7454 * But we want to avoid losing precison if possible, so:
1041a02f 7455 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7456 *
7457 * and the link clock is simpler:
1041a02f 7458 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7459 */
7460
6878da05
VS		 7461 if (!m_n->link_n)
7462 return 0;
7463
7464 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7465}
7466
18442d08
VS		 7467static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7468 struct intel_crtc_config *pipe_config)
6878da05
VS		 7469{
7470 struct drm_device *dev = crtc->base.dev;
18442d08
VS		 7471
7472 /* read out port_clock from the DPLL */
7473 i9xx_crtc_clock_get(crtc, pipe_config);
6878da05 7474
f1f644dc 7475 /*
18442d08
VS		 7476 * This value does not include pixel_multiplier.
7477 * We will check that port_clock and adjusted_mode.clock
7478 * agree once we know their relationship in the encoder's
7479 * get_config() function.
79e53945 7480 */
18442d08
VS		 7481 pipe_config->adjusted_mode.clock =
7482 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7483 &pipe_config->fdi_m_n);
79e53945
JB		 7484}
7485
7486/** Returns the currently programmed mode of the given pipe. */
7487struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7488 struct drm_crtc *crtc)
7489{
548f245b 7490 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7492 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7493 struct drm_display_mode *mode;
f1f644dc 7494 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7495 int htot = I915_READ(HTOTAL(cpu_transcoder));
7496 int hsync = I915_READ(HSYNC(cpu_transcoder));
7497 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7498 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7499 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7500
7501 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7502 if (!mode)
7503 return NULL;
7504
f1f644dc
JB		 7505 /*
7506 * Construct a pipe_config sufficient for getting the clock info
7507 * back out of crtc_clock_get.
7508 *
7509 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7510 * to use a real value here instead.
7511 */
293623f7 7512 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7513 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7514 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7515 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7516 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7517 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7518
7519 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7520 mode->hdisplay = (htot & 0xffff) + 1;
7521 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7522 mode->hsync_start = (hsync & 0xffff) + 1;
7523 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7524 mode->vdisplay = (vtot & 0xffff) + 1;
7525 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7526 mode->vsync_start = (vsync & 0xffff) + 1;
7527 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7528
7529 drm_mode_set_name(mode);
79e53945
JB		 7530
7531 return mode;
7532}
7533
3dec0095 7534static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7535{
7536 struct drm_device *dev = crtc->dev;
7537 drm_i915_private_t *dev_priv = dev->dev_private;
7538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7539 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7540 int dpll_reg = DPLL(pipe);
7541 int dpll;
652c393a 7542
bad720ff 7543 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7544 return;
7545
7546 if (!dev_priv->lvds_downclock_avail)
7547 return;
7548
dbdc6479 7549 dpll = I915_READ(dpll_reg);
652c393a 7550 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7551 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7552
8ac5a6d5 7553 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7554
7555 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7556 I915_WRITE(dpll_reg, dpll);
9d0498a2 7557 intel_wait_for_vblank(dev, pipe);
dbdc6479 7558
652c393a
JB		 7559 dpll = I915_READ(dpll_reg);
7560 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7561 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7562 }
652c393a
JB		 7563}
7564
7565static void intel_decrease_pllclock(struct drm_crtc *crtc)
7566{
7567 struct drm_device *dev = crtc->dev;
7568 drm_i915_private_t *dev_priv = dev->dev_private;
7569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7570
bad720ff 7571 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7572 return;
7573
7574 if (!dev_priv->lvds_downclock_avail)
7575 return;
7576
7577 /*
7578 * Since this is called by a timer, we should never get here in
7579 * the manual case.
7580 */
7581 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7582 int pipe = intel_crtc->pipe;
7583 int dpll_reg = DPLL(pipe);
7584 int dpll;
f6e5b160 7585
44d98a61 7586 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7587
8ac5a6d5 7588 assert_panel_unlocked(dev_priv, pipe);
652c393a 7589
dc257cf1 7590 dpll = I915_READ(dpll_reg);
652c393a
JB		 7591 dpll |= DISPLAY_RATE_SELECT_FPA1;
7592 I915_WRITE(dpll_reg, dpll);
9d0498a2 7593 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7594 dpll = I915_READ(dpll_reg);
7595 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7596 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7597 }
7598
7599}
7600
f047e395
CW		 7601void intel_mark_busy(struct drm_device *dev)
7602{
c67a470b
PZ		 7603 struct drm_i915_private *dev_priv = dev->dev_private;
7604
7605 hsw_package_c8_gpu_busy(dev_priv);
7606 i915_update_gfx_val(dev_priv);
f047e395
CW		 7607}
7608
7609void intel_mark_idle(struct drm_device *dev)
652c393a 7610{
c67a470b 7611 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7612 struct drm_crtc *crtc;
652c393a 7613
c67a470b
PZ		 7614 hsw_package_c8_gpu_idle(dev_priv);
7615
652c393a
JB		 7616 if (!i915_powersave)
7617 return;
7618
652c393a 7619 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7620 if (!crtc->fb)
7621 continue;
7622
725a5b54 7623 intel_decrease_pllclock(crtc);
652c393a 7624 }
652c393a
JB		 7625}
7626
c65355bb
CW		 7627void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7628 struct intel_ring_buffer *ring)
652c393a 7629{
f047e395
CW		 7630 struct drm_device *dev = obj->base.dev;
7631 struct drm_crtc *crtc;
652c393a 7632
f047e395 7633 if (!i915_powersave)
acb87dfb
CW		 7634 return;
7635
652c393a
JB		 7636 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7637 if (!crtc->fb)
7638 continue;
7639
c65355bb
CW		 7640 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7641 continue;
7642
7643 intel_increase_pllclock(crtc);
7644 if (ring && intel_fbc_enabled(dev))
7645 ring->fbc_dirty = true;
652c393a
JB		 7646 }
7647}
7648
79e53945
JB		 7649static void intel_crtc_destroy(struct drm_crtc *crtc)
7650{
7651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7652 struct drm_device *dev = crtc->dev;
7653 struct intel_unpin_work *work;
7654 unsigned long flags;
7655
7656 spin_lock_irqsave(&dev->event_lock, flags);
7657 work = intel_crtc->unpin_work;
7658 intel_crtc->unpin_work = NULL;
7659 spin_unlock_irqrestore(&dev->event_lock, flags);
7660
7661 if (work) {
7662 cancel_work_sync(&work->work);
7663 kfree(work);
7664 }
79e53945 7665
40ccc72b
MK		 7666 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7667
79e53945 7668 drm_crtc_cleanup(crtc);
67e77c5a 7669
79e53945
JB		 7670 kfree(intel_crtc);
7671}
7672
6b95a207
KH		 7673static void intel_unpin_work_fn(struct work_struct *__work)
7674{
7675 struct intel_unpin_work *work =
7676 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7677 struct drm_device *dev = work->crtc->dev;
6b95a207 7678
b4a98e57 7679 mutex_lock(&dev->struct_mutex);
1690e1eb 7680 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7681 drm_gem_object_unreference(&work->pending_flip_obj->base);
7682 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7683
b4a98e57
CW		 7684 intel_update_fbc(dev);
7685 mutex_unlock(&dev->struct_mutex);
7686
7687 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7688 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7689
6b95a207
KH		 7690 kfree(work);
7691}
7692
1afe3e9d 7693static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7694 struct drm_crtc *crtc)
6b95a207
KH		 7695{
7696 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7698 struct intel_unpin_work *work;
6b95a207
KH		 7699 unsigned long flags;
7700
7701 /* Ignore early vblank irqs */
7702 if (intel_crtc == NULL)
7703 return;
7704
7705 spin_lock_irqsave(&dev->event_lock, flags);
7706 work = intel_crtc->unpin_work;
e7d841ca
CW		 7707
7708 /* Ensure we don't miss a work->pending update ... */
7709 smp_rmb();
7710
7711 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7712 spin_unlock_irqrestore(&dev->event_lock, flags);
7713 return;
7714 }
7715
e7d841ca
CW		 7716 /* and that the unpin work is consistent wrt ->pending. */
7717 smp_rmb();
7718
6b95a207 7719 intel_crtc->unpin_work = NULL;
6b95a207 7720
45a066eb
RC		 7721 if (work->event)
7722 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7723
0af7e4df
MK		 7724 drm_vblank_put(dev, intel_crtc->pipe);
7725
6b95a207
KH		 7726 spin_unlock_irqrestore(&dev->event_lock, flags);
7727
2c10d571 7728 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7729
7730 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7731
7732 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7733}
7734
1afe3e9d
JB		 7735void intel_finish_page_flip(struct drm_device *dev, int pipe)
7736{
7737 drm_i915_private_t *dev_priv = dev->dev_private;
7738 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7739
49b14a5c 7740 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7741}
7742
7743void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7744{
7745 drm_i915_private_t *dev_priv = dev->dev_private;
7746 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7747
49b14a5c 7748 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7749}
7750
6b95a207
KH		 7751void intel_prepare_page_flip(struct drm_device *dev, int plane)
7752{
7753 drm_i915_private_t *dev_priv = dev->dev_private;
7754 struct intel_crtc *intel_crtc =
7755 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7756 unsigned long flags;
7757
e7d841ca
CW		 7758 /* NB: An MMIO update of the plane base pointer will also
7759 * generate a page-flip completion irq, i.e. every modeset
7760 * is also accompanied by a spurious intel_prepare_page_flip().
7761 */
6b95a207 7762 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7763 if (intel_crtc->unpin_work)
7764 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7765 spin_unlock_irqrestore(&dev->event_lock, flags);
7766}
7767
e7d841ca
CW		 7768inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7769{
7770 /* Ensure that the work item is consistent when activating it ... */
7771 smp_wmb();
7772 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7773 /* and that it is marked active as soon as the irq could fire. */
7774 smp_wmb();
7775}
7776
8c9f3aaf
JB		 7777static int intel_gen2_queue_flip(struct drm_device *dev,
7778 struct drm_crtc *crtc,
7779 struct drm_framebuffer *fb,
ed8d1975
KP		 7780 struct drm_i915_gem_object *obj,
7781 uint32_t flags)
8c9f3aaf
JB		 7782{
7783 struct drm_i915_private *dev_priv = dev->dev_private;
7784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7785 u32 flip_mask;
6d90c952 7786 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7787 int ret;
7788
6d90c952 7789 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7790 if (ret)
83d4092b 7791 goto err;
8c9f3aaf 7792
6d90c952 7793 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7794 if (ret)
83d4092b 7795 goto err_unpin;
8c9f3aaf
JB		 7796
7797 /* Can't queue multiple flips, so wait for the previous
7798 * one to finish before executing the next.
7799 */
7800 if (intel_crtc->plane)
7801 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7802 else
7803 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7804 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7805 intel_ring_emit(ring, MI_NOOP);
7806 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7807 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7808 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7809 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7810 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7811
7812 intel_mark_page_flip_active(intel_crtc);
09246732 7813 __intel_ring_advance(ring);
83d4092b
CW		 7814 return 0;
7815
7816err_unpin:
7817 intel_unpin_fb_obj(obj);
7818err:
8c9f3aaf
JB		 7819 return ret;
7820}
7821
7822static int intel_gen3_queue_flip(struct drm_device *dev,
7823 struct drm_crtc *crtc,
7824 struct drm_framebuffer *fb,
ed8d1975
KP		 7825 struct drm_i915_gem_object *obj,
7826 uint32_t flags)
8c9f3aaf
JB		 7827{
7828 struct drm_i915_private *dev_priv = dev->dev_private;
7829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7830 u32 flip_mask;
6d90c952 7831 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7832 int ret;
7833
6d90c952 7834 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7835 if (ret)
83d4092b 7836 goto err;
8c9f3aaf 7837
6d90c952 7838 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7839 if (ret)
83d4092b 7840 goto err_unpin;
8c9f3aaf
JB		 7841
7842 if (intel_crtc->plane)
7843 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7844 else
7845 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7846 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7847 intel_ring_emit(ring, MI_NOOP);
7848 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7849 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7850 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7851 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7852 intel_ring_emit(ring, MI_NOOP);
7853
e7d841ca 7854 intel_mark_page_flip_active(intel_crtc);
09246732 7855 __intel_ring_advance(ring);
83d4092b
CW		 7856 return 0;
7857
7858err_unpin:
7859 intel_unpin_fb_obj(obj);
7860err:
8c9f3aaf
JB		 7861 return ret;
7862}
7863
7864static int intel_gen4_queue_flip(struct drm_device *dev,
7865 struct drm_crtc *crtc,
7866 struct drm_framebuffer *fb,
ed8d1975
KP		 7867 struct drm_i915_gem_object *obj,
7868 uint32_t flags)
8c9f3aaf
JB		 7869{
7870 struct drm_i915_private *dev_priv = dev->dev_private;
7871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7872 uint32_t pf, pipesrc;
6d90c952 7873 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7874 int ret;
7875
6d90c952 7876 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7877 if (ret)
83d4092b 7878 goto err;
8c9f3aaf 7879
6d90c952 7880 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7881 if (ret)
83d4092b 7882 goto err_unpin;
8c9f3aaf
JB		 7883
7884 /* i965+ uses the linear or tiled offsets from the
7885 * Display Registers (which do not change across a page-flip)
7886 * so we need only reprogram the base address.
7887 */
6d90c952
DV		 7888 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7889 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7890 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7891 intel_ring_emit(ring,
f343c5f6 7892 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7893 obj->tiling_mode);
8c9f3aaf
JB		 7894
7895 /* XXX Enabling the panel-fitter across page-flip is so far
7896 * untested on non-native modes, so ignore it for now.
7897 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7898 */
7899 pf = 0;
7900 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7901 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7902
7903 intel_mark_page_flip_active(intel_crtc);
09246732 7904 __intel_ring_advance(ring);
83d4092b
CW		 7905 return 0;
7906
7907err_unpin:
7908 intel_unpin_fb_obj(obj);
7909err:
8c9f3aaf
JB		 7910 return ret;
7911}
7912
7913static int intel_gen6_queue_flip(struct drm_device *dev,
7914 struct drm_crtc *crtc,
7915 struct drm_framebuffer *fb,
ed8d1975
KP		 7916 struct drm_i915_gem_object *obj,
7917 uint32_t flags)
8c9f3aaf
JB		 7918{
7919 struct drm_i915_private *dev_priv = dev->dev_private;
7920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7921 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7922 uint32_t pf, pipesrc;
7923 int ret;
7924
6d90c952 7925 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7926 if (ret)
83d4092b 7927 goto err;
8c9f3aaf 7928
6d90c952 7929 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7930 if (ret)
83d4092b 7931 goto err_unpin;
8c9f3aaf 7932
6d90c952
DV		 7933 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7934 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7935 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7936 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7937
dc257cf1
DV		 7938 /* Contrary to the suggestions in the documentation,
7939 * "Enable Panel Fitter" does not seem to be required when page
7940 * flipping with a non-native mode, and worse causes a normal
7941 * modeset to fail.
7942 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7943 */
7944 pf = 0;
8c9f3aaf 7945 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7946 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7947
7948 intel_mark_page_flip_active(intel_crtc);
09246732 7949 __intel_ring_advance(ring);
83d4092b
CW		 7950 return 0;
7951
7952err_unpin:
7953 intel_unpin_fb_obj(obj);
7954err:
8c9f3aaf
JB		 7955 return ret;
7956}
7957
7c9017e5
JB		 7958static int intel_gen7_queue_flip(struct drm_device *dev,
7959 struct drm_crtc *crtc,
7960 struct drm_framebuffer *fb,
ed8d1975
KP		 7961 struct drm_i915_gem_object *obj,
7962 uint32_t flags)
7c9017e5
JB		 7963{
7964 struct drm_i915_private *dev_priv = dev->dev_private;
7965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7966 struct intel_ring_buffer *ring;
cb05d8de 7967 uint32_t plane_bit = 0;
ffe74d75
CW		 7968 int len, ret;
7969
7970 ring = obj->ring;
7971 if (ring == NULL || ring->id != RCS)
7972 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7973
7974 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7975 if (ret)
83d4092b 7976 goto err;
7c9017e5 7977
cb05d8de
DV		 7978 switch(intel_crtc->plane) {
7979 case PLANE_A:
7980 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7981 break;
7982 case PLANE_B:
7983 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7984 break;
7985 case PLANE_C:
7986 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7987 break;
7988 default:
7989 WARN_ONCE(1, "unknown plane in flip command\n");
7990 ret = -ENODEV;
ab3951eb 7991 goto err_unpin;
cb05d8de
DV		 7992 }
7993
ffe74d75
CW		 7994 len = 4;
7995 if (ring->id == RCS)
7996 len += 6;
7997
7998 ret = intel_ring_begin(ring, len);
7c9017e5 7999 if (ret)
83d4092b 8000 goto err_unpin;
7c9017e5 8001
ffe74d75
CW		 8002 /* Unmask the flip-done completion message. Note that the bspec says that
8003 * we should do this for both the BCS and RCS, and that we must not unmask
8004 * more than one flip event at any time (or ensure that one flip message
8005 * can be sent by waiting for flip-done prior to queueing new flips).
8006 * Experimentation says that BCS works despite DERRMR masking all
8007 * flip-done completion events and that unmasking all planes at once
8008 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8009 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8010 */
8011 if (ring->id == RCS) {
8012 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8013 intel_ring_emit(ring, DERRMR);
8014 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8015 DERRMR_PIPEB_PRI_FLIP_DONE |
8016 DERRMR_PIPEC_PRI_FLIP_DONE));
8017 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8018 intel_ring_emit(ring, DERRMR);
8019 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8020 }
8021
cb05d8de 8022 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8023 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8024 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8025 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8026
8027 intel_mark_page_flip_active(intel_crtc);
09246732 8028 __intel_ring_advance(ring);
83d4092b
CW		 8029 return 0;
8030
8031err_unpin:
8032 intel_unpin_fb_obj(obj);
8033err:
7c9017e5
JB		 8034 return ret;
8035}
8036
8c9f3aaf
JB		 8037static int intel_default_queue_flip(struct drm_device *dev,
8038 struct drm_crtc *crtc,
8039 struct drm_framebuffer *fb,
ed8d1975
KP		 8040 struct drm_i915_gem_object *obj,
8041 uint32_t flags)
8c9f3aaf
JB		 8042{
8043 return -ENODEV;
8044}
8045
6b95a207
KH		 8046static int intel_crtc_page_flip(struct drm_crtc *crtc,
8047 struct drm_framebuffer *fb,
ed8d1975
KP		 8048 struct drm_pending_vblank_event *event,
8049 uint32_t page_flip_flags)
6b95a207
KH		 8050{
8051 struct drm_device *dev = crtc->dev;
8052 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8053 struct drm_framebuffer *old_fb = crtc->fb;
8054 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8056 struct intel_unpin_work *work;
8c9f3aaf 8057 unsigned long flags;
52e68630 8058 int ret;
6b95a207 8059
e6a595d2
VS		 8060 /* Can't change pixel format via MI display flips. */
8061 if (fb->pixel_format != crtc->fb->pixel_format)
8062 return -EINVAL;
8063
8064 /*
8065 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8066 * Note that pitch changes could also affect these register.
8067 */
8068 if (INTEL_INFO(dev)->gen > 3 &&
8069 (fb->offsets[0] != crtc->fb->offsets[0] ||
8070 fb->pitches[0] != crtc->fb->pitches[0]))
8071 return -EINVAL;
8072
6b95a207
KH		 8073 work = kzalloc(sizeof *work, GFP_KERNEL);
8074 if (work == NULL)
8075 return -ENOMEM;
8076
6b95a207 8077 work->event = event;
b4a98e57 8078 work->crtc = crtc;
4a35f83b 8079 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8080 INIT_WORK(&work->work, intel_unpin_work_fn);
8081
7317c75e
JB		 8082 ret = drm_vblank_get(dev, intel_crtc->pipe);
8083 if (ret)
8084 goto free_work;
8085
6b95a207
KH		 8086 /* We borrow the event spin lock for protecting unpin_work */
8087 spin_lock_irqsave(&dev->event_lock, flags);
8088 if (intel_crtc->unpin_work) {
8089 spin_unlock_irqrestore(&dev->event_lock, flags);
8090 kfree(work);
7317c75e 8091 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8092
8093 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8094 return -EBUSY;
8095 }
8096 intel_crtc->unpin_work = work;
8097 spin_unlock_irqrestore(&dev->event_lock, flags);
8098
b4a98e57
CW		 8099 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8100 flush_workqueue(dev_priv->wq);
8101
79158103
CW		 8102 ret = i915_mutex_lock_interruptible(dev);
8103 if (ret)
8104 goto cleanup;
6b95a207 8105
75dfca80 8106 /* Reference the objects for the scheduled work. */
05394f39
CW		 8107 drm_gem_object_reference(&work->old_fb_obj->base);
8108 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8109
8110 crtc->fb = fb;
96b099fd 8111
e1f99ce6 8112 work->pending_flip_obj = obj;
e1f99ce6 8113
4e5359cd
SF		 8114 work->enable_stall_check = true;
8115
b4a98e57 8116 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8117 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8118
ed8d1975 8119 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8120 if (ret)
8121 goto cleanup_pending;
6b95a207 8122
7782de3b 8123 intel_disable_fbc(dev);
c65355bb 8124 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8125 mutex_unlock(&dev->struct_mutex);
8126
e5510fac
JB		 8127 trace_i915_flip_request(intel_crtc->plane, obj);
8128
6b95a207 8129 return 0;
96b099fd 8130
8c9f3aaf 8131cleanup_pending:
b4a98e57 8132 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8133 crtc->fb = old_fb;
05394f39
CW		 8134 drm_gem_object_unreference(&work->old_fb_obj->base);
8135 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8136 mutex_unlock(&dev->struct_mutex);
8137
79158103 8138cleanup:
96b099fd
CW		 8139 spin_lock_irqsave(&dev->event_lock, flags);
8140 intel_crtc->unpin_work = NULL;
8141 spin_unlock_irqrestore(&dev->event_lock, flags);
8142
7317c75e
JB		 8143 drm_vblank_put(dev, intel_crtc->pipe);
8144free_work:
96b099fd
CW		 8145 kfree(work);
8146
8147 return ret;
6b95a207
KH		 8148}
8149
f6e5b160 8150static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8151 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8152 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8153};
8154
50f56119
DV		 8155static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8156 struct drm_crtc *crtc)
8157{
8158 struct drm_device *dev;
8159 struct drm_crtc *tmp;
8160 int crtc_mask = 1;
47f1c6c9 8161
50f56119 8162 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8163
50f56119 8164 dev = crtc->dev;
47f1c6c9 8165
50f56119
DV		 8166 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8167 if (tmp == crtc)
8168 break;
8169 crtc_mask <<= 1;
8170 }
47f1c6c9 8171
50f56119
DV		 8172 if (encoder->possible_crtcs & crtc_mask)
8173 return true;
8174 return false;
47f1c6c9 8175}
79e53945 8176
9a935856
DV		 8177/**
8178 * intel_modeset_update_staged_output_state
8179 *
8180 * Updates the staged output configuration state, e.g. after we've read out the
8181 * current hw state.
8182 */
8183static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8184{
9a935856
DV		 8185 struct intel_encoder *encoder;
8186 struct intel_connector *connector;
f6e5b160 8187
9a935856
DV		 8188 list_for_each_entry(connector, &dev->mode_config.connector_list,
8189 base.head) {
8190 connector->new_encoder =
8191 to_intel_encoder(connector->base.encoder);
8192 }
f6e5b160 8193
9a935856
DV		 8194 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8195 base.head) {
8196 encoder->new_crtc =
8197 to_intel_crtc(encoder->base.crtc);
8198 }
f6e5b160
CW		 8199}
8200
9a935856
DV		 8201/**
8202 * intel_modeset_commit_output_state
8203 *
8204 * This function copies the stage display pipe configuration to the real one.
8205 */
8206static void intel_modeset_commit_output_state(struct drm_device *dev)
8207{
8208 struct intel_encoder *encoder;
8209 struct intel_connector *connector;
f6e5b160 8210
9a935856
DV		 8211 list_for_each_entry(connector, &dev->mode_config.connector_list,
8212 base.head) {
8213 connector->base.encoder = &connector->new_encoder->base;
8214 }
f6e5b160 8215
9a935856
DV		 8216 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8217 base.head) {
8218 encoder->base.crtc = &encoder->new_crtc->base;
8219 }
8220}
8221
050f7aeb
DV		 8222static void
8223connected_sink_compute_bpp(struct intel_connector * connector,
8224 struct intel_crtc_config *pipe_config)
8225{
8226 int bpp = pipe_config->pipe_bpp;
8227
8228 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8229 connector->base.base.id,
8230 drm_get_connector_name(&connector->base));
8231
8232 /* Don't use an invalid EDID bpc value */
8233 if (connector->base.display_info.bpc &&
8234 connector->base.display_info.bpc * 3 < bpp) {
8235 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8236 bpp, connector->base.display_info.bpc*3);
8237 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8238 }
8239
8240 /* Clamp bpp to 8 on screens without EDID 1.4 */
8241 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8242 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8243 bpp);
8244 pipe_config->pipe_bpp = 24;
8245 }
8246}
8247
4e53c2e0 8248static int
050f7aeb
DV		 8249compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8250 struct drm_framebuffer *fb,
8251 struct intel_crtc_config *pipe_config)
4e53c2e0 8252{
050f7aeb
DV		 8253 struct drm_device *dev = crtc->base.dev;
8254 struct intel_connector *connector;
4e53c2e0
DV		 8255 int bpp;
8256
d42264b1
DV		 8257 switch (fb->pixel_format) {
8258 case DRM_FORMAT_C8:
4e53c2e0
DV		 8259 bpp = 8*3; /* since we go through a colormap */
8260 break;
d42264b1
DV		 8261 case DRM_FORMAT_XRGB1555:
8262 case DRM_FORMAT_ARGB1555:
8263 /* checked in intel_framebuffer_init already */
8264 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8265 return -EINVAL;
8266 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8267 bpp = 6*3; /* min is 18bpp */
8268 break;
d42264b1
DV		 8269 case DRM_FORMAT_XBGR8888:
8270 case DRM_FORMAT_ABGR8888:
8271 /* checked in intel_framebuffer_init already */
8272 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8273 return -EINVAL;
8274 case DRM_FORMAT_XRGB8888:
8275 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8276 bpp = 8*3;
8277 break;
d42264b1
DV		 8278 case DRM_FORMAT_XRGB2101010:
8279 case DRM_FORMAT_ARGB2101010:
8280 case DRM_FORMAT_XBGR2101010:
8281 case DRM_FORMAT_ABGR2101010:
8282 /* checked in intel_framebuffer_init already */
8283 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8284 return -EINVAL;
4e53c2e0
DV		 8285 bpp = 10*3;
8286 break;
baba133a 8287 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8288 default:
8289 DRM_DEBUG_KMS("unsupported depth\n");
8290 return -EINVAL;
8291 }
8292
4e53c2e0
DV		 8293 pipe_config->pipe_bpp = bpp;
8294
8295 /* Clamp display bpp to EDID value */
8296 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8297 base.head) {
1b829e05
DV		 8298 if (!connector->new_encoder ||
8299 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8300 continue;
8301
050f7aeb 8302 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8303 }
8304
8305 return bpp;
8306}
8307
c0b03411
DV		 8308static void intel_dump_pipe_config(struct intel_crtc *crtc,
8309 struct intel_crtc_config *pipe_config,
8310 const char *context)
8311{
8312 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8313 context, pipe_name(crtc->pipe));
8314
8315 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8316 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8317 pipe_config->pipe_bpp, pipe_config->dither);
8318 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8319 pipe_config->has_pch_encoder,
8320 pipe_config->fdi_lanes,
8321 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8322 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8323 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8324 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8325 pipe_config->has_dp_encoder,
8326 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8327 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8328 pipe_config->dp_m_n.tu);
c0b03411
DV		 8329 DRM_DEBUG_KMS("requested mode:\n");
8330 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8331 DRM_DEBUG_KMS("adjusted mode:\n");
8332 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8333 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8334 pipe_config->gmch_pfit.control,
8335 pipe_config->gmch_pfit.pgm_ratios,
8336 pipe_config->gmch_pfit.lvds_border_bits);
8337 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8338 pipe_config->pch_pfit.pos,
8339 pipe_config->pch_pfit.size);
42db64ef 8340 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8341}
8342
accfc0c5
DV		 8343static bool check_encoder_cloning(struct drm_crtc *crtc)
8344{
8345 int num_encoders = 0;
8346 bool uncloneable_encoders = false;
8347 struct intel_encoder *encoder;
8348
8349 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8350 base.head) {
8351 if (&encoder->new_crtc->base != crtc)
8352 continue;
8353
8354 num_encoders++;
8355 if (!encoder->cloneable)
8356 uncloneable_encoders = true;
8357 }
8358
8359 return !(num_encoders > 1 && uncloneable_encoders);
8360}
8361
b8cecdf5
DV		 8362static struct intel_crtc_config *
8363intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8364 struct drm_framebuffer *fb,
b8cecdf5 8365 struct drm_display_mode *mode)
ee7b9f93 8366{
7758a113 8367 struct drm_device *dev = crtc->dev;
7758a113 8368 struct intel_encoder *encoder;
b8cecdf5 8369 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8370 int plane_bpp, ret = -EINVAL;
8371 bool retry = true;
ee7b9f93 8372
accfc0c5
DV		 8373 if (!check_encoder_cloning(crtc)) {
8374 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8375 return ERR_PTR(-EINVAL);
8376 }
8377
b8cecdf5
DV		 8378 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8379 if (!pipe_config)
7758a113
DV		 8380 return ERR_PTR(-ENOMEM);
8381
b8cecdf5
DV		 8382 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8383 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 8384 pipe_config->cpu_transcoder =
8385 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8386 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8387
2960bc9c
ID		 8388 /*
8389 * Sanitize sync polarity flags based on requested ones. If neither
8390 * positive or negative polarity is requested, treat this as meaning
8391 * negative polarity.
8392 */
8393 if (!(pipe_config->adjusted_mode.flags &
8394 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8395 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8396
8397 if (!(pipe_config->adjusted_mode.flags &
8398 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8399 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8400
050f7aeb
DV		 8401 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8402 * plane pixel format and any sink constraints into account. Returns the
8403 * source plane bpp so that dithering can be selected on mismatches
8404 * after encoders and crtc also have had their say. */
8405 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8406 fb, pipe_config);
4e53c2e0
DV		 8407 if (plane_bpp < 0)
8408 goto fail;
8409
e29c22c0 8410encoder_retry:
ef1b460d 8411 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8412 pipe_config->port_clock = 0;
ef1b460d 8413 pipe_config->pixel_multiplier = 1;
ff9a6750 8414
135c81b8
DV		 8415 /* Fill in default crtc timings, allow encoders to overwrite them. */
8416 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8417
7758a113
DV		 8418 /* Pass our mode to the connectors and the CRTC to give them a chance to
8419 * adjust it according to limitations or connector properties, and also
8420 * a chance to reject the mode entirely.
47f1c6c9 8421 */
7758a113
DV		 8422 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8423 base.head) {
47f1c6c9 8424
7758a113
DV		 8425 if (&encoder->new_crtc->base != crtc)
8426 continue;
7ae89233 8427
efea6e8e
DV		 8428 if (!(encoder->compute_config(encoder, pipe_config))) {
8429 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8430 goto fail;
8431 }
ee7b9f93 8432 }
47f1c6c9 8433
ff9a6750
DV		 8434 /* Set default port clock if not overwritten by the encoder. Needs to be
8435 * done afterwards in case the encoder adjusts the mode. */
8436 if (!pipe_config->port_clock)
3c52f4eb
VS		 8437 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8438 pipe_config->pixel_multiplier;
ff9a6750 8439
a43f6e0f 8440 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8441 if (ret < 0) {
7758a113
DV		 8442 DRM_DEBUG_KMS("CRTC fixup failed\n");
8443 goto fail;
ee7b9f93 8444 }
e29c22c0
DV		 8445
8446 if (ret == RETRY) {
8447 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8448 ret = -EINVAL;
8449 goto fail;
8450 }
8451
8452 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8453 retry = false;
8454 goto encoder_retry;
8455 }
8456
4e53c2e0
DV		 8457 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8458 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8459 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8460
b8cecdf5 8461 return pipe_config;
7758a113 8462fail:
b8cecdf5 8463 kfree(pipe_config);
e29c22c0 8464 return ERR_PTR(ret);
ee7b9f93 8465}
47f1c6c9 8466
e2e1ed41
DV		 8467/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8468 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8469static void
8470intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8471 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8472{
8473 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8474 struct drm_device *dev = crtc->dev;
8475 struct intel_encoder *encoder;
8476 struct intel_connector *connector;
8477 struct drm_crtc *tmp_crtc;
79e53945 8478
e2e1ed41 8479 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8480
e2e1ed41
DV		 8481 /* Check which crtcs have changed outputs connected to them, these need
8482 * to be part of the prepare_pipes mask. We don't (yet) support global
8483 * modeset across multiple crtcs, so modeset_pipes will only have one
8484 * bit set at most. */
8485 list_for_each_entry(connector, &dev->mode_config.connector_list,
8486 base.head) {
8487 if (connector->base.encoder == &connector->new_encoder->base)
8488 continue;
79e53945 8489
e2e1ed41
DV		 8490 if (connector->base.encoder) {
8491 tmp_crtc = connector->base.encoder->crtc;
8492
8493 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8494 }
8495
8496 if (connector->new_encoder)
8497 *prepare_pipes |=
8498 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8499 }
8500
e2e1ed41
DV		 8501 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8502 base.head) {
8503 if (encoder->base.crtc == &encoder->new_crtc->base)
8504 continue;
8505
8506 if (encoder->base.crtc) {
8507 tmp_crtc = encoder->base.crtc;
8508
8509 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8510 }
8511
8512 if (encoder->new_crtc)
8513 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8514 }
8515
e2e1ed41
DV		 8516 /* Check for any pipes that will be fully disabled ... */
8517 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8518 base.head) {
8519 bool used = false;
22fd0fab 8520
e2e1ed41
DV		 8521 /* Don't try to disable disabled crtcs. */
8522 if (!intel_crtc->base.enabled)
8523 continue;
7e7d76c3 8524
e2e1ed41
DV		 8525 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8526 base.head) {
8527 if (encoder->new_crtc == intel_crtc)
8528 used = true;
8529 }
8530
8531 if (!used)
8532 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8533 }
8534
e2e1ed41
DV		 8535
8536 /* set_mode is also used to update properties on life display pipes. */
8537 intel_crtc = to_intel_crtc(crtc);
8538 if (crtc->enabled)
8539 *prepare_pipes |= 1 << intel_crtc->pipe;
8540
b6c5164d
DV		 8541 /*
8542 * For simplicity do a full modeset on any pipe where the output routing
8543 * changed. We could be more clever, but that would require us to be
8544 * more careful with calling the relevant encoder->mode_set functions.
8545 */
e2e1ed41
DV		 8546 if (*prepare_pipes)
8547 *modeset_pipes = *prepare_pipes;
8548
8549 /* ... and mask these out. */
8550 *modeset_pipes &= ~(*disable_pipes);
8551 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8552
8553 /*
8554 * HACK: We don't (yet) fully support global modesets. intel_set_config
8555 * obies this rule, but the modeset restore mode of
8556 * intel_modeset_setup_hw_state does not.
8557 */
8558 *modeset_pipes &= 1 << intel_crtc->pipe;
8559 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8560
8561 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8562 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8563}
79e53945 8564
ea9d758d 8565static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8566{
ea9d758d 8567 struct drm_encoder *encoder;
f6e5b160 8568 struct drm_device *dev = crtc->dev;
f6e5b160 8569
ea9d758d
DV		 8570 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8571 if (encoder->crtc == crtc)
8572 return true;
8573
8574 return false;
8575}
8576
8577static void
8578intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8579{
8580 struct intel_encoder *intel_encoder;
8581 struct intel_crtc *intel_crtc;
8582 struct drm_connector *connector;
8583
8584 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8585 base.head) {
8586 if (!intel_encoder->base.crtc)
8587 continue;
8588
8589 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8590
8591 if (prepare_pipes & (1 << intel_crtc->pipe))
8592 intel_encoder->connectors_active = false;
8593 }
8594
8595 intel_modeset_commit_output_state(dev);
8596
8597 /* Update computed state. */
8598 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8599 base.head) {
8600 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8601 }
8602
8603 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8604 if (!connector->encoder || !connector->encoder->crtc)
8605 continue;
8606
8607 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8608
8609 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8610 struct drm_property *dpms_property =
8611 dev->mode_config.dpms_property;
8612
ea9d758d 8613 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8614 drm_object_property_set_value(&connector->base,
68d34720
DV		 8615 dpms_property,
8616 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8617
8618 intel_encoder = to_intel_encoder(connector->encoder);
8619 intel_encoder->connectors_active = true;
8620 }
8621 }
8622
8623}
8624
3bd26263 8625static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8626{
3bd26263 8627 int diff;
f1f644dc
JB		 8628
8629 if (clock1 == clock2)
8630 return true;
8631
8632 if (!clock1 || !clock2)
8633 return false;
8634
8635 diff = abs(clock1 - clock2);
8636
8637 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8638 return true;
8639
8640 return false;
8641}
8642
25c5b266
DV		 8643#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8644 list_for_each_entry((intel_crtc), \
8645 &(dev)->mode_config.crtc_list, \
8646 base.head) \
0973f18f 8647 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8648
0e8ffe1b 8649static bool
2fa2fe9a
DV		 8650intel_pipe_config_compare(struct drm_device *dev,
8651 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8652 struct intel_crtc_config *pipe_config)
8653{
66e985c0
DV		 8654#define PIPE_CONF_CHECK_X(name) \
8655 if (current_config->name != pipe_config->name) { \
8656 DRM_ERROR("mismatch in " #name " " \
8657 "(expected 0x%08x, found 0x%08x)\n", \
8658 current_config->name, \
8659 pipe_config->name); \
8660 return false; \
8661 }
8662
08a24034
DV		 8663#define PIPE_CONF_CHECK_I(name) \
8664 if (current_config->name != pipe_config->name) { \
8665 DRM_ERROR("mismatch in " #name " " \
8666 "(expected %i, found %i)\n", \
8667 current_config->name, \
8668 pipe_config->name); \
8669 return false; \
88adfff1
DV		 8670 }
8671
1bd1bd80
DV		 8672#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8673 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8674 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8675 "(expected %i, found %i)\n", \
8676 current_config->name & (mask), \
8677 pipe_config->name & (mask)); \
8678 return false; \
8679 }
8680
bb760063
DV		 8681#define PIPE_CONF_QUIRK(quirk) \
8682 ((current_config->quirks | pipe_config->quirks) & (quirk))
8683
eccb140b
DV		 8684 PIPE_CONF_CHECK_I(cpu_transcoder);
8685
08a24034
DV		 8686 PIPE_CONF_CHECK_I(has_pch_encoder);
8687 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8688 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8689 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8690 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8691 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8692 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8693
eb14cb74
VS		 8694 PIPE_CONF_CHECK_I(has_dp_encoder);
8695 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8696 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8697 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8698 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8699 PIPE_CONF_CHECK_I(dp_m_n.tu);
8700
1bd1bd80
DV		 8701 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8702 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8703 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8704 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8705 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8706 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8707
8708 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8709 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8710 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8711 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8712 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8713 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8714
c93f54cf 8715 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8716
1bd1bd80
DV		 8717 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8718 DRM_MODE_FLAG_INTERLACE);
8719
bb760063
DV		 8720 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8721 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8722 DRM_MODE_FLAG_PHSYNC);
8723 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8724 DRM_MODE_FLAG_NHSYNC);
8725 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8726 DRM_MODE_FLAG_PVSYNC);
8727 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8728 DRM_MODE_FLAG_NVSYNC);
8729 }
045ac3b5 8730
1bd1bd80
DV		 8731 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8732 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8733
2fa2fe9a
DV		 8734 PIPE_CONF_CHECK_I(gmch_pfit.control);
8735 /* pfit ratios are autocomputed by the hw on gen4+ */
8736 if (INTEL_INFO(dev)->gen < 4)
8737 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8738 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8739 PIPE_CONF_CHECK_I(pch_pfit.pos);
8740 PIPE_CONF_CHECK_I(pch_pfit.size);
8741
42db64ef
PZ		 8742 PIPE_CONF_CHECK_I(ips_enabled);
8743
c0d43d62 8744 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8745 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8746 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8747 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8748 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8749
42571aef
VS		 8750 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8751 PIPE_CONF_CHECK_I(pipe_bpp);
8752
66e985c0 8753#undef PIPE_CONF_CHECK_X
08a24034 8754#undef PIPE_CONF_CHECK_I
1bd1bd80 8755#undef PIPE_CONF_CHECK_FLAGS
bb760063 8756#undef PIPE_CONF_QUIRK
88adfff1 8757
f1f644dc 8758 if (!IS_HASWELL(dev)) {
3bd26263
VS		 8759 if (!intel_fuzzy_clock_check(current_config->adjusted_mode.clock,
8760 pipe_config->adjusted_mode.clock)) {
6f02488e 8761 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8762 current_config->adjusted_mode.clock,
8763 pipe_config->adjusted_mode.clock);
8764 return false;
8765 }
8766 }
8767
0e8ffe1b
DV		 8768 return true;
8769}
8770
91d1b4bd
DV		 8771static void
8772check_connector_state(struct drm_device *dev)
8af6cf88 8773{
8af6cf88
DV		 8774 struct intel_connector *connector;
8775
8776 list_for_each_entry(connector, &dev->mode_config.connector_list,
8777 base.head) {
8778 /* This also checks the encoder/connector hw state with the
8779 * ->get_hw_state callbacks. */
8780 intel_connector_check_state(connector);
8781
8782 WARN(&connector->new_encoder->base != connector->base.encoder,
8783 "connector's staged encoder doesn't match current encoder\n");
8784 }
91d1b4bd
DV		 8785}
8786
8787static void
8788check_encoder_state(struct drm_device *dev)
8789{
8790 struct intel_encoder *encoder;
8791 struct intel_connector *connector;
8af6cf88
DV		 8792
8793 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8794 base.head) {
8795 bool enabled = false;
8796 bool active = false;
8797 enum pipe pipe, tracked_pipe;
8798
8799 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8800 encoder->base.base.id,
8801 drm_get_encoder_name(&encoder->base));
8802
8803 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8804 "encoder's stage crtc doesn't match current crtc\n");
8805 WARN(encoder->connectors_active && !encoder->base.crtc,
8806 "encoder's active_connectors set, but no crtc\n");
8807
8808 list_for_each_entry(connector, &dev->mode_config.connector_list,
8809 base.head) {
8810 if (connector->base.encoder != &encoder->base)
8811 continue;
8812 enabled = true;
8813 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8814 active = true;
8815 }
8816 WARN(!!encoder->base.crtc != enabled,
8817 "encoder's enabled state mismatch "
8818 "(expected %i, found %i)\n",
8819 !!encoder->base.crtc, enabled);
8820 WARN(active && !encoder->base.crtc,
8821 "active encoder with no crtc\n");
8822
8823 WARN(encoder->connectors_active != active,
8824 "encoder's computed active state doesn't match tracked active state "
8825 "(expected %i, found %i)\n", active, encoder->connectors_active);
8826
8827 active = encoder->get_hw_state(encoder, &pipe);
8828 WARN(active != encoder->connectors_active,
8829 "encoder's hw state doesn't match sw tracking "
8830 "(expected %i, found %i)\n",
8831 encoder->connectors_active, active);
8832
8833 if (!encoder->base.crtc)
8834 continue;
8835
8836 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8837 WARN(active && pipe != tracked_pipe,
8838 "active encoder's pipe doesn't match"
8839 "(expected %i, found %i)\n",
8840 tracked_pipe, pipe);
8841
8842 }
91d1b4bd
DV		 8843}
8844
8845static void
8846check_crtc_state(struct drm_device *dev)
8847{
8848 drm_i915_private_t *dev_priv = dev->dev_private;
8849 struct intel_crtc *crtc;
8850 struct intel_encoder *encoder;
8851 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8852
8853 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8854 base.head) {
8855 bool enabled = false;
8856 bool active = false;
8857
045ac3b5
JB		 8858 memset(&pipe_config, 0, sizeof(pipe_config));
8859
8af6cf88
DV		 8860 DRM_DEBUG_KMS("[CRTC:%d]\n",
8861 crtc->base.base.id);
8862
8863 WARN(crtc->active && !crtc->base.enabled,
8864 "active crtc, but not enabled in sw tracking\n");
8865
8866 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8867 base.head) {
8868 if (encoder->base.crtc != &crtc->base)
8869 continue;
8870 enabled = true;
8871 if (encoder->connectors_active)
8872 active = true;
8873 }
6c49f241 8874
8af6cf88
DV		 8875 WARN(active != crtc->active,
8876 "crtc's computed active state doesn't match tracked active state "
8877 "(expected %i, found %i)\n", active, crtc->active);
8878 WARN(enabled != crtc->base.enabled,
8879 "crtc's computed enabled state doesn't match tracked enabled state "
8880 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8881
0e8ffe1b
DV		 8882 active = dev_priv->display.get_pipe_config(crtc,
8883 &pipe_config);
d62cf62a
DV		 8884
8885 /* hw state is inconsistent with the pipe A quirk */
8886 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8887 active = crtc->active;
8888
6c49f241
DV		 8889 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8890 base.head) {
3eaba51c 8891 enum pipe pipe;
6c49f241
DV		 8892 if (encoder->base.crtc != &crtc->base)
8893 continue;
3eaba51c
VS		 8894 if (encoder->get_config &&
8895 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8896 encoder->get_config(encoder, &pipe_config);
8897 }
8898
0e8ffe1b
DV		 8899 WARN(crtc->active != active,
8900 "crtc active state doesn't match with hw state "
8901 "(expected %i, found %i)\n", crtc->active, active);
8902
c0b03411
DV		 8903 if (active &&
8904 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8905 WARN(1, "pipe state doesn't match!\n");
8906 intel_dump_pipe_config(crtc, &pipe_config,
8907 "[hw state]");
8908 intel_dump_pipe_config(crtc, &crtc->config,
8909 "[sw state]");
8910 }
8af6cf88
DV		 8911 }
8912}
8913
91d1b4bd
DV		 8914static void
8915check_shared_dpll_state(struct drm_device *dev)
8916{
8917 drm_i915_private_t *dev_priv = dev->dev_private;
8918 struct intel_crtc *crtc;
8919 struct intel_dpll_hw_state dpll_hw_state;
8920 int i;
5358901f
DV		 8921
8922 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8923 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8924 int enabled_crtcs = 0, active_crtcs = 0;
8925 bool active;
8926
8927 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8928
8929 DRM_DEBUG_KMS("%s\n", pll->name);
8930
8931 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8932
8933 WARN(pll->active > pll->refcount,
8934 "more active pll users than references: %i vs %i\n",
8935 pll->active, pll->refcount);
8936 WARN(pll->active && !pll->on,
8937 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8938 WARN(pll->on && !pll->active,
8939 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8940 WARN(pll->on != active,
8941 "pll on state mismatch (expected %i, found %i)\n",
8942 pll->on, active);
8943
8944 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8945 base.head) {
8946 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8947 enabled_crtcs++;
8948 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8949 active_crtcs++;
8950 }
8951 WARN(pll->active != active_crtcs,
8952 "pll active crtcs mismatch (expected %i, found %i)\n",
8953 pll->active, active_crtcs);
8954 WARN(pll->refcount != enabled_crtcs,
8955 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8956 pll->refcount, enabled_crtcs);
66e985c0
DV		 8957
8958 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8959 sizeof(dpll_hw_state)),
8960 "pll hw state mismatch\n");
5358901f 8961 }
8af6cf88
DV		 8962}
8963
91d1b4bd
DV		 8964void
8965intel_modeset_check_state(struct drm_device *dev)
8966{
8967 check_connector_state(dev);
8968 check_encoder_state(dev);
8969 check_crtc_state(dev);
8970 check_shared_dpll_state(dev);
8971}
8972
18442d08
VS		 8973void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
8974 int dotclock)
8975{
8976 /*
8977 * FDI already provided one idea for the dotclock.
8978 * Yell if the encoder disagrees.
8979 */
8980 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
8981 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
8982 pipe_config->adjusted_mode.clock, dotclock);
8983}
8984
f30da187
DV		 8985static int __intel_set_mode(struct drm_crtc *crtc,
8986 struct drm_display_mode *mode,
8987 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8988{
8989 struct drm_device *dev = crtc->dev;
dbf2b54e 8990 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8991 struct drm_display_mode *saved_mode, *saved_hwmode;
8992 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8993 struct intel_crtc *intel_crtc;
8994 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8995 int ret = 0;
a6778b3c 8996
3ac18232 8997 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8998 if (!saved_mode)
8999 return -ENOMEM;
3ac18232 9000 saved_hwmode = saved_mode + 1;
a6778b3c 9001
e2e1ed41 9002 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9003 &prepare_pipes, &disable_pipes);
9004
3ac18232
TG		 9005 *saved_hwmode = crtc->hwmode;
9006 *saved_mode = crtc->mode;
a6778b3c 9007
25c5b266
DV		 9008 /* Hack: Because we don't (yet) support global modeset on multiple
9009 * crtcs, we don't keep track of the new mode for more than one crtc.
9010 * Hence simply check whether any bit is set in modeset_pipes in all the
9011 * pieces of code that are not yet converted to deal with mutliple crtcs
9012 * changing their mode at the same time. */
25c5b266 9013 if (modeset_pipes) {
4e53c2e0 9014 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9015 if (IS_ERR(pipe_config)) {
9016 ret = PTR_ERR(pipe_config);
9017 pipe_config = NULL;
9018
3ac18232 9019 goto out;
25c5b266 9020 }
c0b03411
DV		 9021 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9022 "[modeset]");
25c5b266 9023 }
a6778b3c 9024
460da916
DV		 9025 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9026 intel_crtc_disable(&intel_crtc->base);
9027
ea9d758d
DV		 9028 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9029 if (intel_crtc->base.enabled)
9030 dev_priv->display.crtc_disable(&intel_crtc->base);
9031 }
a6778b3c 9032
6c4c86f5
DV		 9033 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9034 * to set it here already despite that we pass it down the callchain.
f6e5b160 9035 */
b8cecdf5 9036 if (modeset_pipes) {
25c5b266 9037 crtc->mode = *mode;
b8cecdf5
DV		 9038 /* mode_set/enable/disable functions rely on a correct pipe
9039 * config. */
9040 to_intel_crtc(crtc)->config = *pipe_config;
9041 }
7758a113 9042
ea9d758d
DV		 9043 /* Only after disabling all output pipelines that will be changed can we
9044 * update the the output configuration. */
9045 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9046
47fab737
DV		 9047 if (dev_priv->display.modeset_global_resources)
9048 dev_priv->display.modeset_global_resources(dev);
9049
a6778b3c
DV		 9050 /* Set up the DPLL and any encoders state that needs to adjust or depend
9051 * on the DPLL.
f6e5b160 9052 */
25c5b266 9053 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9054 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9055 x, y, fb);
9056 if (ret)
9057 goto done;
a6778b3c
DV		 9058 }
9059
9060 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9061 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9062 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9063
25c5b266
DV		 9064 if (modeset_pipes) {
9065 /* Store real post-adjustment hardware mode. */
b8cecdf5 9066 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9067
25c5b266
DV		 9068 /* Calculate and store various constants which
9069 * are later needed by vblank and swap-completion
9070 * timestamping. They are derived from true hwmode.
9071 */
9072 drm_calc_timestamping_constants(crtc);
9073 }
a6778b3c
DV		 9074
9075 /* FIXME: add subpixel order */
9076done:
c0c36b94 9077 if (ret && crtc->enabled) {
3ac18232
TG		 9078 crtc->hwmode = *saved_hwmode;
9079 crtc->mode = *saved_mode;
a6778b3c
DV		 9080 }
9081
3ac18232 9082out:
b8cecdf5 9083 kfree(pipe_config);
3ac18232 9084 kfree(saved_mode);
a6778b3c 9085 return ret;
f6e5b160
CW		 9086}
9087
e7457a9a
DL		 9088static int intel_set_mode(struct drm_crtc *crtc,
9089 struct drm_display_mode *mode,
9090 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9091{
9092 int ret;
9093
9094 ret = __intel_set_mode(crtc, mode, x, y, fb);
9095
9096 if (ret == 0)
9097 intel_modeset_check_state(crtc->dev);
9098
9099 return ret;
9100}
9101
c0c36b94
CW		 9102void intel_crtc_restore_mode(struct drm_crtc *crtc)
9103{
9104 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9105}
9106
25c5b266
DV		 9107#undef for_each_intel_crtc_masked
9108
d9e55608
DV		 9109static void intel_set_config_free(struct intel_set_config *config)
9110{
9111 if (!config)
9112 return;
9113
1aa4b628
DV		 9114 kfree(config->save_connector_encoders);
9115 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9116 kfree(config);
9117}
9118
85f9eb71
DV		 9119static int intel_set_config_save_state(struct drm_device *dev,
9120 struct intel_set_config *config)
9121{
85f9eb71
DV		 9122 struct drm_encoder *encoder;
9123 struct drm_connector *connector;
9124 int count;
9125
1aa4b628
DV		 9126 config->save_encoder_crtcs =
9127 kcalloc(dev->mode_config.num_encoder,
9128 sizeof(struct drm_crtc *), GFP_KERNEL);
9129 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9130 return -ENOMEM;
9131
1aa4b628
DV		 9132 config->save_connector_encoders =
9133 kcalloc(dev->mode_config.num_connector,
9134 sizeof(struct drm_encoder *), GFP_KERNEL);
9135 if (!config->save_connector_encoders)
85f9eb71
DV		 9136 return -ENOMEM;
9137
9138 /* Copy data. Note that driver private data is not affected.
9139 * Should anything bad happen only the expected state is
9140 * restored, not the drivers personal bookkeeping.
9141 */
85f9eb71
DV		 9142 count = 0;
9143 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9144 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9145 }
9146
9147 count = 0;
9148 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9149 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9150 }
9151
9152 return 0;
9153}
9154
9155static void intel_set_config_restore_state(struct drm_device *dev,
9156 struct intel_set_config *config)
9157{
9a935856
DV		 9158 struct intel_encoder *encoder;
9159 struct intel_connector *connector;
85f9eb71
DV		 9160 int count;
9161
85f9eb71 9162 count = 0;
9a935856
DV		 9163 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9164 encoder->new_crtc =
9165 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9166 }
9167
9168 count = 0;
9a935856
DV		 9169 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9170 connector->new_encoder =
9171 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9172 }
9173}
9174
e3de42b6 9175static bool
2e57f47d 9176is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9177{
9178 int i;
9179
2e57f47d
CW		 9180 if (set->num_connectors == 0)
9181 return false;
9182
9183 if (WARN_ON(set->connectors == NULL))
9184 return false;
9185
9186 for (i = 0; i < set->num_connectors; i++)
9187 if (set->connectors[i]->encoder &&
9188 set->connectors[i]->encoder->crtc == set->crtc &&
9189 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9190 return true;
9191
9192 return false;
9193}
9194
5e2b584e
DV		 9195static void
9196intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9197 struct intel_set_config *config)
9198{
9199
9200 /* We should be able to check here if the fb has the same properties
9201 * and then just flip_or_move it */
2e57f47d
CW		 9202 if (is_crtc_connector_off(set)) {
9203 config->mode_changed = true;
e3de42b6 9204 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9205 /* If we have no fb then treat it as a full mode set */
9206 if (set->crtc->fb == NULL) {
319d9827
JB		 9207 struct intel_crtc *intel_crtc =
9208 to_intel_crtc(set->crtc);
9209
9210 if (intel_crtc->active && i915_fastboot) {
9211 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9212 config->fb_changed = true;
9213 } else {
9214 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9215 config->mode_changed = true;
9216 }
5e2b584e
DV		 9217 } else if (set->fb == NULL) {
9218 config->mode_changed = true;
72f4901e
DV		 9219 } else if (set->fb->pixel_format !=
9220 set->crtc->fb->pixel_format) {
5e2b584e 9221 config->mode_changed = true;
e3de42b6 9222 } else {
5e2b584e 9223 config->fb_changed = true;
e3de42b6 9224 }
5e2b584e
DV		 9225 }
9226
835c5873 9227 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9228 config->fb_changed = true;
9229
9230 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9231 DRM_DEBUG_KMS("modes are different, full mode set\n");
9232 drm_mode_debug_printmodeline(&set->crtc->mode);
9233 drm_mode_debug_printmodeline(set->mode);
9234 config->mode_changed = true;
9235 }
a1d95703
CW		 9236
9237 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9238 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9239}
9240
2e431051 9241static int
9a935856
DV		 9242intel_modeset_stage_output_state(struct drm_device *dev,
9243 struct drm_mode_set *set,
9244 struct intel_set_config *config)
50f56119 9245{
85f9eb71 9246 struct drm_crtc *new_crtc;
9a935856
DV		 9247 struct intel_connector *connector;
9248 struct intel_encoder *encoder;
f3f08572 9249 int ro;
50f56119 9250
9abdda74 9251 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9252 * of connectors. For paranoia, double-check this. */
9253 WARN_ON(!set->fb && (set->num_connectors != 0));
9254 WARN_ON(set->fb && (set->num_connectors == 0));
9255
9a935856
DV		 9256 list_for_each_entry(connector, &dev->mode_config.connector_list,
9257 base.head) {
9258 /* Otherwise traverse passed in connector list and get encoders
9259 * for them. */
50f56119 9260 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9261 if (set->connectors[ro] == &connector->base) {
9262 connector->new_encoder = connector->encoder;
50f56119
DV		 9263 break;
9264 }
9265 }
9266
9a935856
DV		 9267 /* If we disable the crtc, disable all its connectors. Also, if
9268 * the connector is on the changing crtc but not on the new
9269 * connector list, disable it. */
9270 if ((!set->fb || ro == set->num_connectors) &&
9271 connector->base.encoder &&
9272 connector->base.encoder->crtc == set->crtc) {
9273 connector->new_encoder = NULL;
9274
9275 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9276 connector->base.base.id,
9277 drm_get_connector_name(&connector->base));
9278 }
9279
9280
9281 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9282 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9283 config->mode_changed = true;
50f56119
DV		 9284 }
9285 }
9a935856 9286 /* connector->new_encoder is now updated for all connectors. */
50f56119 9287
9a935856 9288 /* Update crtc of enabled connectors. */
9a935856
DV		 9289 list_for_each_entry(connector, &dev->mode_config.connector_list,
9290 base.head) {
9291 if (!connector->new_encoder)
50f56119
DV		 9292 continue;
9293
9a935856 9294 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9295
9296 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9297 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9298 new_crtc = set->crtc;
9299 }
9300
9301 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9302 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9303 new_crtc)) {
5e2b584e 9304 return -EINVAL;
50f56119 9305 }
9a935856
DV		 9306 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9307
9308 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9309 connector->base.base.id,
9310 drm_get_connector_name(&connector->base),
9311 new_crtc->base.id);
9312 }
9313
9314 /* Check for any encoders that needs to be disabled. */
9315 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9316 base.head) {
9317 list_for_each_entry(connector,
9318 &dev->mode_config.connector_list,
9319 base.head) {
9320 if (connector->new_encoder == encoder) {
9321 WARN_ON(!connector->new_encoder->new_crtc);
9322
9323 goto next_encoder;
9324 }
9325 }
9326 encoder->new_crtc = NULL;
9327next_encoder:
9328 /* Only now check for crtc changes so we don't miss encoders
9329 * that will be disabled. */
9330 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9331 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9332 config->mode_changed = true;
50f56119
DV		 9333 }
9334 }
9a935856 9335 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9336
2e431051
DV		 9337 return 0;
9338}
9339
9340static int intel_crtc_set_config(struct drm_mode_set *set)
9341{
9342 struct drm_device *dev;
2e431051
DV		 9343 struct drm_mode_set save_set;
9344 struct intel_set_config *config;
9345 int ret;
2e431051 9346
8d3e375e
DV		 9347 BUG_ON(!set);
9348 BUG_ON(!set->crtc);
9349 BUG_ON(!set->crtc->helper_private);
2e431051 9350
7e53f3a4
DV		 9351 /* Enforce sane interface api - has been abused by the fb helper. */
9352 BUG_ON(!set->mode && set->fb);
9353 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9354
2e431051
DV		 9355 if (set->fb) {
9356 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9357 set->crtc->base.id, set->fb->base.id,
9358 (int)set->num_connectors, set->x, set->y);
9359 } else {
9360 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9361 }
9362
9363 dev = set->crtc->dev;
9364
9365 ret = -ENOMEM;
9366 config = kzalloc(sizeof(*config), GFP_KERNEL);
9367 if (!config)
9368 goto out_config;
9369
9370 ret = intel_set_config_save_state(dev, config);
9371 if (ret)
9372 goto out_config;
9373
9374 save_set.crtc = set->crtc;
9375 save_set.mode = &set->crtc->mode;
9376 save_set.x = set->crtc->x;
9377 save_set.y = set->crtc->y;
9378 save_set.fb = set->crtc->fb;
9379
9380 /* Compute whether we need a full modeset, only an fb base update or no
9381 * change at all. In the future we might also check whether only the
9382 * mode changed, e.g. for LVDS where we only change the panel fitter in
9383 * such cases. */
9384 intel_set_config_compute_mode_changes(set, config);
9385
9a935856 9386 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9387 if (ret)
9388 goto fail;
9389
5e2b584e 9390 if (config->mode_changed) {
c0c36b94
CW		 9391 ret = intel_set_mode(set->crtc, set->mode,
9392 set->x, set->y, set->fb);
5e2b584e 9393 } else if (config->fb_changed) {
4878cae2
VS		 9394 intel_crtc_wait_for_pending_flips(set->crtc);
9395
4f660f49 9396 ret = intel_pipe_set_base(set->crtc,
94352cf9 9397 set->x, set->y, set->fb);
50f56119
DV		 9398 }
9399
2d05eae1 9400 if (ret) {
bf67dfeb
DV		 9401 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9402 set->crtc->base.id, ret);
50f56119 9403fail:
2d05eae1 9404 intel_set_config_restore_state(dev, config);
50f56119 9405
2d05eae1
CW		 9406 /* Try to restore the config */
9407 if (config->mode_changed &&
9408 intel_set_mode(save_set.crtc, save_set.mode,
9409 save_set.x, save_set.y, save_set.fb))
9410 DRM_ERROR("failed to restore config after modeset failure\n");
9411 }
50f56119 9412
d9e55608
DV		 9413out_config:
9414 intel_set_config_free(config);
50f56119
DV		 9415 return ret;
9416}
f6e5b160
CW		 9417
9418static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9419 .cursor_set = intel_crtc_cursor_set,
9420 .cursor_move = intel_crtc_cursor_move,
9421 .gamma_set = intel_crtc_gamma_set,
50f56119 9422 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9423 .destroy = intel_crtc_destroy,
9424 .page_flip = intel_crtc_page_flip,
9425};
9426
79f689aa
PZ		 9427static void intel_cpu_pll_init(struct drm_device *dev)
9428{
affa9354 9429 if (HAS_DDI(dev))
79f689aa
PZ		 9430 intel_ddi_pll_init(dev);
9431}
9432
5358901f
DV		 9433static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9434 struct intel_shared_dpll *pll,
9435 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9436{
5358901f 9437 uint32_t val;
ee7b9f93 9438
5358901f 9439 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9440 hw_state->dpll = val;
9441 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9442 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9443
9444 return val & DPLL_VCO_ENABLE;
9445}
9446
15bdd4cf
DV		 9447static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9448 struct intel_shared_dpll *pll)
9449{
9450 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9451 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9452}
9453
e7b903d2
DV		 9454static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9455 struct intel_shared_dpll *pll)
9456{
e7b903d2
DV		 9457 /* PCH refclock must be enabled first */
9458 assert_pch_refclk_enabled(dev_priv);
9459
15bdd4cf
DV		 9460 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9461
9462 /* Wait for the clocks to stabilize. */
9463 POSTING_READ(PCH_DPLL(pll->id));
9464 udelay(150);
9465
9466 /* The pixel multiplier can only be updated once the
9467 * DPLL is enabled and the clocks are stable.
9468 *
9469 * So write it again.
9470 */
9471 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9472 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9473 udelay(200);
9474}
9475
9476static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9477 struct intel_shared_dpll *pll)
9478{
9479 struct drm_device *dev = dev_priv->dev;
9480 struct intel_crtc *crtc;
e7b903d2
DV		 9481
9482 /* Make sure no transcoder isn't still depending on us. */
9483 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9484 if (intel_crtc_to_shared_dpll(crtc) == pll)
9485 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9486 }
9487
15bdd4cf
DV		 9488 I915_WRITE(PCH_DPLL(pll->id), 0);
9489 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9490 udelay(200);
9491}
9492
46edb027
DV		 9493static char *ibx_pch_dpll_names[] = {
9494 "PCH DPLL A",
9495 "PCH DPLL B",
9496};
9497
7c74ade1 9498static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9499{
e7b903d2 9500 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9501 int i;
9502
7c74ade1 9503 dev_priv->num_shared_dpll = 2;
ee7b9f93 9504
e72f9fbf 9505 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9506 dev_priv->shared_dplls[i].id = i;
9507 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9508 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9509 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9510 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9511 dev_priv->shared_dplls[i].get_hw_state =
9512 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9513 }
9514}
9515
7c74ade1
DV		 9516static void intel_shared_dpll_init(struct drm_device *dev)
9517{
e7b903d2 9518 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9519
9520 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9521 ibx_pch_dpll_init(dev);
9522 else
9523 dev_priv->num_shared_dpll = 0;
9524
9525 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9526 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9527 dev_priv->num_shared_dpll);
9528}
9529
b358d0a6 9530static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9531{
22fd0fab 9532 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9533 struct intel_crtc *intel_crtc;
9534 int i;
9535
9536 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9537 if (intel_crtc == NULL)
9538 return;
9539
9540 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9541
9542 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9543 for (i = 0; i < 256; i++) {
9544 intel_crtc->lut_r[i] = i;
9545 intel_crtc->lut_g[i] = i;
9546 intel_crtc->lut_b[i] = i;
9547 }
9548
80824003
JB		 9549 /* Swap pipes & planes for FBC on pre-965 */
9550 intel_crtc->pipe = pipe;
9551 intel_crtc->plane = pipe;
e2e767ab 9552 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9553 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9554 intel_crtc->plane = !pipe;
80824003
JB		 9555 }
9556
22fd0fab
JB		 9557 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9558 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9559 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9560 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9561
79e53945 9562 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9563}
9564
08d7b3d1 9565int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9566 struct drm_file *file)
08d7b3d1 9567{
08d7b3d1 9568 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9569 struct drm_mode_object *drmmode_obj;
9570 struct intel_crtc *crtc;
08d7b3d1 9571
1cff8f6b
DV		 9572 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9573 return -ENODEV;
08d7b3d1 9574
c05422d5
DV		 9575 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9576 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9577
c05422d5 9578 if (!drmmode_obj) {
08d7b3d1
CW		 9579 DRM_ERROR("no such CRTC id\n");
9580 return -EINVAL;
9581 }
9582
c05422d5
DV		 9583 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9584 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9585
c05422d5 9586 return 0;
08d7b3d1
CW		 9587}
9588
66a9278e 9589static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9590{
66a9278e
DV		 9591 struct drm_device *dev = encoder->base.dev;
9592 struct intel_encoder *source_encoder;
79e53945 9593 int index_mask = 0;
79e53945
JB		 9594 int entry = 0;
9595
66a9278e
DV		 9596 list_for_each_entry(source_encoder,
9597 &dev->mode_config.encoder_list, base.head) {
9598
9599 if (encoder == source_encoder)
79e53945 9600 index_mask |= (1 << entry);
66a9278e
DV		 9601
9602 /* Intel hw has only one MUX where enocoders could be cloned. */
9603 if (encoder->cloneable && source_encoder->cloneable)
9604 index_mask |= (1 << entry);
9605
79e53945
JB		 9606 entry++;
9607 }
4ef69c7a 9608
79e53945
JB		 9609 return index_mask;
9610}
9611
4d302442
CW		 9612static bool has_edp_a(struct drm_device *dev)
9613{
9614 struct drm_i915_private *dev_priv = dev->dev_private;
9615
9616 if (!IS_MOBILE(dev))
9617 return false;
9618
9619 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9620 return false;
9621
9622 if (IS_GEN5(dev) &&
9623 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9624 return false;
9625
9626 return true;
9627}
9628
79e53945
JB		 9629static void intel_setup_outputs(struct drm_device *dev)
9630{
725e30ad 9631 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9632 struct intel_encoder *encoder;
cb0953d7 9633 bool dpd_is_edp = false;
79e53945 9634
c9093354 9635 intel_lvds_init(dev);
79e53945 9636
c40c0f5b 9637 if (!IS_ULT(dev))
79935fca 9638 intel_crt_init(dev);
cb0953d7 9639
affa9354 9640 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9641 int found;
9642
9643 /* Haswell uses DDI functions to detect digital outputs */
9644 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9645 /* DDI A only supports eDP */
9646 if (found)
9647 intel_ddi_init(dev, PORT_A);
9648
9649 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9650 * register */
9651 found = I915_READ(SFUSE_STRAP);
9652
9653 if (found & SFUSE_STRAP_DDIB_DETECTED)
9654 intel_ddi_init(dev, PORT_B);
9655 if (found & SFUSE_STRAP_DDIC_DETECTED)
9656 intel_ddi_init(dev, PORT_C);
9657 if (found & SFUSE_STRAP_DDID_DETECTED)
9658 intel_ddi_init(dev, PORT_D);
9659 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9660 int found;
270b3042
DV		 9661 dpd_is_edp = intel_dpd_is_edp(dev);
9662
9663 if (has_edp_a(dev))
9664 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9665
dc0fa718 9666 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9667 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9668 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9669 if (!found)
e2debe91 9670 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9671 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9672 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9673 }
9674
dc0fa718 9675 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9676 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9677
dc0fa718 9678 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9679 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9680
5eb08b69 9681 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9682 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9683
270b3042 9684 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9685 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9686 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9687 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9688 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9689 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9690 PORT_C);
9691 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9692 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9693 PORT_C);
9694 }
19c03924 9695
dc0fa718 9696 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9697 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9698 PORT_B);
67cfc203
VS		 9699 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9700 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9701 }
3cfca973
JN		 9702
9703 intel_dsi_init(dev);
103a196f 9704 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9705 bool found = false;
7d57382e 9706
e2debe91 9707 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9708 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9709 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9710 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9711 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9712 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9713 }
27185ae1 9714
e7281eab 9715 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9716 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9717 }
13520b05
KH		 9718
9719 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9720
e2debe91 9721 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9722 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9723 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9724 }
27185ae1 9725
e2debe91 9726 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9727
b01f2c3a
JB		 9728 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9729 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9730 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9731 }
e7281eab 9732 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9733 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9734 }
27185ae1 9735
b01f2c3a 9736 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9737 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9738 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9739 } else if (IS_GEN2(dev))
79e53945
JB		 9740 intel_dvo_init(dev);
9741
103a196f 9742 if (SUPPORTS_TV(dev))
79e53945
JB		 9743 intel_tv_init(dev);
9744
4ef69c7a
CW		 9745 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9746 encoder->base.possible_crtcs = encoder->crtc_mask;
9747 encoder->base.possible_clones =
66a9278e 9748 intel_encoder_clones(encoder);
79e53945 9749 }
47356eb6 9750
dde86e2d 9751 intel_init_pch_refclk(dev);
270b3042
DV		 9752
9753 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9754}
9755
ddfe1567
CW		 9756void intel_framebuffer_fini(struct intel_framebuffer *fb)
9757{
9758 drm_framebuffer_cleanup(&fb->base);
9759 drm_gem_object_unreference_unlocked(&fb->obj->base);
9760}
9761
79e53945
JB		 9762static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9763{
9764 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9765
ddfe1567 9766 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9767 kfree(intel_fb);
9768}
9769
9770static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9771 struct drm_file *file,
79e53945
JB		 9772 unsigned int *handle)
9773{
9774 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9775 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9776
05394f39 9777 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9778}
9779
9780static const struct drm_framebuffer_funcs intel_fb_funcs = {
9781 .destroy = intel_user_framebuffer_destroy,
9782 .create_handle = intel_user_framebuffer_create_handle,
9783};
9784
38651674
DA		 9785int intel_framebuffer_init(struct drm_device *dev,
9786 struct intel_framebuffer *intel_fb,
308e5bcb 9787 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9788 struct drm_i915_gem_object *obj)
79e53945 9789{
a35cdaa0 9790 int pitch_limit;
79e53945
JB		 9791 int ret;
9792
c16ed4be
CW		 9793 if (obj->tiling_mode == I915_TILING_Y) {
9794 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9795 return -EINVAL;
c16ed4be 9796 }
57cd6508 9797
c16ed4be
CW		 9798 if (mode_cmd->pitches[0] & 63) {
9799 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9800 mode_cmd->pitches[0]);
57cd6508 9801 return -EINVAL;
c16ed4be 9802 }
57cd6508 9803
a35cdaa0
CW		 9804 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9805 pitch_limit = 32*1024;
9806 } else if (INTEL_INFO(dev)->gen >= 4) {
9807 if (obj->tiling_mode)
9808 pitch_limit = 16*1024;
9809 else
9810 pitch_limit = 32*1024;
9811 } else if (INTEL_INFO(dev)->gen >= 3) {
9812 if (obj->tiling_mode)
9813 pitch_limit = 8*1024;
9814 else
9815 pitch_limit = 16*1024;
9816 } else
9817 /* XXX DSPC is limited to 4k tiled */
9818 pitch_limit = 8*1024;
9819
9820 if (mode_cmd->pitches[0] > pitch_limit) {
9821 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9822 obj->tiling_mode ? "tiled" : "linear",
9823 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9824 return -EINVAL;
c16ed4be 9825 }
5d7bd705
VS		 9826
9827 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9828 mode_cmd->pitches[0] != obj->stride) {
9829 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9830 mode_cmd->pitches[0], obj->stride);
5d7bd705 9831 return -EINVAL;
c16ed4be 9832 }
5d7bd705 9833
57779d06 9834 /* Reject formats not supported by any plane early. */
308e5bcb 9835 switch (mode_cmd->pixel_format) {
57779d06 9836 case DRM_FORMAT_C8:
04b3924d
VS		 9837 case DRM_FORMAT_RGB565:
9838 case DRM_FORMAT_XRGB8888:
9839 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9840 break;
9841 case DRM_FORMAT_XRGB1555:
9842 case DRM_FORMAT_ARGB1555:
c16ed4be 9843 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9844 DRM_DEBUG("unsupported pixel format: %s\n",
9845 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9846 return -EINVAL;
c16ed4be 9847 }
57779d06
VS		 9848 break;
9849 case DRM_FORMAT_XBGR8888:
9850 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9851 case DRM_FORMAT_XRGB2101010:
9852 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9853 case DRM_FORMAT_XBGR2101010:
9854 case DRM_FORMAT_ABGR2101010:
c16ed4be 9855 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9856 DRM_DEBUG("unsupported pixel format: %s\n",
9857 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9858 return -EINVAL;
c16ed4be 9859 }
b5626747 9860 break;
04b3924d
VS		 9861 case DRM_FORMAT_YUYV:
9862 case DRM_FORMAT_UYVY:
9863 case DRM_FORMAT_YVYU:
9864 case DRM_FORMAT_VYUY:
c16ed4be 9865 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9866 DRM_DEBUG("unsupported pixel format: %s\n",
9867 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9868 return -EINVAL;
c16ed4be 9869 }
57cd6508
CW		 9870 break;
9871 default:
4ee62c76
VS		 9872 DRM_DEBUG("unsupported pixel format: %s\n",
9873 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9874 return -EINVAL;
9875 }
9876
90f9a336
VS		 9877 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9878 if (mode_cmd->offsets[0] != 0)
9879 return -EINVAL;
9880
c7d73f6a
DV		 9881 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9882 intel_fb->obj = obj;
9883
79e53945
JB		 9884 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9885 if (ret) {
9886 DRM_ERROR("framebuffer init failed %d\n", ret);
9887 return ret;
9888 }
9889
79e53945
JB		 9890 return 0;
9891}
9892
79e53945
JB		 9893static struct drm_framebuffer *
9894intel_user_framebuffer_create(struct drm_device *dev,
9895 struct drm_file *filp,
308e5bcb 9896 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9897{
05394f39 9898 struct drm_i915_gem_object *obj;
79e53945 9899
308e5bcb
JB		 9900 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9901 mode_cmd->handles[0]));
c8725226 9902 if (&obj->base == NULL)
cce13ff7 9903 return ERR_PTR(-ENOENT);
79e53945 9904
d2dff872 9905 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9906}
9907
79e53945 9908static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9909 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9910 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9911};
9912
e70236a8
JB		 9913/* Set up chip specific display functions */
9914static void intel_init_display(struct drm_device *dev)
9915{
9916 struct drm_i915_private *dev_priv = dev->dev_private;
9917
ee9300bb
DV		 9918 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9919 dev_priv->display.find_dpll = g4x_find_best_dpll;
9920 else if (IS_VALLEYVIEW(dev))
9921 dev_priv->display.find_dpll = vlv_find_best_dpll;
9922 else if (IS_PINEVIEW(dev))
9923 dev_priv->display.find_dpll = pnv_find_best_dpll;
9924 else
9925 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9926
affa9354 9927 if (HAS_DDI(dev)) {
0e8ffe1b 9928 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9929 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9930 dev_priv->display.crtc_enable = haswell_crtc_enable;
9931 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9932 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9933 dev_priv->display.update_plane = ironlake_update_plane;
9934 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9935 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9936 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9937 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9938 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9939 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9940 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9941 } else if (IS_VALLEYVIEW(dev)) {
9942 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9943 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9944 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9945 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9946 dev_priv->display.off = i9xx_crtc_off;
9947 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9948 } else {
0e8ffe1b 9949 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9950 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9951 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9952 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9953 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9954 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9955 }
e70236a8 9956
e70236a8 9957 /* Returns the core display clock speed */
25eb05fc
JB		 9958 if (IS_VALLEYVIEW(dev))
9959 dev_priv->display.get_display_clock_speed =
9960 valleyview_get_display_clock_speed;
9961 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9962 dev_priv->display.get_display_clock_speed =
9963 i945_get_display_clock_speed;
9964 else if (IS_I915G(dev))
9965 dev_priv->display.get_display_clock_speed =
9966 i915_get_display_clock_speed;
257a7ffc 9967 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9968 dev_priv->display.get_display_clock_speed =
9969 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9970 else if (IS_PINEVIEW(dev))
9971 dev_priv->display.get_display_clock_speed =
9972 pnv_get_display_clock_speed;
e70236a8
JB		 9973 else if (IS_I915GM(dev))
9974 dev_priv->display.get_display_clock_speed =
9975 i915gm_get_display_clock_speed;
9976 else if (IS_I865G(dev))
9977 dev_priv->display.get_display_clock_speed =
9978 i865_get_display_clock_speed;
f0f8a9ce 9979 else if (IS_I85X(dev))
e70236a8
JB		 9980 dev_priv->display.get_display_clock_speed =
9981 i855_get_display_clock_speed;
9982 else /* 852, 830 */
9983 dev_priv->display.get_display_clock_speed =
9984 i830_get_display_clock_speed;
9985
7f8a8569 9986 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9987 if (IS_GEN5(dev)) {
674cf967 9988 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9989 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9990 } else if (IS_GEN6(dev)) {
674cf967 9991 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9992 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9993 } else if (IS_IVYBRIDGE(dev)) {
9994 /* FIXME: detect B0+ stepping and use auto training */
9995 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9996 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9997 dev_priv->display.modeset_global_resources =
9998 ivb_modeset_global_resources;
c82e4d26
ED		 9999 } else if (IS_HASWELL(dev)) {
10000 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10001 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10002 dev_priv->display.modeset_global_resources =
10003 haswell_modeset_global_resources;
a0e63c22 10004 }
6067aaea 10005 } else if (IS_G4X(dev)) {
e0dac65e 10006 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10007 }
8c9f3aaf
JB		 10008
10009 /* Default just returns -ENODEV to indicate unsupported */
10010 dev_priv->display.queue_flip = intel_default_queue_flip;
10011
10012 switch (INTEL_INFO(dev)->gen) {
10013 case 2:
10014 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10015 break;
10016
10017 case 3:
10018 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10019 break;
10020
10021 case 4:
10022 case 5:
10023 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10024 break;
10025
10026 case 6:
10027 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10028 break;
7c9017e5
JB		 10029 case 7:
10030 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10031 break;
8c9f3aaf 10032 }
e70236a8
JB		 10033}
10034
b690e96c
JB		 10035/*
10036 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10037 * resume, or other times. This quirk makes sure that's the case for
10038 * affected systems.
10039 */
0206e353 10040static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10041{
10042 struct drm_i915_private *dev_priv = dev->dev_private;
10043
10044 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10045 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10046}
10047
435793df
KP		 10048/*
10049 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10050 */
10051static void quirk_ssc_force_disable(struct drm_device *dev)
10052{
10053 struct drm_i915_private *dev_priv = dev->dev_private;
10054 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10055 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10056}
10057
4dca20ef 10058/*
5a15ab5b
CE		 10059 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10060 * brightness value
4dca20ef
CE		 10061 */
10062static void quirk_invert_brightness(struct drm_device *dev)
10063{
10064 struct drm_i915_private *dev_priv = dev->dev_private;
10065 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10066 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10067}
10068
e85843be
KM		 10069/*
10070 * Some machines (Dell XPS13) suffer broken backlight controls if
10071 * BLM_PCH_PWM_ENABLE is set.
10072 */
10073static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10074{
10075 struct drm_i915_private *dev_priv = dev->dev_private;
10076 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10077 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10078}
10079
b690e96c
JB		 10080struct intel_quirk {
10081 int device;
10082 int subsystem_vendor;
10083 int subsystem_device;
10084 void (*hook)(struct drm_device *dev);
10085};
10086
5f85f176
EE		 10087/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10088struct intel_dmi_quirk {
10089 void (*hook)(struct drm_device *dev);
10090 const struct dmi_system_id (*dmi_id_list)[];
10091};
10092
10093static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10094{
10095 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10096 return 1;
10097}
10098
10099static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10100 {
10101 .dmi_id_list = &(const struct dmi_system_id[]) {
10102 {
10103 .callback = intel_dmi_reverse_brightness,
10104 .ident = "NCR Corporation",
10105 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10106 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10107 },
10108 },
10109 { } /* terminating entry */
10110 },
10111 .hook = quirk_invert_brightness,
10112 },
10113};
10114
c43b5634 10115static struct intel_quirk intel_quirks[] = {
b690e96c 10116 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10117 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10118
b690e96c
JB		 10119 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10120 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10121
b690e96c
JB		 10122 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10123 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10124
ccd0d36e 10125 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10126 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10127 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10128
10129 /* Lenovo U160 cannot use SSC on LVDS */
10130 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10131
10132 /* Sony Vaio Y cannot use SSC on LVDS */
10133 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10134
10135 /* Acer Aspire 5734Z must invert backlight brightness */
10136 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10137
10138 /* Acer/eMachines G725 */
10139 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10140
10141 /* Acer/eMachines e725 */
10142 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10143
10144 /* Acer/Packard Bell NCL20 */
10145 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10146
10147 /* Acer Aspire 4736Z */
10148 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10149
10150 /* Dell XPS13 HD Sandy Bridge */
10151 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10152 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10153 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10154};
10155
10156static void intel_init_quirks(struct drm_device *dev)
10157{
10158 struct pci_dev *d = dev->pdev;
10159 int i;
10160
10161 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10162 struct intel_quirk *q = &intel_quirks[i];
10163
10164 if (d->device == q->device &&
10165 (d->subsystem_vendor == q->subsystem_vendor ||
10166 q->subsystem_vendor == PCI_ANY_ID) &&
10167 (d->subsystem_device == q->subsystem_device ||
10168 q->subsystem_device == PCI_ANY_ID))
10169 q->hook(dev);
10170 }
5f85f176
EE		 10171 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10172 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10173 intel_dmi_quirks[i].hook(dev);
10174 }
b690e96c
JB		 10175}
10176
9cce37f4
JB		 10177/* Disable the VGA plane that we never use */
10178static void i915_disable_vga(struct drm_device *dev)
10179{
10180 struct drm_i915_private *dev_priv = dev->dev_private;
10181 u8 sr1;
766aa1c4 10182 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10183
10184 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10185 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10186 sr1 = inb(VGA_SR_DATA);
10187 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10188
10189 /* Disable VGA memory on Intel HD */
10190 if (HAS_PCH_SPLIT(dev)) {
10191 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10192 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10193 VGA_RSRC_NORMAL_IO |
10194 VGA_RSRC_NORMAL_MEM);
10195 }
10196
9cce37f4
JB		 10197 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10198 udelay(300);
10199
10200 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10201 POSTING_READ(vga_reg);
10202}
10203
81b5c7bc
AW		 10204static void i915_enable_vga(struct drm_device *dev)
10205{
10206 /* Enable VGA memory on Intel HD */
10207 if (HAS_PCH_SPLIT(dev)) {
10208 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10209 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10210 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10211 VGA_RSRC_LEGACY_MEM |
10212 VGA_RSRC_NORMAL_IO |
10213 VGA_RSRC_NORMAL_MEM);
10214 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10215 }
10216}
10217
f817586c
DV		 10218void intel_modeset_init_hw(struct drm_device *dev)
10219{
fa42e23c 10220 intel_init_power_well(dev);
0232e927 10221
a8f78b58
ED		 10222 intel_prepare_ddi(dev);
10223
f817586c
DV		 10224 intel_init_clock_gating(dev);
10225
79f5b2c7 10226 mutex_lock(&dev->struct_mutex);
8090c6b9 10227 intel_enable_gt_powersave(dev);
79f5b2c7 10228 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10229}
10230
7d708ee4
ID		 10231void intel_modeset_suspend_hw(struct drm_device *dev)
10232{
10233 intel_suspend_hw(dev);
10234}
10235
79e53945
JB		 10236void intel_modeset_init(struct drm_device *dev)
10237{
652c393a 10238 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10239 int i, j, ret;
79e53945
JB		 10240
10241 drm_mode_config_init(dev);
10242
10243 dev->mode_config.min_width = 0;
10244 dev->mode_config.min_height = 0;
10245
019d96cb
DA		 10246 dev->mode_config.preferred_depth = 24;
10247 dev->mode_config.prefer_shadow = 1;
10248
e6ecefaa 10249 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10250
b690e96c
JB		 10251 intel_init_quirks(dev);
10252
1fa61106
ED		 10253 intel_init_pm(dev);
10254
e3c74757
BW		 10255 if (INTEL_INFO(dev)->num_pipes == 0)
10256 return;
10257
e70236a8
JB		 10258 intel_init_display(dev);
10259
a6c45cf0
CW		 10260 if (IS_GEN2(dev)) {
10261 dev->mode_config.max_width = 2048;
10262 dev->mode_config.max_height = 2048;
10263 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10264 dev->mode_config.max_width = 4096;
10265 dev->mode_config.max_height = 4096;
79e53945 10266 } else {
a6c45cf0
CW		 10267 dev->mode_config.max_width = 8192;
10268 dev->mode_config.max_height = 8192;
79e53945 10269 }
5d4545ae 10270 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10271
28c97730 10272 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10273 INTEL_INFO(dev)->num_pipes,
10274 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10275
08e2a7de 10276 for_each_pipe(i) {
79e53945 10277 intel_crtc_init(dev, i);
7f1f3851
JB		 10278 for (j = 0; j < dev_priv->num_plane; j++) {
10279 ret = intel_plane_init(dev, i, j);
10280 if (ret)
06da8da2
VS		 10281 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10282 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10283 }
79e53945
JB		 10284 }
10285
79f689aa 10286 intel_cpu_pll_init(dev);
e72f9fbf 10287 intel_shared_dpll_init(dev);
ee7b9f93 10288
9cce37f4
JB		 10289 /* Just disable it once at startup */
10290 i915_disable_vga(dev);
79e53945 10291 intel_setup_outputs(dev);
11be49eb
CW		 10292
10293 /* Just in case the BIOS is doing something questionable. */
10294 intel_disable_fbc(dev);
2c7111db
CW		 10295}
10296
24929352
DV		 10297static void
10298intel_connector_break_all_links(struct intel_connector *connector)
10299{
10300 connector->base.dpms = DRM_MODE_DPMS_OFF;
10301 connector->base.encoder = NULL;
10302 connector->encoder->connectors_active = false;
10303 connector->encoder->base.crtc = NULL;
10304}
10305
7fad798e
DV		 10306static void intel_enable_pipe_a(struct drm_device *dev)
10307{
10308 struct intel_connector *connector;
10309 struct drm_connector *crt = NULL;
10310 struct intel_load_detect_pipe load_detect_temp;
10311
10312 /* We can't just switch on the pipe A, we need to set things up with a
10313 * proper mode and output configuration. As a gross hack, enable pipe A
10314 * by enabling the load detect pipe once. */
10315 list_for_each_entry(connector,
10316 &dev->mode_config.connector_list,
10317 base.head) {
10318 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10319 crt = &connector->base;
10320 break;
10321 }
10322 }
10323
10324 if (!crt)
10325 return;
10326
10327 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10328 intel_release_load_detect_pipe(crt, &load_detect_temp);
10329
652c393a 10330
7fad798e
DV		 10331}
10332
fa555837
DV		 10333static bool
10334intel_check_plane_mapping(struct intel_crtc *crtc)
10335{
7eb552ae
BW		 10336 struct drm_device *dev = crtc->base.dev;
10337 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10338 u32 reg, val;
10339
7eb552ae 10340 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10341 return true;
10342
10343 reg = DSPCNTR(!crtc->plane);
10344 val = I915_READ(reg);
10345
10346 if ((val & DISPLAY_PLANE_ENABLE) &&
10347 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10348 return false;
10349
10350 return true;
10351}
10352
24929352
DV		 10353static void intel_sanitize_crtc(struct intel_crtc *crtc)
10354{
10355 struct drm_device *dev = crtc->base.dev;
10356 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10357 u32 reg;
24929352 10358
24929352 10359 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10360 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10361 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10362
10363 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10364 * disable the crtc (and hence change the state) if it is wrong. Note
10365 * that gen4+ has a fixed plane -> pipe mapping. */
10366 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10367 struct intel_connector *connector;
10368 bool plane;
10369
24929352
DV		 10370 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10371 crtc->base.base.id);
10372
10373 /* Pipe has the wrong plane attached and the plane is active.
10374 * Temporarily change the plane mapping and disable everything
10375 * ... */
10376 plane = crtc->plane;
10377 crtc->plane = !plane;
10378 dev_priv->display.crtc_disable(&crtc->base);
10379 crtc->plane = plane;
10380
10381 /* ... and break all links. */
10382 list_for_each_entry(connector, &dev->mode_config.connector_list,
10383 base.head) {
10384 if (connector->encoder->base.crtc != &crtc->base)
10385 continue;
10386
10387 intel_connector_break_all_links(connector);
10388 }
10389
10390 WARN_ON(crtc->active);
10391 crtc->base.enabled = false;
10392 }
24929352 10393
7fad798e
DV		 10394 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10395 crtc->pipe == PIPE_A && !crtc->active) {
10396 /* BIOS forgot to enable pipe A, this mostly happens after
10397 * resume. Force-enable the pipe to fix this, the update_dpms
10398 * call below we restore the pipe to the right state, but leave
10399 * the required bits on. */
10400 intel_enable_pipe_a(dev);
10401 }
10402
24929352
DV		 10403 /* Adjust the state of the output pipe according to whether we
10404 * have active connectors/encoders. */
10405 intel_crtc_update_dpms(&crtc->base);
10406
10407 if (crtc->active != crtc->base.enabled) {
10408 struct intel_encoder *encoder;
10409
10410 /* This can happen either due to bugs in the get_hw_state
10411 * functions or because the pipe is force-enabled due to the
10412 * pipe A quirk. */
10413 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10414 crtc->base.base.id,
10415 crtc->base.enabled ? "enabled" : "disabled",
10416 crtc->active ? "enabled" : "disabled");
10417
10418 crtc->base.enabled = crtc->active;
10419
10420 /* Because we only establish the connector -> encoder ->
10421 * crtc links if something is active, this means the
10422 * crtc is now deactivated. Break the links. connector
10423 * -> encoder links are only establish when things are
10424 * actually up, hence no need to break them. */
10425 WARN_ON(crtc->active);
10426
10427 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10428 WARN_ON(encoder->connectors_active);
10429 encoder->base.crtc = NULL;
10430 }
10431 }
10432}
10433
10434static void intel_sanitize_encoder(struct intel_encoder *encoder)
10435{
10436 struct intel_connector *connector;
10437 struct drm_device *dev = encoder->base.dev;
10438
10439 /* We need to check both for a crtc link (meaning that the
10440 * encoder is active and trying to read from a pipe) and the
10441 * pipe itself being active. */
10442 bool has_active_crtc = encoder->base.crtc &&
10443 to_intel_crtc(encoder->base.crtc)->active;
10444
10445 if (encoder->connectors_active && !has_active_crtc) {
10446 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10447 encoder->base.base.id,
10448 drm_get_encoder_name(&encoder->base));
10449
10450 /* Connector is active, but has no active pipe. This is
10451 * fallout from our resume register restoring. Disable
10452 * the encoder manually again. */
10453 if (encoder->base.crtc) {
10454 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10455 encoder->base.base.id,
10456 drm_get_encoder_name(&encoder->base));
10457 encoder->disable(encoder);
10458 }
10459
10460 /* Inconsistent output/port/pipe state happens presumably due to
10461 * a bug in one of the get_hw_state functions. Or someplace else
10462 * in our code, like the register restore mess on resume. Clamp
10463 * things to off as a safer default. */
10464 list_for_each_entry(connector,
10465 &dev->mode_config.connector_list,
10466 base.head) {
10467 if (connector->encoder != encoder)
10468 continue;
10469
10470 intel_connector_break_all_links(connector);
10471 }
10472 }
10473 /* Enabled encoders without active connectors will be fixed in
10474 * the crtc fixup. */
10475}
10476
44cec740 10477void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10478{
10479 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10480 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10481
8dc8a27c
PZ		 10482 /* This function can be called both from intel_modeset_setup_hw_state or
10483 * at a very early point in our resume sequence, where the power well
10484 * structures are not yet restored. Since this function is at a very
10485 * paranoid "someone might have enabled VGA while we were not looking"
10486 * level, just check if the power well is enabled instead of trying to
10487 * follow the "don't touch the power well if we don't need it" policy
10488 * the rest of the driver uses. */
10489 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10490 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10491 return;
10492
0fde901f
KM		 10493 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10494 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10495 i915_disable_vga(dev);
0fde901f
KM		 10496 }
10497}
10498
30e984df 10499static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10500{
10501 struct drm_i915_private *dev_priv = dev->dev_private;
10502 enum pipe pipe;
24929352
DV		 10503 struct intel_crtc *crtc;
10504 struct intel_encoder *encoder;
10505 struct intel_connector *connector;
5358901f 10506 int i;
24929352 10507
0e8ffe1b
DV		 10508 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10509 base.head) {
88adfff1 10510 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10511
0e8ffe1b
DV		 10512 crtc->active = dev_priv->display.get_pipe_config(crtc,
10513 &crtc->config);
24929352
DV		 10514
10515 crtc->base.enabled = crtc->active;
10516
10517 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10518 crtc->base.base.id,
10519 crtc->active ? "enabled" : "disabled");
10520 }
10521
5358901f 10522 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10523 if (HAS_DDI(dev))
6441ab5f
PZ		 10524 intel_ddi_setup_hw_pll_state(dev);
10525
5358901f
DV		 10526 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10527 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10528
10529 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10530 pll->active = 0;
10531 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10532 base.head) {
10533 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10534 pll->active++;
10535 }
10536 pll->refcount = pll->active;
10537
35c95375
DV		 10538 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10539 pll->name, pll->refcount, pll->on);
5358901f
DV		 10540 }
10541
24929352
DV		 10542 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10543 base.head) {
10544 pipe = 0;
10545
10546 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10547 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10548 encoder->base.crtc = &crtc->base;
510d5f2f 10549 if (encoder->get_config)
045ac3b5 10550 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10551 } else {
10552 encoder->base.crtc = NULL;
10553 }
10554
10555 encoder->connectors_active = false;
10556 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10557 encoder->base.base.id,
10558 drm_get_encoder_name(&encoder->base),
10559 encoder->base.crtc ? "enabled" : "disabled",
10560 pipe);
10561 }
10562
10563 list_for_each_entry(connector, &dev->mode_config.connector_list,
10564 base.head) {
10565 if (connector->get_hw_state(connector)) {
10566 connector->base.dpms = DRM_MODE_DPMS_ON;
10567 connector->encoder->connectors_active = true;
10568 connector->base.encoder = &connector->encoder->base;
10569 } else {
10570 connector->base.dpms = DRM_MODE_DPMS_OFF;
10571 connector->base.encoder = NULL;
10572 }
10573 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10574 connector->base.base.id,
10575 drm_get_connector_name(&connector->base),
10576 connector->base.encoder ? "enabled" : "disabled");
10577 }
30e984df
DV		 10578}
10579
10580/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10581 * and i915 state tracking structures. */
10582void intel_modeset_setup_hw_state(struct drm_device *dev,
10583 bool force_restore)
10584{
10585 struct drm_i915_private *dev_priv = dev->dev_private;
10586 enum pipe pipe;
10587 struct drm_plane *plane;
10588 struct intel_crtc *crtc;
10589 struct intel_encoder *encoder;
35c95375 10590 int i;
30e984df
DV		 10591
10592 intel_modeset_readout_hw_state(dev);
24929352 10593
babea61d
JB		 10594 /*
10595 * Now that we have the config, copy it to each CRTC struct
10596 * Note that this could go away if we move to using crtc_config
10597 * checking everywhere.
10598 */
10599 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10600 base.head) {
10601 if (crtc->active && i915_fastboot) {
10602 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10603
10604 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10605 crtc->base.base.id);
10606 drm_mode_debug_printmodeline(&crtc->base.mode);
10607 }
10608 }
10609
24929352
DV		 10610 /* HW state is read out, now we need to sanitize this mess. */
10611 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10612 base.head) {
10613 intel_sanitize_encoder(encoder);
10614 }
10615
10616 for_each_pipe(pipe) {
10617 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10618 intel_sanitize_crtc(crtc);
c0b03411 10619 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10620 }
9a935856 10621
35c95375
DV		 10622 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10623 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10624
10625 if (!pll->on || pll->active)
10626 continue;
10627
10628 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10629
10630 pll->disable(dev_priv, pll);
10631 pll->on = false;
10632 }
10633
45e2b5f6 10634 if (force_restore) {
f30da187
DV		 10635 /*
10636 * We need to use raw interfaces for restoring state to avoid
10637 * checking (bogus) intermediate states.
10638 */
45e2b5f6 10639 for_each_pipe(pipe) {
b5644d05
JB		 10640 struct drm_crtc *crtc =
10641 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10642
10643 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10644 crtc->fb);
45e2b5f6 10645 }
b5644d05
JB		 10646 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10647 intel_plane_restore(plane);
0fde901f
KM		 10648
10649 i915_redisable_vga(dev);
45e2b5f6
DV		 10650 } else {
10651 intel_modeset_update_staged_output_state(dev);
10652 }
8af6cf88
DV		 10653
10654 intel_modeset_check_state(dev);
2e938892
DV		 10655
10656 drm_mode_config_reset(dev);
2c7111db
CW		 10657}
10658
10659void intel_modeset_gem_init(struct drm_device *dev)
10660{
1833b134 10661 intel_modeset_init_hw(dev);
02e792fb
DV		 10662
10663 intel_setup_overlay(dev);
24929352 10664
45e2b5f6 10665 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10666}
10667
10668void intel_modeset_cleanup(struct drm_device *dev)
10669{
652c393a
JB		 10670 struct drm_i915_private *dev_priv = dev->dev_private;
10671 struct drm_crtc *crtc;
652c393a 10672
fd0c0642
DV		 10673 /*
10674 * Interrupts and polling as the first thing to avoid creating havoc.
10675 * Too much stuff here (turning of rps, connectors, ...) would
10676 * experience fancy races otherwise.
10677 */
10678 drm_irq_uninstall(dev);
10679 cancel_work_sync(&dev_priv->hotplug_work);
10680 /*
10681 * Due to the hpd irq storm handling the hotplug work can re-arm the
10682 * poll handlers. Hence disable polling after hpd handling is shut down.
10683 */
f87ea761 10684 drm_kms_helper_poll_fini(dev);
fd0c0642 10685
652c393a
JB		 10686 mutex_lock(&dev->struct_mutex);
10687
723bfd70
JB		 10688 intel_unregister_dsm_handler();
10689
652c393a
JB		 10690 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10691 /* Skip inactive CRTCs */
10692 if (!crtc->fb)
10693 continue;
10694
3dec0095 10695 intel_increase_pllclock(crtc);
652c393a
JB		 10696 }
10697
973d04f9 10698 intel_disable_fbc(dev);
e70236a8 10699
81b5c7bc
AW		 10700 i915_enable_vga(dev);
10701
8090c6b9 10702 intel_disable_gt_powersave(dev);
0cdab21f 10703
930ebb46
DV		 10704 ironlake_teardown_rc6(dev);
10705
69341a5e
KH		 10706 mutex_unlock(&dev->struct_mutex);
10707
1630fe75
CW		 10708 /* flush any delayed tasks or pending work */
10709 flush_scheduled_work();
10710
dc652f90
JN		 10711 /* destroy backlight, if any, before the connectors */
10712 intel_panel_destroy_backlight(dev);
10713
79e53945 10714 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10715
10716 intel_cleanup_overlay(dev);
79e53945
JB		 10717}
10718
f1c79df3
ZW		 10719/*
10720 * Return which encoder is currently attached for connector.
10721 */
df0e9248 10722struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10723{
df0e9248
CW		 10724 return &intel_attached_encoder(connector)->base;
10725}
f1c79df3 10726
df0e9248
CW		 10727void intel_connector_attach_encoder(struct intel_connector *connector,
10728 struct intel_encoder *encoder)
10729{
10730 connector->encoder = encoder;
10731 drm_mode_connector_attach_encoder(&connector->base,
10732 &encoder->base);
79e53945 10733}
28d52043
DA		 10734
10735/*
10736 * set vga decode state - true == enable VGA decode
10737 */
10738int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10739{
10740 struct drm_i915_private *dev_priv = dev->dev_private;
10741 u16 gmch_ctrl;
10742
10743 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10744 if (state)
10745 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10746 else
10747 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10748 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10749 return 0;
10750}
c4a1d9e4 10751
c4a1d9e4 10752struct intel_display_error_state {
ff57f1b0
PZ		 10753
10754 u32 power_well_driver;
10755
63b66e5b
CW		 10756 int num_transcoders;
10757
c4a1d9e4
CW		 10758 struct intel_cursor_error_state {
10759 u32 control;
10760 u32 position;
10761 u32 base;
10762 u32 size;
52331309 10763 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10764
10765 struct intel_pipe_error_state {
c4a1d9e4 10766 u32 source;
52331309 10767 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10768
10769 struct intel_plane_error_state {
10770 u32 control;
10771 u32 stride;
10772 u32 size;
10773 u32 pos;
10774 u32 addr;
10775 u32 surface;
10776 u32 tile_offset;
52331309 10777 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10778
10779 struct intel_transcoder_error_state {
10780 enum transcoder cpu_transcoder;
10781
10782 u32 conf;
10783
10784 u32 htotal;
10785 u32 hblank;
10786 u32 hsync;
10787 u32 vtotal;
10788 u32 vblank;
10789 u32 vsync;
10790 } transcoder[4];
c4a1d9e4
CW		 10791};
10792
10793struct intel_display_error_state *
10794intel_display_capture_error_state(struct drm_device *dev)
10795{
0206e353 10796 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10797 struct intel_display_error_state *error;
63b66e5b
CW		 10798 int transcoders[] = {
10799 TRANSCODER_A,
10800 TRANSCODER_B,
10801 TRANSCODER_C,
10802 TRANSCODER_EDP,
10803 };
c4a1d9e4
CW		 10804 int i;
10805
63b66e5b
CW		 10806 if (INTEL_INFO(dev)->num_pipes == 0)
10807 return NULL;
10808
c4a1d9e4
CW		 10809 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10810 if (error == NULL)
10811 return NULL;
10812
ff57f1b0
PZ		 10813 if (HAS_POWER_WELL(dev))
10814 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10815
52331309 10816 for_each_pipe(i) {
a18c4c3d
PZ		 10817 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10818 error->cursor[i].control = I915_READ(CURCNTR(i));
10819 error->cursor[i].position = I915_READ(CURPOS(i));
10820 error->cursor[i].base = I915_READ(CURBASE(i));
10821 } else {
10822 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10823 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10824 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10825 }
c4a1d9e4
CW		 10826
10827 error->plane[i].control = I915_READ(DSPCNTR(i));
10828 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10829 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10830 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10831 error->plane[i].pos = I915_READ(DSPPOS(i));
10832 }
ca291363
PZ		 10833 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10834 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10835 if (INTEL_INFO(dev)->gen >= 4) {
10836 error->plane[i].surface = I915_READ(DSPSURF(i));
10837 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10838 }
10839
c4a1d9e4 10840 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10841 }
10842
10843 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10844 if (HAS_DDI(dev_priv->dev))
10845 error->num_transcoders++; /* Account for eDP. */
10846
10847 for (i = 0; i < error->num_transcoders; i++) {
10848 enum transcoder cpu_transcoder = transcoders[i];
10849
10850 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10851
10852 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10853 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10854 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10855 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10856 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10857 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10858 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10859 }
10860
12d217c7
PZ		 10861 /* In the code above we read the registers without checking if the power
10862 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10863 * prevent the next I915_WRITE from detecting it and printing an error
10864 * message. */
907b28c5 10865 intel_uncore_clear_errors(dev);
12d217c7 10866
c4a1d9e4
CW		 10867 return error;
10868}
10869
edc3d884
MK		 10870#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10871
c4a1d9e4 10872void
edc3d884 10873intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10874 struct drm_device *dev,
10875 struct intel_display_error_state *error)
10876{
10877 int i;
10878
63b66e5b
CW		 10879 if (!error)
10880 return;
10881
edc3d884 10882 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10883 if (HAS_POWER_WELL(dev))
edc3d884 10884 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10885 error->power_well_driver);
52331309 10886 for_each_pipe(i) {
edc3d884 10887 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10888 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10889
10890 err_printf(m, "Plane [%d]:\n", i);
10891 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10892 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10893 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10894 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10895 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10896 }
4b71a570 10897 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10898 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10899 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10900 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10901 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10902 }
10903
edc3d884
MK		 10904 err_printf(m, "Cursor [%d]:\n", i);
10905 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10906 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10907 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10908 }
63b66e5b
CW		 10909
10910 for (i = 0; i < error->num_transcoders; i++) {
10911 err_printf(m, " CPU transcoder: %c\n",
10912 transcoder_name(error->transcoder[i].cpu_transcoder));
10913 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10914 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10915 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10916 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10917 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10918 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10919 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10920 }
c4a1d9e4 10921}
Linux kernel - Deliverables
This page took 2.381216 seconds and 5 git commands to generate.