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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
200757f5 | 119 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
e7457a9a | 120 | |
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
bfa7df01 VS |
136 | /* returns HPLL frequency in kHz */ |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
150 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
151 | const char *name, u32 reg) | |
152 | { | |
153 | u32 val; | |
154 | int divider; | |
155 | ||
156 | if (dev_priv->hpll_freq == 0) | |
157 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
158 | ||
159 | mutex_lock(&dev_priv->sb_lock); | |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
169 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
170 | } | |
171 | ||
d2acd215 DV |
172 | int |
173 | intel_pch_rawclk(struct drm_device *dev) | |
174 | { | |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
176 | ||
177 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
178 | ||
179 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
180 | } | |
181 | ||
79e50a4f JN |
182 | /* hrawclock is 1/4 the FSB frequency */ |
183 | int intel_hrawclk(struct drm_device *dev) | |
184 | { | |
185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
186 | uint32_t clkcfg; | |
187 | ||
188 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
666a4537 | 189 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
79e50a4f JN |
190 | return 200; |
191 | ||
192 | clkcfg = I915_READ(CLKCFG); | |
193 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
194 | case CLKCFG_FSB_400: | |
195 | return 100; | |
196 | case CLKCFG_FSB_533: | |
197 | return 133; | |
198 | case CLKCFG_FSB_667: | |
199 | return 166; | |
200 | case CLKCFG_FSB_800: | |
201 | return 200; | |
202 | case CLKCFG_FSB_1067: | |
203 | return 266; | |
204 | case CLKCFG_FSB_1333: | |
205 | return 333; | |
206 | /* these two are just a guess; one of them might be right */ | |
207 | case CLKCFG_FSB_1600: | |
208 | case CLKCFG_FSB_1600_ALT: | |
209 | return 400; | |
210 | default: | |
211 | return 133; | |
212 | } | |
213 | } | |
214 | ||
bfa7df01 VS |
215 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
216 | { | |
666a4537 | 217 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
218 | return; |
219 | ||
220 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
221 | CCK_CZ_CLOCK_CONTROL); | |
222 | ||
223 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
224 | } | |
225 | ||
021357ac CW |
226 | static inline u32 /* units of 100MHz */ |
227 | intel_fdi_link_freq(struct drm_device *dev) | |
228 | { | |
8b99e68c CW |
229 | if (IS_GEN5(dev)) { |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
232 | } else | |
233 | return 27; | |
021357ac CW |
234 | } |
235 | ||
5d536e28 | 236 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 237 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 238 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 239 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
240 | .m = { .min = 96, .max = 140 }, |
241 | .m1 = { .min = 18, .max = 26 }, | |
242 | .m2 = { .min = 6, .max = 16 }, | |
243 | .p = { .min = 4, .max = 128 }, | |
244 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
245 | .p2 = { .dot_limit = 165000, |
246 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
247 | }; |
248 | ||
5d536e28 DV |
249 | static const intel_limit_t intel_limits_i8xx_dvo = { |
250 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 251 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 252 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
253 | .m = { .min = 96, .max = 140 }, |
254 | .m1 = { .min = 18, .max = 26 }, | |
255 | .m2 = { .min = 6, .max = 16 }, | |
256 | .p = { .min = 4, .max = 128 }, | |
257 | .p1 = { .min = 2, .max = 33 }, | |
258 | .p2 = { .dot_limit = 165000, | |
259 | .p2_slow = 4, .p2_fast = 4 }, | |
260 | }; | |
261 | ||
e4b36699 | 262 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 263 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 264 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 265 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
266 | .m = { .min = 96, .max = 140 }, |
267 | .m1 = { .min = 18, .max = 26 }, | |
268 | .m2 = { .min = 6, .max = 16 }, | |
269 | .p = { .min = 4, .max = 128 }, | |
270 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
271 | .p2 = { .dot_limit = 165000, |
272 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 273 | }; |
273e27ca | 274 | |
e4b36699 | 275 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
276 | .dot = { .min = 20000, .max = 400000 }, |
277 | .vco = { .min = 1400000, .max = 2800000 }, | |
278 | .n = { .min = 1, .max = 6 }, | |
279 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
280 | .m1 = { .min = 8, .max = 18 }, |
281 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
282 | .p = { .min = 5, .max = 80 }, |
283 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
284 | .p2 = { .dot_limit = 200000, |
285 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
286 | }; |
287 | ||
288 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
289 | .dot = { .min = 20000, .max = 400000 }, |
290 | .vco = { .min = 1400000, .max = 2800000 }, | |
291 | .n = { .min = 1, .max = 6 }, | |
292 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
293 | .m1 = { .min = 8, .max = 18 }, |
294 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
295 | .p = { .min = 7, .max = 98 }, |
296 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
297 | .p2 = { .dot_limit = 112000, |
298 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
299 | }; |
300 | ||
273e27ca | 301 | |
e4b36699 | 302 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 270000 }, |
304 | .vco = { .min = 1750000, .max = 3500000}, | |
305 | .n = { .min = 1, .max = 4 }, | |
306 | .m = { .min = 104, .max = 138 }, | |
307 | .m1 = { .min = 17, .max = 23 }, | |
308 | .m2 = { .min = 5, .max = 11 }, | |
309 | .p = { .min = 10, .max = 30 }, | |
310 | .p1 = { .min = 1, .max = 3}, | |
311 | .p2 = { .dot_limit = 270000, | |
312 | .p2_slow = 10, | |
313 | .p2_fast = 10 | |
044c7c41 | 314 | }, |
e4b36699 KP |
315 | }; |
316 | ||
317 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
318 | .dot = { .min = 22000, .max = 400000 }, |
319 | .vco = { .min = 1750000, .max = 3500000}, | |
320 | .n = { .min = 1, .max = 4 }, | |
321 | .m = { .min = 104, .max = 138 }, | |
322 | .m1 = { .min = 16, .max = 23 }, | |
323 | .m2 = { .min = 5, .max = 11 }, | |
324 | .p = { .min = 5, .max = 80 }, | |
325 | .p1 = { .min = 1, .max = 8}, | |
326 | .p2 = { .dot_limit = 165000, | |
327 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
328 | }; |
329 | ||
330 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
331 | .dot = { .min = 20000, .max = 115000 }, |
332 | .vco = { .min = 1750000, .max = 3500000 }, | |
333 | .n = { .min = 1, .max = 3 }, | |
334 | .m = { .min = 104, .max = 138 }, | |
335 | .m1 = { .min = 17, .max = 23 }, | |
336 | .m2 = { .min = 5, .max = 11 }, | |
337 | .p = { .min = 28, .max = 112 }, | |
338 | .p1 = { .min = 2, .max = 8 }, | |
339 | .p2 = { .dot_limit = 0, | |
340 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
344 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
345 | .dot = { .min = 80000, .max = 224000 }, |
346 | .vco = { .min = 1750000, .max = 3500000 }, | |
347 | .n = { .min = 1, .max = 3 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 17, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 14, .max = 42 }, | |
352 | .p1 = { .min = 2, .max = 6 }, | |
353 | .p2 = { .dot_limit = 0, | |
354 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 355 | }, |
e4b36699 KP |
356 | }; |
357 | ||
f2b115e6 | 358 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
359 | .dot = { .min = 20000, .max = 400000}, |
360 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 361 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
362 | .n = { .min = 3, .max = 6 }, |
363 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 364 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
365 | .m1 = { .min = 0, .max = 0 }, |
366 | .m2 = { .min = 0, .max = 254 }, | |
367 | .p = { .min = 5, .max = 80 }, | |
368 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
369 | .p2 = { .dot_limit = 200000, |
370 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
371 | }; |
372 | ||
f2b115e6 | 373 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
374 | .dot = { .min = 20000, .max = 400000 }, |
375 | .vco = { .min = 1700000, .max = 3500000 }, | |
376 | .n = { .min = 3, .max = 6 }, | |
377 | .m = { .min = 2, .max = 256 }, | |
378 | .m1 = { .min = 0, .max = 0 }, | |
379 | .m2 = { .min = 0, .max = 254 }, | |
380 | .p = { .min = 7, .max = 112 }, | |
381 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
382 | .p2 = { .dot_limit = 112000, |
383 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
384 | }; |
385 | ||
273e27ca EA |
386 | /* Ironlake / Sandybridge |
387 | * | |
388 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
389 | * the range value for them is (actual_value - 2). | |
390 | */ | |
b91ad0ec | 391 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
392 | .dot = { .min = 25000, .max = 350000 }, |
393 | .vco = { .min = 1760000, .max = 3510000 }, | |
394 | .n = { .min = 1, .max = 5 }, | |
395 | .m = { .min = 79, .max = 127 }, | |
396 | .m1 = { .min = 12, .max = 22 }, | |
397 | .m2 = { .min = 5, .max = 9 }, | |
398 | .p = { .min = 5, .max = 80 }, | |
399 | .p1 = { .min = 1, .max = 8 }, | |
400 | .p2 = { .dot_limit = 225000, | |
401 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
402 | }; |
403 | ||
b91ad0ec | 404 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
405 | .dot = { .min = 25000, .max = 350000 }, |
406 | .vco = { .min = 1760000, .max = 3510000 }, | |
407 | .n = { .min = 1, .max = 3 }, | |
408 | .m = { .min = 79, .max = 118 }, | |
409 | .m1 = { .min = 12, .max = 22 }, | |
410 | .m2 = { .min = 5, .max = 9 }, | |
411 | .p = { .min = 28, .max = 112 }, | |
412 | .p1 = { .min = 2, .max = 8 }, | |
413 | .p2 = { .dot_limit = 225000, | |
414 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
415 | }; |
416 | ||
417 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
418 | .dot = { .min = 25000, .max = 350000 }, |
419 | .vco = { .min = 1760000, .max = 3510000 }, | |
420 | .n = { .min = 1, .max = 3 }, | |
421 | .m = { .min = 79, .max = 127 }, | |
422 | .m1 = { .min = 12, .max = 22 }, | |
423 | .m2 = { .min = 5, .max = 9 }, | |
424 | .p = { .min = 14, .max = 56 }, | |
425 | .p1 = { .min = 2, .max = 8 }, | |
426 | .p2 = { .dot_limit = 225000, | |
427 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
428 | }; |
429 | ||
273e27ca | 430 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 431 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 2 }, | |
435 | .m = { .min = 79, .max = 126 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 439 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
440 | .p2 = { .dot_limit = 225000, |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
444 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 126 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 452 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
453 | .p2 = { .dot_limit = 225000, |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
455 | }; |
456 | ||
dc730512 | 457 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
458 | /* |
459 | * These are the data rate limits (measured in fast clocks) | |
460 | * since those are the strictest limits we have. The fast | |
461 | * clock and actual rate limits are more relaxed, so checking | |
462 | * them would make no difference. | |
463 | */ | |
464 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 465 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 466 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
467 | .m1 = { .min = 2, .max = 3 }, |
468 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 469 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 470 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
471 | }; |
472 | ||
ef9348c8 CML |
473 | static const intel_limit_t intel_limits_chv = { |
474 | /* | |
475 | * These are the data rate limits (measured in fast clocks) | |
476 | * since those are the strictest limits we have. The fast | |
477 | * clock and actual rate limits are more relaxed, so checking | |
478 | * them would make no difference. | |
479 | */ | |
480 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 481 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
482 | .n = { .min = 1, .max = 1 }, |
483 | .m1 = { .min = 2, .max = 2 }, | |
484 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
485 | .p1 = { .min = 2, .max = 4 }, | |
486 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
487 | }; | |
488 | ||
5ab7b0b7 ID |
489 | static const intel_limit_t intel_limits_bxt = { |
490 | /* FIXME: find real dot limits */ | |
491 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 492 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
493 | .n = { .min = 1, .max = 1 }, |
494 | .m1 = { .min = 2, .max = 2 }, | |
495 | /* FIXME: find real m2 limits */ | |
496 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
497 | .p1 = { .min = 2, .max = 4 }, | |
498 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
499 | }; | |
500 | ||
cdba954e ACO |
501 | static bool |
502 | needs_modeset(struct drm_crtc_state *state) | |
503 | { | |
fc596660 | 504 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
505 | } |
506 | ||
e0638cdf PZ |
507 | /** |
508 | * Returns whether any output on the specified pipe is of the specified type | |
509 | */ | |
4093561b | 510 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 511 | { |
409ee761 | 512 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
513 | struct intel_encoder *encoder; |
514 | ||
409ee761 | 515 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
516 | if (encoder->type == type) |
517 | return true; | |
518 | ||
519 | return false; | |
520 | } | |
521 | ||
d0737e1d ACO |
522 | /** |
523 | * Returns whether any output on the specified pipe will have the specified | |
524 | * type after a staged modeset is complete, i.e., the same as | |
525 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
526 | * encoder->crtc. | |
527 | */ | |
a93e255f ACO |
528 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
529 | int type) | |
d0737e1d | 530 | { |
a93e255f | 531 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 532 | struct drm_connector *connector; |
a93e255f | 533 | struct drm_connector_state *connector_state; |
d0737e1d | 534 | struct intel_encoder *encoder; |
a93e255f ACO |
535 | int i, num_connectors = 0; |
536 | ||
da3ced29 | 537 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
538 | if (connector_state->crtc != crtc_state->base.crtc) |
539 | continue; | |
540 | ||
541 | num_connectors++; | |
d0737e1d | 542 | |
a93e255f ACO |
543 | encoder = to_intel_encoder(connector_state->best_encoder); |
544 | if (encoder->type == type) | |
d0737e1d | 545 | return true; |
a93e255f ACO |
546 | } |
547 | ||
548 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
549 | |
550 | return false; | |
551 | } | |
552 | ||
a93e255f ACO |
553 | static const intel_limit_t * |
554 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 555 | { |
a93e255f | 556 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 557 | const intel_limit_t *limit; |
b91ad0ec | 558 | |
a93e255f | 559 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 560 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 561 | if (refclk == 100000) |
b91ad0ec ZW |
562 | limit = &intel_limits_ironlake_dual_lvds_100m; |
563 | else | |
564 | limit = &intel_limits_ironlake_dual_lvds; | |
565 | } else { | |
1b894b59 | 566 | if (refclk == 100000) |
b91ad0ec ZW |
567 | limit = &intel_limits_ironlake_single_lvds_100m; |
568 | else | |
569 | limit = &intel_limits_ironlake_single_lvds; | |
570 | } | |
c6bb3538 | 571 | } else |
b91ad0ec | 572 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
573 | |
574 | return limit; | |
575 | } | |
576 | ||
a93e255f ACO |
577 | static const intel_limit_t * |
578 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 579 | { |
a93e255f | 580 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
581 | const intel_limit_t *limit; |
582 | ||
a93e255f | 583 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 584 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 585 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 586 | else |
e4b36699 | 587 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
588 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
589 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 590 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 591 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 592 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 593 | } else /* The option is for other outputs */ |
e4b36699 | 594 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
595 | |
596 | return limit; | |
597 | } | |
598 | ||
a93e255f ACO |
599 | static const intel_limit_t * |
600 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 601 | { |
a93e255f | 602 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
603 | const intel_limit_t *limit; |
604 | ||
5ab7b0b7 ID |
605 | if (IS_BROXTON(dev)) |
606 | limit = &intel_limits_bxt; | |
607 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 608 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 609 | else if (IS_G4X(dev)) { |
a93e255f | 610 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 611 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 612 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 613 | limit = &intel_limits_pineview_lvds; |
2177832f | 614 | else |
f2b115e6 | 615 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
616 | } else if (IS_CHERRYVIEW(dev)) { |
617 | limit = &intel_limits_chv; | |
a0c4da24 | 618 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 619 | limit = &intel_limits_vlv; |
a6c45cf0 | 620 | } else if (!IS_GEN2(dev)) { |
a93e255f | 621 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
622 | limit = &intel_limits_i9xx_lvds; |
623 | else | |
624 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 625 | } else { |
a93e255f | 626 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 627 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 628 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 629 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
630 | else |
631 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
632 | } |
633 | return limit; | |
634 | } | |
635 | ||
dccbea3b ID |
636 | /* |
637 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
638 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
639 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
640 | * The helpers' return value is the rate of the clock that is fed to the | |
641 | * display engine's pipe which can be the above fast dot clock rate or a | |
642 | * divided-down version of it. | |
643 | */ | |
f2b115e6 | 644 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 645 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 646 | { |
2177832f SL |
647 | clock->m = clock->m2 + 2; |
648 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 649 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 650 | return 0; |
fb03ac01 VS |
651 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
652 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
653 | |
654 | return clock->dot; | |
2177832f SL |
655 | } |
656 | ||
7429e9d4 DV |
657 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
658 | { | |
659 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
660 | } | |
661 | ||
dccbea3b | 662 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 663 | { |
7429e9d4 | 664 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 665 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 666 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 667 | return 0; |
fb03ac01 VS |
668 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
669 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
670 | |
671 | return clock->dot; | |
79e53945 JB |
672 | } |
673 | ||
dccbea3b | 674 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
675 | { |
676 | clock->m = clock->m1 * clock->m2; | |
677 | clock->p = clock->p1 * clock->p2; | |
678 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 679 | return 0; |
589eca67 ID |
680 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
681 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
682 | |
683 | return clock->dot / 5; | |
589eca67 ID |
684 | } |
685 | ||
dccbea3b | 686 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
687 | { |
688 | clock->m = clock->m1 * clock->m2; | |
689 | clock->p = clock->p1 * clock->p2; | |
690 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 691 | return 0; |
ef9348c8 CML |
692 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
693 | clock->n << 22); | |
694 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
695 | |
696 | return clock->dot / 5; | |
ef9348c8 CML |
697 | } |
698 | ||
7c04d1d9 | 699 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
700 | /** |
701 | * Returns whether the given set of divisors are valid for a given refclk with | |
702 | * the given connectors. | |
703 | */ | |
704 | ||
1b894b59 CW |
705 | static bool intel_PLL_is_valid(struct drm_device *dev, |
706 | const intel_limit_t *limit, | |
707 | const intel_clock_t *clock) | |
79e53945 | 708 | { |
f01b7962 VS |
709 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
710 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 711 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 712 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 713 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 714 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 715 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 716 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 717 | |
666a4537 WB |
718 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
719 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
720 | if (clock->m1 <= clock->m2) |
721 | INTELPllInvalid("m1 <= m2\n"); | |
722 | ||
666a4537 | 723 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
724 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
725 | INTELPllInvalid("p out of range\n"); | |
726 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
727 | INTELPllInvalid("m out of range\n"); | |
728 | } | |
729 | ||
79e53945 | 730 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 731 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
732 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
733 | * connector, etc., rather than just a single range. | |
734 | */ | |
735 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 736 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
737 | |
738 | return true; | |
739 | } | |
740 | ||
3b1429d9 VS |
741 | static int |
742 | i9xx_select_p2_div(const intel_limit_t *limit, | |
743 | const struct intel_crtc_state *crtc_state, | |
744 | int target) | |
79e53945 | 745 | { |
3b1429d9 | 746 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 747 | |
a93e255f | 748 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 749 | /* |
a210b028 DV |
750 | * For LVDS just rely on its current settings for dual-channel. |
751 | * We haven't figured out how to reliably set up different | |
752 | * single/dual channel state, if we even can. | |
79e53945 | 753 | */ |
1974cad0 | 754 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 755 | return limit->p2.p2_fast; |
79e53945 | 756 | else |
3b1429d9 | 757 | return limit->p2.p2_slow; |
79e53945 JB |
758 | } else { |
759 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 760 | return limit->p2.p2_slow; |
79e53945 | 761 | else |
3b1429d9 | 762 | return limit->p2.p2_fast; |
79e53945 | 763 | } |
3b1429d9 VS |
764 | } |
765 | ||
766 | static bool | |
767 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
768 | struct intel_crtc_state *crtc_state, | |
769 | int target, int refclk, intel_clock_t *match_clock, | |
770 | intel_clock_t *best_clock) | |
771 | { | |
772 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
773 | intel_clock_t clock; | |
774 | int err = target; | |
79e53945 | 775 | |
0206e353 | 776 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 777 | |
3b1429d9 VS |
778 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
779 | ||
42158660 ZY |
780 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
781 | clock.m1++) { | |
782 | for (clock.m2 = limit->m2.min; | |
783 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 784 | if (clock.m2 >= clock.m1) |
42158660 ZY |
785 | break; |
786 | for (clock.n = limit->n.min; | |
787 | clock.n <= limit->n.max; clock.n++) { | |
788 | for (clock.p1 = limit->p1.min; | |
789 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
790 | int this_err; |
791 | ||
dccbea3b | 792 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
793 | if (!intel_PLL_is_valid(dev, limit, |
794 | &clock)) | |
795 | continue; | |
796 | if (match_clock && | |
797 | clock.p != match_clock->p) | |
798 | continue; | |
799 | ||
800 | this_err = abs(clock.dot - target); | |
801 | if (this_err < err) { | |
802 | *best_clock = clock; | |
803 | err = this_err; | |
804 | } | |
805 | } | |
806 | } | |
807 | } | |
808 | } | |
809 | ||
810 | return (err != target); | |
811 | } | |
812 | ||
813 | static bool | |
a93e255f ACO |
814 | pnv_find_best_dpll(const intel_limit_t *limit, |
815 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
816 | int target, int refclk, intel_clock_t *match_clock, |
817 | intel_clock_t *best_clock) | |
79e53945 | 818 | { |
3b1429d9 | 819 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 820 | intel_clock_t clock; |
79e53945 JB |
821 | int err = target; |
822 | ||
0206e353 | 823 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 824 | |
3b1429d9 VS |
825 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
826 | ||
42158660 ZY |
827 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
828 | clock.m1++) { | |
829 | for (clock.m2 = limit->m2.min; | |
830 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
831 | for (clock.n = limit->n.min; |
832 | clock.n <= limit->n.max; clock.n++) { | |
833 | for (clock.p1 = limit->p1.min; | |
834 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
835 | int this_err; |
836 | ||
dccbea3b | 837 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
838 | if (!intel_PLL_is_valid(dev, limit, |
839 | &clock)) | |
79e53945 | 840 | continue; |
cec2f356 SP |
841 | if (match_clock && |
842 | clock.p != match_clock->p) | |
843 | continue; | |
79e53945 JB |
844 | |
845 | this_err = abs(clock.dot - target); | |
846 | if (this_err < err) { | |
847 | *best_clock = clock; | |
848 | err = this_err; | |
849 | } | |
850 | } | |
851 | } | |
852 | } | |
853 | } | |
854 | ||
855 | return (err != target); | |
856 | } | |
857 | ||
d4906093 | 858 | static bool |
a93e255f ACO |
859 | g4x_find_best_dpll(const intel_limit_t *limit, |
860 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
861 | int target, int refclk, intel_clock_t *match_clock, |
862 | intel_clock_t *best_clock) | |
d4906093 | 863 | { |
3b1429d9 | 864 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
865 | intel_clock_t clock; |
866 | int max_n; | |
3b1429d9 | 867 | bool found = false; |
6ba770dc AJ |
868 | /* approximately equals target * 0.00585 */ |
869 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
870 | |
871 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
872 | |
873 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
874 | ||
d4906093 | 875 | max_n = limit->n.max; |
f77f13e2 | 876 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 877 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 878 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
879 | for (clock.m1 = limit->m1.max; |
880 | clock.m1 >= limit->m1.min; clock.m1--) { | |
881 | for (clock.m2 = limit->m2.max; | |
882 | clock.m2 >= limit->m2.min; clock.m2--) { | |
883 | for (clock.p1 = limit->p1.max; | |
884 | clock.p1 >= limit->p1.min; clock.p1--) { | |
885 | int this_err; | |
886 | ||
dccbea3b | 887 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
888 | if (!intel_PLL_is_valid(dev, limit, |
889 | &clock)) | |
d4906093 | 890 | continue; |
1b894b59 CW |
891 | |
892 | this_err = abs(clock.dot - target); | |
d4906093 ML |
893 | if (this_err < err_most) { |
894 | *best_clock = clock; | |
895 | err_most = this_err; | |
896 | max_n = clock.n; | |
897 | found = true; | |
898 | } | |
899 | } | |
900 | } | |
901 | } | |
902 | } | |
2c07245f ZW |
903 | return found; |
904 | } | |
905 | ||
d5dd62bd ID |
906 | /* |
907 | * Check if the calculated PLL configuration is more optimal compared to the | |
908 | * best configuration and error found so far. Return the calculated error. | |
909 | */ | |
910 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
911 | const intel_clock_t *calculated_clock, | |
912 | const intel_clock_t *best_clock, | |
913 | unsigned int best_error_ppm, | |
914 | unsigned int *error_ppm) | |
915 | { | |
9ca3ba01 ID |
916 | /* |
917 | * For CHV ignore the error and consider only the P value. | |
918 | * Prefer a bigger P value based on HW requirements. | |
919 | */ | |
920 | if (IS_CHERRYVIEW(dev)) { | |
921 | *error_ppm = 0; | |
922 | ||
923 | return calculated_clock->p > best_clock->p; | |
924 | } | |
925 | ||
24be4e46 ID |
926 | if (WARN_ON_ONCE(!target_freq)) |
927 | return false; | |
928 | ||
d5dd62bd ID |
929 | *error_ppm = div_u64(1000000ULL * |
930 | abs(target_freq - calculated_clock->dot), | |
931 | target_freq); | |
932 | /* | |
933 | * Prefer a better P value over a better (smaller) error if the error | |
934 | * is small. Ensure this preference for future configurations too by | |
935 | * setting the error to 0. | |
936 | */ | |
937 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
938 | *error_ppm = 0; | |
939 | ||
940 | return true; | |
941 | } | |
942 | ||
943 | return *error_ppm + 10 < best_error_ppm; | |
944 | } | |
945 | ||
a0c4da24 | 946 | static bool |
a93e255f ACO |
947 | vlv_find_best_dpll(const intel_limit_t *limit, |
948 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
949 | int target, int refclk, intel_clock_t *match_clock, |
950 | intel_clock_t *best_clock) | |
a0c4da24 | 951 | { |
a93e255f | 952 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 953 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 954 | intel_clock_t clock; |
69e4f900 | 955 | unsigned int bestppm = 1000000; |
27e639bf VS |
956 | /* min update 19.2 MHz */ |
957 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 958 | bool found = false; |
a0c4da24 | 959 | |
6b4bf1c4 VS |
960 | target *= 5; /* fast clock */ |
961 | ||
962 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
963 | |
964 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 965 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 966 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 967 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 968 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 969 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 970 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 971 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 972 | unsigned int ppm; |
69e4f900 | 973 | |
6b4bf1c4 VS |
974 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
975 | refclk * clock.m1); | |
976 | ||
dccbea3b | 977 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 978 | |
f01b7962 VS |
979 | if (!intel_PLL_is_valid(dev, limit, |
980 | &clock)) | |
43b0ac53 VS |
981 | continue; |
982 | ||
d5dd62bd ID |
983 | if (!vlv_PLL_is_optimal(dev, target, |
984 | &clock, | |
985 | best_clock, | |
986 | bestppm, &ppm)) | |
987 | continue; | |
6b4bf1c4 | 988 | |
d5dd62bd ID |
989 | *best_clock = clock; |
990 | bestppm = ppm; | |
991 | found = true; | |
a0c4da24 JB |
992 | } |
993 | } | |
994 | } | |
995 | } | |
a0c4da24 | 996 | |
49e497ef | 997 | return found; |
a0c4da24 | 998 | } |
a4fc5ed6 | 999 | |
ef9348c8 | 1000 | static bool |
a93e255f ACO |
1001 | chv_find_best_dpll(const intel_limit_t *limit, |
1002 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1003 | int target, int refclk, intel_clock_t *match_clock, |
1004 | intel_clock_t *best_clock) | |
1005 | { | |
a93e255f | 1006 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1007 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1008 | unsigned int best_error_ppm; |
ef9348c8 CML |
1009 | intel_clock_t clock; |
1010 | uint64_t m2; | |
1011 | int found = false; | |
1012 | ||
1013 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1014 | best_error_ppm = 1000000; |
ef9348c8 CML |
1015 | |
1016 | /* | |
1017 | * Based on hardware doc, the n always set to 1, and m1 always | |
1018 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1019 | * revisit this because n may not 1 anymore. | |
1020 | */ | |
1021 | clock.n = 1, clock.m1 = 2; | |
1022 | target *= 5; /* fast clock */ | |
1023 | ||
1024 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1025 | for (clock.p2 = limit->p2.p2_fast; | |
1026 | clock.p2 >= limit->p2.p2_slow; | |
1027 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1028 | unsigned int error_ppm; |
ef9348c8 CML |
1029 | |
1030 | clock.p = clock.p1 * clock.p2; | |
1031 | ||
1032 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1033 | clock.n) << 22, refclk * clock.m1); | |
1034 | ||
1035 | if (m2 > INT_MAX/clock.m1) | |
1036 | continue; | |
1037 | ||
1038 | clock.m2 = m2; | |
1039 | ||
dccbea3b | 1040 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1041 | |
1042 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1043 | continue; | |
1044 | ||
9ca3ba01 ID |
1045 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1046 | best_error_ppm, &error_ppm)) | |
1047 | continue; | |
1048 | ||
1049 | *best_clock = clock; | |
1050 | best_error_ppm = error_ppm; | |
1051 | found = true; | |
ef9348c8 CML |
1052 | } |
1053 | } | |
1054 | ||
1055 | return found; | |
1056 | } | |
1057 | ||
5ab7b0b7 ID |
1058 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1059 | intel_clock_t *best_clock) | |
1060 | { | |
1061 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1062 | ||
1063 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1064 | target_clock, refclk, NULL, best_clock); | |
1065 | } | |
1066 | ||
20ddf665 VS |
1067 | bool intel_crtc_active(struct drm_crtc *crtc) |
1068 | { | |
1069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1070 | ||
1071 | /* Be paranoid as we can arrive here with only partial | |
1072 | * state retrieved from the hardware during setup. | |
1073 | * | |
241bfc38 | 1074 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1075 | * as Haswell has gained clock readout/fastboot support. |
1076 | * | |
66e514c1 | 1077 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1078 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1079 | * |
1080 | * FIXME: The intel_crtc->active here should be switched to | |
1081 | * crtc->state->active once we have proper CRTC states wired up | |
1082 | * for atomic. | |
20ddf665 | 1083 | */ |
c3d1f436 | 1084 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1085 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1086 | } |
1087 | ||
a5c961d1 PZ |
1088 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1089 | enum pipe pipe) | |
1090 | { | |
1091 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1093 | ||
6e3c9717 | 1094 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1095 | } |
1096 | ||
fbf49ea2 VS |
1097 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1098 | { | |
1099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1100 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1101 | u32 line1, line2; |
1102 | u32 line_mask; | |
1103 | ||
1104 | if (IS_GEN2(dev)) | |
1105 | line_mask = DSL_LINEMASK_GEN2; | |
1106 | else | |
1107 | line_mask = DSL_LINEMASK_GEN3; | |
1108 | ||
1109 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1110 | msleep(5); |
fbf49ea2 VS |
1111 | line2 = I915_READ(reg) & line_mask; |
1112 | ||
1113 | return line1 == line2; | |
1114 | } | |
1115 | ||
ab7ad7f6 KP |
1116 | /* |
1117 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1118 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1119 | * |
1120 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1121 | * spinning on the vblank interrupt status bit, since we won't actually | |
1122 | * see an interrupt when the pipe is disabled. | |
1123 | * | |
ab7ad7f6 KP |
1124 | * On Gen4 and above: |
1125 | * wait for the pipe register state bit to turn off | |
1126 | * | |
1127 | * Otherwise: | |
1128 | * wait for the display line value to settle (it usually | |
1129 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1130 | * |
9d0498a2 | 1131 | */ |
575f7ab7 | 1132 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1133 | { |
575f7ab7 | 1134 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1135 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1136 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1137 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1138 | |
1139 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1140 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1141 | |
1142 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1143 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1144 | 100)) | |
284637d9 | 1145 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1146 | } else { |
ab7ad7f6 | 1147 | /* Wait for the display line to settle */ |
fbf49ea2 | 1148 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1149 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1150 | } |
79e53945 JB |
1151 | } |
1152 | ||
b24e7179 | 1153 | /* Only for pre-ILK configs */ |
55607e8a DV |
1154 | void assert_pll(struct drm_i915_private *dev_priv, |
1155 | enum pipe pipe, bool state) | |
b24e7179 | 1156 | { |
b24e7179 JB |
1157 | u32 val; |
1158 | bool cur_state; | |
1159 | ||
649636ef | 1160 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1161 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1162 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1163 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1164 | onoff(state), onoff(cur_state)); |
b24e7179 | 1165 | } |
b24e7179 | 1166 | |
23538ef1 JN |
1167 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1168 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1169 | { | |
1170 | u32 val; | |
1171 | bool cur_state; | |
1172 | ||
a580516d | 1173 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1174 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1175 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1176 | |
1177 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1178 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1179 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1180 | onoff(state), onoff(cur_state)); |
23538ef1 JN |
1181 | } |
1182 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1183 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1184 | ||
55607e8a | 1185 | struct intel_shared_dpll * |
e2b78267 DV |
1186 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1187 | { | |
1188 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1189 | ||
6e3c9717 | 1190 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1191 | return NULL; |
1192 | ||
6e3c9717 | 1193 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1194 | } |
1195 | ||
040484af | 1196 | /* For ILK+ */ |
55607e8a DV |
1197 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1198 | struct intel_shared_dpll *pll, | |
1199 | bool state) | |
040484af | 1200 | { |
040484af | 1201 | bool cur_state; |
5358901f | 1202 | struct intel_dpll_hw_state hw_state; |
040484af | 1203 | |
87ad3212 | 1204 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) |
ee7b9f93 | 1205 | return; |
ee7b9f93 | 1206 | |
5358901f | 1207 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1208 | I915_STATE_WARN(cur_state != state, |
5358901f | 1209 | "%s assertion failure (expected %s, current %s)\n", |
87ad3212 | 1210 | pll->name, onoff(state), onoff(cur_state)); |
040484af | 1211 | } |
040484af JB |
1212 | |
1213 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1214 | enum pipe pipe, bool state) | |
1215 | { | |
040484af | 1216 | bool cur_state; |
ad80a810 PZ |
1217 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1218 | pipe); | |
040484af | 1219 | |
affa9354 PZ |
1220 | if (HAS_DDI(dev_priv->dev)) { |
1221 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1222 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1223 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1224 | } else { |
649636ef | 1225 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1226 | cur_state = !!(val & FDI_TX_ENABLE); |
1227 | } | |
e2c719b7 | 1228 | I915_STATE_WARN(cur_state != state, |
040484af | 1229 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1230 | onoff(state), onoff(cur_state)); |
040484af JB |
1231 | } |
1232 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1233 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1234 | ||
1235 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1236 | enum pipe pipe, bool state) | |
1237 | { | |
040484af JB |
1238 | u32 val; |
1239 | bool cur_state; | |
1240 | ||
649636ef | 1241 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1242 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1243 | I915_STATE_WARN(cur_state != state, |
040484af | 1244 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1245 | onoff(state), onoff(cur_state)); |
040484af JB |
1246 | } |
1247 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1248 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1249 | ||
1250 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1251 | enum pipe pipe) | |
1252 | { | |
040484af JB |
1253 | u32 val; |
1254 | ||
1255 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1256 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1257 | return; |
1258 | ||
bf507ef7 | 1259 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1260 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1261 | return; |
1262 | ||
649636ef | 1263 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1264 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1265 | } |
1266 | ||
55607e8a DV |
1267 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1268 | enum pipe pipe, bool state) | |
040484af | 1269 | { |
040484af | 1270 | u32 val; |
55607e8a | 1271 | bool cur_state; |
040484af | 1272 | |
649636ef | 1273 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1274 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1275 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1276 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1277 | onoff(state), onoff(cur_state)); |
040484af JB |
1278 | } |
1279 | ||
b680c37a DV |
1280 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1281 | enum pipe pipe) | |
ea0760cf | 1282 | { |
bedd4dba | 1283 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1284 | i915_reg_t pp_reg; |
ea0760cf JB |
1285 | u32 val; |
1286 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1287 | bool locked = true; |
ea0760cf | 1288 | |
bedd4dba JN |
1289 | if (WARN_ON(HAS_DDI(dev))) |
1290 | return; | |
1291 | ||
1292 | if (HAS_PCH_SPLIT(dev)) { | |
1293 | u32 port_sel; | |
1294 | ||
ea0760cf | 1295 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1296 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1297 | ||
1298 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1299 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1300 | panel_pipe = PIPE_B; | |
1301 | /* XXX: else fix for eDP */ | |
666a4537 | 1302 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1303 | /* presumably write lock depends on pipe, not port select */ |
1304 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1305 | panel_pipe = pipe; | |
ea0760cf JB |
1306 | } else { |
1307 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1308 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1309 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1310 | } |
1311 | ||
1312 | val = I915_READ(pp_reg); | |
1313 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1314 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1315 | locked = false; |
1316 | ||
e2c719b7 | 1317 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1318 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1319 | pipe_name(pipe)); |
ea0760cf JB |
1320 | } |
1321 | ||
93ce0ba6 JN |
1322 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1323 | enum pipe pipe, bool state) | |
1324 | { | |
1325 | struct drm_device *dev = dev_priv->dev; | |
1326 | bool cur_state; | |
1327 | ||
d9d82081 | 1328 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1329 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1330 | else |
5efb3e28 | 1331 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1332 | |
e2c719b7 | 1333 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1334 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1335 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1336 | } |
1337 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1338 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1339 | ||
b840d907 JB |
1340 | void assert_pipe(struct drm_i915_private *dev_priv, |
1341 | enum pipe pipe, bool state) | |
b24e7179 | 1342 | { |
63d7bbe9 | 1343 | bool cur_state; |
702e7a56 PZ |
1344 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1345 | pipe); | |
b24e7179 | 1346 | |
b6b5d049 VS |
1347 | /* if we need the pipe quirk it must be always on */ |
1348 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1349 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1350 | state = true; |
1351 | ||
f458ebbc | 1352 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1353 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1354 | cur_state = false; |
1355 | } else { | |
649636ef | 1356 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 PZ |
1357 | cur_state = !!(val & PIPECONF_ENABLE); |
1358 | } | |
1359 | ||
e2c719b7 | 1360 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1361 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1362 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1363 | } |
1364 | ||
931872fc CW |
1365 | static void assert_plane(struct drm_i915_private *dev_priv, |
1366 | enum plane plane, bool state) | |
b24e7179 | 1367 | { |
b24e7179 | 1368 | u32 val; |
931872fc | 1369 | bool cur_state; |
b24e7179 | 1370 | |
649636ef | 1371 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1372 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1373 | I915_STATE_WARN(cur_state != state, |
931872fc | 1374 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1375 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1376 | } |
1377 | ||
931872fc CW |
1378 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1379 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1380 | ||
b24e7179 JB |
1381 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1382 | enum pipe pipe) | |
1383 | { | |
653e1026 | 1384 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1385 | int i; |
b24e7179 | 1386 | |
653e1026 VS |
1387 | /* Primary planes are fixed to pipes on gen4+ */ |
1388 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1389 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1390 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1391 | "plane %c assertion failure, should be disabled but not\n", |
1392 | plane_name(pipe)); | |
19ec1358 | 1393 | return; |
28c05794 | 1394 | } |
19ec1358 | 1395 | |
b24e7179 | 1396 | /* Need to check both planes against the pipe */ |
055e393f | 1397 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1398 | u32 val = I915_READ(DSPCNTR(i)); |
1399 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1400 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1401 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1402 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1403 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1404 | } |
1405 | } | |
1406 | ||
19332d7a JB |
1407 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1408 | enum pipe pipe) | |
1409 | { | |
20674eef | 1410 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1411 | int sprite; |
19332d7a | 1412 | |
7feb8b88 | 1413 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1414 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1415 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1416 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1417 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1418 | sprite, pipe_name(pipe)); | |
1419 | } | |
666a4537 | 1420 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1421 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1422 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1423 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1424 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1425 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1426 | } |
1427 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1428 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1429 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1430 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1431 | plane_name(pipe), pipe_name(pipe)); |
1432 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1433 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1434 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1435 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1436 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1437 | } |
1438 | } | |
1439 | ||
08c71e5e VS |
1440 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1441 | { | |
e2c719b7 | 1442 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1443 | drm_crtc_vblank_put(crtc); |
1444 | } | |
1445 | ||
89eff4be | 1446 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1447 | { |
1448 | u32 val; | |
1449 | bool enabled; | |
1450 | ||
e2c719b7 | 1451 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1452 | |
92f2584a JB |
1453 | val = I915_READ(PCH_DREF_CONTROL); |
1454 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1455 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1456 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1457 | } |
1458 | ||
ab9412ba DV |
1459 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1460 | enum pipe pipe) | |
92f2584a | 1461 | { |
92f2584a JB |
1462 | u32 val; |
1463 | bool enabled; | |
1464 | ||
649636ef | 1465 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1466 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1467 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1468 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1469 | pipe_name(pipe)); | |
92f2584a JB |
1470 | } |
1471 | ||
4e634389 KP |
1472 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1473 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1474 | { |
1475 | if ((val & DP_PORT_EN) == 0) | |
1476 | return false; | |
1477 | ||
1478 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1479 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1480 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1481 | return false; | |
44f37d1f CML |
1482 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1483 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1484 | return false; | |
f0575e92 KP |
1485 | } else { |
1486 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1487 | return false; | |
1488 | } | |
1489 | return true; | |
1490 | } | |
1491 | ||
1519b995 KP |
1492 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1493 | enum pipe pipe, u32 val) | |
1494 | { | |
dc0fa718 | 1495 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1496 | return false; |
1497 | ||
1498 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1499 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1500 | return false; |
44f37d1f CML |
1501 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1502 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1503 | return false; | |
1519b995 | 1504 | } else { |
dc0fa718 | 1505 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1506 | return false; |
1507 | } | |
1508 | return true; | |
1509 | } | |
1510 | ||
1511 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1512 | enum pipe pipe, u32 val) | |
1513 | { | |
1514 | if ((val & LVDS_PORT_EN) == 0) | |
1515 | return false; | |
1516 | ||
1517 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1518 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1519 | return false; | |
1520 | } else { | |
1521 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1522 | return false; | |
1523 | } | |
1524 | return true; | |
1525 | } | |
1526 | ||
1527 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1528 | enum pipe pipe, u32 val) | |
1529 | { | |
1530 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1531 | return false; | |
1532 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1533 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1534 | return false; | |
1535 | } else { | |
1536 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1537 | return false; | |
1538 | } | |
1539 | return true; | |
1540 | } | |
1541 | ||
291906f1 | 1542 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1543 | enum pipe pipe, i915_reg_t reg, |
1544 | u32 port_sel) | |
291906f1 | 1545 | { |
47a05eca | 1546 | u32 val = I915_READ(reg); |
e2c719b7 | 1547 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1548 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1549 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1550 | |
e2c719b7 | 1551 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1552 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1553 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1554 | } |
1555 | ||
1556 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1557 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1558 | { |
47a05eca | 1559 | u32 val = I915_READ(reg); |
e2c719b7 | 1560 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1561 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1562 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1563 | |
e2c719b7 | 1564 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1565 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1566 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1567 | } |
1568 | ||
1569 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1570 | enum pipe pipe) | |
1571 | { | |
291906f1 | 1572 | u32 val; |
291906f1 | 1573 | |
f0575e92 KP |
1574 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1575 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1576 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1577 | |
649636ef | 1578 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1579 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1580 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1581 | pipe_name(pipe)); |
291906f1 | 1582 | |
649636ef | 1583 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1584 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1585 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1586 | pipe_name(pipe)); |
291906f1 | 1587 | |
e2debe91 PZ |
1588 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1589 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1590 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1591 | } |
1592 | ||
d288f65f | 1593 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1594 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1595 | { |
426115cf DV |
1596 | struct drm_device *dev = crtc->base.dev; |
1597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1598 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1599 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1600 | |
426115cf | 1601 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1602 | |
87442f73 | 1603 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1604 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1605 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1606 | |
426115cf DV |
1607 | I915_WRITE(reg, dpll); |
1608 | POSTING_READ(reg); | |
1609 | udelay(150); | |
1610 | ||
1611 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1612 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1613 | ||
d288f65f | 1614 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1615 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1616 | |
1617 | /* We do this three times for luck */ | |
426115cf | 1618 | I915_WRITE(reg, dpll); |
87442f73 DV |
1619 | POSTING_READ(reg); |
1620 | udelay(150); /* wait for warmup */ | |
426115cf | 1621 | I915_WRITE(reg, dpll); |
87442f73 DV |
1622 | POSTING_READ(reg); |
1623 | udelay(150); /* wait for warmup */ | |
426115cf | 1624 | I915_WRITE(reg, dpll); |
87442f73 DV |
1625 | POSTING_READ(reg); |
1626 | udelay(150); /* wait for warmup */ | |
1627 | } | |
1628 | ||
d288f65f | 1629 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1630 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1631 | { |
1632 | struct drm_device *dev = crtc->base.dev; | |
1633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1634 | int pipe = crtc->pipe; | |
1635 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1636 | u32 tmp; |
1637 | ||
1638 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1639 | ||
a580516d | 1640 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1641 | |
1642 | /* Enable back the 10bit clock to display controller */ | |
1643 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1644 | tmp |= DPIO_DCLKP_EN; | |
1645 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1646 | ||
54433e91 VS |
1647 | mutex_unlock(&dev_priv->sb_lock); |
1648 | ||
9d556c99 CML |
1649 | /* |
1650 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1651 | */ | |
1652 | udelay(1); | |
1653 | ||
1654 | /* Enable PLL */ | |
d288f65f | 1655 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1656 | |
1657 | /* Check PLL is locked */ | |
a11b0703 | 1658 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1659 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1660 | ||
a11b0703 | 1661 | /* not sure when this should be written */ |
d288f65f | 1662 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1663 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1664 | } |
1665 | ||
1c4e0274 VS |
1666 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1667 | { | |
1668 | struct intel_crtc *crtc; | |
1669 | int count = 0; | |
1670 | ||
1671 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1672 | count += crtc->base.state->active && |
409ee761 | 1673 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1674 | |
1675 | return count; | |
1676 | } | |
1677 | ||
66e3d5c0 | 1678 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1679 | { |
66e3d5c0 DV |
1680 | struct drm_device *dev = crtc->base.dev; |
1681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1682 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1683 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1684 | |
66e3d5c0 | 1685 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1686 | |
63d7bbe9 | 1687 | /* No really, not for ILK+ */ |
3d13ef2e | 1688 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1689 | |
1690 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1691 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1692 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1693 | |
1c4e0274 VS |
1694 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1695 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1696 | /* | |
1697 | * It appears to be important that we don't enable this | |
1698 | * for the current pipe before otherwise configuring the | |
1699 | * PLL. No idea how this should be handled if multiple | |
1700 | * DVO outputs are enabled simultaneosly. | |
1701 | */ | |
1702 | dpll |= DPLL_DVO_2X_MODE; | |
1703 | I915_WRITE(DPLL(!crtc->pipe), | |
1704 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1705 | } | |
66e3d5c0 | 1706 | |
c2b63374 VS |
1707 | /* |
1708 | * Apparently we need to have VGA mode enabled prior to changing | |
1709 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1710 | * dividers, even though the register value does change. | |
1711 | */ | |
1712 | I915_WRITE(reg, 0); | |
1713 | ||
8e7a65aa VS |
1714 | I915_WRITE(reg, dpll); |
1715 | ||
66e3d5c0 DV |
1716 | /* Wait for the clocks to stabilize. */ |
1717 | POSTING_READ(reg); | |
1718 | udelay(150); | |
1719 | ||
1720 | if (INTEL_INFO(dev)->gen >= 4) { | |
1721 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1722 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1723 | } else { |
1724 | /* The pixel multiplier can only be updated once the | |
1725 | * DPLL is enabled and the clocks are stable. | |
1726 | * | |
1727 | * So write it again. | |
1728 | */ | |
1729 | I915_WRITE(reg, dpll); | |
1730 | } | |
63d7bbe9 JB |
1731 | |
1732 | /* We do this three times for luck */ | |
66e3d5c0 | 1733 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1734 | POSTING_READ(reg); |
1735 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1736 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1737 | POSTING_READ(reg); |
1738 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1739 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1740 | POSTING_READ(reg); |
1741 | udelay(150); /* wait for warmup */ | |
1742 | } | |
1743 | ||
1744 | /** | |
50b44a44 | 1745 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1746 | * @dev_priv: i915 private structure |
1747 | * @pipe: pipe PLL to disable | |
1748 | * | |
1749 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1750 | * | |
1751 | * Note! This is for pre-ILK only. | |
1752 | */ | |
1c4e0274 | 1753 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1754 | { |
1c4e0274 VS |
1755 | struct drm_device *dev = crtc->base.dev; |
1756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1757 | enum pipe pipe = crtc->pipe; | |
1758 | ||
1759 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1760 | if (IS_I830(dev) && | |
409ee761 | 1761 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1762 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1763 | I915_WRITE(DPLL(PIPE_B), |
1764 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1765 | I915_WRITE(DPLL(PIPE_A), | |
1766 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1767 | } | |
1768 | ||
b6b5d049 VS |
1769 | /* Don't disable pipe or pipe PLLs if needed */ |
1770 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1771 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1772 | return; |
1773 | ||
1774 | /* Make sure the pipe isn't still relying on us */ | |
1775 | assert_pipe_disabled(dev_priv, pipe); | |
1776 | ||
b8afb911 | 1777 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1778 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1779 | } |
1780 | ||
f6071166 JB |
1781 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1782 | { | |
b8afb911 | 1783 | u32 val; |
f6071166 JB |
1784 | |
1785 | /* Make sure the pipe isn't still relying on us */ | |
1786 | assert_pipe_disabled(dev_priv, pipe); | |
1787 | ||
e5cbfbfb ID |
1788 | /* |
1789 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1790 | * The latter is needed for VGA hotplug / manual detection. | |
1791 | */ | |
b8afb911 | 1792 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1793 | if (pipe == PIPE_B) |
60bfe44f | 1794 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1795 | I915_WRITE(DPLL(pipe), val); |
1796 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1797 | |
1798 | } | |
1799 | ||
1800 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1801 | { | |
d752048d | 1802 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1803 | u32 val; |
1804 | ||
a11b0703 VS |
1805 | /* Make sure the pipe isn't still relying on us */ |
1806 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1807 | |
a11b0703 | 1808 | /* Set PLL en = 0 */ |
60bfe44f VS |
1809 | val = DPLL_SSC_REF_CLK_CHV | |
1810 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1811 | if (pipe != PIPE_A) |
1812 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1813 | I915_WRITE(DPLL(pipe), val); | |
1814 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1815 | |
a580516d | 1816 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1817 | |
1818 | /* Disable 10bit clock to display controller */ | |
1819 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1820 | val &= ~DPIO_DCLKP_EN; | |
1821 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1822 | ||
a580516d | 1823 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1824 | } |
1825 | ||
e4607fcf | 1826 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1827 | struct intel_digital_port *dport, |
1828 | unsigned int expected_mask) | |
89b667f8 JB |
1829 | { |
1830 | u32 port_mask; | |
f0f59a00 | 1831 | i915_reg_t dpll_reg; |
89b667f8 | 1832 | |
e4607fcf CML |
1833 | switch (dport->port) { |
1834 | case PORT_B: | |
89b667f8 | 1835 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1836 | dpll_reg = DPLL(0); |
e4607fcf CML |
1837 | break; |
1838 | case PORT_C: | |
89b667f8 | 1839 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1840 | dpll_reg = DPLL(0); |
9b6de0a1 | 1841 | expected_mask <<= 4; |
00fc31b7 CML |
1842 | break; |
1843 | case PORT_D: | |
1844 | port_mask = DPLL_PORTD_READY_MASK; | |
1845 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1846 | break; |
1847 | default: | |
1848 | BUG(); | |
1849 | } | |
89b667f8 | 1850 | |
9b6de0a1 VS |
1851 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1852 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1853 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1854 | } |
1855 | ||
b14b1055 DV |
1856 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1857 | { | |
1858 | struct drm_device *dev = crtc->base.dev; | |
1859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1860 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1861 | ||
be19f0ff CW |
1862 | if (WARN_ON(pll == NULL)) |
1863 | return; | |
1864 | ||
3e369b76 | 1865 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1866 | if (pll->active == 0) { |
1867 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1868 | WARN_ON(pll->on); | |
1869 | assert_shared_dpll_disabled(dev_priv, pll); | |
1870 | ||
1871 | pll->mode_set(dev_priv, pll); | |
1872 | } | |
1873 | } | |
1874 | ||
92f2584a | 1875 | /** |
85b3894f | 1876 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1877 | * @dev_priv: i915 private structure |
1878 | * @pipe: pipe PLL to enable | |
1879 | * | |
1880 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1881 | * drives the transcoder clock. | |
1882 | */ | |
85b3894f | 1883 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1884 | { |
3d13ef2e DL |
1885 | struct drm_device *dev = crtc->base.dev; |
1886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1887 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1888 | |
87a875bb | 1889 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1890 | return; |
1891 | ||
3e369b76 | 1892 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1893 | return; |
ee7b9f93 | 1894 | |
74dd6928 | 1895 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1896 | pll->name, pll->active, pll->on, |
e2b78267 | 1897 | crtc->base.base.id); |
92f2584a | 1898 | |
cdbd2316 DV |
1899 | if (pll->active++) { |
1900 | WARN_ON(!pll->on); | |
e9d6944e | 1901 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1902 | return; |
1903 | } | |
f4a091c7 | 1904 | WARN_ON(pll->on); |
ee7b9f93 | 1905 | |
bd2bb1b9 PZ |
1906 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1907 | ||
46edb027 | 1908 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1909 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1910 | pll->on = true; |
92f2584a JB |
1911 | } |
1912 | ||
f6daaec2 | 1913 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1914 | { |
3d13ef2e DL |
1915 | struct drm_device *dev = crtc->base.dev; |
1916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1917 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1918 | |
92f2584a | 1919 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1920 | if (INTEL_INFO(dev)->gen < 5) |
1921 | return; | |
1922 | ||
eddfcbcd ML |
1923 | if (pll == NULL) |
1924 | return; | |
92f2584a | 1925 | |
eddfcbcd | 1926 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1927 | return; |
7a419866 | 1928 | |
46edb027 DV |
1929 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1930 | pll->name, pll->active, pll->on, | |
e2b78267 | 1931 | crtc->base.base.id); |
7a419866 | 1932 | |
48da64a8 | 1933 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1934 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1935 | return; |
1936 | } | |
1937 | ||
e9d6944e | 1938 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1939 | WARN_ON(!pll->on); |
cdbd2316 | 1940 | if (--pll->active) |
7a419866 | 1941 | return; |
ee7b9f93 | 1942 | |
46edb027 | 1943 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1944 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1945 | pll->on = false; |
bd2bb1b9 PZ |
1946 | |
1947 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1948 | } |
1949 | ||
b8a4f404 PZ |
1950 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1951 | enum pipe pipe) | |
040484af | 1952 | { |
23670b32 | 1953 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1954 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1955 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1956 | i915_reg_t reg; |
1957 | uint32_t val, pipeconf_val; | |
040484af JB |
1958 | |
1959 | /* PCH only available on ILK+ */ | |
55522f37 | 1960 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1961 | |
1962 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1963 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1964 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1965 | |
1966 | /* FDI must be feeding us bits for PCH ports */ | |
1967 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1968 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1969 | ||
23670b32 DV |
1970 | if (HAS_PCH_CPT(dev)) { |
1971 | /* Workaround: Set the timing override bit before enabling the | |
1972 | * pch transcoder. */ | |
1973 | reg = TRANS_CHICKEN2(pipe); | |
1974 | val = I915_READ(reg); | |
1975 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1976 | I915_WRITE(reg, val); | |
59c859d6 | 1977 | } |
23670b32 | 1978 | |
ab9412ba | 1979 | reg = PCH_TRANSCONF(pipe); |
040484af | 1980 | val = I915_READ(reg); |
5f7f726d | 1981 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1982 | |
1983 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1984 | /* | |
c5de7c6f VS |
1985 | * Make the BPC in transcoder be consistent with |
1986 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1987 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1988 | */ |
dfd07d72 | 1989 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1990 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1991 | val |= PIPECONF_8BPC; | |
1992 | else | |
1993 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1994 | } |
5f7f726d PZ |
1995 | |
1996 | val &= ~TRANS_INTERLACE_MASK; | |
1997 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1998 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1999 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2000 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2001 | else | |
2002 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2003 | else |
2004 | val |= TRANS_PROGRESSIVE; | |
2005 | ||
040484af JB |
2006 | I915_WRITE(reg, val | TRANS_ENABLE); |
2007 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2008 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2009 | } |
2010 | ||
8fb033d7 | 2011 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2012 | enum transcoder cpu_transcoder) |
040484af | 2013 | { |
8fb033d7 | 2014 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2015 | |
2016 | /* PCH only available on ILK+ */ | |
55522f37 | 2017 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2018 | |
8fb033d7 | 2019 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2020 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2021 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2022 | |
223a6fdf | 2023 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2024 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2025 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2026 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2027 | |
25f3ef11 | 2028 | val = TRANS_ENABLE; |
937bb610 | 2029 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2030 | |
9a76b1c6 PZ |
2031 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2032 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2033 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2034 | else |
2035 | val |= TRANS_PROGRESSIVE; | |
2036 | ||
ab9412ba DV |
2037 | I915_WRITE(LPT_TRANSCONF, val); |
2038 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2039 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2040 | } |
2041 | ||
b8a4f404 PZ |
2042 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2043 | enum pipe pipe) | |
040484af | 2044 | { |
23670b32 | 2045 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2046 | i915_reg_t reg; |
2047 | uint32_t val; | |
040484af JB |
2048 | |
2049 | /* FDI relies on the transcoder */ | |
2050 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2051 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2052 | ||
291906f1 JB |
2053 | /* Ports must be off as well */ |
2054 | assert_pch_ports_disabled(dev_priv, pipe); | |
2055 | ||
ab9412ba | 2056 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2057 | val = I915_READ(reg); |
2058 | val &= ~TRANS_ENABLE; | |
2059 | I915_WRITE(reg, val); | |
2060 | /* wait for PCH transcoder off, transcoder state */ | |
2061 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2062 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2063 | |
c465613b | 2064 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2065 | /* Workaround: Clear the timing override chicken bit again. */ |
2066 | reg = TRANS_CHICKEN2(pipe); | |
2067 | val = I915_READ(reg); | |
2068 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2069 | I915_WRITE(reg, val); | |
2070 | } | |
040484af JB |
2071 | } |
2072 | ||
ab4d966c | 2073 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2074 | { |
8fb033d7 PZ |
2075 | u32 val; |
2076 | ||
ab9412ba | 2077 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2078 | val &= ~TRANS_ENABLE; |
ab9412ba | 2079 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2080 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2081 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2082 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2083 | |
2084 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2085 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2086 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2087 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2088 | } |
2089 | ||
b24e7179 | 2090 | /** |
309cfea8 | 2091 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2092 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2093 | * |
0372264a | 2094 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2095 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2096 | */ |
e1fdc473 | 2097 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2098 | { |
0372264a PZ |
2099 | struct drm_device *dev = crtc->base.dev; |
2100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2101 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2102 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2103 | enum pipe pch_transcoder; |
f0f59a00 | 2104 | i915_reg_t reg; |
b24e7179 JB |
2105 | u32 val; |
2106 | ||
9e2ee2dd VS |
2107 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2108 | ||
58c6eaa2 | 2109 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2110 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2111 | assert_sprites_disabled(dev_priv, pipe); |
2112 | ||
681e5811 | 2113 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2114 | pch_transcoder = TRANSCODER_A; |
2115 | else | |
2116 | pch_transcoder = pipe; | |
2117 | ||
b24e7179 JB |
2118 | /* |
2119 | * A pipe without a PLL won't actually be able to drive bits from | |
2120 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2121 | * need the check. | |
2122 | */ | |
50360403 | 2123 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2124 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2125 | assert_dsi_pll_enabled(dev_priv); |
2126 | else | |
2127 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2128 | else { |
6e3c9717 | 2129 | if (crtc->config->has_pch_encoder) { |
040484af | 2130 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2131 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2132 | assert_fdi_tx_pll_enabled(dev_priv, |
2133 | (enum pipe) cpu_transcoder); | |
040484af JB |
2134 | } |
2135 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2136 | } | |
b24e7179 | 2137 | |
702e7a56 | 2138 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2139 | val = I915_READ(reg); |
7ad25d48 | 2140 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2141 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2142 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2143 | return; |
7ad25d48 | 2144 | } |
00d70b15 CW |
2145 | |
2146 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2147 | POSTING_READ(reg); |
b7792d8b VS |
2148 | |
2149 | /* | |
2150 | * Until the pipe starts DSL will read as 0, which would cause | |
2151 | * an apparent vblank timestamp jump, which messes up also the | |
2152 | * frame count when it's derived from the timestamps. So let's | |
2153 | * wait for the pipe to start properly before we call | |
2154 | * drm_crtc_vblank_on() | |
2155 | */ | |
2156 | if (dev->max_vblank_count == 0 && | |
2157 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2158 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2159 | } |
2160 | ||
2161 | /** | |
309cfea8 | 2162 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2163 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2164 | * |
575f7ab7 VS |
2165 | * Disable the pipe of @crtc, making sure that various hardware |
2166 | * specific requirements are met, if applicable, e.g. plane | |
2167 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2168 | * |
2169 | * Will wait until the pipe has shut down before returning. | |
2170 | */ | |
575f7ab7 | 2171 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2172 | { |
575f7ab7 | 2173 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2174 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2175 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2176 | i915_reg_t reg; |
b24e7179 JB |
2177 | u32 val; |
2178 | ||
9e2ee2dd VS |
2179 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2180 | ||
b24e7179 JB |
2181 | /* |
2182 | * Make sure planes won't keep trying to pump pixels to us, | |
2183 | * or we might hang the display. | |
2184 | */ | |
2185 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2186 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2187 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2188 | |
702e7a56 | 2189 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2190 | val = I915_READ(reg); |
00d70b15 CW |
2191 | if ((val & PIPECONF_ENABLE) == 0) |
2192 | return; | |
2193 | ||
67adc644 VS |
2194 | /* |
2195 | * Double wide has implications for planes | |
2196 | * so best keep it disabled when not needed. | |
2197 | */ | |
6e3c9717 | 2198 | if (crtc->config->double_wide) |
67adc644 VS |
2199 | val &= ~PIPECONF_DOUBLE_WIDE; |
2200 | ||
2201 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2202 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2203 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2204 | val &= ~PIPECONF_ENABLE; |
2205 | ||
2206 | I915_WRITE(reg, val); | |
2207 | if ((val & PIPECONF_ENABLE) == 0) | |
2208 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2209 | } |
2210 | ||
693db184 CW |
2211 | static bool need_vtd_wa(struct drm_device *dev) |
2212 | { | |
2213 | #ifdef CONFIG_INTEL_IOMMU | |
2214 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2215 | return true; | |
2216 | #endif | |
2217 | return false; | |
2218 | } | |
2219 | ||
832be82f VS |
2220 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2221 | { | |
2222 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2223 | } | |
2224 | ||
7b49f948 VS |
2225 | static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv, |
2226 | uint64_t fb_modifier, unsigned int cpp) | |
2227 | { | |
2228 | switch (fb_modifier) { | |
2229 | case DRM_FORMAT_MOD_NONE: | |
2230 | return cpp; | |
2231 | case I915_FORMAT_MOD_X_TILED: | |
2232 | if (IS_GEN2(dev_priv)) | |
2233 | return 128; | |
2234 | else | |
2235 | return 512; | |
2236 | case I915_FORMAT_MOD_Y_TILED: | |
2237 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2238 | return 128; | |
2239 | else | |
2240 | return 512; | |
2241 | case I915_FORMAT_MOD_Yf_TILED: | |
2242 | switch (cpp) { | |
2243 | case 1: | |
2244 | return 64; | |
2245 | case 2: | |
2246 | case 4: | |
2247 | return 128; | |
2248 | case 8: | |
2249 | case 16: | |
2250 | return 256; | |
2251 | default: | |
2252 | MISSING_CASE(cpp); | |
2253 | return cpp; | |
2254 | } | |
2255 | break; | |
2256 | default: | |
2257 | MISSING_CASE(fb_modifier); | |
2258 | return cpp; | |
2259 | } | |
2260 | } | |
2261 | ||
832be82f VS |
2262 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2263 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2264 | { |
832be82f VS |
2265 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2266 | return 1; | |
2267 | else | |
2268 | return intel_tile_size(dev_priv) / | |
2269 | intel_tile_width(dev_priv, fb_modifier, cpp); | |
6761dd31 TU |
2270 | } |
2271 | ||
2272 | unsigned int | |
2273 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2274 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2275 | { |
832be82f VS |
2276 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2277 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2278 | ||
2279 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2280 | } |
2281 | ||
75c82a53 | 2282 | static void |
f64b98cd TU |
2283 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2284 | const struct drm_plane_state *plane_state) | |
2285 | { | |
832be82f | 2286 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
7723f47d | 2287 | struct intel_rotation_info *info = &view->params.rotated; |
d9b3288e | 2288 | unsigned int tile_size, tile_width, tile_height, cpp; |
50470bb0 | 2289 | |
f64b98cd TU |
2290 | *view = i915_ggtt_view_normal; |
2291 | ||
50470bb0 | 2292 | if (!plane_state) |
75c82a53 | 2293 | return; |
50470bb0 | 2294 | |
121920fa | 2295 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
75c82a53 | 2296 | return; |
50470bb0 | 2297 | |
9abc4648 | 2298 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2299 | |
2300 | info->height = fb->height; | |
2301 | info->pixel_format = fb->pixel_format; | |
2302 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2303 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2304 | info->fb_modifier = fb->modifier[0]; |
2305 | ||
d9b3288e VS |
2306 | tile_size = intel_tile_size(dev_priv); |
2307 | ||
2308 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
b16bb01f | 2309 | tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp); |
d9b3288e VS |
2310 | tile_height = tile_size / tile_width; |
2311 | ||
2312 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width); | |
84fe03f7 | 2313 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); |
d9b3288e | 2314 | info->size = info->width_pages * info->height_pages * tile_size; |
84fe03f7 | 2315 | |
89e3e142 | 2316 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2317 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
d9b3288e VS |
2318 | tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp); |
2319 | tile_height = tile_size / tile_width; | |
2320 | ||
2321 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width); | |
832be82f | 2322 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height); |
d9b3288e | 2323 | info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size; |
89e3e142 | 2324 | } |
f64b98cd TU |
2325 | } |
2326 | ||
603525d7 | 2327 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2328 | { |
2329 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2330 | return 256 * 1024; | |
985b8bb4 | 2331 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2332 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2333 | return 128 * 1024; |
2334 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2335 | return 4 * 1024; | |
2336 | else | |
44c5905e | 2337 | return 0; |
4e9a86b6 VS |
2338 | } |
2339 | ||
603525d7 VS |
2340 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2341 | uint64_t fb_modifier) | |
2342 | { | |
2343 | switch (fb_modifier) { | |
2344 | case DRM_FORMAT_MOD_NONE: | |
2345 | return intel_linear_alignment(dev_priv); | |
2346 | case I915_FORMAT_MOD_X_TILED: | |
2347 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2348 | return 256 * 1024; | |
2349 | return 0; | |
2350 | case I915_FORMAT_MOD_Y_TILED: | |
2351 | case I915_FORMAT_MOD_Yf_TILED: | |
2352 | return 1 * 1024 * 1024; | |
2353 | default: | |
2354 | MISSING_CASE(fb_modifier); | |
2355 | return 0; | |
2356 | } | |
2357 | } | |
2358 | ||
127bd2ac | 2359 | int |
850c4cdc TU |
2360 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2361 | struct drm_framebuffer *fb, | |
7580d774 | 2362 | const struct drm_plane_state *plane_state) |
6b95a207 | 2363 | { |
850c4cdc | 2364 | struct drm_device *dev = fb->dev; |
ce453d81 | 2365 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2366 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2367 | struct i915_ggtt_view view; |
6b95a207 KH |
2368 | u32 alignment; |
2369 | int ret; | |
2370 | ||
ebcdd39e MR |
2371 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2372 | ||
603525d7 | 2373 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2374 | |
75c82a53 | 2375 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2376 | |
693db184 CW |
2377 | /* Note that the w/a also requires 64 PTE of padding following the |
2378 | * bo. We currently fill all unused PTE with the shadow page and so | |
2379 | * we should always have valid PTE following the scanout preventing | |
2380 | * the VT-d warning. | |
2381 | */ | |
2382 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2383 | alignment = 256 * 1024; | |
2384 | ||
d6dd6843 PZ |
2385 | /* |
2386 | * Global gtt pte registers are special registers which actually forward | |
2387 | * writes to a chunk of system memory. Which means that there is no risk | |
2388 | * that the register values disappear as soon as we call | |
2389 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2390 | * pin/unpin/fence and not more. | |
2391 | */ | |
2392 | intel_runtime_pm_get(dev_priv); | |
2393 | ||
7580d774 ML |
2394 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2395 | &view); | |
48b956c5 | 2396 | if (ret) |
b26a6b35 | 2397 | goto err_pm; |
6b95a207 KH |
2398 | |
2399 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2400 | * fence, whereas 965+ only requires a fence if using | |
2401 | * framebuffer compression. For simplicity, we always install | |
2402 | * a fence as the cost is not that onerous. | |
2403 | */ | |
9807216f VK |
2404 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2405 | ret = i915_gem_object_get_fence(obj); | |
2406 | if (ret == -EDEADLK) { | |
2407 | /* | |
2408 | * -EDEADLK means there are no free fences | |
2409 | * no pending flips. | |
2410 | * | |
2411 | * This is propagated to atomic, but it uses | |
2412 | * -EDEADLK to force a locking recovery, so | |
2413 | * change the returned error to -EBUSY. | |
2414 | */ | |
2415 | ret = -EBUSY; | |
2416 | goto err_unpin; | |
2417 | } else if (ret) | |
2418 | goto err_unpin; | |
1690e1eb | 2419 | |
9807216f VK |
2420 | i915_gem_object_pin_fence(obj); |
2421 | } | |
6b95a207 | 2422 | |
d6dd6843 | 2423 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2424 | return 0; |
48b956c5 CW |
2425 | |
2426 | err_unpin: | |
f64b98cd | 2427 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2428 | err_pm: |
d6dd6843 | 2429 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2430 | return ret; |
6b95a207 KH |
2431 | } |
2432 | ||
82bc3b2d TU |
2433 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2434 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2435 | { |
82bc3b2d | 2436 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2437 | struct i915_ggtt_view view; |
82bc3b2d | 2438 | |
ebcdd39e MR |
2439 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2440 | ||
75c82a53 | 2441 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2442 | |
9807216f VK |
2443 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2444 | i915_gem_object_unpin_fence(obj); | |
2445 | ||
f64b98cd | 2446 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2447 | } |
2448 | ||
c2c75131 DV |
2449 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2450 | * is assumed to be a power-of-two. */ | |
54ea9da8 VS |
2451 | u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv, |
2452 | int *x, int *y, | |
2453 | uint64_t fb_modifier, | |
2454 | unsigned int cpp, | |
2455 | unsigned int pitch) | |
c2c75131 | 2456 | { |
b5c65338 | 2457 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
d843310d | 2458 | unsigned int tile_size, tile_width, tile_height; |
bc752862 | 2459 | unsigned int tile_rows, tiles; |
c2c75131 | 2460 | |
d843310d VS |
2461 | tile_size = intel_tile_size(dev_priv); |
2462 | tile_width = intel_tile_width(dev_priv, fb_modifier, cpp); | |
2463 | tile_height = tile_size / tile_width; | |
2464 | ||
2465 | tile_rows = *y / tile_height; | |
2466 | *y %= tile_height; | |
c2c75131 | 2467 | |
d843310d VS |
2468 | tiles = *x / (tile_width/cpp); |
2469 | *x %= tile_width/cpp; | |
bc752862 | 2470 | |
d843310d | 2471 | return tile_rows * pitch * tile_height + tiles * tile_size; |
bc752862 | 2472 | } else { |
4e9a86b6 | 2473 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2474 | unsigned int offset; |
2475 | ||
2476 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2477 | *y = (offset & alignment) / pitch; |
2478 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2479 | return offset & ~alignment; | |
bc752862 | 2480 | } |
c2c75131 DV |
2481 | } |
2482 | ||
b35d63fa | 2483 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2484 | { |
2485 | switch (format) { | |
2486 | case DISPPLANE_8BPP: | |
2487 | return DRM_FORMAT_C8; | |
2488 | case DISPPLANE_BGRX555: | |
2489 | return DRM_FORMAT_XRGB1555; | |
2490 | case DISPPLANE_BGRX565: | |
2491 | return DRM_FORMAT_RGB565; | |
2492 | default: | |
2493 | case DISPPLANE_BGRX888: | |
2494 | return DRM_FORMAT_XRGB8888; | |
2495 | case DISPPLANE_RGBX888: | |
2496 | return DRM_FORMAT_XBGR8888; | |
2497 | case DISPPLANE_BGRX101010: | |
2498 | return DRM_FORMAT_XRGB2101010; | |
2499 | case DISPPLANE_RGBX101010: | |
2500 | return DRM_FORMAT_XBGR2101010; | |
2501 | } | |
2502 | } | |
2503 | ||
bc8d7dff DL |
2504 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2505 | { | |
2506 | switch (format) { | |
2507 | case PLANE_CTL_FORMAT_RGB_565: | |
2508 | return DRM_FORMAT_RGB565; | |
2509 | default: | |
2510 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2511 | if (rgb_order) { | |
2512 | if (alpha) | |
2513 | return DRM_FORMAT_ABGR8888; | |
2514 | else | |
2515 | return DRM_FORMAT_XBGR8888; | |
2516 | } else { | |
2517 | if (alpha) | |
2518 | return DRM_FORMAT_ARGB8888; | |
2519 | else | |
2520 | return DRM_FORMAT_XRGB8888; | |
2521 | } | |
2522 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2523 | if (rgb_order) | |
2524 | return DRM_FORMAT_XBGR2101010; | |
2525 | else | |
2526 | return DRM_FORMAT_XRGB2101010; | |
2527 | } | |
2528 | } | |
2529 | ||
5724dbd1 | 2530 | static bool |
f6936e29 DV |
2531 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2532 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2533 | { |
2534 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2535 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2536 | struct drm_i915_gem_object *obj = NULL; |
2537 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2538 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2539 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2540 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2541 | PAGE_SIZE); | |
2542 | ||
2543 | size_aligned -= base_aligned; | |
46f297fb | 2544 | |
ff2652ea CW |
2545 | if (plane_config->size == 0) |
2546 | return false; | |
2547 | ||
3badb49f PZ |
2548 | /* If the FB is too big, just don't use it since fbdev is not very |
2549 | * important and we should probably use that space with FBC or other | |
2550 | * features. */ | |
2551 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2552 | return false; | |
2553 | ||
12c83d99 TU |
2554 | mutex_lock(&dev->struct_mutex); |
2555 | ||
f37b5c2b DV |
2556 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2557 | base_aligned, | |
2558 | base_aligned, | |
2559 | size_aligned); | |
12c83d99 TU |
2560 | if (!obj) { |
2561 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2562 | return false; |
12c83d99 | 2563 | } |
46f297fb | 2564 | |
49af449b DL |
2565 | obj->tiling_mode = plane_config->tiling; |
2566 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2567 | obj->stride = fb->pitches[0]; |
46f297fb | 2568 | |
6bf129df DL |
2569 | mode_cmd.pixel_format = fb->pixel_format; |
2570 | mode_cmd.width = fb->width; | |
2571 | mode_cmd.height = fb->height; | |
2572 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2573 | mode_cmd.modifier[0] = fb->modifier[0]; |
2574 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2575 | |
6bf129df | 2576 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2577 | &mode_cmd, obj)) { |
46f297fb JB |
2578 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2579 | goto out_unref_obj; | |
2580 | } | |
12c83d99 | 2581 | |
46f297fb | 2582 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2583 | |
f6936e29 | 2584 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2585 | return true; |
46f297fb JB |
2586 | |
2587 | out_unref_obj: | |
2588 | drm_gem_object_unreference(&obj->base); | |
2589 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2590 | return false; |
2591 | } | |
2592 | ||
afd65eb4 MR |
2593 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2594 | static void | |
2595 | update_state_fb(struct drm_plane *plane) | |
2596 | { | |
2597 | if (plane->fb == plane->state->fb) | |
2598 | return; | |
2599 | ||
2600 | if (plane->state->fb) | |
2601 | drm_framebuffer_unreference(plane->state->fb); | |
2602 | plane->state->fb = plane->fb; | |
2603 | if (plane->state->fb) | |
2604 | drm_framebuffer_reference(plane->state->fb); | |
2605 | } | |
2606 | ||
5724dbd1 | 2607 | static void |
f6936e29 DV |
2608 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2609 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2610 | { |
2611 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2612 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2613 | struct drm_crtc *c; |
2614 | struct intel_crtc *i; | |
2ff8fde1 | 2615 | struct drm_i915_gem_object *obj; |
88595ac9 | 2616 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2617 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2618 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2619 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2620 | struct intel_plane_state *intel_state = |
2621 | to_intel_plane_state(plane_state); | |
88595ac9 | 2622 | struct drm_framebuffer *fb; |
484b41dd | 2623 | |
2d14030b | 2624 | if (!plane_config->fb) |
484b41dd JB |
2625 | return; |
2626 | ||
f6936e29 | 2627 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2628 | fb = &plane_config->fb->base; |
2629 | goto valid_fb; | |
f55548b5 | 2630 | } |
484b41dd | 2631 | |
2d14030b | 2632 | kfree(plane_config->fb); |
484b41dd JB |
2633 | |
2634 | /* | |
2635 | * Failed to alloc the obj, check to see if we should share | |
2636 | * an fb with another CRTC instead | |
2637 | */ | |
70e1e0ec | 2638 | for_each_crtc(dev, c) { |
484b41dd JB |
2639 | i = to_intel_crtc(c); |
2640 | ||
2641 | if (c == &intel_crtc->base) | |
2642 | continue; | |
2643 | ||
2ff8fde1 MR |
2644 | if (!i->active) |
2645 | continue; | |
2646 | ||
88595ac9 DV |
2647 | fb = c->primary->fb; |
2648 | if (!fb) | |
484b41dd JB |
2649 | continue; |
2650 | ||
88595ac9 | 2651 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2652 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2653 | drm_framebuffer_reference(fb); |
2654 | goto valid_fb; | |
484b41dd JB |
2655 | } |
2656 | } | |
88595ac9 | 2657 | |
200757f5 MR |
2658 | /* |
2659 | * We've failed to reconstruct the BIOS FB. Current display state | |
2660 | * indicates that the primary plane is visible, but has a NULL FB, | |
2661 | * which will lead to problems later if we don't fix it up. The | |
2662 | * simplest solution is to just disable the primary plane now and | |
2663 | * pretend the BIOS never had it enabled. | |
2664 | */ | |
2665 | to_intel_plane_state(plane_state)->visible = false; | |
2666 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2667 | intel_pre_disable_primary(&intel_crtc->base); | |
2668 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2669 | ||
88595ac9 DV |
2670 | return; |
2671 | ||
2672 | valid_fb: | |
f44e2659 VS |
2673 | plane_state->src_x = 0; |
2674 | plane_state->src_y = 0; | |
be5651f2 ML |
2675 | plane_state->src_w = fb->width << 16; |
2676 | plane_state->src_h = fb->height << 16; | |
2677 | ||
f44e2659 VS |
2678 | plane_state->crtc_x = 0; |
2679 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2680 | plane_state->crtc_w = fb->width; |
2681 | plane_state->crtc_h = fb->height; | |
2682 | ||
0a8d8a86 MR |
2683 | intel_state->src.x1 = plane_state->src_x; |
2684 | intel_state->src.y1 = plane_state->src_y; | |
2685 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2686 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2687 | intel_state->dst.x1 = plane_state->crtc_x; | |
2688 | intel_state->dst.y1 = plane_state->crtc_y; | |
2689 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2690 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2691 | ||
88595ac9 DV |
2692 | obj = intel_fb_obj(fb); |
2693 | if (obj->tiling_mode != I915_TILING_NONE) | |
2694 | dev_priv->preserve_bios_swizzle = true; | |
2695 | ||
be5651f2 ML |
2696 | drm_framebuffer_reference(fb); |
2697 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2698 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2699 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2700 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2701 | } |
2702 | ||
a8d201af ML |
2703 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2704 | const struct intel_crtc_state *crtc_state, | |
2705 | const struct intel_plane_state *plane_state) | |
81255565 | 2706 | { |
a8d201af | 2707 | struct drm_device *dev = primary->dev; |
81255565 | 2708 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2709 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2710 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2711 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2712 | int plane = intel_crtc->plane; |
54ea9da8 | 2713 | u32 linear_offset; |
81255565 | 2714 | u32 dspcntr; |
f0f59a00 | 2715 | i915_reg_t reg = DSPCNTR(plane); |
ac484963 | 2716 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2717 | int x = plane_state->src.x1 >> 16; |
2718 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2719 | |
f45651ba VS |
2720 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2721 | ||
fdd508a6 | 2722 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2723 | |
2724 | if (INTEL_INFO(dev)->gen < 4) { | |
2725 | if (intel_crtc->pipe == PIPE_B) | |
2726 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2727 | ||
2728 | /* pipesrc and dspsize control the size that is scaled from, | |
2729 | * which should always be the user's requested size. | |
2730 | */ | |
2731 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2732 | ((crtc_state->pipe_src_h - 1) << 16) | |
2733 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2734 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2735 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2736 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2737 | ((crtc_state->pipe_src_h - 1) << 16) | |
2738 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2739 | I915_WRITE(PRIMPOS(plane), 0); |
2740 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2741 | } |
81255565 | 2742 | |
57779d06 VS |
2743 | switch (fb->pixel_format) { |
2744 | case DRM_FORMAT_C8: | |
81255565 JB |
2745 | dspcntr |= DISPPLANE_8BPP; |
2746 | break; | |
57779d06 | 2747 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2748 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2749 | break; |
57779d06 VS |
2750 | case DRM_FORMAT_RGB565: |
2751 | dspcntr |= DISPPLANE_BGRX565; | |
2752 | break; | |
2753 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2754 | dspcntr |= DISPPLANE_BGRX888; |
2755 | break; | |
2756 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2757 | dspcntr |= DISPPLANE_RGBX888; |
2758 | break; | |
2759 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2760 | dspcntr |= DISPPLANE_BGRX101010; |
2761 | break; | |
2762 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2763 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2764 | break; |
2765 | default: | |
baba133a | 2766 | BUG(); |
81255565 | 2767 | } |
57779d06 | 2768 | |
f45651ba VS |
2769 | if (INTEL_INFO(dev)->gen >= 4 && |
2770 | obj->tiling_mode != I915_TILING_NONE) | |
2771 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2772 | |
de1aa629 VS |
2773 | if (IS_G4X(dev)) |
2774 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2775 | ||
ac484963 | 2776 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2777 | |
c2c75131 DV |
2778 | if (INTEL_INFO(dev)->gen >= 4) { |
2779 | intel_crtc->dspaddr_offset = | |
ce1e5c14 | 2780 | intel_compute_tile_offset(dev_priv, &x, &y, |
ac484963 | 2781 | fb->modifier[0], cpp, |
ce1e5c14 | 2782 | fb->pitches[0]); |
c2c75131 DV |
2783 | linear_offset -= intel_crtc->dspaddr_offset; |
2784 | } else { | |
e506a0c6 | 2785 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2786 | } |
e506a0c6 | 2787 | |
a8d201af | 2788 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2789 | dspcntr |= DISPPLANE_ROTATE_180; |
2790 | ||
a8d201af ML |
2791 | x += (crtc_state->pipe_src_w - 1); |
2792 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2793 | |
2794 | /* Finding the last pixel of the last line of the display | |
2795 | data and adding to linear_offset*/ | |
2796 | linear_offset += | |
a8d201af | 2797 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2798 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2799 | } |
2800 | ||
2db3366b PZ |
2801 | intel_crtc->adjusted_x = x; |
2802 | intel_crtc->adjusted_y = y; | |
2803 | ||
48404c1e SJ |
2804 | I915_WRITE(reg, dspcntr); |
2805 | ||
01f2c773 | 2806 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2807 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2808 | I915_WRITE(DSPSURF(plane), |
2809 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2810 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2811 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2812 | } else |
f343c5f6 | 2813 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2814 | POSTING_READ(reg); |
17638cd6 JB |
2815 | } |
2816 | ||
a8d201af ML |
2817 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2818 | struct drm_crtc *crtc) | |
17638cd6 JB |
2819 | { |
2820 | struct drm_device *dev = crtc->dev; | |
2821 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2823 | int plane = intel_crtc->plane; |
f45651ba | 2824 | |
a8d201af ML |
2825 | I915_WRITE(DSPCNTR(plane), 0); |
2826 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2827 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2828 | else |
2829 | I915_WRITE(DSPADDR(plane), 0); | |
2830 | POSTING_READ(DSPCNTR(plane)); | |
2831 | } | |
c9ba6fad | 2832 | |
a8d201af ML |
2833 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2834 | const struct intel_crtc_state *crtc_state, | |
2835 | const struct intel_plane_state *plane_state) | |
2836 | { | |
2837 | struct drm_device *dev = primary->dev; | |
2838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2839 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2840 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2841 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2842 | int plane = intel_crtc->plane; | |
54ea9da8 | 2843 | u32 linear_offset; |
a8d201af ML |
2844 | u32 dspcntr; |
2845 | i915_reg_t reg = DSPCNTR(plane); | |
ac484963 | 2846 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2847 | int x = plane_state->src.x1 >> 16; |
2848 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2849 | |
f45651ba | 2850 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2851 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2852 | |
2853 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2854 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2855 | |
57779d06 VS |
2856 | switch (fb->pixel_format) { |
2857 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2858 | dspcntr |= DISPPLANE_8BPP; |
2859 | break; | |
57779d06 VS |
2860 | case DRM_FORMAT_RGB565: |
2861 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2862 | break; |
57779d06 | 2863 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2864 | dspcntr |= DISPPLANE_BGRX888; |
2865 | break; | |
2866 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2867 | dspcntr |= DISPPLANE_RGBX888; |
2868 | break; | |
2869 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2870 | dspcntr |= DISPPLANE_BGRX101010; |
2871 | break; | |
2872 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2873 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2874 | break; |
2875 | default: | |
baba133a | 2876 | BUG(); |
17638cd6 JB |
2877 | } |
2878 | ||
2879 | if (obj->tiling_mode != I915_TILING_NONE) | |
2880 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2881 | |
f45651ba | 2882 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2883 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2884 | |
ac484963 | 2885 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2886 | intel_crtc->dspaddr_offset = |
ce1e5c14 | 2887 | intel_compute_tile_offset(dev_priv, &x, &y, |
ac484963 | 2888 | fb->modifier[0], cpp, |
ce1e5c14 | 2889 | fb->pitches[0]); |
c2c75131 | 2890 | linear_offset -= intel_crtc->dspaddr_offset; |
a8d201af | 2891 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2892 | dspcntr |= DISPPLANE_ROTATE_180; |
2893 | ||
2894 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2895 | x += (crtc_state->pipe_src_w - 1); |
2896 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2897 | |
2898 | /* Finding the last pixel of the last line of the display | |
2899 | data and adding to linear_offset*/ | |
2900 | linear_offset += | |
a8d201af | 2901 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2902 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2903 | } |
2904 | } | |
2905 | ||
2db3366b PZ |
2906 | intel_crtc->adjusted_x = x; |
2907 | intel_crtc->adjusted_y = y; | |
2908 | ||
48404c1e | 2909 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2910 | |
01f2c773 | 2911 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2912 | I915_WRITE(DSPSURF(plane), |
2913 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2914 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2915 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2916 | } else { | |
2917 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2918 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2919 | } | |
17638cd6 | 2920 | POSTING_READ(reg); |
17638cd6 JB |
2921 | } |
2922 | ||
7b49f948 VS |
2923 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2924 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2925 | { |
7b49f948 | 2926 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2927 | return 64; |
7b49f948 VS |
2928 | } else { |
2929 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2930 | ||
2931 | return intel_tile_width(dev_priv, fb_modifier, cpp); | |
b321803d DL |
2932 | } |
2933 | } | |
2934 | ||
44eb0cb9 MK |
2935 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2936 | struct drm_i915_gem_object *obj, | |
2937 | unsigned int plane) | |
121920fa | 2938 | { |
ce7f1728 | 2939 | struct i915_ggtt_view view; |
dedf278c | 2940 | struct i915_vma *vma; |
44eb0cb9 | 2941 | u64 offset; |
121920fa | 2942 | |
e7941294 | 2943 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
ce7f1728 | 2944 | intel_plane->base.state); |
121920fa | 2945 | |
ce7f1728 | 2946 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2947 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2948 | view.type)) |
dedf278c TU |
2949 | return -1; |
2950 | ||
44eb0cb9 | 2951 | offset = vma->node.start; |
dedf278c TU |
2952 | |
2953 | if (plane == 1) { | |
7723f47d | 2954 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2955 | PAGE_SIZE; |
2956 | } | |
2957 | ||
44eb0cb9 MK |
2958 | WARN_ON(upper_32_bits(offset)); |
2959 | ||
2960 | return lower_32_bits(offset); | |
121920fa TU |
2961 | } |
2962 | ||
e435d6e5 ML |
2963 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2964 | { | |
2965 | struct drm_device *dev = intel_crtc->base.dev; | |
2966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2967 | ||
2968 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2969 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2970 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2971 | } |
2972 | ||
a1b2278e CK |
2973 | /* |
2974 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2975 | */ | |
0583236e | 2976 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2977 | { |
a1b2278e CK |
2978 | struct intel_crtc_scaler_state *scaler_state; |
2979 | int i; | |
2980 | ||
a1b2278e CK |
2981 | scaler_state = &intel_crtc->config->scaler_state; |
2982 | ||
2983 | /* loop through and disable scalers that aren't in use */ | |
2984 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2985 | if (!scaler_state->scalers[i].in_use) |
2986 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2987 | } |
2988 | } | |
2989 | ||
6156a456 | 2990 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2991 | { |
6156a456 | 2992 | switch (pixel_format) { |
d161cf7a | 2993 | case DRM_FORMAT_C8: |
c34ce3d1 | 2994 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2995 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2996 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2997 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2998 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2999 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3000 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3001 | /* |
3002 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3003 | * to be already pre-multiplied. We need to add a knob (or a different | |
3004 | * DRM_FORMAT) for user-space to configure that. | |
3005 | */ | |
f75fb42a | 3006 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3007 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3008 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3009 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3010 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3011 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3012 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3013 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3014 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3015 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3016 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3017 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3018 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3019 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3020 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3021 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3022 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3023 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3024 | default: |
4249eeef | 3025 | MISSING_CASE(pixel_format); |
70d21f0e | 3026 | } |
8cfcba41 | 3027 | |
c34ce3d1 | 3028 | return 0; |
6156a456 | 3029 | } |
70d21f0e | 3030 | |
6156a456 CK |
3031 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3032 | { | |
6156a456 | 3033 | switch (fb_modifier) { |
30af77c4 | 3034 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3035 | break; |
30af77c4 | 3036 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3037 | return PLANE_CTL_TILED_X; |
b321803d | 3038 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3039 | return PLANE_CTL_TILED_Y; |
b321803d | 3040 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3041 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3042 | default: |
6156a456 | 3043 | MISSING_CASE(fb_modifier); |
70d21f0e | 3044 | } |
8cfcba41 | 3045 | |
c34ce3d1 | 3046 | return 0; |
6156a456 | 3047 | } |
70d21f0e | 3048 | |
6156a456 CK |
3049 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3050 | { | |
3b7a5119 | 3051 | switch (rotation) { |
6156a456 CK |
3052 | case BIT(DRM_ROTATE_0): |
3053 | break; | |
1e8df167 SJ |
3054 | /* |
3055 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3056 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3057 | */ | |
3b7a5119 | 3058 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3059 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3060 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3061 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3062 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3063 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3064 | default: |
3065 | MISSING_CASE(rotation); | |
3066 | } | |
3067 | ||
c34ce3d1 | 3068 | return 0; |
6156a456 CK |
3069 | } |
3070 | ||
a8d201af ML |
3071 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3072 | const struct intel_crtc_state *crtc_state, | |
3073 | const struct intel_plane_state *plane_state) | |
6156a456 | 3074 | { |
a8d201af | 3075 | struct drm_device *dev = plane->dev; |
6156a456 | 3076 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3078 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3079 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3080 | int pipe = intel_crtc->pipe; |
3081 | u32 plane_ctl, stride_div, stride; | |
3082 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3083 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3084 | int x_offset, y_offset; |
44eb0cb9 | 3085 | u32 surf_addr; |
a8d201af ML |
3086 | int scaler_id = plane_state->scaler_id; |
3087 | int src_x = plane_state->src.x1 >> 16; | |
3088 | int src_y = plane_state->src.y1 >> 16; | |
3089 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3090 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3091 | int dst_x = plane_state->dst.x1; | |
3092 | int dst_y = plane_state->dst.y1; | |
3093 | int dst_w = drm_rect_width(&plane_state->dst); | |
3094 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3095 | |
6156a456 CK |
3096 | plane_ctl = PLANE_CTL_ENABLE | |
3097 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3098 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3099 | ||
3100 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3101 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3102 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3103 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3104 | ||
7b49f948 | 3105 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3106 | fb->pixel_format); |
dedf278c | 3107 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3108 | |
a42e5a23 PZ |
3109 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3110 | ||
3b7a5119 | 3111 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3112 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3113 | ||
3b7a5119 | 3114 | /* stride = Surface height in tiles */ |
832be82f | 3115 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3116 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3117 | x_offset = stride * tile_height - src_y - src_h; |
3118 | y_offset = src_x; | |
6156a456 | 3119 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3120 | } else { |
3121 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3122 | x_offset = src_x; |
3123 | y_offset = src_y; | |
6156a456 | 3124 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3125 | } |
3126 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3127 | |
2db3366b PZ |
3128 | intel_crtc->adjusted_x = x_offset; |
3129 | intel_crtc->adjusted_y = y_offset; | |
3130 | ||
70d21f0e | 3131 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3132 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3133 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3134 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3135 | |
3136 | if (scaler_id >= 0) { | |
3137 | uint32_t ps_ctrl = 0; | |
3138 | ||
3139 | WARN_ON(!dst_w || !dst_h); | |
3140 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3141 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3142 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3143 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3144 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3145 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3146 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3147 | } else { | |
3148 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3149 | } | |
3150 | ||
121920fa | 3151 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3152 | |
3153 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3154 | } | |
3155 | ||
a8d201af ML |
3156 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3157 | struct drm_crtc *crtc) | |
17638cd6 JB |
3158 | { |
3159 | struct drm_device *dev = crtc->dev; | |
3160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3161 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3162 | |
a8d201af ML |
3163 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3164 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3165 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3166 | } | |
29b9bde6 | 3167 | |
a8d201af ML |
3168 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3169 | static int | |
3170 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3171 | int x, int y, enum mode_set_atomic state) | |
3172 | { | |
3173 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3174 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3175 | ||
3176 | return -ENODEV; | |
81255565 JB |
3177 | } |
3178 | ||
7514747d | 3179 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3180 | { |
96a02917 VS |
3181 | struct drm_crtc *crtc; |
3182 | ||
70e1e0ec | 3183 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3184 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3185 | enum plane plane = intel_crtc->plane; | |
3186 | ||
3187 | intel_prepare_page_flip(dev, plane); | |
3188 | intel_finish_page_flip_plane(dev, plane); | |
3189 | } | |
7514747d VS |
3190 | } |
3191 | ||
3192 | static void intel_update_primary_planes(struct drm_device *dev) | |
3193 | { | |
7514747d | 3194 | struct drm_crtc *crtc; |
96a02917 | 3195 | |
70e1e0ec | 3196 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3197 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3198 | struct intel_plane_state *plane_state; | |
96a02917 | 3199 | |
11c22da6 | 3200 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3201 | plane_state = to_intel_plane_state(plane->base.state); |
3202 | ||
a8d201af ML |
3203 | if (plane_state->visible) |
3204 | plane->update_plane(&plane->base, | |
3205 | to_intel_crtc_state(crtc->state), | |
3206 | plane_state); | |
11c22da6 ML |
3207 | |
3208 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3209 | } |
3210 | } | |
3211 | ||
7514747d VS |
3212 | void intel_prepare_reset(struct drm_device *dev) |
3213 | { | |
3214 | /* no reset support for gen2 */ | |
3215 | if (IS_GEN2(dev)) | |
3216 | return; | |
3217 | ||
3218 | /* reset doesn't touch the display */ | |
3219 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3220 | return; | |
3221 | ||
3222 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3223 | /* |
3224 | * Disabling the crtcs gracefully seems nicer. Also the | |
3225 | * g33 docs say we should at least disable all the planes. | |
3226 | */ | |
6b72d486 | 3227 | intel_display_suspend(dev); |
7514747d VS |
3228 | } |
3229 | ||
3230 | void intel_finish_reset(struct drm_device *dev) | |
3231 | { | |
3232 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3233 | ||
3234 | /* | |
3235 | * Flips in the rings will be nuked by the reset, | |
3236 | * so complete all pending flips so that user space | |
3237 | * will get its events and not get stuck. | |
3238 | */ | |
3239 | intel_complete_page_flips(dev); | |
3240 | ||
3241 | /* no reset support for gen2 */ | |
3242 | if (IS_GEN2(dev)) | |
3243 | return; | |
3244 | ||
3245 | /* reset doesn't touch the display */ | |
3246 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3247 | /* | |
3248 | * Flips in the rings have been nuked by the reset, | |
3249 | * so update the base address of all primary | |
3250 | * planes to the the last fb to make sure we're | |
3251 | * showing the correct fb after a reset. | |
11c22da6 ML |
3252 | * |
3253 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3254 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3255 | */ |
3256 | intel_update_primary_planes(dev); | |
3257 | return; | |
3258 | } | |
3259 | ||
3260 | /* | |
3261 | * The display has been reset as well, | |
3262 | * so need a full re-initialization. | |
3263 | */ | |
3264 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3265 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3266 | ||
3267 | intel_modeset_init_hw(dev); | |
3268 | ||
3269 | spin_lock_irq(&dev_priv->irq_lock); | |
3270 | if (dev_priv->display.hpd_irq_setup) | |
3271 | dev_priv->display.hpd_irq_setup(dev); | |
3272 | spin_unlock_irq(&dev_priv->irq_lock); | |
3273 | ||
043e9bda | 3274 | intel_display_resume(dev); |
7514747d VS |
3275 | |
3276 | intel_hpd_init(dev_priv); | |
3277 | ||
3278 | drm_modeset_unlock_all(dev); | |
3279 | } | |
3280 | ||
7d5e3799 CW |
3281 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3282 | { | |
3283 | struct drm_device *dev = crtc->dev; | |
3284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3285 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3286 | bool pending; |
3287 | ||
3288 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3289 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3290 | return false; | |
3291 | ||
5e2d7afc | 3292 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3293 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3294 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3295 | |
3296 | return pending; | |
3297 | } | |
3298 | ||
bfd16b2a ML |
3299 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3300 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3301 | { |
3302 | struct drm_device *dev = crtc->base.dev; | |
3303 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3304 | struct intel_crtc_state *pipe_config = |
3305 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3306 | |
bfd16b2a ML |
3307 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3308 | crtc->base.mode = crtc->base.state->mode; | |
3309 | ||
3310 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3311 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3312 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3313 | |
44522d85 ML |
3314 | if (HAS_DDI(dev)) |
3315 | intel_set_pipe_csc(&crtc->base); | |
3316 | ||
e30e8f75 GP |
3317 | /* |
3318 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3319 | * that in compute_mode_changes we check the native mode (not the pfit | |
3320 | * mode) to see if we can flip rather than do a full mode set. In the | |
3321 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3322 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3323 | * sized surface. | |
e30e8f75 GP |
3324 | */ |
3325 | ||
e30e8f75 | 3326 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3327 | ((pipe_config->pipe_src_w - 1) << 16) | |
3328 | (pipe_config->pipe_src_h - 1)); | |
3329 | ||
3330 | /* on skylake this is done by detaching scalers */ | |
3331 | if (INTEL_INFO(dev)->gen >= 9) { | |
3332 | skl_detach_scalers(crtc); | |
3333 | ||
3334 | if (pipe_config->pch_pfit.enabled) | |
3335 | skylake_pfit_enable(crtc); | |
3336 | } else if (HAS_PCH_SPLIT(dev)) { | |
3337 | if (pipe_config->pch_pfit.enabled) | |
3338 | ironlake_pfit_enable(crtc); | |
3339 | else if (old_crtc_state->pch_pfit.enabled) | |
3340 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3341 | } |
e30e8f75 GP |
3342 | } |
3343 | ||
5e84e1a4 ZW |
3344 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3345 | { | |
3346 | struct drm_device *dev = crtc->dev; | |
3347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3348 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3349 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3350 | i915_reg_t reg; |
3351 | u32 temp; | |
5e84e1a4 ZW |
3352 | |
3353 | /* enable normal train */ | |
3354 | reg = FDI_TX_CTL(pipe); | |
3355 | temp = I915_READ(reg); | |
61e499bf | 3356 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3357 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3358 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3359 | } else { |
3360 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3361 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3362 | } |
5e84e1a4 ZW |
3363 | I915_WRITE(reg, temp); |
3364 | ||
3365 | reg = FDI_RX_CTL(pipe); | |
3366 | temp = I915_READ(reg); | |
3367 | if (HAS_PCH_CPT(dev)) { | |
3368 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3369 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3370 | } else { | |
3371 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3372 | temp |= FDI_LINK_TRAIN_NONE; | |
3373 | } | |
3374 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3375 | ||
3376 | /* wait one idle pattern time */ | |
3377 | POSTING_READ(reg); | |
3378 | udelay(1000); | |
357555c0 JB |
3379 | |
3380 | /* IVB wants error correction enabled */ | |
3381 | if (IS_IVYBRIDGE(dev)) | |
3382 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3383 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3384 | } |
3385 | ||
8db9d77b ZW |
3386 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3387 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3388 | { | |
3389 | struct drm_device *dev = crtc->dev; | |
3390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3391 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3392 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3393 | i915_reg_t reg; |
3394 | u32 temp, tries; | |
8db9d77b | 3395 | |
1c8562f6 | 3396 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3397 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3398 | |
e1a44743 AJ |
3399 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3400 | for train result */ | |
5eddb70b CW |
3401 | reg = FDI_RX_IMR(pipe); |
3402 | temp = I915_READ(reg); | |
e1a44743 AJ |
3403 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3404 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3405 | I915_WRITE(reg, temp); |
3406 | I915_READ(reg); | |
e1a44743 AJ |
3407 | udelay(150); |
3408 | ||
8db9d77b | 3409 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3410 | reg = FDI_TX_CTL(pipe); |
3411 | temp = I915_READ(reg); | |
627eb5a3 | 3412 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3413 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3414 | temp &= ~FDI_LINK_TRAIN_NONE; |
3415 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3416 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3417 | |
5eddb70b CW |
3418 | reg = FDI_RX_CTL(pipe); |
3419 | temp = I915_READ(reg); | |
8db9d77b ZW |
3420 | temp &= ~FDI_LINK_TRAIN_NONE; |
3421 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3422 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3423 | ||
3424 | POSTING_READ(reg); | |
8db9d77b ZW |
3425 | udelay(150); |
3426 | ||
5b2adf89 | 3427 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3428 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3429 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3430 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3431 | |
5eddb70b | 3432 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3433 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3434 | temp = I915_READ(reg); |
8db9d77b ZW |
3435 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3436 | ||
3437 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3438 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3439 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3440 | break; |
3441 | } | |
8db9d77b | 3442 | } |
e1a44743 | 3443 | if (tries == 5) |
5eddb70b | 3444 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3445 | |
3446 | /* Train 2 */ | |
5eddb70b CW |
3447 | reg = FDI_TX_CTL(pipe); |
3448 | temp = I915_READ(reg); | |
8db9d77b ZW |
3449 | temp &= ~FDI_LINK_TRAIN_NONE; |
3450 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3451 | I915_WRITE(reg, temp); |
8db9d77b | 3452 | |
5eddb70b CW |
3453 | reg = FDI_RX_CTL(pipe); |
3454 | temp = I915_READ(reg); | |
8db9d77b ZW |
3455 | temp &= ~FDI_LINK_TRAIN_NONE; |
3456 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3457 | I915_WRITE(reg, temp); |
8db9d77b | 3458 | |
5eddb70b CW |
3459 | POSTING_READ(reg); |
3460 | udelay(150); | |
8db9d77b | 3461 | |
5eddb70b | 3462 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3463 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3464 | temp = I915_READ(reg); |
8db9d77b ZW |
3465 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3466 | ||
3467 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3468 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3469 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3470 | break; | |
3471 | } | |
8db9d77b | 3472 | } |
e1a44743 | 3473 | if (tries == 5) |
5eddb70b | 3474 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3475 | |
3476 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3477 | |
8db9d77b ZW |
3478 | } |
3479 | ||
0206e353 | 3480 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3481 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3482 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3483 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3484 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3485 | }; | |
3486 | ||
3487 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3488 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3489 | { | |
3490 | struct drm_device *dev = crtc->dev; | |
3491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3492 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3493 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3494 | i915_reg_t reg; |
3495 | u32 temp, i, retry; | |
8db9d77b | 3496 | |
e1a44743 AJ |
3497 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3498 | for train result */ | |
5eddb70b CW |
3499 | reg = FDI_RX_IMR(pipe); |
3500 | temp = I915_READ(reg); | |
e1a44743 AJ |
3501 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3502 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3503 | I915_WRITE(reg, temp); |
3504 | ||
3505 | POSTING_READ(reg); | |
e1a44743 AJ |
3506 | udelay(150); |
3507 | ||
8db9d77b | 3508 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3509 | reg = FDI_TX_CTL(pipe); |
3510 | temp = I915_READ(reg); | |
627eb5a3 | 3511 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3512 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3513 | temp &= ~FDI_LINK_TRAIN_NONE; |
3514 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3515 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3516 | /* SNB-B */ | |
3517 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3518 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3519 | |
d74cf324 DV |
3520 | I915_WRITE(FDI_RX_MISC(pipe), |
3521 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3522 | ||
5eddb70b CW |
3523 | reg = FDI_RX_CTL(pipe); |
3524 | temp = I915_READ(reg); | |
8db9d77b ZW |
3525 | if (HAS_PCH_CPT(dev)) { |
3526 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3527 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3528 | } else { | |
3529 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3530 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3531 | } | |
5eddb70b CW |
3532 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3533 | ||
3534 | POSTING_READ(reg); | |
8db9d77b ZW |
3535 | udelay(150); |
3536 | ||
0206e353 | 3537 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3538 | reg = FDI_TX_CTL(pipe); |
3539 | temp = I915_READ(reg); | |
8db9d77b ZW |
3540 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3541 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3542 | I915_WRITE(reg, temp); |
3543 | ||
3544 | POSTING_READ(reg); | |
8db9d77b ZW |
3545 | udelay(500); |
3546 | ||
fa37d39e SP |
3547 | for (retry = 0; retry < 5; retry++) { |
3548 | reg = FDI_RX_IIR(pipe); | |
3549 | temp = I915_READ(reg); | |
3550 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3551 | if (temp & FDI_RX_BIT_LOCK) { | |
3552 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3553 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3554 | break; | |
3555 | } | |
3556 | udelay(50); | |
8db9d77b | 3557 | } |
fa37d39e SP |
3558 | if (retry < 5) |
3559 | break; | |
8db9d77b ZW |
3560 | } |
3561 | if (i == 4) | |
5eddb70b | 3562 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3563 | |
3564 | /* Train 2 */ | |
5eddb70b CW |
3565 | reg = FDI_TX_CTL(pipe); |
3566 | temp = I915_READ(reg); | |
8db9d77b ZW |
3567 | temp &= ~FDI_LINK_TRAIN_NONE; |
3568 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3569 | if (IS_GEN6(dev)) { | |
3570 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3571 | /* SNB-B */ | |
3572 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3573 | } | |
5eddb70b | 3574 | I915_WRITE(reg, temp); |
8db9d77b | 3575 | |
5eddb70b CW |
3576 | reg = FDI_RX_CTL(pipe); |
3577 | temp = I915_READ(reg); | |
8db9d77b ZW |
3578 | if (HAS_PCH_CPT(dev)) { |
3579 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3580 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3581 | } else { | |
3582 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3583 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3584 | } | |
5eddb70b CW |
3585 | I915_WRITE(reg, temp); |
3586 | ||
3587 | POSTING_READ(reg); | |
8db9d77b ZW |
3588 | udelay(150); |
3589 | ||
0206e353 | 3590 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3591 | reg = FDI_TX_CTL(pipe); |
3592 | temp = I915_READ(reg); | |
8db9d77b ZW |
3593 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3594 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3595 | I915_WRITE(reg, temp); |
3596 | ||
3597 | POSTING_READ(reg); | |
8db9d77b ZW |
3598 | udelay(500); |
3599 | ||
fa37d39e SP |
3600 | for (retry = 0; retry < 5; retry++) { |
3601 | reg = FDI_RX_IIR(pipe); | |
3602 | temp = I915_READ(reg); | |
3603 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3604 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3605 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3606 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3607 | break; | |
3608 | } | |
3609 | udelay(50); | |
8db9d77b | 3610 | } |
fa37d39e SP |
3611 | if (retry < 5) |
3612 | break; | |
8db9d77b ZW |
3613 | } |
3614 | if (i == 4) | |
5eddb70b | 3615 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3616 | |
3617 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3618 | } | |
3619 | ||
357555c0 JB |
3620 | /* Manual link training for Ivy Bridge A0 parts */ |
3621 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3622 | { | |
3623 | struct drm_device *dev = crtc->dev; | |
3624 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3625 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3626 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3627 | i915_reg_t reg; |
3628 | u32 temp, i, j; | |
357555c0 JB |
3629 | |
3630 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3631 | for train result */ | |
3632 | reg = FDI_RX_IMR(pipe); | |
3633 | temp = I915_READ(reg); | |
3634 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3635 | temp &= ~FDI_RX_BIT_LOCK; | |
3636 | I915_WRITE(reg, temp); | |
3637 | ||
3638 | POSTING_READ(reg); | |
3639 | udelay(150); | |
3640 | ||
01a415fd DV |
3641 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3642 | I915_READ(FDI_RX_IIR(pipe))); | |
3643 | ||
139ccd3f JB |
3644 | /* Try each vswing and preemphasis setting twice before moving on */ |
3645 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3646 | /* disable first in case we need to retry */ | |
3647 | reg = FDI_TX_CTL(pipe); | |
3648 | temp = I915_READ(reg); | |
3649 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3650 | temp &= ~FDI_TX_ENABLE; | |
3651 | I915_WRITE(reg, temp); | |
357555c0 | 3652 | |
139ccd3f JB |
3653 | reg = FDI_RX_CTL(pipe); |
3654 | temp = I915_READ(reg); | |
3655 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3656 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3657 | temp &= ~FDI_RX_ENABLE; | |
3658 | I915_WRITE(reg, temp); | |
357555c0 | 3659 | |
139ccd3f | 3660 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3661 | reg = FDI_TX_CTL(pipe); |
3662 | temp = I915_READ(reg); | |
139ccd3f | 3663 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3664 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3665 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3666 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3667 | temp |= snb_b_fdi_train_param[j/2]; |
3668 | temp |= FDI_COMPOSITE_SYNC; | |
3669 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3670 | |
139ccd3f JB |
3671 | I915_WRITE(FDI_RX_MISC(pipe), |
3672 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3673 | |
139ccd3f | 3674 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3675 | temp = I915_READ(reg); |
139ccd3f JB |
3676 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3677 | temp |= FDI_COMPOSITE_SYNC; | |
3678 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3679 | |
139ccd3f JB |
3680 | POSTING_READ(reg); |
3681 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3682 | |
139ccd3f JB |
3683 | for (i = 0; i < 4; i++) { |
3684 | reg = FDI_RX_IIR(pipe); | |
3685 | temp = I915_READ(reg); | |
3686 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3687 | |
139ccd3f JB |
3688 | if (temp & FDI_RX_BIT_LOCK || |
3689 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3690 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3691 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3692 | i); | |
3693 | break; | |
3694 | } | |
3695 | udelay(1); /* should be 0.5us */ | |
3696 | } | |
3697 | if (i == 4) { | |
3698 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3699 | continue; | |
3700 | } | |
357555c0 | 3701 | |
139ccd3f | 3702 | /* Train 2 */ |
357555c0 JB |
3703 | reg = FDI_TX_CTL(pipe); |
3704 | temp = I915_READ(reg); | |
139ccd3f JB |
3705 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3706 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3707 | I915_WRITE(reg, temp); | |
3708 | ||
3709 | reg = FDI_RX_CTL(pipe); | |
3710 | temp = I915_READ(reg); | |
3711 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3712 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3713 | I915_WRITE(reg, temp); |
3714 | ||
3715 | POSTING_READ(reg); | |
139ccd3f | 3716 | udelay(2); /* should be 1.5us */ |
357555c0 | 3717 | |
139ccd3f JB |
3718 | for (i = 0; i < 4; i++) { |
3719 | reg = FDI_RX_IIR(pipe); | |
3720 | temp = I915_READ(reg); | |
3721 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3722 | |
139ccd3f JB |
3723 | if (temp & FDI_RX_SYMBOL_LOCK || |
3724 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3725 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3726 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3727 | i); | |
3728 | goto train_done; | |
3729 | } | |
3730 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3731 | } |
139ccd3f JB |
3732 | if (i == 4) |
3733 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3734 | } |
357555c0 | 3735 | |
139ccd3f | 3736 | train_done: |
357555c0 JB |
3737 | DRM_DEBUG_KMS("FDI train done.\n"); |
3738 | } | |
3739 | ||
88cefb6c | 3740 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3741 | { |
88cefb6c | 3742 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3743 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3744 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3745 | i915_reg_t reg; |
3746 | u32 temp; | |
c64e311e | 3747 | |
c98e9dcf | 3748 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3749 | reg = FDI_RX_CTL(pipe); |
3750 | temp = I915_READ(reg); | |
627eb5a3 | 3751 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3752 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3753 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3754 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3755 | ||
3756 | POSTING_READ(reg); | |
c98e9dcf JB |
3757 | udelay(200); |
3758 | ||
3759 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3760 | temp = I915_READ(reg); |
3761 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3762 | ||
3763 | POSTING_READ(reg); | |
c98e9dcf JB |
3764 | udelay(200); |
3765 | ||
20749730 PZ |
3766 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3767 | reg = FDI_TX_CTL(pipe); | |
3768 | temp = I915_READ(reg); | |
3769 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3770 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3771 | |
20749730 PZ |
3772 | POSTING_READ(reg); |
3773 | udelay(100); | |
6be4a607 | 3774 | } |
0e23b99d JB |
3775 | } |
3776 | ||
88cefb6c DV |
3777 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3778 | { | |
3779 | struct drm_device *dev = intel_crtc->base.dev; | |
3780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3781 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3782 | i915_reg_t reg; |
3783 | u32 temp; | |
88cefb6c DV |
3784 | |
3785 | /* Switch from PCDclk to Rawclk */ | |
3786 | reg = FDI_RX_CTL(pipe); | |
3787 | temp = I915_READ(reg); | |
3788 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3789 | ||
3790 | /* Disable CPU FDI TX PLL */ | |
3791 | reg = FDI_TX_CTL(pipe); | |
3792 | temp = I915_READ(reg); | |
3793 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3794 | ||
3795 | POSTING_READ(reg); | |
3796 | udelay(100); | |
3797 | ||
3798 | reg = FDI_RX_CTL(pipe); | |
3799 | temp = I915_READ(reg); | |
3800 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3801 | ||
3802 | /* Wait for the clocks to turn off. */ | |
3803 | POSTING_READ(reg); | |
3804 | udelay(100); | |
3805 | } | |
3806 | ||
0fc932b8 JB |
3807 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3808 | { | |
3809 | struct drm_device *dev = crtc->dev; | |
3810 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3811 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3812 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3813 | i915_reg_t reg; |
3814 | u32 temp; | |
0fc932b8 JB |
3815 | |
3816 | /* disable CPU FDI tx and PCH FDI rx */ | |
3817 | reg = FDI_TX_CTL(pipe); | |
3818 | temp = I915_READ(reg); | |
3819 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3820 | POSTING_READ(reg); | |
3821 | ||
3822 | reg = FDI_RX_CTL(pipe); | |
3823 | temp = I915_READ(reg); | |
3824 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3825 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3826 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3827 | ||
3828 | POSTING_READ(reg); | |
3829 | udelay(100); | |
3830 | ||
3831 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3832 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3833 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3834 | |
3835 | /* still set train pattern 1 */ | |
3836 | reg = FDI_TX_CTL(pipe); | |
3837 | temp = I915_READ(reg); | |
3838 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3839 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3840 | I915_WRITE(reg, temp); | |
3841 | ||
3842 | reg = FDI_RX_CTL(pipe); | |
3843 | temp = I915_READ(reg); | |
3844 | if (HAS_PCH_CPT(dev)) { | |
3845 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3846 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3847 | } else { | |
3848 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3849 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3850 | } | |
3851 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3852 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3853 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3854 | I915_WRITE(reg, temp); |
3855 | ||
3856 | POSTING_READ(reg); | |
3857 | udelay(100); | |
3858 | } | |
3859 | ||
5dce5b93 CW |
3860 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3861 | { | |
3862 | struct intel_crtc *crtc; | |
3863 | ||
3864 | /* Note that we don't need to be called with mode_config.lock here | |
3865 | * as our list of CRTC objects is static for the lifetime of the | |
3866 | * device and so cannot disappear as we iterate. Similarly, we can | |
3867 | * happily treat the predicates as racy, atomic checks as userspace | |
3868 | * cannot claim and pin a new fb without at least acquring the | |
3869 | * struct_mutex and so serialising with us. | |
3870 | */ | |
d3fcc808 | 3871 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3872 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3873 | continue; | |
3874 | ||
3875 | if (crtc->unpin_work) | |
3876 | intel_wait_for_vblank(dev, crtc->pipe); | |
3877 | ||
3878 | return true; | |
3879 | } | |
3880 | ||
3881 | return false; | |
3882 | } | |
3883 | ||
d6bbafa1 CW |
3884 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3885 | { | |
3886 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3887 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3888 | ||
3889 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3890 | smp_rmb(); | |
3891 | intel_crtc->unpin_work = NULL; | |
3892 | ||
3893 | if (work->event) | |
3894 | drm_send_vblank_event(intel_crtc->base.dev, | |
3895 | intel_crtc->pipe, | |
3896 | work->event); | |
3897 | ||
3898 | drm_crtc_vblank_put(&intel_crtc->base); | |
3899 | ||
3900 | wake_up_all(&dev_priv->pending_flip_queue); | |
3901 | queue_work(dev_priv->wq, &work->work); | |
3902 | ||
3903 | trace_i915_flip_complete(intel_crtc->plane, | |
3904 | work->pending_flip_obj); | |
3905 | } | |
3906 | ||
5008e874 | 3907 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3908 | { |
0f91128d | 3909 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3910 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3911 | long ret; |
e6c3a2a6 | 3912 | |
2c10d571 | 3913 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3914 | |
3915 | ret = wait_event_interruptible_timeout( | |
3916 | dev_priv->pending_flip_queue, | |
3917 | !intel_crtc_has_pending_flip(crtc), | |
3918 | 60*HZ); | |
3919 | ||
3920 | if (ret < 0) | |
3921 | return ret; | |
3922 | ||
3923 | if (ret == 0) { | |
9c787942 | 3924 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3925 | |
5e2d7afc | 3926 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3927 | if (intel_crtc->unpin_work) { |
3928 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3929 | page_flip_completed(intel_crtc); | |
3930 | } | |
5e2d7afc | 3931 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3932 | } |
5bb61643 | 3933 | |
5008e874 | 3934 | return 0; |
e6c3a2a6 CW |
3935 | } |
3936 | ||
060f02d8 VS |
3937 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3938 | { | |
3939 | u32 temp; | |
3940 | ||
3941 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3942 | ||
3943 | mutex_lock(&dev_priv->sb_lock); | |
3944 | ||
3945 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3946 | temp |= SBI_SSCCTL_DISABLE; | |
3947 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3948 | ||
3949 | mutex_unlock(&dev_priv->sb_lock); | |
3950 | } | |
3951 | ||
e615efe4 ED |
3952 | /* Program iCLKIP clock to the desired frequency */ |
3953 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3954 | { | |
3955 | struct drm_device *dev = crtc->dev; | |
3956 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3957 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3958 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3959 | u32 temp; | |
3960 | ||
060f02d8 | 3961 | lpt_disable_iclkip(dev_priv); |
e615efe4 ED |
3962 | |
3963 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3964 | if (clock == 20000) { |
e615efe4 ED |
3965 | auxdiv = 1; |
3966 | divsel = 0x41; | |
3967 | phaseinc = 0x20; | |
3968 | } else { | |
3969 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3970 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3971 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3972 | * convert the virtual clock precision to KHz here for higher |
3973 | * precision. | |
3974 | */ | |
3975 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3976 | u32 iclk_pi_range = 64; | |
3977 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3978 | ||
a2572f5c | 3979 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
e615efe4 ED |
3980 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3981 | pi_value = desired_divisor % iclk_pi_range; | |
3982 | ||
3983 | auxdiv = 0; | |
3984 | divsel = msb_divisor_value - 2; | |
3985 | phaseinc = pi_value; | |
3986 | } | |
3987 | ||
3988 | /* This should not happen with any sane values */ | |
3989 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3990 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3991 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3992 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3993 | ||
3994 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3995 | clock, |
e615efe4 ED |
3996 | auxdiv, |
3997 | divsel, | |
3998 | phasedir, | |
3999 | phaseinc); | |
4000 | ||
060f02d8 VS |
4001 | mutex_lock(&dev_priv->sb_lock); |
4002 | ||
e615efe4 | 4003 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4004 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4005 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4006 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4007 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4008 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4009 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4010 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4011 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4012 | |
4013 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4014 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4015 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4016 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4017 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4018 | |
4019 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4020 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4021 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4022 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4023 | |
060f02d8 VS |
4024 | mutex_unlock(&dev_priv->sb_lock); |
4025 | ||
e615efe4 ED |
4026 | /* Wait for initialization time */ |
4027 | udelay(24); | |
4028 | ||
4029 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4030 | } | |
4031 | ||
275f01b2 DV |
4032 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4033 | enum pipe pch_transcoder) | |
4034 | { | |
4035 | struct drm_device *dev = crtc->base.dev; | |
4036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4037 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4038 | |
4039 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4040 | I915_READ(HTOTAL(cpu_transcoder))); | |
4041 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4042 | I915_READ(HBLANK(cpu_transcoder))); | |
4043 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4044 | I915_READ(HSYNC(cpu_transcoder))); | |
4045 | ||
4046 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4047 | I915_READ(VTOTAL(cpu_transcoder))); | |
4048 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4049 | I915_READ(VBLANK(cpu_transcoder))); | |
4050 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4051 | I915_READ(VSYNC(cpu_transcoder))); | |
4052 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4053 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4054 | } | |
4055 | ||
003632d9 | 4056 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4057 | { |
4058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4059 | uint32_t temp; | |
4060 | ||
4061 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4062 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4063 | return; |
4064 | ||
4065 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4066 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4067 | ||
003632d9 ACO |
4068 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4069 | if (enable) | |
4070 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4071 | ||
4072 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4073 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4074 | POSTING_READ(SOUTH_CHICKEN1); | |
4075 | } | |
4076 | ||
4077 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4078 | { | |
4079 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4080 | |
4081 | switch (intel_crtc->pipe) { | |
4082 | case PIPE_A: | |
4083 | break; | |
4084 | case PIPE_B: | |
6e3c9717 | 4085 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4086 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4087 | else |
003632d9 | 4088 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4089 | |
4090 | break; | |
4091 | case PIPE_C: | |
003632d9 | 4092 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4093 | |
4094 | break; | |
4095 | default: | |
4096 | BUG(); | |
4097 | } | |
4098 | } | |
4099 | ||
c48b5305 VS |
4100 | /* Return which DP Port should be selected for Transcoder DP control */ |
4101 | static enum port | |
4102 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4103 | { | |
4104 | struct drm_device *dev = crtc->dev; | |
4105 | struct intel_encoder *encoder; | |
4106 | ||
4107 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4108 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4109 | encoder->type == INTEL_OUTPUT_EDP) | |
4110 | return enc_to_dig_port(&encoder->base)->port; | |
4111 | } | |
4112 | ||
4113 | return -1; | |
4114 | } | |
4115 | ||
f67a559d JB |
4116 | /* |
4117 | * Enable PCH resources required for PCH ports: | |
4118 | * - PCH PLLs | |
4119 | * - FDI training & RX/TX | |
4120 | * - update transcoder timings | |
4121 | * - DP transcoding bits | |
4122 | * - transcoder | |
4123 | */ | |
4124 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4125 | { |
4126 | struct drm_device *dev = crtc->dev; | |
4127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4128 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4129 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4130 | u32 temp; |
2c07245f | 4131 | |
ab9412ba | 4132 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4133 | |
1fbc0d78 DV |
4134 | if (IS_IVYBRIDGE(dev)) |
4135 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4136 | ||
cd986abb DV |
4137 | /* Write the TU size bits before fdi link training, so that error |
4138 | * detection works. */ | |
4139 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4140 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4141 | ||
3860b2ec VS |
4142 | /* |
4143 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4144 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4145 | */ | |
4146 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4147 | ||
c98e9dcf | 4148 | /* For PCH output, training FDI link */ |
674cf967 | 4149 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4150 | |
3ad8a208 DV |
4151 | /* We need to program the right clock selection before writing the pixel |
4152 | * mutliplier into the DPLL. */ | |
303b81e0 | 4153 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4154 | u32 sel; |
4b645f14 | 4155 | |
c98e9dcf | 4156 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4157 | temp |= TRANS_DPLL_ENABLE(pipe); |
4158 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4159 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4160 | temp |= sel; |
4161 | else | |
4162 | temp &= ~sel; | |
c98e9dcf | 4163 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4164 | } |
5eddb70b | 4165 | |
3ad8a208 DV |
4166 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4167 | * transcoder, and we actually should do this to not upset any PCH | |
4168 | * transcoder that already use the clock when we share it. | |
4169 | * | |
4170 | * Note that enable_shared_dpll tries to do the right thing, but | |
4171 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4172 | * the right LVDS enable sequence. */ | |
85b3894f | 4173 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4174 | |
d9b6cb56 JB |
4175 | /* set transcoder timing, panel must allow it */ |
4176 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4177 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4178 | |
303b81e0 | 4179 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4180 | |
3860b2ec VS |
4181 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4182 | ||
c98e9dcf | 4183 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4184 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4185 | const struct drm_display_mode *adjusted_mode = |
4186 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4187 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4188 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4189 | temp = I915_READ(reg); |
4190 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4191 | TRANS_DP_SYNC_MASK | |
4192 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4193 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4194 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4195 | |
9c4edaee | 4196 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4197 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4198 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4199 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4200 | |
4201 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4202 | case PORT_B: |
5eddb70b | 4203 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4204 | break; |
c48b5305 | 4205 | case PORT_C: |
5eddb70b | 4206 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4207 | break; |
c48b5305 | 4208 | case PORT_D: |
5eddb70b | 4209 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4210 | break; |
4211 | default: | |
e95d41e1 | 4212 | BUG(); |
32f9d658 | 4213 | } |
2c07245f | 4214 | |
5eddb70b | 4215 | I915_WRITE(reg, temp); |
6be4a607 | 4216 | } |
b52eb4dc | 4217 | |
b8a4f404 | 4218 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4219 | } |
4220 | ||
1507e5bd PZ |
4221 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4222 | { | |
4223 | struct drm_device *dev = crtc->dev; | |
4224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4225 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4226 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4227 | |
ab9412ba | 4228 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4229 | |
8c52b5e8 | 4230 | lpt_program_iclkip(crtc); |
1507e5bd | 4231 | |
0540e488 | 4232 | /* Set transcoder timing. */ |
275f01b2 | 4233 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4234 | |
937bb610 | 4235 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4236 | } |
4237 | ||
190f68c5 ACO |
4238 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4239 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4240 | { |
e2b78267 | 4241 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4242 | struct intel_shared_dpll *pll; |
de419ab6 | 4243 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4244 | enum intel_dpll_id i; |
00490c22 | 4245 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4246 | |
de419ab6 ML |
4247 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4248 | ||
98b6bd99 DV |
4249 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4250 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4251 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4252 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4253 | |
46edb027 DV |
4254 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4255 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4256 | |
de419ab6 | 4257 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4258 | |
98b6bd99 DV |
4259 | goto found; |
4260 | } | |
4261 | ||
bcddf610 S |
4262 | if (IS_BROXTON(dev_priv->dev)) { |
4263 | /* PLL is attached to port in bxt */ | |
4264 | struct intel_encoder *encoder; | |
4265 | struct intel_digital_port *intel_dig_port; | |
4266 | ||
4267 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4268 | if (WARN_ON(!encoder)) | |
4269 | return NULL; | |
4270 | ||
4271 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4272 | /* 1:1 mapping between ports and PLLs */ | |
4273 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4274 | pll = &dev_priv->shared_dplls[i]; | |
4275 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4276 | crtc->base.base.id, pll->name); | |
de419ab6 | 4277 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4278 | |
4279 | goto found; | |
00490c22 ML |
4280 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4281 | /* Do not consider SPLL */ | |
4282 | max = 2; | |
bcddf610 | 4283 | |
00490c22 | 4284 | for (i = 0; i < max; i++) { |
e72f9fbf | 4285 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4286 | |
4287 | /* Only want to check enabled timings first */ | |
de419ab6 | 4288 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4289 | continue; |
4290 | ||
190f68c5 | 4291 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4292 | &shared_dpll[i].hw_state, |
4293 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4294 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4295 | crtc->base.base.id, pll->name, |
de419ab6 | 4296 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4297 | pll->active); |
ee7b9f93 JB |
4298 | goto found; |
4299 | } | |
4300 | } | |
4301 | ||
4302 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4303 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4304 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4305 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4306 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4307 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4308 | goto found; |
4309 | } | |
4310 | } | |
4311 | ||
4312 | return NULL; | |
4313 | ||
4314 | found: | |
de419ab6 ML |
4315 | if (shared_dpll[i].crtc_mask == 0) |
4316 | shared_dpll[i].hw_state = | |
4317 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4318 | |
190f68c5 | 4319 | crtc_state->shared_dpll = i; |
46edb027 DV |
4320 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4321 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4322 | |
de419ab6 | 4323 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4324 | |
ee7b9f93 JB |
4325 | return pll; |
4326 | } | |
4327 | ||
de419ab6 | 4328 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4329 | { |
de419ab6 ML |
4330 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4331 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4332 | struct intel_shared_dpll *pll; |
4333 | enum intel_dpll_id i; | |
4334 | ||
de419ab6 ML |
4335 | if (!to_intel_atomic_state(state)->dpll_set) |
4336 | return; | |
8bd31e67 | 4337 | |
de419ab6 | 4338 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4339 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4340 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4341 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4342 | } |
4343 | } | |
4344 | ||
a1520318 | 4345 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4346 | { |
4347 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4348 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4349 | u32 temp; |
4350 | ||
4351 | temp = I915_READ(dslreg); | |
4352 | udelay(500); | |
4353 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4354 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4355 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4356 | } |
4357 | } | |
4358 | ||
86adf9d7 ML |
4359 | static int |
4360 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4361 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4362 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4363 | { |
86adf9d7 ML |
4364 | struct intel_crtc_scaler_state *scaler_state = |
4365 | &crtc_state->scaler_state; | |
4366 | struct intel_crtc *intel_crtc = | |
4367 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4368 | int need_scaling; |
6156a456 CK |
4369 | |
4370 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4371 | (src_h != dst_w || src_w != dst_h): | |
4372 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4373 | |
4374 | /* | |
4375 | * if plane is being disabled or scaler is no more required or force detach | |
4376 | * - free scaler binded to this plane/crtc | |
4377 | * - in order to do this, update crtc->scaler_usage | |
4378 | * | |
4379 | * Here scaler state in crtc_state is set free so that | |
4380 | * scaler can be assigned to other user. Actual register | |
4381 | * update to free the scaler is done in plane/panel-fit programming. | |
4382 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4383 | */ | |
86adf9d7 | 4384 | if (force_detach || !need_scaling) { |
a1b2278e | 4385 | if (*scaler_id >= 0) { |
86adf9d7 | 4386 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4387 | scaler_state->scalers[*scaler_id].in_use = 0; |
4388 | ||
86adf9d7 ML |
4389 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4390 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4391 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4392 | scaler_state->scaler_users); |
4393 | *scaler_id = -1; | |
4394 | } | |
4395 | return 0; | |
4396 | } | |
4397 | ||
4398 | /* range checks */ | |
4399 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4400 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4401 | ||
4402 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4403 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4404 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4405 | "size is out of scaler range\n", |
86adf9d7 | 4406 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4407 | return -EINVAL; |
4408 | } | |
4409 | ||
86adf9d7 ML |
4410 | /* mark this plane as a scaler user in crtc_state */ |
4411 | scaler_state->scaler_users |= (1 << scaler_user); | |
4412 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4413 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4414 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4415 | scaler_state->scaler_users); | |
4416 | ||
4417 | return 0; | |
4418 | } | |
4419 | ||
4420 | /** | |
4421 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4422 | * | |
4423 | * @state: crtc's scaler state | |
86adf9d7 ML |
4424 | * |
4425 | * Return | |
4426 | * 0 - scaler_usage updated successfully | |
4427 | * error - requested scaling cannot be supported or other error condition | |
4428 | */ | |
e435d6e5 | 4429 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4430 | { |
4431 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4432 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4433 | |
4434 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4435 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4436 | ||
e435d6e5 | 4437 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4438 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4439 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4440 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4441 | } |
4442 | ||
4443 | /** | |
4444 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4445 | * | |
4446 | * @state: crtc's scaler state | |
86adf9d7 ML |
4447 | * @plane_state: atomic plane state to update |
4448 | * | |
4449 | * Return | |
4450 | * 0 - scaler_usage updated successfully | |
4451 | * error - requested scaling cannot be supported or other error condition | |
4452 | */ | |
da20eabd ML |
4453 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4454 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4455 | { |
4456 | ||
4457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4458 | struct intel_plane *intel_plane = |
4459 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4460 | struct drm_framebuffer *fb = plane_state->base.fb; |
4461 | int ret; | |
4462 | ||
4463 | bool force_detach = !fb || !plane_state->visible; | |
4464 | ||
4465 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4466 | intel_plane->base.base.id, intel_crtc->pipe, | |
4467 | drm_plane_index(&intel_plane->base)); | |
4468 | ||
4469 | ret = skl_update_scaler(crtc_state, force_detach, | |
4470 | drm_plane_index(&intel_plane->base), | |
4471 | &plane_state->scaler_id, | |
4472 | plane_state->base.rotation, | |
4473 | drm_rect_width(&plane_state->src) >> 16, | |
4474 | drm_rect_height(&plane_state->src) >> 16, | |
4475 | drm_rect_width(&plane_state->dst), | |
4476 | drm_rect_height(&plane_state->dst)); | |
4477 | ||
4478 | if (ret || plane_state->scaler_id < 0) | |
4479 | return ret; | |
4480 | ||
a1b2278e | 4481 | /* check colorkey */ |
818ed961 | 4482 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4483 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4484 | intel_plane->base.base.id); |
a1b2278e CK |
4485 | return -EINVAL; |
4486 | } | |
4487 | ||
4488 | /* Check src format */ | |
86adf9d7 ML |
4489 | switch (fb->pixel_format) { |
4490 | case DRM_FORMAT_RGB565: | |
4491 | case DRM_FORMAT_XBGR8888: | |
4492 | case DRM_FORMAT_XRGB8888: | |
4493 | case DRM_FORMAT_ABGR8888: | |
4494 | case DRM_FORMAT_ARGB8888: | |
4495 | case DRM_FORMAT_XRGB2101010: | |
4496 | case DRM_FORMAT_XBGR2101010: | |
4497 | case DRM_FORMAT_YUYV: | |
4498 | case DRM_FORMAT_YVYU: | |
4499 | case DRM_FORMAT_UYVY: | |
4500 | case DRM_FORMAT_VYUY: | |
4501 | break; | |
4502 | default: | |
4503 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4504 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4505 | return -EINVAL; | |
a1b2278e CK |
4506 | } |
4507 | ||
a1b2278e CK |
4508 | return 0; |
4509 | } | |
4510 | ||
e435d6e5 ML |
4511 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4512 | { | |
4513 | int i; | |
4514 | ||
4515 | for (i = 0; i < crtc->num_scalers; i++) | |
4516 | skl_detach_scaler(crtc, i); | |
4517 | } | |
4518 | ||
4519 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4520 | { |
4521 | struct drm_device *dev = crtc->base.dev; | |
4522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4523 | int pipe = crtc->pipe; | |
a1b2278e CK |
4524 | struct intel_crtc_scaler_state *scaler_state = |
4525 | &crtc->config->scaler_state; | |
4526 | ||
4527 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4528 | ||
6e3c9717 | 4529 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4530 | int id; |
4531 | ||
4532 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4533 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4534 | return; | |
4535 | } | |
4536 | ||
4537 | id = scaler_state->scaler_id; | |
4538 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4539 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4540 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4541 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4542 | ||
4543 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4544 | } |
4545 | } | |
4546 | ||
b074cec8 JB |
4547 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4548 | { | |
4549 | struct drm_device *dev = crtc->base.dev; | |
4550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4551 | int pipe = crtc->pipe; | |
4552 | ||
6e3c9717 | 4553 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4554 | /* Force use of hard-coded filter coefficients |
4555 | * as some pre-programmed values are broken, | |
4556 | * e.g. x201. | |
4557 | */ | |
4558 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4559 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4560 | PF_PIPE_SEL_IVB(pipe)); | |
4561 | else | |
4562 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4563 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4564 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4565 | } |
4566 | } | |
4567 | ||
20bc8673 | 4568 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4569 | { |
cea165c3 VS |
4570 | struct drm_device *dev = crtc->base.dev; |
4571 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4572 | |
6e3c9717 | 4573 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4574 | return; |
4575 | ||
cea165c3 VS |
4576 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4577 | intel_wait_for_vblank(dev, crtc->pipe); | |
4578 | ||
d77e4531 | 4579 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4580 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4581 | mutex_lock(&dev_priv->rps.hw_lock); |
4582 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4583 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4584 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4585 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4586 | * mailbox." Moreover, the mailbox may return a bogus state, |
4587 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4588 | */ |
4589 | } else { | |
4590 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4591 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4592 | * is essentially intel_wait_for_vblank. If we don't have this | |
4593 | * and don't wait for vblanks until the end of crtc_enable, then | |
4594 | * the HW state readout code will complain that the expected | |
4595 | * IPS_CTL value is not the one we read. */ | |
4596 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4597 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4598 | } | |
d77e4531 PZ |
4599 | } |
4600 | ||
20bc8673 | 4601 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4602 | { |
4603 | struct drm_device *dev = crtc->base.dev; | |
4604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4605 | ||
6e3c9717 | 4606 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4607 | return; |
4608 | ||
4609 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4610 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4611 | mutex_lock(&dev_priv->rps.hw_lock); |
4612 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4613 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4614 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4615 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4616 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4617 | } else { |
2a114cc1 | 4618 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4619 | POSTING_READ(IPS_CTL); |
4620 | } | |
d77e4531 PZ |
4621 | |
4622 | /* We need to wait for a vblank before we can disable the plane. */ | |
4623 | intel_wait_for_vblank(dev, crtc->pipe); | |
4624 | } | |
4625 | ||
4626 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4627 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4628 | { | |
4629 | struct drm_device *dev = crtc->dev; | |
4630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4631 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4632 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4633 | int i; |
4634 | bool reenable_ips = false; | |
4635 | ||
4636 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4637 | if (!crtc->state->active) |
d77e4531 PZ |
4638 | return; |
4639 | ||
50360403 | 4640 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4641 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4642 | assert_dsi_pll_enabled(dev_priv); |
4643 | else | |
4644 | assert_pll_enabled(dev_priv, pipe); | |
4645 | } | |
4646 | ||
d77e4531 PZ |
4647 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4648 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4649 | */ | |
6e3c9717 | 4650 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4651 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4652 | GAMMA_MODE_MODE_SPLIT)) { | |
4653 | hsw_disable_ips(intel_crtc); | |
4654 | reenable_ips = true; | |
4655 | } | |
4656 | ||
4657 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4658 | i915_reg_t palreg; |
f65a9c5b VS |
4659 | |
4660 | if (HAS_GMCH_DISPLAY(dev)) | |
4661 | palreg = PALETTE(pipe, i); | |
4662 | else | |
4663 | palreg = LGC_PALETTE(pipe, i); | |
4664 | ||
4665 | I915_WRITE(palreg, | |
d77e4531 PZ |
4666 | (intel_crtc->lut_r[i] << 16) | |
4667 | (intel_crtc->lut_g[i] << 8) | | |
4668 | intel_crtc->lut_b[i]); | |
4669 | } | |
4670 | ||
4671 | if (reenable_ips) | |
4672 | hsw_enable_ips(intel_crtc); | |
4673 | } | |
4674 | ||
7cac945f | 4675 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4676 | { |
7cac945f | 4677 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4678 | struct drm_device *dev = intel_crtc->base.dev; |
4679 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4680 | ||
4681 | mutex_lock(&dev->struct_mutex); | |
4682 | dev_priv->mm.interruptible = false; | |
4683 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4684 | dev_priv->mm.interruptible = true; | |
4685 | mutex_unlock(&dev->struct_mutex); | |
4686 | } | |
4687 | ||
4688 | /* Let userspace switch the overlay on again. In most cases userspace | |
4689 | * has to recompute where to put it anyway. | |
4690 | */ | |
4691 | } | |
4692 | ||
87d4300a ML |
4693 | /** |
4694 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4695 | * @crtc: the CRTC whose primary plane was just enabled | |
4696 | * | |
4697 | * Performs potentially sleeping operations that must be done after the primary | |
4698 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4699 | * called due to an explicit primary plane update, or due to an implicit | |
4700 | * re-enable that is caused when a sprite plane is updated to no longer | |
4701 | * completely hide the primary plane. | |
4702 | */ | |
4703 | static void | |
4704 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4705 | { |
4706 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4707 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4708 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4709 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4710 | |
87d4300a ML |
4711 | /* |
4712 | * FIXME IPS should be fine as long as one plane is | |
4713 | * enabled, but in practice it seems to have problems | |
4714 | * when going from primary only to sprite only and vice | |
4715 | * versa. | |
4716 | */ | |
a5c4d7bc VS |
4717 | hsw_enable_ips(intel_crtc); |
4718 | ||
f99d7069 | 4719 | /* |
87d4300a ML |
4720 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4721 | * So don't enable underrun reporting before at least some planes | |
4722 | * are enabled. | |
4723 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4724 | * but leave the pipe running. | |
f99d7069 | 4725 | */ |
87d4300a ML |
4726 | if (IS_GEN2(dev)) |
4727 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4728 | ||
aca7b684 VS |
4729 | /* Underruns don't always raise interrupts, so check manually. */ |
4730 | intel_check_cpu_fifo_underruns(dev_priv); | |
4731 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4732 | } |
4733 | ||
87d4300a ML |
4734 | /** |
4735 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4736 | * @crtc: the CRTC whose primary plane is to be disabled | |
4737 | * | |
4738 | * Performs potentially sleeping operations that must be done before the | |
4739 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4740 | * be called due to an explicit primary plane update, or due to an implicit | |
4741 | * disable that is caused when a sprite plane completely hides the primary | |
4742 | * plane. | |
4743 | */ | |
4744 | static void | |
4745 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4746 | { |
4747 | struct drm_device *dev = crtc->dev; | |
4748 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4749 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4750 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4751 | |
87d4300a ML |
4752 | /* |
4753 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4754 | * So diasble underrun reporting before all the planes get disabled. | |
4755 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4756 | * but leave the pipe running. | |
4757 | */ | |
4758 | if (IS_GEN2(dev)) | |
4759 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4760 | |
87d4300a ML |
4761 | /* |
4762 | * Vblank time updates from the shadow to live plane control register | |
4763 | * are blocked if the memory self-refresh mode is active at that | |
4764 | * moment. So to make sure the plane gets truly disabled, disable | |
4765 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4766 | * will be checked/applied by the HW only at the next frame start | |
4767 | * event which is after the vblank start event, so we need to have a | |
4768 | * wait-for-vblank between disabling the plane and the pipe. | |
4769 | */ | |
262cd2e1 | 4770 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4771 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4772 | dev_priv->wm.vlv.cxsr = false; |
4773 | intel_wait_for_vblank(dev, pipe); | |
4774 | } | |
87d4300a | 4775 | |
87d4300a ML |
4776 | /* |
4777 | * FIXME IPS should be fine as long as one plane is | |
4778 | * enabled, but in practice it seems to have problems | |
4779 | * when going from primary only to sprite only and vice | |
4780 | * versa. | |
4781 | */ | |
a5c4d7bc | 4782 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4783 | } |
4784 | ||
ac21b225 ML |
4785 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4786 | { | |
4787 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4788 | struct intel_crtc_state *pipe_config = |
4789 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4790 | struct drm_device *dev = crtc->base.dev; |
ac21b225 ML |
4791 | |
4792 | if (atomic->wait_vblank) | |
4793 | intel_wait_for_vblank(dev, crtc->pipe); | |
4794 | ||
4795 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4796 | ||
ab1d3a0e | 4797 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4798 | |
b9001114 | 4799 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4800 | intel_update_watermarks(&crtc->base); |
4801 | ||
c80ac854 | 4802 | if (atomic->update_fbc) |
1eb52238 | 4803 | intel_fbc_post_update(crtc); |
ac21b225 ML |
4804 | |
4805 | if (atomic->post_enable_primary) | |
4806 | intel_post_enable_primary(&crtc->base); | |
4807 | ||
ac21b225 ML |
4808 | memset(atomic, 0, sizeof(*atomic)); |
4809 | } | |
4810 | ||
5c74cd73 | 4811 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4812 | { |
5c74cd73 | 4813 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4814 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4815 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4816 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4817 | struct intel_crtc_state *pipe_config = |
4818 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4819 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4820 | struct drm_plane *primary = crtc->base.primary; | |
4821 | struct drm_plane_state *old_pri_state = | |
4822 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4823 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4824 | |
1eb52238 PZ |
4825 | if (atomic->update_fbc) |
4826 | intel_fbc_pre_update(crtc); | |
ac21b225 | 4827 | |
5c74cd73 ML |
4828 | if (old_pri_state) { |
4829 | struct intel_plane_state *primary_state = | |
4830 | to_intel_plane_state(primary->state); | |
4831 | struct intel_plane_state *old_primary_state = | |
4832 | to_intel_plane_state(old_pri_state); | |
4833 | ||
4834 | if (old_primary_state->visible && | |
4835 | (modeset || !primary_state->visible)) | |
4836 | intel_pre_disable_primary(&crtc->base); | |
4837 | } | |
852eb00d | 4838 | |
ab1d3a0e | 4839 | if (pipe_config->disable_cxsr) { |
852eb00d | 4840 | crtc->wm.cxsr_allowed = false; |
2dfd178d ML |
4841 | |
4842 | if (old_crtc_state->base.active) | |
4843 | intel_set_memory_cxsr(dev_priv, false); | |
852eb00d | 4844 | } |
92826fcd | 4845 | |
bf220452 | 4846 | if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed) |
92826fcd | 4847 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4848 | } |
4849 | ||
d032ffa0 | 4850 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4851 | { |
4852 | struct drm_device *dev = crtc->dev; | |
4853 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4854 | struct drm_plane *p; |
87d4300a ML |
4855 | int pipe = intel_crtc->pipe; |
4856 | ||
7cac945f | 4857 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4858 | |
d032ffa0 ML |
4859 | drm_for_each_plane_mask(p, dev, plane_mask) |
4860 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4861 | |
f99d7069 DV |
4862 | /* |
4863 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4864 | * to compute the mask of flip planes precisely. For the time being | |
4865 | * consider this a flip to a NULL plane. | |
4866 | */ | |
4867 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4868 | } |
4869 | ||
f67a559d JB |
4870 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4871 | { | |
4872 | struct drm_device *dev = crtc->dev; | |
4873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4874 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4875 | struct intel_encoder *encoder; |
f67a559d | 4876 | int pipe = intel_crtc->pipe; |
f67a559d | 4877 | |
53d9f4e9 | 4878 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4879 | return; |
4880 | ||
81b088ca VS |
4881 | if (intel_crtc->config->has_pch_encoder) |
4882 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4883 | ||
6e3c9717 | 4884 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4885 | intel_prepare_shared_dpll(intel_crtc); |
4886 | ||
6e3c9717 | 4887 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4888 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4889 | |
4890 | intel_set_pipe_timings(intel_crtc); | |
4891 | ||
6e3c9717 | 4892 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4893 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4894 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4895 | } |
4896 | ||
4897 | ironlake_set_pipeconf(crtc); | |
4898 | ||
f67a559d | 4899 | intel_crtc->active = true; |
8664281b | 4900 | |
a72e4c9f | 4901 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4902 | |
f6736a1a | 4903 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4904 | if (encoder->pre_enable) |
4905 | encoder->pre_enable(encoder); | |
f67a559d | 4906 | |
6e3c9717 | 4907 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4908 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4909 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4910 | * enabling. */ | |
88cefb6c | 4911 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4912 | } else { |
4913 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4914 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4915 | } | |
f67a559d | 4916 | |
b074cec8 | 4917 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4918 | |
9c54c0dd JB |
4919 | /* |
4920 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4921 | * clocks enabled | |
4922 | */ | |
4923 | intel_crtc_load_lut(crtc); | |
4924 | ||
f37fcc2a | 4925 | intel_update_watermarks(crtc); |
e1fdc473 | 4926 | intel_enable_pipe(intel_crtc); |
f67a559d | 4927 | |
6e3c9717 | 4928 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4929 | ironlake_pch_enable(crtc); |
c98e9dcf | 4930 | |
f9b61ff6 DV |
4931 | assert_vblank_disabled(crtc); |
4932 | drm_crtc_vblank_on(crtc); | |
4933 | ||
fa5c73b1 DV |
4934 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4935 | encoder->enable(encoder); | |
61b77ddd DV |
4936 | |
4937 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4938 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4939 | |
4940 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4941 | if (intel_crtc->config->has_pch_encoder) | |
4942 | intel_wait_for_vblank(dev, pipe); | |
4943 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 JB |
4944 | } |
4945 | ||
42db64ef PZ |
4946 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4947 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4948 | { | |
f5adf94e | 4949 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4950 | } |
4951 | ||
4f771f10 PZ |
4952 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4953 | { | |
4954 | struct drm_device *dev = crtc->dev; | |
4955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4956 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4957 | struct intel_encoder *encoder; | |
99d736a2 ML |
4958 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4959 | struct intel_crtc_state *pipe_config = | |
4960 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4961 | |
53d9f4e9 | 4962 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4963 | return; |
4964 | ||
81b088ca VS |
4965 | if (intel_crtc->config->has_pch_encoder) |
4966 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4967 | false); | |
4968 | ||
df8ad70c DV |
4969 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4970 | intel_enable_shared_dpll(intel_crtc); | |
4971 | ||
6e3c9717 | 4972 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4973 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4974 | |
4975 | intel_set_pipe_timings(intel_crtc); | |
4976 | ||
6e3c9717 ACO |
4977 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4978 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4979 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4980 | } |
4981 | ||
6e3c9717 | 4982 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4983 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4984 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4985 | } |
4986 | ||
4987 | haswell_set_pipeconf(crtc); | |
4988 | ||
4989 | intel_set_pipe_csc(crtc); | |
4990 | ||
4f771f10 | 4991 | intel_crtc->active = true; |
8664281b | 4992 | |
6b698516 DV |
4993 | if (intel_crtc->config->has_pch_encoder) |
4994 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4995 | else | |
4996 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4997 | ||
7d4aefd0 | 4998 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4999 | if (encoder->pre_enable) |
5000 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5001 | } |
4f771f10 | 5002 | |
d2d65408 | 5003 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5004 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5005 | |
a65347ba | 5006 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5007 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5008 | |
1c132b44 | 5009 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5010 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5011 | else |
1c132b44 | 5012 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5013 | |
5014 | /* | |
5015 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5016 | * clocks enabled | |
5017 | */ | |
5018 | intel_crtc_load_lut(crtc); | |
5019 | ||
1f544388 | 5020 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5021 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5022 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5023 | |
f37fcc2a | 5024 | intel_update_watermarks(crtc); |
e1fdc473 | 5025 | intel_enable_pipe(intel_crtc); |
42db64ef | 5026 | |
6e3c9717 | 5027 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5028 | lpt_pch_enable(crtc); |
4f771f10 | 5029 | |
a65347ba | 5030 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5031 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5032 | ||
f9b61ff6 DV |
5033 | assert_vblank_disabled(crtc); |
5034 | drm_crtc_vblank_on(crtc); | |
5035 | ||
8807e55b | 5036 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5037 | encoder->enable(encoder); |
8807e55b JN |
5038 | intel_opregion_notify_encoder(encoder, true); |
5039 | } | |
4f771f10 | 5040 | |
6b698516 DV |
5041 | if (intel_crtc->config->has_pch_encoder) { |
5042 | intel_wait_for_vblank(dev, pipe); | |
5043 | intel_wait_for_vblank(dev, pipe); | |
5044 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5045 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5046 | true); | |
6b698516 | 5047 | } |
d2d65408 | 5048 | |
e4916946 PZ |
5049 | /* If we change the relative order between pipe/planes enabling, we need |
5050 | * to change the workaround. */ | |
99d736a2 ML |
5051 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5052 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5053 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5054 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5055 | } | |
4f771f10 PZ |
5056 | } |
5057 | ||
bfd16b2a | 5058 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5059 | { |
5060 | struct drm_device *dev = crtc->base.dev; | |
5061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5062 | int pipe = crtc->pipe; | |
5063 | ||
5064 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5065 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5066 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5067 | I915_WRITE(PF_CTL(pipe), 0); |
5068 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5069 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5070 | } | |
5071 | } | |
5072 | ||
6be4a607 JB |
5073 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5074 | { | |
5075 | struct drm_device *dev = crtc->dev; | |
5076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5078 | struct intel_encoder *encoder; |
6be4a607 | 5079 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5080 | |
37ca8d4c VS |
5081 | if (intel_crtc->config->has_pch_encoder) |
5082 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5083 | ||
ea9d758d DV |
5084 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5085 | encoder->disable(encoder); | |
5086 | ||
f9b61ff6 DV |
5087 | drm_crtc_vblank_off(crtc); |
5088 | assert_vblank_disabled(crtc); | |
5089 | ||
3860b2ec VS |
5090 | /* |
5091 | * Sometimes spurious CPU pipe underruns happen when the | |
5092 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5093 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5094 | */ | |
5095 | if (intel_crtc->config->has_pch_encoder) | |
5096 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5097 | ||
575f7ab7 | 5098 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5099 | |
bfd16b2a | 5100 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5101 | |
3860b2ec | 5102 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5103 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5104 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5105 | } | |
5a74f70a | 5106 | |
bf49ec8c DV |
5107 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5108 | if (encoder->post_disable) | |
5109 | encoder->post_disable(encoder); | |
2c07245f | 5110 | |
6e3c9717 | 5111 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5112 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5113 | |
d925c59a | 5114 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5115 | i915_reg_t reg; |
5116 | u32 temp; | |
5117 | ||
d925c59a DV |
5118 | /* disable TRANS_DP_CTL */ |
5119 | reg = TRANS_DP_CTL(pipe); | |
5120 | temp = I915_READ(reg); | |
5121 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5122 | TRANS_DP_PORT_SEL_MASK); | |
5123 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5124 | I915_WRITE(reg, temp); | |
5125 | ||
5126 | /* disable DPLL_SEL */ | |
5127 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5128 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5129 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5130 | } |
e3421a18 | 5131 | |
d925c59a DV |
5132 | ironlake_fdi_pll_disable(intel_crtc); |
5133 | } | |
81b088ca VS |
5134 | |
5135 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 | 5136 | } |
1b3c7a47 | 5137 | |
4f771f10 | 5138 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5139 | { |
4f771f10 PZ |
5140 | struct drm_device *dev = crtc->dev; |
5141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5142 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5143 | struct intel_encoder *encoder; |
6e3c9717 | 5144 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5145 | |
d2d65408 VS |
5146 | if (intel_crtc->config->has_pch_encoder) |
5147 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5148 | false); | |
5149 | ||
8807e55b JN |
5150 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5151 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5152 | encoder->disable(encoder); |
8807e55b | 5153 | } |
4f771f10 | 5154 | |
f9b61ff6 DV |
5155 | drm_crtc_vblank_off(crtc); |
5156 | assert_vblank_disabled(crtc); | |
5157 | ||
575f7ab7 | 5158 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5159 | |
6e3c9717 | 5160 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5161 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5162 | ||
a65347ba | 5163 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5164 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5165 | |
1c132b44 | 5166 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5167 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5168 | else |
bfd16b2a | 5169 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5170 | |
a65347ba | 5171 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5172 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5173 | |
97b040aa ID |
5174 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5175 | if (encoder->post_disable) | |
5176 | encoder->post_disable(encoder); | |
81b088ca | 5177 | |
92966a37 VS |
5178 | if (intel_crtc->config->has_pch_encoder) { |
5179 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5180 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5181 | intel_ddi_fdi_disable(crtc); |
5182 | ||
81b088ca VS |
5183 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5184 | true); | |
92966a37 | 5185 | } |
4f771f10 PZ |
5186 | } |
5187 | ||
2dd24552 JB |
5188 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5189 | { | |
5190 | struct drm_device *dev = crtc->base.dev; | |
5191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5192 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5193 | |
681a8504 | 5194 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5195 | return; |
5196 | ||
2dd24552 | 5197 | /* |
c0b03411 DV |
5198 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5199 | * according to register description and PRM. | |
2dd24552 | 5200 | */ |
c0b03411 DV |
5201 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5202 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5203 | |
b074cec8 JB |
5204 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5205 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5206 | |
5207 | /* Border color in case we don't scale up to the full screen. Black by | |
5208 | * default, change to something else for debugging. */ | |
5209 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5210 | } |
5211 | ||
d05410f9 DA |
5212 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5213 | { | |
5214 | switch (port) { | |
5215 | case PORT_A: | |
6331a704 | 5216 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5217 | case PORT_B: |
6331a704 | 5218 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5219 | case PORT_C: |
6331a704 | 5220 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5221 | case PORT_D: |
6331a704 | 5222 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5223 | case PORT_E: |
6331a704 | 5224 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5225 | default: |
b9fec167 | 5226 | MISSING_CASE(port); |
d05410f9 DA |
5227 | return POWER_DOMAIN_PORT_OTHER; |
5228 | } | |
5229 | } | |
5230 | ||
25f78f58 VS |
5231 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5232 | { | |
5233 | switch (port) { | |
5234 | case PORT_A: | |
5235 | return POWER_DOMAIN_AUX_A; | |
5236 | case PORT_B: | |
5237 | return POWER_DOMAIN_AUX_B; | |
5238 | case PORT_C: | |
5239 | return POWER_DOMAIN_AUX_C; | |
5240 | case PORT_D: | |
5241 | return POWER_DOMAIN_AUX_D; | |
5242 | case PORT_E: | |
5243 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5244 | return POWER_DOMAIN_AUX_D; | |
5245 | default: | |
b9fec167 | 5246 | MISSING_CASE(port); |
25f78f58 VS |
5247 | return POWER_DOMAIN_AUX_A; |
5248 | } | |
5249 | } | |
5250 | ||
319be8ae ID |
5251 | enum intel_display_power_domain |
5252 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5253 | { | |
5254 | struct drm_device *dev = intel_encoder->base.dev; | |
5255 | struct intel_digital_port *intel_dig_port; | |
5256 | ||
5257 | switch (intel_encoder->type) { | |
5258 | case INTEL_OUTPUT_UNKNOWN: | |
5259 | /* Only DDI platforms should ever use this output type */ | |
5260 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5261 | case INTEL_OUTPUT_DISPLAYPORT: | |
5262 | case INTEL_OUTPUT_HDMI: | |
5263 | case INTEL_OUTPUT_EDP: | |
5264 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5265 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5266 | case INTEL_OUTPUT_DP_MST: |
5267 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5268 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5269 | case INTEL_OUTPUT_ANALOG: |
5270 | return POWER_DOMAIN_PORT_CRT; | |
5271 | case INTEL_OUTPUT_DSI: | |
5272 | return POWER_DOMAIN_PORT_DSI; | |
5273 | default: | |
5274 | return POWER_DOMAIN_PORT_OTHER; | |
5275 | } | |
5276 | } | |
5277 | ||
25f78f58 VS |
5278 | enum intel_display_power_domain |
5279 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5280 | { | |
5281 | struct drm_device *dev = intel_encoder->base.dev; | |
5282 | struct intel_digital_port *intel_dig_port; | |
5283 | ||
5284 | switch (intel_encoder->type) { | |
5285 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5286 | case INTEL_OUTPUT_HDMI: |
5287 | /* | |
5288 | * Only DDI platforms should ever use these output types. | |
5289 | * We can get here after the HDMI detect code has already set | |
5290 | * the type of the shared encoder. Since we can't be sure | |
5291 | * what's the status of the given connectors, play safe and | |
5292 | * run the DP detection too. | |
5293 | */ | |
25f78f58 VS |
5294 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5295 | case INTEL_OUTPUT_DISPLAYPORT: | |
5296 | case INTEL_OUTPUT_EDP: | |
5297 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5298 | return port_to_aux_power_domain(intel_dig_port->port); | |
5299 | case INTEL_OUTPUT_DP_MST: | |
5300 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5301 | return port_to_aux_power_domain(intel_dig_port->port); | |
5302 | default: | |
b9fec167 | 5303 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5304 | return POWER_DOMAIN_AUX_A; |
5305 | } | |
5306 | } | |
5307 | ||
319be8ae | 5308 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5309 | { |
319be8ae ID |
5310 | struct drm_device *dev = crtc->dev; |
5311 | struct intel_encoder *intel_encoder; | |
5312 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5313 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5314 | unsigned long mask; |
1a70a728 | 5315 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
77d22dca | 5316 | |
292b990e ML |
5317 | if (!crtc->state->active) |
5318 | return 0; | |
5319 | ||
77d22dca ID |
5320 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5321 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5322 | if (intel_crtc->config->pch_pfit.enabled || |
5323 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5324 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5325 | ||
319be8ae ID |
5326 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5327 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5328 | ||
77d22dca ID |
5329 | return mask; |
5330 | } | |
5331 | ||
292b990e | 5332 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5333 | { |
292b990e ML |
5334 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5336 | enum intel_display_power_domain domain; | |
5337 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5338 | |
292b990e ML |
5339 | old_domains = intel_crtc->enabled_power_domains; |
5340 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5341 | |
292b990e ML |
5342 | domains = new_domains & ~old_domains; |
5343 | ||
5344 | for_each_power_domain(domain, domains) | |
5345 | intel_display_power_get(dev_priv, domain); | |
5346 | ||
5347 | return old_domains & ~new_domains; | |
5348 | } | |
5349 | ||
5350 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5351 | unsigned long domains) | |
5352 | { | |
5353 | enum intel_display_power_domain domain; | |
5354 | ||
5355 | for_each_power_domain(domain, domains) | |
5356 | intel_display_power_put(dev_priv, domain); | |
5357 | } | |
77d22dca | 5358 | |
292b990e ML |
5359 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5360 | { | |
1a617b77 | 5361 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
292b990e ML |
5362 | struct drm_device *dev = state->dev; |
5363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5364 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5365 | struct drm_crtc_state *crtc_state; | |
5366 | struct drm_crtc *crtc; | |
5367 | int i; | |
77d22dca | 5368 | |
292b990e ML |
5369 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5370 | if (needs_modeset(crtc->state)) | |
5371 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5372 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5373 | } |
5374 | ||
1a617b77 ML |
5375 | if (dev_priv->display.modeset_commit_cdclk && |
5376 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
5377 | dev_priv->display.modeset_commit_cdclk(state); | |
50f6e502 | 5378 | |
292b990e ML |
5379 | for (i = 0; i < I915_MAX_PIPES; i++) |
5380 | if (put_domains[i]) | |
5381 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5382 | } |
5383 | ||
adafdc6f MK |
5384 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5385 | { | |
5386 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5387 | ||
5388 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5389 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5390 | return max_cdclk_freq; | |
5391 | else if (IS_CHERRYVIEW(dev_priv)) | |
5392 | return max_cdclk_freq*95/100; | |
5393 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5394 | return 2*max_cdclk_freq*90/100; | |
5395 | else | |
5396 | return max_cdclk_freq*90/100; | |
5397 | } | |
5398 | ||
560a7ae4 DL |
5399 | static void intel_update_max_cdclk(struct drm_device *dev) |
5400 | { | |
5401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5402 | ||
ef11bdb3 | 5403 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5404 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5405 | ||
5406 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5407 | dev_priv->max_cdclk_freq = 675000; | |
5408 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5409 | dev_priv->max_cdclk_freq = 540000; | |
5410 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5411 | dev_priv->max_cdclk_freq = 450000; | |
5412 | else | |
5413 | dev_priv->max_cdclk_freq = 337500; | |
5414 | } else if (IS_BROADWELL(dev)) { | |
5415 | /* | |
5416 | * FIXME with extra cooling we can allow | |
5417 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5418 | * How can we know if extra cooling is | |
5419 | * available? PCI ID, VTB, something else? | |
5420 | */ | |
5421 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5422 | dev_priv->max_cdclk_freq = 450000; | |
5423 | else if (IS_BDW_ULX(dev)) | |
5424 | dev_priv->max_cdclk_freq = 450000; | |
5425 | else if (IS_BDW_ULT(dev)) | |
5426 | dev_priv->max_cdclk_freq = 540000; | |
5427 | else | |
5428 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5429 | } else if (IS_CHERRYVIEW(dev)) { |
5430 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5431 | } else if (IS_VALLEYVIEW(dev)) { |
5432 | dev_priv->max_cdclk_freq = 400000; | |
5433 | } else { | |
5434 | /* otherwise assume cdclk is fixed */ | |
5435 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5436 | } | |
5437 | ||
adafdc6f MK |
5438 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5439 | ||
560a7ae4 DL |
5440 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5441 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5442 | |
5443 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5444 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5445 | } |
5446 | ||
5447 | static void intel_update_cdclk(struct drm_device *dev) | |
5448 | { | |
5449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5450 | ||
5451 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5452 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5453 | dev_priv->cdclk_freq); | |
5454 | ||
5455 | /* | |
5456 | * Program the gmbus_freq based on the cdclk frequency. | |
5457 | * BSpec erroneously claims we should aim for 4MHz, but | |
5458 | * in fact 1MHz is the correct frequency. | |
5459 | */ | |
666a4537 | 5460 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5461 | /* |
5462 | * Program the gmbus_freq based on the cdclk frequency. | |
5463 | * BSpec erroneously claims we should aim for 4MHz, but | |
5464 | * in fact 1MHz is the correct frequency. | |
5465 | */ | |
5466 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5467 | } | |
5468 | ||
5469 | if (dev_priv->max_cdclk_freq == 0) | |
5470 | intel_update_max_cdclk(dev); | |
5471 | } | |
5472 | ||
70d0c574 | 5473 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5474 | { |
5475 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5476 | uint32_t divider; | |
5477 | uint32_t ratio; | |
5478 | uint32_t current_freq; | |
5479 | int ret; | |
5480 | ||
5481 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5482 | switch (frequency) { | |
5483 | case 144000: | |
5484 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5485 | ratio = BXT_DE_PLL_RATIO(60); | |
5486 | break; | |
5487 | case 288000: | |
5488 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5489 | ratio = BXT_DE_PLL_RATIO(60); | |
5490 | break; | |
5491 | case 384000: | |
5492 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5493 | ratio = BXT_DE_PLL_RATIO(60); | |
5494 | break; | |
5495 | case 576000: | |
5496 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5497 | ratio = BXT_DE_PLL_RATIO(60); | |
5498 | break; | |
5499 | case 624000: | |
5500 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5501 | ratio = BXT_DE_PLL_RATIO(65); | |
5502 | break; | |
5503 | case 19200: | |
5504 | /* | |
5505 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5506 | * to suppress GCC warning. | |
5507 | */ | |
5508 | ratio = 0; | |
5509 | divider = 0; | |
5510 | break; | |
5511 | default: | |
5512 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5513 | ||
5514 | return; | |
5515 | } | |
5516 | ||
5517 | mutex_lock(&dev_priv->rps.hw_lock); | |
5518 | /* Inform power controller of upcoming frequency change */ | |
5519 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5520 | 0x80000000); | |
5521 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5522 | ||
5523 | if (ret) { | |
5524 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5525 | ret, frequency); | |
5526 | return; | |
5527 | } | |
5528 | ||
5529 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5530 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5531 | current_freq = current_freq * 500 + 1000; | |
5532 | ||
5533 | /* | |
5534 | * DE PLL has to be disabled when | |
5535 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5536 | * - before setting to 624MHz (PLL needs toggling) | |
5537 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5538 | */ | |
5539 | if (frequency == 19200 || frequency == 624000 || | |
5540 | current_freq == 624000) { | |
5541 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5542 | /* Timeout 200us */ | |
5543 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5544 | 1)) | |
5545 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5546 | } | |
5547 | ||
5548 | if (frequency != 19200) { | |
5549 | uint32_t val; | |
5550 | ||
5551 | val = I915_READ(BXT_DE_PLL_CTL); | |
5552 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5553 | val |= ratio; | |
5554 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5555 | ||
5556 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5557 | /* Timeout 200us */ | |
5558 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5559 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5560 | ||
5561 | val = I915_READ(CDCLK_CTL); | |
5562 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5563 | val |= divider; | |
5564 | /* | |
5565 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5566 | * enable otherwise. | |
5567 | */ | |
5568 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5569 | if (frequency >= 500000) | |
5570 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5571 | ||
5572 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5573 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5574 | val |= (frequency - 1000) / 500; | |
5575 | I915_WRITE(CDCLK_CTL, val); | |
5576 | } | |
5577 | ||
5578 | mutex_lock(&dev_priv->rps.hw_lock); | |
5579 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5580 | DIV_ROUND_UP(frequency, 25000)); | |
5581 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5582 | ||
5583 | if (ret) { | |
5584 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5585 | ret, frequency); | |
5586 | return; | |
5587 | } | |
5588 | ||
a47871bd | 5589 | intel_update_cdclk(dev); |
f8437dd1 VK |
5590 | } |
5591 | ||
5592 | void broxton_init_cdclk(struct drm_device *dev) | |
5593 | { | |
5594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5595 | uint32_t val; | |
5596 | ||
5597 | /* | |
5598 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5599 | * or else the reset will hang because there is no PCH to respond. | |
5600 | * Move the handshake programming to initialization sequence. | |
5601 | * Previously was left up to BIOS. | |
5602 | */ | |
5603 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5604 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5605 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5606 | ||
5607 | /* Enable PG1 for cdclk */ | |
5608 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5609 | ||
5610 | /* check if cd clock is enabled */ | |
5611 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5612 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5613 | return; | |
5614 | } | |
5615 | ||
5616 | /* | |
5617 | * FIXME: | |
5618 | * - The initial CDCLK needs to be read from VBT. | |
5619 | * Need to make this change after VBT has changes for BXT. | |
5620 | * - check if setting the max (or any) cdclk freq is really necessary | |
5621 | * here, it belongs to modeset time | |
5622 | */ | |
5623 | broxton_set_cdclk(dev, 624000); | |
5624 | ||
5625 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5626 | POSTING_READ(DBUF_CTL); |
5627 | ||
f8437dd1 VK |
5628 | udelay(10); |
5629 | ||
5630 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5631 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5632 | } | |
5633 | ||
5634 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5635 | { | |
5636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5637 | ||
5638 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5639 | POSTING_READ(DBUF_CTL); |
5640 | ||
f8437dd1 VK |
5641 | udelay(10); |
5642 | ||
5643 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5644 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5645 | ||
5646 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5647 | broxton_set_cdclk(dev, 19200); | |
5648 | ||
5649 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5650 | } | |
5651 | ||
5d96d8af DL |
5652 | static const struct skl_cdclk_entry { |
5653 | unsigned int freq; | |
5654 | unsigned int vco; | |
5655 | } skl_cdclk_frequencies[] = { | |
5656 | { .freq = 308570, .vco = 8640 }, | |
5657 | { .freq = 337500, .vco = 8100 }, | |
5658 | { .freq = 432000, .vco = 8640 }, | |
5659 | { .freq = 450000, .vco = 8100 }, | |
5660 | { .freq = 540000, .vco = 8100 }, | |
5661 | { .freq = 617140, .vco = 8640 }, | |
5662 | { .freq = 675000, .vco = 8100 }, | |
5663 | }; | |
5664 | ||
5665 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5666 | { | |
5667 | return (freq - 1000) / 500; | |
5668 | } | |
5669 | ||
5670 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5671 | { | |
5672 | unsigned int i; | |
5673 | ||
5674 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5675 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5676 | ||
5677 | if (e->freq == freq) | |
5678 | return e->vco; | |
5679 | } | |
5680 | ||
5681 | return 8100; | |
5682 | } | |
5683 | ||
5684 | static void | |
5685 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5686 | { | |
5687 | unsigned int min_freq; | |
5688 | u32 val; | |
5689 | ||
5690 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5691 | val = I915_READ(CDCLK_CTL); | |
5692 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5693 | val |= CDCLK_FREQ_337_308; | |
5694 | ||
5695 | if (required_vco == 8640) | |
5696 | min_freq = 308570; | |
5697 | else | |
5698 | min_freq = 337500; | |
5699 | ||
5700 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5701 | ||
5702 | I915_WRITE(CDCLK_CTL, val); | |
5703 | POSTING_READ(CDCLK_CTL); | |
5704 | ||
5705 | /* | |
5706 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5707 | * taking into account the VCO required to operate the eDP panel at the | |
5708 | * desired frequency. The usual DP link rates operate with a VCO of | |
5709 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5710 | * The modeset code is responsible for the selection of the exact link | |
5711 | * rate later on, with the constraint of choosing a frequency that | |
5712 | * works with required_vco. | |
5713 | */ | |
5714 | val = I915_READ(DPLL_CTRL1); | |
5715 | ||
5716 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5717 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5718 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5719 | if (required_vco == 8640) | |
5720 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5721 | SKL_DPLL0); | |
5722 | else | |
5723 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5724 | SKL_DPLL0); | |
5725 | ||
5726 | I915_WRITE(DPLL_CTRL1, val); | |
5727 | POSTING_READ(DPLL_CTRL1); | |
5728 | ||
5729 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5730 | ||
5731 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5732 | DRM_ERROR("DPLL0 not locked\n"); | |
5733 | } | |
5734 | ||
5735 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5736 | { | |
5737 | int ret; | |
5738 | u32 val; | |
5739 | ||
5740 | /* inform PCU we want to change CDCLK */ | |
5741 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5742 | mutex_lock(&dev_priv->rps.hw_lock); | |
5743 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5744 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5745 | ||
5746 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5747 | } | |
5748 | ||
5749 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5750 | { | |
5751 | unsigned int i; | |
5752 | ||
5753 | for (i = 0; i < 15; i++) { | |
5754 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5755 | return true; | |
5756 | udelay(10); | |
5757 | } | |
5758 | ||
5759 | return false; | |
5760 | } | |
5761 | ||
5762 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5763 | { | |
560a7ae4 | 5764 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5765 | u32 freq_select, pcu_ack; |
5766 | ||
5767 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5768 | ||
5769 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5770 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5771 | return; | |
5772 | } | |
5773 | ||
5774 | /* set CDCLK_CTL */ | |
5775 | switch(freq) { | |
5776 | case 450000: | |
5777 | case 432000: | |
5778 | freq_select = CDCLK_FREQ_450_432; | |
5779 | pcu_ack = 1; | |
5780 | break; | |
5781 | case 540000: | |
5782 | freq_select = CDCLK_FREQ_540; | |
5783 | pcu_ack = 2; | |
5784 | break; | |
5785 | case 308570: | |
5786 | case 337500: | |
5787 | default: | |
5788 | freq_select = CDCLK_FREQ_337_308; | |
5789 | pcu_ack = 0; | |
5790 | break; | |
5791 | case 617140: | |
5792 | case 675000: | |
5793 | freq_select = CDCLK_FREQ_675_617; | |
5794 | pcu_ack = 3; | |
5795 | break; | |
5796 | } | |
5797 | ||
5798 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5799 | POSTING_READ(CDCLK_CTL); | |
5800 | ||
5801 | /* inform PCU of the change */ | |
5802 | mutex_lock(&dev_priv->rps.hw_lock); | |
5803 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5804 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5805 | |
5806 | intel_update_cdclk(dev); | |
5d96d8af DL |
5807 | } |
5808 | ||
5809 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5810 | { | |
5811 | /* disable DBUF power */ | |
5812 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5813 | POSTING_READ(DBUF_CTL); | |
5814 | ||
5815 | udelay(10); | |
5816 | ||
5817 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5818 | DRM_ERROR("DBuf power disable timeout\n"); | |
5819 | ||
ab96c1ee ID |
5820 | /* disable DPLL0 */ |
5821 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5822 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5823 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5824 | } |
5825 | ||
5826 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5827 | { | |
5d96d8af DL |
5828 | unsigned int required_vco; |
5829 | ||
39d9b85a GW |
5830 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5831 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5832 | /* enable DPLL0 */ | |
5833 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5834 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5835 | } |
5836 | ||
5d96d8af DL |
5837 | /* set CDCLK to the frequency the BIOS chose */ |
5838 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5839 | ||
5840 | /* enable DBUF power */ | |
5841 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5842 | POSTING_READ(DBUF_CTL); | |
5843 | ||
5844 | udelay(10); | |
5845 | ||
5846 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5847 | DRM_ERROR("DBuf power enable timeout\n"); | |
5848 | } | |
5849 | ||
c73666f3 SK |
5850 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5851 | { | |
5852 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5853 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5854 | int freq = dev_priv->skl_boot_cdclk; | |
5855 | ||
f1b391a5 SK |
5856 | /* |
5857 | * check if the pre-os intialized the display | |
5858 | * There is SWF18 scratchpad register defined which is set by the | |
5859 | * pre-os which can be used by the OS drivers to check the status | |
5860 | */ | |
5861 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5862 | goto sanitize; | |
5863 | ||
c73666f3 SK |
5864 | /* Is PLL enabled and locked ? */ |
5865 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5866 | goto sanitize; | |
5867 | ||
5868 | /* DPLL okay; verify the cdclock | |
5869 | * | |
5870 | * Noticed in some instances that the freq selection is correct but | |
5871 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5872 | * enable display. Verify the same as well. | |
5873 | */ | |
5874 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5875 | /* All well; nothing to sanitize */ | |
5876 | return false; | |
5877 | sanitize: | |
5878 | /* | |
5879 | * As of now initialize with max cdclk till | |
5880 | * we get dynamic cdclk support | |
5881 | * */ | |
5882 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5883 | skl_init_cdclk(dev_priv); | |
5884 | ||
5885 | /* we did have to sanitize */ | |
5886 | return true; | |
5887 | } | |
5888 | ||
30a970c6 JB |
5889 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5890 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5891 | { | |
5892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5893 | u32 val, cmd; | |
5894 | ||
164dfd28 VK |
5895 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5896 | != dev_priv->cdclk_freq); | |
d60c4473 | 5897 | |
dfcab17e | 5898 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5899 | cmd = 2; |
dfcab17e | 5900 | else if (cdclk == 266667) |
30a970c6 JB |
5901 | cmd = 1; |
5902 | else | |
5903 | cmd = 0; | |
5904 | ||
5905 | mutex_lock(&dev_priv->rps.hw_lock); | |
5906 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5907 | val &= ~DSPFREQGUAR_MASK; | |
5908 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5909 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5910 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5911 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5912 | 50)) { | |
5913 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5914 | } | |
5915 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5916 | ||
54433e91 VS |
5917 | mutex_lock(&dev_priv->sb_lock); |
5918 | ||
dfcab17e | 5919 | if (cdclk == 400000) { |
6bcda4f0 | 5920 | u32 divider; |
30a970c6 | 5921 | |
6bcda4f0 | 5922 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5923 | |
30a970c6 JB |
5924 | /* adjust cdclk divider */ |
5925 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5926 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5927 | val |= divider; |
5928 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5929 | |
5930 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5931 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5932 | 50)) |
5933 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5934 | } |
5935 | ||
30a970c6 JB |
5936 | /* adjust self-refresh exit latency value */ |
5937 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5938 | val &= ~0x7f; | |
5939 | ||
5940 | /* | |
5941 | * For high bandwidth configs, we set a higher latency in the bunit | |
5942 | * so that the core display fetch happens in time to avoid underruns. | |
5943 | */ | |
dfcab17e | 5944 | if (cdclk == 400000) |
30a970c6 JB |
5945 | val |= 4500 / 250; /* 4.5 usec */ |
5946 | else | |
5947 | val |= 3000 / 250; /* 3.0 usec */ | |
5948 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5949 | |
a580516d | 5950 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5951 | |
b6283055 | 5952 | intel_update_cdclk(dev); |
30a970c6 JB |
5953 | } |
5954 | ||
383c5a6a VS |
5955 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5956 | { | |
5957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5958 | u32 val, cmd; | |
5959 | ||
164dfd28 VK |
5960 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5961 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5962 | |
5963 | switch (cdclk) { | |
383c5a6a VS |
5964 | case 333333: |
5965 | case 320000: | |
383c5a6a | 5966 | case 266667: |
383c5a6a | 5967 | case 200000: |
383c5a6a VS |
5968 | break; |
5969 | default: | |
5f77eeb0 | 5970 | MISSING_CASE(cdclk); |
383c5a6a VS |
5971 | return; |
5972 | } | |
5973 | ||
9d0d3fda VS |
5974 | /* |
5975 | * Specs are full of misinformation, but testing on actual | |
5976 | * hardware has shown that we just need to write the desired | |
5977 | * CCK divider into the Punit register. | |
5978 | */ | |
5979 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5980 | ||
383c5a6a VS |
5981 | mutex_lock(&dev_priv->rps.hw_lock); |
5982 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5983 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5984 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5985 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5986 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5987 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5988 | 50)) { | |
5989 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5990 | } | |
5991 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5992 | ||
b6283055 | 5993 | intel_update_cdclk(dev); |
383c5a6a VS |
5994 | } |
5995 | ||
30a970c6 JB |
5996 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5997 | int max_pixclk) | |
5998 | { | |
6bcda4f0 | 5999 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6000 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6001 | |
30a970c6 JB |
6002 | /* |
6003 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6004 | * 200MHz | |
6005 | * 267MHz | |
29dc7ef3 | 6006 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6007 | * 400MHz (VLV only) |
6008 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6009 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6010 | * |
6011 | * We seem to get an unstable or solid color picture at 200MHz. | |
6012 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6013 | * are off. | |
30a970c6 | 6014 | */ |
6cca3195 VS |
6015 | if (!IS_CHERRYVIEW(dev_priv) && |
6016 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6017 | return 400000; |
6cca3195 | 6018 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6019 | return freq_320; |
e37c67a1 | 6020 | else if (max_pixclk > 0) |
dfcab17e | 6021 | return 266667; |
e37c67a1 VS |
6022 | else |
6023 | return 200000; | |
30a970c6 JB |
6024 | } |
6025 | ||
f8437dd1 VK |
6026 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6027 | int max_pixclk) | |
6028 | { | |
6029 | /* | |
6030 | * FIXME: | |
6031 | * - remove the guardband, it's not needed on BXT | |
6032 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6033 | */ | |
6034 | if (max_pixclk > 576000*9/10) | |
6035 | return 624000; | |
6036 | else if (max_pixclk > 384000*9/10) | |
6037 | return 576000; | |
6038 | else if (max_pixclk > 288000*9/10) | |
6039 | return 384000; | |
6040 | else if (max_pixclk > 144000*9/10) | |
6041 | return 288000; | |
6042 | else | |
6043 | return 144000; | |
6044 | } | |
6045 | ||
a821fc46 ACO |
6046 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
6047 | * that's non-NULL, look at current state otherwise. */ | |
6048 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
6049 | struct drm_atomic_state *state) | |
30a970c6 | 6050 | { |
565602d7 ML |
6051 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
6052 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6053 | struct drm_crtc *crtc; | |
6054 | struct drm_crtc_state *crtc_state; | |
6055 | unsigned max_pixclk = 0, i; | |
6056 | enum pipe pipe; | |
30a970c6 | 6057 | |
565602d7 ML |
6058 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6059 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6060 | |
565602d7 ML |
6061 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6062 | int pixclk = 0; | |
6063 | ||
6064 | if (crtc_state->enable) | |
6065 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6066 | |
565602d7 | 6067 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6068 | } |
6069 | ||
565602d7 ML |
6070 | if (!intel_state->active_crtcs) |
6071 | return 0; | |
6072 | ||
6073 | for_each_pipe(dev_priv, pipe) | |
6074 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6075 | ||
30a970c6 JB |
6076 | return max_pixclk; |
6077 | } | |
6078 | ||
27c329ed | 6079 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6080 | { |
27c329ed ML |
6081 | struct drm_device *dev = state->dev; |
6082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6083 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6084 | struct intel_atomic_state *intel_state = |
6085 | to_intel_atomic_state(state); | |
30a970c6 | 6086 | |
304603f4 ACO |
6087 | if (max_pixclk < 0) |
6088 | return max_pixclk; | |
30a970c6 | 6089 | |
1a617b77 | 6090 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6091 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6092 | |
1a617b77 ML |
6093 | if (!intel_state->active_crtcs) |
6094 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6095 | ||
27c329ed ML |
6096 | return 0; |
6097 | } | |
304603f4 | 6098 | |
27c329ed ML |
6099 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6100 | { | |
6101 | struct drm_device *dev = state->dev; | |
6102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6103 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6104 | struct intel_atomic_state *intel_state = |
6105 | to_intel_atomic_state(state); | |
85a96e7a | 6106 | |
27c329ed ML |
6107 | if (max_pixclk < 0) |
6108 | return max_pixclk; | |
85a96e7a | 6109 | |
1a617b77 | 6110 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6111 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 6112 | |
1a617b77 ML |
6113 | if (!intel_state->active_crtcs) |
6114 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
6115 | ||
27c329ed | 6116 | return 0; |
30a970c6 JB |
6117 | } |
6118 | ||
1e69cd74 VS |
6119 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6120 | { | |
6121 | unsigned int credits, default_credits; | |
6122 | ||
6123 | if (IS_CHERRYVIEW(dev_priv)) | |
6124 | default_credits = PFI_CREDIT(12); | |
6125 | else | |
6126 | default_credits = PFI_CREDIT(8); | |
6127 | ||
bfa7df01 | 6128 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6129 | /* CHV suggested value is 31 or 63 */ |
6130 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6131 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6132 | else |
6133 | credits = PFI_CREDIT(15); | |
6134 | } else { | |
6135 | credits = default_credits; | |
6136 | } | |
6137 | ||
6138 | /* | |
6139 | * WA - write default credits before re-programming | |
6140 | * FIXME: should we also set the resend bit here? | |
6141 | */ | |
6142 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6143 | default_credits); | |
6144 | ||
6145 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6146 | credits | PFI_CREDIT_RESEND); | |
6147 | ||
6148 | /* | |
6149 | * FIXME is this guaranteed to clear | |
6150 | * immediately or should we poll for it? | |
6151 | */ | |
6152 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6153 | } | |
6154 | ||
27c329ed | 6155 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6156 | { |
a821fc46 | 6157 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6158 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6159 | struct intel_atomic_state *old_intel_state = |
6160 | to_intel_atomic_state(old_state); | |
6161 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6162 | |
27c329ed ML |
6163 | /* |
6164 | * FIXME: We can end up here with all power domains off, yet | |
6165 | * with a CDCLK frequency other than the minimum. To account | |
6166 | * for this take the PIPE-A power domain, which covers the HW | |
6167 | * blocks needed for the following programming. This can be | |
6168 | * removed once it's guaranteed that we get here either with | |
6169 | * the minimum CDCLK set, or the required power domains | |
6170 | * enabled. | |
6171 | */ | |
6172 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6173 | |
27c329ed ML |
6174 | if (IS_CHERRYVIEW(dev)) |
6175 | cherryview_set_cdclk(dev, req_cdclk); | |
6176 | else | |
6177 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6178 | |
27c329ed | 6179 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6180 | |
27c329ed | 6181 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6182 | } |
6183 | ||
89b667f8 JB |
6184 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6185 | { | |
6186 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6187 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6189 | struct intel_encoder *encoder; | |
6190 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6191 | |
53d9f4e9 | 6192 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6193 | return; |
6194 | ||
6e3c9717 | 6195 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6196 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6197 | |
6198 | intel_set_pipe_timings(intel_crtc); | |
6199 | ||
c14b0485 VS |
6200 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6201 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6202 | ||
6203 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6204 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6205 | } | |
6206 | ||
5b18e57c DV |
6207 | i9xx_set_pipeconf(intel_crtc); |
6208 | ||
89b667f8 | 6209 | intel_crtc->active = true; |
89b667f8 | 6210 | |
a72e4c9f | 6211 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6212 | |
89b667f8 JB |
6213 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6214 | if (encoder->pre_pll_enable) | |
6215 | encoder->pre_pll_enable(encoder); | |
6216 | ||
a65347ba | 6217 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6218 | if (IS_CHERRYVIEW(dev)) { |
6219 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6220 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6221 | } else { |
6222 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6223 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6224 | } |
9d556c99 | 6225 | } |
89b667f8 JB |
6226 | |
6227 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6228 | if (encoder->pre_enable) | |
6229 | encoder->pre_enable(encoder); | |
6230 | ||
2dd24552 JB |
6231 | i9xx_pfit_enable(intel_crtc); |
6232 | ||
63cbb074 VS |
6233 | intel_crtc_load_lut(crtc); |
6234 | ||
e1fdc473 | 6235 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6236 | |
4b3a9526 VS |
6237 | assert_vblank_disabled(crtc); |
6238 | drm_crtc_vblank_on(crtc); | |
6239 | ||
f9b61ff6 DV |
6240 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6241 | encoder->enable(encoder); | |
89b667f8 JB |
6242 | } |
6243 | ||
f13c2ef3 DV |
6244 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6245 | { | |
6246 | struct drm_device *dev = crtc->base.dev; | |
6247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6248 | ||
6e3c9717 ACO |
6249 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6250 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6251 | } |
6252 | ||
0b8765c6 | 6253 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6254 | { |
6255 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6256 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6257 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6258 | struct intel_encoder *encoder; |
79e53945 | 6259 | int pipe = intel_crtc->pipe; |
79e53945 | 6260 | |
53d9f4e9 | 6261 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6262 | return; |
6263 | ||
f13c2ef3 DV |
6264 | i9xx_set_pll_dividers(intel_crtc); |
6265 | ||
6e3c9717 | 6266 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6267 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6268 | |
6269 | intel_set_pipe_timings(intel_crtc); | |
6270 | ||
5b18e57c DV |
6271 | i9xx_set_pipeconf(intel_crtc); |
6272 | ||
f7abfe8b | 6273 | intel_crtc->active = true; |
6b383a7f | 6274 | |
4a3436e8 | 6275 | if (!IS_GEN2(dev)) |
a72e4c9f | 6276 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6277 | |
9d6d9f19 MK |
6278 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6279 | if (encoder->pre_enable) | |
6280 | encoder->pre_enable(encoder); | |
6281 | ||
f6736a1a DV |
6282 | i9xx_enable_pll(intel_crtc); |
6283 | ||
2dd24552 JB |
6284 | i9xx_pfit_enable(intel_crtc); |
6285 | ||
63cbb074 VS |
6286 | intel_crtc_load_lut(crtc); |
6287 | ||
f37fcc2a | 6288 | intel_update_watermarks(crtc); |
e1fdc473 | 6289 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6290 | |
4b3a9526 VS |
6291 | assert_vblank_disabled(crtc); |
6292 | drm_crtc_vblank_on(crtc); | |
6293 | ||
f9b61ff6 DV |
6294 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6295 | encoder->enable(encoder); | |
0b8765c6 | 6296 | } |
79e53945 | 6297 | |
87476d63 DV |
6298 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6299 | { | |
6300 | struct drm_device *dev = crtc->base.dev; | |
6301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6302 | |
6e3c9717 | 6303 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6304 | return; |
87476d63 | 6305 | |
328d8e82 | 6306 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6307 | |
328d8e82 DV |
6308 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6309 | I915_READ(PFIT_CONTROL)); | |
6310 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6311 | } |
6312 | ||
0b8765c6 JB |
6313 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6314 | { | |
6315 | struct drm_device *dev = crtc->dev; | |
6316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6317 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6318 | struct intel_encoder *encoder; |
0b8765c6 | 6319 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6320 | |
6304cd91 VS |
6321 | /* |
6322 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6323 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6324 | * We also need to wait on all gmch platforms because of the |
6325 | * self-refresh mode constraint explained above. | |
6304cd91 | 6326 | */ |
564ed191 | 6327 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6328 | |
4b3a9526 VS |
6329 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6330 | encoder->disable(encoder); | |
6331 | ||
f9b61ff6 DV |
6332 | drm_crtc_vblank_off(crtc); |
6333 | assert_vblank_disabled(crtc); | |
6334 | ||
575f7ab7 | 6335 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6336 | |
87476d63 | 6337 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6338 | |
89b667f8 JB |
6339 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6340 | if (encoder->post_disable) | |
6341 | encoder->post_disable(encoder); | |
6342 | ||
a65347ba | 6343 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6344 | if (IS_CHERRYVIEW(dev)) |
6345 | chv_disable_pll(dev_priv, pipe); | |
6346 | else if (IS_VALLEYVIEW(dev)) | |
6347 | vlv_disable_pll(dev_priv, pipe); | |
6348 | else | |
1c4e0274 | 6349 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6350 | } |
0b8765c6 | 6351 | |
d6db995f VS |
6352 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6353 | if (encoder->post_pll_disable) | |
6354 | encoder->post_pll_disable(encoder); | |
6355 | ||
4a3436e8 | 6356 | if (!IS_GEN2(dev)) |
a72e4c9f | 6357 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6358 | } |
6359 | ||
b17d48e2 ML |
6360 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6361 | { | |
6362 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6363 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6364 | enum intel_display_power_domain domain; | |
6365 | unsigned long domains; | |
6366 | ||
6367 | if (!intel_crtc->active) | |
6368 | return; | |
6369 | ||
a539205a | 6370 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6371 | WARN_ON(intel_crtc->unpin_work); |
6372 | ||
a539205a | 6373 | intel_pre_disable_primary(crtc); |
54a41961 ML |
6374 | |
6375 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6376 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6377 | } |
6378 | ||
b17d48e2 | 6379 | dev_priv->display.crtc_disable(crtc); |
37d9078b | 6380 | intel_crtc->active = false; |
58f9c0bc | 6381 | intel_fbc_disable(intel_crtc); |
37d9078b | 6382 | intel_update_watermarks(crtc); |
1f7457b1 | 6383 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6384 | |
6385 | domains = intel_crtc->enabled_power_domains; | |
6386 | for_each_power_domain(domain, domains) | |
6387 | intel_display_power_put(dev_priv, domain); | |
6388 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6389 | |
6390 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6391 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6392 | } |
6393 | ||
6b72d486 ML |
6394 | /* |
6395 | * turn all crtc's off, but do not adjust state | |
6396 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6397 | */ | |
70e0bd74 | 6398 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6399 | { |
70e0bd74 ML |
6400 | struct drm_mode_config *config = &dev->mode_config; |
6401 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6402 | struct drm_atomic_state *state; | |
6b72d486 | 6403 | struct drm_crtc *crtc; |
70e0bd74 ML |
6404 | unsigned crtc_mask = 0; |
6405 | int ret = 0; | |
6406 | ||
6407 | if (WARN_ON(!ctx)) | |
6408 | return 0; | |
6409 | ||
6410 | lockdep_assert_held(&ctx->ww_ctx); | |
6411 | state = drm_atomic_state_alloc(dev); | |
6412 | if (WARN_ON(!state)) | |
6413 | return -ENOMEM; | |
6414 | ||
6415 | state->acquire_ctx = ctx; | |
6416 | state->allow_modeset = true; | |
6417 | ||
6418 | for_each_crtc(dev, crtc) { | |
6419 | struct drm_crtc_state *crtc_state = | |
6420 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6421 | |
70e0bd74 ML |
6422 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6423 | if (ret) | |
6424 | goto free; | |
6425 | ||
6426 | if (!crtc_state->active) | |
6427 | continue; | |
6428 | ||
6429 | crtc_state->active = false; | |
6430 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6431 | } | |
6432 | ||
6433 | if (crtc_mask) { | |
74c090b1 | 6434 | ret = drm_atomic_commit(state); |
70e0bd74 ML |
6435 | |
6436 | if (!ret) { | |
6437 | for_each_crtc(dev, crtc) | |
6438 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6439 | crtc->state->active = true; | |
6440 | ||
6441 | return ret; | |
6442 | } | |
6443 | } | |
6444 | ||
6445 | free: | |
6446 | if (ret) | |
6447 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6448 | drm_atomic_state_free(state); | |
6449 | return ret; | |
ee7b9f93 JB |
6450 | } |
6451 | ||
ea5b213a | 6452 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6453 | { |
4ef69c7a | 6454 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6455 | |
ea5b213a CW |
6456 | drm_encoder_cleanup(encoder); |
6457 | kfree(intel_encoder); | |
7e7d76c3 JB |
6458 | } |
6459 | ||
0a91ca29 DV |
6460 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6461 | * internal consistency). */ | |
b980514c | 6462 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6463 | { |
35dd3c64 ML |
6464 | struct drm_crtc *crtc = connector->base.state->crtc; |
6465 | ||
6466 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6467 | connector->base.base.id, | |
6468 | connector->base.name); | |
6469 | ||
0a91ca29 | 6470 | if (connector->get_hw_state(connector)) { |
e85376cb | 6471 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6472 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6473 | |
35dd3c64 ML |
6474 | I915_STATE_WARN(!crtc, |
6475 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6476 | |
35dd3c64 ML |
6477 | if (!crtc) |
6478 | return; | |
6479 | ||
6480 | I915_STATE_WARN(!crtc->state->active, | |
6481 | "connector is active, but attached crtc isn't\n"); | |
6482 | ||
e85376cb | 6483 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6484 | return; |
6485 | ||
e85376cb | 6486 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6487 | "atomic encoder doesn't match attached encoder\n"); |
6488 | ||
e85376cb | 6489 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6490 | "attached encoder crtc differs from connector crtc\n"); |
6491 | } else { | |
4d688a2a ML |
6492 | I915_STATE_WARN(crtc && crtc->state->active, |
6493 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6494 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6495 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6496 | } |
79e53945 JB |
6497 | } |
6498 | ||
08d9bc92 ACO |
6499 | int intel_connector_init(struct intel_connector *connector) |
6500 | { | |
5350a031 | 6501 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6502 | |
5350a031 | 6503 | if (!connector->base.state) |
08d9bc92 ACO |
6504 | return -ENOMEM; |
6505 | ||
08d9bc92 ACO |
6506 | return 0; |
6507 | } | |
6508 | ||
6509 | struct intel_connector *intel_connector_alloc(void) | |
6510 | { | |
6511 | struct intel_connector *connector; | |
6512 | ||
6513 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6514 | if (!connector) | |
6515 | return NULL; | |
6516 | ||
6517 | if (intel_connector_init(connector) < 0) { | |
6518 | kfree(connector); | |
6519 | return NULL; | |
6520 | } | |
6521 | ||
6522 | return connector; | |
6523 | } | |
6524 | ||
f0947c37 DV |
6525 | /* Simple connector->get_hw_state implementation for encoders that support only |
6526 | * one connector and no cloning and hence the encoder state determines the state | |
6527 | * of the connector. */ | |
6528 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6529 | { |
24929352 | 6530 | enum pipe pipe = 0; |
f0947c37 | 6531 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6532 | |
f0947c37 | 6533 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6534 | } |
6535 | ||
6d293983 | 6536 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6537 | { |
6d293983 ACO |
6538 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6539 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6540 | |
6541 | return 0; | |
6542 | } | |
6543 | ||
6d293983 | 6544 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6545 | struct intel_crtc_state *pipe_config) |
1857e1da | 6546 | { |
6d293983 ACO |
6547 | struct drm_atomic_state *state = pipe_config->base.state; |
6548 | struct intel_crtc *other_crtc; | |
6549 | struct intel_crtc_state *other_crtc_state; | |
6550 | ||
1857e1da DV |
6551 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6552 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6553 | if (pipe_config->fdi_lanes > 4) { | |
6554 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6555 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6556 | return -EINVAL; |
1857e1da DV |
6557 | } |
6558 | ||
bafb6553 | 6559 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6560 | if (pipe_config->fdi_lanes > 2) { |
6561 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6562 | pipe_config->fdi_lanes); | |
6d293983 | 6563 | return -EINVAL; |
1857e1da | 6564 | } else { |
6d293983 | 6565 | return 0; |
1857e1da DV |
6566 | } |
6567 | } | |
6568 | ||
6569 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6570 | return 0; |
1857e1da DV |
6571 | |
6572 | /* Ivybridge 3 pipe is really complicated */ | |
6573 | switch (pipe) { | |
6574 | case PIPE_A: | |
6d293983 | 6575 | return 0; |
1857e1da | 6576 | case PIPE_B: |
6d293983 ACO |
6577 | if (pipe_config->fdi_lanes <= 2) |
6578 | return 0; | |
6579 | ||
6580 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6581 | other_crtc_state = | |
6582 | intel_atomic_get_crtc_state(state, other_crtc); | |
6583 | if (IS_ERR(other_crtc_state)) | |
6584 | return PTR_ERR(other_crtc_state); | |
6585 | ||
6586 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6587 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6588 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6589 | return -EINVAL; |
1857e1da | 6590 | } |
6d293983 | 6591 | return 0; |
1857e1da | 6592 | case PIPE_C: |
251cc67c VS |
6593 | if (pipe_config->fdi_lanes > 2) { |
6594 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6595 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6596 | return -EINVAL; |
251cc67c | 6597 | } |
6d293983 ACO |
6598 | |
6599 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6600 | other_crtc_state = | |
6601 | intel_atomic_get_crtc_state(state, other_crtc); | |
6602 | if (IS_ERR(other_crtc_state)) | |
6603 | return PTR_ERR(other_crtc_state); | |
6604 | ||
6605 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6606 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6607 | return -EINVAL; |
1857e1da | 6608 | } |
6d293983 | 6609 | return 0; |
1857e1da DV |
6610 | default: |
6611 | BUG(); | |
6612 | } | |
6613 | } | |
6614 | ||
e29c22c0 DV |
6615 | #define RETRY 1 |
6616 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6617 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6618 | { |
1857e1da | 6619 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6620 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6621 | int lane, link_bw, fdi_dotclock, ret; |
6622 | bool needs_recompute = false; | |
877d48d5 | 6623 | |
e29c22c0 | 6624 | retry: |
877d48d5 DV |
6625 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6626 | * each output octet as 10 bits. The actual frequency | |
6627 | * is stored as a divider into a 100MHz clock, and the | |
6628 | * mode pixel clock is stored in units of 1KHz. | |
6629 | * Hence the bw of each lane in terms of the mode signal | |
6630 | * is: | |
6631 | */ | |
6632 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6633 | ||
241bfc38 | 6634 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6635 | |
2bd89a07 | 6636 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6637 | pipe_config->pipe_bpp); |
6638 | ||
6639 | pipe_config->fdi_lanes = lane; | |
6640 | ||
2bd89a07 | 6641 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6642 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6643 | |
6d293983 ACO |
6644 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6645 | intel_crtc->pipe, pipe_config); | |
6646 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6647 | pipe_config->pipe_bpp -= 2*3; |
6648 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6649 | pipe_config->pipe_bpp); | |
6650 | needs_recompute = true; | |
6651 | pipe_config->bw_constrained = true; | |
6652 | ||
6653 | goto retry; | |
6654 | } | |
6655 | ||
6656 | if (needs_recompute) | |
6657 | return RETRY; | |
6658 | ||
6d293983 | 6659 | return ret; |
877d48d5 DV |
6660 | } |
6661 | ||
8cfb3407 VS |
6662 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6663 | struct intel_crtc_state *pipe_config) | |
6664 | { | |
6665 | if (pipe_config->pipe_bpp > 24) | |
6666 | return false; | |
6667 | ||
6668 | /* HSW can handle pixel rate up to cdclk? */ | |
6669 | if (IS_HASWELL(dev_priv->dev)) | |
6670 | return true; | |
6671 | ||
6672 | /* | |
b432e5cf VS |
6673 | * We compare against max which means we must take |
6674 | * the increased cdclk requirement into account when | |
6675 | * calculating the new cdclk. | |
6676 | * | |
6677 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6678 | */ |
6679 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6680 | dev_priv->max_cdclk_freq * 95 / 100; | |
6681 | } | |
6682 | ||
42db64ef | 6683 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6684 | struct intel_crtc_state *pipe_config) |
42db64ef | 6685 | { |
8cfb3407 VS |
6686 | struct drm_device *dev = crtc->base.dev; |
6687 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6688 | ||
d330a953 | 6689 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6690 | hsw_crtc_supports_ips(crtc) && |
6691 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6692 | } |
6693 | ||
39acb4aa VS |
6694 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6695 | { | |
6696 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6697 | ||
6698 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6699 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6700 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6701 | } | |
6702 | ||
a43f6e0f | 6703 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6704 | struct intel_crtc_state *pipe_config) |
79e53945 | 6705 | { |
a43f6e0f | 6706 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6707 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6708 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6709 | |
ad3a4479 | 6710 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6711 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6712 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6713 | |
6714 | /* | |
39acb4aa | 6715 | * Enable double wide mode when the dot clock |
cf532bb2 | 6716 | * is > 90% of the (display) core speed. |
cf532bb2 | 6717 | */ |
39acb4aa VS |
6718 | if (intel_crtc_supports_double_wide(crtc) && |
6719 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6720 | clock_limit *= 2; |
cf532bb2 | 6721 | pipe_config->double_wide = true; |
ad3a4479 VS |
6722 | } |
6723 | ||
39acb4aa VS |
6724 | if (adjusted_mode->crtc_clock > clock_limit) { |
6725 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6726 | adjusted_mode->crtc_clock, clock_limit, | |
6727 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6728 | return -EINVAL; |
39acb4aa | 6729 | } |
2c07245f | 6730 | } |
89749350 | 6731 | |
1d1d0e27 VS |
6732 | /* |
6733 | * Pipe horizontal size must be even in: | |
6734 | * - DVO ganged mode | |
6735 | * - LVDS dual channel mode | |
6736 | * - Double wide pipe | |
6737 | */ | |
a93e255f | 6738 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6739 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6740 | pipe_config->pipe_src_w &= ~1; | |
6741 | ||
8693a824 DL |
6742 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6743 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6744 | */ |
6745 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6746 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6747 | return -EINVAL; |
44f46b42 | 6748 | |
f5adf94e | 6749 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6750 | hsw_compute_ips_config(crtc, pipe_config); |
6751 | ||
877d48d5 | 6752 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6753 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6754 | |
cf5a15be | 6755 | return 0; |
79e53945 JB |
6756 | } |
6757 | ||
1652d19e VS |
6758 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6759 | { | |
6760 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6761 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6762 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6763 | uint32_t linkrate; | |
6764 | ||
414355a7 | 6765 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6766 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6767 | |
6768 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6769 | return 540000; | |
6770 | ||
6771 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6772 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6773 | |
71cd8423 DL |
6774 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6775 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6776 | /* vco 8640 */ |
6777 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6778 | case CDCLK_FREQ_450_432: | |
6779 | return 432000; | |
6780 | case CDCLK_FREQ_337_308: | |
6781 | return 308570; | |
6782 | case CDCLK_FREQ_675_617: | |
6783 | return 617140; | |
6784 | default: | |
6785 | WARN(1, "Unknown cd freq selection\n"); | |
6786 | } | |
6787 | } else { | |
6788 | /* vco 8100 */ | |
6789 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6790 | case CDCLK_FREQ_450_432: | |
6791 | return 450000; | |
6792 | case CDCLK_FREQ_337_308: | |
6793 | return 337500; | |
6794 | case CDCLK_FREQ_675_617: | |
6795 | return 675000; | |
6796 | default: | |
6797 | WARN(1, "Unknown cd freq selection\n"); | |
6798 | } | |
6799 | } | |
6800 | ||
6801 | /* error case, do as if DPLL0 isn't enabled */ | |
6802 | return 24000; | |
6803 | } | |
6804 | ||
acd3f3d3 BP |
6805 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6806 | { | |
6807 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6808 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6809 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6810 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6811 | int cdclk; | |
6812 | ||
6813 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6814 | return 19200; | |
6815 | ||
6816 | cdclk = 19200 * pll_ratio / 2; | |
6817 | ||
6818 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6819 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6820 | return cdclk; /* 576MHz or 624MHz */ | |
6821 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6822 | return cdclk * 2 / 3; /* 384MHz */ | |
6823 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6824 | return cdclk / 2; /* 288MHz */ | |
6825 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6826 | return cdclk / 4; /* 144MHz */ | |
6827 | } | |
6828 | ||
6829 | /* error case, do as if DE PLL isn't enabled */ | |
6830 | return 19200; | |
6831 | } | |
6832 | ||
1652d19e VS |
6833 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6834 | { | |
6835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6836 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6837 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6838 | ||
6839 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6840 | return 800000; | |
6841 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6842 | return 450000; | |
6843 | else if (freq == LCPLL_CLK_FREQ_450) | |
6844 | return 450000; | |
6845 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6846 | return 540000; | |
6847 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6848 | return 337500; | |
6849 | else | |
6850 | return 675000; | |
6851 | } | |
6852 | ||
6853 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6854 | { | |
6855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6856 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6857 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6858 | ||
6859 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6860 | return 800000; | |
6861 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6862 | return 450000; | |
6863 | else if (freq == LCPLL_CLK_FREQ_450) | |
6864 | return 450000; | |
6865 | else if (IS_HSW_ULT(dev)) | |
6866 | return 337500; | |
6867 | else | |
6868 | return 540000; | |
79e53945 JB |
6869 | } |
6870 | ||
25eb05fc JB |
6871 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6872 | { | |
bfa7df01 VS |
6873 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6874 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6875 | } |
6876 | ||
b37a6434 VS |
6877 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6878 | { | |
6879 | return 450000; | |
6880 | } | |
6881 | ||
e70236a8 JB |
6882 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6883 | { | |
6884 | return 400000; | |
6885 | } | |
79e53945 | 6886 | |
e70236a8 | 6887 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6888 | { |
e907f170 | 6889 | return 333333; |
e70236a8 | 6890 | } |
79e53945 | 6891 | |
e70236a8 JB |
6892 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6893 | { | |
6894 | return 200000; | |
6895 | } | |
79e53945 | 6896 | |
257a7ffc DV |
6897 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6898 | { | |
6899 | u16 gcfgc = 0; | |
6900 | ||
6901 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6902 | ||
6903 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6904 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6905 | return 266667; |
257a7ffc | 6906 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6907 | return 333333; |
257a7ffc | 6908 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6909 | return 444444; |
257a7ffc DV |
6910 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6911 | return 200000; | |
6912 | default: | |
6913 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6914 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6915 | return 133333; |
257a7ffc | 6916 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6917 | return 166667; |
257a7ffc DV |
6918 | } |
6919 | } | |
6920 | ||
e70236a8 JB |
6921 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6922 | { | |
6923 | u16 gcfgc = 0; | |
79e53945 | 6924 | |
e70236a8 JB |
6925 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6926 | ||
6927 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6928 | return 133333; |
e70236a8 JB |
6929 | else { |
6930 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6931 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6932 | return 333333; |
e70236a8 JB |
6933 | default: |
6934 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6935 | return 190000; | |
79e53945 | 6936 | } |
e70236a8 JB |
6937 | } |
6938 | } | |
6939 | ||
6940 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6941 | { | |
e907f170 | 6942 | return 266667; |
e70236a8 JB |
6943 | } |
6944 | ||
1b1d2716 | 6945 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6946 | { |
6947 | u16 hpllcc = 0; | |
1b1d2716 | 6948 | |
65cd2b3f VS |
6949 | /* |
6950 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6951 | * encoding is different :( | |
6952 | * FIXME is this the right way to detect 852GM/852GMV? | |
6953 | */ | |
6954 | if (dev->pdev->revision == 0x1) | |
6955 | return 133333; | |
6956 | ||
1b1d2716 VS |
6957 | pci_bus_read_config_word(dev->pdev->bus, |
6958 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6959 | ||
e70236a8 JB |
6960 | /* Assume that the hardware is in the high speed state. This |
6961 | * should be the default. | |
6962 | */ | |
6963 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6964 | case GC_CLOCK_133_200: | |
1b1d2716 | 6965 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6966 | case GC_CLOCK_100_200: |
6967 | return 200000; | |
6968 | case GC_CLOCK_166_250: | |
6969 | return 250000; | |
6970 | case GC_CLOCK_100_133: | |
e907f170 | 6971 | return 133333; |
1b1d2716 VS |
6972 | case GC_CLOCK_133_266: |
6973 | case GC_CLOCK_133_266_2: | |
6974 | case GC_CLOCK_166_266: | |
6975 | return 266667; | |
e70236a8 | 6976 | } |
79e53945 | 6977 | |
e70236a8 JB |
6978 | /* Shouldn't happen */ |
6979 | return 0; | |
6980 | } | |
79e53945 | 6981 | |
e70236a8 JB |
6982 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6983 | { | |
e907f170 | 6984 | return 133333; |
79e53945 JB |
6985 | } |
6986 | ||
34edce2f VS |
6987 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6988 | { | |
6989 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6990 | static const unsigned int blb_vco[8] = { | |
6991 | [0] = 3200000, | |
6992 | [1] = 4000000, | |
6993 | [2] = 5333333, | |
6994 | [3] = 4800000, | |
6995 | [4] = 6400000, | |
6996 | }; | |
6997 | static const unsigned int pnv_vco[8] = { | |
6998 | [0] = 3200000, | |
6999 | [1] = 4000000, | |
7000 | [2] = 5333333, | |
7001 | [3] = 4800000, | |
7002 | [4] = 2666667, | |
7003 | }; | |
7004 | static const unsigned int cl_vco[8] = { | |
7005 | [0] = 3200000, | |
7006 | [1] = 4000000, | |
7007 | [2] = 5333333, | |
7008 | [3] = 6400000, | |
7009 | [4] = 3333333, | |
7010 | [5] = 3566667, | |
7011 | [6] = 4266667, | |
7012 | }; | |
7013 | static const unsigned int elk_vco[8] = { | |
7014 | [0] = 3200000, | |
7015 | [1] = 4000000, | |
7016 | [2] = 5333333, | |
7017 | [3] = 4800000, | |
7018 | }; | |
7019 | static const unsigned int ctg_vco[8] = { | |
7020 | [0] = 3200000, | |
7021 | [1] = 4000000, | |
7022 | [2] = 5333333, | |
7023 | [3] = 6400000, | |
7024 | [4] = 2666667, | |
7025 | [5] = 4266667, | |
7026 | }; | |
7027 | const unsigned int *vco_table; | |
7028 | unsigned int vco; | |
7029 | uint8_t tmp = 0; | |
7030 | ||
7031 | /* FIXME other chipsets? */ | |
7032 | if (IS_GM45(dev)) | |
7033 | vco_table = ctg_vco; | |
7034 | else if (IS_G4X(dev)) | |
7035 | vco_table = elk_vco; | |
7036 | else if (IS_CRESTLINE(dev)) | |
7037 | vco_table = cl_vco; | |
7038 | else if (IS_PINEVIEW(dev)) | |
7039 | vco_table = pnv_vco; | |
7040 | else if (IS_G33(dev)) | |
7041 | vco_table = blb_vco; | |
7042 | else | |
7043 | return 0; | |
7044 | ||
7045 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7046 | ||
7047 | vco = vco_table[tmp & 0x7]; | |
7048 | if (vco == 0) | |
7049 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7050 | else | |
7051 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7052 | ||
7053 | return vco; | |
7054 | } | |
7055 | ||
7056 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7057 | { | |
7058 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7059 | uint16_t tmp = 0; | |
7060 | ||
7061 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7062 | ||
7063 | cdclk_sel = (tmp >> 12) & 0x1; | |
7064 | ||
7065 | switch (vco) { | |
7066 | case 2666667: | |
7067 | case 4000000: | |
7068 | case 5333333: | |
7069 | return cdclk_sel ? 333333 : 222222; | |
7070 | case 3200000: | |
7071 | return cdclk_sel ? 320000 : 228571; | |
7072 | default: | |
7073 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7074 | return 222222; | |
7075 | } | |
7076 | } | |
7077 | ||
7078 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7079 | { | |
7080 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7081 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7082 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7083 | const uint8_t *div_table; | |
7084 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7085 | uint16_t tmp = 0; | |
7086 | ||
7087 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7088 | ||
7089 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7090 | ||
7091 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7092 | goto fail; | |
7093 | ||
7094 | switch (vco) { | |
7095 | case 3200000: | |
7096 | div_table = div_3200; | |
7097 | break; | |
7098 | case 4000000: | |
7099 | div_table = div_4000; | |
7100 | break; | |
7101 | case 5333333: | |
7102 | div_table = div_5333; | |
7103 | break; | |
7104 | default: | |
7105 | goto fail; | |
7106 | } | |
7107 | ||
7108 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7109 | ||
caf4e252 | 7110 | fail: |
34edce2f VS |
7111 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7112 | return 200000; | |
7113 | } | |
7114 | ||
7115 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7116 | { | |
7117 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7118 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7119 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7120 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7121 | const uint8_t *div_table; | |
7122 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7123 | uint16_t tmp = 0; | |
7124 | ||
7125 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7126 | ||
7127 | cdclk_sel = (tmp >> 4) & 0x7; | |
7128 | ||
7129 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7130 | goto fail; | |
7131 | ||
7132 | switch (vco) { | |
7133 | case 3200000: | |
7134 | div_table = div_3200; | |
7135 | break; | |
7136 | case 4000000: | |
7137 | div_table = div_4000; | |
7138 | break; | |
7139 | case 4800000: | |
7140 | div_table = div_4800; | |
7141 | break; | |
7142 | case 5333333: | |
7143 | div_table = div_5333; | |
7144 | break; | |
7145 | default: | |
7146 | goto fail; | |
7147 | } | |
7148 | ||
7149 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7150 | ||
caf4e252 | 7151 | fail: |
34edce2f VS |
7152 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7153 | return 190476; | |
7154 | } | |
7155 | ||
2c07245f | 7156 | static void |
a65851af | 7157 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7158 | { |
a65851af VS |
7159 | while (*num > DATA_LINK_M_N_MASK || |
7160 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7161 | *num >>= 1; |
7162 | *den >>= 1; | |
7163 | } | |
7164 | } | |
7165 | ||
a65851af VS |
7166 | static void compute_m_n(unsigned int m, unsigned int n, |
7167 | uint32_t *ret_m, uint32_t *ret_n) | |
7168 | { | |
7169 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7170 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7171 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7172 | } | |
7173 | ||
e69d0bc1 DV |
7174 | void |
7175 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7176 | int pixel_clock, int link_clock, | |
7177 | struct intel_link_m_n *m_n) | |
2c07245f | 7178 | { |
e69d0bc1 | 7179 | m_n->tu = 64; |
a65851af VS |
7180 | |
7181 | compute_m_n(bits_per_pixel * pixel_clock, | |
7182 | link_clock * nlanes * 8, | |
7183 | &m_n->gmch_m, &m_n->gmch_n); | |
7184 | ||
7185 | compute_m_n(pixel_clock, link_clock, | |
7186 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7187 | } |
7188 | ||
a7615030 CW |
7189 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7190 | { | |
d330a953 JN |
7191 | if (i915.panel_use_ssc >= 0) |
7192 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7193 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7194 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7195 | } |
7196 | ||
a93e255f ACO |
7197 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7198 | int num_connectors) | |
c65d77d8 | 7199 | { |
a93e255f | 7200 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7201 | struct drm_i915_private *dev_priv = dev->dev_private; |
7202 | int refclk; | |
7203 | ||
a93e255f ACO |
7204 | WARN_ON(!crtc_state->base.state); |
7205 | ||
666a4537 | 7206 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7207 | refclk = 100000; |
a93e255f | 7208 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7209 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7210 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7211 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7212 | } else if (!IS_GEN2(dev)) { |
7213 | refclk = 96000; | |
7214 | } else { | |
7215 | refclk = 48000; | |
7216 | } | |
7217 | ||
7218 | return refclk; | |
7219 | } | |
7220 | ||
7429e9d4 | 7221 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7222 | { |
7df00d7a | 7223 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7224 | } |
f47709a9 | 7225 | |
7429e9d4 DV |
7226 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7227 | { | |
7228 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7229 | } |
7230 | ||
f47709a9 | 7231 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7232 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7233 | intel_clock_t *reduced_clock) |
7234 | { | |
f47709a9 | 7235 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7236 | u32 fp, fp2 = 0; |
7237 | ||
7238 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7239 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7240 | if (reduced_clock) |
7429e9d4 | 7241 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7242 | } else { |
190f68c5 | 7243 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7244 | if (reduced_clock) |
7429e9d4 | 7245 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7246 | } |
7247 | ||
190f68c5 | 7248 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7249 | |
f47709a9 | 7250 | crtc->lowfreq_avail = false; |
a93e255f | 7251 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7252 | reduced_clock) { |
190f68c5 | 7253 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7254 | crtc->lowfreq_avail = true; |
a7516a05 | 7255 | } else { |
190f68c5 | 7256 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7257 | } |
7258 | } | |
7259 | ||
5e69f97f CML |
7260 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7261 | pipe) | |
89b667f8 JB |
7262 | { |
7263 | u32 reg_val; | |
7264 | ||
7265 | /* | |
7266 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7267 | * and set it to a reasonable value instead. | |
7268 | */ | |
ab3c759a | 7269 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7270 | reg_val &= 0xffffff00; |
7271 | reg_val |= 0x00000030; | |
ab3c759a | 7272 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7273 | |
ab3c759a | 7274 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7275 | reg_val &= 0x8cffffff; |
7276 | reg_val = 0x8c000000; | |
ab3c759a | 7277 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7278 | |
ab3c759a | 7279 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7280 | reg_val &= 0xffffff00; |
ab3c759a | 7281 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7282 | |
ab3c759a | 7283 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7284 | reg_val &= 0x00ffffff; |
7285 | reg_val |= 0xb0000000; | |
ab3c759a | 7286 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7287 | } |
7288 | ||
b551842d DV |
7289 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7290 | struct intel_link_m_n *m_n) | |
7291 | { | |
7292 | struct drm_device *dev = crtc->base.dev; | |
7293 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7294 | int pipe = crtc->pipe; | |
7295 | ||
e3b95f1e DV |
7296 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7297 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7298 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7299 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7300 | } |
7301 | ||
7302 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7303 | struct intel_link_m_n *m_n, |
7304 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7305 | { |
7306 | struct drm_device *dev = crtc->base.dev; | |
7307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7308 | int pipe = crtc->pipe; | |
6e3c9717 | 7309 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7310 | |
7311 | if (INTEL_INFO(dev)->gen >= 5) { | |
7312 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7313 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7314 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7315 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7316 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7317 | * for gen < 8) and if DRRS is supported (to make sure the | |
7318 | * registers are not unnecessarily accessed). | |
7319 | */ | |
44395bfe | 7320 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7321 | crtc->config->has_drrs) { |
f769cd24 VK |
7322 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7323 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7324 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7325 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7326 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7327 | } | |
b551842d | 7328 | } else { |
e3b95f1e DV |
7329 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7330 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7331 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7332 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7333 | } |
7334 | } | |
7335 | ||
fe3cd48d | 7336 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7337 | { |
fe3cd48d R |
7338 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7339 | ||
7340 | if (m_n == M1_N1) { | |
7341 | dp_m_n = &crtc->config->dp_m_n; | |
7342 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7343 | } else if (m_n == M2_N2) { | |
7344 | ||
7345 | /* | |
7346 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7347 | * needs to be programmed into M1_N1. | |
7348 | */ | |
7349 | dp_m_n = &crtc->config->dp_m2_n2; | |
7350 | } else { | |
7351 | DRM_ERROR("Unsupported divider value\n"); | |
7352 | return; | |
7353 | } | |
7354 | ||
6e3c9717 ACO |
7355 | if (crtc->config->has_pch_encoder) |
7356 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7357 | else |
fe3cd48d | 7358 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7359 | } |
7360 | ||
251ac862 DV |
7361 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7362 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7363 | { |
7364 | u32 dpll, dpll_md; | |
7365 | ||
7366 | /* | |
7367 | * Enable DPIO clock input. We should never disable the reference | |
7368 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7369 | * on it. | |
7370 | */ | |
60bfe44f VS |
7371 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7372 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7373 | /* We should never disable this, set it here for state tracking */ |
7374 | if (crtc->pipe == PIPE_B) | |
7375 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7376 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7377 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7378 | |
d288f65f | 7379 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7380 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7381 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7382 | } |
7383 | ||
d288f65f | 7384 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7385 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7386 | { |
f47709a9 | 7387 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7388 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7389 | int pipe = crtc->pipe; |
bdd4b6a6 | 7390 | u32 mdiv; |
a0c4da24 | 7391 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7392 | u32 coreclk, reg_val; |
a0c4da24 | 7393 | |
a580516d | 7394 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7395 | |
d288f65f VS |
7396 | bestn = pipe_config->dpll.n; |
7397 | bestm1 = pipe_config->dpll.m1; | |
7398 | bestm2 = pipe_config->dpll.m2; | |
7399 | bestp1 = pipe_config->dpll.p1; | |
7400 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7401 | |
89b667f8 JB |
7402 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7403 | ||
7404 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7405 | if (pipe == PIPE_B) |
5e69f97f | 7406 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7407 | |
7408 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7409 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7410 | |
7411 | /* Disable target IRef on PLL */ | |
ab3c759a | 7412 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7413 | reg_val &= 0x00ffffff; |
ab3c759a | 7414 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7415 | |
7416 | /* Disable fast lock */ | |
ab3c759a | 7417 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7418 | |
7419 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7420 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7421 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7422 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7423 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7424 | |
7425 | /* | |
7426 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7427 | * but we don't support that). | |
7428 | * Note: don't use the DAC post divider as it seems unstable. | |
7429 | */ | |
7430 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7431 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7432 | |
a0c4da24 | 7433 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7434 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7435 | |
89b667f8 | 7436 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7437 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7438 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7439 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7440 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7441 | 0x009f0003); |
89b667f8 | 7442 | else |
ab3c759a | 7443 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7444 | 0x00d0000f); |
7445 | ||
681a8504 | 7446 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7447 | /* Use SSC source */ |
bdd4b6a6 | 7448 | if (pipe == PIPE_A) |
ab3c759a | 7449 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7450 | 0x0df40000); |
7451 | else | |
ab3c759a | 7452 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7453 | 0x0df70000); |
7454 | } else { /* HDMI or VGA */ | |
7455 | /* Use bend source */ | |
bdd4b6a6 | 7456 | if (pipe == PIPE_A) |
ab3c759a | 7457 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7458 | 0x0df70000); |
7459 | else | |
ab3c759a | 7460 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7461 | 0x0df40000); |
7462 | } | |
a0c4da24 | 7463 | |
ab3c759a | 7464 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7465 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7466 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7467 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7468 | coreclk |= 0x01000000; |
ab3c759a | 7469 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7470 | |
ab3c759a | 7471 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7472 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7473 | } |
7474 | ||
251ac862 DV |
7475 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7476 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7477 | { |
60bfe44f VS |
7478 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7479 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7480 | DPLL_VCO_ENABLE; |
7481 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7482 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7483 | |
d288f65f VS |
7484 | pipe_config->dpll_hw_state.dpll_md = |
7485 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7486 | } |
7487 | ||
d288f65f | 7488 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7489 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7490 | { |
7491 | struct drm_device *dev = crtc->base.dev; | |
7492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7493 | int pipe = crtc->pipe; | |
f0f59a00 | 7494 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7495 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7496 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7497 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7498 | u32 dpio_val; |
9cbe40c1 | 7499 | int vco; |
9d556c99 | 7500 | |
d288f65f VS |
7501 | bestn = pipe_config->dpll.n; |
7502 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7503 | bestm1 = pipe_config->dpll.m1; | |
7504 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7505 | bestp1 = pipe_config->dpll.p1; | |
7506 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7507 | vco = pipe_config->dpll.vco; |
a945ce7e | 7508 | dpio_val = 0; |
9cbe40c1 | 7509 | loopfilter = 0; |
9d556c99 CML |
7510 | |
7511 | /* | |
7512 | * Enable Refclk and SSC | |
7513 | */ | |
a11b0703 | 7514 | I915_WRITE(dpll_reg, |
d288f65f | 7515 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7516 | |
a580516d | 7517 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7518 | |
9d556c99 CML |
7519 | /* p1 and p2 divider */ |
7520 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7521 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7522 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7523 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7524 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7525 | ||
7526 | /* Feedback post-divider - m2 */ | |
7527 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7528 | ||
7529 | /* Feedback refclk divider - n and m1 */ | |
7530 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7531 | DPIO_CHV_M1_DIV_BY_2 | | |
7532 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7533 | ||
7534 | /* M2 fraction division */ | |
25a25dfc | 7535 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7536 | |
7537 | /* M2 fraction division enable */ | |
a945ce7e VP |
7538 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7539 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7540 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7541 | if (bestm2_frac) | |
7542 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7543 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7544 | |
de3a0fde VP |
7545 | /* Program digital lock detect threshold */ |
7546 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7547 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7548 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7549 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7550 | if (!bestm2_frac) | |
7551 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7552 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7553 | ||
9d556c99 | 7554 | /* Loop filter */ |
9cbe40c1 VP |
7555 | if (vco == 5400000) { |
7556 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7557 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7558 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7559 | tribuf_calcntr = 0x9; | |
7560 | } else if (vco <= 6200000) { | |
7561 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7562 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7563 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7564 | tribuf_calcntr = 0x9; | |
7565 | } else if (vco <= 6480000) { | |
7566 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7567 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7568 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7569 | tribuf_calcntr = 0x8; | |
7570 | } else { | |
7571 | /* Not supported. Apply the same limits as in the max case */ | |
7572 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7573 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7574 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7575 | tribuf_calcntr = 0; | |
7576 | } | |
9d556c99 CML |
7577 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7578 | ||
968040b2 | 7579 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7580 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7581 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7582 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7583 | ||
9d556c99 CML |
7584 | /* AFC Recal */ |
7585 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7586 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7587 | DPIO_AFC_RECAL); | |
7588 | ||
a580516d | 7589 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7590 | } |
7591 | ||
d288f65f VS |
7592 | /** |
7593 | * vlv_force_pll_on - forcibly enable just the PLL | |
7594 | * @dev_priv: i915 private structure | |
7595 | * @pipe: pipe PLL to enable | |
7596 | * @dpll: PLL configuration | |
7597 | * | |
7598 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7599 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7600 | * be enabled. | |
7601 | */ | |
3f36b937 TU |
7602 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7603 | const struct dpll *dpll) | |
d288f65f VS |
7604 | { |
7605 | struct intel_crtc *crtc = | |
7606 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7607 | struct intel_crtc_state *pipe_config; |
7608 | ||
7609 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7610 | if (!pipe_config) | |
7611 | return -ENOMEM; | |
7612 | ||
7613 | pipe_config->base.crtc = &crtc->base; | |
7614 | pipe_config->pixel_multiplier = 1; | |
7615 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7616 | |
7617 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7618 | chv_compute_dpll(crtc, pipe_config); |
7619 | chv_prepare_pll(crtc, pipe_config); | |
7620 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7621 | } else { |
3f36b937 TU |
7622 | vlv_compute_dpll(crtc, pipe_config); |
7623 | vlv_prepare_pll(crtc, pipe_config); | |
7624 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7625 | } |
3f36b937 TU |
7626 | |
7627 | kfree(pipe_config); | |
7628 | ||
7629 | return 0; | |
d288f65f VS |
7630 | } |
7631 | ||
7632 | /** | |
7633 | * vlv_force_pll_off - forcibly disable just the PLL | |
7634 | * @dev_priv: i915 private structure | |
7635 | * @pipe: pipe PLL to disable | |
7636 | * | |
7637 | * Disable the PLL for @pipe. To be used in cases where we need | |
7638 | * the PLL enabled even when @pipe is not going to be enabled. | |
7639 | */ | |
7640 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7641 | { | |
7642 | if (IS_CHERRYVIEW(dev)) | |
7643 | chv_disable_pll(to_i915(dev), pipe); | |
7644 | else | |
7645 | vlv_disable_pll(to_i915(dev), pipe); | |
7646 | } | |
7647 | ||
251ac862 DV |
7648 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7649 | struct intel_crtc_state *crtc_state, | |
7650 | intel_clock_t *reduced_clock, | |
7651 | int num_connectors) | |
eb1cbe48 | 7652 | { |
f47709a9 | 7653 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7654 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7655 | u32 dpll; |
7656 | bool is_sdvo; | |
190f68c5 | 7657 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7658 | |
190f68c5 | 7659 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7660 | |
a93e255f ACO |
7661 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7662 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7663 | |
7664 | dpll = DPLL_VGA_MODE_DIS; | |
7665 | ||
a93e255f | 7666 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7667 | dpll |= DPLLB_MODE_LVDS; |
7668 | else | |
7669 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7670 | |
ef1b460d | 7671 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7672 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7673 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7674 | } |
198a037f DV |
7675 | |
7676 | if (is_sdvo) | |
4a33e48d | 7677 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7678 | |
190f68c5 | 7679 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7680 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7681 | |
7682 | /* compute bitmask from p1 value */ | |
7683 | if (IS_PINEVIEW(dev)) | |
7684 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7685 | else { | |
7686 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7687 | if (IS_G4X(dev) && reduced_clock) | |
7688 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7689 | } | |
7690 | switch (clock->p2) { | |
7691 | case 5: | |
7692 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7693 | break; | |
7694 | case 7: | |
7695 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7696 | break; | |
7697 | case 10: | |
7698 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7699 | break; | |
7700 | case 14: | |
7701 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7702 | break; | |
7703 | } | |
7704 | if (INTEL_INFO(dev)->gen >= 4) | |
7705 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7706 | ||
190f68c5 | 7707 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7708 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7709 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7710 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7711 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7712 | else | |
7713 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7714 | ||
7715 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7716 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7717 | |
eb1cbe48 | 7718 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7719 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7720 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7721 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7722 | } |
7723 | } | |
7724 | ||
251ac862 DV |
7725 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7726 | struct intel_crtc_state *crtc_state, | |
7727 | intel_clock_t *reduced_clock, | |
7728 | int num_connectors) | |
eb1cbe48 | 7729 | { |
f47709a9 | 7730 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7731 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7732 | u32 dpll; |
190f68c5 | 7733 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7734 | |
190f68c5 | 7735 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7736 | |
eb1cbe48 DV |
7737 | dpll = DPLL_VGA_MODE_DIS; |
7738 | ||
a93e255f | 7739 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7740 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7741 | } else { | |
7742 | if (clock->p1 == 2) | |
7743 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7744 | else | |
7745 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7746 | if (clock->p2 == 4) | |
7747 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7748 | } | |
7749 | ||
a93e255f | 7750 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7751 | dpll |= DPLL_DVO_2X_MODE; |
7752 | ||
a93e255f | 7753 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7754 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7755 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7756 | else | |
7757 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7758 | ||
7759 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7760 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7761 | } |
7762 | ||
8a654f3b | 7763 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7764 | { |
7765 | struct drm_device *dev = intel_crtc->base.dev; | |
7766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7767 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7768 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7769 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7770 | uint32_t crtc_vtotal, crtc_vblank_end; |
7771 | int vsyncshift = 0; | |
4d8a62ea DV |
7772 | |
7773 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7774 | * the hw state checker will get angry at the mismatch. */ | |
7775 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7776 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7777 | |
609aeaca | 7778 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7779 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7780 | crtc_vtotal -= 1; |
7781 | crtc_vblank_end -= 1; | |
609aeaca | 7782 | |
409ee761 | 7783 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7784 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7785 | else | |
7786 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7787 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7788 | if (vsyncshift < 0) |
7789 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7790 | } |
7791 | ||
7792 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7793 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7794 | |
fe2b8f9d | 7795 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7796 | (adjusted_mode->crtc_hdisplay - 1) | |
7797 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7798 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7799 | (adjusted_mode->crtc_hblank_start - 1) | |
7800 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7801 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7802 | (adjusted_mode->crtc_hsync_start - 1) | |
7803 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7804 | ||
fe2b8f9d | 7805 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7806 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7807 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7808 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7809 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7810 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7811 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7812 | (adjusted_mode->crtc_vsync_start - 1) | |
7813 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7814 | ||
b5e508d4 PZ |
7815 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7816 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7817 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7818 | * bits. */ | |
7819 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7820 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7821 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7822 | ||
b0e77b9c PZ |
7823 | /* pipesrc controls the size that is scaled from, which should |
7824 | * always be the user's requested size. | |
7825 | */ | |
7826 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7827 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7828 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7829 | } |
7830 | ||
1bd1bd80 | 7831 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7832 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7833 | { |
7834 | struct drm_device *dev = crtc->base.dev; | |
7835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7836 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7837 | uint32_t tmp; | |
7838 | ||
7839 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7840 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7841 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7842 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7843 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7844 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7845 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7846 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7847 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7848 | |
7849 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7850 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7851 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7852 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7853 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7854 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7855 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7856 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7857 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7858 | |
7859 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7860 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7861 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7862 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7863 | } |
7864 | ||
7865 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7866 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7867 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7868 | ||
2d112de7 ACO |
7869 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7870 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7871 | } |
7872 | ||
f6a83288 | 7873 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7874 | struct intel_crtc_state *pipe_config) |
babea61d | 7875 | { |
2d112de7 ACO |
7876 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7877 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7878 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7879 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7880 | |
2d112de7 ACO |
7881 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7882 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7883 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7884 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7885 | |
2d112de7 | 7886 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7887 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7888 | |
2d112de7 ACO |
7889 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7890 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7891 | |
7892 | mode->hsync = drm_mode_hsync(mode); | |
7893 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7894 | drm_mode_set_name(mode); | |
babea61d JB |
7895 | } |
7896 | ||
84b046f3 DV |
7897 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7898 | { | |
7899 | struct drm_device *dev = intel_crtc->base.dev; | |
7900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7901 | uint32_t pipeconf; | |
7902 | ||
9f11a9e4 | 7903 | pipeconf = 0; |
84b046f3 | 7904 | |
b6b5d049 VS |
7905 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7906 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7907 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7908 | |
6e3c9717 | 7909 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7910 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7911 | |
ff9ce46e | 7912 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7913 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7914 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7915 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7916 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7917 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7918 | |
6e3c9717 | 7919 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7920 | case 18: |
7921 | pipeconf |= PIPECONF_6BPC; | |
7922 | break; | |
7923 | case 24: | |
7924 | pipeconf |= PIPECONF_8BPC; | |
7925 | break; | |
7926 | case 30: | |
7927 | pipeconf |= PIPECONF_10BPC; | |
7928 | break; | |
7929 | default: | |
7930 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7931 | BUG(); | |
84b046f3 DV |
7932 | } |
7933 | } | |
7934 | ||
7935 | if (HAS_PIPE_CXSR(dev)) { | |
7936 | if (intel_crtc->lowfreq_avail) { | |
7937 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7938 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7939 | } else { | |
7940 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7941 | } |
7942 | } | |
7943 | ||
6e3c9717 | 7944 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7945 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7946 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7947 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7948 | else | |
7949 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7950 | } else | |
84b046f3 DV |
7951 | pipeconf |= PIPECONF_PROGRESSIVE; |
7952 | ||
666a4537 WB |
7953 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7954 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7955 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7956 | |
84b046f3 DV |
7957 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7958 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7959 | } | |
7960 | ||
190f68c5 ACO |
7961 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7962 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7963 | { |
c7653199 | 7964 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7965 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7966 | int refclk, num_connectors = 0; |
c329a4ec DV |
7967 | intel_clock_t clock; |
7968 | bool ok; | |
d4906093 | 7969 | const intel_limit_t *limit; |
55bb9992 | 7970 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7971 | struct drm_connector *connector; |
55bb9992 ACO |
7972 | struct drm_connector_state *connector_state; |
7973 | int i; | |
79e53945 | 7974 | |
dd3cd74a ACO |
7975 | memset(&crtc_state->dpll_hw_state, 0, |
7976 | sizeof(crtc_state->dpll_hw_state)); | |
7977 | ||
a65347ba JN |
7978 | if (crtc_state->has_dsi_encoder) |
7979 | return 0; | |
43565a06 | 7980 | |
a65347ba JN |
7981 | for_each_connector_in_state(state, connector, connector_state, i) { |
7982 | if (connector_state->crtc == &crtc->base) | |
7983 | num_connectors++; | |
79e53945 JB |
7984 | } |
7985 | ||
190f68c5 | 7986 | if (!crtc_state->clock_set) { |
a93e255f | 7987 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7988 | |
e9fd1c02 JN |
7989 | /* |
7990 | * Returns a set of divisors for the desired target clock with | |
7991 | * the given refclk, or FALSE. The returned values represent | |
7992 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7993 | * 2) / p1 / p2. | |
7994 | */ | |
a93e255f ACO |
7995 | limit = intel_limit(crtc_state, refclk); |
7996 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7997 | crtc_state->port_clock, |
e9fd1c02 | 7998 | refclk, NULL, &clock); |
f2335330 | 7999 | if (!ok) { |
e9fd1c02 JN |
8000 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8001 | return -EINVAL; | |
8002 | } | |
79e53945 | 8003 | |
f2335330 | 8004 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8005 | crtc_state->dpll.n = clock.n; |
8006 | crtc_state->dpll.m1 = clock.m1; | |
8007 | crtc_state->dpll.m2 = clock.m2; | |
8008 | crtc_state->dpll.p1 = clock.p1; | |
8009 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8010 | } |
7026d4ac | 8011 | |
e9fd1c02 | 8012 | if (IS_GEN2(dev)) { |
c329a4ec | 8013 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8014 | num_connectors); |
9d556c99 | 8015 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 8016 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8017 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 8018 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8019 | } else { |
c329a4ec | 8020 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8021 | num_connectors); |
e9fd1c02 | 8022 | } |
79e53945 | 8023 | |
c8f7a0db | 8024 | return 0; |
f564048e EA |
8025 | } |
8026 | ||
2fa2fe9a | 8027 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8028 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8029 | { |
8030 | struct drm_device *dev = crtc->base.dev; | |
8031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8032 | uint32_t tmp; | |
8033 | ||
dc9e7dec VS |
8034 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8035 | return; | |
8036 | ||
2fa2fe9a | 8037 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8038 | if (!(tmp & PFIT_ENABLE)) |
8039 | return; | |
2fa2fe9a | 8040 | |
06922821 | 8041 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8042 | if (INTEL_INFO(dev)->gen < 4) { |
8043 | if (crtc->pipe != PIPE_B) | |
8044 | return; | |
2fa2fe9a DV |
8045 | } else { |
8046 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8047 | return; | |
8048 | } | |
8049 | ||
06922821 | 8050 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8051 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8052 | if (INTEL_INFO(dev)->gen < 5) | |
8053 | pipe_config->gmch_pfit.lvds_border_bits = | |
8054 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8055 | } | |
8056 | ||
acbec814 | 8057 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8058 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8059 | { |
8060 | struct drm_device *dev = crtc->base.dev; | |
8061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8062 | int pipe = pipe_config->cpu_transcoder; | |
8063 | intel_clock_t clock; | |
8064 | u32 mdiv; | |
662c6ecb | 8065 | int refclk = 100000; |
acbec814 | 8066 | |
f573de5a SK |
8067 | /* In case of MIPI DPLL will not even be used */ |
8068 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8069 | return; | |
8070 | ||
a580516d | 8071 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8072 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8073 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8074 | |
8075 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8076 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8077 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8078 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8079 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8080 | ||
dccbea3b | 8081 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8082 | } |
8083 | ||
5724dbd1 DL |
8084 | static void |
8085 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8086 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8087 | { |
8088 | struct drm_device *dev = crtc->base.dev; | |
8089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8090 | u32 val, base, offset; | |
8091 | int pipe = crtc->pipe, plane = crtc->plane; | |
8092 | int fourcc, pixel_format; | |
6761dd31 | 8093 | unsigned int aligned_height; |
b113d5ee | 8094 | struct drm_framebuffer *fb; |
1b842c89 | 8095 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8096 | |
42a7b088 DL |
8097 | val = I915_READ(DSPCNTR(plane)); |
8098 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8099 | return; | |
8100 | ||
d9806c9f | 8101 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8102 | if (!intel_fb) { |
1ad292b5 JB |
8103 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8104 | return; | |
8105 | } | |
8106 | ||
1b842c89 DL |
8107 | fb = &intel_fb->base; |
8108 | ||
18c5247e DV |
8109 | if (INTEL_INFO(dev)->gen >= 4) { |
8110 | if (val & DISPPLANE_TILED) { | |
49af449b | 8111 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8112 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8113 | } | |
8114 | } | |
1ad292b5 JB |
8115 | |
8116 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8117 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8118 | fb->pixel_format = fourcc; |
8119 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8120 | |
8121 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8122 | if (plane_config->tiling) |
1ad292b5 JB |
8123 | offset = I915_READ(DSPTILEOFF(plane)); |
8124 | else | |
8125 | offset = I915_READ(DSPLINOFF(plane)); | |
8126 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8127 | } else { | |
8128 | base = I915_READ(DSPADDR(plane)); | |
8129 | } | |
8130 | plane_config->base = base; | |
8131 | ||
8132 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8133 | fb->width = ((val >> 16) & 0xfff) + 1; |
8134 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8135 | |
8136 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8137 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8138 | |
b113d5ee | 8139 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8140 | fb->pixel_format, |
8141 | fb->modifier[0]); | |
1ad292b5 | 8142 | |
f37b5c2b | 8143 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8144 | |
2844a921 DL |
8145 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8146 | pipe_name(pipe), plane, fb->width, fb->height, | |
8147 | fb->bits_per_pixel, base, fb->pitches[0], | |
8148 | plane_config->size); | |
1ad292b5 | 8149 | |
2d14030b | 8150 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8151 | } |
8152 | ||
70b23a98 | 8153 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8154 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8155 | { |
8156 | struct drm_device *dev = crtc->base.dev; | |
8157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8158 | int pipe = pipe_config->cpu_transcoder; | |
8159 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8160 | intel_clock_t clock; | |
0d7b6b11 | 8161 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8162 | int refclk = 100000; |
8163 | ||
a580516d | 8164 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8165 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8166 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8167 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8168 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8169 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8170 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8171 | |
8172 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8173 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8174 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8175 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8176 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8177 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8178 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8179 | ||
dccbea3b | 8180 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8181 | } |
8182 | ||
0e8ffe1b | 8183 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8184 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8185 | { |
8186 | struct drm_device *dev = crtc->base.dev; | |
8187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8188 | uint32_t tmp; | |
8189 | ||
f458ebbc DV |
8190 | if (!intel_display_power_is_enabled(dev_priv, |
8191 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8192 | return false; |
8193 | ||
e143a21c | 8194 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8195 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8196 | |
0e8ffe1b DV |
8197 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8198 | if (!(tmp & PIPECONF_ENABLE)) | |
8199 | return false; | |
8200 | ||
666a4537 | 8201 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8202 | switch (tmp & PIPECONF_BPC_MASK) { |
8203 | case PIPECONF_6BPC: | |
8204 | pipe_config->pipe_bpp = 18; | |
8205 | break; | |
8206 | case PIPECONF_8BPC: | |
8207 | pipe_config->pipe_bpp = 24; | |
8208 | break; | |
8209 | case PIPECONF_10BPC: | |
8210 | pipe_config->pipe_bpp = 30; | |
8211 | break; | |
8212 | default: | |
8213 | break; | |
8214 | } | |
8215 | } | |
8216 | ||
666a4537 WB |
8217 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8218 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8219 | pipe_config->limited_color_range = true; |
8220 | ||
282740f7 VS |
8221 | if (INTEL_INFO(dev)->gen < 4) |
8222 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8223 | ||
1bd1bd80 DV |
8224 | intel_get_pipe_timings(crtc, pipe_config); |
8225 | ||
2fa2fe9a DV |
8226 | i9xx_get_pfit_config(crtc, pipe_config); |
8227 | ||
6c49f241 DV |
8228 | if (INTEL_INFO(dev)->gen >= 4) { |
8229 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8230 | pipe_config->pixel_multiplier = | |
8231 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8232 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8233 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8234 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8235 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8236 | pipe_config->pixel_multiplier = | |
8237 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8238 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8239 | } else { | |
8240 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8241 | * port and will be fixed up in the encoder->get_config | |
8242 | * function. */ | |
8243 | pipe_config->pixel_multiplier = 1; | |
8244 | } | |
8bcc2795 | 8245 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8246 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8247 | /* |
8248 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8249 | * on 830. Filter it out here so that we don't | |
8250 | * report errors due to that. | |
8251 | */ | |
8252 | if (IS_I830(dev)) | |
8253 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8254 | ||
8bcc2795 DV |
8255 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8256 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8257 | } else { |
8258 | /* Mask out read-only status bits. */ | |
8259 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8260 | DPLL_PORTC_READY_MASK | | |
8261 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8262 | } |
6c49f241 | 8263 | |
70b23a98 VS |
8264 | if (IS_CHERRYVIEW(dev)) |
8265 | chv_crtc_clock_get(crtc, pipe_config); | |
8266 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8267 | vlv_crtc_clock_get(crtc, pipe_config); |
8268 | else | |
8269 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8270 | |
0f64614d VS |
8271 | /* |
8272 | * Normally the dotclock is filled in by the encoder .get_config() | |
8273 | * but in case the pipe is enabled w/o any ports we need a sane | |
8274 | * default. | |
8275 | */ | |
8276 | pipe_config->base.adjusted_mode.crtc_clock = | |
8277 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8278 | ||
0e8ffe1b DV |
8279 | return true; |
8280 | } | |
8281 | ||
dde86e2d | 8282 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8283 | { |
8284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8285 | struct intel_encoder *encoder; |
74cfd7ac | 8286 | u32 val, final; |
13d83a67 | 8287 | bool has_lvds = false; |
199e5d79 | 8288 | bool has_cpu_edp = false; |
199e5d79 | 8289 | bool has_panel = false; |
99eb6a01 KP |
8290 | bool has_ck505 = false; |
8291 | bool can_ssc = false; | |
13d83a67 JB |
8292 | |
8293 | /* We need to take the global config into account */ | |
b2784e15 | 8294 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8295 | switch (encoder->type) { |
8296 | case INTEL_OUTPUT_LVDS: | |
8297 | has_panel = true; | |
8298 | has_lvds = true; | |
8299 | break; | |
8300 | case INTEL_OUTPUT_EDP: | |
8301 | has_panel = true; | |
2de6905f | 8302 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8303 | has_cpu_edp = true; |
8304 | break; | |
6847d71b PZ |
8305 | default: |
8306 | break; | |
13d83a67 JB |
8307 | } |
8308 | } | |
8309 | ||
99eb6a01 | 8310 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8311 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8312 | can_ssc = has_ck505; |
8313 | } else { | |
8314 | has_ck505 = false; | |
8315 | can_ssc = true; | |
8316 | } | |
8317 | ||
2de6905f ID |
8318 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8319 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8320 | |
8321 | /* Ironlake: try to setup display ref clock before DPLL | |
8322 | * enabling. This is only under driver's control after | |
8323 | * PCH B stepping, previous chipset stepping should be | |
8324 | * ignoring this setting. | |
8325 | */ | |
74cfd7ac CW |
8326 | val = I915_READ(PCH_DREF_CONTROL); |
8327 | ||
8328 | /* As we must carefully and slowly disable/enable each source in turn, | |
8329 | * compute the final state we want first and check if we need to | |
8330 | * make any changes at all. | |
8331 | */ | |
8332 | final = val; | |
8333 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8334 | if (has_ck505) | |
8335 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8336 | else | |
8337 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8338 | ||
8339 | final &= ~DREF_SSC_SOURCE_MASK; | |
8340 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8341 | final &= ~DREF_SSC1_ENABLE; | |
8342 | ||
8343 | if (has_panel) { | |
8344 | final |= DREF_SSC_SOURCE_ENABLE; | |
8345 | ||
8346 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8347 | final |= DREF_SSC1_ENABLE; | |
8348 | ||
8349 | if (has_cpu_edp) { | |
8350 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8351 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8352 | else | |
8353 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8354 | } else | |
8355 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8356 | } else { | |
8357 | final |= DREF_SSC_SOURCE_DISABLE; | |
8358 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8359 | } | |
8360 | ||
8361 | if (final == val) | |
8362 | return; | |
8363 | ||
13d83a67 | 8364 | /* Always enable nonspread source */ |
74cfd7ac | 8365 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8366 | |
99eb6a01 | 8367 | if (has_ck505) |
74cfd7ac | 8368 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8369 | else |
74cfd7ac | 8370 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8371 | |
199e5d79 | 8372 | if (has_panel) { |
74cfd7ac CW |
8373 | val &= ~DREF_SSC_SOURCE_MASK; |
8374 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8375 | |
199e5d79 | 8376 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8377 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8378 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8379 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8380 | } else |
74cfd7ac | 8381 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8382 | |
8383 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8384 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8385 | POSTING_READ(PCH_DREF_CONTROL); |
8386 | udelay(200); | |
8387 | ||
74cfd7ac | 8388 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8389 | |
8390 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8391 | if (has_cpu_edp) { |
99eb6a01 | 8392 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8393 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8394 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8395 | } else |
74cfd7ac | 8396 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8397 | } else |
74cfd7ac | 8398 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8399 | |
74cfd7ac | 8400 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8401 | POSTING_READ(PCH_DREF_CONTROL); |
8402 | udelay(200); | |
8403 | } else { | |
8404 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8405 | ||
74cfd7ac | 8406 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8407 | |
8408 | /* Turn off CPU output */ | |
74cfd7ac | 8409 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8410 | |
74cfd7ac | 8411 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8412 | POSTING_READ(PCH_DREF_CONTROL); |
8413 | udelay(200); | |
8414 | ||
8415 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8416 | val &= ~DREF_SSC_SOURCE_MASK; |
8417 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8418 | |
8419 | /* Turn off SSC1 */ | |
74cfd7ac | 8420 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8421 | |
74cfd7ac | 8422 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8423 | POSTING_READ(PCH_DREF_CONTROL); |
8424 | udelay(200); | |
8425 | } | |
74cfd7ac CW |
8426 | |
8427 | BUG_ON(val != final); | |
13d83a67 JB |
8428 | } |
8429 | ||
f31f2d55 | 8430 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8431 | { |
f31f2d55 | 8432 | uint32_t tmp; |
dde86e2d | 8433 | |
0ff066a9 PZ |
8434 | tmp = I915_READ(SOUTH_CHICKEN2); |
8435 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8436 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8437 | |
0ff066a9 PZ |
8438 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8439 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8440 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8441 | |
0ff066a9 PZ |
8442 | tmp = I915_READ(SOUTH_CHICKEN2); |
8443 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8444 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8445 | |
0ff066a9 PZ |
8446 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8447 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8448 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8449 | } |
8450 | ||
8451 | /* WaMPhyProgramming:hsw */ | |
8452 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8453 | { | |
8454 | uint32_t tmp; | |
dde86e2d PZ |
8455 | |
8456 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8457 | tmp &= ~(0xFF << 24); | |
8458 | tmp |= (0x12 << 24); | |
8459 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8460 | ||
dde86e2d PZ |
8461 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8462 | tmp |= (1 << 11); | |
8463 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8464 | ||
8465 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8466 | tmp |= (1 << 11); | |
8467 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8468 | ||
dde86e2d PZ |
8469 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8470 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8471 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8472 | ||
8473 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8474 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8475 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8476 | ||
0ff066a9 PZ |
8477 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8478 | tmp &= ~(7 << 13); | |
8479 | tmp |= (5 << 13); | |
8480 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8481 | |
0ff066a9 PZ |
8482 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8483 | tmp &= ~(7 << 13); | |
8484 | tmp |= (5 << 13); | |
8485 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8486 | |
8487 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8488 | tmp &= ~0xFF; | |
8489 | tmp |= 0x1C; | |
8490 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8491 | ||
8492 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8493 | tmp &= ~0xFF; | |
8494 | tmp |= 0x1C; | |
8495 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8496 | ||
8497 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8498 | tmp &= ~(0xFF << 16); | |
8499 | tmp |= (0x1C << 16); | |
8500 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8501 | ||
8502 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8503 | tmp &= ~(0xFF << 16); | |
8504 | tmp |= (0x1C << 16); | |
8505 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8506 | ||
0ff066a9 PZ |
8507 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8508 | tmp |= (1 << 27); | |
8509 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8510 | |
0ff066a9 PZ |
8511 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8512 | tmp |= (1 << 27); | |
8513 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8514 | |
0ff066a9 PZ |
8515 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8516 | tmp &= ~(0xF << 28); | |
8517 | tmp |= (4 << 28); | |
8518 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8519 | |
0ff066a9 PZ |
8520 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8521 | tmp &= ~(0xF << 28); | |
8522 | tmp |= (4 << 28); | |
8523 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8524 | } |
8525 | ||
2fa86a1f PZ |
8526 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8527 | * Programming" based on the parameters passed: | |
8528 | * - Sequence to enable CLKOUT_DP | |
8529 | * - Sequence to enable CLKOUT_DP without spread | |
8530 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8531 | */ | |
8532 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8533 | bool with_fdi) | |
f31f2d55 PZ |
8534 | { |
8535 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8536 | uint32_t reg, tmp; |
8537 | ||
8538 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8539 | with_spread = true; | |
c2699524 | 8540 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8541 | with_fdi = false; |
f31f2d55 | 8542 | |
a580516d | 8543 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8544 | |
8545 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8546 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8547 | tmp |= SBI_SSCCTL_PATHALT; | |
8548 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8549 | ||
8550 | udelay(24); | |
8551 | ||
2fa86a1f PZ |
8552 | if (with_spread) { |
8553 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8554 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8555 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8556 | |
2fa86a1f PZ |
8557 | if (with_fdi) { |
8558 | lpt_reset_fdi_mphy(dev_priv); | |
8559 | lpt_program_fdi_mphy(dev_priv); | |
8560 | } | |
8561 | } | |
dde86e2d | 8562 | |
c2699524 | 8563 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8564 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8565 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8566 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8567 | |
a580516d | 8568 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8569 | } |
8570 | ||
47701c3b PZ |
8571 | /* Sequence to disable CLKOUT_DP */ |
8572 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8573 | { | |
8574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8575 | uint32_t reg, tmp; | |
8576 | ||
a580516d | 8577 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8578 | |
c2699524 | 8579 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8580 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8581 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8582 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8583 | ||
8584 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8585 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8586 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8587 | tmp |= SBI_SSCCTL_PATHALT; | |
8588 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8589 | udelay(32); | |
8590 | } | |
8591 | tmp |= SBI_SSCCTL_DISABLE; | |
8592 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8593 | } | |
8594 | ||
a580516d | 8595 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8596 | } |
8597 | ||
f7be2c21 VS |
8598 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8599 | ||
8600 | static const uint16_t sscdivintphase[] = { | |
8601 | [BEND_IDX( 50)] = 0x3B23, | |
8602 | [BEND_IDX( 45)] = 0x3B23, | |
8603 | [BEND_IDX( 40)] = 0x3C23, | |
8604 | [BEND_IDX( 35)] = 0x3C23, | |
8605 | [BEND_IDX( 30)] = 0x3D23, | |
8606 | [BEND_IDX( 25)] = 0x3D23, | |
8607 | [BEND_IDX( 20)] = 0x3E23, | |
8608 | [BEND_IDX( 15)] = 0x3E23, | |
8609 | [BEND_IDX( 10)] = 0x3F23, | |
8610 | [BEND_IDX( 5)] = 0x3F23, | |
8611 | [BEND_IDX( 0)] = 0x0025, | |
8612 | [BEND_IDX( -5)] = 0x0025, | |
8613 | [BEND_IDX(-10)] = 0x0125, | |
8614 | [BEND_IDX(-15)] = 0x0125, | |
8615 | [BEND_IDX(-20)] = 0x0225, | |
8616 | [BEND_IDX(-25)] = 0x0225, | |
8617 | [BEND_IDX(-30)] = 0x0325, | |
8618 | [BEND_IDX(-35)] = 0x0325, | |
8619 | [BEND_IDX(-40)] = 0x0425, | |
8620 | [BEND_IDX(-45)] = 0x0425, | |
8621 | [BEND_IDX(-50)] = 0x0525, | |
8622 | }; | |
8623 | ||
8624 | /* | |
8625 | * Bend CLKOUT_DP | |
8626 | * steps -50 to 50 inclusive, in steps of 5 | |
8627 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8628 | * change in clock period = -(steps / 10) * 5.787 ps | |
8629 | */ | |
8630 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8631 | { | |
8632 | uint32_t tmp; | |
8633 | int idx = BEND_IDX(steps); | |
8634 | ||
8635 | if (WARN_ON(steps % 5 != 0)) | |
8636 | return; | |
8637 | ||
8638 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8639 | return; | |
8640 | ||
8641 | mutex_lock(&dev_priv->sb_lock); | |
8642 | ||
8643 | if (steps % 10 != 0) | |
8644 | tmp = 0xAAAAAAAB; | |
8645 | else | |
8646 | tmp = 0x00000000; | |
8647 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8648 | ||
8649 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8650 | tmp &= 0xffff0000; | |
8651 | tmp |= sscdivintphase[idx]; | |
8652 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8653 | ||
8654 | mutex_unlock(&dev_priv->sb_lock); | |
8655 | } | |
8656 | ||
8657 | #undef BEND_IDX | |
8658 | ||
bf8fa3d3 PZ |
8659 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8660 | { | |
bf8fa3d3 PZ |
8661 | struct intel_encoder *encoder; |
8662 | bool has_vga = false; | |
8663 | ||
b2784e15 | 8664 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8665 | switch (encoder->type) { |
8666 | case INTEL_OUTPUT_ANALOG: | |
8667 | has_vga = true; | |
8668 | break; | |
6847d71b PZ |
8669 | default: |
8670 | break; | |
bf8fa3d3 PZ |
8671 | } |
8672 | } | |
8673 | ||
f7be2c21 VS |
8674 | if (has_vga) { |
8675 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8676 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8677 | } else { |
47701c3b | 8678 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8679 | } |
bf8fa3d3 PZ |
8680 | } |
8681 | ||
dde86e2d PZ |
8682 | /* |
8683 | * Initialize reference clocks when the driver loads | |
8684 | */ | |
8685 | void intel_init_pch_refclk(struct drm_device *dev) | |
8686 | { | |
8687 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8688 | ironlake_init_pch_refclk(dev); | |
8689 | else if (HAS_PCH_LPT(dev)) | |
8690 | lpt_init_pch_refclk(dev); | |
8691 | } | |
8692 | ||
55bb9992 | 8693 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8694 | { |
55bb9992 | 8695 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8696 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8697 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8698 | struct drm_connector *connector; |
55bb9992 | 8699 | struct drm_connector_state *connector_state; |
d9d444cb | 8700 | struct intel_encoder *encoder; |
55bb9992 | 8701 | int num_connectors = 0, i; |
d9d444cb JB |
8702 | bool is_lvds = false; |
8703 | ||
da3ced29 | 8704 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8705 | if (connector_state->crtc != crtc_state->base.crtc) |
8706 | continue; | |
8707 | ||
8708 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8709 | ||
d9d444cb JB |
8710 | switch (encoder->type) { |
8711 | case INTEL_OUTPUT_LVDS: | |
8712 | is_lvds = true; | |
8713 | break; | |
6847d71b PZ |
8714 | default: |
8715 | break; | |
d9d444cb JB |
8716 | } |
8717 | num_connectors++; | |
8718 | } | |
8719 | ||
8720 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8721 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8722 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8723 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8724 | } |
8725 | ||
8726 | return 120000; | |
8727 | } | |
8728 | ||
6ff93609 | 8729 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8730 | { |
c8203565 | 8731 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8732 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8733 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8734 | uint32_t val; |
8735 | ||
78114071 | 8736 | val = 0; |
c8203565 | 8737 | |
6e3c9717 | 8738 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8739 | case 18: |
dfd07d72 | 8740 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8741 | break; |
8742 | case 24: | |
dfd07d72 | 8743 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8744 | break; |
8745 | case 30: | |
dfd07d72 | 8746 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8747 | break; |
8748 | case 36: | |
dfd07d72 | 8749 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8750 | break; |
8751 | default: | |
cc769b62 PZ |
8752 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8753 | BUG(); | |
c8203565 PZ |
8754 | } |
8755 | ||
6e3c9717 | 8756 | if (intel_crtc->config->dither) |
c8203565 PZ |
8757 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8758 | ||
6e3c9717 | 8759 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8760 | val |= PIPECONF_INTERLACED_ILK; |
8761 | else | |
8762 | val |= PIPECONF_PROGRESSIVE; | |
8763 | ||
6e3c9717 | 8764 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8765 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8766 | |
c8203565 PZ |
8767 | I915_WRITE(PIPECONF(pipe), val); |
8768 | POSTING_READ(PIPECONF(pipe)); | |
8769 | } | |
8770 | ||
86d3efce VS |
8771 | /* |
8772 | * Set up the pipe CSC unit. | |
8773 | * | |
8774 | * Currently only full range RGB to limited range RGB conversion | |
8775 | * is supported, but eventually this should handle various | |
8776 | * RGB<->YCbCr scenarios as well. | |
8777 | */ | |
50f3b016 | 8778 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8779 | { |
8780 | struct drm_device *dev = crtc->dev; | |
8781 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8782 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8783 | int pipe = intel_crtc->pipe; | |
8784 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8785 | ||
8786 | /* | |
8787 | * TODO: Check what kind of values actually come out of the pipe | |
8788 | * with these coeff/postoff values and adjust to get the best | |
8789 | * accuracy. Perhaps we even need to take the bpc value into | |
8790 | * consideration. | |
8791 | */ | |
8792 | ||
6e3c9717 | 8793 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8794 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8795 | ||
8796 | /* | |
8797 | * GY/GU and RY/RU should be the other way around according | |
8798 | * to BSpec, but reality doesn't agree. Just set them up in | |
8799 | * a way that results in the correct picture. | |
8800 | */ | |
8801 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8802 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8803 | ||
8804 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8805 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8806 | ||
8807 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8808 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8809 | ||
8810 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8811 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8812 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8813 | ||
8814 | if (INTEL_INFO(dev)->gen > 6) { | |
8815 | uint16_t postoff = 0; | |
8816 | ||
6e3c9717 | 8817 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8818 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8819 | |
8820 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8821 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8822 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8823 | ||
8824 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8825 | } else { | |
8826 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8827 | ||
6e3c9717 | 8828 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8829 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8830 | ||
8831 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8832 | } | |
8833 | } | |
8834 | ||
6ff93609 | 8835 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8836 | { |
756f85cf PZ |
8837 | struct drm_device *dev = crtc->dev; |
8838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8839 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8840 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8841 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8842 | uint32_t val; |
8843 | ||
3eff4faa | 8844 | val = 0; |
ee2b0b38 | 8845 | |
6e3c9717 | 8846 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8847 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8848 | ||
6e3c9717 | 8849 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8850 | val |= PIPECONF_INTERLACED_ILK; |
8851 | else | |
8852 | val |= PIPECONF_PROGRESSIVE; | |
8853 | ||
702e7a56 PZ |
8854 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8855 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8856 | |
8857 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8858 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8859 | |
3cdf122c | 8860 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8861 | val = 0; |
8862 | ||
6e3c9717 | 8863 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8864 | case 18: |
8865 | val |= PIPEMISC_DITHER_6_BPC; | |
8866 | break; | |
8867 | case 24: | |
8868 | val |= PIPEMISC_DITHER_8_BPC; | |
8869 | break; | |
8870 | case 30: | |
8871 | val |= PIPEMISC_DITHER_10_BPC; | |
8872 | break; | |
8873 | case 36: | |
8874 | val |= PIPEMISC_DITHER_12_BPC; | |
8875 | break; | |
8876 | default: | |
8877 | /* Case prevented by pipe_config_set_bpp. */ | |
8878 | BUG(); | |
8879 | } | |
8880 | ||
6e3c9717 | 8881 | if (intel_crtc->config->dither) |
756f85cf PZ |
8882 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8883 | ||
8884 | I915_WRITE(PIPEMISC(pipe), val); | |
8885 | } | |
ee2b0b38 PZ |
8886 | } |
8887 | ||
6591c6e4 | 8888 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8889 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8890 | intel_clock_t *clock, |
8891 | bool *has_reduced_clock, | |
8892 | intel_clock_t *reduced_clock) | |
8893 | { | |
8894 | struct drm_device *dev = crtc->dev; | |
8895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8896 | int refclk; |
d4906093 | 8897 | const intel_limit_t *limit; |
c329a4ec | 8898 | bool ret; |
79e53945 | 8899 | |
55bb9992 | 8900 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8901 | |
d4906093 ML |
8902 | /* |
8903 | * Returns a set of divisors for the desired target clock with the given | |
8904 | * refclk, or FALSE. The returned values represent the clock equation: | |
8905 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8906 | */ | |
a93e255f ACO |
8907 | limit = intel_limit(crtc_state, refclk); |
8908 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8909 | crtc_state->port_clock, |
ee9300bb | 8910 | refclk, NULL, clock); |
6591c6e4 PZ |
8911 | if (!ret) |
8912 | return false; | |
cda4b7d3 | 8913 | |
6591c6e4 PZ |
8914 | return true; |
8915 | } | |
8916 | ||
d4b1931c PZ |
8917 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8918 | { | |
8919 | /* | |
8920 | * Account for spread spectrum to avoid | |
8921 | * oversubscribing the link. Max center spread | |
8922 | * is 2.5%; use 5% for safety's sake. | |
8923 | */ | |
8924 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8925 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8926 | } |
8927 | ||
7429e9d4 | 8928 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8929 | { |
7429e9d4 | 8930 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8931 | } |
8932 | ||
de13a2e3 | 8933 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8934 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8935 | u32 *fp, |
9a7c7890 | 8936 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8937 | { |
de13a2e3 | 8938 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8939 | struct drm_device *dev = crtc->dev; |
8940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8941 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8942 | struct drm_connector *connector; |
55bb9992 ACO |
8943 | struct drm_connector_state *connector_state; |
8944 | struct intel_encoder *encoder; | |
de13a2e3 | 8945 | uint32_t dpll; |
55bb9992 | 8946 | int factor, num_connectors = 0, i; |
09ede541 | 8947 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8948 | |
da3ced29 | 8949 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8950 | if (connector_state->crtc != crtc_state->base.crtc) |
8951 | continue; | |
8952 | ||
8953 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8954 | ||
8955 | switch (encoder->type) { | |
79e53945 JB |
8956 | case INTEL_OUTPUT_LVDS: |
8957 | is_lvds = true; | |
8958 | break; | |
8959 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8960 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8961 | is_sdvo = true; |
79e53945 | 8962 | break; |
6847d71b PZ |
8963 | default: |
8964 | break; | |
79e53945 | 8965 | } |
43565a06 | 8966 | |
c751ce4f | 8967 | num_connectors++; |
79e53945 | 8968 | } |
79e53945 | 8969 | |
c1858123 | 8970 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8971 | factor = 21; |
8972 | if (is_lvds) { | |
8973 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8974 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8975 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8976 | factor = 25; |
190f68c5 | 8977 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8978 | factor = 20; |
c1858123 | 8979 | |
190f68c5 | 8980 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8981 | *fp |= FP_CB_TUNE; |
2c07245f | 8982 | |
9a7c7890 DV |
8983 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8984 | *fp2 |= FP_CB_TUNE; | |
8985 | ||
5eddb70b | 8986 | dpll = 0; |
2c07245f | 8987 | |
a07d6787 EA |
8988 | if (is_lvds) |
8989 | dpll |= DPLLB_MODE_LVDS; | |
8990 | else | |
8991 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8992 | |
190f68c5 | 8993 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8994 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8995 | |
8996 | if (is_sdvo) | |
4a33e48d | 8997 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8998 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8999 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9000 | |
a07d6787 | 9001 | /* compute bitmask from p1 value */ |
190f68c5 | 9002 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9003 | /* also FPA1 */ |
190f68c5 | 9004 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9005 | |
190f68c5 | 9006 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9007 | case 5: |
9008 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9009 | break; | |
9010 | case 7: | |
9011 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9012 | break; | |
9013 | case 10: | |
9014 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9015 | break; | |
9016 | case 14: | |
9017 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9018 | break; | |
79e53945 JB |
9019 | } |
9020 | ||
b4c09f3b | 9021 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 9022 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9023 | else |
9024 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9025 | ||
959e16d6 | 9026 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
9027 | } |
9028 | ||
190f68c5 ACO |
9029 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9030 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9031 | { |
c7653199 | 9032 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 9033 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 9034 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 9035 | bool ok, has_reduced_clock = false; |
8b47047b | 9036 | bool is_lvds = false; |
e2b78267 | 9037 | struct intel_shared_dpll *pll; |
de13a2e3 | 9038 | |
dd3cd74a ACO |
9039 | memset(&crtc_state->dpll_hw_state, 0, |
9040 | sizeof(crtc_state->dpll_hw_state)); | |
9041 | ||
7905df29 | 9042 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 9043 | |
5dc5298b PZ |
9044 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
9045 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 9046 | |
190f68c5 | 9047 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 9048 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 9049 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
9050 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9051 | return -EINVAL; | |
79e53945 | 9052 | } |
f47709a9 | 9053 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9054 | if (!crtc_state->clock_set) { |
9055 | crtc_state->dpll.n = clock.n; | |
9056 | crtc_state->dpll.m1 = clock.m1; | |
9057 | crtc_state->dpll.m2 = clock.m2; | |
9058 | crtc_state->dpll.p1 = clock.p1; | |
9059 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9060 | } |
79e53945 | 9061 | |
5dc5298b | 9062 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9063 | if (crtc_state->has_pch_encoder) { |
9064 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9065 | if (has_reduced_clock) |
7429e9d4 | 9066 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9067 | |
190f68c5 | 9068 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9069 | &fp, &reduced_clock, |
9070 | has_reduced_clock ? &fp2 : NULL); | |
9071 | ||
190f68c5 ACO |
9072 | crtc_state->dpll_hw_state.dpll = dpll; |
9073 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9074 | if (has_reduced_clock) |
190f68c5 | 9075 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9076 | else |
190f68c5 | 9077 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9078 | |
190f68c5 | 9079 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9080 | if (pll == NULL) { |
84f44ce7 | 9081 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9082 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9083 | return -EINVAL; |
9084 | } | |
3fb37703 | 9085 | } |
79e53945 | 9086 | |
ab585dea | 9087 | if (is_lvds && has_reduced_clock) |
c7653199 | 9088 | crtc->lowfreq_avail = true; |
bcd644e0 | 9089 | else |
c7653199 | 9090 | crtc->lowfreq_avail = false; |
e2b78267 | 9091 | |
c8f7a0db | 9092 | return 0; |
79e53945 JB |
9093 | } |
9094 | ||
eb14cb74 VS |
9095 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9096 | struct intel_link_m_n *m_n) | |
9097 | { | |
9098 | struct drm_device *dev = crtc->base.dev; | |
9099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9100 | enum pipe pipe = crtc->pipe; | |
9101 | ||
9102 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9103 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9104 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9105 | & ~TU_SIZE_MASK; | |
9106 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9107 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9108 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9109 | } | |
9110 | ||
9111 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9112 | enum transcoder transcoder, | |
b95af8be VK |
9113 | struct intel_link_m_n *m_n, |
9114 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9115 | { |
9116 | struct drm_device *dev = crtc->base.dev; | |
9117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9118 | enum pipe pipe = crtc->pipe; |
72419203 | 9119 | |
eb14cb74 VS |
9120 | if (INTEL_INFO(dev)->gen >= 5) { |
9121 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9122 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9123 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9124 | & ~TU_SIZE_MASK; | |
9125 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9126 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9127 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9128 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9129 | * gen < 8) and if DRRS is supported (to make sure the | |
9130 | * registers are not unnecessarily read). | |
9131 | */ | |
9132 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9133 | crtc->config->has_drrs) { |
b95af8be VK |
9134 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9135 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9136 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9137 | & ~TU_SIZE_MASK; | |
9138 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9139 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9140 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9141 | } | |
eb14cb74 VS |
9142 | } else { |
9143 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9144 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9145 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9146 | & ~TU_SIZE_MASK; | |
9147 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9148 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9149 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9150 | } | |
9151 | } | |
9152 | ||
9153 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9154 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9155 | { |
681a8504 | 9156 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9157 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9158 | else | |
9159 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9160 | &pipe_config->dp_m_n, |
9161 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9162 | } |
72419203 | 9163 | |
eb14cb74 | 9164 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9165 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9166 | { |
9167 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9168 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9169 | } |
9170 | ||
bd2e244f | 9171 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9172 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9173 | { |
9174 | struct drm_device *dev = crtc->base.dev; | |
9175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9176 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9177 | uint32_t ps_ctrl = 0; | |
9178 | int id = -1; | |
9179 | int i; | |
bd2e244f | 9180 | |
a1b2278e CK |
9181 | /* find scaler attached to this pipe */ |
9182 | for (i = 0; i < crtc->num_scalers; i++) { | |
9183 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9184 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9185 | id = i; | |
9186 | pipe_config->pch_pfit.enabled = true; | |
9187 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9188 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9189 | break; | |
9190 | } | |
9191 | } | |
bd2e244f | 9192 | |
a1b2278e CK |
9193 | scaler_state->scaler_id = id; |
9194 | if (id >= 0) { | |
9195 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9196 | } else { | |
9197 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9198 | } |
9199 | } | |
9200 | ||
5724dbd1 DL |
9201 | static void |
9202 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9203 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9204 | { |
9205 | struct drm_device *dev = crtc->base.dev; | |
9206 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9207 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9208 | int pipe = crtc->pipe; |
9209 | int fourcc, pixel_format; | |
6761dd31 | 9210 | unsigned int aligned_height; |
bc8d7dff | 9211 | struct drm_framebuffer *fb; |
1b842c89 | 9212 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9213 | |
d9806c9f | 9214 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9215 | if (!intel_fb) { |
bc8d7dff DL |
9216 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9217 | return; | |
9218 | } | |
9219 | ||
1b842c89 DL |
9220 | fb = &intel_fb->base; |
9221 | ||
bc8d7dff | 9222 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9223 | if (!(val & PLANE_CTL_ENABLE)) |
9224 | goto error; | |
9225 | ||
bc8d7dff DL |
9226 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9227 | fourcc = skl_format_to_fourcc(pixel_format, | |
9228 | val & PLANE_CTL_ORDER_RGBX, | |
9229 | val & PLANE_CTL_ALPHA_MASK); | |
9230 | fb->pixel_format = fourcc; | |
9231 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9232 | ||
40f46283 DL |
9233 | tiling = val & PLANE_CTL_TILED_MASK; |
9234 | switch (tiling) { | |
9235 | case PLANE_CTL_TILED_LINEAR: | |
9236 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9237 | break; | |
9238 | case PLANE_CTL_TILED_X: | |
9239 | plane_config->tiling = I915_TILING_X; | |
9240 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9241 | break; | |
9242 | case PLANE_CTL_TILED_Y: | |
9243 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9244 | break; | |
9245 | case PLANE_CTL_TILED_YF: | |
9246 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9247 | break; | |
9248 | default: | |
9249 | MISSING_CASE(tiling); | |
9250 | goto error; | |
9251 | } | |
9252 | ||
bc8d7dff DL |
9253 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9254 | plane_config->base = base; | |
9255 | ||
9256 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9257 | ||
9258 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9259 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9260 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9261 | ||
9262 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9263 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9264 | fb->pixel_format); |
bc8d7dff DL |
9265 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9266 | ||
9267 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9268 | fb->pixel_format, |
9269 | fb->modifier[0]); | |
bc8d7dff | 9270 | |
f37b5c2b | 9271 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9272 | |
9273 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9274 | pipe_name(pipe), fb->width, fb->height, | |
9275 | fb->bits_per_pixel, base, fb->pitches[0], | |
9276 | plane_config->size); | |
9277 | ||
2d14030b | 9278 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9279 | return; |
9280 | ||
9281 | error: | |
9282 | kfree(fb); | |
9283 | } | |
9284 | ||
2fa2fe9a | 9285 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9286 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9287 | { |
9288 | struct drm_device *dev = crtc->base.dev; | |
9289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9290 | uint32_t tmp; | |
9291 | ||
9292 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9293 | ||
9294 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9295 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9296 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9297 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9298 | |
9299 | /* We currently do not free assignements of panel fitters on | |
9300 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9301 | * differentiates them) so just WARN about this case for now. */ | |
9302 | if (IS_GEN7(dev)) { | |
9303 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9304 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9305 | } | |
2fa2fe9a | 9306 | } |
79e53945 JB |
9307 | } |
9308 | ||
5724dbd1 DL |
9309 | static void |
9310 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9311 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9312 | { |
9313 | struct drm_device *dev = crtc->base.dev; | |
9314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9315 | u32 val, base, offset; | |
aeee5a49 | 9316 | int pipe = crtc->pipe; |
4c6baa59 | 9317 | int fourcc, pixel_format; |
6761dd31 | 9318 | unsigned int aligned_height; |
b113d5ee | 9319 | struct drm_framebuffer *fb; |
1b842c89 | 9320 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9321 | |
42a7b088 DL |
9322 | val = I915_READ(DSPCNTR(pipe)); |
9323 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9324 | return; | |
9325 | ||
d9806c9f | 9326 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9327 | if (!intel_fb) { |
4c6baa59 JB |
9328 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9329 | return; | |
9330 | } | |
9331 | ||
1b842c89 DL |
9332 | fb = &intel_fb->base; |
9333 | ||
18c5247e DV |
9334 | if (INTEL_INFO(dev)->gen >= 4) { |
9335 | if (val & DISPPLANE_TILED) { | |
49af449b | 9336 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9337 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9338 | } | |
9339 | } | |
4c6baa59 JB |
9340 | |
9341 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9342 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9343 | fb->pixel_format = fourcc; |
9344 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9345 | |
aeee5a49 | 9346 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9347 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9348 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9349 | } else { |
49af449b | 9350 | if (plane_config->tiling) |
aeee5a49 | 9351 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9352 | else |
aeee5a49 | 9353 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9354 | } |
9355 | plane_config->base = base; | |
9356 | ||
9357 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9358 | fb->width = ((val >> 16) & 0xfff) + 1; |
9359 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9360 | |
9361 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9362 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9363 | |
b113d5ee | 9364 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9365 | fb->pixel_format, |
9366 | fb->modifier[0]); | |
4c6baa59 | 9367 | |
f37b5c2b | 9368 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9369 | |
2844a921 DL |
9370 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9371 | pipe_name(pipe), fb->width, fb->height, | |
9372 | fb->bits_per_pixel, base, fb->pitches[0], | |
9373 | plane_config->size); | |
b113d5ee | 9374 | |
2d14030b | 9375 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9376 | } |
9377 | ||
0e8ffe1b | 9378 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9379 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9380 | { |
9381 | struct drm_device *dev = crtc->base.dev; | |
9382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9383 | uint32_t tmp; | |
9384 | ||
f458ebbc DV |
9385 | if (!intel_display_power_is_enabled(dev_priv, |
9386 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9387 | return false; |
9388 | ||
e143a21c | 9389 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9390 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9391 | |
0e8ffe1b DV |
9392 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9393 | if (!(tmp & PIPECONF_ENABLE)) | |
9394 | return false; | |
9395 | ||
42571aef VS |
9396 | switch (tmp & PIPECONF_BPC_MASK) { |
9397 | case PIPECONF_6BPC: | |
9398 | pipe_config->pipe_bpp = 18; | |
9399 | break; | |
9400 | case PIPECONF_8BPC: | |
9401 | pipe_config->pipe_bpp = 24; | |
9402 | break; | |
9403 | case PIPECONF_10BPC: | |
9404 | pipe_config->pipe_bpp = 30; | |
9405 | break; | |
9406 | case PIPECONF_12BPC: | |
9407 | pipe_config->pipe_bpp = 36; | |
9408 | break; | |
9409 | default: | |
9410 | break; | |
9411 | } | |
9412 | ||
b5a9fa09 DV |
9413 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9414 | pipe_config->limited_color_range = true; | |
9415 | ||
ab9412ba | 9416 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9417 | struct intel_shared_dpll *pll; |
9418 | ||
88adfff1 DV |
9419 | pipe_config->has_pch_encoder = true; |
9420 | ||
627eb5a3 DV |
9421 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9422 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9423 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9424 | |
9425 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9426 | |
c0d43d62 | 9427 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9428 | pipe_config->shared_dpll = |
9429 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9430 | } else { |
9431 | tmp = I915_READ(PCH_DPLL_SEL); | |
9432 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9433 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9434 | else | |
9435 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9436 | } | |
66e985c0 DV |
9437 | |
9438 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9439 | ||
9440 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9441 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9442 | |
9443 | tmp = pipe_config->dpll_hw_state.dpll; | |
9444 | pipe_config->pixel_multiplier = | |
9445 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9446 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9447 | |
9448 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9449 | } else { |
9450 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9451 | } |
9452 | ||
1bd1bd80 DV |
9453 | intel_get_pipe_timings(crtc, pipe_config); |
9454 | ||
2fa2fe9a DV |
9455 | ironlake_get_pfit_config(crtc, pipe_config); |
9456 | ||
0e8ffe1b DV |
9457 | return true; |
9458 | } | |
9459 | ||
be256dc7 PZ |
9460 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9461 | { | |
9462 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9463 | struct intel_crtc *crtc; |
be256dc7 | 9464 | |
d3fcc808 | 9465 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9466 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9467 | pipe_name(crtc->pipe)); |
9468 | ||
e2c719b7 RC |
9469 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9470 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9471 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9472 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9473 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9474 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9475 | "CPU PWM1 enabled\n"); |
c5107b87 | 9476 | if (IS_HASWELL(dev)) |
e2c719b7 | 9477 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9478 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9479 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9480 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9481 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9482 | "Utility pin enabled\n"); |
e2c719b7 | 9483 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9484 | |
9926ada1 PZ |
9485 | /* |
9486 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9487 | * interrupts remain enabled. We used to check for that, but since it's | |
9488 | * gen-specific and since we only disable LCPLL after we fully disable | |
9489 | * the interrupts, the check below should be enough. | |
9490 | */ | |
e2c719b7 | 9491 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9492 | } |
9493 | ||
9ccd5aeb PZ |
9494 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9495 | { | |
9496 | struct drm_device *dev = dev_priv->dev; | |
9497 | ||
9498 | if (IS_HASWELL(dev)) | |
9499 | return I915_READ(D_COMP_HSW); | |
9500 | else | |
9501 | return I915_READ(D_COMP_BDW); | |
9502 | } | |
9503 | ||
3c4c9b81 PZ |
9504 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9505 | { | |
9506 | struct drm_device *dev = dev_priv->dev; | |
9507 | ||
9508 | if (IS_HASWELL(dev)) { | |
9509 | mutex_lock(&dev_priv->rps.hw_lock); | |
9510 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9511 | val)) | |
f475dadf | 9512 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9513 | mutex_unlock(&dev_priv->rps.hw_lock); |
9514 | } else { | |
9ccd5aeb PZ |
9515 | I915_WRITE(D_COMP_BDW, val); |
9516 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9517 | } |
be256dc7 PZ |
9518 | } |
9519 | ||
9520 | /* | |
9521 | * This function implements pieces of two sequences from BSpec: | |
9522 | * - Sequence for display software to disable LCPLL | |
9523 | * - Sequence for display software to allow package C8+ | |
9524 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9525 | * register. Callers should take care of disabling all the display engine | |
9526 | * functions, doing the mode unset, fixing interrupts, etc. | |
9527 | */ | |
6ff58d53 PZ |
9528 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9529 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9530 | { |
9531 | uint32_t val; | |
9532 | ||
9533 | assert_can_disable_lcpll(dev_priv); | |
9534 | ||
9535 | val = I915_READ(LCPLL_CTL); | |
9536 | ||
9537 | if (switch_to_fclk) { | |
9538 | val |= LCPLL_CD_SOURCE_FCLK; | |
9539 | I915_WRITE(LCPLL_CTL, val); | |
9540 | ||
9541 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9542 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9543 | DRM_ERROR("Switching to FCLK failed\n"); | |
9544 | ||
9545 | val = I915_READ(LCPLL_CTL); | |
9546 | } | |
9547 | ||
9548 | val |= LCPLL_PLL_DISABLE; | |
9549 | I915_WRITE(LCPLL_CTL, val); | |
9550 | POSTING_READ(LCPLL_CTL); | |
9551 | ||
9552 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9553 | DRM_ERROR("LCPLL still locked\n"); | |
9554 | ||
9ccd5aeb | 9555 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9556 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9557 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9558 | ndelay(100); |
9559 | ||
9ccd5aeb PZ |
9560 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9561 | 1)) | |
be256dc7 PZ |
9562 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9563 | ||
9564 | if (allow_power_down) { | |
9565 | val = I915_READ(LCPLL_CTL); | |
9566 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9567 | I915_WRITE(LCPLL_CTL, val); | |
9568 | POSTING_READ(LCPLL_CTL); | |
9569 | } | |
9570 | } | |
9571 | ||
9572 | /* | |
9573 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9574 | * source. | |
9575 | */ | |
6ff58d53 | 9576 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9577 | { |
9578 | uint32_t val; | |
9579 | ||
9580 | val = I915_READ(LCPLL_CTL); | |
9581 | ||
9582 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9583 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9584 | return; | |
9585 | ||
a8a8bd54 PZ |
9586 | /* |
9587 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9588 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9589 | */ |
59bad947 | 9590 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9591 | |
be256dc7 PZ |
9592 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9593 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9594 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9595 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9596 | } |
9597 | ||
9ccd5aeb | 9598 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9599 | val |= D_COMP_COMP_FORCE; |
9600 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9601 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9602 | |
9603 | val = I915_READ(LCPLL_CTL); | |
9604 | val &= ~LCPLL_PLL_DISABLE; | |
9605 | I915_WRITE(LCPLL_CTL, val); | |
9606 | ||
9607 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9608 | DRM_ERROR("LCPLL not locked yet\n"); | |
9609 | ||
9610 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9611 | val = I915_READ(LCPLL_CTL); | |
9612 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9613 | I915_WRITE(LCPLL_CTL, val); | |
9614 | ||
9615 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9616 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9617 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9618 | } | |
215733fa | 9619 | |
59bad947 | 9620 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9621 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9622 | } |
9623 | ||
765dab67 PZ |
9624 | /* |
9625 | * Package states C8 and deeper are really deep PC states that can only be | |
9626 | * reached when all the devices on the system allow it, so even if the graphics | |
9627 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9628 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9629 | * | |
9630 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9631 | * well is disabled and most interrupts are disabled, and these are also | |
9632 | * requirements for runtime PM. When these conditions are met, we manually do | |
9633 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9634 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9635 | * hang the machine. | |
9636 | * | |
9637 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9638 | * the state of some registers, so when we come back from PC8+ we need to | |
9639 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9640 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9641 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9642 | * because of the runtime PM support). | |
9643 | * | |
9644 | * For more, read "Display Sequences for Package C8" on the hardware | |
9645 | * documentation. | |
9646 | */ | |
a14cb6fc | 9647 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9648 | { |
c67a470b PZ |
9649 | struct drm_device *dev = dev_priv->dev; |
9650 | uint32_t val; | |
9651 | ||
c67a470b PZ |
9652 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9653 | ||
c2699524 | 9654 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9655 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9656 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9657 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9658 | } | |
9659 | ||
9660 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9661 | hsw_disable_lcpll(dev_priv, true, true); |
9662 | } | |
9663 | ||
a14cb6fc | 9664 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9665 | { |
9666 | struct drm_device *dev = dev_priv->dev; | |
9667 | uint32_t val; | |
9668 | ||
c67a470b PZ |
9669 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9670 | ||
9671 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9672 | lpt_init_pch_refclk(dev); |
9673 | ||
c2699524 | 9674 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9675 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9676 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9677 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9678 | } | |
c67a470b PZ |
9679 | } |
9680 | ||
27c329ed | 9681 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9682 | { |
a821fc46 | 9683 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9684 | struct intel_atomic_state *old_intel_state = |
9685 | to_intel_atomic_state(old_state); | |
9686 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9687 | |
27c329ed | 9688 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9689 | } |
9690 | ||
b432e5cf | 9691 | /* compute the max rate for new configuration */ |
27c329ed | 9692 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9693 | { |
565602d7 ML |
9694 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9695 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9696 | struct drm_crtc *crtc; | |
9697 | struct drm_crtc_state *cstate; | |
27c329ed | 9698 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9699 | unsigned max_pixel_rate = 0, i; |
9700 | enum pipe pipe; | |
b432e5cf | 9701 | |
565602d7 ML |
9702 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9703 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9704 | |
565602d7 ML |
9705 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9706 | int pixel_rate; | |
27c329ed | 9707 | |
565602d7 ML |
9708 | crtc_state = to_intel_crtc_state(cstate); |
9709 | if (!crtc_state->base.enable) { | |
9710 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9711 | continue; |
565602d7 | 9712 | } |
b432e5cf | 9713 | |
27c329ed | 9714 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9715 | |
9716 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9717 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9718 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9719 | ||
565602d7 | 9720 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9721 | } |
9722 | ||
565602d7 ML |
9723 | if (!intel_state->active_crtcs) |
9724 | return 0; | |
9725 | ||
9726 | for_each_pipe(dev_priv, pipe) | |
9727 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9728 | ||
b432e5cf VS |
9729 | return max_pixel_rate; |
9730 | } | |
9731 | ||
9732 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9733 | { | |
9734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9735 | uint32_t val, data; | |
9736 | int ret; | |
9737 | ||
9738 | if (WARN((I915_READ(LCPLL_CTL) & | |
9739 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9740 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9741 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9742 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9743 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9744 | return; | |
9745 | ||
9746 | mutex_lock(&dev_priv->rps.hw_lock); | |
9747 | ret = sandybridge_pcode_write(dev_priv, | |
9748 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9749 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9750 | if (ret) { | |
9751 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9752 | return; | |
9753 | } | |
9754 | ||
9755 | val = I915_READ(LCPLL_CTL); | |
9756 | val |= LCPLL_CD_SOURCE_FCLK; | |
9757 | I915_WRITE(LCPLL_CTL, val); | |
9758 | ||
9759 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9760 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9761 | DRM_ERROR("Switching to FCLK failed\n"); | |
9762 | ||
9763 | val = I915_READ(LCPLL_CTL); | |
9764 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9765 | ||
9766 | switch (cdclk) { | |
9767 | case 450000: | |
9768 | val |= LCPLL_CLK_FREQ_450; | |
9769 | data = 0; | |
9770 | break; | |
9771 | case 540000: | |
9772 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9773 | data = 1; | |
9774 | break; | |
9775 | case 337500: | |
9776 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9777 | data = 2; | |
9778 | break; | |
9779 | case 675000: | |
9780 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9781 | data = 3; | |
9782 | break; | |
9783 | default: | |
9784 | WARN(1, "invalid cdclk frequency\n"); | |
9785 | return; | |
9786 | } | |
9787 | ||
9788 | I915_WRITE(LCPLL_CTL, val); | |
9789 | ||
9790 | val = I915_READ(LCPLL_CTL); | |
9791 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9792 | I915_WRITE(LCPLL_CTL, val); | |
9793 | ||
9794 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9795 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9796 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9797 | ||
9798 | mutex_lock(&dev_priv->rps.hw_lock); | |
9799 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9800 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9801 | ||
9802 | intel_update_cdclk(dev); | |
9803 | ||
9804 | WARN(cdclk != dev_priv->cdclk_freq, | |
9805 | "cdclk requested %d kHz but got %d kHz\n", | |
9806 | cdclk, dev_priv->cdclk_freq); | |
9807 | } | |
9808 | ||
27c329ed | 9809 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9810 | { |
27c329ed | 9811 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9812 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9813 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9814 | int cdclk; |
9815 | ||
9816 | /* | |
9817 | * FIXME should also account for plane ratio | |
9818 | * once 64bpp pixel formats are supported. | |
9819 | */ | |
27c329ed | 9820 | if (max_pixclk > 540000) |
b432e5cf | 9821 | cdclk = 675000; |
27c329ed | 9822 | else if (max_pixclk > 450000) |
b432e5cf | 9823 | cdclk = 540000; |
27c329ed | 9824 | else if (max_pixclk > 337500) |
b432e5cf VS |
9825 | cdclk = 450000; |
9826 | else | |
9827 | cdclk = 337500; | |
9828 | ||
b432e5cf | 9829 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9830 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9831 | cdclk, dev_priv->max_cdclk_freq); | |
9832 | return -EINVAL; | |
b432e5cf VS |
9833 | } |
9834 | ||
1a617b77 ML |
9835 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9836 | if (!intel_state->active_crtcs) | |
9837 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9838 | |
9839 | return 0; | |
9840 | } | |
9841 | ||
27c329ed | 9842 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9843 | { |
27c329ed | 9844 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9845 | struct intel_atomic_state *old_intel_state = |
9846 | to_intel_atomic_state(old_state); | |
9847 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9848 | |
27c329ed | 9849 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9850 | } |
9851 | ||
190f68c5 ACO |
9852 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9853 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9854 | { |
af3997b5 MK |
9855 | struct intel_encoder *intel_encoder = |
9856 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9857 | ||
9858 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9859 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9860 | return -EINVAL; | |
9861 | } | |
716c2e55 | 9862 | |
c7653199 | 9863 | crtc->lowfreq_avail = false; |
644cef34 | 9864 | |
c8f7a0db | 9865 | return 0; |
79e53945 JB |
9866 | } |
9867 | ||
3760b59c S |
9868 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9869 | enum port port, | |
9870 | struct intel_crtc_state *pipe_config) | |
9871 | { | |
9872 | switch (port) { | |
9873 | case PORT_A: | |
9874 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9875 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9876 | break; | |
9877 | case PORT_B: | |
9878 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9879 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9880 | break; | |
9881 | case PORT_C: | |
9882 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9883 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9884 | break; | |
9885 | default: | |
9886 | DRM_ERROR("Incorrect port type\n"); | |
9887 | } | |
9888 | } | |
9889 | ||
96b7dfb7 S |
9890 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9891 | enum port port, | |
5cec258b | 9892 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9893 | { |
3148ade7 | 9894 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9895 | |
9896 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9897 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9898 | ||
9899 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9900 | case SKL_DPLL0: |
9901 | /* | |
9902 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9903 | * of the shared DPLL framework and thus needs to be read out | |
9904 | * separately | |
9905 | */ | |
9906 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9907 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9908 | break; | |
96b7dfb7 S |
9909 | case SKL_DPLL1: |
9910 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9911 | break; | |
9912 | case SKL_DPLL2: | |
9913 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9914 | break; | |
9915 | case SKL_DPLL3: | |
9916 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9917 | break; | |
96b7dfb7 S |
9918 | } |
9919 | } | |
9920 | ||
7d2c8175 DL |
9921 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9922 | enum port port, | |
5cec258b | 9923 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9924 | { |
9925 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9926 | ||
9927 | switch (pipe_config->ddi_pll_sel) { | |
9928 | case PORT_CLK_SEL_WRPLL1: | |
9929 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9930 | break; | |
9931 | case PORT_CLK_SEL_WRPLL2: | |
9932 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9933 | break; | |
00490c22 ML |
9934 | case PORT_CLK_SEL_SPLL: |
9935 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 9936 | break; |
7d2c8175 DL |
9937 | } |
9938 | } | |
9939 | ||
26804afd | 9940 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9941 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9942 | { |
9943 | struct drm_device *dev = crtc->base.dev; | |
9944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9945 | struct intel_shared_dpll *pll; |
26804afd DV |
9946 | enum port port; |
9947 | uint32_t tmp; | |
9948 | ||
9949 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9950 | ||
9951 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9952 | ||
ef11bdb3 | 9953 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9954 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9955 | else if (IS_BROXTON(dev)) |
9956 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9957 | else |
9958 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9959 | |
d452c5b6 DV |
9960 | if (pipe_config->shared_dpll >= 0) { |
9961 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9962 | ||
9963 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9964 | &pipe_config->dpll_hw_state)); | |
9965 | } | |
9966 | ||
26804afd DV |
9967 | /* |
9968 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9969 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9970 | * the PCH transcoder is on. | |
9971 | */ | |
ca370455 DL |
9972 | if (INTEL_INFO(dev)->gen < 9 && |
9973 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9974 | pipe_config->has_pch_encoder = true; |
9975 | ||
9976 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9977 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9978 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9979 | ||
9980 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9981 | } | |
9982 | } | |
9983 | ||
0e8ffe1b | 9984 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9985 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9986 | { |
9987 | struct drm_device *dev = crtc->base.dev; | |
9988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9989 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9990 | uint32_t tmp; |
9991 | ||
f458ebbc | 9992 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9993 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9994 | return false; | |
9995 | ||
e143a21c | 9996 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9997 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9998 | ||
eccb140b DV |
9999 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
10000 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10001 | enum pipe trans_edp_pipe; | |
10002 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10003 | default: | |
10004 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10005 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10006 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10007 | trans_edp_pipe = PIPE_A; | |
10008 | break; | |
10009 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10010 | trans_edp_pipe = PIPE_B; | |
10011 | break; | |
10012 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10013 | trans_edp_pipe = PIPE_C; | |
10014 | break; | |
10015 | } | |
10016 | ||
10017 | if (trans_edp_pipe == crtc->pipe) | |
10018 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10019 | } | |
10020 | ||
f458ebbc | 10021 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 10022 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
10023 | return false; |
10024 | ||
eccb140b | 10025 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
10026 | if (!(tmp & PIPECONF_ENABLE)) |
10027 | return false; | |
10028 | ||
26804afd | 10029 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 10030 | |
1bd1bd80 DV |
10031 | intel_get_pipe_timings(crtc, pipe_config); |
10032 | ||
a1b2278e CK |
10033 | if (INTEL_INFO(dev)->gen >= 9) { |
10034 | skl_init_scalers(dev, crtc, pipe_config); | |
10035 | } | |
10036 | ||
2fa2fe9a | 10037 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
10038 | |
10039 | if (INTEL_INFO(dev)->gen >= 9) { | |
10040 | pipe_config->scaler_state.scaler_id = -1; | |
10041 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10042 | } | |
10043 | ||
bd2e244f | 10044 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 10045 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10046 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10047 | else |
1c132b44 | 10048 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10049 | } |
88adfff1 | 10050 | |
e59150dc JB |
10051 | if (IS_HASWELL(dev)) |
10052 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10053 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10054 | |
ebb69c95 CT |
10055 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10056 | pipe_config->pixel_multiplier = | |
10057 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10058 | } else { | |
10059 | pipe_config->pixel_multiplier = 1; | |
10060 | } | |
6c49f241 | 10061 | |
0e8ffe1b DV |
10062 | return true; |
10063 | } | |
10064 | ||
55a08b3f ML |
10065 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10066 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10067 | { |
10068 | struct drm_device *dev = crtc->dev; | |
10069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10071 | uint32_t cntl = 0, size = 0; |
560b85bb | 10072 | |
55a08b3f ML |
10073 | if (plane_state && plane_state->visible) { |
10074 | unsigned int width = plane_state->base.crtc_w; | |
10075 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10076 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10077 | ||
10078 | switch (stride) { | |
10079 | default: | |
10080 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10081 | width, stride); | |
10082 | stride = 256; | |
10083 | /* fallthrough */ | |
10084 | case 256: | |
10085 | case 512: | |
10086 | case 1024: | |
10087 | case 2048: | |
10088 | break; | |
4b0e333e CW |
10089 | } |
10090 | ||
dc41c154 VS |
10091 | cntl |= CURSOR_ENABLE | |
10092 | CURSOR_GAMMA_ENABLE | | |
10093 | CURSOR_FORMAT_ARGB | | |
10094 | CURSOR_STRIDE(stride); | |
10095 | ||
10096 | size = (height << 12) | width; | |
4b0e333e | 10097 | } |
560b85bb | 10098 | |
dc41c154 VS |
10099 | if (intel_crtc->cursor_cntl != 0 && |
10100 | (intel_crtc->cursor_base != base || | |
10101 | intel_crtc->cursor_size != size || | |
10102 | intel_crtc->cursor_cntl != cntl)) { | |
10103 | /* On these chipsets we can only modify the base/size/stride | |
10104 | * whilst the cursor is disabled. | |
10105 | */ | |
0b87c24e VS |
10106 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10107 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10108 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10109 | } |
560b85bb | 10110 | |
99d1f387 | 10111 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10112 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10113 | intel_crtc->cursor_base = base; |
10114 | } | |
4726e0b0 | 10115 | |
dc41c154 VS |
10116 | if (intel_crtc->cursor_size != size) { |
10117 | I915_WRITE(CURSIZE, size); | |
10118 | intel_crtc->cursor_size = size; | |
4b0e333e | 10119 | } |
560b85bb | 10120 | |
4b0e333e | 10121 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10122 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10123 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10124 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10125 | } |
560b85bb CW |
10126 | } |
10127 | ||
55a08b3f ML |
10128 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10129 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10130 | { |
10131 | struct drm_device *dev = crtc->dev; | |
10132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10133 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10134 | int pipe = intel_crtc->pipe; | |
663f3122 | 10135 | uint32_t cntl = 0; |
4b0e333e | 10136 | |
55a08b3f | 10137 | if (plane_state && plane_state->visible) { |
4b0e333e | 10138 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10139 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10140 | case 64: |
10141 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10142 | break; | |
10143 | case 128: | |
10144 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10145 | break; | |
10146 | case 256: | |
10147 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10148 | break; | |
10149 | default: | |
55a08b3f | 10150 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10151 | return; |
65a21cd6 | 10152 | } |
4b0e333e | 10153 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10154 | |
fc6f93bc | 10155 | if (HAS_DDI(dev)) |
47bf17a7 | 10156 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10157 | |
55a08b3f ML |
10158 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10159 | cntl |= CURSOR_ROTATE_180; | |
10160 | } | |
4398ad45 | 10161 | |
4b0e333e CW |
10162 | if (intel_crtc->cursor_cntl != cntl) { |
10163 | I915_WRITE(CURCNTR(pipe), cntl); | |
10164 | POSTING_READ(CURCNTR(pipe)); | |
10165 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10166 | } |
4b0e333e | 10167 | |
65a21cd6 | 10168 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10169 | I915_WRITE(CURBASE(pipe), base); |
10170 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10171 | |
10172 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10173 | } |
10174 | ||
cda4b7d3 | 10175 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10176 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10177 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10178 | { |
10179 | struct drm_device *dev = crtc->dev; | |
10180 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10181 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10182 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10183 | u32 base = intel_crtc->cursor_addr; |
10184 | u32 pos = 0; | |
cda4b7d3 | 10185 | |
55a08b3f ML |
10186 | if (plane_state) { |
10187 | int x = plane_state->base.crtc_x; | |
10188 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10189 | |
55a08b3f ML |
10190 | if (x < 0) { |
10191 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10192 | x = -x; | |
10193 | } | |
10194 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10195 | |
55a08b3f ML |
10196 | if (y < 0) { |
10197 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10198 | y = -y; | |
10199 | } | |
10200 | pos |= y << CURSOR_Y_SHIFT; | |
10201 | ||
10202 | /* ILK+ do this automagically */ | |
10203 | if (HAS_GMCH_DISPLAY(dev) && | |
10204 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10205 | base += (plane_state->base.crtc_h * | |
10206 | plane_state->base.crtc_w - 1) * 4; | |
10207 | } | |
cda4b7d3 | 10208 | } |
cda4b7d3 | 10209 | |
5efb3e28 VS |
10210 | I915_WRITE(CURPOS(pipe), pos); |
10211 | ||
8ac54669 | 10212 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10213 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10214 | else |
55a08b3f | 10215 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10216 | } |
10217 | ||
dc41c154 VS |
10218 | static bool cursor_size_ok(struct drm_device *dev, |
10219 | uint32_t width, uint32_t height) | |
10220 | { | |
10221 | if (width == 0 || height == 0) | |
10222 | return false; | |
10223 | ||
10224 | /* | |
10225 | * 845g/865g are special in that they are only limited by | |
10226 | * the width of their cursors, the height is arbitrary up to | |
10227 | * the precision of the register. Everything else requires | |
10228 | * square cursors, limited to a few power-of-two sizes. | |
10229 | */ | |
10230 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10231 | if ((width & 63) != 0) | |
10232 | return false; | |
10233 | ||
10234 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10235 | return false; | |
10236 | ||
10237 | if (height > 1023) | |
10238 | return false; | |
10239 | } else { | |
10240 | switch (width | height) { | |
10241 | case 256: | |
10242 | case 128: | |
10243 | if (IS_GEN2(dev)) | |
10244 | return false; | |
10245 | case 64: | |
10246 | break; | |
10247 | default: | |
10248 | return false; | |
10249 | } | |
10250 | } | |
10251 | ||
10252 | return true; | |
10253 | } | |
10254 | ||
79e53945 | 10255 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10256 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10257 | { |
7203425a | 10258 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10259 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10260 | |
7203425a | 10261 | for (i = start; i < end; i++) { |
79e53945 JB |
10262 | intel_crtc->lut_r[i] = red[i] >> 8; |
10263 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10264 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10265 | } | |
10266 | ||
10267 | intel_crtc_load_lut(crtc); | |
10268 | } | |
10269 | ||
79e53945 JB |
10270 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10271 | static struct drm_display_mode load_detect_mode = { | |
10272 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10273 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10274 | }; | |
10275 | ||
a8bb6818 DV |
10276 | struct drm_framebuffer * |
10277 | __intel_framebuffer_create(struct drm_device *dev, | |
10278 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10279 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10280 | { |
10281 | struct intel_framebuffer *intel_fb; | |
10282 | int ret; | |
10283 | ||
10284 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10285 | if (!intel_fb) |
d2dff872 | 10286 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10287 | |
10288 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10289 | if (ret) |
10290 | goto err; | |
d2dff872 CW |
10291 | |
10292 | return &intel_fb->base; | |
dcb1394e | 10293 | |
dd4916c5 | 10294 | err: |
dd4916c5 | 10295 | kfree(intel_fb); |
dd4916c5 | 10296 | return ERR_PTR(ret); |
d2dff872 CW |
10297 | } |
10298 | ||
b5ea642a | 10299 | static struct drm_framebuffer * |
a8bb6818 DV |
10300 | intel_framebuffer_create(struct drm_device *dev, |
10301 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10302 | struct drm_i915_gem_object *obj) | |
10303 | { | |
10304 | struct drm_framebuffer *fb; | |
10305 | int ret; | |
10306 | ||
10307 | ret = i915_mutex_lock_interruptible(dev); | |
10308 | if (ret) | |
10309 | return ERR_PTR(ret); | |
10310 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10311 | mutex_unlock(&dev->struct_mutex); | |
10312 | ||
10313 | return fb; | |
10314 | } | |
10315 | ||
d2dff872 CW |
10316 | static u32 |
10317 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10318 | { | |
10319 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10320 | return ALIGN(pitch, 64); | |
10321 | } | |
10322 | ||
10323 | static u32 | |
10324 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10325 | { | |
10326 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10327 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10328 | } |
10329 | ||
10330 | static struct drm_framebuffer * | |
10331 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10332 | struct drm_display_mode *mode, | |
10333 | int depth, int bpp) | |
10334 | { | |
dcb1394e | 10335 | struct drm_framebuffer *fb; |
d2dff872 | 10336 | struct drm_i915_gem_object *obj; |
0fed39bd | 10337 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10338 | |
10339 | obj = i915_gem_alloc_object(dev, | |
10340 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10341 | if (obj == NULL) | |
10342 | return ERR_PTR(-ENOMEM); | |
10343 | ||
10344 | mode_cmd.width = mode->hdisplay; | |
10345 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10346 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10347 | bpp); | |
5ca0c34a | 10348 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10349 | |
dcb1394e LW |
10350 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10351 | if (IS_ERR(fb)) | |
10352 | drm_gem_object_unreference_unlocked(&obj->base); | |
10353 | ||
10354 | return fb; | |
d2dff872 CW |
10355 | } |
10356 | ||
10357 | static struct drm_framebuffer * | |
10358 | mode_fits_in_fbdev(struct drm_device *dev, | |
10359 | struct drm_display_mode *mode) | |
10360 | { | |
0695726e | 10361 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10362 | struct drm_i915_private *dev_priv = dev->dev_private; |
10363 | struct drm_i915_gem_object *obj; | |
10364 | struct drm_framebuffer *fb; | |
10365 | ||
4c0e5528 | 10366 | if (!dev_priv->fbdev) |
d2dff872 CW |
10367 | return NULL; |
10368 | ||
4c0e5528 | 10369 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10370 | return NULL; |
10371 | ||
4c0e5528 DV |
10372 | obj = dev_priv->fbdev->fb->obj; |
10373 | BUG_ON(!obj); | |
10374 | ||
8bcd4553 | 10375 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10376 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10377 | fb->bits_per_pixel)) | |
d2dff872 CW |
10378 | return NULL; |
10379 | ||
01f2c773 | 10380 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10381 | return NULL; |
10382 | ||
10383 | return fb; | |
4520f53a DV |
10384 | #else |
10385 | return NULL; | |
10386 | #endif | |
d2dff872 CW |
10387 | } |
10388 | ||
d3a40d1b ACO |
10389 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10390 | struct drm_crtc *crtc, | |
10391 | struct drm_display_mode *mode, | |
10392 | struct drm_framebuffer *fb, | |
10393 | int x, int y) | |
10394 | { | |
10395 | struct drm_plane_state *plane_state; | |
10396 | int hdisplay, vdisplay; | |
10397 | int ret; | |
10398 | ||
10399 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10400 | if (IS_ERR(plane_state)) | |
10401 | return PTR_ERR(plane_state); | |
10402 | ||
10403 | if (mode) | |
10404 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10405 | else | |
10406 | hdisplay = vdisplay = 0; | |
10407 | ||
10408 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10409 | if (ret) | |
10410 | return ret; | |
10411 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10412 | plane_state->crtc_x = 0; | |
10413 | plane_state->crtc_y = 0; | |
10414 | plane_state->crtc_w = hdisplay; | |
10415 | plane_state->crtc_h = vdisplay; | |
10416 | plane_state->src_x = x << 16; | |
10417 | plane_state->src_y = y << 16; | |
10418 | plane_state->src_w = hdisplay << 16; | |
10419 | plane_state->src_h = vdisplay << 16; | |
10420 | ||
10421 | return 0; | |
10422 | } | |
10423 | ||
d2434ab7 | 10424 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10425 | struct drm_display_mode *mode, |
51fd371b RC |
10426 | struct intel_load_detect_pipe *old, |
10427 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10428 | { |
10429 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10430 | struct intel_encoder *intel_encoder = |
10431 | intel_attached_encoder(connector); | |
79e53945 | 10432 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10433 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10434 | struct drm_crtc *crtc = NULL; |
10435 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10436 | struct drm_framebuffer *fb; |
51fd371b | 10437 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10438 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10439 | struct drm_connector_state *connector_state; |
4be07317 | 10440 | struct intel_crtc_state *crtc_state; |
51fd371b | 10441 | int ret, i = -1; |
79e53945 | 10442 | |
d2dff872 | 10443 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10444 | connector->base.id, connector->name, |
8e329a03 | 10445 | encoder->base.id, encoder->name); |
d2dff872 | 10446 | |
51fd371b RC |
10447 | retry: |
10448 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10449 | if (ret) | |
ad3c558f | 10450 | goto fail; |
6e9f798d | 10451 | |
79e53945 JB |
10452 | /* |
10453 | * Algorithm gets a little messy: | |
7a5e4805 | 10454 | * |
79e53945 JB |
10455 | * - if the connector already has an assigned crtc, use it (but make |
10456 | * sure it's on first) | |
7a5e4805 | 10457 | * |
79e53945 JB |
10458 | * - try to find the first unused crtc that can drive this connector, |
10459 | * and use that if we find one | |
79e53945 JB |
10460 | */ |
10461 | ||
10462 | /* See if we already have a CRTC for this connector */ | |
10463 | if (encoder->crtc) { | |
10464 | crtc = encoder->crtc; | |
8261b191 | 10465 | |
51fd371b | 10466 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10467 | if (ret) |
ad3c558f | 10468 | goto fail; |
4d02e2de | 10469 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10470 | if (ret) |
ad3c558f | 10471 | goto fail; |
7b24056b | 10472 | |
24218aac | 10473 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10474 | old->load_detect_temp = false; |
10475 | ||
10476 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10477 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10478 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10479 | |
7173188d | 10480 | return true; |
79e53945 JB |
10481 | } |
10482 | ||
10483 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10484 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10485 | i++; |
10486 | if (!(encoder->possible_crtcs & (1 << i))) | |
10487 | continue; | |
83d65738 | 10488 | if (possible_crtc->state->enable) |
a459249c | 10489 | continue; |
a459249c VS |
10490 | |
10491 | crtc = possible_crtc; | |
10492 | break; | |
79e53945 JB |
10493 | } |
10494 | ||
10495 | /* | |
10496 | * If we didn't find an unused CRTC, don't use any. | |
10497 | */ | |
10498 | if (!crtc) { | |
7173188d | 10499 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10500 | goto fail; |
79e53945 JB |
10501 | } |
10502 | ||
51fd371b RC |
10503 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10504 | if (ret) | |
ad3c558f | 10505 | goto fail; |
4d02e2de DV |
10506 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10507 | if (ret) | |
ad3c558f | 10508 | goto fail; |
79e53945 JB |
10509 | |
10510 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10511 | old->dpms_mode = connector->dpms; |
8261b191 | 10512 | old->load_detect_temp = true; |
d2dff872 | 10513 | old->release_fb = NULL; |
79e53945 | 10514 | |
83a57153 ACO |
10515 | state = drm_atomic_state_alloc(dev); |
10516 | if (!state) | |
10517 | return false; | |
10518 | ||
10519 | state->acquire_ctx = ctx; | |
10520 | ||
944b0c76 ACO |
10521 | connector_state = drm_atomic_get_connector_state(state, connector); |
10522 | if (IS_ERR(connector_state)) { | |
10523 | ret = PTR_ERR(connector_state); | |
10524 | goto fail; | |
10525 | } | |
10526 | ||
10527 | connector_state->crtc = crtc; | |
944b0c76 | 10528 | |
4be07317 ACO |
10529 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10530 | if (IS_ERR(crtc_state)) { | |
10531 | ret = PTR_ERR(crtc_state); | |
10532 | goto fail; | |
10533 | } | |
10534 | ||
49d6fa21 | 10535 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10536 | |
6492711d CW |
10537 | if (!mode) |
10538 | mode = &load_detect_mode; | |
79e53945 | 10539 | |
d2dff872 CW |
10540 | /* We need a framebuffer large enough to accommodate all accesses |
10541 | * that the plane may generate whilst we perform load detection. | |
10542 | * We can not rely on the fbcon either being present (we get called | |
10543 | * during its initialisation to detect all boot displays, or it may | |
10544 | * not even exist) or that it is large enough to satisfy the | |
10545 | * requested mode. | |
10546 | */ | |
94352cf9 DV |
10547 | fb = mode_fits_in_fbdev(dev, mode); |
10548 | if (fb == NULL) { | |
d2dff872 | 10549 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10550 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10551 | old->release_fb = fb; | |
d2dff872 CW |
10552 | } else |
10553 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10554 | if (IS_ERR(fb)) { |
d2dff872 | 10555 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10556 | goto fail; |
79e53945 | 10557 | } |
79e53945 | 10558 | |
d3a40d1b ACO |
10559 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10560 | if (ret) | |
10561 | goto fail; | |
10562 | ||
8c7b5ccb ACO |
10563 | drm_mode_copy(&crtc_state->base.mode, mode); |
10564 | ||
74c090b1 | 10565 | if (drm_atomic_commit(state)) { |
6492711d | 10566 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10567 | if (old->release_fb) |
10568 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10569 | goto fail; |
79e53945 | 10570 | } |
9128b040 | 10571 | crtc->primary->crtc = crtc; |
7173188d | 10572 | |
79e53945 | 10573 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10574 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10575 | return true; |
412b61d8 | 10576 | |
ad3c558f | 10577 | fail: |
e5d958ef ACO |
10578 | drm_atomic_state_free(state); |
10579 | state = NULL; | |
83a57153 | 10580 | |
51fd371b RC |
10581 | if (ret == -EDEADLK) { |
10582 | drm_modeset_backoff(ctx); | |
10583 | goto retry; | |
10584 | } | |
10585 | ||
412b61d8 | 10586 | return false; |
79e53945 JB |
10587 | } |
10588 | ||
d2434ab7 | 10589 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10590 | struct intel_load_detect_pipe *old, |
10591 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10592 | { |
83a57153 | 10593 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10594 | struct intel_encoder *intel_encoder = |
10595 | intel_attached_encoder(connector); | |
4ef69c7a | 10596 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10597 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10598 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10599 | struct drm_atomic_state *state; |
944b0c76 | 10600 | struct drm_connector_state *connector_state; |
4be07317 | 10601 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10602 | int ret; |
79e53945 | 10603 | |
d2dff872 | 10604 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10605 | connector->base.id, connector->name, |
8e329a03 | 10606 | encoder->base.id, encoder->name); |
d2dff872 | 10607 | |
8261b191 | 10608 | if (old->load_detect_temp) { |
83a57153 | 10609 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10610 | if (!state) |
10611 | goto fail; | |
83a57153 ACO |
10612 | |
10613 | state->acquire_ctx = ctx; | |
10614 | ||
944b0c76 ACO |
10615 | connector_state = drm_atomic_get_connector_state(state, connector); |
10616 | if (IS_ERR(connector_state)) | |
10617 | goto fail; | |
10618 | ||
4be07317 ACO |
10619 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10620 | if (IS_ERR(crtc_state)) | |
10621 | goto fail; | |
10622 | ||
944b0c76 ACO |
10623 | connector_state->crtc = NULL; |
10624 | ||
49d6fa21 | 10625 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10626 | |
d3a40d1b ACO |
10627 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10628 | 0, 0); | |
10629 | if (ret) | |
10630 | goto fail; | |
10631 | ||
74c090b1 | 10632 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10633 | if (ret) |
10634 | goto fail; | |
d2dff872 | 10635 | |
36206361 DV |
10636 | if (old->release_fb) { |
10637 | drm_framebuffer_unregister_private(old->release_fb); | |
10638 | drm_framebuffer_unreference(old->release_fb); | |
10639 | } | |
d2dff872 | 10640 | |
0622a53c | 10641 | return; |
79e53945 JB |
10642 | } |
10643 | ||
c751ce4f | 10644 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10645 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10646 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10647 | |
10648 | return; | |
10649 | fail: | |
10650 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10651 | drm_atomic_state_free(state); | |
79e53945 JB |
10652 | } |
10653 | ||
da4a1efa | 10654 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10655 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10656 | { |
10657 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10658 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10659 | ||
10660 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10661 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10662 | else if (HAS_PCH_SPLIT(dev)) |
10663 | return 120000; | |
10664 | else if (!IS_GEN2(dev)) | |
10665 | return 96000; | |
10666 | else | |
10667 | return 48000; | |
10668 | } | |
10669 | ||
79e53945 | 10670 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10671 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10672 | struct intel_crtc_state *pipe_config) |
79e53945 | 10673 | { |
f1f644dc | 10674 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10675 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10676 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10677 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10678 | u32 fp; |
10679 | intel_clock_t clock; | |
dccbea3b | 10680 | int port_clock; |
da4a1efa | 10681 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10682 | |
10683 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10684 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10685 | else |
293623f7 | 10686 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10687 | |
10688 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10689 | if (IS_PINEVIEW(dev)) { |
10690 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10691 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10692 | } else { |
10693 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10694 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10695 | } | |
10696 | ||
a6c45cf0 | 10697 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10698 | if (IS_PINEVIEW(dev)) |
10699 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10700 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10701 | else |
10702 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10703 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10704 | ||
10705 | switch (dpll & DPLL_MODE_MASK) { | |
10706 | case DPLLB_MODE_DAC_SERIAL: | |
10707 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10708 | 5 : 10; | |
10709 | break; | |
10710 | case DPLLB_MODE_LVDS: | |
10711 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10712 | 7 : 14; | |
10713 | break; | |
10714 | default: | |
28c97730 | 10715 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10716 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10717 | return; |
79e53945 JB |
10718 | } |
10719 | ||
ac58c3f0 | 10720 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10721 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10722 | else |
dccbea3b | 10723 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10724 | } else { |
0fb58223 | 10725 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10726 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10727 | |
10728 | if (is_lvds) { | |
10729 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10730 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10731 | |
10732 | if (lvds & LVDS_CLKB_POWER_UP) | |
10733 | clock.p2 = 7; | |
10734 | else | |
10735 | clock.p2 = 14; | |
79e53945 JB |
10736 | } else { |
10737 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10738 | clock.p1 = 2; | |
10739 | else { | |
10740 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10741 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10742 | } | |
10743 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10744 | clock.p2 = 4; | |
10745 | else | |
10746 | clock.p2 = 2; | |
79e53945 | 10747 | } |
da4a1efa | 10748 | |
dccbea3b | 10749 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10750 | } |
10751 | ||
18442d08 VS |
10752 | /* |
10753 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10754 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10755 | * encoder's get_config() function. |
10756 | */ | |
dccbea3b | 10757 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10758 | } |
10759 | ||
6878da05 VS |
10760 | int intel_dotclock_calculate(int link_freq, |
10761 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10762 | { |
f1f644dc JB |
10763 | /* |
10764 | * The calculation for the data clock is: | |
1041a02f | 10765 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10766 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10767 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10768 | * |
10769 | * and the link clock is simpler: | |
1041a02f | 10770 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10771 | */ |
10772 | ||
6878da05 VS |
10773 | if (!m_n->link_n) |
10774 | return 0; | |
f1f644dc | 10775 | |
6878da05 VS |
10776 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10777 | } | |
f1f644dc | 10778 | |
18442d08 | 10779 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10780 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10781 | { |
10782 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10783 | |
18442d08 VS |
10784 | /* read out port_clock from the DPLL */ |
10785 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10786 | |
f1f644dc | 10787 | /* |
18442d08 | 10788 | * This value does not include pixel_multiplier. |
241bfc38 | 10789 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10790 | * agree once we know their relationship in the encoder's |
10791 | * get_config() function. | |
79e53945 | 10792 | */ |
2d112de7 | 10793 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10794 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10795 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10796 | } |
10797 | ||
10798 | /** Returns the currently programmed mode of the given pipe. */ | |
10799 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10800 | struct drm_crtc *crtc) | |
10801 | { | |
548f245b | 10802 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10803 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10804 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10805 | struct drm_display_mode *mode; |
3f36b937 | 10806 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10807 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10808 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10809 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10810 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10811 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10812 | |
10813 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10814 | if (!mode) | |
10815 | return NULL; | |
10816 | ||
3f36b937 TU |
10817 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10818 | if (!pipe_config) { | |
10819 | kfree(mode); | |
10820 | return NULL; | |
10821 | } | |
10822 | ||
f1f644dc JB |
10823 | /* |
10824 | * Construct a pipe_config sufficient for getting the clock info | |
10825 | * back out of crtc_clock_get. | |
10826 | * | |
10827 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10828 | * to use a real value here instead. | |
10829 | */ | |
3f36b937 TU |
10830 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10831 | pipe_config->pixel_multiplier = 1; | |
10832 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10833 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10834 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10835 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10836 | ||
10837 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10838 | mode->hdisplay = (htot & 0xffff) + 1; |
10839 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10840 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10841 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10842 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10843 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10844 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10845 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10846 | ||
10847 | drm_mode_set_name(mode); | |
79e53945 | 10848 | |
3f36b937 TU |
10849 | kfree(pipe_config); |
10850 | ||
79e53945 JB |
10851 | return mode; |
10852 | } | |
10853 | ||
f047e395 CW |
10854 | void intel_mark_busy(struct drm_device *dev) |
10855 | { | |
c67a470b PZ |
10856 | struct drm_i915_private *dev_priv = dev->dev_private; |
10857 | ||
f62a0076 CW |
10858 | if (dev_priv->mm.busy) |
10859 | return; | |
10860 | ||
43694d69 | 10861 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10862 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10863 | if (INTEL_INFO(dev)->gen >= 6) |
10864 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10865 | dev_priv->mm.busy = true; |
f047e395 CW |
10866 | } |
10867 | ||
10868 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10869 | { |
c67a470b | 10870 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10871 | |
f62a0076 CW |
10872 | if (!dev_priv->mm.busy) |
10873 | return; | |
10874 | ||
10875 | dev_priv->mm.busy = false; | |
10876 | ||
3d13ef2e | 10877 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10878 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10879 | |
43694d69 | 10880 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10881 | } |
10882 | ||
79e53945 JB |
10883 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10884 | { | |
10885 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10886 | struct drm_device *dev = crtc->dev; |
10887 | struct intel_unpin_work *work; | |
67e77c5a | 10888 | |
5e2d7afc | 10889 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10890 | work = intel_crtc->unpin_work; |
10891 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10892 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10893 | |
10894 | if (work) { | |
10895 | cancel_work_sync(&work->work); | |
10896 | kfree(work); | |
10897 | } | |
79e53945 JB |
10898 | |
10899 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10900 | |
79e53945 JB |
10901 | kfree(intel_crtc); |
10902 | } | |
10903 | ||
6b95a207 KH |
10904 | static void intel_unpin_work_fn(struct work_struct *__work) |
10905 | { | |
10906 | struct intel_unpin_work *work = | |
10907 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10908 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10909 | struct drm_device *dev = crtc->base.dev; | |
10910 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10911 | |
b4a98e57 | 10912 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10913 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10914 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10915 | |
f06cc1b9 | 10916 | if (work->flip_queued_req) |
146d84f0 | 10917 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10918 | mutex_unlock(&dev->struct_mutex); |
10919 | ||
a9ff8714 | 10920 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 10921 | intel_fbc_post_update(crtc); |
89ed88ba | 10922 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10923 | |
a9ff8714 VS |
10924 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10925 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10926 | |
6b95a207 KH |
10927 | kfree(work); |
10928 | } | |
10929 | ||
1afe3e9d | 10930 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10931 | struct drm_crtc *crtc) |
6b95a207 | 10932 | { |
6b95a207 KH |
10933 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10934 | struct intel_unpin_work *work; | |
6b95a207 KH |
10935 | unsigned long flags; |
10936 | ||
10937 | /* Ignore early vblank irqs */ | |
10938 | if (intel_crtc == NULL) | |
10939 | return; | |
10940 | ||
f326038a DV |
10941 | /* |
10942 | * This is called both by irq handlers and the reset code (to complete | |
10943 | * lost pageflips) so needs the full irqsave spinlocks. | |
10944 | */ | |
6b95a207 KH |
10945 | spin_lock_irqsave(&dev->event_lock, flags); |
10946 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10947 | |
10948 | /* Ensure we don't miss a work->pending update ... */ | |
10949 | smp_rmb(); | |
10950 | ||
10951 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10952 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10953 | return; | |
10954 | } | |
10955 | ||
d6bbafa1 | 10956 | page_flip_completed(intel_crtc); |
0af7e4df | 10957 | |
6b95a207 | 10958 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10959 | } |
10960 | ||
1afe3e9d JB |
10961 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10962 | { | |
fbee40df | 10963 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10964 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10965 | ||
49b14a5c | 10966 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10967 | } |
10968 | ||
10969 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10970 | { | |
fbee40df | 10971 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10972 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10973 | ||
49b14a5c | 10974 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10975 | } |
10976 | ||
75f7f3ec VS |
10977 | /* Is 'a' after or equal to 'b'? */ |
10978 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10979 | { | |
10980 | return !((a - b) & 0x80000000); | |
10981 | } | |
10982 | ||
10983 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10984 | { | |
10985 | struct drm_device *dev = crtc->base.dev; | |
10986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10987 | ||
bdfa7542 VS |
10988 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10989 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10990 | return true; | |
10991 | ||
75f7f3ec VS |
10992 | /* |
10993 | * The relevant registers doen't exist on pre-ctg. | |
10994 | * As the flip done interrupt doesn't trigger for mmio | |
10995 | * flips on gmch platforms, a flip count check isn't | |
10996 | * really needed there. But since ctg has the registers, | |
10997 | * include it in the check anyway. | |
10998 | */ | |
10999 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11000 | return true; | |
11001 | ||
11002 | /* | |
11003 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11004 | * used the same base address. In that case the mmio flip might | |
11005 | * have completed, but the CS hasn't even executed the flip yet. | |
11006 | * | |
11007 | * A flip count check isn't enough as the CS might have updated | |
11008 | * the base address just after start of vblank, but before we | |
11009 | * managed to process the interrupt. This means we'd complete the | |
11010 | * CS flip too soon. | |
11011 | * | |
11012 | * Combining both checks should get us a good enough result. It may | |
11013 | * still happen that the CS flip has been executed, but has not | |
11014 | * yet actually completed. But in case the base address is the same | |
11015 | * anyway, we don't really care. | |
11016 | */ | |
11017 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11018 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 11019 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
11020 | crtc->unpin_work->flip_count); |
11021 | } | |
11022 | ||
6b95a207 KH |
11023 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
11024 | { | |
fbee40df | 11025 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
11026 | struct intel_crtc *intel_crtc = |
11027 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
11028 | unsigned long flags; | |
11029 | ||
f326038a DV |
11030 | |
11031 | /* | |
11032 | * This is called both by irq handlers and the reset code (to complete | |
11033 | * lost pageflips) so needs the full irqsave spinlocks. | |
11034 | * | |
11035 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
11036 | * generate a page-flip completion irq, i.e. every modeset |
11037 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
11038 | */ | |
6b95a207 | 11039 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 11040 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 11041 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
11042 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11043 | } | |
11044 | ||
6042639c | 11045 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
11046 | { |
11047 | /* Ensure that the work item is consistent when activating it ... */ | |
11048 | smp_wmb(); | |
6042639c | 11049 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11050 | /* and that it is marked active as soon as the irq could fire. */ |
11051 | smp_wmb(); | |
11052 | } | |
11053 | ||
8c9f3aaf JB |
11054 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11055 | struct drm_crtc *crtc, | |
11056 | struct drm_framebuffer *fb, | |
ed8d1975 | 11057 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11058 | struct drm_i915_gem_request *req, |
ed8d1975 | 11059 | uint32_t flags) |
8c9f3aaf | 11060 | { |
6258fbe2 | 11061 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11062 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11063 | u32 flip_mask; |
11064 | int ret; | |
11065 | ||
5fb9de1a | 11066 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11067 | if (ret) |
4fa62c89 | 11068 | return ret; |
8c9f3aaf JB |
11069 | |
11070 | /* Can't queue multiple flips, so wait for the previous | |
11071 | * one to finish before executing the next. | |
11072 | */ | |
11073 | if (intel_crtc->plane) | |
11074 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11075 | else | |
11076 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11077 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11078 | intel_ring_emit(ring, MI_NOOP); | |
11079 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11080 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11081 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11082 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11083 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11084 | |
6042639c | 11085 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11086 | return 0; |
8c9f3aaf JB |
11087 | } |
11088 | ||
11089 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11090 | struct drm_crtc *crtc, | |
11091 | struct drm_framebuffer *fb, | |
ed8d1975 | 11092 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11093 | struct drm_i915_gem_request *req, |
ed8d1975 | 11094 | uint32_t flags) |
8c9f3aaf | 11095 | { |
6258fbe2 | 11096 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11097 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11098 | u32 flip_mask; |
11099 | int ret; | |
11100 | ||
5fb9de1a | 11101 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11102 | if (ret) |
4fa62c89 | 11103 | return ret; |
8c9f3aaf JB |
11104 | |
11105 | if (intel_crtc->plane) | |
11106 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11107 | else | |
11108 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11109 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11110 | intel_ring_emit(ring, MI_NOOP); | |
11111 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11112 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11113 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11114 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11115 | intel_ring_emit(ring, MI_NOOP); |
11116 | ||
6042639c | 11117 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11118 | return 0; |
8c9f3aaf JB |
11119 | } |
11120 | ||
11121 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11122 | struct drm_crtc *crtc, | |
11123 | struct drm_framebuffer *fb, | |
ed8d1975 | 11124 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11125 | struct drm_i915_gem_request *req, |
ed8d1975 | 11126 | uint32_t flags) |
8c9f3aaf | 11127 | { |
6258fbe2 | 11128 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11129 | struct drm_i915_private *dev_priv = dev->dev_private; |
11130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11131 | uint32_t pf, pipesrc; | |
11132 | int ret; | |
11133 | ||
5fb9de1a | 11134 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11135 | if (ret) |
4fa62c89 | 11136 | return ret; |
8c9f3aaf JB |
11137 | |
11138 | /* i965+ uses the linear or tiled offsets from the | |
11139 | * Display Registers (which do not change across a page-flip) | |
11140 | * so we need only reprogram the base address. | |
11141 | */ | |
6d90c952 DV |
11142 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11143 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11144 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11145 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11146 | obj->tiling_mode); |
8c9f3aaf JB |
11147 | |
11148 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11149 | * untested on non-native modes, so ignore it for now. | |
11150 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11151 | */ | |
11152 | pf = 0; | |
11153 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11154 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11155 | |
6042639c | 11156 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11157 | return 0; |
8c9f3aaf JB |
11158 | } |
11159 | ||
11160 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11161 | struct drm_crtc *crtc, | |
11162 | struct drm_framebuffer *fb, | |
ed8d1975 | 11163 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11164 | struct drm_i915_gem_request *req, |
ed8d1975 | 11165 | uint32_t flags) |
8c9f3aaf | 11166 | { |
6258fbe2 | 11167 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11168 | struct drm_i915_private *dev_priv = dev->dev_private; |
11169 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11170 | uint32_t pf, pipesrc; | |
11171 | int ret; | |
11172 | ||
5fb9de1a | 11173 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11174 | if (ret) |
4fa62c89 | 11175 | return ret; |
8c9f3aaf | 11176 | |
6d90c952 DV |
11177 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11178 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11179 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11180 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11181 | |
dc257cf1 DV |
11182 | /* Contrary to the suggestions in the documentation, |
11183 | * "Enable Panel Fitter" does not seem to be required when page | |
11184 | * flipping with a non-native mode, and worse causes a normal | |
11185 | * modeset to fail. | |
11186 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11187 | */ | |
11188 | pf = 0; | |
8c9f3aaf | 11189 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11190 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11191 | |
6042639c | 11192 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11193 | return 0; |
8c9f3aaf JB |
11194 | } |
11195 | ||
7c9017e5 JB |
11196 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11197 | struct drm_crtc *crtc, | |
11198 | struct drm_framebuffer *fb, | |
ed8d1975 | 11199 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11200 | struct drm_i915_gem_request *req, |
ed8d1975 | 11201 | uint32_t flags) |
7c9017e5 | 11202 | { |
6258fbe2 | 11203 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11204 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11205 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11206 | int len, ret; |
11207 | ||
eba905b2 | 11208 | switch (intel_crtc->plane) { |
cb05d8de DV |
11209 | case PLANE_A: |
11210 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11211 | break; | |
11212 | case PLANE_B: | |
11213 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11214 | break; | |
11215 | case PLANE_C: | |
11216 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11217 | break; | |
11218 | default: | |
11219 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11220 | return -ENODEV; |
cb05d8de DV |
11221 | } |
11222 | ||
ffe74d75 | 11223 | len = 4; |
f476828a | 11224 | if (ring->id == RCS) { |
ffe74d75 | 11225 | len += 6; |
f476828a DL |
11226 | /* |
11227 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11228 | * 48bits addresses, and we need a NOOP for the batch size to | |
11229 | * stay even. | |
11230 | */ | |
11231 | if (IS_GEN8(dev)) | |
11232 | len += 2; | |
11233 | } | |
ffe74d75 | 11234 | |
f66fab8e VS |
11235 | /* |
11236 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11237 | * "The full packet must be contained within the same cache line." | |
11238 | * | |
11239 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11240 | * cacheline, if we ever start emitting more commands before | |
11241 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11242 | * then do the cacheline alignment, and finally emit the | |
11243 | * MI_DISPLAY_FLIP. | |
11244 | */ | |
bba09b12 | 11245 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11246 | if (ret) |
4fa62c89 | 11247 | return ret; |
f66fab8e | 11248 | |
5fb9de1a | 11249 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11250 | if (ret) |
4fa62c89 | 11251 | return ret; |
7c9017e5 | 11252 | |
ffe74d75 CW |
11253 | /* Unmask the flip-done completion message. Note that the bspec says that |
11254 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11255 | * more than one flip event at any time (or ensure that one flip message | |
11256 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11257 | * Experimentation says that BCS works despite DERRMR masking all | |
11258 | * flip-done completion events and that unmasking all planes at once | |
11259 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11260 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11261 | */ | |
11262 | if (ring->id == RCS) { | |
11263 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11264 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11265 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11266 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11267 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11268 | if (IS_GEN8(dev)) |
f1afe24f | 11269 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11270 | MI_SRM_LRM_GLOBAL_GTT); |
11271 | else | |
f1afe24f | 11272 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11273 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11274 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11275 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11276 | if (IS_GEN8(dev)) { |
11277 | intel_ring_emit(ring, 0); | |
11278 | intel_ring_emit(ring, MI_NOOP); | |
11279 | } | |
ffe74d75 CW |
11280 | } |
11281 | ||
cb05d8de | 11282 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11283 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11284 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11285 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11286 | |
6042639c | 11287 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11288 | return 0; |
7c9017e5 JB |
11289 | } |
11290 | ||
84c33a64 SG |
11291 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11292 | struct drm_i915_gem_object *obj) | |
11293 | { | |
11294 | /* | |
11295 | * This is not being used for older platforms, because | |
11296 | * non-availability of flip done interrupt forces us to use | |
11297 | * CS flips. Older platforms derive flip done using some clever | |
11298 | * tricks involving the flip_pending status bits and vblank irqs. | |
11299 | * So using MMIO flips there would disrupt this mechanism. | |
11300 | */ | |
11301 | ||
8e09bf83 CW |
11302 | if (ring == NULL) |
11303 | return true; | |
11304 | ||
84c33a64 SG |
11305 | if (INTEL_INFO(ring->dev)->gen < 5) |
11306 | return false; | |
11307 | ||
11308 | if (i915.use_mmio_flip < 0) | |
11309 | return false; | |
11310 | else if (i915.use_mmio_flip > 0) | |
11311 | return true; | |
14bf993e OM |
11312 | else if (i915.enable_execlists) |
11313 | return true; | |
fd8e058a AG |
11314 | else if (obj->base.dma_buf && |
11315 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11316 | false)) | |
11317 | return true; | |
84c33a64 | 11318 | else |
b4716185 | 11319 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11320 | } |
11321 | ||
6042639c | 11322 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11323 | unsigned int rotation, |
6042639c | 11324 | struct intel_unpin_work *work) |
ff944564 DL |
11325 | { |
11326 | struct drm_device *dev = intel_crtc->base.dev; | |
11327 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11328 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11329 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11330 | u32 ctl, stride, tile_height; |
ff944564 DL |
11331 | |
11332 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11333 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11334 | switch (fb->modifier[0]) { |
11335 | case DRM_FORMAT_MOD_NONE: | |
11336 | break; | |
11337 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11338 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11339 | break; |
11340 | case I915_FORMAT_MOD_Y_TILED: | |
11341 | ctl |= PLANE_CTL_TILED_Y; | |
11342 | break; | |
11343 | case I915_FORMAT_MOD_Yf_TILED: | |
11344 | ctl |= PLANE_CTL_TILED_YF; | |
11345 | break; | |
11346 | default: | |
11347 | MISSING_CASE(fb->modifier[0]); | |
11348 | } | |
ff944564 DL |
11349 | |
11350 | /* | |
11351 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11352 | * linear buffers or in number of tiles for tiled buffers. | |
11353 | */ | |
86efe24a TU |
11354 | if (intel_rotation_90_or_270(rotation)) { |
11355 | /* stride = Surface height in tiles */ | |
832be82f | 11356 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11357 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11358 | } else { | |
11359 | stride = fb->pitches[0] / | |
7b49f948 VS |
11360 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11361 | fb->pixel_format); | |
86efe24a | 11362 | } |
ff944564 DL |
11363 | |
11364 | /* | |
11365 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11366 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11367 | */ | |
11368 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11369 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11370 | ||
6042639c | 11371 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11372 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11373 | } | |
11374 | ||
6042639c CW |
11375 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11376 | struct intel_unpin_work *work) | |
84c33a64 SG |
11377 | { |
11378 | struct drm_device *dev = intel_crtc->base.dev; | |
11379 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11380 | struct intel_framebuffer *intel_fb = | |
11381 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11382 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11383 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11384 | u32 dspcntr; |
84c33a64 | 11385 | |
84c33a64 SG |
11386 | dspcntr = I915_READ(reg); |
11387 | ||
c5d97472 DL |
11388 | if (obj->tiling_mode != I915_TILING_NONE) |
11389 | dspcntr |= DISPPLANE_TILED; | |
11390 | else | |
11391 | dspcntr &= ~DISPPLANE_TILED; | |
11392 | ||
84c33a64 SG |
11393 | I915_WRITE(reg, dspcntr); |
11394 | ||
6042639c | 11395 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11396 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11397 | } |
11398 | ||
11399 | /* | |
11400 | * XXX: This is the temporary way to update the plane registers until we get | |
11401 | * around to using the usual plane update functions for MMIO flips | |
11402 | */ | |
6042639c | 11403 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11404 | { |
6042639c CW |
11405 | struct intel_crtc *crtc = mmio_flip->crtc; |
11406 | struct intel_unpin_work *work; | |
11407 | ||
11408 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11409 | work = crtc->unpin_work; | |
11410 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11411 | if (work == NULL) | |
11412 | return; | |
ff944564 | 11413 | |
6042639c | 11414 | intel_mark_page_flip_active(work); |
ff944564 | 11415 | |
6042639c | 11416 | intel_pipe_update_start(crtc); |
ff944564 | 11417 | |
6042639c | 11418 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11419 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11420 | else |
11421 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11422 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11423 | |
6042639c | 11424 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11425 | } |
11426 | ||
9362c7c5 | 11427 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11428 | { |
b2cfe0ab CW |
11429 | struct intel_mmio_flip *mmio_flip = |
11430 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11431 | struct intel_framebuffer *intel_fb = |
11432 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11433 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11434 | |
6042639c | 11435 | if (mmio_flip->req) { |
eed29a5b | 11436 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11437 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11438 | false, NULL, |
11439 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11440 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11441 | } | |
84c33a64 | 11442 | |
fd8e058a AG |
11443 | /* For framebuffer backed by dmabuf, wait for fence */ |
11444 | if (obj->base.dma_buf) | |
11445 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11446 | false, false, | |
11447 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11448 | ||
6042639c | 11449 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11450 | kfree(mmio_flip); |
84c33a64 SG |
11451 | } |
11452 | ||
11453 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11454 | struct drm_crtc *crtc, | |
86efe24a | 11455 | struct drm_i915_gem_object *obj) |
84c33a64 | 11456 | { |
b2cfe0ab CW |
11457 | struct intel_mmio_flip *mmio_flip; |
11458 | ||
11459 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11460 | if (mmio_flip == NULL) | |
11461 | return -ENOMEM; | |
84c33a64 | 11462 | |
bcafc4e3 | 11463 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11464 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11465 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11466 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11467 | |
b2cfe0ab CW |
11468 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11469 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11470 | |
84c33a64 SG |
11471 | return 0; |
11472 | } | |
11473 | ||
8c9f3aaf JB |
11474 | static int intel_default_queue_flip(struct drm_device *dev, |
11475 | struct drm_crtc *crtc, | |
11476 | struct drm_framebuffer *fb, | |
ed8d1975 | 11477 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11478 | struct drm_i915_gem_request *req, |
ed8d1975 | 11479 | uint32_t flags) |
8c9f3aaf JB |
11480 | { |
11481 | return -ENODEV; | |
11482 | } | |
11483 | ||
d6bbafa1 CW |
11484 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11485 | struct drm_crtc *crtc) | |
11486 | { | |
11487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11488 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11489 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11490 | u32 addr; | |
11491 | ||
11492 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11493 | return true; | |
11494 | ||
908565c2 CW |
11495 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11496 | return false; | |
11497 | ||
d6bbafa1 CW |
11498 | if (!work->enable_stall_check) |
11499 | return false; | |
11500 | ||
11501 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11502 | if (work->flip_queued_req && |
11503 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11504 | return false; |
11505 | ||
1e3feefd | 11506 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11507 | } |
11508 | ||
1e3feefd | 11509 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11510 | return false; |
11511 | ||
11512 | /* Potential stall - if we see that the flip has happened, | |
11513 | * assume a missed interrupt. */ | |
11514 | if (INTEL_INFO(dev)->gen >= 4) | |
11515 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11516 | else | |
11517 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11518 | ||
11519 | /* There is a potential issue here with a false positive after a flip | |
11520 | * to the same address. We could address this by checking for a | |
11521 | * non-incrementing frame counter. | |
11522 | */ | |
11523 | return addr == work->gtt_offset; | |
11524 | } | |
11525 | ||
11526 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11527 | { | |
11528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11529 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11530 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11531 | struct intel_unpin_work *work; |
f326038a | 11532 | |
6c51d46f | 11533 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11534 | |
11535 | if (crtc == NULL) | |
11536 | return; | |
11537 | ||
f326038a | 11538 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11539 | work = intel_crtc->unpin_work; |
11540 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11541 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11542 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11543 | page_flip_completed(intel_crtc); |
6ad790c0 | 11544 | work = NULL; |
d6bbafa1 | 11545 | } |
6ad790c0 CW |
11546 | if (work != NULL && |
11547 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11548 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11549 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11550 | } |
11551 | ||
6b95a207 KH |
11552 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11553 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11554 | struct drm_pending_vblank_event *event, |
11555 | uint32_t page_flip_flags) | |
6b95a207 KH |
11556 | { |
11557 | struct drm_device *dev = crtc->dev; | |
11558 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11559 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11560 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11561 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11562 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11563 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11564 | struct intel_unpin_work *work; |
a4872ba6 | 11565 | struct intel_engine_cs *ring; |
cf5d8a46 | 11566 | bool mmio_flip; |
91af127f | 11567 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11568 | int ret; |
6b95a207 | 11569 | |
2ff8fde1 MR |
11570 | /* |
11571 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11572 | * check to be safe. In the future we may enable pageflipping from | |
11573 | * a disabled primary plane. | |
11574 | */ | |
11575 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11576 | return -EBUSY; | |
11577 | ||
e6a595d2 | 11578 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11579 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11580 | return -EINVAL; |
11581 | ||
11582 | /* | |
11583 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11584 | * Note that pitch changes could also affect these register. | |
11585 | */ | |
11586 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11587 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11588 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11589 | return -EINVAL; |
11590 | ||
f900db47 CW |
11591 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11592 | goto out_hang; | |
11593 | ||
b14c5679 | 11594 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11595 | if (work == NULL) |
11596 | return -ENOMEM; | |
11597 | ||
6b95a207 | 11598 | work->event = event; |
b4a98e57 | 11599 | work->crtc = crtc; |
ab8d6675 | 11600 | work->old_fb = old_fb; |
6b95a207 KH |
11601 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11602 | ||
87b6b101 | 11603 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11604 | if (ret) |
11605 | goto free_work; | |
11606 | ||
6b95a207 | 11607 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11608 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11609 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11610 | /* Before declaring the flip queue wedged, check if |
11611 | * the hardware completed the operation behind our backs. | |
11612 | */ | |
11613 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11614 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11615 | page_flip_completed(intel_crtc); | |
11616 | } else { | |
11617 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11618 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11619 | |
d6bbafa1 CW |
11620 | drm_crtc_vblank_put(crtc); |
11621 | kfree(work); | |
11622 | return -EBUSY; | |
11623 | } | |
6b95a207 KH |
11624 | } |
11625 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11626 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11627 | |
b4a98e57 CW |
11628 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11629 | flush_workqueue(dev_priv->wq); | |
11630 | ||
75dfca80 | 11631 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11632 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11633 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11634 | |
f4510a27 | 11635 | crtc->primary->fb = fb; |
afd65eb4 | 11636 | update_state_fb(crtc->primary); |
e8216e50 | 11637 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11638 | |
e1f99ce6 | 11639 | work->pending_flip_obj = obj; |
e1f99ce6 | 11640 | |
89ed88ba CW |
11641 | ret = i915_mutex_lock_interruptible(dev); |
11642 | if (ret) | |
11643 | goto cleanup; | |
11644 | ||
b4a98e57 | 11645 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11646 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11647 | |
75f7f3ec | 11648 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11649 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11650 | |
666a4537 | 11651 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11652 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11653 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11654 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11655 | ring = NULL; | |
48bf5b2d | 11656 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11657 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11658 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11659 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11660 | if (ring == NULL || ring->id != RCS) |
11661 | ring = &dev_priv->ring[BCS]; | |
11662 | } else { | |
11663 | ring = &dev_priv->ring[RCS]; | |
11664 | } | |
11665 | ||
cf5d8a46 CW |
11666 | mmio_flip = use_mmio_flip(ring, obj); |
11667 | ||
11668 | /* When using CS flips, we want to emit semaphores between rings. | |
11669 | * However, when using mmio flips we will create a task to do the | |
11670 | * synchronisation, so all we want here is to pin the framebuffer | |
11671 | * into the display plane and skip any waits. | |
11672 | */ | |
7580d774 ML |
11673 | if (!mmio_flip) { |
11674 | ret = i915_gem_object_sync(obj, ring, &request); | |
11675 | if (ret) | |
11676 | goto cleanup_pending; | |
11677 | } | |
11678 | ||
82bc3b2d | 11679 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
7580d774 | 11680 | crtc->primary->state); |
8c9f3aaf JB |
11681 | if (ret) |
11682 | goto cleanup_pending; | |
6b95a207 | 11683 | |
dedf278c TU |
11684 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11685 | obj, 0); | |
11686 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11687 | |
cf5d8a46 | 11688 | if (mmio_flip) { |
86efe24a | 11689 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11690 | if (ret) |
11691 | goto cleanup_unpin; | |
11692 | ||
f06cc1b9 JH |
11693 | i915_gem_request_assign(&work->flip_queued_req, |
11694 | obj->last_write_req); | |
d6bbafa1 | 11695 | } else { |
6258fbe2 | 11696 | if (!request) { |
26827088 DG |
11697 | request = i915_gem_request_alloc(ring, NULL); |
11698 | if (IS_ERR(request)) { | |
11699 | ret = PTR_ERR(request); | |
6258fbe2 | 11700 | goto cleanup_unpin; |
26827088 | 11701 | } |
6258fbe2 JH |
11702 | } |
11703 | ||
11704 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11705 | page_flip_flags); |
11706 | if (ret) | |
11707 | goto cleanup_unpin; | |
11708 | ||
6258fbe2 | 11709 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11710 | } |
11711 | ||
91af127f | 11712 | if (request) |
75289874 | 11713 | i915_add_request_no_flush(request); |
91af127f | 11714 | |
1e3feefd | 11715 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11716 | work->enable_stall_check = true; |
4fa62c89 | 11717 | |
ab8d6675 | 11718 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11719 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11720 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11721 | |
a9ff8714 VS |
11722 | intel_frontbuffer_flip_prepare(dev, |
11723 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11724 | |
e5510fac JB |
11725 | trace_i915_flip_request(intel_crtc->plane, obj); |
11726 | ||
6b95a207 | 11727 | return 0; |
96b099fd | 11728 | |
4fa62c89 | 11729 | cleanup_unpin: |
82bc3b2d | 11730 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11731 | cleanup_pending: |
0aa498d5 | 11732 | if (!IS_ERR_OR_NULL(request)) |
91af127f | 11733 | i915_gem_request_cancel(request); |
b4a98e57 | 11734 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11735 | mutex_unlock(&dev->struct_mutex); |
11736 | cleanup: | |
f4510a27 | 11737 | crtc->primary->fb = old_fb; |
afd65eb4 | 11738 | update_state_fb(crtc->primary); |
89ed88ba CW |
11739 | |
11740 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11741 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11742 | |
5e2d7afc | 11743 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11744 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11745 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11746 | |
87b6b101 | 11747 | drm_crtc_vblank_put(crtc); |
7317c75e | 11748 | free_work: |
96b099fd CW |
11749 | kfree(work); |
11750 | ||
f900db47 | 11751 | if (ret == -EIO) { |
02e0efb5 ML |
11752 | struct drm_atomic_state *state; |
11753 | struct drm_plane_state *plane_state; | |
11754 | ||
f900db47 | 11755 | out_hang: |
02e0efb5 ML |
11756 | state = drm_atomic_state_alloc(dev); |
11757 | if (!state) | |
11758 | return -ENOMEM; | |
11759 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11760 | ||
11761 | retry: | |
11762 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11763 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11764 | if (!ret) { | |
11765 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11766 | ||
11767 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11768 | if (!ret) | |
11769 | ret = drm_atomic_commit(state); | |
11770 | } | |
11771 | ||
11772 | if (ret == -EDEADLK) { | |
11773 | drm_modeset_backoff(state->acquire_ctx); | |
11774 | drm_atomic_state_clear(state); | |
11775 | goto retry; | |
11776 | } | |
11777 | ||
11778 | if (ret) | |
11779 | drm_atomic_state_free(state); | |
11780 | ||
f0d3dad3 | 11781 | if (ret == 0 && event) { |
5e2d7afc | 11782 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11783 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11784 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11785 | } |
f900db47 | 11786 | } |
96b099fd | 11787 | return ret; |
6b95a207 KH |
11788 | } |
11789 | ||
da20eabd ML |
11790 | |
11791 | /** | |
11792 | * intel_wm_need_update - Check whether watermarks need updating | |
11793 | * @plane: drm plane | |
11794 | * @state: new plane state | |
11795 | * | |
11796 | * Check current plane state versus the new one to determine whether | |
11797 | * watermarks need to be recalculated. | |
11798 | * | |
11799 | * Returns true or false. | |
11800 | */ | |
11801 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11802 | struct drm_plane_state *state) | |
11803 | { | |
d21fbe87 MR |
11804 | struct intel_plane_state *new = to_intel_plane_state(state); |
11805 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11806 | ||
11807 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11808 | if (new->visible != cur->visible) |
11809 | return true; | |
11810 | ||
11811 | if (!cur->base.fb || !new->base.fb) | |
11812 | return false; | |
11813 | ||
11814 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11815 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11816 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11817 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11818 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11819 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11820 | return true; |
7809e5ae | 11821 | |
2791a16c | 11822 | return false; |
7809e5ae MR |
11823 | } |
11824 | ||
d21fbe87 MR |
11825 | static bool needs_scaling(struct intel_plane_state *state) |
11826 | { | |
11827 | int src_w = drm_rect_width(&state->src) >> 16; | |
11828 | int src_h = drm_rect_height(&state->src) >> 16; | |
11829 | int dst_w = drm_rect_width(&state->dst); | |
11830 | int dst_h = drm_rect_height(&state->dst); | |
11831 | ||
11832 | return (src_w != dst_w || src_h != dst_h); | |
11833 | } | |
11834 | ||
da20eabd ML |
11835 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11836 | struct drm_plane_state *plane_state) | |
11837 | { | |
ab1d3a0e | 11838 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11839 | struct drm_crtc *crtc = crtc_state->crtc; |
11840 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11841 | struct drm_plane *plane = plane_state->plane; | |
11842 | struct drm_device *dev = crtc->dev; | |
da20eabd ML |
11843 | struct intel_plane_state *old_plane_state = |
11844 | to_intel_plane_state(plane->state); | |
11845 | int idx = intel_crtc->base.base.id, ret; | |
11846 | int i = drm_plane_index(plane); | |
11847 | bool mode_changed = needs_modeset(crtc_state); | |
11848 | bool was_crtc_enabled = crtc->state->active; | |
11849 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11850 | bool turn_off, turn_on, visible, was_visible; |
11851 | struct drm_framebuffer *fb = plane_state->fb; | |
11852 | ||
11853 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11854 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11855 | ret = skl_update_scaler_plane( | |
11856 | to_intel_crtc_state(crtc_state), | |
11857 | to_intel_plane_state(plane_state)); | |
11858 | if (ret) | |
11859 | return ret; | |
11860 | } | |
11861 | ||
da20eabd ML |
11862 | was_visible = old_plane_state->visible; |
11863 | visible = to_intel_plane_state(plane_state)->visible; | |
11864 | ||
11865 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11866 | was_visible = false; | |
11867 | ||
35c08f43 ML |
11868 | /* |
11869 | * Visibility is calculated as if the crtc was on, but | |
11870 | * after scaler setup everything depends on it being off | |
11871 | * when the crtc isn't active. | |
11872 | */ | |
11873 | if (!is_crtc_enabled) | |
11874 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11875 | |
11876 | if (!was_visible && !visible) | |
11877 | return 0; | |
11878 | ||
11879 | turn_off = was_visible && (!visible || mode_changed); | |
11880 | turn_on = visible && (!was_visible || mode_changed); | |
11881 | ||
11882 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11883 | plane->base.id, fb ? fb->base.id : -1); | |
11884 | ||
11885 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11886 | plane->base.id, was_visible, visible, | |
11887 | turn_off, turn_on, mode_changed); | |
11888 | ||
92826fcd ML |
11889 | if (turn_on || turn_off) { |
11890 | pipe_config->wm_changed = true; | |
11891 | ||
852eb00d VS |
11892 | /* must disable cxsr around plane enable/disable */ |
11893 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11894 | if (is_crtc_enabled) | |
11895 | intel_crtc->atomic.wait_vblank = true; | |
ab1d3a0e | 11896 | pipe_config->disable_cxsr = true; |
852eb00d VS |
11897 | } |
11898 | } else if (intel_wm_need_update(plane, plane_state)) { | |
92826fcd | 11899 | pipe_config->wm_changed = true; |
852eb00d | 11900 | } |
da20eabd | 11901 | |
8be6ca85 | 11902 | if (visible || was_visible) |
a9ff8714 VS |
11903 | intel_crtc->atomic.fb_bits |= |
11904 | to_intel_plane(plane)->frontbuffer_bit; | |
11905 | ||
da20eabd ML |
11906 | switch (plane->type) { |
11907 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd | 11908 | intel_crtc->atomic.post_enable_primary = turn_on; |
fcf38d13 | 11909 | intel_crtc->atomic.update_fbc = true; |
da20eabd | 11910 | |
da20eabd ML |
11911 | /* |
11912 | * BDW signals flip done immediately if the plane | |
11913 | * is disabled, even if the plane enable is already | |
11914 | * armed to occur at the next vblank :( | |
11915 | */ | |
11916 | if (turn_on && IS_BROADWELL(dev)) | |
11917 | intel_crtc->atomic.wait_vblank = true; | |
11918 | ||
da20eabd ML |
11919 | break; |
11920 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11921 | break; |
11922 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
11923 | /* |
11924 | * WaCxSRDisabledForSpriteScaling:ivb | |
11925 | * | |
11926 | * cstate->update_wm was already set above, so this flag will | |
11927 | * take effect when we commit and program watermarks. | |
11928 | */ | |
11929 | if (IS_IVYBRIDGE(dev) && | |
11930 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11931 | !needs_scaling(old_plane_state)) { | |
11932 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; | |
11933 | } else if (turn_off && !mode_changed) { | |
da20eabd ML |
11934 | intel_crtc->atomic.wait_vblank = true; |
11935 | intel_crtc->atomic.update_sprite_watermarks |= | |
11936 | 1 << i; | |
11937 | } | |
d21fbe87 MR |
11938 | |
11939 | break; | |
da20eabd ML |
11940 | } |
11941 | return 0; | |
11942 | } | |
11943 | ||
6d3a1ce7 ML |
11944 | static bool encoders_cloneable(const struct intel_encoder *a, |
11945 | const struct intel_encoder *b) | |
11946 | { | |
11947 | /* masks could be asymmetric, so check both ways */ | |
11948 | return a == b || (a->cloneable & (1 << b->type) && | |
11949 | b->cloneable & (1 << a->type)); | |
11950 | } | |
11951 | ||
11952 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11953 | struct intel_crtc *crtc, | |
11954 | struct intel_encoder *encoder) | |
11955 | { | |
11956 | struct intel_encoder *source_encoder; | |
11957 | struct drm_connector *connector; | |
11958 | struct drm_connector_state *connector_state; | |
11959 | int i; | |
11960 | ||
11961 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11962 | if (connector_state->crtc != &crtc->base) | |
11963 | continue; | |
11964 | ||
11965 | source_encoder = | |
11966 | to_intel_encoder(connector_state->best_encoder); | |
11967 | if (!encoders_cloneable(encoder, source_encoder)) | |
11968 | return false; | |
11969 | } | |
11970 | ||
11971 | return true; | |
11972 | } | |
11973 | ||
11974 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11975 | struct intel_crtc *crtc) | |
11976 | { | |
11977 | struct intel_encoder *encoder; | |
11978 | struct drm_connector *connector; | |
11979 | struct drm_connector_state *connector_state; | |
11980 | int i; | |
11981 | ||
11982 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11983 | if (connector_state->crtc != &crtc->base) | |
11984 | continue; | |
11985 | ||
11986 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11987 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11988 | return false; | |
11989 | } | |
11990 | ||
11991 | return true; | |
11992 | } | |
11993 | ||
11994 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11995 | struct drm_crtc_state *crtc_state) | |
11996 | { | |
cf5a15be | 11997 | struct drm_device *dev = crtc->dev; |
ad421372 | 11998 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11999 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12000 | struct intel_crtc_state *pipe_config = |
12001 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12002 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12003 | int ret; |
6d3a1ce7 ML |
12004 | bool mode_changed = needs_modeset(crtc_state); |
12005 | ||
12006 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
12007 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12008 | return -EINVAL; | |
12009 | } | |
12010 | ||
852eb00d | 12011 | if (mode_changed && !crtc_state->active) |
92826fcd | 12012 | pipe_config->wm_changed = true; |
eddfcbcd | 12013 | |
ad421372 ML |
12014 | if (mode_changed && crtc_state->enable && |
12015 | dev_priv->display.crtc_compute_clock && | |
12016 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
12017 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
12018 | pipe_config); | |
12019 | if (ret) | |
12020 | return ret; | |
12021 | } | |
12022 | ||
e435d6e5 | 12023 | ret = 0; |
86c8bbbe MR |
12024 | if (dev_priv->display.compute_pipe_wm) { |
12025 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
bf220452 | 12026 | if (ret) |
86c8bbbe MR |
12027 | return ret; |
12028 | } | |
12029 | ||
e435d6e5 ML |
12030 | if (INTEL_INFO(dev)->gen >= 9) { |
12031 | if (mode_changed) | |
12032 | ret = skl_update_scaler_crtc(pipe_config); | |
12033 | ||
12034 | if (!ret) | |
12035 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12036 | pipe_config); | |
12037 | } | |
12038 | ||
12039 | return ret; | |
6d3a1ce7 ML |
12040 | } |
12041 | ||
65b38e0d | 12042 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
12043 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
12044 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
12045 | .atomic_begin = intel_begin_crtc_commit, |
12046 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12047 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12048 | }; |
12049 | ||
d29b2f9d ACO |
12050 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12051 | { | |
12052 | struct intel_connector *connector; | |
12053 | ||
12054 | for_each_intel_connector(dev, connector) { | |
12055 | if (connector->base.encoder) { | |
12056 | connector->base.state->best_encoder = | |
12057 | connector->base.encoder; | |
12058 | connector->base.state->crtc = | |
12059 | connector->base.encoder->crtc; | |
12060 | } else { | |
12061 | connector->base.state->best_encoder = NULL; | |
12062 | connector->base.state->crtc = NULL; | |
12063 | } | |
12064 | } | |
12065 | } | |
12066 | ||
050f7aeb | 12067 | static void |
eba905b2 | 12068 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12069 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12070 | { |
12071 | int bpp = pipe_config->pipe_bpp; | |
12072 | ||
12073 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12074 | connector->base.base.id, | |
c23cc417 | 12075 | connector->base.name); |
050f7aeb DV |
12076 | |
12077 | /* Don't use an invalid EDID bpc value */ | |
12078 | if (connector->base.display_info.bpc && | |
12079 | connector->base.display_info.bpc * 3 < bpp) { | |
12080 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12081 | bpp, connector->base.display_info.bpc*3); | |
12082 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12083 | } | |
12084 | ||
013dd9e0 JN |
12085 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12086 | if (connector->base.display_info.bpc == 0) { | |
12087 | int type = connector->base.connector_type; | |
12088 | int clamp_bpp = 24; | |
12089 | ||
12090 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12091 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12092 | type == DRM_MODE_CONNECTOR_eDP) | |
12093 | clamp_bpp = 18; | |
12094 | ||
12095 | if (bpp > clamp_bpp) { | |
12096 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12097 | bpp, clamp_bpp); | |
12098 | pipe_config->pipe_bpp = clamp_bpp; | |
12099 | } | |
050f7aeb DV |
12100 | } |
12101 | } | |
12102 | ||
4e53c2e0 | 12103 | static int |
050f7aeb | 12104 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12105 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12106 | { |
050f7aeb | 12107 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12108 | struct drm_atomic_state *state; |
da3ced29 ACO |
12109 | struct drm_connector *connector; |
12110 | struct drm_connector_state *connector_state; | |
1486017f | 12111 | int bpp, i; |
4e53c2e0 | 12112 | |
666a4537 | 12113 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12114 | bpp = 10*3; |
d328c9d7 DV |
12115 | else if (INTEL_INFO(dev)->gen >= 5) |
12116 | bpp = 12*3; | |
12117 | else | |
12118 | bpp = 8*3; | |
12119 | ||
4e53c2e0 | 12120 | |
4e53c2e0 DV |
12121 | pipe_config->pipe_bpp = bpp; |
12122 | ||
1486017f ACO |
12123 | state = pipe_config->base.state; |
12124 | ||
4e53c2e0 | 12125 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12126 | for_each_connector_in_state(state, connector, connector_state, i) { |
12127 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12128 | continue; |
12129 | ||
da3ced29 ACO |
12130 | connected_sink_compute_bpp(to_intel_connector(connector), |
12131 | pipe_config); | |
4e53c2e0 DV |
12132 | } |
12133 | ||
12134 | return bpp; | |
12135 | } | |
12136 | ||
644db711 DV |
12137 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12138 | { | |
12139 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12140 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12141 | mode->crtc_clock, |
644db711 DV |
12142 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12143 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12144 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12145 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12146 | } | |
12147 | ||
c0b03411 | 12148 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12149 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12150 | const char *context) |
12151 | { | |
6a60cd87 CK |
12152 | struct drm_device *dev = crtc->base.dev; |
12153 | struct drm_plane *plane; | |
12154 | struct intel_plane *intel_plane; | |
12155 | struct intel_plane_state *state; | |
12156 | struct drm_framebuffer *fb; | |
12157 | ||
12158 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12159 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12160 | |
12161 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12162 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12163 | pipe_config->pipe_bpp, pipe_config->dither); | |
12164 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12165 | pipe_config->has_pch_encoder, | |
12166 | pipe_config->fdi_lanes, | |
12167 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12168 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12169 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12170 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12171 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12172 | pipe_config->lane_count, |
eb14cb74 VS |
12173 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12174 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12175 | pipe_config->dp_m_n.tu); | |
b95af8be | 12176 | |
90a6b7b0 | 12177 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12178 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12179 | pipe_config->lane_count, |
b95af8be VK |
12180 | pipe_config->dp_m2_n2.gmch_m, |
12181 | pipe_config->dp_m2_n2.gmch_n, | |
12182 | pipe_config->dp_m2_n2.link_m, | |
12183 | pipe_config->dp_m2_n2.link_n, | |
12184 | pipe_config->dp_m2_n2.tu); | |
12185 | ||
55072d19 DV |
12186 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12187 | pipe_config->has_audio, | |
12188 | pipe_config->has_infoframe); | |
12189 | ||
c0b03411 | 12190 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12191 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12192 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12193 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12194 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12195 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12196 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12197 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12198 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12199 | crtc->num_scalers, | |
12200 | pipe_config->scaler_state.scaler_users, | |
12201 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12202 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12203 | pipe_config->gmch_pfit.control, | |
12204 | pipe_config->gmch_pfit.pgm_ratios, | |
12205 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12206 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12207 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12208 | pipe_config->pch_pfit.size, |
12209 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12210 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12211 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12212 | |
415ff0f6 | 12213 | if (IS_BROXTON(dev)) { |
05712c15 | 12214 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12215 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12216 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12217 | pipe_config->ddi_pll_sel, |
12218 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12219 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12220 | pipe_config->dpll_hw_state.pll0, |
12221 | pipe_config->dpll_hw_state.pll1, | |
12222 | pipe_config->dpll_hw_state.pll2, | |
12223 | pipe_config->dpll_hw_state.pll3, | |
12224 | pipe_config->dpll_hw_state.pll6, | |
12225 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12226 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12227 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12228 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12229 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12230 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12231 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12232 | pipe_config->ddi_pll_sel, | |
12233 | pipe_config->dpll_hw_state.ctrl1, | |
12234 | pipe_config->dpll_hw_state.cfgcr1, | |
12235 | pipe_config->dpll_hw_state.cfgcr2); | |
12236 | } else if (HAS_DDI(dev)) { | |
00490c22 | 12237 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12238 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12239 | pipe_config->dpll_hw_state.wrpll, |
12240 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12241 | } else { |
12242 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12243 | "fp0: 0x%x, fp1: 0x%x\n", | |
12244 | pipe_config->dpll_hw_state.dpll, | |
12245 | pipe_config->dpll_hw_state.dpll_md, | |
12246 | pipe_config->dpll_hw_state.fp0, | |
12247 | pipe_config->dpll_hw_state.fp1); | |
12248 | } | |
12249 | ||
6a60cd87 CK |
12250 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12251 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12252 | intel_plane = to_intel_plane(plane); | |
12253 | if (intel_plane->pipe != crtc->pipe) | |
12254 | continue; | |
12255 | ||
12256 | state = to_intel_plane_state(plane->state); | |
12257 | fb = state->base.fb; | |
12258 | if (!fb) { | |
12259 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12260 | "disabled, scaler_id = %d\n", | |
12261 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12262 | plane->base.id, intel_plane->pipe, | |
12263 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12264 | drm_plane_index(plane), state->scaler_id); | |
12265 | continue; | |
12266 | } | |
12267 | ||
12268 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12269 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12270 | plane->base.id, intel_plane->pipe, | |
12271 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12272 | drm_plane_index(plane)); | |
12273 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12274 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12275 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12276 | state->scaler_id, | |
12277 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12278 | drm_rect_width(&state->src) >> 16, | |
12279 | drm_rect_height(&state->src) >> 16, | |
12280 | state->dst.x1, state->dst.y1, | |
12281 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12282 | } | |
c0b03411 DV |
12283 | } |
12284 | ||
5448a00d | 12285 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12286 | { |
5448a00d | 12287 | struct drm_device *dev = state->dev; |
da3ced29 | 12288 | struct drm_connector *connector; |
00f0b378 VS |
12289 | unsigned int used_ports = 0; |
12290 | ||
12291 | /* | |
12292 | * Walk the connector list instead of the encoder | |
12293 | * list to detect the problem on ddi platforms | |
12294 | * where there's just one encoder per digital port. | |
12295 | */ | |
0bff4858 VS |
12296 | drm_for_each_connector(connector, dev) { |
12297 | struct drm_connector_state *connector_state; | |
12298 | struct intel_encoder *encoder; | |
12299 | ||
12300 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12301 | if (!connector_state) | |
12302 | connector_state = connector->state; | |
12303 | ||
5448a00d | 12304 | if (!connector_state->best_encoder) |
00f0b378 VS |
12305 | continue; |
12306 | ||
5448a00d ACO |
12307 | encoder = to_intel_encoder(connector_state->best_encoder); |
12308 | ||
12309 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12310 | |
12311 | switch (encoder->type) { | |
12312 | unsigned int port_mask; | |
12313 | case INTEL_OUTPUT_UNKNOWN: | |
12314 | if (WARN_ON(!HAS_DDI(dev))) | |
12315 | break; | |
12316 | case INTEL_OUTPUT_DISPLAYPORT: | |
12317 | case INTEL_OUTPUT_HDMI: | |
12318 | case INTEL_OUTPUT_EDP: | |
12319 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12320 | ||
12321 | /* the same port mustn't appear more than once */ | |
12322 | if (used_ports & port_mask) | |
12323 | return false; | |
12324 | ||
12325 | used_ports |= port_mask; | |
12326 | default: | |
12327 | break; | |
12328 | } | |
12329 | } | |
12330 | ||
12331 | return true; | |
12332 | } | |
12333 | ||
83a57153 ACO |
12334 | static void |
12335 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12336 | { | |
12337 | struct drm_crtc_state tmp_state; | |
663a3640 | 12338 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12339 | struct intel_dpll_hw_state dpll_hw_state; |
12340 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12341 | uint32_t ddi_pll_sel; |
c4e2d043 | 12342 | bool force_thru; |
83a57153 | 12343 | |
7546a384 ACO |
12344 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12345 | * kzalloc'd. Code that depends on any field being zero should be | |
12346 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12347 | * only fields that are know to not cause problems are preserved. */ | |
12348 | ||
83a57153 | 12349 | tmp_state = crtc_state->base; |
663a3640 | 12350 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12351 | shared_dpll = crtc_state->shared_dpll; |
12352 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12353 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12354 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12355 | |
83a57153 | 12356 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12357 | |
83a57153 | 12358 | crtc_state->base = tmp_state; |
663a3640 | 12359 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12360 | crtc_state->shared_dpll = shared_dpll; |
12361 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12362 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12363 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12364 | } |
12365 | ||
548ee15b | 12366 | static int |
b8cecdf5 | 12367 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12368 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12369 | { |
b359283a | 12370 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12371 | struct intel_encoder *encoder; |
da3ced29 | 12372 | struct drm_connector *connector; |
0b901879 | 12373 | struct drm_connector_state *connector_state; |
d328c9d7 | 12374 | int base_bpp, ret = -EINVAL; |
0b901879 | 12375 | int i; |
e29c22c0 | 12376 | bool retry = true; |
ee7b9f93 | 12377 | |
83a57153 | 12378 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12379 | |
e143a21c DV |
12380 | pipe_config->cpu_transcoder = |
12381 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12382 | |
2960bc9c ID |
12383 | /* |
12384 | * Sanitize sync polarity flags based on requested ones. If neither | |
12385 | * positive or negative polarity is requested, treat this as meaning | |
12386 | * negative polarity. | |
12387 | */ | |
2d112de7 | 12388 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12389 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12390 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12391 | |
2d112de7 | 12392 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12393 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12394 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12395 | |
d328c9d7 DV |
12396 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12397 | pipe_config); | |
12398 | if (base_bpp < 0) | |
4e53c2e0 DV |
12399 | goto fail; |
12400 | ||
e41a56be VS |
12401 | /* |
12402 | * Determine the real pipe dimensions. Note that stereo modes can | |
12403 | * increase the actual pipe size due to the frame doubling and | |
12404 | * insertion of additional space for blanks between the frame. This | |
12405 | * is stored in the crtc timings. We use the requested mode to do this | |
12406 | * computation to clearly distinguish it from the adjusted mode, which | |
12407 | * can be changed by the connectors in the below retry loop. | |
12408 | */ | |
2d112de7 | 12409 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12410 | &pipe_config->pipe_src_w, |
12411 | &pipe_config->pipe_src_h); | |
e41a56be | 12412 | |
e29c22c0 | 12413 | encoder_retry: |
ef1b460d | 12414 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12415 | pipe_config->port_clock = 0; |
ef1b460d | 12416 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12417 | |
135c81b8 | 12418 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12419 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12420 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12421 | |
7758a113 DV |
12422 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12423 | * adjust it according to limitations or connector properties, and also | |
12424 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12425 | */ |
da3ced29 | 12426 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12427 | if (connector_state->crtc != crtc) |
7758a113 | 12428 | continue; |
7ae89233 | 12429 | |
0b901879 ACO |
12430 | encoder = to_intel_encoder(connector_state->best_encoder); |
12431 | ||
efea6e8e DV |
12432 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12433 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12434 | goto fail; |
12435 | } | |
ee7b9f93 | 12436 | } |
47f1c6c9 | 12437 | |
ff9a6750 DV |
12438 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12439 | * done afterwards in case the encoder adjusts the mode. */ | |
12440 | if (!pipe_config->port_clock) | |
2d112de7 | 12441 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12442 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12443 | |
a43f6e0f | 12444 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12445 | if (ret < 0) { |
7758a113 DV |
12446 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12447 | goto fail; | |
ee7b9f93 | 12448 | } |
e29c22c0 DV |
12449 | |
12450 | if (ret == RETRY) { | |
12451 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12452 | ret = -EINVAL; | |
12453 | goto fail; | |
12454 | } | |
12455 | ||
12456 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12457 | retry = false; | |
12458 | goto encoder_retry; | |
12459 | } | |
12460 | ||
e8fa4270 DV |
12461 | /* Dithering seems to not pass-through bits correctly when it should, so |
12462 | * only enable it on 6bpc panels. */ | |
12463 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12464 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12465 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12466 | |
7758a113 | 12467 | fail: |
548ee15b | 12468 | return ret; |
ee7b9f93 | 12469 | } |
47f1c6c9 | 12470 | |
ea9d758d | 12471 | static void |
4740b0f2 | 12472 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12473 | { |
0a9ab303 ACO |
12474 | struct drm_crtc *crtc; |
12475 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12476 | int i; |
ea9d758d | 12477 | |
7668851f | 12478 | /* Double check state. */ |
8a75d157 | 12479 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12480 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12481 | |
12482 | /* Update hwmode for vblank functions */ | |
12483 | if (crtc->state->active) | |
12484 | crtc->hwmode = crtc->state->adjusted_mode; | |
12485 | else | |
12486 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12487 | |
12488 | /* | |
12489 | * Update legacy state to satisfy fbc code. This can | |
12490 | * be removed when fbc uses the atomic state. | |
12491 | */ | |
12492 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12493 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12494 | ||
12495 | crtc->primary->fb = plane_state->fb; | |
12496 | crtc->x = plane_state->src_x >> 16; | |
12497 | crtc->y = plane_state->src_y >> 16; | |
12498 | } | |
ea9d758d | 12499 | } |
ea9d758d DV |
12500 | } |
12501 | ||
3bd26263 | 12502 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12503 | { |
3bd26263 | 12504 | int diff; |
f1f644dc JB |
12505 | |
12506 | if (clock1 == clock2) | |
12507 | return true; | |
12508 | ||
12509 | if (!clock1 || !clock2) | |
12510 | return false; | |
12511 | ||
12512 | diff = abs(clock1 - clock2); | |
12513 | ||
12514 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12515 | return true; | |
12516 | ||
12517 | return false; | |
12518 | } | |
12519 | ||
25c5b266 DV |
12520 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12521 | list_for_each_entry((intel_crtc), \ | |
12522 | &(dev)->mode_config.crtc_list, \ | |
12523 | base.head) \ | |
95150bdf | 12524 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12525 | |
cfb23ed6 ML |
12526 | static bool |
12527 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12528 | unsigned int m2, unsigned int n2, | |
12529 | bool exact) | |
12530 | { | |
12531 | if (m == m2 && n == n2) | |
12532 | return true; | |
12533 | ||
12534 | if (exact || !m || !n || !m2 || !n2) | |
12535 | return false; | |
12536 | ||
12537 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12538 | ||
31d10b57 ML |
12539 | if (n > n2) { |
12540 | while (n > n2) { | |
cfb23ed6 ML |
12541 | m2 <<= 1; |
12542 | n2 <<= 1; | |
12543 | } | |
31d10b57 ML |
12544 | } else if (n < n2) { |
12545 | while (n < n2) { | |
cfb23ed6 ML |
12546 | m <<= 1; |
12547 | n <<= 1; | |
12548 | } | |
12549 | } | |
12550 | ||
31d10b57 ML |
12551 | if (n != n2) |
12552 | return false; | |
12553 | ||
12554 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12555 | } |
12556 | ||
12557 | static bool | |
12558 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12559 | struct intel_link_m_n *m2_n2, | |
12560 | bool adjust) | |
12561 | { | |
12562 | if (m_n->tu == m2_n2->tu && | |
12563 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12564 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12565 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12566 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12567 | if (adjust) | |
12568 | *m2_n2 = *m_n; | |
12569 | ||
12570 | return true; | |
12571 | } | |
12572 | ||
12573 | return false; | |
12574 | } | |
12575 | ||
0e8ffe1b | 12576 | static bool |
2fa2fe9a | 12577 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12578 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12579 | struct intel_crtc_state *pipe_config, |
12580 | bool adjust) | |
0e8ffe1b | 12581 | { |
cfb23ed6 ML |
12582 | bool ret = true; |
12583 | ||
12584 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12585 | do { \ | |
12586 | if (!adjust) \ | |
12587 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12588 | else \ | |
12589 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12590 | } while (0) | |
12591 | ||
66e985c0 DV |
12592 | #define PIPE_CONF_CHECK_X(name) \ |
12593 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12594 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12595 | "(expected 0x%08x, found 0x%08x)\n", \ |
12596 | current_config->name, \ | |
12597 | pipe_config->name); \ | |
cfb23ed6 | 12598 | ret = false; \ |
66e985c0 DV |
12599 | } |
12600 | ||
08a24034 DV |
12601 | #define PIPE_CONF_CHECK_I(name) \ |
12602 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12603 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12604 | "(expected %i, found %i)\n", \ |
12605 | current_config->name, \ | |
12606 | pipe_config->name); \ | |
cfb23ed6 ML |
12607 | ret = false; \ |
12608 | } | |
12609 | ||
12610 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12611 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12612 | &pipe_config->name,\ | |
12613 | adjust)) { \ | |
12614 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12615 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12616 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12617 | current_config->name.tu, \ | |
12618 | current_config->name.gmch_m, \ | |
12619 | current_config->name.gmch_n, \ | |
12620 | current_config->name.link_m, \ | |
12621 | current_config->name.link_n, \ | |
12622 | pipe_config->name.tu, \ | |
12623 | pipe_config->name.gmch_m, \ | |
12624 | pipe_config->name.gmch_n, \ | |
12625 | pipe_config->name.link_m, \ | |
12626 | pipe_config->name.link_n); \ | |
12627 | ret = false; \ | |
12628 | } | |
12629 | ||
12630 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12631 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12632 | &pipe_config->name, adjust) && \ | |
12633 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12634 | &pipe_config->name, adjust)) { \ | |
12635 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12636 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12637 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12638 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12639 | current_config->name.tu, \ | |
12640 | current_config->name.gmch_m, \ | |
12641 | current_config->name.gmch_n, \ | |
12642 | current_config->name.link_m, \ | |
12643 | current_config->name.link_n, \ | |
12644 | current_config->alt_name.tu, \ | |
12645 | current_config->alt_name.gmch_m, \ | |
12646 | current_config->alt_name.gmch_n, \ | |
12647 | current_config->alt_name.link_m, \ | |
12648 | current_config->alt_name.link_n, \ | |
12649 | pipe_config->name.tu, \ | |
12650 | pipe_config->name.gmch_m, \ | |
12651 | pipe_config->name.gmch_n, \ | |
12652 | pipe_config->name.link_m, \ | |
12653 | pipe_config->name.link_n); \ | |
12654 | ret = false; \ | |
88adfff1 DV |
12655 | } |
12656 | ||
b95af8be VK |
12657 | /* This is required for BDW+ where there is only one set of registers for |
12658 | * switching between high and low RR. | |
12659 | * This macro can be used whenever a comparison has to be made between one | |
12660 | * hw state and multiple sw state variables. | |
12661 | */ | |
12662 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12663 | if ((current_config->name != pipe_config->name) && \ | |
12664 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12665 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12666 | "(expected %i or %i, found %i)\n", \ |
12667 | current_config->name, \ | |
12668 | current_config->alt_name, \ | |
12669 | pipe_config->name); \ | |
cfb23ed6 | 12670 | ret = false; \ |
b95af8be VK |
12671 | } |
12672 | ||
1bd1bd80 DV |
12673 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12674 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12675 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12676 | "(expected %i, found %i)\n", \ |
12677 | current_config->name & (mask), \ | |
12678 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12679 | ret = false; \ |
1bd1bd80 DV |
12680 | } |
12681 | ||
5e550656 VS |
12682 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12683 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12684 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12685 | "(expected %i, found %i)\n", \ |
12686 | current_config->name, \ | |
12687 | pipe_config->name); \ | |
cfb23ed6 | 12688 | ret = false; \ |
5e550656 VS |
12689 | } |
12690 | ||
bb760063 DV |
12691 | #define PIPE_CONF_QUIRK(quirk) \ |
12692 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12693 | ||
eccb140b DV |
12694 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12695 | ||
08a24034 DV |
12696 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12697 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12698 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12699 | |
eb14cb74 | 12700 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12701 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12702 | |
12703 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12704 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12705 | ||
cfb23ed6 ML |
12706 | if (current_config->has_drrs) |
12707 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12708 | } else | |
12709 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12710 | |
a65347ba JN |
12711 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12712 | ||
2d112de7 ACO |
12713 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12714 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12715 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12716 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12717 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12718 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12719 | |
2d112de7 ACO |
12720 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12721 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12722 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12723 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12724 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12725 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12726 | |
c93f54cf | 12727 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12728 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12729 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12730 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12731 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12732 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12733 | |
9ed109a7 DV |
12734 | PIPE_CONF_CHECK_I(has_audio); |
12735 | ||
2d112de7 | 12736 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12737 | DRM_MODE_FLAG_INTERLACE); |
12738 | ||
bb760063 | 12739 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12740 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12741 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12742 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12743 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12744 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12745 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12746 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12747 | DRM_MODE_FLAG_NVSYNC); |
12748 | } | |
045ac3b5 | 12749 | |
333b8ca8 | 12750 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12751 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12752 | if (INTEL_INFO(dev)->gen < 4) | |
12753 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12754 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12755 | |
bfd16b2a ML |
12756 | if (!adjust) { |
12757 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12758 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12759 | ||
12760 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12761 | if (current_config->pch_pfit.enabled) { | |
12762 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12763 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12764 | } | |
2fa2fe9a | 12765 | |
7aefe2b5 ML |
12766 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12767 | } | |
a1b2278e | 12768 | |
e59150dc JB |
12769 | /* BDW+ don't expose a synchronous way to read the state */ |
12770 | if (IS_HASWELL(dev)) | |
12771 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12772 | |
282740f7 VS |
12773 | PIPE_CONF_CHECK_I(double_wide); |
12774 | ||
26804afd DV |
12775 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12776 | ||
c0d43d62 | 12777 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12778 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12779 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12780 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12781 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12782 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12783 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12784 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12785 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12786 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12787 | |
42571aef VS |
12788 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12789 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12790 | ||
2d112de7 | 12791 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12792 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12793 | |
66e985c0 | 12794 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12795 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12796 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12797 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12798 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12799 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12800 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12801 | |
cfb23ed6 | 12802 | return ret; |
0e8ffe1b DV |
12803 | } |
12804 | ||
08db6652 DL |
12805 | static void check_wm_state(struct drm_device *dev) |
12806 | { | |
12807 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12808 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12809 | struct intel_crtc *intel_crtc; | |
12810 | int plane; | |
12811 | ||
12812 | if (INTEL_INFO(dev)->gen < 9) | |
12813 | return; | |
12814 | ||
12815 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12816 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12817 | ||
12818 | for_each_intel_crtc(dev, intel_crtc) { | |
12819 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12820 | const enum pipe pipe = intel_crtc->pipe; | |
12821 | ||
12822 | if (!intel_crtc->active) | |
12823 | continue; | |
12824 | ||
12825 | /* planes */ | |
dd740780 | 12826 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12827 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12828 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12829 | ||
12830 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12831 | continue; | |
12832 | ||
12833 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12834 | "(expected (%u,%u), found (%u,%u))\n", | |
12835 | pipe_name(pipe), plane + 1, | |
12836 | sw_entry->start, sw_entry->end, | |
12837 | hw_entry->start, hw_entry->end); | |
12838 | } | |
12839 | ||
12840 | /* cursor */ | |
4969d33e MR |
12841 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12842 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12843 | |
12844 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12845 | continue; | |
12846 | ||
12847 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12848 | "(expected (%u,%u), found (%u,%u))\n", | |
12849 | pipe_name(pipe), | |
12850 | sw_entry->start, sw_entry->end, | |
12851 | hw_entry->start, hw_entry->end); | |
12852 | } | |
12853 | } | |
12854 | ||
91d1b4bd | 12855 | static void |
35dd3c64 ML |
12856 | check_connector_state(struct drm_device *dev, |
12857 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12858 | { |
35dd3c64 ML |
12859 | struct drm_connector_state *old_conn_state; |
12860 | struct drm_connector *connector; | |
12861 | int i; | |
8af6cf88 | 12862 | |
35dd3c64 ML |
12863 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12864 | struct drm_encoder *encoder = connector->encoder; | |
12865 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12866 | |
8af6cf88 DV |
12867 | /* This also checks the encoder/connector hw state with the |
12868 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12869 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12870 | |
ad3c558f | 12871 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12872 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12873 | } |
91d1b4bd DV |
12874 | } |
12875 | ||
12876 | static void | |
12877 | check_encoder_state(struct drm_device *dev) | |
12878 | { | |
12879 | struct intel_encoder *encoder; | |
12880 | struct intel_connector *connector; | |
8af6cf88 | 12881 | |
b2784e15 | 12882 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12883 | bool enabled = false; |
4d20cd86 | 12884 | enum pipe pipe; |
8af6cf88 DV |
12885 | |
12886 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12887 | encoder->base.base.id, | |
8e329a03 | 12888 | encoder->base.name); |
8af6cf88 | 12889 | |
3a3371ff | 12890 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12891 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12892 | continue; |
12893 | enabled = true; | |
ad3c558f ML |
12894 | |
12895 | I915_STATE_WARN(connector->base.state->crtc != | |
12896 | encoder->base.crtc, | |
12897 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12898 | } |
0e32b39c | 12899 | |
e2c719b7 | 12900 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12901 | "encoder's enabled state mismatch " |
12902 | "(expected %i, found %i)\n", | |
12903 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12904 | |
12905 | if (!encoder->base.crtc) { | |
4d20cd86 | 12906 | bool active; |
7c60d198 | 12907 | |
4d20cd86 ML |
12908 | active = encoder->get_hw_state(encoder, &pipe); |
12909 | I915_STATE_WARN(active, | |
12910 | "encoder detached but still enabled on pipe %c.\n", | |
12911 | pipe_name(pipe)); | |
7c60d198 | 12912 | } |
8af6cf88 | 12913 | } |
91d1b4bd DV |
12914 | } |
12915 | ||
12916 | static void | |
4d20cd86 | 12917 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12918 | { |
fbee40df | 12919 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12920 | struct intel_encoder *encoder; |
4d20cd86 ML |
12921 | struct drm_crtc_state *old_crtc_state; |
12922 | struct drm_crtc *crtc; | |
12923 | int i; | |
8af6cf88 | 12924 | |
4d20cd86 ML |
12925 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12926 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12927 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12928 | bool active; |
8af6cf88 | 12929 | |
bfd16b2a ML |
12930 | if (!needs_modeset(crtc->state) && |
12931 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12932 | continue; |
045ac3b5 | 12933 | |
4d20cd86 ML |
12934 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12935 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12936 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12937 | pipe_config->base.crtc = crtc; | |
12938 | pipe_config->base.state = old_state; | |
8af6cf88 | 12939 | |
4d20cd86 ML |
12940 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12941 | crtc->base.id); | |
8af6cf88 | 12942 | |
4d20cd86 ML |
12943 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12944 | pipe_config); | |
d62cf62a | 12945 | |
b6b5d049 | 12946 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12947 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12948 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12949 | active = crtc->state->active; | |
6c49f241 | 12950 | |
4d20cd86 | 12951 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12952 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12953 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12954 | |
4d20cd86 | 12955 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12956 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12957 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12958 | ||
12959 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12960 | enum pipe pipe; | |
12961 | ||
12962 | active = encoder->get_hw_state(encoder, &pipe); | |
12963 | I915_STATE_WARN(active != crtc->state->active, | |
12964 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12965 | encoder->base.base.id, active, crtc->state->active); | |
12966 | ||
12967 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12968 | "Encoder connected to wrong pipe %c\n", | |
12969 | pipe_name(pipe)); | |
12970 | ||
12971 | if (active) | |
12972 | encoder->get_config(encoder, pipe_config); | |
12973 | } | |
53d9f4e9 | 12974 | |
4d20cd86 | 12975 | if (!crtc->state->active) |
cfb23ed6 ML |
12976 | continue; |
12977 | ||
4d20cd86 ML |
12978 | sw_config = to_intel_crtc_state(crtc->state); |
12979 | if (!intel_pipe_config_compare(dev, sw_config, | |
12980 | pipe_config, false)) { | |
e2c719b7 | 12981 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12982 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12983 | "[hw state]"); |
4d20cd86 | 12984 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12985 | "[sw state]"); |
12986 | } | |
8af6cf88 DV |
12987 | } |
12988 | } | |
12989 | ||
91d1b4bd DV |
12990 | static void |
12991 | check_shared_dpll_state(struct drm_device *dev) | |
12992 | { | |
fbee40df | 12993 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12994 | struct intel_crtc *crtc; |
12995 | struct intel_dpll_hw_state dpll_hw_state; | |
12996 | int i; | |
5358901f DV |
12997 | |
12998 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12999 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13000 | int enabled_crtcs = 0, active_crtcs = 0; | |
13001 | bool active; | |
13002 | ||
13003 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
13004 | ||
13005 | DRM_DEBUG_KMS("%s\n", pll->name); | |
13006 | ||
13007 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
13008 | ||
e2c719b7 | 13009 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 13010 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 13011 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 13012 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 13013 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 13014 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 13015 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 13016 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
13017 | "pll on state mismatch (expected %i, found %i)\n", |
13018 | pll->on, active); | |
13019 | ||
d3fcc808 | 13020 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 13021 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
13022 | enabled_crtcs++; |
13023 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
13024 | active_crtcs++; | |
13025 | } | |
e2c719b7 | 13026 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
13027 | "pll active crtcs mismatch (expected %i, found %i)\n", |
13028 | pll->active, active_crtcs); | |
e2c719b7 | 13029 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 13030 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 13031 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 13032 | |
e2c719b7 | 13033 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
13034 | sizeof(dpll_hw_state)), |
13035 | "pll hw state mismatch\n"); | |
5358901f | 13036 | } |
8af6cf88 DV |
13037 | } |
13038 | ||
ee165b1a ML |
13039 | static void |
13040 | intel_modeset_check_state(struct drm_device *dev, | |
13041 | struct drm_atomic_state *old_state) | |
91d1b4bd | 13042 | { |
08db6652 | 13043 | check_wm_state(dev); |
35dd3c64 | 13044 | check_connector_state(dev, old_state); |
91d1b4bd | 13045 | check_encoder_state(dev); |
4d20cd86 | 13046 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
13047 | check_shared_dpll_state(dev); |
13048 | } | |
13049 | ||
5cec258b | 13050 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
13051 | int dotclock) |
13052 | { | |
13053 | /* | |
13054 | * FDI already provided one idea for the dotclock. | |
13055 | * Yell if the encoder disagrees. | |
13056 | */ | |
2d112de7 | 13057 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 13058 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 13059 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
13060 | } |
13061 | ||
80715b2f VS |
13062 | static void update_scanline_offset(struct intel_crtc *crtc) |
13063 | { | |
13064 | struct drm_device *dev = crtc->base.dev; | |
13065 | ||
13066 | /* | |
13067 | * The scanline counter increments at the leading edge of hsync. | |
13068 | * | |
13069 | * On most platforms it starts counting from vtotal-1 on the | |
13070 | * first active line. That means the scanline counter value is | |
13071 | * always one less than what we would expect. Ie. just after | |
13072 | * start of vblank, which also occurs at start of hsync (on the | |
13073 | * last active line), the scanline counter will read vblank_start-1. | |
13074 | * | |
13075 | * On gen2 the scanline counter starts counting from 1 instead | |
13076 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13077 | * to keep the value positive), instead of adding one. | |
13078 | * | |
13079 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13080 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13081 | * there's an extra 1 line difference. So we need to add two instead of | |
13082 | * one to the value. | |
13083 | */ | |
13084 | if (IS_GEN2(dev)) { | |
124abe07 | 13085 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13086 | int vtotal; |
13087 | ||
124abe07 VS |
13088 | vtotal = adjusted_mode->crtc_vtotal; |
13089 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13090 | vtotal /= 2; |
13091 | ||
13092 | crtc->scanline_offset = vtotal - 1; | |
13093 | } else if (HAS_DDI(dev) && | |
409ee761 | 13094 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13095 | crtc->scanline_offset = 2; |
13096 | } else | |
13097 | crtc->scanline_offset = 1; | |
13098 | } | |
13099 | ||
ad421372 | 13100 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13101 | { |
225da59b | 13102 | struct drm_device *dev = state->dev; |
ed6739ef | 13103 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13104 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13105 | struct drm_crtc *crtc; |
13106 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13107 | int i; |
ed6739ef ACO |
13108 | |
13109 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13110 | return; |
ed6739ef | 13111 | |
0a9ab303 | 13112 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 ML |
13113 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13114 | int old_dpll = to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13115 | |
fb1a38a9 | 13116 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13117 | continue; |
13118 | ||
fb1a38a9 ML |
13119 | to_intel_crtc_state(crtc_state)->shared_dpll = DPLL_ID_PRIVATE; |
13120 | ||
13121 | if (old_dpll == DPLL_ID_PRIVATE) | |
13122 | continue; | |
0a9ab303 | 13123 | |
ad421372 ML |
13124 | if (!shared_dpll) |
13125 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13126 | |
fb1a38a9 | 13127 | shared_dpll[old_dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
ad421372 | 13128 | } |
ed6739ef ACO |
13129 | } |
13130 | ||
99d736a2 ML |
13131 | /* |
13132 | * This implements the workaround described in the "notes" section of the mode | |
13133 | * set sequence documentation. When going from no pipes or single pipe to | |
13134 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13135 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13136 | */ | |
13137 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13138 | { | |
13139 | struct drm_crtc_state *crtc_state; | |
13140 | struct intel_crtc *intel_crtc; | |
13141 | struct drm_crtc *crtc; | |
13142 | struct intel_crtc_state *first_crtc_state = NULL; | |
13143 | struct intel_crtc_state *other_crtc_state = NULL; | |
13144 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13145 | int i; | |
13146 | ||
13147 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13148 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13149 | intel_crtc = to_intel_crtc(crtc); | |
13150 | ||
13151 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13152 | continue; | |
13153 | ||
13154 | if (first_crtc_state) { | |
13155 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13156 | break; | |
13157 | } else { | |
13158 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13159 | first_pipe = intel_crtc->pipe; | |
13160 | } | |
13161 | } | |
13162 | ||
13163 | /* No workaround needed? */ | |
13164 | if (!first_crtc_state) | |
13165 | return 0; | |
13166 | ||
13167 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13168 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13169 | struct intel_crtc_state *pipe_config; | |
13170 | ||
13171 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13172 | if (IS_ERR(pipe_config)) | |
13173 | return PTR_ERR(pipe_config); | |
13174 | ||
13175 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13176 | ||
13177 | if (!pipe_config->base.active || | |
13178 | needs_modeset(&pipe_config->base)) | |
13179 | continue; | |
13180 | ||
13181 | /* 2 or more enabled crtcs means no need for w/a */ | |
13182 | if (enabled_pipe != INVALID_PIPE) | |
13183 | return 0; | |
13184 | ||
13185 | enabled_pipe = intel_crtc->pipe; | |
13186 | } | |
13187 | ||
13188 | if (enabled_pipe != INVALID_PIPE) | |
13189 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13190 | else if (other_crtc_state) | |
13191 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13192 | ||
13193 | return 0; | |
13194 | } | |
13195 | ||
27c329ed ML |
13196 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13197 | { | |
13198 | struct drm_crtc *crtc; | |
13199 | struct drm_crtc_state *crtc_state; | |
13200 | int ret = 0; | |
13201 | ||
13202 | /* add all active pipes to the state */ | |
13203 | for_each_crtc(state->dev, crtc) { | |
13204 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13205 | if (IS_ERR(crtc_state)) | |
13206 | return PTR_ERR(crtc_state); | |
13207 | ||
13208 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13209 | continue; | |
13210 | ||
13211 | crtc_state->mode_changed = true; | |
13212 | ||
13213 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13214 | if (ret) | |
13215 | break; | |
13216 | ||
13217 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13218 | if (ret) | |
13219 | break; | |
13220 | } | |
13221 | ||
13222 | return ret; | |
13223 | } | |
13224 | ||
c347a676 | 13225 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13226 | { |
565602d7 ML |
13227 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13228 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13229 | struct drm_crtc *crtc; | |
13230 | struct drm_crtc_state *crtc_state; | |
13231 | int ret = 0, i; | |
054518dd | 13232 | |
b359283a ML |
13233 | if (!check_digital_port_conflicts(state)) { |
13234 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13235 | return -EINVAL; | |
13236 | } | |
13237 | ||
565602d7 ML |
13238 | intel_state->modeset = true; |
13239 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13240 | ||
13241 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13242 | if (crtc_state->active) | |
13243 | intel_state->active_crtcs |= 1 << i; | |
13244 | else | |
13245 | intel_state->active_crtcs &= ~(1 << i); | |
13246 | } | |
13247 | ||
054518dd ACO |
13248 | /* |
13249 | * See if the config requires any additional preparation, e.g. | |
13250 | * to adjust global state with pipes off. We need to do this | |
13251 | * here so we can get the modeset_pipe updated config for the new | |
13252 | * mode set on this crtc. For other crtcs we need to use the | |
13253 | * adjusted_mode bits in the crtc directly. | |
13254 | */ | |
27c329ed | 13255 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13256 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13257 | ||
1a617b77 | 13258 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13259 | ret = intel_modeset_all_pipes(state); |
13260 | ||
13261 | if (ret < 0) | |
054518dd | 13262 | return ret; |
27c329ed | 13263 | } else |
1a617b77 | 13264 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13265 | |
ad421372 | 13266 | intel_modeset_clear_plls(state); |
054518dd | 13267 | |
565602d7 | 13268 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13269 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13270 | |
ad421372 | 13271 | return 0; |
c347a676 ACO |
13272 | } |
13273 | ||
aa363136 MR |
13274 | /* |
13275 | * Handle calculation of various watermark data at the end of the atomic check | |
13276 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13277 | * handlers to ensure that all derived state has been updated. | |
13278 | */ | |
13279 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13280 | { | |
13281 | struct drm_device *dev = state->dev; | |
13282 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13283 | struct drm_crtc *crtc; | |
13284 | struct drm_crtc_state *cstate; | |
13285 | struct drm_plane *plane; | |
13286 | struct drm_plane_state *pstate; | |
13287 | ||
13288 | /* | |
13289 | * Calculate watermark configuration details now that derived | |
13290 | * plane/crtc state is all properly updated. | |
13291 | */ | |
13292 | drm_for_each_crtc(crtc, dev) { | |
13293 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13294 | crtc->state; | |
13295 | ||
13296 | if (cstate->active) | |
13297 | intel_state->wm_config.num_pipes_active++; | |
13298 | } | |
13299 | drm_for_each_legacy_plane(plane, dev) { | |
13300 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13301 | plane->state; | |
13302 | ||
13303 | if (!to_intel_plane_state(pstate)->visible) | |
13304 | continue; | |
13305 | ||
13306 | intel_state->wm_config.sprites_enabled = true; | |
13307 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13308 | pstate->crtc_h != pstate->src_h >> 16) | |
13309 | intel_state->wm_config.sprites_scaled = true; | |
13310 | } | |
13311 | } | |
13312 | ||
74c090b1 ML |
13313 | /** |
13314 | * intel_atomic_check - validate state object | |
13315 | * @dev: drm device | |
13316 | * @state: state to validate | |
13317 | */ | |
13318 | static int intel_atomic_check(struct drm_device *dev, | |
13319 | struct drm_atomic_state *state) | |
c347a676 | 13320 | { |
dd8b3bdb | 13321 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13322 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13323 | struct drm_crtc *crtc; |
13324 | struct drm_crtc_state *crtc_state; | |
13325 | int ret, i; | |
61333b60 | 13326 | bool any_ms = false; |
c347a676 | 13327 | |
74c090b1 | 13328 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13329 | if (ret) |
13330 | return ret; | |
13331 | ||
c347a676 | 13332 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13333 | struct intel_crtc_state *pipe_config = |
13334 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13335 | |
ba8af3e5 ML |
13336 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13337 | sizeof(struct intel_crtc_atomic_commit)); | |
13338 | ||
1ed51de9 DV |
13339 | /* Catch I915_MODE_FLAG_INHERITED */ |
13340 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13341 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13342 | |
61333b60 ML |
13343 | if (!crtc_state->enable) { |
13344 | if (needs_modeset(crtc_state)) | |
13345 | any_ms = true; | |
c347a676 | 13346 | continue; |
61333b60 | 13347 | } |
c347a676 | 13348 | |
26495481 | 13349 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13350 | continue; |
13351 | ||
26495481 DV |
13352 | /* FIXME: For only active_changed we shouldn't need to do any |
13353 | * state recomputation at all. */ | |
13354 | ||
1ed51de9 DV |
13355 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13356 | if (ret) | |
13357 | return ret; | |
b359283a | 13358 | |
cfb23ed6 | 13359 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13360 | if (ret) |
13361 | return ret; | |
13362 | ||
73831236 | 13363 | if (i915.fastboot && |
dd8b3bdb | 13364 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13365 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13366 | pipe_config, true)) { |
26495481 | 13367 | crtc_state->mode_changed = false; |
bfd16b2a | 13368 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13369 | } |
13370 | ||
13371 | if (needs_modeset(crtc_state)) { | |
13372 | any_ms = true; | |
cfb23ed6 ML |
13373 | |
13374 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13375 | if (ret) | |
13376 | return ret; | |
13377 | } | |
61333b60 | 13378 | |
26495481 DV |
13379 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13380 | needs_modeset(crtc_state) ? | |
13381 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13382 | } |
13383 | ||
61333b60 ML |
13384 | if (any_ms) { |
13385 | ret = intel_modeset_checks(state); | |
13386 | ||
13387 | if (ret) | |
13388 | return ret; | |
27c329ed | 13389 | } else |
dd8b3bdb | 13390 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13391 | |
dd8b3bdb | 13392 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13393 | if (ret) |
13394 | return ret; | |
13395 | ||
f51be2e0 | 13396 | intel_fbc_choose_crtc(dev_priv, state); |
aa363136 MR |
13397 | calc_watermark_data(state); |
13398 | ||
13399 | return 0; | |
054518dd ACO |
13400 | } |
13401 | ||
5008e874 ML |
13402 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13403 | struct drm_atomic_state *state, | |
13404 | bool async) | |
13405 | { | |
7580d774 ML |
13406 | struct drm_i915_private *dev_priv = dev->dev_private; |
13407 | struct drm_plane_state *plane_state; | |
5008e874 | 13408 | struct drm_crtc_state *crtc_state; |
7580d774 | 13409 | struct drm_plane *plane; |
5008e874 ML |
13410 | struct drm_crtc *crtc; |
13411 | int i, ret; | |
13412 | ||
13413 | if (async) { | |
13414 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13415 | return -EINVAL; | |
13416 | } | |
13417 | ||
13418 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13419 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13420 | if (ret) | |
13421 | return ret; | |
7580d774 ML |
13422 | |
13423 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13424 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13425 | } |
13426 | ||
f935675f ML |
13427 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13428 | if (ret) | |
13429 | return ret; | |
13430 | ||
5008e874 | 13431 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13432 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13433 | u32 reset_counter; | |
13434 | ||
13435 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13436 | mutex_unlock(&dev->struct_mutex); | |
13437 | ||
13438 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13439 | struct intel_plane_state *intel_plane_state = | |
13440 | to_intel_plane_state(plane_state); | |
13441 | ||
13442 | if (!intel_plane_state->wait_req) | |
13443 | continue; | |
13444 | ||
13445 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13446 | reset_counter, true, | |
13447 | NULL, NULL); | |
13448 | ||
13449 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13450 | if (ret == -EIO) | |
13451 | ret = 0; | |
13452 | ||
13453 | if (ret) | |
13454 | break; | |
13455 | } | |
13456 | ||
13457 | if (!ret) | |
13458 | return 0; | |
13459 | ||
13460 | mutex_lock(&dev->struct_mutex); | |
13461 | drm_atomic_helper_cleanup_planes(dev, state); | |
13462 | } | |
5008e874 | 13463 | |
f935675f | 13464 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13465 | return ret; |
13466 | } | |
13467 | ||
74c090b1 ML |
13468 | /** |
13469 | * intel_atomic_commit - commit validated state object | |
13470 | * @dev: DRM device | |
13471 | * @state: the top-level driver state object | |
13472 | * @async: asynchronous commit | |
13473 | * | |
13474 | * This function commits a top-level state object that has been validated | |
13475 | * with drm_atomic_helper_check(). | |
13476 | * | |
13477 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13478 | * we can only handle plane-related operations and do not yet support | |
13479 | * asynchronous commit. | |
13480 | * | |
13481 | * RETURNS | |
13482 | * Zero for success or -errno. | |
13483 | */ | |
13484 | static int intel_atomic_commit(struct drm_device *dev, | |
13485 | struct drm_atomic_state *state, | |
13486 | bool async) | |
a6778b3c | 13487 | { |
565602d7 | 13488 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13489 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13490 | struct drm_crtc_state *crtc_state; |
7580d774 | 13491 | struct drm_crtc *crtc; |
565602d7 ML |
13492 | int ret = 0, i; |
13493 | bool hw_check = intel_state->modeset; | |
a6778b3c | 13494 | |
5008e874 | 13495 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13496 | if (ret) { |
13497 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13498 | return ret; |
7580d774 | 13499 | } |
d4afb8cc | 13500 | |
1c5e19f8 | 13501 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13502 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13503 | |
565602d7 ML |
13504 | if (intel_state->modeset) { |
13505 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13506 | sizeof(intel_state->min_pixclk)); | |
13507 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13508 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
565602d7 ML |
13509 | } |
13510 | ||
0a9ab303 | 13511 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13512 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13513 | ||
61333b60 ML |
13514 | if (!needs_modeset(crtc->state)) |
13515 | continue; | |
13516 | ||
5c74cd73 | 13517 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
460da916 | 13518 | |
a539205a ML |
13519 | if (crtc_state->active) { |
13520 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13521 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd | 13522 | intel_crtc->active = false; |
58f9c0bc | 13523 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13524 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13525 | |
13526 | /* | |
13527 | * Underruns don't always raise | |
13528 | * interrupts, so check manually. | |
13529 | */ | |
13530 | intel_check_cpu_fifo_underruns(dev_priv); | |
13531 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13532 | |
13533 | if (!crtc->state->active) | |
13534 | intel_update_watermarks(crtc); | |
a539205a | 13535 | } |
b8cecdf5 | 13536 | } |
7758a113 | 13537 | |
ea9d758d DV |
13538 | /* Only after disabling all output pipelines that will be changed can we |
13539 | * update the the output configuration. */ | |
4740b0f2 | 13540 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13541 | |
565602d7 | 13542 | if (intel_state->modeset) { |
4740b0f2 ML |
13543 | intel_shared_dpll_commit(state); |
13544 | ||
13545 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13546 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13547 | } |
47fab737 | 13548 | |
a6778b3c | 13549 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13550 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13551 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13552 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13553 | bool update_pipe = !modeset && |
13554 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13555 | unsigned long put_domains = 0; | |
f6ac4b2a | 13556 | |
9f836f90 PJ |
13557 | if (modeset) |
13558 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
13559 | ||
f6ac4b2a | 13560 | if (modeset && crtc->state->active) { |
a539205a ML |
13561 | update_scanline_offset(to_intel_crtc(crtc)); |
13562 | dev_priv->display.crtc_enable(crtc); | |
13563 | } | |
80715b2f | 13564 | |
bfd16b2a ML |
13565 | if (update_pipe) { |
13566 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13567 | ||
13568 | /* make sure intel_modeset_check_state runs */ | |
565602d7 | 13569 | hw_check = true; |
bfd16b2a ML |
13570 | } |
13571 | ||
f6ac4b2a | 13572 | if (!modeset) |
5c74cd73 | 13573 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
f6ac4b2a | 13574 | |
49227c4a PZ |
13575 | if (crtc->state->active && intel_crtc->atomic.update_fbc) |
13576 | intel_fbc_enable(intel_crtc); | |
13577 | ||
6173ee28 ML |
13578 | if (crtc->state->active && |
13579 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13580 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13581 | |
13582 | if (put_domains) | |
13583 | modeset_put_power_domains(dev_priv, put_domains); | |
13584 | ||
f6ac4b2a | 13585 | intel_post_plane_update(intel_crtc); |
9f836f90 PJ |
13586 | |
13587 | if (modeset) | |
13588 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
80715b2f | 13589 | } |
a6778b3c | 13590 | |
a6778b3c | 13591 | /* FIXME: add subpixel order */ |
83a57153 | 13592 | |
74c090b1 | 13593 | drm_atomic_helper_wait_for_vblanks(dev, state); |
f935675f ML |
13594 | |
13595 | mutex_lock(&dev->struct_mutex); | |
d4afb8cc | 13596 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13597 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13598 | |
565602d7 | 13599 | if (hw_check) |
ee165b1a ML |
13600 | intel_modeset_check_state(dev, state); |
13601 | ||
13602 | drm_atomic_state_free(state); | |
f30da187 | 13603 | |
75714940 MK |
13604 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13605 | * of triggering bugs in unclaimed access. After we finish | |
13606 | * modesetting, see if an error has been flagged, and if so | |
13607 | * enable debugging for the next modeset - and hope we catch | |
13608 | * the culprit. | |
13609 | * | |
13610 | * XXX note that we assume display power is on at this point. | |
13611 | * This might hold true now but we need to add pm helper to check | |
13612 | * unclaimed only when the hardware is on, as atomic commits | |
13613 | * can happen also when the device is completely off. | |
13614 | */ | |
13615 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13616 | ||
74c090b1 | 13617 | return 0; |
7f27126e JB |
13618 | } |
13619 | ||
c0c36b94 CW |
13620 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13621 | { | |
83a57153 ACO |
13622 | struct drm_device *dev = crtc->dev; |
13623 | struct drm_atomic_state *state; | |
e694eb02 | 13624 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13625 | int ret; |
83a57153 ACO |
13626 | |
13627 | state = drm_atomic_state_alloc(dev); | |
13628 | if (!state) { | |
e694eb02 | 13629 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13630 | crtc->base.id); |
13631 | return; | |
13632 | } | |
13633 | ||
e694eb02 | 13634 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13635 | |
e694eb02 ML |
13636 | retry: |
13637 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13638 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13639 | if (!ret) { | |
13640 | if (!crtc_state->active) | |
13641 | goto out; | |
83a57153 | 13642 | |
e694eb02 | 13643 | crtc_state->mode_changed = true; |
74c090b1 | 13644 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13645 | } |
13646 | ||
e694eb02 ML |
13647 | if (ret == -EDEADLK) { |
13648 | drm_atomic_state_clear(state); | |
13649 | drm_modeset_backoff(state->acquire_ctx); | |
13650 | goto retry; | |
4ed9fb37 | 13651 | } |
4be07317 | 13652 | |
2bfb4627 | 13653 | if (ret) |
e694eb02 | 13654 | out: |
2bfb4627 | 13655 | drm_atomic_state_free(state); |
c0c36b94 CW |
13656 | } |
13657 | ||
25c5b266 DV |
13658 | #undef for_each_intel_crtc_masked |
13659 | ||
f6e5b160 | 13660 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13661 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13662 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13663 | .destroy = intel_crtc_destroy, |
13664 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13665 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13666 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13667 | }; |
13668 | ||
5358901f DV |
13669 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13670 | struct intel_shared_dpll *pll, | |
13671 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13672 | { |
5358901f | 13673 | uint32_t val; |
ee7b9f93 | 13674 | |
f458ebbc | 13675 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13676 | return false; |
13677 | ||
5358901f | 13678 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13679 | hw_state->dpll = val; |
13680 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13681 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13682 | |
13683 | return val & DPLL_VCO_ENABLE; | |
13684 | } | |
13685 | ||
15bdd4cf DV |
13686 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13687 | struct intel_shared_dpll *pll) | |
13688 | { | |
3e369b76 ACO |
13689 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13690 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13691 | } |
13692 | ||
e7b903d2 DV |
13693 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13694 | struct intel_shared_dpll *pll) | |
13695 | { | |
e7b903d2 | 13696 | /* PCH refclock must be enabled first */ |
89eff4be | 13697 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13698 | |
3e369b76 | 13699 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13700 | |
13701 | /* Wait for the clocks to stabilize. */ | |
13702 | POSTING_READ(PCH_DPLL(pll->id)); | |
13703 | udelay(150); | |
13704 | ||
13705 | /* The pixel multiplier can only be updated once the | |
13706 | * DPLL is enabled and the clocks are stable. | |
13707 | * | |
13708 | * So write it again. | |
13709 | */ | |
3e369b76 | 13710 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13711 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13712 | udelay(200); |
13713 | } | |
13714 | ||
13715 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13716 | struct intel_shared_dpll *pll) | |
13717 | { | |
13718 | struct drm_device *dev = dev_priv->dev; | |
13719 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13720 | |
13721 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13722 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13723 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13724 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13725 | } |
13726 | ||
15bdd4cf DV |
13727 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13728 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13729 | udelay(200); |
13730 | } | |
13731 | ||
46edb027 DV |
13732 | static char *ibx_pch_dpll_names[] = { |
13733 | "PCH DPLL A", | |
13734 | "PCH DPLL B", | |
13735 | }; | |
13736 | ||
7c74ade1 | 13737 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13738 | { |
e7b903d2 | 13739 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13740 | int i; |
13741 | ||
7c74ade1 | 13742 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13743 | |
e72f9fbf | 13744 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13745 | dev_priv->shared_dplls[i].id = i; |
13746 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13747 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13748 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13749 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13750 | dev_priv->shared_dplls[i].get_hw_state = |
13751 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13752 | } |
13753 | } | |
13754 | ||
7c74ade1 DV |
13755 | static void intel_shared_dpll_init(struct drm_device *dev) |
13756 | { | |
e7b903d2 | 13757 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13758 | |
9cd86933 DV |
13759 | if (HAS_DDI(dev)) |
13760 | intel_ddi_pll_init(dev); | |
13761 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13762 | ibx_pch_dpll_init(dev); |
13763 | else | |
13764 | dev_priv->num_shared_dpll = 0; | |
13765 | ||
13766 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13767 | } |
13768 | ||
6beb8c23 MR |
13769 | /** |
13770 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13771 | * @plane: drm plane to prepare for | |
13772 | * @fb: framebuffer to prepare for presentation | |
13773 | * | |
13774 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13775 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13776 | * bits. Some older platforms need special physical address handling for | |
13777 | * cursor planes. | |
13778 | * | |
f935675f ML |
13779 | * Must be called with struct_mutex held. |
13780 | * | |
6beb8c23 MR |
13781 | * Returns 0 on success, negative error code on failure. |
13782 | */ | |
13783 | int | |
13784 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13785 | const struct drm_plane_state *new_state) |
465c120c MR |
13786 | { |
13787 | struct drm_device *dev = plane->dev; | |
844f9111 | 13788 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13789 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13790 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13791 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13792 | int ret = 0; |
465c120c | 13793 | |
1ee49399 | 13794 | if (!obj && !old_obj) |
465c120c MR |
13795 | return 0; |
13796 | ||
5008e874 ML |
13797 | if (old_obj) { |
13798 | struct drm_crtc_state *crtc_state = | |
13799 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13800 | ||
13801 | /* Big Hammer, we also need to ensure that any pending | |
13802 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13803 | * current scanout is retired before unpinning the old | |
13804 | * framebuffer. Note that we rely on userspace rendering | |
13805 | * into the buffer attached to the pipe they are waiting | |
13806 | * on. If not, userspace generates a GPU hang with IPEHR | |
13807 | * point to the MI_WAIT_FOR_EVENT. | |
13808 | * | |
13809 | * This should only fail upon a hung GPU, in which case we | |
13810 | * can safely continue. | |
13811 | */ | |
13812 | if (needs_modeset(crtc_state)) | |
13813 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13814 | ||
13815 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13816 | if (ret && ret != -EIO) | |
f935675f | 13817 | return ret; |
5008e874 ML |
13818 | } |
13819 | ||
3c28ff22 AG |
13820 | /* For framebuffer backed by dmabuf, wait for fence */ |
13821 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13822 | long lret; |
13823 | ||
13824 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13825 | false, true, | |
13826 | MAX_SCHEDULE_TIMEOUT); | |
13827 | if (lret == -ERESTARTSYS) | |
13828 | return lret; | |
3c28ff22 | 13829 | |
bcf8be27 | 13830 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13831 | } |
13832 | ||
1ee49399 ML |
13833 | if (!obj) { |
13834 | ret = 0; | |
13835 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13836 | INTEL_INFO(dev)->cursor_needs_physical) { |
13837 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13838 | ret = i915_gem_object_attach_phys(obj, align); | |
13839 | if (ret) | |
13840 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13841 | } else { | |
7580d774 | 13842 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
6beb8c23 | 13843 | } |
465c120c | 13844 | |
7580d774 ML |
13845 | if (ret == 0) { |
13846 | if (obj) { | |
13847 | struct intel_plane_state *plane_state = | |
13848 | to_intel_plane_state(new_state); | |
13849 | ||
13850 | i915_gem_request_assign(&plane_state->wait_req, | |
13851 | obj->last_write_req); | |
13852 | } | |
13853 | ||
a9ff8714 | 13854 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13855 | } |
fdd508a6 | 13856 | |
6beb8c23 MR |
13857 | return ret; |
13858 | } | |
13859 | ||
38f3ce3a MR |
13860 | /** |
13861 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13862 | * @plane: drm plane to clean up for | |
13863 | * @fb: old framebuffer that was on plane | |
13864 | * | |
13865 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13866 | * |
13867 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13868 | */ |
13869 | void | |
13870 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13871 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13872 | { |
13873 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13874 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13875 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13876 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13877 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13878 | |
7580d774 ML |
13879 | old_intel_state = to_intel_plane_state(old_state); |
13880 | ||
1ee49399 | 13881 | if (!obj && !old_obj) |
38f3ce3a MR |
13882 | return; |
13883 | ||
1ee49399 ML |
13884 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13885 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
844f9111 | 13886 | intel_unpin_fb_obj(old_state->fb, old_state); |
1ee49399 ML |
13887 | |
13888 | /* prepare_fb aborted? */ | |
13889 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13890 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13891 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13892 | |
13893 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13894 | ||
465c120c MR |
13895 | } |
13896 | ||
6156a456 CK |
13897 | int |
13898 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13899 | { | |
13900 | int max_scale; | |
13901 | struct drm_device *dev; | |
13902 | struct drm_i915_private *dev_priv; | |
13903 | int crtc_clock, cdclk; | |
13904 | ||
bf8a0af0 | 13905 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13906 | return DRM_PLANE_HELPER_NO_SCALING; |
13907 | ||
13908 | dev = intel_crtc->base.dev; | |
13909 | dev_priv = dev->dev_private; | |
13910 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13911 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13912 | |
54bf1ce6 | 13913 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13914 | return DRM_PLANE_HELPER_NO_SCALING; |
13915 | ||
13916 | /* | |
13917 | * skl max scale is lower of: | |
13918 | * close to 3 but not 3, -1 is for that purpose | |
13919 | * or | |
13920 | * cdclk/crtc_clock | |
13921 | */ | |
13922 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13923 | ||
13924 | return max_scale; | |
13925 | } | |
13926 | ||
465c120c | 13927 | static int |
3c692a41 | 13928 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13929 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13930 | struct intel_plane_state *state) |
13931 | { | |
2b875c22 MR |
13932 | struct drm_crtc *crtc = state->base.crtc; |
13933 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13934 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13935 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13936 | bool can_position = false; | |
465c120c | 13937 | |
693bdc28 VS |
13938 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
13939 | /* use scaler when colorkey is not required */ | |
13940 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13941 | min_scale = 1; | |
13942 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13943 | } | |
d8106366 | 13944 | can_position = true; |
6156a456 | 13945 | } |
d8106366 | 13946 | |
061e4b8d ML |
13947 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13948 | &state->dst, &state->clip, | |
da20eabd ML |
13949 | min_scale, max_scale, |
13950 | can_position, true, | |
13951 | &state->visible); | |
14af293f GP |
13952 | } |
13953 | ||
613d2b27 ML |
13954 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13955 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13956 | { |
32b7eeec | 13957 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13958 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13959 | struct intel_crtc_state *old_intel_state = |
13960 | to_intel_crtc_state(old_crtc_state); | |
13961 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13962 | |
c34c9ee4 | 13963 | /* Perform vblank evasion around commit operation */ |
62852622 | 13964 | intel_pipe_update_start(intel_crtc); |
0583236e | 13965 | |
bfd16b2a ML |
13966 | if (modeset) |
13967 | return; | |
13968 | ||
13969 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13970 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13971 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13972 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13973 | } |
13974 | ||
613d2b27 ML |
13975 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13976 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13977 | { |
32b7eeec | 13978 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13979 | |
62852622 | 13980 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13981 | } |
13982 | ||
cf4c7c12 | 13983 | /** |
4a3b8769 MR |
13984 | * intel_plane_destroy - destroy a plane |
13985 | * @plane: plane to destroy | |
cf4c7c12 | 13986 | * |
4a3b8769 MR |
13987 | * Common destruction function for all types of planes (primary, cursor, |
13988 | * sprite). | |
cf4c7c12 | 13989 | */ |
4a3b8769 | 13990 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13991 | { |
13992 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13993 | drm_plane_cleanup(plane); | |
13994 | kfree(intel_plane); | |
13995 | } | |
13996 | ||
65a3fea0 | 13997 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13998 | .update_plane = drm_atomic_helper_update_plane, |
13999 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14000 | .destroy = intel_plane_destroy, |
c196e1d6 | 14001 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14002 | .atomic_get_property = intel_plane_atomic_get_property, |
14003 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14004 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14005 | .atomic_destroy_state = intel_plane_destroy_state, | |
14006 | ||
465c120c MR |
14007 | }; |
14008 | ||
14009 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14010 | int pipe) | |
14011 | { | |
14012 | struct intel_plane *primary; | |
8e7d688b | 14013 | struct intel_plane_state *state; |
465c120c | 14014 | const uint32_t *intel_primary_formats; |
45e3743a | 14015 | unsigned int num_formats; |
465c120c MR |
14016 | |
14017 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
14018 | if (primary == NULL) | |
14019 | return NULL; | |
14020 | ||
8e7d688b MR |
14021 | state = intel_create_plane_state(&primary->base); |
14022 | if (!state) { | |
ea2c67bb MR |
14023 | kfree(primary); |
14024 | return NULL; | |
14025 | } | |
8e7d688b | 14026 | primary->base.state = &state->base; |
ea2c67bb | 14027 | |
465c120c MR |
14028 | primary->can_scale = false; |
14029 | primary->max_downscale = 1; | |
6156a456 CK |
14030 | if (INTEL_INFO(dev)->gen >= 9) { |
14031 | primary->can_scale = true; | |
af99ceda | 14032 | state->scaler_id = -1; |
6156a456 | 14033 | } |
465c120c MR |
14034 | primary->pipe = pipe; |
14035 | primary->plane = pipe; | |
a9ff8714 | 14036 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14037 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14038 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14039 | primary->plane = !pipe; | |
14040 | ||
6c0fd451 DL |
14041 | if (INTEL_INFO(dev)->gen >= 9) { |
14042 | intel_primary_formats = skl_primary_formats; | |
14043 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14044 | |
14045 | primary->update_plane = skylake_update_primary_plane; | |
14046 | primary->disable_plane = skylake_disable_primary_plane; | |
14047 | } else if (HAS_PCH_SPLIT(dev)) { | |
14048 | intel_primary_formats = i965_primary_formats; | |
14049 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14050 | ||
14051 | primary->update_plane = ironlake_update_primary_plane; | |
14052 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14053 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14054 | intel_primary_formats = i965_primary_formats; |
14055 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14056 | |
14057 | primary->update_plane = i9xx_update_primary_plane; | |
14058 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14059 | } else { |
14060 | intel_primary_formats = i8xx_primary_formats; | |
14061 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14062 | |
14063 | primary->update_plane = i9xx_update_primary_plane; | |
14064 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14065 | } |
14066 | ||
14067 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14068 | &intel_plane_funcs, |
465c120c | 14069 | intel_primary_formats, num_formats, |
b0b3b795 | 14070 | DRM_PLANE_TYPE_PRIMARY, NULL); |
48404c1e | 14071 | |
3b7a5119 SJ |
14072 | if (INTEL_INFO(dev)->gen >= 4) |
14073 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14074 | |
ea2c67bb MR |
14075 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14076 | ||
465c120c MR |
14077 | return &primary->base; |
14078 | } | |
14079 | ||
3b7a5119 SJ |
14080 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14081 | { | |
14082 | if (!dev->mode_config.rotation_property) { | |
14083 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14084 | BIT(DRM_ROTATE_180); | |
14085 | ||
14086 | if (INTEL_INFO(dev)->gen >= 9) | |
14087 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14088 | ||
14089 | dev->mode_config.rotation_property = | |
14090 | drm_mode_create_rotation_property(dev, flags); | |
14091 | } | |
14092 | if (dev->mode_config.rotation_property) | |
14093 | drm_object_attach_property(&plane->base.base, | |
14094 | dev->mode_config.rotation_property, | |
14095 | plane->base.state->rotation); | |
14096 | } | |
14097 | ||
3d7d6510 | 14098 | static int |
852e787c | 14099 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14100 | struct intel_crtc_state *crtc_state, |
852e787c | 14101 | struct intel_plane_state *state) |
3d7d6510 | 14102 | { |
061e4b8d | 14103 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14104 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14105 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14106 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14107 | unsigned stride; |
14108 | int ret; | |
3d7d6510 | 14109 | |
061e4b8d ML |
14110 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14111 | &state->dst, &state->clip, | |
3d7d6510 MR |
14112 | DRM_PLANE_HELPER_NO_SCALING, |
14113 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14114 | true, true, &state->visible); |
757f9a3e GP |
14115 | if (ret) |
14116 | return ret; | |
14117 | ||
757f9a3e GP |
14118 | /* if we want to turn off the cursor ignore width and height */ |
14119 | if (!obj) | |
da20eabd | 14120 | return 0; |
757f9a3e | 14121 | |
757f9a3e | 14122 | /* Check for which cursor types we support */ |
061e4b8d | 14123 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14124 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14125 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14126 | return -EINVAL; |
14127 | } | |
14128 | ||
ea2c67bb MR |
14129 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14130 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14131 | DRM_DEBUG_KMS("buffer is too small\n"); |
14132 | return -ENOMEM; | |
14133 | } | |
14134 | ||
3a656b54 | 14135 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14136 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14137 | return -EINVAL; |
32b7eeec MR |
14138 | } |
14139 | ||
b29ec92c VS |
14140 | /* |
14141 | * There's something wrong with the cursor on CHV pipe C. | |
14142 | * If it straddles the left edge of the screen then | |
14143 | * moving it away from the edge or disabling it often | |
14144 | * results in a pipe underrun, and often that can lead to | |
14145 | * dead pipe (constant underrun reported, and it scans | |
14146 | * out just a solid color). To recover from that, the | |
14147 | * display power well must be turned off and on again. | |
14148 | * Refuse the put the cursor into that compromised position. | |
14149 | */ | |
14150 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14151 | state->visible && state->base.crtc_x < 0) { | |
14152 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14153 | return -EINVAL; | |
14154 | } | |
14155 | ||
da20eabd | 14156 | return 0; |
852e787c | 14157 | } |
3d7d6510 | 14158 | |
a8ad0d8e ML |
14159 | static void |
14160 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14161 | struct drm_crtc *crtc) |
a8ad0d8e | 14162 | { |
f2858021 ML |
14163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14164 | ||
14165 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14166 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14167 | } |
14168 | ||
f4a2cf29 | 14169 | static void |
55a08b3f ML |
14170 | intel_update_cursor_plane(struct drm_plane *plane, |
14171 | const struct intel_crtc_state *crtc_state, | |
14172 | const struct intel_plane_state *state) | |
852e787c | 14173 | { |
55a08b3f ML |
14174 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14175 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14176 | struct drm_device *dev = plane->dev; |
2b875c22 | 14177 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14178 | uint32_t addr; |
852e787c | 14179 | |
f4a2cf29 | 14180 | if (!obj) |
a912f12f | 14181 | addr = 0; |
f4a2cf29 | 14182 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14183 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14184 | else |
a912f12f | 14185 | addr = obj->phys_handle->busaddr; |
852e787c | 14186 | |
a912f12f | 14187 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14188 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14189 | } |
14190 | ||
3d7d6510 MR |
14191 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14192 | int pipe) | |
14193 | { | |
14194 | struct intel_plane *cursor; | |
8e7d688b | 14195 | struct intel_plane_state *state; |
3d7d6510 MR |
14196 | |
14197 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14198 | if (cursor == NULL) | |
14199 | return NULL; | |
14200 | ||
8e7d688b MR |
14201 | state = intel_create_plane_state(&cursor->base); |
14202 | if (!state) { | |
ea2c67bb MR |
14203 | kfree(cursor); |
14204 | return NULL; | |
14205 | } | |
8e7d688b | 14206 | cursor->base.state = &state->base; |
ea2c67bb | 14207 | |
3d7d6510 MR |
14208 | cursor->can_scale = false; |
14209 | cursor->max_downscale = 1; | |
14210 | cursor->pipe = pipe; | |
14211 | cursor->plane = pipe; | |
a9ff8714 | 14212 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14213 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14214 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14215 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14216 | |
14217 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14218 | &intel_plane_funcs, |
3d7d6510 MR |
14219 | intel_cursor_formats, |
14220 | ARRAY_SIZE(intel_cursor_formats), | |
b0b3b795 | 14221 | DRM_PLANE_TYPE_CURSOR, NULL); |
4398ad45 VS |
14222 | |
14223 | if (INTEL_INFO(dev)->gen >= 4) { | |
14224 | if (!dev->mode_config.rotation_property) | |
14225 | dev->mode_config.rotation_property = | |
14226 | drm_mode_create_rotation_property(dev, | |
14227 | BIT(DRM_ROTATE_0) | | |
14228 | BIT(DRM_ROTATE_180)); | |
14229 | if (dev->mode_config.rotation_property) | |
14230 | drm_object_attach_property(&cursor->base.base, | |
14231 | dev->mode_config.rotation_property, | |
8e7d688b | 14232 | state->base.rotation); |
4398ad45 VS |
14233 | } |
14234 | ||
af99ceda CK |
14235 | if (INTEL_INFO(dev)->gen >=9) |
14236 | state->scaler_id = -1; | |
14237 | ||
ea2c67bb MR |
14238 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14239 | ||
3d7d6510 MR |
14240 | return &cursor->base; |
14241 | } | |
14242 | ||
549e2bfb CK |
14243 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14244 | struct intel_crtc_state *crtc_state) | |
14245 | { | |
14246 | int i; | |
14247 | struct intel_scaler *intel_scaler; | |
14248 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14249 | ||
14250 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14251 | intel_scaler = &scaler_state->scalers[i]; | |
14252 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14253 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14254 | } | |
14255 | ||
14256 | scaler_state->scaler_id = -1; | |
14257 | } | |
14258 | ||
b358d0a6 | 14259 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14260 | { |
fbee40df | 14261 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14262 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14263 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14264 | struct drm_plane *primary = NULL; |
14265 | struct drm_plane *cursor = NULL; | |
465c120c | 14266 | int i, ret; |
79e53945 | 14267 | |
955382f3 | 14268 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14269 | if (intel_crtc == NULL) |
14270 | return; | |
14271 | ||
f5de6e07 ACO |
14272 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14273 | if (!crtc_state) | |
14274 | goto fail; | |
550acefd ACO |
14275 | intel_crtc->config = crtc_state; |
14276 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14277 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14278 | |
549e2bfb CK |
14279 | /* initialize shared scalers */ |
14280 | if (INTEL_INFO(dev)->gen >= 9) { | |
14281 | if (pipe == PIPE_C) | |
14282 | intel_crtc->num_scalers = 1; | |
14283 | else | |
14284 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14285 | ||
14286 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14287 | } | |
14288 | ||
465c120c | 14289 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14290 | if (!primary) |
14291 | goto fail; | |
14292 | ||
14293 | cursor = intel_cursor_plane_create(dev, pipe); | |
14294 | if (!cursor) | |
14295 | goto fail; | |
14296 | ||
465c120c | 14297 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14298 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14299 | if (ret) |
14300 | goto fail; | |
79e53945 JB |
14301 | |
14302 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14303 | for (i = 0; i < 256; i++) { |
14304 | intel_crtc->lut_r[i] = i; | |
14305 | intel_crtc->lut_g[i] = i; | |
14306 | intel_crtc->lut_b[i] = i; | |
14307 | } | |
14308 | ||
1f1c2e24 VS |
14309 | /* |
14310 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14311 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14312 | */ |
80824003 JB |
14313 | intel_crtc->pipe = pipe; |
14314 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14315 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14316 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14317 | intel_crtc->plane = !pipe; |
80824003 JB |
14318 | } |
14319 | ||
4b0e333e CW |
14320 | intel_crtc->cursor_base = ~0; |
14321 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14322 | intel_crtc->cursor_size = ~0; |
8d7849db | 14323 | |
852eb00d VS |
14324 | intel_crtc->wm.cxsr_allowed = true; |
14325 | ||
22fd0fab JB |
14326 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14327 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14328 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14329 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14330 | ||
79e53945 | 14331 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14332 | |
14333 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14334 | return; |
14335 | ||
14336 | fail: | |
14337 | if (primary) | |
14338 | drm_plane_cleanup(primary); | |
14339 | if (cursor) | |
14340 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14341 | kfree(crtc_state); |
3d7d6510 | 14342 | kfree(intel_crtc); |
79e53945 JB |
14343 | } |
14344 | ||
752aa88a JB |
14345 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14346 | { | |
14347 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14348 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14349 | |
51fd371b | 14350 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14351 | |
d3babd3f | 14352 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14353 | return INVALID_PIPE; |
14354 | ||
14355 | return to_intel_crtc(encoder->crtc)->pipe; | |
14356 | } | |
14357 | ||
08d7b3d1 | 14358 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14359 | struct drm_file *file) |
08d7b3d1 | 14360 | { |
08d7b3d1 | 14361 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14362 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14363 | struct intel_crtc *crtc; |
08d7b3d1 | 14364 | |
7707e653 | 14365 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14366 | |
7707e653 | 14367 | if (!drmmode_crtc) { |
08d7b3d1 | 14368 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14369 | return -ENOENT; |
08d7b3d1 CW |
14370 | } |
14371 | ||
7707e653 | 14372 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14373 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14374 | |
c05422d5 | 14375 | return 0; |
08d7b3d1 CW |
14376 | } |
14377 | ||
66a9278e | 14378 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14379 | { |
66a9278e DV |
14380 | struct drm_device *dev = encoder->base.dev; |
14381 | struct intel_encoder *source_encoder; | |
79e53945 | 14382 | int index_mask = 0; |
79e53945 JB |
14383 | int entry = 0; |
14384 | ||
b2784e15 | 14385 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14386 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14387 | index_mask |= (1 << entry); |
14388 | ||
79e53945 JB |
14389 | entry++; |
14390 | } | |
4ef69c7a | 14391 | |
79e53945 JB |
14392 | return index_mask; |
14393 | } | |
14394 | ||
4d302442 CW |
14395 | static bool has_edp_a(struct drm_device *dev) |
14396 | { | |
14397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14398 | ||
14399 | if (!IS_MOBILE(dev)) | |
14400 | return false; | |
14401 | ||
14402 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14403 | return false; | |
14404 | ||
e3589908 | 14405 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14406 | return false; |
14407 | ||
14408 | return true; | |
14409 | } | |
14410 | ||
84b4e042 JB |
14411 | static bool intel_crt_present(struct drm_device *dev) |
14412 | { | |
14413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14414 | ||
884497ed DL |
14415 | if (INTEL_INFO(dev)->gen >= 9) |
14416 | return false; | |
14417 | ||
cf404ce4 | 14418 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14419 | return false; |
14420 | ||
14421 | if (IS_CHERRYVIEW(dev)) | |
14422 | return false; | |
14423 | ||
65e472e4 VS |
14424 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14425 | return false; | |
14426 | ||
70ac54d0 VS |
14427 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14428 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14429 | return false; | |
14430 | ||
e4abb733 | 14431 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14432 | return false; |
14433 | ||
14434 | return true; | |
14435 | } | |
14436 | ||
79e53945 JB |
14437 | static void intel_setup_outputs(struct drm_device *dev) |
14438 | { | |
725e30ad | 14439 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14440 | struct intel_encoder *encoder; |
cb0953d7 | 14441 | bool dpd_is_edp = false; |
79e53945 | 14442 | |
c9093354 | 14443 | intel_lvds_init(dev); |
79e53945 | 14444 | |
84b4e042 | 14445 | if (intel_crt_present(dev)) |
79935fca | 14446 | intel_crt_init(dev); |
cb0953d7 | 14447 | |
c776eb2e VK |
14448 | if (IS_BROXTON(dev)) { |
14449 | /* | |
14450 | * FIXME: Broxton doesn't support port detection via the | |
14451 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14452 | * detect the ports. | |
14453 | */ | |
14454 | intel_ddi_init(dev, PORT_A); | |
14455 | intel_ddi_init(dev, PORT_B); | |
14456 | intel_ddi_init(dev, PORT_C); | |
14457 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14458 | int found; |
14459 | ||
de31facd JB |
14460 | /* |
14461 | * Haswell uses DDI functions to detect digital outputs. | |
14462 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14463 | * it's there. | |
14464 | */ | |
77179400 | 14465 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14466 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14467 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14468 | intel_ddi_init(dev, PORT_A); |
14469 | ||
14470 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14471 | * register */ | |
14472 | found = I915_READ(SFUSE_STRAP); | |
14473 | ||
14474 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14475 | intel_ddi_init(dev, PORT_B); | |
14476 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14477 | intel_ddi_init(dev, PORT_C); | |
14478 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14479 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14480 | /* |
14481 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14482 | */ | |
ef11bdb3 | 14483 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14484 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14485 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14486 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14487 | intel_ddi_init(dev, PORT_E); | |
14488 | ||
0e72a5b5 | 14489 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14490 | int found; |
5d8a7752 | 14491 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14492 | |
14493 | if (has_edp_a(dev)) | |
14494 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14495 | |
dc0fa718 | 14496 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14497 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14498 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14499 | if (!found) |
e2debe91 | 14500 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14501 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14502 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14503 | } |
14504 | ||
dc0fa718 | 14505 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14506 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14507 | |
dc0fa718 | 14508 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14509 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14510 | |
5eb08b69 | 14511 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14512 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14513 | |
270b3042 | 14514 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14515 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14516 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14517 | /* |
14518 | * The DP_DETECTED bit is the latched state of the DDC | |
14519 | * SDA pin at boot. However since eDP doesn't require DDC | |
14520 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14521 | * eDP ports may have been muxed to an alternate function. | |
14522 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14523 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14524 | * detect eDP ports. | |
14525 | */ | |
e66eb81d | 14526 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14527 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14528 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14529 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14530 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14531 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14532 | |
e66eb81d | 14533 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14534 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14535 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14536 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14537 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14538 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14539 | |
9418c1f1 | 14540 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14541 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14542 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14543 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14544 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14545 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14546 | } |
14547 | ||
3cfca973 | 14548 | intel_dsi_init(dev); |
09da55dc | 14549 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14550 | bool found = false; |
7d57382e | 14551 | |
e2debe91 | 14552 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14553 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14554 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14555 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14556 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14557 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14558 | } |
27185ae1 | 14559 | |
3fec3d2f | 14560 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14561 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14562 | } |
13520b05 KH |
14563 | |
14564 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14565 | |
e2debe91 | 14566 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14567 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14568 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14569 | } |
27185ae1 | 14570 | |
e2debe91 | 14571 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14572 | |
3fec3d2f | 14573 | if (IS_G4X(dev)) { |
b01f2c3a | 14574 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14575 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14576 | } |
3fec3d2f | 14577 | if (IS_G4X(dev)) |
ab9d7c30 | 14578 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14579 | } |
27185ae1 | 14580 | |
3fec3d2f | 14581 | if (IS_G4X(dev) && |
e7281eab | 14582 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14583 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14584 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14585 | intel_dvo_init(dev); |
14586 | ||
103a196f | 14587 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14588 | intel_tv_init(dev); |
14589 | ||
0bc12bcb | 14590 | intel_psr_init(dev); |
7c8f8a70 | 14591 | |
b2784e15 | 14592 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14593 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14594 | encoder->base.possible_clones = | |
66a9278e | 14595 | intel_encoder_clones(encoder); |
79e53945 | 14596 | } |
47356eb6 | 14597 | |
dde86e2d | 14598 | intel_init_pch_refclk(dev); |
270b3042 DV |
14599 | |
14600 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14601 | } |
14602 | ||
14603 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14604 | { | |
60a5ca01 | 14605 | struct drm_device *dev = fb->dev; |
79e53945 | 14606 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14607 | |
ef2d633e | 14608 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14609 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14610 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14611 | drm_gem_object_unreference(&intel_fb->obj->base); |
14612 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14613 | kfree(intel_fb); |
14614 | } | |
14615 | ||
14616 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14617 | struct drm_file *file, |
79e53945 JB |
14618 | unsigned int *handle) |
14619 | { | |
14620 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14621 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14622 | |
cc917ab4 CW |
14623 | if (obj->userptr.mm) { |
14624 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14625 | return -EINVAL; | |
14626 | } | |
14627 | ||
05394f39 | 14628 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14629 | } |
14630 | ||
86c98588 RV |
14631 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14632 | struct drm_file *file, | |
14633 | unsigned flags, unsigned color, | |
14634 | struct drm_clip_rect *clips, | |
14635 | unsigned num_clips) | |
14636 | { | |
14637 | struct drm_device *dev = fb->dev; | |
14638 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14639 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14640 | ||
14641 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14642 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14643 | mutex_unlock(&dev->struct_mutex); |
14644 | ||
14645 | return 0; | |
14646 | } | |
14647 | ||
79e53945 JB |
14648 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14649 | .destroy = intel_user_framebuffer_destroy, | |
14650 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14651 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14652 | }; |
14653 | ||
b321803d DL |
14654 | static |
14655 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14656 | uint32_t pixel_format) | |
14657 | { | |
14658 | u32 gen = INTEL_INFO(dev)->gen; | |
14659 | ||
14660 | if (gen >= 9) { | |
ac484963 VS |
14661 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14662 | ||
b321803d DL |
14663 | /* "The stride in bytes must not exceed the of the size of 8K |
14664 | * pixels and 32K bytes." | |
14665 | */ | |
ac484963 | 14666 | return min(8192 * cpp, 32768); |
666a4537 | 14667 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14668 | return 32*1024; |
14669 | } else if (gen >= 4) { | |
14670 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14671 | return 16*1024; | |
14672 | else | |
14673 | return 32*1024; | |
14674 | } else if (gen >= 3) { | |
14675 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14676 | return 8*1024; | |
14677 | else | |
14678 | return 16*1024; | |
14679 | } else { | |
14680 | /* XXX DSPC is limited to 4k tiled */ | |
14681 | return 8*1024; | |
14682 | } | |
14683 | } | |
14684 | ||
b5ea642a DV |
14685 | static int intel_framebuffer_init(struct drm_device *dev, |
14686 | struct intel_framebuffer *intel_fb, | |
14687 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14688 | struct drm_i915_gem_object *obj) | |
79e53945 | 14689 | { |
7b49f948 | 14690 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14691 | unsigned int aligned_height; |
79e53945 | 14692 | int ret; |
b321803d | 14693 | u32 pitch_limit, stride_alignment; |
79e53945 | 14694 | |
dd4916c5 DV |
14695 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14696 | ||
2a80eada DV |
14697 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14698 | /* Enforce that fb modifier and tiling mode match, but only for | |
14699 | * X-tiled. This is needed for FBC. */ | |
14700 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14701 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14702 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14703 | return -EINVAL; | |
14704 | } | |
14705 | } else { | |
14706 | if (obj->tiling_mode == I915_TILING_X) | |
14707 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14708 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14709 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14710 | return -EINVAL; | |
14711 | } | |
14712 | } | |
14713 | ||
9a8f0a12 TU |
14714 | /* Passed in modifier sanity checking. */ |
14715 | switch (mode_cmd->modifier[0]) { | |
14716 | case I915_FORMAT_MOD_Y_TILED: | |
14717 | case I915_FORMAT_MOD_Yf_TILED: | |
14718 | if (INTEL_INFO(dev)->gen < 9) { | |
14719 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14720 | mode_cmd->modifier[0]); | |
14721 | return -EINVAL; | |
14722 | } | |
14723 | case DRM_FORMAT_MOD_NONE: | |
14724 | case I915_FORMAT_MOD_X_TILED: | |
14725 | break; | |
14726 | default: | |
c0f40428 JB |
14727 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14728 | mode_cmd->modifier[0]); | |
57cd6508 | 14729 | return -EINVAL; |
c16ed4be | 14730 | } |
57cd6508 | 14731 | |
7b49f948 VS |
14732 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14733 | mode_cmd->modifier[0], | |
b321803d DL |
14734 | mode_cmd->pixel_format); |
14735 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14736 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14737 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14738 | return -EINVAL; |
c16ed4be | 14739 | } |
57cd6508 | 14740 | |
b321803d DL |
14741 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14742 | mode_cmd->pixel_format); | |
a35cdaa0 | 14743 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14744 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14745 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14746 | "tiled" : "linear", |
a35cdaa0 | 14747 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14748 | return -EINVAL; |
c16ed4be | 14749 | } |
5d7bd705 | 14750 | |
2a80eada | 14751 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14752 | mode_cmd->pitches[0] != obj->stride) { |
14753 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14754 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14755 | return -EINVAL; |
c16ed4be | 14756 | } |
5d7bd705 | 14757 | |
57779d06 | 14758 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14759 | switch (mode_cmd->pixel_format) { |
57779d06 | 14760 | case DRM_FORMAT_C8: |
04b3924d VS |
14761 | case DRM_FORMAT_RGB565: |
14762 | case DRM_FORMAT_XRGB8888: | |
14763 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14764 | break; |
14765 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14766 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14767 | DRM_DEBUG("unsupported pixel format: %s\n", |
14768 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14769 | return -EINVAL; |
c16ed4be | 14770 | } |
57779d06 | 14771 | break; |
57779d06 | 14772 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14773 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14774 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14775 | DRM_DEBUG("unsupported pixel format: %s\n", |
14776 | drm_get_format_name(mode_cmd->pixel_format)); | |
14777 | return -EINVAL; | |
14778 | } | |
14779 | break; | |
14780 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14781 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14782 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14783 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14784 | DRM_DEBUG("unsupported pixel format: %s\n", |
14785 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14786 | return -EINVAL; |
c16ed4be | 14787 | } |
b5626747 | 14788 | break; |
7531208b | 14789 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14790 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14791 | DRM_DEBUG("unsupported pixel format: %s\n", |
14792 | drm_get_format_name(mode_cmd->pixel_format)); | |
14793 | return -EINVAL; | |
14794 | } | |
14795 | break; | |
04b3924d VS |
14796 | case DRM_FORMAT_YUYV: |
14797 | case DRM_FORMAT_UYVY: | |
14798 | case DRM_FORMAT_YVYU: | |
14799 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14800 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14801 | DRM_DEBUG("unsupported pixel format: %s\n", |
14802 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14803 | return -EINVAL; |
c16ed4be | 14804 | } |
57cd6508 CW |
14805 | break; |
14806 | default: | |
4ee62c76 VS |
14807 | DRM_DEBUG("unsupported pixel format: %s\n", |
14808 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14809 | return -EINVAL; |
14810 | } | |
14811 | ||
90f9a336 VS |
14812 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14813 | if (mode_cmd->offsets[0] != 0) | |
14814 | return -EINVAL; | |
14815 | ||
ec2c981e | 14816 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14817 | mode_cmd->pixel_format, |
14818 | mode_cmd->modifier[0]); | |
53155c0a DV |
14819 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14820 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14821 | return -EINVAL; | |
14822 | ||
c7d73f6a DV |
14823 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14824 | intel_fb->obj = obj; | |
14825 | ||
79e53945 JB |
14826 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14827 | if (ret) { | |
14828 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14829 | return ret; | |
14830 | } | |
14831 | ||
0b05e1e0 VS |
14832 | intel_fb->obj->framebuffer_references++; |
14833 | ||
79e53945 JB |
14834 | return 0; |
14835 | } | |
14836 | ||
79e53945 JB |
14837 | static struct drm_framebuffer * |
14838 | intel_user_framebuffer_create(struct drm_device *dev, | |
14839 | struct drm_file *filp, | |
1eb83451 | 14840 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14841 | { |
dcb1394e | 14842 | struct drm_framebuffer *fb; |
05394f39 | 14843 | struct drm_i915_gem_object *obj; |
76dc3769 | 14844 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14845 | |
308e5bcb | 14846 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14847 | mode_cmd.handles[0])); |
c8725226 | 14848 | if (&obj->base == NULL) |
cce13ff7 | 14849 | return ERR_PTR(-ENOENT); |
79e53945 | 14850 | |
92907cbb | 14851 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14852 | if (IS_ERR(fb)) |
14853 | drm_gem_object_unreference_unlocked(&obj->base); | |
14854 | ||
14855 | return fb; | |
79e53945 JB |
14856 | } |
14857 | ||
0695726e | 14858 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14859 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14860 | { |
14861 | } | |
14862 | #endif | |
14863 | ||
79e53945 | 14864 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14865 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14866 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14867 | .atomic_check = intel_atomic_check, |
14868 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14869 | .atomic_state_alloc = intel_atomic_state_alloc, |
14870 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14871 | }; |
14872 | ||
e70236a8 JB |
14873 | /* Set up chip specific display functions */ |
14874 | static void intel_init_display(struct drm_device *dev) | |
14875 | { | |
14876 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14877 | ||
ee9300bb DV |
14878 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14879 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14880 | else if (IS_CHERRYVIEW(dev)) |
14881 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14882 | else if (IS_VALLEYVIEW(dev)) |
14883 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14884 | else if (IS_PINEVIEW(dev)) | |
14885 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14886 | else | |
14887 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14888 | ||
bc8d7dff DL |
14889 | if (INTEL_INFO(dev)->gen >= 9) { |
14890 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14891 | dev_priv->display.get_initial_plane_config = |
14892 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14893 | dev_priv->display.crtc_compute_clock = |
14894 | haswell_crtc_compute_clock; | |
14895 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14896 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff | 14897 | } else if (HAS_DDI(dev)) { |
0e8ffe1b | 14898 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14899 | dev_priv->display.get_initial_plane_config = |
14900 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14901 | dev_priv->display.crtc_compute_clock = |
14902 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14903 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14904 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
09b4ddf9 | 14905 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14906 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14907 | dev_priv->display.get_initial_plane_config = |
14908 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14909 | dev_priv->display.crtc_compute_clock = |
14910 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14911 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14912 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
666a4537 | 14913 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 14914 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14915 | dev_priv->display.get_initial_plane_config = |
14916 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14917 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14918 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14919 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14920 | } else { |
0e8ffe1b | 14921 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14922 | dev_priv->display.get_initial_plane_config = |
14923 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14924 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14925 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14926 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14927 | } |
e70236a8 | 14928 | |
e70236a8 | 14929 | /* Returns the core display clock speed */ |
ef11bdb3 | 14930 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
14931 | dev_priv->display.get_display_clock_speed = |
14932 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14933 | else if (IS_BROXTON(dev)) |
14934 | dev_priv->display.get_display_clock_speed = | |
14935 | broxton_get_display_clock_speed; | |
1652d19e VS |
14936 | else if (IS_BROADWELL(dev)) |
14937 | dev_priv->display.get_display_clock_speed = | |
14938 | broadwell_get_display_clock_speed; | |
14939 | else if (IS_HASWELL(dev)) | |
14940 | dev_priv->display.get_display_clock_speed = | |
14941 | haswell_get_display_clock_speed; | |
666a4537 | 14942 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
14943 | dev_priv->display.get_display_clock_speed = |
14944 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14945 | else if (IS_GEN5(dev)) |
14946 | dev_priv->display.get_display_clock_speed = | |
14947 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14948 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14949 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14950 | dev_priv->display.get_display_clock_speed = |
14951 | i945_get_display_clock_speed; | |
34edce2f VS |
14952 | else if (IS_GM45(dev)) |
14953 | dev_priv->display.get_display_clock_speed = | |
14954 | gm45_get_display_clock_speed; | |
14955 | else if (IS_CRESTLINE(dev)) | |
14956 | dev_priv->display.get_display_clock_speed = | |
14957 | i965gm_get_display_clock_speed; | |
14958 | else if (IS_PINEVIEW(dev)) | |
14959 | dev_priv->display.get_display_clock_speed = | |
14960 | pnv_get_display_clock_speed; | |
14961 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14962 | dev_priv->display.get_display_clock_speed = | |
14963 | g33_get_display_clock_speed; | |
e70236a8 JB |
14964 | else if (IS_I915G(dev)) |
14965 | dev_priv->display.get_display_clock_speed = | |
14966 | i915_get_display_clock_speed; | |
257a7ffc | 14967 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14968 | dev_priv->display.get_display_clock_speed = |
14969 | i9xx_misc_get_display_clock_speed; | |
14970 | else if (IS_I915GM(dev)) | |
14971 | dev_priv->display.get_display_clock_speed = | |
14972 | i915gm_get_display_clock_speed; | |
14973 | else if (IS_I865G(dev)) | |
14974 | dev_priv->display.get_display_clock_speed = | |
14975 | i865_get_display_clock_speed; | |
f0f8a9ce | 14976 | else if (IS_I85X(dev)) |
e70236a8 | 14977 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14978 | i85x_get_display_clock_speed; |
623e01e5 VS |
14979 | else { /* 830 */ |
14980 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14981 | dev_priv->display.get_display_clock_speed = |
14982 | i830_get_display_clock_speed; | |
623e01e5 | 14983 | } |
e70236a8 | 14984 | |
7c10a2b5 | 14985 | if (IS_GEN5(dev)) { |
3bb11b53 | 14986 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14987 | } else if (IS_GEN6(dev)) { |
14988 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14989 | } else if (IS_IVYBRIDGE(dev)) { |
14990 | /* FIXME: detect B0+ stepping and use auto training */ | |
14991 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14992 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14993 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
14994 | if (IS_BROADWELL(dev)) { |
14995 | dev_priv->display.modeset_commit_cdclk = | |
14996 | broadwell_modeset_commit_cdclk; | |
14997 | dev_priv->display.modeset_calc_cdclk = | |
14998 | broadwell_modeset_calc_cdclk; | |
14999 | } | |
666a4537 | 15000 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
15001 | dev_priv->display.modeset_commit_cdclk = |
15002 | valleyview_modeset_commit_cdclk; | |
15003 | dev_priv->display.modeset_calc_cdclk = | |
15004 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 15005 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
15006 | dev_priv->display.modeset_commit_cdclk = |
15007 | broxton_modeset_commit_cdclk; | |
15008 | dev_priv->display.modeset_calc_cdclk = | |
15009 | broxton_modeset_calc_cdclk; | |
e70236a8 | 15010 | } |
8c9f3aaf | 15011 | |
8c9f3aaf JB |
15012 | switch (INTEL_INFO(dev)->gen) { |
15013 | case 2: | |
15014 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15015 | break; | |
15016 | ||
15017 | case 3: | |
15018 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15019 | break; | |
15020 | ||
15021 | case 4: | |
15022 | case 5: | |
15023 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15024 | break; | |
15025 | ||
15026 | case 6: | |
15027 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15028 | break; | |
7c9017e5 | 15029 | case 7: |
4e0bbc31 | 15030 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15031 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15032 | break; | |
830c81db | 15033 | case 9: |
ba343e02 TU |
15034 | /* Drop through - unsupported since execlist only. */ |
15035 | default: | |
15036 | /* Default just returns -ENODEV to indicate unsupported */ | |
15037 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15038 | } |
7bd688cd | 15039 | |
e39b999a | 15040 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
15041 | } |
15042 | ||
b690e96c JB |
15043 | /* |
15044 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15045 | * resume, or other times. This quirk makes sure that's the case for | |
15046 | * affected systems. | |
15047 | */ | |
0206e353 | 15048 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15049 | { |
15050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15051 | ||
15052 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15053 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15054 | } |
15055 | ||
b6b5d049 VS |
15056 | static void quirk_pipeb_force(struct drm_device *dev) |
15057 | { | |
15058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15059 | ||
15060 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15061 | DRM_INFO("applying pipe b force quirk\n"); | |
15062 | } | |
15063 | ||
435793df KP |
15064 | /* |
15065 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15066 | */ | |
15067 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15068 | { | |
15069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15070 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15071 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15072 | } |
15073 | ||
4dca20ef | 15074 | /* |
5a15ab5b CE |
15075 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15076 | * brightness value | |
4dca20ef CE |
15077 | */ |
15078 | static void quirk_invert_brightness(struct drm_device *dev) | |
15079 | { | |
15080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15081 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15082 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15083 | } |
15084 | ||
9c72cc6f SD |
15085 | /* Some VBT's incorrectly indicate no backlight is present */ |
15086 | static void quirk_backlight_present(struct drm_device *dev) | |
15087 | { | |
15088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15089 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15090 | DRM_INFO("applying backlight present quirk\n"); | |
15091 | } | |
15092 | ||
b690e96c JB |
15093 | struct intel_quirk { |
15094 | int device; | |
15095 | int subsystem_vendor; | |
15096 | int subsystem_device; | |
15097 | void (*hook)(struct drm_device *dev); | |
15098 | }; | |
15099 | ||
5f85f176 EE |
15100 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15101 | struct intel_dmi_quirk { | |
15102 | void (*hook)(struct drm_device *dev); | |
15103 | const struct dmi_system_id (*dmi_id_list)[]; | |
15104 | }; | |
15105 | ||
15106 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15107 | { | |
15108 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15109 | return 1; | |
15110 | } | |
15111 | ||
15112 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15113 | { | |
15114 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15115 | { | |
15116 | .callback = intel_dmi_reverse_brightness, | |
15117 | .ident = "NCR Corporation", | |
15118 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15119 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15120 | }, | |
15121 | }, | |
15122 | { } /* terminating entry */ | |
15123 | }, | |
15124 | .hook = quirk_invert_brightness, | |
15125 | }, | |
15126 | }; | |
15127 | ||
c43b5634 | 15128 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15129 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15130 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15131 | ||
b690e96c JB |
15132 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15133 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15134 | ||
5f080c0f VS |
15135 | /* 830 needs to leave pipe A & dpll A up */ |
15136 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15137 | ||
b6b5d049 VS |
15138 | /* 830 needs to leave pipe B & dpll B up */ |
15139 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15140 | ||
435793df KP |
15141 | /* Lenovo U160 cannot use SSC on LVDS */ |
15142 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15143 | |
15144 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15145 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15146 | |
be505f64 AH |
15147 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15148 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15149 | ||
15150 | /* Acer/eMachines G725 */ | |
15151 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15152 | ||
15153 | /* Acer/eMachines e725 */ | |
15154 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15155 | ||
15156 | /* Acer/Packard Bell NCL20 */ | |
15157 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15158 | ||
15159 | /* Acer Aspire 4736Z */ | |
15160 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15161 | |
15162 | /* Acer Aspire 5336 */ | |
15163 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15164 | |
15165 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15166 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15167 | |
dfb3d47b SD |
15168 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15169 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15170 | ||
b2a9601c | 15171 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15172 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15173 | ||
1b9448b0 JN |
15174 | /* Apple Macbook 4,1 */ |
15175 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15176 | ||
d4967d8c SD |
15177 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15178 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15179 | |
15180 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15181 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15182 | |
15183 | /* Dell Chromebook 11 */ | |
15184 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15185 | |
15186 | /* Dell Chromebook 11 (2015 version) */ | |
15187 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15188 | }; |
15189 | ||
15190 | static void intel_init_quirks(struct drm_device *dev) | |
15191 | { | |
15192 | struct pci_dev *d = dev->pdev; | |
15193 | int i; | |
15194 | ||
15195 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15196 | struct intel_quirk *q = &intel_quirks[i]; | |
15197 | ||
15198 | if (d->device == q->device && | |
15199 | (d->subsystem_vendor == q->subsystem_vendor || | |
15200 | q->subsystem_vendor == PCI_ANY_ID) && | |
15201 | (d->subsystem_device == q->subsystem_device || | |
15202 | q->subsystem_device == PCI_ANY_ID)) | |
15203 | q->hook(dev); | |
15204 | } | |
5f85f176 EE |
15205 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15206 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15207 | intel_dmi_quirks[i].hook(dev); | |
15208 | } | |
b690e96c JB |
15209 | } |
15210 | ||
9cce37f4 JB |
15211 | /* Disable the VGA plane that we never use */ |
15212 | static void i915_disable_vga(struct drm_device *dev) | |
15213 | { | |
15214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15215 | u8 sr1; | |
f0f59a00 | 15216 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15217 | |
2b37c616 | 15218 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15219 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15220 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15221 | sr1 = inb(VGA_SR_DATA); |
15222 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15223 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15224 | udelay(300); | |
15225 | ||
01f5a626 | 15226 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15227 | POSTING_READ(vga_reg); |
15228 | } | |
15229 | ||
f817586c DV |
15230 | void intel_modeset_init_hw(struct drm_device *dev) |
15231 | { | |
1a617b77 ML |
15232 | struct drm_i915_private *dev_priv = dev->dev_private; |
15233 | ||
b6283055 | 15234 | intel_update_cdclk(dev); |
1a617b77 ML |
15235 | |
15236 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15237 | ||
f817586c | 15238 | intel_init_clock_gating(dev); |
8090c6b9 | 15239 | intel_enable_gt_powersave(dev); |
f817586c DV |
15240 | } |
15241 | ||
d93c0372 MR |
15242 | /* |
15243 | * Calculate what we think the watermarks should be for the state we've read | |
15244 | * out of the hardware and then immediately program those watermarks so that | |
15245 | * we ensure the hardware settings match our internal state. | |
15246 | * | |
15247 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15248 | * current state (which was constructed during hardware readout) and running it | |
15249 | * through the atomic check code to calculate new watermark values in the | |
15250 | * state object. | |
15251 | */ | |
15252 | static void sanitize_watermarks(struct drm_device *dev) | |
15253 | { | |
15254 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15255 | struct drm_atomic_state *state; | |
15256 | struct drm_crtc *crtc; | |
15257 | struct drm_crtc_state *cstate; | |
15258 | struct drm_modeset_acquire_ctx ctx; | |
15259 | int ret; | |
15260 | int i; | |
15261 | ||
15262 | /* Only supported on platforms that use atomic watermark design */ | |
bf220452 | 15263 | if (!dev_priv->display.program_watermarks) |
d93c0372 MR |
15264 | return; |
15265 | ||
15266 | /* | |
15267 | * We need to hold connection_mutex before calling duplicate_state so | |
15268 | * that the connector loop is protected. | |
15269 | */ | |
15270 | drm_modeset_acquire_init(&ctx, 0); | |
15271 | retry: | |
0cd1262d | 15272 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15273 | if (ret == -EDEADLK) { |
15274 | drm_modeset_backoff(&ctx); | |
15275 | goto retry; | |
15276 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15277 | goto fail; |
d93c0372 MR |
15278 | } |
15279 | ||
15280 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15281 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15282 | goto fail; |
d93c0372 MR |
15283 | |
15284 | ret = intel_atomic_check(dev, state); | |
15285 | if (ret) { | |
15286 | /* | |
15287 | * If we fail here, it means that the hardware appears to be | |
15288 | * programmed in a way that shouldn't be possible, given our | |
15289 | * understanding of watermark requirements. This might mean a | |
15290 | * mistake in the hardware readout code or a mistake in the | |
15291 | * watermark calculations for a given platform. Raise a WARN | |
15292 | * so that this is noticeable. | |
15293 | * | |
15294 | * If this actually happens, we'll have to just leave the | |
15295 | * BIOS-programmed watermarks untouched and hope for the best. | |
15296 | */ | |
15297 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15298 | goto fail; |
d93c0372 MR |
15299 | } |
15300 | ||
15301 | /* Write calculated watermark values back */ | |
15302 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15303 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15304 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15305 | ||
bf220452 | 15306 | dev_priv->display.program_watermarks(cs); |
d93c0372 MR |
15307 | } |
15308 | ||
15309 | drm_atomic_state_free(state); | |
0cd1262d | 15310 | fail: |
d93c0372 MR |
15311 | drm_modeset_drop_locks(&ctx); |
15312 | drm_modeset_acquire_fini(&ctx); | |
15313 | } | |
15314 | ||
79e53945 JB |
15315 | void intel_modeset_init(struct drm_device *dev) |
15316 | { | |
652c393a | 15317 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15318 | int sprite, ret; |
8cc87b75 | 15319 | enum pipe pipe; |
46f297fb | 15320 | struct intel_crtc *crtc; |
79e53945 JB |
15321 | |
15322 | drm_mode_config_init(dev); | |
15323 | ||
15324 | dev->mode_config.min_width = 0; | |
15325 | dev->mode_config.min_height = 0; | |
15326 | ||
019d96cb DA |
15327 | dev->mode_config.preferred_depth = 24; |
15328 | dev->mode_config.prefer_shadow = 1; | |
15329 | ||
25bab385 TU |
15330 | dev->mode_config.allow_fb_modifiers = true; |
15331 | ||
e6ecefaa | 15332 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15333 | |
b690e96c JB |
15334 | intel_init_quirks(dev); |
15335 | ||
1fa61106 ED |
15336 | intel_init_pm(dev); |
15337 | ||
e3c74757 BW |
15338 | if (INTEL_INFO(dev)->num_pipes == 0) |
15339 | return; | |
15340 | ||
69f92f67 LW |
15341 | /* |
15342 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15343 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15344 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15345 | * indicates as much. | |
15346 | */ | |
15347 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15348 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15349 | DREF_SSC1_ENABLE); | |
15350 | ||
15351 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15352 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15353 | bios_lvds_use_ssc ? "en" : "dis", | |
15354 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15355 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15356 | } | |
15357 | } | |
15358 | ||
e70236a8 | 15359 | intel_init_display(dev); |
7c10a2b5 | 15360 | intel_init_audio(dev); |
e70236a8 | 15361 | |
a6c45cf0 CW |
15362 | if (IS_GEN2(dev)) { |
15363 | dev->mode_config.max_width = 2048; | |
15364 | dev->mode_config.max_height = 2048; | |
15365 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15366 | dev->mode_config.max_width = 4096; |
15367 | dev->mode_config.max_height = 4096; | |
79e53945 | 15368 | } else { |
a6c45cf0 CW |
15369 | dev->mode_config.max_width = 8192; |
15370 | dev->mode_config.max_height = 8192; | |
79e53945 | 15371 | } |
068be561 | 15372 | |
dc41c154 VS |
15373 | if (IS_845G(dev) || IS_I865G(dev)) { |
15374 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15375 | dev->mode_config.cursor_height = 1023; | |
15376 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15377 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15378 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15379 | } else { | |
15380 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15381 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15382 | } | |
15383 | ||
5d4545ae | 15384 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15385 | |
28c97730 | 15386 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15387 | INTEL_INFO(dev)->num_pipes, |
15388 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15389 | |
055e393f | 15390 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15391 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15392 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15393 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15394 | if (ret) |
06da8da2 | 15395 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15396 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15397 | } |
79e53945 JB |
15398 | } |
15399 | ||
bfa7df01 VS |
15400 | intel_update_czclk(dev_priv); |
15401 | intel_update_cdclk(dev); | |
15402 | ||
e72f9fbf | 15403 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15404 | |
9cce37f4 JB |
15405 | /* Just disable it once at startup */ |
15406 | i915_disable_vga(dev); | |
79e53945 | 15407 | intel_setup_outputs(dev); |
11be49eb | 15408 | |
6e9f798d | 15409 | drm_modeset_lock_all(dev); |
043e9bda | 15410 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15411 | drm_modeset_unlock_all(dev); |
46f297fb | 15412 | |
d3fcc808 | 15413 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15414 | struct intel_initial_plane_config plane_config = {}; |
15415 | ||
46f297fb JB |
15416 | if (!crtc->active) |
15417 | continue; | |
15418 | ||
46f297fb | 15419 | /* |
46f297fb JB |
15420 | * Note that reserving the BIOS fb up front prevents us |
15421 | * from stuffing other stolen allocations like the ring | |
15422 | * on top. This prevents some ugliness at boot time, and | |
15423 | * can even allow for smooth boot transitions if the BIOS | |
15424 | * fb is large enough for the active pipe configuration. | |
15425 | */ | |
eeebeac5 ML |
15426 | dev_priv->display.get_initial_plane_config(crtc, |
15427 | &plane_config); | |
15428 | ||
15429 | /* | |
15430 | * If the fb is shared between multiple heads, we'll | |
15431 | * just get the first one. | |
15432 | */ | |
15433 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15434 | } |
d93c0372 MR |
15435 | |
15436 | /* | |
15437 | * Make sure hardware watermarks really match the state we read out. | |
15438 | * Note that we need to do this after reconstructing the BIOS fb's | |
15439 | * since the watermark calculation done here will use pstate->fb. | |
15440 | */ | |
15441 | sanitize_watermarks(dev); | |
2c7111db CW |
15442 | } |
15443 | ||
7fad798e DV |
15444 | static void intel_enable_pipe_a(struct drm_device *dev) |
15445 | { | |
15446 | struct intel_connector *connector; | |
15447 | struct drm_connector *crt = NULL; | |
15448 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15449 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15450 | |
15451 | /* We can't just switch on the pipe A, we need to set things up with a | |
15452 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15453 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15454 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15455 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15456 | crt = &connector->base; | |
15457 | break; | |
15458 | } | |
15459 | } | |
15460 | ||
15461 | if (!crt) | |
15462 | return; | |
15463 | ||
208bf9fd | 15464 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15465 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15466 | } |
15467 | ||
fa555837 DV |
15468 | static bool |
15469 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15470 | { | |
7eb552ae BW |
15471 | struct drm_device *dev = crtc->base.dev; |
15472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15473 | u32 val; |
fa555837 | 15474 | |
7eb552ae | 15475 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15476 | return true; |
15477 | ||
649636ef | 15478 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15479 | |
15480 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15481 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15482 | return false; | |
15483 | ||
15484 | return true; | |
15485 | } | |
15486 | ||
02e93c35 VS |
15487 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15488 | { | |
15489 | struct drm_device *dev = crtc->base.dev; | |
15490 | struct intel_encoder *encoder; | |
15491 | ||
15492 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15493 | return true; | |
15494 | ||
15495 | return false; | |
15496 | } | |
15497 | ||
24929352 DV |
15498 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15499 | { | |
15500 | struct drm_device *dev = crtc->base.dev; | |
15501 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15502 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15503 | |
24929352 | 15504 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15505 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15506 | ||
d3eaf884 | 15507 | /* restore vblank interrupts to correct state */ |
9625604c | 15508 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15509 | if (crtc->active) { |
f9cd7b88 VS |
15510 | struct intel_plane *plane; |
15511 | ||
9625604c | 15512 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15513 | |
15514 | /* Disable everything but the primary plane */ | |
15515 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15516 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15517 | continue; | |
15518 | ||
15519 | plane->disable_plane(&plane->base, &crtc->base); | |
15520 | } | |
9625604c | 15521 | } |
d3eaf884 | 15522 | |
24929352 | 15523 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15524 | * disable the crtc (and hence change the state) if it is wrong. Note |
15525 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15526 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15527 | bool plane; |
15528 | ||
24929352 DV |
15529 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15530 | crtc->base.base.id); | |
15531 | ||
15532 | /* Pipe has the wrong plane attached and the plane is active. | |
15533 | * Temporarily change the plane mapping and disable everything | |
15534 | * ... */ | |
15535 | plane = crtc->plane; | |
b70709a6 | 15536 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15537 | crtc->plane = !plane; |
b17d48e2 | 15538 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15539 | crtc->plane = plane; |
24929352 | 15540 | } |
24929352 | 15541 | |
7fad798e DV |
15542 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15543 | crtc->pipe == PIPE_A && !crtc->active) { | |
15544 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15545 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15546 | * call below we restore the pipe to the right state, but leave | |
15547 | * the required bits on. */ | |
15548 | intel_enable_pipe_a(dev); | |
15549 | } | |
15550 | ||
24929352 DV |
15551 | /* Adjust the state of the output pipe according to whether we |
15552 | * have active connectors/encoders. */ | |
02e93c35 | 15553 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15554 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15555 | |
53d9f4e9 | 15556 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15557 | struct intel_encoder *encoder; |
24929352 DV |
15558 | |
15559 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15560 | * functions or because of calls to intel_crtc_disable_noatomic, |
15561 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15562 | * pipe A quirk. */ |
15563 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15564 | crtc->base.base.id, | |
83d65738 | 15565 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15566 | crtc->active ? "enabled" : "disabled"); |
15567 | ||
4be40c98 | 15568 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15569 | crtc->base.state->active = crtc->active; |
24929352 | 15570 | crtc->base.enabled = crtc->active; |
2aa974c9 | 15571 | crtc->base.state->connector_mask = 0; |
e87a52b3 | 15572 | crtc->base.state->encoder_mask = 0; |
24929352 DV |
15573 | |
15574 | /* Because we only establish the connector -> encoder -> | |
15575 | * crtc links if something is active, this means the | |
15576 | * crtc is now deactivated. Break the links. connector | |
15577 | * -> encoder links are only establish when things are | |
15578 | * actually up, hence no need to break them. */ | |
15579 | WARN_ON(crtc->active); | |
15580 | ||
2d406bb0 | 15581 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15582 | encoder->base.crtc = NULL; |
24929352 | 15583 | } |
c5ab3bc0 | 15584 | |
a3ed6aad | 15585 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15586 | /* |
15587 | * We start out with underrun reporting disabled to avoid races. | |
15588 | * For correct bookkeeping mark this on active crtcs. | |
15589 | * | |
c5ab3bc0 DV |
15590 | * Also on gmch platforms we dont have any hardware bits to |
15591 | * disable the underrun reporting. Which means we need to start | |
15592 | * out with underrun reporting disabled also on inactive pipes, | |
15593 | * since otherwise we'll complain about the garbage we read when | |
15594 | * e.g. coming up after runtime pm. | |
15595 | * | |
4cc31489 DV |
15596 | * No protection against concurrent access is required - at |
15597 | * worst a fifo underrun happens which also sets this to false. | |
15598 | */ | |
15599 | crtc->cpu_fifo_underrun_disabled = true; | |
15600 | crtc->pch_fifo_underrun_disabled = true; | |
15601 | } | |
24929352 DV |
15602 | } |
15603 | ||
15604 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15605 | { | |
15606 | struct intel_connector *connector; | |
15607 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15608 | bool active = false; |
24929352 DV |
15609 | |
15610 | /* We need to check both for a crtc link (meaning that the | |
15611 | * encoder is active and trying to read from a pipe) and the | |
15612 | * pipe itself being active. */ | |
15613 | bool has_active_crtc = encoder->base.crtc && | |
15614 | to_intel_crtc(encoder->base.crtc)->active; | |
15615 | ||
873ffe69 ML |
15616 | for_each_intel_connector(dev, connector) { |
15617 | if (connector->base.encoder != &encoder->base) | |
15618 | continue; | |
15619 | ||
15620 | active = true; | |
15621 | break; | |
15622 | } | |
15623 | ||
15624 | if (active && !has_active_crtc) { | |
24929352 DV |
15625 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15626 | encoder->base.base.id, | |
8e329a03 | 15627 | encoder->base.name); |
24929352 DV |
15628 | |
15629 | /* Connector is active, but has no active pipe. This is | |
15630 | * fallout from our resume register restoring. Disable | |
15631 | * the encoder manually again. */ | |
15632 | if (encoder->base.crtc) { | |
15633 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15634 | encoder->base.base.id, | |
8e329a03 | 15635 | encoder->base.name); |
24929352 | 15636 | encoder->disable(encoder); |
a62d1497 VS |
15637 | if (encoder->post_disable) |
15638 | encoder->post_disable(encoder); | |
24929352 | 15639 | } |
7f1950fb | 15640 | encoder->base.crtc = NULL; |
24929352 DV |
15641 | |
15642 | /* Inconsistent output/port/pipe state happens presumably due to | |
15643 | * a bug in one of the get_hw_state functions. Or someplace else | |
15644 | * in our code, like the register restore mess on resume. Clamp | |
15645 | * things to off as a safer default. */ | |
3a3371ff | 15646 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15647 | if (connector->encoder != encoder) |
15648 | continue; | |
7f1950fb EE |
15649 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15650 | connector->base.encoder = NULL; | |
24929352 DV |
15651 | } |
15652 | } | |
15653 | /* Enabled encoders without active connectors will be fixed in | |
15654 | * the crtc fixup. */ | |
15655 | } | |
15656 | ||
04098753 | 15657 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15658 | { |
15659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15660 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15661 | |
04098753 ID |
15662 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15663 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15664 | i915_disable_vga(dev); | |
15665 | } | |
15666 | } | |
15667 | ||
15668 | void i915_redisable_vga(struct drm_device *dev) | |
15669 | { | |
15670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15671 | ||
8dc8a27c PZ |
15672 | /* This function can be called both from intel_modeset_setup_hw_state or |
15673 | * at a very early point in our resume sequence, where the power well | |
15674 | * structures are not yet restored. Since this function is at a very | |
15675 | * paranoid "someone might have enabled VGA while we were not looking" | |
15676 | * level, just check if the power well is enabled instead of trying to | |
15677 | * follow the "don't touch the power well if we don't need it" policy | |
15678 | * the rest of the driver uses. */ | |
f458ebbc | 15679 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15680 | return; |
15681 | ||
04098753 | 15682 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15683 | } |
15684 | ||
f9cd7b88 | 15685 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15686 | { |
f9cd7b88 | 15687 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15688 | |
f9cd7b88 | 15689 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15690 | } |
15691 | ||
f9cd7b88 VS |
15692 | /* FIXME read out full plane state for all planes */ |
15693 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15694 | { |
b26d3ea3 | 15695 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15696 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15697 | to_intel_plane_state(primary->state); |
d032ffa0 | 15698 | |
19b8d387 | 15699 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15700 | primary_get_hw_state(to_intel_plane(primary)); |
15701 | ||
15702 | if (plane_state->visible) | |
15703 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15704 | } |
15705 | ||
30e984df | 15706 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15707 | { |
15708 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15709 | enum pipe pipe; | |
24929352 DV |
15710 | struct intel_crtc *crtc; |
15711 | struct intel_encoder *encoder; | |
15712 | struct intel_connector *connector; | |
5358901f | 15713 | int i; |
24929352 | 15714 | |
565602d7 ML |
15715 | dev_priv->active_crtcs = 0; |
15716 | ||
d3fcc808 | 15717 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15718 | struct intel_crtc_state *crtc_state = crtc->config; |
15719 | int pixclk = 0; | |
3b117c8f | 15720 | |
565602d7 ML |
15721 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15722 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15723 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15724 | |
565602d7 ML |
15725 | crtc_state->base.active = crtc_state->base.enable = |
15726 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15727 | ||
15728 | crtc->base.enabled = crtc_state->base.enable; | |
15729 | crtc->active = crtc_state->base.active; | |
15730 | ||
15731 | if (crtc_state->base.active) { | |
15732 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15733 | ||
15734 | if (IS_BROADWELL(dev_priv)) { | |
15735 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15736 | ||
15737 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15738 | if (crtc_state->ips_enabled) | |
15739 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15740 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15741 | IS_CHERRYVIEW(dev_priv) || | |
15742 | IS_BROXTON(dev_priv)) | |
15743 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15744 | else | |
15745 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15746 | } | |
15747 | ||
15748 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15749 | |
f9cd7b88 | 15750 | readout_plane_state(crtc); |
24929352 DV |
15751 | |
15752 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15753 | crtc->base.base.id, | |
15754 | crtc->active ? "enabled" : "disabled"); | |
15755 | } | |
15756 | ||
5358901f DV |
15757 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15758 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15759 | ||
3e369b76 ACO |
15760 | pll->on = pll->get_hw_state(dev_priv, pll, |
15761 | &pll->config.hw_state); | |
5358901f | 15762 | pll->active = 0; |
3e369b76 | 15763 | pll->config.crtc_mask = 0; |
d3fcc808 | 15764 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15765 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15766 | pll->active++; |
3e369b76 | 15767 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15768 | } |
5358901f | 15769 | } |
5358901f | 15770 | |
1e6f2ddc | 15771 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15772 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15773 | |
3e369b76 | 15774 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15775 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15776 | } |
15777 | ||
b2784e15 | 15778 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15779 | pipe = 0; |
15780 | ||
15781 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15782 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15783 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15784 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15785 | } else { |
15786 | encoder->base.crtc = NULL; | |
15787 | } | |
15788 | ||
6f2bcceb | 15789 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15790 | encoder->base.base.id, |
8e329a03 | 15791 | encoder->base.name, |
24929352 | 15792 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15793 | pipe_name(pipe)); |
24929352 DV |
15794 | } |
15795 | ||
3a3371ff | 15796 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15797 | if (connector->get_hw_state(connector)) { |
15798 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15799 | |
15800 | encoder = connector->encoder; | |
15801 | connector->base.encoder = &encoder->base; | |
15802 | ||
15803 | if (encoder->base.crtc && | |
15804 | encoder->base.crtc->state->active) { | |
15805 | /* | |
15806 | * This has to be done during hardware readout | |
15807 | * because anything calling .crtc_disable may | |
15808 | * rely on the connector_mask being accurate. | |
15809 | */ | |
15810 | encoder->base.crtc->state->connector_mask |= | |
15811 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15812 | encoder->base.crtc->state->encoder_mask |= |
15813 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15814 | } |
15815 | ||
24929352 DV |
15816 | } else { |
15817 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15818 | connector->base.encoder = NULL; | |
15819 | } | |
15820 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15821 | connector->base.base.id, | |
c23cc417 | 15822 | connector->base.name, |
24929352 DV |
15823 | connector->base.encoder ? "enabled" : "disabled"); |
15824 | } | |
7f4c6284 VS |
15825 | |
15826 | for_each_intel_crtc(dev, crtc) { | |
15827 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15828 | ||
15829 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15830 | if (crtc->base.state->active) { | |
15831 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15832 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15833 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15834 | ||
15835 | /* | |
15836 | * The initial mode needs to be set in order to keep | |
15837 | * the atomic core happy. It wants a valid mode if the | |
15838 | * crtc's enabled, so we do the above call. | |
15839 | * | |
15840 | * At this point some state updated by the connectors | |
15841 | * in their ->detect() callback has not run yet, so | |
15842 | * no recalculation can be done yet. | |
15843 | * | |
15844 | * Even if we could do a recalculation and modeset | |
15845 | * right now it would cause a double modeset if | |
15846 | * fbdev or userspace chooses a different initial mode. | |
15847 | * | |
15848 | * If that happens, someone indicated they wanted a | |
15849 | * mode change, which means it's safe to do a full | |
15850 | * recalculation. | |
15851 | */ | |
15852 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15853 | |
15854 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15855 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15856 | } |
15857 | } | |
30e984df DV |
15858 | } |
15859 | ||
043e9bda ML |
15860 | /* Scan out the current hw modeset state, |
15861 | * and sanitizes it to the current state | |
15862 | */ | |
15863 | static void | |
15864 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15865 | { |
15866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15867 | enum pipe pipe; | |
30e984df DV |
15868 | struct intel_crtc *crtc; |
15869 | struct intel_encoder *encoder; | |
35c95375 | 15870 | int i; |
30e984df DV |
15871 | |
15872 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15873 | |
15874 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15875 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15876 | intel_sanitize_encoder(encoder); |
15877 | } | |
15878 | ||
055e393f | 15879 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15880 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15881 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15882 | intel_dump_pipe_config(crtc, crtc->config, |
15883 | "[setup_hw_state]"); | |
24929352 | 15884 | } |
9a935856 | 15885 | |
d29b2f9d ACO |
15886 | intel_modeset_update_connector_atomic_state(dev); |
15887 | ||
35c95375 DV |
15888 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15889 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15890 | ||
15891 | if (!pll->on || pll->active) | |
15892 | continue; | |
15893 | ||
15894 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15895 | ||
15896 | pll->disable(dev_priv, pll); | |
15897 | pll->on = false; | |
15898 | } | |
15899 | ||
666a4537 | 15900 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15901 | vlv_wm_get_hw_state(dev); |
15902 | else if (IS_GEN9(dev)) | |
3078999f PB |
15903 | skl_wm_get_hw_state(dev); |
15904 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15905 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15906 | |
15907 | for_each_intel_crtc(dev, crtc) { | |
15908 | unsigned long put_domains; | |
15909 | ||
15910 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15911 | if (WARN_ON(put_domains)) | |
15912 | modeset_put_power_domains(dev_priv, put_domains); | |
15913 | } | |
15914 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
15915 | |
15916 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 15917 | } |
7d0bc1ea | 15918 | |
043e9bda ML |
15919 | void intel_display_resume(struct drm_device *dev) |
15920 | { | |
15921 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15922 | struct intel_connector *conn; | |
15923 | struct intel_plane *plane; | |
15924 | struct drm_crtc *crtc; | |
15925 | int ret; | |
f30da187 | 15926 | |
043e9bda ML |
15927 | if (!state) |
15928 | return; | |
15929 | ||
15930 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15931 | ||
043e9bda ML |
15932 | for_each_crtc(dev, crtc) { |
15933 | struct drm_crtc_state *crtc_state = | |
15934 | drm_atomic_get_crtc_state(state, crtc); | |
15935 | ||
15936 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
15937 | if (ret) | |
15938 | goto err; | |
15939 | ||
15940 | /* force a restore */ | |
15941 | crtc_state->mode_changed = true; | |
45e2b5f6 | 15942 | } |
8af6cf88 | 15943 | |
043e9bda ML |
15944 | for_each_intel_plane(dev, plane) { |
15945 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
15946 | if (ret) | |
15947 | goto err; | |
15948 | } | |
15949 | ||
15950 | for_each_intel_connector(dev, conn) { | |
15951 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
15952 | if (ret) | |
15953 | goto err; | |
15954 | } | |
15955 | ||
15956 | intel_modeset_setup_hw_state(dev); | |
15957 | ||
15958 | i915_redisable_vga(dev); | |
74c090b1 | 15959 | ret = drm_atomic_commit(state); |
043e9bda ML |
15960 | if (!ret) |
15961 | return; | |
15962 | ||
15963 | err: | |
15964 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15965 | drm_atomic_state_free(state); | |
2c7111db CW |
15966 | } |
15967 | ||
15968 | void intel_modeset_gem_init(struct drm_device *dev) | |
15969 | { | |
484b41dd | 15970 | struct drm_crtc *c; |
2ff8fde1 | 15971 | struct drm_i915_gem_object *obj; |
e0d6149b | 15972 | int ret; |
484b41dd | 15973 | |
ae48434c | 15974 | intel_init_gt_powersave(dev); |
ae48434c | 15975 | |
1833b134 | 15976 | intel_modeset_init_hw(dev); |
02e792fb DV |
15977 | |
15978 | intel_setup_overlay(dev); | |
484b41dd JB |
15979 | |
15980 | /* | |
15981 | * Make sure any fbs we allocated at startup are properly | |
15982 | * pinned & fenced. When we do the allocation it's too early | |
15983 | * for this. | |
15984 | */ | |
70e1e0ec | 15985 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15986 | obj = intel_fb_obj(c->primary->fb); |
15987 | if (obj == NULL) | |
484b41dd JB |
15988 | continue; |
15989 | ||
e0d6149b TU |
15990 | mutex_lock(&dev->struct_mutex); |
15991 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15992 | c->primary->fb, | |
7580d774 | 15993 | c->primary->state); |
e0d6149b TU |
15994 | mutex_unlock(&dev->struct_mutex); |
15995 | if (ret) { | |
484b41dd JB |
15996 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15997 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15998 | drm_framebuffer_unreference(c->primary->fb); |
15999 | c->primary->fb = NULL; | |
36750f28 | 16000 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 16001 | update_state_fb(c->primary); |
36750f28 | 16002 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16003 | } |
16004 | } | |
0962c3c9 VS |
16005 | |
16006 | intel_backlight_register(dev); | |
79e53945 JB |
16007 | } |
16008 | ||
4932e2c3 ID |
16009 | void intel_connector_unregister(struct intel_connector *intel_connector) |
16010 | { | |
16011 | struct drm_connector *connector = &intel_connector->base; | |
16012 | ||
16013 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 16014 | drm_connector_unregister(connector); |
4932e2c3 ID |
16015 | } |
16016 | ||
79e53945 JB |
16017 | void intel_modeset_cleanup(struct drm_device *dev) |
16018 | { | |
652c393a | 16019 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 16020 | struct intel_connector *connector; |
652c393a | 16021 | |
2eb5252e ID |
16022 | intel_disable_gt_powersave(dev); |
16023 | ||
0962c3c9 VS |
16024 | intel_backlight_unregister(dev); |
16025 | ||
fd0c0642 DV |
16026 | /* |
16027 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16028 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16029 | * experience fancy races otherwise. |
16030 | */ | |
2aeb7d3a | 16031 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16032 | |
fd0c0642 DV |
16033 | /* |
16034 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16035 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16036 | */ | |
f87ea761 | 16037 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16038 | |
723bfd70 JB |
16039 | intel_unregister_dsm_handler(); |
16040 | ||
c937ab3e | 16041 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16042 | |
1630fe75 CW |
16043 | /* flush any delayed tasks or pending work */ |
16044 | flush_scheduled_work(); | |
16045 | ||
db31af1d | 16046 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16047 | for_each_intel_connector(dev, connector) |
16048 | connector->unregister(connector); | |
d9255d57 | 16049 | |
79e53945 | 16050 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
16051 | |
16052 | intel_cleanup_overlay(dev); | |
ae48434c | 16053 | |
ae48434c | 16054 | intel_cleanup_gt_powersave(dev); |
f5949141 DV |
16055 | |
16056 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16057 | } |
16058 | ||
f1c79df3 ZW |
16059 | /* |
16060 | * Return which encoder is currently attached for connector. | |
16061 | */ | |
df0e9248 | 16062 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16063 | { |
df0e9248 CW |
16064 | return &intel_attached_encoder(connector)->base; |
16065 | } | |
f1c79df3 | 16066 | |
df0e9248 CW |
16067 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16068 | struct intel_encoder *encoder) | |
16069 | { | |
16070 | connector->encoder = encoder; | |
16071 | drm_mode_connector_attach_encoder(&connector->base, | |
16072 | &encoder->base); | |
79e53945 | 16073 | } |
28d52043 DA |
16074 | |
16075 | /* | |
16076 | * set vga decode state - true == enable VGA decode | |
16077 | */ | |
16078 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16079 | { | |
16080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16081 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16082 | u16 gmch_ctrl; |
16083 | ||
75fa041d CW |
16084 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16085 | DRM_ERROR("failed to read control word\n"); | |
16086 | return -EIO; | |
16087 | } | |
16088 | ||
c0cc8a55 CW |
16089 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16090 | return 0; | |
16091 | ||
28d52043 DA |
16092 | if (state) |
16093 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16094 | else | |
16095 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16096 | |
16097 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16098 | DRM_ERROR("failed to write control word\n"); | |
16099 | return -EIO; | |
16100 | } | |
16101 | ||
28d52043 DA |
16102 | return 0; |
16103 | } | |
c4a1d9e4 | 16104 | |
c4a1d9e4 | 16105 | struct intel_display_error_state { |
ff57f1b0 PZ |
16106 | |
16107 | u32 power_well_driver; | |
16108 | ||
63b66e5b CW |
16109 | int num_transcoders; |
16110 | ||
c4a1d9e4 CW |
16111 | struct intel_cursor_error_state { |
16112 | u32 control; | |
16113 | u32 position; | |
16114 | u32 base; | |
16115 | u32 size; | |
52331309 | 16116 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16117 | |
16118 | struct intel_pipe_error_state { | |
ddf9c536 | 16119 | bool power_domain_on; |
c4a1d9e4 | 16120 | u32 source; |
f301b1e1 | 16121 | u32 stat; |
52331309 | 16122 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16123 | |
16124 | struct intel_plane_error_state { | |
16125 | u32 control; | |
16126 | u32 stride; | |
16127 | u32 size; | |
16128 | u32 pos; | |
16129 | u32 addr; | |
16130 | u32 surface; | |
16131 | u32 tile_offset; | |
52331309 | 16132 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16133 | |
16134 | struct intel_transcoder_error_state { | |
ddf9c536 | 16135 | bool power_domain_on; |
63b66e5b CW |
16136 | enum transcoder cpu_transcoder; |
16137 | ||
16138 | u32 conf; | |
16139 | ||
16140 | u32 htotal; | |
16141 | u32 hblank; | |
16142 | u32 hsync; | |
16143 | u32 vtotal; | |
16144 | u32 vblank; | |
16145 | u32 vsync; | |
16146 | } transcoder[4]; | |
c4a1d9e4 CW |
16147 | }; |
16148 | ||
16149 | struct intel_display_error_state * | |
16150 | intel_display_capture_error_state(struct drm_device *dev) | |
16151 | { | |
fbee40df | 16152 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16153 | struct intel_display_error_state *error; |
63b66e5b CW |
16154 | int transcoders[] = { |
16155 | TRANSCODER_A, | |
16156 | TRANSCODER_B, | |
16157 | TRANSCODER_C, | |
16158 | TRANSCODER_EDP, | |
16159 | }; | |
c4a1d9e4 CW |
16160 | int i; |
16161 | ||
63b66e5b CW |
16162 | if (INTEL_INFO(dev)->num_pipes == 0) |
16163 | return NULL; | |
16164 | ||
9d1cb914 | 16165 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16166 | if (error == NULL) |
16167 | return NULL; | |
16168 | ||
190be112 | 16169 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16170 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16171 | ||
055e393f | 16172 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16173 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16174 | __intel_display_power_is_enabled(dev_priv, |
16175 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16176 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16177 | continue; |
16178 | ||
5efb3e28 VS |
16179 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16180 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16181 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16182 | |
16183 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16184 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16185 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16186 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16187 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16188 | } | |
ca291363 PZ |
16189 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16190 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16191 | if (INTEL_INFO(dev)->gen >= 4) { |
16192 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16193 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16194 | } | |
16195 | ||
c4a1d9e4 | 16196 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16197 | |
3abfce77 | 16198 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16199 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16200 | } |
16201 | ||
16202 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16203 | if (HAS_DDI(dev_priv->dev)) | |
16204 | error->num_transcoders++; /* Account for eDP. */ | |
16205 | ||
16206 | for (i = 0; i < error->num_transcoders; i++) { | |
16207 | enum transcoder cpu_transcoder = transcoders[i]; | |
16208 | ||
ddf9c536 | 16209 | error->transcoder[i].power_domain_on = |
f458ebbc | 16210 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16211 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16212 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16213 | continue; |
16214 | ||
63b66e5b CW |
16215 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16216 | ||
16217 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16218 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16219 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16220 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16221 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16222 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16223 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16224 | } |
16225 | ||
16226 | return error; | |
16227 | } | |
16228 | ||
edc3d884 MK |
16229 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16230 | ||
c4a1d9e4 | 16231 | void |
edc3d884 | 16232 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16233 | struct drm_device *dev, |
16234 | struct intel_display_error_state *error) | |
16235 | { | |
055e393f | 16236 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16237 | int i; |
16238 | ||
63b66e5b CW |
16239 | if (!error) |
16240 | return; | |
16241 | ||
edc3d884 | 16242 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16243 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16244 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16245 | error->power_well_driver); |
055e393f | 16246 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16247 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16248 | err_printf(m, " Power: %s\n", |
87ad3212 | 16249 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16250 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16251 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16252 | |
16253 | err_printf(m, "Plane [%d]:\n", i); | |
16254 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16255 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16256 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16257 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16258 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16259 | } |
4b71a570 | 16260 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16261 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16262 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16263 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16264 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16265 | } |
16266 | ||
edc3d884 MK |
16267 | err_printf(m, "Cursor [%d]:\n", i); |
16268 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16269 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16270 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16271 | } |
63b66e5b CW |
16272 | |
16273 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16274 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16275 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16276 | err_printf(m, " Power: %s\n", |
87ad3212 | 16277 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16278 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16279 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16280 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16281 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16282 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16283 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16284 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16285 | } | |
c4a1d9e4 | 16286 | } |