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drm/i915: drop unnecessary clearing of pch dp transcoder timings
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
419 unsigned long flags;
420 u32 val = 0;
421
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
425 goto out_unlock;
426 }
427
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430 DPIO_BYTE);
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
433 goto out_unlock;
434 }
435 val = I915_READ(DPIO_DATA);
436
437out_unlock:
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439 return val;
440}
441
a0c4da24
JB		 442static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443 u32 val)
444{
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
450 goto out_unlock;
451 }
452
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456 DPIO_BYTE);
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
459
460out_unlock:
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462}
463
57f350b6
JB		 464static void vlv_init_dpio(struct drm_device *dev)
465{
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
473}
474
1b894b59
CW		 475static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
476 int refclk)
2c07245f 477{
b91ad0ec 478 struct drm_device *dev = crtc->dev;
2c07245f 479 const intel_limit_t *limit;
b91ad0ec
ZW		 480
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 482 if (intel_is_dual_link_lvds(dev)) {
b91ad0ec 483 /* LVDS dual channel */
1b894b59 484 if (refclk == 100000)
b91ad0ec
ZW		 485 limit = &intel_limits_ironlake_dual_lvds_100m;
486 else
487 limit = &intel_limits_ironlake_dual_lvds;
488 } else {
1b894b59 489 if (refclk == 100000)
b91ad0ec
ZW		 490 limit = &intel_limits_ironlake_single_lvds_100m;
491 else
492 limit = &intel_limits_ironlake_single_lvds;
493 }
494 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 495 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 496 limit = &intel_limits_ironlake_display_port;
2c07245f 497 else
b91ad0ec 498 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 499
500 return limit;
501}
502
044c7c41
ML		 503static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
504{
505 struct drm_device *dev = crtc->dev;
044c7c41
ML		 506 const intel_limit_t *limit;
507
508 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 509 if (intel_is_dual_link_lvds(dev))
044c7c41 510 /* LVDS with dual channel */
e4b36699 511 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 512 else
513 /* LVDS with dual channel */
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 515 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
044c7c41 518 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
0206e353 520 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 521 limit = &intel_limits_g4x_display_port;
044c7c41 522 } else /* The option is for other outputs */
e4b36699 523 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 524
525 return limit;
526}
527
1b894b59 528static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 529{
530 struct drm_device *dev = crtc->dev;
531 const intel_limit_t *limit;
532
bad720ff 533 if (HAS_PCH_SPLIT(dev))
1b894b59 534 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 535 else if (IS_G4X(dev)) {
044c7c41 536 limit = intel_g4x_limit(crtc);
f2b115e6 537 } else if (IS_PINEVIEW(dev)) {
2177832f 538 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 539 limit = &intel_limits_pineview_lvds;
2177832f 540 else
f2b115e6 541 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 542 } else if (IS_VALLEYVIEW(dev)) {
543 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
544 limit = &intel_limits_vlv_dac;
545 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
546 limit = &intel_limits_vlv_hdmi;
547 else
548 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 549 } else if (!IS_GEN2(dev)) {
550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
551 limit = &intel_limits_i9xx_lvds;
552 else
553 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 554 } else {
555 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 556 limit = &intel_limits_i8xx_lvds;
79e53945 557 else
e4b36699 558 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
568 clock->vco = refclk * clock->m / clock->n;
569 clock->dot = clock->vco / clock->p;
570}
571
572static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
573{
f2b115e6
AJ		 574 if (IS_PINEVIEW(dev)) {
575 pineview_clock(refclk, clock);
2177832f
SL		 576 return;
577 }
79e53945
JB		 578 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
579 clock->p = clock->p1 * clock->p2;
580 clock->vco = refclk * clock->m / (clock->n + 2);
581 clock->dot = clock->vco / clock->p;
582}
583
79e53945
JB		 584/**
585 * Returns whether any output on the specified pipe is of the specified type
586 */
4ef69c7a 587bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 588{
4ef69c7a 589 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 590 struct intel_encoder *encoder;
591
6c2b7c12
DV		 592 for_each_encoder_on_crtc(dev, crtc, encoder)
593 if (encoder->type == type)
4ef69c7a
CW		 594 return true;
595
596 return false;
79e53945
JB		 597}
598
7c04d1d9 599#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 600/**
601 * Returns whether the given set of divisors are valid for a given refclk with
602 * the given connectors.
603 */
604
1b894b59
CW		 605static bool intel_PLL_is_valid(struct drm_device *dev,
606 const intel_limit_t *limit,
607 const intel_clock_t *clock)
79e53945 608{
79e53945 609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 610 INTELPllInvalid("p1 out of range\n");
79e53945 611 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 612 INTELPllInvalid("p out of range\n");
79e53945 613 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 614 INTELPllInvalid("m2 out of range\n");
79e53945 615 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 616 INTELPllInvalid("m1 out of range\n");
f2b115e6 617 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 618 INTELPllInvalid("m1 <= m2\n");
79e53945 619 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 620 INTELPllInvalid("m out of range\n");
79e53945 621 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 622 INTELPllInvalid("n out of range\n");
79e53945 623 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 624 INTELPllInvalid("vco out of range\n");
79e53945
JB		 625 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
626 * connector, etc., rather than just a single range.
627 */
628 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 629 INTELPllInvalid("dot out of range\n");
79e53945
JB		 630
631 return true;
632}
633
d4906093
ML		 634static bool
635intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 636 int target, int refclk, intel_clock_t *match_clock,
637 intel_clock_t *best_clock)
d4906093 638
79e53945
JB		 639{
640 struct drm_device *dev = crtc->dev;
79e53945 641 intel_clock_t clock;
79e53945
JB		 642 int err = target;
643
a210b028 644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 645 /*
a210b028
DV		 646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
79e53945 649 */
1974cad0 650 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 651 clock.p2 = limit->p2.p2_fast;
652 else
653 clock.p2 = limit->p2.p2_slow;
654 } else {
655 if (target < limit->p2.dot_limit)
656 clock.p2 = limit->p2.p2_slow;
657 else
658 clock.p2 = limit->p2.p2_fast;
659 }
660
0206e353 661 memset(best_clock, 0, sizeof(*best_clock));
79e53945 662
42158660
ZY		 663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
664 clock.m1++) {
665 for (clock.m2 = limit->m2.min;
666 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 667 /* m1 is always 0 in Pineview */
668 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 669 break;
670 for (clock.n = limit->n.min;
671 clock.n <= limit->n.max; clock.n++) {
672 for (clock.p1 = limit->p1.min;
673 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 674 int this_err;
675
2177832f 676 intel_clock(dev, refclk, &clock);
1b894b59
CW		 677 if (!intel_PLL_is_valid(dev, limit,
678 &clock))
79e53945 679 continue;
cec2f356
SP		 680 if (match_clock &&
681 clock.p != match_clock->p)
682 continue;
79e53945
JB		 683
684 this_err = abs(clock.dot - target);
685 if (this_err < err) {
686 *best_clock = clock;
687 err = this_err;
688 }
689 }
690 }
691 }
692 }
693
694 return (err != target);
695}
696
d4906093
ML		 697static bool
698intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 699 int target, int refclk, intel_clock_t *match_clock,
700 intel_clock_t *best_clock)
d4906093
ML		 701{
702 struct drm_device *dev = crtc->dev;
d4906093
ML		 703 intel_clock_t clock;
704 int max_n;
705 bool found;
6ba770dc
AJ		 706 /* approximately equals target * 0.00585 */
707 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 708 found = false;
709
710 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 711 int lvds_reg;
712
c619eed4 713 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 714 lvds_reg = PCH_LVDS;
715 else
716 lvds_reg = LVDS;
1974cad0 717 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729 max_n = limit->n.max;
f77f13e2 730 /* based on hardware requirement, prefer smaller n to precision */
d4906093 731 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 732 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 733 for (clock.m1 = limit->m1.max;
734 clock.m1 >= limit->m1.min; clock.m1--) {
735 for (clock.m2 = limit->m2.max;
736 clock.m2 >= limit->m2.min; clock.m2--) {
737 for (clock.p1 = limit->p1.max;
738 clock.p1 >= limit->p1.min; clock.p1--) {
739 int this_err;
740
2177832f 741 intel_clock(dev, refclk, &clock);
1b894b59
CW		 742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
d4906093 744 continue;
cec2f356
SP		 745 if (match_clock &&
746 clock.p != match_clock->p)
747 continue;
1b894b59
CW		 748
749 this_err = abs(clock.dot - target);
d4906093
ML		 750 if (this_err < err_most) {
751 *best_clock = clock;
752 err_most = this_err;
753 max_n = clock.n;
754 found = true;
755 }
756 }
757 }
758 }
759 }
2c07245f
ZW		 760 return found;
761}
762
5eb08b69 763static bool
f2b115e6 764intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 765 int target, int refclk, intel_clock_t *match_clock,
766 intel_clock_t *best_clock)
5eb08b69
ZW		 767{
768 struct drm_device *dev = crtc->dev;
769 intel_clock_t clock;
4547668a 770
5eb08b69
ZW		 771 if (target < 200000) {
772 clock.n = 1;
773 clock.p1 = 2;
774 clock.p2 = 10;
775 clock.m1 = 12;
776 clock.m2 = 9;
777 } else {
778 clock.n = 2;
779 clock.p1 = 1;
780 clock.p2 = 10;
781 clock.m1 = 14;
782 clock.m2 = 8;
783 }
784 intel_clock(dev, refclk, &clock);
785 memcpy(best_clock, &clock, sizeof(intel_clock_t));
786 return true;
787}
788
a4fc5ed6
KP		 789/* DisplayPort has only two frequencies, 162MHz and 270MHz */
790static bool
791intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 792 int target, int refclk, intel_clock_t *match_clock,
793 intel_clock_t *best_clock)
a4fc5ed6 794{
5eddb70b
CW		 795 intel_clock_t clock;
796 if (target < 200000) {
797 clock.p1 = 2;
798 clock.p2 = 10;
799 clock.n = 2;
800 clock.m1 = 23;
801 clock.m2 = 8;
802 } else {
803 clock.p1 = 1;
804 clock.p2 = 10;
805 clock.n = 1;
806 clock.m1 = 14;
807 clock.m2 = 2;
808 }
809 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
810 clock.p = (clock.p1 * clock.p2);
811 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
812 clock.vco = 0;
813 memcpy(best_clock, &clock, sizeof(intel_clock_t));
814 return true;
a4fc5ed6 815}
a0c4da24
JB		 816static bool
817intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
818 int target, int refclk, intel_clock_t *match_clock,
819 intel_clock_t *best_clock)
820{
821 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
822 u32 m, n, fastclk;
823 u32 updrate, minupdate, fracbits, p;
824 unsigned long bestppm, ppm, absppm;
825 int dotclk, flag;
826
af447bd3 827 flag = 0;
a0c4da24
JB		 828 dotclk = target * 1000;
829 bestppm = 1000000;
830 ppm = absppm = 0;
831 fastclk = dotclk / (2*100);
832 updrate = 0;
833 minupdate = 19200;
834 fracbits = 1;
835 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
836 bestm1 = bestm2 = bestp1 = bestp2 = 0;
837
838 /* based on hardware requirement, prefer smaller n to precision */
839 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
840 updrate = refclk / n;
841 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
842 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
843 if (p2 > 10)
844 p2 = p2 - 1;
845 p = p1 * p2;
846 /* based on hardware requirement, prefer bigger m1,m2 values */
847 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
848 m2 = (((2*(fastclk * p * n / m1 )) +
849 refclk) / (2*refclk));
850 m = m1 * m2;
851 vco = updrate * m;
852 if (vco >= limit->vco.min && vco < limit->vco.max) {
853 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
854 absppm = (ppm > 0) ? ppm : (-ppm);
855 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
856 bestppm = 0;
857 flag = 1;
858 }
859 if (absppm < bestppm - 10) {
860 bestppm = absppm;
861 flag = 1;
862 }
863 if (flag) {
864 bestn = n;
865 bestm1 = m1;
866 bestm2 = m2;
867 bestp1 = p1;
868 bestp2 = p2;
869 flag = 0;
870 }
871 }
872 }
873 }
874 }
875 }
876 best_clock->n = bestn;
877 best_clock->m1 = bestm1;
878 best_clock->m2 = bestm2;
879 best_clock->p1 = bestp1;
880 best_clock->p2 = bestp2;
881
882 return true;
883}
a4fc5ed6 884
a5c961d1
PZ		 885enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
886 enum pipe pipe)
887{
888 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 return intel_crtc->cpu_transcoder;
892}
893
a928d536
PZ		 894static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
895{
896 struct drm_i915_private *dev_priv = dev->dev_private;
897 u32 frame, frame_reg = PIPEFRAME(pipe);
898
899 frame = I915_READ(frame_reg);
900
901 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
902 DRM_DEBUG_KMS("vblank wait timed out\n");
903}
904
9d0498a2
JB		 905/**
906 * intel_wait_for_vblank - wait for vblank on a given pipe
907 * @dev: drm device
908 * @pipe: pipe to wait for
909 *
910 * Wait for vblank to occur on a given pipe. Needed for various bits of
911 * mode setting code.
912 */
913void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 914{
9d0498a2 915 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 916 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 917
a928d536
PZ		 918 if (INTEL_INFO(dev)->gen >= 5) {
919 ironlake_wait_for_vblank(dev, pipe);
920 return;
921 }
922
300387c0
CW		 923 /* Clear existing vblank status. Note this will clear any other
924 * sticky status fields as well.
925 *
926 * This races with i915_driver_irq_handler() with the result
927 * that either function could miss a vblank event. Here it is not
928 * fatal, as we will either wait upon the next vblank interrupt or
929 * timeout. Generally speaking intel_wait_for_vblank() is only
930 * called during modeset at which time the GPU should be idle and
931 * should *not* be performing page flips and thus not waiting on
932 * vblanks...
933 * Currently, the result of us stealing a vblank from the irq
934 * handler is that a single frame will be skipped during swapbuffers.
935 */
936 I915_WRITE(pipestat_reg,
937 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
938
9d0498a2 939 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 940 if (wait_for(I915_READ(pipestat_reg) &
941 PIPE_VBLANK_INTERRUPT_STATUS,
942 50))
9d0498a2
JB		 943 DRM_DEBUG_KMS("vblank wait timed out\n");
944}
945
ab7ad7f6
KP		 946/*
947 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 948 * @dev: drm device
949 * @pipe: pipe to wait for
950 *
951 * After disabling a pipe, we can't wait for vblank in the usual way,
952 * spinning on the vblank interrupt status bit, since we won't actually
953 * see an interrupt when the pipe is disabled.
954 *
ab7ad7f6
KP		 955 * On Gen4 and above:
956 * wait for the pipe register state bit to turn off
957 *
958 * Otherwise:
959 * wait for the display line value to settle (it usually
960 * ends up stopping at the start of the next frame).
58e10eb9 961 *
9d0498a2 962 */
58e10eb9 963void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 964{
965 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 966 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
967 pipe);
ab7ad7f6
KP		 968
969 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 970 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 971
972 /* Wait for the Pipe State to go off */
58e10eb9
CW		 973 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
974 100))
284637d9 975 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 976 } else {
837ba00f 977 u32 last_line, line_mask;
58e10eb9 978 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 979 unsigned long timeout = jiffies + msecs_to_jiffies(100);
980
837ba00f
PZ		 981 if (IS_GEN2(dev))
982 line_mask = DSL_LINEMASK_GEN2;
983 else
984 line_mask = DSL_LINEMASK_GEN3;
985
ab7ad7f6
KP		 986 /* Wait for the display line to settle */
987 do {
837ba00f 988 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 989 mdelay(5);
837ba00f 990 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 991 time_after(timeout, jiffies));
992 if (time_after(jiffies, timeout))
284637d9 993 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 994 }
79e53945
JB		 995}
996
b24e7179
JB		 997static const char *state_string(bool enabled)
998{
999 return enabled ? "on" : "off";
1000}
1001
1002/* Only for pre-ILK configs */
1003static void assert_pll(struct drm_i915_private *dev_priv,
1004 enum pipe pipe, bool state)
1005{
1006 int reg;
1007 u32 val;
1008 bool cur_state;
1009
1010 reg = DPLL(pipe);
1011 val = I915_READ(reg);
1012 cur_state = !!(val & DPLL_VCO_ENABLE);
1013 WARN(cur_state != state,
1014 "PLL state assertion failure (expected %s, current %s)\n",
1015 state_string(state), state_string(cur_state));
1016}
1017#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1018#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1019
040484af
JB		 1020/* For ILK+ */
1021static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1022 struct intel_pch_pll *pll,
1023 struct intel_crtc *crtc,
1024 bool state)
040484af 1025{
040484af
JB		 1026 u32 val;
1027 bool cur_state;
1028
9d82aa17
ED		 1029 if (HAS_PCH_LPT(dev_priv->dev)) {
1030 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1031 return;
1032 }
1033
92b27b08
CW		 1034 if (WARN (!pll,
1035 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1036 return;
ee7b9f93 1037
92b27b08
CW		 1038 val = I915_READ(pll->pll_reg);
1039 cur_state = !!(val & DPLL_VCO_ENABLE);
1040 WARN(cur_state != state,
1041 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1042 pll->pll_reg, state_string(state), state_string(cur_state), val);
1043
1044 /* Make sure the selected PLL is correctly attached to the transcoder */
1045 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1046 u32 pch_dpll;
1047
1048 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1049 cur_state = pll->pll_reg == _PCH_DPLL_B;
1050 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1051 "PLL[%d] not attached to this transcoder %d: %08x\n",
1052 cur_state, crtc->pipe, pch_dpll)) {
1053 cur_state = !!(val >> (4*crtc->pipe + 3));
1054 WARN(cur_state != state,
1055 "PLL[%d] not %s on this transcoder %d: %08x\n",
1056 pll->pll_reg == _PCH_DPLL_B,
1057 state_string(state),
1058 crtc->pipe,
1059 val);
1060 }
d3ccbe86 1061 }
040484af 1062}
92b27b08
CW		 1063#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1064#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1065
1066static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1067 enum pipe pipe, bool state)
1068{
1069 int reg;
1070 u32 val;
1071 bool cur_state;
ad80a810
PZ		 1072 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1073 pipe);
040484af 1074
affa9354
PZ		 1075 if (HAS_DDI(dev_priv->dev)) {
1076 /* DDI does not have a specific FDI_TX register */
ad80a810 1077 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1078 val = I915_READ(reg);
ad80a810 1079 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1080 } else {
1081 reg = FDI_TX_CTL(pipe);
1082 val = I915_READ(reg);
1083 cur_state = !!(val & FDI_TX_ENABLE);
1084 }
040484af
JB		 1085 WARN(cur_state != state,
1086 "FDI TX state assertion failure (expected %s, current %s)\n",
1087 state_string(state), state_string(cur_state));
1088}
1089#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1090#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1091
1092static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1093 enum pipe pipe, bool state)
1094{
1095 int reg;
1096 u32 val;
1097 bool cur_state;
1098
d63fa0dc
PZ		 1099 reg = FDI_RX_CTL(pipe);
1100 val = I915_READ(reg);
1101 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1102 WARN(cur_state != state,
1103 "FDI RX state assertion failure (expected %s, current %s)\n",
1104 state_string(state), state_string(cur_state));
1105}
1106#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1107#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1108
1109static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1110 enum pipe pipe)
1111{
1112 int reg;
1113 u32 val;
1114
1115 /* ILK FDI PLL is always enabled */
1116 if (dev_priv->info->gen == 5)
1117 return;
1118
bf507ef7 1119 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1120 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1121 return;
1122
040484af
JB		 1123 reg = FDI_TX_CTL(pipe);
1124 val = I915_READ(reg);
1125 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1126}
1127
1128static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1129 enum pipe pipe)
1130{
1131 int reg;
1132 u32 val;
1133
1134 reg = FDI_RX_CTL(pipe);
1135 val = I915_READ(reg);
1136 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1137}
1138
ea0760cf
JB		 1139static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1140 enum pipe pipe)
1141{
1142 int pp_reg, lvds_reg;
1143 u32 val;
1144 enum pipe panel_pipe = PIPE_A;
0de3b485 1145 bool locked = true;
ea0760cf
JB		 1146
1147 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1148 pp_reg = PCH_PP_CONTROL;
1149 lvds_reg = PCH_LVDS;
1150 } else {
1151 pp_reg = PP_CONTROL;
1152 lvds_reg = LVDS;
1153 }
1154
1155 val = I915_READ(pp_reg);
1156 if (!(val & PANEL_POWER_ON) ||
1157 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1158 locked = false;
1159
1160 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1161 panel_pipe = PIPE_B;
1162
1163 WARN(panel_pipe == pipe && locked,
1164 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1165 pipe_name(pipe));
ea0760cf
JB		 1166}
1167
b840d907
JB		 1168void assert_pipe(struct drm_i915_private *dev_priv,
1169 enum pipe pipe, bool state)
b24e7179
JB		 1170{
1171 int reg;
1172 u32 val;
63d7bbe9 1173 bool cur_state;
702e7a56
PZ		 1174 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1175 pipe);
b24e7179 1176
8e636784
DV		 1177 /* if we need the pipe A quirk it must be always on */
1178 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1179 state = true;
1180
702e7a56 1181 reg = PIPECONF(cpu_transcoder);
b24e7179 1182 val = I915_READ(reg);
63d7bbe9
JB		 1183 cur_state = !!(val & PIPECONF_ENABLE);
1184 WARN(cur_state != state,
1185 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1186 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1187}
1188
931872fc
CW		 1189static void assert_plane(struct drm_i915_private *dev_priv,
1190 enum plane plane, bool state)
b24e7179
JB		 1191{
1192 int reg;
1193 u32 val;
931872fc 1194 bool cur_state;
b24e7179
JB		 1195
1196 reg = DSPCNTR(plane);
1197 val = I915_READ(reg);
931872fc
CW		 1198 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1199 WARN(cur_state != state,
1200 "plane %c assertion failure (expected %s, current %s)\n",
1201 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1202}
1203
931872fc
CW		 1204#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1205#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1206
b24e7179
JB		 1207static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1208 enum pipe pipe)
1209{
1210 int reg, i;
1211 u32 val;
1212 int cur_pipe;
1213
19ec1358 1214 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1215 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1216 reg = DSPCNTR(pipe);
1217 val = I915_READ(reg);
1218 WARN((val & DISPLAY_PLANE_ENABLE),
1219 "plane %c assertion failure, should be disabled but not\n",
1220 plane_name(pipe));
19ec1358 1221 return;
28c05794 1222 }
19ec1358 1223
b24e7179
JB		 1224 /* Need to check both planes against the pipe */
1225 for (i = 0; i < 2; i++) {
1226 reg = DSPCNTR(i);
1227 val = I915_READ(reg);
1228 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1229 DISPPLANE_SEL_PIPE_SHIFT;
1230 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1231 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1232 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1233 }
1234}
1235
92f2584a
JB		 1236static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1237{
1238 u32 val;
1239 bool enabled;
1240
9d82aa17
ED		 1241 if (HAS_PCH_LPT(dev_priv->dev)) {
1242 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1243 return;
1244 }
1245
92f2584a
JB		 1246 val = I915_READ(PCH_DREF_CONTROL);
1247 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1248 DREF_SUPERSPREAD_SOURCE_MASK));
1249 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1250}
1251
1252static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe)
1254{
1255 int reg;
1256 u32 val;
1257 bool enabled;
1258
1259 reg = TRANSCONF(pipe);
1260 val = I915_READ(reg);
1261 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1262 WARN(enabled,
1263 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1264 pipe_name(pipe));
92f2584a
JB		 1265}
1266
4e634389
KP		 1267static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1268 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1269{
1270 if ((val & DP_PORT_EN) == 0)
1271 return false;
1272
1273 if (HAS_PCH_CPT(dev_priv->dev)) {
1274 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1275 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1276 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1277 return false;
1278 } else {
1279 if ((val & DP_PIPE_MASK) != (pipe << 30))
1280 return false;
1281 }
1282 return true;
1283}
1284
1519b995
KP		 1285static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1286 enum pipe pipe, u32 val)
1287{
1288 if ((val & PORT_ENABLE) == 0)
1289 return false;
1290
1291 if (HAS_PCH_CPT(dev_priv->dev)) {
1292 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1293 return false;
1294 } else {
1295 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1296 return false;
1297 }
1298 return true;
1299}
1300
1301static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1302 enum pipe pipe, u32 val)
1303{
1304 if ((val & LVDS_PORT_EN) == 0)
1305 return false;
1306
1307 if (HAS_PCH_CPT(dev_priv->dev)) {
1308 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1309 return false;
1310 } else {
1311 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1312 return false;
1313 }
1314 return true;
1315}
1316
1317static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, u32 val)
1319{
1320 if ((val & ADPA_DAC_ENABLE) == 0)
1321 return false;
1322 if (HAS_PCH_CPT(dev_priv->dev)) {
1323 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1324 return false;
1325 } else {
1326 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1327 return false;
1328 }
1329 return true;
1330}
1331
291906f1 1332static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1333 enum pipe pipe, int reg, u32 port_sel)
291906f1 1334{
47a05eca 1335 u32 val = I915_READ(reg);
4e634389 1336 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1337 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1338 reg, pipe_name(pipe));
de9a35ab 1339
75c5da27
DV		 1340 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1341 && (val & DP_PIPEB_SELECT),
de9a35ab 1342 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1343}
1344
1345static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1346 enum pipe pipe, int reg)
1347{
47a05eca 1348 u32 val = I915_READ(reg);
b70ad586 1349 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1350 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1351 reg, pipe_name(pipe));
de9a35ab 1352
75c5da27
DV		 1353 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1354 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1355 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1356}
1357
1358static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1359 enum pipe pipe)
1360{
1361 int reg;
1362 u32 val;
291906f1 1363
f0575e92
KP		 1364 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1365 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1366 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1367
1368 reg = PCH_ADPA;
1369 val = I915_READ(reg);
b70ad586 1370 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1371 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1372 pipe_name(pipe));
291906f1
JB		 1373
1374 reg = PCH_LVDS;
1375 val = I915_READ(reg);
b70ad586 1376 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1377 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1378 pipe_name(pipe));
291906f1
JB		 1379
1380 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1381 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1382 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1383}
1384
63d7bbe9
JB		 1385/**
1386 * intel_enable_pll - enable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to enable
1389 *
1390 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1391 * make sure the PLL reg is writable first though, since the panel write
1392 * protect mechanism may be enabled.
1393 *
1394 * Note! This is for pre-ILK only.
7434a255
TR		 1395 *
1396 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1397 */
1398static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1399{
1400 int reg;
1401 u32 val;
1402
1403 /* No really, not for ILK+ */
a0c4da24 1404 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1405
1406 /* PLL is protected by panel, make sure we can write it */
1407 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1408 assert_panel_unlocked(dev_priv, pipe);
1409
1410 reg = DPLL(pipe);
1411 val = I915_READ(reg);
1412 val |= DPLL_VCO_ENABLE;
1413
1414 /* We do this three times for luck */
1415 I915_WRITE(reg, val);
1416 POSTING_READ(reg);
1417 udelay(150); /* wait for warmup */
1418 I915_WRITE(reg, val);
1419 POSTING_READ(reg);
1420 udelay(150); /* wait for warmup */
1421 I915_WRITE(reg, val);
1422 POSTING_READ(reg);
1423 udelay(150); /* wait for warmup */
1424}
1425
1426/**
1427 * intel_disable_pll - disable a PLL
1428 * @dev_priv: i915 private structure
1429 * @pipe: pipe PLL to disable
1430 *
1431 * Disable the PLL for @pipe, making sure the pipe is off first.
1432 *
1433 * Note! This is for pre-ILK only.
1434 */
1435static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436{
1437 int reg;
1438 u32 val;
1439
1440 /* Don't disable pipe A or pipe A PLLs if needed */
1441 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1442 return;
1443
1444 /* Make sure the pipe isn't still relying on us */
1445 assert_pipe_disabled(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val &= ~DPLL_VCO_ENABLE;
1450 I915_WRITE(reg, val);
1451 POSTING_READ(reg);
1452}
1453
a416edef
ED		 1454/* SBI access */
1455static void
1456intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1457{
1458 unsigned long flags;
1459
1460 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1461 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1462 100)) {
1463 DRM_ERROR("timeout waiting for SBI to become ready\n");
1464 goto out_unlock;
1465 }
1466
1467 I915_WRITE(SBI_ADDR,
1468 (reg << 16));
1469 I915_WRITE(SBI_DATA,
1470 value);
1471 I915_WRITE(SBI_CTL_STAT,
1472 SBI_BUSY |
1473 SBI_CTL_OP_CRWR);
1474
39fb50f6 1475 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1476 100)) {
1477 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1478 goto out_unlock;
1479 }
1480
1481out_unlock:
1482 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1483}
1484
1485static u32
1486intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1487{
1488 unsigned long flags;
39fb50f6 1489 u32 value = 0;
a416edef
ED		 1490
1491 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1492 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1493 100)) {
1494 DRM_ERROR("timeout waiting for SBI to become ready\n");
1495 goto out_unlock;
1496 }
1497
1498 I915_WRITE(SBI_ADDR,
1499 (reg << 16));
1500 I915_WRITE(SBI_CTL_STAT,
1501 SBI_BUSY |
1502 SBI_CTL_OP_CRRD);
1503
39fb50f6 1504 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1505 100)) {
1506 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1507 goto out_unlock;
1508 }
1509
1510 value = I915_READ(SBI_DATA);
1511
1512out_unlock:
1513 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1514 return value;
1515}
1516
92f2584a 1517/**
b6b4e185 1518 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1519 * @dev_priv: i915 private structure
1520 * @pipe: pipe PLL to enable
1521 *
1522 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1523 * drives the transcoder clock.
1524 */
b6b4e185 1525static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1526{
ee7b9f93 1527 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1528 struct intel_pch_pll *pll;
92f2584a
JB		 1529 int reg;
1530 u32 val;
1531
48da64a8 1532 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1533 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1534 pll = intel_crtc->pch_pll;
1535 if (pll == NULL)
1536 return;
1537
1538 if (WARN_ON(pll->refcount == 0))
1539 return;
ee7b9f93
JB		 1540
1541 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1542 pll->pll_reg, pll->active, pll->on,
1543 intel_crtc->base.base.id);
92f2584a
JB		 1544
1545 /* PCH refclock must be enabled first */
1546 assert_pch_refclk_enabled(dev_priv);
1547
ee7b9f93 1548 if (pll->active++ && pll->on) {
92b27b08 1549 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1550 return;
1551 }
1552
1553 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1554
1555 reg = pll->pll_reg;
92f2584a
JB		 1556 val = I915_READ(reg);
1557 val |= DPLL_VCO_ENABLE;
1558 I915_WRITE(reg, val);
1559 POSTING_READ(reg);
1560 udelay(200);
ee7b9f93
JB		 1561
1562 pll->on = true;
92f2584a
JB		 1563}
1564
ee7b9f93 1565static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1566{
ee7b9f93
JB		 1567 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1568 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1569 int reg;
ee7b9f93 1570 u32 val;
4c609cb8 1571
92f2584a
JB		 1572 /* PCH only available on ILK+ */
1573 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1574 if (pll == NULL)
1575 return;
92f2584a 1576
48da64a8
CW		 1577 if (WARN_ON(pll->refcount == 0))
1578 return;
7a419866 1579
ee7b9f93
JB		 1580 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1581 pll->pll_reg, pll->active, pll->on,
1582 intel_crtc->base.base.id);
7a419866 1583
48da64a8 1584 if (WARN_ON(pll->active == 0)) {
92b27b08 1585 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1586 return;
1587 }
1588
ee7b9f93 1589 if (--pll->active) {
92b27b08 1590 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1591 return;
ee7b9f93
JB		 1592 }
1593
1594 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1595
1596 /* Make sure transcoder isn't still depending on us */
1597 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1598
ee7b9f93 1599 reg = pll->pll_reg;
92f2584a
JB		 1600 val = I915_READ(reg);
1601 val &= ~DPLL_VCO_ENABLE;
1602 I915_WRITE(reg, val);
1603 POSTING_READ(reg);
1604 udelay(200);
ee7b9f93
JB		 1605
1606 pll->on = false;
92f2584a
JB		 1607}
1608
b8a4f404
PZ		 1609static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1610 enum pipe pipe)
040484af 1611{
23670b32 1612 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1613 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1614 uint32_t reg, val, pipeconf_val;
040484af
JB		 1615
1616 /* PCH only available on ILK+ */
1617 BUG_ON(dev_priv->info->gen < 5);
1618
1619 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1620 assert_pch_pll_enabled(dev_priv,
1621 to_intel_crtc(crtc)->pch_pll,
1622 to_intel_crtc(crtc));
040484af
JB		 1623
1624 /* FDI must be feeding us bits for PCH ports */
1625 assert_fdi_tx_enabled(dev_priv, pipe);
1626 assert_fdi_rx_enabled(dev_priv, pipe);
1627
23670b32
DV		 1628 if (HAS_PCH_CPT(dev)) {
1629 /* Workaround: Set the timing override bit before enabling the
1630 * pch transcoder. */
1631 reg = TRANS_CHICKEN2(pipe);
1632 val = I915_READ(reg);
1633 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1634 I915_WRITE(reg, val);
59c859d6 1635 }
23670b32 1636
040484af
JB		 1637 reg = TRANSCONF(pipe);
1638 val = I915_READ(reg);
5f7f726d 1639 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1640
1641 if (HAS_PCH_IBX(dev_priv->dev)) {
1642 /*
1643 * make the BPC in transcoder be consistent with
1644 * that in pipeconf reg.
1645 */
1646 val &= ~PIPE_BPC_MASK;
5f7f726d 1647 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1648 }
5f7f726d
PZ		 1649
1650 val &= ~TRANS_INTERLACE_MASK;
1651 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1652 if (HAS_PCH_IBX(dev_priv->dev) &&
1653 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1654 val |= TRANS_LEGACY_INTERLACED_ILK;
1655 else
1656 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1657 else
1658 val |= TRANS_PROGRESSIVE;
1659
040484af
JB		 1660 I915_WRITE(reg, val | TRANS_ENABLE);
1661 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1662 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1663}
1664
8fb033d7 1665static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1666 enum transcoder cpu_transcoder)
040484af 1667{
8fb033d7 1668 u32 val, pipeconf_val;
8fb033d7
PZ		 1669
1670 /* PCH only available on ILK+ */
1671 BUG_ON(dev_priv->info->gen < 5);
1672
8fb033d7 1673 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1674 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1675 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1676
223a6fdf
PZ		 1677 /* Workaround: set timing override bit. */
1678 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1679 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1680 I915_WRITE(_TRANSA_CHICKEN2, val);
1681
25f3ef11 1682 val = TRANS_ENABLE;
937bb610 1683 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1684
9a76b1c6
PZ		 1685 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1686 PIPECONF_INTERLACED_ILK)
a35f2679 1687 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1688 else
1689 val |= TRANS_PROGRESSIVE;
1690
25f3ef11 1691 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1692 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1693 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1694}
1695
b8a4f404
PZ		 1696static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1697 enum pipe pipe)
040484af 1698{
23670b32
DV		 1699 struct drm_device *dev = dev_priv->dev;
1700 uint32_t reg, val;
040484af
JB		 1701
1702 /* FDI relies on the transcoder */
1703 assert_fdi_tx_disabled(dev_priv, pipe);
1704 assert_fdi_rx_disabled(dev_priv, pipe);
1705
291906f1
JB		 1706 /* Ports must be off as well */
1707 assert_pch_ports_disabled(dev_priv, pipe);
1708
040484af
JB		 1709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
1711 val &= ~TRANS_ENABLE;
1712 I915_WRITE(reg, val);
1713 /* wait for PCH transcoder off, transcoder state */
1714 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1715 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1716
1717 if (!HAS_PCH_IBX(dev)) {
1718 /* Workaround: Clear the timing override chicken bit again. */
1719 reg = TRANS_CHICKEN2(pipe);
1720 val = I915_READ(reg);
1721 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1722 I915_WRITE(reg, val);
1723 }
040484af
JB		 1724}
1725
ab4d966c 1726static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1727{
8fb033d7
PZ		 1728 u32 val;
1729
8a52fd9f 1730 val = I915_READ(_TRANSACONF);
8fb033d7 1731 val &= ~TRANS_ENABLE;
8a52fd9f 1732 I915_WRITE(_TRANSACONF, val);
8fb033d7 1733 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1734 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1735 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1736
1737 /* Workaround: clear timing override bit. */
1738 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1739 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1740 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1741}
1742
b24e7179 1743/**
309cfea8 1744 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1745 * @dev_priv: i915 private structure
1746 * @pipe: pipe to enable
040484af 1747 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1748 *
1749 * Enable @pipe, making sure that various hardware specific requirements
1750 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1751 *
1752 * @pipe should be %PIPE_A or %PIPE_B.
1753 *
1754 * Will wait until the pipe is actually running (i.e. first vblank) before
1755 * returning.
1756 */
040484af
JB		 1757static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1758 bool pch_port)
b24e7179 1759{
702e7a56
PZ		 1760 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1761 pipe);
1a240d4d 1762 enum pipe pch_transcoder;
b24e7179
JB		 1763 int reg;
1764 u32 val;
1765
cc391bbb
PZ		 1766 if (IS_HASWELL(dev_priv->dev))
1767 pch_transcoder = TRANSCODER_A;
1768 else
1769 pch_transcoder = pipe;
1770
b24e7179
JB		 1771 /*
1772 * A pipe without a PLL won't actually be able to drive bits from
1773 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1774 * need the check.
1775 */
1776 if (!HAS_PCH_SPLIT(dev_priv->dev))
1777 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1778 else {
1779 if (pch_port) {
1780 /* if driving the PCH, we need FDI enabled */
cc391bbb 1781 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1782 assert_fdi_tx_pll_enabled(dev_priv,
1783 (enum pipe) cpu_transcoder);
040484af
JB		 1784 }
1785 /* FIXME: assert CPU port conditions for SNB+ */
1786 }
b24e7179 1787
702e7a56 1788 reg = PIPECONF(cpu_transcoder);
b24e7179 1789 val = I915_READ(reg);
00d70b15
CW		 1790 if (val & PIPECONF_ENABLE)
1791 return;
1792
1793 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1794 intel_wait_for_vblank(dev_priv->dev, pipe);
1795}
1796
1797/**
309cfea8 1798 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1799 * @dev_priv: i915 private structure
1800 * @pipe: pipe to disable
1801 *
1802 * Disable @pipe, making sure that various hardware specific requirements
1803 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1804 *
1805 * @pipe should be %PIPE_A or %PIPE_B.
1806 *
1807 * Will wait until the pipe has shut down before returning.
1808 */
1809static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1810 enum pipe pipe)
1811{
702e7a56
PZ		 1812 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1813 pipe);
b24e7179
JB		 1814 int reg;
1815 u32 val;
1816
1817 /*
1818 * Make sure planes won't keep trying to pump pixels to us,
1819 * or we might hang the display.
1820 */
1821 assert_planes_disabled(dev_priv, pipe);
1822
1823 /* Don't disable pipe A or pipe A PLLs if needed */
1824 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1825 return;
1826
702e7a56 1827 reg = PIPECONF(cpu_transcoder);
b24e7179 1828 val = I915_READ(reg);
00d70b15
CW		 1829 if ((val & PIPECONF_ENABLE) == 0)
1830 return;
1831
1832 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1833 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1834}
1835
d74362c9
KP		 1836/*
1837 * Plane regs are double buffered, going from enabled->disabled needs a
1838 * trigger in order to latch. The display address reg provides this.
1839 */
6f1d69b0 1840void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1841 enum plane plane)
1842{
14f86147
DL		 1843 if (dev_priv->info->gen >= 4)
1844 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1845 else
1846 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1847}
1848
b24e7179
JB		 1849/**
1850 * intel_enable_plane - enable a display plane on a given pipe
1851 * @dev_priv: i915 private structure
1852 * @plane: plane to enable
1853 * @pipe: pipe being fed
1854 *
1855 * Enable @plane on @pipe, making sure that @pipe is running first.
1856 */
1857static void intel_enable_plane(struct drm_i915_private *dev_priv,
1858 enum plane plane, enum pipe pipe)
1859{
1860 int reg;
1861 u32 val;
1862
1863 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1864 assert_pipe_enabled(dev_priv, pipe);
1865
1866 reg = DSPCNTR(plane);
1867 val = I915_READ(reg);
00d70b15
CW		 1868 if (val & DISPLAY_PLANE_ENABLE)
1869 return;
1870
1871 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1872 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1873 intel_wait_for_vblank(dev_priv->dev, pipe);
1874}
1875
b24e7179
JB		 1876/**
1877 * intel_disable_plane - disable a display plane
1878 * @dev_priv: i915 private structure
1879 * @plane: plane to disable
1880 * @pipe: pipe consuming the data
1881 *
1882 * Disable @plane; should be an independent operation.
1883 */
1884static void intel_disable_plane(struct drm_i915_private *dev_priv,
1885 enum plane plane, enum pipe pipe)
1886{
1887 int reg;
1888 u32 val;
1889
1890 reg = DSPCNTR(plane);
1891 val = I915_READ(reg);
00d70b15
CW		 1892 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1893 return;
1894
1895 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1896 intel_flush_display_plane(dev_priv, plane);
1897 intel_wait_for_vblank(dev_priv->dev, pipe);
1898}
1899
127bd2ac 1900int
48b956c5 1901intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1902 struct drm_i915_gem_object *obj,
919926ae 1903 struct intel_ring_buffer *pipelined)
6b95a207 1904{
ce453d81 1905 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1906 u32 alignment;
1907 int ret;
1908
05394f39 1909 switch (obj->tiling_mode) {
6b95a207 1910 case I915_TILING_NONE:
534843da
CW		 1911 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1912 alignment = 128 * 1024;
a6c45cf0 1913 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1914 alignment = 4 * 1024;
1915 else
1916 alignment = 64 * 1024;
6b95a207
KH		 1917 break;
1918 case I915_TILING_X:
1919 /* pin() will align the object as required by fence */
1920 alignment = 0;
1921 break;
1922 case I915_TILING_Y:
1923 /* FIXME: Is this true? */
1924 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1925 return -EINVAL;
1926 default:
1927 BUG();
1928 }
1929
ce453d81 1930 dev_priv->mm.interruptible = false;
2da3b9b9 1931 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1932 if (ret)
ce453d81 1933 goto err_interruptible;
6b95a207
KH		 1934
1935 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1936 * fence, whereas 965+ only requires a fence if using
1937 * framebuffer compression. For simplicity, we always install
1938 * a fence as the cost is not that onerous.
1939 */
06d98131 1940 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1941 if (ret)
1942 goto err_unpin;
1690e1eb 1943
9a5a53b3 1944 i915_gem_object_pin_fence(obj);
6b95a207 1945
ce453d81 1946 dev_priv->mm.interruptible = true;
6b95a207 1947 return 0;
48b956c5
CW		 1948
1949err_unpin:
1950 i915_gem_object_unpin(obj);
ce453d81
CW		 1951err_interruptible:
1952 dev_priv->mm.interruptible = true;
48b956c5 1953 return ret;
6b95a207
KH		 1954}
1955
1690e1eb
CW		 1956void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1957{
1958 i915_gem_object_unpin_fence(obj);
1959 i915_gem_object_unpin(obj);
1960}
1961
c2c75131
DV		 1962/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1963 * is assumed to be a power-of-two. */
5a35e99e
DL		 1964unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1965 unsigned int bpp,
1966 unsigned int pitch)
c2c75131
DV		 1967{
1968 int tile_rows, tiles;
1969
1970 tile_rows = *y / 8;
1971 *y %= 8;
1972 tiles = *x / (512/bpp);
1973 *x %= 512/bpp;
1974
1975 return tile_rows * pitch * 8 + tiles * 4096;
1976}
1977
17638cd6
JB		 1978static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1979 int x, int y)
81255565
JB		 1980{
1981 struct drm_device *dev = crtc->dev;
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984 struct intel_framebuffer *intel_fb;
05394f39 1985 struct drm_i915_gem_object *obj;
81255565 1986 int plane = intel_crtc->plane;
e506a0c6 1987 unsigned long linear_offset;
81255565 1988 u32 dspcntr;
5eddb70b 1989 u32 reg;
81255565
JB		 1990
1991 switch (plane) {
1992 case 0:
1993 case 1:
1994 break;
1995 default:
1996 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1997 return -EINVAL;
1998 }
1999
2000 intel_fb = to_intel_framebuffer(fb);
2001 obj = intel_fb->obj;
81255565 2002
5eddb70b
CW		 2003 reg = DSPCNTR(plane);
2004 dspcntr = I915_READ(reg);
81255565
JB		 2005 /* Mask out pixel format bits in case we change it */
2006 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2007 switch (fb->pixel_format) {
2008 case DRM_FORMAT_C8:
81255565
JB		 2009 dspcntr |= DISPPLANE_8BPP;
2010 break;
57779d06
VS		 2011 case DRM_FORMAT_XRGB1555:
2012 case DRM_FORMAT_ARGB1555:
2013 dspcntr |= DISPPLANE_BGRX555;
81255565 2014 break;
57779d06
VS		 2015 case DRM_FORMAT_RGB565:
2016 dspcntr |= DISPPLANE_BGRX565;
2017 break;
2018 case DRM_FORMAT_XRGB8888:
2019 case DRM_FORMAT_ARGB8888:
2020 dspcntr |= DISPPLANE_BGRX888;
2021 break;
2022 case DRM_FORMAT_XBGR8888:
2023 case DRM_FORMAT_ABGR8888:
2024 dspcntr |= DISPPLANE_RGBX888;
2025 break;
2026 case DRM_FORMAT_XRGB2101010:
2027 case DRM_FORMAT_ARGB2101010:
2028 dspcntr |= DISPPLANE_BGRX101010;
2029 break;
2030 case DRM_FORMAT_XBGR2101010:
2031 case DRM_FORMAT_ABGR2101010:
2032 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2033 break;
2034 default:
57779d06 2035 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2036 return -EINVAL;
2037 }
57779d06 2038
a6c45cf0 2039 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2040 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2041 dspcntr |= DISPPLANE_TILED;
2042 else
2043 dspcntr &= ~DISPPLANE_TILED;
2044 }
2045
5eddb70b 2046 I915_WRITE(reg, dspcntr);
81255565 2047
e506a0c6 2048 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2049
c2c75131
DV		 2050 if (INTEL_INFO(dev)->gen >= 4) {
2051 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2052 intel_gen4_compute_offset_xtiled(&x, &y,
2053 fb->bits_per_pixel / 8,
2054 fb->pitches[0]);
c2c75131
DV		 2055 linear_offset -= intel_crtc->dspaddr_offset;
2056 } else {
e506a0c6 2057 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2058 }
e506a0c6
DV		 2059
2060 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2061 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2062 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2063 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2064 I915_MODIFY_DISPBASE(DSPSURF(plane),
2065 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2066 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2067 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2068 } else
e506a0c6 2069 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2070 POSTING_READ(reg);
81255565 2071
17638cd6
JB		 2072 return 0;
2073}
2074
2075static int ironlake_update_plane(struct drm_crtc *crtc,
2076 struct drm_framebuffer *fb, int x, int y)
2077{
2078 struct drm_device *dev = crtc->dev;
2079 struct drm_i915_private *dev_priv = dev->dev_private;
2080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2081 struct intel_framebuffer *intel_fb;
2082 struct drm_i915_gem_object *obj;
2083 int plane = intel_crtc->plane;
e506a0c6 2084 unsigned long linear_offset;
17638cd6
JB		 2085 u32 dspcntr;
2086 u32 reg;
2087
2088 switch (plane) {
2089 case 0:
2090 case 1:
27f8227b 2091 case 2:
17638cd6
JB		 2092 break;
2093 default:
2094 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2095 return -EINVAL;
2096 }
2097
2098 intel_fb = to_intel_framebuffer(fb);
2099 obj = intel_fb->obj;
2100
2101 reg = DSPCNTR(plane);
2102 dspcntr = I915_READ(reg);
2103 /* Mask out pixel format bits in case we change it */
2104 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2105 switch (fb->pixel_format) {
2106 case DRM_FORMAT_C8:
17638cd6
JB		 2107 dspcntr |= DISPPLANE_8BPP;
2108 break;
57779d06
VS		 2109 case DRM_FORMAT_RGB565:
2110 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2111 break;
57779d06
VS		 2112 case DRM_FORMAT_XRGB8888:
2113 case DRM_FORMAT_ARGB8888:
2114 dspcntr |= DISPPLANE_BGRX888;
2115 break;
2116 case DRM_FORMAT_XBGR8888:
2117 case DRM_FORMAT_ABGR8888:
2118 dspcntr |= DISPPLANE_RGBX888;
2119 break;
2120 case DRM_FORMAT_XRGB2101010:
2121 case DRM_FORMAT_ARGB2101010:
2122 dspcntr |= DISPPLANE_BGRX101010;
2123 break;
2124 case DRM_FORMAT_XBGR2101010:
2125 case DRM_FORMAT_ABGR2101010:
2126 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2127 break;
2128 default:
57779d06 2129 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2130 return -EINVAL;
2131 }
2132
2133 if (obj->tiling_mode != I915_TILING_NONE)
2134 dspcntr |= DISPPLANE_TILED;
2135 else
2136 dspcntr &= ~DISPPLANE_TILED;
2137
2138 /* must disable */
2139 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2140
2141 I915_WRITE(reg, dspcntr);
2142
e506a0c6 2143 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2144 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2145 intel_gen4_compute_offset_xtiled(&x, &y,
2146 fb->bits_per_pixel / 8,
2147 fb->pitches[0]);
c2c75131 2148 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2149
e506a0c6
DV		 2150 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2151 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2152 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2153 I915_MODIFY_DISPBASE(DSPSURF(plane),
2154 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2155 if (IS_HASWELL(dev)) {
2156 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2157 } else {
2158 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2159 I915_WRITE(DSPLINOFF(plane), linear_offset);
2160 }
17638cd6
JB		 2161 POSTING_READ(reg);
2162
2163 return 0;
2164}
2165
2166/* Assume fb object is pinned & idle & fenced and just update base pointers */
2167static int
2168intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2169 int x, int y, enum mode_set_atomic state)
2170{
2171 struct drm_device *dev = crtc->dev;
2172 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2173
6b8e6ed0
CW		 2174 if (dev_priv->display.disable_fbc)
2175 dev_priv->display.disable_fbc(dev);
3dec0095 2176 intel_increase_pllclock(crtc);
81255565 2177
6b8e6ed0 2178 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2179}
2180
14667a4b
CW		 2181static int
2182intel_finish_fb(struct drm_framebuffer *old_fb)
2183{
2184 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2185 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2186 bool was_interruptible = dev_priv->mm.interruptible;
2187 int ret;
2188
2189 wait_event(dev_priv->pending_flip_queue,
2190 atomic_read(&dev_priv->mm.wedged) ||
2191 atomic_read(&obj->pending_flip) == 0);
2192
2193 /* Big Hammer, we also need to ensure that any pending
2194 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2195 * current scanout is retired before unpinning the old
2196 * framebuffer.
2197 *
2198 * This should only fail upon a hung GPU, in which case we
2199 * can safely continue.
2200 */
2201 dev_priv->mm.interruptible = false;
2202 ret = i915_gem_object_finish_gpu(obj);
2203 dev_priv->mm.interruptible = was_interruptible;
2204
2205 return ret;
2206}
2207
198598d0
VS		 2208static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2209{
2210 struct drm_device *dev = crtc->dev;
2211 struct drm_i915_master_private *master_priv;
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 if (!dev->primary->master)
2215 return;
2216
2217 master_priv = dev->primary->master->driver_priv;
2218 if (!master_priv->sarea_priv)
2219 return;
2220
2221 switch (intel_crtc->pipe) {
2222 case 0:
2223 master_priv->sarea_priv->pipeA_x = x;
2224 master_priv->sarea_priv->pipeA_y = y;
2225 break;
2226 case 1:
2227 master_priv->sarea_priv->pipeB_x = x;
2228 master_priv->sarea_priv->pipeB_y = y;
2229 break;
2230 default:
2231 break;
2232 }
2233}
2234
5c3b82e2 2235static int
3c4fdcfb 2236intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2237 struct drm_framebuffer *fb)
79e53945
JB		 2238{
2239 struct drm_device *dev = crtc->dev;
6b8e6ed0 2240 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2242 struct drm_framebuffer *old_fb;
5c3b82e2 2243 int ret;
79e53945
JB		 2244
2245 /* no fb bound */
94352cf9 2246 if (!fb) {
a5071c2f 2247 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2248 return 0;
2249 }
2250
5826eca5
ED		 2251 if(intel_crtc->plane > dev_priv->num_pipe) {
2252 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2253 intel_crtc->plane,
2254 dev_priv->num_pipe);
5c3b82e2 2255 return -EINVAL;
79e53945
JB		 2256 }
2257
5c3b82e2 2258 mutex_lock(&dev->struct_mutex);
265db958 2259 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2260 to_intel_framebuffer(fb)->obj,
919926ae 2261 NULL);
5c3b82e2
CW		 2262 if (ret != 0) {
2263 mutex_unlock(&dev->struct_mutex);
a5071c2f 2264 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2265 return ret;
2266 }
79e53945 2267
94352cf9
DV		 2268 if (crtc->fb)
2269 intel_finish_fb(crtc->fb);
265db958 2270
94352cf9 2271 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2272 if (ret) {
94352cf9 2273 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2274 mutex_unlock(&dev->struct_mutex);
a5071c2f 2275 DRM_ERROR("failed to update base address\n");
4e6cfefc 2276 return ret;
79e53945 2277 }
3c4fdcfb 2278
94352cf9
DV		 2279 old_fb = crtc->fb;
2280 crtc->fb = fb;
6c4c86f5
DV		 2281 crtc->x = x;
2282 crtc->y = y;
94352cf9 2283
b7f1de28
CW		 2284 if (old_fb) {
2285 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2286 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2287 }
652c393a 2288
6b8e6ed0 2289 intel_update_fbc(dev);
5c3b82e2 2290 mutex_unlock(&dev->struct_mutex);
79e53945 2291
198598d0 2292 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2293
2294 return 0;
79e53945
JB		 2295}
2296
5e84e1a4
ZW		 2297static void intel_fdi_normal_train(struct drm_crtc *crtc)
2298{
2299 struct drm_device *dev = crtc->dev;
2300 struct drm_i915_private *dev_priv = dev->dev_private;
2301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2302 int pipe = intel_crtc->pipe;
2303 u32 reg, temp;
2304
2305 /* enable normal train */
2306 reg = FDI_TX_CTL(pipe);
2307 temp = I915_READ(reg);
61e499bf 2308 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2309 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2310 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2311 } else {
2312 temp &= ~FDI_LINK_TRAIN_NONE;
2313 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2314 }
5e84e1a4
ZW		 2315 I915_WRITE(reg, temp);
2316
2317 reg = FDI_RX_CTL(pipe);
2318 temp = I915_READ(reg);
2319 if (HAS_PCH_CPT(dev)) {
2320 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2321 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2322 } else {
2323 temp &= ~FDI_LINK_TRAIN_NONE;
2324 temp |= FDI_LINK_TRAIN_NONE;
2325 }
2326 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2327
2328 /* wait one idle pattern time */
2329 POSTING_READ(reg);
2330 udelay(1000);
357555c0
JB		 2331
2332 /* IVB wants error correction enabled */
2333 if (IS_IVYBRIDGE(dev))
2334 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2335 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2336}
2337
291427f5
JB		 2338static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2339{
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 u32 flags = I915_READ(SOUTH_CHICKEN1);
2342
2343 flags |= FDI_PHASE_SYNC_OVR(pipe);
2344 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2345 flags |= FDI_PHASE_SYNC_EN(pipe);
2346 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2347 POSTING_READ(SOUTH_CHICKEN1);
2348}
2349
01a415fd
DV		 2350static void ivb_modeset_global_resources(struct drm_device *dev)
2351{
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 struct intel_crtc *pipe_B_crtc =
2354 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2355 struct intel_crtc *pipe_C_crtc =
2356 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2357 uint32_t temp;
2358
2359 /* When everything is off disable fdi C so that we could enable fdi B
2360 * with all lanes. XXX: This misses the case where a pipe is not using
2361 * any pch resources and so doesn't need any fdi lanes. */
2362 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2363 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2364 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2365
2366 temp = I915_READ(SOUTH_CHICKEN1);
2367 temp &= ~FDI_BC_BIFURCATION_SELECT;
2368 DRM_DEBUG_KMS("disabling fdi C rx\n");
2369 I915_WRITE(SOUTH_CHICKEN1, temp);
2370 }
2371}
2372
8db9d77b
ZW		 2373/* The FDI link training functions for ILK/Ibexpeak. */
2374static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2375{
2376 struct drm_device *dev = crtc->dev;
2377 struct drm_i915_private *dev_priv = dev->dev_private;
2378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2379 int pipe = intel_crtc->pipe;
0fc932b8 2380 int plane = intel_crtc->plane;
5eddb70b 2381 u32 reg, temp, tries;
8db9d77b 2382
0fc932b8
JB		 2383 /* FDI needs bits from pipe & plane first */
2384 assert_pipe_enabled(dev_priv, pipe);
2385 assert_plane_enabled(dev_priv, plane);
2386
e1a44743
AJ		 2387 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2388 for train result */
5eddb70b
CW		 2389 reg = FDI_RX_IMR(pipe);
2390 temp = I915_READ(reg);
e1a44743
AJ		 2391 temp &= ~FDI_RX_SYMBOL_LOCK;
2392 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2393 I915_WRITE(reg, temp);
2394 I915_READ(reg);
e1a44743
AJ		 2395 udelay(150);
2396
8db9d77b 2397 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2398 reg = FDI_TX_CTL(pipe);
2399 temp = I915_READ(reg);
77ffb597
AJ		 2400 temp &= ~(7 << 19);
2401 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2402 temp &= ~FDI_LINK_TRAIN_NONE;
2403 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2404 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2405
5eddb70b
CW		 2406 reg = FDI_RX_CTL(pipe);
2407 temp = I915_READ(reg);
8db9d77b
ZW		 2408 temp &= ~FDI_LINK_TRAIN_NONE;
2409 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2410 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2411
2412 POSTING_READ(reg);
8db9d77b
ZW		 2413 udelay(150);
2414
5b2adf89 2415 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2416 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2417 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2418 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2419
5eddb70b 2420 reg = FDI_RX_IIR(pipe);
e1a44743 2421 for (tries = 0; tries < 5; tries++) {
5eddb70b 2422 temp = I915_READ(reg);
8db9d77b
ZW		 2423 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2424
2425 if ((temp & FDI_RX_BIT_LOCK)) {
2426 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2427 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2428 break;
2429 }
8db9d77b 2430 }
e1a44743 2431 if (tries == 5)
5eddb70b 2432 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2433
2434 /* Train 2 */
5eddb70b
CW		 2435 reg = FDI_TX_CTL(pipe);
2436 temp = I915_READ(reg);
8db9d77b
ZW		 2437 temp &= ~FDI_LINK_TRAIN_NONE;
2438 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2439 I915_WRITE(reg, temp);
8db9d77b 2440
5eddb70b
CW		 2441 reg = FDI_RX_CTL(pipe);
2442 temp = I915_READ(reg);
8db9d77b
ZW		 2443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2445 I915_WRITE(reg, temp);
8db9d77b 2446
5eddb70b
CW		 2447 POSTING_READ(reg);
2448 udelay(150);
8db9d77b 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2456 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2457 DRM_DEBUG_KMS("FDI train 2 done.\n");
2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2463
2464 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2465
8db9d77b
ZW		 2466}
2467
0206e353 2468static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2469 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2470 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2471 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2472 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2473};
2474
2475/* The FDI link training functions for SNB/Cougarpoint. */
2476static void gen6_fdi_link_train(struct drm_crtc *crtc)
2477{
2478 struct drm_device *dev = crtc->dev;
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481 int pipe = intel_crtc->pipe;
fa37d39e 2482 u32 reg, temp, i, retry;
8db9d77b 2483
e1a44743
AJ		 2484 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2485 for train result */
5eddb70b
CW		 2486 reg = FDI_RX_IMR(pipe);
2487 temp = I915_READ(reg);
e1a44743
AJ		 2488 temp &= ~FDI_RX_SYMBOL_LOCK;
2489 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2490 I915_WRITE(reg, temp);
2491
2492 POSTING_READ(reg);
e1a44743
AJ		 2493 udelay(150);
2494
8db9d77b 2495 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
77ffb597
AJ		 2498 temp &= ~(7 << 19);
2499 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 /* SNB-B */
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2505 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2506
d74cf324
DV		 2507 I915_WRITE(FDI_RX_MISC(pipe),
2508 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2509
5eddb70b
CW		 2510 reg = FDI_RX_CTL(pipe);
2511 temp = I915_READ(reg);
8db9d77b
ZW		 2512 if (HAS_PCH_CPT(dev)) {
2513 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2514 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2515 } else {
2516 temp &= ~FDI_LINK_TRAIN_NONE;
2517 temp |= FDI_LINK_TRAIN_PATTERN_1;
2518 }
5eddb70b
CW		 2519 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2520
2521 POSTING_READ(reg);
8db9d77b
ZW		 2522 udelay(150);
2523
8f5718a6 2524 cpt_phase_pointer_enable(dev, pipe);
291427f5 2525
0206e353 2526 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2527 reg = FDI_TX_CTL(pipe);
2528 temp = I915_READ(reg);
8db9d77b
ZW		 2529 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2530 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2531 I915_WRITE(reg, temp);
2532
2533 POSTING_READ(reg);
8db9d77b
ZW		 2534 udelay(500);
2535
fa37d39e
SP		 2536 for (retry = 0; retry < 5; retry++) {
2537 reg = FDI_RX_IIR(pipe);
2538 temp = I915_READ(reg);
2539 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2540 if (temp & FDI_RX_BIT_LOCK) {
2541 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2542 DRM_DEBUG_KMS("FDI train 1 done.\n");
2543 break;
2544 }
2545 udelay(50);
8db9d77b 2546 }
fa37d39e
SP		 2547 if (retry < 5)
2548 break;
8db9d77b
ZW		 2549 }
2550 if (i == 4)
5eddb70b 2551 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2552
2553 /* Train 2 */
5eddb70b
CW		 2554 reg = FDI_TX_CTL(pipe);
2555 temp = I915_READ(reg);
8db9d77b
ZW		 2556 temp &= ~FDI_LINK_TRAIN_NONE;
2557 temp |= FDI_LINK_TRAIN_PATTERN_2;
2558 if (IS_GEN6(dev)) {
2559 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2560 /* SNB-B */
2561 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2562 }
5eddb70b 2563 I915_WRITE(reg, temp);
8db9d77b 2564
5eddb70b
CW		 2565 reg = FDI_RX_CTL(pipe);
2566 temp = I915_READ(reg);
8db9d77b
ZW		 2567 if (HAS_PCH_CPT(dev)) {
2568 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2569 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2570 } else {
2571 temp &= ~FDI_LINK_TRAIN_NONE;
2572 temp |= FDI_LINK_TRAIN_PATTERN_2;
2573 }
5eddb70b
CW		 2574 I915_WRITE(reg, temp);
2575
2576 POSTING_READ(reg);
8db9d77b
ZW		 2577 udelay(150);
2578
0206e353 2579 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2580 reg = FDI_TX_CTL(pipe);
2581 temp = I915_READ(reg);
8db9d77b
ZW		 2582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2583 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2584 I915_WRITE(reg, temp);
2585
2586 POSTING_READ(reg);
8db9d77b
ZW		 2587 udelay(500);
2588
fa37d39e
SP		 2589 for (retry = 0; retry < 5; retry++) {
2590 reg = FDI_RX_IIR(pipe);
2591 temp = I915_READ(reg);
2592 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2593 if (temp & FDI_RX_SYMBOL_LOCK) {
2594 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2595 DRM_DEBUG_KMS("FDI train 2 done.\n");
2596 break;
2597 }
2598 udelay(50);
8db9d77b 2599 }
fa37d39e
SP		 2600 if (retry < 5)
2601 break;
8db9d77b
ZW		 2602 }
2603 if (i == 4)
5eddb70b 2604 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2605
2606 DRM_DEBUG_KMS("FDI train done.\n");
2607}
2608
357555c0
JB		 2609/* Manual link training for Ivy Bridge A0 parts */
2610static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2611{
2612 struct drm_device *dev = crtc->dev;
2613 struct drm_i915_private *dev_priv = dev->dev_private;
2614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2615 int pipe = intel_crtc->pipe;
2616 u32 reg, temp, i;
2617
2618 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2619 for train result */
2620 reg = FDI_RX_IMR(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~FDI_RX_SYMBOL_LOCK;
2623 temp &= ~FDI_RX_BIT_LOCK;
2624 I915_WRITE(reg, temp);
2625
2626 POSTING_READ(reg);
2627 udelay(150);
2628
01a415fd
DV		 2629 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2630 I915_READ(FDI_RX_IIR(pipe)));
2631
357555c0
JB		 2632 /* enable CPU FDI TX and PCH FDI RX */
2633 reg = FDI_TX_CTL(pipe);
2634 temp = I915_READ(reg);
2635 temp &= ~(7 << 19);
2636 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2637 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2638 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2639 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2641 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2642 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2643
d74cf324
DV		 2644 I915_WRITE(FDI_RX_MISC(pipe),
2645 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2646
357555c0
JB		 2647 reg = FDI_RX_CTL(pipe);
2648 temp = I915_READ(reg);
2649 temp &= ~FDI_LINK_TRAIN_AUTO;
2650 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2651 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2652 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2653 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2654
2655 POSTING_READ(reg);
2656 udelay(150);
2657
8f5718a6 2658 cpt_phase_pointer_enable(dev, pipe);
291427f5 2659
0206e353 2660 for (i = 0; i < 4; i++) {
357555c0
JB		 2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664 temp |= snb_b_fdi_train_param[i];
2665 I915_WRITE(reg, temp);
2666
2667 POSTING_READ(reg);
2668 udelay(500);
2669
2670 reg = FDI_RX_IIR(pipe);
2671 temp = I915_READ(reg);
2672 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2673
2674 if (temp & FDI_RX_BIT_LOCK ||
2675 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2676 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2677 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2678 break;
2679 }
2680 }
2681 if (i == 4)
2682 DRM_ERROR("FDI train 1 fail!\n");
2683
2684 /* Train 2 */
2685 reg = FDI_TX_CTL(pipe);
2686 temp = I915_READ(reg);
2687 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2688 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2691 I915_WRITE(reg, temp);
2692
2693 reg = FDI_RX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2696 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2697 I915_WRITE(reg, temp);
2698
2699 POSTING_READ(reg);
2700 udelay(150);
2701
0206e353 2702 for (i = 0; i < 4; i++) {
357555c0
JB		 2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2706 temp |= snb_b_fdi_train_param[i];
2707 I915_WRITE(reg, temp);
2708
2709 POSTING_READ(reg);
2710 udelay(500);
2711
2712 reg = FDI_RX_IIR(pipe);
2713 temp = I915_READ(reg);
2714 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2715
2716 if (temp & FDI_RX_SYMBOL_LOCK) {
2717 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2718 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2719 break;
2720 }
2721 }
2722 if (i == 4)
2723 DRM_ERROR("FDI train 2 fail!\n");
2724
2725 DRM_DEBUG_KMS("FDI train done.\n");
2726}
2727
88cefb6c 2728static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2729{
88cefb6c 2730 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2731 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2732 int pipe = intel_crtc->pipe;
5eddb70b 2733 u32 reg, temp;
79e53945 2734
c64e311e 2735
c98e9dcf 2736 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2737 reg = FDI_RX_CTL(pipe);
2738 temp = I915_READ(reg);
2739 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2740 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2741 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2742 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2743
2744 POSTING_READ(reg);
c98e9dcf
JB		 2745 udelay(200);
2746
2747 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2748 temp = I915_READ(reg);
2749 I915_WRITE(reg, temp | FDI_PCDCLK);
2750
2751 POSTING_READ(reg);
c98e9dcf
JB		 2752 udelay(200);
2753
20749730
PZ		 2754 /* Enable CPU FDI TX PLL, always on for Ironlake */
2755 reg = FDI_TX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2758 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2759
20749730
PZ		 2760 POSTING_READ(reg);
2761 udelay(100);
6be4a607 2762 }
0e23b99d
JB		 2763}
2764
88cefb6c
DV		 2765static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2766{
2767 struct drm_device *dev = intel_crtc->base.dev;
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 int pipe = intel_crtc->pipe;
2770 u32 reg, temp;
2771
2772 /* Switch from PCDclk to Rawclk */
2773 reg = FDI_RX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2776
2777 /* Disable CPU FDI TX PLL */
2778 reg = FDI_TX_CTL(pipe);
2779 temp = I915_READ(reg);
2780 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2781
2782 POSTING_READ(reg);
2783 udelay(100);
2784
2785 reg = FDI_RX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2788
2789 /* Wait for the clocks to turn off. */
2790 POSTING_READ(reg);
2791 udelay(100);
2792}
2793
291427f5
JB		 2794static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2795{
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 u32 flags = I915_READ(SOUTH_CHICKEN1);
2798
2799 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2800 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2801 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2802 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2803 POSTING_READ(SOUTH_CHICKEN1);
2804}
0fc932b8
JB		 2805static void ironlake_fdi_disable(struct drm_crtc *crtc)
2806{
2807 struct drm_device *dev = crtc->dev;
2808 struct drm_i915_private *dev_priv = dev->dev_private;
2809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2810 int pipe = intel_crtc->pipe;
2811 u32 reg, temp;
2812
2813 /* disable CPU FDI tx and PCH FDI rx */
2814 reg = FDI_TX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2817 POSTING_READ(reg);
2818
2819 reg = FDI_RX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 temp &= ~(0x7 << 16);
2822 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2823 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2824
2825 POSTING_READ(reg);
2826 udelay(100);
2827
2828 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2829 if (HAS_PCH_IBX(dev)) {
2830 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
291427f5
JB		 2831 } else if (HAS_PCH_CPT(dev)) {
2832 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2833 }
0fc932b8
JB		 2834
2835 /* still set train pattern 1 */
2836 reg = FDI_TX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 temp &= ~FDI_LINK_TRAIN_NONE;
2839 temp |= FDI_LINK_TRAIN_PATTERN_1;
2840 I915_WRITE(reg, temp);
2841
2842 reg = FDI_RX_CTL(pipe);
2843 temp = I915_READ(reg);
2844 if (HAS_PCH_CPT(dev)) {
2845 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2847 } else {
2848 temp &= ~FDI_LINK_TRAIN_NONE;
2849 temp |= FDI_LINK_TRAIN_PATTERN_1;
2850 }
2851 /* BPC in FDI rx is consistent with that in PIPECONF */
2852 temp &= ~(0x07 << 16);
2853 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2854 I915_WRITE(reg, temp);
2855
2856 POSTING_READ(reg);
2857 udelay(100);
2858}
2859
5bb61643
CW		 2860static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2861{
2862 struct drm_device *dev = crtc->dev;
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 unsigned long flags;
2865 bool pending;
2866
2867 if (atomic_read(&dev_priv->mm.wedged))
2868 return false;
2869
2870 spin_lock_irqsave(&dev->event_lock, flags);
2871 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2872 spin_unlock_irqrestore(&dev->event_lock, flags);
2873
2874 return pending;
2875}
2876
e6c3a2a6
CW		 2877static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2878{
0f91128d 2879 struct drm_device *dev = crtc->dev;
5bb61643 2880 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2881
2882 if (crtc->fb == NULL)
2883 return;
2884
5bb61643
CW		 2885 wait_event(dev_priv->pending_flip_queue,
2886 !intel_crtc_has_pending_flip(crtc));
2887
0f91128d
CW		 2888 mutex_lock(&dev->struct_mutex);
2889 intel_finish_fb(crtc->fb);
2890 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2891}
2892
fc316cbe 2893static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2894{
2895 struct drm_device *dev = crtc->dev;
228d3e36 2896 struct intel_encoder *intel_encoder;
040484af
JB		 2897
2898 /*
2899 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2900 * must be driven by its own crtc; no sharing is possible.
2901 */
228d3e36 2902 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2903 switch (intel_encoder->type) {
040484af 2904 case INTEL_OUTPUT_EDP:
228d3e36 2905 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2906 return false;
2907 continue;
2908 }
2909 }
2910
2911 return true;
2912}
2913
fc316cbe
PZ		 2914static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2915{
2916 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2917}
2918
e615efe4
ED		 2919/* Program iCLKIP clock to the desired frequency */
2920static void lpt_program_iclkip(struct drm_crtc *crtc)
2921{
2922 struct drm_device *dev = crtc->dev;
2923 struct drm_i915_private *dev_priv = dev->dev_private;
2924 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2925 u32 temp;
2926
2927 /* It is necessary to ungate the pixclk gate prior to programming
2928 * the divisors, and gate it back when it is done.
2929 */
2930 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2931
2932 /* Disable SSCCTL */
2933 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2934 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2935 SBI_SSCCTL_DISABLE);
2936
2937 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2938 if (crtc->mode.clock == 20000) {
2939 auxdiv = 1;
2940 divsel = 0x41;
2941 phaseinc = 0x20;
2942 } else {
2943 /* The iCLK virtual clock root frequency is in MHz,
2944 * but the crtc->mode.clock in in KHz. To get the divisors,
2945 * it is necessary to divide one by another, so we
2946 * convert the virtual clock precision to KHz here for higher
2947 * precision.
2948 */
2949 u32 iclk_virtual_root_freq = 172800 * 1000;
2950 u32 iclk_pi_range = 64;
2951 u32 desired_divisor, msb_divisor_value, pi_value;
2952
2953 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2954 msb_divisor_value = desired_divisor / iclk_pi_range;
2955 pi_value = desired_divisor % iclk_pi_range;
2956
2957 auxdiv = 0;
2958 divsel = msb_divisor_value - 2;
2959 phaseinc = pi_value;
2960 }
2961
2962 /* This should not happen with any sane values */
2963 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2964 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2965 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2966 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2967
2968 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2969 crtc->mode.clock,
2970 auxdiv,
2971 divsel,
2972 phasedir,
2973 phaseinc);
2974
2975 /* Program SSCDIVINTPHASE6 */
2976 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2977 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2978 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2979 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2980 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2981 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2982 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2983
2984 intel_sbi_write(dev_priv,
2985 SBI_SSCDIVINTPHASE6,
2986 temp);
2987
2988 /* Program SSCAUXDIV */
2989 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2990 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2991 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2992 intel_sbi_write(dev_priv,
2993 SBI_SSCAUXDIV6,
2994 temp);
2995
2996
2997 /* Enable modulator and associated divider */
2998 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2999 temp &= ~SBI_SSCCTL_DISABLE;
3000 intel_sbi_write(dev_priv,
3001 SBI_SSCCTL6,
3002 temp);
3003
3004 /* Wait for initialization time */
3005 udelay(24);
3006
3007 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3008}
3009
f67a559d
JB		 3010/*
3011 * Enable PCH resources required for PCH ports:
3012 * - PCH PLLs
3013 * - FDI training & RX/TX
3014 * - update transcoder timings
3015 * - DP transcoding bits
3016 * - transcoder
3017 */
3018static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3019{
3020 struct drm_device *dev = crtc->dev;
3021 struct drm_i915_private *dev_priv = dev->dev_private;
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3023 int pipe = intel_crtc->pipe;
ee7b9f93 3024 u32 reg, temp;
2c07245f 3025
e7e164db
CW		 3026 assert_transcoder_disabled(dev_priv, pipe);
3027
cd986abb
DV		 3028 /* Write the TU size bits before fdi link training, so that error
3029 * detection works. */
3030 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3031 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3032
c98e9dcf 3033 /* For PCH output, training FDI link */
674cf967 3034 dev_priv->display.fdi_link_train(crtc);
2c07245f 3035
572deb37
DV		 3036 /* XXX: pch pll's can be enabled any time before we enable the PCH
3037 * transcoder, and we actually should do this to not upset any PCH
3038 * transcoder that already use the clock when we share it.
3039 *
3040 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3041 * unconditionally resets the pll - we need that to have the right LVDS
3042 * enable sequence. */
b6b4e185 3043 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3044
303b81e0 3045 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3046 u32 sel;
4b645f14 3047
c98e9dcf 3048 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3049 switch (pipe) {
3050 default:
3051 case 0:
3052 temp |= TRANSA_DPLL_ENABLE;
3053 sel = TRANSA_DPLLB_SEL;
3054 break;
3055 case 1:
3056 temp |= TRANSB_DPLL_ENABLE;
3057 sel = TRANSB_DPLLB_SEL;
3058 break;
3059 case 2:
3060 temp |= TRANSC_DPLL_ENABLE;
3061 sel = TRANSC_DPLLB_SEL;
3062 break;
d64311ab 3063 }
ee7b9f93
JB		 3064 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3065 temp |= sel;
3066 else
3067 temp &= ~sel;
c98e9dcf 3068 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3069 }
5eddb70b 3070
d9b6cb56
JB		 3071 /* set transcoder timing, panel must allow it */
3072 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3073 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3074 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3075 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3076
5eddb70b
CW		 3077 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3078 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3079 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3080 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3081
303b81e0 3082 intel_fdi_normal_train(crtc);
5e84e1a4 3083
c98e9dcf
JB		 3084 /* For PCH DP, enable TRANS_DP_CTL */
3085 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3086 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3087 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3088 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3089 reg = TRANS_DP_CTL(pipe);
3090 temp = I915_READ(reg);
3091 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3092 TRANS_DP_SYNC_MASK |
3093 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3094 temp |= (TRANS_DP_OUTPUT_ENABLE |
3095 TRANS_DP_ENH_FRAMING);
9325c9f0 3096 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3097
3098 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3099 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3100 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3101 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3102
3103 switch (intel_trans_dp_port_sel(crtc)) {
3104 case PCH_DP_B:
5eddb70b 3105 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3106 break;
3107 case PCH_DP_C:
5eddb70b 3108 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3109 break;
3110 case PCH_DP_D:
5eddb70b 3111 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3112 break;
3113 default:
e95d41e1 3114 BUG();
32f9d658 3115 }
2c07245f 3116
5eddb70b 3117 I915_WRITE(reg, temp);
6be4a607 3118 }
b52eb4dc 3119
b8a4f404 3120 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3121}
3122
1507e5bd
PZ		 3123static void lpt_pch_enable(struct drm_crtc *crtc)
3124{
3125 struct drm_device *dev = crtc->dev;
3126 struct drm_i915_private *dev_priv = dev->dev_private;
3127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3128 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3129
daed2dbb 3130 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3131
8c52b5e8 3132 lpt_program_iclkip(crtc);
1507e5bd 3133
0540e488 3134 /* Set transcoder timing. */
daed2dbb
PZ		 3135 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3136 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3137 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3138
daed2dbb
PZ		 3139 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3140 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3141 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3142 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3143
937bb610 3144 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3145}
3146
ee7b9f93
JB		 3147static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3148{
3149 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3150
3151 if (pll == NULL)
3152 return;
3153
3154 if (pll->refcount == 0) {
3155 WARN(1, "bad PCH PLL refcount\n");
3156 return;
3157 }
3158
3159 --pll->refcount;
3160 intel_crtc->pch_pll = NULL;
3161}
3162
3163static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3164{
3165 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3166 struct intel_pch_pll *pll;
3167 int i;
3168
3169 pll = intel_crtc->pch_pll;
3170 if (pll) {
3171 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3172 intel_crtc->base.base.id, pll->pll_reg);
3173 goto prepare;
3174 }
3175
98b6bd99
DV		 3176 if (HAS_PCH_IBX(dev_priv->dev)) {
3177 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3178 i = intel_crtc->pipe;
3179 pll = &dev_priv->pch_plls[i];
3180
3181 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3182 intel_crtc->base.base.id, pll->pll_reg);
3183
3184 goto found;
3185 }
3186
ee7b9f93
JB		 3187 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3188 pll = &dev_priv->pch_plls[i];
3189
3190 /* Only want to check enabled timings first */
3191 if (pll->refcount == 0)
3192 continue;
3193
3194 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3195 fp == I915_READ(pll->fp0_reg)) {
3196 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3197 intel_crtc->base.base.id,
3198 pll->pll_reg, pll->refcount, pll->active);
3199
3200 goto found;
3201 }
3202 }
3203
3204 /* Ok no matching timings, maybe there's a free one? */
3205 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3206 pll = &dev_priv->pch_plls[i];
3207 if (pll->refcount == 0) {
3208 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3209 intel_crtc->base.base.id, pll->pll_reg);
3210 goto found;
3211 }
3212 }
3213
3214 return NULL;
3215
3216found:
3217 intel_crtc->pch_pll = pll;
3218 pll->refcount++;
3219 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3220prepare: /* separate function? */
3221 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3222
e04c7350
CW		 3223 /* Wait for the clocks to stabilize before rewriting the regs */
3224 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3225 POSTING_READ(pll->pll_reg);
3226 udelay(150);
e04c7350
CW		 3227
3228 I915_WRITE(pll->fp0_reg, fp);
3229 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3230 pll->on = false;
3231 return pll;
3232}
3233
d4270e57
JB		 3234void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3235{
3236 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3237 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3238 u32 temp;
3239
3240 temp = I915_READ(dslreg);
3241 udelay(500);
3242 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3243 if (wait_for(I915_READ(dslreg) != temp, 5))
3244 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3245 }
3246}
3247
f67a559d
JB		 3248static void ironlake_crtc_enable(struct drm_crtc *crtc)
3249{
3250 struct drm_device *dev = crtc->dev;
3251 struct drm_i915_private *dev_priv = dev->dev_private;
3252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3253 struct intel_encoder *encoder;
f67a559d
JB		 3254 int pipe = intel_crtc->pipe;
3255 int plane = intel_crtc->plane;
3256 u32 temp;
3257 bool is_pch_port;
3258
08a48469
DV		 3259 WARN_ON(!crtc->enabled);
3260
f67a559d
JB		 3261 if (intel_crtc->active)
3262 return;
3263
3264 intel_crtc->active = true;
3265 intel_update_watermarks(dev);
3266
3267 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3268 temp = I915_READ(PCH_LVDS);
3269 if ((temp & LVDS_PORT_EN) == 0)
3270 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3271 }
3272
fc316cbe 3273 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3274
46b6f814 3275 if (is_pch_port) {
fff367c7
DV		 3276 /* Note: FDI PLL enabling _must_ be done before we enable the
3277 * cpu pipes, hence this is separate from all the other fdi/pch
3278 * enabling. */
88cefb6c 3279 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3280 } else {
3281 assert_fdi_tx_disabled(dev_priv, pipe);
3282 assert_fdi_rx_disabled(dev_priv, pipe);
3283 }
f67a559d 3284
bf49ec8c
DV		 3285 for_each_encoder_on_crtc(dev, crtc, encoder)
3286 if (encoder->pre_enable)
3287 encoder->pre_enable(encoder);
f67a559d
JB		 3288
3289 /* Enable panel fitting for LVDS */
3290 if (dev_priv->pch_pf_size &&
547dc041
JN		 3291 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3292 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3293 /* Force use of hard-coded filter coefficients
3294 * as some pre-programmed values are broken,
3295 * e.g. x201.
3296 */
13888d78
PZ		 3297 if (IS_IVYBRIDGE(dev))
3298 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3299 PF_PIPE_SEL_IVB(pipe));
3300 else
3301 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3302 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3303 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3304 }
3305
9c54c0dd
JB		 3306 /*
3307 * On ILK+ LUT must be loaded before the pipe is running but with
3308 * clocks enabled
3309 */
3310 intel_crtc_load_lut(crtc);
3311
f67a559d
JB		 3312 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3313 intel_enable_plane(dev_priv, plane, pipe);
3314
3315 if (is_pch_port)
3316 ironlake_pch_enable(crtc);
c98e9dcf 3317
d1ebd816 3318 mutex_lock(&dev->struct_mutex);
bed4a673 3319 intel_update_fbc(dev);
d1ebd816
BW		 3320 mutex_unlock(&dev->struct_mutex);
3321
6b383a7f 3322 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3323
fa5c73b1
DV		 3324 for_each_encoder_on_crtc(dev, crtc, encoder)
3325 encoder->enable(encoder);
61b77ddd
DV		 3326
3327 if (HAS_PCH_CPT(dev))
3328 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3329
3330 /*
3331 * There seems to be a race in PCH platform hw (at least on some
3332 * outputs) where an enabled pipe still completes any pageflip right
3333 * away (as if the pipe is off) instead of waiting for vblank. As soon
3334 * as the first vblank happend, everything works as expected. Hence just
3335 * wait for one vblank before returning to avoid strange things
3336 * happening.
3337 */
3338 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3339}
3340
4f771f10
PZ		 3341static void haswell_crtc_enable(struct drm_crtc *crtc)
3342{
3343 struct drm_device *dev = crtc->dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3346 struct intel_encoder *encoder;
3347 int pipe = intel_crtc->pipe;
3348 int plane = intel_crtc->plane;
4f771f10
PZ		 3349 bool is_pch_port;
3350
3351 WARN_ON(!crtc->enabled);
3352
3353 if (intel_crtc->active)
3354 return;
3355
3356 intel_crtc->active = true;
3357 intel_update_watermarks(dev);
3358
fc316cbe 3359 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3360
83616634 3361 if (is_pch_port)
04945641 3362 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3363
3364 for_each_encoder_on_crtc(dev, crtc, encoder)
3365 if (encoder->pre_enable)
3366 encoder->pre_enable(encoder);
3367
1f544388 3368 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3369
1f544388 3370 /* Enable panel fitting for eDP */
547dc041
JN		 3371 if (dev_priv->pch_pf_size &&
3372 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3373 /* Force use of hard-coded filter coefficients
3374 * as some pre-programmed values are broken,
3375 * e.g. x201.
3376 */
54075a7d
PZ		 3377 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3378 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3379 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3380 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3381 }
3382
3383 /*
3384 * On ILK+ LUT must be loaded before the pipe is running but with
3385 * clocks enabled
3386 */
3387 intel_crtc_load_lut(crtc);
3388
1f544388
PZ		 3389 intel_ddi_set_pipe_settings(crtc);
3390 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3391
3392 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3393 intel_enable_plane(dev_priv, plane, pipe);
3394
3395 if (is_pch_port)
1507e5bd 3396 lpt_pch_enable(crtc);
4f771f10
PZ		 3397
3398 mutex_lock(&dev->struct_mutex);
3399 intel_update_fbc(dev);
3400 mutex_unlock(&dev->struct_mutex);
3401
3402 intel_crtc_update_cursor(crtc, true);
3403
3404 for_each_encoder_on_crtc(dev, crtc, encoder)
3405 encoder->enable(encoder);
3406
4f771f10
PZ		 3407 /*
3408 * There seems to be a race in PCH platform hw (at least on some
3409 * outputs) where an enabled pipe still completes any pageflip right
3410 * away (as if the pipe is off) instead of waiting for vblank. As soon
3411 * as the first vblank happend, everything works as expected. Hence just
3412 * wait for one vblank before returning to avoid strange things
3413 * happening.
3414 */
3415 intel_wait_for_vblank(dev, intel_crtc->pipe);
3416}
3417
6be4a607
JB		 3418static void ironlake_crtc_disable(struct drm_crtc *crtc)
3419{
3420 struct drm_device *dev = crtc->dev;
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3423 struct intel_encoder *encoder;
6be4a607
JB		 3424 int pipe = intel_crtc->pipe;
3425 int plane = intel_crtc->plane;
5eddb70b 3426 u32 reg, temp;
b52eb4dc 3427
ef9c3aee 3428
f7abfe8b
CW		 3429 if (!intel_crtc->active)
3430 return;
3431
ea9d758d
DV		 3432 for_each_encoder_on_crtc(dev, crtc, encoder)
3433 encoder->disable(encoder);
3434
e6c3a2a6 3435 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3436 drm_vblank_off(dev, pipe);
6b383a7f 3437 intel_crtc_update_cursor(crtc, false);
5eddb70b 3438
b24e7179 3439 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3440
973d04f9
CW		 3441 if (dev_priv->cfb_plane == plane)
3442 intel_disable_fbc(dev);
2c07245f 3443
b24e7179 3444 intel_disable_pipe(dev_priv, pipe);
32f9d658 3445
6be4a607 3446 /* Disable PF */
9db4a9c7
JB		 3447 I915_WRITE(PF_CTL(pipe), 0);
3448 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3449
bf49ec8c
DV		 3450 for_each_encoder_on_crtc(dev, crtc, encoder)
3451 if (encoder->post_disable)
3452 encoder->post_disable(encoder);
2c07245f 3453
0fc932b8 3454 ironlake_fdi_disable(crtc);
249c0e64 3455
b8a4f404 3456 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3457
6be4a607
JB		 3458 if (HAS_PCH_CPT(dev)) {
3459 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3460 reg = TRANS_DP_CTL(pipe);
3461 temp = I915_READ(reg);
3462 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3463 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3464 I915_WRITE(reg, temp);
6be4a607
JB		 3465
3466 /* disable DPLL_SEL */
3467 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3468 switch (pipe) {
3469 case 0:
d64311ab 3470 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3471 break;
3472 case 1:
6be4a607 3473 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3474 break;
3475 case 2:
4b645f14 3476 /* C shares PLL A or B */
d64311ab 3477 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3478 break;
3479 default:
3480 BUG(); /* wtf */
3481 }
6be4a607 3482 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3483 }
e3421a18 3484
6be4a607 3485 /* disable PCH DPLL */
ee7b9f93 3486 intel_disable_pch_pll(intel_crtc);
8db9d77b 3487
88cefb6c 3488 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3489
f7abfe8b 3490 intel_crtc->active = false;
6b383a7f 3491 intel_update_watermarks(dev);
d1ebd816
BW		 3492
3493 mutex_lock(&dev->struct_mutex);
6b383a7f 3494 intel_update_fbc(dev);
d1ebd816 3495 mutex_unlock(&dev->struct_mutex);
6be4a607 3496}
1b3c7a47 3497
4f771f10 3498static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3499{
4f771f10
PZ		 3500 struct drm_device *dev = crtc->dev;
3501 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3503 struct intel_encoder *encoder;
3504 int pipe = intel_crtc->pipe;
3505 int plane = intel_crtc->plane;
ad80a810 3506 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3507 bool is_pch_port;
ee7b9f93 3508
4f771f10
PZ		 3509 if (!intel_crtc->active)
3510 return;
3511
83616634
PZ		 3512 is_pch_port = haswell_crtc_driving_pch(crtc);
3513
4f771f10
PZ		 3514 for_each_encoder_on_crtc(dev, crtc, encoder)
3515 encoder->disable(encoder);
3516
3517 intel_crtc_wait_for_pending_flips(crtc);
3518 drm_vblank_off(dev, pipe);
3519 intel_crtc_update_cursor(crtc, false);
3520
3521 intel_disable_plane(dev_priv, plane, pipe);
3522
3523 if (dev_priv->cfb_plane == plane)
3524 intel_disable_fbc(dev);
3525
3526 intel_disable_pipe(dev_priv, pipe);
3527
ad80a810 3528 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3529
3530 /* Disable PF */
3531 I915_WRITE(PF_CTL(pipe), 0);
3532 I915_WRITE(PF_WIN_SZ(pipe), 0);
3533
1f544388 3534 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3535
3536 for_each_encoder_on_crtc(dev, crtc, encoder)
3537 if (encoder->post_disable)
3538 encoder->post_disable(encoder);
3539
83616634 3540 if (is_pch_port) {
ab4d966c 3541 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3542 intel_ddi_fdi_disable(crtc);
83616634 3543 }
4f771f10
PZ		 3544
3545 intel_crtc->active = false;
3546 intel_update_watermarks(dev);
3547
3548 mutex_lock(&dev->struct_mutex);
3549 intel_update_fbc(dev);
3550 mutex_unlock(&dev->struct_mutex);
3551}
3552
ee7b9f93
JB		 3553static void ironlake_crtc_off(struct drm_crtc *crtc)
3554{
3555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3556 intel_put_pch_pll(intel_crtc);
3557}
3558
6441ab5f
PZ		 3559static void haswell_crtc_off(struct drm_crtc *crtc)
3560{
a5c961d1
PZ		 3561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3562
3563 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3564 * start using it. */
1a240d4d 3565 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3566
6441ab5f
PZ		 3567 intel_ddi_put_crtc_pll(crtc);
3568}
3569
02e792fb
DV		 3570static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3571{
02e792fb 3572 if (!enable && intel_crtc->overlay) {
23f09ce3 3573 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3574 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3575
23f09ce3 3576 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3577 dev_priv->mm.interruptible = false;
3578 (void) intel_overlay_switch_off(intel_crtc->overlay);
3579 dev_priv->mm.interruptible = true;
23f09ce3 3580 mutex_unlock(&dev->struct_mutex);
02e792fb 3581 }
02e792fb 3582
5dcdbcb0
CW		 3583 /* Let userspace switch the overlay on again. In most cases userspace
3584 * has to recompute where to put it anyway.
3585 */
02e792fb
DV		 3586}
3587
0b8765c6 3588static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3589{
3590 struct drm_device *dev = crtc->dev;
79e53945
JB		 3591 struct drm_i915_private *dev_priv = dev->dev_private;
3592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3593 struct intel_encoder *encoder;
79e53945 3594 int pipe = intel_crtc->pipe;
80824003 3595 int plane = intel_crtc->plane;
79e53945 3596
08a48469
DV		 3597 WARN_ON(!crtc->enabled);
3598
f7abfe8b
CW		 3599 if (intel_crtc->active)
3600 return;
3601
3602 intel_crtc->active = true;
6b383a7f
CW		 3603 intel_update_watermarks(dev);
3604
63d7bbe9 3605 intel_enable_pll(dev_priv, pipe);
040484af 3606 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3607 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3608
0b8765c6 3609 intel_crtc_load_lut(crtc);
bed4a673 3610 intel_update_fbc(dev);
79e53945 3611
0b8765c6
JB		 3612 /* Give the overlay scaler a chance to enable if it's on this pipe */
3613 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3614 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3615
fa5c73b1
DV		 3616 for_each_encoder_on_crtc(dev, crtc, encoder)
3617 encoder->enable(encoder);
0b8765c6 3618}
79e53945 3619
0b8765c6
JB		 3620static void i9xx_crtc_disable(struct drm_crtc *crtc)
3621{
3622 struct drm_device *dev = crtc->dev;
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3625 struct intel_encoder *encoder;
0b8765c6
JB		 3626 int pipe = intel_crtc->pipe;
3627 int plane = intel_crtc->plane;
b690e96c 3628
ef9c3aee 3629
f7abfe8b
CW		 3630 if (!intel_crtc->active)
3631 return;
3632
ea9d758d
DV		 3633 for_each_encoder_on_crtc(dev, crtc, encoder)
3634 encoder->disable(encoder);
3635
0b8765c6 3636 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3637 intel_crtc_wait_for_pending_flips(crtc);
3638 drm_vblank_off(dev, pipe);
0b8765c6 3639 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3640 intel_crtc_update_cursor(crtc, false);
0b8765c6 3641
973d04f9
CW		 3642 if (dev_priv->cfb_plane == plane)
3643 intel_disable_fbc(dev);
79e53945 3644
b24e7179 3645 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3646 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3647 intel_disable_pll(dev_priv, pipe);
0b8765c6 3648
f7abfe8b 3649 intel_crtc->active = false;
6b383a7f
CW		 3650 intel_update_fbc(dev);
3651 intel_update_watermarks(dev);
0b8765c6
JB		 3652}
3653
ee7b9f93
JB		 3654static void i9xx_crtc_off(struct drm_crtc *crtc)
3655{
3656}
3657
976f8a20
DV		 3658static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3659 bool enabled)
2c07245f
ZW		 3660{
3661 struct drm_device *dev = crtc->dev;
3662 struct drm_i915_master_private *master_priv;
3663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3664 int pipe = intel_crtc->pipe;
79e53945
JB		 3665
3666 if (!dev->primary->master)
3667 return;
3668
3669 master_priv = dev->primary->master->driver_priv;
3670 if (!master_priv->sarea_priv)
3671 return;
3672
79e53945
JB		 3673 switch (pipe) {
3674 case 0:
3675 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3676 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3677 break;
3678 case 1:
3679 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3680 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3681 break;
3682 default:
9db4a9c7 3683 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3684 break;
3685 }
79e53945
JB		 3686}
3687
976f8a20
DV		 3688/**
3689 * Sets the power management mode of the pipe and plane.
3690 */
3691void intel_crtc_update_dpms(struct drm_crtc *crtc)
3692{
3693 struct drm_device *dev = crtc->dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 struct intel_encoder *intel_encoder;
3696 bool enable = false;
3697
3698 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3699 enable |= intel_encoder->connectors_active;
3700
3701 if (enable)
3702 dev_priv->display.crtc_enable(crtc);
3703 else
3704 dev_priv->display.crtc_disable(crtc);
3705
3706 intel_crtc_update_sarea(crtc, enable);
3707}
3708
3709static void intel_crtc_noop(struct drm_crtc *crtc)
3710{
3711}
3712
cdd59983
CW		 3713static void intel_crtc_disable(struct drm_crtc *crtc)
3714{
cdd59983 3715 struct drm_device *dev = crtc->dev;
976f8a20 3716 struct drm_connector *connector;
ee7b9f93 3717 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3718
976f8a20
DV		 3719 /* crtc should still be enabled when we disable it. */
3720 WARN_ON(!crtc->enabled);
3721
3722 dev_priv->display.crtc_disable(crtc);
3723 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3724 dev_priv->display.off(crtc);
3725
931872fc
CW		 3726 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3727 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3728
3729 if (crtc->fb) {
3730 mutex_lock(&dev->struct_mutex);
1690e1eb 3731 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3732 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3733 crtc->fb = NULL;
3734 }
3735
3736 /* Update computed state. */
3737 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3738 if (!connector->encoder || !connector->encoder->crtc)
3739 continue;
3740
3741 if (connector->encoder->crtc != crtc)
3742 continue;
3743
3744 connector->dpms = DRM_MODE_DPMS_OFF;
3745 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3746 }
3747}
3748
a261b246 3749void intel_modeset_disable(struct drm_device *dev)
79e53945 3750{
a261b246
DV		 3751 struct drm_crtc *crtc;
3752
3753 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3754 if (crtc->enabled)
3755 intel_crtc_disable(crtc);
3756 }
79e53945
JB		 3757}
3758
1f703855 3759void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3760{
7e7d76c3
JB		 3761}
3762
ea5b213a 3763void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3764{
4ef69c7a 3765 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3766
ea5b213a
CW		 3767 drm_encoder_cleanup(encoder);
3768 kfree(intel_encoder);
7e7d76c3
JB		 3769}
3770
5ab432ef
DV		 3771/* Simple dpms helper for encodres with just one connector, no cloning and only
3772 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3773 * state of the entire output pipe. */
3774void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3775{
5ab432ef
DV		 3776 if (mode == DRM_MODE_DPMS_ON) {
3777 encoder->connectors_active = true;
3778
b2cabb0e 3779 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3780 } else {
3781 encoder->connectors_active = false;
3782
b2cabb0e 3783 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3784 }
79e53945
JB		 3785}
3786
0a91ca29
DV		 3787/* Cross check the actual hw state with our own modeset state tracking (and it's
3788 * internal consistency). */
b980514c 3789static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3790{
0a91ca29
DV		 3791 if (connector->get_hw_state(connector)) {
3792 struct intel_encoder *encoder = connector->encoder;
3793 struct drm_crtc *crtc;
3794 bool encoder_enabled;
3795 enum pipe pipe;
3796
3797 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3798 connector->base.base.id,
3799 drm_get_connector_name(&connector->base));
3800
3801 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3802 "wrong connector dpms state\n");
3803 WARN(connector->base.encoder != &encoder->base,
3804 "active connector not linked to encoder\n");
3805 WARN(!encoder->connectors_active,
3806 "encoder->connectors_active not set\n");
3807
3808 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3809 WARN(!encoder_enabled, "encoder not enabled\n");
3810 if (WARN_ON(!encoder->base.crtc))
3811 return;
3812
3813 crtc = encoder->base.crtc;
3814
3815 WARN(!crtc->enabled, "crtc not enabled\n");
3816 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3817 WARN(pipe != to_intel_crtc(crtc)->pipe,
3818 "encoder active on the wrong pipe\n");
3819 }
79e53945
JB		 3820}
3821
5ab432ef
DV		 3822/* Even simpler default implementation, if there's really no special case to
3823 * consider. */
3824void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3825{
5ab432ef 3826 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3827
5ab432ef
DV		 3828 /* All the simple cases only support two dpms states. */
3829 if (mode != DRM_MODE_DPMS_ON)
3830 mode = DRM_MODE_DPMS_OFF;
d4270e57 3831
5ab432ef
DV		 3832 if (mode == connector->dpms)
3833 return;
3834
3835 connector->dpms = mode;
3836
3837 /* Only need to change hw state when actually enabled */
3838 if (encoder->base.crtc)
3839 intel_encoder_dpms(encoder, mode);
3840 else
8af6cf88 3841 WARN_ON(encoder->connectors_active != false);
0a91ca29 3842
b980514c 3843 intel_modeset_check_state(connector->dev);
79e53945
JB		 3844}
3845
f0947c37
DV		 3846/* Simple connector->get_hw_state implementation for encoders that support only
3847 * one connector and no cloning and hence the encoder state determines the state
3848 * of the connector. */
3849bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3850{
24929352 3851 enum pipe pipe = 0;
f0947c37 3852 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3853
f0947c37 3854 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3855}
3856
79e53945 3857static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3858 const struct drm_display_mode *mode,
79e53945
JB		 3859 struct drm_display_mode *adjusted_mode)
3860{
2c07245f 3861 struct drm_device *dev = crtc->dev;
89749350 3862
bad720ff 3863 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3864 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3865 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3866 return false;
2c07245f 3867 }
89749350 3868
f9bef081
DV		 3869 /* All interlaced capable intel hw wants timings in frames. Note though
3870 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3871 * timings, so we need to be careful not to clobber these.*/
3872 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3873 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3874
44f46b42
CW		 3875 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3876 * with a hsync front porch of 0.
3877 */
3878 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3879 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3880 return false;
3881
79e53945
JB		 3882 return true;
3883}
3884
25eb05fc
JB		 3885static int valleyview_get_display_clock_speed(struct drm_device *dev)
3886{
3887 return 400000; /* FIXME */
3888}
3889
e70236a8
JB		 3890static int i945_get_display_clock_speed(struct drm_device *dev)
3891{
3892 return 400000;
3893}
79e53945 3894
e70236a8 3895static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3896{
e70236a8
JB		 3897 return 333000;
3898}
79e53945 3899
e70236a8
JB		 3900static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3901{
3902 return 200000;
3903}
79e53945 3904
e70236a8
JB		 3905static int i915gm_get_display_clock_speed(struct drm_device *dev)
3906{
3907 u16 gcfgc = 0;
79e53945 3908
e70236a8
JB		 3909 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3910
3911 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3912 return 133000;
3913 else {
3914 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3915 case GC_DISPLAY_CLOCK_333_MHZ:
3916 return 333000;
3917 default:
3918 case GC_DISPLAY_CLOCK_190_200_MHZ:
3919 return 190000;
79e53945 3920 }
e70236a8
JB		 3921 }
3922}
3923
3924static int i865_get_display_clock_speed(struct drm_device *dev)
3925{
3926 return 266000;
3927}
3928
3929static int i855_get_display_clock_speed(struct drm_device *dev)
3930{
3931 u16 hpllcc = 0;
3932 /* Assume that the hardware is in the high speed state. This
3933 * should be the default.
3934 */
3935 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3936 case GC_CLOCK_133_200:
3937 case GC_CLOCK_100_200:
3938 return 200000;
3939 case GC_CLOCK_166_250:
3940 return 250000;
3941 case GC_CLOCK_100_133:
79e53945 3942 return 133000;
e70236a8 3943 }
79e53945 3944
e70236a8
JB		 3945 /* Shouldn't happen */
3946 return 0;
3947}
79e53945 3948
e70236a8
JB		 3949static int i830_get_display_clock_speed(struct drm_device *dev)
3950{
3951 return 133000;
79e53945
JB		 3952}
3953
2c07245f
ZW		 3954struct fdi_m_n {
3955 u32 tu;
3956 u32 gmch_m;
3957 u32 gmch_n;
3958 u32 link_m;
3959 u32 link_n;
3960};
3961
3962static void
3963fdi_reduce_ratio(u32 *num, u32 *den)
3964{
3965 while (*num > 0xffffff || *den > 0xffffff) {
3966 *num >>= 1;
3967 *den >>= 1;
3968 }
3969}
3970
2c07245f 3971static void
f2b115e6
AJ		 3972ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3973 int link_clock, struct fdi_m_n *m_n)
2c07245f 3974{
2c07245f
ZW		 3975 m_n->tu = 64; /* default size */
3976
22ed1113
CW		 3977 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3978 m_n->gmch_m = bits_per_pixel * pixel_clock;
3979 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3980 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3981
22ed1113
CW		 3982 m_n->link_m = pixel_clock;
3983 m_n->link_n = link_clock;
2c07245f
ZW		 3984 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3985}
3986
a7615030
CW		 3987static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3988{
72bbe58c
KP		 3989 if (i915_panel_use_ssc >= 0)
3990 return i915_panel_use_ssc != 0;
3991 return dev_priv->lvds_use_ssc
435793df 3992 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3993}
3994
5a354204
JB		 3995/**
3996 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3997 * @crtc: CRTC structure
3b5c78a3 3998 * @mode: requested mode
5a354204
JB		 3999 *
4000 * A pipe may be connected to one or more outputs. Based on the depth of the
4001 * attached framebuffer, choose a good color depth to use on the pipe.
4002 *
4003 * If possible, match the pipe depth to the fb depth. In some cases, this
4004 * isn't ideal, because the connected output supports a lesser or restricted
4005 * set of depths. Resolve that here:
4006 * LVDS typically supports only 6bpc, so clamp down in that case
4007 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4008 * Displays may support a restricted set as well, check EDID and clamp as
4009 * appropriate.
3b5c78a3 4010 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4011 *
4012 * RETURNS:
4013 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4014 * true if they don't match).
4015 */
4016static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4017 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4018 unsigned int *pipe_bpp,
4019 struct drm_display_mode *mode)
5a354204
JB		 4020{
4021 struct drm_device *dev = crtc->dev;
4022 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4023 struct drm_connector *connector;
6c2b7c12 4024 struct intel_encoder *intel_encoder;
5a354204
JB		 4025 unsigned int display_bpc = UINT_MAX, bpc;
4026
4027 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4028 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4029
4030 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4031 unsigned int lvds_bpc;
4032
4033 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4034 LVDS_A3_POWER_UP)
4035 lvds_bpc = 8;
4036 else
4037 lvds_bpc = 6;
4038
4039 if (lvds_bpc < display_bpc) {
82820490 4040 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4041 display_bpc = lvds_bpc;
4042 }
4043 continue;
4044 }
4045
5a354204
JB		 4046 /* Not one of the known troublemakers, check the EDID */
4047 list_for_each_entry(connector, &dev->mode_config.connector_list,
4048 head) {
6c2b7c12 4049 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4050 continue;
4051
62ac41a6
JB		 4052 /* Don't use an invalid EDID bpc value */
4053 if (connector->display_info.bpc &&
4054 connector->display_info.bpc < display_bpc) {
82820490 4055 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4056 display_bpc = connector->display_info.bpc;
4057 }
4058 }
4059
4060 /*
4061 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4062 * through, clamp it down. (Note: >12bpc will be caught below.)
4063 */
4064 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4065 if (display_bpc > 8 && display_bpc < 12) {
82820490 4066 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4067 display_bpc = 12;
4068 } else {
82820490 4069 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4070 display_bpc = 8;
4071 }
4072 }
4073 }
4074
3b5c78a3
AJ		 4075 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4076 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4077 display_bpc = 6;
4078 }
4079
5a354204
JB		 4080 /*
4081 * We could just drive the pipe at the highest bpc all the time and
4082 * enable dithering as needed, but that costs bandwidth. So choose
4083 * the minimum value that expresses the full color range of the fb but
4084 * also stays within the max display bpc discovered above.
4085 */
4086
94352cf9 4087 switch (fb->depth) {
5a354204
JB		 4088 case 8:
4089 bpc = 8; /* since we go through a colormap */
4090 break;
4091 case 15:
4092 case 16:
4093 bpc = 6; /* min is 18bpp */
4094 break;
4095 case 24:
578393cd 4096 bpc = 8;
5a354204
JB		 4097 break;
4098 case 30:
578393cd 4099 bpc = 10;
5a354204
JB		 4100 break;
4101 case 48:
578393cd 4102 bpc = 12;
5a354204
JB		 4103 break;
4104 default:
4105 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4106 bpc = min((unsigned int)8, display_bpc);
4107 break;
4108 }
4109
578393cd
KP		 4110 display_bpc = min(display_bpc, bpc);
4111
82820490
AJ		 4112 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4113 bpc, display_bpc);
5a354204 4114
578393cd 4115 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4116
4117 return display_bpc != bpc;
4118}
4119
a0c4da24
JB		 4120static int vlv_get_refclk(struct drm_crtc *crtc)
4121{
4122 struct drm_device *dev = crtc->dev;
4123 struct drm_i915_private *dev_priv = dev->dev_private;
4124 int refclk = 27000; /* for DP & HDMI */
4125
4126 return 100000; /* only one validated so far */
4127
4128 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4129 refclk = 96000;
4130 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4131 if (intel_panel_use_ssc(dev_priv))
4132 refclk = 100000;
4133 else
4134 refclk = 96000;
4135 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4136 refclk = 100000;
4137 }
4138
4139 return refclk;
4140}
4141
c65d77d8
JB		 4142static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4143{
4144 struct drm_device *dev = crtc->dev;
4145 struct drm_i915_private *dev_priv = dev->dev_private;
4146 int refclk;
4147
a0c4da24
JB		 4148 if (IS_VALLEYVIEW(dev)) {
4149 refclk = vlv_get_refclk(crtc);
4150 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4151 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4152 refclk = dev_priv->lvds_ssc_freq * 1000;
4153 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4154 refclk / 1000);
4155 } else if (!IS_GEN2(dev)) {
4156 refclk = 96000;
4157 } else {
4158 refclk = 48000;
4159 }
4160
4161 return refclk;
4162}
4163
4164static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4165 intel_clock_t *clock)
4166{
4167 /* SDVO TV has fixed PLL values depend on its clock range,
4168 this mirrors vbios setting. */
4169 if (adjusted_mode->clock >= 100000
4170 && adjusted_mode->clock < 140500) {
4171 clock->p1 = 2;
4172 clock->p2 = 10;
4173 clock->n = 3;
4174 clock->m1 = 16;
4175 clock->m2 = 8;
4176 } else if (adjusted_mode->clock >= 140500
4177 && adjusted_mode->clock <= 200000) {
4178 clock->p1 = 1;
4179 clock->p2 = 10;
4180 clock->n = 6;
4181 clock->m1 = 12;
4182 clock->m2 = 8;
4183 }
4184}
4185
a7516a05
JB		 4186static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4187 intel_clock_t *clock,
4188 intel_clock_t *reduced_clock)
4189{
4190 struct drm_device *dev = crtc->dev;
4191 struct drm_i915_private *dev_priv = dev->dev_private;
4192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4193 int pipe = intel_crtc->pipe;
4194 u32 fp, fp2 = 0;
4195
4196 if (IS_PINEVIEW(dev)) {
4197 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4198 if (reduced_clock)
4199 fp2 = (1 << reduced_clock->n) << 16 |
4200 reduced_clock->m1 << 8 | reduced_clock->m2;
4201 } else {
4202 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4203 if (reduced_clock)
4204 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4205 reduced_clock->m2;
4206 }
4207
4208 I915_WRITE(FP0(pipe), fp);
4209
4210 intel_crtc->lowfreq_avail = false;
4211 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4212 reduced_clock && i915_powersave) {
4213 I915_WRITE(FP1(pipe), fp2);
4214 intel_crtc->lowfreq_avail = true;
4215 } else {
4216 I915_WRITE(FP1(pipe), fp);
4217 }
4218}
4219
a0c4da24
JB		 4220static void vlv_update_pll(struct drm_crtc *crtc,
4221 struct drm_display_mode *mode,
4222 struct drm_display_mode *adjusted_mode,
4223 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4224 int num_connectors)
a0c4da24
JB		 4225{
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4229 int pipe = intel_crtc->pipe;
4230 u32 dpll, mdiv, pdiv;
4231 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4232 bool is_sdvo;
4233 u32 temp;
a0c4da24 4234
2a8f64ca
VP		 4235 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4236 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4237
2a8f64ca
VP		 4238 dpll = DPLL_VGA_MODE_DIS;
4239 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4240 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4241 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4242
4243 I915_WRITE(DPLL(pipe), dpll);
4244 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4245
4246 bestn = clock->n;
4247 bestm1 = clock->m1;
4248 bestm2 = clock->m2;
4249 bestp1 = clock->p1;
4250 bestp2 = clock->p2;
4251
2a8f64ca
VP		 4252 /*
4253 * In Valleyview PLL and program lane counter registers are exposed
4254 * through DPIO interface
4255 */
a0c4da24
JB		 4256 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4257 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4258 mdiv |= ((bestn << DPIO_N_SHIFT));
4259 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4260 mdiv |= (1 << DPIO_K_SHIFT);
4261 mdiv |= DPIO_ENABLE_CALIBRATION;
4262 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4263
4264 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4265
2a8f64ca 4266 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4267 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4268 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4269 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4270 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4271
2a8f64ca 4272 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4273
4274 dpll |= DPLL_VCO_ENABLE;
4275 I915_WRITE(DPLL(pipe), dpll);
4276 POSTING_READ(DPLL(pipe));
4277 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4278 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4279
2a8f64ca
VP		 4280 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4281
4282 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4283 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4284
4285 I915_WRITE(DPLL(pipe), dpll);
4286
4287 /* Wait for the clocks to stabilize. */
4288 POSTING_READ(DPLL(pipe));
4289 udelay(150);
a0c4da24 4290
2a8f64ca
VP		 4291 temp = 0;
4292 if (is_sdvo) {
4293 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4294 if (temp > 1)
4295 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4296 else
4297 temp = 0;
a0c4da24 4298 }
2a8f64ca
VP		 4299 I915_WRITE(DPLL_MD(pipe), temp);
4300 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4301
2a8f64ca
VP		 4302 /* Now program lane control registers */
4303 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4304 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4305 {
4306 temp = 0x1000C4;
4307 if(pipe == 1)
4308 temp |= (1 << 21);
4309 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4310 }
4311 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4312 {
4313 temp = 0x1000C4;
4314 if(pipe == 1)
4315 temp |= (1 << 21);
4316 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4317 }
a0c4da24
JB		 4318}
4319
eb1cbe48
DV		 4320static void i9xx_update_pll(struct drm_crtc *crtc,
4321 struct drm_display_mode *mode,
4322 struct drm_display_mode *adjusted_mode,
4323 intel_clock_t *clock, intel_clock_t *reduced_clock,
4324 int num_connectors)
4325{
4326 struct drm_device *dev = crtc->dev;
4327 struct drm_i915_private *dev_priv = dev->dev_private;
4328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4329 struct intel_encoder *encoder;
eb1cbe48
DV		 4330 int pipe = intel_crtc->pipe;
4331 u32 dpll;
4332 bool is_sdvo;
4333
2a8f64ca
VP		 4334 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4335
eb1cbe48
DV		 4336 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4337 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4338
4339 dpll = DPLL_VGA_MODE_DIS;
4340
4341 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4342 dpll |= DPLLB_MODE_LVDS;
4343 else
4344 dpll |= DPLLB_MODE_DAC_SERIAL;
4345 if (is_sdvo) {
4346 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4347 if (pixel_multiplier > 1) {
4348 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4349 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4350 }
4351 dpll |= DPLL_DVO_HIGH_SPEED;
4352 }
4353 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4354 dpll |= DPLL_DVO_HIGH_SPEED;
4355
4356 /* compute bitmask from p1 value */
4357 if (IS_PINEVIEW(dev))
4358 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4359 else {
4360 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4361 if (IS_G4X(dev) && reduced_clock)
4362 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4363 }
4364 switch (clock->p2) {
4365 case 5:
4366 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4367 break;
4368 case 7:
4369 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4370 break;
4371 case 10:
4372 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4373 break;
4374 case 14:
4375 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4376 break;
4377 }
4378 if (INTEL_INFO(dev)->gen >= 4)
4379 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4380
4381 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4382 dpll |= PLL_REF_INPUT_TVCLKINBC;
4383 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4384 /* XXX: just matching BIOS for now */
4385 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4386 dpll |= 3;
4387 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4388 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4389 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4390 else
4391 dpll |= PLL_REF_INPUT_DREFCLK;
4392
4393 dpll |= DPLL_VCO_ENABLE;
4394 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4395 POSTING_READ(DPLL(pipe));
4396 udelay(150);
4397
dafd226c
DV		 4398 for_each_encoder_on_crtc(dev, crtc, encoder)
4399 if (encoder->pre_pll_enable)
4400 encoder->pre_pll_enable(encoder);
4401
eb1cbe48
DV		 4402 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4403 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4404
4405 I915_WRITE(DPLL(pipe), dpll);
4406
4407 /* Wait for the clocks to stabilize. */
4408 POSTING_READ(DPLL(pipe));
4409 udelay(150);
4410
4411 if (INTEL_INFO(dev)->gen >= 4) {
4412 u32 temp = 0;
4413 if (is_sdvo) {
4414 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4415 if (temp > 1)
4416 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4417 else
4418 temp = 0;
4419 }
4420 I915_WRITE(DPLL_MD(pipe), temp);
4421 } else {
4422 /* The pixel multiplier can only be updated once the
4423 * DPLL is enabled and the clocks are stable.
4424 *
4425 * So write it again.
4426 */
4427 I915_WRITE(DPLL(pipe), dpll);
4428 }
4429}
4430
4431static void i8xx_update_pll(struct drm_crtc *crtc,
4432 struct drm_display_mode *adjusted_mode,
2a8f64ca 4433 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4434 int num_connectors)
4435{
4436 struct drm_device *dev = crtc->dev;
4437 struct drm_i915_private *dev_priv = dev->dev_private;
4438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4439 struct intel_encoder *encoder;
eb1cbe48
DV		 4440 int pipe = intel_crtc->pipe;
4441 u32 dpll;
4442
2a8f64ca
VP		 4443 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4444
eb1cbe48
DV		 4445 dpll = DPLL_VGA_MODE_DIS;
4446
4447 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4448 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4449 } else {
4450 if (clock->p1 == 2)
4451 dpll |= PLL_P1_DIVIDE_BY_TWO;
4452 else
4453 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4454 if (clock->p2 == 4)
4455 dpll |= PLL_P2_DIVIDE_BY_4;
4456 }
4457
4458 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4459 /* XXX: just matching BIOS for now */
4460 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4461 dpll |= 3;
4462 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4463 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4464 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4465 else
4466 dpll |= PLL_REF_INPUT_DREFCLK;
4467
4468 dpll |= DPLL_VCO_ENABLE;
4469 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4470 POSTING_READ(DPLL(pipe));
4471 udelay(150);
4472
dafd226c
DV		 4473 for_each_encoder_on_crtc(dev, crtc, encoder)
4474 if (encoder->pre_pll_enable)
4475 encoder->pre_pll_enable(encoder);
4476
5b5896e4
DV		 4477 I915_WRITE(DPLL(pipe), dpll);
4478
4479 /* Wait for the clocks to stabilize. */
4480 POSTING_READ(DPLL(pipe));
4481 udelay(150);
4482
eb1cbe48
DV		 4483 /* The pixel multiplier can only be updated once the
4484 * DPLL is enabled and the clocks are stable.
4485 *
4486 * So write it again.
4487 */
4488 I915_WRITE(DPLL(pipe), dpll);
4489}
4490
b0e77b9c
PZ		 4491static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4492 struct drm_display_mode *mode,
4493 struct drm_display_mode *adjusted_mode)
4494{
4495 struct drm_device *dev = intel_crtc->base.dev;
4496 struct drm_i915_private *dev_priv = dev->dev_private;
4497 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4498 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4499 uint32_t vsyncshift;
4500
4501 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4502 /* the chip adds 2 halflines automatically */
4503 adjusted_mode->crtc_vtotal -= 1;
4504 adjusted_mode->crtc_vblank_end -= 1;
4505 vsyncshift = adjusted_mode->crtc_hsync_start
4506 - adjusted_mode->crtc_htotal / 2;
4507 } else {
4508 vsyncshift = 0;
4509 }
4510
4511 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4512 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4513
fe2b8f9d 4514 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4515 (adjusted_mode->crtc_hdisplay - 1) |
4516 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4517 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4518 (adjusted_mode->crtc_hblank_start - 1) |
4519 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4520 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4521 (adjusted_mode->crtc_hsync_start - 1) |
4522 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4523
fe2b8f9d 4524 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4525 (adjusted_mode->crtc_vdisplay - 1) |
4526 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4527 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4528 (adjusted_mode->crtc_vblank_start - 1) |
4529 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4530 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4531 (adjusted_mode->crtc_vsync_start - 1) |
4532 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4533
b5e508d4
PZ		 4534 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4535 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4536 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4537 * bits. */
4538 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4539 (pipe == PIPE_B || pipe == PIPE_C))
4540 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4541
b0e77b9c
PZ		 4542 /* pipesrc controls the size that is scaled from, which should
4543 * always be the user's requested size.
4544 */
4545 I915_WRITE(PIPESRC(pipe),
4546 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4547}
4548
f564048e
EA		 4549static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4550 struct drm_display_mode *mode,
4551 struct drm_display_mode *adjusted_mode,
4552 int x, int y,
94352cf9 4553 struct drm_framebuffer *fb)
79e53945
JB		 4554{
4555 struct drm_device *dev = crtc->dev;
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4558 int pipe = intel_crtc->pipe;
80824003 4559 int plane = intel_crtc->plane;
c751ce4f 4560 int refclk, num_connectors = 0;
652c393a 4561 intel_clock_t clock, reduced_clock;
b0e77b9c 4562 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4563 bool ok, has_reduced_clock = false, is_sdvo = false;
4564 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4565 struct intel_encoder *encoder;
d4906093 4566 const intel_limit_t *limit;
5c3b82e2 4567 int ret;
79e53945 4568
6c2b7c12 4569 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4570 switch (encoder->type) {
79e53945
JB		 4571 case INTEL_OUTPUT_LVDS:
4572 is_lvds = true;
4573 break;
4574 case INTEL_OUTPUT_SDVO:
7d57382e 4575 case INTEL_OUTPUT_HDMI:
79e53945 4576 is_sdvo = true;
5eddb70b 4577 if (encoder->needs_tv_clock)
e2f0ba97 4578 is_tv = true;
79e53945 4579 break;
79e53945
JB		 4580 case INTEL_OUTPUT_TVOUT:
4581 is_tv = true;
4582 break;
a4fc5ed6
KP		 4583 case INTEL_OUTPUT_DISPLAYPORT:
4584 is_dp = true;
4585 break;
79e53945 4586 }
43565a06 4587
c751ce4f 4588 num_connectors++;
79e53945
JB		 4589 }
4590
c65d77d8 4591 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4592
d4906093
ML		 4593 /*
4594 * Returns a set of divisors for the desired target clock with the given
4595 * refclk, or FALSE. The returned values represent the clock equation:
4596 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4597 */
1b894b59 4598 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4599 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4600 &clock);
79e53945
JB		 4601 if (!ok) {
4602 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4603 return -EINVAL;
79e53945
JB		 4604 }
4605
cda4b7d3 4606 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4607 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4608
ddc9003c 4609 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4610 /*
4611 * Ensure we match the reduced clock's P to the target clock.
4612 * If the clocks don't match, we can't switch the display clock
4613 * by using the FP0/FP1. In such case we will disable the LVDS
4614 * downclock feature.
4615 */
ddc9003c 4616 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4617 dev_priv->lvds_downclock,
4618 refclk,
cec2f356 4619 &clock,
5eddb70b 4620 &reduced_clock);
7026d4ac
ZW		 4621 }
4622
c65d77d8
JB		 4623 if (is_sdvo && is_tv)
4624 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4625
eb1cbe48 4626 if (IS_GEN2(dev))
2a8f64ca
VP		 4627 i8xx_update_pll(crtc, adjusted_mode, &clock,
4628 has_reduced_clock ? &reduced_clock : NULL,
4629 num_connectors);
a0c4da24 4630 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4631 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4632 has_reduced_clock ? &reduced_clock : NULL,
4633 num_connectors);
79e53945 4634 else
eb1cbe48
DV		 4635 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4636 has_reduced_clock ? &reduced_clock : NULL,
4637 num_connectors);
79e53945
JB		 4638
4639 /* setup pipeconf */
5eddb70b 4640 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4641
4642 /* Set up the display plane register */
4643 dspcntr = DISPPLANE_GAMMA_ENABLE;
4644
929c77fb
EA		 4645 if (pipe == 0)
4646 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4647 else
4648 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4649
a6c45cf0 4650 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4651 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4652 * core speed.
4653 *
4654 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4655 * pipe == 0 check?
4656 */
e70236a8
JB		 4657 if (mode->clock >
4658 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4659 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4660 else
5eddb70b 4661 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4662 }
4663
3b5c78a3
AJ		 4664 /* default to 8bpc */
4665 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4666 if (is_dp) {
0c96c65b 4667 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4668 pipeconf |= PIPECONF_BPP_6 |
4669 PIPECONF_DITHER_EN |
4670 PIPECONF_DITHER_TYPE_SP;
4671 }
4672 }
4673
19c03924
GB		 4674 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4675 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4676 pipeconf |= PIPECONF_BPP_6 |
4677 PIPECONF_ENABLE |
4678 I965_PIPECONF_ACTIVE;
4679 }
4680 }
4681
28c97730 4682 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4683 drm_mode_debug_printmodeline(mode);
4684
a7516a05
JB		 4685 if (HAS_PIPE_CXSR(dev)) {
4686 if (intel_crtc->lowfreq_avail) {
28c97730 4687 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4688 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4689 } else {
28c97730 4690 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4691 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4692 }
4693 }
4694
617cf884 4695 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4696 if (!IS_GEN2(dev) &&
b0e77b9c 4697 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4698 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4699 else
617cf884 4700 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4701
b0e77b9c 4702 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4703
4704 /* pipesrc and dspsize control the size that is scaled from,
4705 * which should always be the user's requested size.
79e53945 4706 */
929c77fb
EA		 4707 I915_WRITE(DSPSIZE(plane),
4708 ((mode->vdisplay - 1) << 16) |
4709 (mode->hdisplay - 1));
4710 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4711
f564048e
EA		 4712 I915_WRITE(PIPECONF(pipe), pipeconf);
4713 POSTING_READ(PIPECONF(pipe));
929c77fb 4714 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4715
4716 intel_wait_for_vblank(dev, pipe);
4717
f564048e
EA		 4718 I915_WRITE(DSPCNTR(plane), dspcntr);
4719 POSTING_READ(DSPCNTR(plane));
4720
94352cf9 4721 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4722
4723 intel_update_watermarks(dev);
4724
f564048e
EA		 4725 return ret;
4726}
4727
9fb526db
KP		 4728/*
4729 * Initialize reference clocks when the driver loads
4730 */
4731void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4732{
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4734 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4735 struct intel_encoder *encoder;
13d83a67
JB		 4736 u32 temp;
4737 bool has_lvds = false;
199e5d79
KP		 4738 bool has_cpu_edp = false;
4739 bool has_pch_edp = false;
4740 bool has_panel = false;
99eb6a01
KP		 4741 bool has_ck505 = false;
4742 bool can_ssc = false;
13d83a67
JB		 4743
4744 /* We need to take the global config into account */
199e5d79
KP		 4745 list_for_each_entry(encoder, &mode_config->encoder_list,
4746 base.head) {
4747 switch (encoder->type) {
4748 case INTEL_OUTPUT_LVDS:
4749 has_panel = true;
4750 has_lvds = true;
4751 break;
4752 case INTEL_OUTPUT_EDP:
4753 has_panel = true;
4754 if (intel_encoder_is_pch_edp(&encoder->base))
4755 has_pch_edp = true;
4756 else
4757 has_cpu_edp = true;
4758 break;
13d83a67
JB		 4759 }
4760 }
4761
99eb6a01
KP		 4762 if (HAS_PCH_IBX(dev)) {
4763 has_ck505 = dev_priv->display_clock_mode;
4764 can_ssc = has_ck505;
4765 } else {
4766 has_ck505 = false;
4767 can_ssc = true;
4768 }
4769
4770 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4771 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4772 has_ck505);
13d83a67
JB		 4773
4774 /* Ironlake: try to setup display ref clock before DPLL
4775 * enabling. This is only under driver's control after
4776 * PCH B stepping, previous chipset stepping should be
4777 * ignoring this setting.
4778 */
4779 temp = I915_READ(PCH_DREF_CONTROL);
4780 /* Always enable nonspread source */
4781 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4782
99eb6a01
KP		 4783 if (has_ck505)
4784 temp |= DREF_NONSPREAD_CK505_ENABLE;
4785 else
4786 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4787
199e5d79
KP		 4788 if (has_panel) {
4789 temp &= ~DREF_SSC_SOURCE_MASK;
4790 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4791
199e5d79 4792 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4793 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4794 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4795 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4796 } else
4797 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4798
4799 /* Get SSC going before enabling the outputs */
4800 I915_WRITE(PCH_DREF_CONTROL, temp);
4801 POSTING_READ(PCH_DREF_CONTROL);
4802 udelay(200);
4803
13d83a67
JB		 4804 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4805
4806 /* Enable CPU source on CPU attached eDP */
199e5d79 4807 if (has_cpu_edp) {
99eb6a01 4808 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4809 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4810 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4811 }
13d83a67
JB		 4812 else
4813 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4814 } else
4815 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4816
4817 I915_WRITE(PCH_DREF_CONTROL, temp);
4818 POSTING_READ(PCH_DREF_CONTROL);
4819 udelay(200);
4820 } else {
4821 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4822
4823 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4824
4825 /* Turn off CPU output */
4826 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4827
4828 I915_WRITE(PCH_DREF_CONTROL, temp);
4829 POSTING_READ(PCH_DREF_CONTROL);
4830 udelay(200);
4831
4832 /* Turn off the SSC source */
4833 temp &= ~DREF_SSC_SOURCE_MASK;
4834 temp |= DREF_SSC_SOURCE_DISABLE;
4835
4836 /* Turn off SSC1 */
4837 temp &= ~ DREF_SSC1_ENABLE;
4838
13d83a67
JB		 4839 I915_WRITE(PCH_DREF_CONTROL, temp);
4840 POSTING_READ(PCH_DREF_CONTROL);
4841 udelay(200);
4842 }
4843}
4844
d9d444cb
JB		 4845static int ironlake_get_refclk(struct drm_crtc *crtc)
4846{
4847 struct drm_device *dev = crtc->dev;
4848 struct drm_i915_private *dev_priv = dev->dev_private;
4849 struct intel_encoder *encoder;
d9d444cb
JB		 4850 struct intel_encoder *edp_encoder = NULL;
4851 int num_connectors = 0;
4852 bool is_lvds = false;
4853
6c2b7c12 4854 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4855 switch (encoder->type) {
4856 case INTEL_OUTPUT_LVDS:
4857 is_lvds = true;
4858 break;
4859 case INTEL_OUTPUT_EDP:
4860 edp_encoder = encoder;
4861 break;
4862 }
4863 num_connectors++;
4864 }
4865
4866 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4867 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4868 dev_priv->lvds_ssc_freq);
4869 return dev_priv->lvds_ssc_freq * 1000;
4870 }
4871
4872 return 120000;
4873}
4874
c8203565 4875static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 4876 struct drm_display_mode *adjusted_mode,
c8203565 4877 bool dither)
79e53945 4878{
c8203565 4879 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 4880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4881 int pipe = intel_crtc->pipe;
c8203565
PZ		 4882 uint32_t val;
4883
4884 val = I915_READ(PIPECONF(pipe));
4885
4886 val &= ~PIPE_BPC_MASK;
4887 switch (intel_crtc->bpp) {
4888 case 18:
4889 val |= PIPE_6BPC;
4890 break;
4891 case 24:
4892 val |= PIPE_8BPC;
4893 break;
4894 case 30:
4895 val |= PIPE_10BPC;
4896 break;
4897 case 36:
4898 val |= PIPE_12BPC;
4899 break;
4900 default:
cc769b62
PZ		 4901 /* Case prevented by intel_choose_pipe_bpp_dither. */
4902 BUG();
c8203565
PZ		 4903 }
4904
4905 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4906 if (dither)
4907 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4908
4909 val &= ~PIPECONF_INTERLACE_MASK;
4910 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4911 val |= PIPECONF_INTERLACED_ILK;
4912 else
4913 val |= PIPECONF_PROGRESSIVE;
4914
4915 I915_WRITE(PIPECONF(pipe), val);
4916 POSTING_READ(PIPECONF(pipe));
4917}
4918
ee2b0b38
PZ		 4919static void haswell_set_pipeconf(struct drm_crtc *crtc,
4920 struct drm_display_mode *adjusted_mode,
4921 bool dither)
4922{
4923 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4924 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 4925 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 4926 uint32_t val;
4927
702e7a56 4928 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4929
4930 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4931 if (dither)
4932 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4933
4934 val &= ~PIPECONF_INTERLACE_MASK_HSW;
4935 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4936 val |= PIPECONF_INTERLACED_ILK;
4937 else
4938 val |= PIPECONF_PROGRESSIVE;
4939
702e7a56
PZ		 4940 I915_WRITE(PIPECONF(cpu_transcoder), val);
4941 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 4942}
4943
6591c6e4
PZ		 4944static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4945 struct drm_display_mode *adjusted_mode,
4946 intel_clock_t *clock,
4947 bool *has_reduced_clock,
4948 intel_clock_t *reduced_clock)
4949{
4950 struct drm_device *dev = crtc->dev;
4951 struct drm_i915_private *dev_priv = dev->dev_private;
4952 struct intel_encoder *intel_encoder;
4953 int refclk;
d4906093 4954 const intel_limit_t *limit;
6591c6e4 4955 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 4956
6591c6e4
PZ		 4957 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4958 switch (intel_encoder->type) {
79e53945
JB		 4959 case INTEL_OUTPUT_LVDS:
4960 is_lvds = true;
4961 break;
4962 case INTEL_OUTPUT_SDVO:
7d57382e 4963 case INTEL_OUTPUT_HDMI:
79e53945 4964 is_sdvo = true;
6591c6e4 4965 if (intel_encoder->needs_tv_clock)
e2f0ba97 4966 is_tv = true;
79e53945 4967 break;
79e53945
JB		 4968 case INTEL_OUTPUT_TVOUT:
4969 is_tv = true;
4970 break;
79e53945
JB		 4971 }
4972 }
4973
d9d444cb 4974 refclk = ironlake_get_refclk(crtc);
79e53945 4975
d4906093
ML		 4976 /*
4977 * Returns a set of divisors for the desired target clock with the given
4978 * refclk, or FALSE. The returned values represent the clock equation:
4979 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4980 */
1b894b59 4981 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 4982 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4983 clock);
4984 if (!ret)
4985 return false;
cda4b7d3 4986
ddc9003c 4987 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4988 /*
4989 * Ensure we match the reduced clock's P to the target clock.
4990 * If the clocks don't match, we can't switch the display clock
4991 * by using the FP0/FP1. In such case we will disable the LVDS
4992 * downclock feature.
4993 */
6591c6e4
PZ		 4994 *has_reduced_clock = limit->find_pll(limit, crtc,
4995 dev_priv->lvds_downclock,
4996 refclk,
4997 clock,
4998 reduced_clock);
652c393a 4999 }
61e9653f
DV		 5000
5001 if (is_sdvo && is_tv)
6591c6e4
PZ		 5002 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5003
5004 return true;
5005}
5006
01a415fd
DV		 5007static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5008{
5009 struct drm_i915_private *dev_priv = dev->dev_private;
5010 uint32_t temp;
5011
5012 temp = I915_READ(SOUTH_CHICKEN1);
5013 if (temp & FDI_BC_BIFURCATION_SELECT)
5014 return;
5015
5016 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5017 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5018
5019 temp |= FDI_BC_BIFURCATION_SELECT;
5020 DRM_DEBUG_KMS("enabling fdi C rx\n");
5021 I915_WRITE(SOUTH_CHICKEN1, temp);
5022 POSTING_READ(SOUTH_CHICKEN1);
5023}
5024
5025static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5026{
5027 struct drm_device *dev = intel_crtc->base.dev;
5028 struct drm_i915_private *dev_priv = dev->dev_private;
5029 struct intel_crtc *pipe_B_crtc =
5030 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5031
5032 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5033 intel_crtc->pipe, intel_crtc->fdi_lanes);
5034 if (intel_crtc->fdi_lanes > 4) {
5035 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5036 intel_crtc->pipe, intel_crtc->fdi_lanes);
5037 /* Clamp lanes to avoid programming the hw with bogus values. */
5038 intel_crtc->fdi_lanes = 4;
5039
5040 return false;
5041 }
5042
5043 if (dev_priv->num_pipe == 2)
5044 return true;
5045
5046 switch (intel_crtc->pipe) {
5047 case PIPE_A:
5048 return true;
5049 case PIPE_B:
5050 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5051 intel_crtc->fdi_lanes > 2) {
5052 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5053 intel_crtc->pipe, intel_crtc->fdi_lanes);
5054 /* Clamp lanes to avoid programming the hw with bogus values. */
5055 intel_crtc->fdi_lanes = 2;
5056
5057 return false;
5058 }
5059
5060 if (intel_crtc->fdi_lanes > 2)
5061 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5062 else
5063 cpt_enable_fdi_bc_bifurcation(dev);
5064
5065 return true;
5066 case PIPE_C:
5067 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5068 if (intel_crtc->fdi_lanes > 2) {
5069 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5070 intel_crtc->pipe, intel_crtc->fdi_lanes);
5071 /* Clamp lanes to avoid programming the hw with bogus values. */
5072 intel_crtc->fdi_lanes = 2;
5073
5074 return false;
5075 }
5076 } else {
5077 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5078 return false;
5079 }
5080
5081 cpt_enable_fdi_bc_bifurcation(dev);
5082
5083 return true;
5084 default:
5085 BUG();
5086 }
5087}
5088
f48d8f23
PZ		 5089static void ironlake_set_m_n(struct drm_crtc *crtc,
5090 struct drm_display_mode *mode,
5091 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5092{
5093 struct drm_device *dev = crtc->dev;
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5096 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5097 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
2c07245f 5098 struct fdi_m_n m_n = {0};
f48d8f23
PZ		 5099 int target_clock, pixel_multiplier, lane, link_bw;
5100 bool is_dp = false, is_cpu_edp = false;
79e53945 5101
f48d8f23
PZ		 5102 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5103 switch (intel_encoder->type) {
a4fc5ed6
KP		 5104 case INTEL_OUTPUT_DISPLAYPORT:
5105 is_dp = true;
5106 break;
32f9d658 5107 case INTEL_OUTPUT_EDP:
e3aef172 5108 is_dp = true;
f48d8f23 5109 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5110 is_cpu_edp = true;
f48d8f23 5111 edp_encoder = intel_encoder;
32f9d658 5112 break;
79e53945 5113 }
79e53945 5114 }
61e9653f 5115
2c07245f 5116 /* FDI link */
8febb297
EA		 5117 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5118 lane = 0;
5119 /* CPU eDP doesn't require FDI link, so just set DP M/N
5120 according to current link config */
e3aef172 5121 if (is_cpu_edp) {
e3aef172 5122 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5123 } else {
8febb297
EA		 5124 /* FDI is a binary signal running at ~2.7GHz, encoding
5125 * each output octet as 10 bits. The actual frequency
5126 * is stored as a divider into a 100MHz clock, and the
5127 * mode pixel clock is stored in units of 1KHz.
5128 * Hence the bw of each lane in terms of the mode signal
5129 * is:
5130 */
5131 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5132 }
58a27471 5133
94bf2ced
DV		 5134 /* [e]DP over FDI requires target mode clock instead of link clock. */
5135 if (edp_encoder)
5136 target_clock = intel_edp_target_clock(edp_encoder, mode);
5137 else if (is_dp)
5138 target_clock = mode->clock;
5139 else
5140 target_clock = adjusted_mode->clock;
5141
8febb297
EA		 5142 if (!lane) {
5143 /*
5144 * Account for spread spectrum to avoid
5145 * oversubscribing the link. Max center spread
5146 * is 2.5%; use 5% for safety's sake.
5147 */
5a354204 5148 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5149 lane = bps / (link_bw * 8) + 1;
5eb08b69 5150 }
2c07245f 5151
8febb297
EA		 5152 intel_crtc->fdi_lanes = lane;
5153
5154 if (pixel_multiplier > 1)
5155 link_bw *= pixel_multiplier;
5a354204
JB		 5156 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5157 &m_n);
8febb297 5158
afe2fcf5
PZ		 5159 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5160 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5161 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5162 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5163}
5164
de13a2e3
PZ		 5165static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5166 struct drm_display_mode *adjusted_mode,
5167 intel_clock_t *clock, u32 fp)
79e53945 5168{
de13a2e3 5169 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5170 struct drm_device *dev = crtc->dev;
5171 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5172 struct intel_encoder *intel_encoder;
5173 uint32_t dpll;
5174 int factor, pixel_multiplier, num_connectors = 0;
5175 bool is_lvds = false, is_sdvo = false, is_tv = false;
5176 bool is_dp = false, is_cpu_edp = false;
79e53945 5177
de13a2e3
PZ		 5178 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5179 switch (intel_encoder->type) {
79e53945
JB		 5180 case INTEL_OUTPUT_LVDS:
5181 is_lvds = true;
5182 break;
5183 case INTEL_OUTPUT_SDVO:
7d57382e 5184 case INTEL_OUTPUT_HDMI:
79e53945 5185 is_sdvo = true;
de13a2e3 5186 if (intel_encoder->needs_tv_clock)
e2f0ba97 5187 is_tv = true;
79e53945 5188 break;
79e53945
JB		 5189 case INTEL_OUTPUT_TVOUT:
5190 is_tv = true;
5191 break;
a4fc5ed6
KP		 5192 case INTEL_OUTPUT_DISPLAYPORT:
5193 is_dp = true;
5194 break;
32f9d658 5195 case INTEL_OUTPUT_EDP:
e3aef172 5196 is_dp = true;
de13a2e3 5197 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5198 is_cpu_edp = true;
32f9d658 5199 break;
79e53945 5200 }
43565a06 5201
c751ce4f 5202 num_connectors++;
79e53945 5203 }
79e53945 5204
c1858123 5205 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5206 factor = 21;
5207 if (is_lvds) {
5208 if ((intel_panel_use_ssc(dev_priv) &&
5209 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5210 intel_is_dual_link_lvds(dev))
8febb297
EA		 5211 factor = 25;
5212 } else if (is_sdvo && is_tv)
5213 factor = 20;
c1858123 5214
de13a2e3 5215 if (clock->m < factor * clock->n)
8febb297 5216 fp |= FP_CB_TUNE;
2c07245f 5217
5eddb70b 5218 dpll = 0;
2c07245f 5219
a07d6787
EA		 5220 if (is_lvds)
5221 dpll |= DPLLB_MODE_LVDS;
5222 else
5223 dpll |= DPLLB_MODE_DAC_SERIAL;
5224 if (is_sdvo) {
de13a2e3 5225 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5226 if (pixel_multiplier > 1) {
5227 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5228 }
a07d6787
EA		 5229 dpll |= DPLL_DVO_HIGH_SPEED;
5230 }
e3aef172 5231 if (is_dp && !is_cpu_edp)
a07d6787 5232 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5233
a07d6787 5234 /* compute bitmask from p1 value */
de13a2e3 5235 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5236 /* also FPA1 */
de13a2e3 5237 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5238
de13a2e3 5239 switch (clock->p2) {
a07d6787
EA		 5240 case 5:
5241 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5242 break;
5243 case 7:
5244 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5245 break;
5246 case 10:
5247 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5248 break;
5249 case 14:
5250 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5251 break;
79e53945
JB		 5252 }
5253
43565a06
KH		 5254 if (is_sdvo && is_tv)
5255 dpll |= PLL_REF_INPUT_TVCLKINBC;
5256 else if (is_tv)
79e53945 5257 /* XXX: just matching BIOS for now */
43565a06 5258 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5259 dpll |= 3;
a7615030 5260 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5261 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5262 else
5263 dpll |= PLL_REF_INPUT_DREFCLK;
5264
de13a2e3
PZ		 5265 return dpll;
5266}
5267
5268static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5269 struct drm_display_mode *mode,
5270 struct drm_display_mode *adjusted_mode,
5271 int x, int y,
5272 struct drm_framebuffer *fb)
5273{
5274 struct drm_device *dev = crtc->dev;
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5277 int pipe = intel_crtc->pipe;
5278 int plane = intel_crtc->plane;
5279 int num_connectors = 0;
5280 intel_clock_t clock, reduced_clock;
5281 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5282 bool ok, has_reduced_clock = false;
5283 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5284 struct intel_encoder *encoder;
de13a2e3 5285 int ret;
01a415fd 5286 bool dither, fdi_config_ok;
de13a2e3
PZ		 5287
5288 for_each_encoder_on_crtc(dev, crtc, encoder) {
5289 switch (encoder->type) {
5290 case INTEL_OUTPUT_LVDS:
5291 is_lvds = true;
5292 break;
de13a2e3
PZ		 5293 case INTEL_OUTPUT_DISPLAYPORT:
5294 is_dp = true;
5295 break;
5296 case INTEL_OUTPUT_EDP:
5297 is_dp = true;
e2f12b07 5298 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5299 is_cpu_edp = true;
5300 break;
5301 }
5302
5303 num_connectors++;
a07d6787 5304 }
79e53945 5305
5dc5298b
PZ		 5306 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5307 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5308
de13a2e3
PZ		 5309 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5310 &has_reduced_clock, &reduced_clock);
5311 if (!ok) {
5312 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5313 return -EINVAL;
79e53945
JB		 5314 }
5315
de13a2e3
PZ		 5316 /* Ensure that the cursor is valid for the new mode before changing... */
5317 intel_crtc_update_cursor(crtc, true);
5318
5319 /* determine panel color depth */
c8241969
JN		 5320 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5321 adjusted_mode);
de13a2e3
PZ		 5322 if (is_lvds && dev_priv->lvds_dither)
5323 dither = true;
5324
5325 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5326 if (has_reduced_clock)
5327 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5328 reduced_clock.m2;
5329
5330 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5331
f7cb34d4 5332 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5333 drm_mode_debug_printmodeline(mode);
5334
5dc5298b
PZ		 5335 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5336 if (!is_cpu_edp) {
ee7b9f93 5337 struct intel_pch_pll *pll;
4b645f14 5338
ee7b9f93
JB		 5339 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5340 if (pll == NULL) {
5341 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5342 pipe);
4b645f14
JB		 5343 return -EINVAL;
5344 }
ee7b9f93
JB		 5345 } else
5346 intel_put_pch_pll(intel_crtc);
79e53945 5347
2f0c2ad1 5348 if (is_dp && !is_cpu_edp)
a4fc5ed6 5349 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5350
dafd226c
DV		 5351 for_each_encoder_on_crtc(dev, crtc, encoder)
5352 if (encoder->pre_pll_enable)
5353 encoder->pre_pll_enable(encoder);
5354
ee7b9f93
JB		 5355 if (intel_crtc->pch_pll) {
5356 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5357
32f9d658 5358 /* Wait for the clocks to stabilize. */
ee7b9f93 5359 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5360 udelay(150);
5361
8febb297
EA		 5362 /* The pixel multiplier can only be updated once the
5363 * DPLL is enabled and the clocks are stable.
5364 *
5365 * So write it again.
5366 */
ee7b9f93 5367 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5368 }
79e53945 5369
5eddb70b 5370 intel_crtc->lowfreq_avail = false;
ee7b9f93 5371 if (intel_crtc->pch_pll) {
4b645f14 5372 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5373 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5374 intel_crtc->lowfreq_avail = true;
4b645f14 5375 } else {
ee7b9f93 5376 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5377 }
5378 }
5379
b0e77b9c 5380 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5381
01a415fd
DV		 5382 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5383 * ironlake_check_fdi_lanes. */
f48d8f23 5384 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5385
01a415fd 5386 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5387
c8203565 5388 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5389
9d0498a2 5390 intel_wait_for_vblank(dev, pipe);
79e53945 5391
a1f9e77e
PZ		 5392 /* Set up the display plane register */
5393 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5394 POSTING_READ(DSPCNTR(plane));
79e53945 5395
94352cf9 5396 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5397
5398 intel_update_watermarks(dev);
5399
1f8eeabf
ED		 5400 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5401
01a415fd 5402 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5403}
5404
09b4ddf9
PZ		 5405static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5406 struct drm_display_mode *mode,
5407 struct drm_display_mode *adjusted_mode,
5408 int x, int y,
5409 struct drm_framebuffer *fb)
5410{
5411 struct drm_device *dev = crtc->dev;
5412 struct drm_i915_private *dev_priv = dev->dev_private;
5413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5414 int pipe = intel_crtc->pipe;
5415 int plane = intel_crtc->plane;
5416 int num_connectors = 0;
ed7ef439 5417 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5418 struct intel_encoder *encoder;
09b4ddf9
PZ		 5419 int ret;
5420 bool dither;
5421
5422 for_each_encoder_on_crtc(dev, crtc, encoder) {
5423 switch (encoder->type) {
09b4ddf9
PZ		 5424 case INTEL_OUTPUT_DISPLAYPORT:
5425 is_dp = true;
5426 break;
5427 case INTEL_OUTPUT_EDP:
5428 is_dp = true;
5429 if (!intel_encoder_is_pch_edp(&encoder->base))
5430 is_cpu_edp = true;
5431 break;
5432 }
5433
5434 num_connectors++;
5435 }
5436
a5c961d1
PZ		 5437 if (is_cpu_edp)
5438 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5439 else
5440 intel_crtc->cpu_transcoder = pipe;
5441
5dc5298b
PZ		 5442 /* We are not sure yet this won't happen. */
5443 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5444 INTEL_PCH_TYPE(dev));
5445
5446 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5447 num_connectors, pipe_name(pipe));
5448
702e7a56 5449 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5450 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5451
5452 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5453
6441ab5f
PZ		 5454 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5455 return -EINVAL;
5456
09b4ddf9
PZ		 5457 /* Ensure that the cursor is valid for the new mode before changing... */
5458 intel_crtc_update_cursor(crtc, true);
5459
5460 /* determine panel color depth */
c8241969
JN		 5461 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5462 adjusted_mode);
09b4ddf9 5463
09b4ddf9
PZ		 5464 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5465 drm_mode_debug_printmodeline(mode);
5466
ed7ef439 5467 if (is_dp && !is_cpu_edp)
09b4ddf9 5468 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5469
5470 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5471
5472 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5473
1eb8dfec
PZ		 5474 if (!is_dp || is_cpu_edp)
5475 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5476
ee2b0b38 5477 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5478
09b4ddf9
PZ		 5479 /* Set up the display plane register */
5480 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5481 POSTING_READ(DSPCNTR(plane));
5482
5483 ret = intel_pipe_set_base(crtc, x, y, fb);
5484
5485 intel_update_watermarks(dev);
5486
5487 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5488
1f803ee5 5489 return ret;
79e53945
JB		 5490}
5491
f564048e
EA		 5492static int intel_crtc_mode_set(struct drm_crtc *crtc,
5493 struct drm_display_mode *mode,
5494 struct drm_display_mode *adjusted_mode,
5495 int x, int y,
94352cf9 5496 struct drm_framebuffer *fb)
f564048e
EA		 5497{
5498 struct drm_device *dev = crtc->dev;
5499 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5500 struct drm_encoder_helper_funcs *encoder_funcs;
5501 struct intel_encoder *encoder;
0b701d27
EA		 5502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5503 int pipe = intel_crtc->pipe;
f564048e
EA		 5504 int ret;
5505
0b701d27 5506 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5507
f564048e 5508 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5509 x, y, fb);
79e53945 5510 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5511
9256aa19
DV		 5512 if (ret != 0)
5513 return ret;
5514
5515 for_each_encoder_on_crtc(dev, crtc, encoder) {
5516 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5517 encoder->base.base.id,
5518 drm_get_encoder_name(&encoder->base),
5519 mode->base.id, mode->name);
5520 encoder_funcs = encoder->base.helper_private;
5521 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5522 }
5523
5524 return 0;
79e53945
JB		 5525}
5526
3a9627f4
WF		 5527static bool intel_eld_uptodate(struct drm_connector *connector,
5528 int reg_eldv, uint32_t bits_eldv,
5529 int reg_elda, uint32_t bits_elda,
5530 int reg_edid)
5531{
5532 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5533 uint8_t *eld = connector->eld;
5534 uint32_t i;
5535
5536 i = I915_READ(reg_eldv);
5537 i &= bits_eldv;
5538
5539 if (!eld[0])
5540 return !i;
5541
5542 if (!i)
5543 return false;
5544
5545 i = I915_READ(reg_elda);
5546 i &= ~bits_elda;
5547 I915_WRITE(reg_elda, i);
5548
5549 for (i = 0; i < eld[2]; i++)
5550 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5551 return false;
5552
5553 return true;
5554}
5555
e0dac65e
WF		 5556static void g4x_write_eld(struct drm_connector *connector,
5557 struct drm_crtc *crtc)
5558{
5559 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5560 uint8_t *eld = connector->eld;
5561 uint32_t eldv;
5562 uint32_t len;
5563 uint32_t i;
5564
5565 i = I915_READ(G4X_AUD_VID_DID);
5566
5567 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5568 eldv = G4X_ELDV_DEVCL_DEVBLC;
5569 else
5570 eldv = G4X_ELDV_DEVCTG;
5571
3a9627f4
WF		 5572 if (intel_eld_uptodate(connector,
5573 G4X_AUD_CNTL_ST, eldv,
5574 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5575 G4X_HDMIW_HDMIEDID))
5576 return;
5577
e0dac65e
WF		 5578 i = I915_READ(G4X_AUD_CNTL_ST);
5579 i &= ~(eldv | G4X_ELD_ADDR);
5580 len = (i >> 9) & 0x1f; /* ELD buffer size */
5581 I915_WRITE(G4X_AUD_CNTL_ST, i);
5582
5583 if (!eld[0])
5584 return;
5585
5586 len = min_t(uint8_t, eld[2], len);
5587 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5588 for (i = 0; i < len; i++)
5589 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5590
5591 i = I915_READ(G4X_AUD_CNTL_ST);
5592 i |= eldv;
5593 I915_WRITE(G4X_AUD_CNTL_ST, i);
5594}
5595
83358c85
WX		 5596static void haswell_write_eld(struct drm_connector *connector,
5597 struct drm_crtc *crtc)
5598{
5599 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5600 uint8_t *eld = connector->eld;
5601 struct drm_device *dev = crtc->dev;
5602 uint32_t eldv;
5603 uint32_t i;
5604 int len;
5605 int pipe = to_intel_crtc(crtc)->pipe;
5606 int tmp;
5607
5608 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5609 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5610 int aud_config = HSW_AUD_CFG(pipe);
5611 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5612
5613
5614 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5615
5616 /* Audio output enable */
5617 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5618 tmp = I915_READ(aud_cntrl_st2);
5619 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5620 I915_WRITE(aud_cntrl_st2, tmp);
5621
5622 /* Wait for 1 vertical blank */
5623 intel_wait_for_vblank(dev, pipe);
5624
5625 /* Set ELD valid state */
5626 tmp = I915_READ(aud_cntrl_st2);
5627 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5628 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5629 I915_WRITE(aud_cntrl_st2, tmp);
5630 tmp = I915_READ(aud_cntrl_st2);
5631 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5632
5633 /* Enable HDMI mode */
5634 tmp = I915_READ(aud_config);
5635 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5636 /* clear N_programing_enable and N_value_index */
5637 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5638 I915_WRITE(aud_config, tmp);
5639
5640 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5641
5642 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5643
5644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5645 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5646 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5647 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5648 } else
5649 I915_WRITE(aud_config, 0);
5650
5651 if (intel_eld_uptodate(connector,
5652 aud_cntrl_st2, eldv,
5653 aud_cntl_st, IBX_ELD_ADDRESS,
5654 hdmiw_hdmiedid))
5655 return;
5656
5657 i = I915_READ(aud_cntrl_st2);
5658 i &= ~eldv;
5659 I915_WRITE(aud_cntrl_st2, i);
5660
5661 if (!eld[0])
5662 return;
5663
5664 i = I915_READ(aud_cntl_st);
5665 i &= ~IBX_ELD_ADDRESS;
5666 I915_WRITE(aud_cntl_st, i);
5667 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5668 DRM_DEBUG_DRIVER("port num:%d\n", i);
5669
5670 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5671 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5672 for (i = 0; i < len; i++)
5673 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5674
5675 i = I915_READ(aud_cntrl_st2);
5676 i |= eldv;
5677 I915_WRITE(aud_cntrl_st2, i);
5678
5679}
5680
e0dac65e
WF		 5681static void ironlake_write_eld(struct drm_connector *connector,
5682 struct drm_crtc *crtc)
5683{
5684 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5685 uint8_t *eld = connector->eld;
5686 uint32_t eldv;
5687 uint32_t i;
5688 int len;
5689 int hdmiw_hdmiedid;
b6daa025 5690 int aud_config;
e0dac65e
WF		 5691 int aud_cntl_st;
5692 int aud_cntrl_st2;
9b138a83 5693 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5694
b3f33cbf 5695 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5696 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5697 aud_config = IBX_AUD_CFG(pipe);
5698 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5699 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5700 } else {
9b138a83
WX		 5701 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5702 aud_config = CPT_AUD_CFG(pipe);
5703 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5704 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5705 }
5706
9b138a83 5707 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5708
5709 i = I915_READ(aud_cntl_st);
9b138a83 5710 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5711 if (!i) {
5712 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5713 /* operate blindly on all ports */
1202b4c6
WF		 5714 eldv = IBX_ELD_VALIDB;
5715 eldv |= IBX_ELD_VALIDB << 4;
5716 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5717 } else {
5718 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5719 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5720 }
5721
3a9627f4
WF		 5722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5723 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5724 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5725 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5726 } else
5727 I915_WRITE(aud_config, 0);
e0dac65e 5728
3a9627f4
WF		 5729 if (intel_eld_uptodate(connector,
5730 aud_cntrl_st2, eldv,
5731 aud_cntl_st, IBX_ELD_ADDRESS,
5732 hdmiw_hdmiedid))
5733 return;
5734
e0dac65e
WF		 5735 i = I915_READ(aud_cntrl_st2);
5736 i &= ~eldv;
5737 I915_WRITE(aud_cntrl_st2, i);
5738
5739 if (!eld[0])
5740 return;
5741
e0dac65e 5742 i = I915_READ(aud_cntl_st);
1202b4c6 5743 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5744 I915_WRITE(aud_cntl_st, i);
5745
5746 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5747 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5748 for (i = 0; i < len; i++)
5749 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5750
5751 i = I915_READ(aud_cntrl_st2);
5752 i |= eldv;
5753 I915_WRITE(aud_cntrl_st2, i);
5754}
5755
5756void intel_write_eld(struct drm_encoder *encoder,
5757 struct drm_display_mode *mode)
5758{
5759 struct drm_crtc *crtc = encoder->crtc;
5760 struct drm_connector *connector;
5761 struct drm_device *dev = encoder->dev;
5762 struct drm_i915_private *dev_priv = dev->dev_private;
5763
5764 connector = drm_select_eld(encoder, mode);
5765 if (!connector)
5766 return;
5767
5768 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5769 connector->base.id,
5770 drm_get_connector_name(connector),
5771 connector->encoder->base.id,
5772 drm_get_encoder_name(connector->encoder));
5773
5774 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5775
5776 if (dev_priv->display.write_eld)
5777 dev_priv->display.write_eld(connector, crtc);
5778}
5779
79e53945
JB		 5780/** Loads the palette/gamma unit for the CRTC with the prepared values */
5781void intel_crtc_load_lut(struct drm_crtc *crtc)
5782{
5783 struct drm_device *dev = crtc->dev;
5784 struct drm_i915_private *dev_priv = dev->dev_private;
5785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5786 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5787 int i;
5788
5789 /* The clocks have to be on to load the palette. */
aed3f09d 5790 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5791 return;
5792
f2b115e6 5793 /* use legacy palette for Ironlake */
bad720ff 5794 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5795 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5796
79e53945
JB		 5797 for (i = 0; i < 256; i++) {
5798 I915_WRITE(palreg + 4 * i,
5799 (intel_crtc->lut_r[i] << 16) |
5800 (intel_crtc->lut_g[i] << 8) |
5801 intel_crtc->lut_b[i]);
5802 }
5803}
5804
560b85bb
CW		 5805static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5806{
5807 struct drm_device *dev = crtc->dev;
5808 struct drm_i915_private *dev_priv = dev->dev_private;
5809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5810 bool visible = base != 0;
5811 u32 cntl;
5812
5813 if (intel_crtc->cursor_visible == visible)
5814 return;
5815
9db4a9c7 5816 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5817 if (visible) {
5818 /* On these chipsets we can only modify the base whilst
5819 * the cursor is disabled.
5820 */
9db4a9c7 5821 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5822
5823 cntl &= ~(CURSOR_FORMAT_MASK);
5824 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5825 cntl |= CURSOR_ENABLE |
5826 CURSOR_GAMMA_ENABLE |
5827 CURSOR_FORMAT_ARGB;
5828 } else
5829 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5830 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5831
5832 intel_crtc->cursor_visible = visible;
5833}
5834
5835static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5836{
5837 struct drm_device *dev = crtc->dev;
5838 struct drm_i915_private *dev_priv = dev->dev_private;
5839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5840 int pipe = intel_crtc->pipe;
5841 bool visible = base != 0;
5842
5843 if (intel_crtc->cursor_visible != visible) {
548f245b 5844 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5845 if (base) {
5846 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5847 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5848 cntl |= pipe << 28; /* Connect to correct pipe */
5849 } else {
5850 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5851 cntl |= CURSOR_MODE_DISABLE;
5852 }
9db4a9c7 5853 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5854
5855 intel_crtc->cursor_visible = visible;
5856 }
5857 /* and commit changes on next vblank */
9db4a9c7 5858 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5859}
5860
65a21cd6
JB		 5861static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5862{
5863 struct drm_device *dev = crtc->dev;
5864 struct drm_i915_private *dev_priv = dev->dev_private;
5865 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5866 int pipe = intel_crtc->pipe;
5867 bool visible = base != 0;
5868
5869 if (intel_crtc->cursor_visible != visible) {
5870 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5871 if (base) {
5872 cntl &= ~CURSOR_MODE;
5873 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5874 } else {
5875 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5876 cntl |= CURSOR_MODE_DISABLE;
5877 }
5878 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5879
5880 intel_crtc->cursor_visible = visible;
5881 }
5882 /* and commit changes on next vblank */
5883 I915_WRITE(CURBASE_IVB(pipe), base);
5884}
5885
cda4b7d3 5886/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5887static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5888 bool on)
cda4b7d3
CW		 5889{
5890 struct drm_device *dev = crtc->dev;
5891 struct drm_i915_private *dev_priv = dev->dev_private;
5892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5893 int pipe = intel_crtc->pipe;
5894 int x = intel_crtc->cursor_x;
5895 int y = intel_crtc->cursor_y;
560b85bb 5896 u32 base, pos;
cda4b7d3
CW		 5897 bool visible;
5898
5899 pos = 0;
5900
6b383a7f 5901 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5902 base = intel_crtc->cursor_addr;
5903 if (x > (int) crtc->fb->width)
5904 base = 0;
5905
5906 if (y > (int) crtc->fb->height)
5907 base = 0;
5908 } else
5909 base = 0;
5910
5911 if (x < 0) {
5912 if (x + intel_crtc->cursor_width < 0)
5913 base = 0;
5914
5915 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5916 x = -x;
5917 }
5918 pos |= x << CURSOR_X_SHIFT;
5919
5920 if (y < 0) {
5921 if (y + intel_crtc->cursor_height < 0)
5922 base = 0;
5923
5924 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5925 y = -y;
5926 }
5927 pos |= y << CURSOR_Y_SHIFT;
5928
5929 visible = base != 0;
560b85bb 5930 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5931 return;
5932
0cd83aa9 5933 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5934 I915_WRITE(CURPOS_IVB(pipe), pos);
5935 ivb_update_cursor(crtc, base);
5936 } else {
5937 I915_WRITE(CURPOS(pipe), pos);
5938 if (IS_845G(dev) || IS_I865G(dev))
5939 i845_update_cursor(crtc, base);
5940 else
5941 i9xx_update_cursor(crtc, base);
5942 }
cda4b7d3
CW		 5943}
5944
79e53945 5945static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5946 struct drm_file *file,
79e53945
JB		 5947 uint32_t handle,
5948 uint32_t width, uint32_t height)
5949{
5950 struct drm_device *dev = crtc->dev;
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5953 struct drm_i915_gem_object *obj;
cda4b7d3 5954 uint32_t addr;
3f8bc370 5955 int ret;
79e53945 5956
79e53945
JB		 5957 /* if we want to turn off the cursor ignore width and height */
5958 if (!handle) {
28c97730 5959 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5960 addr = 0;
05394f39 5961 obj = NULL;
5004417d 5962 mutex_lock(&dev->struct_mutex);
3f8bc370 5963 goto finish;
79e53945
JB		 5964 }
5965
5966 /* Currently we only support 64x64 cursors */
5967 if (width != 64 || height != 64) {
5968 DRM_ERROR("we currently only support 64x64 cursors\n");
5969 return -EINVAL;
5970 }
5971
05394f39 5972 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5973 if (&obj->base == NULL)
79e53945
JB		 5974 return -ENOENT;
5975
05394f39 5976 if (obj->base.size < width * height * 4) {
79e53945 5977 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5978 ret = -ENOMEM;
5979 goto fail;
79e53945
JB		 5980 }
5981
71acb5eb 5982 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5983 mutex_lock(&dev->struct_mutex);
b295d1b6 5984 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5985 if (obj->tiling_mode) {
5986 DRM_ERROR("cursor cannot be tiled\n");
5987 ret = -EINVAL;
5988 goto fail_locked;
5989 }
5990
2da3b9b9 5991 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5992 if (ret) {
5993 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5994 goto fail_locked;
e7b526bb
CW		 5995 }
5996
d9e86c0e
CW		 5997 ret = i915_gem_object_put_fence(obj);
5998 if (ret) {
2da3b9b9 5999 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6000 goto fail_unpin;
6001 }
6002
05394f39 6003 addr = obj->gtt_offset;
71acb5eb 6004 } else {
6eeefaf3 6005 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6006 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6007 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6008 align);
71acb5eb
DA		 6009 if (ret) {
6010 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6011 goto fail_locked;
71acb5eb 6012 }
05394f39 6013 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6014 }
6015
a6c45cf0 6016 if (IS_GEN2(dev))
14b60391
JB		 6017 I915_WRITE(CURSIZE, (height << 12) | width);
6018
3f8bc370 6019 finish:
3f8bc370 6020 if (intel_crtc->cursor_bo) {
b295d1b6 6021 if (dev_priv->info->cursor_needs_physical) {
05394f39 6022 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6023 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6024 } else
6025 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6026 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6027 }
80824003 6028
7f9872e0 6029 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6030
6031 intel_crtc->cursor_addr = addr;
05394f39 6032 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6033 intel_crtc->cursor_width = width;
6034 intel_crtc->cursor_height = height;
6035
6b383a7f 6036 intel_crtc_update_cursor(crtc, true);
3f8bc370 6037
79e53945 6038 return 0;
e7b526bb 6039fail_unpin:
05394f39 6040 i915_gem_object_unpin(obj);
7f9872e0 6041fail_locked:
34b8686e 6042 mutex_unlock(&dev->struct_mutex);
bc9025bd 6043fail:
05394f39 6044 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6045 return ret;
79e53945
JB		 6046}
6047
6048static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6049{
79e53945 6050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6051
cda4b7d3
CW		 6052 intel_crtc->cursor_x = x;
6053 intel_crtc->cursor_y = y;
652c393a 6054
6b383a7f 6055 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6056
6057 return 0;
6058}
6059
6060/** Sets the color ramps on behalf of RandR */
6061void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6062 u16 blue, int regno)
6063{
6064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6065
6066 intel_crtc->lut_r[regno] = red >> 8;
6067 intel_crtc->lut_g[regno] = green >> 8;
6068 intel_crtc->lut_b[regno] = blue >> 8;
6069}
6070
b8c00ac5
DA		 6071void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6072 u16 *blue, int regno)
6073{
6074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6075
6076 *red = intel_crtc->lut_r[regno] << 8;
6077 *green = intel_crtc->lut_g[regno] << 8;
6078 *blue = intel_crtc->lut_b[regno] << 8;
6079}
6080
79e53945 6081static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6082 u16 *blue, uint32_t start, uint32_t size)
79e53945 6083{
7203425a 6084 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6086
7203425a 6087 for (i = start; i < end; i++) {
79e53945
JB		 6088 intel_crtc->lut_r[i] = red[i] >> 8;
6089 intel_crtc->lut_g[i] = green[i] >> 8;
6090 intel_crtc->lut_b[i] = blue[i] >> 8;
6091 }
6092
6093 intel_crtc_load_lut(crtc);
6094}
6095
6096/**
6097 * Get a pipe with a simple mode set on it for doing load-based monitor
6098 * detection.
6099 *
6100 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6101 * its requirements. The pipe will be connected to no other encoders.
79e53945 6102 *
c751ce4f 6103 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6104 * configured for it. In the future, it could choose to temporarily disable
6105 * some outputs to free up a pipe for its use.
6106 *
6107 * \return crtc, or NULL if no pipes are available.
6108 */
6109
6110/* VESA 640x480x72Hz mode to set on the pipe */
6111static struct drm_display_mode load_detect_mode = {
6112 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6113 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6114};
6115
d2dff872
CW		 6116static struct drm_framebuffer *
6117intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6118 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6119 struct drm_i915_gem_object *obj)
6120{
6121 struct intel_framebuffer *intel_fb;
6122 int ret;
6123
6124 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6125 if (!intel_fb) {
6126 drm_gem_object_unreference_unlocked(&obj->base);
6127 return ERR_PTR(-ENOMEM);
6128 }
6129
6130 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6131 if (ret) {
6132 drm_gem_object_unreference_unlocked(&obj->base);
6133 kfree(intel_fb);
6134 return ERR_PTR(ret);
6135 }
6136
6137 return &intel_fb->base;
6138}
6139
6140static u32
6141intel_framebuffer_pitch_for_width(int width, int bpp)
6142{
6143 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6144 return ALIGN(pitch, 64);
6145}
6146
6147static u32
6148intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6149{
6150 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6151 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6152}
6153
6154static struct drm_framebuffer *
6155intel_framebuffer_create_for_mode(struct drm_device *dev,
6156 struct drm_display_mode *mode,
6157 int depth, int bpp)
6158{
6159 struct drm_i915_gem_object *obj;
0fed39bd 6160 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6161
6162 obj = i915_gem_alloc_object(dev,
6163 intel_framebuffer_size_for_mode(mode, bpp));
6164 if (obj == NULL)
6165 return ERR_PTR(-ENOMEM);
6166
6167 mode_cmd.width = mode->hdisplay;
6168 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6169 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6170 bpp);
5ca0c34a 6171 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6172
6173 return intel_framebuffer_create(dev, &mode_cmd, obj);
6174}
6175
6176static struct drm_framebuffer *
6177mode_fits_in_fbdev(struct drm_device *dev,
6178 struct drm_display_mode *mode)
6179{
6180 struct drm_i915_private *dev_priv = dev->dev_private;
6181 struct drm_i915_gem_object *obj;
6182 struct drm_framebuffer *fb;
6183
6184 if (dev_priv->fbdev == NULL)
6185 return NULL;
6186
6187 obj = dev_priv->fbdev->ifb.obj;
6188 if (obj == NULL)
6189 return NULL;
6190
6191 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6192 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6193 fb->bits_per_pixel))
d2dff872
CW		 6194 return NULL;
6195
01f2c773 6196 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6197 return NULL;
6198
6199 return fb;
6200}
6201
d2434ab7 6202bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6203 struct drm_display_mode *mode,
8261b191 6204 struct intel_load_detect_pipe *old)
79e53945
JB		 6205{
6206 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6207 struct intel_encoder *intel_encoder =
6208 intel_attached_encoder(connector);
79e53945 6209 struct drm_crtc *possible_crtc;
4ef69c7a 6210 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6211 struct drm_crtc *crtc = NULL;
6212 struct drm_device *dev = encoder->dev;
94352cf9 6213 struct drm_framebuffer *fb;
79e53945
JB		 6214 int i = -1;
6215
d2dff872
CW		 6216 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6217 connector->base.id, drm_get_connector_name(connector),
6218 encoder->base.id, drm_get_encoder_name(encoder));
6219
79e53945
JB		 6220 /*
6221 * Algorithm gets a little messy:
7a5e4805 6222 *
79e53945
JB		 6223 * - if the connector already has an assigned crtc, use it (but make
6224 * sure it's on first)
7a5e4805 6225 *
79e53945
JB		 6226 * - try to find the first unused crtc that can drive this connector,
6227 * and use that if we find one
79e53945
JB		 6228 */
6229
6230 /* See if we already have a CRTC for this connector */
6231 if (encoder->crtc) {
6232 crtc = encoder->crtc;
8261b191 6233
24218aac 6234 old->dpms_mode = connector->dpms;
8261b191
CW		 6235 old->load_detect_temp = false;
6236
6237 /* Make sure the crtc and connector are running */
24218aac
DV		 6238 if (connector->dpms != DRM_MODE_DPMS_ON)
6239 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6240
7173188d 6241 return true;
79e53945
JB		 6242 }
6243
6244 /* Find an unused one (if possible) */
6245 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6246 i++;
6247 if (!(encoder->possible_crtcs & (1 << i)))
6248 continue;
6249 if (!possible_crtc->enabled) {
6250 crtc = possible_crtc;
6251 break;
6252 }
79e53945
JB		 6253 }
6254
6255 /*
6256 * If we didn't find an unused CRTC, don't use any.
6257 */
6258 if (!crtc) {
7173188d
CW		 6259 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6260 return false;
79e53945
JB		 6261 }
6262
fc303101
DV		 6263 intel_encoder->new_crtc = to_intel_crtc(crtc);
6264 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6265
6266 intel_crtc = to_intel_crtc(crtc);
24218aac 6267 old->dpms_mode = connector->dpms;
8261b191 6268 old->load_detect_temp = true;
d2dff872 6269 old->release_fb = NULL;
79e53945 6270
6492711d
CW		 6271 if (!mode)
6272 mode = &load_detect_mode;
79e53945 6273
d2dff872
CW		 6274 /* We need a framebuffer large enough to accommodate all accesses
6275 * that the plane may generate whilst we perform load detection.
6276 * We can not rely on the fbcon either being present (we get called
6277 * during its initialisation to detect all boot displays, or it may
6278 * not even exist) or that it is large enough to satisfy the
6279 * requested mode.
6280 */
94352cf9
DV		 6281 fb = mode_fits_in_fbdev(dev, mode);
6282 if (fb == NULL) {
d2dff872 6283 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6284 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6285 old->release_fb = fb;
d2dff872
CW		 6286 } else
6287 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6288 if (IS_ERR(fb)) {
d2dff872 6289 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
0e8b3d3e 6290 return false;
79e53945 6291 }
79e53945 6292
94352cf9 6293 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6294 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6295 if (old->release_fb)
6296 old->release_fb->funcs->destroy(old->release_fb);
0e8b3d3e 6297 return false;
79e53945 6298 }
7173188d 6299
79e53945 6300 /* let the connector get through one full cycle before testing */
9d0498a2 6301 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6302 return true;
79e53945
JB		 6303}
6304
d2434ab7 6305void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6306 struct intel_load_detect_pipe *old)
79e53945 6307{
d2434ab7
DV		 6308 struct intel_encoder *intel_encoder =
6309 intel_attached_encoder(connector);
4ef69c7a 6310 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6311
d2dff872
CW		 6312 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6313 connector->base.id, drm_get_connector_name(connector),
6314 encoder->base.id, drm_get_encoder_name(encoder));
6315
8261b191 6316 if (old->load_detect_temp) {
fc303101
DV		 6317 struct drm_crtc *crtc = encoder->crtc;
6318
6319 to_intel_connector(connector)->new_encoder = NULL;
6320 intel_encoder->new_crtc = NULL;
6321 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6322
6323 if (old->release_fb)
6324 old->release_fb->funcs->destroy(old->release_fb);
6325
0622a53c 6326 return;
79e53945
JB		 6327 }
6328
c751ce4f 6329 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6330 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6331 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6332}
6333
6334/* Returns the clock of the currently programmed mode of the given pipe. */
6335static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6336{
6337 struct drm_i915_private *dev_priv = dev->dev_private;
6338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6339 int pipe = intel_crtc->pipe;
548f245b 6340 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6341 u32 fp;
6342 intel_clock_t clock;
6343
6344 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6345 fp = I915_READ(FP0(pipe));
79e53945 6346 else
39adb7a5 6347 fp = I915_READ(FP1(pipe));
79e53945
JB		 6348
6349 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6350 if (IS_PINEVIEW(dev)) {
6351 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6352 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6353 } else {
6354 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6355 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6356 }
6357
a6c45cf0 6358 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6359 if (IS_PINEVIEW(dev))
6360 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6361 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6362 else
6363 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6364 DPLL_FPA01_P1_POST_DIV_SHIFT);
6365
6366 switch (dpll & DPLL_MODE_MASK) {
6367 case DPLLB_MODE_DAC_SERIAL:
6368 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6369 5 : 10;
6370 break;
6371 case DPLLB_MODE_LVDS:
6372 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6373 7 : 14;
6374 break;
6375 default:
28c97730 6376 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6377 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6378 return 0;
6379 }
6380
6381 /* XXX: Handle the 100Mhz refclk */
2177832f 6382 intel_clock(dev, 96000, &clock);
79e53945
JB		 6383 } else {
6384 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6385
6386 if (is_lvds) {
6387 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6388 DPLL_FPA01_P1_POST_DIV_SHIFT);
6389 clock.p2 = 14;
6390
6391 if ((dpll & PLL_REF_INPUT_MASK) ==
6392 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6393 /* XXX: might not be 66MHz */
2177832f 6394 intel_clock(dev, 66000, &clock);
79e53945 6395 } else
2177832f 6396 intel_clock(dev, 48000, &clock);
79e53945
JB		 6397 } else {
6398 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6399 clock.p1 = 2;
6400 else {
6401 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6402 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6403 }
6404 if (dpll & PLL_P2_DIVIDE_BY_4)
6405 clock.p2 = 4;
6406 else
6407 clock.p2 = 2;
6408
2177832f 6409 intel_clock(dev, 48000, &clock);
79e53945
JB		 6410 }
6411 }
6412
6413 /* XXX: It would be nice to validate the clocks, but we can't reuse
6414 * i830PllIsValid() because it relies on the xf86_config connector
6415 * configuration being accurate, which it isn't necessarily.
6416 */
6417
6418 return clock.dot;
6419}
6420
6421/** Returns the currently programmed mode of the given pipe. */
6422struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6423 struct drm_crtc *crtc)
6424{
548f245b 6425 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6427 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6428 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6429 int htot = I915_READ(HTOTAL(cpu_transcoder));
6430 int hsync = I915_READ(HSYNC(cpu_transcoder));
6431 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6432 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6433
6434 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6435 if (!mode)
6436 return NULL;
6437
6438 mode->clock = intel_crtc_clock_get(dev, crtc);
6439 mode->hdisplay = (htot & 0xffff) + 1;
6440 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6441 mode->hsync_start = (hsync & 0xffff) + 1;
6442 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6443 mode->vdisplay = (vtot & 0xffff) + 1;
6444 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6445 mode->vsync_start = (vsync & 0xffff) + 1;
6446 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6447
6448 drm_mode_set_name(mode);
79e53945
JB		 6449
6450 return mode;
6451}
6452
3dec0095 6453static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6454{
6455 struct drm_device *dev = crtc->dev;
6456 drm_i915_private_t *dev_priv = dev->dev_private;
6457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6458 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6459 int dpll_reg = DPLL(pipe);
6460 int dpll;
652c393a 6461
bad720ff 6462 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6463 return;
6464
6465 if (!dev_priv->lvds_downclock_avail)
6466 return;
6467
dbdc6479 6468 dpll = I915_READ(dpll_reg);
652c393a 6469 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6470 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6471
8ac5a6d5 6472 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6473
6474 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6475 I915_WRITE(dpll_reg, dpll);
9d0498a2 6476 intel_wait_for_vblank(dev, pipe);
dbdc6479 6477
652c393a
JB		 6478 dpll = I915_READ(dpll_reg);
6479 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6480 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6481 }
652c393a
JB		 6482}
6483
6484static void intel_decrease_pllclock(struct drm_crtc *crtc)
6485{
6486 struct drm_device *dev = crtc->dev;
6487 drm_i915_private_t *dev_priv = dev->dev_private;
6488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6489
bad720ff 6490 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6491 return;
6492
6493 if (!dev_priv->lvds_downclock_avail)
6494 return;
6495
6496 /*
6497 * Since this is called by a timer, we should never get here in
6498 * the manual case.
6499 */
6500 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6501 int pipe = intel_crtc->pipe;
6502 int dpll_reg = DPLL(pipe);
6503 int dpll;
f6e5b160 6504
44d98a61 6505 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6506
8ac5a6d5 6507 assert_panel_unlocked(dev_priv, pipe);
652c393a 6508
dc257cf1 6509 dpll = I915_READ(dpll_reg);
652c393a
JB		 6510 dpll |= DISPLAY_RATE_SELECT_FPA1;
6511 I915_WRITE(dpll_reg, dpll);
9d0498a2 6512 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6513 dpll = I915_READ(dpll_reg);
6514 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6515 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6516 }
6517
6518}
6519
f047e395
CW		 6520void intel_mark_busy(struct drm_device *dev)
6521{
f047e395
CW		 6522 i915_update_gfx_val(dev->dev_private);
6523}
6524
6525void intel_mark_idle(struct drm_device *dev)
652c393a 6526{
f047e395
CW		 6527}
6528
6529void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6530{
6531 struct drm_device *dev = obj->base.dev;
652c393a 6532 struct drm_crtc *crtc;
652c393a
JB		 6533
6534 if (!i915_powersave)
6535 return;
6536
652c393a 6537 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6538 if (!crtc->fb)
6539 continue;
6540
f047e395
CW		 6541 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6542 intel_increase_pllclock(crtc);
652c393a 6543 }
652c393a
JB		 6544}
6545
f047e395 6546void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6547{
f047e395
CW		 6548 struct drm_device *dev = obj->base.dev;
6549 struct drm_crtc *crtc;
652c393a 6550
f047e395 6551 if (!i915_powersave)
acb87dfb
CW		 6552 return;
6553
652c393a
JB		 6554 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6555 if (!crtc->fb)
6556 continue;
6557
f047e395
CW		 6558 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6559 intel_decrease_pllclock(crtc);
652c393a
JB		 6560 }
6561}
6562
79e53945
JB		 6563static void intel_crtc_destroy(struct drm_crtc *crtc)
6564{
6565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6566 struct drm_device *dev = crtc->dev;
6567 struct intel_unpin_work *work;
6568 unsigned long flags;
6569
6570 spin_lock_irqsave(&dev->event_lock, flags);
6571 work = intel_crtc->unpin_work;
6572 intel_crtc->unpin_work = NULL;
6573 spin_unlock_irqrestore(&dev->event_lock, flags);
6574
6575 if (work) {
6576 cancel_work_sync(&work->work);
6577 kfree(work);
6578 }
79e53945
JB		 6579
6580 drm_crtc_cleanup(crtc);
67e77c5a 6581
79e53945
JB		 6582 kfree(intel_crtc);
6583}
6584
6b95a207
KH		 6585static void intel_unpin_work_fn(struct work_struct *__work)
6586{
6587 struct intel_unpin_work *work =
6588 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6589 struct drm_device *dev = work->crtc->dev;
6b95a207 6590
b4a98e57 6591 mutex_lock(&dev->struct_mutex);
1690e1eb 6592 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6593 drm_gem_object_unreference(&work->pending_flip_obj->base);
6594 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6595
b4a98e57
CW		 6596 intel_update_fbc(dev);
6597 mutex_unlock(&dev->struct_mutex);
6598
6599 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6600 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6601
6b95a207
KH		 6602 kfree(work);
6603}
6604
1afe3e9d 6605static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6606 struct drm_crtc *crtc)
6b95a207
KH		 6607{
6608 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6610 struct intel_unpin_work *work;
05394f39 6611 struct drm_i915_gem_object *obj;
6b95a207
KH		 6612 unsigned long flags;
6613
6614 /* Ignore early vblank irqs */
6615 if (intel_crtc == NULL)
6616 return;
6617
6618 spin_lock_irqsave(&dev->event_lock, flags);
6619 work = intel_crtc->unpin_work;
6620 if (work == NULL || !work->pending) {
6621 spin_unlock_irqrestore(&dev->event_lock, flags);
6622 return;
6623 }
6624
6625 intel_crtc->unpin_work = NULL;
6b95a207 6626
45a066eb
RC		 6627 if (work->event)
6628 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6629
0af7e4df
MK		 6630 drm_vblank_put(dev, intel_crtc->pipe);
6631
6b95a207
KH		 6632 spin_unlock_irqrestore(&dev->event_lock, flags);
6633
05394f39 6634 obj = work->old_fb_obj;
d9e86c0e 6635
5bb61643 6636 wake_up(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6637
6638 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6639
6640 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6641}
6642
1afe3e9d
JB		 6643void intel_finish_page_flip(struct drm_device *dev, int pipe)
6644{
6645 drm_i915_private_t *dev_priv = dev->dev_private;
6646 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6647
49b14a5c 6648 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6649}
6650
6651void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6652{
6653 drm_i915_private_t *dev_priv = dev->dev_private;
6654 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6655
49b14a5c 6656 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6657}
6658
6b95a207
KH		 6659void intel_prepare_page_flip(struct drm_device *dev, int plane)
6660{
6661 drm_i915_private_t *dev_priv = dev->dev_private;
6662 struct intel_crtc *intel_crtc =
6663 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6664 unsigned long flags;
6665
6666 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6667 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6668 if ((++intel_crtc->unpin_work->pending) > 1)
6669 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6670 } else {
6671 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6672 }
6b95a207
KH		 6673 spin_unlock_irqrestore(&dev->event_lock, flags);
6674}
6675
8c9f3aaf
JB		 6676static int intel_gen2_queue_flip(struct drm_device *dev,
6677 struct drm_crtc *crtc,
6678 struct drm_framebuffer *fb,
6679 struct drm_i915_gem_object *obj)
6680{
6681 struct drm_i915_private *dev_priv = dev->dev_private;
6682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6683 u32 flip_mask;
6d90c952 6684 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6685 int ret;
6686
6d90c952 6687 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6688 if (ret)
83d4092b 6689 goto err;
8c9f3aaf 6690
6d90c952 6691 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6692 if (ret)
83d4092b 6693 goto err_unpin;
8c9f3aaf
JB		 6694
6695 /* Can't queue multiple flips, so wait for the previous
6696 * one to finish before executing the next.
6697 */
6698 if (intel_crtc->plane)
6699 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6700 else
6701 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6702 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6703 intel_ring_emit(ring, MI_NOOP);
6704 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6705 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6706 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6707 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6708 intel_ring_emit(ring, 0); /* aux display base address, unused */
6709 intel_ring_advance(ring);
83d4092b
CW		 6710 return 0;
6711
6712err_unpin:
6713 intel_unpin_fb_obj(obj);
6714err:
8c9f3aaf
JB		 6715 return ret;
6716}
6717
6718static int intel_gen3_queue_flip(struct drm_device *dev,
6719 struct drm_crtc *crtc,
6720 struct drm_framebuffer *fb,
6721 struct drm_i915_gem_object *obj)
6722{
6723 struct drm_i915_private *dev_priv = dev->dev_private;
6724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6725 u32 flip_mask;
6d90c952 6726 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6727 int ret;
6728
6d90c952 6729 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6730 if (ret)
83d4092b 6731 goto err;
8c9f3aaf 6732
6d90c952 6733 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6734 if (ret)
83d4092b 6735 goto err_unpin;
8c9f3aaf
JB		 6736
6737 if (intel_crtc->plane)
6738 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6739 else
6740 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6741 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6742 intel_ring_emit(ring, MI_NOOP);
6743 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6744 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6745 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6746 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6747 intel_ring_emit(ring, MI_NOOP);
6748
6749 intel_ring_advance(ring);
83d4092b
CW		 6750 return 0;
6751
6752err_unpin:
6753 intel_unpin_fb_obj(obj);
6754err:
8c9f3aaf
JB		 6755 return ret;
6756}
6757
6758static int intel_gen4_queue_flip(struct drm_device *dev,
6759 struct drm_crtc *crtc,
6760 struct drm_framebuffer *fb,
6761 struct drm_i915_gem_object *obj)
6762{
6763 struct drm_i915_private *dev_priv = dev->dev_private;
6764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6765 uint32_t pf, pipesrc;
6d90c952 6766 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6767 int ret;
6768
6d90c952 6769 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6770 if (ret)
83d4092b 6771 goto err;
8c9f3aaf 6772
6d90c952 6773 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6774 if (ret)
83d4092b 6775 goto err_unpin;
8c9f3aaf
JB		 6776
6777 /* i965+ uses the linear or tiled offsets from the
6778 * Display Registers (which do not change across a page-flip)
6779 * so we need only reprogram the base address.
6780 */
6d90c952
DV		 6781 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6782 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6783 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6784 intel_ring_emit(ring,
6785 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6786 obj->tiling_mode);
8c9f3aaf
JB		 6787
6788 /* XXX Enabling the panel-fitter across page-flip is so far
6789 * untested on non-native modes, so ignore it for now.
6790 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6791 */
6792 pf = 0;
6793 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6794 intel_ring_emit(ring, pf | pipesrc);
6795 intel_ring_advance(ring);
83d4092b
CW		 6796 return 0;
6797
6798err_unpin:
6799 intel_unpin_fb_obj(obj);
6800err:
8c9f3aaf
JB		 6801 return ret;
6802}
6803
6804static int intel_gen6_queue_flip(struct drm_device *dev,
6805 struct drm_crtc *crtc,
6806 struct drm_framebuffer *fb,
6807 struct drm_i915_gem_object *obj)
6808{
6809 struct drm_i915_private *dev_priv = dev->dev_private;
6810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6811 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6812 uint32_t pf, pipesrc;
6813 int ret;
6814
6d90c952 6815 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6816 if (ret)
83d4092b 6817 goto err;
8c9f3aaf 6818
6d90c952 6819 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6820 if (ret)
83d4092b 6821 goto err_unpin;
8c9f3aaf 6822
6d90c952
DV		 6823 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6824 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6825 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6826 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6827
dc257cf1
DV		 6828 /* Contrary to the suggestions in the documentation,
6829 * "Enable Panel Fitter" does not seem to be required when page
6830 * flipping with a non-native mode, and worse causes a normal
6831 * modeset to fail.
6832 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6833 */
6834 pf = 0;
8c9f3aaf 6835 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6836 intel_ring_emit(ring, pf | pipesrc);
6837 intel_ring_advance(ring);
83d4092b
CW		 6838 return 0;
6839
6840err_unpin:
6841 intel_unpin_fb_obj(obj);
6842err:
8c9f3aaf
JB		 6843 return ret;
6844}
6845
7c9017e5
JB		 6846/*
6847 * On gen7 we currently use the blit ring because (in early silicon at least)
6848 * the render ring doesn't give us interrpts for page flip completion, which
6849 * means clients will hang after the first flip is queued. Fortunately the
6850 * blit ring generates interrupts properly, so use it instead.
6851 */
6852static int intel_gen7_queue_flip(struct drm_device *dev,
6853 struct drm_crtc *crtc,
6854 struct drm_framebuffer *fb,
6855 struct drm_i915_gem_object *obj)
6856{
6857 struct drm_i915_private *dev_priv = dev->dev_private;
6858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6859 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6860 uint32_t plane_bit = 0;
7c9017e5
JB		 6861 int ret;
6862
6863 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6864 if (ret)
83d4092b 6865 goto err;
7c9017e5 6866
cb05d8de
DV		 6867 switch(intel_crtc->plane) {
6868 case PLANE_A:
6869 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6870 break;
6871 case PLANE_B:
6872 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6873 break;
6874 case PLANE_C:
6875 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6876 break;
6877 default:
6878 WARN_ONCE(1, "unknown plane in flip command\n");
6879 ret = -ENODEV;
ab3951eb 6880 goto err_unpin;
cb05d8de
DV		 6881 }
6882
7c9017e5
JB		 6883 ret = intel_ring_begin(ring, 4);
6884 if (ret)
83d4092b 6885 goto err_unpin;
7c9017e5 6886
cb05d8de 6887 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6888 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6889 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6890 intel_ring_emit(ring, (MI_NOOP));
6891 intel_ring_advance(ring);
83d4092b
CW		 6892 return 0;
6893
6894err_unpin:
6895 intel_unpin_fb_obj(obj);
6896err:
7c9017e5
JB		 6897 return ret;
6898}
6899
8c9f3aaf
JB		 6900static int intel_default_queue_flip(struct drm_device *dev,
6901 struct drm_crtc *crtc,
6902 struct drm_framebuffer *fb,
6903 struct drm_i915_gem_object *obj)
6904{
6905 return -ENODEV;
6906}
6907
6b95a207
KH		 6908static int intel_crtc_page_flip(struct drm_crtc *crtc,
6909 struct drm_framebuffer *fb,
6910 struct drm_pending_vblank_event *event)
6911{
6912 struct drm_device *dev = crtc->dev;
6913 struct drm_i915_private *dev_priv = dev->dev_private;
6914 struct intel_framebuffer *intel_fb;
05394f39 6915 struct drm_i915_gem_object *obj;
6b95a207
KH		 6916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6917 struct intel_unpin_work *work;
8c9f3aaf 6918 unsigned long flags;
52e68630 6919 int ret;
6b95a207 6920
e6a595d2
VS		 6921 /* Can't change pixel format via MI display flips. */
6922 if (fb->pixel_format != crtc->fb->pixel_format)
6923 return -EINVAL;
6924
6925 /*
6926 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6927 * Note that pitch changes could also affect these register.
6928 */
6929 if (INTEL_INFO(dev)->gen > 3 &&
6930 (fb->offsets[0] != crtc->fb->offsets[0] ||
6931 fb->pitches[0] != crtc->fb->pitches[0]))
6932 return -EINVAL;
6933
6b95a207
KH		 6934 work = kzalloc(sizeof *work, GFP_KERNEL);
6935 if (work == NULL)
6936 return -ENOMEM;
6937
6b95a207 6938 work->event = event;
b4a98e57 6939 work->crtc = crtc;
6b95a207 6940 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6941 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6942 INIT_WORK(&work->work, intel_unpin_work_fn);
6943
7317c75e
JB		 6944 ret = drm_vblank_get(dev, intel_crtc->pipe);
6945 if (ret)
6946 goto free_work;
6947
6b95a207
KH		 6948 /* We borrow the event spin lock for protecting unpin_work */
6949 spin_lock_irqsave(&dev->event_lock, flags);
6950 if (intel_crtc->unpin_work) {
6951 spin_unlock_irqrestore(&dev->event_lock, flags);
6952 kfree(work);
7317c75e 6953 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6954
6955 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6956 return -EBUSY;
6957 }
6958 intel_crtc->unpin_work = work;
6959 spin_unlock_irqrestore(&dev->event_lock, flags);
6960
6961 intel_fb = to_intel_framebuffer(fb);
6962 obj = intel_fb->obj;
6963
b4a98e57
CW		 6964 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
6965 flush_workqueue(dev_priv->wq);
6966
79158103
CW		 6967 ret = i915_mutex_lock_interruptible(dev);
6968 if (ret)
6969 goto cleanup;
6b95a207 6970
75dfca80 6971 /* Reference the objects for the scheduled work. */
05394f39
CW		 6972 drm_gem_object_reference(&work->old_fb_obj->base);
6973 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6974
6975 crtc->fb = fb;
96b099fd 6976
e1f99ce6 6977 work->pending_flip_obj = obj;
e1f99ce6 6978
4e5359cd
SF		 6979 work->enable_stall_check = true;
6980
b4a98e57 6981 atomic_inc(&intel_crtc->unpin_work_count);
e1f99ce6 6982
8c9f3aaf
JB		 6983 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6984 if (ret)
6985 goto cleanup_pending;
6b95a207 6986
7782de3b 6987 intel_disable_fbc(dev);
f047e395 6988 intel_mark_fb_busy(obj);
6b95a207
KH		 6989 mutex_unlock(&dev->struct_mutex);
6990
e5510fac
JB		 6991 trace_i915_flip_request(intel_crtc->plane, obj);
6992
6b95a207 6993 return 0;
96b099fd 6994
8c9f3aaf 6995cleanup_pending:
b4a98e57 6996 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 6997 drm_gem_object_unreference(&work->old_fb_obj->base);
6998 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6999 mutex_unlock(&dev->struct_mutex);
7000
79158103 7001cleanup:
96b099fd
CW		 7002 spin_lock_irqsave(&dev->event_lock, flags);
7003 intel_crtc->unpin_work = NULL;
7004 spin_unlock_irqrestore(&dev->event_lock, flags);
7005
7317c75e
JB		 7006 drm_vblank_put(dev, intel_crtc->pipe);
7007free_work:
96b099fd
CW		 7008 kfree(work);
7009
7010 return ret;
6b95a207
KH		 7011}
7012
f6e5b160 7013static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7014 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7015 .load_lut = intel_crtc_load_lut,
976f8a20 7016 .disable = intel_crtc_noop,
f6e5b160
CW		 7017};
7018
6ed0f796 7019bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7020{
6ed0f796
DV		 7021 struct intel_encoder *other_encoder;
7022 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7023
6ed0f796
DV		 7024 if (WARN_ON(!crtc))
7025 return false;
7026
7027 list_for_each_entry(other_encoder,
7028 &crtc->dev->mode_config.encoder_list,
7029 base.head) {
7030
7031 if (&other_encoder->new_crtc->base != crtc ||
7032 encoder == other_encoder)
7033 continue;
7034 else
7035 return true;
f47166d2
CW		 7036 }
7037
6ed0f796
DV		 7038 return false;
7039}
47f1c6c9 7040
50f56119
DV		 7041static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7042 struct drm_crtc *crtc)
7043{
7044 struct drm_device *dev;
7045 struct drm_crtc *tmp;
7046 int crtc_mask = 1;
47f1c6c9 7047
50f56119 7048 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7049
50f56119 7050 dev = crtc->dev;
47f1c6c9 7051
50f56119
DV		 7052 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7053 if (tmp == crtc)
7054 break;
7055 crtc_mask <<= 1;
7056 }
47f1c6c9 7057
50f56119
DV		 7058 if (encoder->possible_crtcs & crtc_mask)
7059 return true;
7060 return false;
47f1c6c9 7061}
79e53945 7062
9a935856
DV		 7063/**
7064 * intel_modeset_update_staged_output_state
7065 *
7066 * Updates the staged output configuration state, e.g. after we've read out the
7067 * current hw state.
7068 */
7069static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7070{
9a935856
DV		 7071 struct intel_encoder *encoder;
7072 struct intel_connector *connector;
f6e5b160 7073
9a935856
DV		 7074 list_for_each_entry(connector, &dev->mode_config.connector_list,
7075 base.head) {
7076 connector->new_encoder =
7077 to_intel_encoder(connector->base.encoder);
7078 }
f6e5b160 7079
9a935856
DV		 7080 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7081 base.head) {
7082 encoder->new_crtc =
7083 to_intel_crtc(encoder->base.crtc);
7084 }
f6e5b160
CW		 7085}
7086
9a935856
DV		 7087/**
7088 * intel_modeset_commit_output_state
7089 *
7090 * This function copies the stage display pipe configuration to the real one.
7091 */
7092static void intel_modeset_commit_output_state(struct drm_device *dev)
7093{
7094 struct intel_encoder *encoder;
7095 struct intel_connector *connector;
f6e5b160 7096
9a935856
DV		 7097 list_for_each_entry(connector, &dev->mode_config.connector_list,
7098 base.head) {
7099 connector->base.encoder = &connector->new_encoder->base;
7100 }
f6e5b160 7101
9a935856
DV		 7102 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7103 base.head) {
7104 encoder->base.crtc = &encoder->new_crtc->base;
7105 }
7106}
7107
7758a113
DV		 7108static struct drm_display_mode *
7109intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7110 struct drm_display_mode *mode)
ee7b9f93 7111{
7758a113
DV		 7112 struct drm_device *dev = crtc->dev;
7113 struct drm_display_mode *adjusted_mode;
7114 struct drm_encoder_helper_funcs *encoder_funcs;
7115 struct intel_encoder *encoder;
ee7b9f93 7116
7758a113
DV		 7117 adjusted_mode = drm_mode_duplicate(dev, mode);
7118 if (!adjusted_mode)
7119 return ERR_PTR(-ENOMEM);
7120
7121 /* Pass our mode to the connectors and the CRTC to give them a chance to
7122 * adjust it according to limitations or connector properties, and also
7123 * a chance to reject the mode entirely.
47f1c6c9 7124 */
7758a113
DV		 7125 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7126 base.head) {
47f1c6c9 7127
7758a113
DV		 7128 if (&encoder->new_crtc->base != crtc)
7129 continue;
7130 encoder_funcs = encoder->base.helper_private;
7131 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7132 adjusted_mode))) {
7133 DRM_DEBUG_KMS("Encoder fixup failed\n");
7134 goto fail;
7135 }
ee7b9f93 7136 }
47f1c6c9 7137
7758a113
DV		 7138 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7139 DRM_DEBUG_KMS("CRTC fixup failed\n");
7140 goto fail;
ee7b9f93 7141 }
7758a113 7142 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7143
7758a113
DV		 7144 return adjusted_mode;
7145fail:
7146 drm_mode_destroy(dev, adjusted_mode);
7147 return ERR_PTR(-EINVAL);
ee7b9f93 7148}
47f1c6c9 7149
e2e1ed41
DV		 7150/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7151 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7152static void
7153intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7154 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7155{
7156 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7157 struct drm_device *dev = crtc->dev;
7158 struct intel_encoder *encoder;
7159 struct intel_connector *connector;
7160 struct drm_crtc *tmp_crtc;
79e53945 7161
e2e1ed41 7162 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7163
e2e1ed41
DV		 7164 /* Check which crtcs have changed outputs connected to them, these need
7165 * to be part of the prepare_pipes mask. We don't (yet) support global
7166 * modeset across multiple crtcs, so modeset_pipes will only have one
7167 * bit set at most. */
7168 list_for_each_entry(connector, &dev->mode_config.connector_list,
7169 base.head) {
7170 if (connector->base.encoder == &connector->new_encoder->base)
7171 continue;
79e53945 7172
e2e1ed41
DV		 7173 if (connector->base.encoder) {
7174 tmp_crtc = connector->base.encoder->crtc;
7175
7176 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7177 }
7178
7179 if (connector->new_encoder)
7180 *prepare_pipes |=
7181 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7182 }
7183
e2e1ed41
DV		 7184 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7185 base.head) {
7186 if (encoder->base.crtc == &encoder->new_crtc->base)
7187 continue;
7188
7189 if (encoder->base.crtc) {
7190 tmp_crtc = encoder->base.crtc;
7191
7192 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7193 }
7194
7195 if (encoder->new_crtc)
7196 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7197 }
7198
e2e1ed41
DV		 7199 /* Check for any pipes that will be fully disabled ... */
7200 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7201 base.head) {
7202 bool used = false;
22fd0fab 7203
e2e1ed41
DV		 7204 /* Don't try to disable disabled crtcs. */
7205 if (!intel_crtc->base.enabled)
7206 continue;
7e7d76c3 7207
e2e1ed41
DV		 7208 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7209 base.head) {
7210 if (encoder->new_crtc == intel_crtc)
7211 used = true;
7212 }
7213
7214 if (!used)
7215 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7216 }
7217
e2e1ed41
DV		 7218
7219 /* set_mode is also used to update properties on life display pipes. */
7220 intel_crtc = to_intel_crtc(crtc);
7221 if (crtc->enabled)
7222 *prepare_pipes |= 1 << intel_crtc->pipe;
7223
7224 /* We only support modeset on one single crtc, hence we need to do that
7225 * only for the passed in crtc iff we change anything else than just
7226 * disable crtcs.
7227 *
7228 * This is actually not true, to be fully compatible with the old crtc
7229 * helper we automatically disable _any_ output (i.e. doesn't need to be
7230 * connected to the crtc we're modesetting on) if it's disconnected.
7231 * Which is a rather nutty api (since changed the output configuration
7232 * without userspace's explicit request can lead to confusion), but
7233 * alas. Hence we currently need to modeset on all pipes we prepare. */
7234 if (*prepare_pipes)
7235 *modeset_pipes = *prepare_pipes;
7236
7237 /* ... and mask these out. */
7238 *modeset_pipes &= ~(*disable_pipes);
7239 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7240}
79e53945 7241
ea9d758d 7242static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7243{
ea9d758d 7244 struct drm_encoder *encoder;
f6e5b160 7245 struct drm_device *dev = crtc->dev;
f6e5b160 7246
ea9d758d
DV		 7247 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7248 if (encoder->crtc == crtc)
7249 return true;
7250
7251 return false;
7252}
7253
7254static void
7255intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7256{
7257 struct intel_encoder *intel_encoder;
7258 struct intel_crtc *intel_crtc;
7259 struct drm_connector *connector;
7260
7261 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7262 base.head) {
7263 if (!intel_encoder->base.crtc)
7264 continue;
7265
7266 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7267
7268 if (prepare_pipes & (1 << intel_crtc->pipe))
7269 intel_encoder->connectors_active = false;
7270 }
7271
7272 intel_modeset_commit_output_state(dev);
7273
7274 /* Update computed state. */
7275 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7276 base.head) {
7277 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7278 }
7279
7280 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7281 if (!connector->encoder || !connector->encoder->crtc)
7282 continue;
7283
7284 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7285
7286 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7287 struct drm_property *dpms_property =
7288 dev->mode_config.dpms_property;
7289
ea9d758d 7290 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7291 drm_object_property_set_value(&connector->base,
68d34720
DV		 7292 dpms_property,
7293 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7294
7295 intel_encoder = to_intel_encoder(connector->encoder);
7296 intel_encoder->connectors_active = true;
7297 }
7298 }
7299
7300}
7301
25c5b266
DV		 7302#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7303 list_for_each_entry((intel_crtc), \
7304 &(dev)->mode_config.crtc_list, \
7305 base.head) \
7306 if (mask & (1 <<(intel_crtc)->pipe)) \
7307
b980514c 7308void
8af6cf88
DV		 7309intel_modeset_check_state(struct drm_device *dev)
7310{
7311 struct intel_crtc *crtc;
7312 struct intel_encoder *encoder;
7313 struct intel_connector *connector;
7314
7315 list_for_each_entry(connector, &dev->mode_config.connector_list,
7316 base.head) {
7317 /* This also checks the encoder/connector hw state with the
7318 * ->get_hw_state callbacks. */
7319 intel_connector_check_state(connector);
7320
7321 WARN(&connector->new_encoder->base != connector->base.encoder,
7322 "connector's staged encoder doesn't match current encoder\n");
7323 }
7324
7325 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7326 base.head) {
7327 bool enabled = false;
7328 bool active = false;
7329 enum pipe pipe, tracked_pipe;
7330
7331 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7332 encoder->base.base.id,
7333 drm_get_encoder_name(&encoder->base));
7334
7335 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7336 "encoder's stage crtc doesn't match current crtc\n");
7337 WARN(encoder->connectors_active && !encoder->base.crtc,
7338 "encoder's active_connectors set, but no crtc\n");
7339
7340 list_for_each_entry(connector, &dev->mode_config.connector_list,
7341 base.head) {
7342 if (connector->base.encoder != &encoder->base)
7343 continue;
7344 enabled = true;
7345 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7346 active = true;
7347 }
7348 WARN(!!encoder->base.crtc != enabled,
7349 "encoder's enabled state mismatch "
7350 "(expected %i, found %i)\n",
7351 !!encoder->base.crtc, enabled);
7352 WARN(active && !encoder->base.crtc,
7353 "active encoder with no crtc\n");
7354
7355 WARN(encoder->connectors_active != active,
7356 "encoder's computed active state doesn't match tracked active state "
7357 "(expected %i, found %i)\n", active, encoder->connectors_active);
7358
7359 active = encoder->get_hw_state(encoder, &pipe);
7360 WARN(active != encoder->connectors_active,
7361 "encoder's hw state doesn't match sw tracking "
7362 "(expected %i, found %i)\n",
7363 encoder->connectors_active, active);
7364
7365 if (!encoder->base.crtc)
7366 continue;
7367
7368 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7369 WARN(active && pipe != tracked_pipe,
7370 "active encoder's pipe doesn't match"
7371 "(expected %i, found %i)\n",
7372 tracked_pipe, pipe);
7373
7374 }
7375
7376 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7377 base.head) {
7378 bool enabled = false;
7379 bool active = false;
7380
7381 DRM_DEBUG_KMS("[CRTC:%d]\n",
7382 crtc->base.base.id);
7383
7384 WARN(crtc->active && !crtc->base.enabled,
7385 "active crtc, but not enabled in sw tracking\n");
7386
7387 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7388 base.head) {
7389 if (encoder->base.crtc != &crtc->base)
7390 continue;
7391 enabled = true;
7392 if (encoder->connectors_active)
7393 active = true;
7394 }
7395 WARN(active != crtc->active,
7396 "crtc's computed active state doesn't match tracked active state "
7397 "(expected %i, found %i)\n", active, crtc->active);
7398 WARN(enabled != crtc->base.enabled,
7399 "crtc's computed enabled state doesn't match tracked enabled state "
7400 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7401
7402 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7403 }
7404}
7405
a6778b3c
DV		 7406bool intel_set_mode(struct drm_crtc *crtc,
7407 struct drm_display_mode *mode,
94352cf9 7408 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7409{
7410 struct drm_device *dev = crtc->dev;
dbf2b54e 7411 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7412 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7413 struct intel_crtc *intel_crtc;
7414 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7415 bool ret = true;
7416
e2e1ed41 7417 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7418 &prepare_pipes, &disable_pipes);
7419
7420 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7421 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7422
976f8a20
DV		 7423 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7424 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7425
a6778b3c
DV		 7426 saved_hwmode = crtc->hwmode;
7427 saved_mode = crtc->mode;
a6778b3c 7428
25c5b266
DV		 7429 /* Hack: Because we don't (yet) support global modeset on multiple
7430 * crtcs, we don't keep track of the new mode for more than one crtc.
7431 * Hence simply check whether any bit is set in modeset_pipes in all the
7432 * pieces of code that are not yet converted to deal with mutliple crtcs
7433 * changing their mode at the same time. */
7434 adjusted_mode = NULL;
7435 if (modeset_pipes) {
7436 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7437 if (IS_ERR(adjusted_mode)) {
7438 return false;
7439 }
25c5b266 7440 }
a6778b3c 7441
ea9d758d
DV		 7442 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7443 if (intel_crtc->base.enabled)
7444 dev_priv->display.crtc_disable(&intel_crtc->base);
7445 }
a6778b3c 7446
6c4c86f5
DV		 7447 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7448 * to set it here already despite that we pass it down the callchain.
f6e5b160 7449 */
6c4c86f5 7450 if (modeset_pipes)
25c5b266 7451 crtc->mode = *mode;
7758a113 7452
ea9d758d
DV		 7453 /* Only after disabling all output pipelines that will be changed can we
7454 * update the the output configuration. */
7455 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7456
47fab737
DV		 7457 if (dev_priv->display.modeset_global_resources)
7458 dev_priv->display.modeset_global_resources(dev);
7459
a6778b3c
DV		 7460 /* Set up the DPLL and any encoders state that needs to adjust or depend
7461 * on the DPLL.
f6e5b160 7462 */
25c5b266
DV		 7463 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7464 ret = !intel_crtc_mode_set(&intel_crtc->base,
7465 mode, adjusted_mode,
7466 x, y, fb);
7467 if (!ret)
7468 goto done;
a6778b3c
DV		 7469 }
7470
7471 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7472 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7473 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7474
25c5b266
DV		 7475 if (modeset_pipes) {
7476 /* Store real post-adjustment hardware mode. */
7477 crtc->hwmode = *adjusted_mode;
a6778b3c 7478
25c5b266
DV		 7479 /* Calculate and store various constants which
7480 * are later needed by vblank and swap-completion
7481 * timestamping. They are derived from true hwmode.
7482 */
7483 drm_calc_timestamping_constants(crtc);
7484 }
a6778b3c
DV		 7485
7486 /* FIXME: add subpixel order */
7487done:
7488 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7489 if (!ret && crtc->enabled) {
a6778b3c
DV		 7490 crtc->hwmode = saved_hwmode;
7491 crtc->mode = saved_mode;
8af6cf88
DV		 7492 } else {
7493 intel_modeset_check_state(dev);
a6778b3c
DV		 7494 }
7495
7496 return ret;
f6e5b160
CW		 7497}
7498
25c5b266
DV		 7499#undef for_each_intel_crtc_masked
7500
d9e55608
DV		 7501static void intel_set_config_free(struct intel_set_config *config)
7502{
7503 if (!config)
7504 return;
7505
1aa4b628
DV		 7506 kfree(config->save_connector_encoders);
7507 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7508 kfree(config);
7509}
7510
85f9eb71
DV		 7511static int intel_set_config_save_state(struct drm_device *dev,
7512 struct intel_set_config *config)
7513{
85f9eb71
DV		 7514 struct drm_encoder *encoder;
7515 struct drm_connector *connector;
7516 int count;
7517
1aa4b628
DV		 7518 config->save_encoder_crtcs =
7519 kcalloc(dev->mode_config.num_encoder,
7520 sizeof(struct drm_crtc *), GFP_KERNEL);
7521 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7522 return -ENOMEM;
7523
1aa4b628
DV		 7524 config->save_connector_encoders =
7525 kcalloc(dev->mode_config.num_connector,
7526 sizeof(struct drm_encoder *), GFP_KERNEL);
7527 if (!config->save_connector_encoders)
85f9eb71
DV		 7528 return -ENOMEM;
7529
7530 /* Copy data. Note that driver private data is not affected.
7531 * Should anything bad happen only the expected state is
7532 * restored, not the drivers personal bookkeeping.
7533 */
85f9eb71
DV		 7534 count = 0;
7535 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7536 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7537 }
7538
7539 count = 0;
7540 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7541 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7542 }
7543
7544 return 0;
7545}
7546
7547static void intel_set_config_restore_state(struct drm_device *dev,
7548 struct intel_set_config *config)
7549{
9a935856
DV		 7550 struct intel_encoder *encoder;
7551 struct intel_connector *connector;
85f9eb71
DV		 7552 int count;
7553
85f9eb71 7554 count = 0;
9a935856
DV		 7555 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7556 encoder->new_crtc =
7557 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7558 }
7559
7560 count = 0;
9a935856
DV		 7561 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7562 connector->new_encoder =
7563 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7564 }
7565}
7566
5e2b584e
DV		 7567static void
7568intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7569 struct intel_set_config *config)
7570{
7571
7572 /* We should be able to check here if the fb has the same properties
7573 * and then just flip_or_move it */
7574 if (set->crtc->fb != set->fb) {
7575 /* If we have no fb then treat it as a full mode set */
7576 if (set->crtc->fb == NULL) {
7577 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7578 config->mode_changed = true;
7579 } else if (set->fb == NULL) {
7580 config->mode_changed = true;
7581 } else if (set->fb->depth != set->crtc->fb->depth) {
7582 config->mode_changed = true;
7583 } else if (set->fb->bits_per_pixel !=
7584 set->crtc->fb->bits_per_pixel) {
7585 config->mode_changed = true;
7586 } else
7587 config->fb_changed = true;
7588 }
7589
835c5873 7590 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7591 config->fb_changed = true;
7592
7593 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7594 DRM_DEBUG_KMS("modes are different, full mode set\n");
7595 drm_mode_debug_printmodeline(&set->crtc->mode);
7596 drm_mode_debug_printmodeline(set->mode);
7597 config->mode_changed = true;
7598 }
7599}
7600
2e431051 7601static int
9a935856
DV		 7602intel_modeset_stage_output_state(struct drm_device *dev,
7603 struct drm_mode_set *set,
7604 struct intel_set_config *config)
50f56119 7605{
85f9eb71 7606 struct drm_crtc *new_crtc;
9a935856
DV		 7607 struct intel_connector *connector;
7608 struct intel_encoder *encoder;
2e431051 7609 int count, ro;
50f56119 7610
9a935856
DV		 7611 /* The upper layers ensure that we either disabl a crtc or have a list
7612 * of connectors. For paranoia, double-check this. */
7613 WARN_ON(!set->fb && (set->num_connectors != 0));
7614 WARN_ON(set->fb && (set->num_connectors == 0));
7615
50f56119 7616 count = 0;
9a935856
DV		 7617 list_for_each_entry(connector, &dev->mode_config.connector_list,
7618 base.head) {
7619 /* Otherwise traverse passed in connector list and get encoders
7620 * for them. */
50f56119 7621 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7622 if (set->connectors[ro] == &connector->base) {
7623 connector->new_encoder = connector->encoder;
50f56119
DV		 7624 break;
7625 }
7626 }
7627
9a935856
DV		 7628 /* If we disable the crtc, disable all its connectors. Also, if
7629 * the connector is on the changing crtc but not on the new
7630 * connector list, disable it. */
7631 if ((!set->fb || ro == set->num_connectors) &&
7632 connector->base.encoder &&
7633 connector->base.encoder->crtc == set->crtc) {
7634 connector->new_encoder = NULL;
7635
7636 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7637 connector->base.base.id,
7638 drm_get_connector_name(&connector->base));
7639 }
7640
7641
7642 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7643 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7644 config->mode_changed = true;
50f56119 7645 }
9a935856
DV		 7646
7647 /* Disable all disconnected encoders. */
7648 if (connector->base.status == connector_status_disconnected)
7649 connector->new_encoder = NULL;
50f56119 7650 }
9a935856 7651 /* connector->new_encoder is now updated for all connectors. */
50f56119 7652
9a935856 7653 /* Update crtc of enabled connectors. */
50f56119 7654 count = 0;
9a935856
DV		 7655 list_for_each_entry(connector, &dev->mode_config.connector_list,
7656 base.head) {
7657 if (!connector->new_encoder)
50f56119
DV		 7658 continue;
7659
9a935856 7660 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7661
7662 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7663 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7664 new_crtc = set->crtc;
7665 }
7666
7667 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7668 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7669 new_crtc)) {
5e2b584e 7670 return -EINVAL;
50f56119 7671 }
9a935856
DV		 7672 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7673
7674 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7675 connector->base.base.id,
7676 drm_get_connector_name(&connector->base),
7677 new_crtc->base.id);
7678 }
7679
7680 /* Check for any encoders that needs to be disabled. */
7681 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7682 base.head) {
7683 list_for_each_entry(connector,
7684 &dev->mode_config.connector_list,
7685 base.head) {
7686 if (connector->new_encoder == encoder) {
7687 WARN_ON(!connector->new_encoder->new_crtc);
7688
7689 goto next_encoder;
7690 }
7691 }
7692 encoder->new_crtc = NULL;
7693next_encoder:
7694 /* Only now check for crtc changes so we don't miss encoders
7695 * that will be disabled. */
7696 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7697 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7698 config->mode_changed = true;
50f56119
DV		 7699 }
7700 }
9a935856 7701 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7702
2e431051
DV		 7703 return 0;
7704}
7705
7706static int intel_crtc_set_config(struct drm_mode_set *set)
7707{
7708 struct drm_device *dev;
2e431051
DV		 7709 struct drm_mode_set save_set;
7710 struct intel_set_config *config;
7711 int ret;
2e431051 7712
8d3e375e
DV		 7713 BUG_ON(!set);
7714 BUG_ON(!set->crtc);
7715 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7716
7717 if (!set->mode)
7718 set->fb = NULL;
7719
431e50f7
DV		 7720 /* The fb helper likes to play gross jokes with ->mode_set_config.
7721 * Unfortunately the crtc helper doesn't do much at all for this case,
7722 * so we have to cope with this madness until the fb helper is fixed up. */
7723 if (set->fb && set->num_connectors == 0)
7724 return 0;
7725
2e431051
DV		 7726 if (set->fb) {
7727 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7728 set->crtc->base.id, set->fb->base.id,
7729 (int)set->num_connectors, set->x, set->y);
7730 } else {
7731 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7732 }
7733
7734 dev = set->crtc->dev;
7735
7736 ret = -ENOMEM;
7737 config = kzalloc(sizeof(*config), GFP_KERNEL);
7738 if (!config)
7739 goto out_config;
7740
7741 ret = intel_set_config_save_state(dev, config);
7742 if (ret)
7743 goto out_config;
7744
7745 save_set.crtc = set->crtc;
7746 save_set.mode = &set->crtc->mode;
7747 save_set.x = set->crtc->x;
7748 save_set.y = set->crtc->y;
7749 save_set.fb = set->crtc->fb;
7750
7751 /* Compute whether we need a full modeset, only an fb base update or no
7752 * change at all. In the future we might also check whether only the
7753 * mode changed, e.g. for LVDS where we only change the panel fitter in
7754 * such cases. */
7755 intel_set_config_compute_mode_changes(set, config);
7756
9a935856 7757 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7758 if (ret)
7759 goto fail;
7760
5e2b584e 7761 if (config->mode_changed) {
87f1faa6 7762 if (set->mode) {
50f56119
DV		 7763 DRM_DEBUG_KMS("attempting to set mode from"
7764 " userspace\n");
7765 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7766 }
7767
7768 if (!intel_set_mode(set->crtc, set->mode,
7769 set->x, set->y, set->fb)) {
7770 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7771 set->crtc->base.id);
7772 ret = -EINVAL;
7773 goto fail;
7774 }
5e2b584e 7775 } else if (config->fb_changed) {
4f660f49 7776 ret = intel_pipe_set_base(set->crtc,
94352cf9 7777 set->x, set->y, set->fb);
50f56119
DV		 7778 }
7779
d9e55608
DV		 7780 intel_set_config_free(config);
7781
50f56119
DV		 7782 return 0;
7783
7784fail:
85f9eb71 7785 intel_set_config_restore_state(dev, config);
50f56119
DV		 7786
7787 /* Try to restore the config */
5e2b584e 7788 if (config->mode_changed &&
a6778b3c
DV		 7789 !intel_set_mode(save_set.crtc, save_set.mode,
7790 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 7791 DRM_ERROR("failed to restore config after modeset failure\n");
7792
d9e55608
DV		 7793out_config:
7794 intel_set_config_free(config);
50f56119
DV		 7795 return ret;
7796}
f6e5b160
CW		 7797
7798static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7799 .cursor_set = intel_crtc_cursor_set,
7800 .cursor_move = intel_crtc_cursor_move,
7801 .gamma_set = intel_crtc_gamma_set,
50f56119 7802 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7803 .destroy = intel_crtc_destroy,
7804 .page_flip = intel_crtc_page_flip,
7805};
7806
79f689aa
PZ		 7807static void intel_cpu_pll_init(struct drm_device *dev)
7808{
affa9354 7809 if (HAS_DDI(dev))
79f689aa
PZ		 7810 intel_ddi_pll_init(dev);
7811}
7812
ee7b9f93
JB		 7813static void intel_pch_pll_init(struct drm_device *dev)
7814{
7815 drm_i915_private_t *dev_priv = dev->dev_private;
7816 int i;
7817
7818 if (dev_priv->num_pch_pll == 0) {
7819 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7820 return;
7821 }
7822
7823 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7824 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7825 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7826 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7827 }
7828}
7829
b358d0a6 7830static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7831{
22fd0fab 7832 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7833 struct intel_crtc *intel_crtc;
7834 int i;
7835
7836 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7837 if (intel_crtc == NULL)
7838 return;
7839
7840 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7841
7842 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7843 for (i = 0; i < 256; i++) {
7844 intel_crtc->lut_r[i] = i;
7845 intel_crtc->lut_g[i] = i;
7846 intel_crtc->lut_b[i] = i;
7847 }
7848
80824003
JB		 7849 /* Swap pipes & planes for FBC on pre-965 */
7850 intel_crtc->pipe = pipe;
7851 intel_crtc->plane = pipe;
a5c961d1 7852 intel_crtc->cpu_transcoder = pipe;
e2e767ab 7853 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7854 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7855 intel_crtc->plane = !pipe;
80824003
JB		 7856 }
7857
22fd0fab
JB		 7858 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7859 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7860 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7861 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7862
5a354204 7863 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7864
79e53945 7865 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7866}
7867
08d7b3d1 7868int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7869 struct drm_file *file)
08d7b3d1 7870{
08d7b3d1 7871 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7872 struct drm_mode_object *drmmode_obj;
7873 struct intel_crtc *crtc;
08d7b3d1 7874
1cff8f6b
DV		 7875 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7876 return -ENODEV;
08d7b3d1 7877
c05422d5
DV		 7878 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7879 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7880
c05422d5 7881 if (!drmmode_obj) {
08d7b3d1
CW		 7882 DRM_ERROR("no such CRTC id\n");
7883 return -EINVAL;
7884 }
7885
c05422d5
DV		 7886 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7887 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7888
c05422d5 7889 return 0;
08d7b3d1
CW		 7890}
7891
66a9278e 7892static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7893{
66a9278e
DV		 7894 struct drm_device *dev = encoder->base.dev;
7895 struct intel_encoder *source_encoder;
79e53945 7896 int index_mask = 0;
79e53945
JB		 7897 int entry = 0;
7898
66a9278e
DV		 7899 list_for_each_entry(source_encoder,
7900 &dev->mode_config.encoder_list, base.head) {
7901
7902 if (encoder == source_encoder)
79e53945 7903 index_mask |= (1 << entry);
66a9278e
DV		 7904
7905 /* Intel hw has only one MUX where enocoders could be cloned. */
7906 if (encoder->cloneable && source_encoder->cloneable)
7907 index_mask |= (1 << entry);
7908
79e53945
JB		 7909 entry++;
7910 }
4ef69c7a 7911
79e53945
JB		 7912 return index_mask;
7913}
7914
4d302442
CW		 7915static bool has_edp_a(struct drm_device *dev)
7916{
7917 struct drm_i915_private *dev_priv = dev->dev_private;
7918
7919 if (!IS_MOBILE(dev))
7920 return false;
7921
7922 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7923 return false;
7924
7925 if (IS_GEN5(dev) &&
7926 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7927 return false;
7928
7929 return true;
7930}
7931
79e53945
JB		 7932static void intel_setup_outputs(struct drm_device *dev)
7933{
725e30ad 7934 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7935 struct intel_encoder *encoder;
cb0953d7 7936 bool dpd_is_edp = false;
f3cfcba6 7937 bool has_lvds;
79e53945 7938
f3cfcba6 7939 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7940 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7941 /* disable the panel fitter on everything but LVDS */
7942 I915_WRITE(PFIT_CONTROL, 0);
7943 }
79e53945 7944
affa9354 7945 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 7946 intel_crt_init(dev);
cb0953d7 7947
affa9354 7948 if (HAS_DDI(dev)) {
0e72a5b5
ED		 7949 int found;
7950
7951 /* Haswell uses DDI functions to detect digital outputs */
7952 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7953 /* DDI A only supports eDP */
7954 if (found)
7955 intel_ddi_init(dev, PORT_A);
7956
7957 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7958 * register */
7959 found = I915_READ(SFUSE_STRAP);
7960
7961 if (found & SFUSE_STRAP_DDIB_DETECTED)
7962 intel_ddi_init(dev, PORT_B);
7963 if (found & SFUSE_STRAP_DDIC_DETECTED)
7964 intel_ddi_init(dev, PORT_C);
7965 if (found & SFUSE_STRAP_DDID_DETECTED)
7966 intel_ddi_init(dev, PORT_D);
7967 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7968 int found;
270b3042
DV		 7969 dpd_is_edp = intel_dpd_is_edp(dev);
7970
7971 if (has_edp_a(dev))
7972 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 7973
30ad48b7 7974 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 7975 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 7976 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 7977 if (!found)
08d644ad 7978 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 7979 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 7980 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 7981 }
7982
7983 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 7984 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 7985
b708a1d5 7986 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 7987 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 7988
5eb08b69 7989 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 7990 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 7991
270b3042 7992 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 7993 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 7994 } else if (IS_VALLEYVIEW(dev)) {
7995 int found;
7996
19c03924
GB		 7997 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
7998 if (I915_READ(DP_C) & DP_DETECTED)
7999 intel_dp_init(dev, DP_C, PORT_C);
8000
4a87d65d
JB		 8001 if (I915_READ(SDVOB) & PORT_DETECTED) {
8002 /* SDVOB multiplex with HDMIB */
8003 found = intel_sdvo_init(dev, SDVOB, true);
8004 if (!found)
08d644ad 8005 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8006 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8007 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8008 }
8009
8010 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8011 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8012
103a196f 8013 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8014 bool found = false;
7d57382e 8015
725e30ad 8016 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8017 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8018 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8019 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8020 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8021 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8022 }
27185ae1 8023
b01f2c3a
JB		 8024 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8025 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8026 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8027 }
725e30ad 8028 }
13520b05
KH		 8029
8030 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8031
b01f2c3a
JB		 8032 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8033 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8034 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8035 }
27185ae1
ML		 8036
8037 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8038
b01f2c3a
JB		 8039 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8040 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8041 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8042 }
8043 if (SUPPORTS_INTEGRATED_DP(dev)) {
8044 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8045 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8046 }
725e30ad 8047 }
27185ae1 8048
b01f2c3a
JB		 8049 if (SUPPORTS_INTEGRATED_DP(dev) &&
8050 (I915_READ(DP_D) & DP_DETECTED)) {
8051 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8052 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8053 }
bad720ff 8054 } else if (IS_GEN2(dev))
79e53945
JB		 8055 intel_dvo_init(dev);
8056
103a196f 8057 if (SUPPORTS_TV(dev))
79e53945
JB		 8058 intel_tv_init(dev);
8059
4ef69c7a
CW		 8060 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8061 encoder->base.possible_crtcs = encoder->crtc_mask;
8062 encoder->base.possible_clones =
66a9278e 8063 intel_encoder_clones(encoder);
79e53945 8064 }
47356eb6 8065
40579abe 8066 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8067 ironlake_init_pch_refclk(dev);
270b3042
DV		 8068
8069 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8070}
8071
8072static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8073{
8074 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8075
8076 drm_framebuffer_cleanup(fb);
05394f39 8077 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8078
8079 kfree(intel_fb);
8080}
8081
8082static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8083 struct drm_file *file,
79e53945
JB		 8084 unsigned int *handle)
8085{
8086 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8087 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8088
05394f39 8089 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8090}
8091
8092static const struct drm_framebuffer_funcs intel_fb_funcs = {
8093 .destroy = intel_user_framebuffer_destroy,
8094 .create_handle = intel_user_framebuffer_create_handle,
8095};
8096
38651674
DA		 8097int intel_framebuffer_init(struct drm_device *dev,
8098 struct intel_framebuffer *intel_fb,
308e5bcb 8099 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8100 struct drm_i915_gem_object *obj)
79e53945 8101{
79e53945
JB		 8102 int ret;
8103
05394f39 8104 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8105 return -EINVAL;
8106
308e5bcb 8107 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8108 return -EINVAL;
8109
5d7bd705
VS		 8110 /* FIXME <= Gen4 stride limits are bit unclear */
8111 if (mode_cmd->pitches[0] > 32768)
8112 return -EINVAL;
8113
8114 if (obj->tiling_mode != I915_TILING_NONE &&
8115 mode_cmd->pitches[0] != obj->stride)
8116 return -EINVAL;
8117
57779d06 8118 /* Reject formats not supported by any plane early. */
308e5bcb 8119 switch (mode_cmd->pixel_format) {
57779d06 8120 case DRM_FORMAT_C8:
04b3924d
VS		 8121 case DRM_FORMAT_RGB565:
8122 case DRM_FORMAT_XRGB8888:
8123 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8124 break;
8125 case DRM_FORMAT_XRGB1555:
8126 case DRM_FORMAT_ARGB1555:
8127 if (INTEL_INFO(dev)->gen > 3)
8128 return -EINVAL;
8129 break;
8130 case DRM_FORMAT_XBGR8888:
8131 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8132 case DRM_FORMAT_XRGB2101010:
8133 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8134 case DRM_FORMAT_XBGR2101010:
8135 case DRM_FORMAT_ABGR2101010:
8136 if (INTEL_INFO(dev)->gen < 4)
8137 return -EINVAL;
b5626747 8138 break;
04b3924d
VS		 8139 case DRM_FORMAT_YUYV:
8140 case DRM_FORMAT_UYVY:
8141 case DRM_FORMAT_YVYU:
8142 case DRM_FORMAT_VYUY:
57779d06
VS		 8143 if (INTEL_INFO(dev)->gen < 6)
8144 return -EINVAL;
57cd6508
CW		 8145 break;
8146 default:
57779d06 8147 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8148 return -EINVAL;
8149 }
8150
90f9a336
VS		 8151 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8152 if (mode_cmd->offsets[0] != 0)
8153 return -EINVAL;
8154
79e53945
JB		 8155 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8156 if (ret) {
8157 DRM_ERROR("framebuffer init failed %d\n", ret);
8158 return ret;
8159 }
8160
8161 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8162 intel_fb->obj = obj;
79e53945
JB		 8163 return 0;
8164}
8165
79e53945
JB		 8166static struct drm_framebuffer *
8167intel_user_framebuffer_create(struct drm_device *dev,
8168 struct drm_file *filp,
308e5bcb 8169 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8170{
05394f39 8171 struct drm_i915_gem_object *obj;
79e53945 8172
308e5bcb
JB		 8173 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8174 mode_cmd->handles[0]));
c8725226 8175 if (&obj->base == NULL)
cce13ff7 8176 return ERR_PTR(-ENOENT);
79e53945 8177
d2dff872 8178 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8179}
8180
79e53945 8181static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8182 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8183 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8184};
8185
e70236a8
JB		 8186/* Set up chip specific display functions */
8187static void intel_init_display(struct drm_device *dev)
8188{
8189 struct drm_i915_private *dev_priv = dev->dev_private;
8190
8191 /* We always want a DPMS function */
affa9354 8192 if (HAS_DDI(dev)) {
09b4ddf9 8193 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8194 dev_priv->display.crtc_enable = haswell_crtc_enable;
8195 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8196 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8197 dev_priv->display.update_plane = ironlake_update_plane;
8198 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8199 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8200 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8201 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8202 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8203 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8204 } else {
f564048e 8205 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8206 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8207 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8208 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8209 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8210 }
e70236a8 8211
e70236a8 8212 /* Returns the core display clock speed */
25eb05fc
JB		 8213 if (IS_VALLEYVIEW(dev))
8214 dev_priv->display.get_display_clock_speed =
8215 valleyview_get_display_clock_speed;
8216 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8217 dev_priv->display.get_display_clock_speed =
8218 i945_get_display_clock_speed;
8219 else if (IS_I915G(dev))
8220 dev_priv->display.get_display_clock_speed =
8221 i915_get_display_clock_speed;
f2b115e6 8222 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8223 dev_priv->display.get_display_clock_speed =
8224 i9xx_misc_get_display_clock_speed;
8225 else if (IS_I915GM(dev))
8226 dev_priv->display.get_display_clock_speed =
8227 i915gm_get_display_clock_speed;
8228 else if (IS_I865G(dev))
8229 dev_priv->display.get_display_clock_speed =
8230 i865_get_display_clock_speed;
f0f8a9ce 8231 else if (IS_I85X(dev))
e70236a8
JB		 8232 dev_priv->display.get_display_clock_speed =
8233 i855_get_display_clock_speed;
8234 else /* 852, 830 */
8235 dev_priv->display.get_display_clock_speed =
8236 i830_get_display_clock_speed;
8237
7f8a8569 8238 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8239 if (IS_GEN5(dev)) {
674cf967 8240 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8241 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8242 } else if (IS_GEN6(dev)) {
674cf967 8243 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8244 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8245 } else if (IS_IVYBRIDGE(dev)) {
8246 /* FIXME: detect B0+ stepping and use auto training */
8247 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8248 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8249 dev_priv->display.modeset_global_resources =
8250 ivb_modeset_global_resources;
c82e4d26
ED		 8251 } else if (IS_HASWELL(dev)) {
8252 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8253 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8254 } else
8255 dev_priv->display.update_wm = NULL;
6067aaea 8256 } else if (IS_G4X(dev)) {
e0dac65e 8257 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8258 }
8c9f3aaf
JB		 8259
8260 /* Default just returns -ENODEV to indicate unsupported */
8261 dev_priv->display.queue_flip = intel_default_queue_flip;
8262
8263 switch (INTEL_INFO(dev)->gen) {
8264 case 2:
8265 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8266 break;
8267
8268 case 3:
8269 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8270 break;
8271
8272 case 4:
8273 case 5:
8274 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8275 break;
8276
8277 case 6:
8278 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8279 break;
7c9017e5
JB		 8280 case 7:
8281 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8282 break;
8c9f3aaf 8283 }
e70236a8
JB		 8284}
8285
b690e96c
JB		 8286/*
8287 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8288 * resume, or other times. This quirk makes sure that's the case for
8289 * affected systems.
8290 */
0206e353 8291static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8292{
8293 struct drm_i915_private *dev_priv = dev->dev_private;
8294
8295 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8296 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8297}
8298
435793df
KP		 8299/*
8300 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8301 */
8302static void quirk_ssc_force_disable(struct drm_device *dev)
8303{
8304 struct drm_i915_private *dev_priv = dev->dev_private;
8305 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8306 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8307}
8308
4dca20ef 8309/*
5a15ab5b
CE		 8310 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8311 * brightness value
4dca20ef
CE		 8312 */
8313static void quirk_invert_brightness(struct drm_device *dev)
8314{
8315 struct drm_i915_private *dev_priv = dev->dev_private;
8316 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8317 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8318}
8319
b690e96c
JB		 8320struct intel_quirk {
8321 int device;
8322 int subsystem_vendor;
8323 int subsystem_device;
8324 void (*hook)(struct drm_device *dev);
8325};
8326
5f85f176
EE		 8327/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8328struct intel_dmi_quirk {
8329 void (*hook)(struct drm_device *dev);
8330 const struct dmi_system_id (*dmi_id_list)[];
8331};
8332
8333static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8334{
8335 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8336 return 1;
8337}
8338
8339static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8340 {
8341 .dmi_id_list = &(const struct dmi_system_id[]) {
8342 {
8343 .callback = intel_dmi_reverse_brightness,
8344 .ident = "NCR Corporation",
8345 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8346 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8347 },
8348 },
8349 { } /* terminating entry */
8350 },
8351 .hook = quirk_invert_brightness,
8352 },
8353};
8354
c43b5634 8355static struct intel_quirk intel_quirks[] = {
b690e96c 8356 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8357 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8358
b690e96c
JB		 8359 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8360 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8361
b690e96c
JB		 8362 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8363 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8364
ccd0d36e 8365 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8366 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8367 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8368
8369 /* Lenovo U160 cannot use SSC on LVDS */
8370 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8371
8372 /* Sony Vaio Y cannot use SSC on LVDS */
8373 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8374
8375 /* Acer Aspire 5734Z must invert backlight brightness */
8376 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8377};
8378
8379static void intel_init_quirks(struct drm_device *dev)
8380{
8381 struct pci_dev *d = dev->pdev;
8382 int i;
8383
8384 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8385 struct intel_quirk *q = &intel_quirks[i];
8386
8387 if (d->device == q->device &&
8388 (d->subsystem_vendor == q->subsystem_vendor ||
8389 q->subsystem_vendor == PCI_ANY_ID) &&
8390 (d->subsystem_device == q->subsystem_device ||
8391 q->subsystem_device == PCI_ANY_ID))
8392 q->hook(dev);
8393 }
5f85f176
EE		 8394 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8395 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8396 intel_dmi_quirks[i].hook(dev);
8397 }
b690e96c
JB		 8398}
8399
9cce37f4
JB		 8400/* Disable the VGA plane that we never use */
8401static void i915_disable_vga(struct drm_device *dev)
8402{
8403 struct drm_i915_private *dev_priv = dev->dev_private;
8404 u8 sr1;
8405 u32 vga_reg;
8406
8407 if (HAS_PCH_SPLIT(dev))
8408 vga_reg = CPU_VGACNTRL;
8409 else
8410 vga_reg = VGACNTRL;
8411
8412 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8413 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8414 sr1 = inb(VGA_SR_DATA);
8415 outb(sr1 | 1<<5, VGA_SR_DATA);
8416 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8417 udelay(300);
8418
8419 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8420 POSTING_READ(vga_reg);
8421}
8422
f817586c
DV		 8423void intel_modeset_init_hw(struct drm_device *dev)
8424{
0232e927
ED		 8425 /* We attempt to init the necessary power wells early in the initialization
8426 * time, so the subsystems that expect power to be enabled can work.
8427 */
8428 intel_init_power_wells(dev);
8429
a8f78b58
ED		 8430 intel_prepare_ddi(dev);
8431
f817586c
DV		 8432 intel_init_clock_gating(dev);
8433
79f5b2c7 8434 mutex_lock(&dev->struct_mutex);
8090c6b9 8435 intel_enable_gt_powersave(dev);
79f5b2c7 8436 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8437}
8438
79e53945
JB		 8439void intel_modeset_init(struct drm_device *dev)
8440{
652c393a 8441 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8442 int i, ret;
79e53945
JB		 8443
8444 drm_mode_config_init(dev);
8445
8446 dev->mode_config.min_width = 0;
8447 dev->mode_config.min_height = 0;
8448
019d96cb
DA		 8449 dev->mode_config.preferred_depth = 24;
8450 dev->mode_config.prefer_shadow = 1;
8451
e6ecefaa 8452 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8453
b690e96c
JB		 8454 intel_init_quirks(dev);
8455
1fa61106
ED		 8456 intel_init_pm(dev);
8457
e70236a8
JB		 8458 intel_init_display(dev);
8459
a6c45cf0
CW		 8460 if (IS_GEN2(dev)) {
8461 dev->mode_config.max_width = 2048;
8462 dev->mode_config.max_height = 2048;
8463 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8464 dev->mode_config.max_width = 4096;
8465 dev->mode_config.max_height = 4096;
79e53945 8466 } else {
a6c45cf0
CW		 8467 dev->mode_config.max_width = 8192;
8468 dev->mode_config.max_height = 8192;
79e53945 8469 }
dd2757f8 8470 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8471
28c97730 8472 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8473 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8474
a3524f1b 8475 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8476 intel_crtc_init(dev, i);
00c2064b
JB		 8477 ret = intel_plane_init(dev, i);
8478 if (ret)
8479 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8480 }
8481
79f689aa 8482 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8483 intel_pch_pll_init(dev);
8484
9cce37f4
JB		 8485 /* Just disable it once at startup */
8486 i915_disable_vga(dev);
79e53945 8487 intel_setup_outputs(dev);
11be49eb
CW		 8488
8489 /* Just in case the BIOS is doing something questionable. */
8490 intel_disable_fbc(dev);
2c7111db
CW		 8491}
8492
24929352
DV		 8493static void
8494intel_connector_break_all_links(struct intel_connector *connector)
8495{
8496 connector->base.dpms = DRM_MODE_DPMS_OFF;
8497 connector->base.encoder = NULL;
8498 connector->encoder->connectors_active = false;
8499 connector->encoder->base.crtc = NULL;
8500}
8501
7fad798e
DV		 8502static void intel_enable_pipe_a(struct drm_device *dev)
8503{
8504 struct intel_connector *connector;
8505 struct drm_connector *crt = NULL;
8506 struct intel_load_detect_pipe load_detect_temp;
8507
8508 /* We can't just switch on the pipe A, we need to set things up with a
8509 * proper mode and output configuration. As a gross hack, enable pipe A
8510 * by enabling the load detect pipe once. */
8511 list_for_each_entry(connector,
8512 &dev->mode_config.connector_list,
8513 base.head) {
8514 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8515 crt = &connector->base;
8516 break;
8517 }
8518 }
8519
8520 if (!crt)
8521 return;
8522
8523 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8524 intel_release_load_detect_pipe(crt, &load_detect_temp);
8525
652c393a 8526
7fad798e
DV		 8527}
8528
fa555837
DV		 8529static bool
8530intel_check_plane_mapping(struct intel_crtc *crtc)
8531{
8532 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8533 u32 reg, val;
8534
8535 if (dev_priv->num_pipe == 1)
8536 return true;
8537
8538 reg = DSPCNTR(!crtc->plane);
8539 val = I915_READ(reg);
8540
8541 if ((val & DISPLAY_PLANE_ENABLE) &&
8542 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8543 return false;
8544
8545 return true;
8546}
8547
24929352
DV		 8548static void intel_sanitize_crtc(struct intel_crtc *crtc)
8549{
8550 struct drm_device *dev = crtc->base.dev;
8551 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8552 u32 reg;
24929352 8553
24929352 8554 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8555 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8556 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8557
8558 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8559 * disable the crtc (and hence change the state) if it is wrong. Note
8560 * that gen4+ has a fixed plane -> pipe mapping. */
8561 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8562 struct intel_connector *connector;
8563 bool plane;
8564
24929352
DV		 8565 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8566 crtc->base.base.id);
8567
8568 /* Pipe has the wrong plane attached and the plane is active.
8569 * Temporarily change the plane mapping and disable everything
8570 * ... */
8571 plane = crtc->plane;
8572 crtc->plane = !plane;
8573 dev_priv->display.crtc_disable(&crtc->base);
8574 crtc->plane = plane;
8575
8576 /* ... and break all links. */
8577 list_for_each_entry(connector, &dev->mode_config.connector_list,
8578 base.head) {
8579 if (connector->encoder->base.crtc != &crtc->base)
8580 continue;
8581
8582 intel_connector_break_all_links(connector);
8583 }
8584
8585 WARN_ON(crtc->active);
8586 crtc->base.enabled = false;
8587 }
24929352 8588
7fad798e
DV		 8589 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8590 crtc->pipe == PIPE_A && !crtc->active) {
8591 /* BIOS forgot to enable pipe A, this mostly happens after
8592 * resume. Force-enable the pipe to fix this, the update_dpms
8593 * call below we restore the pipe to the right state, but leave
8594 * the required bits on. */
8595 intel_enable_pipe_a(dev);
8596 }
8597
24929352
DV		 8598 /* Adjust the state of the output pipe according to whether we
8599 * have active connectors/encoders. */
8600 intel_crtc_update_dpms(&crtc->base);
8601
8602 if (crtc->active != crtc->base.enabled) {
8603 struct intel_encoder *encoder;
8604
8605 /* This can happen either due to bugs in the get_hw_state
8606 * functions or because the pipe is force-enabled due to the
8607 * pipe A quirk. */
8608 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8609 crtc->base.base.id,
8610 crtc->base.enabled ? "enabled" : "disabled",
8611 crtc->active ? "enabled" : "disabled");
8612
8613 crtc->base.enabled = crtc->active;
8614
8615 /* Because we only establish the connector -> encoder ->
8616 * crtc links if something is active, this means the
8617 * crtc is now deactivated. Break the links. connector
8618 * -> encoder links are only establish when things are
8619 * actually up, hence no need to break them. */
8620 WARN_ON(crtc->active);
8621
8622 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8623 WARN_ON(encoder->connectors_active);
8624 encoder->base.crtc = NULL;
8625 }
8626 }
8627}
8628
8629static void intel_sanitize_encoder(struct intel_encoder *encoder)
8630{
8631 struct intel_connector *connector;
8632 struct drm_device *dev = encoder->base.dev;
8633
8634 /* We need to check both for a crtc link (meaning that the
8635 * encoder is active and trying to read from a pipe) and the
8636 * pipe itself being active. */
8637 bool has_active_crtc = encoder->base.crtc &&
8638 to_intel_crtc(encoder->base.crtc)->active;
8639
8640 if (encoder->connectors_active && !has_active_crtc) {
8641 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8642 encoder->base.base.id,
8643 drm_get_encoder_name(&encoder->base));
8644
8645 /* Connector is active, but has no active pipe. This is
8646 * fallout from our resume register restoring. Disable
8647 * the encoder manually again. */
8648 if (encoder->base.crtc) {
8649 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8650 encoder->base.base.id,
8651 drm_get_encoder_name(&encoder->base));
8652 encoder->disable(encoder);
8653 }
8654
8655 /* Inconsistent output/port/pipe state happens presumably due to
8656 * a bug in one of the get_hw_state functions. Or someplace else
8657 * in our code, like the register restore mess on resume. Clamp
8658 * things to off as a safer default. */
8659 list_for_each_entry(connector,
8660 &dev->mode_config.connector_list,
8661 base.head) {
8662 if (connector->encoder != encoder)
8663 continue;
8664
8665 intel_connector_break_all_links(connector);
8666 }
8667 }
8668 /* Enabled encoders without active connectors will be fixed in
8669 * the crtc fixup. */
8670}
8671
8672/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8673 * and i915 state tracking structures. */
45e2b5f6
DV		 8674void intel_modeset_setup_hw_state(struct drm_device *dev,
8675 bool force_restore)
24929352
DV		 8676{
8677 struct drm_i915_private *dev_priv = dev->dev_private;
8678 enum pipe pipe;
8679 u32 tmp;
8680 struct intel_crtc *crtc;
8681 struct intel_encoder *encoder;
8682 struct intel_connector *connector;
8683
affa9354 8684 if (HAS_DDI(dev)) {
e28d54cb
PZ		 8685 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8686
8687 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8688 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8689 case TRANS_DDI_EDP_INPUT_A_ON:
8690 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8691 pipe = PIPE_A;
8692 break;
8693 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8694 pipe = PIPE_B;
8695 break;
8696 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8697 pipe = PIPE_C;
8698 break;
8699 }
8700
8701 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8702 crtc->cpu_transcoder = TRANSCODER_EDP;
8703
8704 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8705 pipe_name(pipe));
8706 }
8707 }
8708
24929352
DV		 8709 for_each_pipe(pipe) {
8710 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8711
702e7a56 8712 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8713 if (tmp & PIPECONF_ENABLE)
8714 crtc->active = true;
8715 else
8716 crtc->active = false;
8717
8718 crtc->base.enabled = crtc->active;
8719
8720 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8721 crtc->base.base.id,
8722 crtc->active ? "enabled" : "disabled");
8723 }
8724
affa9354 8725 if (HAS_DDI(dev))
6441ab5f
PZ		 8726 intel_ddi_setup_hw_pll_state(dev);
8727
24929352
DV		 8728 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8729 base.head) {
8730 pipe = 0;
8731
8732 if (encoder->get_hw_state(encoder, &pipe)) {
8733 encoder->base.crtc =
8734 dev_priv->pipe_to_crtc_mapping[pipe];
8735 } else {
8736 encoder->base.crtc = NULL;
8737 }
8738
8739 encoder->connectors_active = false;
8740 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8741 encoder->base.base.id,
8742 drm_get_encoder_name(&encoder->base),
8743 encoder->base.crtc ? "enabled" : "disabled",
8744 pipe);
8745 }
8746
8747 list_for_each_entry(connector, &dev->mode_config.connector_list,
8748 base.head) {
8749 if (connector->get_hw_state(connector)) {
8750 connector->base.dpms = DRM_MODE_DPMS_ON;
8751 connector->encoder->connectors_active = true;
8752 connector->base.encoder = &connector->encoder->base;
8753 } else {
8754 connector->base.dpms = DRM_MODE_DPMS_OFF;
8755 connector->base.encoder = NULL;
8756 }
8757 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8758 connector->base.base.id,
8759 drm_get_connector_name(&connector->base),
8760 connector->base.encoder ? "enabled" : "disabled");
8761 }
8762
8763 /* HW state is read out, now we need to sanitize this mess. */
8764 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8765 base.head) {
8766 intel_sanitize_encoder(encoder);
8767 }
8768
8769 for_each_pipe(pipe) {
8770 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8771 intel_sanitize_crtc(crtc);
8772 }
9a935856 8773
45e2b5f6
DV		 8774 if (force_restore) {
8775 for_each_pipe(pipe) {
8776 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8777 intel_set_mode(&crtc->base, &crtc->base.mode,
8778 crtc->base.x, crtc->base.y, crtc->base.fb);
8779 }
8780 } else {
8781 intel_modeset_update_staged_output_state(dev);
8782 }
8af6cf88
DV		 8783
8784 intel_modeset_check_state(dev);
2e938892
DV		 8785
8786 drm_mode_config_reset(dev);
2c7111db
CW		 8787}
8788
8789void intel_modeset_gem_init(struct drm_device *dev)
8790{
1833b134 8791 intel_modeset_init_hw(dev);
02e792fb
DV		 8792
8793 intel_setup_overlay(dev);
24929352 8794
45e2b5f6 8795 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 8796}
8797
8798void intel_modeset_cleanup(struct drm_device *dev)
8799{
652c393a
JB		 8800 struct drm_i915_private *dev_priv = dev->dev_private;
8801 struct drm_crtc *crtc;
8802 struct intel_crtc *intel_crtc;
8803
f87ea761 8804 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8805 mutex_lock(&dev->struct_mutex);
8806
723bfd70
JB		 8807 intel_unregister_dsm_handler();
8808
8809
652c393a
JB		 8810 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8811 /* Skip inactive CRTCs */
8812 if (!crtc->fb)
8813 continue;
8814
8815 intel_crtc = to_intel_crtc(crtc);
3dec0095 8816 intel_increase_pllclock(crtc);
652c393a
JB		 8817 }
8818
973d04f9 8819 intel_disable_fbc(dev);
e70236a8 8820
8090c6b9 8821 intel_disable_gt_powersave(dev);
0cdab21f 8822
930ebb46
DV		 8823 ironlake_teardown_rc6(dev);
8824
57f350b6
JB		 8825 if (IS_VALLEYVIEW(dev))
8826 vlv_init_dpio(dev);
8827
69341a5e
KH		 8828 mutex_unlock(&dev->struct_mutex);
8829
6c0d9350
DV		 8830 /* Disable the irq before mode object teardown, for the irq might
8831 * enqueue unpin/hotplug work. */
8832 drm_irq_uninstall(dev);
8833 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8834 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8835
1630fe75
CW		 8836 /* flush any delayed tasks or pending work */
8837 flush_scheduled_work();
8838
79e53945
JB		 8839 drm_mode_config_cleanup(dev);
8840}
8841
f1c79df3
ZW		 8842/*
8843 * Return which encoder is currently attached for connector.
8844 */
df0e9248 8845struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8846{
df0e9248
CW		 8847 return &intel_attached_encoder(connector)->base;
8848}
f1c79df3 8849
df0e9248
CW		 8850void intel_connector_attach_encoder(struct intel_connector *connector,
8851 struct intel_encoder *encoder)
8852{
8853 connector->encoder = encoder;
8854 drm_mode_connector_attach_encoder(&connector->base,
8855 &encoder->base);
79e53945 8856}
28d52043
DA		 8857
8858/*
8859 * set vga decode state - true == enable VGA decode
8860 */
8861int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8862{
8863 struct drm_i915_private *dev_priv = dev->dev_private;
8864 u16 gmch_ctrl;
8865
8866 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8867 if (state)
8868 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8869 else
8870 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8871 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8872 return 0;
8873}
c4a1d9e4
CW		 8874
8875#ifdef CONFIG_DEBUG_FS
8876#include <linux/seq_file.h>
8877
8878struct intel_display_error_state {
8879 struct intel_cursor_error_state {
8880 u32 control;
8881 u32 position;
8882 u32 base;
8883 u32 size;
52331309 8884 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 8885
8886 struct intel_pipe_error_state {
8887 u32 conf;
8888 u32 source;
8889
8890 u32 htotal;
8891 u32 hblank;
8892 u32 hsync;
8893 u32 vtotal;
8894 u32 vblank;
8895 u32 vsync;
52331309 8896 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 8897
8898 struct intel_plane_error_state {
8899 u32 control;
8900 u32 stride;
8901 u32 size;
8902 u32 pos;
8903 u32 addr;
8904 u32 surface;
8905 u32 tile_offset;
52331309 8906 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 8907};
8908
8909struct intel_display_error_state *
8910intel_display_capture_error_state(struct drm_device *dev)
8911{
0206e353 8912 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 8913 struct intel_display_error_state *error;
702e7a56 8914 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 8915 int i;
8916
8917 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8918 if (error == NULL)
8919 return NULL;
8920
52331309 8921 for_each_pipe(i) {
702e7a56
PZ		 8922 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
8923
c4a1d9e4
CW		 8924 error->cursor[i].control = I915_READ(CURCNTR(i));
8925 error->cursor[i].position = I915_READ(CURPOS(i));
8926 error->cursor[i].base = I915_READ(CURBASE(i));
8927
8928 error->plane[i].control = I915_READ(DSPCNTR(i));
8929 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8930 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8931 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8932 error->plane[i].addr = I915_READ(DSPADDR(i));
8933 if (INTEL_INFO(dev)->gen >= 4) {
8934 error->plane[i].surface = I915_READ(DSPSURF(i));
8935 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8936 }
8937
702e7a56 8938 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 8939 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 8940 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
8941 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
8942 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
8943 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
8944 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
8945 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 8946 }
8947
8948 return error;
8949}
8950
8951void
8952intel_display_print_error_state(struct seq_file *m,
8953 struct drm_device *dev,
8954 struct intel_display_error_state *error)
8955{
52331309 8956 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8957 int i;
8958
52331309
DL		 8959 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8960 for_each_pipe(i) {
c4a1d9e4
CW		 8961 seq_printf(m, "Pipe [%d]:\n", i);
8962 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8963 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8964 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8965 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8966 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8967 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8968 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8969 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8970
8971 seq_printf(m, "Plane [%d]:\n", i);
8972 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8973 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8974 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8975 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8976 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8977 if (INTEL_INFO(dev)->gen >= 4) {
8978 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8979 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8980 }
8981
8982 seq_printf(m, "Cursor [%d]:\n", i);
8983 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8984 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8985 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8986 }
8987}
8988#endif
Linux kernel - Deliverables
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