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drm/i915: Don't use staged config for VLV cdclk calculations
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
83a57153
ACO		 86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
eb1bfe80
JB		 88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
5b18e57c
DV		 92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
29407aab 97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 100static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
d288f65f 102static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
e7457a9a 106
0e32b39c
DA		 107static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
108{
109 if (!connector->mst_port)
110 return connector->encoder;
111 else
112 return &connector->mst_port->mst_encoders[pipe]->base;
113}
114
79e53945 115typedef struct {
0206e353 116 int min, max;
79e53945
JB		 117} intel_range_t;
118
119typedef struct {
0206e353
AJ		 120 int dot_limit;
121 int p2_slow, p2_fast;
79e53945
JB		 122} intel_p2_t;
123
d4906093
ML		 124typedef struct intel_limit intel_limit_t;
125struct intel_limit {
0206e353
AJ		 126 intel_range_t dot, vco, n, m, m1, m2, p, p1;
127 intel_p2_t p2;
d4906093 128};
79e53945 129
d2acd215
DV		 130int
131intel_pch_rawclk(struct drm_device *dev)
132{
133 struct drm_i915_private *dev_priv = dev->dev_private;
134
135 WARN_ON(!HAS_PCH_SPLIT(dev));
136
137 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
138}
139
021357ac
CW		 140static inline u32 /* units of 100MHz */
141intel_fdi_link_freq(struct drm_device *dev)
142{
8b99e68c
CW		 143 if (IS_GEN5(dev)) {
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
146 } else
147 return 27;
021357ac
CW		 148}
149
5d536e28 150static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 151 .dot = { .min = 25000, .max = 350000 },
9c333719 152 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 153 .n = { .min = 2, .max = 16 },
0206e353
AJ		 154 .m = { .min = 96, .max = 140 },
155 .m1 = { .min = 18, .max = 26 },
156 .m2 = { .min = 6, .max = 16 },
157 .p = { .min = 4, .max = 128 },
158 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 159 .p2 = { .dot_limit = 165000,
160 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 161};
162
5d536e28
DV		 163static const intel_limit_t intel_limits_i8xx_dvo = {
164 .dot = { .min = 25000, .max = 350000 },
9c333719 165 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 166 .n = { .min = 2, .max = 16 },
5d536e28
DV		 167 .m = { .min = 96, .max = 140 },
168 .m1 = { .min = 18, .max = 26 },
169 .m2 = { .min = 6, .max = 16 },
170 .p = { .min = 4, .max = 128 },
171 .p1 = { .min = 2, .max = 33 },
172 .p2 = { .dot_limit = 165000,
173 .p2_slow = 4, .p2_fast = 4 },
174};
175
e4b36699 176static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 177 .dot = { .min = 25000, .max = 350000 },
9c333719 178 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 179 .n = { .min = 2, .max = 16 },
0206e353
AJ		 180 .m = { .min = 96, .max = 140 },
181 .m1 = { .min = 18, .max = 26 },
182 .m2 = { .min = 6, .max = 16 },
183 .p = { .min = 4, .max = 128 },
184 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 14, .p2_fast = 7 },
e4b36699 187};
273e27ca 188
e4b36699 189static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 190 .dot = { .min = 20000, .max = 400000 },
191 .vco = { .min = 1400000, .max = 2800000 },
192 .n = { .min = 1, .max = 6 },
193 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 194 .m1 = { .min = 8, .max = 18 },
195 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 198 .p2 = { .dot_limit = 200000,
199 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 200};
201
202static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 203 .dot = { .min = 20000, .max = 400000 },
204 .vco = { .min = 1400000, .max = 2800000 },
205 .n = { .min = 1, .max = 6 },
206 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 207 .m1 = { .min = 8, .max = 18 },
208 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 209 .p = { .min = 7, .max = 98 },
210 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 211 .p2 = { .dot_limit = 112000,
212 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 213};
214
273e27ca 215
e4b36699 216static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 217 .dot = { .min = 25000, .max = 270000 },
218 .vco = { .min = 1750000, .max = 3500000},
219 .n = { .min = 1, .max = 4 },
220 .m = { .min = 104, .max = 138 },
221 .m1 = { .min = 17, .max = 23 },
222 .m2 = { .min = 5, .max = 11 },
223 .p = { .min = 10, .max = 30 },
224 .p1 = { .min = 1, .max = 3},
225 .p2 = { .dot_limit = 270000,
226 .p2_slow = 10,
227 .p2_fast = 10
044c7c41 228 },
e4b36699
KP		 229};
230
231static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 232 .dot = { .min = 22000, .max = 400000 },
233 .vco = { .min = 1750000, .max = 3500000},
234 .n = { .min = 1, .max = 4 },
235 .m = { .min = 104, .max = 138 },
236 .m1 = { .min = 16, .max = 23 },
237 .m2 = { .min = 5, .max = 11 },
238 .p = { .min = 5, .max = 80 },
239 .p1 = { .min = 1, .max = 8},
240 .p2 = { .dot_limit = 165000,
241 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 242};
243
244static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 245 .dot = { .min = 20000, .max = 115000 },
246 .vco = { .min = 1750000, .max = 3500000 },
247 .n = { .min = 1, .max = 3 },
248 .m = { .min = 104, .max = 138 },
249 .m1 = { .min = 17, .max = 23 },
250 .m2 = { .min = 5, .max = 11 },
251 .p = { .min = 28, .max = 112 },
252 .p1 = { .min = 2, .max = 8 },
253 .p2 = { .dot_limit = 0,
254 .p2_slow = 14, .p2_fast = 14
044c7c41 255 },
e4b36699
KP		 256};
257
258static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 259 .dot = { .min = 80000, .max = 224000 },
260 .vco = { .min = 1750000, .max = 3500000 },
261 .n = { .min = 1, .max = 3 },
262 .m = { .min = 104, .max = 138 },
263 .m1 = { .min = 17, .max = 23 },
264 .m2 = { .min = 5, .max = 11 },
265 .p = { .min = 14, .max = 42 },
266 .p1 = { .min = 2, .max = 6 },
267 .p2 = { .dot_limit = 0,
268 .p2_slow = 7, .p2_fast = 7
044c7c41 269 },
e4b36699
KP		 270};
271
f2b115e6 272static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 273 .dot = { .min = 20000, .max = 400000},
274 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 275 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
273e27ca 278 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 279 .m1 = { .min = 0, .max = 0 },
280 .m2 = { .min = 0, .max = 254 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 298};
299
273e27ca
EA		 300/* Ironlake / Sandybridge
301 *
302 * We calculate clock using (register_value + 2) for N/M1/M2, so here
303 * the range value for them is (actual_value - 2).
304 */
b91ad0ec 305static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 5 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 5, .max = 80 },
313 .p1 = { .min = 1, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 316};
317
b91ad0ec 318static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 118 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 28, .max = 112 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 329};
330
331static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 127 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 56 },
339 .p1 = { .min = 2, .max = 8 },
340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 342};
343
273e27ca 344/* LVDS 100mhz refclk limits. */
b91ad0ec 345static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000 },
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 79, .max = 126 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 28, .max = 112 },
0206e353 353 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 354 .p2 = { .dot_limit = 225000,
355 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 356};
357
358static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 3 },
362 .m = { .min = 79, .max = 126 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 14, .max = 42 },
0206e353 366 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 369};
370
dc730512 371static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 372 /*
373 * These are the data rate limits (measured in fast clocks)
374 * since those are the strictest limits we have. The fast
375 * clock and actual rate limits are more relaxed, so checking
376 * them would make no difference.
377 */
378 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 379 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 380 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 381 .m1 = { .min = 2, .max = 3 },
382 .m2 = { .min = 11, .max = 156 },
b99ab663 383 .p1 = { .min = 2, .max = 3 },
5fdc9c49 384 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 385};
386
ef9348c8
CML		 387static const intel_limit_t intel_limits_chv = {
388 /*
389 * These are the data rate limits (measured in fast clocks)
390 * since those are the strictest limits we have. The fast
391 * clock and actual rate limits are more relaxed, so checking
392 * them would make no difference.
393 */
394 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 395 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 396 .n = { .min = 1, .max = 1 },
397 .m1 = { .min = 2, .max = 2 },
398 .m2 = { .min = 24 << 22, .max = 175 << 22 },
399 .p1 = { .min = 2, .max = 4 },
400 .p2 = { .p2_slow = 1, .p2_fast = 14 },
401};
402
6b4bf1c4
VS		 403static void vlv_clock(int refclk, intel_clock_t *clock)
404{
405 clock->m = clock->m1 * clock->m2;
406 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 407 if (WARN_ON(clock->n == 0 || clock->p == 0))
408 return;
fb03ac01
VS		 409 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
410 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 411}
412
e0638cdf
PZ		 413/**
414 * Returns whether any output on the specified pipe is of the specified type
415 */
4093561b 416bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 417{
409ee761 418 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 419 struct intel_encoder *encoder;
420
409ee761 421 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 422 if (encoder->type == type)
423 return true;
424
425 return false;
426}
427
d0737e1d
ACO		 428/**
429 * Returns whether any output on the specified pipe will have the specified
430 * type after a staged modeset is complete, i.e., the same as
431 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
432 * encoder->crtc.
433 */
a93e255f
ACO		 434static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
435 int type)
d0737e1d 436{
a93e255f
ACO		 437 struct drm_atomic_state *state = crtc_state->base.state;
438 struct drm_connector_state *connector_state;
d0737e1d 439 struct intel_encoder *encoder;
a93e255f
ACO		 440 int i, num_connectors = 0;
441
442 for (i = 0; i < state->num_connector; i++) {
443 if (!state->connectors[i])
444 continue;
445
446 connector_state = state->connector_states[i];
447 if (connector_state->crtc != crtc_state->base.crtc)
448 continue;
449
450 num_connectors++;
d0737e1d 451
a93e255f
ACO		 452 encoder = to_intel_encoder(connector_state->best_encoder);
453 if (encoder->type == type)
d0737e1d 454 return true;
a93e255f
ACO		 455 }
456
457 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 458
459 return false;
460}
461
a93e255f
ACO		 462static const intel_limit_t *
463intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 464{
a93e255f 465 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 466 const intel_limit_t *limit;
b91ad0ec 467
a93e255f 468 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 469 if (intel_is_dual_link_lvds(dev)) {
1b894b59 470 if (refclk == 100000)
b91ad0ec
ZW		 471 limit = &intel_limits_ironlake_dual_lvds_100m;
472 else
473 limit = &intel_limits_ironlake_dual_lvds;
474 } else {
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_single_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_single_lvds;
479 }
c6bb3538 480 } else
b91ad0ec 481 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 482
483 return limit;
484}
485
a93e255f
ACO		 486static const intel_limit_t *
487intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 488{
a93e255f 489 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 490 const intel_limit_t *limit;
491
a93e255f 492 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 493 if (intel_is_dual_link_lvds(dev))
e4b36699 494 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 495 else
e4b36699 496 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 497 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
498 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 499 limit = &intel_limits_g4x_hdmi;
a93e255f 500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 501 limit = &intel_limits_g4x_sdvo;
044c7c41 502 } else /* The option is for other outputs */
e4b36699 503 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 504
505 return limit;
506}
507
a93e255f
ACO		 508static const intel_limit_t *
509intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 510{
a93e255f 511 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 512 const intel_limit_t *limit;
513
bad720ff 514 if (HAS_PCH_SPLIT(dev))
a93e255f 515 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 516 else if (IS_G4X(dev)) {
a93e255f 517 limit = intel_g4x_limit(crtc_state);
f2b115e6 518 } else if (IS_PINEVIEW(dev)) {
a93e255f 519 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 520 limit = &intel_limits_pineview_lvds;
2177832f 521 else
f2b115e6 522 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 523 } else if (IS_CHERRYVIEW(dev)) {
524 limit = &intel_limits_chv;
a0c4da24 525 } else if (IS_VALLEYVIEW(dev)) {
dc730512 526 limit = &intel_limits_vlv;
a6c45cf0 527 } else if (!IS_GEN2(dev)) {
a93e255f 528 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 529 limit = &intel_limits_i9xx_lvds;
530 else
531 limit = &intel_limits_i9xx_sdvo;
79e53945 532 } else {
a93e255f 533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 534 limit = &intel_limits_i8xx_lvds;
a93e255f 535 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 536 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 537 else
538 limit = &intel_limits_i8xx_dac;
79e53945
JB		 539 }
540 return limit;
541}
542
f2b115e6
AJ		 543/* m1 is reserved as 0 in Pineview, n is a ring counter */
544static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 545{
2177832f
SL		 546 clock->m = clock->m2 + 2;
547 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 548 if (WARN_ON(clock->n == 0 || clock->p == 0))
549 return;
fb03ac01
VS		 550 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
551 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 552}
553
7429e9d4
DV		 554static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
555{
556 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
557}
558
ac58c3f0 559static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 560{
7429e9d4 561 clock->m = i9xx_dpll_compute_m(clock);
79e53945 562 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 563 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
564 return;
fb03ac01
VS		 565 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
566 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 567}
568
ef9348c8
CML		 569static void chv_clock(int refclk, intel_clock_t *clock)
570{
571 clock->m = clock->m1 * clock->m2;
572 clock->p = clock->p1 * clock->p2;
573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
575 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
576 clock->n << 22);
577 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
578}
579
7c04d1d9 580#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 581/**
582 * Returns whether the given set of divisors are valid for a given refclk with
583 * the given connectors.
584 */
585
1b894b59
CW		 586static bool intel_PLL_is_valid(struct drm_device *dev,
587 const intel_limit_t *limit,
588 const intel_clock_t *clock)
79e53945 589{
f01b7962
VS		 590 if (clock->n < limit->n.min || limit->n.max < clock->n)
591 INTELPllInvalid("n out of range\n");
79e53945 592 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 593 INTELPllInvalid("p1 out of range\n");
79e53945 594 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 595 INTELPllInvalid("m2 out of range\n");
79e53945 596 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 597 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 598
599 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
600 if (clock->m1 <= clock->m2)
601 INTELPllInvalid("m1 <= m2\n");
602
603 if (!IS_VALLEYVIEW(dev)) {
604 if (clock->p < limit->p.min || limit->p.max < clock->p)
605 INTELPllInvalid("p out of range\n");
606 if (clock->m < limit->m.min || limit->m.max < clock->m)
607 INTELPllInvalid("m out of range\n");
608 }
609
79e53945 610 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 611 INTELPllInvalid("vco out of range\n");
79e53945
JB		 612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
614 */
615 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 616 INTELPllInvalid("dot out of range\n");
79e53945
JB		 617
618 return true;
619}
620
d4906093 621static bool
a93e255f
ACO		 622i9xx_find_best_dpll(const intel_limit_t *limit,
623 struct intel_crtc_state *crtc_state,
cec2f356
SP		 624 int target, int refclk, intel_clock_t *match_clock,
625 intel_clock_t *best_clock)
79e53945 626{
a93e255f 627 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 628 struct drm_device *dev = crtc->base.dev;
79e53945 629 intel_clock_t clock;
79e53945
JB		 630 int err = target;
631
a93e255f 632 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 633 /*
a210b028
DV		 634 * For LVDS just rely on its current settings for dual-channel.
635 * We haven't figured out how to reliably set up different
636 * single/dual channel state, if we even can.
79e53945 637 */
1974cad0 638 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 639 clock.p2 = limit->p2.p2_fast;
640 else
641 clock.p2 = limit->p2.p2_slow;
642 } else {
643 if (target < limit->p2.dot_limit)
644 clock.p2 = limit->p2.p2_slow;
645 else
646 clock.p2 = limit->p2.p2_fast;
647 }
648
0206e353 649 memset(best_clock, 0, sizeof(*best_clock));
79e53945 650
42158660
ZY		 651 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
652 clock.m1++) {
653 for (clock.m2 = limit->m2.min;
654 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 655 if (clock.m2 >= clock.m1)
42158660
ZY		 656 break;
657 for (clock.n = limit->n.min;
658 clock.n <= limit->n.max; clock.n++) {
659 for (clock.p1 = limit->p1.min;
660 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 661 int this_err;
662
ac58c3f0
DV		 663 i9xx_clock(refclk, &clock);
664 if (!intel_PLL_is_valid(dev, limit,
665 &clock))
666 continue;
667 if (match_clock &&
668 clock.p != match_clock->p)
669 continue;
670
671 this_err = abs(clock.dot - target);
672 if (this_err < err) {
673 *best_clock = clock;
674 err = this_err;
675 }
676 }
677 }
678 }
679 }
680
681 return (err != target);
682}
683
684static bool
a93e255f
ACO		 685pnv_find_best_dpll(const intel_limit_t *limit,
686 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 687 int target, int refclk, intel_clock_t *match_clock,
688 intel_clock_t *best_clock)
79e53945 689{
a93e255f 690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 691 struct drm_device *dev = crtc->base.dev;
79e53945 692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
a93e255f 695 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 696 /*
a210b028
DV		 697 * For LVDS just rely on its current settings for dual-channel.
698 * We haven't figured out how to reliably set up different
699 * single/dual channel state, if we even can.
79e53945 700 */
1974cad0 701 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 702 clock.p2 = limit->p2.p2_fast;
703 else
704 clock.p2 = limit->p2.p2_slow;
705 } else {
706 if (target < limit->p2.dot_limit)
707 clock.p2 = limit->p2.p2_slow;
708 else
709 clock.p2 = limit->p2.p2_fast;
710 }
711
0206e353 712 memset(best_clock, 0, sizeof(*best_clock));
79e53945 713
42158660
ZY		 714 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
715 clock.m1++) {
716 for (clock.m2 = limit->m2.min;
717 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 718 for (clock.n = limit->n.min;
719 clock.n <= limit->n.max; clock.n++) {
720 for (clock.p1 = limit->p1.min;
721 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 722 int this_err;
723
ac58c3f0 724 pineview_clock(refclk, &clock);
1b894b59
CW		 725 if (!intel_PLL_is_valid(dev, limit,
726 &clock))
79e53945 727 continue;
cec2f356
SP		 728 if (match_clock &&
729 clock.p != match_clock->p)
730 continue;
79e53945
JB		 731
732 this_err = abs(clock.dot - target);
733 if (this_err < err) {
734 *best_clock = clock;
735 err = this_err;
736 }
737 }
738 }
739 }
740 }
741
742 return (err != target);
743}
744
d4906093 745static bool
a93e255f
ACO		 746g4x_find_best_dpll(const intel_limit_t *limit,
747 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 748 int target, int refclk, intel_clock_t *match_clock,
749 intel_clock_t *best_clock)
d4906093 750{
a93e255f 751 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 752 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 753 intel_clock_t clock;
754 int max_n;
755 bool found;
6ba770dc
AJ		 756 /* approximately equals target * 0.00585 */
757 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 758 found = false;
759
a93e255f 760 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 761 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 762 clock.p2 = limit->p2.p2_fast;
763 else
764 clock.p2 = limit->p2.p2_slow;
765 } else {
766 if (target < limit->p2.dot_limit)
767 clock.p2 = limit->p2.p2_slow;
768 else
769 clock.p2 = limit->p2.p2_fast;
770 }
771
772 memset(best_clock, 0, sizeof(*best_clock));
773 max_n = limit->n.max;
f77f13e2 774 /* based on hardware requirement, prefer smaller n to precision */
d4906093 775 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 776 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 777 for (clock.m1 = limit->m1.max;
778 clock.m1 >= limit->m1.min; clock.m1--) {
779 for (clock.m2 = limit->m2.max;
780 clock.m2 >= limit->m2.min; clock.m2--) {
781 for (clock.p1 = limit->p1.max;
782 clock.p1 >= limit->p1.min; clock.p1--) {
783 int this_err;
784
ac58c3f0 785 i9xx_clock(refclk, &clock);
1b894b59
CW		 786 if (!intel_PLL_is_valid(dev, limit,
787 &clock))
d4906093 788 continue;
1b894b59
CW		 789
790 this_err = abs(clock.dot - target);
d4906093
ML		 791 if (this_err < err_most) {
792 *best_clock = clock;
793 err_most = this_err;
794 max_n = clock.n;
795 found = true;
796 }
797 }
798 }
799 }
800 }
2c07245f
ZW		 801 return found;
802}
803
d5dd62bd
ID		 804/*
805 * Check if the calculated PLL configuration is more optimal compared to the
806 * best configuration and error found so far. Return the calculated error.
807 */
808static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
809 const intel_clock_t *calculated_clock,
810 const intel_clock_t *best_clock,
811 unsigned int best_error_ppm,
812 unsigned int *error_ppm)
813{
9ca3ba01
ID		 814 /*
815 * For CHV ignore the error and consider only the P value.
816 * Prefer a bigger P value based on HW requirements.
817 */
818 if (IS_CHERRYVIEW(dev)) {
819 *error_ppm = 0;
820
821 return calculated_clock->p > best_clock->p;
822 }
823
24be4e46
ID		 824 if (WARN_ON_ONCE(!target_freq))
825 return false;
826
d5dd62bd
ID		 827 *error_ppm = div_u64(1000000ULL *
828 abs(target_freq - calculated_clock->dot),
829 target_freq);
830 /*
831 * Prefer a better P value over a better (smaller) error if the error
832 * is small. Ensure this preference for future configurations too by
833 * setting the error to 0.
834 */
835 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
836 *error_ppm = 0;
837
838 return true;
839 }
840
841 return *error_ppm + 10 < best_error_ppm;
842}
843
a0c4da24 844static bool
a93e255f
ACO		 845vlv_find_best_dpll(const intel_limit_t *limit,
846 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a0c4da24 849{
a93e255f 850 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 851 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 852 intel_clock_t clock;
69e4f900 853 unsigned int bestppm = 1000000;
27e639bf
VS		 854 /* min update 19.2 MHz */
855 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 856 bool found = false;
a0c4da24 857
6b4bf1c4
VS		 858 target *= 5; /* fast clock */
859
860 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 861
862 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 863 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 864 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 865 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 866 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 867 clock.p = clock.p1 * clock.p2;
a0c4da24 868 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 869 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 870 unsigned int ppm;
69e4f900 871
6b4bf1c4
VS		 872 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
873 refclk * clock.m1);
874
875 vlv_clock(refclk, &clock);
43b0ac53 876
f01b7962
VS		 877 if (!intel_PLL_is_valid(dev, limit,
878 &clock))
43b0ac53
VS		 879 continue;
880
d5dd62bd
ID		 881 if (!vlv_PLL_is_optimal(dev, target,
882 &clock,
883 best_clock,
884 bestppm, &ppm))
885 continue;
6b4bf1c4 886
d5dd62bd
ID		 887 *best_clock = clock;
888 bestppm = ppm;
889 found = true;
a0c4da24
JB		 890 }
891 }
892 }
893 }
a0c4da24 894
49e497ef 895 return found;
a0c4da24 896}
a4fc5ed6 897
ef9348c8 898static bool
a93e255f
ACO		 899chv_find_best_dpll(const intel_limit_t *limit,
900 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 901 int target, int refclk, intel_clock_t *match_clock,
902 intel_clock_t *best_clock)
903{
a93e255f 904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 905 struct drm_device *dev = crtc->base.dev;
9ca3ba01 906 unsigned int best_error_ppm;
ef9348c8
CML		 907 intel_clock_t clock;
908 uint64_t m2;
909 int found = false;
910
911 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 912 best_error_ppm = 1000000;
ef9348c8
CML		 913
914 /*
915 * Based on hardware doc, the n always set to 1, and m1 always
916 * set to 2. If requires to support 200Mhz refclk, we need to
917 * revisit this because n may not 1 anymore.
918 */
919 clock.n = 1, clock.m1 = 2;
920 target *= 5; /* fast clock */
921
922 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
923 for (clock.p2 = limit->p2.p2_fast;
924 clock.p2 >= limit->p2.p2_slow;
925 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 926 unsigned int error_ppm;
ef9348c8
CML		 927
928 clock.p = clock.p1 * clock.p2;
929
930 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
931 clock.n) << 22, refclk * clock.m1);
932
933 if (m2 > INT_MAX/clock.m1)
934 continue;
935
936 clock.m2 = m2;
937
938 chv_clock(refclk, &clock);
939
940 if (!intel_PLL_is_valid(dev, limit, &clock))
941 continue;
942
9ca3ba01
ID		 943 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
944 best_error_ppm, &error_ppm))
945 continue;
946
947 *best_clock = clock;
948 best_error_ppm = error_ppm;
949 found = true;
ef9348c8
CML		 950 }
951 }
952
953 return found;
954}
955
20ddf665
VS		 956bool intel_crtc_active(struct drm_crtc *crtc)
957{
958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
959
960 /* Be paranoid as we can arrive here with only partial
961 * state retrieved from the hardware during setup.
962 *
241bfc38 963 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 964 * as Haswell has gained clock readout/fastboot support.
965 *
66e514c1 966 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 967 * properly reconstruct framebuffers.
c3d1f436
MR		 968 *
969 * FIXME: The intel_crtc->active here should be switched to
970 * crtc->state->active once we have proper CRTC states wired up
971 * for atomic.
20ddf665 972 */
c3d1f436 973 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 974 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 975}
976
a5c961d1
PZ		 977enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
978 enum pipe pipe)
979{
980 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
982
6e3c9717 983 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 984}
985
fbf49ea2
VS		 986static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
987{
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 u32 reg = PIPEDSL(pipe);
990 u32 line1, line2;
991 u32 line_mask;
992
993 if (IS_GEN2(dev))
994 line_mask = DSL_LINEMASK_GEN2;
995 else
996 line_mask = DSL_LINEMASK_GEN3;
997
998 line1 = I915_READ(reg) & line_mask;
999 mdelay(5);
1000 line2 = I915_READ(reg) & line_mask;
1001
1002 return line1 == line2;
1003}
1004
ab7ad7f6
KP		 1005/*
1006 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1007 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1008 *
1009 * After disabling a pipe, we can't wait for vblank in the usual way,
1010 * spinning on the vblank interrupt status bit, since we won't actually
1011 * see an interrupt when the pipe is disabled.
1012 *
ab7ad7f6
KP		 1013 * On Gen4 and above:
1014 * wait for the pipe register state bit to turn off
1015 *
1016 * Otherwise:
1017 * wait for the display line value to settle (it usually
1018 * ends up stopping at the start of the next frame).
58e10eb9 1019 *
9d0498a2 1020 */
575f7ab7 1021static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1022{
575f7ab7 1023 struct drm_device *dev = crtc->base.dev;
9d0498a2 1024 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1025 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1026 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1027
1028 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1029 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1030
1031 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1032 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1033 100))
284637d9 1034 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1035 } else {
ab7ad7f6 1036 /* Wait for the display line to settle */
fbf49ea2 1037 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1038 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1039 }
79e53945
JB		 1040}
1041
b0ea7d37
DL		 1042/*
1043 * ibx_digital_port_connected - is the specified port connected?
1044 * @dev_priv: i915 private structure
1045 * @port: the port to test
1046 *
1047 * Returns true if @port is connected, false otherwise.
1048 */
1049bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1050 struct intel_digital_port *port)
1051{
1052 u32 bit;
1053
c36346e3 1054 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1055 switch (port->port) {
c36346e3
DL		 1056 case PORT_B:
1057 bit = SDE_PORTB_HOTPLUG;
1058 break;
1059 case PORT_C:
1060 bit = SDE_PORTC_HOTPLUG;
1061 break;
1062 case PORT_D:
1063 bit = SDE_PORTD_HOTPLUG;
1064 break;
1065 default:
1066 return true;
1067 }
1068 } else {
eba905b2 1069 switch (port->port) {
c36346e3
DL		 1070 case PORT_B:
1071 bit = SDE_PORTB_HOTPLUG_CPT;
1072 break;
1073 case PORT_C:
1074 bit = SDE_PORTC_HOTPLUG_CPT;
1075 break;
1076 case PORT_D:
1077 bit = SDE_PORTD_HOTPLUG_CPT;
1078 break;
1079 default:
1080 return true;
1081 }
b0ea7d37
DL		 1082 }
1083
1084 return I915_READ(SDEISR) & bit;
1085}
1086
b24e7179
JB		 1087static const char *state_string(bool enabled)
1088{
1089 return enabled ? "on" : "off";
1090}
1091
1092/* Only for pre-ILK configs */
55607e8a
DV		 1093void assert_pll(struct drm_i915_private *dev_priv,
1094 enum pipe pipe, bool state)
b24e7179
JB		 1095{
1096 int reg;
1097 u32 val;
1098 bool cur_state;
1099
1100 reg = DPLL(pipe);
1101 val = I915_READ(reg);
1102 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1103 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1104 "PLL state assertion failure (expected %s, current %s)\n",
1105 state_string(state), state_string(cur_state));
1106}
b24e7179 1107
23538ef1
JN		 1108/* XXX: the dsi pll is shared between MIPI DSI ports */
1109static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1110{
1111 u32 val;
1112 bool cur_state;
1113
1114 mutex_lock(&dev_priv->dpio_lock);
1115 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1116 mutex_unlock(&dev_priv->dpio_lock);
1117
1118 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1119 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1120 "DSI PLL state assertion failure (expected %s, current %s)\n",
1121 state_string(state), state_string(cur_state));
1122}
1123#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1124#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1125
55607e8a 1126struct intel_shared_dpll *
e2b78267
DV		 1127intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1128{
1129 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1130
6e3c9717 1131 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1132 return NULL;
1133
6e3c9717 1134 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1135}
1136
040484af 1137/* For ILK+ */
55607e8a
DV		 1138void assert_shared_dpll(struct drm_i915_private *dev_priv,
1139 struct intel_shared_dpll *pll,
1140 bool state)
040484af 1141{
040484af 1142 bool cur_state;
5358901f 1143 struct intel_dpll_hw_state hw_state;
040484af 1144
92b27b08 1145 if (WARN (!pll,
46edb027 1146 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1147 return;
ee7b9f93 1148
5358901f 1149 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1150 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1151 "%s assertion failure (expected %s, current %s)\n",
1152 pll->name, state_string(state), state_string(cur_state));
040484af 1153}
040484af
JB		 1154
1155static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1156 enum pipe pipe, bool state)
1157{
1158 int reg;
1159 u32 val;
1160 bool cur_state;
ad80a810
PZ		 1161 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1162 pipe);
040484af 1163
affa9354
PZ		 1164 if (HAS_DDI(dev_priv->dev)) {
1165 /* DDI does not have a specific FDI_TX register */
ad80a810 1166 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1167 val = I915_READ(reg);
ad80a810 1168 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1169 } else {
1170 reg = FDI_TX_CTL(pipe);
1171 val = I915_READ(reg);
1172 cur_state = !!(val & FDI_TX_ENABLE);
1173 }
e2c719b7 1174 I915_STATE_WARN(cur_state != state,
040484af
JB		 1175 "FDI TX state assertion failure (expected %s, current %s)\n",
1176 state_string(state), state_string(cur_state));
1177}
1178#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1180
1181static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, bool state)
1183{
1184 int reg;
1185 u32 val;
1186 bool cur_state;
1187
d63fa0dc
PZ		 1188 reg = FDI_RX_CTL(pipe);
1189 val = I915_READ(reg);
1190 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1191 I915_STATE_WARN(cur_state != state,
040484af
JB		 1192 "FDI RX state assertion failure (expected %s, current %s)\n",
1193 state_string(state), state_string(cur_state));
1194}
1195#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1196#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1197
1198static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1199 enum pipe pipe)
1200{
1201 int reg;
1202 u32 val;
1203
1204 /* ILK FDI PLL is always enabled */
3d13ef2e 1205 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1206 return;
1207
bf507ef7 1208 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1209 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1210 return;
1211
040484af
JB		 1212 reg = FDI_TX_CTL(pipe);
1213 val = I915_READ(reg);
e2c719b7 1214 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1215}
1216
55607e8a
DV		 1217void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
040484af
JB		 1219{
1220 int reg;
1221 u32 val;
55607e8a 1222 bool cur_state;
040484af
JB		 1223
1224 reg = FDI_RX_CTL(pipe);
1225 val = I915_READ(reg);
55607e8a 1226 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1227 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1228 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1229 state_string(state), state_string(cur_state));
040484af
JB		 1230}
1231
b680c37a
DV		 1232void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
ea0760cf 1234{
bedd4dba
JN		 1235 struct drm_device *dev = dev_priv->dev;
1236 int pp_reg;
ea0760cf
JB		 1237 u32 val;
1238 enum pipe panel_pipe = PIPE_A;
0de3b485 1239 bool locked = true;
ea0760cf 1240
bedd4dba
JN		 1241 if (WARN_ON(HAS_DDI(dev)))
1242 return;
1243
1244 if (HAS_PCH_SPLIT(dev)) {
1245 u32 port_sel;
1246
ea0760cf 1247 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1248 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1249
1250 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1251 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1252 panel_pipe = PIPE_B;
1253 /* XXX: else fix for eDP */
1254 } else if (IS_VALLEYVIEW(dev)) {
1255 /* presumably write lock depends on pipe, not port select */
1256 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1257 panel_pipe = pipe;
ea0760cf
JB		 1258 } else {
1259 pp_reg = PP_CONTROL;
bedd4dba
JN		 1260 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1261 panel_pipe = PIPE_B;
ea0760cf
JB		 1262 }
1263
1264 val = I915_READ(pp_reg);
1265 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1266 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1267 locked = false;
1268
e2c719b7 1269 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1270 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1271 pipe_name(pipe));
ea0760cf
JB		 1272}
1273
93ce0ba6
JN		 1274static void assert_cursor(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, bool state)
1276{
1277 struct drm_device *dev = dev_priv->dev;
1278 bool cur_state;
1279
d9d82081 1280 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1281 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1282 else
5efb3e28 1283 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1284
e2c719b7 1285 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1286 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1287 pipe_name(pipe), state_string(state), state_string(cur_state));
1288}
1289#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1290#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1291
b840d907
JB		 1292void assert_pipe(struct drm_i915_private *dev_priv,
1293 enum pipe pipe, bool state)
b24e7179
JB		 1294{
1295 int reg;
1296 u32 val;
63d7bbe9 1297 bool cur_state;
702e7a56
PZ		 1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1299 pipe);
b24e7179 1300
b6b5d049
VS		 1301 /* if we need the pipe quirk it must be always on */
1302 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1303 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1304 state = true;
1305
f458ebbc 1306 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1307 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1308 cur_state = false;
1309 } else {
1310 reg = PIPECONF(cpu_transcoder);
1311 val = I915_READ(reg);
1312 cur_state = !!(val & PIPECONF_ENABLE);
1313 }
1314
e2c719b7 1315 I915_STATE_WARN(cur_state != state,
63d7bbe9 1316 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1317 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1318}
1319
931872fc
CW		 1320static void assert_plane(struct drm_i915_private *dev_priv,
1321 enum plane plane, bool state)
b24e7179
JB		 1322{
1323 int reg;
1324 u32 val;
931872fc 1325 bool cur_state;
b24e7179
JB		 1326
1327 reg = DSPCNTR(plane);
1328 val = I915_READ(reg);
931872fc 1329 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1330 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1333}
1334
931872fc
CW		 1335#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1337
b24e7179
JB		 1338static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1339 enum pipe pipe)
1340{
653e1026 1341 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1342 int reg, i;
1343 u32 val;
1344 int cur_pipe;
1345
653e1026
VS		 1346 /* Primary planes are fixed to pipes on gen4+ */
1347 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1348 reg = DSPCNTR(pipe);
1349 val = I915_READ(reg);
e2c719b7 1350 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1351 "plane %c assertion failure, should be disabled but not\n",
1352 plane_name(pipe));
19ec1358 1353 return;
28c05794 1354 }
19ec1358 1355
b24e7179 1356 /* Need to check both planes against the pipe */
055e393f 1357 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1358 reg = DSPCNTR(i);
1359 val = I915_READ(reg);
1360 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1361 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1362 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1363 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1364 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1365 }
1366}
1367
19332d7a
JB		 1368static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe)
1370{
20674eef 1371 struct drm_device *dev = dev_priv->dev;
1fe47785 1372 int reg, sprite;
19332d7a
JB		 1373 u32 val;
1374
7feb8b88 1375 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1376 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1377 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1378 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1379 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1380 sprite, pipe_name(pipe));
1381 }
1382 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1383 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1384 reg = SPCNTR(pipe, sprite);
20674eef 1385 val = I915_READ(reg);
e2c719b7 1386 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1388 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1389 }
1390 } else if (INTEL_INFO(dev)->gen >= 7) {
1391 reg = SPRCTL(pipe);
19332d7a 1392 val = I915_READ(reg);
e2c719b7 1393 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1394 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1395 plane_name(pipe), pipe_name(pipe));
1396 } else if (INTEL_INFO(dev)->gen >= 5) {
1397 reg = DVSCNTR(pipe);
19332d7a 1398 val = I915_READ(reg);
e2c719b7 1399 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1400 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1401 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1402 }
1403}
1404
08c71e5e
VS		 1405static void assert_vblank_disabled(struct drm_crtc *crtc)
1406{
e2c719b7 1407 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1408 drm_crtc_vblank_put(crtc);
1409}
1410
89eff4be 1411static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1412{
1413 u32 val;
1414 bool enabled;
1415
e2c719b7 1416 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1417
92f2584a
JB		 1418 val = I915_READ(PCH_DREF_CONTROL);
1419 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1420 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1421 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1422}
1423
ab9412ba
DV		 1424static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1425 enum pipe pipe)
92f2584a
JB		 1426{
1427 int reg;
1428 u32 val;
1429 bool enabled;
1430
ab9412ba 1431 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1432 val = I915_READ(reg);
1433 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1434 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1435 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1436 pipe_name(pipe));
92f2584a
JB		 1437}
1438
4e634389
KP		 1439static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1440 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1441{
1442 if ((val & DP_PORT_EN) == 0)
1443 return false;
1444
1445 if (HAS_PCH_CPT(dev_priv->dev)) {
1446 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1447 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1448 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1449 return false;
44f37d1f
CML		 1450 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1451 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1452 return false;
f0575e92
KP		 1453 } else {
1454 if ((val & DP_PIPE_MASK) != (pipe << 30))
1455 return false;
1456 }
1457 return true;
1458}
1459
1519b995
KP		 1460static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe, u32 val)
1462{
dc0fa718 1463 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1464 return false;
1465
1466 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1467 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1468 return false;
44f37d1f
CML		 1469 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1470 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1471 return false;
1519b995 1472 } else {
dc0fa718 1473 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1474 return false;
1475 }
1476 return true;
1477}
1478
1479static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1480 enum pipe pipe, u32 val)
1481{
1482 if ((val & LVDS_PORT_EN) == 0)
1483 return false;
1484
1485 if (HAS_PCH_CPT(dev_priv->dev)) {
1486 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1487 return false;
1488 } else {
1489 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1490 return false;
1491 }
1492 return true;
1493}
1494
1495static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1496 enum pipe pipe, u32 val)
1497{
1498 if ((val & ADPA_DAC_ENABLE) == 0)
1499 return false;
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
1501 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1502 return false;
1503 } else {
1504 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1505 return false;
1506 }
1507 return true;
1508}
1509
291906f1 1510static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1511 enum pipe pipe, int reg, u32 port_sel)
291906f1 1512{
47a05eca 1513 u32 val = I915_READ(reg);
e2c719b7 1514 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1515 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1516 reg, pipe_name(pipe));
de9a35ab 1517
e2c719b7 1518 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1519 && (val & DP_PIPEB_SELECT),
de9a35ab 1520 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1521}
1522
1523static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1524 enum pipe pipe, int reg)
1525{
47a05eca 1526 u32 val = I915_READ(reg);
e2c719b7 1527 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1528 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1529 reg, pipe_name(pipe));
de9a35ab 1530
e2c719b7 1531 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1532 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1533 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1534}
1535
1536static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1537 enum pipe pipe)
1538{
1539 int reg;
1540 u32 val;
291906f1 1541
f0575e92
KP		 1542 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1543 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1544 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1545
1546 reg = PCH_ADPA;
1547 val = I915_READ(reg);
e2c719b7 1548 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1549 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1550 pipe_name(pipe));
291906f1
JB		 1551
1552 reg = PCH_LVDS;
1553 val = I915_READ(reg);
e2c719b7 1554 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1555 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1556 pipe_name(pipe));
291906f1 1557
e2debe91
PZ		 1558 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1559 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1560 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1561}
1562
40e9cf64
JB		 1563static void intel_init_dpio(struct drm_device *dev)
1564{
1565 struct drm_i915_private *dev_priv = dev->dev_private;
1566
1567 if (!IS_VALLEYVIEW(dev))
1568 return;
1569
a09caddd
CML		 1570 /*
1571 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1572 * CHV x1 PHY (DP/HDMI D)
1573 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1574 */
1575 if (IS_CHERRYVIEW(dev)) {
1576 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1577 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1578 } else {
1579 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1580 }
5382f5f3
JB		 1581}
1582
d288f65f 1583static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1584 const struct intel_crtc_state *pipe_config)
87442f73 1585{
426115cf
DV		 1586 struct drm_device *dev = crtc->base.dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 int reg = DPLL(crtc->pipe);
d288f65f 1589 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1590
426115cf 1591 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1592
1593 /* No really, not for ILK+ */
1594 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1595
1596 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1597 if (IS_MOBILE(dev_priv->dev))
426115cf 1598 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1599
426115cf
DV		 1600 I915_WRITE(reg, dpll);
1601 POSTING_READ(reg);
1602 udelay(150);
1603
1604 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1605 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1606
d288f65f 1607 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1608 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1609
1610 /* We do this three times for luck */
426115cf 1611 I915_WRITE(reg, dpll);
87442f73
DV		 1612 POSTING_READ(reg);
1613 udelay(150); /* wait for warmup */
426115cf 1614 I915_WRITE(reg, dpll);
87442f73
DV		 1615 POSTING_READ(reg);
1616 udelay(150); /* wait for warmup */
426115cf 1617 I915_WRITE(reg, dpll);
87442f73
DV		 1618 POSTING_READ(reg);
1619 udelay(150); /* wait for warmup */
1620}
1621
d288f65f 1622static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1623 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1624{
1625 struct drm_device *dev = crtc->base.dev;
1626 struct drm_i915_private *dev_priv = dev->dev_private;
1627 int pipe = crtc->pipe;
1628 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1629 u32 tmp;
1630
1631 assert_pipe_disabled(dev_priv, crtc->pipe);
1632
1633 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1634
1635 mutex_lock(&dev_priv->dpio_lock);
1636
1637 /* Enable back the 10bit clock to display controller */
1638 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1639 tmp |= DPIO_DCLKP_EN;
1640 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1641
1642 /*
1643 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1644 */
1645 udelay(1);
1646
1647 /* Enable PLL */
d288f65f 1648 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1649
1650 /* Check PLL is locked */
a11b0703 1651 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1652 DRM_ERROR("PLL %d failed to lock\n", pipe);
1653
a11b0703 1654 /* not sure when this should be written */
d288f65f 1655 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1656 POSTING_READ(DPLL_MD(pipe));
1657
9d556c99
CML		 1658 mutex_unlock(&dev_priv->dpio_lock);
1659}
1660
1c4e0274
VS		 1661static int intel_num_dvo_pipes(struct drm_device *dev)
1662{
1663 struct intel_crtc *crtc;
1664 int count = 0;
1665
1666 for_each_intel_crtc(dev, crtc)
1667 count += crtc->active &&
409ee761 1668 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1669
1670 return count;
1671}
1672
66e3d5c0 1673static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1674{
66e3d5c0
DV		 1675 struct drm_device *dev = crtc->base.dev;
1676 struct drm_i915_private *dev_priv = dev->dev_private;
1677 int reg = DPLL(crtc->pipe);
6e3c9717 1678 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1679
66e3d5c0 1680 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1681
63d7bbe9 1682 /* No really, not for ILK+ */
3d13ef2e 1683 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1684
1685 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1686 if (IS_MOBILE(dev) && !IS_I830(dev))
1687 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1688
1c4e0274
VS		 1689 /* Enable DVO 2x clock on both PLLs if necessary */
1690 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1691 /*
1692 * It appears to be important that we don't enable this
1693 * for the current pipe before otherwise configuring the
1694 * PLL. No idea how this should be handled if multiple
1695 * DVO outputs are enabled simultaneosly.
1696 */
1697 dpll |= DPLL_DVO_2X_MODE;
1698 I915_WRITE(DPLL(!crtc->pipe),
1699 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1700 }
66e3d5c0
DV		 1701
1702 /* Wait for the clocks to stabilize. */
1703 POSTING_READ(reg);
1704 udelay(150);
1705
1706 if (INTEL_INFO(dev)->gen >= 4) {
1707 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1708 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1709 } else {
1710 /* The pixel multiplier can only be updated once the
1711 * DPLL is enabled and the clocks are stable.
1712 *
1713 * So write it again.
1714 */
1715 I915_WRITE(reg, dpll);
1716 }
63d7bbe9
JB		 1717
1718 /* We do this three times for luck */
66e3d5c0 1719 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1720 POSTING_READ(reg);
1721 udelay(150); /* wait for warmup */
66e3d5c0 1722 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1723 POSTING_READ(reg);
1724 udelay(150); /* wait for warmup */
66e3d5c0 1725 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1726 POSTING_READ(reg);
1727 udelay(150); /* wait for warmup */
1728}
1729
1730/**
50b44a44 1731 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe PLL to disable
1734 *
1735 * Disable the PLL for @pipe, making sure the pipe is off first.
1736 *
1737 * Note! This is for pre-ILK only.
1738 */
1c4e0274 1739static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1740{
1c4e0274
VS		 1741 struct drm_device *dev = crtc->base.dev;
1742 struct drm_i915_private *dev_priv = dev->dev_private;
1743 enum pipe pipe = crtc->pipe;
1744
1745 /* Disable DVO 2x clock on both PLLs if necessary */
1746 if (IS_I830(dev) &&
409ee761 1747 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1748 intel_num_dvo_pipes(dev) == 1) {
1749 I915_WRITE(DPLL(PIPE_B),
1750 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1751 I915_WRITE(DPLL(PIPE_A),
1752 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1753 }
1754
b6b5d049
VS		 1755 /* Don't disable pipe or pipe PLLs if needed */
1756 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1757 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1758 return;
1759
1760 /* Make sure the pipe isn't still relying on us */
1761 assert_pipe_disabled(dev_priv, pipe);
1762
50b44a44
DV		 1763 I915_WRITE(DPLL(pipe), 0);
1764 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1765}
1766
f6071166
JB		 1767static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1768{
1769 u32 val = 0;
1770
1771 /* Make sure the pipe isn't still relying on us */
1772 assert_pipe_disabled(dev_priv, pipe);
1773
e5cbfbfb
ID		 1774 /*
1775 * Leave integrated clock source and reference clock enabled for pipe B.
1776 * The latter is needed for VGA hotplug / manual detection.
1777 */
f6071166 1778 if (pipe == PIPE_B)
e5cbfbfb 1779 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1780 I915_WRITE(DPLL(pipe), val);
1781 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1782
1783}
1784
1785static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1786{
d752048d 1787 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1788 u32 val;
1789
a11b0703
VS		 1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1792
a11b0703 1793 /* Set PLL en = 0 */
d17ec4ce 1794 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1795 if (pipe != PIPE_A)
1796 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1797 I915_WRITE(DPLL(pipe), val);
1798 POSTING_READ(DPLL(pipe));
d752048d
VS		 1799
1800 mutex_lock(&dev_priv->dpio_lock);
1801
1802 /* Disable 10bit clock to display controller */
1803 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1804 val &= ~DPIO_DCLKP_EN;
1805 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1806
61407f6d
VS		 1807 /* disable left/right clock distribution */
1808 if (pipe != PIPE_B) {
1809 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1810 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1811 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1812 } else {
1813 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1814 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1815 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1816 }
1817
d752048d 1818 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1819}
1820
e4607fcf
CML		 1821void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1822 struct intel_digital_port *dport)
89b667f8
JB		 1823{
1824 u32 port_mask;
00fc31b7 1825 int dpll_reg;
89b667f8 1826
e4607fcf
CML		 1827 switch (dport->port) {
1828 case PORT_B:
89b667f8 1829 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1830 dpll_reg = DPLL(0);
e4607fcf
CML		 1831 break;
1832 case PORT_C:
89b667f8 1833 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1834 dpll_reg = DPLL(0);
1835 break;
1836 case PORT_D:
1837 port_mask = DPLL_PORTD_READY_MASK;
1838 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1839 break;
1840 default:
1841 BUG();
1842 }
89b667f8 1843
00fc31b7 1844 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1845 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1846 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1847}
1848
b14b1055
DV		 1849static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1850{
1851 struct drm_device *dev = crtc->base.dev;
1852 struct drm_i915_private *dev_priv = dev->dev_private;
1853 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1854
be19f0ff
CW		 1855 if (WARN_ON(pll == NULL))
1856 return;
1857
3e369b76 1858 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1859 if (pll->active == 0) {
1860 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1861 WARN_ON(pll->on);
1862 assert_shared_dpll_disabled(dev_priv, pll);
1863
1864 pll->mode_set(dev_priv, pll);
1865 }
1866}
1867
92f2584a 1868/**
85b3894f 1869 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1870 * @dev_priv: i915 private structure
1871 * @pipe: pipe PLL to enable
1872 *
1873 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1874 * drives the transcoder clock.
1875 */
85b3894f 1876static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1877{
3d13ef2e
DL		 1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1881
87a875bb 1882 if (WARN_ON(pll == NULL))
48da64a8
CW		 1883 return;
1884
3e369b76 1885 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1886 return;
ee7b9f93 1887
74dd6928 1888 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1889 pll->name, pll->active, pll->on,
e2b78267 1890 crtc->base.base.id);
92f2584a 1891
cdbd2316
DV		 1892 if (pll->active++) {
1893 WARN_ON(!pll->on);
e9d6944e 1894 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1895 return;
1896 }
f4a091c7 1897 WARN_ON(pll->on);
ee7b9f93 1898
bd2bb1b9
PZ		 1899 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1900
46edb027 1901 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1902 pll->enable(dev_priv, pll);
ee7b9f93 1903 pll->on = true;
92f2584a
JB		 1904}
1905
f6daaec2 1906static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1907{
3d13ef2e
DL		 1908 struct drm_device *dev = crtc->base.dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1910 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1911
92f2584a 1912 /* PCH only available on ILK+ */
3d13ef2e 1913 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1914 if (WARN_ON(pll == NULL))
ee7b9f93 1915 return;
92f2584a 1916
3e369b76 1917 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1918 return;
7a419866 1919
46edb027
DV		 1920 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1921 pll->name, pll->active, pll->on,
e2b78267 1922 crtc->base.base.id);
7a419866 1923
48da64a8 1924 if (WARN_ON(pll->active == 0)) {
e9d6944e 1925 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1926 return;
1927 }
1928
e9d6944e 1929 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1930 WARN_ON(!pll->on);
cdbd2316 1931 if (--pll->active)
7a419866 1932 return;
ee7b9f93 1933
46edb027 1934 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1935 pll->disable(dev_priv, pll);
ee7b9f93 1936 pll->on = false;
bd2bb1b9
PZ		 1937
1938 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1939}
1940
b8a4f404
PZ		 1941static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1942 enum pipe pipe)
040484af 1943{
23670b32 1944 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1945 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1946 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1947 uint32_t reg, val, pipeconf_val;
040484af
JB		 1948
1949 /* PCH only available on ILK+ */
55522f37 1950 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1951
1952 /* Make sure PCH DPLL is enabled */
e72f9fbf 1953 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1954 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1955
1956 /* FDI must be feeding us bits for PCH ports */
1957 assert_fdi_tx_enabled(dev_priv, pipe);
1958 assert_fdi_rx_enabled(dev_priv, pipe);
1959
23670b32
DV		 1960 if (HAS_PCH_CPT(dev)) {
1961 /* Workaround: Set the timing override bit before enabling the
1962 * pch transcoder. */
1963 reg = TRANS_CHICKEN2(pipe);
1964 val = I915_READ(reg);
1965 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1966 I915_WRITE(reg, val);
59c859d6 1967 }
23670b32 1968
ab9412ba 1969 reg = PCH_TRANSCONF(pipe);
040484af 1970 val = I915_READ(reg);
5f7f726d 1971 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1972
1973 if (HAS_PCH_IBX(dev_priv->dev)) {
1974 /*
1975 * make the BPC in transcoder be consistent with
1976 * that in pipeconf reg.
1977 */
dfd07d72
DV		 1978 val &= ~PIPECONF_BPC_MASK;
1979 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1980 }
5f7f726d
PZ		 1981
1982 val &= ~TRANS_INTERLACE_MASK;
1983 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1984 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1985 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1986 val |= TRANS_LEGACY_INTERLACED_ILK;
1987 else
1988 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1989 else
1990 val |= TRANS_PROGRESSIVE;
1991
040484af
JB		 1992 I915_WRITE(reg, val | TRANS_ENABLE);
1993 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1994 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1995}
1996
8fb033d7 1997static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1998 enum transcoder cpu_transcoder)
040484af 1999{
8fb033d7 2000 u32 val, pipeconf_val;
8fb033d7
PZ		 2001
2002 /* PCH only available on ILK+ */
55522f37 2003 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2004
8fb033d7 2005 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2006 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2007 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2008
223a6fdf
PZ		 2009 /* Workaround: set timing override bit. */
2010 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2011 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2012 I915_WRITE(_TRANSA_CHICKEN2, val);
2013
25f3ef11 2014 val = TRANS_ENABLE;
937bb610 2015 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2016
9a76b1c6
PZ		 2017 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2018 PIPECONF_INTERLACED_ILK)
a35f2679 2019 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
ab9412ba
DV		 2023 I915_WRITE(LPT_TRANSCONF, val);
2024 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2025 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2026}
2027
b8a4f404
PZ		 2028static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2029 enum pipe pipe)
040484af 2030{
23670b32
DV		 2031 struct drm_device *dev = dev_priv->dev;
2032 uint32_t reg, val;
040484af
JB		 2033
2034 /* FDI relies on the transcoder */
2035 assert_fdi_tx_disabled(dev_priv, pipe);
2036 assert_fdi_rx_disabled(dev_priv, pipe);
2037
291906f1
JB		 2038 /* Ports must be off as well */
2039 assert_pch_ports_disabled(dev_priv, pipe);
2040
ab9412ba 2041 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2042 val = I915_READ(reg);
2043 val &= ~TRANS_ENABLE;
2044 I915_WRITE(reg, val);
2045 /* wait for PCH transcoder off, transcoder state */
2046 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2047 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2048
2049 if (!HAS_PCH_IBX(dev)) {
2050 /* Workaround: Clear the timing override chicken bit again. */
2051 reg = TRANS_CHICKEN2(pipe);
2052 val = I915_READ(reg);
2053 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2054 I915_WRITE(reg, val);
2055 }
040484af
JB		 2056}
2057
ab4d966c 2058static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2059{
8fb033d7
PZ		 2060 u32 val;
2061
ab9412ba 2062 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2063 val &= ~TRANS_ENABLE;
ab9412ba 2064 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2065 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2066 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2067 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2068
2069 /* Workaround: clear timing override bit. */
2070 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2071 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2072 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2073}
2074
b24e7179 2075/**
309cfea8 2076 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2077 * @crtc: crtc responsible for the pipe
b24e7179 2078 *
0372264a 2079 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2080 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2081 */
e1fdc473 2082static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2083{
0372264a
PZ		 2084 struct drm_device *dev = crtc->base.dev;
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2087 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2088 pipe);
1a240d4d 2089 enum pipe pch_transcoder;
b24e7179
JB		 2090 int reg;
2091 u32 val;
2092
58c6eaa2 2093 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2094 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2095 assert_sprites_disabled(dev_priv, pipe);
2096
681e5811 2097 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2098 pch_transcoder = TRANSCODER_A;
2099 else
2100 pch_transcoder = pipe;
2101
b24e7179
JB		 2102 /*
2103 * A pipe without a PLL won't actually be able to drive bits from
2104 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2105 * need the check.
2106 */
2107 if (!HAS_PCH_SPLIT(dev_priv->dev))
409ee761 2108 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2109 assert_dsi_pll_enabled(dev_priv);
2110 else
2111 assert_pll_enabled(dev_priv, pipe);
040484af 2112 else {
6e3c9717 2113 if (crtc->config->has_pch_encoder) {
040484af 2114 /* if driving the PCH, we need FDI enabled */
cc391bbb 2115 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2116 assert_fdi_tx_pll_enabled(dev_priv,
2117 (enum pipe) cpu_transcoder);
040484af
JB		 2118 }
2119 /* FIXME: assert CPU port conditions for SNB+ */
2120 }
b24e7179 2121
702e7a56 2122 reg = PIPECONF(cpu_transcoder);
b24e7179 2123 val = I915_READ(reg);
7ad25d48 2124 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2125 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2126 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2127 return;
7ad25d48 2128 }
00d70b15
CW		 2129
2130 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2131 POSTING_READ(reg);
b24e7179
JB		 2132}
2133
2134/**
309cfea8 2135 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2136 * @crtc: crtc whose pipes is to be disabled
b24e7179 2137 *
575f7ab7
VS		 2138 * Disable the pipe of @crtc, making sure that various hardware
2139 * specific requirements are met, if applicable, e.g. plane
2140 * disabled, panel fitter off, etc.
b24e7179
JB		 2141 *
2142 * Will wait until the pipe has shut down before returning.
2143 */
575f7ab7 2144static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2145{
575f7ab7 2146 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2147 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2148 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2149 int reg;
2150 u32 val;
2151
2152 /*
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2155 */
2156 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2157 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2158 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2159
702e7a56 2160 reg = PIPECONF(cpu_transcoder);
b24e7179 2161 val = I915_READ(reg);
00d70b15
CW		 2162 if ((val & PIPECONF_ENABLE) == 0)
2163 return;
2164
67adc644
VS		 2165 /*
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2168 */
6e3c9717 2169 if (crtc->config->double_wide)
67adc644
VS		 2170 val &= ~PIPECONF_DOUBLE_WIDE;
2171
2172 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2173 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2174 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2175 val &= ~PIPECONF_ENABLE;
2176
2177 I915_WRITE(reg, val);
2178 if ((val & PIPECONF_ENABLE) == 0)
2179 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2180}
2181
d74362c9
KP		 2182/*
2183 * Plane regs are double buffered, going from enabled->disabled needs a
2184 * trigger in order to latch. The display address reg provides this.
2185 */
1dba99f4
VS		 2186void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2187 enum plane plane)
d74362c9 2188{
3d13ef2e
DL		 2189 struct drm_device *dev = dev_priv->dev;
2190 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2191
2192 I915_WRITE(reg, I915_READ(reg));
2193 POSTING_READ(reg);
d74362c9
KP		 2194}
2195
b24e7179 2196/**
262ca2b0 2197 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2198 * @plane: plane to be enabled
2199 * @crtc: crtc for the plane
b24e7179 2200 *
fdd508a6 2201 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2202 */
fdd508a6
VS		 2203static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2204 struct drm_crtc *crtc)
b24e7179 2205{
fdd508a6
VS		 2206 struct drm_device *dev = plane->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2209
2210 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2211 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2212
98ec7739
VS		 2213 if (intel_crtc->primary_enabled)
2214 return;
0037f71c 2215
4c445e0e 2216 intel_crtc->primary_enabled = true;
939c2fe8 2217
fdd508a6
VS		 2218 dev_priv->display.update_primary_plane(crtc, plane->fb,
2219 crtc->x, crtc->y);
33c3b0d1
VS		 2220
2221 /*
2222 * BDW signals flip done immediately if the plane
2223 * is disabled, even if the plane enable is already
2224 * armed to occur at the next vblank :(
2225 */
2226 if (IS_BROADWELL(dev))
2227 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2228}
2229
b24e7179 2230/**
262ca2b0 2231 * intel_disable_primary_hw_plane - disable the primary hardware plane
fdd508a6
VS		 2232 * @plane: plane to be disabled
2233 * @crtc: crtc for the plane
b24e7179 2234 *
fdd508a6 2235 * Disable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2236 */
fdd508a6
VS		 2237static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2238 struct drm_crtc *crtc)
b24e7179 2239{
fdd508a6
VS		 2240 struct drm_device *dev = plane->dev;
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2243
32b7eeec
MR		 2244 if (WARN_ON(!intel_crtc->active))
2245 return;
b24e7179 2246
98ec7739
VS		 2247 if (!intel_crtc->primary_enabled)
2248 return;
0037f71c 2249
4c445e0e 2250 intel_crtc->primary_enabled = false;
939c2fe8 2251
fdd508a6
VS		 2252 dev_priv->display.update_primary_plane(crtc, plane->fb,
2253 crtc->x, crtc->y);
b24e7179
JB		 2254}
2255
693db184
CW		 2256static bool need_vtd_wa(struct drm_device *dev)
2257{
2258#ifdef CONFIG_INTEL_IOMMU
2259 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2260 return true;
2261#endif
2262 return false;
2263}
2264
50470bb0 2265unsigned int
6761dd31
TU		 2266intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2267 uint64_t fb_format_modifier)
a57ce0b2 2268{
6761dd31
TU		 2269 unsigned int tile_height;
2270 uint32_t pixel_bytes;
a57ce0b2 2271
b5d0e9bf
DL		 2272 switch (fb_format_modifier) {
2273 case DRM_FORMAT_MOD_NONE:
2274 tile_height = 1;
2275 break;
2276 case I915_FORMAT_MOD_X_TILED:
2277 tile_height = IS_GEN2(dev) ? 16 : 8;
2278 break;
2279 case I915_FORMAT_MOD_Y_TILED:
2280 tile_height = 32;
2281 break;
2282 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2283 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2284 switch (pixel_bytes) {
b5d0e9bf 2285 default:
6761dd31 2286 case 1:
b5d0e9bf
DL		 2287 tile_height = 64;
2288 break;
6761dd31
TU		 2289 case 2:
2290 case 4:
b5d0e9bf
DL		 2291 tile_height = 32;
2292 break;
6761dd31 2293 case 8:
b5d0e9bf
DL		 2294 tile_height = 16;
2295 break;
6761dd31 2296 case 16:
b5d0e9bf
DL		 2297 WARN_ONCE(1,
2298 "128-bit pixels are not supported for display!");
2299 tile_height = 16;
2300 break;
2301 }
2302 break;
2303 default:
2304 MISSING_CASE(fb_format_modifier);
2305 tile_height = 1;
2306 break;
2307 }
091df6cb 2308
6761dd31
TU		 2309 return tile_height;
2310}
2311
2312unsigned int
2313intel_fb_align_height(struct drm_device *dev, unsigned int height,
2314 uint32_t pixel_format, uint64_t fb_format_modifier)
2315{
2316 return ALIGN(height, intel_tile_height(dev, pixel_format,
2317 fb_format_modifier));
a57ce0b2
JB		 2318}
2319
f64b98cd
TU		 2320static int
2321intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2322 const struct drm_plane_state *plane_state)
2323{
50470bb0 2324 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2325
f64b98cd
TU		 2326 *view = i915_ggtt_view_normal;
2327
50470bb0
TU		 2328 if (!plane_state)
2329 return 0;
2330
121920fa 2331 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2332 return 0;
2333
9abc4648 2334 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2335
2336 info->height = fb->height;
2337 info->pixel_format = fb->pixel_format;
2338 info->pitch = fb->pitches[0];
2339 info->fb_modifier = fb->modifier[0];
2340
2341 if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2342 info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2343 DRM_DEBUG_KMS(
2344 "Y or Yf tiling is needed for 90/270 rotation!\n");
2345 return -EINVAL;
2346 }
2347
f64b98cd
TU		 2348 return 0;
2349}
2350
127bd2ac 2351int
850c4cdc
TU		 2352intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2353 struct drm_framebuffer *fb,
82bc3b2d 2354 const struct drm_plane_state *plane_state,
a4872ba6 2355 struct intel_engine_cs *pipelined)
6b95a207 2356{
850c4cdc 2357 struct drm_device *dev = fb->dev;
ce453d81 2358 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2359 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2360 struct i915_ggtt_view view;
6b95a207
KH		 2361 u32 alignment;
2362 int ret;
2363
ebcdd39e
MR		 2364 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2365
7b911adc
TU		 2366 switch (fb->modifier[0]) {
2367 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2368 if (INTEL_INFO(dev)->gen >= 9)
2369 alignment = 256 * 1024;
2370 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2371 alignment = 128 * 1024;
a6c45cf0 2372 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2373 alignment = 4 * 1024;
2374 else
2375 alignment = 64 * 1024;
6b95a207 2376 break;
7b911adc 2377 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2378 if (INTEL_INFO(dev)->gen >= 9)
2379 alignment = 256 * 1024;
2380 else {
2381 /* pin() will align the object as required by fence */
2382 alignment = 0;
2383 }
6b95a207 2384 break;
7b911adc 2385 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2386 case I915_FORMAT_MOD_Yf_TILED:
2387 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2388 "Y tiling bo slipped through, driver bug!\n"))
2389 return -EINVAL;
2390 alignment = 1 * 1024 * 1024;
2391 break;
6b95a207 2392 default:
7b911adc
TU		 2393 MISSING_CASE(fb->modifier[0]);
2394 return -EINVAL;
6b95a207
KH		 2395 }
2396
f64b98cd
TU		 2397 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2398 if (ret)
2399 return ret;
2400
693db184
CW		 2401 /* Note that the w/a also requires 64 PTE of padding following the
2402 * bo. We currently fill all unused PTE with the shadow page and so
2403 * we should always have valid PTE following the scanout preventing
2404 * the VT-d warning.
2405 */
2406 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2407 alignment = 256 * 1024;
2408
d6dd6843
PZ		 2409 /*
2410 * Global gtt pte registers are special registers which actually forward
2411 * writes to a chunk of system memory. Which means that there is no risk
2412 * that the register values disappear as soon as we call
2413 * intel_runtime_pm_put(), so it is correct to wrap only the
2414 * pin/unpin/fence and not more.
2415 */
2416 intel_runtime_pm_get(dev_priv);
2417
ce453d81 2418 dev_priv->mm.interruptible = false;
e6617330 2419 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2420 &view);
48b956c5 2421 if (ret)
ce453d81 2422 goto err_interruptible;
6b95a207
KH		 2423
2424 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2425 * fence, whereas 965+ only requires a fence if using
2426 * framebuffer compression. For simplicity, we always install
2427 * a fence as the cost is not that onerous.
2428 */
06d98131 2429 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2430 if (ret)
2431 goto err_unpin;
1690e1eb 2432
9a5a53b3 2433 i915_gem_object_pin_fence(obj);
6b95a207 2434
ce453d81 2435 dev_priv->mm.interruptible = true;
d6dd6843 2436 intel_runtime_pm_put(dev_priv);
6b95a207 2437 return 0;
48b956c5
CW		 2438
2439err_unpin:
f64b98cd 2440 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2441err_interruptible:
2442 dev_priv->mm.interruptible = true;
d6dd6843 2443 intel_runtime_pm_put(dev_priv);
48b956c5 2444 return ret;
6b95a207
KH		 2445}
2446
82bc3b2d
TU		 2447static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2448 const struct drm_plane_state *plane_state)
1690e1eb 2449{
82bc3b2d 2450 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2451 struct i915_ggtt_view view;
2452 int ret;
82bc3b2d 2453
ebcdd39e
MR		 2454 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2455
f64b98cd
TU		 2456 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2457 WARN_ONCE(ret, "Couldn't get view from plane state!");
2458
1690e1eb 2459 i915_gem_object_unpin_fence(obj);
f64b98cd 2460 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2461}
2462
c2c75131
DV		 2463/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2464 * is assumed to be a power-of-two. */
bc752862
CW		 2465unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2466 unsigned int tiling_mode,
2467 unsigned int cpp,
2468 unsigned int pitch)
c2c75131 2469{
bc752862
CW		 2470 if (tiling_mode != I915_TILING_NONE) {
2471 unsigned int tile_rows, tiles;
c2c75131 2472
bc752862
CW		 2473 tile_rows = *y / 8;
2474 *y %= 8;
c2c75131 2475
bc752862
CW		 2476 tiles = *x / (512/cpp);
2477 *x %= 512/cpp;
2478
2479 return tile_rows * pitch * 8 + tiles * 4096;
2480 } else {
2481 unsigned int offset;
2482
2483 offset = *y * pitch + *x * cpp;
2484 *y = 0;
2485 *x = (offset & 4095) / cpp;
2486 return offset & -4096;
2487 }
c2c75131
DV		 2488}
2489
b35d63fa 2490static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2491{
2492 switch (format) {
2493 case DISPPLANE_8BPP:
2494 return DRM_FORMAT_C8;
2495 case DISPPLANE_BGRX555:
2496 return DRM_FORMAT_XRGB1555;
2497 case DISPPLANE_BGRX565:
2498 return DRM_FORMAT_RGB565;
2499 default:
2500 case DISPPLANE_BGRX888:
2501 return DRM_FORMAT_XRGB8888;
2502 case DISPPLANE_RGBX888:
2503 return DRM_FORMAT_XBGR8888;
2504 case DISPPLANE_BGRX101010:
2505 return DRM_FORMAT_XRGB2101010;
2506 case DISPPLANE_RGBX101010:
2507 return DRM_FORMAT_XBGR2101010;
2508 }
2509}
2510
bc8d7dff
DL		 2511static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2512{
2513 switch (format) {
2514 case PLANE_CTL_FORMAT_RGB_565:
2515 return DRM_FORMAT_RGB565;
2516 default:
2517 case PLANE_CTL_FORMAT_XRGB_8888:
2518 if (rgb_order) {
2519 if (alpha)
2520 return DRM_FORMAT_ABGR8888;
2521 else
2522 return DRM_FORMAT_XBGR8888;
2523 } else {
2524 if (alpha)
2525 return DRM_FORMAT_ARGB8888;
2526 else
2527 return DRM_FORMAT_XRGB8888;
2528 }
2529 case PLANE_CTL_FORMAT_XRGB_2101010:
2530 if (rgb_order)
2531 return DRM_FORMAT_XBGR2101010;
2532 else
2533 return DRM_FORMAT_XRGB2101010;
2534 }
2535}
2536
5724dbd1 2537static bool
f6936e29
DV		 2538intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2539 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2540{
2541 struct drm_device *dev = crtc->base.dev;
2542 struct drm_i915_gem_object *obj = NULL;
2543 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2544 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2545 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2546 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2547 PAGE_SIZE);
2548
2549 size_aligned -= base_aligned;
46f297fb 2550
ff2652ea
CW		 2551 if (plane_config->size == 0)
2552 return false;
2553
f37b5c2b
DV		 2554 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2555 base_aligned,
2556 base_aligned,
2557 size_aligned);
46f297fb 2558 if (!obj)
484b41dd 2559 return false;
46f297fb 2560
49af449b
DL		 2561 obj->tiling_mode = plane_config->tiling;
2562 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2563 obj->stride = fb->pitches[0];
46f297fb 2564
6bf129df
DL		 2565 mode_cmd.pixel_format = fb->pixel_format;
2566 mode_cmd.width = fb->width;
2567 mode_cmd.height = fb->height;
2568 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2569 mode_cmd.modifier[0] = fb->modifier[0];
2570 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2571
2572 mutex_lock(&dev->struct_mutex);
6bf129df 2573 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2574 &mode_cmd, obj)) {
46f297fb
JB		 2575 DRM_DEBUG_KMS("intel fb init failed\n");
2576 goto out_unref_obj;
2577 }
46f297fb 2578 mutex_unlock(&dev->struct_mutex);
484b41dd 2579
f6936e29 2580 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2581 return true;
46f297fb
JB		 2582
2583out_unref_obj:
2584 drm_gem_object_unreference(&obj->base);
2585 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2586 return false;
2587}
2588
afd65eb4
MR		 2589/* Update plane->state->fb to match plane->fb after driver-internal updates */
2590static void
2591update_state_fb(struct drm_plane *plane)
2592{
2593 if (plane->fb == plane->state->fb)
2594 return;
2595
2596 if (plane->state->fb)
2597 drm_framebuffer_unreference(plane->state->fb);
2598 plane->state->fb = plane->fb;
2599 if (plane->state->fb)
2600 drm_framebuffer_reference(plane->state->fb);
2601}
2602
5724dbd1 2603static void
f6936e29
DV		 2604intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2605 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2606{
2607 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2608 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2609 struct drm_crtc *c;
2610 struct intel_crtc *i;
2ff8fde1 2611 struct drm_i915_gem_object *obj;
88595ac9
DV		 2612 struct drm_plane *primary = intel_crtc->base.primary;
2613 struct drm_framebuffer *fb;
484b41dd 2614
2d14030b 2615 if (!plane_config->fb)
484b41dd
JB		 2616 return;
2617
f6936e29 2618 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2619 fb = &plane_config->fb->base;
2620 goto valid_fb;
f55548b5 2621 }
484b41dd 2622
2d14030b 2623 kfree(plane_config->fb);
484b41dd
JB		 2624
2625 /*
2626 * Failed to alloc the obj, check to see if we should share
2627 * an fb with another CRTC instead
2628 */
70e1e0ec 2629 for_each_crtc(dev, c) {
484b41dd
JB		 2630 i = to_intel_crtc(c);
2631
2632 if (c == &intel_crtc->base)
2633 continue;
2634
2ff8fde1
MR		 2635 if (!i->active)
2636 continue;
2637
88595ac9
DV		 2638 fb = c->primary->fb;
2639 if (!fb)
484b41dd
JB		 2640 continue;
2641
88595ac9 2642 obj = intel_fb_obj(fb);
2ff8fde1 2643 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2644 drm_framebuffer_reference(fb);
2645 goto valid_fb;
484b41dd
JB		 2646 }
2647 }
88595ac9
DV		 2648
2649 return;
2650
2651valid_fb:
2652 obj = intel_fb_obj(fb);
2653 if (obj->tiling_mode != I915_TILING_NONE)
2654 dev_priv->preserve_bios_swizzle = true;
2655
2656 primary->fb = fb;
2657 primary->state->crtc = &intel_crtc->base;
2658 primary->crtc = &intel_crtc->base;
2659 update_state_fb(primary);
2660 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2661}
2662
29b9bde6
DV		 2663static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2664 struct drm_framebuffer *fb,
2665 int x, int y)
81255565
JB		 2666{
2667 struct drm_device *dev = crtc->dev;
2668 struct drm_i915_private *dev_priv = dev->dev_private;
2669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2670 struct drm_i915_gem_object *obj;
81255565 2671 int plane = intel_crtc->plane;
e506a0c6 2672 unsigned long linear_offset;
81255565 2673 u32 dspcntr;
f45651ba 2674 u32 reg = DSPCNTR(plane);
48404c1e 2675 int pixel_size;
f45651ba 2676
fdd508a6
VS		 2677 if (!intel_crtc->primary_enabled) {
2678 I915_WRITE(reg, 0);
2679 if (INTEL_INFO(dev)->gen >= 4)
2680 I915_WRITE(DSPSURF(plane), 0);
2681 else
2682 I915_WRITE(DSPADDR(plane), 0);
2683 POSTING_READ(reg);
2684 return;
2685 }
2686
c9ba6fad
VS		 2687 obj = intel_fb_obj(fb);
2688 if (WARN_ON(obj == NULL))
2689 return;
2690
2691 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2692
f45651ba
VS		 2693 dspcntr = DISPPLANE_GAMMA_ENABLE;
2694
fdd508a6 2695 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2696
2697 if (INTEL_INFO(dev)->gen < 4) {
2698 if (intel_crtc->pipe == PIPE_B)
2699 dspcntr |= DISPPLANE_SEL_PIPE_B;
2700
2701 /* pipesrc and dspsize control the size that is scaled from,
2702 * which should always be the user's requested size.
2703 */
2704 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2705 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2706 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2707 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2708 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2709 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2710 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2711 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2712 I915_WRITE(PRIMPOS(plane), 0);
2713 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2714 }
81255565 2715
57779d06
VS		 2716 switch (fb->pixel_format) {
2717 case DRM_FORMAT_C8:
81255565
JB		 2718 dspcntr |= DISPPLANE_8BPP;
2719 break;
57779d06
VS		 2720 case DRM_FORMAT_XRGB1555:
2721 case DRM_FORMAT_ARGB1555:
2722 dspcntr |= DISPPLANE_BGRX555;
81255565 2723 break;
57779d06
VS		 2724 case DRM_FORMAT_RGB565:
2725 dspcntr |= DISPPLANE_BGRX565;
2726 break;
2727 case DRM_FORMAT_XRGB8888:
2728 case DRM_FORMAT_ARGB8888:
2729 dspcntr |= DISPPLANE_BGRX888;
2730 break;
2731 case DRM_FORMAT_XBGR8888:
2732 case DRM_FORMAT_ABGR8888:
2733 dspcntr |= DISPPLANE_RGBX888;
2734 break;
2735 case DRM_FORMAT_XRGB2101010:
2736 case DRM_FORMAT_ARGB2101010:
2737 dspcntr |= DISPPLANE_BGRX101010;
2738 break;
2739 case DRM_FORMAT_XBGR2101010:
2740 case DRM_FORMAT_ABGR2101010:
2741 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2742 break;
2743 default:
baba133a 2744 BUG();
81255565 2745 }
57779d06 2746
f45651ba
VS		 2747 if (INTEL_INFO(dev)->gen >= 4 &&
2748 obj->tiling_mode != I915_TILING_NONE)
2749 dspcntr |= DISPPLANE_TILED;
81255565 2750
de1aa629
VS		 2751 if (IS_G4X(dev))
2752 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2753
b9897127 2754 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2755
c2c75131
DV		 2756 if (INTEL_INFO(dev)->gen >= 4) {
2757 intel_crtc->dspaddr_offset =
bc752862 2758 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2759 pixel_size,
bc752862 2760 fb->pitches[0]);
c2c75131
DV		 2761 linear_offset -= intel_crtc->dspaddr_offset;
2762 } else {
e506a0c6 2763 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2764 }
e506a0c6 2765
8e7d688b 2766 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2767 dspcntr |= DISPPLANE_ROTATE_180;
2768
6e3c9717
ACO		 2769 x += (intel_crtc->config->pipe_src_w - 1);
2770 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2771
2772 /* Finding the last pixel of the last line of the display
2773 data and adding to linear_offset*/
2774 linear_offset +=
6e3c9717
ACO		 2775 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2776 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2777 }
2778
2779 I915_WRITE(reg, dspcntr);
2780
01f2c773 2781 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2782 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2783 I915_WRITE(DSPSURF(plane),
2784 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2785 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2786 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2787 } else
f343c5f6 2788 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2789 POSTING_READ(reg);
17638cd6
JB		 2790}
2791
29b9bde6
DV		 2792static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2793 struct drm_framebuffer *fb,
2794 int x, int y)
17638cd6
JB		 2795{
2796 struct drm_device *dev = crtc->dev;
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2799 struct drm_i915_gem_object *obj;
17638cd6 2800 int plane = intel_crtc->plane;
e506a0c6 2801 unsigned long linear_offset;
17638cd6 2802 u32 dspcntr;
f45651ba 2803 u32 reg = DSPCNTR(plane);
48404c1e 2804 int pixel_size;
f45651ba 2805
fdd508a6
VS		 2806 if (!intel_crtc->primary_enabled) {
2807 I915_WRITE(reg, 0);
2808 I915_WRITE(DSPSURF(plane), 0);
2809 POSTING_READ(reg);
2810 return;
2811 }
2812
c9ba6fad
VS		 2813 obj = intel_fb_obj(fb);
2814 if (WARN_ON(obj == NULL))
2815 return;
2816
2817 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2818
f45651ba
VS		 2819 dspcntr = DISPPLANE_GAMMA_ENABLE;
2820
fdd508a6 2821 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2822
2823 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2824 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2825
57779d06
VS		 2826 switch (fb->pixel_format) {
2827 case DRM_FORMAT_C8:
17638cd6
JB		 2828 dspcntr |= DISPPLANE_8BPP;
2829 break;
57779d06
VS		 2830 case DRM_FORMAT_RGB565:
2831 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2832 break;
57779d06
VS		 2833 case DRM_FORMAT_XRGB8888:
2834 case DRM_FORMAT_ARGB8888:
2835 dspcntr |= DISPPLANE_BGRX888;
2836 break;
2837 case DRM_FORMAT_XBGR8888:
2838 case DRM_FORMAT_ABGR8888:
2839 dspcntr |= DISPPLANE_RGBX888;
2840 break;
2841 case DRM_FORMAT_XRGB2101010:
2842 case DRM_FORMAT_ARGB2101010:
2843 dspcntr |= DISPPLANE_BGRX101010;
2844 break;
2845 case DRM_FORMAT_XBGR2101010:
2846 case DRM_FORMAT_ABGR2101010:
2847 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2848 break;
2849 default:
baba133a 2850 BUG();
17638cd6
JB		 2851 }
2852
2853 if (obj->tiling_mode != I915_TILING_NONE)
2854 dspcntr |= DISPPLANE_TILED;
17638cd6 2855
f45651ba 2856 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2857 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2858
b9897127 2859 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2860 intel_crtc->dspaddr_offset =
bc752862 2861 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2862 pixel_size,
bc752862 2863 fb->pitches[0]);
c2c75131 2864 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2865 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2866 dspcntr |= DISPPLANE_ROTATE_180;
2867
2868 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2869 x += (intel_crtc->config->pipe_src_w - 1);
2870 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2871
2872 /* Finding the last pixel of the last line of the display
2873 data and adding to linear_offset*/
2874 linear_offset +=
6e3c9717
ACO		 2875 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2876 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2877 }
2878 }
2879
2880 I915_WRITE(reg, dspcntr);
17638cd6 2881
01f2c773 2882 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2883 I915_WRITE(DSPSURF(plane),
2884 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2885 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2886 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2887 } else {
2888 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2889 I915_WRITE(DSPLINOFF(plane), linear_offset);
2890 }
17638cd6 2891 POSTING_READ(reg);
17638cd6
JB		 2892}
2893
b321803d
DL		 2894u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2895 uint32_t pixel_format)
2896{
2897 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2898
2899 /*
2900 * The stride is either expressed as a multiple of 64 bytes
2901 * chunks for linear buffers or in number of tiles for tiled
2902 * buffers.
2903 */
2904 switch (fb_modifier) {
2905 case DRM_FORMAT_MOD_NONE:
2906 return 64;
2907 case I915_FORMAT_MOD_X_TILED:
2908 if (INTEL_INFO(dev)->gen == 2)
2909 return 128;
2910 return 512;
2911 case I915_FORMAT_MOD_Y_TILED:
2912 /* No need to check for old gens and Y tiling since this is
2913 * about the display engine and those will be blocked before
2914 * we get here.
2915 */
2916 return 128;
2917 case I915_FORMAT_MOD_Yf_TILED:
2918 if (bits_per_pixel == 8)
2919 return 64;
2920 else
2921 return 128;
2922 default:
2923 MISSING_CASE(fb_modifier);
2924 return 64;
2925 }
2926}
2927
121920fa
TU		 2928unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2929 struct drm_i915_gem_object *obj)
2930{
9abc4648 2931 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2932
2933 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2934 view = &i915_ggtt_view_rotated;
121920fa
TU		 2935
2936 return i915_gem_obj_ggtt_offset_view(obj, view);
2937}
2938
70d21f0e
DL		 2939static void skylake_update_primary_plane(struct drm_crtc *crtc,
2940 struct drm_framebuffer *fb,
2941 int x, int y)
2942{
2943 struct drm_device *dev = crtc->dev;
2944 struct drm_i915_private *dev_priv = dev->dev_private;
2945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
70d21f0e
DL		 2946 struct drm_i915_gem_object *obj;
2947 int pipe = intel_crtc->pipe;
b321803d 2948 u32 plane_ctl, stride_div;
121920fa 2949 unsigned long surf_addr;
70d21f0e
DL		 2950
2951 if (!intel_crtc->primary_enabled) {
2952 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2953 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2954 POSTING_READ(PLANE_CTL(pipe, 0));
2955 return;
2956 }
2957
2958 plane_ctl = PLANE_CTL_ENABLE |
2959 PLANE_CTL_PIPE_GAMMA_ENABLE |
2960 PLANE_CTL_PIPE_CSC_ENABLE;
2961
2962 switch (fb->pixel_format) {
2963 case DRM_FORMAT_RGB565:
2964 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2965 break;
2966 case DRM_FORMAT_XRGB8888:
2967 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2968 break;
f75fb42a
JN		 2969 case DRM_FORMAT_ARGB8888:
2970 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2971 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2972 break;
70d21f0e
DL		 2973 case DRM_FORMAT_XBGR8888:
2974 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2975 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2976 break;
f75fb42a
JN		 2977 case DRM_FORMAT_ABGR8888:
2978 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2979 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2980 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2981 break;
70d21f0e
DL		 2982 case DRM_FORMAT_XRGB2101010:
2983 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2984 break;
2985 case DRM_FORMAT_XBGR2101010:
2986 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2987 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2988 break;
2989 default:
2990 BUG();
2991 }
2992
30af77c4
DV		 2993 switch (fb->modifier[0]) {
2994 case DRM_FORMAT_MOD_NONE:
70d21f0e 2995 break;
30af77c4 2996 case I915_FORMAT_MOD_X_TILED:
70d21f0e 2997 plane_ctl |= PLANE_CTL_TILED_X;
b321803d
DL		 2998 break;
2999 case I915_FORMAT_MOD_Y_TILED:
3000 plane_ctl |= PLANE_CTL_TILED_Y;
3001 break;
3002 case I915_FORMAT_MOD_Yf_TILED:
3003 plane_ctl |= PLANE_CTL_TILED_YF;
70d21f0e
DL		 3004 break;
3005 default:
b321803d 3006 MISSING_CASE(fb->modifier[0]);
70d21f0e
DL		 3007 }
3008
3009 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
8e7d688b 3010 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
1447dde0 3011 plane_ctl |= PLANE_CTL_ROTATE_180;
70d21f0e 3012
b321803d
DL		 3013 obj = intel_fb_obj(fb);
3014 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3015 fb->pixel_format);
121920fa 3016 surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
b321803d 3017
70d21f0e 3018 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
70d21f0e
DL		 3019 I915_WRITE(PLANE_POS(pipe, 0), 0);
3020 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
3021 I915_WRITE(PLANE_SIZE(pipe, 0),
6e3c9717
ACO		 3022 (intel_crtc->config->pipe_src_h - 1) << 16 |
3023 (intel_crtc->config->pipe_src_w - 1));
b321803d 3024 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
121920fa 3025 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3026
3027 POSTING_READ(PLANE_SURF(pipe, 0));
3028}
3029
17638cd6
JB		 3030/* Assume fb object is pinned & idle & fenced and just update base pointers */
3031static int
3032intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3033 int x, int y, enum mode_set_atomic state)
3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3037
6b8e6ed0
CW		 3038 if (dev_priv->display.disable_fbc)
3039 dev_priv->display.disable_fbc(dev);
81255565 3040
29b9bde6
DV		 3041 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3042
3043 return 0;
81255565
JB		 3044}
3045
7514747d 3046static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3047{
96a02917
VS		 3048 struct drm_crtc *crtc;
3049
70e1e0ec 3050 for_each_crtc(dev, crtc) {
96a02917
VS		 3051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3052 enum plane plane = intel_crtc->plane;
3053
3054 intel_prepare_page_flip(dev, plane);
3055 intel_finish_page_flip_plane(dev, plane);
3056 }
7514747d
VS		 3057}
3058
3059static void intel_update_primary_planes(struct drm_device *dev)
3060{
3061 struct drm_i915_private *dev_priv = dev->dev_private;
3062 struct drm_crtc *crtc;
96a02917 3063
70e1e0ec 3064 for_each_crtc(dev, crtc) {
96a02917
VS		 3065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066
51fd371b 3067 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3068 /*
3069 * FIXME: Once we have proper support for primary planes (and
3070 * disabling them without disabling the entire crtc) allow again
66e514c1 3071 * a NULL crtc->primary->fb.
947fdaad 3072 */
f4510a27 3073 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3074 dev_priv->display.update_primary_plane(crtc,
66e514c1 3075 crtc->primary->fb,
262ca2b0
MR		 3076 crtc->x,
3077 crtc->y);
51fd371b 3078 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3079 }
3080}
3081
7514747d
VS		 3082void intel_prepare_reset(struct drm_device *dev)
3083{
f98ce92f
VS		 3084 struct drm_i915_private *dev_priv = to_i915(dev);
3085 struct intel_crtc *crtc;
3086
7514747d
VS		 3087 /* no reset support for gen2 */
3088 if (IS_GEN2(dev))
3089 return;
3090
3091 /* reset doesn't touch the display */
3092 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3093 return;
3094
3095 drm_modeset_lock_all(dev);
f98ce92f
VS		 3096
3097 /*
3098 * Disabling the crtcs gracefully seems nicer. Also the
3099 * g33 docs say we should at least disable all the planes.
3100 */
3101 for_each_intel_crtc(dev, crtc) {
3102 if (crtc->active)
3103 dev_priv->display.crtc_disable(&crtc->base);
3104 }
7514747d
VS		 3105}
3106
3107void intel_finish_reset(struct drm_device *dev)
3108{
3109 struct drm_i915_private *dev_priv = to_i915(dev);
3110
3111 /*
3112 * Flips in the rings will be nuked by the reset,
3113 * so complete all pending flips so that user space
3114 * will get its events and not get stuck.
3115 */
3116 intel_complete_page_flips(dev);
3117
3118 /* no reset support for gen2 */
3119 if (IS_GEN2(dev))
3120 return;
3121
3122 /* reset doesn't touch the display */
3123 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3124 /*
3125 * Flips in the rings have been nuked by the reset,
3126 * so update the base address of all primary
3127 * planes to the the last fb to make sure we're
3128 * showing the correct fb after a reset.
3129 */
3130 intel_update_primary_planes(dev);
3131 return;
3132 }
3133
3134 /*
3135 * The display has been reset as well,
3136 * so need a full re-initialization.
3137 */
3138 intel_runtime_pm_disable_interrupts(dev_priv);
3139 intel_runtime_pm_enable_interrupts(dev_priv);
3140
3141 intel_modeset_init_hw(dev);
3142
3143 spin_lock_irq(&dev_priv->irq_lock);
3144 if (dev_priv->display.hpd_irq_setup)
3145 dev_priv->display.hpd_irq_setup(dev);
3146 spin_unlock_irq(&dev_priv->irq_lock);
3147
3148 intel_modeset_setup_hw_state(dev, true);
3149
3150 intel_hpd_init(dev_priv);
3151
3152 drm_modeset_unlock_all(dev);
3153}
3154
14667a4b
CW		 3155static int
3156intel_finish_fb(struct drm_framebuffer *old_fb)
3157{
2ff8fde1 3158 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3159 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3160 bool was_interruptible = dev_priv->mm.interruptible;
3161 int ret;
3162
14667a4b
CW		 3163 /* Big Hammer, we also need to ensure that any pending
3164 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3165 * current scanout is retired before unpinning the old
3166 * framebuffer.
3167 *
3168 * This should only fail upon a hung GPU, in which case we
3169 * can safely continue.
3170 */
3171 dev_priv->mm.interruptible = false;
3172 ret = i915_gem_object_finish_gpu(obj);
3173 dev_priv->mm.interruptible = was_interruptible;
3174
3175 return ret;
3176}
3177
7d5e3799
CW		 3178static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3179{
3180 struct drm_device *dev = crtc->dev;
3181 struct drm_i915_private *dev_priv = dev->dev_private;
3182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3183 bool pending;
3184
3185 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3186 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3187 return false;
3188
5e2d7afc 3189 spin_lock_irq(&dev->event_lock);
7d5e3799 3190 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3191 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3192
3193 return pending;
3194}
3195
e30e8f75
GP		 3196static void intel_update_pipe_size(struct intel_crtc *crtc)
3197{
3198 struct drm_device *dev = crtc->base.dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 const struct drm_display_mode *adjusted_mode;
3201
3202 if (!i915.fastboot)
3203 return;
3204
3205 /*
3206 * Update pipe size and adjust fitter if needed: the reason for this is
3207 * that in compute_mode_changes we check the native mode (not the pfit
3208 * mode) to see if we can flip rather than do a full mode set. In the
3209 * fastboot case, we'll flip, but if we don't update the pipesrc and
3210 * pfit state, we'll end up with a big fb scanned out into the wrong
3211 * sized surface.
3212 *
3213 * To fix this properly, we need to hoist the checks up into
3214 * compute_mode_changes (or above), check the actual pfit state and
3215 * whether the platform allows pfit disable with pipe active, and only
3216 * then update the pipesrc and pfit state, even on the flip path.
3217 */
3218
6e3c9717 3219 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3220
3221 I915_WRITE(PIPESRC(crtc->pipe),
3222 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3223 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3224 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3225 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3226 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3227 I915_WRITE(PF_CTL(crtc->pipe), 0);
3228 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3229 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3230 }
6e3c9717
ACO		 3231 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3232 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3233}
3234
5e84e1a4
ZW		 3235static void intel_fdi_normal_train(struct drm_crtc *crtc)
3236{
3237 struct drm_device *dev = crtc->dev;
3238 struct drm_i915_private *dev_priv = dev->dev_private;
3239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3240 int pipe = intel_crtc->pipe;
3241 u32 reg, temp;
3242
3243 /* enable normal train */
3244 reg = FDI_TX_CTL(pipe);
3245 temp = I915_READ(reg);
61e499bf 3246 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3247 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3248 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3249 } else {
3250 temp &= ~FDI_LINK_TRAIN_NONE;
3251 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3252 }
5e84e1a4
ZW		 3253 I915_WRITE(reg, temp);
3254
3255 reg = FDI_RX_CTL(pipe);
3256 temp = I915_READ(reg);
3257 if (HAS_PCH_CPT(dev)) {
3258 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3259 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3260 } else {
3261 temp &= ~FDI_LINK_TRAIN_NONE;
3262 temp |= FDI_LINK_TRAIN_NONE;
3263 }
3264 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3265
3266 /* wait one idle pattern time */
3267 POSTING_READ(reg);
3268 udelay(1000);
357555c0
JB		 3269
3270 /* IVB wants error correction enabled */
3271 if (IS_IVYBRIDGE(dev))
3272 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3273 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3274}
3275
8db9d77b
ZW		 3276/* The FDI link training functions for ILK/Ibexpeak. */
3277static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3278{
3279 struct drm_device *dev = crtc->dev;
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3282 int pipe = intel_crtc->pipe;
5eddb70b 3283 u32 reg, temp, tries;
8db9d77b 3284
1c8562f6 3285 /* FDI needs bits from pipe first */
0fc932b8 3286 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3287
e1a44743
AJ		 3288 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3289 for train result */
5eddb70b
CW		 3290 reg = FDI_RX_IMR(pipe);
3291 temp = I915_READ(reg);
e1a44743
AJ		 3292 temp &= ~FDI_RX_SYMBOL_LOCK;
3293 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3294 I915_WRITE(reg, temp);
3295 I915_READ(reg);
e1a44743
AJ		 3296 udelay(150);
3297
8db9d77b 3298 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3299 reg = FDI_TX_CTL(pipe);
3300 temp = I915_READ(reg);
627eb5a3 3301 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3302 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3303 temp &= ~FDI_LINK_TRAIN_NONE;
3304 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3305 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3306
5eddb70b
CW		 3307 reg = FDI_RX_CTL(pipe);
3308 temp = I915_READ(reg);
8db9d77b
ZW		 3309 temp &= ~FDI_LINK_TRAIN_NONE;
3310 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3311 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3312
3313 POSTING_READ(reg);
8db9d77b
ZW		 3314 udelay(150);
3315
5b2adf89 3316 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3317 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3318 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3319 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3320
5eddb70b 3321 reg = FDI_RX_IIR(pipe);
e1a44743 3322 for (tries = 0; tries < 5; tries++) {
5eddb70b 3323 temp = I915_READ(reg);
8db9d77b
ZW		 3324 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3325
3326 if ((temp & FDI_RX_BIT_LOCK)) {
3327 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3328 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3329 break;
3330 }
8db9d77b 3331 }
e1a44743 3332 if (tries == 5)
5eddb70b 3333 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3334
3335 /* Train 2 */
5eddb70b
CW		 3336 reg = FDI_TX_CTL(pipe);
3337 temp = I915_READ(reg);
8db9d77b
ZW		 3338 temp &= ~FDI_LINK_TRAIN_NONE;
3339 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3340 I915_WRITE(reg, temp);
8db9d77b 3341
5eddb70b
CW		 3342 reg = FDI_RX_CTL(pipe);
3343 temp = I915_READ(reg);
8db9d77b
ZW		 3344 temp &= ~FDI_LINK_TRAIN_NONE;
3345 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3346 I915_WRITE(reg, temp);
8db9d77b 3347
5eddb70b
CW		 3348 POSTING_READ(reg);
3349 udelay(150);
8db9d77b 3350
5eddb70b 3351 reg = FDI_RX_IIR(pipe);
e1a44743 3352 for (tries = 0; tries < 5; tries++) {
5eddb70b 3353 temp = I915_READ(reg);
8db9d77b
ZW		 3354 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3355
3356 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3357 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3358 DRM_DEBUG_KMS("FDI train 2 done.\n");
3359 break;
3360 }
8db9d77b 3361 }
e1a44743 3362 if (tries == 5)
5eddb70b 3363 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3364
3365 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3366
8db9d77b
ZW		 3367}
3368
0206e353 3369static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3370 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3371 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3372 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3373 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3374};
3375
3376/* The FDI link training functions for SNB/Cougarpoint. */
3377static void gen6_fdi_link_train(struct drm_crtc *crtc)
3378{
3379 struct drm_device *dev = crtc->dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382 int pipe = intel_crtc->pipe;
fa37d39e 3383 u32 reg, temp, i, retry;
8db9d77b 3384
e1a44743
AJ		 3385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3386 for train result */
5eddb70b
CW		 3387 reg = FDI_RX_IMR(pipe);
3388 temp = I915_READ(reg);
e1a44743
AJ		 3389 temp &= ~FDI_RX_SYMBOL_LOCK;
3390 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3391 I915_WRITE(reg, temp);
3392
3393 POSTING_READ(reg);
e1a44743
AJ		 3394 udelay(150);
3395
8db9d77b 3396 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3397 reg = FDI_TX_CTL(pipe);
3398 temp = I915_READ(reg);
627eb5a3 3399 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3400 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3401 temp &= ~FDI_LINK_TRAIN_NONE;
3402 temp |= FDI_LINK_TRAIN_PATTERN_1;
3403 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3404 /* SNB-B */
3405 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3406 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3407
d74cf324
DV		 3408 I915_WRITE(FDI_RX_MISC(pipe),
3409 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3410
5eddb70b
CW		 3411 reg = FDI_RX_CTL(pipe);
3412 temp = I915_READ(reg);
8db9d77b
ZW		 3413 if (HAS_PCH_CPT(dev)) {
3414 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3415 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3416 } else {
3417 temp &= ~FDI_LINK_TRAIN_NONE;
3418 temp |= FDI_LINK_TRAIN_PATTERN_1;
3419 }
5eddb70b
CW		 3420 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3421
3422 POSTING_READ(reg);
8db9d77b
ZW		 3423 udelay(150);
3424
0206e353 3425 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3426 reg = FDI_TX_CTL(pipe);
3427 temp = I915_READ(reg);
8db9d77b
ZW		 3428 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3429 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3430 I915_WRITE(reg, temp);
3431
3432 POSTING_READ(reg);
8db9d77b
ZW		 3433 udelay(500);
3434
fa37d39e
SP		 3435 for (retry = 0; retry < 5; retry++) {
3436 reg = FDI_RX_IIR(pipe);
3437 temp = I915_READ(reg);
3438 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3439 if (temp & FDI_RX_BIT_LOCK) {
3440 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3441 DRM_DEBUG_KMS("FDI train 1 done.\n");
3442 break;
3443 }
3444 udelay(50);
8db9d77b 3445 }
fa37d39e
SP		 3446 if (retry < 5)
3447 break;
8db9d77b
ZW		 3448 }
3449 if (i == 4)
5eddb70b 3450 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3451
3452 /* Train 2 */
5eddb70b
CW		 3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
8db9d77b
ZW		 3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_2;
3457 if (IS_GEN6(dev)) {
3458 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3459 /* SNB-B */
3460 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3461 }
5eddb70b 3462 I915_WRITE(reg, temp);
8db9d77b 3463
5eddb70b
CW		 3464 reg = FDI_RX_CTL(pipe);
3465 temp = I915_READ(reg);
8db9d77b
ZW		 3466 if (HAS_PCH_CPT(dev)) {
3467 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3468 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3469 } else {
3470 temp &= ~FDI_LINK_TRAIN_NONE;
3471 temp |= FDI_LINK_TRAIN_PATTERN_2;
3472 }
5eddb70b
CW		 3473 I915_WRITE(reg, temp);
3474
3475 POSTING_READ(reg);
8db9d77b
ZW		 3476 udelay(150);
3477
0206e353 3478 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3479 reg = FDI_TX_CTL(pipe);
3480 temp = I915_READ(reg);
8db9d77b
ZW		 3481 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3482 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3483 I915_WRITE(reg, temp);
3484
3485 POSTING_READ(reg);
8db9d77b
ZW		 3486 udelay(500);
3487
fa37d39e
SP		 3488 for (retry = 0; retry < 5; retry++) {
3489 reg = FDI_RX_IIR(pipe);
3490 temp = I915_READ(reg);
3491 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3492 if (temp & FDI_RX_SYMBOL_LOCK) {
3493 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3494 DRM_DEBUG_KMS("FDI train 2 done.\n");
3495 break;
3496 }
3497 udelay(50);
8db9d77b 3498 }
fa37d39e
SP		 3499 if (retry < 5)
3500 break;
8db9d77b
ZW		 3501 }
3502 if (i == 4)
5eddb70b 3503 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3504
3505 DRM_DEBUG_KMS("FDI train done.\n");
3506}
3507
357555c0
JB		 3508/* Manual link training for Ivy Bridge A0 parts */
3509static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3510{
3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514 int pipe = intel_crtc->pipe;
139ccd3f 3515 u32 reg, temp, i, j;
357555c0
JB		 3516
3517 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3518 for train result */
3519 reg = FDI_RX_IMR(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~FDI_RX_SYMBOL_LOCK;
3522 temp &= ~FDI_RX_BIT_LOCK;
3523 I915_WRITE(reg, temp);
3524
3525 POSTING_READ(reg);
3526 udelay(150);
3527
01a415fd
DV		 3528 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3529 I915_READ(FDI_RX_IIR(pipe)));
3530
139ccd3f
JB		 3531 /* Try each vswing and preemphasis setting twice before moving on */
3532 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3533 /* disable first in case we need to retry */
3534 reg = FDI_TX_CTL(pipe);
3535 temp = I915_READ(reg);
3536 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3537 temp &= ~FDI_TX_ENABLE;
3538 I915_WRITE(reg, temp);
357555c0 3539
139ccd3f
JB		 3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~FDI_LINK_TRAIN_AUTO;
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp &= ~FDI_RX_ENABLE;
3545 I915_WRITE(reg, temp);
357555c0 3546
139ccd3f 3547 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3548 reg = FDI_TX_CTL(pipe);
3549 temp = I915_READ(reg);
139ccd3f 3550 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3551 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3552 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3554 temp |= snb_b_fdi_train_param[j/2];
3555 temp |= FDI_COMPOSITE_SYNC;
3556 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3557
139ccd3f
JB		 3558 I915_WRITE(FDI_RX_MISC(pipe),
3559 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3560
139ccd3f 3561 reg = FDI_RX_CTL(pipe);
357555c0 3562 temp = I915_READ(reg);
139ccd3f
JB		 3563 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3564 temp |= FDI_COMPOSITE_SYNC;
3565 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3566
139ccd3f
JB		 3567 POSTING_READ(reg);
3568 udelay(1); /* should be 0.5us */
357555c0 3569
139ccd3f
JB		 3570 for (i = 0; i < 4; i++) {
3571 reg = FDI_RX_IIR(pipe);
3572 temp = I915_READ(reg);
3573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3574
139ccd3f
JB		 3575 if (temp & FDI_RX_BIT_LOCK ||
3576 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3577 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3578 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3579 i);
3580 break;
3581 }
3582 udelay(1); /* should be 0.5us */
3583 }
3584 if (i == 4) {
3585 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3586 continue;
3587 }
357555c0 3588
139ccd3f 3589 /* Train 2 */
357555c0
JB		 3590 reg = FDI_TX_CTL(pipe);
3591 temp = I915_READ(reg);
139ccd3f
JB		 3592 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3593 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3594 I915_WRITE(reg, temp);
3595
3596 reg = FDI_RX_CTL(pipe);
3597 temp = I915_READ(reg);
3598 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3599 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3600 I915_WRITE(reg, temp);
3601
3602 POSTING_READ(reg);
139ccd3f 3603 udelay(2); /* should be 1.5us */
357555c0 3604
139ccd3f
JB		 3605 for (i = 0; i < 4; i++) {
3606 reg = FDI_RX_IIR(pipe);
3607 temp = I915_READ(reg);
3608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3609
139ccd3f
JB		 3610 if (temp & FDI_RX_SYMBOL_LOCK ||
3611 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3612 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3613 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3614 i);
3615 goto train_done;
3616 }
3617 udelay(2); /* should be 1.5us */
357555c0 3618 }
139ccd3f
JB		 3619 if (i == 4)
3620 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3621 }
357555c0 3622
139ccd3f 3623train_done:
357555c0
JB		 3624 DRM_DEBUG_KMS("FDI train done.\n");
3625}
3626
88cefb6c 3627static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3628{
88cefb6c 3629 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3630 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3631 int pipe = intel_crtc->pipe;
5eddb70b 3632 u32 reg, temp;
79e53945 3633
c64e311e 3634
c98e9dcf 3635 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3636 reg = FDI_RX_CTL(pipe);
3637 temp = I915_READ(reg);
627eb5a3 3638 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3639 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3640 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3641 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3642
3643 POSTING_READ(reg);
c98e9dcf
JB		 3644 udelay(200);
3645
3646 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3647 temp = I915_READ(reg);
3648 I915_WRITE(reg, temp | FDI_PCDCLK);
3649
3650 POSTING_READ(reg);
c98e9dcf
JB		 3651 udelay(200);
3652
20749730
PZ		 3653 /* Enable CPU FDI TX PLL, always on for Ironlake */
3654 reg = FDI_TX_CTL(pipe);
3655 temp = I915_READ(reg);
3656 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3657 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3658
20749730
PZ		 3659 POSTING_READ(reg);
3660 udelay(100);
6be4a607 3661 }
0e23b99d
JB		 3662}
3663
88cefb6c
DV		 3664static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3665{
3666 struct drm_device *dev = intel_crtc->base.dev;
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 int pipe = intel_crtc->pipe;
3669 u32 reg, temp;
3670
3671 /* Switch from PCDclk to Rawclk */
3672 reg = FDI_RX_CTL(pipe);
3673 temp = I915_READ(reg);
3674 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3675
3676 /* Disable CPU FDI TX PLL */
3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3680
3681 POSTING_READ(reg);
3682 udelay(100);
3683
3684 reg = FDI_RX_CTL(pipe);
3685 temp = I915_READ(reg);
3686 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3687
3688 /* Wait for the clocks to turn off. */
3689 POSTING_READ(reg);
3690 udelay(100);
3691}
3692
0fc932b8
JB		 3693static void ironlake_fdi_disable(struct drm_crtc *crtc)
3694{
3695 struct drm_device *dev = crtc->dev;
3696 struct drm_i915_private *dev_priv = dev->dev_private;
3697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3698 int pipe = intel_crtc->pipe;
3699 u32 reg, temp;
3700
3701 /* disable CPU FDI tx and PCH FDI rx */
3702 reg = FDI_TX_CTL(pipe);
3703 temp = I915_READ(reg);
3704 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3705 POSTING_READ(reg);
3706
3707 reg = FDI_RX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~(0x7 << 16);
dfd07d72 3710 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3711 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3712
3713 POSTING_READ(reg);
3714 udelay(100);
3715
3716 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3717 if (HAS_PCH_IBX(dev))
6f06ce18 3718 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3719
3720 /* still set train pattern 1 */
3721 reg = FDI_TX_CTL(pipe);
3722 temp = I915_READ(reg);
3723 temp &= ~FDI_LINK_TRAIN_NONE;
3724 temp |= FDI_LINK_TRAIN_PATTERN_1;
3725 I915_WRITE(reg, temp);
3726
3727 reg = FDI_RX_CTL(pipe);
3728 temp = I915_READ(reg);
3729 if (HAS_PCH_CPT(dev)) {
3730 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3731 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3732 } else {
3733 temp &= ~FDI_LINK_TRAIN_NONE;
3734 temp |= FDI_LINK_TRAIN_PATTERN_1;
3735 }
3736 /* BPC in FDI rx is consistent with that in PIPECONF */
3737 temp &= ~(0x07 << 16);
dfd07d72 3738 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3739 I915_WRITE(reg, temp);
3740
3741 POSTING_READ(reg);
3742 udelay(100);
3743}
3744
5dce5b93
CW		 3745bool intel_has_pending_fb_unpin(struct drm_device *dev)
3746{
3747 struct intel_crtc *crtc;
3748
3749 /* Note that we don't need to be called with mode_config.lock here
3750 * as our list of CRTC objects is static for the lifetime of the
3751 * device and so cannot disappear as we iterate. Similarly, we can
3752 * happily treat the predicates as racy, atomic checks as userspace
3753 * cannot claim and pin a new fb without at least acquring the
3754 * struct_mutex and so serialising with us.
3755 */
d3fcc808 3756 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3757 if (atomic_read(&crtc->unpin_work_count) == 0)
3758 continue;
3759
3760 if (crtc->unpin_work)
3761 intel_wait_for_vblank(dev, crtc->pipe);
3762
3763 return true;
3764 }
3765
3766 return false;
3767}
3768
d6bbafa1
CW		 3769static void page_flip_completed(struct intel_crtc *intel_crtc)
3770{
3771 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3772 struct intel_unpin_work *work = intel_crtc->unpin_work;
3773
3774 /* ensure that the unpin work is consistent wrt ->pending. */
3775 smp_rmb();
3776 intel_crtc->unpin_work = NULL;
3777
3778 if (work->event)
3779 drm_send_vblank_event(intel_crtc->base.dev,
3780 intel_crtc->pipe,
3781 work->event);
3782
3783 drm_crtc_vblank_put(&intel_crtc->base);
3784
3785 wake_up_all(&dev_priv->pending_flip_queue);
3786 queue_work(dev_priv->wq, &work->work);
3787
3788 trace_i915_flip_complete(intel_crtc->plane,
3789 work->pending_flip_obj);
3790}
3791
46a55d30 3792void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3793{
0f91128d 3794 struct drm_device *dev = crtc->dev;
5bb61643 3795 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3796
2c10d571 3797 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3798 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3799 !intel_crtc_has_pending_flip(crtc),
3800 60*HZ) == 0)) {
3801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3802
5e2d7afc 3803 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3804 if (intel_crtc->unpin_work) {
3805 WARN_ONCE(1, "Removing stuck page flip\n");
3806 page_flip_completed(intel_crtc);
3807 }
5e2d7afc 3808 spin_unlock_irq(&dev->event_lock);
9c787942 3809 }
5bb61643 3810
975d568a
CW		 3811 if (crtc->primary->fb) {
3812 mutex_lock(&dev->struct_mutex);
3813 intel_finish_fb(crtc->primary->fb);
3814 mutex_unlock(&dev->struct_mutex);
3815 }
e6c3a2a6
CW		 3816}
3817
e615efe4
ED		 3818/* Program iCLKIP clock to the desired frequency */
3819static void lpt_program_iclkip(struct drm_crtc *crtc)
3820{
3821 struct drm_device *dev = crtc->dev;
3822 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3823 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3824 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3825 u32 temp;
3826
09153000
DV		 3827 mutex_lock(&dev_priv->dpio_lock);
3828
e615efe4
ED		 3829 /* It is necessary to ungate the pixclk gate prior to programming
3830 * the divisors, and gate it back when it is done.
3831 */
3832 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3833
3834 /* Disable SSCCTL */
3835 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3836 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3837 SBI_SSCCTL_DISABLE,
3838 SBI_ICLK);
e615efe4
ED		 3839
3840 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3841 if (clock == 20000) {
e615efe4
ED		 3842 auxdiv = 1;
3843 divsel = 0x41;
3844 phaseinc = 0x20;
3845 } else {
3846 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3847 * but the adjusted_mode->crtc_clock in in KHz. To get the
3848 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3849 * convert the virtual clock precision to KHz here for higher
3850 * precision.
3851 */
3852 u32 iclk_virtual_root_freq = 172800 * 1000;
3853 u32 iclk_pi_range = 64;
3854 u32 desired_divisor, msb_divisor_value, pi_value;
3855
12d7ceed 3856 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3857 msb_divisor_value = desired_divisor / iclk_pi_range;
3858 pi_value = desired_divisor % iclk_pi_range;
3859
3860 auxdiv = 0;
3861 divsel = msb_divisor_value - 2;
3862 phaseinc = pi_value;
3863 }
3864
3865 /* This should not happen with any sane values */
3866 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3867 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3868 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3869 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3870
3871 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3872 clock,
e615efe4
ED		 3873 auxdiv,
3874 divsel,
3875 phasedir,
3876 phaseinc);
3877
3878 /* Program SSCDIVINTPHASE6 */
988d6ee8 3879 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3880 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3881 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3882 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3883 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3884 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3885 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3886 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3887
3888 /* Program SSCAUXDIV */
988d6ee8 3889 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3890 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3891 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3892 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3893
3894 /* Enable modulator and associated divider */
988d6ee8 3895 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3896 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3897 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3898
3899 /* Wait for initialization time */
3900 udelay(24);
3901
3902 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3903
3904 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3905}
3906
275f01b2
DV		 3907static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3908 enum pipe pch_transcoder)
3909{
3910 struct drm_device *dev = crtc->base.dev;
3911 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3912 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3913
3914 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3915 I915_READ(HTOTAL(cpu_transcoder)));
3916 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3917 I915_READ(HBLANK(cpu_transcoder)));
3918 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3919 I915_READ(HSYNC(cpu_transcoder)));
3920
3921 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3922 I915_READ(VTOTAL(cpu_transcoder)));
3923 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3924 I915_READ(VBLANK(cpu_transcoder)));
3925 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3926 I915_READ(VSYNC(cpu_transcoder)));
3927 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3928 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3929}
3930
003632d9 3931static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 3932{
3933 struct drm_i915_private *dev_priv = dev->dev_private;
3934 uint32_t temp;
3935
3936 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 3937 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 3938 return;
3939
3940 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3941 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3942
003632d9
ACO		 3943 temp &= ~FDI_BC_BIFURCATION_SELECT;
3944 if (enable)
3945 temp |= FDI_BC_BIFURCATION_SELECT;
3946
3947 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 3948 I915_WRITE(SOUTH_CHICKEN1, temp);
3949 POSTING_READ(SOUTH_CHICKEN1);
3950}
3951
3952static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3953{
3954 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 3955
3956 switch (intel_crtc->pipe) {
3957 case PIPE_A:
3958 break;
3959 case PIPE_B:
6e3c9717 3960 if (intel_crtc->config->fdi_lanes > 2)
003632d9 3961 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 3962 else
003632d9 3963 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3964
3965 break;
3966 case PIPE_C:
003632d9 3967 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3968
3969 break;
3970 default:
3971 BUG();
3972 }
3973}
3974
f67a559d
JB		 3975/*
3976 * Enable PCH resources required for PCH ports:
3977 * - PCH PLLs
3978 * - FDI training & RX/TX
3979 * - update transcoder timings
3980 * - DP transcoding bits
3981 * - transcoder
3982 */
3983static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3984{
3985 struct drm_device *dev = crtc->dev;
3986 struct drm_i915_private *dev_priv = dev->dev_private;
3987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3988 int pipe = intel_crtc->pipe;
ee7b9f93 3989 u32 reg, temp;
2c07245f 3990
ab9412ba 3991 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3992
1fbc0d78
DV		 3993 if (IS_IVYBRIDGE(dev))
3994 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3995
cd986abb
DV		 3996 /* Write the TU size bits before fdi link training, so that error
3997 * detection works. */
3998 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3999 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4000
c98e9dcf 4001 /* For PCH output, training FDI link */
674cf967 4002 dev_priv->display.fdi_link_train(crtc);
2c07245f 4003
3ad8a208
DV		 4004 /* We need to program the right clock selection before writing the pixel
4005 * mutliplier into the DPLL. */
303b81e0 4006 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4007 u32 sel;
4b645f14 4008
c98e9dcf 4009 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4010 temp |= TRANS_DPLL_ENABLE(pipe);
4011 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4012 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4013 temp |= sel;
4014 else
4015 temp &= ~sel;
c98e9dcf 4016 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4017 }
5eddb70b 4018
3ad8a208
DV		 4019 /* XXX: pch pll's can be enabled any time before we enable the PCH
4020 * transcoder, and we actually should do this to not upset any PCH
4021 * transcoder that already use the clock when we share it.
4022 *
4023 * Note that enable_shared_dpll tries to do the right thing, but
4024 * get_shared_dpll unconditionally resets the pll - we need that to have
4025 * the right LVDS enable sequence. */
85b3894f 4026 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4027
d9b6cb56
JB		 4028 /* set transcoder timing, panel must allow it */
4029 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4030 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4031
303b81e0 4032 intel_fdi_normal_train(crtc);
5e84e1a4 4033
c98e9dcf 4034 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4035 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4036 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4037 reg = TRANS_DP_CTL(pipe);
4038 temp = I915_READ(reg);
4039 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4040 TRANS_DP_SYNC_MASK |
4041 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4042 temp |= (TRANS_DP_OUTPUT_ENABLE |
4043 TRANS_DP_ENH_FRAMING);
9325c9f0 4044 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4045
4046 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4047 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4048 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4049 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4050
4051 switch (intel_trans_dp_port_sel(crtc)) {
4052 case PCH_DP_B:
5eddb70b 4053 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4054 break;
4055 case PCH_DP_C:
5eddb70b 4056 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4057 break;
4058 case PCH_DP_D:
5eddb70b 4059 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4060 break;
4061 default:
e95d41e1 4062 BUG();
32f9d658 4063 }
2c07245f 4064
5eddb70b 4065 I915_WRITE(reg, temp);
6be4a607 4066 }
b52eb4dc 4067
b8a4f404 4068 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4069}
4070
1507e5bd
PZ		 4071static void lpt_pch_enable(struct drm_crtc *crtc)
4072{
4073 struct drm_device *dev = crtc->dev;
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4076 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4077
ab9412ba 4078 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4079
8c52b5e8 4080 lpt_program_iclkip(crtc);
1507e5bd 4081
0540e488 4082 /* Set transcoder timing. */
275f01b2 4083 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4084
937bb610 4085 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4086}
4087
716c2e55 4088void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4089{
e2b78267 4090 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4091
4092 if (pll == NULL)
4093 return;
4094
3e369b76 4095 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4096 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4097 return;
4098 }
4099
3e369b76
ACO		 4100 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4101 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4102 WARN_ON(pll->on);
4103 WARN_ON(pll->active);
4104 }
4105
6e3c9717 4106 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4107}
4108
190f68c5
ACO		 4109struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4110 struct intel_crtc_state *crtc_state)
ee7b9f93 4111{
e2b78267 4112 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4113 struct intel_shared_dpll *pll;
e2b78267 4114 enum intel_dpll_id i;
ee7b9f93 4115
98b6bd99
DV		 4116 if (HAS_PCH_IBX(dev_priv->dev)) {
4117 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4118 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4119 pll = &dev_priv->shared_dplls[i];
98b6bd99 4120
46edb027
DV		 4121 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4122 crtc->base.base.id, pll->name);
98b6bd99 4123
8bd31e67 4124 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4125
98b6bd99
DV		 4126 goto found;
4127 }
4128
e72f9fbf
DV		 4129 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4130 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4131
4132 /* Only want to check enabled timings first */
8bd31e67 4133 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4134 continue;
4135
190f68c5 4136 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4137 &pll->new_config->hw_state,
4138 sizeof(pll->new_config->hw_state)) == 0) {
4139 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4140 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4141 pll->new_config->crtc_mask,
4142 pll->active);
ee7b9f93
JB		 4143 goto found;
4144 }
4145 }
4146
4147 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4148 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4149 pll = &dev_priv->shared_dplls[i];
8bd31e67 4150 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4151 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4152 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4153 goto found;
4154 }
4155 }
4156
4157 return NULL;
4158
4159found:
8bd31e67 4160 if (pll->new_config->crtc_mask == 0)
190f68c5 4161 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4162
190f68c5 4163 crtc_state->shared_dpll = i;
46edb027
DV		 4164 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4165 pipe_name(crtc->pipe));
ee7b9f93 4166
8bd31e67 4167 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4168
ee7b9f93
JB		 4169 return pll;
4170}
4171
8bd31e67
ACO		 4172/**
4173 * intel_shared_dpll_start_config - start a new PLL staged config
4174 * @dev_priv: DRM device
4175 * @clear_pipes: mask of pipes that will have their PLLs freed
4176 *
4177 * Starts a new PLL staged config, copying the current config but
4178 * releasing the references of pipes specified in clear_pipes.
4179 */
4180static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4181 unsigned clear_pipes)
4182{
4183 struct intel_shared_dpll *pll;
4184 enum intel_dpll_id i;
4185
4186 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4187 pll = &dev_priv->shared_dplls[i];
4188
4189 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4190 GFP_KERNEL);
4191 if (!pll->new_config)
4192 goto cleanup;
4193
4194 pll->new_config->crtc_mask &= ~clear_pipes;
4195 }
4196
4197 return 0;
4198
4199cleanup:
4200 while (--i >= 0) {
4201 pll = &dev_priv->shared_dplls[i];
f354d733 4202 kfree(pll->new_config);
8bd31e67
ACO		 4203 pll->new_config = NULL;
4204 }
4205
4206 return -ENOMEM;
4207}
4208
4209static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4210{
4211 struct intel_shared_dpll *pll;
4212 enum intel_dpll_id i;
4213
4214 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4215 pll = &dev_priv->shared_dplls[i];
4216
4217 WARN_ON(pll->new_config == &pll->config);
4218
4219 pll->config = *pll->new_config;
4220 kfree(pll->new_config);
4221 pll->new_config = NULL;
4222 }
4223}
4224
4225static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4226{
4227 struct intel_shared_dpll *pll;
4228 enum intel_dpll_id i;
4229
4230 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4231 pll = &dev_priv->shared_dplls[i];
4232
4233 WARN_ON(pll->new_config == &pll->config);
4234
4235 kfree(pll->new_config);
4236 pll->new_config = NULL;
4237 }
4238}
4239
a1520318 4240static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4241{
4242 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4243 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4244 u32 temp;
4245
4246 temp = I915_READ(dslreg);
4247 udelay(500);
4248 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4249 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4250 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4251 }
4252}
4253
bd2e244f
JB		 4254static void skylake_pfit_enable(struct intel_crtc *crtc)
4255{
4256 struct drm_device *dev = crtc->base.dev;
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258 int pipe = crtc->pipe;
4259
6e3c9717 4260 if (crtc->config->pch_pfit.enabled) {
bd2e244f 4261 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
6e3c9717
ACO		 4262 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4263 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
bd2e244f
JB		 4264 }
4265}
4266
b074cec8
JB		 4267static void ironlake_pfit_enable(struct intel_crtc *crtc)
4268{
4269 struct drm_device *dev = crtc->base.dev;
4270 struct drm_i915_private *dev_priv = dev->dev_private;
4271 int pipe = crtc->pipe;
4272
6e3c9717 4273 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4274 /* Force use of hard-coded filter coefficients
4275 * as some pre-programmed values are broken,
4276 * e.g. x201.
4277 */
4278 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4279 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4280 PF_PIPE_SEL_IVB(pipe));
4281 else
4282 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4283 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4284 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4285 }
4286}
4287
4a3b8769 4288static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4289{
4290 struct drm_device *dev = crtc->dev;
4291 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4292 struct drm_plane *plane;
bb53d4ae
VS		 4293 struct intel_plane *intel_plane;
4294
af2b653b
MR		 4295 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4296 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4297 if (intel_plane->pipe == pipe)
4298 intel_plane_restore(&intel_plane->base);
af2b653b 4299 }
bb53d4ae
VS		 4300}
4301
0d703d4e
MR		 4302/*
4303 * Disable a plane internally without actually modifying the plane's state.
4304 * This will allow us to easily restore the plane later by just reprogramming
4305 * its state.
4306 */
4307static void disable_plane_internal(struct drm_plane *plane)
4308{
4309 struct intel_plane *intel_plane = to_intel_plane(plane);
4310 struct drm_plane_state *state =
4311 plane->funcs->atomic_duplicate_state(plane);
4312 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4313
4314 intel_state->visible = false;
4315 intel_plane->commit_plane(plane, intel_state);
4316
4317 intel_plane_destroy_state(plane, state);
4318}
4319
4a3b8769 4320static void intel_disable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4321{
4322 struct drm_device *dev = crtc->dev;
4323 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4324 struct drm_plane *plane;
bb53d4ae
VS		 4325 struct intel_plane *intel_plane;
4326
af2b653b
MR		 4327 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4328 intel_plane = to_intel_plane(plane);
0d703d4e
MR		 4329 if (plane->fb && intel_plane->pipe == pipe)
4330 disable_plane_internal(plane);
af2b653b 4331 }
bb53d4ae
VS		 4332}
4333
20bc8673 4334void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4335{
cea165c3
VS		 4336 struct drm_device *dev = crtc->base.dev;
4337 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4338
6e3c9717 4339 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4340 return;
4341
cea165c3
VS		 4342 /* We can only enable IPS after we enable a plane and wait for a vblank */
4343 intel_wait_for_vblank(dev, crtc->pipe);
4344
d77e4531 4345 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4346 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4347 mutex_lock(&dev_priv->rps.hw_lock);
4348 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4349 mutex_unlock(&dev_priv->rps.hw_lock);
4350 /* Quoting Art Runyan: "its not safe to expect any particular
4351 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4352 * mailbox." Moreover, the mailbox may return a bogus state,
4353 * so we need to just enable it and continue on.
2a114cc1
BW		 4354 */
4355 } else {
4356 I915_WRITE(IPS_CTL, IPS_ENABLE);
4357 /* The bit only becomes 1 in the next vblank, so this wait here
4358 * is essentially intel_wait_for_vblank. If we don't have this
4359 * and don't wait for vblanks until the end of crtc_enable, then
4360 * the HW state readout code will complain that the expected
4361 * IPS_CTL value is not the one we read. */
4362 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4363 DRM_ERROR("Timed out waiting for IPS enable\n");
4364 }
d77e4531
PZ		 4365}
4366
20bc8673 4367void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4368{
4369 struct drm_device *dev = crtc->base.dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371
6e3c9717 4372 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4373 return;
4374
4375 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4376 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4377 mutex_lock(&dev_priv->rps.hw_lock);
4378 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4379 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4380 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4381 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4382 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4383 } else {
2a114cc1 4384 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4385 POSTING_READ(IPS_CTL);
4386 }
d77e4531
PZ		 4387
4388 /* We need to wait for a vblank before we can disable the plane. */
4389 intel_wait_for_vblank(dev, crtc->pipe);
4390}
4391
4392/** Loads the palette/gamma unit for the CRTC with the prepared values */
4393static void intel_crtc_load_lut(struct drm_crtc *crtc)
4394{
4395 struct drm_device *dev = crtc->dev;
4396 struct drm_i915_private *dev_priv = dev->dev_private;
4397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4398 enum pipe pipe = intel_crtc->pipe;
4399 int palreg = PALETTE(pipe);
4400 int i;
4401 bool reenable_ips = false;
4402
4403 /* The clocks have to be on to load the palette. */
83d65738 4404 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4405 return;
4406
4407 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
409ee761 4408 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4409 assert_dsi_pll_enabled(dev_priv);
4410 else
4411 assert_pll_enabled(dev_priv, pipe);
4412 }
4413
4414 /* use legacy palette for Ironlake */
7a1db49a 4415 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4416 palreg = LGC_PALETTE(pipe);
4417
4418 /* Workaround : Do not read or write the pipe palette/gamma data while
4419 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4420 */
6e3c9717 4421 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4422 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4423 GAMMA_MODE_MODE_SPLIT)) {
4424 hsw_disable_ips(intel_crtc);
4425 reenable_ips = true;
4426 }
4427
4428 for (i = 0; i < 256; i++) {
4429 I915_WRITE(palreg + 4 * i,
4430 (intel_crtc->lut_r[i] << 16) |
4431 (intel_crtc->lut_g[i] << 8) |
4432 intel_crtc->lut_b[i]);
4433 }
4434
4435 if (reenable_ips)
4436 hsw_enable_ips(intel_crtc);
4437}
4438
d3eedb1a
VS		 4439static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4440{
4441 if (!enable && intel_crtc->overlay) {
4442 struct drm_device *dev = intel_crtc->base.dev;
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444
4445 mutex_lock(&dev->struct_mutex);
4446 dev_priv->mm.interruptible = false;
4447 (void) intel_overlay_switch_off(intel_crtc->overlay);
4448 dev_priv->mm.interruptible = true;
4449 mutex_unlock(&dev->struct_mutex);
4450 }
4451
4452 /* Let userspace switch the overlay on again. In most cases userspace
4453 * has to recompute where to put it anyway.
4454 */
4455}
4456
d3eedb1a 4457static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4458{
4459 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4461 int pipe = intel_crtc->pipe;
a5c4d7bc 4462
fdd508a6 4463 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4464 intel_enable_sprite_planes(crtc);
a5c4d7bc 4465 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4466 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4467
4468 hsw_enable_ips(intel_crtc);
4469
4470 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4471 intel_fbc_update(dev);
a5c4d7bc 4472 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4473
4474 /*
4475 * FIXME: Once we grow proper nuclear flip support out of this we need
4476 * to compute the mask of flip planes precisely. For the time being
4477 * consider this a flip from a NULL plane.
4478 */
4479 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4480}
4481
d3eedb1a 4482static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4483{
4484 struct drm_device *dev = crtc->dev;
4485 struct drm_i915_private *dev_priv = dev->dev_private;
4486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4487 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4488
4489 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4490
e35fef21 4491 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4492 intel_fbc_disable(dev);
a5c4d7bc
VS		 4493
4494 hsw_disable_ips(intel_crtc);
4495
d3eedb1a 4496 intel_crtc_dpms_overlay(intel_crtc, false);
a5c4d7bc 4497 intel_crtc_update_cursor(crtc, false);
4a3b8769 4498 intel_disable_sprite_planes(crtc);
fdd508a6 4499 intel_disable_primary_hw_plane(crtc->primary, crtc);
f98551ae 4500
f99d7069
DV		 4501 /*
4502 * FIXME: Once we grow proper nuclear flip support out of this we need
4503 * to compute the mask of flip planes precisely. For the time being
4504 * consider this a flip to a NULL plane.
4505 */
4506 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4507}
4508
f67a559d
JB		 4509static void ironlake_crtc_enable(struct drm_crtc *crtc)
4510{
4511 struct drm_device *dev = crtc->dev;
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4514 struct intel_encoder *encoder;
f67a559d 4515 int pipe = intel_crtc->pipe;
f67a559d 4516
83d65738 4517 WARN_ON(!crtc->state->enable);
08a48469 4518
f67a559d
JB		 4519 if (intel_crtc->active)
4520 return;
4521
6e3c9717 4522 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4523 intel_prepare_shared_dpll(intel_crtc);
4524
6e3c9717 4525 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4526 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4527
4528 intel_set_pipe_timings(intel_crtc);
4529
6e3c9717 4530 if (intel_crtc->config->has_pch_encoder) {
29407aab 4531 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4532 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4533 }
4534
4535 ironlake_set_pipeconf(crtc);
4536
f67a559d 4537 intel_crtc->active = true;
8664281b 4538
a72e4c9f
DV		 4539 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4540 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4541
f6736a1a 4542 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4543 if (encoder->pre_enable)
4544 encoder->pre_enable(encoder);
f67a559d 4545
6e3c9717 4546 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4547 /* Note: FDI PLL enabling _must_ be done before we enable the
4548 * cpu pipes, hence this is separate from all the other fdi/pch
4549 * enabling. */
88cefb6c 4550 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4551 } else {
4552 assert_fdi_tx_disabled(dev_priv, pipe);
4553 assert_fdi_rx_disabled(dev_priv, pipe);
4554 }
f67a559d 4555
b074cec8 4556 ironlake_pfit_enable(intel_crtc);
f67a559d 4557
9c54c0dd
JB		 4558 /*
4559 * On ILK+ LUT must be loaded before the pipe is running but with
4560 * clocks enabled
4561 */
4562 intel_crtc_load_lut(crtc);
4563
f37fcc2a 4564 intel_update_watermarks(crtc);
e1fdc473 4565 intel_enable_pipe(intel_crtc);
f67a559d 4566
6e3c9717 4567 if (intel_crtc->config->has_pch_encoder)
f67a559d 4568 ironlake_pch_enable(crtc);
c98e9dcf 4569
f9b61ff6
DV		 4570 assert_vblank_disabled(crtc);
4571 drm_crtc_vblank_on(crtc);
4572
fa5c73b1
DV		 4573 for_each_encoder_on_crtc(dev, crtc, encoder)
4574 encoder->enable(encoder);
61b77ddd
DV		 4575
4576 if (HAS_PCH_CPT(dev))
a1520318 4577 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4578
d3eedb1a 4579 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4580}
4581
42db64ef
PZ		 4582/* IPS only exists on ULT machines and is tied to pipe A. */
4583static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4584{
f5adf94e 4585 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4586}
4587
e4916946
PZ		 4588/*
4589 * This implements the workaround described in the "notes" section of the mode
4590 * set sequence documentation. When going from no pipes or single pipe to
4591 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4592 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4593 */
4594static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4595{
4596 struct drm_device *dev = crtc->base.dev;
4597 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4598
4599 /* We want to get the other_active_crtc only if there's only 1 other
4600 * active crtc. */
d3fcc808 4601 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4602 if (!crtc_it->active || crtc_it == crtc)
4603 continue;
4604
4605 if (other_active_crtc)
4606 return;
4607
4608 other_active_crtc = crtc_it;
4609 }
4610 if (!other_active_crtc)
4611 return;
4612
4613 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4614 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4615}
4616
4f771f10
PZ		 4617static void haswell_crtc_enable(struct drm_crtc *crtc)
4618{
4619 struct drm_device *dev = crtc->dev;
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4622 struct intel_encoder *encoder;
4623 int pipe = intel_crtc->pipe;
4f771f10 4624
83d65738 4625 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4626
4627 if (intel_crtc->active)
4628 return;
4629
df8ad70c
DV		 4630 if (intel_crtc_to_shared_dpll(intel_crtc))
4631 intel_enable_shared_dpll(intel_crtc);
4632
6e3c9717 4633 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4634 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4635
4636 intel_set_pipe_timings(intel_crtc);
4637
6e3c9717
ACO		 4638 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4639 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4640 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4641 }
4642
6e3c9717 4643 if (intel_crtc->config->has_pch_encoder) {
229fca97 4644 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4645 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4646 }
4647
4648 haswell_set_pipeconf(crtc);
4649
4650 intel_set_pipe_csc(crtc);
4651
4f771f10 4652 intel_crtc->active = true;
8664281b 4653
a72e4c9f 4654 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4655 for_each_encoder_on_crtc(dev, crtc, encoder)
4656 if (encoder->pre_enable)
4657 encoder->pre_enable(encoder);
4658
6e3c9717 4659 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4660 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4661 true);
4fe9467d
ID		 4662 dev_priv->display.fdi_link_train(crtc);
4663 }
4664
1f544388 4665 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4666
bd2e244f
JB		 4667 if (IS_SKYLAKE(dev))
4668 skylake_pfit_enable(intel_crtc);
4669 else
4670 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4671
4672 /*
4673 * On ILK+ LUT must be loaded before the pipe is running but with
4674 * clocks enabled
4675 */
4676 intel_crtc_load_lut(crtc);
4677
1f544388 4678 intel_ddi_set_pipe_settings(crtc);
8228c251 4679 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4680
f37fcc2a 4681 intel_update_watermarks(crtc);
e1fdc473 4682 intel_enable_pipe(intel_crtc);
42db64ef 4683
6e3c9717 4684 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4685 lpt_pch_enable(crtc);
4f771f10 4686
6e3c9717 4687 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4688 intel_ddi_set_vc_payload_alloc(crtc, true);
4689
f9b61ff6
DV		 4690 assert_vblank_disabled(crtc);
4691 drm_crtc_vblank_on(crtc);
4692
8807e55b 4693 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4694 encoder->enable(encoder);
8807e55b
JN		 4695 intel_opregion_notify_encoder(encoder, true);
4696 }
4f771f10 4697
e4916946
PZ		 4698 /* If we change the relative order between pipe/planes enabling, we need
4699 * to change the workaround. */
4700 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4701 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4702}
4703
bd2e244f
JB		 4704static void skylake_pfit_disable(struct intel_crtc *crtc)
4705{
4706 struct drm_device *dev = crtc->base.dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 int pipe = crtc->pipe;
4709
4710 /* To avoid upsetting the power well on haswell only disable the pfit if
4711 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4712 if (crtc->config->pch_pfit.enabled) {
bd2e244f
JB		 4713 I915_WRITE(PS_CTL(pipe), 0);
4714 I915_WRITE(PS_WIN_POS(pipe), 0);
4715 I915_WRITE(PS_WIN_SZ(pipe), 0);
4716 }
4717}
4718
3f8dce3a
DV		 4719static void ironlake_pfit_disable(struct intel_crtc *crtc)
4720{
4721 struct drm_device *dev = crtc->base.dev;
4722 struct drm_i915_private *dev_priv = dev->dev_private;
4723 int pipe = crtc->pipe;
4724
4725 /* To avoid upsetting the power well on haswell only disable the pfit if
4726 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4727 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4728 I915_WRITE(PF_CTL(pipe), 0);
4729 I915_WRITE(PF_WIN_POS(pipe), 0);
4730 I915_WRITE(PF_WIN_SZ(pipe), 0);
4731 }
4732}
4733
6be4a607
JB		 4734static void ironlake_crtc_disable(struct drm_crtc *crtc)
4735{
4736 struct drm_device *dev = crtc->dev;
4737 struct drm_i915_private *dev_priv = dev->dev_private;
4738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4739 struct intel_encoder *encoder;
6be4a607 4740 int pipe = intel_crtc->pipe;
5eddb70b 4741 u32 reg, temp;
b52eb4dc 4742
f7abfe8b
CW		 4743 if (!intel_crtc->active)
4744 return;
4745
d3eedb1a 4746 intel_crtc_disable_planes(crtc);
a5c4d7bc 4747
ea9d758d
DV		 4748 for_each_encoder_on_crtc(dev, crtc, encoder)
4749 encoder->disable(encoder);
4750
f9b61ff6
DV		 4751 drm_crtc_vblank_off(crtc);
4752 assert_vblank_disabled(crtc);
4753
6e3c9717 4754 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4755 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4756
575f7ab7 4757 intel_disable_pipe(intel_crtc);
32f9d658 4758
3f8dce3a 4759 ironlake_pfit_disable(intel_crtc);
2c07245f 4760
bf49ec8c
DV		 4761 for_each_encoder_on_crtc(dev, crtc, encoder)
4762 if (encoder->post_disable)
4763 encoder->post_disable(encoder);
2c07245f 4764
6e3c9717 4765 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4766 ironlake_fdi_disable(crtc);
913d8d11 4767
d925c59a 4768 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4769
d925c59a
DV		 4770 if (HAS_PCH_CPT(dev)) {
4771 /* disable TRANS_DP_CTL */
4772 reg = TRANS_DP_CTL(pipe);
4773 temp = I915_READ(reg);
4774 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4775 TRANS_DP_PORT_SEL_MASK);
4776 temp |= TRANS_DP_PORT_SEL_NONE;
4777 I915_WRITE(reg, temp);
4778
4779 /* disable DPLL_SEL */
4780 temp = I915_READ(PCH_DPLL_SEL);
11887397 4781 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 4782 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 4783 }
e3421a18 4784
d925c59a 4785 /* disable PCH DPLL */
e72f9fbf 4786 intel_disable_shared_dpll(intel_crtc);
8db9d77b 4787
d925c59a
DV		 4788 ironlake_fdi_pll_disable(intel_crtc);
4789 }
6b383a7f 4790
f7abfe8b 4791 intel_crtc->active = false;
46ba614c 4792 intel_update_watermarks(crtc);
d1ebd816
BW		 4793
4794 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4795 intel_fbc_update(dev);
d1ebd816 4796 mutex_unlock(&dev->struct_mutex);
6be4a607 4797}
1b3c7a47 4798
4f771f10 4799static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 4800{
4f771f10
PZ		 4801 struct drm_device *dev = crtc->dev;
4802 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 4803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 4804 struct intel_encoder *encoder;
6e3c9717 4805 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 4806
4f771f10
PZ		 4807 if (!intel_crtc->active)
4808 return;
4809
d3eedb1a 4810 intel_crtc_disable_planes(crtc);
dda9a66a 4811
8807e55b
JN		 4812 for_each_encoder_on_crtc(dev, crtc, encoder) {
4813 intel_opregion_notify_encoder(encoder, false);
4f771f10 4814 encoder->disable(encoder);
8807e55b 4815 }
4f771f10 4816
f9b61ff6
DV		 4817 drm_crtc_vblank_off(crtc);
4818 assert_vblank_disabled(crtc);
4819
6e3c9717 4820 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 4821 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4822 false);
575f7ab7 4823 intel_disable_pipe(intel_crtc);
4f771f10 4824
6e3c9717 4825 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 4826 intel_ddi_set_vc_payload_alloc(crtc, false);
4827
ad80a810 4828 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 4829
bd2e244f
JB		 4830 if (IS_SKYLAKE(dev))
4831 skylake_pfit_disable(intel_crtc);
4832 else
4833 ironlake_pfit_disable(intel_crtc);
4f771f10 4834
1f544388 4835 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 4836
6e3c9717 4837 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 4838 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 4839 intel_ddi_fdi_disable(crtc);
83616634 4840 }
4f771f10 4841
97b040aa
ID		 4842 for_each_encoder_on_crtc(dev, crtc, encoder)
4843 if (encoder->post_disable)
4844 encoder->post_disable(encoder);
4845
4f771f10 4846 intel_crtc->active = false;
46ba614c 4847 intel_update_watermarks(crtc);
4f771f10
PZ		 4848
4849 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4850 intel_fbc_update(dev);
4f771f10 4851 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 4852
4853 if (intel_crtc_to_shared_dpll(intel_crtc))
4854 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 4855}
4856
ee7b9f93
JB		 4857static void ironlake_crtc_off(struct drm_crtc *crtc)
4858{
4859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 4860 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 4861}
4862
6441ab5f 4863
2dd24552
JB		 4864static void i9xx_pfit_enable(struct intel_crtc *crtc)
4865{
4866 struct drm_device *dev = crtc->base.dev;
4867 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4868 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 4869
681a8504 4870 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 4871 return;
4872
2dd24552 4873 /*
c0b03411
DV		 4874 * The panel fitter should only be adjusted whilst the pipe is disabled,
4875 * according to register description and PRM.
2dd24552 4876 */
c0b03411
DV		 4877 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4878 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 4879
b074cec8
JB		 4880 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4881 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 4882
4883 /* Border color in case we don't scale up to the full screen. Black by
4884 * default, change to something else for debugging. */
4885 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 4886}
4887
d05410f9
DA		 4888static enum intel_display_power_domain port_to_power_domain(enum port port)
4889{
4890 switch (port) {
4891 case PORT_A:
4892 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4893 case PORT_B:
4894 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4895 case PORT_C:
4896 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4897 case PORT_D:
4898 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4899 default:
4900 WARN_ON_ONCE(1);
4901 return POWER_DOMAIN_PORT_OTHER;
4902 }
4903}
4904
77d22dca
ID		 4905#define for_each_power_domain(domain, mask) \
4906 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4907 if ((1 << (domain)) & (mask))
4908
319be8ae
ID		 4909enum intel_display_power_domain
4910intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4911{
4912 struct drm_device *dev = intel_encoder->base.dev;
4913 struct intel_digital_port *intel_dig_port;
4914
4915 switch (intel_encoder->type) {
4916 case INTEL_OUTPUT_UNKNOWN:
4917 /* Only DDI platforms should ever use this output type */
4918 WARN_ON_ONCE(!HAS_DDI(dev));
4919 case INTEL_OUTPUT_DISPLAYPORT:
4920 case INTEL_OUTPUT_HDMI:
4921 case INTEL_OUTPUT_EDP:
4922 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 4923 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 4924 case INTEL_OUTPUT_DP_MST:
4925 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4926 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 4927 case INTEL_OUTPUT_ANALOG:
4928 return POWER_DOMAIN_PORT_CRT;
4929 case INTEL_OUTPUT_DSI:
4930 return POWER_DOMAIN_PORT_DSI;
4931 default:
4932 return POWER_DOMAIN_PORT_OTHER;
4933 }
4934}
4935
4936static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 4937{
319be8ae
ID		 4938 struct drm_device *dev = crtc->dev;
4939 struct intel_encoder *intel_encoder;
4940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4941 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 4942 unsigned long mask;
4943 enum transcoder transcoder;
4944
4945 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4946
4947 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4948 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 4949 if (intel_crtc->config->pch_pfit.enabled ||
4950 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 4951 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4952
319be8ae
ID		 4953 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4954 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4955
77d22dca
ID		 4956 return mask;
4957}
4958
679dacd4 4959static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 4960{
679dacd4 4961 struct drm_device *dev = state->dev;
77d22dca
ID		 4962 struct drm_i915_private *dev_priv = dev->dev_private;
4963 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4964 struct intel_crtc *crtc;
4965
4966 /*
4967 * First get all needed power domains, then put all unneeded, to avoid
4968 * any unnecessary toggling of the power wells.
4969 */
d3fcc808 4970 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4971 enum intel_display_power_domain domain;
4972
83d65738 4973 if (!crtc->base.state->enable)
77d22dca
ID		 4974 continue;
4975
319be8ae 4976 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 4977
4978 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4979 intel_display_power_get(dev_priv, domain);
4980 }
4981
50f6e502 4982 if (dev_priv->display.modeset_global_resources)
679dacd4 4983 dev_priv->display.modeset_global_resources(state);
50f6e502 4984
d3fcc808 4985 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4986 enum intel_display_power_domain domain;
4987
4988 for_each_power_domain(domain, crtc->enabled_power_domains)
4989 intel_display_power_put(dev_priv, domain);
4990
4991 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4992 }
4993
4994 intel_display_set_init_power(dev_priv, false);
4995}
4996
dfcab17e 4997/* returns HPLL frequency in kHz */
f8bf63fd 4998static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 4999{
586f49dc 5000 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5001
586f49dc
JB		 5002 /* Obtain SKU information */
5003 mutex_lock(&dev_priv->dpio_lock);
5004 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5005 CCK_FUSE_HPLL_FREQ_MASK;
5006 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5007
dfcab17e 5008 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5009}
5010
f8bf63fd
VS		 5011static void vlv_update_cdclk(struct drm_device *dev)
5012{
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014
5015 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5016 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
f8bf63fd
VS		 5017 dev_priv->vlv_cdclk_freq);
5018
5019 /*
5020 * Program the gmbus_freq based on the cdclk frequency.
5021 * BSpec erroneously claims we should aim for 4MHz, but
5022 * in fact 1MHz is the correct frequency.
5023 */
6be1e3d3 5024 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
f8bf63fd
VS		 5025}
5026
30a970c6
JB		 5027/* Adjust CDclk dividers to allow high res or save power if possible */
5028static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5029{
5030 struct drm_i915_private *dev_priv = dev->dev_private;
5031 u32 val, cmd;
5032
d197b7d3 5033 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
d60c4473 5034
dfcab17e 5035 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5036 cmd = 2;
dfcab17e 5037 else if (cdclk == 266667)
30a970c6
JB		 5038 cmd = 1;
5039 else
5040 cmd = 0;
5041
5042 mutex_lock(&dev_priv->rps.hw_lock);
5043 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5044 val &= ~DSPFREQGUAR_MASK;
5045 val |= (cmd << DSPFREQGUAR_SHIFT);
5046 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5047 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5048 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5049 50)) {
5050 DRM_ERROR("timed out waiting for CDclk change\n");
5051 }
5052 mutex_unlock(&dev_priv->rps.hw_lock);
5053
dfcab17e 5054 if (cdclk == 400000) {
6bcda4f0 5055 u32 divider;
30a970c6 5056
6bcda4f0 5057 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5058
5059 mutex_lock(&dev_priv->dpio_lock);
5060 /* adjust cdclk divider */
5061 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5062 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5063 val |= divider;
5064 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5065
5066 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5067 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5068 50))
5069 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5070 mutex_unlock(&dev_priv->dpio_lock);
5071 }
5072
5073 mutex_lock(&dev_priv->dpio_lock);
5074 /* adjust self-refresh exit latency value */
5075 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5076 val &= ~0x7f;
5077
5078 /*
5079 * For high bandwidth configs, we set a higher latency in the bunit
5080 * so that the core display fetch happens in time to avoid underruns.
5081 */
dfcab17e 5082 if (cdclk == 400000)
30a970c6
JB		 5083 val |= 4500 / 250; /* 4.5 usec */
5084 else
5085 val |= 3000 / 250; /* 3.0 usec */
5086 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5087 mutex_unlock(&dev_priv->dpio_lock);
5088
f8bf63fd 5089 vlv_update_cdclk(dev);
30a970c6
JB		 5090}
5091
383c5a6a
VS		 5092static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5093{
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 u32 val, cmd;
5096
5097 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5098
5099 switch (cdclk) {
383c5a6a
VS		 5100 case 333333:
5101 case 320000:
383c5a6a 5102 case 266667:
383c5a6a 5103 case 200000:
383c5a6a
VS		 5104 break;
5105 default:
5f77eeb0 5106 MISSING_CASE(cdclk);
383c5a6a
VS		 5107 return;
5108 }
5109
9d0d3fda
VS		 5110 /*
5111 * Specs are full of misinformation, but testing on actual
5112 * hardware has shown that we just need to write the desired
5113 * CCK divider into the Punit register.
5114 */
5115 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5116
383c5a6a
VS		 5117 mutex_lock(&dev_priv->rps.hw_lock);
5118 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5119 val &= ~DSPFREQGUAR_MASK_CHV;
5120 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5121 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5122 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5123 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5124 50)) {
5125 DRM_ERROR("timed out waiting for CDclk change\n");
5126 }
5127 mutex_unlock(&dev_priv->rps.hw_lock);
5128
5129 vlv_update_cdclk(dev);
5130}
5131
30a970c6
JB		 5132static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5133 int max_pixclk)
5134{
6bcda4f0 5135 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5136 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5137
30a970c6
JB		 5138 /*
5139 * Really only a few cases to deal with, as only 4 CDclks are supported:
5140 * 200MHz
5141 * 267MHz
29dc7ef3 5142 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5143 * 400MHz (VLV only)
5144 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5145 * of the lower bin and adjust if needed.
e37c67a1
VS		 5146 *
5147 * We seem to get an unstable or solid color picture at 200MHz.
5148 * Not sure what's wrong. For now use 200MHz only when all pipes
5149 * are off.
30a970c6 5150 */
6cca3195
VS		 5151 if (!IS_CHERRYVIEW(dev_priv) &&
5152 max_pixclk > freq_320*limit/100)
dfcab17e 5153 return 400000;
6cca3195 5154 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5155 return freq_320;
e37c67a1 5156 else if (max_pixclk > 0)
dfcab17e 5157 return 266667;
e37c67a1
VS		 5158 else
5159 return 200000;
30a970c6
JB		 5160}
5161
2f2d7aa1 5162/* compute the max pixel clock for new configuration */
304603f4 5163static int intel_mode_max_pixclk(struct drm_atomic_state *state)
30a970c6 5164{
304603f4 5165 struct drm_device *dev = state->dev;
30a970c6 5166 struct intel_crtc *intel_crtc;
304603f4 5167 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5168 int max_pixclk = 0;
5169
d3fcc808 5170 for_each_intel_crtc(dev, intel_crtc) {
304603f4
ACO		 5171 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5172 if (IS_ERR(crtc_state))
5173 return PTR_ERR(crtc_state);
5174
5175 if (!crtc_state->base.enable)
5176 continue;
5177
5178 max_pixclk = max(max_pixclk,
5179 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5180 }
5181
5182 return max_pixclk;
5183}
5184
304603f4 5185static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
2f2d7aa1 5186 unsigned *prepare_pipes)
30a970c6 5187{
304603f4 5188 struct drm_i915_private *dev_priv = to_i915(state->dev);
30a970c6 5189 struct intel_crtc *intel_crtc;
304603f4
ACO		 5190 int max_pixclk = intel_mode_max_pixclk(state);
5191
5192 if (max_pixclk < 0)
5193 return max_pixclk;
30a970c6 5194
d60c4473
ID		 5195 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5196 dev_priv->vlv_cdclk_freq)
304603f4 5197 return 0;
30a970c6 5198
2f2d7aa1 5199 /* disable/enable all currently active pipes while we change cdclk */
304603f4 5200 for_each_intel_crtc(state->dev, intel_crtc)
83d65738 5201 if (intel_crtc->base.state->enable)
30a970c6 5202 *prepare_pipes |= (1 << intel_crtc->pipe);
304603f4
ACO		 5203
5204 return 0;
30a970c6
JB		 5205}
5206
1e69cd74
VS		 5207static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5208{
5209 unsigned int credits, default_credits;
5210
5211 if (IS_CHERRYVIEW(dev_priv))
5212 default_credits = PFI_CREDIT(12);
5213 else
5214 default_credits = PFI_CREDIT(8);
5215
5216 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5217 /* CHV suggested value is 31 or 63 */
5218 if (IS_CHERRYVIEW(dev_priv))
5219 credits = PFI_CREDIT_31;
5220 else
5221 credits = PFI_CREDIT(15);
5222 } else {
5223 credits = default_credits;
5224 }
5225
5226 /*
5227 * WA - write default credits before re-programming
5228 * FIXME: should we also set the resend bit here?
5229 */
5230 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5231 default_credits);
5232
5233 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5234 credits | PFI_CREDIT_RESEND);
5235
5236 /*
5237 * FIXME is this guaranteed to clear
5238 * immediately or should we poll for it?
5239 */
5240 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5241}
5242
679dacd4 5243static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
30a970c6 5244{
679dacd4 5245 struct drm_device *dev = state->dev;
30a970c6 5246 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4
ACO		 5247 int max_pixclk = intel_mode_max_pixclk(state);
5248 int req_cdclk;
5249
5250 /* The only reason this can fail is if we fail to add the crtc_state
5251 * to the atomic state. But that can't happen since the call to
5252 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5253 * can't have failed otherwise the mode set would be aborted) added all
5254 * the states already. */
5255 if (WARN_ON(max_pixclk < 0))
5256 return;
5257
5258 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5259
383c5a6a 5260 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
738c05c0
ID		 5261 /*
5262 * FIXME: We can end up here with all power domains off, yet
5263 * with a CDCLK frequency other than the minimum. To account
5264 * for this take the PIPE-A power domain, which covers the HW
5265 * blocks needed for the following programming. This can be
5266 * removed once it's guaranteed that we get here either with
5267 * the minimum CDCLK set, or the required power domains
5268 * enabled.
5269 */
5270 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5271
383c5a6a
VS		 5272 if (IS_CHERRYVIEW(dev))
5273 cherryview_set_cdclk(dev, req_cdclk);
5274 else
5275 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5276
1e69cd74
VS		 5277 vlv_program_pfi_credits(dev_priv);
5278
738c05c0 5279 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5280 }
30a970c6
JB		 5281}
5282
89b667f8
JB		 5283static void valleyview_crtc_enable(struct drm_crtc *crtc)
5284{
5285 struct drm_device *dev = crtc->dev;
a72e4c9f 5286 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5288 struct intel_encoder *encoder;
5289 int pipe = intel_crtc->pipe;
23538ef1 5290 bool is_dsi;
89b667f8 5291
83d65738 5292 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5293
5294 if (intel_crtc->active)
5295 return;
5296
409ee761 5297 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5298
1ae0d137
VS		 5299 if (!is_dsi) {
5300 if (IS_CHERRYVIEW(dev))
6e3c9717 5301 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5302 else
6e3c9717 5303 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5304 }
5b18e57c 5305
6e3c9717 5306 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5307 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5308
5309 intel_set_pipe_timings(intel_crtc);
5310
c14b0485
VS		 5311 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5312 struct drm_i915_private *dev_priv = dev->dev_private;
5313
5314 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5315 I915_WRITE(CHV_CANVAS(pipe), 0);
5316 }
5317
5b18e57c
DV		 5318 i9xx_set_pipeconf(intel_crtc);
5319
89b667f8 5320 intel_crtc->active = true;
89b667f8 5321
a72e4c9f 5322 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5323
89b667f8
JB		 5324 for_each_encoder_on_crtc(dev, crtc, encoder)
5325 if (encoder->pre_pll_enable)
5326 encoder->pre_pll_enable(encoder);
5327
9d556c99
CML		 5328 if (!is_dsi) {
5329 if (IS_CHERRYVIEW(dev))
6e3c9717 5330 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5331 else
6e3c9717 5332 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5333 }
89b667f8
JB		 5334
5335 for_each_encoder_on_crtc(dev, crtc, encoder)
5336 if (encoder->pre_enable)
5337 encoder->pre_enable(encoder);
5338
2dd24552
JB		 5339 i9xx_pfit_enable(intel_crtc);
5340
63cbb074
VS		 5341 intel_crtc_load_lut(crtc);
5342
f37fcc2a 5343 intel_update_watermarks(crtc);
e1fdc473 5344 intel_enable_pipe(intel_crtc);
be6a6f8e 5345
4b3a9526
VS		 5346 assert_vblank_disabled(crtc);
5347 drm_crtc_vblank_on(crtc);
5348
f9b61ff6
DV		 5349 for_each_encoder_on_crtc(dev, crtc, encoder)
5350 encoder->enable(encoder);
5351
9ab0460b 5352 intel_crtc_enable_planes(crtc);
d40d9187 5353
56b80e1f 5354 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5355 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5356}
5357
f13c2ef3
DV		 5358static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5359{
5360 struct drm_device *dev = crtc->base.dev;
5361 struct drm_i915_private *dev_priv = dev->dev_private;
5362
6e3c9717
ACO		 5363 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5364 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5365}
5366
0b8765c6 5367static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5368{
5369 struct drm_device *dev = crtc->dev;
a72e4c9f 5370 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5372 struct intel_encoder *encoder;
79e53945 5373 int pipe = intel_crtc->pipe;
79e53945 5374
83d65738 5375 WARN_ON(!crtc->state->enable);
08a48469 5376
f7abfe8b
CW		 5377 if (intel_crtc->active)
5378 return;
5379
f13c2ef3
DV		 5380 i9xx_set_pll_dividers(intel_crtc);
5381
6e3c9717 5382 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5383 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5384
5385 intel_set_pipe_timings(intel_crtc);
5386
5b18e57c
DV		 5387 i9xx_set_pipeconf(intel_crtc);
5388
f7abfe8b 5389 intel_crtc->active = true;
6b383a7f 5390
4a3436e8 5391 if (!IS_GEN2(dev))
a72e4c9f 5392 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5393
9d6d9f19
MK		 5394 for_each_encoder_on_crtc(dev, crtc, encoder)
5395 if (encoder->pre_enable)
5396 encoder->pre_enable(encoder);
5397
f6736a1a
DV		 5398 i9xx_enable_pll(intel_crtc);
5399
2dd24552
JB		 5400 i9xx_pfit_enable(intel_crtc);
5401
63cbb074
VS		 5402 intel_crtc_load_lut(crtc);
5403
f37fcc2a 5404 intel_update_watermarks(crtc);
e1fdc473 5405 intel_enable_pipe(intel_crtc);
be6a6f8e 5406
4b3a9526
VS		 5407 assert_vblank_disabled(crtc);
5408 drm_crtc_vblank_on(crtc);
5409
f9b61ff6
DV		 5410 for_each_encoder_on_crtc(dev, crtc, encoder)
5411 encoder->enable(encoder);
5412
9ab0460b 5413 intel_crtc_enable_planes(crtc);
d40d9187 5414
4a3436e8
VS		 5415 /*
5416 * Gen2 reports pipe underruns whenever all planes are disabled.
5417 * So don't enable underrun reporting before at least some planes
5418 * are enabled.
5419 * FIXME: Need to fix the logic to work when we turn off all planes
5420 * but leave the pipe running.
5421 */
5422 if (IS_GEN2(dev))
a72e4c9f 5423 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5424
56b80e1f 5425 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5426 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5427}
79e53945 5428
87476d63
DV		 5429static void i9xx_pfit_disable(struct intel_crtc *crtc)
5430{
5431 struct drm_device *dev = crtc->base.dev;
5432 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5433
6e3c9717 5434 if (!crtc->config->gmch_pfit.control)
328d8e82 5435 return;
87476d63 5436
328d8e82 5437 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5438
328d8e82
DV		 5439 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5440 I915_READ(PFIT_CONTROL));
5441 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5442}
5443
0b8765c6
JB		 5444static void i9xx_crtc_disable(struct drm_crtc *crtc)
5445{
5446 struct drm_device *dev = crtc->dev;
5447 struct drm_i915_private *dev_priv = dev->dev_private;
5448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5449 struct intel_encoder *encoder;
0b8765c6 5450 int pipe = intel_crtc->pipe;
ef9c3aee 5451
f7abfe8b
CW		 5452 if (!intel_crtc->active)
5453 return;
5454
4a3436e8
VS		 5455 /*
5456 * Gen2 reports pipe underruns whenever all planes are disabled.
5457 * So diasble underrun reporting before all the planes get disabled.
5458 * FIXME: Need to fix the logic to work when we turn off all planes
5459 * but leave the pipe running.
5460 */
5461 if (IS_GEN2(dev))
a72e4c9f 5462 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5463
564ed191
ID		 5464 /*
5465 * Vblank time updates from the shadow to live plane control register
5466 * are blocked if the memory self-refresh mode is active at that
5467 * moment. So to make sure the plane gets truly disabled, disable
5468 * first the self-refresh mode. The self-refresh enable bit in turn
5469 * will be checked/applied by the HW only at the next frame start
5470 * event which is after the vblank start event, so we need to have a
5471 * wait-for-vblank between disabling the plane and the pipe.
5472 */
5473 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5474 intel_crtc_disable_planes(crtc);
5475
6304cd91
VS		 5476 /*
5477 * On gen2 planes are double buffered but the pipe isn't, so we must
5478 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5479 * We also need to wait on all gmch platforms because of the
5480 * self-refresh mode constraint explained above.
6304cd91 5481 */
564ed191 5482 intel_wait_for_vblank(dev, pipe);
6304cd91 5483
4b3a9526
VS		 5484 for_each_encoder_on_crtc(dev, crtc, encoder)
5485 encoder->disable(encoder);
5486
f9b61ff6
DV		 5487 drm_crtc_vblank_off(crtc);
5488 assert_vblank_disabled(crtc);
5489
575f7ab7 5490 intel_disable_pipe(intel_crtc);
24a1f16d 5491
87476d63 5492 i9xx_pfit_disable(intel_crtc);
24a1f16d 5493
89b667f8
JB		 5494 for_each_encoder_on_crtc(dev, crtc, encoder)
5495 if (encoder->post_disable)
5496 encoder->post_disable(encoder);
5497
409ee761 5498 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5499 if (IS_CHERRYVIEW(dev))
5500 chv_disable_pll(dev_priv, pipe);
5501 else if (IS_VALLEYVIEW(dev))
5502 vlv_disable_pll(dev_priv, pipe);
5503 else
1c4e0274 5504 i9xx_disable_pll(intel_crtc);
076ed3b2 5505 }
0b8765c6 5506
4a3436e8 5507 if (!IS_GEN2(dev))
a72e4c9f 5508 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5509
f7abfe8b 5510 intel_crtc->active = false;
46ba614c 5511 intel_update_watermarks(crtc);
f37fcc2a 5512
efa9624e 5513 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5514 intel_fbc_update(dev);
efa9624e 5515 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 5516}
5517
ee7b9f93
JB		 5518static void i9xx_crtc_off(struct drm_crtc *crtc)
5519{
5520}
5521
b04c5bd6
BF		 5522/* Master function to enable/disable CRTC and corresponding power wells */
5523void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 5524{
5525 struct drm_device *dev = crtc->dev;
5526 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 5527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 5528 enum intel_display_power_domain domain;
5529 unsigned long domains;
976f8a20 5530
0e572fe7
DV		 5531 if (enable) {
5532 if (!intel_crtc->active) {
e1e9fb84
DV		 5533 domains = get_crtc_power_domains(crtc);
5534 for_each_power_domain(domain, domains)
5535 intel_display_power_get(dev_priv, domain);
5536 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 5537
5538 dev_priv->display.crtc_enable(crtc);
5539 }
5540 } else {
5541 if (intel_crtc->active) {
5542 dev_priv->display.crtc_disable(crtc);
5543
e1e9fb84
DV		 5544 domains = intel_crtc->enabled_power_domains;
5545 for_each_power_domain(domain, domains)
5546 intel_display_power_put(dev_priv, domain);
5547 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 5548 }
5549 }
b04c5bd6
BF		 5550}
5551
5552/**
5553 * Sets the power management mode of the pipe and plane.
5554 */
5555void intel_crtc_update_dpms(struct drm_crtc *crtc)
5556{
5557 struct drm_device *dev = crtc->dev;
5558 struct intel_encoder *intel_encoder;
5559 bool enable = false;
5560
5561 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5562 enable |= intel_encoder->connectors_active;
5563
5564 intel_crtc_control(crtc, enable);
976f8a20
DV		 5565}
5566
cdd59983
CW		 5567static void intel_crtc_disable(struct drm_crtc *crtc)
5568{
cdd59983 5569 struct drm_device *dev = crtc->dev;
976f8a20 5570 struct drm_connector *connector;
ee7b9f93 5571 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 5572
976f8a20 5573 /* crtc should still be enabled when we disable it. */
83d65738 5574 WARN_ON(!crtc->state->enable);
976f8a20
DV		 5575
5576 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 5577 dev_priv->display.off(crtc);
5578
455a6808 5579 crtc->primary->funcs->disable_plane(crtc->primary);
976f8a20
DV		 5580
5581 /* Update computed state. */
5582 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5583 if (!connector->encoder || !connector->encoder->crtc)
5584 continue;
5585
5586 if (connector->encoder->crtc != crtc)
5587 continue;
5588
5589 connector->dpms = DRM_MODE_DPMS_OFF;
5590 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 5591 }
5592}
5593
ea5b213a 5594void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 5595{
4ef69c7a 5596 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 5597
ea5b213a
CW		 5598 drm_encoder_cleanup(encoder);
5599 kfree(intel_encoder);
7e7d76c3
JB		 5600}
5601
9237329d 5602/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 5603 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5604 * state of the entire output pipe. */
9237329d 5605static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 5606{
5ab432ef
DV		 5607 if (mode == DRM_MODE_DPMS_ON) {
5608 encoder->connectors_active = true;
5609
b2cabb0e 5610 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 5611 } else {
5612 encoder->connectors_active = false;
5613
b2cabb0e 5614 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 5615 }
79e53945
JB		 5616}
5617
0a91ca29
DV		 5618/* Cross check the actual hw state with our own modeset state tracking (and it's
5619 * internal consistency). */
b980514c 5620static void intel_connector_check_state(struct intel_connector *connector)
79e53945 5621{
0a91ca29
DV		 5622 if (connector->get_hw_state(connector)) {
5623 struct intel_encoder *encoder = connector->encoder;
5624 struct drm_crtc *crtc;
5625 bool encoder_enabled;
5626 enum pipe pipe;
5627
5628 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5629 connector->base.base.id,
c23cc417 5630 connector->base.name);
0a91ca29 5631
0e32b39c
DA		 5632 /* there is no real hw state for MST connectors */
5633 if (connector->mst_port)
5634 return;
5635
e2c719b7 5636 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 5637 "wrong connector dpms state\n");
e2c719b7 5638 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 5639 "active connector not linked to encoder\n");
0a91ca29 5640
36cd7444 5641 if (encoder) {
e2c719b7 5642 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 5643 "encoder->connectors_active not set\n");
5644
5645 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 5646 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5647 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 5648 return;
0a91ca29 5649
36cd7444 5650 crtc = encoder->base.crtc;
0a91ca29 5651
83d65738
MR		 5652 I915_STATE_WARN(!crtc->state->enable,
5653 "crtc not enabled\n");
e2c719b7
RC		 5654 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5655 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 5656 "encoder active on the wrong pipe\n");
5657 }
0a91ca29 5658 }
79e53945
JB		 5659}
5660
5ab432ef
DV		 5661/* Even simpler default implementation, if there's really no special case to
5662 * consider. */
5663void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 5664{
5ab432ef
DV		 5665 /* All the simple cases only support two dpms states. */
5666 if (mode != DRM_MODE_DPMS_ON)
5667 mode = DRM_MODE_DPMS_OFF;
d4270e57 5668
5ab432ef
DV		 5669 if (mode == connector->dpms)
5670 return;
5671
5672 connector->dpms = mode;
5673
5674 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 5675 if (connector->encoder)
5676 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 5677
b980514c 5678 intel_modeset_check_state(connector->dev);
79e53945
JB		 5679}
5680
f0947c37
DV		 5681/* Simple connector->get_hw_state implementation for encoders that support only
5682 * one connector and no cloning and hence the encoder state determines the state
5683 * of the connector. */
5684bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 5685{
24929352 5686 enum pipe pipe = 0;
f0947c37 5687 struct intel_encoder *encoder = connector->encoder;
ea5b213a 5688
f0947c37 5689 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 5690}
5691
6d293983 5692static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 5693{
6d293983
ACO		 5694 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
5695 return crtc_state->fdi_lanes;
d272ddfa
VS		 5696
5697 return 0;
5698}
5699
6d293983 5700static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 5701 struct intel_crtc_state *pipe_config)
1857e1da 5702{
6d293983
ACO		 5703 struct drm_atomic_state *state = pipe_config->base.state;
5704 struct intel_crtc *other_crtc;
5705 struct intel_crtc_state *other_crtc_state;
5706
1857e1da
DV		 5707 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5708 pipe_name(pipe), pipe_config->fdi_lanes);
5709 if (pipe_config->fdi_lanes > 4) {
5710 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5711 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5712 return -EINVAL;
1857e1da
DV		 5713 }
5714
bafb6553 5715 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 5716 if (pipe_config->fdi_lanes > 2) {
5717 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5718 pipe_config->fdi_lanes);
6d293983 5719 return -EINVAL;
1857e1da 5720 } else {
6d293983 5721 return 0;
1857e1da
DV		 5722 }
5723 }
5724
5725 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 5726 return 0;
1857e1da
DV		 5727
5728 /* Ivybridge 3 pipe is really complicated */
5729 switch (pipe) {
5730 case PIPE_A:
6d293983 5731 return 0;
1857e1da 5732 case PIPE_B:
6d293983
ACO		 5733 if (pipe_config->fdi_lanes <= 2)
5734 return 0;
5735
5736 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
5737 other_crtc_state =
5738 intel_atomic_get_crtc_state(state, other_crtc);
5739 if (IS_ERR(other_crtc_state))
5740 return PTR_ERR(other_crtc_state);
5741
5742 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 5743 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5744 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5745 return -EINVAL;
1857e1da 5746 }
6d293983 5747 return 0;
1857e1da 5748 case PIPE_C:
251cc67c
VS		 5749 if (pipe_config->fdi_lanes > 2) {
5750 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5751 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 5752 return -EINVAL;
251cc67c 5753 }
6d293983
ACO		 5754
5755 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
5756 other_crtc_state =
5757 intel_atomic_get_crtc_state(state, other_crtc);
5758 if (IS_ERR(other_crtc_state))
5759 return PTR_ERR(other_crtc_state);
5760
5761 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 5762 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 5763 return -EINVAL;
1857e1da 5764 }
6d293983 5765 return 0;
1857e1da
DV		 5766 default:
5767 BUG();
5768 }
5769}
5770
e29c22c0
DV		 5771#define RETRY 1
5772static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 5773 struct intel_crtc_state *pipe_config)
877d48d5 5774{
1857e1da 5775 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 5776 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 5777 int lane, link_bw, fdi_dotclock, ret;
5778 bool needs_recompute = false;
877d48d5 5779
e29c22c0 5780retry:
877d48d5
DV		 5781 /* FDI is a binary signal running at ~2.7GHz, encoding
5782 * each output octet as 10 bits. The actual frequency
5783 * is stored as a divider into a 100MHz clock, and the
5784 * mode pixel clock is stored in units of 1KHz.
5785 * Hence the bw of each lane in terms of the mode signal
5786 * is:
5787 */
5788 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5789
241bfc38 5790 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 5791
2bd89a07 5792 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 5793 pipe_config->pipe_bpp);
5794
5795 pipe_config->fdi_lanes = lane;
5796
2bd89a07 5797 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 5798 link_bw, &pipe_config->fdi_m_n);
1857e1da 5799
6d293983
ACO		 5800 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5801 intel_crtc->pipe, pipe_config);
5802 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 5803 pipe_config->pipe_bpp -= 2*3;
5804 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5805 pipe_config->pipe_bpp);
5806 needs_recompute = true;
5807 pipe_config->bw_constrained = true;
5808
5809 goto retry;
5810 }
5811
5812 if (needs_recompute)
5813 return RETRY;
5814
6d293983 5815 return ret;
877d48d5
DV		 5816}
5817
42db64ef 5818static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 5819 struct intel_crtc_state *pipe_config)
42db64ef 5820{
d330a953 5821 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 5822 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 5823 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 5824}
5825
a43f6e0f 5826static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 5827 struct intel_crtc_state *pipe_config)
79e53945 5828{
a43f6e0f 5829 struct drm_device *dev = crtc->base.dev;
8bd31e67 5830 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 5831 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 5832
ad3a4479 5833 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 5834 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 5835 int clock_limit =
5836 dev_priv->display.get_display_clock_speed(dev);
5837
5838 /*
5839 * Enable pixel doubling when the dot clock
5840 * is > 90% of the (display) core speed.
5841 *
b397c96b
VS		 5842 * GDG double wide on either pipe,
5843 * otherwise pipe A only.
cf532bb2 5844 */
b397c96b 5845 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 5846 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 5847 clock_limit *= 2;
cf532bb2 5848 pipe_config->double_wide = true;
ad3a4479
VS		 5849 }
5850
241bfc38 5851 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 5852 return -EINVAL;
2c07245f 5853 }
89749350 5854
1d1d0e27
VS		 5855 /*
5856 * Pipe horizontal size must be even in:
5857 * - DVO ganged mode
5858 * - LVDS dual channel mode
5859 * - Double wide pipe
5860 */
a93e255f 5861 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 5862 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5863 pipe_config->pipe_src_w &= ~1;
5864
8693a824
DL		 5865 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5866 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 5867 */
5868 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5869 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 5870 return -EINVAL;
44f46b42 5871
bd080ee5 5872 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 5873 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 5874 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 5875 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5876 * for lvds. */
5877 pipe_config->pipe_bpp = 8*3;
5878 }
5879
f5adf94e 5880 if (HAS_IPS(dev))
a43f6e0f
DV		 5881 hsw_compute_ips_config(crtc, pipe_config);
5882
877d48d5 5883 if (pipe_config->has_pch_encoder)
a43f6e0f 5884 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 5885
e29c22c0 5886 return 0;
79e53945
JB		 5887}
5888
1652d19e
VS		 5889static int skylake_get_display_clock_speed(struct drm_device *dev)
5890{
5891 struct drm_i915_private *dev_priv = to_i915(dev);
5892 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5893 uint32_t cdctl = I915_READ(CDCLK_CTL);
5894 uint32_t linkrate;
5895
5896 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
5897 WARN(1, "LCPLL1 not enabled\n");
5898 return 24000; /* 24MHz is the cd freq with NSSC ref */
5899 }
5900
5901 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
5902 return 540000;
5903
5904 linkrate = (I915_READ(DPLL_CTRL1) &
5905 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
5906
5907 if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
5908 linkrate == DPLL_CRTL1_LINK_RATE_1080) {
5909 /* vco 8640 */
5910 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
5911 case CDCLK_FREQ_450_432:
5912 return 432000;
5913 case CDCLK_FREQ_337_308:
5914 return 308570;
5915 case CDCLK_FREQ_675_617:
5916 return 617140;
5917 default:
5918 WARN(1, "Unknown cd freq selection\n");
5919 }
5920 } else {
5921 /* vco 8100 */
5922 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
5923 case CDCLK_FREQ_450_432:
5924 return 450000;
5925 case CDCLK_FREQ_337_308:
5926 return 337500;
5927 case CDCLK_FREQ_675_617:
5928 return 675000;
5929 default:
5930 WARN(1, "Unknown cd freq selection\n");
5931 }
5932 }
5933
5934 /* error case, do as if DPLL0 isn't enabled */
5935 return 24000;
5936}
5937
5938static int broadwell_get_display_clock_speed(struct drm_device *dev)
5939{
5940 struct drm_i915_private *dev_priv = dev->dev_private;
5941 uint32_t lcpll = I915_READ(LCPLL_CTL);
5942 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
5943
5944 if (lcpll & LCPLL_CD_SOURCE_FCLK)
5945 return 800000;
5946 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5947 return 450000;
5948 else if (freq == LCPLL_CLK_FREQ_450)
5949 return 450000;
5950 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
5951 return 540000;
5952 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
5953 return 337500;
5954 else
5955 return 675000;
5956}
5957
5958static int haswell_get_display_clock_speed(struct drm_device *dev)
5959{
5960 struct drm_i915_private *dev_priv = dev->dev_private;
5961 uint32_t lcpll = I915_READ(LCPLL_CTL);
5962 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
5963
5964 if (lcpll & LCPLL_CD_SOURCE_FCLK)
5965 return 800000;
5966 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5967 return 450000;
5968 else if (freq == LCPLL_CLK_FREQ_450)
5969 return 450000;
5970 else if (IS_HSW_ULT(dev))
5971 return 337500;
5972 else
5973 return 540000;
5974}
5975
25eb05fc
JB		 5976static int valleyview_get_display_clock_speed(struct drm_device *dev)
5977{
d197b7d3 5978 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 5979 u32 val;
5980 int divider;
5981
6bcda4f0
VS		 5982 if (dev_priv->hpll_freq == 0)
5983 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5984
d197b7d3
VS		 5985 mutex_lock(&dev_priv->dpio_lock);
5986 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5987 mutex_unlock(&dev_priv->dpio_lock);
5988
5989 divider = val & DISPLAY_FREQUENCY_VALUES;
5990
7d007f40
VS		 5991 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5992 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5993 "cdclk change in progress\n");
5994
6bcda4f0 5995 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 5996}
5997
b37a6434
VS		 5998static int ilk_get_display_clock_speed(struct drm_device *dev)
5999{
6000 return 450000;
6001}
6002
e70236a8
JB		 6003static int i945_get_display_clock_speed(struct drm_device *dev)
6004{
6005 return 400000;
6006}
79e53945 6007
e70236a8 6008static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6009{
e907f170 6010 return 333333;
e70236a8 6011}
79e53945 6012
e70236a8
JB		 6013static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6014{
6015 return 200000;
6016}
79e53945 6017
257a7ffc
DV		 6018static int pnv_get_display_clock_speed(struct drm_device *dev)
6019{
6020 u16 gcfgc = 0;
6021
6022 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6023
6024 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6025 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6026 return 266667;
257a7ffc 6027 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6028 return 333333;
257a7ffc 6029 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6030 return 444444;
257a7ffc
DV		 6031 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6032 return 200000;
6033 default:
6034 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6035 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6036 return 133333;
257a7ffc 6037 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6038 return 166667;
257a7ffc
DV		 6039 }
6040}
6041
e70236a8
JB		 6042static int i915gm_get_display_clock_speed(struct drm_device *dev)
6043{
6044 u16 gcfgc = 0;
79e53945 6045
e70236a8
JB		 6046 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6047
6048 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6049 return 133333;
e70236a8
JB		 6050 else {
6051 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6052 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6053 return 333333;
e70236a8
JB		 6054 default:
6055 case GC_DISPLAY_CLOCK_190_200_MHZ:
6056 return 190000;
79e53945 6057 }
e70236a8
JB		 6058 }
6059}
6060
6061static int i865_get_display_clock_speed(struct drm_device *dev)
6062{
e907f170 6063 return 266667;
e70236a8
JB		 6064}
6065
6066static int i855_get_display_clock_speed(struct drm_device *dev)
6067{
6068 u16 hpllcc = 0;
6069 /* Assume that the hardware is in the high speed state. This
6070 * should be the default.
6071 */
6072 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6073 case GC_CLOCK_133_200:
6074 case GC_CLOCK_100_200:
6075 return 200000;
6076 case GC_CLOCK_166_250:
6077 return 250000;
6078 case GC_CLOCK_100_133:
e907f170 6079 return 133333;
e70236a8 6080 }
79e53945 6081
e70236a8
JB		 6082 /* Shouldn't happen */
6083 return 0;
6084}
79e53945 6085
e70236a8
JB		 6086static int i830_get_display_clock_speed(struct drm_device *dev)
6087{
e907f170 6088 return 133333;
79e53945
JB		 6089}
6090
2c07245f 6091static void
a65851af 6092intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6093{
a65851af
VS		 6094 while (*num > DATA_LINK_M_N_MASK ||
6095 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6096 *num >>= 1;
6097 *den >>= 1;
6098 }
6099}
6100
a65851af
VS		 6101static void compute_m_n(unsigned int m, unsigned int n,
6102 uint32_t *ret_m, uint32_t *ret_n)
6103{
6104 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6105 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6106 intel_reduce_m_n_ratio(ret_m, ret_n);
6107}
6108
e69d0bc1
DV		 6109void
6110intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6111 int pixel_clock, int link_clock,
6112 struct intel_link_m_n *m_n)
2c07245f 6113{
e69d0bc1 6114 m_n->tu = 64;
a65851af
VS		 6115
6116 compute_m_n(bits_per_pixel * pixel_clock,
6117 link_clock * nlanes * 8,
6118 &m_n->gmch_m, &m_n->gmch_n);
6119
6120 compute_m_n(pixel_clock, link_clock,
6121 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6122}
6123
a7615030
CW		 6124static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6125{
d330a953
JN		 6126 if (i915.panel_use_ssc >= 0)
6127 return i915.panel_use_ssc != 0;
41aa3448 6128 return dev_priv->vbt.lvds_use_ssc
435793df 6129 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6130}
6131
a93e255f
ACO		 6132static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6133 int num_connectors)
c65d77d8 6134{
a93e255f 6135 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6136 struct drm_i915_private *dev_priv = dev->dev_private;
6137 int refclk;
6138
a93e255f
ACO		 6139 WARN_ON(!crtc_state->base.state);
6140
a0c4da24 6141 if (IS_VALLEYVIEW(dev)) {
9a0ea498 6142 refclk = 100000;
a93e255f 6143 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6144 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6145 refclk = dev_priv->vbt.lvds_ssc_freq;
6146 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6147 } else if (!IS_GEN2(dev)) {
6148 refclk = 96000;
6149 } else {
6150 refclk = 48000;
6151 }
6152
6153 return refclk;
6154}
6155
7429e9d4 6156static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6157{
7df00d7a 6158 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6159}
f47709a9 6160
7429e9d4
DV		 6161static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6162{
6163 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6164}
6165
f47709a9 6166static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6167 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6168 intel_clock_t *reduced_clock)
6169{
f47709a9 6170 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6171 u32 fp, fp2 = 0;
6172
6173 if (IS_PINEVIEW(dev)) {
190f68c5 6174 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6175 if (reduced_clock)
7429e9d4 6176 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6177 } else {
190f68c5 6178 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6179 if (reduced_clock)
7429e9d4 6180 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6181 }
6182
190f68c5 6183 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6184
f47709a9 6185 crtc->lowfreq_avail = false;
a93e255f 6186 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6187 reduced_clock) {
190f68c5 6188 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6189 crtc->lowfreq_avail = true;
a7516a05 6190 } else {
190f68c5 6191 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6192 }
6193}
6194
5e69f97f
CML		 6195static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6196 pipe)
89b667f8
JB		 6197{
6198 u32 reg_val;
6199
6200 /*
6201 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6202 * and set it to a reasonable value instead.
6203 */
ab3c759a 6204 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6205 reg_val &= 0xffffff00;
6206 reg_val |= 0x00000030;
ab3c759a 6207 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6208
ab3c759a 6209 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6210 reg_val &= 0x8cffffff;
6211 reg_val = 0x8c000000;
ab3c759a 6212 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6213
ab3c759a 6214 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6215 reg_val &= 0xffffff00;
ab3c759a 6216 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6217
ab3c759a 6218 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6219 reg_val &= 0x00ffffff;
6220 reg_val |= 0xb0000000;
ab3c759a 6221 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6222}
6223
b551842d
DV		 6224static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6225 struct intel_link_m_n *m_n)
6226{
6227 struct drm_device *dev = crtc->base.dev;
6228 struct drm_i915_private *dev_priv = dev->dev_private;
6229 int pipe = crtc->pipe;
6230
e3b95f1e
DV		 6231 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6232 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6233 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6234 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6235}
6236
6237static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6238 struct intel_link_m_n *m_n,
6239 struct intel_link_m_n *m2_n2)
b551842d
DV		 6240{
6241 struct drm_device *dev = crtc->base.dev;
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243 int pipe = crtc->pipe;
6e3c9717 6244 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6245
6246 if (INTEL_INFO(dev)->gen >= 5) {
6247 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6248 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6249 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6250 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6251 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6252 * for gen < 8) and if DRRS is supported (to make sure the
6253 * registers are not unnecessarily accessed).
6254 */
44395bfe 6255 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6256 crtc->config->has_drrs) {
f769cd24
VK		 6257 I915_WRITE(PIPE_DATA_M2(transcoder),
6258 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6259 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6260 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6261 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6262 }
b551842d 6263 } else {
e3b95f1e
DV		 6264 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6265 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6266 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6267 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6268 }
6269}
6270
fe3cd48d 6271void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6272{
fe3cd48d
R		 6273 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6274
6275 if (m_n == M1_N1) {
6276 dp_m_n = &crtc->config->dp_m_n;
6277 dp_m2_n2 = &crtc->config->dp_m2_n2;
6278 } else if (m_n == M2_N2) {
6279
6280 /*
6281 * M2_N2 registers are not supported. Hence m2_n2 divider value
6282 * needs to be programmed into M1_N1.
6283 */
6284 dp_m_n = &crtc->config->dp_m2_n2;
6285 } else {
6286 DRM_ERROR("Unsupported divider value\n");
6287 return;
6288 }
6289
6e3c9717
ACO		 6290 if (crtc->config->has_pch_encoder)
6291 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6292 else
fe3cd48d 6293 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6294}
6295
d288f65f 6296static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6297 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6298{
6299 u32 dpll, dpll_md;
6300
6301 /*
6302 * Enable DPIO clock input. We should never disable the reference
6303 * clock for pipe B, since VGA hotplug / manual detection depends
6304 * on it.
6305 */
6306 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6307 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6308 /* We should never disable this, set it here for state tracking */
6309 if (crtc->pipe == PIPE_B)
6310 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6311 dpll |= DPLL_VCO_ENABLE;
d288f65f 6312 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6313
d288f65f 6314 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6315 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6316 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6317}
6318
d288f65f 6319static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6320 const struct intel_crtc_state *pipe_config)
a0c4da24 6321{
f47709a9 6322 struct drm_device *dev = crtc->base.dev;
a0c4da24 6323 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6324 int pipe = crtc->pipe;
bdd4b6a6 6325 u32 mdiv;
a0c4da24 6326 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6327 u32 coreclk, reg_val;
a0c4da24 6328
09153000
DV		 6329 mutex_lock(&dev_priv->dpio_lock);
6330
d288f65f
VS		 6331 bestn = pipe_config->dpll.n;
6332 bestm1 = pipe_config->dpll.m1;
6333 bestm2 = pipe_config->dpll.m2;
6334 bestp1 = pipe_config->dpll.p1;
6335 bestp2 = pipe_config->dpll.p2;
a0c4da24 6336
89b667f8
JB		 6337 /* See eDP HDMI DPIO driver vbios notes doc */
6338
6339 /* PLL B needs special handling */
bdd4b6a6 6340 if (pipe == PIPE_B)
5e69f97f 6341 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6342
6343 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6344 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6345
6346 /* Disable target IRef on PLL */
ab3c759a 6347 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6348 reg_val &= 0x00ffffff;
ab3c759a 6349 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6350
6351 /* Disable fast lock */
ab3c759a 6352 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6353
6354 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6355 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6356 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6357 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6358 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6359
6360 /*
6361 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6362 * but we don't support that).
6363 * Note: don't use the DAC post divider as it seems unstable.
6364 */
6365 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6366 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6367
a0c4da24 6368 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6369 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6370
89b667f8 6371 /* Set HBR and RBR LPF coefficients */
d288f65f 6372 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6373 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6374 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6375 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6376 0x009f0003);
89b667f8 6377 else
ab3c759a 6378 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6379 0x00d0000f);
6380
681a8504 6381 if (pipe_config->has_dp_encoder) {
89b667f8 6382 /* Use SSC source */
bdd4b6a6 6383 if (pipe == PIPE_A)
ab3c759a 6384 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6385 0x0df40000);
6386 else
ab3c759a 6387 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6388 0x0df70000);
6389 } else { /* HDMI or VGA */
6390 /* Use bend source */
bdd4b6a6 6391 if (pipe == PIPE_A)
ab3c759a 6392 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6393 0x0df70000);
6394 else
ab3c759a 6395 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6396 0x0df40000);
6397 }
a0c4da24 6398
ab3c759a 6399 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6400 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6402 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6403 coreclk |= 0x01000000;
ab3c759a 6404 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6405
ab3c759a 6406 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6407 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6408}
6409
d288f65f 6410static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6411 struct intel_crtc_state *pipe_config)
1ae0d137 6412{
d288f65f 6413 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6414 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6415 DPLL_VCO_ENABLE;
6416 if (crtc->pipe != PIPE_A)
d288f65f 6417 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6418
d288f65f
VS		 6419 pipe_config->dpll_hw_state.dpll_md =
6420 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6421}
6422
d288f65f 6423static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6424 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6425{
6426 struct drm_device *dev = crtc->base.dev;
6427 struct drm_i915_private *dev_priv = dev->dev_private;
6428 int pipe = crtc->pipe;
6429 int dpll_reg = DPLL(crtc->pipe);
6430 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6431 u32 loopfilter, tribuf_calcntr;
9d556c99 6432 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6433 u32 dpio_val;
9cbe40c1 6434 int vco;
9d556c99 6435
d288f65f
VS		 6436 bestn = pipe_config->dpll.n;
6437 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6438 bestm1 = pipe_config->dpll.m1;
6439 bestm2 = pipe_config->dpll.m2 >> 22;
6440 bestp1 = pipe_config->dpll.p1;
6441 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6442 vco = pipe_config->dpll.vco;
a945ce7e 6443 dpio_val = 0;
9cbe40c1 6444 loopfilter = 0;
9d556c99
CML		 6445
6446 /*
6447 * Enable Refclk and SSC
6448 */
a11b0703 6449 I915_WRITE(dpll_reg,
d288f65f 6450 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6451
6452 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6453
9d556c99
CML		 6454 /* p1 and p2 divider */
6455 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6456 5 << DPIO_CHV_S1_DIV_SHIFT |
6457 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6458 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6459 1 << DPIO_CHV_K_DIV_SHIFT);
6460
6461 /* Feedback post-divider - m2 */
6462 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6463
6464 /* Feedback refclk divider - n and m1 */
6465 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6466 DPIO_CHV_M1_DIV_BY_2 |
6467 1 << DPIO_CHV_N_DIV_SHIFT);
6468
6469 /* M2 fraction division */
a945ce7e
VP		 6470 if (bestm2_frac)
6471 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 6472
6473 /* M2 fraction division enable */
a945ce7e
VP		 6474 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6475 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6476 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6477 if (bestm2_frac)
6478 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6479 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6480
de3a0fde
VP		 6481 /* Program digital lock detect threshold */
6482 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6483 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6484 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6485 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6486 if (!bestm2_frac)
6487 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6488 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6489
9d556c99 6490 /* Loop filter */
9cbe40c1
VP		 6491 if (vco == 5400000) {
6492 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6493 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6494 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6495 tribuf_calcntr = 0x9;
6496 } else if (vco <= 6200000) {
6497 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6498 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6499 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6500 tribuf_calcntr = 0x9;
6501 } else if (vco <= 6480000) {
6502 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6503 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6504 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6505 tribuf_calcntr = 0x8;
6506 } else {
6507 /* Not supported. Apply the same limits as in the max case */
6508 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6509 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6510 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6511 tribuf_calcntr = 0;
6512 }
9d556c99
CML		 6513 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6514
968040b2 6515 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 6516 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6517 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6518 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6519
9d556c99
CML		 6520 /* AFC Recal */
6521 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6522 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6523 DPIO_AFC_RECAL);
6524
6525 mutex_unlock(&dev_priv->dpio_lock);
6526}
6527
d288f65f
VS		 6528/**
6529 * vlv_force_pll_on - forcibly enable just the PLL
6530 * @dev_priv: i915 private structure
6531 * @pipe: pipe PLL to enable
6532 * @dpll: PLL configuration
6533 *
6534 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6535 * in cases where we need the PLL enabled even when @pipe is not going to
6536 * be enabled.
6537 */
6538void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6539 const struct dpll *dpll)
6540{
6541 struct intel_crtc *crtc =
6542 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 6543 struct intel_crtc_state pipe_config = {
a93e255f 6544 .base.crtc = &crtc->base,
d288f65f
VS		 6545 .pixel_multiplier = 1,
6546 .dpll = *dpll,
6547 };
6548
6549 if (IS_CHERRYVIEW(dev)) {
6550 chv_update_pll(crtc, &pipe_config);
6551 chv_prepare_pll(crtc, &pipe_config);
6552 chv_enable_pll(crtc, &pipe_config);
6553 } else {
6554 vlv_update_pll(crtc, &pipe_config);
6555 vlv_prepare_pll(crtc, &pipe_config);
6556 vlv_enable_pll(crtc, &pipe_config);
6557 }
6558}
6559
6560/**
6561 * vlv_force_pll_off - forcibly disable just the PLL
6562 * @dev_priv: i915 private structure
6563 * @pipe: pipe PLL to disable
6564 *
6565 * Disable the PLL for @pipe. To be used in cases where we need
6566 * the PLL enabled even when @pipe is not going to be enabled.
6567 */
6568void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6569{
6570 if (IS_CHERRYVIEW(dev))
6571 chv_disable_pll(to_i915(dev), pipe);
6572 else
6573 vlv_disable_pll(to_i915(dev), pipe);
6574}
6575
f47709a9 6576static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 6577 struct intel_crtc_state *crtc_state,
f47709a9 6578 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6579 int num_connectors)
6580{
f47709a9 6581 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6582 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 6583 u32 dpll;
6584 bool is_sdvo;
190f68c5 6585 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6586
190f68c5 6587 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6588
a93e255f
ACO		 6589 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6590 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 6591
6592 dpll = DPLL_VGA_MODE_DIS;
6593
a93e255f 6594 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 6595 dpll |= DPLLB_MODE_LVDS;
6596 else
6597 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 6598
ef1b460d 6599 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 6600 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 6601 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 6602 }
198a037f
DV		 6603
6604 if (is_sdvo)
4a33e48d 6605 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 6606
190f68c5 6607 if (crtc_state->has_dp_encoder)
4a33e48d 6608 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 6609
6610 /* compute bitmask from p1 value */
6611 if (IS_PINEVIEW(dev))
6612 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6613 else {
6614 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6615 if (IS_G4X(dev) && reduced_clock)
6616 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6617 }
6618 switch (clock->p2) {
6619 case 5:
6620 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6621 break;
6622 case 7:
6623 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6624 break;
6625 case 10:
6626 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6627 break;
6628 case 14:
6629 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6630 break;
6631 }
6632 if (INTEL_INFO(dev)->gen >= 4)
6633 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6634
190f68c5 6635 if (crtc_state->sdvo_tv_clock)
eb1cbe48 6636 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 6637 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6638 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6639 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6640 else
6641 dpll |= PLL_REF_INPUT_DREFCLK;
6642
6643 dpll |= DPLL_VCO_ENABLE;
190f68c5 6644 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 6645
eb1cbe48 6646 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 6647 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 6648 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 6649 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 6650 }
6651}
6652
f47709a9 6653static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 6654 struct intel_crtc_state *crtc_state,
f47709a9 6655 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6656 int num_connectors)
6657{
f47709a9 6658 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6659 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 6660 u32 dpll;
190f68c5 6661 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6662
190f68c5 6663 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6664
eb1cbe48
DV		 6665 dpll = DPLL_VGA_MODE_DIS;
6666
a93e255f 6667 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 6668 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6669 } else {
6670 if (clock->p1 == 2)
6671 dpll |= PLL_P1_DIVIDE_BY_TWO;
6672 else
6673 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6674 if (clock->p2 == 4)
6675 dpll |= PLL_P2_DIVIDE_BY_4;
6676 }
6677
a93e255f 6678 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 6679 dpll |= DPLL_DVO_2X_MODE;
6680
a93e255f 6681 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6682 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6683 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6684 else
6685 dpll |= PLL_REF_INPUT_DREFCLK;
6686
6687 dpll |= DPLL_VCO_ENABLE;
190f68c5 6688 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 6689}
6690
8a654f3b 6691static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 6692{
6693 struct drm_device *dev = intel_crtc->base.dev;
6694 struct drm_i915_private *dev_priv = dev->dev_private;
6695 enum pipe pipe = intel_crtc->pipe;
6e3c9717 6696 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 6697 struct drm_display_mode *adjusted_mode =
6e3c9717 6698 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 6699 uint32_t crtc_vtotal, crtc_vblank_end;
6700 int vsyncshift = 0;
4d8a62ea
DV		 6701
6702 /* We need to be careful not to changed the adjusted mode, for otherwise
6703 * the hw state checker will get angry at the mismatch. */
6704 crtc_vtotal = adjusted_mode->crtc_vtotal;
6705 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 6706
609aeaca 6707 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 6708 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 6709 crtc_vtotal -= 1;
6710 crtc_vblank_end -= 1;
609aeaca 6711
409ee761 6712 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 6713 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6714 else
6715 vsyncshift = adjusted_mode->crtc_hsync_start -
6716 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 6717 if (vsyncshift < 0)
6718 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 6719 }
6720
6721 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 6722 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 6723
fe2b8f9d 6724 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 6725 (adjusted_mode->crtc_hdisplay - 1) |
6726 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 6727 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 6728 (adjusted_mode->crtc_hblank_start - 1) |
6729 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 6730 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 6731 (adjusted_mode->crtc_hsync_start - 1) |
6732 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6733
fe2b8f9d 6734 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 6735 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 6736 ((crtc_vtotal - 1) << 16));
fe2b8f9d 6737 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 6738 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 6739 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 6740 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 6741 (adjusted_mode->crtc_vsync_start - 1) |
6742 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6743
b5e508d4
PZ		 6744 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6745 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6746 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6747 * bits. */
6748 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6749 (pipe == PIPE_B || pipe == PIPE_C))
6750 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6751
b0e77b9c
PZ		 6752 /* pipesrc controls the size that is scaled from, which should
6753 * always be the user's requested size.
6754 */
6755 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 6756 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6757 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 6758}
6759
1bd1bd80 6760static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 6761 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 6762{
6763 struct drm_device *dev = crtc->base.dev;
6764 struct drm_i915_private *dev_priv = dev->dev_private;
6765 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6766 uint32_t tmp;
6767
6768 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 6769 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6770 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6771 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 6772 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6773 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6774 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 6775 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6776 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6777
6778 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 6779 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6780 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6781 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 6782 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6783 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6784 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 6785 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6786 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6787
6788 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 6789 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6790 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6791 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 6792 }
6793
6794 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 6795 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6796 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6797
2d112de7
ACO		 6798 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6799 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 6800}
6801
f6a83288 6802void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 6803 struct intel_crtc_state *pipe_config)
babea61d 6804{
2d112de7
ACO		 6805 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6806 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6807 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6808 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 6809
2d112de7
ACO		 6810 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6811 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6812 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6813 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 6814
2d112de7 6815 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 6816
2d112de7
ACO		 6817 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6818 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 6819}
6820
84b046f3
DV		 6821static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6822{
6823 struct drm_device *dev = intel_crtc->base.dev;
6824 struct drm_i915_private *dev_priv = dev->dev_private;
6825 uint32_t pipeconf;
6826
9f11a9e4 6827 pipeconf = 0;
84b046f3 6828
b6b5d049
VS		 6829 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6830 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6831 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 6832
6e3c9717 6833 if (intel_crtc->config->double_wide)
cf532bb2 6834 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 6835
ff9ce46e
DV		 6836 /* only g4x and later have fancy bpc/dither controls */
6837 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 6838 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 6839 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 6840 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 6841 PIPECONF_DITHER_TYPE_SP;
84b046f3 6842
6e3c9717 6843 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 6844 case 18:
6845 pipeconf |= PIPECONF_6BPC;
6846 break;
6847 case 24:
6848 pipeconf |= PIPECONF_8BPC;
6849 break;
6850 case 30:
6851 pipeconf |= PIPECONF_10BPC;
6852 break;
6853 default:
6854 /* Case prevented by intel_choose_pipe_bpp_dither. */
6855 BUG();
84b046f3
DV		 6856 }
6857 }
6858
6859 if (HAS_PIPE_CXSR(dev)) {
6860 if (intel_crtc->lowfreq_avail) {
6861 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6862 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6863 } else {
6864 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 6865 }
6866 }
6867
6e3c9717 6868 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 6869 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 6870 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 6871 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6872 else
6873 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6874 } else
84b046f3
DV		 6875 pipeconf |= PIPECONF_PROGRESSIVE;
6876
6e3c9717 6877 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 6878 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 6879
84b046f3
DV		 6880 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6881 POSTING_READ(PIPECONF(intel_crtc->pipe));
6882}
6883
190f68c5
ACO		 6884static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6885 struct intel_crtc_state *crtc_state)
79e53945 6886{
c7653199 6887 struct drm_device *dev = crtc->base.dev;
79e53945 6888 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 6889 int refclk, num_connectors = 0;
652c393a 6890 intel_clock_t clock, reduced_clock;
a16af721 6891 bool ok, has_reduced_clock = false;
e9fd1c02 6892 bool is_lvds = false, is_dsi = false;
5eddb70b 6893 struct intel_encoder *encoder;
d4906093 6894 const intel_limit_t *limit;
55bb9992
ACO		 6895 struct drm_atomic_state *state = crtc_state->base.state;
6896 struct drm_connector_state *connector_state;
6897 int i;
79e53945 6898
55bb9992
ACO		 6899 for (i = 0; i < state->num_connector; i++) {
6900 if (!state->connectors[i])
d0737e1d
ACO		 6901 continue;
6902
55bb9992
ACO		 6903 connector_state = state->connector_states[i];
6904 if (connector_state->crtc != &crtc->base)
6905 continue;
6906
6907 encoder = to_intel_encoder(connector_state->best_encoder);
6908
5eddb70b 6909 switch (encoder->type) {
79e53945
JB		 6910 case INTEL_OUTPUT_LVDS:
6911 is_lvds = true;
6912 break;
e9fd1c02
JN		 6913 case INTEL_OUTPUT_DSI:
6914 is_dsi = true;
6915 break;
6847d71b
PZ		 6916 default:
6917 break;
79e53945 6918 }
43565a06 6919
c751ce4f 6920 num_connectors++;
79e53945
JB		 6921 }
6922
f2335330 6923 if (is_dsi)
5b18e57c 6924 return 0;
f2335330 6925
190f68c5 6926 if (!crtc_state->clock_set) {
a93e255f 6927 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 6928
e9fd1c02
JN		 6929 /*
6930 * Returns a set of divisors for the desired target clock with
6931 * the given refclk, or FALSE. The returned values represent
6932 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6933 * 2) / p1 / p2.
6934 */
a93e255f
ACO		 6935 limit = intel_limit(crtc_state, refclk);
6936 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 6937 crtc_state->port_clock,
e9fd1c02 6938 refclk, NULL, &clock);
f2335330 6939 if (!ok) {
e9fd1c02
JN		 6940 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6941 return -EINVAL;
6942 }
79e53945 6943
f2335330
JN		 6944 if (is_lvds && dev_priv->lvds_downclock_avail) {
6945 /*
6946 * Ensure we match the reduced clock's P to the target
6947 * clock. If the clocks don't match, we can't switch
6948 * the display clock by using the FP0/FP1. In such case
6949 * we will disable the LVDS downclock feature.
6950 */
6951 has_reduced_clock =
a93e255f 6952 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 6953 dev_priv->lvds_downclock,
6954 refclk, &clock,
6955 &reduced_clock);
6956 }
6957 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 6958 crtc_state->dpll.n = clock.n;
6959 crtc_state->dpll.m1 = clock.m1;
6960 crtc_state->dpll.m2 = clock.m2;
6961 crtc_state->dpll.p1 = clock.p1;
6962 crtc_state->dpll.p2 = clock.p2;
f47709a9 6963 }
7026d4ac 6964
e9fd1c02 6965 if (IS_GEN2(dev)) {
190f68c5 6966 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 6967 has_reduced_clock ? &reduced_clock : NULL,
6968 num_connectors);
9d556c99 6969 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 6970 chv_update_pll(crtc, crtc_state);
e9fd1c02 6971 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 6972 vlv_update_pll(crtc, crtc_state);
e9fd1c02 6973 } else {
190f68c5 6974 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 6975 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 6976 num_connectors);
e9fd1c02 6977 }
79e53945 6978
c8f7a0db 6979 return 0;
f564048e
EA		 6980}
6981
2fa2fe9a 6982static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 6983 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 6984{
6985 struct drm_device *dev = crtc->base.dev;
6986 struct drm_i915_private *dev_priv = dev->dev_private;
6987 uint32_t tmp;
6988
dc9e7dec
VS		 6989 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6990 return;
6991
2fa2fe9a 6992 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 6993 if (!(tmp & PFIT_ENABLE))
6994 return;
2fa2fe9a 6995
06922821 6996 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 6997 if (INTEL_INFO(dev)->gen < 4) {
6998 if (crtc->pipe != PIPE_B)
6999 return;
2fa2fe9a
DV		 7000 } else {
7001 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7002 return;
7003 }
7004
06922821 7005 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7006 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7007 if (INTEL_INFO(dev)->gen < 5)
7008 pipe_config->gmch_pfit.lvds_border_bits =
7009 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7010}
7011
acbec814 7012static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7013 struct intel_crtc_state *pipe_config)
acbec814
JB		 7014{
7015 struct drm_device *dev = crtc->base.dev;
7016 struct drm_i915_private *dev_priv = dev->dev_private;
7017 int pipe = pipe_config->cpu_transcoder;
7018 intel_clock_t clock;
7019 u32 mdiv;
662c6ecb 7020 int refclk = 100000;
acbec814 7021
f573de5a
SK		 7022 /* In case of MIPI DPLL will not even be used */
7023 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7024 return;
7025
acbec814 7026 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7027 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7028 mutex_unlock(&dev_priv->dpio_lock);
7029
7030 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7031 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7032 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7033 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7034 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7035
f646628b 7036 vlv_clock(refclk, &clock);
acbec814 7037
f646628b
VS		 7038 /* clock.dot is the fast clock */
7039 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7040}
7041
5724dbd1
DL		 7042static void
7043i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7044 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7045{
7046 struct drm_device *dev = crtc->base.dev;
7047 struct drm_i915_private *dev_priv = dev->dev_private;
7048 u32 val, base, offset;
7049 int pipe = crtc->pipe, plane = crtc->plane;
7050 int fourcc, pixel_format;
6761dd31 7051 unsigned int aligned_height;
b113d5ee 7052 struct drm_framebuffer *fb;
1b842c89 7053 struct intel_framebuffer *intel_fb;
1ad292b5 7054
42a7b088
DL		 7055 val = I915_READ(DSPCNTR(plane));
7056 if (!(val & DISPLAY_PLANE_ENABLE))
7057 return;
7058
d9806c9f 7059 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7060 if (!intel_fb) {
1ad292b5
JB		 7061 DRM_DEBUG_KMS("failed to alloc fb\n");
7062 return;
7063 }
7064
1b842c89
DL		 7065 fb = &intel_fb->base;
7066
18c5247e
DV		 7067 if (INTEL_INFO(dev)->gen >= 4) {
7068 if (val & DISPPLANE_TILED) {
49af449b 7069 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7070 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7071 }
7072 }
1ad292b5
JB		 7073
7074 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7075 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7076 fb->pixel_format = fourcc;
7077 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7078
7079 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7080 if (plane_config->tiling)
1ad292b5
JB		 7081 offset = I915_READ(DSPTILEOFF(plane));
7082 else
7083 offset = I915_READ(DSPLINOFF(plane));
7084 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7085 } else {
7086 base = I915_READ(DSPADDR(plane));
7087 }
7088 plane_config->base = base;
7089
7090 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7091 fb->width = ((val >> 16) & 0xfff) + 1;
7092 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7093
7094 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7095 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7096
b113d5ee 7097 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7098 fb->pixel_format,
7099 fb->modifier[0]);
1ad292b5 7100
f37b5c2b 7101 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7102
2844a921
DL		 7103 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7104 pipe_name(pipe), plane, fb->width, fb->height,
7105 fb->bits_per_pixel, base, fb->pitches[0],
7106 plane_config->size);
1ad292b5 7107
2d14030b 7108 plane_config->fb = intel_fb;
1ad292b5
JB		 7109}
7110
70b23a98 7111static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7112 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7113{
7114 struct drm_device *dev = crtc->base.dev;
7115 struct drm_i915_private *dev_priv = dev->dev_private;
7116 int pipe = pipe_config->cpu_transcoder;
7117 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7118 intel_clock_t clock;
7119 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7120 int refclk = 100000;
7121
7122 mutex_lock(&dev_priv->dpio_lock);
7123 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7124 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7125 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7126 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7127 mutex_unlock(&dev_priv->dpio_lock);
7128
7129 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7130 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7131 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7132 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7133 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7134
7135 chv_clock(refclk, &clock);
7136
7137 /* clock.dot is the fast clock */
7138 pipe_config->port_clock = clock.dot / 5;
7139}
7140
0e8ffe1b 7141static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7142 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7143{
7144 struct drm_device *dev = crtc->base.dev;
7145 struct drm_i915_private *dev_priv = dev->dev_private;
7146 uint32_t tmp;
7147
f458ebbc
DV		 7148 if (!intel_display_power_is_enabled(dev_priv,
7149 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7150 return false;
7151
e143a21c 7152 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7153 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7154
0e8ffe1b
DV		 7155 tmp = I915_READ(PIPECONF(crtc->pipe));
7156 if (!(tmp & PIPECONF_ENABLE))
7157 return false;
7158
42571aef
VS		 7159 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7160 switch (tmp & PIPECONF_BPC_MASK) {
7161 case PIPECONF_6BPC:
7162 pipe_config->pipe_bpp = 18;
7163 break;
7164 case PIPECONF_8BPC:
7165 pipe_config->pipe_bpp = 24;
7166 break;
7167 case PIPECONF_10BPC:
7168 pipe_config->pipe_bpp = 30;
7169 break;
7170 default:
7171 break;
7172 }
7173 }
7174
b5a9fa09
DV		 7175 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7176 pipe_config->limited_color_range = true;
7177
282740f7
VS		 7178 if (INTEL_INFO(dev)->gen < 4)
7179 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7180
1bd1bd80
DV		 7181 intel_get_pipe_timings(crtc, pipe_config);
7182
2fa2fe9a
DV		 7183 i9xx_get_pfit_config(crtc, pipe_config);
7184
6c49f241
DV		 7185 if (INTEL_INFO(dev)->gen >= 4) {
7186 tmp = I915_READ(DPLL_MD(crtc->pipe));
7187 pipe_config->pixel_multiplier =
7188 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7189 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7190 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7191 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7192 tmp = I915_READ(DPLL(crtc->pipe));
7193 pipe_config->pixel_multiplier =
7194 ((tmp & SDVO_MULTIPLIER_MASK)
7195 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7196 } else {
7197 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7198 * port and will be fixed up in the encoder->get_config
7199 * function. */
7200 pipe_config->pixel_multiplier = 1;
7201 }
8bcc2795
DV		 7202 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7203 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7204 /*
7205 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7206 * on 830. Filter it out here so that we don't
7207 * report errors due to that.
7208 */
7209 if (IS_I830(dev))
7210 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7211
8bcc2795
DV		 7212 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7213 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7214 } else {
7215 /* Mask out read-only status bits. */
7216 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7217 DPLL_PORTC_READY_MASK |
7218 DPLL_PORTB_READY_MASK);
8bcc2795 7219 }
6c49f241 7220
70b23a98
VS		 7221 if (IS_CHERRYVIEW(dev))
7222 chv_crtc_clock_get(crtc, pipe_config);
7223 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7224 vlv_crtc_clock_get(crtc, pipe_config);
7225 else
7226 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7227
0e8ffe1b
DV		 7228 return true;
7229}
7230
dde86e2d 7231static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7232{
7233 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7234 struct intel_encoder *encoder;
74cfd7ac 7235 u32 val, final;
13d83a67 7236 bool has_lvds = false;
199e5d79 7237 bool has_cpu_edp = false;
199e5d79 7238 bool has_panel = false;
99eb6a01
KP		 7239 bool has_ck505 = false;
7240 bool can_ssc = false;
13d83a67
JB		 7241
7242 /* We need to take the global config into account */
b2784e15 7243 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7244 switch (encoder->type) {
7245 case INTEL_OUTPUT_LVDS:
7246 has_panel = true;
7247 has_lvds = true;
7248 break;
7249 case INTEL_OUTPUT_EDP:
7250 has_panel = true;
2de6905f 7251 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7252 has_cpu_edp = true;
7253 break;
6847d71b
PZ		 7254 default:
7255 break;
13d83a67
JB		 7256 }
7257 }
7258
99eb6a01 7259 if (HAS_PCH_IBX(dev)) {
41aa3448 7260 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7261 can_ssc = has_ck505;
7262 } else {
7263 has_ck505 = false;
7264 can_ssc = true;
7265 }
7266
2de6905f
ID		 7267 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7268 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7269
7270 /* Ironlake: try to setup display ref clock before DPLL
7271 * enabling. This is only under driver's control after
7272 * PCH B stepping, previous chipset stepping should be
7273 * ignoring this setting.
7274 */
74cfd7ac
CW		 7275 val = I915_READ(PCH_DREF_CONTROL);
7276
7277 /* As we must carefully and slowly disable/enable each source in turn,
7278 * compute the final state we want first and check if we need to
7279 * make any changes at all.
7280 */
7281 final = val;
7282 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7283 if (has_ck505)
7284 final |= DREF_NONSPREAD_CK505_ENABLE;
7285 else
7286 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7287
7288 final &= ~DREF_SSC_SOURCE_MASK;
7289 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7290 final &= ~DREF_SSC1_ENABLE;
7291
7292 if (has_panel) {
7293 final |= DREF_SSC_SOURCE_ENABLE;
7294
7295 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7296 final |= DREF_SSC1_ENABLE;
7297
7298 if (has_cpu_edp) {
7299 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7300 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7301 else
7302 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7303 } else
7304 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7305 } else {
7306 final |= DREF_SSC_SOURCE_DISABLE;
7307 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7308 }
7309
7310 if (final == val)
7311 return;
7312
13d83a67 7313 /* Always enable nonspread source */
74cfd7ac 7314 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7315
99eb6a01 7316 if (has_ck505)
74cfd7ac 7317 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7318 else
74cfd7ac 7319 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7320
199e5d79 7321 if (has_panel) {
74cfd7ac
CW		 7322 val &= ~DREF_SSC_SOURCE_MASK;
7323 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7324
199e5d79 7325 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7326 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7327 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7328 val |= DREF_SSC1_ENABLE;
e77166b5 7329 } else
74cfd7ac 7330 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7331
7332 /* Get SSC going before enabling the outputs */
74cfd7ac 7333 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7334 POSTING_READ(PCH_DREF_CONTROL);
7335 udelay(200);
7336
74cfd7ac 7337 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7338
7339 /* Enable CPU source on CPU attached eDP */
199e5d79 7340 if (has_cpu_edp) {
99eb6a01 7341 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7342 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7343 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7344 } else
74cfd7ac 7345 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7346 } else
74cfd7ac 7347 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7348
74cfd7ac 7349 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7350 POSTING_READ(PCH_DREF_CONTROL);
7351 udelay(200);
7352 } else {
7353 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7354
74cfd7ac 7355 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7356
7357 /* Turn off CPU output */
74cfd7ac 7358 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7359
74cfd7ac 7360 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7361 POSTING_READ(PCH_DREF_CONTROL);
7362 udelay(200);
7363
7364 /* Turn off the SSC source */
74cfd7ac
CW		 7365 val &= ~DREF_SSC_SOURCE_MASK;
7366 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7367
7368 /* Turn off SSC1 */
74cfd7ac 7369 val &= ~DREF_SSC1_ENABLE;
199e5d79 7370
74cfd7ac 7371 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7372 POSTING_READ(PCH_DREF_CONTROL);
7373 udelay(200);
7374 }
74cfd7ac
CW		 7375
7376 BUG_ON(val != final);
13d83a67
JB		 7377}
7378
f31f2d55 7379static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7380{
f31f2d55 7381 uint32_t tmp;
dde86e2d 7382
0ff066a9
PZ		 7383 tmp = I915_READ(SOUTH_CHICKEN2);
7384 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7385 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7386
0ff066a9
PZ		 7387 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7388 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7389 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7390
0ff066a9
PZ		 7391 tmp = I915_READ(SOUTH_CHICKEN2);
7392 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7393 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7394
0ff066a9
PZ		 7395 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7396 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7397 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7398}
7399
7400/* WaMPhyProgramming:hsw */
7401static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7402{
7403 uint32_t tmp;
dde86e2d
PZ		 7404
7405 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7406 tmp &= ~(0xFF << 24);
7407 tmp |= (0x12 << 24);
7408 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7409
dde86e2d
PZ		 7410 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7411 tmp |= (1 << 11);
7412 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7413
7414 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7415 tmp |= (1 << 11);
7416 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7417
dde86e2d
PZ		 7418 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7419 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7420 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7421
7422 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7423 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7424 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7425
0ff066a9
PZ		 7426 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7427 tmp &= ~(7 << 13);
7428 tmp |= (5 << 13);
7429 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7430
0ff066a9
PZ		 7431 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7432 tmp &= ~(7 << 13);
7433 tmp |= (5 << 13);
7434 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7435
7436 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7437 tmp &= ~0xFF;
7438 tmp |= 0x1C;
7439 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7440
7441 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7442 tmp &= ~0xFF;
7443 tmp |= 0x1C;
7444 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7445
7446 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7447 tmp &= ~(0xFF << 16);
7448 tmp |= (0x1C << 16);
7449 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7450
7451 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7452 tmp &= ~(0xFF << 16);
7453 tmp |= (0x1C << 16);
7454 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7455
0ff066a9
PZ		 7456 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7457 tmp |= (1 << 27);
7458 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7459
0ff066a9
PZ		 7460 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7461 tmp |= (1 << 27);
7462 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7463
0ff066a9
PZ		 7464 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7465 tmp &= ~(0xF << 28);
7466 tmp |= (4 << 28);
7467 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7468
0ff066a9
PZ		 7469 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7470 tmp &= ~(0xF << 28);
7471 tmp |= (4 << 28);
7472 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7473}
7474
2fa86a1f
PZ		 7475/* Implements 3 different sequences from BSpec chapter "Display iCLK
7476 * Programming" based on the parameters passed:
7477 * - Sequence to enable CLKOUT_DP
7478 * - Sequence to enable CLKOUT_DP without spread
7479 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7480 */
7481static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7482 bool with_fdi)
f31f2d55
PZ		 7483{
7484 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 7485 uint32_t reg, tmp;
7486
7487 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7488 with_spread = true;
7489 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7490 with_fdi, "LP PCH doesn't have FDI\n"))
7491 with_fdi = false;
f31f2d55
PZ		 7492
7493 mutex_lock(&dev_priv->dpio_lock);
7494
7495 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7496 tmp &= ~SBI_SSCCTL_DISABLE;
7497 tmp |= SBI_SSCCTL_PATHALT;
7498 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7499
7500 udelay(24);
7501
2fa86a1f
PZ		 7502 if (with_spread) {
7503 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7504 tmp &= ~SBI_SSCCTL_PATHALT;
7505 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7506
2fa86a1f
PZ		 7507 if (with_fdi) {
7508 lpt_reset_fdi_mphy(dev_priv);
7509 lpt_program_fdi_mphy(dev_priv);
7510 }
7511 }
dde86e2d 7512
2fa86a1f
PZ		 7513 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7514 SBI_GEN0 : SBI_DBUFF0;
7515 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7516 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7517 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 7518
7519 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 7520}
7521
47701c3b
PZ		 7522/* Sequence to disable CLKOUT_DP */
7523static void lpt_disable_clkout_dp(struct drm_device *dev)
7524{
7525 struct drm_i915_private *dev_priv = dev->dev_private;
7526 uint32_t reg, tmp;
7527
7528 mutex_lock(&dev_priv->dpio_lock);
7529
7530 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7531 SBI_GEN0 : SBI_DBUFF0;
7532 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7533 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7534 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7535
7536 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7537 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7538 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7539 tmp |= SBI_SSCCTL_PATHALT;
7540 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7541 udelay(32);
7542 }
7543 tmp |= SBI_SSCCTL_DISABLE;
7544 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7545 }
7546
7547 mutex_unlock(&dev_priv->dpio_lock);
7548}
7549
bf8fa3d3
PZ		 7550static void lpt_init_pch_refclk(struct drm_device *dev)
7551{
bf8fa3d3
PZ		 7552 struct intel_encoder *encoder;
7553 bool has_vga = false;
7554
b2784e15 7555 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 7556 switch (encoder->type) {
7557 case INTEL_OUTPUT_ANALOG:
7558 has_vga = true;
7559 break;
6847d71b
PZ		 7560 default:
7561 break;
bf8fa3d3
PZ		 7562 }
7563 }
7564
47701c3b
PZ		 7565 if (has_vga)
7566 lpt_enable_clkout_dp(dev, true, true);
7567 else
7568 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 7569}
7570
dde86e2d
PZ		 7571/*
7572 * Initialize reference clocks when the driver loads
7573 */
7574void intel_init_pch_refclk(struct drm_device *dev)
7575{
7576 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7577 ironlake_init_pch_refclk(dev);
7578 else if (HAS_PCH_LPT(dev))
7579 lpt_init_pch_refclk(dev);
7580}
7581
55bb9992 7582static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 7583{
55bb9992 7584 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 7585 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 7586 struct drm_atomic_state *state = crtc_state->base.state;
7587 struct drm_connector_state *connector_state;
d9d444cb 7588 struct intel_encoder *encoder;
55bb9992 7589 int num_connectors = 0, i;
d9d444cb
JB		 7590 bool is_lvds = false;
7591
55bb9992
ACO		 7592 for (i = 0; i < state->num_connector; i++) {
7593 if (!state->connectors[i])
d0737e1d
ACO		 7594 continue;
7595
55bb9992
ACO		 7596 connector_state = state->connector_states[i];
7597 if (connector_state->crtc != crtc_state->base.crtc)
7598 continue;
7599
7600 encoder = to_intel_encoder(connector_state->best_encoder);
7601
d9d444cb
JB		 7602 switch (encoder->type) {
7603 case INTEL_OUTPUT_LVDS:
7604 is_lvds = true;
7605 break;
6847d71b
PZ		 7606 default:
7607 break;
d9d444cb
JB		 7608 }
7609 num_connectors++;
7610 }
7611
7612 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 7613 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 7614 dev_priv->vbt.lvds_ssc_freq);
e91e941b 7615 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 7616 }
7617
7618 return 120000;
7619}
7620
6ff93609 7621static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 7622{
c8203565 7623 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 7624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7625 int pipe = intel_crtc->pipe;
c8203565
PZ		 7626 uint32_t val;
7627
78114071 7628 val = 0;
c8203565 7629
6e3c9717 7630 switch (intel_crtc->config->pipe_bpp) {
c8203565 7631 case 18:
dfd07d72 7632 val |= PIPECONF_6BPC;
c8203565
PZ		 7633 break;
7634 case 24:
dfd07d72 7635 val |= PIPECONF_8BPC;
c8203565
PZ		 7636 break;
7637 case 30:
dfd07d72 7638 val |= PIPECONF_10BPC;
c8203565
PZ		 7639 break;
7640 case 36:
dfd07d72 7641 val |= PIPECONF_12BPC;
c8203565
PZ		 7642 break;
7643 default:
cc769b62
PZ		 7644 /* Case prevented by intel_choose_pipe_bpp_dither. */
7645 BUG();
c8203565
PZ		 7646 }
7647
6e3c9717 7648 if (intel_crtc->config->dither)
c8203565
PZ		 7649 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7650
6e3c9717 7651 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 7652 val |= PIPECONF_INTERLACED_ILK;
7653 else
7654 val |= PIPECONF_PROGRESSIVE;
7655
6e3c9717 7656 if (intel_crtc->config->limited_color_range)
3685a8f3 7657 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 7658
c8203565
PZ		 7659 I915_WRITE(PIPECONF(pipe), val);
7660 POSTING_READ(PIPECONF(pipe));
7661}
7662
86d3efce
VS		 7663/*
7664 * Set up the pipe CSC unit.
7665 *
7666 * Currently only full range RGB to limited range RGB conversion
7667 * is supported, but eventually this should handle various
7668 * RGB<->YCbCr scenarios as well.
7669 */
50f3b016 7670static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 7671{
7672 struct drm_device *dev = crtc->dev;
7673 struct drm_i915_private *dev_priv = dev->dev_private;
7674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7675 int pipe = intel_crtc->pipe;
7676 uint16_t coeff = 0x7800; /* 1.0 */
7677
7678 /*
7679 * TODO: Check what kind of values actually come out of the pipe
7680 * with these coeff/postoff values and adjust to get the best
7681 * accuracy. Perhaps we even need to take the bpc value into
7682 * consideration.
7683 */
7684
6e3c9717 7685 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7686 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7687
7688 /*
7689 * GY/GU and RY/RU should be the other way around according
7690 * to BSpec, but reality doesn't agree. Just set them up in
7691 * a way that results in the correct picture.
7692 */
7693 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7694 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7695
7696 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7697 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7698
7699 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7700 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7701
7702 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7703 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7704 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7705
7706 if (INTEL_INFO(dev)->gen > 6) {
7707 uint16_t postoff = 0;
7708
6e3c9717 7709 if (intel_crtc->config->limited_color_range)
32cf0cb0 7710 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 7711
7712 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7713 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7714 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7715
7716 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7717 } else {
7718 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7719
6e3c9717 7720 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7721 mode |= CSC_BLACK_SCREEN_OFFSET;
7722
7723 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7724 }
7725}
7726
6ff93609 7727static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 7728{
756f85cf
PZ		 7729 struct drm_device *dev = crtc->dev;
7730 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 7731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 7732 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7733 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 7734 uint32_t val;
7735
3eff4faa 7736 val = 0;
ee2b0b38 7737
6e3c9717 7738 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 7739 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7740
6e3c9717 7741 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 7742 val |= PIPECONF_INTERLACED_ILK;
7743 else
7744 val |= PIPECONF_PROGRESSIVE;
7745
702e7a56
PZ		 7746 I915_WRITE(PIPECONF(cpu_transcoder), val);
7747 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 7748
7749 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7750 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 7751
3cdf122c 7752 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 7753 val = 0;
7754
6e3c9717 7755 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 7756 case 18:
7757 val |= PIPEMISC_DITHER_6_BPC;
7758 break;
7759 case 24:
7760 val |= PIPEMISC_DITHER_8_BPC;
7761 break;
7762 case 30:
7763 val |= PIPEMISC_DITHER_10_BPC;
7764 break;
7765 case 36:
7766 val |= PIPEMISC_DITHER_12_BPC;
7767 break;
7768 default:
7769 /* Case prevented by pipe_config_set_bpp. */
7770 BUG();
7771 }
7772
6e3c9717 7773 if (intel_crtc->config->dither)
756f85cf
PZ		 7774 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7775
7776 I915_WRITE(PIPEMISC(pipe), val);
7777 }
ee2b0b38
PZ		 7778}
7779
6591c6e4 7780static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 7781 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 7782 intel_clock_t *clock,
7783 bool *has_reduced_clock,
7784 intel_clock_t *reduced_clock)
7785{
7786 struct drm_device *dev = crtc->dev;
7787 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 7788 int refclk;
d4906093 7789 const intel_limit_t *limit;
a16af721 7790 bool ret, is_lvds = false;
79e53945 7791
a93e255f 7792 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 7793
55bb9992 7794 refclk = ironlake_get_refclk(crtc_state);
79e53945 7795
d4906093
ML		 7796 /*
7797 * Returns a set of divisors for the desired target clock with the given
7798 * refclk, or FALSE. The returned values represent the clock equation:
7799 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7800 */
a93e255f
ACO		 7801 limit = intel_limit(crtc_state, refclk);
7802 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7803 crtc_state->port_clock,
ee9300bb 7804 refclk, NULL, clock);
6591c6e4
PZ		 7805 if (!ret)
7806 return false;
cda4b7d3 7807
ddc9003c 7808 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 7809 /*
7810 * Ensure we match the reduced clock's P to the target clock.
7811 * If the clocks don't match, we can't switch the display clock
7812 * by using the FP0/FP1. In such case we will disable the LVDS
7813 * downclock feature.
7814 */
ee9300bb 7815 *has_reduced_clock =
a93e255f 7816 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 7817 dev_priv->lvds_downclock,
7818 refclk, clock,
7819 reduced_clock);
652c393a 7820 }
61e9653f 7821
6591c6e4
PZ		 7822 return true;
7823}
7824
d4b1931c
PZ		 7825int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7826{
7827 /*
7828 * Account for spread spectrum to avoid
7829 * oversubscribing the link. Max center spread
7830 * is 2.5%; use 5% for safety's sake.
7831 */
7832 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 7833 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 7834}
7835
7429e9d4 7836static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 7837{
7429e9d4 7838 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 7839}
7840
de13a2e3 7841static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 7842 struct intel_crtc_state *crtc_state,
7429e9d4 7843 u32 *fp,
9a7c7890 7844 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 7845{
de13a2e3 7846 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 7847 struct drm_device *dev = crtc->dev;
7848 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 7849 struct drm_atomic_state *state = crtc_state->base.state;
7850 struct drm_connector_state *connector_state;
7851 struct intel_encoder *encoder;
de13a2e3 7852 uint32_t dpll;
55bb9992 7853 int factor, num_connectors = 0, i;
09ede541 7854 bool is_lvds = false, is_sdvo = false;
79e53945 7855
55bb9992
ACO		 7856 for (i = 0; i < state->num_connector; i++) {
7857 if (!state->connectors[i])
d0737e1d
ACO		 7858 continue;
7859
55bb9992
ACO		 7860 connector_state = state->connector_states[i];
7861 if (connector_state->crtc != crtc_state->base.crtc)
7862 continue;
7863
7864 encoder = to_intel_encoder(connector_state->best_encoder);
7865
7866 switch (encoder->type) {
79e53945
JB		 7867 case INTEL_OUTPUT_LVDS:
7868 is_lvds = true;
7869 break;
7870 case INTEL_OUTPUT_SDVO:
7d57382e 7871 case INTEL_OUTPUT_HDMI:
79e53945 7872 is_sdvo = true;
79e53945 7873 break;
6847d71b
PZ		 7874 default:
7875 break;
79e53945 7876 }
43565a06 7877
c751ce4f 7878 num_connectors++;
79e53945 7879 }
79e53945 7880
c1858123 7881 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 7882 factor = 21;
7883 if (is_lvds) {
7884 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 7885 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 7886 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 7887 factor = 25;
190f68c5 7888 } else if (crtc_state->sdvo_tv_clock)
8febb297 7889 factor = 20;
c1858123 7890
190f68c5 7891 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 7892 *fp |= FP_CB_TUNE;
2c07245f 7893
9a7c7890
DV		 7894 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7895 *fp2 |= FP_CB_TUNE;
7896
5eddb70b 7897 dpll = 0;
2c07245f 7898
a07d6787
EA		 7899 if (is_lvds)
7900 dpll |= DPLLB_MODE_LVDS;
7901 else
7902 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 7903
190f68c5 7904 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 7905 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 7906
7907 if (is_sdvo)
4a33e48d 7908 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 7909 if (crtc_state->has_dp_encoder)
4a33e48d 7910 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 7911
a07d6787 7912 /* compute bitmask from p1 value */
190f68c5 7913 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 7914 /* also FPA1 */
190f68c5 7915 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 7916
190f68c5 7917 switch (crtc_state->dpll.p2) {
a07d6787
EA		 7918 case 5:
7919 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7920 break;
7921 case 7:
7922 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7923 break;
7924 case 10:
7925 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7926 break;
7927 case 14:
7928 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7929 break;
79e53945
JB		 7930 }
7931
b4c09f3b 7932 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 7933 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 7934 else
7935 dpll |= PLL_REF_INPUT_DREFCLK;
7936
959e16d6 7937 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 7938}
7939
190f68c5
ACO		 7940static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7941 struct intel_crtc_state *crtc_state)
de13a2e3 7942{
c7653199 7943 struct drm_device *dev = crtc->base.dev;
de13a2e3 7944 intel_clock_t clock, reduced_clock;
cbbab5bd 7945 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 7946 bool ok, has_reduced_clock = false;
8b47047b 7947 bool is_lvds = false;
e2b78267 7948 struct intel_shared_dpll *pll;
de13a2e3 7949
409ee761 7950 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 7951
5dc5298b
PZ		 7952 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7953 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 7954
190f68c5 7955 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 7956 &has_reduced_clock, &reduced_clock);
190f68c5 7957 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 7958 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7959 return -EINVAL;
79e53945 7960 }
f47709a9 7961 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7962 if (!crtc_state->clock_set) {
7963 crtc_state->dpll.n = clock.n;
7964 crtc_state->dpll.m1 = clock.m1;
7965 crtc_state->dpll.m2 = clock.m2;
7966 crtc_state->dpll.p1 = clock.p1;
7967 crtc_state->dpll.p2 = clock.p2;
f47709a9 7968 }
79e53945 7969
5dc5298b 7970 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 7971 if (crtc_state->has_pch_encoder) {
7972 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 7973 if (has_reduced_clock)
7429e9d4 7974 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 7975
190f68c5 7976 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 7977 &fp, &reduced_clock,
7978 has_reduced_clock ? &fp2 : NULL);
7979
190f68c5
ACO		 7980 crtc_state->dpll_hw_state.dpll = dpll;
7981 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 7982 if (has_reduced_clock)
190f68c5 7983 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 7984 else
190f68c5 7985 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 7986
190f68c5 7987 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 7988 if (pll == NULL) {
84f44ce7 7989 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 7990 pipe_name(crtc->pipe));
4b645f14
JB		 7991 return -EINVAL;
7992 }
3fb37703 7993 }
79e53945 7994
ab585dea 7995 if (is_lvds && has_reduced_clock)
c7653199 7996 crtc->lowfreq_avail = true;
bcd644e0 7997 else
c7653199 7998 crtc->lowfreq_avail = false;
e2b78267 7999
c8f7a0db 8000 return 0;
79e53945
JB		 8001}
8002
eb14cb74
VS		 8003static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8004 struct intel_link_m_n *m_n)
8005{
8006 struct drm_device *dev = crtc->base.dev;
8007 struct drm_i915_private *dev_priv = dev->dev_private;
8008 enum pipe pipe = crtc->pipe;
8009
8010 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8011 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8012 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8013 & ~TU_SIZE_MASK;
8014 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8015 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8016 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8017}
8018
8019static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8020 enum transcoder transcoder,
b95af8be
VK		 8021 struct intel_link_m_n *m_n,
8022 struct intel_link_m_n *m2_n2)
72419203
DV		 8023{
8024 struct drm_device *dev = crtc->base.dev;
8025 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8026 enum pipe pipe = crtc->pipe;
72419203 8027
eb14cb74
VS		 8028 if (INTEL_INFO(dev)->gen >= 5) {
8029 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8030 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8031 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8032 & ~TU_SIZE_MASK;
8033 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8034 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8035 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8036 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8037 * gen < 8) and if DRRS is supported (to make sure the
8038 * registers are not unnecessarily read).
8039 */
8040 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8041 crtc->config->has_drrs) {
b95af8be
VK		 8042 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8043 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8044 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8045 & ~TU_SIZE_MASK;
8046 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8047 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8048 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8049 }
eb14cb74
VS		 8050 } else {
8051 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8052 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8053 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8054 & ~TU_SIZE_MASK;
8055 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8056 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8057 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8058 }
8059}
8060
8061void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8062 struct intel_crtc_state *pipe_config)
eb14cb74 8063{
681a8504 8064 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8065 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8066 else
8067 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8068 &pipe_config->dp_m_n,
8069 &pipe_config->dp_m2_n2);
eb14cb74 8070}
72419203 8071
eb14cb74 8072static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8073 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8074{
8075 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8076 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8077}
8078
bd2e244f 8079static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8080 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8081{
8082 struct drm_device *dev = crtc->base.dev;
8083 struct drm_i915_private *dev_priv = dev->dev_private;
8084 uint32_t tmp;
8085
8086 tmp = I915_READ(PS_CTL(crtc->pipe));
8087
8088 if (tmp & PS_ENABLE) {
8089 pipe_config->pch_pfit.enabled = true;
8090 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
8091 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
8092 }
8093}
8094
5724dbd1
DL		 8095static void
8096skylake_get_initial_plane_config(struct intel_crtc *crtc,
8097 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8098{
8099 struct drm_device *dev = crtc->base.dev;
8100 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8101 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8102 int pipe = crtc->pipe;
8103 int fourcc, pixel_format;
6761dd31 8104 unsigned int aligned_height;
bc8d7dff 8105 struct drm_framebuffer *fb;
1b842c89 8106 struct intel_framebuffer *intel_fb;
bc8d7dff 8107
d9806c9f 8108 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8109 if (!intel_fb) {
bc8d7dff
DL		 8110 DRM_DEBUG_KMS("failed to alloc fb\n");
8111 return;
8112 }
8113
1b842c89
DL		 8114 fb = &intel_fb->base;
8115
bc8d7dff 8116 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8117 if (!(val & PLANE_CTL_ENABLE))
8118 goto error;
8119
bc8d7dff
DL		 8120 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8121 fourcc = skl_format_to_fourcc(pixel_format,
8122 val & PLANE_CTL_ORDER_RGBX,
8123 val & PLANE_CTL_ALPHA_MASK);
8124 fb->pixel_format = fourcc;
8125 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8126
40f46283
DL		 8127 tiling = val & PLANE_CTL_TILED_MASK;
8128 switch (tiling) {
8129 case PLANE_CTL_TILED_LINEAR:
8130 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8131 break;
8132 case PLANE_CTL_TILED_X:
8133 plane_config->tiling = I915_TILING_X;
8134 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8135 break;
8136 case PLANE_CTL_TILED_Y:
8137 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8138 break;
8139 case PLANE_CTL_TILED_YF:
8140 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8141 break;
8142 default:
8143 MISSING_CASE(tiling);
8144 goto error;
8145 }
8146
bc8d7dff
DL		 8147 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8148 plane_config->base = base;
8149
8150 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8151
8152 val = I915_READ(PLANE_SIZE(pipe, 0));
8153 fb->height = ((val >> 16) & 0xfff) + 1;
8154 fb->width = ((val >> 0) & 0x1fff) + 1;
8155
8156 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8157 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8158 fb->pixel_format);
bc8d7dff
DL		 8159 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8160
8161 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8162 fb->pixel_format,
8163 fb->modifier[0]);
bc8d7dff 8164
f37b5c2b 8165 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8166
8167 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8168 pipe_name(pipe), fb->width, fb->height,
8169 fb->bits_per_pixel, base, fb->pitches[0],
8170 plane_config->size);
8171
2d14030b 8172 plane_config->fb = intel_fb;
bc8d7dff
DL		 8173 return;
8174
8175error:
8176 kfree(fb);
8177}
8178
2fa2fe9a 8179static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8180 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8181{
8182 struct drm_device *dev = crtc->base.dev;
8183 struct drm_i915_private *dev_priv = dev->dev_private;
8184 uint32_t tmp;
8185
8186 tmp = I915_READ(PF_CTL(crtc->pipe));
8187
8188 if (tmp & PF_ENABLE) {
fd4daa9c 8189 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8190 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8191 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8192
8193 /* We currently do not free assignements of panel fitters on
8194 * ivb/hsw (since we don't use the higher upscaling modes which
8195 * differentiates them) so just WARN about this case for now. */
8196 if (IS_GEN7(dev)) {
8197 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8198 PF_PIPE_SEL_IVB(crtc->pipe));
8199 }
2fa2fe9a 8200 }
79e53945
JB		 8201}
8202
5724dbd1
DL		 8203static void
8204ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8205 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8206{
8207 struct drm_device *dev = crtc->base.dev;
8208 struct drm_i915_private *dev_priv = dev->dev_private;
8209 u32 val, base, offset;
aeee5a49 8210 int pipe = crtc->pipe;
4c6baa59 8211 int fourcc, pixel_format;
6761dd31 8212 unsigned int aligned_height;
b113d5ee 8213 struct drm_framebuffer *fb;
1b842c89 8214 struct intel_framebuffer *intel_fb;
4c6baa59 8215
42a7b088
DL		 8216 val = I915_READ(DSPCNTR(pipe));
8217 if (!(val & DISPLAY_PLANE_ENABLE))
8218 return;
8219
d9806c9f 8220 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8221 if (!intel_fb) {
4c6baa59
JB		 8222 DRM_DEBUG_KMS("failed to alloc fb\n");
8223 return;
8224 }
8225
1b842c89
DL		 8226 fb = &intel_fb->base;
8227
18c5247e
DV		 8228 if (INTEL_INFO(dev)->gen >= 4) {
8229 if (val & DISPPLANE_TILED) {
49af449b 8230 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8231 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8232 }
8233 }
4c6baa59
JB		 8234
8235 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8236 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8237 fb->pixel_format = fourcc;
8238 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8239
aeee5a49 8240 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8241 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8242 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8243 } else {
49af449b 8244 if (plane_config->tiling)
aeee5a49 8245 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8246 else
aeee5a49 8247 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8248 }
8249 plane_config->base = base;
8250
8251 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8252 fb->width = ((val >> 16) & 0xfff) + 1;
8253 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8254
8255 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8256 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8257
b113d5ee 8258 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8259 fb->pixel_format,
8260 fb->modifier[0]);
4c6baa59 8261
f37b5c2b 8262 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8263
2844a921
DL		 8264 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8265 pipe_name(pipe), fb->width, fb->height,
8266 fb->bits_per_pixel, base, fb->pitches[0],
8267 plane_config->size);
b113d5ee 8268
2d14030b 8269 plane_config->fb = intel_fb;
4c6baa59
JB		 8270}
8271
0e8ffe1b 8272static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8273 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8274{
8275 struct drm_device *dev = crtc->base.dev;
8276 struct drm_i915_private *dev_priv = dev->dev_private;
8277 uint32_t tmp;
8278
f458ebbc
DV		 8279 if (!intel_display_power_is_enabled(dev_priv,
8280 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8281 return false;
8282
e143a21c 8283 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8284 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8285
0e8ffe1b
DV		 8286 tmp = I915_READ(PIPECONF(crtc->pipe));
8287 if (!(tmp & PIPECONF_ENABLE))
8288 return false;
8289
42571aef
VS		 8290 switch (tmp & PIPECONF_BPC_MASK) {
8291 case PIPECONF_6BPC:
8292 pipe_config->pipe_bpp = 18;
8293 break;
8294 case PIPECONF_8BPC:
8295 pipe_config->pipe_bpp = 24;
8296 break;
8297 case PIPECONF_10BPC:
8298 pipe_config->pipe_bpp = 30;
8299 break;
8300 case PIPECONF_12BPC:
8301 pipe_config->pipe_bpp = 36;
8302 break;
8303 default:
8304 break;
8305 }
8306
b5a9fa09
DV		 8307 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8308 pipe_config->limited_color_range = true;
8309
ab9412ba 8310 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8311 struct intel_shared_dpll *pll;
8312
88adfff1
DV		 8313 pipe_config->has_pch_encoder = true;
8314
627eb5a3
DV		 8315 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8316 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8317 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8318
8319 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8320
c0d43d62 8321 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8322 pipe_config->shared_dpll =
8323 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8324 } else {
8325 tmp = I915_READ(PCH_DPLL_SEL);
8326 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8327 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8328 else
8329 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8330 }
66e985c0
DV		 8331
8332 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8333
8334 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8335 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8336
8337 tmp = pipe_config->dpll_hw_state.dpll;
8338 pipe_config->pixel_multiplier =
8339 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8340 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8341
8342 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8343 } else {
8344 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8345 }
8346
1bd1bd80
DV		 8347 intel_get_pipe_timings(crtc, pipe_config);
8348
2fa2fe9a
DV		 8349 ironlake_get_pfit_config(crtc, pipe_config);
8350
0e8ffe1b
DV		 8351 return true;
8352}
8353
be256dc7
PZ		 8354static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8355{
8356 struct drm_device *dev = dev_priv->dev;
be256dc7 8357 struct intel_crtc *crtc;
be256dc7 8358
d3fcc808 8359 for_each_intel_crtc(dev, crtc)
e2c719b7 8360 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8361 pipe_name(crtc->pipe));
8362
e2c719b7
RC		 8363 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8364 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8365 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8366 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8367 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8368 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8369 "CPU PWM1 enabled\n");
c5107b87 8370 if (IS_HASWELL(dev))
e2c719b7 8371 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8372 "CPU PWM2 enabled\n");
e2c719b7 8373 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8374 "PCH PWM1 enabled\n");
e2c719b7 8375 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8376 "Utility pin enabled\n");
e2c719b7 8377 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8378
9926ada1
PZ		 8379 /*
8380 * In theory we can still leave IRQs enabled, as long as only the HPD
8381 * interrupts remain enabled. We used to check for that, but since it's
8382 * gen-specific and since we only disable LCPLL after we fully disable
8383 * the interrupts, the check below should be enough.
8384 */
e2c719b7 8385 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8386}
8387
9ccd5aeb
PZ		 8388static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8389{
8390 struct drm_device *dev = dev_priv->dev;
8391
8392 if (IS_HASWELL(dev))
8393 return I915_READ(D_COMP_HSW);
8394 else
8395 return I915_READ(D_COMP_BDW);
8396}
8397
3c4c9b81
PZ		 8398static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8399{
8400 struct drm_device *dev = dev_priv->dev;
8401
8402 if (IS_HASWELL(dev)) {
8403 mutex_lock(&dev_priv->rps.hw_lock);
8404 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8405 val))
f475dadf 8406 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8407 mutex_unlock(&dev_priv->rps.hw_lock);
8408 } else {
9ccd5aeb
PZ		 8409 I915_WRITE(D_COMP_BDW, val);
8410 POSTING_READ(D_COMP_BDW);
3c4c9b81 8411 }
be256dc7
PZ		 8412}
8413
8414/*
8415 * This function implements pieces of two sequences from BSpec:
8416 * - Sequence for display software to disable LCPLL
8417 * - Sequence for display software to allow package C8+
8418 * The steps implemented here are just the steps that actually touch the LCPLL
8419 * register. Callers should take care of disabling all the display engine
8420 * functions, doing the mode unset, fixing interrupts, etc.
8421 */
6ff58d53
PZ		 8422static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8423 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8424{
8425 uint32_t val;
8426
8427 assert_can_disable_lcpll(dev_priv);
8428
8429 val = I915_READ(LCPLL_CTL);
8430
8431 if (switch_to_fclk) {
8432 val |= LCPLL_CD_SOURCE_FCLK;
8433 I915_WRITE(LCPLL_CTL, val);
8434
8435 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8436 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8437 DRM_ERROR("Switching to FCLK failed\n");
8438
8439 val = I915_READ(LCPLL_CTL);
8440 }
8441
8442 val |= LCPLL_PLL_DISABLE;
8443 I915_WRITE(LCPLL_CTL, val);
8444 POSTING_READ(LCPLL_CTL);
8445
8446 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8447 DRM_ERROR("LCPLL still locked\n");
8448
9ccd5aeb 8449 val = hsw_read_dcomp(dev_priv);
be256dc7 8450 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8451 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8452 ndelay(100);
8453
9ccd5aeb
PZ		 8454 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8455 1))
be256dc7
PZ		 8456 DRM_ERROR("D_COMP RCOMP still in progress\n");
8457
8458 if (allow_power_down) {
8459 val = I915_READ(LCPLL_CTL);
8460 val |= LCPLL_POWER_DOWN_ALLOW;
8461 I915_WRITE(LCPLL_CTL, val);
8462 POSTING_READ(LCPLL_CTL);
8463 }
8464}
8465
8466/*
8467 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8468 * source.
8469 */
6ff58d53 8470static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 8471{
8472 uint32_t val;
8473
8474 val = I915_READ(LCPLL_CTL);
8475
8476 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8477 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8478 return;
8479
a8a8bd54
PZ		 8480 /*
8481 * Make sure we're not on PC8 state before disabling PC8, otherwise
8482 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8483 */
59bad947 8484 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8485
be256dc7
PZ		 8486 if (val & LCPLL_POWER_DOWN_ALLOW) {
8487 val &= ~LCPLL_POWER_DOWN_ALLOW;
8488 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8489 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 8490 }
8491
9ccd5aeb 8492 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 8493 val |= D_COMP_COMP_FORCE;
8494 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8495 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8496
8497 val = I915_READ(LCPLL_CTL);
8498 val &= ~LCPLL_PLL_DISABLE;
8499 I915_WRITE(LCPLL_CTL, val);
8500
8501 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8502 DRM_ERROR("LCPLL not locked yet\n");
8503
8504 if (val & LCPLL_CD_SOURCE_FCLK) {
8505 val = I915_READ(LCPLL_CTL);
8506 val &= ~LCPLL_CD_SOURCE_FCLK;
8507 I915_WRITE(LCPLL_CTL, val);
8508
8509 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8510 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8511 DRM_ERROR("Switching back to LCPLL failed\n");
8512 }
215733fa 8513
59bad947 8514 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 8515}
8516
765dab67
PZ		 8517/*
8518 * Package states C8 and deeper are really deep PC states that can only be
8519 * reached when all the devices on the system allow it, so even if the graphics
8520 * device allows PC8+, it doesn't mean the system will actually get to these
8521 * states. Our driver only allows PC8+ when going into runtime PM.
8522 *
8523 * The requirements for PC8+ are that all the outputs are disabled, the power
8524 * well is disabled and most interrupts are disabled, and these are also
8525 * requirements for runtime PM. When these conditions are met, we manually do
8526 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8527 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8528 * hang the machine.
8529 *
8530 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8531 * the state of some registers, so when we come back from PC8+ we need to
8532 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8533 * need to take care of the registers kept by RC6. Notice that this happens even
8534 * if we don't put the device in PCI D3 state (which is what currently happens
8535 * because of the runtime PM support).
8536 *
8537 * For more, read "Display Sequences for Package C8" on the hardware
8538 * documentation.
8539 */
a14cb6fc 8540void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 8541{
c67a470b
PZ		 8542 struct drm_device *dev = dev_priv->dev;
8543 uint32_t val;
8544
c67a470b
PZ		 8545 DRM_DEBUG_KMS("Enabling package C8+\n");
8546
c67a470b
PZ		 8547 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8548 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8549 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8550 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8551 }
8552
8553 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 8554 hsw_disable_lcpll(dev_priv, true, true);
8555}
8556
a14cb6fc 8557void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 8558{
8559 struct drm_device *dev = dev_priv->dev;
8560 uint32_t val;
8561
c67a470b
PZ		 8562 DRM_DEBUG_KMS("Disabling package C8+\n");
8563
8564 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 8565 lpt_init_pch_refclk(dev);
8566
8567 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8568 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8569 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8570 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8571 }
8572
8573 intel_prepare_ddi(dev);
c67a470b
PZ		 8574}
8575
190f68c5
ACO		 8576static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8577 struct intel_crtc_state *crtc_state)
09b4ddf9 8578{
190f68c5 8579 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 8580 return -EINVAL;
716c2e55 8581
c7653199 8582 crtc->lowfreq_avail = false;
644cef34 8583
c8f7a0db 8584 return 0;
79e53945
JB		 8585}
8586
96b7dfb7
S		 8587static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8588 enum port port,
5cec258b 8589 struct intel_crtc_state *pipe_config)
96b7dfb7 8590{
3148ade7 8591 u32 temp, dpll_ctl1;
96b7dfb7
S		 8592
8593 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8594 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8595
8596 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 8597 case SKL_DPLL0:
8598 /*
8599 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8600 * of the shared DPLL framework and thus needs to be read out
8601 * separately
8602 */
8603 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8604 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8605 break;
96b7dfb7
S		 8606 case SKL_DPLL1:
8607 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8608 break;
8609 case SKL_DPLL2:
8610 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8611 break;
8612 case SKL_DPLL3:
8613 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8614 break;
96b7dfb7
S		 8615 }
8616}
8617
7d2c8175
DL		 8618static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8619 enum port port,
5cec258b 8620 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 8621{
8622 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8623
8624 switch (pipe_config->ddi_pll_sel) {
8625 case PORT_CLK_SEL_WRPLL1:
8626 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8627 break;
8628 case PORT_CLK_SEL_WRPLL2:
8629 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8630 break;
8631 }
8632}
8633
26804afd 8634static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 8635 struct intel_crtc_state *pipe_config)
26804afd
DV		 8636{
8637 struct drm_device *dev = crtc->base.dev;
8638 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 8639 struct intel_shared_dpll *pll;
26804afd
DV		 8640 enum port port;
8641 uint32_t tmp;
8642
8643 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8644
8645 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8646
96b7dfb7
S		 8647 if (IS_SKYLAKE(dev))
8648 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8649 else
8650 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 8651
d452c5b6
DV		 8652 if (pipe_config->shared_dpll >= 0) {
8653 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8654
8655 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8656 &pipe_config->dpll_hw_state));
8657 }
8658
26804afd
DV		 8659 /*
8660 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8661 * DDI E. So just check whether this pipe is wired to DDI E and whether
8662 * the PCH transcoder is on.
8663 */
ca370455
DL		 8664 if (INTEL_INFO(dev)->gen < 9 &&
8665 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 8666 pipe_config->has_pch_encoder = true;
8667
8668 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8669 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8670 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8671
8672 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8673 }
8674}
8675
0e8ffe1b 8676static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8677 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8678{
8679 struct drm_device *dev = crtc->base.dev;
8680 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 8681 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 8682 uint32_t tmp;
8683
f458ebbc 8684 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 8685 POWER_DOMAIN_PIPE(crtc->pipe)))
8686 return false;
8687
e143a21c 8688 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 8689 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8690
eccb140b
DV		 8691 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8692 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8693 enum pipe trans_edp_pipe;
8694 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8695 default:
8696 WARN(1, "unknown pipe linked to edp transcoder\n");
8697 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8698 case TRANS_DDI_EDP_INPUT_A_ON:
8699 trans_edp_pipe = PIPE_A;
8700 break;
8701 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8702 trans_edp_pipe = PIPE_B;
8703 break;
8704 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8705 trans_edp_pipe = PIPE_C;
8706 break;
8707 }
8708
8709 if (trans_edp_pipe == crtc->pipe)
8710 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8711 }
8712
f458ebbc 8713 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 8714 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 8715 return false;
8716
eccb140b 8717 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 8718 if (!(tmp & PIPECONF_ENABLE))
8719 return false;
8720
26804afd 8721 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 8722
1bd1bd80
DV		 8723 intel_get_pipe_timings(crtc, pipe_config);
8724
2fa2fe9a 8725 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f
JB		 8726 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8727 if (IS_SKYLAKE(dev))
8728 skylake_get_pfit_config(crtc, pipe_config);
8729 else
8730 ironlake_get_pfit_config(crtc, pipe_config);
8731 }
88adfff1 8732
e59150dc
JB		 8733 if (IS_HASWELL(dev))
8734 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8735 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 8736
ebb69c95
CT		 8737 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8738 pipe_config->pixel_multiplier =
8739 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8740 } else {
8741 pipe_config->pixel_multiplier = 1;
8742 }
6c49f241 8743
0e8ffe1b
DV		 8744 return true;
8745}
8746
560b85bb
CW		 8747static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8748{
8749 struct drm_device *dev = crtc->dev;
8750 struct drm_i915_private *dev_priv = dev->dev_private;
8751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 8752 uint32_t cntl = 0, size = 0;
560b85bb 8753
dc41c154 8754 if (base) {
3dd512fb
MR		 8755 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8756 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 8757 unsigned int stride = roundup_pow_of_two(width) * 4;
8758
8759 switch (stride) {
8760 default:
8761 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8762 width, stride);
8763 stride = 256;
8764 /* fallthrough */
8765 case 256:
8766 case 512:
8767 case 1024:
8768 case 2048:
8769 break;
4b0e333e
CW		 8770 }
8771
dc41c154
VS		 8772 cntl |= CURSOR_ENABLE |
8773 CURSOR_GAMMA_ENABLE |
8774 CURSOR_FORMAT_ARGB |
8775 CURSOR_STRIDE(stride);
8776
8777 size = (height << 12) | width;
4b0e333e 8778 }
560b85bb 8779
dc41c154
VS		 8780 if (intel_crtc->cursor_cntl != 0 &&
8781 (intel_crtc->cursor_base != base ||
8782 intel_crtc->cursor_size != size ||
8783 intel_crtc->cursor_cntl != cntl)) {
8784 /* On these chipsets we can only modify the base/size/stride
8785 * whilst the cursor is disabled.
8786 */
8787 I915_WRITE(_CURACNTR, 0);
4b0e333e 8788 POSTING_READ(_CURACNTR);
dc41c154 8789 intel_crtc->cursor_cntl = 0;
4b0e333e 8790 }
560b85bb 8791
99d1f387 8792 if (intel_crtc->cursor_base != base) {
9db4a9c7 8793 I915_WRITE(_CURABASE, base);
99d1f387
VS		 8794 intel_crtc->cursor_base = base;
8795 }
4726e0b0 8796
dc41c154
VS		 8797 if (intel_crtc->cursor_size != size) {
8798 I915_WRITE(CURSIZE, size);
8799 intel_crtc->cursor_size = size;
4b0e333e 8800 }
560b85bb 8801
4b0e333e 8802 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 8803 I915_WRITE(_CURACNTR, cntl);
8804 POSTING_READ(_CURACNTR);
4b0e333e 8805 intel_crtc->cursor_cntl = cntl;
560b85bb 8806 }
560b85bb
CW		 8807}
8808
560b85bb 8809static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 8810{
8811 struct drm_device *dev = crtc->dev;
8812 struct drm_i915_private *dev_priv = dev->dev_private;
8813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8814 int pipe = intel_crtc->pipe;
4b0e333e
CW		 8815 uint32_t cntl;
8816
8817 cntl = 0;
8818 if (base) {
8819 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 8820 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 8821 case 64:
8822 cntl |= CURSOR_MODE_64_ARGB_AX;
8823 break;
8824 case 128:
8825 cntl |= CURSOR_MODE_128_ARGB_AX;
8826 break;
8827 case 256:
8828 cntl |= CURSOR_MODE_256_ARGB_AX;
8829 break;
8830 default:
3dd512fb 8831 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 8832 return;
65a21cd6 8833 }
4b0e333e 8834 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 8835
8836 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8837 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 8838 }
65a21cd6 8839
8e7d688b 8840 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 8841 cntl |= CURSOR_ROTATE_180;
8842
4b0e333e
CW		 8843 if (intel_crtc->cursor_cntl != cntl) {
8844 I915_WRITE(CURCNTR(pipe), cntl);
8845 POSTING_READ(CURCNTR(pipe));
8846 intel_crtc->cursor_cntl = cntl;
65a21cd6 8847 }
4b0e333e 8848
65a21cd6 8849 /* and commit changes on next vblank */
5efb3e28
VS		 8850 I915_WRITE(CURBASE(pipe), base);
8851 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 8852
8853 intel_crtc->cursor_base = base;
65a21cd6
JB		 8854}
8855
cda4b7d3 8856/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 8857static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8858 bool on)
cda4b7d3
CW		 8859{
8860 struct drm_device *dev = crtc->dev;
8861 struct drm_i915_private *dev_priv = dev->dev_private;
8862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8863 int pipe = intel_crtc->pipe;
3d7d6510
MR		 8864 int x = crtc->cursor_x;
8865 int y = crtc->cursor_y;
d6e4db15 8866 u32 base = 0, pos = 0;
cda4b7d3 8867
d6e4db15 8868 if (on)
cda4b7d3 8869 base = intel_crtc->cursor_addr;
cda4b7d3 8870
6e3c9717 8871 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 8872 base = 0;
8873
6e3c9717 8874 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 8875 base = 0;
8876
8877 if (x < 0) {
3dd512fb 8878 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 8879 base = 0;
8880
8881 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8882 x = -x;
8883 }
8884 pos |= x << CURSOR_X_SHIFT;
8885
8886 if (y < 0) {
3dd512fb 8887 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 8888 base = 0;
8889
8890 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8891 y = -y;
8892 }
8893 pos |= y << CURSOR_Y_SHIFT;
8894
4b0e333e 8895 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 8896 return;
8897
5efb3e28
VS		 8898 I915_WRITE(CURPOS(pipe), pos);
8899
4398ad45
VS		 8900 /* ILK+ do this automagically */
8901 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 8902 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 8903 base += (intel_crtc->base.cursor->state->crtc_h *
8904 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 8905 }
8906
8ac54669 8907 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 8908 i845_update_cursor(crtc, base);
8909 else
8910 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 8911}
8912
dc41c154
VS		 8913static bool cursor_size_ok(struct drm_device *dev,
8914 uint32_t width, uint32_t height)
8915{
8916 if (width == 0 || height == 0)
8917 return false;
8918
8919 /*
8920 * 845g/865g are special in that they are only limited by
8921 * the width of their cursors, the height is arbitrary up to
8922 * the precision of the register. Everything else requires
8923 * square cursors, limited to a few power-of-two sizes.
8924 */
8925 if (IS_845G(dev) || IS_I865G(dev)) {
8926 if ((width & 63) != 0)
8927 return false;
8928
8929 if (width > (IS_845G(dev) ? 64 : 512))
8930 return false;
8931
8932 if (height > 1023)
8933 return false;
8934 } else {
8935 switch (width | height) {
8936 case 256:
8937 case 128:
8938 if (IS_GEN2(dev))
8939 return false;
8940 case 64:
8941 break;
8942 default:
8943 return false;
8944 }
8945 }
8946
8947 return true;
8948}
8949
79e53945 8950static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 8951 u16 *blue, uint32_t start, uint32_t size)
79e53945 8952{
7203425a 8953 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 8954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 8955
7203425a 8956 for (i = start; i < end; i++) {
79e53945
JB		 8957 intel_crtc->lut_r[i] = red[i] >> 8;
8958 intel_crtc->lut_g[i] = green[i] >> 8;
8959 intel_crtc->lut_b[i] = blue[i] >> 8;
8960 }
8961
8962 intel_crtc_load_lut(crtc);
8963}
8964
79e53945
JB		 8965/* VESA 640x480x72Hz mode to set on the pipe */
8966static struct drm_display_mode load_detect_mode = {
8967 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8968 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8969};
8970
a8bb6818
DV		 8971struct drm_framebuffer *
8972__intel_framebuffer_create(struct drm_device *dev,
8973 struct drm_mode_fb_cmd2 *mode_cmd,
8974 struct drm_i915_gem_object *obj)
d2dff872
CW		 8975{
8976 struct intel_framebuffer *intel_fb;
8977 int ret;
8978
8979 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8980 if (!intel_fb) {
6ccb81f2 8981 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 8982 return ERR_PTR(-ENOMEM);
8983 }
8984
8985 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 8986 if (ret)
8987 goto err;
d2dff872
CW		 8988
8989 return &intel_fb->base;
dd4916c5 8990err:
6ccb81f2 8991 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 8992 kfree(intel_fb);
8993
8994 return ERR_PTR(ret);
d2dff872
CW		 8995}
8996
b5ea642a 8997static struct drm_framebuffer *
a8bb6818
DV		 8998intel_framebuffer_create(struct drm_device *dev,
8999 struct drm_mode_fb_cmd2 *mode_cmd,
9000 struct drm_i915_gem_object *obj)
9001{
9002 struct drm_framebuffer *fb;
9003 int ret;
9004
9005 ret = i915_mutex_lock_interruptible(dev);
9006 if (ret)
9007 return ERR_PTR(ret);
9008 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9009 mutex_unlock(&dev->struct_mutex);
9010
9011 return fb;
9012}
9013
d2dff872
CW		 9014static u32
9015intel_framebuffer_pitch_for_width(int width, int bpp)
9016{
9017 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9018 return ALIGN(pitch, 64);
9019}
9020
9021static u32
9022intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9023{
9024 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9025 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9026}
9027
9028static struct drm_framebuffer *
9029intel_framebuffer_create_for_mode(struct drm_device *dev,
9030 struct drm_display_mode *mode,
9031 int depth, int bpp)
9032{
9033 struct drm_i915_gem_object *obj;
0fed39bd 9034 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9035
9036 obj = i915_gem_alloc_object(dev,
9037 intel_framebuffer_size_for_mode(mode, bpp));
9038 if (obj == NULL)
9039 return ERR_PTR(-ENOMEM);
9040
9041 mode_cmd.width = mode->hdisplay;
9042 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9043 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9044 bpp);
5ca0c34a 9045 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9046
9047 return intel_framebuffer_create(dev, &mode_cmd, obj);
9048}
9049
9050static struct drm_framebuffer *
9051mode_fits_in_fbdev(struct drm_device *dev,
9052 struct drm_display_mode *mode)
9053{
4520f53a 9054#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9055 struct drm_i915_private *dev_priv = dev->dev_private;
9056 struct drm_i915_gem_object *obj;
9057 struct drm_framebuffer *fb;
9058
4c0e5528 9059 if (!dev_priv->fbdev)
d2dff872
CW		 9060 return NULL;
9061
4c0e5528 9062 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9063 return NULL;
9064
4c0e5528
DV		 9065 obj = dev_priv->fbdev->fb->obj;
9066 BUG_ON(!obj);
9067
8bcd4553 9068 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9069 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9070 fb->bits_per_pixel))
d2dff872
CW		 9071 return NULL;
9072
01f2c773 9073 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9074 return NULL;
9075
9076 return fb;
4520f53a
DV		 9077#else
9078 return NULL;
9079#endif
d2dff872
CW		 9080}
9081
d2434ab7 9082bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9083 struct drm_display_mode *mode,
51fd371b
RC		 9084 struct intel_load_detect_pipe *old,
9085 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9086{
9087 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9088 struct intel_encoder *intel_encoder =
9089 intel_attached_encoder(connector);
79e53945 9090 struct drm_crtc *possible_crtc;
4ef69c7a 9091 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9092 struct drm_crtc *crtc = NULL;
9093 struct drm_device *dev = encoder->dev;
94352cf9 9094 struct drm_framebuffer *fb;
51fd371b 9095 struct drm_mode_config *config = &dev->mode_config;
83a57153 9096 struct drm_atomic_state *state = NULL;
944b0c76 9097 struct drm_connector_state *connector_state;
51fd371b 9098 int ret, i = -1;
79e53945 9099
d2dff872 9100 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9101 connector->base.id, connector->name,
8e329a03 9102 encoder->base.id, encoder->name);
d2dff872 9103
51fd371b
RC		 9104retry:
9105 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9106 if (ret)
9107 goto fail_unlock;
6e9f798d 9108
79e53945
JB		 9109 /*
9110 * Algorithm gets a little messy:
7a5e4805 9111 *
79e53945
JB		 9112 * - if the connector already has an assigned crtc, use it (but make
9113 * sure it's on first)
7a5e4805 9114 *
79e53945
JB		 9115 * - try to find the first unused crtc that can drive this connector,
9116 * and use that if we find one
79e53945
JB		 9117 */
9118
9119 /* See if we already have a CRTC for this connector */
9120 if (encoder->crtc) {
9121 crtc = encoder->crtc;
8261b191 9122
51fd371b 9123 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9124 if (ret)
9125 goto fail_unlock;
9126 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9127 if (ret)
9128 goto fail_unlock;
7b24056b 9129
24218aac 9130 old->dpms_mode = connector->dpms;
8261b191
CW		 9131 old->load_detect_temp = false;
9132
9133 /* Make sure the crtc and connector are running */
24218aac
DV		 9134 if (connector->dpms != DRM_MODE_DPMS_ON)
9135 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9136
7173188d 9137 return true;
79e53945
JB		 9138 }
9139
9140 /* Find an unused one (if possible) */
70e1e0ec 9141 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9142 i++;
9143 if (!(encoder->possible_crtcs & (1 << i)))
9144 continue;
83d65738 9145 if (possible_crtc->state->enable)
a459249c
VS		 9146 continue;
9147 /* This can occur when applying the pipe A quirk on resume. */
9148 if (to_intel_crtc(possible_crtc)->new_enabled)
9149 continue;
9150
9151 crtc = possible_crtc;
9152 break;
79e53945
JB		 9153 }
9154
9155 /*
9156 * If we didn't find an unused CRTC, don't use any.
9157 */
9158 if (!crtc) {
7173188d 9159 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9160 goto fail_unlock;
79e53945
JB		 9161 }
9162
51fd371b
RC		 9163 ret = drm_modeset_lock(&crtc->mutex, ctx);
9164 if (ret)
4d02e2de
DV		 9165 goto fail_unlock;
9166 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9167 if (ret)
51fd371b 9168 goto fail_unlock;
fc303101
DV		 9169 intel_encoder->new_crtc = to_intel_crtc(crtc);
9170 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9171
9172 intel_crtc = to_intel_crtc(crtc);
412b61d8 9173 intel_crtc->new_enabled = true;
6e3c9717 9174 intel_crtc->new_config = intel_crtc->config;
24218aac 9175 old->dpms_mode = connector->dpms;
8261b191 9176 old->load_detect_temp = true;
d2dff872 9177 old->release_fb = NULL;
79e53945 9178
83a57153
ACO		 9179 state = drm_atomic_state_alloc(dev);
9180 if (!state)
9181 return false;
9182
9183 state->acquire_ctx = ctx;
9184
944b0c76
ACO		 9185 connector_state = drm_atomic_get_connector_state(state, connector);
9186 if (IS_ERR(connector_state)) {
9187 ret = PTR_ERR(connector_state);
9188 goto fail;
9189 }
9190
9191 connector_state->crtc = crtc;
9192 connector_state->best_encoder = &intel_encoder->base;
9193
6492711d
CW		 9194 if (!mode)
9195 mode = &load_detect_mode;
79e53945 9196
d2dff872
CW		 9197 /* We need a framebuffer large enough to accommodate all accesses
9198 * that the plane may generate whilst we perform load detection.
9199 * We can not rely on the fbcon either being present (we get called
9200 * during its initialisation to detect all boot displays, or it may
9201 * not even exist) or that it is large enough to satisfy the
9202 * requested mode.
9203 */
94352cf9
DV		 9204 fb = mode_fits_in_fbdev(dev, mode);
9205 if (fb == NULL) {
d2dff872 9206 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9207 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9208 old->release_fb = fb;
d2dff872
CW		 9209 } else
9210 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9211 if (IS_ERR(fb)) {
d2dff872 9212 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9213 goto fail;
79e53945 9214 }
79e53945 9215
83a57153 9216 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
6492711d 9217 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9218 if (old->release_fb)
9219 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9220 goto fail;
79e53945 9221 }
9128b040 9222 crtc->primary->crtc = crtc;
7173188d 9223
79e53945 9224 /* let the connector get through one full cycle before testing */
9d0498a2 9225 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9226 return true;
412b61d8
VS		 9227
9228 fail:
83d65738 9229 intel_crtc->new_enabled = crtc->state->enable;
412b61d8 9230 if (intel_crtc->new_enabled)
6e3c9717 9231 intel_crtc->new_config = intel_crtc->config;
412b61d8
VS		 9232 else
9233 intel_crtc->new_config = NULL;
51fd371b 9234fail_unlock:
83a57153
ACO		 9235 if (state) {
9236 drm_atomic_state_free(state);
9237 state = NULL;
9238 }
9239
51fd371b
RC		 9240 if (ret == -EDEADLK) {
9241 drm_modeset_backoff(ctx);
9242 goto retry;
9243 }
9244
412b61d8 9245 return false;
79e53945
JB		 9246}
9247
d2434ab7 9248void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9249 struct intel_load_detect_pipe *old,
9250 struct drm_modeset_acquire_ctx *ctx)
79e53945 9251{
83a57153 9252 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9253 struct intel_encoder *intel_encoder =
9254 intel_attached_encoder(connector);
4ef69c7a 9255 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9256 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9258 struct drm_atomic_state *state;
944b0c76 9259 struct drm_connector_state *connector_state;
79e53945 9260
d2dff872 9261 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9262 connector->base.id, connector->name,
8e329a03 9263 encoder->base.id, encoder->name);
d2dff872 9264
8261b191 9265 if (old->load_detect_temp) {
83a57153 9266 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9267 if (!state)
9268 goto fail;
83a57153
ACO		 9269
9270 state->acquire_ctx = ctx;
9271
944b0c76
ACO		 9272 connector_state = drm_atomic_get_connector_state(state, connector);
9273 if (IS_ERR(connector_state))
9274 goto fail;
9275
fc303101
DV		 9276 to_intel_connector(connector)->new_encoder = NULL;
9277 intel_encoder->new_crtc = NULL;
412b61d8
VS		 9278 intel_crtc->new_enabled = false;
9279 intel_crtc->new_config = NULL;
944b0c76
ACO		 9280
9281 connector_state->best_encoder = NULL;
9282 connector_state->crtc = NULL;
9283
83a57153
ACO		 9284 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9285
9286 drm_atomic_state_free(state);
d2dff872 9287
36206361
DV		 9288 if (old->release_fb) {
9289 drm_framebuffer_unregister_private(old->release_fb);
9290 drm_framebuffer_unreference(old->release_fb);
9291 }
d2dff872 9292
0622a53c 9293 return;
79e53945
JB		 9294 }
9295
c751ce4f 9296 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9297 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9298 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9299
9300 return;
9301fail:
9302 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9303 drm_atomic_state_free(state);
79e53945
JB		 9304}
9305
da4a1efa 9306static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9307 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9308{
9309 struct drm_i915_private *dev_priv = dev->dev_private;
9310 u32 dpll = pipe_config->dpll_hw_state.dpll;
9311
9312 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9313 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9314 else if (HAS_PCH_SPLIT(dev))
9315 return 120000;
9316 else if (!IS_GEN2(dev))
9317 return 96000;
9318 else
9319 return 48000;
9320}
9321
79e53945 9322/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9323static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9324 struct intel_crtc_state *pipe_config)
79e53945 9325{
f1f644dc 9326 struct drm_device *dev = crtc->base.dev;
79e53945 9327 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9328 int pipe = pipe_config->cpu_transcoder;
293623f7 9329 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9330 u32 fp;
9331 intel_clock_t clock;
da4a1efa 9332 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9333
9334 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9335 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9336 else
293623f7 9337 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9338
9339 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9340 if (IS_PINEVIEW(dev)) {
9341 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9342 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9343 } else {
9344 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9345 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9346 }
9347
a6c45cf0 9348 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9349 if (IS_PINEVIEW(dev))
9350 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9351 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9352 else
9353 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9354 DPLL_FPA01_P1_POST_DIV_SHIFT);
9355
9356 switch (dpll & DPLL_MODE_MASK) {
9357 case DPLLB_MODE_DAC_SERIAL:
9358 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9359 5 : 10;
9360 break;
9361 case DPLLB_MODE_LVDS:
9362 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9363 7 : 14;
9364 break;
9365 default:
28c97730 9366 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9367 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9368 return;
79e53945
JB		 9369 }
9370
ac58c3f0 9371 if (IS_PINEVIEW(dev))
da4a1efa 9372 pineview_clock(refclk, &clock);
ac58c3f0 9373 else
da4a1efa 9374 i9xx_clock(refclk, &clock);
79e53945 9375 } else {
0fb58223 9376 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 9377 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 9378
9379 if (is_lvds) {
9380 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9381 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 9382
9383 if (lvds & LVDS_CLKB_POWER_UP)
9384 clock.p2 = 7;
9385 else
9386 clock.p2 = 14;
79e53945
JB		 9387 } else {
9388 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9389 clock.p1 = 2;
9390 else {
9391 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9392 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9393 }
9394 if (dpll & PLL_P2_DIVIDE_BY_4)
9395 clock.p2 = 4;
9396 else
9397 clock.p2 = 2;
79e53945 9398 }
da4a1efa
VS		 9399
9400 i9xx_clock(refclk, &clock);
79e53945
JB		 9401 }
9402
18442d08
VS		 9403 /*
9404 * This value includes pixel_multiplier. We will use
241bfc38 9405 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9406 * encoder's get_config() function.
9407 */
9408 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9409}
9410
6878da05
VS		 9411int intel_dotclock_calculate(int link_freq,
9412 const struct intel_link_m_n *m_n)
f1f644dc 9413{
f1f644dc
JB		 9414 /*
9415 * The calculation for the data clock is:
1041a02f 9416 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9417 * But we want to avoid losing precison if possible, so:
1041a02f 9418 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9419 *
9420 * and the link clock is simpler:
1041a02f 9421 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9422 */
9423
6878da05
VS		 9424 if (!m_n->link_n)
9425 return 0;
f1f644dc 9426
6878da05
VS		 9427 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9428}
f1f644dc 9429
18442d08 9430static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9431 struct intel_crtc_state *pipe_config)
6878da05
VS		 9432{
9433 struct drm_device *dev = crtc->base.dev;
79e53945 9434
18442d08
VS		 9435 /* read out port_clock from the DPLL */
9436 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9437
f1f644dc 9438 /*
18442d08 9439 * This value does not include pixel_multiplier.
241bfc38 9440 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 9441 * agree once we know their relationship in the encoder's
9442 * get_config() function.
79e53945 9443 */
2d112de7 9444 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 9445 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9446 &pipe_config->fdi_m_n);
79e53945
JB		 9447}
9448
9449/** Returns the currently programmed mode of the given pipe. */
9450struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9451 struct drm_crtc *crtc)
9452{
548f245b 9453 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 9454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9455 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9456 struct drm_display_mode *mode;
5cec258b 9457 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 9458 int htot = I915_READ(HTOTAL(cpu_transcoder));
9459 int hsync = I915_READ(HSYNC(cpu_transcoder));
9460 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9461 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 9462 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 9463
9464 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9465 if (!mode)
9466 return NULL;
9467
f1f644dc
JB		 9468 /*
9469 * Construct a pipe_config sufficient for getting the clock info
9470 * back out of crtc_clock_get.
9471 *
9472 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9473 * to use a real value here instead.
9474 */
293623f7 9475 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 9476 pipe_config.pixel_multiplier = 1;
293623f7
VS		 9477 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9478 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9479 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 9480 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9481
773ae034 9482 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 9483 mode->hdisplay = (htot & 0xffff) + 1;
9484 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9485 mode->hsync_start = (hsync & 0xffff) + 1;
9486 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9487 mode->vdisplay = (vtot & 0xffff) + 1;
9488 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9489 mode->vsync_start = (vsync & 0xffff) + 1;
9490 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9491
9492 drm_mode_set_name(mode);
79e53945
JB		 9493
9494 return mode;
9495}
9496
652c393a
JB		 9497static void intel_decrease_pllclock(struct drm_crtc *crtc)
9498{
9499 struct drm_device *dev = crtc->dev;
fbee40df 9500 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 9502
baff296c 9503 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 9504 return;
9505
9506 if (!dev_priv->lvds_downclock_avail)
9507 return;
9508
9509 /*
9510 * Since this is called by a timer, we should never get here in
9511 * the manual case.
9512 */
9513 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 9514 int pipe = intel_crtc->pipe;
9515 int dpll_reg = DPLL(pipe);
9516 int dpll;
f6e5b160 9517
44d98a61 9518 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 9519
8ac5a6d5 9520 assert_panel_unlocked(dev_priv, pipe);
652c393a 9521
dc257cf1 9522 dpll = I915_READ(dpll_reg);
652c393a
JB		 9523 dpll |= DISPLAY_RATE_SELECT_FPA1;
9524 I915_WRITE(dpll_reg, dpll);
9d0498a2 9525 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 9526 dpll = I915_READ(dpll_reg);
9527 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 9528 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 9529 }
9530
9531}
9532
f047e395
CW		 9533void intel_mark_busy(struct drm_device *dev)
9534{
c67a470b
PZ		 9535 struct drm_i915_private *dev_priv = dev->dev_private;
9536
f62a0076
CW		 9537 if (dev_priv->mm.busy)
9538 return;
9539
43694d69 9540 intel_runtime_pm_get(dev_priv);
c67a470b 9541 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 9542 if (INTEL_INFO(dev)->gen >= 6)
9543 gen6_rps_busy(dev_priv);
f62a0076 9544 dev_priv->mm.busy = true;
f047e395
CW		 9545}
9546
9547void intel_mark_idle(struct drm_device *dev)
652c393a 9548{
c67a470b 9549 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9550 struct drm_crtc *crtc;
652c393a 9551
f62a0076
CW		 9552 if (!dev_priv->mm.busy)
9553 return;
9554
9555 dev_priv->mm.busy = false;
9556
70e1e0ec 9557 for_each_crtc(dev, crtc) {
f4510a27 9558 if (!crtc->primary->fb)
652c393a
JB		 9559 continue;
9560
725a5b54 9561 intel_decrease_pllclock(crtc);
652c393a 9562 }
b29c19b6 9563
3d13ef2e 9564 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 9565 gen6_rps_idle(dev->dev_private);
bb4cdd53 9566
43694d69 9567 intel_runtime_pm_put(dev_priv);
652c393a
JB		 9568}
9569
f5de6e07
ACO		 9570static void intel_crtc_set_state(struct intel_crtc *crtc,
9571 struct intel_crtc_state *crtc_state)
9572{
9573 kfree(crtc->config);
9574 crtc->config = crtc_state;
16f3f658 9575 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 9576}
9577
79e53945
JB		 9578static void intel_crtc_destroy(struct drm_crtc *crtc)
9579{
9580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 9581 struct drm_device *dev = crtc->dev;
9582 struct intel_unpin_work *work;
67e77c5a 9583
5e2d7afc 9584 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 9585 work = intel_crtc->unpin_work;
9586 intel_crtc->unpin_work = NULL;
5e2d7afc 9587 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 9588
9589 if (work) {
9590 cancel_work_sync(&work->work);
9591 kfree(work);
9592 }
79e53945 9593
f5de6e07 9594 intel_crtc_set_state(intel_crtc, NULL);
79e53945 9595 drm_crtc_cleanup(crtc);
67e77c5a 9596
79e53945
JB		 9597 kfree(intel_crtc);
9598}
9599
6b95a207
KH		 9600static void intel_unpin_work_fn(struct work_struct *__work)
9601{
9602 struct intel_unpin_work *work =
9603 container_of(__work, struct intel_unpin_work, work);
b4a98e57 9604 struct drm_device *dev = work->crtc->dev;
f99d7069 9605 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 9606
b4a98e57 9607 mutex_lock(&dev->struct_mutex);
82bc3b2d 9608 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 9609 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 9610
7ff0ebcc 9611 intel_fbc_update(dev);
f06cc1b9
JH		 9612
9613 if (work->flip_queued_req)
146d84f0 9614 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 9615 mutex_unlock(&dev->struct_mutex);
9616
f99d7069 9617 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 9618 drm_framebuffer_unreference(work->old_fb);
f99d7069 9619
b4a98e57
CW		 9620 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9621 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9622
6b95a207
KH		 9623 kfree(work);
9624}
9625
1afe3e9d 9626static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 9627 struct drm_crtc *crtc)
6b95a207 9628{
6b95a207
KH		 9629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9630 struct intel_unpin_work *work;
6b95a207
KH		 9631 unsigned long flags;
9632
9633 /* Ignore early vblank irqs */
9634 if (intel_crtc == NULL)
9635 return;
9636
f326038a
DV		 9637 /*
9638 * This is called both by irq handlers and the reset code (to complete
9639 * lost pageflips) so needs the full irqsave spinlocks.
9640 */
6b95a207
KH		 9641 spin_lock_irqsave(&dev->event_lock, flags);
9642 work = intel_crtc->unpin_work;
e7d841ca
CW		 9643
9644 /* Ensure we don't miss a work->pending update ... */
9645 smp_rmb();
9646
9647 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 9648 spin_unlock_irqrestore(&dev->event_lock, flags);
9649 return;
9650 }
9651
d6bbafa1 9652 page_flip_completed(intel_crtc);
0af7e4df 9653
6b95a207 9654 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 9655}
9656
1afe3e9d
JB		 9657void intel_finish_page_flip(struct drm_device *dev, int pipe)
9658{
fbee40df 9659 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9660 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9661
49b14a5c 9662 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9663}
9664
9665void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9666{
fbee40df 9667 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9668 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9669
49b14a5c 9670 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9671}
9672
75f7f3ec
VS		 9673/* Is 'a' after or equal to 'b'? */
9674static bool g4x_flip_count_after_eq(u32 a, u32 b)
9675{
9676 return !((a - b) & 0x80000000);
9677}
9678
9679static bool page_flip_finished(struct intel_crtc *crtc)
9680{
9681 struct drm_device *dev = crtc->base.dev;
9682 struct drm_i915_private *dev_priv = dev->dev_private;
9683
bdfa7542
VS		 9684 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9685 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9686 return true;
9687
75f7f3ec
VS		 9688 /*
9689 * The relevant registers doen't exist on pre-ctg.
9690 * As the flip done interrupt doesn't trigger for mmio
9691 * flips on gmch platforms, a flip count check isn't
9692 * really needed there. But since ctg has the registers,
9693 * include it in the check anyway.
9694 */
9695 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9696 return true;
9697
9698 /*
9699 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9700 * used the same base address. In that case the mmio flip might
9701 * have completed, but the CS hasn't even executed the flip yet.
9702 *
9703 * A flip count check isn't enough as the CS might have updated
9704 * the base address just after start of vblank, but before we
9705 * managed to process the interrupt. This means we'd complete the
9706 * CS flip too soon.
9707 *
9708 * Combining both checks should get us a good enough result. It may
9709 * still happen that the CS flip has been executed, but has not
9710 * yet actually completed. But in case the base address is the same
9711 * anyway, we don't really care.
9712 */
9713 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9714 crtc->unpin_work->gtt_offset &&
9715 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9716 crtc->unpin_work->flip_count);
9717}
9718
6b95a207
KH		 9719void intel_prepare_page_flip(struct drm_device *dev, int plane)
9720{
fbee40df 9721 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 9722 struct intel_crtc *intel_crtc =
9723 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9724 unsigned long flags;
9725
f326038a
DV		 9726
9727 /*
9728 * This is called both by irq handlers and the reset code (to complete
9729 * lost pageflips) so needs the full irqsave spinlocks.
9730 *
9731 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 9732 * generate a page-flip completion irq, i.e. every modeset
9733 * is also accompanied by a spurious intel_prepare_page_flip().
9734 */
6b95a207 9735 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 9736 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 9737 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 9738 spin_unlock_irqrestore(&dev->event_lock, flags);
9739}
9740
eba905b2 9741static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 9742{
9743 /* Ensure that the work item is consistent when activating it ... */
9744 smp_wmb();
9745 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9746 /* and that it is marked active as soon as the irq could fire. */
9747 smp_wmb();
9748}
9749
8c9f3aaf
JB		 9750static int intel_gen2_queue_flip(struct drm_device *dev,
9751 struct drm_crtc *crtc,
9752 struct drm_framebuffer *fb,
ed8d1975 9753 struct drm_i915_gem_object *obj,
a4872ba6 9754 struct intel_engine_cs *ring,
ed8d1975 9755 uint32_t flags)
8c9f3aaf 9756{
8c9f3aaf 9757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9758 u32 flip_mask;
9759 int ret;
9760
6d90c952 9761 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9762 if (ret)
4fa62c89 9763 return ret;
8c9f3aaf
JB		 9764
9765 /* Can't queue multiple flips, so wait for the previous
9766 * one to finish before executing the next.
9767 */
9768 if (intel_crtc->plane)
9769 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9770 else
9771 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9772 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9773 intel_ring_emit(ring, MI_NOOP);
9774 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9775 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9776 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9777 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 9778 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 9779
9780 intel_mark_page_flip_active(intel_crtc);
09246732 9781 __intel_ring_advance(ring);
83d4092b 9782 return 0;
8c9f3aaf
JB		 9783}
9784
9785static int intel_gen3_queue_flip(struct drm_device *dev,
9786 struct drm_crtc *crtc,
9787 struct drm_framebuffer *fb,
ed8d1975 9788 struct drm_i915_gem_object *obj,
a4872ba6 9789 struct intel_engine_cs *ring,
ed8d1975 9790 uint32_t flags)
8c9f3aaf 9791{
8c9f3aaf 9792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9793 u32 flip_mask;
9794 int ret;
9795
6d90c952 9796 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9797 if (ret)
4fa62c89 9798 return ret;
8c9f3aaf
JB		 9799
9800 if (intel_crtc->plane)
9801 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9802 else
9803 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9804 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9805 intel_ring_emit(ring, MI_NOOP);
9806 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9807 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9808 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9809 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 9810 intel_ring_emit(ring, MI_NOOP);
9811
e7d841ca 9812 intel_mark_page_flip_active(intel_crtc);
09246732 9813 __intel_ring_advance(ring);
83d4092b 9814 return 0;
8c9f3aaf
JB		 9815}
9816
9817static int intel_gen4_queue_flip(struct drm_device *dev,
9818 struct drm_crtc *crtc,
9819 struct drm_framebuffer *fb,
ed8d1975 9820 struct drm_i915_gem_object *obj,
a4872ba6 9821 struct intel_engine_cs *ring,
ed8d1975 9822 uint32_t flags)
8c9f3aaf
JB		 9823{
9824 struct drm_i915_private *dev_priv = dev->dev_private;
9825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9826 uint32_t pf, pipesrc;
9827 int ret;
9828
6d90c952 9829 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9830 if (ret)
4fa62c89 9831 return ret;
8c9f3aaf
JB		 9832
9833 /* i965+ uses the linear or tiled offsets from the
9834 * Display Registers (which do not change across a page-flip)
9835 * so we need only reprogram the base address.
9836 */
6d90c952
DV		 9837 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9838 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9839 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9840 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 9841 obj->tiling_mode);
8c9f3aaf
JB		 9842
9843 /* XXX Enabling the panel-fitter across page-flip is so far
9844 * untested on non-native modes, so ignore it for now.
9845 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9846 */
9847 pf = 0;
9848 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9849 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9850
9851 intel_mark_page_flip_active(intel_crtc);
09246732 9852 __intel_ring_advance(ring);
83d4092b 9853 return 0;
8c9f3aaf
JB		 9854}
9855
9856static int intel_gen6_queue_flip(struct drm_device *dev,
9857 struct drm_crtc *crtc,
9858 struct drm_framebuffer *fb,
ed8d1975 9859 struct drm_i915_gem_object *obj,
a4872ba6 9860 struct intel_engine_cs *ring,
ed8d1975 9861 uint32_t flags)
8c9f3aaf
JB		 9862{
9863 struct drm_i915_private *dev_priv = dev->dev_private;
9864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9865 uint32_t pf, pipesrc;
9866 int ret;
9867
6d90c952 9868 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9869 if (ret)
4fa62c89 9870 return ret;
8c9f3aaf 9871
6d90c952
DV		 9872 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9873 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9874 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 9875 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 9876
dc257cf1
DV		 9877 /* Contrary to the suggestions in the documentation,
9878 * "Enable Panel Fitter" does not seem to be required when page
9879 * flipping with a non-native mode, and worse causes a normal
9880 * modeset to fail.
9881 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9882 */
9883 pf = 0;
8c9f3aaf 9884 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9885 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9886
9887 intel_mark_page_flip_active(intel_crtc);
09246732 9888 __intel_ring_advance(ring);
83d4092b 9889 return 0;
8c9f3aaf
JB		 9890}
9891
7c9017e5
JB		 9892static int intel_gen7_queue_flip(struct drm_device *dev,
9893 struct drm_crtc *crtc,
9894 struct drm_framebuffer *fb,
ed8d1975 9895 struct drm_i915_gem_object *obj,
a4872ba6 9896 struct intel_engine_cs *ring,
ed8d1975 9897 uint32_t flags)
7c9017e5 9898{
7c9017e5 9899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 9900 uint32_t plane_bit = 0;
ffe74d75
CW		 9901 int len, ret;
9902
eba905b2 9903 switch (intel_crtc->plane) {
cb05d8de
DV		 9904 case PLANE_A:
9905 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9906 break;
9907 case PLANE_B:
9908 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9909 break;
9910 case PLANE_C:
9911 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9912 break;
9913 default:
9914 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 9915 return -ENODEV;
cb05d8de
DV		 9916 }
9917
ffe74d75 9918 len = 4;
f476828a 9919 if (ring->id == RCS) {
ffe74d75 9920 len += 6;
f476828a
DL		 9921 /*
9922 * On Gen 8, SRM is now taking an extra dword to accommodate
9923 * 48bits addresses, and we need a NOOP for the batch size to
9924 * stay even.
9925 */
9926 if (IS_GEN8(dev))
9927 len += 2;
9928 }
ffe74d75 9929
f66fab8e
VS		 9930 /*
9931 * BSpec MI_DISPLAY_FLIP for IVB:
9932 * "The full packet must be contained within the same cache line."
9933 *
9934 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9935 * cacheline, if we ever start emitting more commands before
9936 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9937 * then do the cacheline alignment, and finally emit the
9938 * MI_DISPLAY_FLIP.
9939 */
9940 ret = intel_ring_cacheline_align(ring);
9941 if (ret)
4fa62c89 9942 return ret;
f66fab8e 9943
ffe74d75 9944 ret = intel_ring_begin(ring, len);
7c9017e5 9945 if (ret)
4fa62c89 9946 return ret;
7c9017e5 9947
ffe74d75
CW		 9948 /* Unmask the flip-done completion message. Note that the bspec says that
9949 * we should do this for both the BCS and RCS, and that we must not unmask
9950 * more than one flip event at any time (or ensure that one flip message
9951 * can be sent by waiting for flip-done prior to queueing new flips).
9952 * Experimentation says that BCS works despite DERRMR masking all
9953 * flip-done completion events and that unmasking all planes at once
9954 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9955 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9956 */
9957 if (ring->id == RCS) {
9958 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9959 intel_ring_emit(ring, DERRMR);
9960 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9961 DERRMR_PIPEB_PRI_FLIP_DONE |
9962 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 9963 if (IS_GEN8(dev))
9964 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9965 MI_SRM_LRM_GLOBAL_GTT);
9966 else
9967 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9968 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 9969 intel_ring_emit(ring, DERRMR);
9970 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 9971 if (IS_GEN8(dev)) {
9972 intel_ring_emit(ring, 0);
9973 intel_ring_emit(ring, MI_NOOP);
9974 }
ffe74d75
CW		 9975 }
9976
cb05d8de 9977 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 9978 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 9979 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 9980 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 9981
9982 intel_mark_page_flip_active(intel_crtc);
09246732 9983 __intel_ring_advance(ring);
83d4092b 9984 return 0;
7c9017e5
JB		 9985}
9986
84c33a64
SG		 9987static bool use_mmio_flip(struct intel_engine_cs *ring,
9988 struct drm_i915_gem_object *obj)
9989{
9990 /*
9991 * This is not being used for older platforms, because
9992 * non-availability of flip done interrupt forces us to use
9993 * CS flips. Older platforms derive flip done using some clever
9994 * tricks involving the flip_pending status bits and vblank irqs.
9995 * So using MMIO flips there would disrupt this mechanism.
9996 */
9997
8e09bf83
CW		 9998 if (ring == NULL)
9999 return true;
10000
84c33a64
SG		 10001 if (INTEL_INFO(ring->dev)->gen < 5)
10002 return false;
10003
10004 if (i915.use_mmio_flip < 0)
10005 return false;
10006 else if (i915.use_mmio_flip > 0)
10007 return true;
14bf993e
OM		 10008 else if (i915.enable_execlists)
10009 return true;
84c33a64 10010 else
41c52415 10011 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10012}
10013
ff944564
DL		 10014static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10015{
10016 struct drm_device *dev = intel_crtc->base.dev;
10017 struct drm_i915_private *dev_priv = dev->dev_private;
10018 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10019 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10020 struct drm_i915_gem_object *obj = intel_fb->obj;
10021 const enum pipe pipe = intel_crtc->pipe;
10022 u32 ctl, stride;
10023
10024 ctl = I915_READ(PLANE_CTL(pipe, 0));
10025 ctl &= ~PLANE_CTL_TILED_MASK;
10026 if (obj->tiling_mode == I915_TILING_X)
10027 ctl |= PLANE_CTL_TILED_X;
10028
10029 /*
10030 * The stride is either expressed as a multiple of 64 bytes chunks for
10031 * linear buffers or in number of tiles for tiled buffers.
10032 */
10033 stride = fb->pitches[0] >> 6;
10034 if (obj->tiling_mode == I915_TILING_X)
10035 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
10036
10037 /*
10038 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10039 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10040 */
10041 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10042 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10043
10044 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10045 POSTING_READ(PLANE_SURF(pipe, 0));
10046}
10047
10048static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10049{
10050 struct drm_device *dev = intel_crtc->base.dev;
10051 struct drm_i915_private *dev_priv = dev->dev_private;
10052 struct intel_framebuffer *intel_fb =
10053 to_intel_framebuffer(intel_crtc->base.primary->fb);
10054 struct drm_i915_gem_object *obj = intel_fb->obj;
10055 u32 dspcntr;
10056 u32 reg;
10057
84c33a64
SG		 10058 reg = DSPCNTR(intel_crtc->plane);
10059 dspcntr = I915_READ(reg);
10060
c5d97472
DL		 10061 if (obj->tiling_mode != I915_TILING_NONE)
10062 dspcntr |= DISPPLANE_TILED;
10063 else
10064 dspcntr &= ~DISPPLANE_TILED;
10065
84c33a64
SG		 10066 I915_WRITE(reg, dspcntr);
10067
10068 I915_WRITE(DSPSURF(intel_crtc->plane),
10069 intel_crtc->unpin_work->gtt_offset);
10070 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10071
ff944564
DL		 10072}
10073
10074/*
10075 * XXX: This is the temporary way to update the plane registers until we get
10076 * around to using the usual plane update functions for MMIO flips
10077 */
10078static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10079{
10080 struct drm_device *dev = intel_crtc->base.dev;
10081 bool atomic_update;
10082 u32 start_vbl_count;
10083
10084 intel_mark_page_flip_active(intel_crtc);
10085
10086 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10087
10088 if (INTEL_INFO(dev)->gen >= 9)
10089 skl_do_mmio_flip(intel_crtc);
10090 else
10091 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10092 ilk_do_mmio_flip(intel_crtc);
10093
9362c7c5
ACO		 10094 if (atomic_update)
10095 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10096}
10097
9362c7c5 10098static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10099{
cc8c4cc2 10100 struct intel_crtc *crtc =
9362c7c5 10101 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 10102 struct intel_mmio_flip *mmio_flip;
84c33a64 10103
cc8c4cc2
JH		 10104 mmio_flip = &crtc->mmio_flip;
10105 if (mmio_flip->req)
9c654818
JH		 10106 WARN_ON(__i915_wait_request(mmio_flip->req,
10107 crtc->reset_counter,
10108 false, NULL, NULL) != 0);
84c33a64 10109
cc8c4cc2
JH		 10110 intel_do_mmio_flip(crtc);
10111 if (mmio_flip->req) {
10112 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 10113 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 10114 mutex_unlock(&crtc->base.dev->struct_mutex);
10115 }
84c33a64
SG		 10116}
10117
10118static int intel_queue_mmio_flip(struct drm_device *dev,
10119 struct drm_crtc *crtc,
10120 struct drm_framebuffer *fb,
10121 struct drm_i915_gem_object *obj,
10122 struct intel_engine_cs *ring,
10123 uint32_t flags)
10124{
84c33a64 10125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 10126
cc8c4cc2
JH		 10127 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10128 obj->last_write_req);
536f5b5e
ACO		 10129
10130 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10131
84c33a64
SG		 10132 return 0;
10133}
10134
8c9f3aaf
JB		 10135static int intel_default_queue_flip(struct drm_device *dev,
10136 struct drm_crtc *crtc,
10137 struct drm_framebuffer *fb,
ed8d1975 10138 struct drm_i915_gem_object *obj,
a4872ba6 10139 struct intel_engine_cs *ring,
ed8d1975 10140 uint32_t flags)
8c9f3aaf
JB		 10141{
10142 return -ENODEV;
10143}
10144
d6bbafa1
CW		 10145static bool __intel_pageflip_stall_check(struct drm_device *dev,
10146 struct drm_crtc *crtc)
10147{
10148 struct drm_i915_private *dev_priv = dev->dev_private;
10149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10150 struct intel_unpin_work *work = intel_crtc->unpin_work;
10151 u32 addr;
10152
10153 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10154 return true;
10155
10156 if (!work->enable_stall_check)
10157 return false;
10158
10159 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10160 if (work->flip_queued_req &&
10161 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10162 return false;
10163
1e3feefd 10164 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10165 }
10166
1e3feefd 10167 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10168 return false;
10169
10170 /* Potential stall - if we see that the flip has happened,
10171 * assume a missed interrupt. */
10172 if (INTEL_INFO(dev)->gen >= 4)
10173 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10174 else
10175 addr = I915_READ(DSPADDR(intel_crtc->plane));
10176
10177 /* There is a potential issue here with a false positive after a flip
10178 * to the same address. We could address this by checking for a
10179 * non-incrementing frame counter.
10180 */
10181 return addr == work->gtt_offset;
10182}
10183
10184void intel_check_page_flip(struct drm_device *dev, int pipe)
10185{
10186 struct drm_i915_private *dev_priv = dev->dev_private;
10187 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f326038a 10189
6c51d46f 10190 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10191
10192 if (crtc == NULL)
10193 return;
10194
f326038a 10195 spin_lock(&dev->event_lock);
d6bbafa1
CW		 10196 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
10197 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
1e3feefd
DV		 10198 intel_crtc->unpin_work->flip_queued_vblank,
10199 drm_vblank_count(dev, pipe));
d6bbafa1
CW		 10200 page_flip_completed(intel_crtc);
10201 }
f326038a 10202 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10203}
10204
6b95a207
KH		 10205static int intel_crtc_page_flip(struct drm_crtc *crtc,
10206 struct drm_framebuffer *fb,
ed8d1975
KP		 10207 struct drm_pending_vblank_event *event,
10208 uint32_t page_flip_flags)
6b95a207
KH		 10209{
10210 struct drm_device *dev = crtc->dev;
10211 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10212 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10213 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10215 struct drm_plane *primary = crtc->primary;
a071fa00 10216 enum pipe pipe = intel_crtc->pipe;
6b95a207 10217 struct intel_unpin_work *work;
a4872ba6 10218 struct intel_engine_cs *ring;
52e68630 10219 int ret;
6b95a207 10220
2ff8fde1
MR		 10221 /*
10222 * drm_mode_page_flip_ioctl() should already catch this, but double
10223 * check to be safe. In the future we may enable pageflipping from
10224 * a disabled primary plane.
10225 */
10226 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10227 return -EBUSY;
10228
e6a595d2 10229 /* Can't change pixel format via MI display flips. */
f4510a27 10230 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10231 return -EINVAL;
10232
10233 /*
10234 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10235 * Note that pitch changes could also affect these register.
10236 */
10237 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10238 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10239 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10240 return -EINVAL;
10241
f900db47
CW		 10242 if (i915_terminally_wedged(&dev_priv->gpu_error))
10243 goto out_hang;
10244
b14c5679 10245 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10246 if (work == NULL)
10247 return -ENOMEM;
10248
6b95a207 10249 work->event = event;
b4a98e57 10250 work->crtc = crtc;
ab8d6675 10251 work->old_fb = old_fb;
6b95a207
KH		 10252 INIT_WORK(&work->work, intel_unpin_work_fn);
10253
87b6b101 10254 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10255 if (ret)
10256 goto free_work;
10257
6b95a207 10258 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10259 spin_lock_irq(&dev->event_lock);
6b95a207 10260 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10261 /* Before declaring the flip queue wedged, check if
10262 * the hardware completed the operation behind our backs.
10263 */
10264 if (__intel_pageflip_stall_check(dev, crtc)) {
10265 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10266 page_flip_completed(intel_crtc);
10267 } else {
10268 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10269 spin_unlock_irq(&dev->event_lock);
468f0b44 10270
d6bbafa1
CW		 10271 drm_crtc_vblank_put(crtc);
10272 kfree(work);
10273 return -EBUSY;
10274 }
6b95a207
KH		 10275 }
10276 intel_crtc->unpin_work = work;
5e2d7afc 10277 spin_unlock_irq(&dev->event_lock);
6b95a207 10278
b4a98e57
CW		 10279 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10280 flush_workqueue(dev_priv->wq);
10281
75dfca80 10282 /* Reference the objects for the scheduled work. */
ab8d6675 10283 drm_framebuffer_reference(work->old_fb);
05394f39 10284 drm_gem_object_reference(&obj->base);
6b95a207 10285
f4510a27 10286 crtc->primary->fb = fb;
afd65eb4 10287 update_state_fb(crtc->primary);
1ed1f968 10288
e1f99ce6 10289 work->pending_flip_obj = obj;
e1f99ce6 10290
89ed88ba
CW		 10291 ret = i915_mutex_lock_interruptible(dev);
10292 if (ret)
10293 goto cleanup;
10294
b4a98e57 10295 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10296 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10297
75f7f3ec 10298 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10299 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10300
4fa62c89
VS		 10301 if (IS_VALLEYVIEW(dev)) {
10302 ring = &dev_priv->ring[BCS];
ab8d6675 10303 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10304 /* vlv: DISPLAY_FLIP fails to change tiling */
10305 ring = NULL;
48bf5b2d 10306 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10307 ring = &dev_priv->ring[BCS];
4fa62c89 10308 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10309 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10310 if (ring == NULL || ring->id != RCS)
10311 ring = &dev_priv->ring[BCS];
10312 } else {
10313 ring = &dev_priv->ring[RCS];
10314 }
10315
82bc3b2d
TU		 10316 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10317 crtc->primary->state, ring);
8c9f3aaf
JB		 10318 if (ret)
10319 goto cleanup_pending;
6b95a207 10320
121920fa
TU		 10321 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10322 + intel_crtc->dspaddr_offset;
4fa62c89 10323
d6bbafa1 10324 if (use_mmio_flip(ring, obj)) {
84c33a64
SG		 10325 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10326 page_flip_flags);
d6bbafa1
CW		 10327 if (ret)
10328 goto cleanup_unpin;
10329
f06cc1b9
JH		 10330 i915_gem_request_assign(&work->flip_queued_req,
10331 obj->last_write_req);
d6bbafa1 10332 } else {
84c33a64 10333 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10334 page_flip_flags);
10335 if (ret)
10336 goto cleanup_unpin;
10337
f06cc1b9
JH		 10338 i915_gem_request_assign(&work->flip_queued_req,
10339 intel_ring_get_request(ring));
d6bbafa1
CW		 10340 }
10341
1e3feefd 10342 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10343 work->enable_stall_check = true;
4fa62c89 10344
ab8d6675 10345 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10346 INTEL_FRONTBUFFER_PRIMARY(pipe));
10347
7ff0ebcc 10348 intel_fbc_disable(dev);
f99d7069 10349 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 10350 mutex_unlock(&dev->struct_mutex);
10351
e5510fac
JB		 10352 trace_i915_flip_request(intel_crtc->plane, obj);
10353
6b95a207 10354 return 0;
96b099fd 10355
4fa62c89 10356cleanup_unpin:
82bc3b2d 10357 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 10358cleanup_pending:
b4a98e57 10359 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 10360 mutex_unlock(&dev->struct_mutex);
10361cleanup:
f4510a27 10362 crtc->primary->fb = old_fb;
afd65eb4 10363 update_state_fb(crtc->primary);
89ed88ba
CW		 10364
10365 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 10366 drm_framebuffer_unreference(work->old_fb);
96b099fd 10367
5e2d7afc 10368 spin_lock_irq(&dev->event_lock);
96b099fd 10369 intel_crtc->unpin_work = NULL;
5e2d7afc 10370 spin_unlock_irq(&dev->event_lock);
96b099fd 10371
87b6b101 10372 drm_crtc_vblank_put(crtc);
7317c75e 10373free_work:
96b099fd
CW		 10374 kfree(work);
10375
f900db47
CW		 10376 if (ret == -EIO) {
10377out_hang:
53a366b9 10378 ret = intel_plane_restore(primary);
f0d3dad3 10379 if (ret == 0 && event) {
5e2d7afc 10380 spin_lock_irq(&dev->event_lock);
a071fa00 10381 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 10382 spin_unlock_irq(&dev->event_lock);
f0d3dad3 10383 }
f900db47 10384 }
96b099fd 10385 return ret;
6b95a207
KH		 10386}
10387
f6e5b160 10388static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 10389 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10390 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10391 .atomic_begin = intel_begin_crtc_commit,
10392 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10393};
10394
9a935856
DV		 10395/**
10396 * intel_modeset_update_staged_output_state
10397 *
10398 * Updates the staged output configuration state, e.g. after we've read out the
10399 * current hw state.
10400 */
10401static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 10402{
7668851f 10403 struct intel_crtc *crtc;
9a935856
DV		 10404 struct intel_encoder *encoder;
10405 struct intel_connector *connector;
f6e5b160 10406
3a3371ff 10407 for_each_intel_connector(dev, connector) {
9a935856
DV		 10408 connector->new_encoder =
10409 to_intel_encoder(connector->base.encoder);
10410 }
f6e5b160 10411
b2784e15 10412 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10413 encoder->new_crtc =
10414 to_intel_crtc(encoder->base.crtc);
10415 }
7668851f 10416
d3fcc808 10417 for_each_intel_crtc(dev, crtc) {
83d65738 10418 crtc->new_enabled = crtc->base.state->enable;
7bd0a8e7
VS		 10419
10420 if (crtc->new_enabled)
6e3c9717 10421 crtc->new_config = crtc->config;
7bd0a8e7
VS		 10422 else
10423 crtc->new_config = NULL;
7668851f 10424 }
f6e5b160
CW		 10425}
10426
d29b2f9d
ACO		 10427/* Transitional helper to copy current connector/encoder state to
10428 * connector->state. This is needed so that code that is partially
10429 * converted to atomic does the right thing.
10430 */
10431static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
10432{
10433 struct intel_connector *connector;
10434
10435 for_each_intel_connector(dev, connector) {
10436 if (connector->base.encoder) {
10437 connector->base.state->best_encoder =
10438 connector->base.encoder;
10439 connector->base.state->crtc =
10440 connector->base.encoder->crtc;
10441 } else {
10442 connector->base.state->best_encoder = NULL;
10443 connector->base.state->crtc = NULL;
10444 }
10445 }
10446}
10447
9a935856
DV		 10448/**
10449 * intel_modeset_commit_output_state
10450 *
10451 * This function copies the stage display pipe configuration to the real one.
10452 */
10453static void intel_modeset_commit_output_state(struct drm_device *dev)
10454{
7668851f 10455 struct intel_crtc *crtc;
9a935856
DV		 10456 struct intel_encoder *encoder;
10457 struct intel_connector *connector;
f6e5b160 10458
3a3371ff 10459 for_each_intel_connector(dev, connector) {
9a935856
DV		 10460 connector->base.encoder = &connector->new_encoder->base;
10461 }
f6e5b160 10462
b2784e15 10463 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10464 encoder->base.crtc = &encoder->new_crtc->base;
10465 }
7668851f 10466
d3fcc808 10467 for_each_intel_crtc(dev, crtc) {
83d65738 10468 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 10469 crtc->base.enabled = crtc->new_enabled;
10470 }
d29b2f9d
ACO		 10471
10472 intel_modeset_update_connector_atomic_state(dev);
9a935856
DV		 10473}
10474
050f7aeb 10475static void
eba905b2 10476connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 10477 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 10478{
10479 int bpp = pipe_config->pipe_bpp;
10480
10481 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10482 connector->base.base.id,
c23cc417 10483 connector->base.name);
050f7aeb
DV		 10484
10485 /* Don't use an invalid EDID bpc value */
10486 if (connector->base.display_info.bpc &&
10487 connector->base.display_info.bpc * 3 < bpp) {
10488 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10489 bpp, connector->base.display_info.bpc*3);
10490 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10491 }
10492
10493 /* Clamp bpp to 8 on screens without EDID 1.4 */
10494 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10495 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10496 bpp);
10497 pipe_config->pipe_bpp = 24;
10498 }
10499}
10500
4e53c2e0 10501static int
050f7aeb
DV		 10502compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10503 struct drm_framebuffer *fb,
5cec258b 10504 struct intel_crtc_state *pipe_config)
4e53c2e0 10505{
050f7aeb 10506 struct drm_device *dev = crtc->base.dev;
1486017f 10507 struct drm_atomic_state *state;
050f7aeb 10508 struct intel_connector *connector;
1486017f 10509 int bpp, i;
4e53c2e0 10510
d42264b1
DV		 10511 switch (fb->pixel_format) {
10512 case DRM_FORMAT_C8:
4e53c2e0
DV		 10513 bpp = 8*3; /* since we go through a colormap */
10514 break;
d42264b1
DV		 10515 case DRM_FORMAT_XRGB1555:
10516 case DRM_FORMAT_ARGB1555:
10517 /* checked in intel_framebuffer_init already */
10518 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10519 return -EINVAL;
10520 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 10521 bpp = 6*3; /* min is 18bpp */
10522 break;
d42264b1
DV		 10523 case DRM_FORMAT_XBGR8888:
10524 case DRM_FORMAT_ABGR8888:
10525 /* checked in intel_framebuffer_init already */
10526 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10527 return -EINVAL;
10528 case DRM_FORMAT_XRGB8888:
10529 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 10530 bpp = 8*3;
10531 break;
d42264b1
DV		 10532 case DRM_FORMAT_XRGB2101010:
10533 case DRM_FORMAT_ARGB2101010:
10534 case DRM_FORMAT_XBGR2101010:
10535 case DRM_FORMAT_ABGR2101010:
10536 /* checked in intel_framebuffer_init already */
10537 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 10538 return -EINVAL;
4e53c2e0
DV		 10539 bpp = 10*3;
10540 break;
baba133a 10541 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 10542 default:
10543 DRM_DEBUG_KMS("unsupported depth\n");
10544 return -EINVAL;
10545 }
10546
4e53c2e0
DV		 10547 pipe_config->pipe_bpp = bpp;
10548
1486017f
ACO		 10549 state = pipe_config->base.state;
10550
4e53c2e0 10551 /* Clamp display bpp to EDID value */
1486017f
ACO		 10552 for (i = 0; i < state->num_connector; i++) {
10553 if (!state->connectors[i])
10554 continue;
10555
10556 connector = to_intel_connector(state->connectors[i]);
10557 if (state->connector_states[i]->crtc != &crtc->base)
4e53c2e0
DV		 10558 continue;
10559
050f7aeb 10560 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 10561 }
10562
10563 return bpp;
10564}
10565
644db711
DV		 10566static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10567{
10568 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10569 "type: 0x%x flags: 0x%x\n",
1342830c 10570 mode->crtc_clock,
644db711
DV		 10571 mode->crtc_hdisplay, mode->crtc_hsync_start,
10572 mode->crtc_hsync_end, mode->crtc_htotal,
10573 mode->crtc_vdisplay, mode->crtc_vsync_start,
10574 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10575}
10576
c0b03411 10577static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 10578 struct intel_crtc_state *pipe_config,
c0b03411
DV		 10579 const char *context)
10580{
10581 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10582 context, pipe_name(crtc->pipe));
10583
10584 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10585 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10586 pipe_config->pipe_bpp, pipe_config->dither);
10587 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10588 pipe_config->has_pch_encoder,
10589 pipe_config->fdi_lanes,
10590 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10591 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10592 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 10593 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10594 pipe_config->has_dp_encoder,
10595 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10596 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10597 pipe_config->dp_m_n.tu);
b95af8be
VK		 10598
10599 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10600 pipe_config->has_dp_encoder,
10601 pipe_config->dp_m2_n2.gmch_m,
10602 pipe_config->dp_m2_n2.gmch_n,
10603 pipe_config->dp_m2_n2.link_m,
10604 pipe_config->dp_m2_n2.link_n,
10605 pipe_config->dp_m2_n2.tu);
10606
55072d19
DV		 10607 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10608 pipe_config->has_audio,
10609 pipe_config->has_infoframe);
10610
c0b03411 10611 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 10612 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 10613 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 10614 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10615 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 10616 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 10617 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10618 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 10619 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10620 pipe_config->gmch_pfit.control,
10621 pipe_config->gmch_pfit.pgm_ratios,
10622 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 10623 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 10624 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 10625 pipe_config->pch_pfit.size,
10626 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 10627 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 10628 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 10629}
10630
bc079e8b
VS		 10631static bool encoders_cloneable(const struct intel_encoder *a,
10632 const struct intel_encoder *b)
accfc0c5 10633{
bc079e8b
VS		 10634 /* masks could be asymmetric, so check both ways */
10635 return a == b || (a->cloneable & (1 << b->type) &&
10636 b->cloneable & (1 << a->type));
10637}
10638
10639static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10640 struct intel_encoder *encoder)
10641{
10642 struct drm_device *dev = crtc->base.dev;
10643 struct intel_encoder *source_encoder;
10644
b2784e15 10645 for_each_intel_encoder(dev, source_encoder) {
bc079e8b
VS		 10646 if (source_encoder->new_crtc != crtc)
10647 continue;
10648
10649 if (!encoders_cloneable(encoder, source_encoder))
10650 return false;
10651 }
10652
10653 return true;
10654}
10655
10656static bool check_encoder_cloning(struct intel_crtc *crtc)
10657{
10658 struct drm_device *dev = crtc->base.dev;
accfc0c5
DV		 10659 struct intel_encoder *encoder;
10660
b2784e15 10661 for_each_intel_encoder(dev, encoder) {
bc079e8b 10662 if (encoder->new_crtc != crtc)
accfc0c5
DV		 10663 continue;
10664
bc079e8b
VS		 10665 if (!check_single_encoder_cloning(crtc, encoder))
10666 return false;
accfc0c5
DV		 10667 }
10668
bc079e8b 10669 return true;
accfc0c5
DV		 10670}
10671
00f0b378
VS		 10672static bool check_digital_port_conflicts(struct drm_device *dev)
10673{
10674 struct intel_connector *connector;
10675 unsigned int used_ports = 0;
10676
10677 /*
10678 * Walk the connector list instead of the encoder
10679 * list to detect the problem on ddi platforms
10680 * where there's just one encoder per digital port.
10681 */
3a3371ff 10682 for_each_intel_connector(dev, connector) {
00f0b378
VS		 10683 struct intel_encoder *encoder = connector->new_encoder;
10684
10685 if (!encoder)
10686 continue;
10687
10688 WARN_ON(!encoder->new_crtc);
10689
10690 switch (encoder->type) {
10691 unsigned int port_mask;
10692 case INTEL_OUTPUT_UNKNOWN:
10693 if (WARN_ON(!HAS_DDI(dev)))
10694 break;
10695 case INTEL_OUTPUT_DISPLAYPORT:
10696 case INTEL_OUTPUT_HDMI:
10697 case INTEL_OUTPUT_EDP:
10698 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10699
10700 /* the same port mustn't appear more than once */
10701 if (used_ports & port_mask)
10702 return false;
10703
10704 used_ports |= port_mask;
10705 default:
10706 break;
10707 }
10708 }
10709
10710 return true;
10711}
10712
83a57153
ACO		 10713static void
10714clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
10715{
10716 struct drm_crtc_state tmp_state;
10717
10718 /* Clear only the intel specific part of the crtc state */
10719 tmp_state = crtc_state->base;
10720 memset(crtc_state, 0, sizeof *crtc_state);
10721 crtc_state->base = tmp_state;
10722}
10723
5cec258b 10724static struct intel_crtc_state *
b8cecdf5 10725intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 10726 struct drm_framebuffer *fb,
83a57153
ACO		 10727 struct drm_display_mode *mode,
10728 struct drm_atomic_state *state)
ee7b9f93 10729{
7758a113 10730 struct drm_device *dev = crtc->dev;
7758a113 10731 struct intel_encoder *encoder;
0b901879
ACO		 10732 struct intel_connector *connector;
10733 struct drm_connector_state *connector_state;
5cec258b 10734 struct intel_crtc_state *pipe_config;
e29c22c0 10735 int plane_bpp, ret = -EINVAL;
0b901879 10736 int i;
e29c22c0 10737 bool retry = true;
ee7b9f93 10738
bc079e8b 10739 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
accfc0c5
DV		 10740 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10741 return ERR_PTR(-EINVAL);
10742 }
10743
00f0b378
VS		 10744 if (!check_digital_port_conflicts(dev)) {
10745 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10746 return ERR_PTR(-EINVAL);
10747 }
10748
83a57153
ACO		 10749 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
10750 if (IS_ERR(pipe_config))
10751 return pipe_config;
10752
10753 clear_intel_crtc_state(pipe_config);
7758a113 10754
07878248 10755 pipe_config->base.crtc = crtc;
2d112de7
ACO		 10756 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10757 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 10758
e143a21c
DV		 10759 pipe_config->cpu_transcoder =
10760 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 10761 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 10762
2960bc9c
ID		 10763 /*
10764 * Sanitize sync polarity flags based on requested ones. If neither
10765 * positive or negative polarity is requested, treat this as meaning
10766 * negative polarity.
10767 */
2d112de7 10768 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10769 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 10770 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 10771
2d112de7 10772 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10773 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 10774 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 10775
050f7aeb
DV		 10776 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10777 * plane pixel format and any sink constraints into account. Returns the
10778 * source plane bpp so that dithering can be selected on mismatches
10779 * after encoders and crtc also have had their say. */
10780 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10781 fb, pipe_config);
4e53c2e0
DV		 10782 if (plane_bpp < 0)
10783 goto fail;
10784
e41a56be
VS		 10785 /*
10786 * Determine the real pipe dimensions. Note that stereo modes can
10787 * increase the actual pipe size due to the frame doubling and
10788 * insertion of additional space for blanks between the frame. This
10789 * is stored in the crtc timings. We use the requested mode to do this
10790 * computation to clearly distinguish it from the adjusted mode, which
10791 * can be changed by the connectors in the below retry loop.
10792 */
2d112de7 10793 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 10794 &pipe_config->pipe_src_w,
10795 &pipe_config->pipe_src_h);
e41a56be 10796
e29c22c0 10797encoder_retry:
ef1b460d 10798 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 10799 pipe_config->port_clock = 0;
ef1b460d 10800 pipe_config->pixel_multiplier = 1;
ff9a6750 10801
135c81b8 10802 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 10803 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10804 CRTC_STEREO_DOUBLE);
135c81b8 10805
7758a113
DV		 10806 /* Pass our mode to the connectors and the CRTC to give them a chance to
10807 * adjust it according to limitations or connector properties, and also
10808 * a chance to reject the mode entirely.
47f1c6c9 10809 */
0b901879
ACO		 10810 for (i = 0; i < state->num_connector; i++) {
10811 connector = to_intel_connector(state->connectors[i]);
10812 if (!connector)
10813 continue;
47f1c6c9 10814
0b901879
ACO		 10815 connector_state = state->connector_states[i];
10816 if (connector_state->crtc != crtc)
7758a113 10817 continue;
7ae89233 10818
0b901879
ACO		 10819 encoder = to_intel_encoder(connector_state->best_encoder);
10820
efea6e8e
DV		 10821 if (!(encoder->compute_config(encoder, pipe_config))) {
10822 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 10823 goto fail;
10824 }
ee7b9f93 10825 }
47f1c6c9 10826
ff9a6750
DV		 10827 /* Set default port clock if not overwritten by the encoder. Needs to be
10828 * done afterwards in case the encoder adjusts the mode. */
10829 if (!pipe_config->port_clock)
2d112de7 10830 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 10831 * pipe_config->pixel_multiplier;
ff9a6750 10832
a43f6e0f 10833 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 10834 if (ret < 0) {
7758a113
DV		 10835 DRM_DEBUG_KMS("CRTC fixup failed\n");
10836 goto fail;
ee7b9f93 10837 }
e29c22c0
DV		 10838
10839 if (ret == RETRY) {
10840 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10841 ret = -EINVAL;
10842 goto fail;
10843 }
10844
10845 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10846 retry = false;
10847 goto encoder_retry;
10848 }
10849
4e53c2e0
DV		 10850 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10851 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10852 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10853
b8cecdf5 10854 return pipe_config;
7758a113 10855fail:
e29c22c0 10856 return ERR_PTR(ret);
ee7b9f93 10857}
47f1c6c9 10858
e2e1ed41
DV		 10859/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10860 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10861static void
10862intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10863 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 10864{
10865 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 10866 struct drm_device *dev = crtc->dev;
10867 struct intel_encoder *encoder;
10868 struct intel_connector *connector;
10869 struct drm_crtc *tmp_crtc;
79e53945 10870
e2e1ed41 10871 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 10872
e2e1ed41
DV		 10873 /* Check which crtcs have changed outputs connected to them, these need
10874 * to be part of the prepare_pipes mask. We don't (yet) support global
10875 * modeset across multiple crtcs, so modeset_pipes will only have one
10876 * bit set at most. */
3a3371ff 10877 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 10878 if (connector->base.encoder == &connector->new_encoder->base)
10879 continue;
79e53945 10880
e2e1ed41
DV		 10881 if (connector->base.encoder) {
10882 tmp_crtc = connector->base.encoder->crtc;
10883
10884 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10885 }
10886
10887 if (connector->new_encoder)
10888 *prepare_pipes |=
10889 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 10890 }
10891
b2784e15 10892 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 10893 if (encoder->base.crtc == &encoder->new_crtc->base)
10894 continue;
10895
10896 if (encoder->base.crtc) {
10897 tmp_crtc = encoder->base.crtc;
10898
10899 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10900 }
10901
10902 if (encoder->new_crtc)
10903 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 10904 }
10905
7668851f 10906 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 10907 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10908 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 10909 continue;
7e7d76c3 10910
7668851f 10911 if (!intel_crtc->new_enabled)
e2e1ed41 10912 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 10913 else
10914 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 10915 }
10916
e2e1ed41
DV		 10917
10918 /* set_mode is also used to update properties on life display pipes. */
10919 intel_crtc = to_intel_crtc(crtc);
7668851f 10920 if (intel_crtc->new_enabled)
e2e1ed41
DV		 10921 *prepare_pipes |= 1 << intel_crtc->pipe;
10922
b6c5164d
DV		 10923 /*
10924 * For simplicity do a full modeset on any pipe where the output routing
10925 * changed. We could be more clever, but that would require us to be
10926 * more careful with calling the relevant encoder->mode_set functions.
10927 */
e2e1ed41
DV		 10928 if (*prepare_pipes)
10929 *modeset_pipes = *prepare_pipes;
10930
10931 /* ... and mask these out. */
10932 *modeset_pipes &= ~(*disable_pipes);
10933 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 10934
10935 /*
10936 * HACK: We don't (yet) fully support global modesets. intel_set_config
10937 * obies this rule, but the modeset restore mode of
10938 * intel_modeset_setup_hw_state does not.
10939 */
10940 *modeset_pipes &= 1 << intel_crtc->pipe;
10941 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 10942
10943 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10944 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 10945}
79e53945 10946
ea9d758d 10947static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 10948{
ea9d758d 10949 struct drm_encoder *encoder;
f6e5b160 10950 struct drm_device *dev = crtc->dev;
f6e5b160 10951
ea9d758d
DV		 10952 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10953 if (encoder->crtc == crtc)
10954 return true;
10955
10956 return false;
10957}
10958
10959static void
10960intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10961{
ba41c0de 10962 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 10963 struct intel_encoder *intel_encoder;
10964 struct intel_crtc *intel_crtc;
10965 struct drm_connector *connector;
10966
ba41c0de
DV		 10967 intel_shared_dpll_commit(dev_priv);
10968
b2784e15 10969 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 10970 if (!intel_encoder->base.crtc)
10971 continue;
10972
10973 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10974
10975 if (prepare_pipes & (1 << intel_crtc->pipe))
10976 intel_encoder->connectors_active = false;
10977 }
10978
10979 intel_modeset_commit_output_state(dev);
10980
7668851f 10981 /* Double check state. */
d3fcc808 10982 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10983 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
7bd0a8e7 10984 WARN_ON(intel_crtc->new_config &&
6e3c9717 10985 intel_crtc->new_config != intel_crtc->config);
83d65738 10986 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
ea9d758d
DV		 10987 }
10988
10989 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10990 if (!connector->encoder || !connector->encoder->crtc)
10991 continue;
10992
10993 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10994
10995 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 10996 struct drm_property *dpms_property =
10997 dev->mode_config.dpms_property;
10998
ea9d758d 10999 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11000 drm_object_property_set_value(&connector->base,
68d34720
DV		 11001 dpms_property,
11002 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11003
11004 intel_encoder = to_intel_encoder(connector->encoder);
11005 intel_encoder->connectors_active = true;
11006 }
11007 }
11008
11009}
11010
3bd26263 11011static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11012{
3bd26263 11013 int diff;
f1f644dc
JB		 11014
11015 if (clock1 == clock2)
11016 return true;
11017
11018 if (!clock1 || !clock2)
11019 return false;
11020
11021 diff = abs(clock1 - clock2);
11022
11023 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11024 return true;
11025
11026 return false;
11027}
11028
25c5b266
DV		 11029#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11030 list_for_each_entry((intel_crtc), \
11031 &(dev)->mode_config.crtc_list, \
11032 base.head) \
0973f18f 11033 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11034
0e8ffe1b 11035static bool
2fa2fe9a 11036intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11037 struct intel_crtc_state *current_config,
11038 struct intel_crtc_state *pipe_config)
0e8ffe1b 11039{
66e985c0
DV		 11040#define PIPE_CONF_CHECK_X(name) \
11041 if (current_config->name != pipe_config->name) { \
11042 DRM_ERROR("mismatch in " #name " " \
11043 "(expected 0x%08x, found 0x%08x)\n", \
11044 current_config->name, \
11045 pipe_config->name); \
11046 return false; \
11047 }
11048
08a24034
DV		 11049#define PIPE_CONF_CHECK_I(name) \
11050 if (current_config->name != pipe_config->name) { \
11051 DRM_ERROR("mismatch in " #name " " \
11052 "(expected %i, found %i)\n", \
11053 current_config->name, \
11054 pipe_config->name); \
11055 return false; \
88adfff1
DV		 11056 }
11057
b95af8be
VK		 11058/* This is required for BDW+ where there is only one set of registers for
11059 * switching between high and low RR.
11060 * This macro can be used whenever a comparison has to be made between one
11061 * hw state and multiple sw state variables.
11062 */
11063#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11064 if ((current_config->name != pipe_config->name) && \
11065 (current_config->alt_name != pipe_config->name)) { \
11066 DRM_ERROR("mismatch in " #name " " \
11067 "(expected %i or %i, found %i)\n", \
11068 current_config->name, \
11069 current_config->alt_name, \
11070 pipe_config->name); \
11071 return false; \
11072 }
11073
1bd1bd80
DV		 11074#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11075 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11076 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11077 "(expected %i, found %i)\n", \
11078 current_config->name & (mask), \
11079 pipe_config->name & (mask)); \
11080 return false; \
11081 }
11082
5e550656
VS		 11083#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11084 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11085 DRM_ERROR("mismatch in " #name " " \
11086 "(expected %i, found %i)\n", \
11087 current_config->name, \
11088 pipe_config->name); \
11089 return false; \
11090 }
11091
bb760063
DV		 11092#define PIPE_CONF_QUIRK(quirk) \
11093 ((current_config->quirks | pipe_config->quirks) & (quirk))
11094
eccb140b
DV		 11095 PIPE_CONF_CHECK_I(cpu_transcoder);
11096
08a24034
DV		 11097 PIPE_CONF_CHECK_I(has_pch_encoder);
11098 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11099 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11100 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11101 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11102 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11103 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11104
eb14cb74 11105 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11106
11107 if (INTEL_INFO(dev)->gen < 8) {
11108 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11109 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11110 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11111 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11112 PIPE_CONF_CHECK_I(dp_m_n.tu);
11113
11114 if (current_config->has_drrs) {
11115 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11116 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11117 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11118 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11119 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11120 }
11121 } else {
11122 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11123 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11124 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11125 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11126 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11127 }
eb14cb74 11128
2d112de7
ACO		 11129 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11130 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11131 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11132 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11133 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11134 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11135
2d112de7
ACO		 11136 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11137 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11138 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11139 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11140 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11141 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11142
c93f54cf 11143 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11144 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11145 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11146 IS_VALLEYVIEW(dev))
11147 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11148 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11149
9ed109a7
DV		 11150 PIPE_CONF_CHECK_I(has_audio);
11151
2d112de7 11152 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11153 DRM_MODE_FLAG_INTERLACE);
11154
bb760063 11155 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11156 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11157 DRM_MODE_FLAG_PHSYNC);
2d112de7 11158 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11159 DRM_MODE_FLAG_NHSYNC);
2d112de7 11160 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11161 DRM_MODE_FLAG_PVSYNC);
2d112de7 11162 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11163 DRM_MODE_FLAG_NVSYNC);
11164 }
045ac3b5 11165
37327abd
VS		 11166 PIPE_CONF_CHECK_I(pipe_src_w);
11167 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11168
9953599b
DV		 11169 /*
11170 * FIXME: BIOS likes to set up a cloned config with lvds+external
11171 * screen. Since we don't yet re-compute the pipe config when moving
11172 * just the lvds port away to another pipe the sw tracking won't match.
11173 *
11174 * Proper atomic modesets with recomputed global state will fix this.
11175 * Until then just don't check gmch state for inherited modes.
11176 */
11177 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11178 PIPE_CONF_CHECK_I(gmch_pfit.control);
11179 /* pfit ratios are autocomputed by the hw on gen4+ */
11180 if (INTEL_INFO(dev)->gen < 4)
11181 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11182 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11183 }
11184
fd4daa9c
CW		 11185 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11186 if (current_config->pch_pfit.enabled) {
11187 PIPE_CONF_CHECK_I(pch_pfit.pos);
11188 PIPE_CONF_CHECK_I(pch_pfit.size);
11189 }
2fa2fe9a 11190
e59150dc
JB		 11191 /* BDW+ don't expose a synchronous way to read the state */
11192 if (IS_HASWELL(dev))
11193 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11194
282740f7
VS		 11195 PIPE_CONF_CHECK_I(double_wide);
11196
26804afd
DV		 11197 PIPE_CONF_CHECK_X(ddi_pll_sel);
11198
c0d43d62 11199 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11200 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11201 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11202 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11203 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11204 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11205 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11206 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11207 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11208
42571aef
VS		 11209 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11210 PIPE_CONF_CHECK_I(pipe_bpp);
11211
2d112de7 11212 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11213 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11214
66e985c0 11215#undef PIPE_CONF_CHECK_X
08a24034 11216#undef PIPE_CONF_CHECK_I
b95af8be 11217#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11218#undef PIPE_CONF_CHECK_FLAGS
5e550656 11219#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11220#undef PIPE_CONF_QUIRK
88adfff1 11221
0e8ffe1b
DV		 11222 return true;
11223}
11224
08db6652
DL		 11225static void check_wm_state(struct drm_device *dev)
11226{
11227 struct drm_i915_private *dev_priv = dev->dev_private;
11228 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11229 struct intel_crtc *intel_crtc;
11230 int plane;
11231
11232 if (INTEL_INFO(dev)->gen < 9)
11233 return;
11234
11235 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11236 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11237
11238 for_each_intel_crtc(dev, intel_crtc) {
11239 struct skl_ddb_entry *hw_entry, *sw_entry;
11240 const enum pipe pipe = intel_crtc->pipe;
11241
11242 if (!intel_crtc->active)
11243 continue;
11244
11245 /* planes */
dd740780 11246 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11247 hw_entry = &hw_ddb.plane[pipe][plane];
11248 sw_entry = &sw_ddb->plane[pipe][plane];
11249
11250 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11251 continue;
11252
11253 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11254 "(expected (%u,%u), found (%u,%u))\n",
11255 pipe_name(pipe), plane + 1,
11256 sw_entry->start, sw_entry->end,
11257 hw_entry->start, hw_entry->end);
11258 }
11259
11260 /* cursor */
11261 hw_entry = &hw_ddb.cursor[pipe];
11262 sw_entry = &sw_ddb->cursor[pipe];
11263
11264 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11265 continue;
11266
11267 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11268 "(expected (%u,%u), found (%u,%u))\n",
11269 pipe_name(pipe),
11270 sw_entry->start, sw_entry->end,
11271 hw_entry->start, hw_entry->end);
11272 }
11273}
11274
91d1b4bd
DV		 11275static void
11276check_connector_state(struct drm_device *dev)
8af6cf88 11277{
8af6cf88
DV		 11278 struct intel_connector *connector;
11279
3a3371ff 11280 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11281 /* This also checks the encoder/connector hw state with the
11282 * ->get_hw_state callbacks. */
11283 intel_connector_check_state(connector);
11284
e2c719b7 11285 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11286 "connector's staged encoder doesn't match current encoder\n");
11287 }
91d1b4bd
DV		 11288}
11289
11290static void
11291check_encoder_state(struct drm_device *dev)
11292{
11293 struct intel_encoder *encoder;
11294 struct intel_connector *connector;
8af6cf88 11295
b2784e15 11296 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11297 bool enabled = false;
11298 bool active = false;
11299 enum pipe pipe, tracked_pipe;
11300
11301 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11302 encoder->base.base.id,
8e329a03 11303 encoder->base.name);
8af6cf88 11304
e2c719b7 11305 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11306 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11307 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11308 "encoder's active_connectors set, but no crtc\n");
11309
3a3371ff 11310 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11311 if (connector->base.encoder != &encoder->base)
11312 continue;
11313 enabled = true;
11314 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11315 active = true;
11316 }
0e32b39c
DA		 11317 /*
11318 * for MST connectors if we unplug the connector is gone
11319 * away but the encoder is still connected to a crtc
11320 * until a modeset happens in response to the hotplug.
11321 */
11322 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11323 continue;
11324
e2c719b7 11325 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11326 "encoder's enabled state mismatch "
11327 "(expected %i, found %i)\n",
11328 !!encoder->base.crtc, enabled);
e2c719b7 11329 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 11330 "active encoder with no crtc\n");
11331
e2c719b7 11332 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 11333 "encoder's computed active state doesn't match tracked active state "
11334 "(expected %i, found %i)\n", active, encoder->connectors_active);
11335
11336 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11337 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 11338 "encoder's hw state doesn't match sw tracking "
11339 "(expected %i, found %i)\n",
11340 encoder->connectors_active, active);
11341
11342 if (!encoder->base.crtc)
11343 continue;
11344
11345 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11346 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 11347 "active encoder's pipe doesn't match"
11348 "(expected %i, found %i)\n",
11349 tracked_pipe, pipe);
11350
11351 }
91d1b4bd
DV		 11352}
11353
11354static void
11355check_crtc_state(struct drm_device *dev)
11356{
fbee40df 11357 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11358 struct intel_crtc *crtc;
11359 struct intel_encoder *encoder;
5cec258b 11360 struct intel_crtc_state pipe_config;
8af6cf88 11361
d3fcc808 11362 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 11363 bool enabled = false;
11364 bool active = false;
11365
045ac3b5
JB		 11366 memset(&pipe_config, 0, sizeof(pipe_config));
11367
8af6cf88
DV		 11368 DRM_DEBUG_KMS("[CRTC:%d]\n",
11369 crtc->base.base.id);
11370
83d65738 11371 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 11372 "active crtc, but not enabled in sw tracking\n");
11373
b2784e15 11374 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11375 if (encoder->base.crtc != &crtc->base)
11376 continue;
11377 enabled = true;
11378 if (encoder->connectors_active)
11379 active = true;
11380 }
6c49f241 11381
e2c719b7 11382 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 11383 "crtc's computed active state doesn't match tracked active state "
11384 "(expected %i, found %i)\n", active, crtc->active);
83d65738 11385 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 11386 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 11387 "(expected %i, found %i)\n", enabled,
11388 crtc->base.state->enable);
8af6cf88 11389
0e8ffe1b
DV		 11390 active = dev_priv->display.get_pipe_config(crtc,
11391 &pipe_config);
d62cf62a 11392
b6b5d049
VS		 11393 /* hw state is inconsistent with the pipe quirk */
11394 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11395 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 11396 active = crtc->active;
11397
b2784e15 11398 for_each_intel_encoder(dev, encoder) {
3eaba51c 11399 enum pipe pipe;
6c49f241
DV		 11400 if (encoder->base.crtc != &crtc->base)
11401 continue;
1d37b689 11402 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 11403 encoder->get_config(encoder, &pipe_config);
11404 }
11405
e2c719b7 11406 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 11407 "crtc active state doesn't match with hw state "
11408 "(expected %i, found %i)\n", crtc->active, active);
11409
c0b03411 11410 if (active &&
6e3c9717 11411 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 11412 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 11413 intel_dump_pipe_config(crtc, &pipe_config,
11414 "[hw state]");
6e3c9717 11415 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 11416 "[sw state]");
11417 }
8af6cf88
DV		 11418 }
11419}
11420
91d1b4bd
DV		 11421static void
11422check_shared_dpll_state(struct drm_device *dev)
11423{
fbee40df 11424 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11425 struct intel_crtc *crtc;
11426 struct intel_dpll_hw_state dpll_hw_state;
11427 int i;
5358901f
DV		 11428
11429 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11430 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11431 int enabled_crtcs = 0, active_crtcs = 0;
11432 bool active;
11433
11434 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11435
11436 DRM_DEBUG_KMS("%s\n", pll->name);
11437
11438 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11439
e2c719b7 11440 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 11441 "more active pll users than references: %i vs %i\n",
3e369b76 11442 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 11443 I915_STATE_WARN(pll->active && !pll->on,
5358901f 11444 "pll in active use but not on in sw tracking\n");
e2c719b7 11445 I915_STATE_WARN(pll->on && !pll->active,
35c95375 11446 "pll in on but not on in use in sw tracking\n");
e2c719b7 11447 I915_STATE_WARN(pll->on != active,
5358901f
DV		 11448 "pll on state mismatch (expected %i, found %i)\n",
11449 pll->on, active);
11450
d3fcc808 11451 for_each_intel_crtc(dev, crtc) {
83d65738 11452 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 11453 enabled_crtcs++;
11454 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11455 active_crtcs++;
11456 }
e2c719b7 11457 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 11458 "pll active crtcs mismatch (expected %i, found %i)\n",
11459 pll->active, active_crtcs);
e2c719b7 11460 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 11461 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 11462 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 11463
e2c719b7 11464 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 11465 sizeof(dpll_hw_state)),
11466 "pll hw state mismatch\n");
5358901f 11467 }
8af6cf88
DV		 11468}
11469
91d1b4bd
DV		 11470void
11471intel_modeset_check_state(struct drm_device *dev)
11472{
08db6652 11473 check_wm_state(dev);
91d1b4bd
DV		 11474 check_connector_state(dev);
11475 check_encoder_state(dev);
11476 check_crtc_state(dev);
11477 check_shared_dpll_state(dev);
11478}
11479
5cec258b 11480void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 11481 int dotclock)
11482{
11483 /*
11484 * FDI already provided one idea for the dotclock.
11485 * Yell if the encoder disagrees.
11486 */
2d112de7 11487 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 11488 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 11489 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 11490}
11491
80715b2f
VS		 11492static void update_scanline_offset(struct intel_crtc *crtc)
11493{
11494 struct drm_device *dev = crtc->base.dev;
11495
11496 /*
11497 * The scanline counter increments at the leading edge of hsync.
11498 *
11499 * On most platforms it starts counting from vtotal-1 on the
11500 * first active line. That means the scanline counter value is
11501 * always one less than what we would expect. Ie. just after
11502 * start of vblank, which also occurs at start of hsync (on the
11503 * last active line), the scanline counter will read vblank_start-1.
11504 *
11505 * On gen2 the scanline counter starts counting from 1 instead
11506 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11507 * to keep the value positive), instead of adding one.
11508 *
11509 * On HSW+ the behaviour of the scanline counter depends on the output
11510 * type. For DP ports it behaves like most other platforms, but on HDMI
11511 * there's an extra 1 line difference. So we need to add two instead of
11512 * one to the value.
11513 */
11514 if (IS_GEN2(dev)) {
6e3c9717 11515 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 11516 int vtotal;
11517
11518 vtotal = mode->crtc_vtotal;
11519 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11520 vtotal /= 2;
11521
11522 crtc->scanline_offset = vtotal - 1;
11523 } else if (HAS_DDI(dev) &&
409ee761 11524 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 11525 crtc->scanline_offset = 2;
11526 } else
11527 crtc->scanline_offset = 1;
11528}
11529
5cec258b 11530static struct intel_crtc_state *
7f27126e
JB		 11531intel_modeset_compute_config(struct drm_crtc *crtc,
11532 struct drm_display_mode *mode,
11533 struct drm_framebuffer *fb,
83a57153 11534 struct drm_atomic_state *state,
7f27126e
JB		 11535 unsigned *modeset_pipes,
11536 unsigned *prepare_pipes,
11537 unsigned *disable_pipes)
11538{
db7542dd 11539 struct drm_device *dev = crtc->dev;
5cec258b 11540 struct intel_crtc_state *pipe_config = NULL;
db7542dd 11541 struct intel_crtc *intel_crtc;
0b901879
ACO		 11542 int ret = 0;
11543
11544 ret = drm_atomic_add_affected_connectors(state, crtc);
11545 if (ret)
11546 return ERR_PTR(ret);
7f27126e
JB		 11547
11548 intel_modeset_affected_pipes(crtc, modeset_pipes,
11549 prepare_pipes, disable_pipes);
11550
db7542dd
ACO		 11551 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
11552 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
11553 if (IS_ERR(pipe_config))
11554 return pipe_config;
11555
11556 pipe_config->base.enable = false;
11557 }
7f27126e
JB		 11558
11559 /*
11560 * Note this needs changes when we start tracking multiple modes
11561 * and crtcs. At that point we'll need to compute the whole config
11562 * (i.e. one pipe_config for each crtc) rather than just the one
11563 * for this crtc.
11564 */
db7542dd
ACO		 11565 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
11566 /* FIXME: For now we still expect modeset_pipes has at most
11567 * one bit set. */
11568 if (WARN_ON(&intel_crtc->base != crtc))
11569 continue;
83a57153 11570
db7542dd
ACO		 11571 pipe_config = intel_modeset_pipe_config(crtc, fb, mode, state);
11572 if (IS_ERR(pipe_config))
11573 return pipe_config;
7f27126e 11574
304603f4
ACO		 11575 pipe_config->base.enable = true;
11576
db7542dd
ACO		 11577 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11578 "[modeset]");
11579 }
11580
11581 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
7f27126e
JB		 11582}
11583
ed6739ef
ACO		 11584static int __intel_set_mode_setup_plls(struct drm_device *dev,
11585 unsigned modeset_pipes,
11586 unsigned disable_pipes)
11587{
11588 struct drm_i915_private *dev_priv = to_i915(dev);
11589 unsigned clear_pipes = modeset_pipes | disable_pipes;
11590 struct intel_crtc *intel_crtc;
11591 int ret = 0;
11592
11593 if (!dev_priv->display.crtc_compute_clock)
11594 return 0;
11595
11596 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11597 if (ret)
11598 goto done;
11599
11600 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11601 struct intel_crtc_state *state = intel_crtc->new_config;
11602 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11603 state);
11604 if (ret) {
11605 intel_shared_dpll_abort_config(dev_priv);
11606 goto done;
11607 }
11608 }
11609
11610done:
11611 return ret;
11612}
11613
f30da187
DV		 11614static int __intel_set_mode(struct drm_crtc *crtc,
11615 struct drm_display_mode *mode,
7f27126e 11616 int x, int y, struct drm_framebuffer *fb,
5cec258b 11617 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11618 unsigned modeset_pipes,
11619 unsigned prepare_pipes,
11620 unsigned disable_pipes)
a6778b3c
DV		 11621{
11622 struct drm_device *dev = crtc->dev;
fbee40df 11623 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 11624 struct drm_display_mode *saved_mode;
304603f4 11625 struct drm_atomic_state *state = pipe_config->base.state;
83a57153 11626 struct intel_crtc_state *crtc_state_copy = NULL;
25c5b266 11627 struct intel_crtc *intel_crtc;
c0c36b94 11628 int ret = 0;
a6778b3c 11629
4b4b9238 11630 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 11631 if (!saved_mode)
11632 return -ENOMEM;
a6778b3c 11633
83a57153
ACO		 11634 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
11635 if (!crtc_state_copy) {
11636 ret = -ENOMEM;
11637 goto done;
11638 }
11639
3ac18232 11640 *saved_mode = crtc->mode;
a6778b3c 11641
b9950a13
VS		 11642 if (modeset_pipes)
11643 to_intel_crtc(crtc)->new_config = pipe_config;
11644
30a970c6
JB		 11645 /*
11646 * See if the config requires any additional preparation, e.g.
11647 * to adjust global state with pipes off. We need to do this
11648 * here so we can get the modeset_pipe updated config for the new
11649 * mode set on this crtc. For other crtcs we need to use the
11650 * adjusted_mode bits in the crtc directly.
11651 */
c164f833 11652 if (IS_VALLEYVIEW(dev)) {
304603f4
ACO		 11653 ret = valleyview_modeset_global_pipes(state, &prepare_pipes);
11654 if (ret)
11655 goto done;
30a970c6 11656
c164f833
VS		 11657 /* may have added more to prepare_pipes than we should */
11658 prepare_pipes &= ~disable_pipes;
11659 }
11660
ed6739ef
ACO		 11661 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11662 if (ret)
11663 goto done;
8bd31e67 11664
460da916
DV		 11665 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11666 intel_crtc_disable(&intel_crtc->base);
11667
ea9d758d 11668 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 11669 if (intel_crtc->base.state->enable)
ea9d758d
DV		 11670 dev_priv->display.crtc_disable(&intel_crtc->base);
11671 }
a6778b3c 11672
6c4c86f5
DV		 11673 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11674 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 11675 *
11676 * Note we'll need to fix this up when we start tracking multiple
11677 * pipes; here we assume a single modeset_pipe and only track the
11678 * single crtc and mode.
f6e5b160 11679 */
b8cecdf5 11680 if (modeset_pipes) {
25c5b266 11681 crtc->mode = *mode;
b8cecdf5
DV		 11682 /* mode_set/enable/disable functions rely on a correct pipe
11683 * config. */
f5de6e07 11684 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 11685
11686 /*
11687 * Calculate and store various constants which
11688 * are later needed by vblank and swap-completion
11689 * timestamping. They are derived from true hwmode.
11690 */
11691 drm_calc_timestamping_constants(crtc,
2d112de7 11692 &pipe_config->base.adjusted_mode);
b8cecdf5 11693 }
7758a113 11694
ea9d758d
DV		 11695 /* Only after disabling all output pipelines that will be changed can we
11696 * update the the output configuration. */
11697 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 11698
304603f4 11699 modeset_update_crtc_power_domains(state);
47fab737 11700
a6778b3c
DV		 11701 /* Set up the DPLL and any encoders state that needs to adjust or depend
11702 * on the DPLL.
f6e5b160 11703 */
25c5b266 11704 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 11705 struct drm_plane *primary = intel_crtc->base.primary;
11706 int vdisplay, hdisplay;
4c10794f 11707
455a6808
GP		 11708 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11709 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11710 fb, 0, 0,
11711 hdisplay, vdisplay,
11712 x << 16, y << 16,
11713 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 11714 }
11715
11716 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 11717 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11718 update_scanline_offset(intel_crtc);
11719
25c5b266 11720 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 11721 }
a6778b3c 11722
a6778b3c
DV		 11723 /* FIXME: add subpixel order */
11724done:
83d65738 11725 if (ret && crtc->state->enable)
3ac18232 11726 crtc->mode = *saved_mode;
a6778b3c 11727
83a57153
ACO		 11728 if (ret == 0 && pipe_config) {
11729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11730
11731 /* The pipe_config will be freed with the atomic state, so
11732 * make a copy. */
11733 memcpy(crtc_state_copy, intel_crtc->config,
11734 sizeof *crtc_state_copy);
11735 intel_crtc->config = crtc_state_copy;
11736 intel_crtc->base.state = &crtc_state_copy->base;
11737
11738 if (modeset_pipes)
11739 intel_crtc->new_config = intel_crtc->config;
11740 } else {
11741 kfree(crtc_state_copy);
11742 }
11743
3ac18232 11744 kfree(saved_mode);
a6778b3c 11745 return ret;
f6e5b160
CW		 11746}
11747
7f27126e
JB		 11748static int intel_set_mode_pipes(struct drm_crtc *crtc,
11749 struct drm_display_mode *mode,
11750 int x, int y, struct drm_framebuffer *fb,
5cec258b 11751 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11752 unsigned modeset_pipes,
11753 unsigned prepare_pipes,
11754 unsigned disable_pipes)
f30da187
DV		 11755{
11756 int ret;
11757
7f27126e
JB		 11758 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11759 prepare_pipes, disable_pipes);
f30da187
DV		 11760
11761 if (ret == 0)
11762 intel_modeset_check_state(crtc->dev);
11763
11764 return ret;
11765}
11766
7f27126e
JB		 11767static int intel_set_mode(struct drm_crtc *crtc,
11768 struct drm_display_mode *mode,
83a57153
ACO		 11769 int x, int y, struct drm_framebuffer *fb,
11770 struct drm_atomic_state *state)
7f27126e 11771{
5cec258b 11772 struct intel_crtc_state *pipe_config;
7f27126e 11773 unsigned modeset_pipes, prepare_pipes, disable_pipes;
83a57153 11774 int ret = 0;
7f27126e 11775
83a57153 11776 pipe_config = intel_modeset_compute_config(crtc, mode, fb, state,
7f27126e
JB		 11777 &modeset_pipes,
11778 &prepare_pipes,
11779 &disable_pipes);
11780
83a57153
ACO		 11781 if (IS_ERR(pipe_config)) {
11782 ret = PTR_ERR(pipe_config);
11783 goto out;
11784 }
11785
11786 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11787 modeset_pipes, prepare_pipes,
11788 disable_pipes);
11789 if (ret)
11790 goto out;
7f27126e 11791
83a57153
ACO		 11792out:
11793 return ret;
7f27126e
JB		 11794}
11795
c0c36b94
CW		 11796void intel_crtc_restore_mode(struct drm_crtc *crtc)
11797{
83a57153
ACO		 11798 struct drm_device *dev = crtc->dev;
11799 struct drm_atomic_state *state;
11800 struct intel_encoder *encoder;
11801 struct intel_connector *connector;
11802 struct drm_connector_state *connector_state;
11803
11804 state = drm_atomic_state_alloc(dev);
11805 if (!state) {
11806 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
11807 crtc->base.id);
11808 return;
11809 }
11810
11811 state->acquire_ctx = dev->mode_config.acquire_ctx;
11812
11813 /* The force restore path in the HW readout code relies on the staged
11814 * config still keeping the user requested config while the actual
11815 * state has been overwritten by the configuration read from HW. We
11816 * need to copy the staged config to the atomic state, otherwise the
11817 * mode set will just reapply the state the HW is already in. */
11818 for_each_intel_encoder(dev, encoder) {
11819 if (&encoder->new_crtc->base != crtc)
11820 continue;
11821
11822 for_each_intel_connector(dev, connector) {
11823 if (connector->new_encoder != encoder)
11824 continue;
11825
11826 connector_state = drm_atomic_get_connector_state(state, &connector->base);
11827 if (IS_ERR(connector_state)) {
11828 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
11829 connector->base.base.id,
11830 connector->base.name,
11831 PTR_ERR(connector_state));
11832 continue;
11833 }
11834
11835 connector_state->crtc = crtc;
11836 connector_state->best_encoder = &encoder->base;
11837 }
11838 }
11839
11840 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
11841 state);
11842
11843 drm_atomic_state_free(state);
c0c36b94
CW		 11844}
11845
25c5b266
DV		 11846#undef for_each_intel_crtc_masked
11847
d9e55608
DV		 11848static void intel_set_config_free(struct intel_set_config *config)
11849{
11850 if (!config)
11851 return;
11852
1aa4b628
DV		 11853 kfree(config->save_connector_encoders);
11854 kfree(config->save_encoder_crtcs);
7668851f 11855 kfree(config->save_crtc_enabled);
d9e55608
DV		 11856 kfree(config);
11857}
11858
85f9eb71
DV		 11859static int intel_set_config_save_state(struct drm_device *dev,
11860 struct intel_set_config *config)
11861{
7668851f 11862 struct drm_crtc *crtc;
85f9eb71
DV		 11863 struct drm_encoder *encoder;
11864 struct drm_connector *connector;
11865 int count;
11866
7668851f
VS		 11867 config->save_crtc_enabled =
11868 kcalloc(dev->mode_config.num_crtc,
11869 sizeof(bool), GFP_KERNEL);
11870 if (!config->save_crtc_enabled)
11871 return -ENOMEM;
11872
1aa4b628
DV		 11873 config->save_encoder_crtcs =
11874 kcalloc(dev->mode_config.num_encoder,
11875 sizeof(struct drm_crtc *), GFP_KERNEL);
11876 if (!config->save_encoder_crtcs)
85f9eb71
DV		 11877 return -ENOMEM;
11878
1aa4b628
DV		 11879 config->save_connector_encoders =
11880 kcalloc(dev->mode_config.num_connector,
11881 sizeof(struct drm_encoder *), GFP_KERNEL);
11882 if (!config->save_connector_encoders)
85f9eb71
DV		 11883 return -ENOMEM;
11884
11885 /* Copy data. Note that driver private data is not affected.
11886 * Should anything bad happen only the expected state is
11887 * restored, not the drivers personal bookkeeping.
11888 */
7668851f 11889 count = 0;
70e1e0ec 11890 for_each_crtc(dev, crtc) {
83d65738 11891 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 11892 }
11893
85f9eb71
DV		 11894 count = 0;
11895 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 11896 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 11897 }
11898
11899 count = 0;
11900 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 11901 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 11902 }
11903
11904 return 0;
11905}
11906
11907static void intel_set_config_restore_state(struct drm_device *dev,
11908 struct intel_set_config *config)
11909{
7668851f 11910 struct intel_crtc *crtc;
9a935856
DV		 11911 struct intel_encoder *encoder;
11912 struct intel_connector *connector;
85f9eb71
DV		 11913 int count;
11914
7668851f 11915 count = 0;
d3fcc808 11916 for_each_intel_crtc(dev, crtc) {
7668851f 11917 crtc->new_enabled = config->save_crtc_enabled[count++];
7bd0a8e7
VS		 11918
11919 if (crtc->new_enabled)
6e3c9717 11920 crtc->new_config = crtc->config;
7bd0a8e7
VS		 11921 else
11922 crtc->new_config = NULL;
7668851f
VS		 11923 }
11924
85f9eb71 11925 count = 0;
b2784e15 11926 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11927 encoder->new_crtc =
11928 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 11929 }
11930
11931 count = 0;
3a3371ff 11932 for_each_intel_connector(dev, connector) {
9a935856
DV		 11933 connector->new_encoder =
11934 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 11935 }
11936}
11937
e3de42b6 11938static bool
2e57f47d 11939is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 11940{
11941 int i;
11942
2e57f47d
CW		 11943 if (set->num_connectors == 0)
11944 return false;
11945
11946 if (WARN_ON(set->connectors == NULL))
11947 return false;
11948
11949 for (i = 0; i < set->num_connectors; i++)
11950 if (set->connectors[i]->encoder &&
11951 set->connectors[i]->encoder->crtc == set->crtc &&
11952 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 11953 return true;
11954
11955 return false;
11956}
11957
5e2b584e
DV		 11958static void
11959intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11960 struct intel_set_config *config)
11961{
11962
11963 /* We should be able to check here if the fb has the same properties
11964 * and then just flip_or_move it */
2e57f47d
CW		 11965 if (is_crtc_connector_off(set)) {
11966 config->mode_changed = true;
f4510a27 11967 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 11968 /*
11969 * If we have no fb, we can only flip as long as the crtc is
11970 * active, otherwise we need a full mode set. The crtc may
11971 * be active if we've only disabled the primary plane, or
11972 * in fastboot situations.
11973 */
f4510a27 11974 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 11975 struct intel_crtc *intel_crtc =
11976 to_intel_crtc(set->crtc);
11977
3b150f08 11978 if (intel_crtc->active) {
319d9827
JB		 11979 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11980 config->fb_changed = true;
11981 } else {
11982 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11983 config->mode_changed = true;
11984 }
5e2b584e
DV		 11985 } else if (set->fb == NULL) {
11986 config->mode_changed = true;
72f4901e 11987 } else if (set->fb->pixel_format !=
f4510a27 11988 set->crtc->primary->fb->pixel_format) {
5e2b584e 11989 config->mode_changed = true;
e3de42b6 11990 } else {
5e2b584e 11991 config->fb_changed = true;
e3de42b6 11992 }
5e2b584e
DV		 11993 }
11994
835c5873 11995 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 11996 config->fb_changed = true;
11997
11998 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11999 DRM_DEBUG_KMS("modes are different, full mode set\n");
12000 drm_mode_debug_printmodeline(&set->crtc->mode);
12001 drm_mode_debug_printmodeline(set->mode);
12002 config->mode_changed = true;
12003 }
a1d95703
CW		 12004
12005 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12006 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 12007}
12008
2e431051 12009static int
9a935856
DV		 12010intel_modeset_stage_output_state(struct drm_device *dev,
12011 struct drm_mode_set *set,
944b0c76
ACO		 12012 struct intel_set_config *config,
12013 struct drm_atomic_state *state)
50f56119 12014{
9a935856 12015 struct intel_connector *connector;
944b0c76 12016 struct drm_connector_state *connector_state;
9a935856 12017 struct intel_encoder *encoder;
7668851f 12018 struct intel_crtc *crtc;
f3f08572 12019 int ro;
50f56119 12020
9abdda74 12021 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12022 * of connectors. For paranoia, double-check this. */
12023 WARN_ON(!set->fb && (set->num_connectors != 0));
12024 WARN_ON(set->fb && (set->num_connectors == 0));
12025
3a3371ff 12026 for_each_intel_connector(dev, connector) {
9a935856
DV		 12027 /* Otherwise traverse passed in connector list and get encoders
12028 * for them. */
50f56119 12029 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12030 if (set->connectors[ro] == &connector->base) {
0e32b39c 12031 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 12032 break;
12033 }
12034 }
12035
9a935856
DV		 12036 /* If we disable the crtc, disable all its connectors. Also, if
12037 * the connector is on the changing crtc but not on the new
12038 * connector list, disable it. */
12039 if ((!set->fb || ro == set->num_connectors) &&
12040 connector->base.encoder &&
12041 connector->base.encoder->crtc == set->crtc) {
12042 connector->new_encoder = NULL;
12043
12044 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12045 connector->base.base.id,
c23cc417 12046 connector->base.name);
9a935856
DV		 12047 }
12048
12049
12050 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 12051 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12052 connector->base.base.id,
12053 connector->base.name);
5e2b584e 12054 config->mode_changed = true;
50f56119
DV		 12055 }
12056 }
9a935856 12057 /* connector->new_encoder is now updated for all connectors. */
50f56119 12058
9a935856 12059 /* Update crtc of enabled connectors. */
3a3371ff 12060 for_each_intel_connector(dev, connector) {
7668851f
VS		 12061 struct drm_crtc *new_crtc;
12062
9a935856 12063 if (!connector->new_encoder)
50f56119
DV		 12064 continue;
12065
9a935856 12066 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 12067
12068 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12069 if (set->connectors[ro] == &connector->base)
50f56119
DV		 12070 new_crtc = set->crtc;
12071 }
12072
12073 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 12074 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12075 new_crtc)) {
5e2b584e 12076 return -EINVAL;
50f56119 12077 }
0e32b39c 12078 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856 12079
944b0c76
ACO		 12080 connector_state =
12081 drm_atomic_get_connector_state(state, &connector->base);
12082 if (IS_ERR(connector_state))
12083 return PTR_ERR(connector_state);
12084
12085 connector_state->crtc = new_crtc;
12086 connector_state->best_encoder = &connector->new_encoder->base;
12087
9a935856
DV		 12088 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12089 connector->base.base.id,
c23cc417 12090 connector->base.name,
9a935856
DV		 12091 new_crtc->base.id);
12092 }
12093
12094 /* Check for any encoders that needs to be disabled. */
b2784e15 12095 for_each_intel_encoder(dev, encoder) {
5a65f358 12096 int num_connectors = 0;
3a3371ff 12097 for_each_intel_connector(dev, connector) {
9a935856
DV		 12098 if (connector->new_encoder == encoder) {
12099 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 12100 num_connectors++;
9a935856
DV		 12101 }
12102 }
5a65f358
PZ		 12103
12104 if (num_connectors == 0)
12105 encoder->new_crtc = NULL;
12106 else if (num_connectors > 1)
12107 return -EINVAL;
12108
9a935856
DV		 12109 /* Only now check for crtc changes so we don't miss encoders
12110 * that will be disabled. */
12111 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 12112 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12113 encoder->base.base.id,
12114 encoder->base.name);
5e2b584e 12115 config->mode_changed = true;
50f56119
DV		 12116 }
12117 }
9a935856 12118 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 12119 for_each_intel_connector(dev, connector) {
944b0c76
ACO		 12120 connector_state =
12121 drm_atomic_get_connector_state(state, &connector->base);
9d918c15
ACO		 12122 if (IS_ERR(connector_state))
12123 return PTR_ERR(connector_state);
944b0c76
ACO		 12124
12125 if (connector->new_encoder) {
0e32b39c
DA		 12126 if (connector->new_encoder != connector->encoder)
12127 connector->encoder = connector->new_encoder;
944b0c76
ACO		 12128 } else {
12129 connector_state->crtc = NULL;
f61cccf3 12130 connector_state->best_encoder = NULL;
944b0c76 12131 }
0e32b39c 12132 }
d3fcc808 12133 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12134 crtc->new_enabled = false;
12135
b2784e15 12136 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 12137 if (encoder->new_crtc == crtc) {
12138 crtc->new_enabled = true;
12139 break;
12140 }
12141 }
12142
83d65738 12143 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 12144 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12145 crtc->base.base.id,
7668851f
VS		 12146 crtc->new_enabled ? "en" : "dis");
12147 config->mode_changed = true;
12148 }
7bd0a8e7
VS		 12149
12150 if (crtc->new_enabled)
6e3c9717 12151 crtc->new_config = crtc->config;
7bd0a8e7
VS		 12152 else
12153 crtc->new_config = NULL;
7668851f
VS		 12154 }
12155
2e431051
DV		 12156 return 0;
12157}
12158
7d00a1f5
VS		 12159static void disable_crtc_nofb(struct intel_crtc *crtc)
12160{
12161 struct drm_device *dev = crtc->base.dev;
12162 struct intel_encoder *encoder;
12163 struct intel_connector *connector;
12164
12165 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12166 pipe_name(crtc->pipe));
12167
3a3371ff 12168 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 12169 if (connector->new_encoder &&
12170 connector->new_encoder->new_crtc == crtc)
12171 connector->new_encoder = NULL;
12172 }
12173
b2784e15 12174 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 12175 if (encoder->new_crtc == crtc)
12176 encoder->new_crtc = NULL;
12177 }
12178
12179 crtc->new_enabled = false;
7bd0a8e7 12180 crtc->new_config = NULL;
7d00a1f5
VS		 12181}
12182
2e431051
DV		 12183static int intel_crtc_set_config(struct drm_mode_set *set)
12184{
12185 struct drm_device *dev;
2e431051 12186 struct drm_mode_set save_set;
83a57153 12187 struct drm_atomic_state *state = NULL;
2e431051 12188 struct intel_set_config *config;
5cec258b 12189 struct intel_crtc_state *pipe_config;
50f52756 12190 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 12191 int ret;
2e431051 12192
8d3e375e
DV		 12193 BUG_ON(!set);
12194 BUG_ON(!set->crtc);
12195 BUG_ON(!set->crtc->helper_private);
2e431051 12196
7e53f3a4
DV		 12197 /* Enforce sane interface api - has been abused by the fb helper. */
12198 BUG_ON(!set->mode && set->fb);
12199 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12200
2e431051
DV		 12201 if (set->fb) {
12202 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12203 set->crtc->base.id, set->fb->base.id,
12204 (int)set->num_connectors, set->x, set->y);
12205 } else {
12206 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12207 }
12208
12209 dev = set->crtc->dev;
12210
12211 ret = -ENOMEM;
12212 config = kzalloc(sizeof(*config), GFP_KERNEL);
12213 if (!config)
12214 goto out_config;
12215
12216 ret = intel_set_config_save_state(dev, config);
12217 if (ret)
12218 goto out_config;
12219
12220 save_set.crtc = set->crtc;
12221 save_set.mode = &set->crtc->mode;
12222 save_set.x = set->crtc->x;
12223 save_set.y = set->crtc->y;
f4510a27 12224 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 12225
12226 /* Compute whether we need a full modeset, only an fb base update or no
12227 * change at all. In the future we might also check whether only the
12228 * mode changed, e.g. for LVDS where we only change the panel fitter in
12229 * such cases. */
12230 intel_set_config_compute_mode_changes(set, config);
12231
83a57153
ACO		 12232 state = drm_atomic_state_alloc(dev);
12233 if (!state) {
12234 ret = -ENOMEM;
12235 goto out_config;
12236 }
12237
12238 state->acquire_ctx = dev->mode_config.acquire_ctx;
12239
944b0c76 12240 ret = intel_modeset_stage_output_state(dev, set, config, state);
2e431051
DV		 12241 if (ret)
12242 goto fail;
12243
50f52756 12244 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
83a57153 12245 set->fb, state,
50f52756
JB		 12246 &modeset_pipes,
12247 &prepare_pipes,
12248 &disable_pipes);
20664591 12249 if (IS_ERR(pipe_config)) {
6ac0483b 12250 ret = PTR_ERR(pipe_config);
50f52756 12251 goto fail;
20664591 12252 } else if (pipe_config) {
b9950a13 12253 if (pipe_config->has_audio !=
6e3c9717 12254 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 12255 config->mode_changed = true;
12256
af15d2ce
JB		 12257 /*
12258 * Note we have an issue here with infoframes: current code
12259 * only updates them on the full mode set path per hw
12260 * requirements. So here we should be checking for any
12261 * required changes and forcing a mode set.
12262 */
20664591 12263 }
50f52756 12264
1f9954d0
JB		 12265 intel_update_pipe_size(to_intel_crtc(set->crtc));
12266
5e2b584e 12267 if (config->mode_changed) {
50f52756
JB		 12268 ret = intel_set_mode_pipes(set->crtc, set->mode,
12269 set->x, set->y, set->fb, pipe_config,
12270 modeset_pipes, prepare_pipes,
12271 disable_pipes);
5e2b584e 12272 } else if (config->fb_changed) {
3b150f08 12273 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 12274 struct drm_plane *primary = set->crtc->primary;
12275 int vdisplay, hdisplay;
3b150f08 12276
455a6808
GP		 12277 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
12278 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
12279 0, 0, hdisplay, vdisplay,
12280 set->x << 16, set->y << 16,
12281 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 12282
12283 /*
12284 * We need to make sure the primary plane is re-enabled if it
12285 * has previously been turned off.
12286 */
12287 if (!intel_crtc->primary_enabled && ret == 0) {
12288 WARN_ON(!intel_crtc->active);
fdd508a6 12289 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 12290 }
12291
7ca51a3a
JB		 12292 /*
12293 * In the fastboot case this may be our only check of the
12294 * state after boot. It would be better to only do it on
12295 * the first update, but we don't have a nice way of doing that
12296 * (and really, set_config isn't used much for high freq page
12297 * flipping, so increasing its cost here shouldn't be a big
12298 * deal).
12299 */
d330a953 12300 if (i915.fastboot && ret == 0)
7ca51a3a 12301 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12302 }
12303
2d05eae1 12304 if (ret) {
bf67dfeb
DV		 12305 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12306 set->crtc->base.id, ret);
50f56119 12307fail:
2d05eae1 12308 intel_set_config_restore_state(dev, config);
50f56119 12309
83a57153
ACO		 12310 drm_atomic_state_clear(state);
12311
7d00a1f5
VS		 12312 /*
12313 * HACK: if the pipe was on, but we didn't have a framebuffer,
12314 * force the pipe off to avoid oopsing in the modeset code
12315 * due to fb==NULL. This should only happen during boot since
12316 * we don't yet reconstruct the FB from the hardware state.
12317 */
12318 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12319 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12320
2d05eae1
CW		 12321 /* Try to restore the config */
12322 if (config->mode_changed &&
12323 intel_set_mode(save_set.crtc, save_set.mode,
83a57153
ACO		 12324 save_set.x, save_set.y, save_set.fb,
12325 state))
2d05eae1
CW		 12326 DRM_ERROR("failed to restore config after modeset failure\n");
12327 }
50f56119 12328
d9e55608 12329out_config:
83a57153
ACO		 12330 if (state)
12331 drm_atomic_state_free(state);
12332
d9e55608 12333 intel_set_config_free(config);
50f56119
DV		 12334 return ret;
12335}
f6e5b160
CW		 12336
12337static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12338 .gamma_set = intel_crtc_gamma_set,
50f56119 12339 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12340 .destroy = intel_crtc_destroy,
12341 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12342 .atomic_duplicate_state = intel_crtc_duplicate_state,
12343 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12344};
12345
5358901f
DV		 12346static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12347 struct intel_shared_dpll *pll,
12348 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12349{
5358901f 12350 uint32_t val;
ee7b9f93 12351
f458ebbc 12352 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12353 return false;
12354
5358901f 12355 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12356 hw_state->dpll = val;
12357 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12358 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12359
12360 return val & DPLL_VCO_ENABLE;
12361}
12362
15bdd4cf
DV		 12363static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12364 struct intel_shared_dpll *pll)
12365{
3e369b76
ACO		 12366 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12367 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12368}
12369
e7b903d2
DV		 12370static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12371 struct intel_shared_dpll *pll)
12372{
e7b903d2 12373 /* PCH refclock must be enabled first */
89eff4be 12374 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12375
3e369b76 12376 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12377
12378 /* Wait for the clocks to stabilize. */
12379 POSTING_READ(PCH_DPLL(pll->id));
12380 udelay(150);
12381
12382 /* The pixel multiplier can only be updated once the
12383 * DPLL is enabled and the clocks are stable.
12384 *
12385 * So write it again.
12386 */
3e369b76 12387 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12388 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12389 udelay(200);
12390}
12391
12392static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12393 struct intel_shared_dpll *pll)
12394{
12395 struct drm_device *dev = dev_priv->dev;
12396 struct intel_crtc *crtc;
e7b903d2
DV		 12397
12398 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12399 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12400 if (intel_crtc_to_shared_dpll(crtc) == pll)
12401 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12402 }
12403
15bdd4cf
DV		 12404 I915_WRITE(PCH_DPLL(pll->id), 0);
12405 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12406 udelay(200);
12407}
12408
46edb027
DV		 12409static char *ibx_pch_dpll_names[] = {
12410 "PCH DPLL A",
12411 "PCH DPLL B",
12412};
12413
7c74ade1 12414static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12415{
e7b903d2 12416 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12417 int i;
12418
7c74ade1 12419 dev_priv->num_shared_dpll = 2;
ee7b9f93 12420
e72f9fbf 12421 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12422 dev_priv->shared_dplls[i].id = i;
12423 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12424 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12425 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12426 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12427 dev_priv->shared_dplls[i].get_hw_state =
12428 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12429 }
12430}
12431
7c74ade1
DV		 12432static void intel_shared_dpll_init(struct drm_device *dev)
12433{
e7b903d2 12434 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12435
9cd86933
DV		 12436 if (HAS_DDI(dev))
12437 intel_ddi_pll_init(dev);
12438 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12439 ibx_pch_dpll_init(dev);
12440 else
12441 dev_priv->num_shared_dpll = 0;
12442
12443 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12444}
12445
1fc0a8f7
TU		 12446/**
12447 * intel_wm_need_update - Check whether watermarks need updating
12448 * @plane: drm plane
12449 * @state: new plane state
12450 *
12451 * Check current plane state versus the new one to determine whether
12452 * watermarks need to be recalculated.
12453 *
12454 * Returns true or false.
12455 */
12456bool intel_wm_need_update(struct drm_plane *plane,
12457 struct drm_plane_state *state)
12458{
12459 /* Update watermarks on tiling changes. */
12460 if (!plane->state->fb || !state->fb ||
12461 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12462 plane->state->rotation != state->rotation)
12463 return true;
12464
12465 return false;
12466}
12467
6beb8c23
MR		 12468/**
12469 * intel_prepare_plane_fb - Prepare fb for usage on plane
12470 * @plane: drm plane to prepare for
12471 * @fb: framebuffer to prepare for presentation
12472 *
12473 * Prepares a framebuffer for usage on a display plane. Generally this
12474 * involves pinning the underlying object and updating the frontbuffer tracking
12475 * bits. Some older platforms need special physical address handling for
12476 * cursor planes.
12477 *
12478 * Returns 0 on success, negative error code on failure.
12479 */
12480int
12481intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12482 struct drm_framebuffer *fb,
12483 const struct drm_plane_state *new_state)
465c120c
MR		 12484{
12485 struct drm_device *dev = plane->dev;
6beb8c23
MR		 12486 struct intel_plane *intel_plane = to_intel_plane(plane);
12487 enum pipe pipe = intel_plane->pipe;
12488 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12489 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12490 unsigned frontbuffer_bits = 0;
12491 int ret = 0;
465c120c 12492
ea2c67bb 12493 if (!obj)
465c120c
MR		 12494 return 0;
12495
6beb8c23
MR		 12496 switch (plane->type) {
12497 case DRM_PLANE_TYPE_PRIMARY:
12498 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12499 break;
12500 case DRM_PLANE_TYPE_CURSOR:
12501 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12502 break;
12503 case DRM_PLANE_TYPE_OVERLAY:
12504 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12505 break;
12506 }
465c120c 12507
6beb8c23 12508 mutex_lock(&dev->struct_mutex);
465c120c 12509
6beb8c23
MR		 12510 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12511 INTEL_INFO(dev)->cursor_needs_physical) {
12512 int align = IS_I830(dev) ? 16 * 1024 : 256;
12513 ret = i915_gem_object_attach_phys(obj, align);
12514 if (ret)
12515 DRM_DEBUG_KMS("failed to attach phys object\n");
12516 } else {
82bc3b2d 12517 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 12518 }
465c120c 12519
6beb8c23
MR		 12520 if (ret == 0)
12521 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 12522
4c34574f 12523 mutex_unlock(&dev->struct_mutex);
465c120c 12524
6beb8c23
MR		 12525 return ret;
12526}
12527
38f3ce3a
MR		 12528/**
12529 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12530 * @plane: drm plane to clean up for
12531 * @fb: old framebuffer that was on plane
12532 *
12533 * Cleans up a framebuffer that has just been removed from a plane.
12534 */
12535void
12536intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12537 struct drm_framebuffer *fb,
12538 const struct drm_plane_state *old_state)
38f3ce3a
MR		 12539{
12540 struct drm_device *dev = plane->dev;
12541 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12542
12543 if (WARN_ON(!obj))
12544 return;
12545
12546 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12547 !INTEL_INFO(dev)->cursor_needs_physical) {
12548 mutex_lock(&dev->struct_mutex);
82bc3b2d 12549 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 12550 mutex_unlock(&dev->struct_mutex);
12551 }
465c120c
MR		 12552}
12553
12554static int
3c692a41
GP		 12555intel_check_primary_plane(struct drm_plane *plane,
12556 struct intel_plane_state *state)
12557{
32b7eeec
MR		 12558 struct drm_device *dev = plane->dev;
12559 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 12560 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12561 struct intel_crtc *intel_crtc;
2b875c22 12562 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 12563 struct drm_rect *dest = &state->dst;
12564 struct drm_rect *src = &state->src;
12565 const struct drm_rect *clip = &state->clip;
465c120c
MR		 12566 int ret;
12567
ea2c67bb
MR		 12568 crtc = crtc ? crtc : plane->crtc;
12569 intel_crtc = to_intel_crtc(crtc);
12570
c59cb179
MR		 12571 ret = drm_plane_helper_check_update(plane, crtc, fb,
12572 src, dest, clip,
12573 DRM_PLANE_HELPER_NO_SCALING,
12574 DRM_PLANE_HELPER_NO_SCALING,
12575 false, true, &state->visible);
12576 if (ret)
12577 return ret;
465c120c 12578
32b7eeec
MR		 12579 if (intel_crtc->active) {
12580 intel_crtc->atomic.wait_for_flips = true;
12581
12582 /*
12583 * FBC does not work on some platforms for rotated
12584 * planes, so disable it when rotation is not 0 and
12585 * update it when rotation is set back to 0.
12586 *
12587 * FIXME: This is redundant with the fbc update done in
12588 * the primary plane enable function except that that
12589 * one is done too late. We eventually need to unify
12590 * this.
12591 */
12592 if (intel_crtc->primary_enabled &&
12593 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 12594 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 12595 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 12596 intel_crtc->atomic.disable_fbc = true;
12597 }
12598
12599 if (state->visible) {
12600 /*
12601 * BDW signals flip done immediately if the plane
12602 * is disabled, even if the plane enable is already
12603 * armed to occur at the next vblank :(
12604 */
12605 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12606 intel_crtc->atomic.wait_vblank = true;
12607 }
12608
12609 intel_crtc->atomic.fb_bits |=
12610 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12611
12612 intel_crtc->atomic.update_fbc = true;
0fda6568 12613
1fc0a8f7 12614 if (intel_wm_need_update(plane, &state->base))
0fda6568 12615 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 12616 }
12617
14af293f
GP		 12618 return 0;
12619}
12620
12621static void
12622intel_commit_primary_plane(struct drm_plane *plane,
12623 struct intel_plane_state *state)
12624{
2b875c22
MR		 12625 struct drm_crtc *crtc = state->base.crtc;
12626 struct drm_framebuffer *fb = state->base.fb;
12627 struct drm_device *dev = plane->dev;
14af293f 12628 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 12629 struct intel_crtc *intel_crtc;
14af293f
GP		 12630 struct drm_rect *src = &state->src;
12631
ea2c67bb
MR		 12632 crtc = crtc ? crtc : plane->crtc;
12633 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 12634
12635 plane->fb = fb;
9dc806fc
MR		 12636 crtc->x = src->x1 >> 16;
12637 crtc->y = src->y1 >> 16;
ccc759dc 12638
ccc759dc 12639 if (intel_crtc->active) {
ccc759dc 12640 if (state->visible) {
ccc759dc
GP		 12641 /* FIXME: kill this fastboot hack */
12642 intel_update_pipe_size(intel_crtc);
465c120c 12643
ccc759dc 12644 intel_crtc->primary_enabled = true;
465c120c 12645
ccc759dc
GP		 12646 dev_priv->display.update_primary_plane(crtc, plane->fb,
12647 crtc->x, crtc->y);
ccc759dc
GP		 12648 } else {
12649 /*
12650 * If clipping results in a non-visible primary plane,
12651 * we'll disable the primary plane. Note that this is
12652 * a bit different than what happens if userspace
12653 * explicitly disables the plane by passing fb=0
12654 * because plane->fb still gets set and pinned.
12655 */
12656 intel_disable_primary_hw_plane(plane, crtc);
48404c1e 12657 }
ccc759dc 12658 }
465c120c
MR		 12659}
12660
32b7eeec 12661static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 12662{
32b7eeec 12663 struct drm_device *dev = crtc->dev;
140fd38d 12664 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 12665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 12666 struct intel_plane *intel_plane;
12667 struct drm_plane *p;
12668 unsigned fb_bits = 0;
12669
12670 /* Track fb's for any planes being disabled */
12671 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12672 intel_plane = to_intel_plane(p);
12673
12674 if (intel_crtc->atomic.disabled_planes &
12675 (1 << drm_plane_index(p))) {
12676 switch (p->type) {
12677 case DRM_PLANE_TYPE_PRIMARY:
12678 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12679 break;
12680 case DRM_PLANE_TYPE_CURSOR:
12681 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12682 break;
12683 case DRM_PLANE_TYPE_OVERLAY:
12684 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12685 break;
12686 }
3c692a41 12687
ea2c67bb
MR		 12688 mutex_lock(&dev->struct_mutex);
12689 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12690 mutex_unlock(&dev->struct_mutex);
12691 }
12692 }
3c692a41 12693
32b7eeec
MR		 12694 if (intel_crtc->atomic.wait_for_flips)
12695 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 12696
32b7eeec
MR		 12697 if (intel_crtc->atomic.disable_fbc)
12698 intel_fbc_disable(dev);
3c692a41 12699
32b7eeec
MR		 12700 if (intel_crtc->atomic.pre_disable_primary)
12701 intel_pre_disable_primary(crtc);
3c692a41 12702
32b7eeec
MR		 12703 if (intel_crtc->atomic.update_wm)
12704 intel_update_watermarks(crtc);
3c692a41 12705
32b7eeec 12706 intel_runtime_pm_get(dev_priv);
3c692a41 12707
c34c9ee4
MR		 12708 /* Perform vblank evasion around commit operation */
12709 if (intel_crtc->active)
12710 intel_crtc->atomic.evade =
12711 intel_pipe_update_start(intel_crtc,
12712 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 12713}
12714
12715static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12716{
12717 struct drm_device *dev = crtc->dev;
12718 struct drm_i915_private *dev_priv = dev->dev_private;
12719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12720 struct drm_plane *p;
12721
c34c9ee4
MR		 12722 if (intel_crtc->atomic.evade)
12723 intel_pipe_update_end(intel_crtc,
12724 intel_crtc->atomic.start_vbl_count);
3c692a41 12725
140fd38d 12726 intel_runtime_pm_put(dev_priv);
3c692a41 12727
32b7eeec
MR		 12728 if (intel_crtc->atomic.wait_vblank)
12729 intel_wait_for_vblank(dev, intel_crtc->pipe);
12730
12731 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12732
12733 if (intel_crtc->atomic.update_fbc) {
ccc759dc 12734 mutex_lock(&dev->struct_mutex);
7ff0ebcc 12735 intel_fbc_update(dev);
ccc759dc 12736 mutex_unlock(&dev->struct_mutex);
38f3ce3a 12737 }
3c692a41 12738
32b7eeec
MR		 12739 if (intel_crtc->atomic.post_enable_primary)
12740 intel_post_enable_primary(crtc);
3c692a41 12741
32b7eeec
MR		 12742 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12743 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12744 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12745 false, false);
12746
12747 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 12748}
12749
cf4c7c12 12750/**
4a3b8769
MR		 12751 * intel_plane_destroy - destroy a plane
12752 * @plane: plane to destroy
cf4c7c12 12753 *
4a3b8769
MR		 12754 * Common destruction function for all types of planes (primary, cursor,
12755 * sprite).
cf4c7c12 12756 */
4a3b8769 12757void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 12758{
12759 struct intel_plane *intel_plane = to_intel_plane(plane);
12760 drm_plane_cleanup(plane);
12761 kfree(intel_plane);
12762}
12763
65a3fea0 12764const struct drm_plane_funcs intel_plane_funcs = {
ff42e093
DV		 12765 .update_plane = drm_plane_helper_update,
12766 .disable_plane = drm_plane_helper_disable,
3d7d6510 12767 .destroy = intel_plane_destroy,
c196e1d6 12768 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 12769 .atomic_get_property = intel_plane_atomic_get_property,
12770 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 12771 .atomic_duplicate_state = intel_plane_duplicate_state,
12772 .atomic_destroy_state = intel_plane_destroy_state,
12773
465c120c
MR		 12774};
12775
12776static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12777 int pipe)
12778{
12779 struct intel_plane *primary;
8e7d688b 12780 struct intel_plane_state *state;
465c120c
MR		 12781 const uint32_t *intel_primary_formats;
12782 int num_formats;
12783
12784 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12785 if (primary == NULL)
12786 return NULL;
12787
8e7d688b
MR		 12788 state = intel_create_plane_state(&primary->base);
12789 if (!state) {
ea2c67bb
MR		 12790 kfree(primary);
12791 return NULL;
12792 }
8e7d688b 12793 primary->base.state = &state->base;
ea2c67bb 12794
465c120c
MR		 12795 primary->can_scale = false;
12796 primary->max_downscale = 1;
12797 primary->pipe = pipe;
12798 primary->plane = pipe;
c59cb179
MR		 12799 primary->check_plane = intel_check_primary_plane;
12800 primary->commit_plane = intel_commit_primary_plane;
465c120c
MR		 12801 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12802 primary->plane = !pipe;
12803
12804 if (INTEL_INFO(dev)->gen <= 3) {
12805 intel_primary_formats = intel_primary_formats_gen2;
12806 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12807 } else {
12808 intel_primary_formats = intel_primary_formats_gen4;
12809 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12810 }
12811
12812 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 12813 &intel_plane_funcs,
465c120c
MR		 12814 intel_primary_formats, num_formats,
12815 DRM_PLANE_TYPE_PRIMARY);
48404c1e
SJ		 12816
12817 if (INTEL_INFO(dev)->gen >= 4) {
12818 if (!dev->mode_config.rotation_property)
12819 dev->mode_config.rotation_property =
12820 drm_mode_create_rotation_property(dev,
12821 BIT(DRM_ROTATE_0) |
12822 BIT(DRM_ROTATE_180));
12823 if (dev->mode_config.rotation_property)
12824 drm_object_attach_property(&primary->base.base,
12825 dev->mode_config.rotation_property,
8e7d688b 12826 state->base.rotation);
48404c1e
SJ		 12827 }
12828
ea2c67bb
MR		 12829 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12830
465c120c
MR		 12831 return &primary->base;
12832}
12833
3d7d6510 12834static int
852e787c
GP		 12835intel_check_cursor_plane(struct drm_plane *plane,
12836 struct intel_plane_state *state)
3d7d6510 12837{
2b875c22 12838 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12839 struct drm_device *dev = plane->dev;
2b875c22 12840 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 12841 struct drm_rect *dest = &state->dst;
12842 struct drm_rect *src = &state->src;
12843 const struct drm_rect *clip = &state->clip;
757f9a3e 12844 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 12845 struct intel_crtc *intel_crtc;
757f9a3e
GP		 12846 unsigned stride;
12847 int ret;
3d7d6510 12848
ea2c67bb
MR		 12849 crtc = crtc ? crtc : plane->crtc;
12850 intel_crtc = to_intel_crtc(crtc);
12851
757f9a3e 12852 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 12853 src, dest, clip,
3d7d6510
MR		 12854 DRM_PLANE_HELPER_NO_SCALING,
12855 DRM_PLANE_HELPER_NO_SCALING,
852e787c 12856 true, true, &state->visible);
757f9a3e
GP		 12857 if (ret)
12858 return ret;
12859
12860
12861 /* if we want to turn off the cursor ignore width and height */
12862 if (!obj)
32b7eeec 12863 goto finish;
757f9a3e 12864
757f9a3e 12865 /* Check for which cursor types we support */
ea2c67bb
MR		 12866 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12867 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12868 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 12869 return -EINVAL;
12870 }
12871
ea2c67bb
MR		 12872 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12873 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 12874 DRM_DEBUG_KMS("buffer is too small\n");
12875 return -ENOMEM;
12876 }
12877
3a656b54 12878 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 12879 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12880 ret = -EINVAL;
12881 }
757f9a3e 12882
32b7eeec
MR		 12883finish:
12884 if (intel_crtc->active) {
3749f463 12885 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 12886 intel_crtc->atomic.update_wm = true;
12887
12888 intel_crtc->atomic.fb_bits |=
12889 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12890 }
12891
757f9a3e 12892 return ret;
852e787c 12893}
3d7d6510 12894
f4a2cf29 12895static void
852e787c
GP		 12896intel_commit_cursor_plane(struct drm_plane *plane,
12897 struct intel_plane_state *state)
12898{
2b875c22 12899 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 12900 struct drm_device *dev = plane->dev;
12901 struct intel_crtc *intel_crtc;
2b875c22 12902 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 12903 uint32_t addr;
852e787c 12904
ea2c67bb
MR		 12905 crtc = crtc ? crtc : plane->crtc;
12906 intel_crtc = to_intel_crtc(crtc);
12907
2b875c22 12908 plane->fb = state->base.fb;
ea2c67bb
MR		 12909 crtc->cursor_x = state->base.crtc_x;
12910 crtc->cursor_y = state->base.crtc_y;
12911
a912f12f
GP		 12912 if (intel_crtc->cursor_bo == obj)
12913 goto update;
4ed91096 12914
f4a2cf29 12915 if (!obj)
a912f12f 12916 addr = 0;
f4a2cf29 12917 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 12918 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 12919 else
a912f12f 12920 addr = obj->phys_handle->busaddr;
852e787c 12921
a912f12f
GP		 12922 intel_crtc->cursor_addr = addr;
12923 intel_crtc->cursor_bo = obj;
12924update:
852e787c 12925
32b7eeec 12926 if (intel_crtc->active)
a912f12f 12927 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 12928}
12929
3d7d6510
MR		 12930static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12931 int pipe)
12932{
12933 struct intel_plane *cursor;
8e7d688b 12934 struct intel_plane_state *state;
3d7d6510
MR		 12935
12936 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12937 if (cursor == NULL)
12938 return NULL;
12939
8e7d688b
MR		 12940 state = intel_create_plane_state(&cursor->base);
12941 if (!state) {
ea2c67bb
MR		 12942 kfree(cursor);
12943 return NULL;
12944 }
8e7d688b 12945 cursor->base.state = &state->base;
ea2c67bb 12946
3d7d6510
MR		 12947 cursor->can_scale = false;
12948 cursor->max_downscale = 1;
12949 cursor->pipe = pipe;
12950 cursor->plane = pipe;
c59cb179
MR		 12951 cursor->check_plane = intel_check_cursor_plane;
12952 cursor->commit_plane = intel_commit_cursor_plane;
3d7d6510
MR		 12953
12954 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 12955 &intel_plane_funcs,
3d7d6510
MR		 12956 intel_cursor_formats,
12957 ARRAY_SIZE(intel_cursor_formats),
12958 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 12959
12960 if (INTEL_INFO(dev)->gen >= 4) {
12961 if (!dev->mode_config.rotation_property)
12962 dev->mode_config.rotation_property =
12963 drm_mode_create_rotation_property(dev,
12964 BIT(DRM_ROTATE_0) |
12965 BIT(DRM_ROTATE_180));
12966 if (dev->mode_config.rotation_property)
12967 drm_object_attach_property(&cursor->base.base,
12968 dev->mode_config.rotation_property,
8e7d688b 12969 state->base.rotation);
4398ad45
VS		 12970 }
12971
ea2c67bb
MR		 12972 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12973
3d7d6510
MR		 12974 return &cursor->base;
12975}
12976
b358d0a6 12977static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 12978{
fbee40df 12979 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 12980 struct intel_crtc *intel_crtc;
f5de6e07 12981 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 12982 struct drm_plane *primary = NULL;
12983 struct drm_plane *cursor = NULL;
465c120c 12984 int i, ret;
79e53945 12985
955382f3 12986 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 12987 if (intel_crtc == NULL)
12988 return;
12989
f5de6e07
ACO		 12990 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12991 if (!crtc_state)
12992 goto fail;
12993 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 12994 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 12995
465c120c 12996 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 12997 if (!primary)
12998 goto fail;
12999
13000 cursor = intel_cursor_plane_create(dev, pipe);
13001 if (!cursor)
13002 goto fail;
13003
465c120c 13004 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13005 cursor, &intel_crtc_funcs);
13006 if (ret)
13007 goto fail;
79e53945
JB		 13008
13009 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13010 for (i = 0; i < 256; i++) {
13011 intel_crtc->lut_r[i] = i;
13012 intel_crtc->lut_g[i] = i;
13013 intel_crtc->lut_b[i] = i;
13014 }
13015
1f1c2e24
VS		 13016 /*
13017 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13018 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13019 */
80824003
JB		 13020 intel_crtc->pipe = pipe;
13021 intel_crtc->plane = pipe;
3a77c4c4 13022 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13023 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13024 intel_crtc->plane = !pipe;
80824003
JB		 13025 }
13026
4b0e333e
CW		 13027 intel_crtc->cursor_base = ~0;
13028 intel_crtc->cursor_cntl = ~0;
dc41c154 13029 intel_crtc->cursor_size = ~0;
8d7849db 13030
22fd0fab
JB		 13031 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13032 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13033 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13034 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13035
9362c7c5
ACO		 13036 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13037
79e53945 13038 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13039
13040 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13041 return;
13042
13043fail:
13044 if (primary)
13045 drm_plane_cleanup(primary);
13046 if (cursor)
13047 drm_plane_cleanup(cursor);
f5de6e07 13048 kfree(crtc_state);
3d7d6510 13049 kfree(intel_crtc);
79e53945
JB		 13050}
13051
752aa88a
JB		 13052enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13053{
13054 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13055 struct drm_device *dev = connector->base.dev;
752aa88a 13056
51fd371b 13057 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13058
d3babd3f 13059 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13060 return INVALID_PIPE;
13061
13062 return to_intel_crtc(encoder->crtc)->pipe;
13063}
13064
08d7b3d1 13065int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13066 struct drm_file *file)
08d7b3d1 13067{
08d7b3d1 13068 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13069 struct drm_crtc *drmmode_crtc;
c05422d5 13070 struct intel_crtc *crtc;
08d7b3d1 13071
7707e653 13072 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13073
7707e653 13074 if (!drmmode_crtc) {
08d7b3d1 13075 DRM_ERROR("no such CRTC id\n");
3f2c2057 13076 return -ENOENT;
08d7b3d1
CW		 13077 }
13078
7707e653 13079 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13080 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13081
c05422d5 13082 return 0;
08d7b3d1
CW		 13083}
13084
66a9278e 13085static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13086{
66a9278e
DV		 13087 struct drm_device *dev = encoder->base.dev;
13088 struct intel_encoder *source_encoder;
79e53945 13089 int index_mask = 0;
79e53945
JB		 13090 int entry = 0;
13091
b2784e15 13092 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13093 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13094 index_mask |= (1 << entry);
13095
79e53945
JB		 13096 entry++;
13097 }
4ef69c7a 13098
79e53945
JB		 13099 return index_mask;
13100}
13101
4d302442
CW		 13102static bool has_edp_a(struct drm_device *dev)
13103{
13104 struct drm_i915_private *dev_priv = dev->dev_private;
13105
13106 if (!IS_MOBILE(dev))
13107 return false;
13108
13109 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13110 return false;
13111
e3589908 13112 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13113 return false;
13114
13115 return true;
13116}
13117
84b4e042
JB		 13118static bool intel_crt_present(struct drm_device *dev)
13119{
13120 struct drm_i915_private *dev_priv = dev->dev_private;
13121
884497ed
DL		 13122 if (INTEL_INFO(dev)->gen >= 9)
13123 return false;
13124
cf404ce4 13125 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13126 return false;
13127
13128 if (IS_CHERRYVIEW(dev))
13129 return false;
13130
13131 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13132 return false;
13133
13134 return true;
13135}
13136
79e53945
JB		 13137static void intel_setup_outputs(struct drm_device *dev)
13138{
725e30ad 13139 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13140 struct intel_encoder *encoder;
c6f95f27 13141 struct drm_connector *connector;
cb0953d7 13142 bool dpd_is_edp = false;
79e53945 13143
c9093354 13144 intel_lvds_init(dev);
79e53945 13145
84b4e042 13146 if (intel_crt_present(dev))
79935fca 13147 intel_crt_init(dev);
cb0953d7 13148
affa9354 13149 if (HAS_DDI(dev)) {
0e72a5b5
ED		 13150 int found;
13151
de31facd
JB		 13152 /*
13153 * Haswell uses DDI functions to detect digital outputs.
13154 * On SKL pre-D0 the strap isn't connected, so we assume
13155 * it's there.
13156 */
0e72a5b5 13157 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13158 /* WaIgnoreDDIAStrap: skl */
13159 if (found ||
13160 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13161 intel_ddi_init(dev, PORT_A);
13162
13163 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13164 * register */
13165 found = I915_READ(SFUSE_STRAP);
13166
13167 if (found & SFUSE_STRAP_DDIB_DETECTED)
13168 intel_ddi_init(dev, PORT_B);
13169 if (found & SFUSE_STRAP_DDIC_DETECTED)
13170 intel_ddi_init(dev, PORT_C);
13171 if (found & SFUSE_STRAP_DDID_DETECTED)
13172 intel_ddi_init(dev, PORT_D);
13173 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13174 int found;
5d8a7752 13175 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13176
13177 if (has_edp_a(dev))
13178 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13179
dc0fa718 13180 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13181 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13182 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13183 if (!found)
e2debe91 13184 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13185 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13186 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13187 }
13188
dc0fa718 13189 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13190 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13191
dc0fa718 13192 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13193 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13194
5eb08b69 13195 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13196 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13197
270b3042 13198 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13199 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13200 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13201 /*
13202 * The DP_DETECTED bit is the latched state of the DDC
13203 * SDA pin at boot. However since eDP doesn't require DDC
13204 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13205 * eDP ports may have been muxed to an alternate function.
13206 * Thus we can't rely on the DP_DETECTED bit alone to detect
13207 * eDP ports. Consult the VBT as well as DP_DETECTED to
13208 * detect eDP ports.
13209 */
d2182a66
VS		 13210 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13211 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13212 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13213 PORT_B);
e17ac6db
VS		 13214 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13215 intel_dp_is_edp(dev, PORT_B))
13216 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13217
d2182a66
VS		 13218 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13219 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13220 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13221 PORT_C);
e17ac6db
VS		 13222 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13223 intel_dp_is_edp(dev, PORT_C))
13224 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13225
9418c1f1 13226 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13227 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13228 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13229 PORT_D);
e17ac6db
VS		 13230 /* eDP not supported on port D, so don't check VBT */
13231 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13232 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13233 }
13234
3cfca973 13235 intel_dsi_init(dev);
103a196f 13236 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13237 bool found = false;
7d57382e 13238
e2debe91 13239 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13240 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13241 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13242 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13243 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13244 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13245 }
27185ae1 13246
e7281eab 13247 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13248 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13249 }
13520b05
KH		 13250
13251 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13252
e2debe91 13253 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13254 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13255 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13256 }
27185ae1 13257
e2debe91 13258 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13259
b01f2c3a
JB		 13260 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13261 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13262 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13263 }
e7281eab 13264 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13265 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13266 }
27185ae1 13267
b01f2c3a 13268 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13269 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13270 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13271 } else if (IS_GEN2(dev))
79e53945
JB		 13272 intel_dvo_init(dev);
13273
103a196f 13274 if (SUPPORTS_TV(dev))
79e53945
JB		 13275 intel_tv_init(dev);
13276
c6f95f27
MR		 13277 /*
13278 * FIXME: We don't have full atomic support yet, but we want to be
13279 * able to enable/test plane updates via the atomic interface in the
13280 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
13281 * will take some atomic codepaths to lookup properties during
13282 * drmModeGetConnector() that unconditionally dereference
13283 * connector->state.
13284 *
13285 * We create a dummy connector state here for each connector to ensure
13286 * the DRM core doesn't try to dereference a NULL connector->state.
13287 * The actual connector properties will never be updated or contain
13288 * useful information, but since we're doing this specifically for
13289 * testing/debug of the plane operations (and only when a specific
13290 * kernel module option is given), that shouldn't really matter.
13291 *
d29b2f9d
ACO		 13292 * We are also relying on these states to convert the legacy mode set
13293 * to use a drm_atomic_state struct. The states are kept consistent
13294 * with actual state, so that it is safe to rely on that instead of
13295 * the staged config.
13296 *
c6f95f27
MR		 13297 * Once atomic support for crtc's + connectors lands, this loop should
13298 * be removed since we'll be setting up real connector state, which
13299 * will contain Intel-specific properties.
13300 */
d29b2f9d
ACO		 13301 list_for_each_entry(connector,
13302 &dev->mode_config.connector_list,
13303 head) {
13304 if (!WARN_ON(connector->state)) {
13305 connector->state = kzalloc(sizeof(*connector->state),
13306 GFP_KERNEL);
c6f95f27
MR		 13307 }
13308 }
13309
0bc12bcb 13310 intel_psr_init(dev);
7c8f8a70 13311
b2784e15 13312 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13313 encoder->base.possible_crtcs = encoder->crtc_mask;
13314 encoder->base.possible_clones =
66a9278e 13315 intel_encoder_clones(encoder);
79e53945 13316 }
47356eb6 13317
dde86e2d 13318 intel_init_pch_refclk(dev);
270b3042
DV		 13319
13320 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13321}
13322
13323static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13324{
60a5ca01 13325 struct drm_device *dev = fb->dev;
79e53945 13326 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13327
ef2d633e 13328 drm_framebuffer_cleanup(fb);
60a5ca01 13329 mutex_lock(&dev->struct_mutex);
ef2d633e 13330 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13331 drm_gem_object_unreference(&intel_fb->obj->base);
13332 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13333 kfree(intel_fb);
13334}
13335
13336static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13337 struct drm_file *file,
79e53945
JB		 13338 unsigned int *handle)
13339{
13340 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13341 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13342
05394f39 13343 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13344}
13345
13346static const struct drm_framebuffer_funcs intel_fb_funcs = {
13347 .destroy = intel_user_framebuffer_destroy,
13348 .create_handle = intel_user_framebuffer_create_handle,
13349};
13350
b321803d
DL		 13351static
13352u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13353 uint32_t pixel_format)
13354{
13355 u32 gen = INTEL_INFO(dev)->gen;
13356
13357 if (gen >= 9) {
13358 /* "The stride in bytes must not exceed the of the size of 8K
13359 * pixels and 32K bytes."
13360 */
13361 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13362 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13363 return 32*1024;
13364 } else if (gen >= 4) {
13365 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13366 return 16*1024;
13367 else
13368 return 32*1024;
13369 } else if (gen >= 3) {
13370 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13371 return 8*1024;
13372 else
13373 return 16*1024;
13374 } else {
13375 /* XXX DSPC is limited to 4k tiled */
13376 return 8*1024;
13377 }
13378}
13379
b5ea642a
DV		 13380static int intel_framebuffer_init(struct drm_device *dev,
13381 struct intel_framebuffer *intel_fb,
13382 struct drm_mode_fb_cmd2 *mode_cmd,
13383 struct drm_i915_gem_object *obj)
79e53945 13384{
6761dd31 13385 unsigned int aligned_height;
79e53945 13386 int ret;
b321803d 13387 u32 pitch_limit, stride_alignment;
79e53945 13388
dd4916c5
DV		 13389 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13390
2a80eada
DV		 13391 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13392 /* Enforce that fb modifier and tiling mode match, but only for
13393 * X-tiled. This is needed for FBC. */
13394 if (!!(obj->tiling_mode == I915_TILING_X) !=
13395 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13396 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13397 return -EINVAL;
13398 }
13399 } else {
13400 if (obj->tiling_mode == I915_TILING_X)
13401 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13402 else if (obj->tiling_mode == I915_TILING_Y) {
13403 DRM_DEBUG("No Y tiling for legacy addfb\n");
13404 return -EINVAL;
13405 }
13406 }
13407
9a8f0a12
TU		 13408 /* Passed in modifier sanity checking. */
13409 switch (mode_cmd->modifier[0]) {
13410 case I915_FORMAT_MOD_Y_TILED:
13411 case I915_FORMAT_MOD_Yf_TILED:
13412 if (INTEL_INFO(dev)->gen < 9) {
13413 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13414 mode_cmd->modifier[0]);
13415 return -EINVAL;
13416 }
13417 case DRM_FORMAT_MOD_NONE:
13418 case I915_FORMAT_MOD_X_TILED:
13419 break;
13420 default:
c0f40428
JB		 13421 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13422 mode_cmd->modifier[0]);
57cd6508 13423 return -EINVAL;
c16ed4be 13424 }
57cd6508 13425
b321803d
DL		 13426 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13427 mode_cmd->pixel_format);
13428 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13429 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13430 mode_cmd->pitches[0], stride_alignment);
57cd6508 13431 return -EINVAL;
c16ed4be 13432 }
57cd6508 13433
b321803d
DL		 13434 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13435 mode_cmd->pixel_format);
a35cdaa0 13436 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13437 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13438 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13439 "tiled" : "linear",
a35cdaa0 13440 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13441 return -EINVAL;
c16ed4be 13442 }
5d7bd705 13443
2a80eada 13444 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13445 mode_cmd->pitches[0] != obj->stride) {
13446 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13447 mode_cmd->pitches[0], obj->stride);
5d7bd705 13448 return -EINVAL;
c16ed4be 13449 }
5d7bd705 13450
57779d06 13451 /* Reject formats not supported by any plane early. */
308e5bcb 13452 switch (mode_cmd->pixel_format) {
57779d06 13453 case DRM_FORMAT_C8:
04b3924d
VS		 13454 case DRM_FORMAT_RGB565:
13455 case DRM_FORMAT_XRGB8888:
13456 case DRM_FORMAT_ARGB8888:
57779d06
VS		 13457 break;
13458 case DRM_FORMAT_XRGB1555:
13459 case DRM_FORMAT_ARGB1555:
c16ed4be 13460 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 13461 DRM_DEBUG("unsupported pixel format: %s\n",
13462 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13463 return -EINVAL;
c16ed4be 13464 }
57779d06
VS		 13465 break;
13466 case DRM_FORMAT_XBGR8888:
13467 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 13468 case DRM_FORMAT_XRGB2101010:
13469 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 13470 case DRM_FORMAT_XBGR2101010:
13471 case DRM_FORMAT_ABGR2101010:
c16ed4be 13472 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 13473 DRM_DEBUG("unsupported pixel format: %s\n",
13474 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13475 return -EINVAL;
c16ed4be 13476 }
b5626747 13477 break;
04b3924d
VS		 13478 case DRM_FORMAT_YUYV:
13479 case DRM_FORMAT_UYVY:
13480 case DRM_FORMAT_YVYU:
13481 case DRM_FORMAT_VYUY:
c16ed4be 13482 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 13483 DRM_DEBUG("unsupported pixel format: %s\n",
13484 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13485 return -EINVAL;
c16ed4be 13486 }
57cd6508
CW		 13487 break;
13488 default:
4ee62c76
VS		 13489 DRM_DEBUG("unsupported pixel format: %s\n",
13490 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 13491 return -EINVAL;
13492 }
13493
90f9a336
VS		 13494 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13495 if (mode_cmd->offsets[0] != 0)
13496 return -EINVAL;
13497
ec2c981e 13498 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 13499 mode_cmd->pixel_format,
13500 mode_cmd->modifier[0]);
53155c0a
DV		 13501 /* FIXME drm helper for size checks (especially planar formats)? */
13502 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13503 return -EINVAL;
13504
c7d73f6a
DV		 13505 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13506 intel_fb->obj = obj;
80075d49 13507 intel_fb->obj->framebuffer_references++;
c7d73f6a 13508
79e53945
JB		 13509 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13510 if (ret) {
13511 DRM_ERROR("framebuffer init failed %d\n", ret);
13512 return ret;
13513 }
13514
79e53945
JB		 13515 return 0;
13516}
13517
79e53945
JB		 13518static struct drm_framebuffer *
13519intel_user_framebuffer_create(struct drm_device *dev,
13520 struct drm_file *filp,
308e5bcb 13521 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 13522{
05394f39 13523 struct drm_i915_gem_object *obj;
79e53945 13524
308e5bcb
JB		 13525 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13526 mode_cmd->handles[0]));
c8725226 13527 if (&obj->base == NULL)
cce13ff7 13528 return ERR_PTR(-ENOENT);
79e53945 13529
d2dff872 13530 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 13531}
13532
4520f53a 13533#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 13534static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 13535{
13536}
13537#endif
13538
79e53945 13539static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 13540 .fb_create = intel_user_framebuffer_create,
0632fef6 13541 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 13542 .atomic_check = intel_atomic_check,
13543 .atomic_commit = intel_atomic_commit,
79e53945
JB		 13544};
13545
e70236a8
JB		 13546/* Set up chip specific display functions */
13547static void intel_init_display(struct drm_device *dev)
13548{
13549 struct drm_i915_private *dev_priv = dev->dev_private;
13550
ee9300bb
DV		 13551 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13552 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 13553 else if (IS_CHERRYVIEW(dev))
13554 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 13555 else if (IS_VALLEYVIEW(dev))
13556 dev_priv->display.find_dpll = vlv_find_best_dpll;
13557 else if (IS_PINEVIEW(dev))
13558 dev_priv->display.find_dpll = pnv_find_best_dpll;
13559 else
13560 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13561
bc8d7dff
DL		 13562 if (INTEL_INFO(dev)->gen >= 9) {
13563 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13564 dev_priv->display.get_initial_plane_config =
13565 skylake_get_initial_plane_config;
bc8d7dff
DL		 13566 dev_priv->display.crtc_compute_clock =
13567 haswell_crtc_compute_clock;
13568 dev_priv->display.crtc_enable = haswell_crtc_enable;
13569 dev_priv->display.crtc_disable = haswell_crtc_disable;
13570 dev_priv->display.off = ironlake_crtc_off;
13571 dev_priv->display.update_primary_plane =
13572 skylake_update_primary_plane;
13573 } else if (HAS_DDI(dev)) {
0e8ffe1b 13574 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13575 dev_priv->display.get_initial_plane_config =
13576 ironlake_get_initial_plane_config;
797d0259
ACO		 13577 dev_priv->display.crtc_compute_clock =
13578 haswell_crtc_compute_clock;
4f771f10
PZ		 13579 dev_priv->display.crtc_enable = haswell_crtc_enable;
13580 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 13581 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 13582 dev_priv->display.update_primary_plane =
13583 ironlake_update_primary_plane;
09b4ddf9 13584 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 13585 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 13586 dev_priv->display.get_initial_plane_config =
13587 ironlake_get_initial_plane_config;
3fb37703
ACO		 13588 dev_priv->display.crtc_compute_clock =
13589 ironlake_crtc_compute_clock;
76e5a89c
DV		 13590 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13591 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 13592 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 13593 dev_priv->display.update_primary_plane =
13594 ironlake_update_primary_plane;
89b667f8
JB		 13595 } else if (IS_VALLEYVIEW(dev)) {
13596 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13597 dev_priv->display.get_initial_plane_config =
13598 i9xx_get_initial_plane_config;
d6dfee7a 13599 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 13600 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13601 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13602 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13603 dev_priv->display.update_primary_plane =
13604 i9xx_update_primary_plane;
f564048e 13605 } else {
0e8ffe1b 13606 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13607 dev_priv->display.get_initial_plane_config =
13608 i9xx_get_initial_plane_config;
d6dfee7a 13609 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 13610 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13611 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 13612 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13613 dev_priv->display.update_primary_plane =
13614 i9xx_update_primary_plane;
f564048e 13615 }
e70236a8 13616
e70236a8 13617 /* Returns the core display clock speed */
1652d19e
VS		 13618 if (IS_SKYLAKE(dev))
13619 dev_priv->display.get_display_clock_speed =
13620 skylake_get_display_clock_speed;
13621 else if (IS_BROADWELL(dev))
13622 dev_priv->display.get_display_clock_speed =
13623 broadwell_get_display_clock_speed;
13624 else if (IS_HASWELL(dev))
13625 dev_priv->display.get_display_clock_speed =
13626 haswell_get_display_clock_speed;
13627 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 13628 dev_priv->display.get_display_clock_speed =
13629 valleyview_get_display_clock_speed;
b37a6434
VS		 13630 else if (IS_GEN5(dev))
13631 dev_priv->display.get_display_clock_speed =
13632 ilk_get_display_clock_speed;
a7c66cd8
VS		 13633 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
13634 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 13635 dev_priv->display.get_display_clock_speed =
13636 i945_get_display_clock_speed;
13637 else if (IS_I915G(dev))
13638 dev_priv->display.get_display_clock_speed =
13639 i915_get_display_clock_speed;
257a7ffc 13640 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 13641 dev_priv->display.get_display_clock_speed =
13642 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 13643 else if (IS_PINEVIEW(dev))
13644 dev_priv->display.get_display_clock_speed =
13645 pnv_get_display_clock_speed;
e70236a8
JB		 13646 else if (IS_I915GM(dev))
13647 dev_priv->display.get_display_clock_speed =
13648 i915gm_get_display_clock_speed;
13649 else if (IS_I865G(dev))
13650 dev_priv->display.get_display_clock_speed =
13651 i865_get_display_clock_speed;
f0f8a9ce 13652 else if (IS_I85X(dev))
e70236a8
JB		 13653 dev_priv->display.get_display_clock_speed =
13654 i855_get_display_clock_speed;
13655 else /* 852, 830 */
13656 dev_priv->display.get_display_clock_speed =
13657 i830_get_display_clock_speed;
13658
7c10a2b5 13659 if (IS_GEN5(dev)) {
3bb11b53 13660 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 13661 } else if (IS_GEN6(dev)) {
13662 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 13663 } else if (IS_IVYBRIDGE(dev)) {
13664 /* FIXME: detect B0+ stepping and use auto training */
13665 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 13666 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 13667 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 13668 } else if (IS_VALLEYVIEW(dev)) {
13669 dev_priv->display.modeset_global_resources =
13670 valleyview_modeset_global_resources;
e70236a8 13671 }
8c9f3aaf 13672
8c9f3aaf
JB		 13673 switch (INTEL_INFO(dev)->gen) {
13674 case 2:
13675 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13676 break;
13677
13678 case 3:
13679 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13680 break;
13681
13682 case 4:
13683 case 5:
13684 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13685 break;
13686
13687 case 6:
13688 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13689 break;
7c9017e5 13690 case 7:
4e0bbc31 13691 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 13692 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13693 break;
830c81db 13694 case 9:
ba343e02
TU		 13695 /* Drop through - unsupported since execlist only. */
13696 default:
13697 /* Default just returns -ENODEV to indicate unsupported */
13698 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 13699 }
7bd688cd
JN		 13700
13701 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 13702
13703 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 13704}
13705
b690e96c
JB		 13706/*
13707 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13708 * resume, or other times. This quirk makes sure that's the case for
13709 * affected systems.
13710 */
0206e353 13711static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 13712{
13713 struct drm_i915_private *dev_priv = dev->dev_private;
13714
13715 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 13716 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 13717}
13718
b6b5d049
VS		 13719static void quirk_pipeb_force(struct drm_device *dev)
13720{
13721 struct drm_i915_private *dev_priv = dev->dev_private;
13722
13723 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13724 DRM_INFO("applying pipe b force quirk\n");
13725}
13726
435793df
KP		 13727/*
13728 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13729 */
13730static void quirk_ssc_force_disable(struct drm_device *dev)
13731{
13732 struct drm_i915_private *dev_priv = dev->dev_private;
13733 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 13734 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 13735}
13736
4dca20ef 13737/*
5a15ab5b
CE		 13738 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13739 * brightness value
4dca20ef
CE		 13740 */
13741static void quirk_invert_brightness(struct drm_device *dev)
13742{
13743 struct drm_i915_private *dev_priv = dev->dev_private;
13744 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 13745 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 13746}
13747
9c72cc6f
SD		 13748/* Some VBT's incorrectly indicate no backlight is present */
13749static void quirk_backlight_present(struct drm_device *dev)
13750{
13751 struct drm_i915_private *dev_priv = dev->dev_private;
13752 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13753 DRM_INFO("applying backlight present quirk\n");
13754}
13755
b690e96c
JB		 13756struct intel_quirk {
13757 int device;
13758 int subsystem_vendor;
13759 int subsystem_device;
13760 void (*hook)(struct drm_device *dev);
13761};
13762
5f85f176
EE		 13763/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13764struct intel_dmi_quirk {
13765 void (*hook)(struct drm_device *dev);
13766 const struct dmi_system_id (*dmi_id_list)[];
13767};
13768
13769static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13770{
13771 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13772 return 1;
13773}
13774
13775static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13776 {
13777 .dmi_id_list = &(const struct dmi_system_id[]) {
13778 {
13779 .callback = intel_dmi_reverse_brightness,
13780 .ident = "NCR Corporation",
13781 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13782 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13783 },
13784 },
13785 { } /* terminating entry */
13786 },
13787 .hook = quirk_invert_brightness,
13788 },
13789};
13790
c43b5634 13791static struct intel_quirk intel_quirks[] = {
b690e96c 13792 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 13793 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 13794
b690e96c
JB		 13795 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13796 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13797
b690e96c
JB		 13798 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13799 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13800
5f080c0f
VS		 13801 /* 830 needs to leave pipe A & dpll A up */
13802 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13803
b6b5d049
VS		 13804 /* 830 needs to leave pipe B & dpll B up */
13805 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13806
435793df
KP		 13807 /* Lenovo U160 cannot use SSC on LVDS */
13808 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 13809
13810 /* Sony Vaio Y cannot use SSC on LVDS */
13811 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 13812
be505f64
AH		 13813 /* Acer Aspire 5734Z must invert backlight brightness */
13814 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13815
13816 /* Acer/eMachines G725 */
13817 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13818
13819 /* Acer/eMachines e725 */
13820 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13821
13822 /* Acer/Packard Bell NCL20 */
13823 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13824
13825 /* Acer Aspire 4736Z */
13826 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 13827
13828 /* Acer Aspire 5336 */
13829 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 13830
13831 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13832 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 13833
dfb3d47b
SD		 13834 /* Acer C720 Chromebook (Core i3 4005U) */
13835 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13836
b2a9601c 13837 /* Apple Macbook 2,1 (Core 2 T7400) */
13838 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13839
d4967d8c
SD		 13840 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13841 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 13842
13843 /* HP Chromebook 14 (Celeron 2955U) */
13844 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 13845
13846 /* Dell Chromebook 11 */
13847 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 13848};
13849
13850static void intel_init_quirks(struct drm_device *dev)
13851{
13852 struct pci_dev *d = dev->pdev;
13853 int i;
13854
13855 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13856 struct intel_quirk *q = &intel_quirks[i];
13857
13858 if (d->device == q->device &&
13859 (d->subsystem_vendor == q->subsystem_vendor ||
13860 q->subsystem_vendor == PCI_ANY_ID) &&
13861 (d->subsystem_device == q->subsystem_device ||
13862 q->subsystem_device == PCI_ANY_ID))
13863 q->hook(dev);
13864 }
5f85f176
EE		 13865 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13866 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13867 intel_dmi_quirks[i].hook(dev);
13868 }
b690e96c
JB		 13869}
13870
9cce37f4
JB		 13871/* Disable the VGA plane that we never use */
13872static void i915_disable_vga(struct drm_device *dev)
13873{
13874 struct drm_i915_private *dev_priv = dev->dev_private;
13875 u8 sr1;
766aa1c4 13876 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 13877
2b37c616 13878 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 13879 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 13880 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 13881 sr1 = inb(VGA_SR_DATA);
13882 outb(sr1 | 1<<5, VGA_SR_DATA);
13883 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13884 udelay(300);
13885
01f5a626 13886 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 13887 POSTING_READ(vga_reg);
13888}
13889
f817586c
DV		 13890void intel_modeset_init_hw(struct drm_device *dev)
13891{
a8f78b58
ED		 13892 intel_prepare_ddi(dev);
13893
f8bf63fd
VS		 13894 if (IS_VALLEYVIEW(dev))
13895 vlv_update_cdclk(dev);
13896
f817586c
DV		 13897 intel_init_clock_gating(dev);
13898
8090c6b9 13899 intel_enable_gt_powersave(dev);
f817586c
DV		 13900}
13901
79e53945
JB		 13902void intel_modeset_init(struct drm_device *dev)
13903{
652c393a 13904 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 13905 int sprite, ret;
8cc87b75 13906 enum pipe pipe;
46f297fb 13907 struct intel_crtc *crtc;
79e53945
JB		 13908
13909 drm_mode_config_init(dev);
13910
13911 dev->mode_config.min_width = 0;
13912 dev->mode_config.min_height = 0;
13913
019d96cb
DA		 13914 dev->mode_config.preferred_depth = 24;
13915 dev->mode_config.prefer_shadow = 1;
13916
25bab385
TU		 13917 dev->mode_config.allow_fb_modifiers = true;
13918
e6ecefaa 13919 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 13920
b690e96c
JB		 13921 intel_init_quirks(dev);
13922
1fa61106
ED		 13923 intel_init_pm(dev);
13924
e3c74757
BW		 13925 if (INTEL_INFO(dev)->num_pipes == 0)
13926 return;
13927
e70236a8 13928 intel_init_display(dev);
7c10a2b5 13929 intel_init_audio(dev);
e70236a8 13930
a6c45cf0
CW		 13931 if (IS_GEN2(dev)) {
13932 dev->mode_config.max_width = 2048;
13933 dev->mode_config.max_height = 2048;
13934 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 13935 dev->mode_config.max_width = 4096;
13936 dev->mode_config.max_height = 4096;
79e53945 13937 } else {
a6c45cf0
CW		 13938 dev->mode_config.max_width = 8192;
13939 dev->mode_config.max_height = 8192;
79e53945 13940 }
068be561 13941
dc41c154
VS		 13942 if (IS_845G(dev) || IS_I865G(dev)) {
13943 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13944 dev->mode_config.cursor_height = 1023;
13945 } else if (IS_GEN2(dev)) {
068be561
DL		 13946 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13947 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13948 } else {
13949 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13950 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13951 }
13952
5d4545ae 13953 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 13954
28c97730 13955 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 13956 INTEL_INFO(dev)->num_pipes,
13957 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 13958
055e393f 13959 for_each_pipe(dev_priv, pipe) {
8cc87b75 13960 intel_crtc_init(dev, pipe);
3bdcfc0c 13961 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 13962 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 13963 if (ret)
06da8da2 13964 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 13965 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 13966 }
79e53945
JB		 13967 }
13968
f42bb70d
JB		 13969 intel_init_dpio(dev);
13970
e72f9fbf 13971 intel_shared_dpll_init(dev);
ee7b9f93 13972
9cce37f4
JB		 13973 /* Just disable it once at startup */
13974 i915_disable_vga(dev);
79e53945 13975 intel_setup_outputs(dev);
11be49eb
CW		 13976
13977 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 13978 intel_fbc_disable(dev);
fa9fa083 13979
6e9f798d 13980 drm_modeset_lock_all(dev);
fa9fa083 13981 intel_modeset_setup_hw_state(dev, false);
6e9f798d 13982 drm_modeset_unlock_all(dev);
46f297fb 13983
d3fcc808 13984 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 13985 if (!crtc->active)
13986 continue;
13987
46f297fb 13988 /*
46f297fb
JB		 13989 * Note that reserving the BIOS fb up front prevents us
13990 * from stuffing other stolen allocations like the ring
13991 * on top. This prevents some ugliness at boot time, and
13992 * can even allow for smooth boot transitions if the BIOS
13993 * fb is large enough for the active pipe configuration.
13994 */
5724dbd1
DL		 13995 if (dev_priv->display.get_initial_plane_config) {
13996 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 13997 &crtc->plane_config);
13998 /*
13999 * If the fb is shared between multiple heads, we'll
14000 * just get the first one.
14001 */
f6936e29 14002 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14003 }
46f297fb 14004 }
2c7111db
CW		 14005}
14006
7fad798e
DV		 14007static void intel_enable_pipe_a(struct drm_device *dev)
14008{
14009 struct intel_connector *connector;
14010 struct drm_connector *crt = NULL;
14011 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14012 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14013
14014 /* We can't just switch on the pipe A, we need to set things up with a
14015 * proper mode and output configuration. As a gross hack, enable pipe A
14016 * by enabling the load detect pipe once. */
3a3371ff 14017 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14018 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14019 crt = &connector->base;
14020 break;
14021 }
14022 }
14023
14024 if (!crt)
14025 return;
14026
208bf9fd 14027 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14028 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14029}
14030
fa555837
DV		 14031static bool
14032intel_check_plane_mapping(struct intel_crtc *crtc)
14033{
7eb552ae
BW		 14034 struct drm_device *dev = crtc->base.dev;
14035 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14036 u32 reg, val;
14037
7eb552ae 14038 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14039 return true;
14040
14041 reg = DSPCNTR(!crtc->plane);
14042 val = I915_READ(reg);
14043
14044 if ((val & DISPLAY_PLANE_ENABLE) &&
14045 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14046 return false;
14047
14048 return true;
14049}
14050
24929352
DV		 14051static void intel_sanitize_crtc(struct intel_crtc *crtc)
14052{
14053 struct drm_device *dev = crtc->base.dev;
14054 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14055 u32 reg;
24929352 14056
24929352 14057 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14058 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14059 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14060
d3eaf884 14061 /* restore vblank interrupts to correct state */
9625604c 14062 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14063 if (crtc->active) {
14064 update_scanline_offset(crtc);
9625604c
DV		 14065 drm_crtc_vblank_on(&crtc->base);
14066 }
d3eaf884 14067
24929352 14068 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14069 * disable the crtc (and hence change the state) if it is wrong. Note
14070 * that gen4+ has a fixed plane -> pipe mapping. */
14071 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14072 struct intel_connector *connector;
14073 bool plane;
14074
24929352
DV		 14075 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14076 crtc->base.base.id);
14077
14078 /* Pipe has the wrong plane attached and the plane is active.
14079 * Temporarily change the plane mapping and disable everything
14080 * ... */
14081 plane = crtc->plane;
14082 crtc->plane = !plane;
9c8958bc 14083 crtc->primary_enabled = true;
24929352
DV		 14084 dev_priv->display.crtc_disable(&crtc->base);
14085 crtc->plane = plane;
14086
14087 /* ... and break all links. */
3a3371ff 14088 for_each_intel_connector(dev, connector) {
24929352
DV		 14089 if (connector->encoder->base.crtc != &crtc->base)
14090 continue;
14091
7f1950fb
EE		 14092 connector->base.dpms = DRM_MODE_DPMS_OFF;
14093 connector->base.encoder = NULL;
24929352 14094 }
7f1950fb
EE		 14095 /* multiple connectors may have the same encoder:
14096 * handle them and break crtc link separately */
3a3371ff 14097 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14098 if (connector->encoder->base.crtc == &crtc->base) {
14099 connector->encoder->base.crtc = NULL;
14100 connector->encoder->connectors_active = false;
14101 }
24929352
DV		 14102
14103 WARN_ON(crtc->active);
83d65738 14104 crtc->base.state->enable = false;
24929352
DV		 14105 crtc->base.enabled = false;
14106 }
24929352 14107
7fad798e
DV		 14108 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14109 crtc->pipe == PIPE_A && !crtc->active) {
14110 /* BIOS forgot to enable pipe A, this mostly happens after
14111 * resume. Force-enable the pipe to fix this, the update_dpms
14112 * call below we restore the pipe to the right state, but leave
14113 * the required bits on. */
14114 intel_enable_pipe_a(dev);
14115 }
14116
24929352
DV		 14117 /* Adjust the state of the output pipe according to whether we
14118 * have active connectors/encoders. */
14119 intel_crtc_update_dpms(&crtc->base);
14120
83d65738 14121 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14122 struct intel_encoder *encoder;
14123
14124 /* This can happen either due to bugs in the get_hw_state
14125 * functions or because the pipe is force-enabled due to the
14126 * pipe A quirk. */
14127 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14128 crtc->base.base.id,
83d65738 14129 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14130 crtc->active ? "enabled" : "disabled");
14131
83d65738 14132 crtc->base.state->enable = crtc->active;
24929352
DV		 14133 crtc->base.enabled = crtc->active;
14134
14135 /* Because we only establish the connector -> encoder ->
14136 * crtc links if something is active, this means the
14137 * crtc is now deactivated. Break the links. connector
14138 * -> encoder links are only establish when things are
14139 * actually up, hence no need to break them. */
14140 WARN_ON(crtc->active);
14141
14142 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14143 WARN_ON(encoder->connectors_active);
14144 encoder->base.crtc = NULL;
14145 }
14146 }
c5ab3bc0 14147
a3ed6aad 14148 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14149 /*
14150 * We start out with underrun reporting disabled to avoid races.
14151 * For correct bookkeeping mark this on active crtcs.
14152 *
c5ab3bc0
DV		 14153 * Also on gmch platforms we dont have any hardware bits to
14154 * disable the underrun reporting. Which means we need to start
14155 * out with underrun reporting disabled also on inactive pipes,
14156 * since otherwise we'll complain about the garbage we read when
14157 * e.g. coming up after runtime pm.
14158 *
4cc31489
DV		 14159 * No protection against concurrent access is required - at
14160 * worst a fifo underrun happens which also sets this to false.
14161 */
14162 crtc->cpu_fifo_underrun_disabled = true;
14163 crtc->pch_fifo_underrun_disabled = true;
14164 }
24929352
DV		 14165}
14166
14167static void intel_sanitize_encoder(struct intel_encoder *encoder)
14168{
14169 struct intel_connector *connector;
14170 struct drm_device *dev = encoder->base.dev;
14171
14172 /* We need to check both for a crtc link (meaning that the
14173 * encoder is active and trying to read from a pipe) and the
14174 * pipe itself being active. */
14175 bool has_active_crtc = encoder->base.crtc &&
14176 to_intel_crtc(encoder->base.crtc)->active;
14177
14178 if (encoder->connectors_active && !has_active_crtc) {
14179 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14180 encoder->base.base.id,
8e329a03 14181 encoder->base.name);
24929352
DV		 14182
14183 /* Connector is active, but has no active pipe. This is
14184 * fallout from our resume register restoring. Disable
14185 * the encoder manually again. */
14186 if (encoder->base.crtc) {
14187 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14188 encoder->base.base.id,
8e329a03 14189 encoder->base.name);
24929352 14190 encoder->disable(encoder);
a62d1497
VS		 14191 if (encoder->post_disable)
14192 encoder->post_disable(encoder);
24929352 14193 }
7f1950fb
EE		 14194 encoder->base.crtc = NULL;
14195 encoder->connectors_active = false;
24929352
DV		 14196
14197 /* Inconsistent output/port/pipe state happens presumably due to
14198 * a bug in one of the get_hw_state functions. Or someplace else
14199 * in our code, like the register restore mess on resume. Clamp
14200 * things to off as a safer default. */
3a3371ff 14201 for_each_intel_connector(dev, connector) {
24929352
DV		 14202 if (connector->encoder != encoder)
14203 continue;
7f1950fb
EE		 14204 connector->base.dpms = DRM_MODE_DPMS_OFF;
14205 connector->base.encoder = NULL;
24929352
DV		 14206 }
14207 }
14208 /* Enabled encoders without active connectors will be fixed in
14209 * the crtc fixup. */
14210}
14211
04098753 14212void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14213{
14214 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14215 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14216
04098753
ID		 14217 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14218 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14219 i915_disable_vga(dev);
14220 }
14221}
14222
14223void i915_redisable_vga(struct drm_device *dev)
14224{
14225 struct drm_i915_private *dev_priv = dev->dev_private;
14226
8dc8a27c
PZ		 14227 /* This function can be called both from intel_modeset_setup_hw_state or
14228 * at a very early point in our resume sequence, where the power well
14229 * structures are not yet restored. Since this function is at a very
14230 * paranoid "someone might have enabled VGA while we were not looking"
14231 * level, just check if the power well is enabled instead of trying to
14232 * follow the "don't touch the power well if we don't need it" policy
14233 * the rest of the driver uses. */
f458ebbc 14234 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14235 return;
14236
04098753 14237 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14238}
14239
98ec7739
VS		 14240static bool primary_get_hw_state(struct intel_crtc *crtc)
14241{
14242 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14243
14244 if (!crtc->active)
14245 return false;
14246
14247 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14248}
14249
30e984df 14250static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14251{
14252 struct drm_i915_private *dev_priv = dev->dev_private;
14253 enum pipe pipe;
24929352
DV		 14254 struct intel_crtc *crtc;
14255 struct intel_encoder *encoder;
14256 struct intel_connector *connector;
5358901f 14257 int i;
24929352 14258
d3fcc808 14259 for_each_intel_crtc(dev, crtc) {
6e3c9717 14260 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14261
6e3c9717 14262 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14263
0e8ffe1b 14264 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14265 crtc->config);
24929352 14266
83d65738 14267 crtc->base.state->enable = crtc->active;
24929352 14268 crtc->base.enabled = crtc->active;
98ec7739 14269 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 14270
14271 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14272 crtc->base.base.id,
14273 crtc->active ? "enabled" : "disabled");
14274 }
14275
5358901f
DV		 14276 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14277 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14278
3e369b76
ACO		 14279 pll->on = pll->get_hw_state(dev_priv, pll,
14280 &pll->config.hw_state);
5358901f 14281 pll->active = 0;
3e369b76 14282 pll->config.crtc_mask = 0;
d3fcc808 14283 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14284 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14285 pll->active++;
3e369b76 14286 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14287 }
5358901f 14288 }
5358901f 14289
1e6f2ddc 14290 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14291 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14292
3e369b76 14293 if (pll->config.crtc_mask)
bd2bb1b9 14294 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14295 }
14296
b2784e15 14297 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14298 pipe = 0;
14299
14300 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14301 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14302 encoder->base.crtc = &crtc->base;
6e3c9717 14303 encoder->get_config(encoder, crtc->config);
24929352
DV		 14304 } else {
14305 encoder->base.crtc = NULL;
14306 }
14307
14308 encoder->connectors_active = false;
6f2bcceb 14309 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14310 encoder->base.base.id,
8e329a03 14311 encoder->base.name,
24929352 14312 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14313 pipe_name(pipe));
24929352
DV		 14314 }
14315
3a3371ff 14316 for_each_intel_connector(dev, connector) {
24929352
DV		 14317 if (connector->get_hw_state(connector)) {
14318 connector->base.dpms = DRM_MODE_DPMS_ON;
14319 connector->encoder->connectors_active = true;
14320 connector->base.encoder = &connector->encoder->base;
14321 } else {
14322 connector->base.dpms = DRM_MODE_DPMS_OFF;
14323 connector->base.encoder = NULL;
14324 }
14325 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14326 connector->base.base.id,
c23cc417 14327 connector->base.name,
24929352
DV		 14328 connector->base.encoder ? "enabled" : "disabled");
14329 }
30e984df
DV		 14330}
14331
14332/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14333 * and i915 state tracking structures. */
14334void intel_modeset_setup_hw_state(struct drm_device *dev,
14335 bool force_restore)
14336{
14337 struct drm_i915_private *dev_priv = dev->dev_private;
14338 enum pipe pipe;
30e984df
DV		 14339 struct intel_crtc *crtc;
14340 struct intel_encoder *encoder;
35c95375 14341 int i;
30e984df
DV		 14342
14343 intel_modeset_readout_hw_state(dev);
24929352 14344
babea61d
JB		 14345 /*
14346 * Now that we have the config, copy it to each CRTC struct
14347 * Note that this could go away if we move to using crtc_config
14348 * checking everywhere.
14349 */
d3fcc808 14350 for_each_intel_crtc(dev, crtc) {
d330a953 14351 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14352 intel_mode_from_pipe_config(&crtc->base.mode,
14353 crtc->config);
babea61d
JB		 14354 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14355 crtc->base.base.id);
14356 drm_mode_debug_printmodeline(&crtc->base.mode);
14357 }
14358 }
14359
24929352 14360 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14361 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14362 intel_sanitize_encoder(encoder);
14363 }
14364
055e393f 14365 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14366 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14367 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14368 intel_dump_pipe_config(crtc, crtc->config,
14369 "[setup_hw_state]");
24929352 14370 }
9a935856 14371
d29b2f9d
ACO		 14372 intel_modeset_update_connector_atomic_state(dev);
14373
35c95375
DV		 14374 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14375 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14376
14377 if (!pll->on || pll->active)
14378 continue;
14379
14380 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14381
14382 pll->disable(dev_priv, pll);
14383 pll->on = false;
14384 }
14385
3078999f
PB		 14386 if (IS_GEN9(dev))
14387 skl_wm_get_hw_state(dev);
14388 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14389 ilk_wm_get_hw_state(dev);
14390
45e2b5f6 14391 if (force_restore) {
7d0bc1ea
VS		 14392 i915_redisable_vga(dev);
14393
f30da187
DV		 14394 /*
14395 * We need to use raw interfaces for restoring state to avoid
14396 * checking (bogus) intermediate states.
14397 */
055e393f 14398 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14399 struct drm_crtc *crtc =
14400 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14401
83a57153 14402 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14403 }
14404 } else {
14405 intel_modeset_update_staged_output_state(dev);
14406 }
8af6cf88
DV		 14407
14408 intel_modeset_check_state(dev);
2c7111db
CW		 14409}
14410
14411void intel_modeset_gem_init(struct drm_device *dev)
14412{
92122789 14413 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 14414 struct drm_crtc *c;
2ff8fde1 14415 struct drm_i915_gem_object *obj;
484b41dd 14416
ae48434c
ID		 14417 mutex_lock(&dev->struct_mutex);
14418 intel_init_gt_powersave(dev);
14419 mutex_unlock(&dev->struct_mutex);
14420
92122789
JB		 14421 /*
14422 * There may be no VBT; and if the BIOS enabled SSC we can
14423 * just keep using it to avoid unnecessary flicker. Whereas if the
14424 * BIOS isn't using it, don't assume it will work even if the VBT
14425 * indicates as much.
14426 */
14427 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14428 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14429 DREF_SSC1_ENABLE);
14430
1833b134 14431 intel_modeset_init_hw(dev);
02e792fb
DV		 14432
14433 intel_setup_overlay(dev);
484b41dd
JB		 14434
14435 /*
14436 * Make sure any fbs we allocated at startup are properly
14437 * pinned & fenced. When we do the allocation it's too early
14438 * for this.
14439 */
14440 mutex_lock(&dev->struct_mutex);
70e1e0ec 14441 for_each_crtc(dev, c) {
2ff8fde1
MR		 14442 obj = intel_fb_obj(c->primary->fb);
14443 if (obj == NULL)
484b41dd
JB		 14444 continue;
14445
850c4cdc
TU		 14446 if (intel_pin_and_fence_fb_obj(c->primary,
14447 c->primary->fb,
82bc3b2d 14448 c->primary->state,
850c4cdc 14449 NULL)) {
484b41dd
JB		 14450 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14451 to_intel_crtc(c)->pipe);
66e514c1
DA		 14452 drm_framebuffer_unreference(c->primary->fb);
14453 c->primary->fb = NULL;
afd65eb4 14454 update_state_fb(c->primary);
484b41dd
JB		 14455 }
14456 }
14457 mutex_unlock(&dev->struct_mutex);
0962c3c9
VS		 14458
14459 intel_backlight_register(dev);
79e53945
JB		 14460}
14461
4932e2c3
ID		 14462void intel_connector_unregister(struct intel_connector *intel_connector)
14463{
14464 struct drm_connector *connector = &intel_connector->base;
14465
14466 intel_panel_destroy_backlight(connector);
34ea3d38 14467 drm_connector_unregister(connector);
4932e2c3
ID		 14468}
14469
79e53945
JB		 14470void intel_modeset_cleanup(struct drm_device *dev)
14471{
652c393a 14472 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 14473 struct drm_connector *connector;
652c393a 14474
2eb5252e
ID		 14475 intel_disable_gt_powersave(dev);
14476
0962c3c9
VS		 14477 intel_backlight_unregister(dev);
14478
fd0c0642
DV		 14479 /*
14480 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 14481 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 14482 * experience fancy races otherwise.
14483 */
2aeb7d3a 14484 intel_irq_uninstall(dev_priv);
eb21b92b 14485
fd0c0642
DV		 14486 /*
14487 * Due to the hpd irq storm handling the hotplug work can re-arm the
14488 * poll handlers. Hence disable polling after hpd handling is shut down.
14489 */
f87ea761 14490 drm_kms_helper_poll_fini(dev);
fd0c0642 14491
652c393a
JB		 14492 mutex_lock(&dev->struct_mutex);
14493
723bfd70
JB		 14494 intel_unregister_dsm_handler();
14495
7ff0ebcc 14496 intel_fbc_disable(dev);
e70236a8 14497
69341a5e
KH		 14498 mutex_unlock(&dev->struct_mutex);
14499
1630fe75
CW		 14500 /* flush any delayed tasks or pending work */
14501 flush_scheduled_work();
14502
db31af1d
JN		 14503 /* destroy the backlight and sysfs files before encoders/connectors */
14504 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 14505 struct intel_connector *intel_connector;
14506
14507 intel_connector = to_intel_connector(connector);
14508 intel_connector->unregister(intel_connector);
db31af1d 14509 }
d9255d57 14510
79e53945 14511 drm_mode_config_cleanup(dev);
4d7bb011
DV		 14512
14513 intel_cleanup_overlay(dev);
ae48434c
ID		 14514
14515 mutex_lock(&dev->struct_mutex);
14516 intel_cleanup_gt_powersave(dev);
14517 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14518}
14519
f1c79df3
ZW		 14520/*
14521 * Return which encoder is currently attached for connector.
14522 */
df0e9248 14523struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 14524{
df0e9248
CW		 14525 return &intel_attached_encoder(connector)->base;
14526}
f1c79df3 14527
df0e9248
CW		 14528void intel_connector_attach_encoder(struct intel_connector *connector,
14529 struct intel_encoder *encoder)
14530{
14531 connector->encoder = encoder;
14532 drm_mode_connector_attach_encoder(&connector->base,
14533 &encoder->base);
79e53945 14534}
28d52043
DA		 14535
14536/*
14537 * set vga decode state - true == enable VGA decode
14538 */
14539int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14540{
14541 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 14542 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 14543 u16 gmch_ctrl;
14544
75fa041d
CW		 14545 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14546 DRM_ERROR("failed to read control word\n");
14547 return -EIO;
14548 }
14549
c0cc8a55
CW		 14550 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14551 return 0;
14552
28d52043
DA		 14553 if (state)
14554 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14555 else
14556 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 14557
14558 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14559 DRM_ERROR("failed to write control word\n");
14560 return -EIO;
14561 }
14562
28d52043
DA		 14563 return 0;
14564}
c4a1d9e4 14565
c4a1d9e4 14566struct intel_display_error_state {
ff57f1b0
PZ		 14567
14568 u32 power_well_driver;
14569
63b66e5b
CW		 14570 int num_transcoders;
14571
c4a1d9e4
CW		 14572 struct intel_cursor_error_state {
14573 u32 control;
14574 u32 position;
14575 u32 base;
14576 u32 size;
52331309 14577 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 14578
14579 struct intel_pipe_error_state {
ddf9c536 14580 bool power_domain_on;
c4a1d9e4 14581 u32 source;
f301b1e1 14582 u32 stat;
52331309 14583 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 14584
14585 struct intel_plane_error_state {
14586 u32 control;
14587 u32 stride;
14588 u32 size;
14589 u32 pos;
14590 u32 addr;
14591 u32 surface;
14592 u32 tile_offset;
52331309 14593 } plane[I915_MAX_PIPES];
63b66e5b
CW		 14594
14595 struct intel_transcoder_error_state {
ddf9c536 14596 bool power_domain_on;
63b66e5b
CW		 14597 enum transcoder cpu_transcoder;
14598
14599 u32 conf;
14600
14601 u32 htotal;
14602 u32 hblank;
14603 u32 hsync;
14604 u32 vtotal;
14605 u32 vblank;
14606 u32 vsync;
14607 } transcoder[4];
c4a1d9e4
CW		 14608};
14609
14610struct intel_display_error_state *
14611intel_display_capture_error_state(struct drm_device *dev)
14612{
fbee40df 14613 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 14614 struct intel_display_error_state *error;
63b66e5b
CW		 14615 int transcoders[] = {
14616 TRANSCODER_A,
14617 TRANSCODER_B,
14618 TRANSCODER_C,
14619 TRANSCODER_EDP,
14620 };
c4a1d9e4
CW		 14621 int i;
14622
63b66e5b
CW		 14623 if (INTEL_INFO(dev)->num_pipes == 0)
14624 return NULL;
14625
9d1cb914 14626 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 14627 if (error == NULL)
14628 return NULL;
14629
190be112 14630 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 14631 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14632
055e393f 14633 for_each_pipe(dev_priv, i) {
ddf9c536 14634 error->pipe[i].power_domain_on =
f458ebbc
DV		 14635 __intel_display_power_is_enabled(dev_priv,
14636 POWER_DOMAIN_PIPE(i));
ddf9c536 14637 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 14638 continue;
14639
5efb3e28
VS		 14640 error->cursor[i].control = I915_READ(CURCNTR(i));
14641 error->cursor[i].position = I915_READ(CURPOS(i));
14642 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 14643
14644 error->plane[i].control = I915_READ(DSPCNTR(i));
14645 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 14646 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 14647 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 14648 error->plane[i].pos = I915_READ(DSPPOS(i));
14649 }
ca291363
PZ		 14650 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14651 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 14652 if (INTEL_INFO(dev)->gen >= 4) {
14653 error->plane[i].surface = I915_READ(DSPSURF(i));
14654 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14655 }
14656
c4a1d9e4 14657 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 14658
3abfce77 14659 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 14660 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 14661 }
14662
14663 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14664 if (HAS_DDI(dev_priv->dev))
14665 error->num_transcoders++; /* Account for eDP. */
14666
14667 for (i = 0; i < error->num_transcoders; i++) {
14668 enum transcoder cpu_transcoder = transcoders[i];
14669
ddf9c536 14670 error->transcoder[i].power_domain_on =
f458ebbc 14671 __intel_display_power_is_enabled(dev_priv,
38cc1daf 14672 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 14673 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 14674 continue;
14675
63b66e5b
CW		 14676 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14677
14678 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14679 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14680 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14681 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14682 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14683 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14684 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 14685 }
14686
14687 return error;
14688}
14689
edc3d884
MK		 14690#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14691
c4a1d9e4 14692void
edc3d884 14693intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 14694 struct drm_device *dev,
14695 struct intel_display_error_state *error)
14696{
055e393f 14697 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 14698 int i;
14699
63b66e5b
CW		 14700 if (!error)
14701 return;
14702
edc3d884 14703 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 14704 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 14705 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 14706 error->power_well_driver);
055e393f 14707 for_each_pipe(dev_priv, i) {
edc3d884 14708 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 14709 err_printf(m, " Power: %s\n",
14710 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 14711 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 14712 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 14713
14714 err_printf(m, "Plane [%d]:\n", i);
14715 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14716 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 14717 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 14718 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14719 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 14720 }
4b71a570 14721 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 14722 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 14723 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 14724 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14725 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 14726 }
14727
edc3d884
MK		 14728 err_printf(m, "Cursor [%d]:\n", i);
14729 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14730 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14731 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 14732 }
63b66e5b
CW		 14733
14734 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 14735 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 14736 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 14737 err_printf(m, " Power: %s\n",
14738 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 14739 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14740 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14741 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14742 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14743 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14744 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14745 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14746 }
c4a1d9e4 14747}
e2fcdaa9
VS		 14748
14749void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14750{
14751 struct intel_crtc *crtc;
14752
14753 for_each_intel_crtc(dev, crtc) {
14754 struct intel_unpin_work *work;
e2fcdaa9 14755
5e2d7afc 14756 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 14757
14758 work = crtc->unpin_work;
14759
14760 if (work && work->event &&
14761 work->event->base.file_priv == file) {
14762 kfree(work->event);
14763 work->event = NULL;
14764 }
14765
5e2d7afc 14766 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 14767 }
14768}
Linux kernel - Deliverables
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