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drm: Change create block to reserve node
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
79e53945 53typedef struct {
0206e353 54 int min, max;
79e53945
JB		 55} intel_range_t;
56
57typedef struct {
0206e353
AJ		 58 int dot_limit;
59 int p2_slow, p2_fast;
79e53945
JB		 60} intel_p2_t;
61
62#define INTEL_P2_NUM 2
d4906093
ML		 63typedef struct intel_limit intel_limit_t;
64struct intel_limit {
0206e353
AJ		 65 intel_range_t dot, vco, n, m, m1, m2, p, p1;
66 intel_p2_t p2;
d4906093 67};
79e53945 68
2377b741
JB		 69/* FDI */
70#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
e4b36699 92static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
105static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 14, .p2_fast = 7 },
e4b36699 116};
273e27ca 117
e4b36699 118static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 119 .dot = { .min = 20000, .max = 400000 },
120 .vco = { .min = 1400000, .max = 2800000 },
121 .n = { .min = 1, .max = 6 },
122 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 123 .m1 = { .min = 8, .max = 18 },
124 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 125 .p = { .min = 5, .max = 80 },
126 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 127 .p2 = { .dot_limit = 200000,
128 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 129};
130
131static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 7, .max = 98 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 112000,
141 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 142};
143
273e27ca 144
e4b36699 145static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 146 .dot = { .min = 25000, .max = 270000 },
147 .vco = { .min = 1750000, .max = 3500000},
148 .n = { .min = 1, .max = 4 },
149 .m = { .min = 104, .max = 138 },
150 .m1 = { .min = 17, .max = 23 },
151 .m2 = { .min = 5, .max = 11 },
152 .p = { .min = 10, .max = 30 },
153 .p1 = { .min = 1, .max = 3},
154 .p2 = { .dot_limit = 270000,
155 .p2_slow = 10,
156 .p2_fast = 10
044c7c41 157 },
e4b36699
KP		 158};
159
160static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 161 .dot = { .min = 22000, .max = 400000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 16, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 5, .max = 80 },
168 .p1 = { .min = 1, .max = 8},
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 174 .dot = { .min = 20000, .max = 115000 },
175 .vco = { .min = 1750000, .max = 3500000 },
176 .n = { .min = 1, .max = 3 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 28, .max = 112 },
181 .p1 = { .min = 2, .max = 8 },
182 .p2 = { .dot_limit = 0,
183 .p2_slow = 14, .p2_fast = 14
044c7c41 184 },
e4b36699
KP		 185};
186
187static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 188 .dot = { .min = 80000, .max = 224000 },
189 .vco = { .min = 1750000, .max = 3500000 },
190 .n = { .min = 1, .max = 3 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 17, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 14, .max = 42 },
195 .p1 = { .min = 2, .max = 6 },
196 .p2 = { .dot_limit = 0,
197 .p2_slow = 7, .p2_fast = 7
044c7c41 198 },
e4b36699
KP		 199};
200
f2b115e6 201static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 202 .dot = { .min = 20000, .max = 400000},
203 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 204 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 205 .n = { .min = 3, .max = 6 },
206 .m = { .min = 2, .max = 256 },
273e27ca 207 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 208 .m1 = { .min = 0, .max = 0 },
209 .m2 = { .min = 0, .max = 254 },
210 .p = { .min = 5, .max = 80 },
211 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 212 .p2 = { .dot_limit = 200000,
213 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 214};
215
f2b115e6 216static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 217 .dot = { .min = 20000, .max = 400000 },
218 .vco = { .min = 1700000, .max = 3500000 },
219 .n = { .min = 3, .max = 6 },
220 .m = { .min = 2, .max = 256 },
221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 7, .max = 112 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 112000,
226 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 227};
228
273e27ca
EA		 229/* Ironlake / Sandybridge
230 *
231 * We calculate clock using (register_value + 2) for N/M1/M2, so here
232 * the range value for them is (actual_value - 2).
233 */
b91ad0ec 234static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 235 .dot = { .min = 25000, .max = 350000 },
236 .vco = { .min = 1760000, .max = 3510000 },
237 .n = { .min = 1, .max = 5 },
238 .m = { .min = 79, .max = 127 },
239 .m1 = { .min = 12, .max = 22 },
240 .m2 = { .min = 5, .max = 9 },
241 .p = { .min = 5, .max = 80 },
242 .p1 = { .min = 1, .max = 8 },
243 .p2 = { .dot_limit = 225000,
244 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 245};
246
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 79, .max = 118 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 28, .max = 112 },
255 .p1 = { .min = 2, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 258};
259
260static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 127 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 14, .max = 56 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 271};
272
273e27ca 273/* LVDS 100mhz refclk limits. */
b91ad0ec 274static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 2 },
278 .m = { .min = 79, .max = 126 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
0206e353 282 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 285};
286
287static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 42 },
0206e353 295 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 298};
299
a0c4da24
JB		 300static const intel_limit_t intel_limits_vlv_dac = {
301 .dot = { .min = 25000, .max = 270000 },
302 .vco = { .min = 4000000, .max = 6000000 },
303 .n = { .min = 1, .max = 7 },
304 .m = { .min = 22, .max = 450 }, /* guess */
305 .m1 = { .min = 2, .max = 3 },
306 .m2 = { .min = 11, .max = 156 },
307 .p = { .min = 10, .max = 30 },
75e53986 308 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 309 .p2 = { .dot_limit = 270000,
310 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 311};
312
313static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 60, .max = 300 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
321 .p1 = { .min = 2, .max = 3 },
322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 329 .n = { .min = 1, .max = 7 },
74a4dd2e 330 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
75e53986 334 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
401 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
402 limit = &intel_limits_vlv_hdmi;
403 else
404 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 405 } else if (!IS_GEN2(dev)) {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_i9xx_lvds;
408 else
409 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 410 } else {
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 412 limit = &intel_limits_i8xx_lvds;
79e53945 413 else
e4b36699 414 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
675 u32 updrate, minupdate, fracbits, p;
676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
686 fracbits = 1;
687 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
688 bestm1 = bestm2 = bestp1 = bestp2 = 0;
689
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
692 updrate = refclk / n;
693 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
694 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
695 if (p2 > 10)
696 p2 = p2 - 1;
697 p = p1 * p2;
698 /* based on hardware requirement, prefer bigger m1,m2 values */
699 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
700 m2 = (((2*(fastclk * p * n / m1 )) +
701 refclk) / (2*refclk));
702 m = m1 * m2;
703 vco = updrate * m;
704 if (vco >= limit->vco.min && vco < limit->vco.max) {
705 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
706 absppm = (ppm > 0) ? ppm : (-ppm);
707 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
708 bestppm = 0;
709 flag = 1;
710 }
711 if (absppm < bestppm - 10) {
712 bestppm = absppm;
713 flag = 1;
714 }
715 if (flag) {
716 bestn = n;
717 bestm1 = m1;
718 bestm2 = m2;
719 bestp1 = p1;
720 bestp2 = p2;
721 flag = 0;
722 }
723 }
724 }
725 }
726 }
727 }
728 best_clock->n = bestn;
729 best_clock->m1 = bestm1;
730 best_clock->m2 = bestm2;
731 best_clock->p1 = bestp1;
732 best_clock->p2 = bestp2;
733
734 return true;
735}
a4fc5ed6 736
a5c961d1
PZ		 737enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
738 enum pipe pipe)
739{
740 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
742
3b117c8f 743 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 744}
745
a928d536
PZ		 746static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
749 u32 frame, frame_reg = PIPEFRAME(pipe);
750
751 frame = I915_READ(frame_reg);
752
753 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
754 DRM_DEBUG_KMS("vblank wait timed out\n");
755}
756
9d0498a2
JB		 757/**
758 * intel_wait_for_vblank - wait for vblank on a given pipe
759 * @dev: drm device
760 * @pipe: pipe to wait for
761 *
762 * Wait for vblank to occur on a given pipe. Needed for various bits of
763 * mode setting code.
764 */
765void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 766{
9d0498a2 767 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 768 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 769
a928d536
PZ		 770 if (INTEL_INFO(dev)->gen >= 5) {
771 ironlake_wait_for_vblank(dev, pipe);
772 return;
773 }
774
300387c0
CW		 775 /* Clear existing vblank status. Note this will clear any other
776 * sticky status fields as well.
777 *
778 * This races with i915_driver_irq_handler() with the result
779 * that either function could miss a vblank event. Here it is not
780 * fatal, as we will either wait upon the next vblank interrupt or
781 * timeout. Generally speaking intel_wait_for_vblank() is only
782 * called during modeset at which time the GPU should be idle and
783 * should *not* be performing page flips and thus not waiting on
784 * vblanks...
785 * Currently, the result of us stealing a vblank from the irq
786 * handler is that a single frame will be skipped during swapbuffers.
787 */
788 I915_WRITE(pipestat_reg,
789 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
790
9d0498a2 791 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 792 if (wait_for(I915_READ(pipestat_reg) &
793 PIPE_VBLANK_INTERRUPT_STATUS,
794 50))
9d0498a2
JB		 795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
ab7ad7f6
KP		 798/*
799 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * After disabling a pipe, we can't wait for vblank in the usual way,
804 * spinning on the vblank interrupt status bit, since we won't actually
805 * see an interrupt when the pipe is disabled.
806 *
ab7ad7f6
KP		 807 * On Gen4 and above:
808 * wait for the pipe register state bit to turn off
809 *
810 * Otherwise:
811 * wait for the display line value to settle (it usually
812 * ends up stopping at the start of the next frame).
58e10eb9 813 *
9d0498a2 814 */
58e10eb9 815void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 816{
817 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 818 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
819 pipe);
ab7ad7f6
KP		 820
821 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 822 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 823
824 /* Wait for the Pipe State to go off */
58e10eb9
CW		 825 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
826 100))
284637d9 827 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 828 } else {
837ba00f 829 u32 last_line, line_mask;
58e10eb9 830 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 831 unsigned long timeout = jiffies + msecs_to_jiffies(100);
832
837ba00f
PZ		 833 if (IS_GEN2(dev))
834 line_mask = DSL_LINEMASK_GEN2;
835 else
836 line_mask = DSL_LINEMASK_GEN3;
837
ab7ad7f6
KP		 838 /* Wait for the display line to settle */
839 do {
837ba00f 840 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 841 mdelay(5);
837ba00f 842 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 843 time_after(timeout, jiffies));
844 if (time_after(jiffies, timeout))
284637d9 845 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 846 }
79e53945
JB		 847}
848
b0ea7d37
DL		 849/*
850 * ibx_digital_port_connected - is the specified port connected?
851 * @dev_priv: i915 private structure
852 * @port: the port to test
853 *
854 * Returns true if @port is connected, false otherwise.
855 */
856bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
857 struct intel_digital_port *port)
858{
859 u32 bit;
860
c36346e3
DL		 861 if (HAS_PCH_IBX(dev_priv->dev)) {
862 switch(port->port) {
863 case PORT_B:
864 bit = SDE_PORTB_HOTPLUG;
865 break;
866 case PORT_C:
867 bit = SDE_PORTC_HOTPLUG;
868 break;
869 case PORT_D:
870 bit = SDE_PORTD_HOTPLUG;
871 break;
872 default:
873 return true;
874 }
875 } else {
876 switch(port->port) {
877 case PORT_B:
878 bit = SDE_PORTB_HOTPLUG_CPT;
879 break;
880 case PORT_C:
881 bit = SDE_PORTC_HOTPLUG_CPT;
882 break;
883 case PORT_D:
884 bit = SDE_PORTD_HOTPLUG_CPT;
885 break;
886 default:
887 return true;
888 }
b0ea7d37
DL		 889 }
890
891 return I915_READ(SDEISR) & bit;
892}
893
b24e7179
JB		 894static const char *state_string(bool enabled)
895{
896 return enabled ? "on" : "off";
897}
898
899/* Only for pre-ILK configs */
55607e8a
DV		 900void assert_pll(struct drm_i915_private *dev_priv,
901 enum pipe pipe, bool state)
b24e7179
JB		 902{
903 int reg;
904 u32 val;
905 bool cur_state;
906
907 reg = DPLL(pipe);
908 val = I915_READ(reg);
909 cur_state = !!(val & DPLL_VCO_ENABLE);
910 WARN(cur_state != state,
911 "PLL state assertion failure (expected %s, current %s)\n",
912 state_string(state), state_string(cur_state));
913}
b24e7179 914
55607e8a 915struct intel_shared_dpll *
e2b78267
DV		 916intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
917{
918 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
919
a43f6e0f 920 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 921 return NULL;
922
a43f6e0f 923 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 924}
925
040484af 926/* For ILK+ */
55607e8a
DV		 927void assert_shared_dpll(struct drm_i915_private *dev_priv,
928 struct intel_shared_dpll *pll,
929 bool state)
040484af 930{
040484af 931 bool cur_state;
5358901f 932 struct intel_dpll_hw_state hw_state;
040484af 933
9d82aa17
ED		 934 if (HAS_PCH_LPT(dev_priv->dev)) {
935 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
936 return;
937 }
938
92b27b08 939 if (WARN (!pll,
46edb027 940 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 941 return;
ee7b9f93 942
5358901f 943 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 944 WARN(cur_state != state,
5358901f
DV		 945 "%s assertion failure (expected %s, current %s)\n",
946 pll->name, state_string(state), state_string(cur_state));
040484af 947}
040484af
JB		 948
949static void assert_fdi_tx(struct drm_i915_private *dev_priv,
950 enum pipe pipe, bool state)
951{
952 int reg;
953 u32 val;
954 bool cur_state;
ad80a810
PZ		 955 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
956 pipe);
040484af 957
affa9354
PZ		 958 if (HAS_DDI(dev_priv->dev)) {
959 /* DDI does not have a specific FDI_TX register */
ad80a810 960 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 961 val = I915_READ(reg);
ad80a810 962 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 963 } else {
964 reg = FDI_TX_CTL(pipe);
965 val = I915_READ(reg);
966 cur_state = !!(val & FDI_TX_ENABLE);
967 }
040484af
JB		 968 WARN(cur_state != state,
969 "FDI TX state assertion failure (expected %s, current %s)\n",
970 state_string(state), state_string(cur_state));
971}
972#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
973#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
974
975static void assert_fdi_rx(struct drm_i915_private *dev_priv,
976 enum pipe pipe, bool state)
977{
978 int reg;
979 u32 val;
980 bool cur_state;
981
d63fa0dc
PZ		 982 reg = FDI_RX_CTL(pipe);
983 val = I915_READ(reg);
984 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 985 WARN(cur_state != state,
986 "FDI RX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
990#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
991
992static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe)
994{
995 int reg;
996 u32 val;
997
998 /* ILK FDI PLL is always enabled */
999 if (dev_priv->info->gen == 5)
1000 return;
1001
bf507ef7 1002 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1003 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1004 return;
1005
040484af
JB		 1006 reg = FDI_TX_CTL(pipe);
1007 val = I915_READ(reg);
1008 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1009}
1010
55607e8a
DV		 1011void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1012 enum pipe pipe, bool state)
040484af
JB		 1013{
1014 int reg;
1015 u32 val;
55607e8a 1016 bool cur_state;
040484af
JB		 1017
1018 reg = FDI_RX_CTL(pipe);
1019 val = I915_READ(reg);
55607e8a
DV		 1020 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1021 WARN(cur_state != state,
1022 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1023 state_string(state), state_string(cur_state));
040484af
JB		 1024}
1025
ea0760cf
JB		 1026static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int pp_reg, lvds_reg;
1030 u32 val;
1031 enum pipe panel_pipe = PIPE_A;
0de3b485 1032 bool locked = true;
ea0760cf
JB		 1033
1034 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1035 pp_reg = PCH_PP_CONTROL;
1036 lvds_reg = PCH_LVDS;
1037 } else {
1038 pp_reg = PP_CONTROL;
1039 lvds_reg = LVDS;
1040 }
1041
1042 val = I915_READ(pp_reg);
1043 if (!(val & PANEL_POWER_ON) ||
1044 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1045 locked = false;
1046
1047 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1048 panel_pipe = PIPE_B;
1049
1050 WARN(panel_pipe == pipe && locked,
1051 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1052 pipe_name(pipe));
ea0760cf
JB		 1053}
1054
b840d907
JB		 1055void assert_pipe(struct drm_i915_private *dev_priv,
1056 enum pipe pipe, bool state)
b24e7179
JB		 1057{
1058 int reg;
1059 u32 val;
63d7bbe9 1060 bool cur_state;
702e7a56
PZ		 1061 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1062 pipe);
b24e7179 1063
8e636784
DV		 1064 /* if we need the pipe A quirk it must be always on */
1065 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1066 state = true;
1067
b97186f0
PZ		 1068 if (!intel_display_power_enabled(dev_priv->dev,
1069 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1070 cur_state = false;
1071 } else {
1072 reg = PIPECONF(cpu_transcoder);
1073 val = I915_READ(reg);
1074 cur_state = !!(val & PIPECONF_ENABLE);
1075 }
1076
63d7bbe9
JB		 1077 WARN(cur_state != state,
1078 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1079 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1080}
1081
931872fc
CW		 1082static void assert_plane(struct drm_i915_private *dev_priv,
1083 enum plane plane, bool state)
b24e7179
JB		 1084{
1085 int reg;
1086 u32 val;
931872fc 1087 bool cur_state;
b24e7179
JB		 1088
1089 reg = DSPCNTR(plane);
1090 val = I915_READ(reg);
931872fc
CW		 1091 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1092 WARN(cur_state != state,
1093 "plane %c assertion failure (expected %s, current %s)\n",
1094 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1095}
1096
931872fc
CW		 1097#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1098#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1099
b24e7179
JB		 1100static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1101 enum pipe pipe)
1102{
653e1026 1103 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1104 int reg, i;
1105 u32 val;
1106 int cur_pipe;
1107
653e1026
VS		 1108 /* Primary planes are fixed to pipes on gen4+ */
1109 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1110 reg = DSPCNTR(pipe);
1111 val = I915_READ(reg);
1112 WARN((val & DISPLAY_PLANE_ENABLE),
1113 "plane %c assertion failure, should be disabled but not\n",
1114 plane_name(pipe));
19ec1358 1115 return;
28c05794 1116 }
19ec1358 1117
b24e7179 1118 /* Need to check both planes against the pipe */
653e1026 1119 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1120 reg = DSPCNTR(i);
1121 val = I915_READ(reg);
1122 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1123 DISPPLANE_SEL_PIPE_SHIFT;
1124 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1125 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1126 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1127 }
1128}
1129
19332d7a
JB		 1130static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1131 enum pipe pipe)
1132{
20674eef 1133 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1134 int reg, i;
1135 u32 val;
1136
20674eef
VS		 1137 if (IS_VALLEYVIEW(dev)) {
1138 for (i = 0; i < dev_priv->num_plane; i++) {
1139 reg = SPCNTR(pipe, i);
1140 val = I915_READ(reg);
1141 WARN((val & SP_ENABLE),
1142 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1143 sprite_name(pipe, i), pipe_name(pipe));
1144 }
1145 } else if (INTEL_INFO(dev)->gen >= 7) {
1146 reg = SPRCTL(pipe);
19332d7a 1147 val = I915_READ(reg);
20674eef 1148 WARN((val & SPRITE_ENABLE),
06da8da2 1149 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1150 plane_name(pipe), pipe_name(pipe));
1151 } else if (INTEL_INFO(dev)->gen >= 5) {
1152 reg = DVSCNTR(pipe);
19332d7a 1153 val = I915_READ(reg);
20674eef 1154 WARN((val & DVS_ENABLE),
06da8da2 1155 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1156 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1157 }
1158}
1159
92f2584a
JB		 1160static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1161{
1162 u32 val;
1163 bool enabled;
1164
9d82aa17
ED		 1165 if (HAS_PCH_LPT(dev_priv->dev)) {
1166 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1167 return;
1168 }
1169
92f2584a
JB		 1170 val = I915_READ(PCH_DREF_CONTROL);
1171 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1172 DREF_SUPERSPREAD_SOURCE_MASK));
1173 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1174}
1175
ab9412ba
DV		 1176static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1177 enum pipe pipe)
92f2584a
JB		 1178{
1179 int reg;
1180 u32 val;
1181 bool enabled;
1182
ab9412ba 1183 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1184 val = I915_READ(reg);
1185 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1186 WARN(enabled,
1187 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1188 pipe_name(pipe));
92f2584a
JB		 1189}
1190
4e634389
KP		 1191static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1193{
1194 if ((val & DP_PORT_EN) == 0)
1195 return false;
1196
1197 if (HAS_PCH_CPT(dev_priv->dev)) {
1198 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1199 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1200 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1201 return false;
1202 } else {
1203 if ((val & DP_PIPE_MASK) != (pipe << 30))
1204 return false;
1205 }
1206 return true;
1207}
1208
1519b995
KP		 1209static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, u32 val)
1211{
dc0fa718 1212 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1213 return false;
1214
1215 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1216 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1217 return false;
1218 } else {
dc0fa718 1219 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1220 return false;
1221 }
1222 return true;
1223}
1224
1225static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe, u32 val)
1227{
1228 if ((val & LVDS_PORT_EN) == 0)
1229 return false;
1230
1231 if (HAS_PCH_CPT(dev_priv->dev)) {
1232 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1233 return false;
1234 } else {
1235 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1236 return false;
1237 }
1238 return true;
1239}
1240
1241static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, u32 val)
1243{
1244 if ((val & ADPA_DAC_ENABLE) == 0)
1245 return false;
1246 if (HAS_PCH_CPT(dev_priv->dev)) {
1247 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248 return false;
1249 } else {
1250 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1251 return false;
1252 }
1253 return true;
1254}
1255
291906f1 1256static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1257 enum pipe pipe, int reg, u32 port_sel)
291906f1 1258{
47a05eca 1259 u32 val = I915_READ(reg);
4e634389 1260 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1261 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1262 reg, pipe_name(pipe));
de9a35ab 1263
75c5da27
DV		 1264 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1265 && (val & DP_PIPEB_SELECT),
de9a35ab 1266 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1267}
1268
1269static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe, int reg)
1271{
47a05eca 1272 u32 val = I915_READ(reg);
b70ad586 1273 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1274 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1275 reg, pipe_name(pipe));
de9a35ab 1276
dc0fa718 1277 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1278 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1279 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1280}
1281
1282static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1283 enum pipe pipe)
1284{
1285 int reg;
1286 u32 val;
291906f1 1287
f0575e92
KP		 1288 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1289 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1290 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1291
1292 reg = PCH_ADPA;
1293 val = I915_READ(reg);
b70ad586 1294 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1295 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1296 pipe_name(pipe));
291906f1
JB		 1297
1298 reg = PCH_LVDS;
1299 val = I915_READ(reg);
b70ad586 1300 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1301 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1302 pipe_name(pipe));
291906f1 1303
e2debe91
PZ		 1304 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1305 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1306 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1307}
1308
87442f73
DV		 1309static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1310{
1311 int reg;
1312 u32 val;
1313
1314 assert_pipe_disabled(dev_priv, pipe);
1315
1316 /* No really, not for ILK+ */
1317 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1318
1319 /* PLL is protected by panel, make sure we can write it */
1320 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1321 assert_panel_unlocked(dev_priv, pipe);
1322
1323 reg = DPLL(pipe);
1324 val = I915_READ(reg);
1325 val |= DPLL_VCO_ENABLE;
1326
1327 /* We do this three times for luck */
1328 I915_WRITE(reg, val);
1329 POSTING_READ(reg);
1330 udelay(150); /* wait for warmup */
1331 I915_WRITE(reg, val);
1332 POSTING_READ(reg);
1333 udelay(150); /* wait for warmup */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337}
1338
66e3d5c0 1339static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1340{
66e3d5c0
DV		 1341 struct drm_device *dev = crtc->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 int reg = DPLL(crtc->pipe);
1344 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1345
66e3d5c0 1346 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1347
63d7bbe9 1348 /* No really, not for ILK+ */
87442f73 1349 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1350
1351 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1352 if (IS_MOBILE(dev) && !IS_I830(dev))
1353 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1354
66e3d5c0
DV		 1355 I915_WRITE(reg, dpll);
1356
1357 /* Wait for the clocks to stabilize. */
1358 POSTING_READ(reg);
1359 udelay(150);
1360
1361 if (INTEL_INFO(dev)->gen >= 4) {
1362 I915_WRITE(DPLL_MD(crtc->pipe),
1363 crtc->config.dpll_hw_state.dpll_md);
1364 } else {
1365 /* The pixel multiplier can only be updated once the
1366 * DPLL is enabled and the clocks are stable.
1367 *
1368 * So write it again.
1369 */
1370 I915_WRITE(reg, dpll);
1371 }
63d7bbe9
JB		 1372
1373 /* We do this three times for luck */
66e3d5c0 1374 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
66e3d5c0 1377 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
66e3d5c0 1380 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
89b667f8
JB		 1413void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1414{
1415 u32 port_mask;
1416
1417 if (!port)
1418 port_mask = DPLL_PORTB_READY_MASK;
1419 else
1420 port_mask = DPLL_PORTC_READY_MASK;
1421
1422 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1423 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1424 'B' + port, I915_READ(DPLL(0)));
1425}
1426
92f2584a 1427/**
e72f9fbf 1428 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1433 * drives the transcoder clock.
1434 */
e2b78267 1435static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1436{
e2b78267
DV		 1437 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1438 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1439
48da64a8 1440 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1441 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1442 if (WARN_ON(pll == NULL))
48da64a8
CW		 1443 return;
1444
1445 if (WARN_ON(pll->refcount == 0))
1446 return;
ee7b9f93 1447
46edb027
DV		 1448 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1449 pll->name, pll->active, pll->on,
e2b78267 1450 crtc->base.base.id);
92f2584a 1451
cdbd2316
DV		 1452 if (pll->active++) {
1453 WARN_ON(!pll->on);
e9d6944e 1454 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1455 return;
1456 }
f4a091c7 1457 WARN_ON(pll->on);
ee7b9f93 1458
46edb027 1459 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1460 pll->enable(dev_priv, pll);
ee7b9f93 1461 pll->on = true;
92f2584a
JB		 1462}
1463
e2b78267 1464static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1465{
e2b78267
DV		 1466 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1467 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1468
92f2584a
JB		 1469 /* PCH only available on ILK+ */
1470 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1471 if (WARN_ON(pll == NULL))
ee7b9f93 1472 return;
92f2584a 1473
48da64a8
CW		 1474 if (WARN_ON(pll->refcount == 0))
1475 return;
7a419866 1476
46edb027
DV		 1477 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1478 pll->name, pll->active, pll->on,
e2b78267 1479 crtc->base.base.id);
7a419866 1480
48da64a8 1481 if (WARN_ON(pll->active == 0)) {
e9d6944e 1482 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1483 return;
1484 }
1485
e9d6944e 1486 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1487 WARN_ON(!pll->on);
cdbd2316 1488 if (--pll->active)
7a419866 1489 return;
ee7b9f93 1490
46edb027 1491 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1492 pll->disable(dev_priv, pll);
ee7b9f93 1493 pll->on = false;
92f2584a
JB		 1494}
1495
b8a4f404
PZ		 1496static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1497 enum pipe pipe)
040484af 1498{
23670b32 1499 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1500 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1502 uint32_t reg, val, pipeconf_val;
040484af
JB		 1503
1504 /* PCH only available on ILK+ */
1505 BUG_ON(dev_priv->info->gen < 5);
1506
1507 /* Make sure PCH DPLL is enabled */
e72f9fbf 1508 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1509 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1510
1511 /* FDI must be feeding us bits for PCH ports */
1512 assert_fdi_tx_enabled(dev_priv, pipe);
1513 assert_fdi_rx_enabled(dev_priv, pipe);
1514
23670b32
DV		 1515 if (HAS_PCH_CPT(dev)) {
1516 /* Workaround: Set the timing override bit before enabling the
1517 * pch transcoder. */
1518 reg = TRANS_CHICKEN2(pipe);
1519 val = I915_READ(reg);
1520 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1521 I915_WRITE(reg, val);
59c859d6 1522 }
23670b32 1523
ab9412ba 1524 reg = PCH_TRANSCONF(pipe);
040484af 1525 val = I915_READ(reg);
5f7f726d 1526 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1527
1528 if (HAS_PCH_IBX(dev_priv->dev)) {
1529 /*
1530 * make the BPC in transcoder be consistent with
1531 * that in pipeconf reg.
1532 */
dfd07d72
DV		 1533 val &= ~PIPECONF_BPC_MASK;
1534 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1535 }
5f7f726d
PZ		 1536
1537 val &= ~TRANS_INTERLACE_MASK;
1538 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1539 if (HAS_PCH_IBX(dev_priv->dev) &&
1540 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1541 val |= TRANS_LEGACY_INTERLACED_ILK;
1542 else
1543 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1544 else
1545 val |= TRANS_PROGRESSIVE;
1546
040484af
JB		 1547 I915_WRITE(reg, val | TRANS_ENABLE);
1548 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1549 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1550}
1551
8fb033d7 1552static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1553 enum transcoder cpu_transcoder)
040484af 1554{
8fb033d7 1555 u32 val, pipeconf_val;
8fb033d7
PZ		 1556
1557 /* PCH only available on ILK+ */
1558 BUG_ON(dev_priv->info->gen < 5);
1559
8fb033d7 1560 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1561 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1562 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1563
223a6fdf
PZ		 1564 /* Workaround: set timing override bit. */
1565 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1566 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1567 I915_WRITE(_TRANSA_CHICKEN2, val);
1568
25f3ef11 1569 val = TRANS_ENABLE;
937bb610 1570 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1571
9a76b1c6
PZ		 1572 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1573 PIPECONF_INTERLACED_ILK)
a35f2679 1574 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1575 else
1576 val |= TRANS_PROGRESSIVE;
1577
ab9412ba
DV		 1578 I915_WRITE(LPT_TRANSCONF, val);
1579 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1580 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1581}
1582
b8a4f404
PZ		 1583static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1584 enum pipe pipe)
040484af 1585{
23670b32
DV		 1586 struct drm_device *dev = dev_priv->dev;
1587 uint32_t reg, val;
040484af
JB		 1588
1589 /* FDI relies on the transcoder */
1590 assert_fdi_tx_disabled(dev_priv, pipe);
1591 assert_fdi_rx_disabled(dev_priv, pipe);
1592
291906f1
JB		 1593 /* Ports must be off as well */
1594 assert_pch_ports_disabled(dev_priv, pipe);
1595
ab9412ba 1596 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1597 val = I915_READ(reg);
1598 val &= ~TRANS_ENABLE;
1599 I915_WRITE(reg, val);
1600 /* wait for PCH transcoder off, transcoder state */
1601 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1602 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1603
1604 if (!HAS_PCH_IBX(dev)) {
1605 /* Workaround: Clear the timing override chicken bit again. */
1606 reg = TRANS_CHICKEN2(pipe);
1607 val = I915_READ(reg);
1608 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1609 I915_WRITE(reg, val);
1610 }
040484af
JB		 1611}
1612
ab4d966c 1613static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1614{
8fb033d7
PZ		 1615 u32 val;
1616
ab9412ba 1617 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1618 val &= ~TRANS_ENABLE;
ab9412ba 1619 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1620 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1621 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1622 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1623
1624 /* Workaround: clear timing override bit. */
1625 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1626 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1627 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1628}
1629
b24e7179 1630/**
309cfea8 1631 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe to enable
040484af 1634 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1635 *
1636 * Enable @pipe, making sure that various hardware specific requirements
1637 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1638 *
1639 * @pipe should be %PIPE_A or %PIPE_B.
1640 *
1641 * Will wait until the pipe is actually running (i.e. first vblank) before
1642 * returning.
1643 */
040484af
JB		 1644static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1645 bool pch_port)
b24e7179 1646{
702e7a56
PZ		 1647 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1648 pipe);
1a240d4d 1649 enum pipe pch_transcoder;
b24e7179
JB		 1650 int reg;
1651 u32 val;
1652
58c6eaa2
DV		 1653 assert_planes_disabled(dev_priv, pipe);
1654 assert_sprites_disabled(dev_priv, pipe);
1655
681e5811 1656 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1657 pch_transcoder = TRANSCODER_A;
1658 else
1659 pch_transcoder = pipe;
1660
b24e7179
JB		 1661 /*
1662 * A pipe without a PLL won't actually be able to drive bits from
1663 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1664 * need the check.
1665 */
1666 if (!HAS_PCH_SPLIT(dev_priv->dev))
1667 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1668 else {
1669 if (pch_port) {
1670 /* if driving the PCH, we need FDI enabled */
cc391bbb 1671 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1672 assert_fdi_tx_pll_enabled(dev_priv,
1673 (enum pipe) cpu_transcoder);
040484af
JB		 1674 }
1675 /* FIXME: assert CPU port conditions for SNB+ */
1676 }
b24e7179 1677
702e7a56 1678 reg = PIPECONF(cpu_transcoder);
b24e7179 1679 val = I915_READ(reg);
00d70b15
CW		 1680 if (val & PIPECONF_ENABLE)
1681 return;
1682
1683 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1684 intel_wait_for_vblank(dev_priv->dev, pipe);
1685}
1686
1687/**
309cfea8 1688 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1689 * @dev_priv: i915 private structure
1690 * @pipe: pipe to disable
1691 *
1692 * Disable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe has shut down before returning.
1698 */
1699static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1700 enum pipe pipe)
1701{
702e7a56
PZ		 1702 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1703 pipe);
b24e7179
JB		 1704 int reg;
1705 u32 val;
1706
1707 /*
1708 * Make sure planes won't keep trying to pump pixels to us,
1709 * or we might hang the display.
1710 */
1711 assert_planes_disabled(dev_priv, pipe);
19332d7a 1712 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1713
1714 /* Don't disable pipe A or pipe A PLLs if needed */
1715 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1716 return;
1717
702e7a56 1718 reg = PIPECONF(cpu_transcoder);
b24e7179 1719 val = I915_READ(reg);
00d70b15
CW		 1720 if ((val & PIPECONF_ENABLE) == 0)
1721 return;
1722
1723 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1724 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1725}
1726
d74362c9
KP		 1727/*
1728 * Plane regs are double buffered, going from enabled->disabled needs a
1729 * trigger in order to latch. The display address reg provides this.
1730 */
6f1d69b0 1731void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1732 enum plane plane)
1733{
14f86147
DL		 1734 if (dev_priv->info->gen >= 4)
1735 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1736 else
1737 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1738}
1739
b24e7179
JB		 1740/**
1741 * intel_enable_plane - enable a display plane on a given pipe
1742 * @dev_priv: i915 private structure
1743 * @plane: plane to enable
1744 * @pipe: pipe being fed
1745 *
1746 * Enable @plane on @pipe, making sure that @pipe is running first.
1747 */
1748static void intel_enable_plane(struct drm_i915_private *dev_priv,
1749 enum plane plane, enum pipe pipe)
1750{
1751 int reg;
1752 u32 val;
1753
1754 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1755 assert_pipe_enabled(dev_priv, pipe);
1756
1757 reg = DSPCNTR(plane);
1758 val = I915_READ(reg);
00d70b15
CW		 1759 if (val & DISPLAY_PLANE_ENABLE)
1760 return;
1761
1762 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1763 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1764 intel_wait_for_vblank(dev_priv->dev, pipe);
1765}
1766
b24e7179
JB		 1767/**
1768 * intel_disable_plane - disable a display plane
1769 * @dev_priv: i915 private structure
1770 * @plane: plane to disable
1771 * @pipe: pipe consuming the data
1772 *
1773 * Disable @plane; should be an independent operation.
1774 */
1775static void intel_disable_plane(struct drm_i915_private *dev_priv,
1776 enum plane plane, enum pipe pipe)
1777{
1778 int reg;
1779 u32 val;
1780
1781 reg = DSPCNTR(plane);
1782 val = I915_READ(reg);
00d70b15
CW		 1783 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1784 return;
1785
1786 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1787 intel_flush_display_plane(dev_priv, plane);
1788 intel_wait_for_vblank(dev_priv->dev, pipe);
1789}
1790
693db184
CW		 1791static bool need_vtd_wa(struct drm_device *dev)
1792{
1793#ifdef CONFIG_INTEL_IOMMU
1794 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1795 return true;
1796#endif
1797 return false;
1798}
1799
127bd2ac 1800int
48b956c5 1801intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1802 struct drm_i915_gem_object *obj,
919926ae 1803 struct intel_ring_buffer *pipelined)
6b95a207 1804{
ce453d81 1805 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1806 u32 alignment;
1807 int ret;
1808
05394f39 1809 switch (obj->tiling_mode) {
6b95a207 1810 case I915_TILING_NONE:
534843da
CW		 1811 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1812 alignment = 128 * 1024;
a6c45cf0 1813 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1814 alignment = 4 * 1024;
1815 else
1816 alignment = 64 * 1024;
6b95a207
KH		 1817 break;
1818 case I915_TILING_X:
1819 /* pin() will align the object as required by fence */
1820 alignment = 0;
1821 break;
1822 case I915_TILING_Y:
8bb6e959
DV		 1823 /* Despite that we check this in framebuffer_init userspace can
1824 * screw us over and change the tiling after the fact. Only
1825 * pinned buffers can't change their tiling. */
1826 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1827 return -EINVAL;
1828 default:
1829 BUG();
1830 }
1831
693db184
CW		 1832 /* Note that the w/a also requires 64 PTE of padding following the
1833 * bo. We currently fill all unused PTE with the shadow page and so
1834 * we should always have valid PTE following the scanout preventing
1835 * the VT-d warning.
1836 */
1837 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1838 alignment = 256 * 1024;
1839
ce453d81 1840 dev_priv->mm.interruptible = false;
2da3b9b9 1841 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1842 if (ret)
ce453d81 1843 goto err_interruptible;
6b95a207
KH		 1844
1845 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1846 * fence, whereas 965+ only requires a fence if using
1847 * framebuffer compression. For simplicity, we always install
1848 * a fence as the cost is not that onerous.
1849 */
06d98131 1850 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1851 if (ret)
1852 goto err_unpin;
1690e1eb 1853
9a5a53b3 1854 i915_gem_object_pin_fence(obj);
6b95a207 1855
ce453d81 1856 dev_priv->mm.interruptible = true;
6b95a207 1857 return 0;
48b956c5
CW		 1858
1859err_unpin:
1860 i915_gem_object_unpin(obj);
ce453d81
CW		 1861err_interruptible:
1862 dev_priv->mm.interruptible = true;
48b956c5 1863 return ret;
6b95a207
KH		 1864}
1865
1690e1eb
CW		 1866void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1867{
1868 i915_gem_object_unpin_fence(obj);
1869 i915_gem_object_unpin(obj);
1870}
1871
c2c75131
DV		 1872/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1873 * is assumed to be a power-of-two. */
bc752862
CW		 1874unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1875 unsigned int tiling_mode,
1876 unsigned int cpp,
1877 unsigned int pitch)
c2c75131 1878{
bc752862
CW		 1879 if (tiling_mode != I915_TILING_NONE) {
1880 unsigned int tile_rows, tiles;
c2c75131 1881
bc752862
CW		 1882 tile_rows = *y / 8;
1883 *y %= 8;
c2c75131 1884
bc752862
CW		 1885 tiles = *x / (512/cpp);
1886 *x %= 512/cpp;
1887
1888 return tile_rows * pitch * 8 + tiles * 4096;
1889 } else {
1890 unsigned int offset;
1891
1892 offset = *y * pitch + *x * cpp;
1893 *y = 0;
1894 *x = (offset & 4095) / cpp;
1895 return offset & -4096;
1896 }
c2c75131
DV		 1897}
1898
17638cd6
JB		 1899static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1900 int x, int y)
81255565
JB		 1901{
1902 struct drm_device *dev = crtc->dev;
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1905 struct intel_framebuffer *intel_fb;
05394f39 1906 struct drm_i915_gem_object *obj;
81255565 1907 int plane = intel_crtc->plane;
e506a0c6 1908 unsigned long linear_offset;
81255565 1909 u32 dspcntr;
5eddb70b 1910 u32 reg;
81255565
JB		 1911
1912 switch (plane) {
1913 case 0:
1914 case 1:
1915 break;
1916 default:
84f44ce7 1917 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1918 return -EINVAL;
1919 }
1920
1921 intel_fb = to_intel_framebuffer(fb);
1922 obj = intel_fb->obj;
81255565 1923
5eddb70b
CW		 1924 reg = DSPCNTR(plane);
1925 dspcntr = I915_READ(reg);
81255565
JB		 1926 /* Mask out pixel format bits in case we change it */
1927 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1928 switch (fb->pixel_format) {
1929 case DRM_FORMAT_C8:
81255565
JB		 1930 dspcntr |= DISPPLANE_8BPP;
1931 break;
57779d06
VS		 1932 case DRM_FORMAT_XRGB1555:
1933 case DRM_FORMAT_ARGB1555:
1934 dspcntr |= DISPPLANE_BGRX555;
81255565 1935 break;
57779d06
VS		 1936 case DRM_FORMAT_RGB565:
1937 dspcntr |= DISPPLANE_BGRX565;
1938 break;
1939 case DRM_FORMAT_XRGB8888:
1940 case DRM_FORMAT_ARGB8888:
1941 dspcntr |= DISPPLANE_BGRX888;
1942 break;
1943 case DRM_FORMAT_XBGR8888:
1944 case DRM_FORMAT_ABGR8888:
1945 dspcntr |= DISPPLANE_RGBX888;
1946 break;
1947 case DRM_FORMAT_XRGB2101010:
1948 case DRM_FORMAT_ARGB2101010:
1949 dspcntr |= DISPPLANE_BGRX101010;
1950 break;
1951 case DRM_FORMAT_XBGR2101010:
1952 case DRM_FORMAT_ABGR2101010:
1953 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1954 break;
1955 default:
baba133a 1956 BUG();
81255565 1957 }
57779d06 1958
a6c45cf0 1959 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1960 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1961 dspcntr |= DISPPLANE_TILED;
1962 else
1963 dspcntr &= ~DISPPLANE_TILED;
1964 }
1965
de1aa629
VS		 1966 if (IS_G4X(dev))
1967 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1968
5eddb70b 1969 I915_WRITE(reg, dspcntr);
81255565 1970
e506a0c6 1971 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1972
c2c75131
DV		 1973 if (INTEL_INFO(dev)->gen >= 4) {
1974 intel_crtc->dspaddr_offset =
bc752862
CW		 1975 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1976 fb->bits_per_pixel / 8,
1977 fb->pitches[0]);
c2c75131
DV		 1978 linear_offset -= intel_crtc->dspaddr_offset;
1979 } else {
e506a0c6 1980 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1981 }
e506a0c6
DV		 1982
1983 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1984 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1985 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1986 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1987 I915_MODIFY_DISPBASE(DSPSURF(plane),
1988 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1989 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1990 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1991 } else
e506a0c6 1992 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1993 POSTING_READ(reg);
81255565 1994
17638cd6
JB		 1995 return 0;
1996}
1997
1998static int ironlake_update_plane(struct drm_crtc *crtc,
1999 struct drm_framebuffer *fb, int x, int y)
2000{
2001 struct drm_device *dev = crtc->dev;
2002 struct drm_i915_private *dev_priv = dev->dev_private;
2003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2004 struct intel_framebuffer *intel_fb;
2005 struct drm_i915_gem_object *obj;
2006 int plane = intel_crtc->plane;
e506a0c6 2007 unsigned long linear_offset;
17638cd6
JB		 2008 u32 dspcntr;
2009 u32 reg;
2010
2011 switch (plane) {
2012 case 0:
2013 case 1:
27f8227b 2014 case 2:
17638cd6
JB		 2015 break;
2016 default:
84f44ce7 2017 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2018 return -EINVAL;
2019 }
2020
2021 intel_fb = to_intel_framebuffer(fb);
2022 obj = intel_fb->obj;
2023
2024 reg = DSPCNTR(plane);
2025 dspcntr = I915_READ(reg);
2026 /* Mask out pixel format bits in case we change it */
2027 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2028 switch (fb->pixel_format) {
2029 case DRM_FORMAT_C8:
17638cd6
JB		 2030 dspcntr |= DISPPLANE_8BPP;
2031 break;
57779d06
VS		 2032 case DRM_FORMAT_RGB565:
2033 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2034 break;
57779d06
VS		 2035 case DRM_FORMAT_XRGB8888:
2036 case DRM_FORMAT_ARGB8888:
2037 dspcntr |= DISPPLANE_BGRX888;
2038 break;
2039 case DRM_FORMAT_XBGR8888:
2040 case DRM_FORMAT_ABGR8888:
2041 dspcntr |= DISPPLANE_RGBX888;
2042 break;
2043 case DRM_FORMAT_XRGB2101010:
2044 case DRM_FORMAT_ARGB2101010:
2045 dspcntr |= DISPPLANE_BGRX101010;
2046 break;
2047 case DRM_FORMAT_XBGR2101010:
2048 case DRM_FORMAT_ABGR2101010:
2049 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2050 break;
2051 default:
baba133a 2052 BUG();
17638cd6
JB		 2053 }
2054
2055 if (obj->tiling_mode != I915_TILING_NONE)
2056 dspcntr |= DISPPLANE_TILED;
2057 else
2058 dspcntr &= ~DISPPLANE_TILED;
2059
2060 /* must disable */
2061 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2062
2063 I915_WRITE(reg, dspcntr);
2064
e506a0c6 2065 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2066 intel_crtc->dspaddr_offset =
bc752862
CW		 2067 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2068 fb->bits_per_pixel / 8,
2069 fb->pitches[0]);
c2c75131 2070 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2071
e506a0c6
DV		 2072 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2073 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2074 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2075 I915_MODIFY_DISPBASE(DSPSURF(plane),
2076 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2077 if (IS_HASWELL(dev)) {
2078 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2079 } else {
2080 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2081 I915_WRITE(DSPLINOFF(plane), linear_offset);
2082 }
17638cd6
JB		 2083 POSTING_READ(reg);
2084
2085 return 0;
2086}
2087
2088/* Assume fb object is pinned & idle & fenced and just update base pointers */
2089static int
2090intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2091 int x, int y, enum mode_set_atomic state)
2092{
2093 struct drm_device *dev = crtc->dev;
2094 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2095
6b8e6ed0
CW		 2096 if (dev_priv->display.disable_fbc)
2097 dev_priv->display.disable_fbc(dev);
3dec0095 2098 intel_increase_pllclock(crtc);
81255565 2099
6b8e6ed0 2100 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2101}
2102
96a02917
VS		 2103void intel_display_handle_reset(struct drm_device *dev)
2104{
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 struct drm_crtc *crtc;
2107
2108 /*
2109 * Flips in the rings have been nuked by the reset,
2110 * so complete all pending flips so that user space
2111 * will get its events and not get stuck.
2112 *
2113 * Also update the base address of all primary
2114 * planes to the the last fb to make sure we're
2115 * showing the correct fb after a reset.
2116 *
2117 * Need to make two loops over the crtcs so that we
2118 * don't try to grab a crtc mutex before the
2119 * pending_flip_queue really got woken up.
2120 */
2121
2122 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2124 enum plane plane = intel_crtc->plane;
2125
2126 intel_prepare_page_flip(dev, plane);
2127 intel_finish_page_flip_plane(dev, plane);
2128 }
2129
2130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132
2133 mutex_lock(&crtc->mutex);
2134 if (intel_crtc->active)
2135 dev_priv->display.update_plane(crtc, crtc->fb,
2136 crtc->x, crtc->y);
2137 mutex_unlock(&crtc->mutex);
2138 }
2139}
2140
14667a4b
CW		 2141static int
2142intel_finish_fb(struct drm_framebuffer *old_fb)
2143{
2144 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2145 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2146 bool was_interruptible = dev_priv->mm.interruptible;
2147 int ret;
2148
14667a4b
CW		 2149 /* Big Hammer, we also need to ensure that any pending
2150 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2151 * current scanout is retired before unpinning the old
2152 * framebuffer.
2153 *
2154 * This should only fail upon a hung GPU, in which case we
2155 * can safely continue.
2156 */
2157 dev_priv->mm.interruptible = false;
2158 ret = i915_gem_object_finish_gpu(obj);
2159 dev_priv->mm.interruptible = was_interruptible;
2160
2161 return ret;
2162}
2163
198598d0
VS		 2164static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2165{
2166 struct drm_device *dev = crtc->dev;
2167 struct drm_i915_master_private *master_priv;
2168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169
2170 if (!dev->primary->master)
2171 return;
2172
2173 master_priv = dev->primary->master->driver_priv;
2174 if (!master_priv->sarea_priv)
2175 return;
2176
2177 switch (intel_crtc->pipe) {
2178 case 0:
2179 master_priv->sarea_priv->pipeA_x = x;
2180 master_priv->sarea_priv->pipeA_y = y;
2181 break;
2182 case 1:
2183 master_priv->sarea_priv->pipeB_x = x;
2184 master_priv->sarea_priv->pipeB_y = y;
2185 break;
2186 default:
2187 break;
2188 }
2189}
2190
5c3b82e2 2191static int
3c4fdcfb 2192intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2193 struct drm_framebuffer *fb)
79e53945
JB		 2194{
2195 struct drm_device *dev = crtc->dev;
6b8e6ed0 2196 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2198 struct drm_framebuffer *old_fb;
5c3b82e2 2199 int ret;
79e53945
JB		 2200
2201 /* no fb bound */
94352cf9 2202 if (!fb) {
a5071c2f 2203 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2204 return 0;
2205 }
2206
7eb552ae 2207 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2208 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2209 plane_name(intel_crtc->plane),
2210 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2211 return -EINVAL;
79e53945
JB		 2212 }
2213
5c3b82e2 2214 mutex_lock(&dev->struct_mutex);
265db958 2215 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2216 to_intel_framebuffer(fb)->obj,
919926ae 2217 NULL);
5c3b82e2
CW		 2218 if (ret != 0) {
2219 mutex_unlock(&dev->struct_mutex);
a5071c2f 2220 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2221 return ret;
2222 }
79e53945 2223
4d6a3e63
JB		 2224 /* Update pipe size and adjust fitter if needed */
2225 if (i915_fastboot) {
2226 I915_WRITE(PIPESRC(intel_crtc->pipe),
2227 ((crtc->mode.hdisplay - 1) << 16) |
2228 (crtc->mode.vdisplay - 1));
2229 if (!intel_crtc->config.pch_pfit.size &&
2230 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2231 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2232 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2233 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2234 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2235 }
2236 }
2237
94352cf9 2238 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2239 if (ret) {
94352cf9 2240 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2241 mutex_unlock(&dev->struct_mutex);
a5071c2f 2242 DRM_ERROR("failed to update base address\n");
4e6cfefc 2243 return ret;
79e53945 2244 }
3c4fdcfb 2245
94352cf9
DV		 2246 old_fb = crtc->fb;
2247 crtc->fb = fb;
6c4c86f5
DV		 2248 crtc->x = x;
2249 crtc->y = y;
94352cf9 2250
b7f1de28 2251 if (old_fb) {
d7697eea
DV		 2252 if (intel_crtc->active && old_fb != fb)
2253 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2254 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2255 }
652c393a 2256
6b8e6ed0 2257 intel_update_fbc(dev);
5c3b82e2 2258 mutex_unlock(&dev->struct_mutex);
79e53945 2259
198598d0 2260 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2261
2262 return 0;
79e53945
JB		 2263}
2264
5e84e1a4
ZW		 2265static void intel_fdi_normal_train(struct drm_crtc *crtc)
2266{
2267 struct drm_device *dev = crtc->dev;
2268 struct drm_i915_private *dev_priv = dev->dev_private;
2269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2270 int pipe = intel_crtc->pipe;
2271 u32 reg, temp;
2272
2273 /* enable normal train */
2274 reg = FDI_TX_CTL(pipe);
2275 temp = I915_READ(reg);
61e499bf 2276 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2277 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2278 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2279 } else {
2280 temp &= ~FDI_LINK_TRAIN_NONE;
2281 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2282 }
5e84e1a4
ZW		 2283 I915_WRITE(reg, temp);
2284
2285 reg = FDI_RX_CTL(pipe);
2286 temp = I915_READ(reg);
2287 if (HAS_PCH_CPT(dev)) {
2288 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2289 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2290 } else {
2291 temp &= ~FDI_LINK_TRAIN_NONE;
2292 temp |= FDI_LINK_TRAIN_NONE;
2293 }
2294 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2295
2296 /* wait one idle pattern time */
2297 POSTING_READ(reg);
2298 udelay(1000);
357555c0
JB		 2299
2300 /* IVB wants error correction enabled */
2301 if (IS_IVYBRIDGE(dev))
2302 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2303 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2304}
2305
1e833f40
DV		 2306static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2307{
2308 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2309}
2310
01a415fd
DV		 2311static void ivb_modeset_global_resources(struct drm_device *dev)
2312{
2313 struct drm_i915_private *dev_priv = dev->dev_private;
2314 struct intel_crtc *pipe_B_crtc =
2315 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2316 struct intel_crtc *pipe_C_crtc =
2317 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2318 uint32_t temp;
2319
1e833f40
DV		 2320 /*
2321 * When everything is off disable fdi C so that we could enable fdi B
2322 * with all lanes. Note that we don't care about enabled pipes without
2323 * an enabled pch encoder.
2324 */
2325 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2326 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2327 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2328 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2329
2330 temp = I915_READ(SOUTH_CHICKEN1);
2331 temp &= ~FDI_BC_BIFURCATION_SELECT;
2332 DRM_DEBUG_KMS("disabling fdi C rx\n");
2333 I915_WRITE(SOUTH_CHICKEN1, temp);
2334 }
2335}
2336
8db9d77b
ZW		 2337/* The FDI link training functions for ILK/Ibexpeak. */
2338static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2339{
2340 struct drm_device *dev = crtc->dev;
2341 struct drm_i915_private *dev_priv = dev->dev_private;
2342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2343 int pipe = intel_crtc->pipe;
0fc932b8 2344 int plane = intel_crtc->plane;
5eddb70b 2345 u32 reg, temp, tries;
8db9d77b 2346
0fc932b8
JB		 2347 /* FDI needs bits from pipe & plane first */
2348 assert_pipe_enabled(dev_priv, pipe);
2349 assert_plane_enabled(dev_priv, plane);
2350
e1a44743
AJ		 2351 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2352 for train result */
5eddb70b
CW		 2353 reg = FDI_RX_IMR(pipe);
2354 temp = I915_READ(reg);
e1a44743
AJ		 2355 temp &= ~FDI_RX_SYMBOL_LOCK;
2356 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2357 I915_WRITE(reg, temp);
2358 I915_READ(reg);
e1a44743
AJ		 2359 udelay(150);
2360
8db9d77b 2361 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2362 reg = FDI_TX_CTL(pipe);
2363 temp = I915_READ(reg);
627eb5a3
DV		 2364 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2365 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2366 temp &= ~FDI_LINK_TRAIN_NONE;
2367 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2368 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2369
5eddb70b
CW		 2370 reg = FDI_RX_CTL(pipe);
2371 temp = I915_READ(reg);
8db9d77b
ZW		 2372 temp &= ~FDI_LINK_TRAIN_NONE;
2373 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2374 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2375
2376 POSTING_READ(reg);
8db9d77b
ZW		 2377 udelay(150);
2378
5b2adf89 2379 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2380 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2381 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2382 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2383
5eddb70b 2384 reg = FDI_RX_IIR(pipe);
e1a44743 2385 for (tries = 0; tries < 5; tries++) {
5eddb70b 2386 temp = I915_READ(reg);
8db9d77b
ZW		 2387 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2388
2389 if ((temp & FDI_RX_BIT_LOCK)) {
2390 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2391 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2392 break;
2393 }
8db9d77b 2394 }
e1a44743 2395 if (tries == 5)
5eddb70b 2396 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2397
2398 /* Train 2 */
5eddb70b
CW		 2399 reg = FDI_TX_CTL(pipe);
2400 temp = I915_READ(reg);
8db9d77b
ZW		 2401 temp &= ~FDI_LINK_TRAIN_NONE;
2402 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2403 I915_WRITE(reg, temp);
8db9d77b 2404
5eddb70b
CW		 2405 reg = FDI_RX_CTL(pipe);
2406 temp = I915_READ(reg);
8db9d77b
ZW		 2407 temp &= ~FDI_LINK_TRAIN_NONE;
2408 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2409 I915_WRITE(reg, temp);
8db9d77b 2410
5eddb70b
CW		 2411 POSTING_READ(reg);
2412 udelay(150);
8db9d77b 2413
5eddb70b 2414 reg = FDI_RX_IIR(pipe);
e1a44743 2415 for (tries = 0; tries < 5; tries++) {
5eddb70b 2416 temp = I915_READ(reg);
8db9d77b
ZW		 2417 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2418
2419 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2420 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2421 DRM_DEBUG_KMS("FDI train 2 done.\n");
2422 break;
2423 }
8db9d77b 2424 }
e1a44743 2425 if (tries == 5)
5eddb70b 2426 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2427
2428 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2429
8db9d77b
ZW		 2430}
2431
0206e353 2432static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2433 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2434 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2435 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2436 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2437};
2438
2439/* The FDI link training functions for SNB/Cougarpoint. */
2440static void gen6_fdi_link_train(struct drm_crtc *crtc)
2441{
2442 struct drm_device *dev = crtc->dev;
2443 struct drm_i915_private *dev_priv = dev->dev_private;
2444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2445 int pipe = intel_crtc->pipe;
fa37d39e 2446 u32 reg, temp, i, retry;
8db9d77b 2447
e1a44743
AJ		 2448 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2449 for train result */
5eddb70b
CW		 2450 reg = FDI_RX_IMR(pipe);
2451 temp = I915_READ(reg);
e1a44743
AJ		 2452 temp &= ~FDI_RX_SYMBOL_LOCK;
2453 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2454 I915_WRITE(reg, temp);
2455
2456 POSTING_READ(reg);
e1a44743
AJ		 2457 udelay(150);
2458
8db9d77b 2459 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2460 reg = FDI_TX_CTL(pipe);
2461 temp = I915_READ(reg);
627eb5a3
DV		 2462 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2463 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2464 temp &= ~FDI_LINK_TRAIN_NONE;
2465 temp |= FDI_LINK_TRAIN_PATTERN_1;
2466 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2467 /* SNB-B */
2468 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2469 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2470
d74cf324
DV		 2471 I915_WRITE(FDI_RX_MISC(pipe),
2472 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2473
5eddb70b
CW		 2474 reg = FDI_RX_CTL(pipe);
2475 temp = I915_READ(reg);
8db9d77b
ZW		 2476 if (HAS_PCH_CPT(dev)) {
2477 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2478 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2479 } else {
2480 temp &= ~FDI_LINK_TRAIN_NONE;
2481 temp |= FDI_LINK_TRAIN_PATTERN_1;
2482 }
5eddb70b
CW		 2483 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2484
2485 POSTING_READ(reg);
8db9d77b
ZW		 2486 udelay(150);
2487
0206e353 2488 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2489 reg = FDI_TX_CTL(pipe);
2490 temp = I915_READ(reg);
8db9d77b
ZW		 2491 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2492 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2493 I915_WRITE(reg, temp);
2494
2495 POSTING_READ(reg);
8db9d77b
ZW		 2496 udelay(500);
2497
fa37d39e
SP		 2498 for (retry = 0; retry < 5; retry++) {
2499 reg = FDI_RX_IIR(pipe);
2500 temp = I915_READ(reg);
2501 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2502 if (temp & FDI_RX_BIT_LOCK) {
2503 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2504 DRM_DEBUG_KMS("FDI train 1 done.\n");
2505 break;
2506 }
2507 udelay(50);
8db9d77b 2508 }
fa37d39e
SP		 2509 if (retry < 5)
2510 break;
8db9d77b
ZW		 2511 }
2512 if (i == 4)
5eddb70b 2513 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2514
2515 /* Train 2 */
5eddb70b
CW		 2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
8db9d77b
ZW		 2518 temp &= ~FDI_LINK_TRAIN_NONE;
2519 temp |= FDI_LINK_TRAIN_PATTERN_2;
2520 if (IS_GEN6(dev)) {
2521 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2522 /* SNB-B */
2523 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2524 }
5eddb70b 2525 I915_WRITE(reg, temp);
8db9d77b 2526
5eddb70b
CW		 2527 reg = FDI_RX_CTL(pipe);
2528 temp = I915_READ(reg);
8db9d77b
ZW		 2529 if (HAS_PCH_CPT(dev)) {
2530 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2531 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2532 } else {
2533 temp &= ~FDI_LINK_TRAIN_NONE;
2534 temp |= FDI_LINK_TRAIN_PATTERN_2;
2535 }
5eddb70b
CW		 2536 I915_WRITE(reg, temp);
2537
2538 POSTING_READ(reg);
8db9d77b
ZW		 2539 udelay(150);
2540
0206e353 2541 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2542 reg = FDI_TX_CTL(pipe);
2543 temp = I915_READ(reg);
8db9d77b
ZW		 2544 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2545 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2546 I915_WRITE(reg, temp);
2547
2548 POSTING_READ(reg);
8db9d77b
ZW		 2549 udelay(500);
2550
fa37d39e
SP		 2551 for (retry = 0; retry < 5; retry++) {
2552 reg = FDI_RX_IIR(pipe);
2553 temp = I915_READ(reg);
2554 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2555 if (temp & FDI_RX_SYMBOL_LOCK) {
2556 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2557 DRM_DEBUG_KMS("FDI train 2 done.\n");
2558 break;
2559 }
2560 udelay(50);
8db9d77b 2561 }
fa37d39e
SP		 2562 if (retry < 5)
2563 break;
8db9d77b
ZW		 2564 }
2565 if (i == 4)
5eddb70b 2566 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2567
2568 DRM_DEBUG_KMS("FDI train done.\n");
2569}
2570
357555c0
JB		 2571/* Manual link training for Ivy Bridge A0 parts */
2572static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2573{
2574 struct drm_device *dev = crtc->dev;
2575 struct drm_i915_private *dev_priv = dev->dev_private;
2576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2577 int pipe = intel_crtc->pipe;
2578 u32 reg, temp, i;
2579
2580 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2581 for train result */
2582 reg = FDI_RX_IMR(pipe);
2583 temp = I915_READ(reg);
2584 temp &= ~FDI_RX_SYMBOL_LOCK;
2585 temp &= ~FDI_RX_BIT_LOCK;
2586 I915_WRITE(reg, temp);
2587
2588 POSTING_READ(reg);
2589 udelay(150);
2590
01a415fd
DV		 2591 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2592 I915_READ(FDI_RX_IIR(pipe)));
2593
357555c0
JB		 2594 /* enable CPU FDI TX and PCH FDI RX */
2595 reg = FDI_TX_CTL(pipe);
2596 temp = I915_READ(reg);
627eb5a3
DV		 2597 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2598 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2599 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2600 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2603 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2604 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2605
d74cf324
DV		 2606 I915_WRITE(FDI_RX_MISC(pipe),
2607 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2608
357555c0
JB		 2609 reg = FDI_RX_CTL(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_LINK_TRAIN_AUTO;
2612 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2613 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2614 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2615 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2616
2617 POSTING_READ(reg);
2618 udelay(150);
2619
0206e353 2620 for (i = 0; i < 4; i++) {
357555c0
JB		 2621 reg = FDI_TX_CTL(pipe);
2622 temp = I915_READ(reg);
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 temp |= snb_b_fdi_train_param[i];
2625 I915_WRITE(reg, temp);
2626
2627 POSTING_READ(reg);
2628 udelay(500);
2629
2630 reg = FDI_RX_IIR(pipe);
2631 temp = I915_READ(reg);
2632 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2633
2634 if (temp & FDI_RX_BIT_LOCK ||
2635 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2636 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2637 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2638 break;
2639 }
2640 }
2641 if (i == 4)
2642 DRM_ERROR("FDI train 1 fail!\n");
2643
2644 /* Train 2 */
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2648 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2649 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2650 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2651 I915_WRITE(reg, temp);
2652
2653 reg = FDI_RX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2656 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2657 I915_WRITE(reg, temp);
2658
2659 POSTING_READ(reg);
2660 udelay(150);
2661
0206e353 2662 for (i = 0; i < 4; i++) {
357555c0
JB		 2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2666 temp |= snb_b_fdi_train_param[i];
2667 I915_WRITE(reg, temp);
2668
2669 POSTING_READ(reg);
2670 udelay(500);
2671
2672 reg = FDI_RX_IIR(pipe);
2673 temp = I915_READ(reg);
2674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2675
2676 if (temp & FDI_RX_SYMBOL_LOCK) {
2677 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2678 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2679 break;
2680 }
2681 }
2682 if (i == 4)
2683 DRM_ERROR("FDI train 2 fail!\n");
2684
2685 DRM_DEBUG_KMS("FDI train done.\n");
2686}
2687
88cefb6c 2688static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2689{
88cefb6c 2690 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2691 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2692 int pipe = intel_crtc->pipe;
5eddb70b 2693 u32 reg, temp;
79e53945 2694
c64e311e 2695
c98e9dcf 2696 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2697 reg = FDI_RX_CTL(pipe);
2698 temp = I915_READ(reg);
627eb5a3
DV		 2699 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2700 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2701 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2702 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2703
2704 POSTING_READ(reg);
c98e9dcf
JB		 2705 udelay(200);
2706
2707 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2708 temp = I915_READ(reg);
2709 I915_WRITE(reg, temp | FDI_PCDCLK);
2710
2711 POSTING_READ(reg);
c98e9dcf
JB		 2712 udelay(200);
2713
20749730
PZ		 2714 /* Enable CPU FDI TX PLL, always on for Ironlake */
2715 reg = FDI_TX_CTL(pipe);
2716 temp = I915_READ(reg);
2717 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2718 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2719
20749730
PZ		 2720 POSTING_READ(reg);
2721 udelay(100);
6be4a607 2722 }
0e23b99d
JB		 2723}
2724
88cefb6c
DV		 2725static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2726{
2727 struct drm_device *dev = intel_crtc->base.dev;
2728 struct drm_i915_private *dev_priv = dev->dev_private;
2729 int pipe = intel_crtc->pipe;
2730 u32 reg, temp;
2731
2732 /* Switch from PCDclk to Rawclk */
2733 reg = FDI_RX_CTL(pipe);
2734 temp = I915_READ(reg);
2735 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2736
2737 /* Disable CPU FDI TX PLL */
2738 reg = FDI_TX_CTL(pipe);
2739 temp = I915_READ(reg);
2740 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2741
2742 POSTING_READ(reg);
2743 udelay(100);
2744
2745 reg = FDI_RX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2748
2749 /* Wait for the clocks to turn off. */
2750 POSTING_READ(reg);
2751 udelay(100);
2752}
2753
0fc932b8
JB		 2754static void ironlake_fdi_disable(struct drm_crtc *crtc)
2755{
2756 struct drm_device *dev = crtc->dev;
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2759 int pipe = intel_crtc->pipe;
2760 u32 reg, temp;
2761
2762 /* disable CPU FDI tx and PCH FDI rx */
2763 reg = FDI_TX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2766 POSTING_READ(reg);
2767
2768 reg = FDI_RX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 temp &= ~(0x7 << 16);
dfd07d72 2771 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2772 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2773
2774 POSTING_READ(reg);
2775 udelay(100);
2776
2777 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2778 if (HAS_PCH_IBX(dev)) {
2779 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2780 }
0fc932b8
JB		 2781
2782 /* still set train pattern 1 */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 temp &= ~FDI_LINK_TRAIN_NONE;
2786 temp |= FDI_LINK_TRAIN_PATTERN_1;
2787 I915_WRITE(reg, temp);
2788
2789 reg = FDI_RX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 if (HAS_PCH_CPT(dev)) {
2792 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2793 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2794 } else {
2795 temp &= ~FDI_LINK_TRAIN_NONE;
2796 temp |= FDI_LINK_TRAIN_PATTERN_1;
2797 }
2798 /* BPC in FDI rx is consistent with that in PIPECONF */
2799 temp &= ~(0x07 << 16);
dfd07d72 2800 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2801 I915_WRITE(reg, temp);
2802
2803 POSTING_READ(reg);
2804 udelay(100);
2805}
2806
5bb61643
CW		 2807static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2808{
2809 struct drm_device *dev = crtc->dev;
2810 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2812 unsigned long flags;
2813 bool pending;
2814
10d83730
VS		 2815 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2816 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2817 return false;
2818
2819 spin_lock_irqsave(&dev->event_lock, flags);
2820 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2821 spin_unlock_irqrestore(&dev->event_lock, flags);
2822
2823 return pending;
2824}
2825
e6c3a2a6
CW		 2826static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2827{
0f91128d 2828 struct drm_device *dev = crtc->dev;
5bb61643 2829 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2830
2831 if (crtc->fb == NULL)
2832 return;
2833
2c10d571
DV		 2834 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2835
5bb61643
CW		 2836 wait_event(dev_priv->pending_flip_queue,
2837 !intel_crtc_has_pending_flip(crtc));
2838
0f91128d
CW		 2839 mutex_lock(&dev->struct_mutex);
2840 intel_finish_fb(crtc->fb);
2841 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2842}
2843
e615efe4
ED		 2844/* Program iCLKIP clock to the desired frequency */
2845static void lpt_program_iclkip(struct drm_crtc *crtc)
2846{
2847 struct drm_device *dev = crtc->dev;
2848 struct drm_i915_private *dev_priv = dev->dev_private;
2849 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2850 u32 temp;
2851
09153000
DV		 2852 mutex_lock(&dev_priv->dpio_lock);
2853
e615efe4
ED		 2854 /* It is necessary to ungate the pixclk gate prior to programming
2855 * the divisors, and gate it back when it is done.
2856 */
2857 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2858
2859 /* Disable SSCCTL */
2860 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2861 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2862 SBI_SSCCTL_DISABLE,
2863 SBI_ICLK);
e615efe4
ED		 2864
2865 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2866 if (crtc->mode.clock == 20000) {
2867 auxdiv = 1;
2868 divsel = 0x41;
2869 phaseinc = 0x20;
2870 } else {
2871 /* The iCLK virtual clock root frequency is in MHz,
2872 * but the crtc->mode.clock in in KHz. To get the divisors,
2873 * it is necessary to divide one by another, so we
2874 * convert the virtual clock precision to KHz here for higher
2875 * precision.
2876 */
2877 u32 iclk_virtual_root_freq = 172800 * 1000;
2878 u32 iclk_pi_range = 64;
2879 u32 desired_divisor, msb_divisor_value, pi_value;
2880
2881 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2882 msb_divisor_value = desired_divisor / iclk_pi_range;
2883 pi_value = desired_divisor % iclk_pi_range;
2884
2885 auxdiv = 0;
2886 divsel = msb_divisor_value - 2;
2887 phaseinc = pi_value;
2888 }
2889
2890 /* This should not happen with any sane values */
2891 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2892 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2893 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2894 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2895
2896 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2897 crtc->mode.clock,
2898 auxdiv,
2899 divsel,
2900 phasedir,
2901 phaseinc);
2902
2903 /* Program SSCDIVINTPHASE6 */
988d6ee8 2904 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2905 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2906 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2907 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2908 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2909 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2910 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2911 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2912
2913 /* Program SSCAUXDIV */
988d6ee8 2914 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2915 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2916 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2917 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2918
2919 /* Enable modulator and associated divider */
988d6ee8 2920 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2921 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2922 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2923
2924 /* Wait for initialization time */
2925 udelay(24);
2926
2927 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2928
2929 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2930}
2931
275f01b2
DV		 2932static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2933 enum pipe pch_transcoder)
2934{
2935 struct drm_device *dev = crtc->base.dev;
2936 struct drm_i915_private *dev_priv = dev->dev_private;
2937 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2938
2939 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2940 I915_READ(HTOTAL(cpu_transcoder)));
2941 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2942 I915_READ(HBLANK(cpu_transcoder)));
2943 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2944 I915_READ(HSYNC(cpu_transcoder)));
2945
2946 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2947 I915_READ(VTOTAL(cpu_transcoder)));
2948 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2949 I915_READ(VBLANK(cpu_transcoder)));
2950 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2951 I915_READ(VSYNC(cpu_transcoder)));
2952 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2953 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2954}
2955
f67a559d
JB		 2956/*
2957 * Enable PCH resources required for PCH ports:
2958 * - PCH PLLs
2959 * - FDI training & RX/TX
2960 * - update transcoder timings
2961 * - DP transcoding bits
2962 * - transcoder
2963 */
2964static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2965{
2966 struct drm_device *dev = crtc->dev;
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2969 int pipe = intel_crtc->pipe;
ee7b9f93 2970 u32 reg, temp;
2c07245f 2971
ab9412ba 2972 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2973
cd986abb
DV		 2974 /* Write the TU size bits before fdi link training, so that error
2975 * detection works. */
2976 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2977 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2978
c98e9dcf 2979 /* For PCH output, training FDI link */
674cf967 2980 dev_priv->display.fdi_link_train(crtc);
2c07245f 2981
572deb37
DV		 2982 /* XXX: pch pll's can be enabled any time before we enable the PCH
2983 * transcoder, and we actually should do this to not upset any PCH
2984 * transcoder that already use the clock when we share it.
2985 *
e72f9fbf
DV		 2986 * Note that enable_shared_dpll tries to do the right thing, but
2987 * get_shared_dpll unconditionally resets the pll - we need that to have
2988 * the right LVDS enable sequence. */
2989 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2990
303b81e0 2991 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2992 u32 sel;
4b645f14 2993
c98e9dcf 2994 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2995 temp |= TRANS_DPLL_ENABLE(pipe);
2996 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2997 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2998 temp |= sel;
2999 else
3000 temp &= ~sel;
c98e9dcf 3001 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3002 }
5eddb70b 3003
d9b6cb56
JB		 3004 /* set transcoder timing, panel must allow it */
3005 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3006 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3007
303b81e0 3008 intel_fdi_normal_train(crtc);
5e84e1a4 3009
c98e9dcf
JB		 3010 /* For PCH DP, enable TRANS_DP_CTL */
3011 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3012 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3013 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3014 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3015 reg = TRANS_DP_CTL(pipe);
3016 temp = I915_READ(reg);
3017 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3018 TRANS_DP_SYNC_MASK |
3019 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3020 temp |= (TRANS_DP_OUTPUT_ENABLE |
3021 TRANS_DP_ENH_FRAMING);
9325c9f0 3022 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3023
3024 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3025 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3026 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3027 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3028
3029 switch (intel_trans_dp_port_sel(crtc)) {
3030 case PCH_DP_B:
5eddb70b 3031 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3032 break;
3033 case PCH_DP_C:
5eddb70b 3034 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3035 break;
3036 case PCH_DP_D:
5eddb70b 3037 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3038 break;
3039 default:
e95d41e1 3040 BUG();
32f9d658 3041 }
2c07245f 3042
5eddb70b 3043 I915_WRITE(reg, temp);
6be4a607 3044 }
b52eb4dc 3045
b8a4f404 3046 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3047}
3048
1507e5bd
PZ		 3049static void lpt_pch_enable(struct drm_crtc *crtc)
3050{
3051 struct drm_device *dev = crtc->dev;
3052 struct drm_i915_private *dev_priv = dev->dev_private;
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3054 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3055
ab9412ba 3056 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3057
8c52b5e8 3058 lpt_program_iclkip(crtc);
1507e5bd 3059
0540e488 3060 /* Set transcoder timing. */
275f01b2 3061 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3062
937bb610 3063 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3064}
3065
e2b78267 3066static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3067{
e2b78267 3068 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3069
3070 if (pll == NULL)
3071 return;
3072
3073 if (pll->refcount == 0) {
46edb027 3074 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3075 return;
3076 }
3077
f4a091c7
DV		 3078 if (--pll->refcount == 0) {
3079 WARN_ON(pll->on);
3080 WARN_ON(pll->active);
3081 }
3082
a43f6e0f 3083 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3084}
3085
b89a1d39 3086static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3087{
e2b78267
DV		 3088 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3089 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3090 enum intel_dpll_id i;
ee7b9f93 3091
ee7b9f93 3092 if (pll) {
46edb027
DV		 3093 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3094 crtc->base.base.id, pll->name);
e2b78267 3095 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3096 }
3097
98b6bd99
DV		 3098 if (HAS_PCH_IBX(dev_priv->dev)) {
3099 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3100 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3101 pll = &dev_priv->shared_dplls[i];
98b6bd99 3102
46edb027
DV		 3103 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3104 crtc->base.base.id, pll->name);
98b6bd99
DV		 3105
3106 goto found;
3107 }
3108
e72f9fbf
DV		 3109 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3110 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3111
3112 /* Only want to check enabled timings first */
3113 if (pll->refcount == 0)
3114 continue;
3115
b89a1d39
DV		 3116 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3117 sizeof(pll->hw_state)) == 0) {
46edb027 3118 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3119 crtc->base.base.id,
46edb027 3120 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3121
3122 goto found;
3123 }
3124 }
3125
3126 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3127 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3128 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3129 if (pll->refcount == 0) {
46edb027
DV		 3130 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3131 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3132 goto found;
3133 }
3134 }
3135
3136 return NULL;
3137
3138found:
a43f6e0f 3139 crtc->config.shared_dpll = i;
46edb027
DV		 3140 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3141 pipe_name(crtc->pipe));
ee7b9f93 3142
cdbd2316 3143 if (pll->active == 0) {
66e985c0
DV		 3144 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3145 sizeof(pll->hw_state));
3146
46edb027 3147 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3148 WARN_ON(pll->on);
e9d6944e 3149 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3150
15bdd4cf 3151 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3152 }
3153 pll->refcount++;
e04c7350 3154
ee7b9f93
JB		 3155 return pll;
3156}
3157
a1520318 3158static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3159{
3160 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3161 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3162 u32 temp;
3163
3164 temp = I915_READ(dslreg);
3165 udelay(500);
3166 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3167 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3168 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3169 }
3170}
3171
b074cec8
JB		 3172static void ironlake_pfit_enable(struct intel_crtc *crtc)
3173{
3174 struct drm_device *dev = crtc->base.dev;
3175 struct drm_i915_private *dev_priv = dev->dev_private;
3176 int pipe = crtc->pipe;
3177
0ef37f3f 3178 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3179 /* Force use of hard-coded filter coefficients
3180 * as some pre-programmed values are broken,
3181 * e.g. x201.
3182 */
3183 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3184 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3185 PF_PIPE_SEL_IVB(pipe));
3186 else
3187 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3188 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3189 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3190 }
3191}
3192
bb53d4ae
VS		 3193static void intel_enable_planes(struct drm_crtc *crtc)
3194{
3195 struct drm_device *dev = crtc->dev;
3196 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3197 struct intel_plane *intel_plane;
3198
3199 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3200 if (intel_plane->pipe == pipe)
3201 intel_plane_restore(&intel_plane->base);
3202}
3203
3204static void intel_disable_planes(struct drm_crtc *crtc)
3205{
3206 struct drm_device *dev = crtc->dev;
3207 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3208 struct intel_plane *intel_plane;
3209
3210 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3211 if (intel_plane->pipe == pipe)
3212 intel_plane_disable(&intel_plane->base);
3213}
3214
f67a559d
JB		 3215static void ironlake_crtc_enable(struct drm_crtc *crtc)
3216{
3217 struct drm_device *dev = crtc->dev;
3218 struct drm_i915_private *dev_priv = dev->dev_private;
3219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3220 struct intel_encoder *encoder;
f67a559d
JB		 3221 int pipe = intel_crtc->pipe;
3222 int plane = intel_crtc->plane;
f67a559d 3223
08a48469
DV		 3224 WARN_ON(!crtc->enabled);
3225
f67a559d
JB		 3226 if (intel_crtc->active)
3227 return;
3228
3229 intel_crtc->active = true;
8664281b
PZ		 3230
3231 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3232 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3233
f67a559d
JB		 3234 intel_update_watermarks(dev);
3235
f6736a1a 3236 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3237 if (encoder->pre_enable)
3238 encoder->pre_enable(encoder);
f67a559d 3239
5bfe2ac0 3240 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3241 /* Note: FDI PLL enabling _must_ be done before we enable the
3242 * cpu pipes, hence this is separate from all the other fdi/pch
3243 * enabling. */
88cefb6c 3244 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3245 } else {
3246 assert_fdi_tx_disabled(dev_priv, pipe);
3247 assert_fdi_rx_disabled(dev_priv, pipe);
3248 }
f67a559d 3249
b074cec8 3250 ironlake_pfit_enable(intel_crtc);
f67a559d 3251
9c54c0dd
JB		 3252 /*
3253 * On ILK+ LUT must be loaded before the pipe is running but with
3254 * clocks enabled
3255 */
3256 intel_crtc_load_lut(crtc);
3257
5bfe2ac0
DV		 3258 intel_enable_pipe(dev_priv, pipe,
3259 intel_crtc->config.has_pch_encoder);
f67a559d 3260 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3261 intel_enable_planes(crtc);
5c38d48c 3262 intel_crtc_update_cursor(crtc, true);
f67a559d 3263
5bfe2ac0 3264 if (intel_crtc->config.has_pch_encoder)
f67a559d 3265 ironlake_pch_enable(crtc);
c98e9dcf 3266
d1ebd816 3267 mutex_lock(&dev->struct_mutex);
bed4a673 3268 intel_update_fbc(dev);
d1ebd816
BW		 3269 mutex_unlock(&dev->struct_mutex);
3270
fa5c73b1
DV		 3271 for_each_encoder_on_crtc(dev, crtc, encoder)
3272 encoder->enable(encoder);
61b77ddd
DV		 3273
3274 if (HAS_PCH_CPT(dev))
a1520318 3275 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3276
3277 /*
3278 * There seems to be a race in PCH platform hw (at least on some
3279 * outputs) where an enabled pipe still completes any pageflip right
3280 * away (as if the pipe is off) instead of waiting for vblank. As soon
3281 * as the first vblank happend, everything works as expected. Hence just
3282 * wait for one vblank before returning to avoid strange things
3283 * happening.
3284 */
3285 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3286}
3287
42db64ef
PZ		 3288/* IPS only exists on ULT machines and is tied to pipe A. */
3289static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3290{
f5adf94e 3291 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3292}
3293
3294static void hsw_enable_ips(struct intel_crtc *crtc)
3295{
3296 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3297
3298 if (!crtc->config.ips_enabled)
3299 return;
3300
3301 /* We can only enable IPS after we enable a plane and wait for a vblank.
3302 * We guarantee that the plane is enabled by calling intel_enable_ips
3303 * only after intel_enable_plane. And intel_enable_plane already waits
3304 * for a vblank, so all we need to do here is to enable the IPS bit. */
3305 assert_plane_enabled(dev_priv, crtc->plane);
3306 I915_WRITE(IPS_CTL, IPS_ENABLE);
3307}
3308
3309static void hsw_disable_ips(struct intel_crtc *crtc)
3310{
3311 struct drm_device *dev = crtc->base.dev;
3312 struct drm_i915_private *dev_priv = dev->dev_private;
3313
3314 if (!crtc->config.ips_enabled)
3315 return;
3316
3317 assert_plane_enabled(dev_priv, crtc->plane);
3318 I915_WRITE(IPS_CTL, 0);
3319
3320 /* We need to wait for a vblank before we can disable the plane. */
3321 intel_wait_for_vblank(dev, crtc->pipe);
3322}
3323
4f771f10
PZ		 3324static void haswell_crtc_enable(struct drm_crtc *crtc)
3325{
3326 struct drm_device *dev = crtc->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3329 struct intel_encoder *encoder;
3330 int pipe = intel_crtc->pipe;
3331 int plane = intel_crtc->plane;
4f771f10
PZ		 3332
3333 WARN_ON(!crtc->enabled);
3334
3335 if (intel_crtc->active)
3336 return;
3337
3338 intel_crtc->active = true;
8664281b
PZ		 3339
3340 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3341 if (intel_crtc->config.has_pch_encoder)
3342 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3343
4f771f10
PZ		 3344 intel_update_watermarks(dev);
3345
5bfe2ac0 3346 if (intel_crtc->config.has_pch_encoder)
04945641 3347 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3348
3349 for_each_encoder_on_crtc(dev, crtc, encoder)
3350 if (encoder->pre_enable)
3351 encoder->pre_enable(encoder);
3352
1f544388 3353 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3354
b074cec8 3355 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3356
3357 /*
3358 * On ILK+ LUT must be loaded before the pipe is running but with
3359 * clocks enabled
3360 */
3361 intel_crtc_load_lut(crtc);
3362
1f544388 3363 intel_ddi_set_pipe_settings(crtc);
8228c251 3364 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3365
5bfe2ac0
DV		 3366 intel_enable_pipe(dev_priv, pipe,
3367 intel_crtc->config.has_pch_encoder);
4f771f10 3368 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3369 intel_enable_planes(crtc);
5c38d48c 3370 intel_crtc_update_cursor(crtc, true);
4f771f10 3371
42db64ef
PZ		 3372 hsw_enable_ips(intel_crtc);
3373
5bfe2ac0 3374 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3375 lpt_pch_enable(crtc);
4f771f10
PZ		 3376
3377 mutex_lock(&dev->struct_mutex);
3378 intel_update_fbc(dev);
3379 mutex_unlock(&dev->struct_mutex);
3380
4f771f10
PZ		 3381 for_each_encoder_on_crtc(dev, crtc, encoder)
3382 encoder->enable(encoder);
3383
4f771f10
PZ		 3384 /*
3385 * There seems to be a race in PCH platform hw (at least on some
3386 * outputs) where an enabled pipe still completes any pageflip right
3387 * away (as if the pipe is off) instead of waiting for vblank. As soon
3388 * as the first vblank happend, everything works as expected. Hence just
3389 * wait for one vblank before returning to avoid strange things
3390 * happening.
3391 */
3392 intel_wait_for_vblank(dev, intel_crtc->pipe);
3393}
3394
3f8dce3a
DV		 3395static void ironlake_pfit_disable(struct intel_crtc *crtc)
3396{
3397 struct drm_device *dev = crtc->base.dev;
3398 struct drm_i915_private *dev_priv = dev->dev_private;
3399 int pipe = crtc->pipe;
3400
3401 /* To avoid upsetting the power well on haswell only disable the pfit if
3402 * it's in use. The hw state code will make sure we get this right. */
3403 if (crtc->config.pch_pfit.size) {
3404 I915_WRITE(PF_CTL(pipe), 0);
3405 I915_WRITE(PF_WIN_POS(pipe), 0);
3406 I915_WRITE(PF_WIN_SZ(pipe), 0);
3407 }
3408}
3409
6be4a607
JB		 3410static void ironlake_crtc_disable(struct drm_crtc *crtc)
3411{
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3415 struct intel_encoder *encoder;
6be4a607
JB		 3416 int pipe = intel_crtc->pipe;
3417 int plane = intel_crtc->plane;
5eddb70b 3418 u32 reg, temp;
b52eb4dc 3419
ef9c3aee 3420
f7abfe8b
CW		 3421 if (!intel_crtc->active)
3422 return;
3423
ea9d758d
DV		 3424 for_each_encoder_on_crtc(dev, crtc, encoder)
3425 encoder->disable(encoder);
3426
e6c3a2a6 3427 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3428 drm_vblank_off(dev, pipe);
913d8d11 3429
5c3fe8b0 3430 if (dev_priv->fbc.plane == plane)
973d04f9 3431 intel_disable_fbc(dev);
2c07245f 3432
0d5b8c61 3433 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3434 intel_disable_planes(crtc);
0d5b8c61
VS		 3435 intel_disable_plane(dev_priv, plane, pipe);
3436
d925c59a
DV		 3437 if (intel_crtc->config.has_pch_encoder)
3438 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3439
b24e7179 3440 intel_disable_pipe(dev_priv, pipe);
32f9d658 3441
3f8dce3a 3442 ironlake_pfit_disable(intel_crtc);
2c07245f 3443
bf49ec8c
DV		 3444 for_each_encoder_on_crtc(dev, crtc, encoder)
3445 if (encoder->post_disable)
3446 encoder->post_disable(encoder);
2c07245f 3447
d925c59a
DV		 3448 if (intel_crtc->config.has_pch_encoder) {
3449 ironlake_fdi_disable(crtc);
913d8d11 3450
d925c59a
DV		 3451 ironlake_disable_pch_transcoder(dev_priv, pipe);
3452 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3453
d925c59a
DV		 3454 if (HAS_PCH_CPT(dev)) {
3455 /* disable TRANS_DP_CTL */
3456 reg = TRANS_DP_CTL(pipe);
3457 temp = I915_READ(reg);
3458 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3459 TRANS_DP_PORT_SEL_MASK);
3460 temp |= TRANS_DP_PORT_SEL_NONE;
3461 I915_WRITE(reg, temp);
3462
3463 /* disable DPLL_SEL */
3464 temp = I915_READ(PCH_DPLL_SEL);
11887397 3465 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3466 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3467 }
e3421a18 3468
d925c59a 3469 /* disable PCH DPLL */
e72f9fbf 3470 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3471
d925c59a
DV		 3472 ironlake_fdi_pll_disable(intel_crtc);
3473 }
6b383a7f 3474
f7abfe8b 3475 intel_crtc->active = false;
6b383a7f 3476 intel_update_watermarks(dev);
d1ebd816
BW		 3477
3478 mutex_lock(&dev->struct_mutex);
6b383a7f 3479 intel_update_fbc(dev);
d1ebd816 3480 mutex_unlock(&dev->struct_mutex);
6be4a607 3481}
1b3c7a47 3482
4f771f10 3483static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3484{
4f771f10
PZ		 3485 struct drm_device *dev = crtc->dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3488 struct intel_encoder *encoder;
3489 int pipe = intel_crtc->pipe;
3490 int plane = intel_crtc->plane;
3b117c8f 3491 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3492
4f771f10
PZ		 3493 if (!intel_crtc->active)
3494 return;
3495
3496 for_each_encoder_on_crtc(dev, crtc, encoder)
3497 encoder->disable(encoder);
3498
3499 intel_crtc_wait_for_pending_flips(crtc);
3500 drm_vblank_off(dev, pipe);
4f771f10 3501
891348b2 3502 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3503 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3504 intel_disable_fbc(dev);
3505
42db64ef
PZ		 3506 hsw_disable_ips(intel_crtc);
3507
0d5b8c61 3508 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3509 intel_disable_planes(crtc);
891348b2
RV		 3510 intel_disable_plane(dev_priv, plane, pipe);
3511
8664281b
PZ		 3512 if (intel_crtc->config.has_pch_encoder)
3513 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3514 intel_disable_pipe(dev_priv, pipe);
3515
ad80a810 3516 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3517
3f8dce3a 3518 ironlake_pfit_disable(intel_crtc);
4f771f10 3519
1f544388 3520 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3521
3522 for_each_encoder_on_crtc(dev, crtc, encoder)
3523 if (encoder->post_disable)
3524 encoder->post_disable(encoder);
3525
88adfff1 3526 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3527 lpt_disable_pch_transcoder(dev_priv);
8664281b 3528 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3529 intel_ddi_fdi_disable(crtc);
83616634 3530 }
4f771f10
PZ		 3531
3532 intel_crtc->active = false;
3533 intel_update_watermarks(dev);
3534
3535 mutex_lock(&dev->struct_mutex);
3536 intel_update_fbc(dev);
3537 mutex_unlock(&dev->struct_mutex);
3538}
3539
ee7b9f93
JB		 3540static void ironlake_crtc_off(struct drm_crtc *crtc)
3541{
3542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3543 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3544}
3545
6441ab5f
PZ		 3546static void haswell_crtc_off(struct drm_crtc *crtc)
3547{
3548 intel_ddi_put_crtc_pll(crtc);
3549}
3550
02e792fb
DV		 3551static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3552{
02e792fb 3553 if (!enable && intel_crtc->overlay) {
23f09ce3 3554 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3555 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3556
23f09ce3 3557 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3558 dev_priv->mm.interruptible = false;
3559 (void) intel_overlay_switch_off(intel_crtc->overlay);
3560 dev_priv->mm.interruptible = true;
23f09ce3 3561 mutex_unlock(&dev->struct_mutex);
02e792fb 3562 }
02e792fb 3563
5dcdbcb0
CW		 3564 /* Let userspace switch the overlay on again. In most cases userspace
3565 * has to recompute where to put it anyway.
3566 */
02e792fb
DV		 3567}
3568
61bc95c1
EE		 3569/**
3570 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3571 * cursor plane briefly if not already running after enabling the display
3572 * plane.
3573 * This workaround avoids occasional blank screens when self refresh is
3574 * enabled.
3575 */
3576static void
3577g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3578{
3579 u32 cntl = I915_READ(CURCNTR(pipe));
3580
3581 if ((cntl & CURSOR_MODE) == 0) {
3582 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3583
3584 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3585 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3586 intel_wait_for_vblank(dev_priv->dev, pipe);
3587 I915_WRITE(CURCNTR(pipe), cntl);
3588 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3589 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3590 }
3591}
3592
2dd24552
JB		 3593static void i9xx_pfit_enable(struct intel_crtc *crtc)
3594{
3595 struct drm_device *dev = crtc->base.dev;
3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 struct intel_crtc_config *pipe_config = &crtc->config;
3598
328d8e82 3599 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3600 return;
3601
2dd24552 3602 /*
c0b03411
DV		 3603 * The panel fitter should only be adjusted whilst the pipe is disabled,
3604 * according to register description and PRM.
2dd24552 3605 */
c0b03411
DV		 3606 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3607 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3608
b074cec8
JB		 3609 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3610 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3611
3612 /* Border color in case we don't scale up to the full screen. Black by
3613 * default, change to something else for debugging. */
3614 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3615}
3616
89b667f8
JB		 3617static void valleyview_crtc_enable(struct drm_crtc *crtc)
3618{
3619 struct drm_device *dev = crtc->dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622 struct intel_encoder *encoder;
3623 int pipe = intel_crtc->pipe;
3624 int plane = intel_crtc->plane;
3625
3626 WARN_ON(!crtc->enabled);
3627
3628 if (intel_crtc->active)
3629 return;
3630
3631 intel_crtc->active = true;
3632 intel_update_watermarks(dev);
3633
3634 mutex_lock(&dev_priv->dpio_lock);
3635
3636 for_each_encoder_on_crtc(dev, crtc, encoder)
3637 if (encoder->pre_pll_enable)
3638 encoder->pre_pll_enable(encoder);
3639
87442f73 3640 vlv_enable_pll(dev_priv, pipe);
89b667f8
JB		 3641
3642 for_each_encoder_on_crtc(dev, crtc, encoder)
3643 if (encoder->pre_enable)
3644 encoder->pre_enable(encoder);
3645
3646 /* VLV wants encoder enabling _before_ the pipe is up. */
3647 for_each_encoder_on_crtc(dev, crtc, encoder)
3648 encoder->enable(encoder);
3649
2dd24552
JB		 3650 i9xx_pfit_enable(intel_crtc);
3651
63cbb074
VS		 3652 intel_crtc_load_lut(crtc);
3653
89b667f8
JB		 3654 intel_enable_pipe(dev_priv, pipe, false);
3655 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3656 intel_enable_planes(crtc);
5c38d48c 3657 intel_crtc_update_cursor(crtc, true);
89b667f8 3658
89b667f8
JB		 3659 intel_update_fbc(dev);
3660
89b667f8
JB		 3661 mutex_unlock(&dev_priv->dpio_lock);
3662}
3663
0b8765c6 3664static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3665{
3666 struct drm_device *dev = crtc->dev;
79e53945
JB		 3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3669 struct intel_encoder *encoder;
79e53945 3670 int pipe = intel_crtc->pipe;
80824003 3671 int plane = intel_crtc->plane;
79e53945 3672
08a48469
DV		 3673 WARN_ON(!crtc->enabled);
3674
f7abfe8b
CW		 3675 if (intel_crtc->active)
3676 return;
3677
3678 intel_crtc->active = true;
6b383a7f
CW		 3679 intel_update_watermarks(dev);
3680
9d6d9f19
MK		 3681 for_each_encoder_on_crtc(dev, crtc, encoder)
3682 if (encoder->pre_enable)
3683 encoder->pre_enable(encoder);
3684
f6736a1a
DV		 3685 i9xx_enable_pll(intel_crtc);
3686
2dd24552
JB		 3687 i9xx_pfit_enable(intel_crtc);
3688
63cbb074
VS		 3689 intel_crtc_load_lut(crtc);
3690
040484af 3691 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3692 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3693 intel_enable_planes(crtc);
22e407d7 3694 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3695 if (IS_G4X(dev))
3696 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3697 intel_crtc_update_cursor(crtc, true);
79e53945 3698
0b8765c6
JB		 3699 /* Give the overlay scaler a chance to enable if it's on this pipe */
3700 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3701
f440eb13 3702 intel_update_fbc(dev);
ef9c3aee 3703
fa5c73b1
DV		 3704 for_each_encoder_on_crtc(dev, crtc, encoder)
3705 encoder->enable(encoder);
0b8765c6 3706}
79e53945 3707
87476d63
DV		 3708static void i9xx_pfit_disable(struct intel_crtc *crtc)
3709{
3710 struct drm_device *dev = crtc->base.dev;
3711 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3712
328d8e82
DV		 3713 if (!crtc->config.gmch_pfit.control)
3714 return;
87476d63 3715
328d8e82 3716 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3717
328d8e82
DV		 3718 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3719 I915_READ(PFIT_CONTROL));
3720 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3721}
3722
0b8765c6
JB		 3723static void i9xx_crtc_disable(struct drm_crtc *crtc)
3724{
3725 struct drm_device *dev = crtc->dev;
3726 struct drm_i915_private *dev_priv = dev->dev_private;
3727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3728 struct intel_encoder *encoder;
0b8765c6
JB		 3729 int pipe = intel_crtc->pipe;
3730 int plane = intel_crtc->plane;
ef9c3aee 3731
f7abfe8b
CW		 3732 if (!intel_crtc->active)
3733 return;
3734
ea9d758d
DV		 3735 for_each_encoder_on_crtc(dev, crtc, encoder)
3736 encoder->disable(encoder);
3737
0b8765c6 3738 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3739 intel_crtc_wait_for_pending_flips(crtc);
3740 drm_vblank_off(dev, pipe);
0b8765c6 3741
5c3fe8b0 3742 if (dev_priv->fbc.plane == plane)
973d04f9 3743 intel_disable_fbc(dev);
79e53945 3744
0d5b8c61
VS		 3745 intel_crtc_dpms_overlay(intel_crtc, false);
3746 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3747 intel_disable_planes(crtc);
b24e7179 3748 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3749
b24e7179 3750 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3751
87476d63 3752 i9xx_pfit_disable(intel_crtc);
24a1f16d 3753
89b667f8
JB		 3754 for_each_encoder_on_crtc(dev, crtc, encoder)
3755 if (encoder->post_disable)
3756 encoder->post_disable(encoder);
3757
63d7bbe9 3758 intel_disable_pll(dev_priv, pipe);
0b8765c6 3759
f7abfe8b 3760 intel_crtc->active = false;
6b383a7f
CW		 3761 intel_update_fbc(dev);
3762 intel_update_watermarks(dev);
0b8765c6
JB		 3763}
3764
ee7b9f93
JB		 3765static void i9xx_crtc_off(struct drm_crtc *crtc)
3766{
3767}
3768
976f8a20
DV		 3769static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3770 bool enabled)
2c07245f
ZW		 3771{
3772 struct drm_device *dev = crtc->dev;
3773 struct drm_i915_master_private *master_priv;
3774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3775 int pipe = intel_crtc->pipe;
79e53945
JB		 3776
3777 if (!dev->primary->master)
3778 return;
3779
3780 master_priv = dev->primary->master->driver_priv;
3781 if (!master_priv->sarea_priv)
3782 return;
3783
79e53945
JB		 3784 switch (pipe) {
3785 case 0:
3786 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3787 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3788 break;
3789 case 1:
3790 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3791 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3792 break;
3793 default:
9db4a9c7 3794 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3795 break;
3796 }
79e53945
JB		 3797}
3798
976f8a20
DV		 3799/**
3800 * Sets the power management mode of the pipe and plane.
3801 */
3802void intel_crtc_update_dpms(struct drm_crtc *crtc)
3803{
3804 struct drm_device *dev = crtc->dev;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806 struct intel_encoder *intel_encoder;
3807 bool enable = false;
3808
3809 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3810 enable |= intel_encoder->connectors_active;
3811
3812 if (enable)
3813 dev_priv->display.crtc_enable(crtc);
3814 else
3815 dev_priv->display.crtc_disable(crtc);
3816
3817 intel_crtc_update_sarea(crtc, enable);
3818}
3819
cdd59983
CW		 3820static void intel_crtc_disable(struct drm_crtc *crtc)
3821{
cdd59983 3822 struct drm_device *dev = crtc->dev;
976f8a20 3823 struct drm_connector *connector;
ee7b9f93 3824 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3826
976f8a20
DV		 3827 /* crtc should still be enabled when we disable it. */
3828 WARN_ON(!crtc->enabled);
3829
3830 dev_priv->display.crtc_disable(crtc);
c77bf565 3831 intel_crtc->eld_vld = false;
976f8a20 3832 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3833 dev_priv->display.off(crtc);
3834
931872fc
CW		 3835 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3836 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3837
3838 if (crtc->fb) {
3839 mutex_lock(&dev->struct_mutex);
1690e1eb 3840 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3841 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3842 crtc->fb = NULL;
3843 }
3844
3845 /* Update computed state. */
3846 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3847 if (!connector->encoder || !connector->encoder->crtc)
3848 continue;
3849
3850 if (connector->encoder->crtc != crtc)
3851 continue;
3852
3853 connector->dpms = DRM_MODE_DPMS_OFF;
3854 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3855 }
3856}
3857
a261b246 3858void intel_modeset_disable(struct drm_device *dev)
79e53945 3859{
a261b246
DV		 3860 struct drm_crtc *crtc;
3861
3862 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3863 if (crtc->enabled)
3864 intel_crtc_disable(crtc);
3865 }
79e53945
JB		 3866}
3867
ea5b213a 3868void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3869{
4ef69c7a 3870 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3871
ea5b213a
CW		 3872 drm_encoder_cleanup(encoder);
3873 kfree(intel_encoder);
7e7d76c3
JB		 3874}
3875
5ab432ef
DV		 3876/* Simple dpms helper for encodres with just one connector, no cloning and only
3877 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3878 * state of the entire output pipe. */
3879void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3880{
5ab432ef
DV		 3881 if (mode == DRM_MODE_DPMS_ON) {
3882 encoder->connectors_active = true;
3883
b2cabb0e 3884 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3885 } else {
3886 encoder->connectors_active = false;
3887
b2cabb0e 3888 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3889 }
79e53945
JB		 3890}
3891
0a91ca29
DV		 3892/* Cross check the actual hw state with our own modeset state tracking (and it's
3893 * internal consistency). */
b980514c 3894static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3895{
0a91ca29
DV		 3896 if (connector->get_hw_state(connector)) {
3897 struct intel_encoder *encoder = connector->encoder;
3898 struct drm_crtc *crtc;
3899 bool encoder_enabled;
3900 enum pipe pipe;
3901
3902 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3903 connector->base.base.id,
3904 drm_get_connector_name(&connector->base));
3905
3906 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3907 "wrong connector dpms state\n");
3908 WARN(connector->base.encoder != &encoder->base,
3909 "active connector not linked to encoder\n");
3910 WARN(!encoder->connectors_active,
3911 "encoder->connectors_active not set\n");
3912
3913 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3914 WARN(!encoder_enabled, "encoder not enabled\n");
3915 if (WARN_ON(!encoder->base.crtc))
3916 return;
3917
3918 crtc = encoder->base.crtc;
3919
3920 WARN(!crtc->enabled, "crtc not enabled\n");
3921 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3922 WARN(pipe != to_intel_crtc(crtc)->pipe,
3923 "encoder active on the wrong pipe\n");
3924 }
79e53945
JB		 3925}
3926
5ab432ef
DV		 3927/* Even simpler default implementation, if there's really no special case to
3928 * consider. */
3929void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3930{
5ab432ef 3931 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3932
5ab432ef
DV		 3933 /* All the simple cases only support two dpms states. */
3934 if (mode != DRM_MODE_DPMS_ON)
3935 mode = DRM_MODE_DPMS_OFF;
d4270e57 3936
5ab432ef
DV		 3937 if (mode == connector->dpms)
3938 return;
3939
3940 connector->dpms = mode;
3941
3942 /* Only need to change hw state when actually enabled */
3943 if (encoder->base.crtc)
3944 intel_encoder_dpms(encoder, mode);
3945 else
8af6cf88 3946 WARN_ON(encoder->connectors_active != false);
0a91ca29 3947
b980514c 3948 intel_modeset_check_state(connector->dev);
79e53945
JB		 3949}
3950
f0947c37
DV		 3951/* Simple connector->get_hw_state implementation for encoders that support only
3952 * one connector and no cloning and hence the encoder state determines the state
3953 * of the connector. */
3954bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3955{
24929352 3956 enum pipe pipe = 0;
f0947c37 3957 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3958
f0947c37 3959 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3960}
3961
1857e1da
DV		 3962static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3963 struct intel_crtc_config *pipe_config)
3964{
3965 struct drm_i915_private *dev_priv = dev->dev_private;
3966 struct intel_crtc *pipe_B_crtc =
3967 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3968
3969 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3970 pipe_name(pipe), pipe_config->fdi_lanes);
3971 if (pipe_config->fdi_lanes > 4) {
3972 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3973 pipe_name(pipe), pipe_config->fdi_lanes);
3974 return false;
3975 }
3976
3977 if (IS_HASWELL(dev)) {
3978 if (pipe_config->fdi_lanes > 2) {
3979 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3980 pipe_config->fdi_lanes);
3981 return false;
3982 } else {
3983 return true;
3984 }
3985 }
3986
3987 if (INTEL_INFO(dev)->num_pipes == 2)
3988 return true;
3989
3990 /* Ivybridge 3 pipe is really complicated */
3991 switch (pipe) {
3992 case PIPE_A:
3993 return true;
3994 case PIPE_B:
3995 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3996 pipe_config->fdi_lanes > 2) {
3997 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3998 pipe_name(pipe), pipe_config->fdi_lanes);
3999 return false;
4000 }
4001 return true;
4002 case PIPE_C:
1e833f40 4003 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4004 pipe_B_crtc->config.fdi_lanes <= 2) {
4005 if (pipe_config->fdi_lanes > 2) {
4006 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4007 pipe_name(pipe), pipe_config->fdi_lanes);
4008 return false;
4009 }
4010 } else {
4011 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4012 return false;
4013 }
4014 return true;
4015 default:
4016 BUG();
4017 }
4018}
4019
e29c22c0
DV		 4020#define RETRY 1
4021static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4022 struct intel_crtc_config *pipe_config)
877d48d5 4023{
1857e1da 4024 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4025 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4026 int lane, link_bw, fdi_dotclock;
e29c22c0 4027 bool setup_ok, needs_recompute = false;
877d48d5 4028
e29c22c0 4029retry:
877d48d5
DV		 4030 /* FDI is a binary signal running at ~2.7GHz, encoding
4031 * each output octet as 10 bits. The actual frequency
4032 * is stored as a divider into a 100MHz clock, and the
4033 * mode pixel clock is stored in units of 1KHz.
4034 * Hence the bw of each lane in terms of the mode signal
4035 * is:
4036 */
4037 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4038
ff9a6750 4039 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4040 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4041
2bd89a07 4042 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4043 pipe_config->pipe_bpp);
4044
4045 pipe_config->fdi_lanes = lane;
4046
2bd89a07 4047 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4048 link_bw, &pipe_config->fdi_m_n);
1857e1da 4049
e29c22c0
DV		 4050 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4051 intel_crtc->pipe, pipe_config);
4052 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4053 pipe_config->pipe_bpp -= 2*3;
4054 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4055 pipe_config->pipe_bpp);
4056 needs_recompute = true;
4057 pipe_config->bw_constrained = true;
4058
4059 goto retry;
4060 }
4061
4062 if (needs_recompute)
4063 return RETRY;
4064
4065 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4066}
4067
42db64ef
PZ		 4068static void hsw_compute_ips_config(struct intel_crtc *crtc,
4069 struct intel_crtc_config *pipe_config)
4070{
3c4ca58c
PZ		 4071 pipe_config->ips_enabled = i915_enable_ips &&
4072 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4073 pipe_config->pipe_bpp == 24;
4074}
4075
a43f6e0f 4076static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4077 struct intel_crtc_config *pipe_config)
79e53945 4078{
a43f6e0f 4079 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4080 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4081
bad720ff 4082 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4083 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4084 if (pipe_config->requested_mode.clock * 3
4085 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4086 return -EINVAL;
2c07245f 4087 }
89749350 4088
f9bef081
DV		 4089 /* All interlaced capable intel hw wants timings in frames. Note though
4090 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4091 * timings, so we need to be careful not to clobber these.*/
7ae89233 4092 if (!pipe_config->timings_set)
f9bef081 4093 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4094
8693a824
DL		 4095 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4096 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4097 */
4098 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4099 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4100 return -EINVAL;
44f46b42 4101
bd080ee5 4102 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4103 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4104 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4105 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4106 * for lvds. */
4107 pipe_config->pipe_bpp = 8*3;
4108 }
4109
f5adf94e 4110 if (HAS_IPS(dev))
a43f6e0f
DV		 4111 hsw_compute_ips_config(crtc, pipe_config);
4112
4113 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4114 * clock survives for now. */
4115 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4116 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4117
877d48d5 4118 if (pipe_config->has_pch_encoder)
a43f6e0f 4119 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4120
e29c22c0 4121 return 0;
79e53945
JB		 4122}
4123
25eb05fc
JB		 4124static int valleyview_get_display_clock_speed(struct drm_device *dev)
4125{
4126 return 400000; /* FIXME */
4127}
4128
e70236a8
JB		 4129static int i945_get_display_clock_speed(struct drm_device *dev)
4130{
4131 return 400000;
4132}
79e53945 4133
e70236a8 4134static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4135{
e70236a8
JB		 4136 return 333000;
4137}
79e53945 4138
e70236a8
JB		 4139static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4140{
4141 return 200000;
4142}
79e53945 4143
e70236a8
JB		 4144static int i915gm_get_display_clock_speed(struct drm_device *dev)
4145{
4146 u16 gcfgc = 0;
79e53945 4147
e70236a8
JB		 4148 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4149
4150 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4151 return 133000;
4152 else {
4153 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4154 case GC_DISPLAY_CLOCK_333_MHZ:
4155 return 333000;
4156 default:
4157 case GC_DISPLAY_CLOCK_190_200_MHZ:
4158 return 190000;
79e53945 4159 }
e70236a8
JB		 4160 }
4161}
4162
4163static int i865_get_display_clock_speed(struct drm_device *dev)
4164{
4165 return 266000;
4166}
4167
4168static int i855_get_display_clock_speed(struct drm_device *dev)
4169{
4170 u16 hpllcc = 0;
4171 /* Assume that the hardware is in the high speed state. This
4172 * should be the default.
4173 */
4174 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4175 case GC_CLOCK_133_200:
4176 case GC_CLOCK_100_200:
4177 return 200000;
4178 case GC_CLOCK_166_250:
4179 return 250000;
4180 case GC_CLOCK_100_133:
79e53945 4181 return 133000;
e70236a8 4182 }
79e53945 4183
e70236a8
JB		 4184 /* Shouldn't happen */
4185 return 0;
4186}
79e53945 4187
e70236a8
JB		 4188static int i830_get_display_clock_speed(struct drm_device *dev)
4189{
4190 return 133000;
79e53945
JB		 4191}
4192
2c07245f 4193static void
a65851af 4194intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4195{
a65851af
VS		 4196 while (*num > DATA_LINK_M_N_MASK ||
4197 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4198 *num >>= 1;
4199 *den >>= 1;
4200 }
4201}
4202
a65851af
VS		 4203static void compute_m_n(unsigned int m, unsigned int n,
4204 uint32_t *ret_m, uint32_t *ret_n)
4205{
4206 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4207 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4208 intel_reduce_m_n_ratio(ret_m, ret_n);
4209}
4210
e69d0bc1
DV		 4211void
4212intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4213 int pixel_clock, int link_clock,
4214 struct intel_link_m_n *m_n)
2c07245f 4215{
e69d0bc1 4216 m_n->tu = 64;
a65851af
VS		 4217
4218 compute_m_n(bits_per_pixel * pixel_clock,
4219 link_clock * nlanes * 8,
4220 &m_n->gmch_m, &m_n->gmch_n);
4221
4222 compute_m_n(pixel_clock, link_clock,
4223 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4224}
4225
a7615030
CW		 4226static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4227{
72bbe58c
KP		 4228 if (i915_panel_use_ssc >= 0)
4229 return i915_panel_use_ssc != 0;
41aa3448 4230 return dev_priv->vbt.lvds_use_ssc
435793df 4231 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4232}
4233
a0c4da24
JB		 4234static int vlv_get_refclk(struct drm_crtc *crtc)
4235{
4236 struct drm_device *dev = crtc->dev;
4237 struct drm_i915_private *dev_priv = dev->dev_private;
4238 int refclk = 27000; /* for DP & HDMI */
4239
4240 return 100000; /* only one validated so far */
4241
4242 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4243 refclk = 96000;
4244 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4245 if (intel_panel_use_ssc(dev_priv))
4246 refclk = 100000;
4247 else
4248 refclk = 96000;
4249 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4250 refclk = 100000;
4251 }
4252
4253 return refclk;
4254}
4255
c65d77d8
JB		 4256static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4257{
4258 struct drm_device *dev = crtc->dev;
4259 struct drm_i915_private *dev_priv = dev->dev_private;
4260 int refclk;
4261
a0c4da24
JB		 4262 if (IS_VALLEYVIEW(dev)) {
4263 refclk = vlv_get_refclk(crtc);
4264 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4265 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4266 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4267 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4268 refclk / 1000);
4269 } else if (!IS_GEN2(dev)) {
4270 refclk = 96000;
4271 } else {
4272 refclk = 48000;
4273 }
4274
4275 return refclk;
4276}
4277
7429e9d4 4278static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4279{
7df00d7a 4280 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4281}
f47709a9 4282
7429e9d4
DV		 4283static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4284{
4285 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4286}
4287
f47709a9 4288static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4289 intel_clock_t *reduced_clock)
4290{
f47709a9 4291 struct drm_device *dev = crtc->base.dev;
a7516a05 4292 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4293 int pipe = crtc->pipe;
a7516a05
JB		 4294 u32 fp, fp2 = 0;
4295
4296 if (IS_PINEVIEW(dev)) {
7429e9d4 4297 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4298 if (reduced_clock)
7429e9d4 4299 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4300 } else {
7429e9d4 4301 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4302 if (reduced_clock)
7429e9d4 4303 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4304 }
4305
4306 I915_WRITE(FP0(pipe), fp);
8bcc2795 4307 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4308
f47709a9
DV		 4309 crtc->lowfreq_avail = false;
4310 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4311 reduced_clock && i915_powersave) {
4312 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4313 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4314 crtc->lowfreq_avail = true;
a7516a05
JB		 4315 } else {
4316 I915_WRITE(FP1(pipe), fp);
8bcc2795 4317 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4318 }
4319}
4320
89b667f8
JB		 4321static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4322{
4323 u32 reg_val;
4324
4325 /*
4326 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4327 * and set it to a reasonable value instead.
4328 */
ae99258f 4329 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4330 reg_val &= 0xffffff00;
4331 reg_val |= 0x00000030;
ae99258f 4332 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4333
ae99258f 4334 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4335 reg_val &= 0x8cffffff;
4336 reg_val = 0x8c000000;
ae99258f 4337 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4338
ae99258f 4339 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4340 reg_val &= 0xffffff00;
ae99258f 4341 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4342
ae99258f 4343 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4344 reg_val &= 0x00ffffff;
4345 reg_val |= 0xb0000000;
ae99258f 4346 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4347}
4348
b551842d
DV		 4349static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4350 struct intel_link_m_n *m_n)
4351{
4352 struct drm_device *dev = crtc->base.dev;
4353 struct drm_i915_private *dev_priv = dev->dev_private;
4354 int pipe = crtc->pipe;
4355
e3b95f1e
DV		 4356 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4357 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4358 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4359 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4360}
4361
4362static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4363 struct intel_link_m_n *m_n)
4364{
4365 struct drm_device *dev = crtc->base.dev;
4366 struct drm_i915_private *dev_priv = dev->dev_private;
4367 int pipe = crtc->pipe;
4368 enum transcoder transcoder = crtc->config.cpu_transcoder;
4369
4370 if (INTEL_INFO(dev)->gen >= 5) {
4371 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4372 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4373 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4374 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4375 } else {
e3b95f1e
DV		 4376 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4377 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4378 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4379 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4380 }
4381}
4382
03afc4a2
DV		 4383static void intel_dp_set_m_n(struct intel_crtc *crtc)
4384{
4385 if (crtc->config.has_pch_encoder)
4386 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4387 else
4388 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4389}
4390
f47709a9 4391static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4392{
f47709a9 4393 struct drm_device *dev = crtc->base.dev;
a0c4da24 4394 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4395 struct intel_encoder *encoder;
f47709a9 4396 int pipe = crtc->pipe;
89b667f8 4397 u32 dpll, mdiv;
a0c4da24 4398 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4399 bool is_hdmi;
198a037f 4400 u32 coreclk, reg_val, dpll_md;
a0c4da24 4401
09153000
DV		 4402 mutex_lock(&dev_priv->dpio_lock);
4403
89b667f8 4404 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4405
f47709a9
DV		 4406 bestn = crtc->config.dpll.n;
4407 bestm1 = crtc->config.dpll.m1;
4408 bestm2 = crtc->config.dpll.m2;
4409 bestp1 = crtc->config.dpll.p1;
4410 bestp2 = crtc->config.dpll.p2;
a0c4da24 4411
89b667f8
JB		 4412 /* See eDP HDMI DPIO driver vbios notes doc */
4413
4414 /* PLL B needs special handling */
4415 if (pipe)
4416 vlv_pllb_recal_opamp(dev_priv);
4417
4418 /* Set up Tx target for periodic Rcomp update */
ae99258f 4419 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4420
4421 /* Disable target IRef on PLL */
ae99258f 4422 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4423 reg_val &= 0x00ffffff;
ae99258f 4424 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4425
4426 /* Disable fast lock */
ae99258f 4427 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4428
4429 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4430 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4431 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4432 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4433 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4434
4435 /*
4436 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4437 * but we don't support that).
4438 * Note: don't use the DAC post divider as it seems unstable.
4439 */
4440 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4441 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4442
a0c4da24 4443 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4444 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4445
89b667f8 4446 /* Set HBR and RBR LPF coefficients */
ff9a6750 4447 if (crtc->config.port_clock == 162000 ||
99750bd4 4448 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4449 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4450 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4451 0x005f0021);
4452 else
4abb2c39 4453 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4454 0x00d0000f);
4455
4456 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4457 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4458 /* Use SSC source */
4459 if (!pipe)
ae99258f 4460 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4461 0x0df40000);
4462 else
ae99258f 4463 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4464 0x0df70000);
4465 } else { /* HDMI or VGA */
4466 /* Use bend source */
4467 if (!pipe)
ae99258f 4468 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4469 0x0df70000);
4470 else
ae99258f 4471 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4472 0x0df40000);
4473 }
a0c4da24 4474
ae99258f 4475 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4476 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4477 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4478 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4479 coreclk |= 0x01000000;
ae99258f 4480 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4481
ae99258f 4482 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4483
89b667f8
JB		 4484 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4485 if (encoder->pre_pll_enable)
4486 encoder->pre_pll_enable(encoder);
a0c4da24 4487
89b667f8
JB		 4488 /* Enable DPIO clock input */
4489 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4490 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4491 if (pipe)
4492 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4493
4494 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4495 crtc->config.dpll_hw_state.dpll = dpll;
4496
a0c4da24
JB		 4497 I915_WRITE(DPLL(pipe), dpll);
4498 POSTING_READ(DPLL(pipe));
2a8f64ca 4499 udelay(150);
a0c4da24 4500
a0c4da24
JB		 4501 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4502 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4503
ef1b460d
DV		 4504 dpll_md = (crtc->config.pixel_multiplier - 1)
4505 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4506 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4507
198a037f 4508 I915_WRITE(DPLL_MD(pipe), dpll_md);
2a8f64ca 4509 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4510
89b667f8
JB		 4511 if (crtc->config.has_dp_encoder)
4512 intel_dp_set_m_n(crtc);
09153000
DV		 4513
4514 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4515}
4516
f47709a9
DV		 4517static void i9xx_update_pll(struct intel_crtc *crtc,
4518 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4519 int num_connectors)
4520{
f47709a9 4521 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4522 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4523 u32 dpll;
4524 bool is_sdvo;
f47709a9 4525 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4526
f47709a9 4527 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4528
f47709a9
DV		 4529 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4530 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4531
4532 dpll = DPLL_VGA_MODE_DIS;
4533
f47709a9 4534 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4535 dpll |= DPLLB_MODE_LVDS;
4536 else
4537 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4538
ef1b460d 4539 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4540 dpll |= (crtc->config.pixel_multiplier - 1)
4541 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4542 }
198a037f
DV		 4543
4544 if (is_sdvo)
4545 dpll |= DPLL_DVO_HIGH_SPEED;
4546
f47709a9 4547 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4548 dpll |= DPLL_DVO_HIGH_SPEED;
4549
4550 /* compute bitmask from p1 value */
4551 if (IS_PINEVIEW(dev))
4552 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4553 else {
4554 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4555 if (IS_G4X(dev) && reduced_clock)
4556 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4557 }
4558 switch (clock->p2) {
4559 case 5:
4560 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4561 break;
4562 case 7:
4563 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4564 break;
4565 case 10:
4566 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4567 break;
4568 case 14:
4569 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4570 break;
4571 }
4572 if (INTEL_INFO(dev)->gen >= 4)
4573 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4574
09ede541 4575 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4576 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4577 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4578 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4579 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4580 else
4581 dpll |= PLL_REF_INPUT_DREFCLK;
4582
4583 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4584 crtc->config.dpll_hw_state.dpll = dpll;
4585
eb1cbe48 4586 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4587 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4588 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4589 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4590 }
66e3d5c0
DV		 4591
4592 if (crtc->config.has_dp_encoder)
4593 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4594}
4595
f47709a9 4596static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4597 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4598 int num_connectors)
4599{
f47709a9 4600 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4601 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4602 u32 dpll;
f47709a9 4603 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4604
f47709a9 4605 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4606
eb1cbe48
DV		 4607 dpll = DPLL_VGA_MODE_DIS;
4608
f47709a9 4609 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4610 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4611 } else {
4612 if (clock->p1 == 2)
4613 dpll |= PLL_P1_DIVIDE_BY_TWO;
4614 else
4615 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4616 if (clock->p2 == 4)
4617 dpll |= PLL_P2_DIVIDE_BY_4;
4618 }
4619
f47709a9 4620 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4621 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4622 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4623 else
4624 dpll |= PLL_REF_INPUT_DREFCLK;
4625
4626 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4627 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4628}
4629
8a654f3b 4630static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4631{
4632 struct drm_device *dev = intel_crtc->base.dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4635 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4636 struct drm_display_mode *adjusted_mode =
4637 &intel_crtc->config.adjusted_mode;
4638 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4639 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4640
4641 /* We need to be careful not to changed the adjusted mode, for otherwise
4642 * the hw state checker will get angry at the mismatch. */
4643 crtc_vtotal = adjusted_mode->crtc_vtotal;
4644 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4645
4646 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4647 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4648 crtc_vtotal -= 1;
4649 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4650 vsyncshift = adjusted_mode->crtc_hsync_start
4651 - adjusted_mode->crtc_htotal / 2;
4652 } else {
4653 vsyncshift = 0;
4654 }
4655
4656 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4657 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4658
fe2b8f9d 4659 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4660 (adjusted_mode->crtc_hdisplay - 1) |
4661 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4662 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4663 (adjusted_mode->crtc_hblank_start - 1) |
4664 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4665 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4666 (adjusted_mode->crtc_hsync_start - 1) |
4667 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4668
fe2b8f9d 4669 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4670 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4671 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4672 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4673 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4674 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4675 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4676 (adjusted_mode->crtc_vsync_start - 1) |
4677 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4678
b5e508d4
PZ		 4679 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4680 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4681 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4682 * bits. */
4683 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4684 (pipe == PIPE_B || pipe == PIPE_C))
4685 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4686
b0e77b9c
PZ		 4687 /* pipesrc controls the size that is scaled from, which should
4688 * always be the user's requested size.
4689 */
4690 I915_WRITE(PIPESRC(pipe),
4691 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4692}
4693
1bd1bd80
DV		 4694static void intel_get_pipe_timings(struct intel_crtc *crtc,
4695 struct intel_crtc_config *pipe_config)
4696{
4697 struct drm_device *dev = crtc->base.dev;
4698 struct drm_i915_private *dev_priv = dev->dev_private;
4699 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4700 uint32_t tmp;
4701
4702 tmp = I915_READ(HTOTAL(cpu_transcoder));
4703 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4704 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4705 tmp = I915_READ(HBLANK(cpu_transcoder));
4706 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4707 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4708 tmp = I915_READ(HSYNC(cpu_transcoder));
4709 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4710 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4711
4712 tmp = I915_READ(VTOTAL(cpu_transcoder));
4713 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4714 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4715 tmp = I915_READ(VBLANK(cpu_transcoder));
4716 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4717 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4718 tmp = I915_READ(VSYNC(cpu_transcoder));
4719 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4720 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4721
4722 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4723 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4724 pipe_config->adjusted_mode.crtc_vtotal += 1;
4725 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4726 }
4727
4728 tmp = I915_READ(PIPESRC(crtc->pipe));
4729 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4730 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4731}
4732
babea61d
JB		 4733static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4734 struct intel_crtc_config *pipe_config)
4735{
4736 struct drm_crtc *crtc = &intel_crtc->base;
4737
4738 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4739 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4740 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4741 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4742
4743 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4744 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4745 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4746 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4747
4748 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4749
4750 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4751 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4752}
4753
84b046f3
DV		 4754static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4755{
4756 struct drm_device *dev = intel_crtc->base.dev;
4757 struct drm_i915_private *dev_priv = dev->dev_private;
4758 uint32_t pipeconf;
4759
9f11a9e4 4760 pipeconf = 0;
84b046f3
DV		 4761
4762 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4763 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4764 * core speed.
4765 *
4766 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4767 * pipe == 0 check?
4768 */
4769 if (intel_crtc->config.requested_mode.clock >
4770 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4771 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4772 }
4773
ff9ce46e
DV		 4774 /* only g4x and later have fancy bpc/dither controls */
4775 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4776 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4777 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4778 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4779 PIPECONF_DITHER_TYPE_SP;
84b046f3 4780
ff9ce46e
DV		 4781 switch (intel_crtc->config.pipe_bpp) {
4782 case 18:
4783 pipeconf |= PIPECONF_6BPC;
4784 break;
4785 case 24:
4786 pipeconf |= PIPECONF_8BPC;
4787 break;
4788 case 30:
4789 pipeconf |= PIPECONF_10BPC;
4790 break;
4791 default:
4792 /* Case prevented by intel_choose_pipe_bpp_dither. */
4793 BUG();
84b046f3
DV		 4794 }
4795 }
4796
4797 if (HAS_PIPE_CXSR(dev)) {
4798 if (intel_crtc->lowfreq_avail) {
4799 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4800 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4801 } else {
4802 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4803 }
4804 }
4805
84b046f3
DV		 4806 if (!IS_GEN2(dev) &&
4807 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4808 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4809 else
4810 pipeconf |= PIPECONF_PROGRESSIVE;
4811
9f11a9e4
DV		 4812 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4813 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4814
84b046f3
DV		 4815 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4816 POSTING_READ(PIPECONF(intel_crtc->pipe));
4817}
4818
f564048e 4819static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4820 int x, int y,
94352cf9 4821 struct drm_framebuffer *fb)
79e53945
JB		 4822{
4823 struct drm_device *dev = crtc->dev;
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4826 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4827 int pipe = intel_crtc->pipe;
80824003 4828 int plane = intel_crtc->plane;
c751ce4f 4829 int refclk, num_connectors = 0;
652c393a 4830 intel_clock_t clock, reduced_clock;
84b046f3 4831 u32 dspcntr;
a16af721
DV		 4832 bool ok, has_reduced_clock = false;
4833 bool is_lvds = false;
5eddb70b 4834 struct intel_encoder *encoder;
d4906093 4835 const intel_limit_t *limit;
5c3b82e2 4836 int ret;
79e53945 4837
6c2b7c12 4838 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4839 switch (encoder->type) {
79e53945
JB		 4840 case INTEL_OUTPUT_LVDS:
4841 is_lvds = true;
4842 break;
79e53945 4843 }
43565a06 4844
c751ce4f 4845 num_connectors++;
79e53945
JB		 4846 }
4847
c65d77d8 4848 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4849
d4906093
ML		 4850 /*
4851 * Returns a set of divisors for the desired target clock with the given
4852 * refclk, or FALSE. The returned values represent the clock equation:
4853 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4854 */
1b894b59 4855 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4856 ok = dev_priv->display.find_dpll(limit, crtc,
4857 intel_crtc->config.port_clock,
ee9300bb
DV		 4858 refclk, NULL, &clock);
4859 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4860 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4861 return -EINVAL;
79e53945
JB		 4862 }
4863
cda4b7d3 4864 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4865 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4866
ddc9003c 4867 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4868 /*
4869 * Ensure we match the reduced clock's P to the target clock.
4870 * If the clocks don't match, we can't switch the display clock
4871 * by using the FP0/FP1. In such case we will disable the LVDS
4872 * downclock feature.
4873 */
ee9300bb
DV		 4874 has_reduced_clock =
4875 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4876 dev_priv->lvds_downclock,
ee9300bb 4877 refclk, &clock,
5eddb70b 4878 &reduced_clock);
7026d4ac 4879 }
f47709a9
DV		 4880 /* Compat-code for transition, will disappear. */
4881 if (!intel_crtc->config.clock_set) {
4882 intel_crtc->config.dpll.n = clock.n;
4883 intel_crtc->config.dpll.m1 = clock.m1;
4884 intel_crtc->config.dpll.m2 = clock.m2;
4885 intel_crtc->config.dpll.p1 = clock.p1;
4886 intel_crtc->config.dpll.p2 = clock.p2;
4887 }
7026d4ac 4888
eb1cbe48 4889 if (IS_GEN2(dev))
8a654f3b 4890 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4891 has_reduced_clock ? &reduced_clock : NULL,
4892 num_connectors);
a0c4da24 4893 else if (IS_VALLEYVIEW(dev))
f47709a9 4894 vlv_update_pll(intel_crtc);
79e53945 4895 else
f47709a9 4896 i9xx_update_pll(intel_crtc,
eb1cbe48 4897 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4898 num_connectors);
79e53945 4899
79e53945
JB		 4900 /* Set up the display plane register */
4901 dspcntr = DISPPLANE_GAMMA_ENABLE;
4902
da6ecc5d
JB		 4903 if (!IS_VALLEYVIEW(dev)) {
4904 if (pipe == 0)
4905 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4906 else
4907 dspcntr |= DISPPLANE_SEL_PIPE_B;
4908 }
79e53945 4909
8a654f3b 4910 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4911
4912 /* pipesrc and dspsize control the size that is scaled from,
4913 * which should always be the user's requested size.
79e53945 4914 */
929c77fb
EA		 4915 I915_WRITE(DSPSIZE(plane),
4916 ((mode->vdisplay - 1) << 16) |
4917 (mode->hdisplay - 1));
4918 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4919
84b046f3
DV		 4920 i9xx_set_pipeconf(intel_crtc);
4921
f564048e
EA		 4922 I915_WRITE(DSPCNTR(plane), dspcntr);
4923 POSTING_READ(DSPCNTR(plane));
4924
94352cf9 4925 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4926
4927 intel_update_watermarks(dev);
4928
f564048e
EA		 4929 return ret;
4930}
4931
2fa2fe9a
DV		 4932static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4933 struct intel_crtc_config *pipe_config)
4934{
4935 struct drm_device *dev = crtc->base.dev;
4936 struct drm_i915_private *dev_priv = dev->dev_private;
4937 uint32_t tmp;
4938
4939 tmp = I915_READ(PFIT_CONTROL);
4940
4941 if (INTEL_INFO(dev)->gen < 4) {
4942 if (crtc->pipe != PIPE_B)
4943 return;
4944
4945 /* gen2/3 store dither state in pfit control, needs to match */
4946 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4947 } else {
4948 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4949 return;
4950 }
4951
4952 if (!(tmp & PFIT_ENABLE))
4953 return;
4954
4955 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4956 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4957 if (INTEL_INFO(dev)->gen < 5)
4958 pipe_config->gmch_pfit.lvds_border_bits =
4959 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4960}
4961
0e8ffe1b
DV		 4962static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4963 struct intel_crtc_config *pipe_config)
4964{
4965 struct drm_device *dev = crtc->base.dev;
4966 struct drm_i915_private *dev_priv = dev->dev_private;
4967 uint32_t tmp;
4968
e143a21c 4969 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 4970 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4971
0e8ffe1b
DV		 4972 tmp = I915_READ(PIPECONF(crtc->pipe));
4973 if (!(tmp & PIPECONF_ENABLE))
4974 return false;
4975
1bd1bd80
DV		 4976 intel_get_pipe_timings(crtc, pipe_config);
4977
2fa2fe9a
DV		 4978 i9xx_get_pfit_config(crtc, pipe_config);
4979
6c49f241
DV		 4980 if (INTEL_INFO(dev)->gen >= 4) {
4981 tmp = I915_READ(DPLL_MD(crtc->pipe));
4982 pipe_config->pixel_multiplier =
4983 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4984 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 4985 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 4986 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4987 tmp = I915_READ(DPLL(crtc->pipe));
4988 pipe_config->pixel_multiplier =
4989 ((tmp & SDVO_MULTIPLIER_MASK)
4990 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4991 } else {
4992 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4993 * port and will be fixed up in the encoder->get_config
4994 * function. */
4995 pipe_config->pixel_multiplier = 1;
4996 }
8bcc2795
DV		 4997 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
4998 if (!IS_VALLEYVIEW(dev)) {
4999 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5000 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5001 } else {
5002 /* Mask out read-only status bits. */
5003 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5004 DPLL_PORTC_READY_MASK |
5005 DPLL_PORTB_READY_MASK);
8bcc2795 5006 }
6c49f241 5007
0e8ffe1b
DV		 5008 return true;
5009}
5010
dde86e2d 5011static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5012{
5013 struct drm_i915_private *dev_priv = dev->dev_private;
5014 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5015 struct intel_encoder *encoder;
74cfd7ac 5016 u32 val, final;
13d83a67 5017 bool has_lvds = false;
199e5d79 5018 bool has_cpu_edp = false;
199e5d79 5019 bool has_panel = false;
99eb6a01
KP		 5020 bool has_ck505 = false;
5021 bool can_ssc = false;
13d83a67
JB		 5022
5023 /* We need to take the global config into account */
199e5d79
KP		 5024 list_for_each_entry(encoder, &mode_config->encoder_list,
5025 base.head) {
5026 switch (encoder->type) {
5027 case INTEL_OUTPUT_LVDS:
5028 has_panel = true;
5029 has_lvds = true;
5030 break;
5031 case INTEL_OUTPUT_EDP:
5032 has_panel = true;
2de6905f 5033 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5034 has_cpu_edp = true;
5035 break;
13d83a67
JB		 5036 }
5037 }
5038
99eb6a01 5039 if (HAS_PCH_IBX(dev)) {
41aa3448 5040 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5041 can_ssc = has_ck505;
5042 } else {
5043 has_ck505 = false;
5044 can_ssc = true;
5045 }
5046
2de6905f
ID		 5047 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5048 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5049
5050 /* Ironlake: try to setup display ref clock before DPLL
5051 * enabling. This is only under driver's control after
5052 * PCH B stepping, previous chipset stepping should be
5053 * ignoring this setting.
5054 */
74cfd7ac
CW		 5055 val = I915_READ(PCH_DREF_CONTROL);
5056
5057 /* As we must carefully and slowly disable/enable each source in turn,
5058 * compute the final state we want first and check if we need to
5059 * make any changes at all.
5060 */
5061 final = val;
5062 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5063 if (has_ck505)
5064 final |= DREF_NONSPREAD_CK505_ENABLE;
5065 else
5066 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5067
5068 final &= ~DREF_SSC_SOURCE_MASK;
5069 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5070 final &= ~DREF_SSC1_ENABLE;
5071
5072 if (has_panel) {
5073 final |= DREF_SSC_SOURCE_ENABLE;
5074
5075 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5076 final |= DREF_SSC1_ENABLE;
5077
5078 if (has_cpu_edp) {
5079 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5080 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5081 else
5082 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5083 } else
5084 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5085 } else {
5086 final |= DREF_SSC_SOURCE_DISABLE;
5087 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5088 }
5089
5090 if (final == val)
5091 return;
5092
13d83a67 5093 /* Always enable nonspread source */
74cfd7ac 5094 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5095
99eb6a01 5096 if (has_ck505)
74cfd7ac 5097 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5098 else
74cfd7ac 5099 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5100
199e5d79 5101 if (has_panel) {
74cfd7ac
CW		 5102 val &= ~DREF_SSC_SOURCE_MASK;
5103 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5104
199e5d79 5105 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5106 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5107 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5108 val |= DREF_SSC1_ENABLE;
e77166b5 5109 } else
74cfd7ac 5110 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5111
5112 /* Get SSC going before enabling the outputs */
74cfd7ac 5113 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5114 POSTING_READ(PCH_DREF_CONTROL);
5115 udelay(200);
5116
74cfd7ac 5117 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5118
5119 /* Enable CPU source on CPU attached eDP */
199e5d79 5120 if (has_cpu_edp) {
99eb6a01 5121 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5122 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5123 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5124 }
13d83a67 5125 else
74cfd7ac 5126 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5127 } else
74cfd7ac 5128 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5129
74cfd7ac 5130 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5131 POSTING_READ(PCH_DREF_CONTROL);
5132 udelay(200);
5133 } else {
5134 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5135
74cfd7ac 5136 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5137
5138 /* Turn off CPU output */
74cfd7ac 5139 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5140
74cfd7ac 5141 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5142 POSTING_READ(PCH_DREF_CONTROL);
5143 udelay(200);
5144
5145 /* Turn off the SSC source */
74cfd7ac
CW		 5146 val &= ~DREF_SSC_SOURCE_MASK;
5147 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5148
5149 /* Turn off SSC1 */
74cfd7ac 5150 val &= ~DREF_SSC1_ENABLE;
199e5d79 5151
74cfd7ac 5152 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5153 POSTING_READ(PCH_DREF_CONTROL);
5154 udelay(200);
5155 }
74cfd7ac
CW		 5156
5157 BUG_ON(val != final);
13d83a67
JB		 5158}
5159
dde86e2d
PZ		 5160/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5161static void lpt_init_pch_refclk(struct drm_device *dev)
5162{
5163 struct drm_i915_private *dev_priv = dev->dev_private;
5164 struct drm_mode_config *mode_config = &dev->mode_config;
5165 struct intel_encoder *encoder;
5166 bool has_vga = false;
5167 bool is_sdv = false;
5168 u32 tmp;
5169
5170 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5171 switch (encoder->type) {
5172 case INTEL_OUTPUT_ANALOG:
5173 has_vga = true;
5174 break;
5175 }
5176 }
5177
5178 if (!has_vga)
5179 return;
5180
c00db246
DV		 5181 mutex_lock(&dev_priv->dpio_lock);
5182
dde86e2d
PZ		 5183 /* XXX: Rip out SDV support once Haswell ships for real. */
5184 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5185 is_sdv = true;
5186
5187 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5188 tmp &= ~SBI_SSCCTL_DISABLE;
5189 tmp |= SBI_SSCCTL_PATHALT;
5190 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5191
5192 udelay(24);
5193
5194 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5195 tmp &= ~SBI_SSCCTL_PATHALT;
5196 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5197
5198 if (!is_sdv) {
5199 tmp = I915_READ(SOUTH_CHICKEN2);
5200 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5201 I915_WRITE(SOUTH_CHICKEN2, tmp);
5202
5203 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5204 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5205 DRM_ERROR("FDI mPHY reset assert timeout\n");
5206
5207 tmp = I915_READ(SOUTH_CHICKEN2);
5208 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5209 I915_WRITE(SOUTH_CHICKEN2, tmp);
5210
5211 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5212 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5213 100))
5214 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5215 }
5216
5217 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5218 tmp &= ~(0xFF << 24);
5219 tmp |= (0x12 << 24);
5220 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5221
dde86e2d
PZ		 5222 if (is_sdv) {
5223 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5224 tmp |= 0x7FFF;
5225 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5226 }
5227
5228 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5229 tmp |= (1 << 11);
5230 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5231
5232 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5233 tmp |= (1 << 11);
5234 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5235
5236 if (is_sdv) {
5237 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5238 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5239 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5240
5241 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5242 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5243 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5244
5245 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5246 tmp |= (0x3F << 8);
5247 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5248
5249 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5250 tmp |= (0x3F << 8);
5251 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5252 }
5253
5254 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5255 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5256 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5259 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5260 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5261
5262 if (!is_sdv) {
5263 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5264 tmp &= ~(7 << 13);
5265 tmp |= (5 << 13);
5266 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5267
5268 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5269 tmp &= ~(7 << 13);
5270 tmp |= (5 << 13);
5271 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5272 }
5273
5274 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5275 tmp &= ~0xFF;
5276 tmp |= 0x1C;
5277 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5278
5279 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5280 tmp &= ~0xFF;
5281 tmp |= 0x1C;
5282 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5283
5284 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5285 tmp &= ~(0xFF << 16);
5286 tmp |= (0x1C << 16);
5287 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5288
5289 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5290 tmp &= ~(0xFF << 16);
5291 tmp |= (0x1C << 16);
5292 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5293
5294 if (!is_sdv) {
5295 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5296 tmp |= (1 << 27);
5297 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5298
5299 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5300 tmp |= (1 << 27);
5301 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5302
5303 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5304 tmp &= ~(0xF << 28);
5305 tmp |= (4 << 28);
5306 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5307
5308 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5309 tmp &= ~(0xF << 28);
5310 tmp |= (4 << 28);
5311 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5312 }
5313
5314 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5315 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5316 tmp |= SBI_DBUFF0_ENABLE;
5317 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5318
5319 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5320}
5321
5322/*
5323 * Initialize reference clocks when the driver loads
5324 */
5325void intel_init_pch_refclk(struct drm_device *dev)
5326{
5327 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5328 ironlake_init_pch_refclk(dev);
5329 else if (HAS_PCH_LPT(dev))
5330 lpt_init_pch_refclk(dev);
5331}
5332
d9d444cb
JB		 5333static int ironlake_get_refclk(struct drm_crtc *crtc)
5334{
5335 struct drm_device *dev = crtc->dev;
5336 struct drm_i915_private *dev_priv = dev->dev_private;
5337 struct intel_encoder *encoder;
d9d444cb
JB		 5338 int num_connectors = 0;
5339 bool is_lvds = false;
5340
6c2b7c12 5341 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5342 switch (encoder->type) {
5343 case INTEL_OUTPUT_LVDS:
5344 is_lvds = true;
5345 break;
d9d444cb
JB		 5346 }
5347 num_connectors++;
5348 }
5349
5350 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5351 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5352 dev_priv->vbt.lvds_ssc_freq);
5353 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5354 }
5355
5356 return 120000;
5357}
5358
6ff93609 5359static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5360{
c8203565 5361 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5363 int pipe = intel_crtc->pipe;
c8203565
PZ		 5364 uint32_t val;
5365
78114071 5366 val = 0;
c8203565 5367
965e0c48 5368 switch (intel_crtc->config.pipe_bpp) {
c8203565 5369 case 18:
dfd07d72 5370 val |= PIPECONF_6BPC;
c8203565
PZ		 5371 break;
5372 case 24:
dfd07d72 5373 val |= PIPECONF_8BPC;
c8203565
PZ		 5374 break;
5375 case 30:
dfd07d72 5376 val |= PIPECONF_10BPC;
c8203565
PZ		 5377 break;
5378 case 36:
dfd07d72 5379 val |= PIPECONF_12BPC;
c8203565
PZ		 5380 break;
5381 default:
cc769b62
PZ		 5382 /* Case prevented by intel_choose_pipe_bpp_dither. */
5383 BUG();
c8203565
PZ		 5384 }
5385
d8b32247 5386 if (intel_crtc->config.dither)
c8203565
PZ		 5387 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5388
6ff93609 5389 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5390 val |= PIPECONF_INTERLACED_ILK;
5391 else
5392 val |= PIPECONF_PROGRESSIVE;
5393
50f3b016 5394 if (intel_crtc->config.limited_color_range)
3685a8f3 5395 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5396
c8203565
PZ		 5397 I915_WRITE(PIPECONF(pipe), val);
5398 POSTING_READ(PIPECONF(pipe));
5399}
5400
86d3efce
VS		 5401/*
5402 * Set up the pipe CSC unit.
5403 *
5404 * Currently only full range RGB to limited range RGB conversion
5405 * is supported, but eventually this should handle various
5406 * RGB<->YCbCr scenarios as well.
5407 */
50f3b016 5408static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5409{
5410 struct drm_device *dev = crtc->dev;
5411 struct drm_i915_private *dev_priv = dev->dev_private;
5412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5413 int pipe = intel_crtc->pipe;
5414 uint16_t coeff = 0x7800; /* 1.0 */
5415
5416 /*
5417 * TODO: Check what kind of values actually come out of the pipe
5418 * with these coeff/postoff values and adjust to get the best
5419 * accuracy. Perhaps we even need to take the bpc value into
5420 * consideration.
5421 */
5422
50f3b016 5423 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5424 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5425
5426 /*
5427 * GY/GU and RY/RU should be the other way around according
5428 * to BSpec, but reality doesn't agree. Just set them up in
5429 * a way that results in the correct picture.
5430 */
5431 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5432 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5433
5434 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5435 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5436
5437 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5438 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5439
5440 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5441 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5442 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5443
5444 if (INTEL_INFO(dev)->gen > 6) {
5445 uint16_t postoff = 0;
5446
50f3b016 5447 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5448 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5449
5450 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5451 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5452 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5453
5454 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5455 } else {
5456 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5457
50f3b016 5458 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5459 mode |= CSC_BLACK_SCREEN_OFFSET;
5460
5461 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5462 }
5463}
5464
6ff93609 5465static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5466{
5467 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5469 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5470 uint32_t val;
5471
3eff4faa 5472 val = 0;
ee2b0b38 5473
d8b32247 5474 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5475 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5476
6ff93609 5477 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5478 val |= PIPECONF_INTERLACED_ILK;
5479 else
5480 val |= PIPECONF_PROGRESSIVE;
5481
702e7a56
PZ		 5482 I915_WRITE(PIPECONF(cpu_transcoder), val);
5483 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5484
5485 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5486 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5487}
5488
6591c6e4 5489static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5490 intel_clock_t *clock,
5491 bool *has_reduced_clock,
5492 intel_clock_t *reduced_clock)
5493{
5494 struct drm_device *dev = crtc->dev;
5495 struct drm_i915_private *dev_priv = dev->dev_private;
5496 struct intel_encoder *intel_encoder;
5497 int refclk;
d4906093 5498 const intel_limit_t *limit;
a16af721 5499 bool ret, is_lvds = false;
79e53945 5500
6591c6e4
PZ		 5501 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5502 switch (intel_encoder->type) {
79e53945
JB		 5503 case INTEL_OUTPUT_LVDS:
5504 is_lvds = true;
5505 break;
79e53945
JB		 5506 }
5507 }
5508
d9d444cb 5509 refclk = ironlake_get_refclk(crtc);
79e53945 5510
d4906093
ML		 5511 /*
5512 * Returns a set of divisors for the desired target clock with the given
5513 * refclk, or FALSE. The returned values represent the clock equation:
5514 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5515 */
1b894b59 5516 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5517 ret = dev_priv->display.find_dpll(limit, crtc,
5518 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5519 refclk, NULL, clock);
6591c6e4
PZ		 5520 if (!ret)
5521 return false;
cda4b7d3 5522
ddc9003c 5523 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5524 /*
5525 * Ensure we match the reduced clock's P to the target clock.
5526 * If the clocks don't match, we can't switch the display clock
5527 * by using the FP0/FP1. In such case we will disable the LVDS
5528 * downclock feature.
5529 */
ee9300bb
DV		 5530 *has_reduced_clock =
5531 dev_priv->display.find_dpll(limit, crtc,
5532 dev_priv->lvds_downclock,
5533 refclk, clock,
5534 reduced_clock);
652c393a 5535 }
61e9653f 5536
6591c6e4
PZ		 5537 return true;
5538}
5539
01a415fd
DV		 5540static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5541{
5542 struct drm_i915_private *dev_priv = dev->dev_private;
5543 uint32_t temp;
5544
5545 temp = I915_READ(SOUTH_CHICKEN1);
5546 if (temp & FDI_BC_BIFURCATION_SELECT)
5547 return;
5548
5549 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5550 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5551
5552 temp |= FDI_BC_BIFURCATION_SELECT;
5553 DRM_DEBUG_KMS("enabling fdi C rx\n");
5554 I915_WRITE(SOUTH_CHICKEN1, temp);
5555 POSTING_READ(SOUTH_CHICKEN1);
5556}
5557
ebfd86fd 5558static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5559{
5560 struct drm_device *dev = intel_crtc->base.dev;
5561 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5562
5563 switch (intel_crtc->pipe) {
5564 case PIPE_A:
ebfd86fd 5565 break;
01a415fd 5566 case PIPE_B:
ebfd86fd 5567 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5568 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5569 else
5570 cpt_enable_fdi_bc_bifurcation(dev);
5571
ebfd86fd 5572 break;
01a415fd 5573 case PIPE_C:
01a415fd
DV		 5574 cpt_enable_fdi_bc_bifurcation(dev);
5575
ebfd86fd 5576 break;
01a415fd
DV		 5577 default:
5578 BUG();
5579 }
5580}
5581
d4b1931c
PZ		 5582int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5583{
5584 /*
5585 * Account for spread spectrum to avoid
5586 * oversubscribing the link. Max center spread
5587 * is 2.5%; use 5% for safety's sake.
5588 */
5589 u32 bps = target_clock * bpp * 21 / 20;
5590 return bps / (link_bw * 8) + 1;
5591}
5592
7429e9d4 5593static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5594{
7429e9d4 5595 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5596}
5597
de13a2e3 5598static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5599 u32 *fp,
9a7c7890 5600 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5601{
de13a2e3 5602 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5603 struct drm_device *dev = crtc->dev;
5604 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5605 struct intel_encoder *intel_encoder;
5606 uint32_t dpll;
6cc5f341 5607 int factor, num_connectors = 0;
09ede541 5608 bool is_lvds = false, is_sdvo = false;
79e53945 5609
de13a2e3
PZ		 5610 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5611 switch (intel_encoder->type) {
79e53945
JB		 5612 case INTEL_OUTPUT_LVDS:
5613 is_lvds = true;
5614 break;
5615 case INTEL_OUTPUT_SDVO:
7d57382e 5616 case INTEL_OUTPUT_HDMI:
79e53945 5617 is_sdvo = true;
79e53945 5618 break;
79e53945 5619 }
43565a06 5620
c751ce4f 5621 num_connectors++;
79e53945 5622 }
79e53945 5623
c1858123 5624 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5625 factor = 21;
5626 if (is_lvds) {
5627 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5628 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5629 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5630 factor = 25;
09ede541 5631 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5632 factor = 20;
c1858123 5633
7429e9d4 5634 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5635 *fp |= FP_CB_TUNE;
2c07245f 5636
9a7c7890
DV		 5637 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5638 *fp2 |= FP_CB_TUNE;
5639
5eddb70b 5640 dpll = 0;
2c07245f 5641
a07d6787
EA		 5642 if (is_lvds)
5643 dpll |= DPLLB_MODE_LVDS;
5644 else
5645 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5646
ef1b460d
DV		 5647 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5648 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5649
5650 if (is_sdvo)
5651 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5652 if (intel_crtc->config.has_dp_encoder)
a07d6787 5653 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5654
a07d6787 5655 /* compute bitmask from p1 value */
7429e9d4 5656 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5657 /* also FPA1 */
7429e9d4 5658 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5659
7429e9d4 5660 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5661 case 5:
5662 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5663 break;
5664 case 7:
5665 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5666 break;
5667 case 10:
5668 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5669 break;
5670 case 14:
5671 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5672 break;
79e53945
JB		 5673 }
5674
b4c09f3b 5675 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5676 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5677 else
5678 dpll |= PLL_REF_INPUT_DREFCLK;
5679
959e16d6 5680 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5681}
5682
5683static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5684 int x, int y,
5685 struct drm_framebuffer *fb)
5686{
5687 struct drm_device *dev = crtc->dev;
5688 struct drm_i915_private *dev_priv = dev->dev_private;
5689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5690 int pipe = intel_crtc->pipe;
5691 int plane = intel_crtc->plane;
5692 int num_connectors = 0;
5693 intel_clock_t clock, reduced_clock;
cbbab5bd 5694 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5695 bool ok, has_reduced_clock = false;
8b47047b 5696 bool is_lvds = false;
de13a2e3 5697 struct intel_encoder *encoder;
e2b78267 5698 struct intel_shared_dpll *pll;
de13a2e3 5699 int ret;
de13a2e3
PZ		 5700
5701 for_each_encoder_on_crtc(dev, crtc, encoder) {
5702 switch (encoder->type) {
5703 case INTEL_OUTPUT_LVDS:
5704 is_lvds = true;
5705 break;
de13a2e3
PZ		 5706 }
5707
5708 num_connectors++;
a07d6787 5709 }
79e53945 5710
5dc5298b
PZ		 5711 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5712 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5713
ff9a6750 5714 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5715 &has_reduced_clock, &reduced_clock);
ee9300bb 5716 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5717 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5718 return -EINVAL;
79e53945 5719 }
f47709a9
DV		 5720 /* Compat-code for transition, will disappear. */
5721 if (!intel_crtc->config.clock_set) {
5722 intel_crtc->config.dpll.n = clock.n;
5723 intel_crtc->config.dpll.m1 = clock.m1;
5724 intel_crtc->config.dpll.m2 = clock.m2;
5725 intel_crtc->config.dpll.p1 = clock.p1;
5726 intel_crtc->config.dpll.p2 = clock.p2;
5727 }
79e53945 5728
de13a2e3
PZ		 5729 /* Ensure that the cursor is valid for the new mode before changing... */
5730 intel_crtc_update_cursor(crtc, true);
5731
5dc5298b 5732 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5733 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5734 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5735 if (has_reduced_clock)
7429e9d4 5736 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5737
7429e9d4 5738 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5739 &fp, &reduced_clock,
5740 has_reduced_clock ? &fp2 : NULL);
5741
959e16d6 5742 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5743 intel_crtc->config.dpll_hw_state.fp0 = fp;
5744 if (has_reduced_clock)
5745 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5746 else
5747 intel_crtc->config.dpll_hw_state.fp1 = fp;
5748
b89a1d39 5749 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5750 if (pll == NULL) {
84f44ce7
VS		 5751 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5752 pipe_name(pipe));
4b645f14
JB		 5753 return -EINVAL;
5754 }
ee7b9f93 5755 } else
e72f9fbf 5756 intel_put_shared_dpll(intel_crtc);
79e53945 5757
03afc4a2
DV		 5758 if (intel_crtc->config.has_dp_encoder)
5759 intel_dp_set_m_n(intel_crtc);
79e53945 5760
bcd644e0
DV		 5761 if (is_lvds && has_reduced_clock && i915_powersave)
5762 intel_crtc->lowfreq_avail = true;
5763 else
5764 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5765
5766 if (intel_crtc->config.has_pch_encoder) {
5767 pll = intel_crtc_to_shared_dpll(intel_crtc);
5768
652c393a
JB		 5769 }
5770
8a654f3b 5771 intel_set_pipe_timings(intel_crtc);
5eddb70b 5772
ca3a0ff8 5773 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5774 intel_cpu_transcoder_set_m_n(intel_crtc,
5775 &intel_crtc->config.fdi_m_n);
5776 }
2c07245f 5777
ebfd86fd
DV		 5778 if (IS_IVYBRIDGE(dev))
5779 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5780
6ff93609 5781 ironlake_set_pipeconf(crtc);
79e53945 5782
a1f9e77e
PZ		 5783 /* Set up the display plane register */
5784 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5785 POSTING_READ(DSPCNTR(plane));
79e53945 5786
94352cf9 5787 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5788
5789 intel_update_watermarks(dev);
5790
1857e1da 5791 return ret;
79e53945
JB		 5792}
5793
72419203
DV		 5794static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5795 struct intel_crtc_config *pipe_config)
5796{
5797 struct drm_device *dev = crtc->base.dev;
5798 struct drm_i915_private *dev_priv = dev->dev_private;
5799 enum transcoder transcoder = pipe_config->cpu_transcoder;
5800
5801 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5802 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5803 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5804 & ~TU_SIZE_MASK;
5805 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5806 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5807 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5808}
5809
2fa2fe9a
DV		 5810static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5811 struct intel_crtc_config *pipe_config)
5812{
5813 struct drm_device *dev = crtc->base.dev;
5814 struct drm_i915_private *dev_priv = dev->dev_private;
5815 uint32_t tmp;
5816
5817 tmp = I915_READ(PF_CTL(crtc->pipe));
5818
5819 if (tmp & PF_ENABLE) {
5820 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5821 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5822
5823 /* We currently do not free assignements of panel fitters on
5824 * ivb/hsw (since we don't use the higher upscaling modes which
5825 * differentiates them) so just WARN about this case for now. */
5826 if (IS_GEN7(dev)) {
5827 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5828 PF_PIPE_SEL_IVB(crtc->pipe));
5829 }
2fa2fe9a 5830 }
79e53945
JB		 5831}
5832
0e8ffe1b
DV		 5833static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5834 struct intel_crtc_config *pipe_config)
5835{
5836 struct drm_device *dev = crtc->base.dev;
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838 uint32_t tmp;
5839
e143a21c 5840 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5841 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5842
0e8ffe1b
DV		 5843 tmp = I915_READ(PIPECONF(crtc->pipe));
5844 if (!(tmp & PIPECONF_ENABLE))
5845 return false;
5846
ab9412ba 5847 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5848 struct intel_shared_dpll *pll;
5849
88adfff1
DV		 5850 pipe_config->has_pch_encoder = true;
5851
627eb5a3
DV		 5852 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5853 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5854 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5855
5856 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5857
c0d43d62 5858 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 5859 pipe_config->shared_dpll =
5860 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 5861 } else {
5862 tmp = I915_READ(PCH_DPLL_SEL);
5863 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5864 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5865 else
5866 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5867 }
66e985c0
DV		 5868
5869 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5870
5871 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5872 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5873
5874 tmp = pipe_config->dpll_hw_state.dpll;
5875 pipe_config->pixel_multiplier =
5876 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5877 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5878 } else {
5879 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5880 }
5881
1bd1bd80
DV		 5882 intel_get_pipe_timings(crtc, pipe_config);
5883
2fa2fe9a
DV		 5884 ironlake_get_pfit_config(crtc, pipe_config);
5885
0e8ffe1b
DV		 5886 return true;
5887}
5888
d6dd9eb1
DV		 5889static void haswell_modeset_global_resources(struct drm_device *dev)
5890{
d6dd9eb1
DV		 5891 bool enable = false;
5892 struct intel_crtc *crtc;
d6dd9eb1
DV		 5893
5894 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5895 if (!crtc->base.enabled)
5896 continue;
d6dd9eb1 5897
e7a639c4
DV		 5898 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5899 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5900 enable = true;
5901 }
5902
d6dd9eb1
DV		 5903 intel_set_power_well(dev, enable);
5904}
5905
09b4ddf9 5906static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5907 int x, int y,
5908 struct drm_framebuffer *fb)
5909{
5910 struct drm_device *dev = crtc->dev;
5911 struct drm_i915_private *dev_priv = dev->dev_private;
5912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5913 int plane = intel_crtc->plane;
09b4ddf9 5914 int ret;
09b4ddf9 5915
ff9a6750 5916 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5917 return -EINVAL;
5918
09b4ddf9
PZ		 5919 /* Ensure that the cursor is valid for the new mode before changing... */
5920 intel_crtc_update_cursor(crtc, true);
5921
03afc4a2
DV		 5922 if (intel_crtc->config.has_dp_encoder)
5923 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5924
5925 intel_crtc->lowfreq_avail = false;
09b4ddf9 5926
8a654f3b 5927 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5928
ca3a0ff8 5929 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5930 intel_cpu_transcoder_set_m_n(intel_crtc,
5931 &intel_crtc->config.fdi_m_n);
5932 }
09b4ddf9 5933
6ff93609 5934 haswell_set_pipeconf(crtc);
09b4ddf9 5935
50f3b016 5936 intel_set_pipe_csc(crtc);
86d3efce 5937
09b4ddf9 5938 /* Set up the display plane register */
86d3efce 5939 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5940 POSTING_READ(DSPCNTR(plane));
5941
5942 ret = intel_pipe_set_base(crtc, x, y, fb);
5943
5944 intel_update_watermarks(dev);
5945
1f803ee5 5946 return ret;
79e53945
JB		 5947}
5948
0e8ffe1b
DV		 5949static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5950 struct intel_crtc_config *pipe_config)
5951{
5952 struct drm_device *dev = crtc->base.dev;
5953 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5954 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5955 uint32_t tmp;
5956
e143a21c 5957 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 5958 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5959
eccb140b
DV		 5960 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5961 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5962 enum pipe trans_edp_pipe;
5963 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5964 default:
5965 WARN(1, "unknown pipe linked to edp transcoder\n");
5966 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5967 case TRANS_DDI_EDP_INPUT_A_ON:
5968 trans_edp_pipe = PIPE_A;
5969 break;
5970 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5971 trans_edp_pipe = PIPE_B;
5972 break;
5973 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5974 trans_edp_pipe = PIPE_C;
5975 break;
5976 }
5977
5978 if (trans_edp_pipe == crtc->pipe)
5979 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5980 }
5981
b97186f0 5982 if (!intel_display_power_enabled(dev,
eccb140b 5983 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5984 return false;
5985
eccb140b 5986 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5987 if (!(tmp & PIPECONF_ENABLE))
5988 return false;
5989
88adfff1 5990 /*
f196e6be 5991 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5992 * DDI E. So just check whether this pipe is wired to DDI E and whether
5993 * the PCH transcoder is on.
5994 */
eccb140b 5995 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5996 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5997 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5998 pipe_config->has_pch_encoder = true;
5999
627eb5a3
DV		 6000 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6001 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6002 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6003
6004 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6005 }
6006
1bd1bd80
DV		 6007 intel_get_pipe_timings(crtc, pipe_config);
6008
2fa2fe9a
DV		 6009 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6010 if (intel_display_power_enabled(dev, pfit_domain))
6011 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6012
42db64ef
PZ		 6013 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6014 (I915_READ(IPS_CTL) & IPS_ENABLE);
6015
6c49f241
DV		 6016 pipe_config->pixel_multiplier = 1;
6017
0e8ffe1b
DV		 6018 return true;
6019}
6020
f564048e 6021static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6022 int x, int y,
94352cf9 6023 struct drm_framebuffer *fb)
f564048e
EA		 6024{
6025 struct drm_device *dev = crtc->dev;
6026 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6027 struct drm_encoder_helper_funcs *encoder_funcs;
6028 struct intel_encoder *encoder;
0b701d27 6029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6030 struct drm_display_mode *adjusted_mode =
6031 &intel_crtc->config.adjusted_mode;
6032 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6033 int pipe = intel_crtc->pipe;
f564048e
EA		 6034 int ret;
6035
0b701d27 6036 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6037
b8cecdf5
DV		 6038 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6039
79e53945 6040 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6041
9256aa19
DV		 6042 if (ret != 0)
6043 return ret;
6044
6045 for_each_encoder_on_crtc(dev, crtc, encoder) {
6046 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6047 encoder->base.base.id,
6048 drm_get_encoder_name(&encoder->base),
6049 mode->base.id, mode->name);
6cc5f341
DV		 6050 if (encoder->mode_set) {
6051 encoder->mode_set(encoder);
6052 } else {
6053 encoder_funcs = encoder->base.helper_private;
6054 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6055 }
9256aa19
DV		 6056 }
6057
6058 return 0;
79e53945
JB		 6059}
6060
3a9627f4
WF		 6061static bool intel_eld_uptodate(struct drm_connector *connector,
6062 int reg_eldv, uint32_t bits_eldv,
6063 int reg_elda, uint32_t bits_elda,
6064 int reg_edid)
6065{
6066 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6067 uint8_t *eld = connector->eld;
6068 uint32_t i;
6069
6070 i = I915_READ(reg_eldv);
6071 i &= bits_eldv;
6072
6073 if (!eld[0])
6074 return !i;
6075
6076 if (!i)
6077 return false;
6078
6079 i = I915_READ(reg_elda);
6080 i &= ~bits_elda;
6081 I915_WRITE(reg_elda, i);
6082
6083 for (i = 0; i < eld[2]; i++)
6084 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6085 return false;
6086
6087 return true;
6088}
6089
e0dac65e
WF		 6090static void g4x_write_eld(struct drm_connector *connector,
6091 struct drm_crtc *crtc)
6092{
6093 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6094 uint8_t *eld = connector->eld;
6095 uint32_t eldv;
6096 uint32_t len;
6097 uint32_t i;
6098
6099 i = I915_READ(G4X_AUD_VID_DID);
6100
6101 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6102 eldv = G4X_ELDV_DEVCL_DEVBLC;
6103 else
6104 eldv = G4X_ELDV_DEVCTG;
6105
3a9627f4
WF		 6106 if (intel_eld_uptodate(connector,
6107 G4X_AUD_CNTL_ST, eldv,
6108 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6109 G4X_HDMIW_HDMIEDID))
6110 return;
6111
e0dac65e
WF		 6112 i = I915_READ(G4X_AUD_CNTL_ST);
6113 i &= ~(eldv | G4X_ELD_ADDR);
6114 len = (i >> 9) & 0x1f; /* ELD buffer size */
6115 I915_WRITE(G4X_AUD_CNTL_ST, i);
6116
6117 if (!eld[0])
6118 return;
6119
6120 len = min_t(uint8_t, eld[2], len);
6121 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6122 for (i = 0; i < len; i++)
6123 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6124
6125 i = I915_READ(G4X_AUD_CNTL_ST);
6126 i |= eldv;
6127 I915_WRITE(G4X_AUD_CNTL_ST, i);
6128}
6129
83358c85
WX		 6130static void haswell_write_eld(struct drm_connector *connector,
6131 struct drm_crtc *crtc)
6132{
6133 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6134 uint8_t *eld = connector->eld;
6135 struct drm_device *dev = crtc->dev;
7b9f35a6 6136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6137 uint32_t eldv;
6138 uint32_t i;
6139 int len;
6140 int pipe = to_intel_crtc(crtc)->pipe;
6141 int tmp;
6142
6143 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6144 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6145 int aud_config = HSW_AUD_CFG(pipe);
6146 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6147
6148
6149 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6150
6151 /* Audio output enable */
6152 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6153 tmp = I915_READ(aud_cntrl_st2);
6154 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6155 I915_WRITE(aud_cntrl_st2, tmp);
6156
6157 /* Wait for 1 vertical blank */
6158 intel_wait_for_vblank(dev, pipe);
6159
6160 /* Set ELD valid state */
6161 tmp = I915_READ(aud_cntrl_st2);
6162 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6163 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6164 I915_WRITE(aud_cntrl_st2, tmp);
6165 tmp = I915_READ(aud_cntrl_st2);
6166 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6167
6168 /* Enable HDMI mode */
6169 tmp = I915_READ(aud_config);
6170 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6171 /* clear N_programing_enable and N_value_index */
6172 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6173 I915_WRITE(aud_config, tmp);
6174
6175 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6176
6177 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6178 intel_crtc->eld_vld = true;
83358c85
WX		 6179
6180 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6181 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6182 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6183 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6184 } else
6185 I915_WRITE(aud_config, 0);
6186
6187 if (intel_eld_uptodate(connector,
6188 aud_cntrl_st2, eldv,
6189 aud_cntl_st, IBX_ELD_ADDRESS,
6190 hdmiw_hdmiedid))
6191 return;
6192
6193 i = I915_READ(aud_cntrl_st2);
6194 i &= ~eldv;
6195 I915_WRITE(aud_cntrl_st2, i);
6196
6197 if (!eld[0])
6198 return;
6199
6200 i = I915_READ(aud_cntl_st);
6201 i &= ~IBX_ELD_ADDRESS;
6202 I915_WRITE(aud_cntl_st, i);
6203 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6204 DRM_DEBUG_DRIVER("port num:%d\n", i);
6205
6206 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6207 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6208 for (i = 0; i < len; i++)
6209 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6210
6211 i = I915_READ(aud_cntrl_st2);
6212 i |= eldv;
6213 I915_WRITE(aud_cntrl_st2, i);
6214
6215}
6216
e0dac65e
WF		 6217static void ironlake_write_eld(struct drm_connector *connector,
6218 struct drm_crtc *crtc)
6219{
6220 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6221 uint8_t *eld = connector->eld;
6222 uint32_t eldv;
6223 uint32_t i;
6224 int len;
6225 int hdmiw_hdmiedid;
b6daa025 6226 int aud_config;
e0dac65e
WF		 6227 int aud_cntl_st;
6228 int aud_cntrl_st2;
9b138a83 6229 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6230
b3f33cbf 6231 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6232 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6233 aud_config = IBX_AUD_CFG(pipe);
6234 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6235 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6236 } else {
9b138a83
WX		 6237 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6238 aud_config = CPT_AUD_CFG(pipe);
6239 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6240 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6241 }
6242
9b138a83 6243 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6244
6245 i = I915_READ(aud_cntl_st);
9b138a83 6246 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6247 if (!i) {
6248 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6249 /* operate blindly on all ports */
1202b4c6
WF		 6250 eldv = IBX_ELD_VALIDB;
6251 eldv |= IBX_ELD_VALIDB << 4;
6252 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6253 } else {
2582a850 6254 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6255 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6256 }
6257
3a9627f4
WF		 6258 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6259 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6260 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6261 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6262 } else
6263 I915_WRITE(aud_config, 0);
e0dac65e 6264
3a9627f4
WF		 6265 if (intel_eld_uptodate(connector,
6266 aud_cntrl_st2, eldv,
6267 aud_cntl_st, IBX_ELD_ADDRESS,
6268 hdmiw_hdmiedid))
6269 return;
6270
e0dac65e
WF		 6271 i = I915_READ(aud_cntrl_st2);
6272 i &= ~eldv;
6273 I915_WRITE(aud_cntrl_st2, i);
6274
6275 if (!eld[0])
6276 return;
6277
e0dac65e 6278 i = I915_READ(aud_cntl_st);
1202b4c6 6279 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6280 I915_WRITE(aud_cntl_st, i);
6281
6282 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6283 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6284 for (i = 0; i < len; i++)
6285 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6286
6287 i = I915_READ(aud_cntrl_st2);
6288 i |= eldv;
6289 I915_WRITE(aud_cntrl_st2, i);
6290}
6291
6292void intel_write_eld(struct drm_encoder *encoder,
6293 struct drm_display_mode *mode)
6294{
6295 struct drm_crtc *crtc = encoder->crtc;
6296 struct drm_connector *connector;
6297 struct drm_device *dev = encoder->dev;
6298 struct drm_i915_private *dev_priv = dev->dev_private;
6299
6300 connector = drm_select_eld(encoder, mode);
6301 if (!connector)
6302 return;
6303
6304 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6305 connector->base.id,
6306 drm_get_connector_name(connector),
6307 connector->encoder->base.id,
6308 drm_get_encoder_name(connector->encoder));
6309
6310 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6311
6312 if (dev_priv->display.write_eld)
6313 dev_priv->display.write_eld(connector, crtc);
6314}
6315
79e53945
JB		 6316/** Loads the palette/gamma unit for the CRTC with the prepared values */
6317void intel_crtc_load_lut(struct drm_crtc *crtc)
6318{
6319 struct drm_device *dev = crtc->dev;
6320 struct drm_i915_private *dev_priv = dev->dev_private;
6321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6322 enum pipe pipe = intel_crtc->pipe;
6323 int palreg = PALETTE(pipe);
79e53945 6324 int i;
42db64ef 6325 bool reenable_ips = false;
79e53945
JB		 6326
6327 /* The clocks have to be on to load the palette. */
aed3f09d 6328 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6329 return;
6330
14420bd0
VS		 6331 if (!HAS_PCH_SPLIT(dev_priv->dev))
6332 assert_pll_enabled(dev_priv, pipe);
6333
f2b115e6 6334 /* use legacy palette for Ironlake */
bad720ff 6335 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6336 palreg = LGC_PALETTE(pipe);
6337
6338 /* Workaround : Do not read or write the pipe palette/gamma data while
6339 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6340 */
6341 if (intel_crtc->config.ips_enabled &&
6342 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6343 GAMMA_MODE_MODE_SPLIT)) {
6344 hsw_disable_ips(intel_crtc);
6345 reenable_ips = true;
6346 }
2c07245f 6347
79e53945
JB		 6348 for (i = 0; i < 256; i++) {
6349 I915_WRITE(palreg + 4 * i,
6350 (intel_crtc->lut_r[i] << 16) |
6351 (intel_crtc->lut_g[i] << 8) |
6352 intel_crtc->lut_b[i]);
6353 }
42db64ef
PZ		 6354
6355 if (reenable_ips)
6356 hsw_enable_ips(intel_crtc);
79e53945
JB		 6357}
6358
560b85bb
CW		 6359static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6360{
6361 struct drm_device *dev = crtc->dev;
6362 struct drm_i915_private *dev_priv = dev->dev_private;
6363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6364 bool visible = base != 0;
6365 u32 cntl;
6366
6367 if (intel_crtc->cursor_visible == visible)
6368 return;
6369
9db4a9c7 6370 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6371 if (visible) {
6372 /* On these chipsets we can only modify the base whilst
6373 * the cursor is disabled.
6374 */
9db4a9c7 6375 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6376
6377 cntl &= ~(CURSOR_FORMAT_MASK);
6378 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6379 cntl |= CURSOR_ENABLE |
6380 CURSOR_GAMMA_ENABLE |
6381 CURSOR_FORMAT_ARGB;
6382 } else
6383 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6384 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6385
6386 intel_crtc->cursor_visible = visible;
6387}
6388
6389static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6390{
6391 struct drm_device *dev = crtc->dev;
6392 struct drm_i915_private *dev_priv = dev->dev_private;
6393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6394 int pipe = intel_crtc->pipe;
6395 bool visible = base != 0;
6396
6397 if (intel_crtc->cursor_visible != visible) {
548f245b 6398 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6399 if (base) {
6400 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6401 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6402 cntl |= pipe << 28; /* Connect to correct pipe */
6403 } else {
6404 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6405 cntl |= CURSOR_MODE_DISABLE;
6406 }
9db4a9c7 6407 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6408
6409 intel_crtc->cursor_visible = visible;
6410 }
6411 /* and commit changes on next vblank */
9db4a9c7 6412 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6413}
6414
65a21cd6
JB		 6415static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6416{
6417 struct drm_device *dev = crtc->dev;
6418 struct drm_i915_private *dev_priv = dev->dev_private;
6419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6420 int pipe = intel_crtc->pipe;
6421 bool visible = base != 0;
6422
6423 if (intel_crtc->cursor_visible != visible) {
6424 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6425 if (base) {
6426 cntl &= ~CURSOR_MODE;
6427 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6428 } else {
6429 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6430 cntl |= CURSOR_MODE_DISABLE;
6431 }
86d3efce
VS		 6432 if (IS_HASWELL(dev))
6433 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6434 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6435
6436 intel_crtc->cursor_visible = visible;
6437 }
6438 /* and commit changes on next vblank */
6439 I915_WRITE(CURBASE_IVB(pipe), base);
6440}
6441
cda4b7d3 6442/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6443static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6444 bool on)
cda4b7d3
CW		 6445{
6446 struct drm_device *dev = crtc->dev;
6447 struct drm_i915_private *dev_priv = dev->dev_private;
6448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6449 int pipe = intel_crtc->pipe;
6450 int x = intel_crtc->cursor_x;
6451 int y = intel_crtc->cursor_y;
560b85bb 6452 u32 base, pos;
cda4b7d3
CW		 6453 bool visible;
6454
6455 pos = 0;
6456
6b383a7f 6457 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6458 base = intel_crtc->cursor_addr;
6459 if (x > (int) crtc->fb->width)
6460 base = 0;
6461
6462 if (y > (int) crtc->fb->height)
6463 base = 0;
6464 } else
6465 base = 0;
6466
6467 if (x < 0) {
6468 if (x + intel_crtc->cursor_width < 0)
6469 base = 0;
6470
6471 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6472 x = -x;
6473 }
6474 pos |= x << CURSOR_X_SHIFT;
6475
6476 if (y < 0) {
6477 if (y + intel_crtc->cursor_height < 0)
6478 base = 0;
6479
6480 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6481 y = -y;
6482 }
6483 pos |= y << CURSOR_Y_SHIFT;
6484
6485 visible = base != 0;
560b85bb 6486 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6487 return;
6488
0cd83aa9 6489 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6490 I915_WRITE(CURPOS_IVB(pipe), pos);
6491 ivb_update_cursor(crtc, base);
6492 } else {
6493 I915_WRITE(CURPOS(pipe), pos);
6494 if (IS_845G(dev) || IS_I865G(dev))
6495 i845_update_cursor(crtc, base);
6496 else
6497 i9xx_update_cursor(crtc, base);
6498 }
cda4b7d3
CW		 6499}
6500
79e53945 6501static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6502 struct drm_file *file,
79e53945
JB		 6503 uint32_t handle,
6504 uint32_t width, uint32_t height)
6505{
6506 struct drm_device *dev = crtc->dev;
6507 struct drm_i915_private *dev_priv = dev->dev_private;
6508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6509 struct drm_i915_gem_object *obj;
cda4b7d3 6510 uint32_t addr;
3f8bc370 6511 int ret;
79e53945 6512
79e53945
JB		 6513 /* if we want to turn off the cursor ignore width and height */
6514 if (!handle) {
28c97730 6515 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6516 addr = 0;
05394f39 6517 obj = NULL;
5004417d 6518 mutex_lock(&dev->struct_mutex);
3f8bc370 6519 goto finish;
79e53945
JB		 6520 }
6521
6522 /* Currently we only support 64x64 cursors */
6523 if (width != 64 || height != 64) {
6524 DRM_ERROR("we currently only support 64x64 cursors\n");
6525 return -EINVAL;
6526 }
6527
05394f39 6528 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6529 if (&obj->base == NULL)
79e53945
JB		 6530 return -ENOENT;
6531
05394f39 6532 if (obj->base.size < width * height * 4) {
79e53945 6533 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6534 ret = -ENOMEM;
6535 goto fail;
79e53945
JB		 6536 }
6537
71acb5eb 6538 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6539 mutex_lock(&dev->struct_mutex);
b295d1b6 6540 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6541 unsigned alignment;
6542
d9e86c0e
CW		 6543 if (obj->tiling_mode) {
6544 DRM_ERROR("cursor cannot be tiled\n");
6545 ret = -EINVAL;
6546 goto fail_locked;
6547 }
6548
693db184
CW		 6549 /* Note that the w/a also requires 2 PTE of padding following
6550 * the bo. We currently fill all unused PTE with the shadow
6551 * page and so we should always have valid PTE following the
6552 * cursor preventing the VT-d warning.
6553 */
6554 alignment = 0;
6555 if (need_vtd_wa(dev))
6556 alignment = 64*1024;
6557
6558 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6559 if (ret) {
6560 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6561 goto fail_locked;
e7b526bb
CW		 6562 }
6563
d9e86c0e
CW		 6564 ret = i915_gem_object_put_fence(obj);
6565 if (ret) {
2da3b9b9 6566 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6567 goto fail_unpin;
6568 }
6569
05394f39 6570 addr = obj->gtt_offset;
71acb5eb 6571 } else {
6eeefaf3 6572 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6573 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6574 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6575 align);
71acb5eb
DA		 6576 if (ret) {
6577 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6578 goto fail_locked;
71acb5eb 6579 }
05394f39 6580 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6581 }
6582
a6c45cf0 6583 if (IS_GEN2(dev))
14b60391
JB		 6584 I915_WRITE(CURSIZE, (height << 12) | width);
6585
3f8bc370 6586 finish:
3f8bc370 6587 if (intel_crtc->cursor_bo) {
b295d1b6 6588 if (dev_priv->info->cursor_needs_physical) {
05394f39 6589 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6590 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6591 } else
6592 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6593 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6594 }
80824003 6595
7f9872e0 6596 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6597
6598 intel_crtc->cursor_addr = addr;
05394f39 6599 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6600 intel_crtc->cursor_width = width;
6601 intel_crtc->cursor_height = height;
6602
40ccc72b 6603 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6604
79e53945 6605 return 0;
e7b526bb 6606fail_unpin:
05394f39 6607 i915_gem_object_unpin(obj);
7f9872e0 6608fail_locked:
34b8686e 6609 mutex_unlock(&dev->struct_mutex);
bc9025bd 6610fail:
05394f39 6611 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6612 return ret;
79e53945
JB		 6613}
6614
6615static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6616{
79e53945 6617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6618
cda4b7d3
CW		 6619 intel_crtc->cursor_x = x;
6620 intel_crtc->cursor_y = y;
652c393a 6621
40ccc72b 6622 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6623
6624 return 0;
6625}
6626
6627/** Sets the color ramps on behalf of RandR */
6628void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6629 u16 blue, int regno)
6630{
6631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6632
6633 intel_crtc->lut_r[regno] = red >> 8;
6634 intel_crtc->lut_g[regno] = green >> 8;
6635 intel_crtc->lut_b[regno] = blue >> 8;
6636}
6637
b8c00ac5
DA		 6638void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6639 u16 *blue, int regno)
6640{
6641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6642
6643 *red = intel_crtc->lut_r[regno] << 8;
6644 *green = intel_crtc->lut_g[regno] << 8;
6645 *blue = intel_crtc->lut_b[regno] << 8;
6646}
6647
79e53945 6648static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6649 u16 *blue, uint32_t start, uint32_t size)
79e53945 6650{
7203425a 6651 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6653
7203425a 6654 for (i = start; i < end; i++) {
79e53945
JB		 6655 intel_crtc->lut_r[i] = red[i] >> 8;
6656 intel_crtc->lut_g[i] = green[i] >> 8;
6657 intel_crtc->lut_b[i] = blue[i] >> 8;
6658 }
6659
6660 intel_crtc_load_lut(crtc);
6661}
6662
79e53945
JB		 6663/* VESA 640x480x72Hz mode to set on the pipe */
6664static struct drm_display_mode load_detect_mode = {
6665 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6666 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6667};
6668
d2dff872
CW		 6669static struct drm_framebuffer *
6670intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6671 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6672 struct drm_i915_gem_object *obj)
6673{
6674 struct intel_framebuffer *intel_fb;
6675 int ret;
6676
6677 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6678 if (!intel_fb) {
6679 drm_gem_object_unreference_unlocked(&obj->base);
6680 return ERR_PTR(-ENOMEM);
6681 }
6682
6683 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6684 if (ret) {
6685 drm_gem_object_unreference_unlocked(&obj->base);
6686 kfree(intel_fb);
6687 return ERR_PTR(ret);
6688 }
6689
6690 return &intel_fb->base;
6691}
6692
6693static u32
6694intel_framebuffer_pitch_for_width(int width, int bpp)
6695{
6696 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6697 return ALIGN(pitch, 64);
6698}
6699
6700static u32
6701intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6702{
6703 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6704 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6705}
6706
6707static struct drm_framebuffer *
6708intel_framebuffer_create_for_mode(struct drm_device *dev,
6709 struct drm_display_mode *mode,
6710 int depth, int bpp)
6711{
6712 struct drm_i915_gem_object *obj;
0fed39bd 6713 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6714
6715 obj = i915_gem_alloc_object(dev,
6716 intel_framebuffer_size_for_mode(mode, bpp));
6717 if (obj == NULL)
6718 return ERR_PTR(-ENOMEM);
6719
6720 mode_cmd.width = mode->hdisplay;
6721 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6722 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6723 bpp);
5ca0c34a 6724 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6725
6726 return intel_framebuffer_create(dev, &mode_cmd, obj);
6727}
6728
6729static struct drm_framebuffer *
6730mode_fits_in_fbdev(struct drm_device *dev,
6731 struct drm_display_mode *mode)
6732{
6733 struct drm_i915_private *dev_priv = dev->dev_private;
6734 struct drm_i915_gem_object *obj;
6735 struct drm_framebuffer *fb;
6736
6737 if (dev_priv->fbdev == NULL)
6738 return NULL;
6739
6740 obj = dev_priv->fbdev->ifb.obj;
6741 if (obj == NULL)
6742 return NULL;
6743
6744 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6745 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6746 fb->bits_per_pixel))
d2dff872
CW		 6747 return NULL;
6748
01f2c773 6749 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6750 return NULL;
6751
6752 return fb;
6753}
6754
d2434ab7 6755bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6756 struct drm_display_mode *mode,
8261b191 6757 struct intel_load_detect_pipe *old)
79e53945
JB		 6758{
6759 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6760 struct intel_encoder *intel_encoder =
6761 intel_attached_encoder(connector);
79e53945 6762 struct drm_crtc *possible_crtc;
4ef69c7a 6763 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6764 struct drm_crtc *crtc = NULL;
6765 struct drm_device *dev = encoder->dev;
94352cf9 6766 struct drm_framebuffer *fb;
79e53945
JB		 6767 int i = -1;
6768
d2dff872
CW		 6769 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6770 connector->base.id, drm_get_connector_name(connector),
6771 encoder->base.id, drm_get_encoder_name(encoder));
6772
79e53945
JB		 6773 /*
6774 * Algorithm gets a little messy:
7a5e4805 6775 *
79e53945
JB		 6776 * - if the connector already has an assigned crtc, use it (but make
6777 * sure it's on first)
7a5e4805 6778 *
79e53945
JB		 6779 * - try to find the first unused crtc that can drive this connector,
6780 * and use that if we find one
79e53945
JB		 6781 */
6782
6783 /* See if we already have a CRTC for this connector */
6784 if (encoder->crtc) {
6785 crtc = encoder->crtc;
8261b191 6786
7b24056b
DV		 6787 mutex_lock(&crtc->mutex);
6788
24218aac 6789 old->dpms_mode = connector->dpms;
8261b191
CW		 6790 old->load_detect_temp = false;
6791
6792 /* Make sure the crtc and connector are running */
24218aac
DV		 6793 if (connector->dpms != DRM_MODE_DPMS_ON)
6794 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6795
7173188d 6796 return true;
79e53945
JB		 6797 }
6798
6799 /* Find an unused one (if possible) */
6800 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6801 i++;
6802 if (!(encoder->possible_crtcs & (1 << i)))
6803 continue;
6804 if (!possible_crtc->enabled) {
6805 crtc = possible_crtc;
6806 break;
6807 }
79e53945
JB		 6808 }
6809
6810 /*
6811 * If we didn't find an unused CRTC, don't use any.
6812 */
6813 if (!crtc) {
7173188d
CW		 6814 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6815 return false;
79e53945
JB		 6816 }
6817
7b24056b 6818 mutex_lock(&crtc->mutex);
fc303101
DV		 6819 intel_encoder->new_crtc = to_intel_crtc(crtc);
6820 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6821
6822 intel_crtc = to_intel_crtc(crtc);
24218aac 6823 old->dpms_mode = connector->dpms;
8261b191 6824 old->load_detect_temp = true;
d2dff872 6825 old->release_fb = NULL;
79e53945 6826
6492711d
CW		 6827 if (!mode)
6828 mode = &load_detect_mode;
79e53945 6829
d2dff872
CW		 6830 /* We need a framebuffer large enough to accommodate all accesses
6831 * that the plane may generate whilst we perform load detection.
6832 * We can not rely on the fbcon either being present (we get called
6833 * during its initialisation to detect all boot displays, or it may
6834 * not even exist) or that it is large enough to satisfy the
6835 * requested mode.
6836 */
94352cf9
DV		 6837 fb = mode_fits_in_fbdev(dev, mode);
6838 if (fb == NULL) {
d2dff872 6839 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6840 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6841 old->release_fb = fb;
d2dff872
CW		 6842 } else
6843 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6844 if (IS_ERR(fb)) {
d2dff872 6845 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6846 mutex_unlock(&crtc->mutex);
0e8b3d3e 6847 return false;
79e53945 6848 }
79e53945 6849
c0c36b94 6850 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6851 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6852 if (old->release_fb)
6853 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6854 mutex_unlock(&crtc->mutex);
0e8b3d3e 6855 return false;
79e53945 6856 }
7173188d 6857
79e53945 6858 /* let the connector get through one full cycle before testing */
9d0498a2 6859 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6860 return true;
79e53945
JB		 6861}
6862
d2434ab7 6863void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6864 struct intel_load_detect_pipe *old)
79e53945 6865{
d2434ab7
DV		 6866 struct intel_encoder *intel_encoder =
6867 intel_attached_encoder(connector);
4ef69c7a 6868 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6869 struct drm_crtc *crtc = encoder->crtc;
79e53945 6870
d2dff872
CW		 6871 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6872 connector->base.id, drm_get_connector_name(connector),
6873 encoder->base.id, drm_get_encoder_name(encoder));
6874
8261b191 6875 if (old->load_detect_temp) {
fc303101
DV		 6876 to_intel_connector(connector)->new_encoder = NULL;
6877 intel_encoder->new_crtc = NULL;
6878 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6879
36206361
DV		 6880 if (old->release_fb) {
6881 drm_framebuffer_unregister_private(old->release_fb);
6882 drm_framebuffer_unreference(old->release_fb);
6883 }
d2dff872 6884
67c96400 6885 mutex_unlock(&crtc->mutex);
0622a53c 6886 return;
79e53945
JB		 6887 }
6888
c751ce4f 6889 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6890 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6891 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6892
6893 mutex_unlock(&crtc->mutex);
79e53945
JB		 6894}
6895
6896/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 6897static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6898 struct intel_crtc_config *pipe_config)
79e53945 6899{
f1f644dc 6900 struct drm_device *dev = crtc->base.dev;
79e53945 6901 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 6902 int pipe = pipe_config->cpu_transcoder;
548f245b 6903 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6904 u32 fp;
6905 intel_clock_t clock;
6906
6907 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6908 fp = I915_READ(FP0(pipe));
79e53945 6909 else
39adb7a5 6910 fp = I915_READ(FP1(pipe));
79e53945
JB		 6911
6912 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6913 if (IS_PINEVIEW(dev)) {
6914 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6915 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6916 } else {
6917 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6918 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6919 }
6920
a6c45cf0 6921 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6922 if (IS_PINEVIEW(dev))
6923 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6924 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6925 else
6926 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6927 DPLL_FPA01_P1_POST_DIV_SHIFT);
6928
6929 switch (dpll & DPLL_MODE_MASK) {
6930 case DPLLB_MODE_DAC_SERIAL:
6931 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6932 5 : 10;
6933 break;
6934 case DPLLB_MODE_LVDS:
6935 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6936 7 : 14;
6937 break;
6938 default:
28c97730 6939 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 6940 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 6941 pipe_config->adjusted_mode.clock = 0;
6942 return;
79e53945
JB		 6943 }
6944
ac58c3f0
DV		 6945 if (IS_PINEVIEW(dev))
6946 pineview_clock(96000, &clock);
6947 else
6948 i9xx_clock(96000, &clock);
79e53945
JB		 6949 } else {
6950 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6951
6952 if (is_lvds) {
6953 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6954 DPLL_FPA01_P1_POST_DIV_SHIFT);
6955 clock.p2 = 14;
6956
6957 if ((dpll & PLL_REF_INPUT_MASK) ==
6958 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6959 /* XXX: might not be 66MHz */
ac58c3f0 6960 i9xx_clock(66000, &clock);
79e53945 6961 } else
ac58c3f0 6962 i9xx_clock(48000, &clock);
79e53945
JB		 6963 } else {
6964 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6965 clock.p1 = 2;
6966 else {
6967 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6968 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6969 }
6970 if (dpll & PLL_P2_DIVIDE_BY_4)
6971 clock.p2 = 4;
6972 else
6973 clock.p2 = 2;
6974
ac58c3f0 6975 i9xx_clock(48000, &clock);
79e53945
JB		 6976 }
6977 }
6978
f1f644dc
JB		 6979 pipe_config->adjusted_mode.clock = clock.dot *
6980 pipe_config->pixel_multiplier;
6981}
6982
6983static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
6984 struct intel_crtc_config *pipe_config)
6985{
6986 struct drm_device *dev = crtc->base.dev;
6987 struct drm_i915_private *dev_priv = dev->dev_private;
6988 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6989 int link_freq, repeat;
6990 u64 clock;
6991 u32 link_m, link_n;
6992
6993 repeat = pipe_config->pixel_multiplier;
6994
6995 /*
6996 * The calculation for the data clock is:
6997 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
6998 * But we want to avoid losing precison if possible, so:
6999 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7000 *
7001 * and the link clock is simpler:
7002 * link_clock = (m * link_clock * repeat) / n
7003 */
7004
7005 /*
7006 * We need to get the FDI or DP link clock here to derive
7007 * the M/N dividers.
7008 *
7009 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7010 * For DP, it's either 1.62GHz or 2.7GHz.
7011 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7012 */
f1f644dc
JB		 7013 if (pipe_config->has_pch_encoder)
7014 link_freq = intel_fdi_link_freq(dev) * 10000;
7015 else
7016 link_freq = pipe_config->port_clock;
7017
7018 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7019 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7020
7021 if (!link_m || !link_n)
7022 return;
79e53945 7023
f1f644dc
JB		 7024 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7025 do_div(clock, link_n);
7026
7027 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 7028}
7029
7030/** Returns the currently programmed mode of the given pipe. */
7031struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7032 struct drm_crtc *crtc)
7033{
548f245b 7034 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7036 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7037 struct drm_display_mode *mode;
f1f644dc 7038 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7039 int htot = I915_READ(HTOTAL(cpu_transcoder));
7040 int hsync = I915_READ(HSYNC(cpu_transcoder));
7041 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7042 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7043
7044 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7045 if (!mode)
7046 return NULL;
7047
f1f644dc
JB		 7048 /*
7049 * Construct a pipe_config sufficient for getting the clock info
7050 * back out of crtc_clock_get.
7051 *
7052 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7053 * to use a real value here instead.
7054 */
e143a21c 7055 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB		 7056 pipe_config.pixel_multiplier = 1;
7057 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7058
7059 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7060 mode->hdisplay = (htot & 0xffff) + 1;
7061 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7062 mode->hsync_start = (hsync & 0xffff) + 1;
7063 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7064 mode->vdisplay = (vtot & 0xffff) + 1;
7065 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7066 mode->vsync_start = (vsync & 0xffff) + 1;
7067 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7068
7069 drm_mode_set_name(mode);
79e53945
JB		 7070
7071 return mode;
7072}
7073
3dec0095 7074static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7075{
7076 struct drm_device *dev = crtc->dev;
7077 drm_i915_private_t *dev_priv = dev->dev_private;
7078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7079 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7080 int dpll_reg = DPLL(pipe);
7081 int dpll;
652c393a 7082
bad720ff 7083 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7084 return;
7085
7086 if (!dev_priv->lvds_downclock_avail)
7087 return;
7088
dbdc6479 7089 dpll = I915_READ(dpll_reg);
652c393a 7090 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7091 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7092
8ac5a6d5 7093 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7094
7095 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7096 I915_WRITE(dpll_reg, dpll);
9d0498a2 7097 intel_wait_for_vblank(dev, pipe);
dbdc6479 7098
652c393a
JB		 7099 dpll = I915_READ(dpll_reg);
7100 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7101 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7102 }
652c393a
JB		 7103}
7104
7105static void intel_decrease_pllclock(struct drm_crtc *crtc)
7106{
7107 struct drm_device *dev = crtc->dev;
7108 drm_i915_private_t *dev_priv = dev->dev_private;
7109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7110
bad720ff 7111 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7112 return;
7113
7114 if (!dev_priv->lvds_downclock_avail)
7115 return;
7116
7117 /*
7118 * Since this is called by a timer, we should never get here in
7119 * the manual case.
7120 */
7121 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7122 int pipe = intel_crtc->pipe;
7123 int dpll_reg = DPLL(pipe);
7124 int dpll;
f6e5b160 7125
44d98a61 7126 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7127
8ac5a6d5 7128 assert_panel_unlocked(dev_priv, pipe);
652c393a 7129
dc257cf1 7130 dpll = I915_READ(dpll_reg);
652c393a
JB		 7131 dpll |= DISPLAY_RATE_SELECT_FPA1;
7132 I915_WRITE(dpll_reg, dpll);
9d0498a2 7133 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7134 dpll = I915_READ(dpll_reg);
7135 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7136 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7137 }
7138
7139}
7140
f047e395
CW		 7141void intel_mark_busy(struct drm_device *dev)
7142{
f047e395
CW		 7143 i915_update_gfx_val(dev->dev_private);
7144}
7145
7146void intel_mark_idle(struct drm_device *dev)
652c393a 7147{
652c393a 7148 struct drm_crtc *crtc;
652c393a
JB		 7149
7150 if (!i915_powersave)
7151 return;
7152
652c393a 7153 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7154 if (!crtc->fb)
7155 continue;
7156
725a5b54 7157 intel_decrease_pllclock(crtc);
652c393a 7158 }
652c393a
JB		 7159}
7160
c65355bb
CW		 7161void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7162 struct intel_ring_buffer *ring)
652c393a 7163{
f047e395
CW		 7164 struct drm_device *dev = obj->base.dev;
7165 struct drm_crtc *crtc;
652c393a 7166
f047e395 7167 if (!i915_powersave)
acb87dfb
CW		 7168 return;
7169
652c393a
JB		 7170 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7171 if (!crtc->fb)
7172 continue;
7173
c65355bb
CW		 7174 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7175 continue;
7176
7177 intel_increase_pllclock(crtc);
7178 if (ring && intel_fbc_enabled(dev))
7179 ring->fbc_dirty = true;
652c393a
JB		 7180 }
7181}
7182
79e53945
JB		 7183static void intel_crtc_destroy(struct drm_crtc *crtc)
7184{
7185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7186 struct drm_device *dev = crtc->dev;
7187 struct intel_unpin_work *work;
7188 unsigned long flags;
7189
7190 spin_lock_irqsave(&dev->event_lock, flags);
7191 work = intel_crtc->unpin_work;
7192 intel_crtc->unpin_work = NULL;
7193 spin_unlock_irqrestore(&dev->event_lock, flags);
7194
7195 if (work) {
7196 cancel_work_sync(&work->work);
7197 kfree(work);
7198 }
79e53945 7199
40ccc72b
MK		 7200 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7201
79e53945 7202 drm_crtc_cleanup(crtc);
67e77c5a 7203
79e53945
JB		 7204 kfree(intel_crtc);
7205}
7206
6b95a207
KH		 7207static void intel_unpin_work_fn(struct work_struct *__work)
7208{
7209 struct intel_unpin_work *work =
7210 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7211 struct drm_device *dev = work->crtc->dev;
6b95a207 7212
b4a98e57 7213 mutex_lock(&dev->struct_mutex);
1690e1eb 7214 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7215 drm_gem_object_unreference(&work->pending_flip_obj->base);
7216 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7217
b4a98e57
CW		 7218 intel_update_fbc(dev);
7219 mutex_unlock(&dev->struct_mutex);
7220
7221 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7222 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7223
6b95a207
KH		 7224 kfree(work);
7225}
7226
1afe3e9d 7227static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7228 struct drm_crtc *crtc)
6b95a207
KH		 7229{
7230 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7232 struct intel_unpin_work *work;
6b95a207
KH		 7233 unsigned long flags;
7234
7235 /* Ignore early vblank irqs */
7236 if (intel_crtc == NULL)
7237 return;
7238
7239 spin_lock_irqsave(&dev->event_lock, flags);
7240 work = intel_crtc->unpin_work;
e7d841ca
CW		 7241
7242 /* Ensure we don't miss a work->pending update ... */
7243 smp_rmb();
7244
7245 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7246 spin_unlock_irqrestore(&dev->event_lock, flags);
7247 return;
7248 }
7249
e7d841ca
CW		 7250 /* and that the unpin work is consistent wrt ->pending. */
7251 smp_rmb();
7252
6b95a207 7253 intel_crtc->unpin_work = NULL;
6b95a207 7254
45a066eb
RC		 7255 if (work->event)
7256 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7257
0af7e4df
MK		 7258 drm_vblank_put(dev, intel_crtc->pipe);
7259
6b95a207
KH		 7260 spin_unlock_irqrestore(&dev->event_lock, flags);
7261
2c10d571 7262 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7263
7264 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7265
7266 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7267}
7268
1afe3e9d
JB		 7269void intel_finish_page_flip(struct drm_device *dev, int pipe)
7270{
7271 drm_i915_private_t *dev_priv = dev->dev_private;
7272 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7273
49b14a5c 7274 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7275}
7276
7277void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7278{
7279 drm_i915_private_t *dev_priv = dev->dev_private;
7280 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7281
49b14a5c 7282 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7283}
7284
6b95a207
KH		 7285void intel_prepare_page_flip(struct drm_device *dev, int plane)
7286{
7287 drm_i915_private_t *dev_priv = dev->dev_private;
7288 struct intel_crtc *intel_crtc =
7289 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7290 unsigned long flags;
7291
e7d841ca
CW		 7292 /* NB: An MMIO update of the plane base pointer will also
7293 * generate a page-flip completion irq, i.e. every modeset
7294 * is also accompanied by a spurious intel_prepare_page_flip().
7295 */
6b95a207 7296 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7297 if (intel_crtc->unpin_work)
7298 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7299 spin_unlock_irqrestore(&dev->event_lock, flags);
7300}
7301
e7d841ca
CW		 7302inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7303{
7304 /* Ensure that the work item is consistent when activating it ... */
7305 smp_wmb();
7306 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7307 /* and that it is marked active as soon as the irq could fire. */
7308 smp_wmb();
7309}
7310
8c9f3aaf
JB		 7311static int intel_gen2_queue_flip(struct drm_device *dev,
7312 struct drm_crtc *crtc,
7313 struct drm_framebuffer *fb,
7314 struct drm_i915_gem_object *obj)
7315{
7316 struct drm_i915_private *dev_priv = dev->dev_private;
7317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7318 u32 flip_mask;
6d90c952 7319 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7320 int ret;
7321
6d90c952 7322 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7323 if (ret)
83d4092b 7324 goto err;
8c9f3aaf 7325
6d90c952 7326 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7327 if (ret)
83d4092b 7328 goto err_unpin;
8c9f3aaf
JB		 7329
7330 /* Can't queue multiple flips, so wait for the previous
7331 * one to finish before executing the next.
7332 */
7333 if (intel_crtc->plane)
7334 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7335 else
7336 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7337 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7338 intel_ring_emit(ring, MI_NOOP);
7339 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7340 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7341 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7342 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7343 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7344
7345 intel_mark_page_flip_active(intel_crtc);
6d90c952 7346 intel_ring_advance(ring);
83d4092b
CW		 7347 return 0;
7348
7349err_unpin:
7350 intel_unpin_fb_obj(obj);
7351err:
8c9f3aaf
JB		 7352 return ret;
7353}
7354
7355static int intel_gen3_queue_flip(struct drm_device *dev,
7356 struct drm_crtc *crtc,
7357 struct drm_framebuffer *fb,
7358 struct drm_i915_gem_object *obj)
7359{
7360 struct drm_i915_private *dev_priv = dev->dev_private;
7361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7362 u32 flip_mask;
6d90c952 7363 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7364 int ret;
7365
6d90c952 7366 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7367 if (ret)
83d4092b 7368 goto err;
8c9f3aaf 7369
6d90c952 7370 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7371 if (ret)
83d4092b 7372 goto err_unpin;
8c9f3aaf
JB		 7373
7374 if (intel_crtc->plane)
7375 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7376 else
7377 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7378 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7379 intel_ring_emit(ring, MI_NOOP);
7380 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7381 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7382 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7383 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7384 intel_ring_emit(ring, MI_NOOP);
7385
e7d841ca 7386 intel_mark_page_flip_active(intel_crtc);
6d90c952 7387 intel_ring_advance(ring);
83d4092b
CW		 7388 return 0;
7389
7390err_unpin:
7391 intel_unpin_fb_obj(obj);
7392err:
8c9f3aaf
JB		 7393 return ret;
7394}
7395
7396static int intel_gen4_queue_flip(struct drm_device *dev,
7397 struct drm_crtc *crtc,
7398 struct drm_framebuffer *fb,
7399 struct drm_i915_gem_object *obj)
7400{
7401 struct drm_i915_private *dev_priv = dev->dev_private;
7402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7403 uint32_t pf, pipesrc;
6d90c952 7404 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7405 int ret;
7406
6d90c952 7407 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7408 if (ret)
83d4092b 7409 goto err;
8c9f3aaf 7410
6d90c952 7411 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7412 if (ret)
83d4092b 7413 goto err_unpin;
8c9f3aaf
JB		 7414
7415 /* i965+ uses the linear or tiled offsets from the
7416 * Display Registers (which do not change across a page-flip)
7417 * so we need only reprogram the base address.
7418 */
6d90c952
DV		 7419 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7420 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7421 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7422 intel_ring_emit(ring,
7423 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7424 obj->tiling_mode);
8c9f3aaf
JB		 7425
7426 /* XXX Enabling the panel-fitter across page-flip is so far
7427 * untested on non-native modes, so ignore it for now.
7428 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7429 */
7430 pf = 0;
7431 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7432 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7433
7434 intel_mark_page_flip_active(intel_crtc);
6d90c952 7435 intel_ring_advance(ring);
83d4092b
CW		 7436 return 0;
7437
7438err_unpin:
7439 intel_unpin_fb_obj(obj);
7440err:
8c9f3aaf
JB		 7441 return ret;
7442}
7443
7444static int intel_gen6_queue_flip(struct drm_device *dev,
7445 struct drm_crtc *crtc,
7446 struct drm_framebuffer *fb,
7447 struct drm_i915_gem_object *obj)
7448{
7449 struct drm_i915_private *dev_priv = dev->dev_private;
7450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7451 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7452 uint32_t pf, pipesrc;
7453 int ret;
7454
6d90c952 7455 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7456 if (ret)
83d4092b 7457 goto err;
8c9f3aaf 7458
6d90c952 7459 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7460 if (ret)
83d4092b 7461 goto err_unpin;
8c9f3aaf 7462
6d90c952
DV		 7463 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7464 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7465 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7466 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7467
dc257cf1
DV		 7468 /* Contrary to the suggestions in the documentation,
7469 * "Enable Panel Fitter" does not seem to be required when page
7470 * flipping with a non-native mode, and worse causes a normal
7471 * modeset to fail.
7472 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7473 */
7474 pf = 0;
8c9f3aaf 7475 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7476 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7477
7478 intel_mark_page_flip_active(intel_crtc);
6d90c952 7479 intel_ring_advance(ring);
83d4092b
CW		 7480 return 0;
7481
7482err_unpin:
7483 intel_unpin_fb_obj(obj);
7484err:
8c9f3aaf
JB		 7485 return ret;
7486}
7487
7c9017e5
JB		 7488/*
7489 * On gen7 we currently use the blit ring because (in early silicon at least)
7490 * the render ring doesn't give us interrpts for page flip completion, which
7491 * means clients will hang after the first flip is queued. Fortunately the
7492 * blit ring generates interrupts properly, so use it instead.
7493 */
7494static int intel_gen7_queue_flip(struct drm_device *dev,
7495 struct drm_crtc *crtc,
7496 struct drm_framebuffer *fb,
7497 struct drm_i915_gem_object *obj)
7498{
7499 struct drm_i915_private *dev_priv = dev->dev_private;
7500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7501 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7502 uint32_t plane_bit = 0;
7c9017e5
JB		 7503 int ret;
7504
7505 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7506 if (ret)
83d4092b 7507 goto err;
7c9017e5 7508
cb05d8de
DV		 7509 switch(intel_crtc->plane) {
7510 case PLANE_A:
7511 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7512 break;
7513 case PLANE_B:
7514 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7515 break;
7516 case PLANE_C:
7517 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7518 break;
7519 default:
7520 WARN_ONCE(1, "unknown plane in flip command\n");
7521 ret = -ENODEV;
ab3951eb 7522 goto err_unpin;
cb05d8de
DV		 7523 }
7524
7c9017e5
JB		 7525 ret = intel_ring_begin(ring, 4);
7526 if (ret)
83d4092b 7527 goto err_unpin;
7c9017e5 7528
cb05d8de 7529 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7530 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7531 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7532 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7533
7534 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7535 intel_ring_advance(ring);
83d4092b
CW		 7536 return 0;
7537
7538err_unpin:
7539 intel_unpin_fb_obj(obj);
7540err:
7c9017e5
JB		 7541 return ret;
7542}
7543
8c9f3aaf
JB		 7544static int intel_default_queue_flip(struct drm_device *dev,
7545 struct drm_crtc *crtc,
7546 struct drm_framebuffer *fb,
7547 struct drm_i915_gem_object *obj)
7548{
7549 return -ENODEV;
7550}
7551
6b95a207
KH		 7552static int intel_crtc_page_flip(struct drm_crtc *crtc,
7553 struct drm_framebuffer *fb,
7554 struct drm_pending_vblank_event *event)
7555{
7556 struct drm_device *dev = crtc->dev;
7557 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7558 struct drm_framebuffer *old_fb = crtc->fb;
7559 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7561 struct intel_unpin_work *work;
8c9f3aaf 7562 unsigned long flags;
52e68630 7563 int ret;
6b95a207 7564
e6a595d2
VS		 7565 /* Can't change pixel format via MI display flips. */
7566 if (fb->pixel_format != crtc->fb->pixel_format)
7567 return -EINVAL;
7568
7569 /*
7570 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7571 * Note that pitch changes could also affect these register.
7572 */
7573 if (INTEL_INFO(dev)->gen > 3 &&
7574 (fb->offsets[0] != crtc->fb->offsets[0] ||
7575 fb->pitches[0] != crtc->fb->pitches[0]))
7576 return -EINVAL;
7577
6b95a207
KH		 7578 work = kzalloc(sizeof *work, GFP_KERNEL);
7579 if (work == NULL)
7580 return -ENOMEM;
7581
6b95a207 7582 work->event = event;
b4a98e57 7583 work->crtc = crtc;
4a35f83b 7584 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7585 INIT_WORK(&work->work, intel_unpin_work_fn);
7586
7317c75e
JB		 7587 ret = drm_vblank_get(dev, intel_crtc->pipe);
7588 if (ret)
7589 goto free_work;
7590
6b95a207
KH		 7591 /* We borrow the event spin lock for protecting unpin_work */
7592 spin_lock_irqsave(&dev->event_lock, flags);
7593 if (intel_crtc->unpin_work) {
7594 spin_unlock_irqrestore(&dev->event_lock, flags);
7595 kfree(work);
7317c75e 7596 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7597
7598 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7599 return -EBUSY;
7600 }
7601 intel_crtc->unpin_work = work;
7602 spin_unlock_irqrestore(&dev->event_lock, flags);
7603
b4a98e57
CW		 7604 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7605 flush_workqueue(dev_priv->wq);
7606
79158103
CW		 7607 ret = i915_mutex_lock_interruptible(dev);
7608 if (ret)
7609 goto cleanup;
6b95a207 7610
75dfca80 7611 /* Reference the objects for the scheduled work. */
05394f39
CW		 7612 drm_gem_object_reference(&work->old_fb_obj->base);
7613 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7614
7615 crtc->fb = fb;
96b099fd 7616
e1f99ce6 7617 work->pending_flip_obj = obj;
e1f99ce6 7618
4e5359cd
SF		 7619 work->enable_stall_check = true;
7620
b4a98e57 7621 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7622 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7623
8c9f3aaf
JB		 7624 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7625 if (ret)
7626 goto cleanup_pending;
6b95a207 7627
7782de3b 7628 intel_disable_fbc(dev);
c65355bb 7629 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7630 mutex_unlock(&dev->struct_mutex);
7631
e5510fac
JB		 7632 trace_i915_flip_request(intel_crtc->plane, obj);
7633
6b95a207 7634 return 0;
96b099fd 7635
8c9f3aaf 7636cleanup_pending:
b4a98e57 7637 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7638 crtc->fb = old_fb;
05394f39
CW		 7639 drm_gem_object_unreference(&work->old_fb_obj->base);
7640 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7641 mutex_unlock(&dev->struct_mutex);
7642
79158103 7643cleanup:
96b099fd
CW		 7644 spin_lock_irqsave(&dev->event_lock, flags);
7645 intel_crtc->unpin_work = NULL;
7646 spin_unlock_irqrestore(&dev->event_lock, flags);
7647
7317c75e
JB		 7648 drm_vblank_put(dev, intel_crtc->pipe);
7649free_work:
96b099fd
CW		 7650 kfree(work);
7651
7652 return ret;
6b95a207
KH		 7653}
7654
f6e5b160 7655static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7656 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7657 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7658};
7659
50f56119
DV		 7660static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7661 struct drm_crtc *crtc)
7662{
7663 struct drm_device *dev;
7664 struct drm_crtc *tmp;
7665 int crtc_mask = 1;
47f1c6c9 7666
50f56119 7667 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7668
50f56119 7669 dev = crtc->dev;
47f1c6c9 7670
50f56119
DV		 7671 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7672 if (tmp == crtc)
7673 break;
7674 crtc_mask <<= 1;
7675 }
47f1c6c9 7676
50f56119
DV		 7677 if (encoder->possible_crtcs & crtc_mask)
7678 return true;
7679 return false;
47f1c6c9 7680}
79e53945 7681
9a935856
DV		 7682/**
7683 * intel_modeset_update_staged_output_state
7684 *
7685 * Updates the staged output configuration state, e.g. after we've read out the
7686 * current hw state.
7687 */
7688static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7689{
9a935856
DV		 7690 struct intel_encoder *encoder;
7691 struct intel_connector *connector;
f6e5b160 7692
9a935856
DV		 7693 list_for_each_entry(connector, &dev->mode_config.connector_list,
7694 base.head) {
7695 connector->new_encoder =
7696 to_intel_encoder(connector->base.encoder);
7697 }
f6e5b160 7698
9a935856
DV		 7699 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7700 base.head) {
7701 encoder->new_crtc =
7702 to_intel_crtc(encoder->base.crtc);
7703 }
f6e5b160
CW		 7704}
7705
9a935856
DV		 7706/**
7707 * intel_modeset_commit_output_state
7708 *
7709 * This function copies the stage display pipe configuration to the real one.
7710 */
7711static void intel_modeset_commit_output_state(struct drm_device *dev)
7712{
7713 struct intel_encoder *encoder;
7714 struct intel_connector *connector;
f6e5b160 7715
9a935856
DV		 7716 list_for_each_entry(connector, &dev->mode_config.connector_list,
7717 base.head) {
7718 connector->base.encoder = &connector->new_encoder->base;
7719 }
f6e5b160 7720
9a935856
DV		 7721 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7722 base.head) {
7723 encoder->base.crtc = &encoder->new_crtc->base;
7724 }
7725}
7726
050f7aeb
DV		 7727static void
7728connected_sink_compute_bpp(struct intel_connector * connector,
7729 struct intel_crtc_config *pipe_config)
7730{
7731 int bpp = pipe_config->pipe_bpp;
7732
7733 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7734 connector->base.base.id,
7735 drm_get_connector_name(&connector->base));
7736
7737 /* Don't use an invalid EDID bpc value */
7738 if (connector->base.display_info.bpc &&
7739 connector->base.display_info.bpc * 3 < bpp) {
7740 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7741 bpp, connector->base.display_info.bpc*3);
7742 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7743 }
7744
7745 /* Clamp bpp to 8 on screens without EDID 1.4 */
7746 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7747 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7748 bpp);
7749 pipe_config->pipe_bpp = 24;
7750 }
7751}
7752
4e53c2e0 7753static int
050f7aeb
DV		 7754compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7755 struct drm_framebuffer *fb,
7756 struct intel_crtc_config *pipe_config)
4e53c2e0 7757{
050f7aeb
DV		 7758 struct drm_device *dev = crtc->base.dev;
7759 struct intel_connector *connector;
4e53c2e0
DV		 7760 int bpp;
7761
d42264b1
DV		 7762 switch (fb->pixel_format) {
7763 case DRM_FORMAT_C8:
4e53c2e0
DV		 7764 bpp = 8*3; /* since we go through a colormap */
7765 break;
d42264b1
DV		 7766 case DRM_FORMAT_XRGB1555:
7767 case DRM_FORMAT_ARGB1555:
7768 /* checked in intel_framebuffer_init already */
7769 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7770 return -EINVAL;
7771 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7772 bpp = 6*3; /* min is 18bpp */
7773 break;
d42264b1
DV		 7774 case DRM_FORMAT_XBGR8888:
7775 case DRM_FORMAT_ABGR8888:
7776 /* checked in intel_framebuffer_init already */
7777 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7778 return -EINVAL;
7779 case DRM_FORMAT_XRGB8888:
7780 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7781 bpp = 8*3;
7782 break;
d42264b1
DV		 7783 case DRM_FORMAT_XRGB2101010:
7784 case DRM_FORMAT_ARGB2101010:
7785 case DRM_FORMAT_XBGR2101010:
7786 case DRM_FORMAT_ABGR2101010:
7787 /* checked in intel_framebuffer_init already */
7788 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7789 return -EINVAL;
4e53c2e0
DV		 7790 bpp = 10*3;
7791 break;
baba133a 7792 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7793 default:
7794 DRM_DEBUG_KMS("unsupported depth\n");
7795 return -EINVAL;
7796 }
7797
4e53c2e0
DV		 7798 pipe_config->pipe_bpp = bpp;
7799
7800 /* Clamp display bpp to EDID value */
7801 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7802 base.head) {
1b829e05
DV		 7803 if (!connector->new_encoder ||
7804 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7805 continue;
7806
050f7aeb 7807 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7808 }
7809
7810 return bpp;
7811}
7812
c0b03411
DV		 7813static void intel_dump_pipe_config(struct intel_crtc *crtc,
7814 struct intel_crtc_config *pipe_config,
7815 const char *context)
7816{
7817 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7818 context, pipe_name(crtc->pipe));
7819
7820 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7821 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7822 pipe_config->pipe_bpp, pipe_config->dither);
7823 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7824 pipe_config->has_pch_encoder,
7825 pipe_config->fdi_lanes,
7826 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7827 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7828 pipe_config->fdi_m_n.tu);
7829 DRM_DEBUG_KMS("requested mode:\n");
7830 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7831 DRM_DEBUG_KMS("adjusted mode:\n");
7832 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7833 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7834 pipe_config->gmch_pfit.control,
7835 pipe_config->gmch_pfit.pgm_ratios,
7836 pipe_config->gmch_pfit.lvds_border_bits);
7837 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7838 pipe_config->pch_pfit.pos,
7839 pipe_config->pch_pfit.size);
42db64ef 7840 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7841}
7842
accfc0c5
DV		 7843static bool check_encoder_cloning(struct drm_crtc *crtc)
7844{
7845 int num_encoders = 0;
7846 bool uncloneable_encoders = false;
7847 struct intel_encoder *encoder;
7848
7849 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7850 base.head) {
7851 if (&encoder->new_crtc->base != crtc)
7852 continue;
7853
7854 num_encoders++;
7855 if (!encoder->cloneable)
7856 uncloneable_encoders = true;
7857 }
7858
7859 return !(num_encoders > 1 && uncloneable_encoders);
7860}
7861
b8cecdf5
DV		 7862static struct intel_crtc_config *
7863intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7864 struct drm_framebuffer *fb,
b8cecdf5 7865 struct drm_display_mode *mode)
ee7b9f93 7866{
7758a113 7867 struct drm_device *dev = crtc->dev;
7758a113
DV		 7868 struct drm_encoder_helper_funcs *encoder_funcs;
7869 struct intel_encoder *encoder;
b8cecdf5 7870 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7871 int plane_bpp, ret = -EINVAL;
7872 bool retry = true;
ee7b9f93 7873
accfc0c5
DV		 7874 if (!check_encoder_cloning(crtc)) {
7875 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7876 return ERR_PTR(-EINVAL);
7877 }
7878
b8cecdf5
DV		 7879 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7880 if (!pipe_config)
7758a113
DV		 7881 return ERR_PTR(-ENOMEM);
7882
b8cecdf5
DV		 7883 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7884 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 7885 pipe_config->cpu_transcoder =
7886 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 7887 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7888
050f7aeb
DV		 7889 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7890 * plane pixel format and any sink constraints into account. Returns the
7891 * source plane bpp so that dithering can be selected on mismatches
7892 * after encoders and crtc also have had their say. */
7893 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7894 fb, pipe_config);
4e53c2e0
DV		 7895 if (plane_bpp < 0)
7896 goto fail;
7897
e29c22c0 7898encoder_retry:
ef1b460d 7899 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7900 pipe_config->port_clock = 0;
ef1b460d 7901 pipe_config->pixel_multiplier = 1;
ff9a6750 7902
7758a113
DV		 7903 /* Pass our mode to the connectors and the CRTC to give them a chance to
7904 * adjust it according to limitations or connector properties, and also
7905 * a chance to reject the mode entirely.
47f1c6c9 7906 */
7758a113
DV		 7907 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7908 base.head) {
47f1c6c9 7909
7758a113
DV		 7910 if (&encoder->new_crtc->base != crtc)
7911 continue;
7ae89233
DV		 7912
7913 if (encoder->compute_config) {
7914 if (!(encoder->compute_config(encoder, pipe_config))) {
7915 DRM_DEBUG_KMS("Encoder config failure\n");
7916 goto fail;
7917 }
7918
7919 continue;
7920 }
7921
7758a113 7922 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7923 if (!(encoder_funcs->mode_fixup(&encoder->base,
7924 &pipe_config->requested_mode,
7925 &pipe_config->adjusted_mode))) {
7758a113
DV		 7926 DRM_DEBUG_KMS("Encoder fixup failed\n");
7927 goto fail;
7928 }
ee7b9f93 7929 }
47f1c6c9 7930
ff9a6750
DV		 7931 /* Set default port clock if not overwritten by the encoder. Needs to be
7932 * done afterwards in case the encoder adjusts the mode. */
7933 if (!pipe_config->port_clock)
7934 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7935
a43f6e0f 7936 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7937 if (ret < 0) {
7758a113
DV		 7938 DRM_DEBUG_KMS("CRTC fixup failed\n");
7939 goto fail;
ee7b9f93 7940 }
e29c22c0
DV		 7941
7942 if (ret == RETRY) {
7943 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7944 ret = -EINVAL;
7945 goto fail;
7946 }
7947
7948 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7949 retry = false;
7950 goto encoder_retry;
7951 }
7952
4e53c2e0
DV		 7953 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7954 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7955 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7956
b8cecdf5 7957 return pipe_config;
7758a113 7958fail:
b8cecdf5 7959 kfree(pipe_config);
e29c22c0 7960 return ERR_PTR(ret);
ee7b9f93 7961}
47f1c6c9 7962
e2e1ed41
DV		 7963/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7964 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7965static void
7966intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7967 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7968{
7969 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7970 struct drm_device *dev = crtc->dev;
7971 struct intel_encoder *encoder;
7972 struct intel_connector *connector;
7973 struct drm_crtc *tmp_crtc;
79e53945 7974
e2e1ed41 7975 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7976
e2e1ed41
DV		 7977 /* Check which crtcs have changed outputs connected to them, these need
7978 * to be part of the prepare_pipes mask. We don't (yet) support global
7979 * modeset across multiple crtcs, so modeset_pipes will only have one
7980 * bit set at most. */
7981 list_for_each_entry(connector, &dev->mode_config.connector_list,
7982 base.head) {
7983 if (connector->base.encoder == &connector->new_encoder->base)
7984 continue;
79e53945 7985
e2e1ed41
DV		 7986 if (connector->base.encoder) {
7987 tmp_crtc = connector->base.encoder->crtc;
7988
7989 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7990 }
7991
7992 if (connector->new_encoder)
7993 *prepare_pipes |=
7994 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7995 }
7996
e2e1ed41
DV		 7997 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7998 base.head) {
7999 if (encoder->base.crtc == &encoder->new_crtc->base)
8000 continue;
8001
8002 if (encoder->base.crtc) {
8003 tmp_crtc = encoder->base.crtc;
8004
8005 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8006 }
8007
8008 if (encoder->new_crtc)
8009 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8010 }
8011
e2e1ed41
DV		 8012 /* Check for any pipes that will be fully disabled ... */
8013 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8014 base.head) {
8015 bool used = false;
22fd0fab 8016
e2e1ed41
DV		 8017 /* Don't try to disable disabled crtcs. */
8018 if (!intel_crtc->base.enabled)
8019 continue;
7e7d76c3 8020
e2e1ed41
DV		 8021 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8022 base.head) {
8023 if (encoder->new_crtc == intel_crtc)
8024 used = true;
8025 }
8026
8027 if (!used)
8028 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8029 }
8030
e2e1ed41
DV		 8031
8032 /* set_mode is also used to update properties on life display pipes. */
8033 intel_crtc = to_intel_crtc(crtc);
8034 if (crtc->enabled)
8035 *prepare_pipes |= 1 << intel_crtc->pipe;
8036
b6c5164d
DV		 8037 /*
8038 * For simplicity do a full modeset on any pipe where the output routing
8039 * changed. We could be more clever, but that would require us to be
8040 * more careful with calling the relevant encoder->mode_set functions.
8041 */
e2e1ed41
DV		 8042 if (*prepare_pipes)
8043 *modeset_pipes = *prepare_pipes;
8044
8045 /* ... and mask these out. */
8046 *modeset_pipes &= ~(*disable_pipes);
8047 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8048
8049 /*
8050 * HACK: We don't (yet) fully support global modesets. intel_set_config
8051 * obies this rule, but the modeset restore mode of
8052 * intel_modeset_setup_hw_state does not.
8053 */
8054 *modeset_pipes &= 1 << intel_crtc->pipe;
8055 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8056
8057 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8058 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8059}
79e53945 8060
ea9d758d 8061static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8062{
ea9d758d 8063 struct drm_encoder *encoder;
f6e5b160 8064 struct drm_device *dev = crtc->dev;
f6e5b160 8065
ea9d758d
DV		 8066 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8067 if (encoder->crtc == crtc)
8068 return true;
8069
8070 return false;
8071}
8072
8073static void
8074intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8075{
8076 struct intel_encoder *intel_encoder;
8077 struct intel_crtc *intel_crtc;
8078 struct drm_connector *connector;
8079
8080 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8081 base.head) {
8082 if (!intel_encoder->base.crtc)
8083 continue;
8084
8085 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8086
8087 if (prepare_pipes & (1 << intel_crtc->pipe))
8088 intel_encoder->connectors_active = false;
8089 }
8090
8091 intel_modeset_commit_output_state(dev);
8092
8093 /* Update computed state. */
8094 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8095 base.head) {
8096 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8097 }
8098
8099 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8100 if (!connector->encoder || !connector->encoder->crtc)
8101 continue;
8102
8103 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8104
8105 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8106 struct drm_property *dpms_property =
8107 dev->mode_config.dpms_property;
8108
ea9d758d 8109 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8110 drm_object_property_set_value(&connector->base,
68d34720
DV		 8111 dpms_property,
8112 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8113
8114 intel_encoder = to_intel_encoder(connector->encoder);
8115 intel_encoder->connectors_active = true;
8116 }
8117 }
8118
8119}
8120
f1f644dc
JB		 8121static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8122 struct intel_crtc_config *new)
8123{
8124 int clock1, clock2, diff;
8125
8126 clock1 = cur->adjusted_mode.clock;
8127 clock2 = new->adjusted_mode.clock;
8128
8129 if (clock1 == clock2)
8130 return true;
8131
8132 if (!clock1 || !clock2)
8133 return false;
8134
8135 diff = abs(clock1 - clock2);
8136
8137 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8138 return true;
8139
8140 return false;
8141}
8142
25c5b266
DV		 8143#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8144 list_for_each_entry((intel_crtc), \
8145 &(dev)->mode_config.crtc_list, \
8146 base.head) \
0973f18f 8147 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8148
0e8ffe1b 8149static bool
2fa2fe9a
DV		 8150intel_pipe_config_compare(struct drm_device *dev,
8151 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8152 struct intel_crtc_config *pipe_config)
8153{
66e985c0
DV		 8154#define PIPE_CONF_CHECK_X(name) \
8155 if (current_config->name != pipe_config->name) { \
8156 DRM_ERROR("mismatch in " #name " " \
8157 "(expected 0x%08x, found 0x%08x)\n", \
8158 current_config->name, \
8159 pipe_config->name); \
8160 return false; \
8161 }
8162
08a24034
DV		 8163#define PIPE_CONF_CHECK_I(name) \
8164 if (current_config->name != pipe_config->name) { \
8165 DRM_ERROR("mismatch in " #name " " \
8166 "(expected %i, found %i)\n", \
8167 current_config->name, \
8168 pipe_config->name); \
8169 return false; \
88adfff1
DV		 8170 }
8171
1bd1bd80
DV		 8172#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8173 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8174 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8175 "(expected %i, found %i)\n", \
8176 current_config->name & (mask), \
8177 pipe_config->name & (mask)); \
8178 return false; \
8179 }
8180
bb760063
DV		 8181#define PIPE_CONF_QUIRK(quirk) \
8182 ((current_config->quirks | pipe_config->quirks) & (quirk))
8183
eccb140b
DV		 8184 PIPE_CONF_CHECK_I(cpu_transcoder);
8185
08a24034
DV		 8186 PIPE_CONF_CHECK_I(has_pch_encoder);
8187 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8188 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8189 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8190 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8191 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8192 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8193
1bd1bd80
DV		 8194 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8195 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8196 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8197 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8198 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8199 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8200
8201 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8202 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8203 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8204 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8205 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8206 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8207
c93f54cf 8208 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8209
1bd1bd80
DV		 8210 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8211 DRM_MODE_FLAG_INTERLACE);
8212
bb760063
DV		 8213 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8214 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8215 DRM_MODE_FLAG_PHSYNC);
8216 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8217 DRM_MODE_FLAG_NHSYNC);
8218 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8219 DRM_MODE_FLAG_PVSYNC);
8220 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8221 DRM_MODE_FLAG_NVSYNC);
8222 }
045ac3b5 8223
1bd1bd80
DV		 8224 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8225 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8226
2fa2fe9a
DV		 8227 PIPE_CONF_CHECK_I(gmch_pfit.control);
8228 /* pfit ratios are autocomputed by the hw on gen4+ */
8229 if (INTEL_INFO(dev)->gen < 4)
8230 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8231 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8232 PIPE_CONF_CHECK_I(pch_pfit.pos);
8233 PIPE_CONF_CHECK_I(pch_pfit.size);
8234
42db64ef
PZ		 8235 PIPE_CONF_CHECK_I(ips_enabled);
8236
c0d43d62 8237 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8238 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8239 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8240 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8241 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8242
66e985c0 8243#undef PIPE_CONF_CHECK_X
08a24034 8244#undef PIPE_CONF_CHECK_I
1bd1bd80 8245#undef PIPE_CONF_CHECK_FLAGS
bb760063 8246#undef PIPE_CONF_QUIRK
88adfff1 8247
f1f644dc
JB		 8248 if (!IS_HASWELL(dev)) {
8249 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8250 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8251 current_config->adjusted_mode.clock,
8252 pipe_config->adjusted_mode.clock);
8253 return false;
8254 }
8255 }
8256
0e8ffe1b
DV		 8257 return true;
8258}
8259
91d1b4bd
DV		 8260static void
8261check_connector_state(struct drm_device *dev)
8af6cf88 8262{
8af6cf88
DV		 8263 struct intel_connector *connector;
8264
8265 list_for_each_entry(connector, &dev->mode_config.connector_list,
8266 base.head) {
8267 /* This also checks the encoder/connector hw state with the
8268 * ->get_hw_state callbacks. */
8269 intel_connector_check_state(connector);
8270
8271 WARN(&connector->new_encoder->base != connector->base.encoder,
8272 "connector's staged encoder doesn't match current encoder\n");
8273 }
91d1b4bd
DV		 8274}
8275
8276static void
8277check_encoder_state(struct drm_device *dev)
8278{
8279 struct intel_encoder *encoder;
8280 struct intel_connector *connector;
8af6cf88
DV		 8281
8282 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8283 base.head) {
8284 bool enabled = false;
8285 bool active = false;
8286 enum pipe pipe, tracked_pipe;
8287
8288 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8289 encoder->base.base.id,
8290 drm_get_encoder_name(&encoder->base));
8291
8292 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8293 "encoder's stage crtc doesn't match current crtc\n");
8294 WARN(encoder->connectors_active && !encoder->base.crtc,
8295 "encoder's active_connectors set, but no crtc\n");
8296
8297 list_for_each_entry(connector, &dev->mode_config.connector_list,
8298 base.head) {
8299 if (connector->base.encoder != &encoder->base)
8300 continue;
8301 enabled = true;
8302 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8303 active = true;
8304 }
8305 WARN(!!encoder->base.crtc != enabled,
8306 "encoder's enabled state mismatch "
8307 "(expected %i, found %i)\n",
8308 !!encoder->base.crtc, enabled);
8309 WARN(active && !encoder->base.crtc,
8310 "active encoder with no crtc\n");
8311
8312 WARN(encoder->connectors_active != active,
8313 "encoder's computed active state doesn't match tracked active state "
8314 "(expected %i, found %i)\n", active, encoder->connectors_active);
8315
8316 active = encoder->get_hw_state(encoder, &pipe);
8317 WARN(active != encoder->connectors_active,
8318 "encoder's hw state doesn't match sw tracking "
8319 "(expected %i, found %i)\n",
8320 encoder->connectors_active, active);
8321
8322 if (!encoder->base.crtc)
8323 continue;
8324
8325 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8326 WARN(active && pipe != tracked_pipe,
8327 "active encoder's pipe doesn't match"
8328 "(expected %i, found %i)\n",
8329 tracked_pipe, pipe);
8330
8331 }
91d1b4bd
DV		 8332}
8333
8334static void
8335check_crtc_state(struct drm_device *dev)
8336{
8337 drm_i915_private_t *dev_priv = dev->dev_private;
8338 struct intel_crtc *crtc;
8339 struct intel_encoder *encoder;
8340 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8341
8342 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8343 base.head) {
8344 bool enabled = false;
8345 bool active = false;
8346
045ac3b5
JB		 8347 memset(&pipe_config, 0, sizeof(pipe_config));
8348
8af6cf88
DV		 8349 DRM_DEBUG_KMS("[CRTC:%d]\n",
8350 crtc->base.base.id);
8351
8352 WARN(crtc->active && !crtc->base.enabled,
8353 "active crtc, but not enabled in sw tracking\n");
8354
8355 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8356 base.head) {
8357 if (encoder->base.crtc != &crtc->base)
8358 continue;
8359 enabled = true;
8360 if (encoder->connectors_active)
8361 active = true;
8362 }
6c49f241 8363
8af6cf88
DV		 8364 WARN(active != crtc->active,
8365 "crtc's computed active state doesn't match tracked active state "
8366 "(expected %i, found %i)\n", active, crtc->active);
8367 WARN(enabled != crtc->base.enabled,
8368 "crtc's computed enabled state doesn't match tracked enabled state "
8369 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8370
0e8ffe1b
DV		 8371 active = dev_priv->display.get_pipe_config(crtc,
8372 &pipe_config);
d62cf62a
DV		 8373
8374 /* hw state is inconsistent with the pipe A quirk */
8375 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8376 active = crtc->active;
8377
6c49f241
DV		 8378 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8379 base.head) {
8380 if (encoder->base.crtc != &crtc->base)
8381 continue;
510d5f2f 8382 if (encoder->get_config)
6c49f241
DV		 8383 encoder->get_config(encoder, &pipe_config);
8384 }
8385
510d5f2f
JB		 8386 if (dev_priv->display.get_clock)
8387 dev_priv->display.get_clock(crtc, &pipe_config);
8388
0e8ffe1b
DV		 8389 WARN(crtc->active != active,
8390 "crtc active state doesn't match with hw state "
8391 "(expected %i, found %i)\n", crtc->active, active);
8392
c0b03411
DV		 8393 if (active &&
8394 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8395 WARN(1, "pipe state doesn't match!\n");
8396 intel_dump_pipe_config(crtc, &pipe_config,
8397 "[hw state]");
8398 intel_dump_pipe_config(crtc, &crtc->config,
8399 "[sw state]");
8400 }
8af6cf88
DV		 8401 }
8402}
8403
91d1b4bd
DV		 8404static void
8405check_shared_dpll_state(struct drm_device *dev)
8406{
8407 drm_i915_private_t *dev_priv = dev->dev_private;
8408 struct intel_crtc *crtc;
8409 struct intel_dpll_hw_state dpll_hw_state;
8410 int i;
5358901f
DV		 8411
8412 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8413 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8414 int enabled_crtcs = 0, active_crtcs = 0;
8415 bool active;
8416
8417 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8418
8419 DRM_DEBUG_KMS("%s\n", pll->name);
8420
8421 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8422
8423 WARN(pll->active > pll->refcount,
8424 "more active pll users than references: %i vs %i\n",
8425 pll->active, pll->refcount);
8426 WARN(pll->active && !pll->on,
8427 "pll in active use but not on in sw tracking\n");
8428 WARN(pll->on != active,
8429 "pll on state mismatch (expected %i, found %i)\n",
8430 pll->on, active);
8431
8432 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8433 base.head) {
8434 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8435 enabled_crtcs++;
8436 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8437 active_crtcs++;
8438 }
8439 WARN(pll->active != active_crtcs,
8440 "pll active crtcs mismatch (expected %i, found %i)\n",
8441 pll->active, active_crtcs);
8442 WARN(pll->refcount != enabled_crtcs,
8443 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8444 pll->refcount, enabled_crtcs);
66e985c0
DV		 8445
8446 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8447 sizeof(dpll_hw_state)),
8448 "pll hw state mismatch\n");
5358901f 8449 }
8af6cf88
DV		 8450}
8451
91d1b4bd
DV		 8452void
8453intel_modeset_check_state(struct drm_device *dev)
8454{
8455 check_connector_state(dev);
8456 check_encoder_state(dev);
8457 check_crtc_state(dev);
8458 check_shared_dpll_state(dev);
8459}
8460
f30da187
DV		 8461static int __intel_set_mode(struct drm_crtc *crtc,
8462 struct drm_display_mode *mode,
8463 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8464{
8465 struct drm_device *dev = crtc->dev;
dbf2b54e 8466 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8467 struct drm_display_mode *saved_mode, *saved_hwmode;
8468 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8469 struct intel_crtc *intel_crtc;
8470 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8471 int ret = 0;
a6778b3c 8472
3ac18232 8473 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8474 if (!saved_mode)
8475 return -ENOMEM;
3ac18232 8476 saved_hwmode = saved_mode + 1;
a6778b3c 8477
e2e1ed41 8478 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8479 &prepare_pipes, &disable_pipes);
8480
3ac18232
TG		 8481 *saved_hwmode = crtc->hwmode;
8482 *saved_mode = crtc->mode;
a6778b3c 8483
25c5b266
DV		 8484 /* Hack: Because we don't (yet) support global modeset on multiple
8485 * crtcs, we don't keep track of the new mode for more than one crtc.
8486 * Hence simply check whether any bit is set in modeset_pipes in all the
8487 * pieces of code that are not yet converted to deal with mutliple crtcs
8488 * changing their mode at the same time. */
25c5b266 8489 if (modeset_pipes) {
4e53c2e0 8490 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8491 if (IS_ERR(pipe_config)) {
8492 ret = PTR_ERR(pipe_config);
8493 pipe_config = NULL;
8494
3ac18232 8495 goto out;
25c5b266 8496 }
c0b03411
DV		 8497 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8498 "[modeset]");
25c5b266 8499 }
a6778b3c 8500
460da916
DV		 8501 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8502 intel_crtc_disable(&intel_crtc->base);
8503
ea9d758d
DV		 8504 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8505 if (intel_crtc->base.enabled)
8506 dev_priv->display.crtc_disable(&intel_crtc->base);
8507 }
a6778b3c 8508
6c4c86f5
DV		 8509 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8510 * to set it here already despite that we pass it down the callchain.
f6e5b160 8511 */
b8cecdf5 8512 if (modeset_pipes) {
25c5b266 8513 crtc->mode = *mode;
b8cecdf5
DV		 8514 /* mode_set/enable/disable functions rely on a correct pipe
8515 * config. */
8516 to_intel_crtc(crtc)->config = *pipe_config;
8517 }
7758a113 8518
ea9d758d
DV		 8519 /* Only after disabling all output pipelines that will be changed can we
8520 * update the the output configuration. */
8521 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8522
47fab737
DV		 8523 if (dev_priv->display.modeset_global_resources)
8524 dev_priv->display.modeset_global_resources(dev);
8525
a6778b3c
DV		 8526 /* Set up the DPLL and any encoders state that needs to adjust or depend
8527 * on the DPLL.
f6e5b160 8528 */
25c5b266 8529 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8530 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8531 x, y, fb);
8532 if (ret)
8533 goto done;
a6778b3c
DV		 8534 }
8535
8536 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8537 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8538 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8539
25c5b266
DV		 8540 if (modeset_pipes) {
8541 /* Store real post-adjustment hardware mode. */
b8cecdf5 8542 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8543
25c5b266
DV		 8544 /* Calculate and store various constants which
8545 * are later needed by vblank and swap-completion
8546 * timestamping. They are derived from true hwmode.
8547 */
8548 drm_calc_timestamping_constants(crtc);
8549 }
a6778b3c
DV		 8550
8551 /* FIXME: add subpixel order */
8552done:
c0c36b94 8553 if (ret && crtc->enabled) {
3ac18232
TG		 8554 crtc->hwmode = *saved_hwmode;
8555 crtc->mode = *saved_mode;
a6778b3c
DV		 8556 }
8557
3ac18232 8558out:
b8cecdf5 8559 kfree(pipe_config);
3ac18232 8560 kfree(saved_mode);
a6778b3c 8561 return ret;
f6e5b160
CW		 8562}
8563
f30da187
DV		 8564int intel_set_mode(struct drm_crtc *crtc,
8565 struct drm_display_mode *mode,
8566 int x, int y, struct drm_framebuffer *fb)
8567{
8568 int ret;
8569
8570 ret = __intel_set_mode(crtc, mode, x, y, fb);
8571
8572 if (ret == 0)
8573 intel_modeset_check_state(crtc->dev);
8574
8575 return ret;
8576}
8577
c0c36b94
CW		 8578void intel_crtc_restore_mode(struct drm_crtc *crtc)
8579{
8580 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8581}
8582
25c5b266
DV		 8583#undef for_each_intel_crtc_masked
8584
d9e55608
DV		 8585static void intel_set_config_free(struct intel_set_config *config)
8586{
8587 if (!config)
8588 return;
8589
1aa4b628
DV		 8590 kfree(config->save_connector_encoders);
8591 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8592 kfree(config);
8593}
8594
85f9eb71
DV		 8595static int intel_set_config_save_state(struct drm_device *dev,
8596 struct intel_set_config *config)
8597{
85f9eb71
DV		 8598 struct drm_encoder *encoder;
8599 struct drm_connector *connector;
8600 int count;
8601
1aa4b628
DV		 8602 config->save_encoder_crtcs =
8603 kcalloc(dev->mode_config.num_encoder,
8604 sizeof(struct drm_crtc *), GFP_KERNEL);
8605 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8606 return -ENOMEM;
8607
1aa4b628
DV		 8608 config->save_connector_encoders =
8609 kcalloc(dev->mode_config.num_connector,
8610 sizeof(struct drm_encoder *), GFP_KERNEL);
8611 if (!config->save_connector_encoders)
85f9eb71
DV		 8612 return -ENOMEM;
8613
8614 /* Copy data. Note that driver private data is not affected.
8615 * Should anything bad happen only the expected state is
8616 * restored, not the drivers personal bookkeeping.
8617 */
85f9eb71
DV		 8618 count = 0;
8619 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8620 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8621 }
8622
8623 count = 0;
8624 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8625 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8626 }
8627
8628 return 0;
8629}
8630
8631static void intel_set_config_restore_state(struct drm_device *dev,
8632 struct intel_set_config *config)
8633{
9a935856
DV		 8634 struct intel_encoder *encoder;
8635 struct intel_connector *connector;
85f9eb71
DV		 8636 int count;
8637
85f9eb71 8638 count = 0;
9a935856
DV		 8639 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8640 encoder->new_crtc =
8641 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8642 }
8643
8644 count = 0;
9a935856
DV		 8645 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8646 connector->new_encoder =
8647 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8648 }
8649}
8650
e3de42b6
ID		 8651static bool
8652is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8653 int num_connectors)
8654{
8655 int i;
8656
8657 for (i = 0; i < num_connectors; i++)
8658 if (connectors[i].encoder &&
8659 connectors[i].encoder->crtc == crtc &&
8660 connectors[i].dpms != DRM_MODE_DPMS_ON)
8661 return true;
8662
8663 return false;
8664}
8665
5e2b584e
DV		 8666static void
8667intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8668 struct intel_set_config *config)
8669{
8670
8671 /* We should be able to check here if the fb has the same properties
8672 * and then just flip_or_move it */
e3de42b6
ID		 8673 if (set->connectors != NULL &&
8674 is_crtc_connector_off(set->crtc, *set->connectors,
8675 set->num_connectors)) {
8676 config->mode_changed = true;
8677 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8678 /* If we have no fb then treat it as a full mode set */
8679 if (set->crtc->fb == NULL) {
319d9827
JB		 8680 struct intel_crtc *intel_crtc =
8681 to_intel_crtc(set->crtc);
8682
8683 if (intel_crtc->active && i915_fastboot) {
8684 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8685 config->fb_changed = true;
8686 } else {
8687 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8688 config->mode_changed = true;
8689 }
5e2b584e
DV		 8690 } else if (set->fb == NULL) {
8691 config->mode_changed = true;
72f4901e
DV		 8692 } else if (set->fb->pixel_format !=
8693 set->crtc->fb->pixel_format) {
5e2b584e 8694 config->mode_changed = true;
e3de42b6 8695 } else {
5e2b584e 8696 config->fb_changed = true;
e3de42b6 8697 }
5e2b584e
DV		 8698 }
8699
835c5873 8700 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8701 config->fb_changed = true;
8702
8703 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8704 DRM_DEBUG_KMS("modes are different, full mode set\n");
8705 drm_mode_debug_printmodeline(&set->crtc->mode);
8706 drm_mode_debug_printmodeline(set->mode);
8707 config->mode_changed = true;
8708 }
8709}
8710
2e431051 8711static int
9a935856
DV		 8712intel_modeset_stage_output_state(struct drm_device *dev,
8713 struct drm_mode_set *set,
8714 struct intel_set_config *config)
50f56119 8715{
85f9eb71 8716 struct drm_crtc *new_crtc;
9a935856
DV		 8717 struct intel_connector *connector;
8718 struct intel_encoder *encoder;
2e431051 8719 int count, ro;
50f56119 8720
9abdda74 8721 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8722 * of connectors. For paranoia, double-check this. */
8723 WARN_ON(!set->fb && (set->num_connectors != 0));
8724 WARN_ON(set->fb && (set->num_connectors == 0));
8725
50f56119 8726 count = 0;
9a935856
DV		 8727 list_for_each_entry(connector, &dev->mode_config.connector_list,
8728 base.head) {
8729 /* Otherwise traverse passed in connector list and get encoders
8730 * for them. */
50f56119 8731 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8732 if (set->connectors[ro] == &connector->base) {
8733 connector->new_encoder = connector->encoder;
50f56119
DV		 8734 break;
8735 }
8736 }
8737
9a935856
DV		 8738 /* If we disable the crtc, disable all its connectors. Also, if
8739 * the connector is on the changing crtc but not on the new
8740 * connector list, disable it. */
8741 if ((!set->fb || ro == set->num_connectors) &&
8742 connector->base.encoder &&
8743 connector->base.encoder->crtc == set->crtc) {
8744 connector->new_encoder = NULL;
8745
8746 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8747 connector->base.base.id,
8748 drm_get_connector_name(&connector->base));
8749 }
8750
8751
8752 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8753 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8754 config->mode_changed = true;
50f56119
DV		 8755 }
8756 }
9a935856 8757 /* connector->new_encoder is now updated for all connectors. */
50f56119 8758
9a935856 8759 /* Update crtc of enabled connectors. */
50f56119 8760 count = 0;
9a935856
DV		 8761 list_for_each_entry(connector, &dev->mode_config.connector_list,
8762 base.head) {
8763 if (!connector->new_encoder)
50f56119
DV		 8764 continue;
8765
9a935856 8766 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8767
8768 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8769 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8770 new_crtc = set->crtc;
8771 }
8772
8773 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8774 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8775 new_crtc)) {
5e2b584e 8776 return -EINVAL;
50f56119 8777 }
9a935856
DV		 8778 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8779
8780 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8781 connector->base.base.id,
8782 drm_get_connector_name(&connector->base),
8783 new_crtc->base.id);
8784 }
8785
8786 /* Check for any encoders that needs to be disabled. */
8787 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8788 base.head) {
8789 list_for_each_entry(connector,
8790 &dev->mode_config.connector_list,
8791 base.head) {
8792 if (connector->new_encoder == encoder) {
8793 WARN_ON(!connector->new_encoder->new_crtc);
8794
8795 goto next_encoder;
8796 }
8797 }
8798 encoder->new_crtc = NULL;
8799next_encoder:
8800 /* Only now check for crtc changes so we don't miss encoders
8801 * that will be disabled. */
8802 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8803 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8804 config->mode_changed = true;
50f56119
DV		 8805 }
8806 }
9a935856 8807 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8808
2e431051
DV		 8809 return 0;
8810}
8811
8812static int intel_crtc_set_config(struct drm_mode_set *set)
8813{
8814 struct drm_device *dev;
2e431051
DV		 8815 struct drm_mode_set save_set;
8816 struct intel_set_config *config;
8817 int ret;
2e431051 8818
8d3e375e
DV		 8819 BUG_ON(!set);
8820 BUG_ON(!set->crtc);
8821 BUG_ON(!set->crtc->helper_private);
2e431051 8822
7e53f3a4
DV		 8823 /* Enforce sane interface api - has been abused by the fb helper. */
8824 BUG_ON(!set->mode && set->fb);
8825 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8826
2e431051
DV		 8827 if (set->fb) {
8828 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8829 set->crtc->base.id, set->fb->base.id,
8830 (int)set->num_connectors, set->x, set->y);
8831 } else {
8832 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8833 }
8834
8835 dev = set->crtc->dev;
8836
8837 ret = -ENOMEM;
8838 config = kzalloc(sizeof(*config), GFP_KERNEL);
8839 if (!config)
8840 goto out_config;
8841
8842 ret = intel_set_config_save_state(dev, config);
8843 if (ret)
8844 goto out_config;
8845
8846 save_set.crtc = set->crtc;
8847 save_set.mode = &set->crtc->mode;
8848 save_set.x = set->crtc->x;
8849 save_set.y = set->crtc->y;
8850 save_set.fb = set->crtc->fb;
8851
8852 /* Compute whether we need a full modeset, only an fb base update or no
8853 * change at all. In the future we might also check whether only the
8854 * mode changed, e.g. for LVDS where we only change the panel fitter in
8855 * such cases. */
8856 intel_set_config_compute_mode_changes(set, config);
8857
9a935856 8858 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8859 if (ret)
8860 goto fail;
8861
5e2b584e 8862 if (config->mode_changed) {
c0c36b94
CW		 8863 ret = intel_set_mode(set->crtc, set->mode,
8864 set->x, set->y, set->fb);
5e2b584e 8865 } else if (config->fb_changed) {
4878cae2
VS		 8866 intel_crtc_wait_for_pending_flips(set->crtc);
8867
4f660f49 8868 ret = intel_pipe_set_base(set->crtc,
94352cf9 8869 set->x, set->y, set->fb);
50f56119
DV		 8870 }
8871
2d05eae1 8872 if (ret) {
bf67dfeb
DV		 8873 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8874 set->crtc->base.id, ret);
50f56119 8875fail:
2d05eae1 8876 intel_set_config_restore_state(dev, config);
50f56119 8877
2d05eae1
CW		 8878 /* Try to restore the config */
8879 if (config->mode_changed &&
8880 intel_set_mode(save_set.crtc, save_set.mode,
8881 save_set.x, save_set.y, save_set.fb))
8882 DRM_ERROR("failed to restore config after modeset failure\n");
8883 }
50f56119 8884
d9e55608
DV		 8885out_config:
8886 intel_set_config_free(config);
50f56119
DV		 8887 return ret;
8888}
f6e5b160
CW		 8889
8890static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8891 .cursor_set = intel_crtc_cursor_set,
8892 .cursor_move = intel_crtc_cursor_move,
8893 .gamma_set = intel_crtc_gamma_set,
50f56119 8894 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8895 .destroy = intel_crtc_destroy,
8896 .page_flip = intel_crtc_page_flip,
8897};
8898
79f689aa
PZ		 8899static void intel_cpu_pll_init(struct drm_device *dev)
8900{
affa9354 8901 if (HAS_DDI(dev))
79f689aa
PZ		 8902 intel_ddi_pll_init(dev);
8903}
8904
5358901f
DV		 8905static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8906 struct intel_shared_dpll *pll,
8907 struct intel_dpll_hw_state *hw_state)
ee7b9f93 8908{
5358901f 8909 uint32_t val;
ee7b9f93 8910
5358901f 8911 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 8912 hw_state->dpll = val;
8913 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8914 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 8915
8916 return val & DPLL_VCO_ENABLE;
8917}
8918
15bdd4cf
DV		 8919static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8920 struct intel_shared_dpll *pll)
8921{
8922 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8923 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8924}
8925
e7b903d2
DV		 8926static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8927 struct intel_shared_dpll *pll)
8928{
e7b903d2
DV		 8929 /* PCH refclock must be enabled first */
8930 assert_pch_refclk_enabled(dev_priv);
8931
15bdd4cf
DV		 8932 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8933
8934 /* Wait for the clocks to stabilize. */
8935 POSTING_READ(PCH_DPLL(pll->id));
8936 udelay(150);
8937
8938 /* The pixel multiplier can only be updated once the
8939 * DPLL is enabled and the clocks are stable.
8940 *
8941 * So write it again.
8942 */
8943 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8944 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8945 udelay(200);
8946}
8947
8948static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8949 struct intel_shared_dpll *pll)
8950{
8951 struct drm_device *dev = dev_priv->dev;
8952 struct intel_crtc *crtc;
e7b903d2
DV		 8953
8954 /* Make sure no transcoder isn't still depending on us. */
8955 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8956 if (intel_crtc_to_shared_dpll(crtc) == pll)
8957 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 8958 }
8959
15bdd4cf
DV		 8960 I915_WRITE(PCH_DPLL(pll->id), 0);
8961 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8962 udelay(200);
8963}
8964
46edb027
DV		 8965static char *ibx_pch_dpll_names[] = {
8966 "PCH DPLL A",
8967 "PCH DPLL B",
8968};
8969
7c74ade1 8970static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8971{
e7b903d2 8972 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8973 int i;
8974
7c74ade1 8975 dev_priv->num_shared_dpll = 2;
ee7b9f93 8976
e72f9fbf 8977 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8978 dev_priv->shared_dplls[i].id = i;
8979 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 8980 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 8981 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8982 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 8983 dev_priv->shared_dplls[i].get_hw_state =
8984 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 8985 }
8986}
8987
7c74ade1
DV		 8988static void intel_shared_dpll_init(struct drm_device *dev)
8989{
e7b903d2 8990 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 8991
8992 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8993 ibx_pch_dpll_init(dev);
8994 else
8995 dev_priv->num_shared_dpll = 0;
8996
8997 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8998 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8999 dev_priv->num_shared_dpll);
9000}
9001
b358d0a6 9002static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9003{
22fd0fab 9004 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9005 struct intel_crtc *intel_crtc;
9006 int i;
9007
9008 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9009 if (intel_crtc == NULL)
9010 return;
9011
9012 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9013
9014 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9015 for (i = 0; i < 256; i++) {
9016 intel_crtc->lut_r[i] = i;
9017 intel_crtc->lut_g[i] = i;
9018 intel_crtc->lut_b[i] = i;
9019 }
9020
80824003
JB		 9021 /* Swap pipes & planes for FBC on pre-965 */
9022 intel_crtc->pipe = pipe;
9023 intel_crtc->plane = pipe;
e2e767ab 9024 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9025 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9026 intel_crtc->plane = !pipe;
80824003
JB		 9027 }
9028
22fd0fab
JB		 9029 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9030 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9031 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9032 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9033
79e53945 9034 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9035}
9036
08d7b3d1 9037int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9038 struct drm_file *file)
08d7b3d1 9039{
08d7b3d1 9040 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9041 struct drm_mode_object *drmmode_obj;
9042 struct intel_crtc *crtc;
08d7b3d1 9043
1cff8f6b
DV		 9044 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9045 return -ENODEV;
08d7b3d1 9046
c05422d5
DV		 9047 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9048 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9049
c05422d5 9050 if (!drmmode_obj) {
08d7b3d1
CW		 9051 DRM_ERROR("no such CRTC id\n");
9052 return -EINVAL;
9053 }
9054
c05422d5
DV		 9055 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9056 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9057
c05422d5 9058 return 0;
08d7b3d1
CW		 9059}
9060
66a9278e 9061static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9062{
66a9278e
DV		 9063 struct drm_device *dev = encoder->base.dev;
9064 struct intel_encoder *source_encoder;
79e53945 9065 int index_mask = 0;
79e53945
JB		 9066 int entry = 0;
9067
66a9278e
DV		 9068 list_for_each_entry(source_encoder,
9069 &dev->mode_config.encoder_list, base.head) {
9070
9071 if (encoder == source_encoder)
79e53945 9072 index_mask |= (1 << entry);
66a9278e
DV		 9073
9074 /* Intel hw has only one MUX where enocoders could be cloned. */
9075 if (encoder->cloneable && source_encoder->cloneable)
9076 index_mask |= (1 << entry);
9077
79e53945
JB		 9078 entry++;
9079 }
4ef69c7a 9080
79e53945
JB		 9081 return index_mask;
9082}
9083
4d302442
CW		 9084static bool has_edp_a(struct drm_device *dev)
9085{
9086 struct drm_i915_private *dev_priv = dev->dev_private;
9087
9088 if (!IS_MOBILE(dev))
9089 return false;
9090
9091 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9092 return false;
9093
9094 if (IS_GEN5(dev) &&
9095 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9096 return false;
9097
9098 return true;
9099}
9100
79e53945
JB		 9101static void intel_setup_outputs(struct drm_device *dev)
9102{
725e30ad 9103 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9104 struct intel_encoder *encoder;
cb0953d7 9105 bool dpd_is_edp = false;
79e53945 9106
c9093354 9107 intel_lvds_init(dev);
79e53945 9108
c40c0f5b 9109 if (!IS_ULT(dev))
79935fca 9110 intel_crt_init(dev);
cb0953d7 9111
affa9354 9112 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9113 int found;
9114
9115 /* Haswell uses DDI functions to detect digital outputs */
9116 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9117 /* DDI A only supports eDP */
9118 if (found)
9119 intel_ddi_init(dev, PORT_A);
9120
9121 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9122 * register */
9123 found = I915_READ(SFUSE_STRAP);
9124
9125 if (found & SFUSE_STRAP_DDIB_DETECTED)
9126 intel_ddi_init(dev, PORT_B);
9127 if (found & SFUSE_STRAP_DDIC_DETECTED)
9128 intel_ddi_init(dev, PORT_C);
9129 if (found & SFUSE_STRAP_DDID_DETECTED)
9130 intel_ddi_init(dev, PORT_D);
9131 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9132 int found;
270b3042
DV		 9133 dpd_is_edp = intel_dpd_is_edp(dev);
9134
9135 if (has_edp_a(dev))
9136 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9137
dc0fa718 9138 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9139 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9140 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9141 if (!found)
e2debe91 9142 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9143 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9144 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9145 }
9146
dc0fa718 9147 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9148 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9149
dc0fa718 9150 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9151 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9152
5eb08b69 9153 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9154 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9155
270b3042 9156 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9157 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9158 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9159 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9160 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9161 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9162
dc0fa718 9163 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9164 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9165 PORT_B);
67cfc203
VS		 9166 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9167 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9168 }
103a196f 9169 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9170 bool found = false;
7d57382e 9171
e2debe91 9172 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9173 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9174 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9175 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9176 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9177 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9178 }
27185ae1 9179
e7281eab 9180 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9181 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9182 }
13520b05
KH		 9183
9184 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9185
e2debe91 9186 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9187 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9188 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9189 }
27185ae1 9190
e2debe91 9191 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9192
b01f2c3a
JB		 9193 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9194 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9195 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9196 }
e7281eab 9197 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9198 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9199 }
27185ae1 9200
b01f2c3a 9201 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9202 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9203 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9204 } else if (IS_GEN2(dev))
79e53945
JB		 9205 intel_dvo_init(dev);
9206
103a196f 9207 if (SUPPORTS_TV(dev))
79e53945
JB		 9208 intel_tv_init(dev);
9209
4ef69c7a
CW		 9210 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9211 encoder->base.possible_crtcs = encoder->crtc_mask;
9212 encoder->base.possible_clones =
66a9278e 9213 intel_encoder_clones(encoder);
79e53945 9214 }
47356eb6 9215
dde86e2d 9216 intel_init_pch_refclk(dev);
270b3042
DV		 9217
9218 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9219}
9220
9221static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9222{
9223 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9224
9225 drm_framebuffer_cleanup(fb);
05394f39 9226 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9227
9228 kfree(intel_fb);
9229}
9230
9231static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9232 struct drm_file *file,
79e53945
JB		 9233 unsigned int *handle)
9234{
9235 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9236 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9237
05394f39 9238 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9239}
9240
9241static const struct drm_framebuffer_funcs intel_fb_funcs = {
9242 .destroy = intel_user_framebuffer_destroy,
9243 .create_handle = intel_user_framebuffer_create_handle,
9244};
9245
38651674
DA		 9246int intel_framebuffer_init(struct drm_device *dev,
9247 struct intel_framebuffer *intel_fb,
308e5bcb 9248 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9249 struct drm_i915_gem_object *obj)
79e53945 9250{
a35cdaa0 9251 int pitch_limit;
79e53945
JB		 9252 int ret;
9253
c16ed4be
CW		 9254 if (obj->tiling_mode == I915_TILING_Y) {
9255 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9256 return -EINVAL;
c16ed4be 9257 }
57cd6508 9258
c16ed4be
CW		 9259 if (mode_cmd->pitches[0] & 63) {
9260 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9261 mode_cmd->pitches[0]);
57cd6508 9262 return -EINVAL;
c16ed4be 9263 }
57cd6508 9264
a35cdaa0
CW		 9265 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9266 pitch_limit = 32*1024;
9267 } else if (INTEL_INFO(dev)->gen >= 4) {
9268 if (obj->tiling_mode)
9269 pitch_limit = 16*1024;
9270 else
9271 pitch_limit = 32*1024;
9272 } else if (INTEL_INFO(dev)->gen >= 3) {
9273 if (obj->tiling_mode)
9274 pitch_limit = 8*1024;
9275 else
9276 pitch_limit = 16*1024;
9277 } else
9278 /* XXX DSPC is limited to 4k tiled */
9279 pitch_limit = 8*1024;
9280
9281 if (mode_cmd->pitches[0] > pitch_limit) {
9282 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9283 obj->tiling_mode ? "tiled" : "linear",
9284 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9285 return -EINVAL;
c16ed4be 9286 }
5d7bd705
VS		 9287
9288 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9289 mode_cmd->pitches[0] != obj->stride) {
9290 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9291 mode_cmd->pitches[0], obj->stride);
5d7bd705 9292 return -EINVAL;
c16ed4be 9293 }
5d7bd705 9294
57779d06 9295 /* Reject formats not supported by any plane early. */
308e5bcb 9296 switch (mode_cmd->pixel_format) {
57779d06 9297 case DRM_FORMAT_C8:
04b3924d
VS		 9298 case DRM_FORMAT_RGB565:
9299 case DRM_FORMAT_XRGB8888:
9300 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9301 break;
9302 case DRM_FORMAT_XRGB1555:
9303 case DRM_FORMAT_ARGB1555:
c16ed4be 9304 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9305 DRM_DEBUG("unsupported pixel format: %s\n",
9306 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9307 return -EINVAL;
c16ed4be 9308 }
57779d06
VS		 9309 break;
9310 case DRM_FORMAT_XBGR8888:
9311 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9312 case DRM_FORMAT_XRGB2101010:
9313 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9314 case DRM_FORMAT_XBGR2101010:
9315 case DRM_FORMAT_ABGR2101010:
c16ed4be 9316 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9317 DRM_DEBUG("unsupported pixel format: %s\n",
9318 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9319 return -EINVAL;
c16ed4be 9320 }
b5626747 9321 break;
04b3924d
VS		 9322 case DRM_FORMAT_YUYV:
9323 case DRM_FORMAT_UYVY:
9324 case DRM_FORMAT_YVYU:
9325 case DRM_FORMAT_VYUY:
c16ed4be 9326 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9327 DRM_DEBUG("unsupported pixel format: %s\n",
9328 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9329 return -EINVAL;
c16ed4be 9330 }
57cd6508
CW		 9331 break;
9332 default:
4ee62c76
VS		 9333 DRM_DEBUG("unsupported pixel format: %s\n",
9334 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9335 return -EINVAL;
9336 }
9337
90f9a336
VS		 9338 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9339 if (mode_cmd->offsets[0] != 0)
9340 return -EINVAL;
9341
c7d73f6a
DV		 9342 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9343 intel_fb->obj = obj;
9344
79e53945
JB		 9345 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9346 if (ret) {
9347 DRM_ERROR("framebuffer init failed %d\n", ret);
9348 return ret;
9349 }
9350
79e53945
JB		 9351 return 0;
9352}
9353
79e53945
JB		 9354static struct drm_framebuffer *
9355intel_user_framebuffer_create(struct drm_device *dev,
9356 struct drm_file *filp,
308e5bcb 9357 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9358{
05394f39 9359 struct drm_i915_gem_object *obj;
79e53945 9360
308e5bcb
JB		 9361 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9362 mode_cmd->handles[0]));
c8725226 9363 if (&obj->base == NULL)
cce13ff7 9364 return ERR_PTR(-ENOENT);
79e53945 9365
d2dff872 9366 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9367}
9368
79e53945 9369static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9370 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9371 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9372};
9373
e70236a8
JB		 9374/* Set up chip specific display functions */
9375static void intel_init_display(struct drm_device *dev)
9376{
9377 struct drm_i915_private *dev_priv = dev->dev_private;
9378
ee9300bb
DV		 9379 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9380 dev_priv->display.find_dpll = g4x_find_best_dpll;
9381 else if (IS_VALLEYVIEW(dev))
9382 dev_priv->display.find_dpll = vlv_find_best_dpll;
9383 else if (IS_PINEVIEW(dev))
9384 dev_priv->display.find_dpll = pnv_find_best_dpll;
9385 else
9386 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9387
affa9354 9388 if (HAS_DDI(dev)) {
0e8ffe1b 9389 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9390 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9391 dev_priv->display.crtc_enable = haswell_crtc_enable;
9392 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9393 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9394 dev_priv->display.update_plane = ironlake_update_plane;
9395 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9396 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9397 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9398 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9399 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9400 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9401 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9402 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9403 } else if (IS_VALLEYVIEW(dev)) {
9404 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9405 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9406 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9407 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9408 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9409 dev_priv->display.off = i9xx_crtc_off;
9410 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9411 } else {
0e8ffe1b 9412 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9413 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9414 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9415 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9416 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9417 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9418 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9419 }
e70236a8 9420
e70236a8 9421 /* Returns the core display clock speed */
25eb05fc
JB		 9422 if (IS_VALLEYVIEW(dev))
9423 dev_priv->display.get_display_clock_speed =
9424 valleyview_get_display_clock_speed;
9425 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9426 dev_priv->display.get_display_clock_speed =
9427 i945_get_display_clock_speed;
9428 else if (IS_I915G(dev))
9429 dev_priv->display.get_display_clock_speed =
9430 i915_get_display_clock_speed;
f2b115e6 9431 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9432 dev_priv->display.get_display_clock_speed =
9433 i9xx_misc_get_display_clock_speed;
9434 else if (IS_I915GM(dev))
9435 dev_priv->display.get_display_clock_speed =
9436 i915gm_get_display_clock_speed;
9437 else if (IS_I865G(dev))
9438 dev_priv->display.get_display_clock_speed =
9439 i865_get_display_clock_speed;
f0f8a9ce 9440 else if (IS_I85X(dev))
e70236a8
JB		 9441 dev_priv->display.get_display_clock_speed =
9442 i855_get_display_clock_speed;
9443 else /* 852, 830 */
9444 dev_priv->display.get_display_clock_speed =
9445 i830_get_display_clock_speed;
9446
7f8a8569 9447 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9448 if (IS_GEN5(dev)) {
674cf967 9449 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9450 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9451 } else if (IS_GEN6(dev)) {
674cf967 9452 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9453 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9454 } else if (IS_IVYBRIDGE(dev)) {
9455 /* FIXME: detect B0+ stepping and use auto training */
9456 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9457 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9458 dev_priv->display.modeset_global_resources =
9459 ivb_modeset_global_resources;
c82e4d26
ED		 9460 } else if (IS_HASWELL(dev)) {
9461 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9462 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9463 dev_priv->display.modeset_global_resources =
9464 haswell_modeset_global_resources;
a0e63c22 9465 }
6067aaea 9466 } else if (IS_G4X(dev)) {
e0dac65e 9467 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9468 }
8c9f3aaf
JB		 9469
9470 /* Default just returns -ENODEV to indicate unsupported */
9471 dev_priv->display.queue_flip = intel_default_queue_flip;
9472
9473 switch (INTEL_INFO(dev)->gen) {
9474 case 2:
9475 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9476 break;
9477
9478 case 3:
9479 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9480 break;
9481
9482 case 4:
9483 case 5:
9484 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9485 break;
9486
9487 case 6:
9488 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9489 break;
7c9017e5
JB		 9490 case 7:
9491 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9492 break;
8c9f3aaf 9493 }
e70236a8
JB		 9494}
9495
b690e96c
JB		 9496/*
9497 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9498 * resume, or other times. This quirk makes sure that's the case for
9499 * affected systems.
9500 */
0206e353 9501static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9502{
9503 struct drm_i915_private *dev_priv = dev->dev_private;
9504
9505 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9506 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9507}
9508
435793df
KP		 9509/*
9510 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9511 */
9512static void quirk_ssc_force_disable(struct drm_device *dev)
9513{
9514 struct drm_i915_private *dev_priv = dev->dev_private;
9515 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9516 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9517}
9518
4dca20ef 9519/*
5a15ab5b
CE		 9520 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9521 * brightness value
4dca20ef
CE		 9522 */
9523static void quirk_invert_brightness(struct drm_device *dev)
9524{
9525 struct drm_i915_private *dev_priv = dev->dev_private;
9526 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9527 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9528}
9529
b690e96c
JB		 9530struct intel_quirk {
9531 int device;
9532 int subsystem_vendor;
9533 int subsystem_device;
9534 void (*hook)(struct drm_device *dev);
9535};
9536
5f85f176
EE		 9537/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9538struct intel_dmi_quirk {
9539 void (*hook)(struct drm_device *dev);
9540 const struct dmi_system_id (*dmi_id_list)[];
9541};
9542
9543static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9544{
9545 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9546 return 1;
9547}
9548
9549static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9550 {
9551 .dmi_id_list = &(const struct dmi_system_id[]) {
9552 {
9553 .callback = intel_dmi_reverse_brightness,
9554 .ident = "NCR Corporation",
9555 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9556 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9557 },
9558 },
9559 { } /* terminating entry */
9560 },
9561 .hook = quirk_invert_brightness,
9562 },
9563};
9564
c43b5634 9565static struct intel_quirk intel_quirks[] = {
b690e96c 9566 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9567 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9568
b690e96c
JB		 9569 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9570 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9571
b690e96c
JB		 9572 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9573 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9574
ccd0d36e 9575 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9576 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9577 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9578
9579 /* Lenovo U160 cannot use SSC on LVDS */
9580 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9581
9582 /* Sony Vaio Y cannot use SSC on LVDS */
9583 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9584
9585 /* Acer Aspire 5734Z must invert backlight brightness */
9586 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9587
9588 /* Acer/eMachines G725 */
9589 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9590
9591 /* Acer/eMachines e725 */
9592 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9593
9594 /* Acer/Packard Bell NCL20 */
9595 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9596
9597 /* Acer Aspire 4736Z */
9598 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9599};
9600
9601static void intel_init_quirks(struct drm_device *dev)
9602{
9603 struct pci_dev *d = dev->pdev;
9604 int i;
9605
9606 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9607 struct intel_quirk *q = &intel_quirks[i];
9608
9609 if (d->device == q->device &&
9610 (d->subsystem_vendor == q->subsystem_vendor ||
9611 q->subsystem_vendor == PCI_ANY_ID) &&
9612 (d->subsystem_device == q->subsystem_device ||
9613 q->subsystem_device == PCI_ANY_ID))
9614 q->hook(dev);
9615 }
5f85f176
EE		 9616 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9617 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9618 intel_dmi_quirks[i].hook(dev);
9619 }
b690e96c
JB		 9620}
9621
9cce37f4
JB		 9622/* Disable the VGA plane that we never use */
9623static void i915_disable_vga(struct drm_device *dev)
9624{
9625 struct drm_i915_private *dev_priv = dev->dev_private;
9626 u8 sr1;
766aa1c4 9627 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9628
9629 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9630 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9631 sr1 = inb(VGA_SR_DATA);
9632 outb(sr1 | 1<<5, VGA_SR_DATA);
9633 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9634 udelay(300);
9635
9636 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9637 POSTING_READ(vga_reg);
9638}
9639
f817586c
DV		 9640void intel_modeset_init_hw(struct drm_device *dev)
9641{
fa42e23c 9642 intel_init_power_well(dev);
0232e927 9643
a8f78b58
ED		 9644 intel_prepare_ddi(dev);
9645
f817586c
DV		 9646 intel_init_clock_gating(dev);
9647
79f5b2c7 9648 mutex_lock(&dev->struct_mutex);
8090c6b9 9649 intel_enable_gt_powersave(dev);
79f5b2c7 9650 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9651}
9652
7d708ee4
ID		 9653void intel_modeset_suspend_hw(struct drm_device *dev)
9654{
9655 intel_suspend_hw(dev);
9656}
9657
79e53945
JB		 9658void intel_modeset_init(struct drm_device *dev)
9659{
652c393a 9660 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9661 int i, j, ret;
79e53945
JB		 9662
9663 drm_mode_config_init(dev);
9664
9665 dev->mode_config.min_width = 0;
9666 dev->mode_config.min_height = 0;
9667
019d96cb
DA		 9668 dev->mode_config.preferred_depth = 24;
9669 dev->mode_config.prefer_shadow = 1;
9670
e6ecefaa 9671 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9672
b690e96c
JB		 9673 intel_init_quirks(dev);
9674
1fa61106
ED		 9675 intel_init_pm(dev);
9676
e3c74757
BW		 9677 if (INTEL_INFO(dev)->num_pipes == 0)
9678 return;
9679
e70236a8
JB		 9680 intel_init_display(dev);
9681
a6c45cf0
CW		 9682 if (IS_GEN2(dev)) {
9683 dev->mode_config.max_width = 2048;
9684 dev->mode_config.max_height = 2048;
9685 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9686 dev->mode_config.max_width = 4096;
9687 dev->mode_config.max_height = 4096;
79e53945 9688 } else {
a6c45cf0
CW		 9689 dev->mode_config.max_width = 8192;
9690 dev->mode_config.max_height = 8192;
79e53945 9691 }
5d4545ae 9692 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9693
28c97730 9694 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9695 INTEL_INFO(dev)->num_pipes,
9696 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9697
7eb552ae 9698 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9699 intel_crtc_init(dev, i);
7f1f3851
JB		 9700 for (j = 0; j < dev_priv->num_plane; j++) {
9701 ret = intel_plane_init(dev, i, j);
9702 if (ret)
06da8da2
VS		 9703 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9704 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9705 }
79e53945
JB		 9706 }
9707
79f689aa 9708 intel_cpu_pll_init(dev);
e72f9fbf 9709 intel_shared_dpll_init(dev);
ee7b9f93 9710
9cce37f4
JB		 9711 /* Just disable it once at startup */
9712 i915_disable_vga(dev);
79e53945 9713 intel_setup_outputs(dev);
11be49eb
CW		 9714
9715 /* Just in case the BIOS is doing something questionable. */
9716 intel_disable_fbc(dev);
2c7111db
CW		 9717}
9718
24929352
DV		 9719static void
9720intel_connector_break_all_links(struct intel_connector *connector)
9721{
9722 connector->base.dpms = DRM_MODE_DPMS_OFF;
9723 connector->base.encoder = NULL;
9724 connector->encoder->connectors_active = false;
9725 connector->encoder->base.crtc = NULL;
9726}
9727
7fad798e
DV		 9728static void intel_enable_pipe_a(struct drm_device *dev)
9729{
9730 struct intel_connector *connector;
9731 struct drm_connector *crt = NULL;
9732 struct intel_load_detect_pipe load_detect_temp;
9733
9734 /* We can't just switch on the pipe A, we need to set things up with a
9735 * proper mode and output configuration. As a gross hack, enable pipe A
9736 * by enabling the load detect pipe once. */
9737 list_for_each_entry(connector,
9738 &dev->mode_config.connector_list,
9739 base.head) {
9740 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9741 crt = &connector->base;
9742 break;
9743 }
9744 }
9745
9746 if (!crt)
9747 return;
9748
9749 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9750 intel_release_load_detect_pipe(crt, &load_detect_temp);
9751
652c393a 9752
7fad798e
DV		 9753}
9754
fa555837
DV		 9755static bool
9756intel_check_plane_mapping(struct intel_crtc *crtc)
9757{
7eb552ae
BW		 9758 struct drm_device *dev = crtc->base.dev;
9759 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9760 u32 reg, val;
9761
7eb552ae 9762 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9763 return true;
9764
9765 reg = DSPCNTR(!crtc->plane);
9766 val = I915_READ(reg);
9767
9768 if ((val & DISPLAY_PLANE_ENABLE) &&
9769 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9770 return false;
9771
9772 return true;
9773}
9774
24929352
DV		 9775static void intel_sanitize_crtc(struct intel_crtc *crtc)
9776{
9777 struct drm_device *dev = crtc->base.dev;
9778 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9779 u32 reg;
24929352 9780
24929352 9781 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9782 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9783 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9784
9785 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9786 * disable the crtc (and hence change the state) if it is wrong. Note
9787 * that gen4+ has a fixed plane -> pipe mapping. */
9788 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9789 struct intel_connector *connector;
9790 bool plane;
9791
24929352
DV		 9792 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9793 crtc->base.base.id);
9794
9795 /* Pipe has the wrong plane attached and the plane is active.
9796 * Temporarily change the plane mapping and disable everything
9797 * ... */
9798 plane = crtc->plane;
9799 crtc->plane = !plane;
9800 dev_priv->display.crtc_disable(&crtc->base);
9801 crtc->plane = plane;
9802
9803 /* ... and break all links. */
9804 list_for_each_entry(connector, &dev->mode_config.connector_list,
9805 base.head) {
9806 if (connector->encoder->base.crtc != &crtc->base)
9807 continue;
9808
9809 intel_connector_break_all_links(connector);
9810 }
9811
9812 WARN_ON(crtc->active);
9813 crtc->base.enabled = false;
9814 }
24929352 9815
7fad798e
DV		 9816 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9817 crtc->pipe == PIPE_A && !crtc->active) {
9818 /* BIOS forgot to enable pipe A, this mostly happens after
9819 * resume. Force-enable the pipe to fix this, the update_dpms
9820 * call below we restore the pipe to the right state, but leave
9821 * the required bits on. */
9822 intel_enable_pipe_a(dev);
9823 }
9824
24929352
DV		 9825 /* Adjust the state of the output pipe according to whether we
9826 * have active connectors/encoders. */
9827 intel_crtc_update_dpms(&crtc->base);
9828
9829 if (crtc->active != crtc->base.enabled) {
9830 struct intel_encoder *encoder;
9831
9832 /* This can happen either due to bugs in the get_hw_state
9833 * functions or because the pipe is force-enabled due to the
9834 * pipe A quirk. */
9835 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9836 crtc->base.base.id,
9837 crtc->base.enabled ? "enabled" : "disabled",
9838 crtc->active ? "enabled" : "disabled");
9839
9840 crtc->base.enabled = crtc->active;
9841
9842 /* Because we only establish the connector -> encoder ->
9843 * crtc links if something is active, this means the
9844 * crtc is now deactivated. Break the links. connector
9845 * -> encoder links are only establish when things are
9846 * actually up, hence no need to break them. */
9847 WARN_ON(crtc->active);
9848
9849 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9850 WARN_ON(encoder->connectors_active);
9851 encoder->base.crtc = NULL;
9852 }
9853 }
9854}
9855
9856static void intel_sanitize_encoder(struct intel_encoder *encoder)
9857{
9858 struct intel_connector *connector;
9859 struct drm_device *dev = encoder->base.dev;
9860
9861 /* We need to check both for a crtc link (meaning that the
9862 * encoder is active and trying to read from a pipe) and the
9863 * pipe itself being active. */
9864 bool has_active_crtc = encoder->base.crtc &&
9865 to_intel_crtc(encoder->base.crtc)->active;
9866
9867 if (encoder->connectors_active && !has_active_crtc) {
9868 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9869 encoder->base.base.id,
9870 drm_get_encoder_name(&encoder->base));
9871
9872 /* Connector is active, but has no active pipe. This is
9873 * fallout from our resume register restoring. Disable
9874 * the encoder manually again. */
9875 if (encoder->base.crtc) {
9876 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9877 encoder->base.base.id,
9878 drm_get_encoder_name(&encoder->base));
9879 encoder->disable(encoder);
9880 }
9881
9882 /* Inconsistent output/port/pipe state happens presumably due to
9883 * a bug in one of the get_hw_state functions. Or someplace else
9884 * in our code, like the register restore mess on resume. Clamp
9885 * things to off as a safer default. */
9886 list_for_each_entry(connector,
9887 &dev->mode_config.connector_list,
9888 base.head) {
9889 if (connector->encoder != encoder)
9890 continue;
9891
9892 intel_connector_break_all_links(connector);
9893 }
9894 }
9895 /* Enabled encoders without active connectors will be fixed in
9896 * the crtc fixup. */
9897}
9898
44cec740 9899void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9900{
9901 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9902 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9903
9904 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9905 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9906 i915_disable_vga(dev);
0fde901f
KM		 9907 }
9908}
9909
30e984df 9910static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9911{
9912 struct drm_i915_private *dev_priv = dev->dev_private;
9913 enum pipe pipe;
24929352
DV		 9914 struct intel_crtc *crtc;
9915 struct intel_encoder *encoder;
9916 struct intel_connector *connector;
5358901f 9917 int i;
24929352 9918
0e8ffe1b
DV		 9919 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9920 base.head) {
88adfff1 9921 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9922
0e8ffe1b
DV		 9923 crtc->active = dev_priv->display.get_pipe_config(crtc,
9924 &crtc->config);
24929352
DV		 9925
9926 crtc->base.enabled = crtc->active;
9927
9928 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9929 crtc->base.base.id,
9930 crtc->active ? "enabled" : "disabled");
9931 }
9932
5358901f 9933 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9934 if (HAS_DDI(dev))
6441ab5f
PZ		 9935 intel_ddi_setup_hw_pll_state(dev);
9936
5358901f
DV		 9937 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9938 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9939
9940 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9941 pll->active = 0;
9942 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9943 base.head) {
9944 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9945 pll->active++;
9946 }
9947 pll->refcount = pll->active;
9948
9949 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9950 pll->name, pll->refcount);
9951 }
9952
24929352
DV		 9953 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9954 base.head) {
9955 pipe = 0;
9956
9957 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9958 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9959 encoder->base.crtc = &crtc->base;
510d5f2f 9960 if (encoder->get_config)
045ac3b5 9961 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9962 } else {
9963 encoder->base.crtc = NULL;
9964 }
9965
9966 encoder->connectors_active = false;
9967 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9968 encoder->base.base.id,
9969 drm_get_encoder_name(&encoder->base),
9970 encoder->base.crtc ? "enabled" : "disabled",
9971 pipe);
9972 }
9973
510d5f2f
JB		 9974 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9975 base.head) {
9976 if (!crtc->active)
9977 continue;
9978 if (dev_priv->display.get_clock)
9979 dev_priv->display.get_clock(crtc,
9980 &crtc->config);
9981 }
9982
24929352
DV		 9983 list_for_each_entry(connector, &dev->mode_config.connector_list,
9984 base.head) {
9985 if (connector->get_hw_state(connector)) {
9986 connector->base.dpms = DRM_MODE_DPMS_ON;
9987 connector->encoder->connectors_active = true;
9988 connector->base.encoder = &connector->encoder->base;
9989 } else {
9990 connector->base.dpms = DRM_MODE_DPMS_OFF;
9991 connector->base.encoder = NULL;
9992 }
9993 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9994 connector->base.base.id,
9995 drm_get_connector_name(&connector->base),
9996 connector->base.encoder ? "enabled" : "disabled");
9997 }
30e984df
DV		 9998}
9999
10000/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10001 * and i915 state tracking structures. */
10002void intel_modeset_setup_hw_state(struct drm_device *dev,
10003 bool force_restore)
10004{
10005 struct drm_i915_private *dev_priv = dev->dev_private;
10006 enum pipe pipe;
10007 struct drm_plane *plane;
10008 struct intel_crtc *crtc;
10009 struct intel_encoder *encoder;
10010
10011 intel_modeset_readout_hw_state(dev);
24929352 10012
babea61d
JB		 10013 /*
10014 * Now that we have the config, copy it to each CRTC struct
10015 * Note that this could go away if we move to using crtc_config
10016 * checking everywhere.
10017 */
10018 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10019 base.head) {
10020 if (crtc->active && i915_fastboot) {
10021 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10022
10023 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10024 crtc->base.base.id);
10025 drm_mode_debug_printmodeline(&crtc->base.mode);
10026 }
10027 }
10028
24929352
DV		 10029 /* HW state is read out, now we need to sanitize this mess. */
10030 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10031 base.head) {
10032 intel_sanitize_encoder(encoder);
10033 }
10034
10035 for_each_pipe(pipe) {
10036 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10037 intel_sanitize_crtc(crtc);
c0b03411 10038 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10039 }
9a935856 10040
45e2b5f6 10041 if (force_restore) {
f30da187
DV		 10042 /*
10043 * We need to use raw interfaces for restoring state to avoid
10044 * checking (bogus) intermediate states.
10045 */
45e2b5f6 10046 for_each_pipe(pipe) {
b5644d05
JB		 10047 struct drm_crtc *crtc =
10048 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10049
10050 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10051 crtc->fb);
45e2b5f6 10052 }
b5644d05
JB		 10053 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10054 intel_plane_restore(plane);
0fde901f
KM		 10055
10056 i915_redisable_vga(dev);
45e2b5f6
DV		 10057 } else {
10058 intel_modeset_update_staged_output_state(dev);
10059 }
8af6cf88
DV		 10060
10061 intel_modeset_check_state(dev);
2e938892
DV		 10062
10063 drm_mode_config_reset(dev);
2c7111db
CW		 10064}
10065
10066void intel_modeset_gem_init(struct drm_device *dev)
10067{
1833b134 10068 intel_modeset_init_hw(dev);
02e792fb
DV		 10069
10070 intel_setup_overlay(dev);
24929352 10071
45e2b5f6 10072 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10073}
10074
10075void intel_modeset_cleanup(struct drm_device *dev)
10076{
652c393a
JB		 10077 struct drm_i915_private *dev_priv = dev->dev_private;
10078 struct drm_crtc *crtc;
10079 struct intel_crtc *intel_crtc;
10080
fd0c0642
DV		 10081 /*
10082 * Interrupts and polling as the first thing to avoid creating havoc.
10083 * Too much stuff here (turning of rps, connectors, ...) would
10084 * experience fancy races otherwise.
10085 */
10086 drm_irq_uninstall(dev);
10087 cancel_work_sync(&dev_priv->hotplug_work);
10088 /*
10089 * Due to the hpd irq storm handling the hotplug work can re-arm the
10090 * poll handlers. Hence disable polling after hpd handling is shut down.
10091 */
f87ea761 10092 drm_kms_helper_poll_fini(dev);
fd0c0642 10093
652c393a
JB		 10094 mutex_lock(&dev->struct_mutex);
10095
723bfd70
JB		 10096 intel_unregister_dsm_handler();
10097
652c393a
JB		 10098 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10099 /* Skip inactive CRTCs */
10100 if (!crtc->fb)
10101 continue;
10102
10103 intel_crtc = to_intel_crtc(crtc);
3dec0095 10104 intel_increase_pllclock(crtc);
652c393a
JB		 10105 }
10106
973d04f9 10107 intel_disable_fbc(dev);
e70236a8 10108
8090c6b9 10109 intel_disable_gt_powersave(dev);
0cdab21f 10110
930ebb46
DV		 10111 ironlake_teardown_rc6(dev);
10112
69341a5e
KH		 10113 mutex_unlock(&dev->struct_mutex);
10114
1630fe75
CW		 10115 /* flush any delayed tasks or pending work */
10116 flush_scheduled_work();
10117
dc652f90
JN		 10118 /* destroy backlight, if any, before the connectors */
10119 intel_panel_destroy_backlight(dev);
10120
79e53945 10121 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10122
10123 intel_cleanup_overlay(dev);
79e53945
JB		 10124}
10125
f1c79df3
ZW		 10126/*
10127 * Return which encoder is currently attached for connector.
10128 */
df0e9248 10129struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10130{
df0e9248
CW		 10131 return &intel_attached_encoder(connector)->base;
10132}
f1c79df3 10133
df0e9248
CW		 10134void intel_connector_attach_encoder(struct intel_connector *connector,
10135 struct intel_encoder *encoder)
10136{
10137 connector->encoder = encoder;
10138 drm_mode_connector_attach_encoder(&connector->base,
10139 &encoder->base);
79e53945 10140}
28d52043
DA		 10141
10142/*
10143 * set vga decode state - true == enable VGA decode
10144 */
10145int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10146{
10147 struct drm_i915_private *dev_priv = dev->dev_private;
10148 u16 gmch_ctrl;
10149
10150 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10151 if (state)
10152 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10153 else
10154 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10155 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10156 return 0;
10157}
c4a1d9e4
CW		 10158
10159#ifdef CONFIG_DEBUG_FS
10160#include <linux/seq_file.h>
10161
10162struct intel_display_error_state {
ff57f1b0
PZ		 10163
10164 u32 power_well_driver;
10165
c4a1d9e4
CW		 10166 struct intel_cursor_error_state {
10167 u32 control;
10168 u32 position;
10169 u32 base;
10170 u32 size;
52331309 10171 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10172
10173 struct intel_pipe_error_state {
ff57f1b0 10174 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10175 u32 conf;
10176 u32 source;
10177
10178 u32 htotal;
10179 u32 hblank;
10180 u32 hsync;
10181 u32 vtotal;
10182 u32 vblank;
10183 u32 vsync;
52331309 10184 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10185
10186 struct intel_plane_error_state {
10187 u32 control;
10188 u32 stride;
10189 u32 size;
10190 u32 pos;
10191 u32 addr;
10192 u32 surface;
10193 u32 tile_offset;
52331309 10194 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10195};
10196
10197struct intel_display_error_state *
10198intel_display_capture_error_state(struct drm_device *dev)
10199{
0206e353 10200 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10201 struct intel_display_error_state *error;
702e7a56 10202 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10203 int i;
10204
10205 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10206 if (error == NULL)
10207 return NULL;
10208
ff57f1b0
PZ		 10209 if (HAS_POWER_WELL(dev))
10210 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10211
52331309 10212 for_each_pipe(i) {
702e7a56 10213 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10214 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10215
a18c4c3d
PZ		 10216 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10217 error->cursor[i].control = I915_READ(CURCNTR(i));
10218 error->cursor[i].position = I915_READ(CURPOS(i));
10219 error->cursor[i].base = I915_READ(CURBASE(i));
10220 } else {
10221 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10222 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10223 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10224 }
c4a1d9e4
CW		 10225
10226 error->plane[i].control = I915_READ(DSPCNTR(i));
10227 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10228 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10229 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10230 error->plane[i].pos = I915_READ(DSPPOS(i));
10231 }
ca291363
PZ		 10232 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10233 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10234 if (INTEL_INFO(dev)->gen >= 4) {
10235 error->plane[i].surface = I915_READ(DSPSURF(i));
10236 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10237 }
10238
702e7a56 10239 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10240 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10241 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10242 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10243 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10244 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10245 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10246 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10247 }
10248
12d217c7
PZ		 10249 /* In the code above we read the registers without checking if the power
10250 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10251 * prevent the next I915_WRITE from detecting it and printing an error
10252 * message. */
10253 if (HAS_POWER_WELL(dev))
10254 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10255
c4a1d9e4
CW		 10256 return error;
10257}
10258
edc3d884
MK		 10259#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10260
c4a1d9e4 10261void
edc3d884 10262intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10263 struct drm_device *dev,
10264 struct intel_display_error_state *error)
10265{
10266 int i;
10267
edc3d884 10268 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10269 if (HAS_POWER_WELL(dev))
edc3d884 10270 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10271 error->power_well_driver);
52331309 10272 for_each_pipe(i) {
edc3d884
MK		 10273 err_printf(m, "Pipe [%d]:\n", i);
10274 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10275 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10276 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10277 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10278 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10279 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10280 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10281 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10282 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10283 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10284
10285 err_printf(m, "Plane [%d]:\n", i);
10286 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10287 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10288 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10289 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10290 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10291 }
4b71a570 10292 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10293 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10294 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10295 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10296 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10297 }
10298
edc3d884
MK		 10299 err_printf(m, "Cursor [%d]:\n", i);
10300 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10301 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10302 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10303 }
10304}
10305#endif
Linux kernel - Deliverables
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