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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c | 48 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 49 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
50 | DRM_FORMAT_C8, |
51 | DRM_FORMAT_RGB565, | |
465c120c | 52 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 53 | DRM_FORMAT_XRGB8888, |
465c120c MR |
54 | }; |
55 | ||
56 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 57 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
58 | DRM_FORMAT_C8, |
59 | DRM_FORMAT_RGB565, | |
60 | DRM_FORMAT_XRGB8888, | |
61 | DRM_FORMAT_XBGR8888, | |
62 | DRM_FORMAT_XRGB2101010, | |
63 | DRM_FORMAT_XBGR2101010, | |
64 | }; | |
65 | ||
66 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
465c120c | 70 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 71 | DRM_FORMAT_ARGB8888, |
465c120c MR |
72 | DRM_FORMAT_ABGR8888, |
73 | DRM_FORMAT_XRGB2101010, | |
465c120c | 74 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
75 | DRM_FORMAT_YUYV, |
76 | DRM_FORMAT_YVYU, | |
77 | DRM_FORMAT_UYVY, | |
78 | DRM_FORMAT_VYUY, | |
465c120c MR |
79 | }; |
80 | ||
3d7d6510 MR |
81 | /* Cursor formats */ |
82 | static const uint32_t intel_cursor_formats[] = { | |
83 | DRM_FORMAT_ARGB8888, | |
84 | }; | |
85 | ||
6b383a7f | 86 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 87 | |
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
e7457a9a | 119 | |
79e53945 | 120 | typedef struct { |
0206e353 | 121 | int min, max; |
79e53945 JB |
122 | } intel_range_t; |
123 | ||
124 | typedef struct { | |
0206e353 AJ |
125 | int dot_limit; |
126 | int p2_slow, p2_fast; | |
79e53945 JB |
127 | } intel_p2_t; |
128 | ||
d4906093 ML |
129 | typedef struct intel_limit intel_limit_t; |
130 | struct intel_limit { | |
0206e353 AJ |
131 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
132 | intel_p2_t p2; | |
d4906093 | 133 | }; |
79e53945 | 134 | |
bfa7df01 VS |
135 | /* returns HPLL frequency in kHz */ |
136 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
137 | { | |
138 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
139 | ||
140 | /* Obtain SKU information */ | |
141 | mutex_lock(&dev_priv->sb_lock); | |
142 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
143 | CCK_FUSE_HPLL_FREQ_MASK; | |
144 | mutex_unlock(&dev_priv->sb_lock); | |
145 | ||
146 | return vco_freq[hpll_freq] * 1000; | |
147 | } | |
148 | ||
149 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
150 | const char *name, u32 reg) | |
151 | { | |
152 | u32 val; | |
153 | int divider; | |
154 | ||
155 | if (dev_priv->hpll_freq == 0) | |
156 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
157 | ||
158 | mutex_lock(&dev_priv->sb_lock); | |
159 | val = vlv_cck_read(dev_priv, reg); | |
160 | mutex_unlock(&dev_priv->sb_lock); | |
161 | ||
162 | divider = val & CCK_FREQUENCY_VALUES; | |
163 | ||
164 | WARN((val & CCK_FREQUENCY_STATUS) != | |
165 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
166 | "%s change in progress\n", name); | |
167 | ||
168 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
169 | } | |
170 | ||
d2acd215 DV |
171 | int |
172 | intel_pch_rawclk(struct drm_device *dev) | |
173 | { | |
174 | struct drm_i915_private *dev_priv = dev->dev_private; | |
175 | ||
176 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
177 | ||
178 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
179 | } | |
180 | ||
79e50a4f JN |
181 | /* hrawclock is 1/4 the FSB frequency */ |
182 | int intel_hrawclk(struct drm_device *dev) | |
183 | { | |
184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
185 | uint32_t clkcfg; | |
186 | ||
187 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
188 | if (IS_VALLEYVIEW(dev)) | |
189 | return 200; | |
190 | ||
191 | clkcfg = I915_READ(CLKCFG); | |
192 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
193 | case CLKCFG_FSB_400: | |
194 | return 100; | |
195 | case CLKCFG_FSB_533: | |
196 | return 133; | |
197 | case CLKCFG_FSB_667: | |
198 | return 166; | |
199 | case CLKCFG_FSB_800: | |
200 | return 200; | |
201 | case CLKCFG_FSB_1067: | |
202 | return 266; | |
203 | case CLKCFG_FSB_1333: | |
204 | return 333; | |
205 | /* these two are just a guess; one of them might be right */ | |
206 | case CLKCFG_FSB_1600: | |
207 | case CLKCFG_FSB_1600_ALT: | |
208 | return 400; | |
209 | default: | |
210 | return 133; | |
211 | } | |
212 | } | |
213 | ||
bfa7df01 VS |
214 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
215 | { | |
216 | if (!IS_VALLEYVIEW(dev_priv)) | |
217 | return; | |
218 | ||
219 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
220 | CCK_CZ_CLOCK_CONTROL); | |
221 | ||
222 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
223 | } | |
224 | ||
021357ac CW |
225 | static inline u32 /* units of 100MHz */ |
226 | intel_fdi_link_freq(struct drm_device *dev) | |
227 | { | |
8b99e68c CW |
228 | if (IS_GEN5(dev)) { |
229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
230 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
231 | } else | |
232 | return 27; | |
021357ac CW |
233 | } |
234 | ||
5d536e28 | 235 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 236 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 237 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 238 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
239 | .m = { .min = 96, .max = 140 }, |
240 | .m1 = { .min = 18, .max = 26 }, | |
241 | .m2 = { .min = 6, .max = 16 }, | |
242 | .p = { .min = 4, .max = 128 }, | |
243 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
244 | .p2 = { .dot_limit = 165000, |
245 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
246 | }; |
247 | ||
5d536e28 DV |
248 | static const intel_limit_t intel_limits_i8xx_dvo = { |
249 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 250 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 251 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
252 | .m = { .min = 96, .max = 140 }, |
253 | .m1 = { .min = 18, .max = 26 }, | |
254 | .m2 = { .min = 6, .max = 16 }, | |
255 | .p = { .min = 4, .max = 128 }, | |
256 | .p1 = { .min = 2, .max = 33 }, | |
257 | .p2 = { .dot_limit = 165000, | |
258 | .p2_slow = 4, .p2_fast = 4 }, | |
259 | }; | |
260 | ||
e4b36699 | 261 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 262 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 263 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 264 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
265 | .m = { .min = 96, .max = 140 }, |
266 | .m1 = { .min = 18, .max = 26 }, | |
267 | .m2 = { .min = 6, .max = 16 }, | |
268 | .p = { .min = 4, .max = 128 }, | |
269 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
270 | .p2 = { .dot_limit = 165000, |
271 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 272 | }; |
273e27ca | 273 | |
e4b36699 | 274 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
275 | .dot = { .min = 20000, .max = 400000 }, |
276 | .vco = { .min = 1400000, .max = 2800000 }, | |
277 | .n = { .min = 1, .max = 6 }, | |
278 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
279 | .m1 = { .min = 8, .max = 18 }, |
280 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
281 | .p = { .min = 5, .max = 80 }, |
282 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
283 | .p2 = { .dot_limit = 200000, |
284 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
285 | }; |
286 | ||
287 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
288 | .dot = { .min = 20000, .max = 400000 }, |
289 | .vco = { .min = 1400000, .max = 2800000 }, | |
290 | .n = { .min = 1, .max = 6 }, | |
291 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
292 | .m1 = { .min = 8, .max = 18 }, |
293 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
294 | .p = { .min = 7, .max = 98 }, |
295 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
296 | .p2 = { .dot_limit = 112000, |
297 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
298 | }; |
299 | ||
273e27ca | 300 | |
e4b36699 | 301 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
302 | .dot = { .min = 25000, .max = 270000 }, |
303 | .vco = { .min = 1750000, .max = 3500000}, | |
304 | .n = { .min = 1, .max = 4 }, | |
305 | .m = { .min = 104, .max = 138 }, | |
306 | .m1 = { .min = 17, .max = 23 }, | |
307 | .m2 = { .min = 5, .max = 11 }, | |
308 | .p = { .min = 10, .max = 30 }, | |
309 | .p1 = { .min = 1, .max = 3}, | |
310 | .p2 = { .dot_limit = 270000, | |
311 | .p2_slow = 10, | |
312 | .p2_fast = 10 | |
044c7c41 | 313 | }, |
e4b36699 KP |
314 | }; |
315 | ||
316 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
317 | .dot = { .min = 22000, .max = 400000 }, |
318 | .vco = { .min = 1750000, .max = 3500000}, | |
319 | .n = { .min = 1, .max = 4 }, | |
320 | .m = { .min = 104, .max = 138 }, | |
321 | .m1 = { .min = 16, .max = 23 }, | |
322 | .m2 = { .min = 5, .max = 11 }, | |
323 | .p = { .min = 5, .max = 80 }, | |
324 | .p1 = { .min = 1, .max = 8}, | |
325 | .p2 = { .dot_limit = 165000, | |
326 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
327 | }; |
328 | ||
329 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
330 | .dot = { .min = 20000, .max = 115000 }, |
331 | .vco = { .min = 1750000, .max = 3500000 }, | |
332 | .n = { .min = 1, .max = 3 }, | |
333 | .m = { .min = 104, .max = 138 }, | |
334 | .m1 = { .min = 17, .max = 23 }, | |
335 | .m2 = { .min = 5, .max = 11 }, | |
336 | .p = { .min = 28, .max = 112 }, | |
337 | .p1 = { .min = 2, .max = 8 }, | |
338 | .p2 = { .dot_limit = 0, | |
339 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 340 | }, |
e4b36699 KP |
341 | }; |
342 | ||
343 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
344 | .dot = { .min = 80000, .max = 224000 }, |
345 | .vco = { .min = 1750000, .max = 3500000 }, | |
346 | .n = { .min = 1, .max = 3 }, | |
347 | .m = { .min = 104, .max = 138 }, | |
348 | .m1 = { .min = 17, .max = 23 }, | |
349 | .m2 = { .min = 5, .max = 11 }, | |
350 | .p = { .min = 14, .max = 42 }, | |
351 | .p1 = { .min = 2, .max = 6 }, | |
352 | .p2 = { .dot_limit = 0, | |
353 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 354 | }, |
e4b36699 KP |
355 | }; |
356 | ||
f2b115e6 | 357 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
358 | .dot = { .min = 20000, .max = 400000}, |
359 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 360 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
361 | .n = { .min = 3, .max = 6 }, |
362 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 363 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
364 | .m1 = { .min = 0, .max = 0 }, |
365 | .m2 = { .min = 0, .max = 254 }, | |
366 | .p = { .min = 5, .max = 80 }, | |
367 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
368 | .p2 = { .dot_limit = 200000, |
369 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
370 | }; |
371 | ||
f2b115e6 | 372 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
373 | .dot = { .min = 20000, .max = 400000 }, |
374 | .vco = { .min = 1700000, .max = 3500000 }, | |
375 | .n = { .min = 3, .max = 6 }, | |
376 | .m = { .min = 2, .max = 256 }, | |
377 | .m1 = { .min = 0, .max = 0 }, | |
378 | .m2 = { .min = 0, .max = 254 }, | |
379 | .p = { .min = 7, .max = 112 }, | |
380 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
381 | .p2 = { .dot_limit = 112000, |
382 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
383 | }; |
384 | ||
273e27ca EA |
385 | /* Ironlake / Sandybridge |
386 | * | |
387 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
388 | * the range value for them is (actual_value - 2). | |
389 | */ | |
b91ad0ec | 390 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
391 | .dot = { .min = 25000, .max = 350000 }, |
392 | .vco = { .min = 1760000, .max = 3510000 }, | |
393 | .n = { .min = 1, .max = 5 }, | |
394 | .m = { .min = 79, .max = 127 }, | |
395 | .m1 = { .min = 12, .max = 22 }, | |
396 | .m2 = { .min = 5, .max = 9 }, | |
397 | .p = { .min = 5, .max = 80 }, | |
398 | .p1 = { .min = 1, .max = 8 }, | |
399 | .p2 = { .dot_limit = 225000, | |
400 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
401 | }; |
402 | ||
b91ad0ec | 403 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
404 | .dot = { .min = 25000, .max = 350000 }, |
405 | .vco = { .min = 1760000, .max = 3510000 }, | |
406 | .n = { .min = 1, .max = 3 }, | |
407 | .m = { .min = 79, .max = 118 }, | |
408 | .m1 = { .min = 12, .max = 22 }, | |
409 | .m2 = { .min = 5, .max = 9 }, | |
410 | .p = { .min = 28, .max = 112 }, | |
411 | .p1 = { .min = 2, .max = 8 }, | |
412 | .p2 = { .dot_limit = 225000, | |
413 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
414 | }; |
415 | ||
416 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
417 | .dot = { .min = 25000, .max = 350000 }, |
418 | .vco = { .min = 1760000, .max = 3510000 }, | |
419 | .n = { .min = 1, .max = 3 }, | |
420 | .m = { .min = 79, .max = 127 }, | |
421 | .m1 = { .min = 12, .max = 22 }, | |
422 | .m2 = { .min = 5, .max = 9 }, | |
423 | .p = { .min = 14, .max = 56 }, | |
424 | .p1 = { .min = 2, .max = 8 }, | |
425 | .p2 = { .dot_limit = 225000, | |
426 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
427 | }; |
428 | ||
273e27ca | 429 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 430 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
431 | .dot = { .min = 25000, .max = 350000 }, |
432 | .vco = { .min = 1760000, .max = 3510000 }, | |
433 | .n = { .min = 1, .max = 2 }, | |
434 | .m = { .min = 79, .max = 126 }, | |
435 | .m1 = { .min = 12, .max = 22 }, | |
436 | .m2 = { .min = 5, .max = 9 }, | |
437 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 438 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
439 | .p2 = { .dot_limit = 225000, |
440 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
441 | }; |
442 | ||
443 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
444 | .dot = { .min = 25000, .max = 350000 }, |
445 | .vco = { .min = 1760000, .max = 3510000 }, | |
446 | .n = { .min = 1, .max = 3 }, | |
447 | .m = { .min = 79, .max = 126 }, | |
448 | .m1 = { .min = 12, .max = 22 }, | |
449 | .m2 = { .min = 5, .max = 9 }, | |
450 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 451 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
452 | .p2 = { .dot_limit = 225000, |
453 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
454 | }; |
455 | ||
dc730512 | 456 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
457 | /* |
458 | * These are the data rate limits (measured in fast clocks) | |
459 | * since those are the strictest limits we have. The fast | |
460 | * clock and actual rate limits are more relaxed, so checking | |
461 | * them would make no difference. | |
462 | */ | |
463 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 464 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 465 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
466 | .m1 = { .min = 2, .max = 3 }, |
467 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 468 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 469 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
470 | }; |
471 | ||
ef9348c8 CML |
472 | static const intel_limit_t intel_limits_chv = { |
473 | /* | |
474 | * These are the data rate limits (measured in fast clocks) | |
475 | * since those are the strictest limits we have. The fast | |
476 | * clock and actual rate limits are more relaxed, so checking | |
477 | * them would make no difference. | |
478 | */ | |
479 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 480 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
481 | .n = { .min = 1, .max = 1 }, |
482 | .m1 = { .min = 2, .max = 2 }, | |
483 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
484 | .p1 = { .min = 2, .max = 4 }, | |
485 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
486 | }; | |
487 | ||
5ab7b0b7 ID |
488 | static const intel_limit_t intel_limits_bxt = { |
489 | /* FIXME: find real dot limits */ | |
490 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 491 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
492 | .n = { .min = 1, .max = 1 }, |
493 | .m1 = { .min = 2, .max = 2 }, | |
494 | /* FIXME: find real m2 limits */ | |
495 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
496 | .p1 = { .min = 2, .max = 4 }, | |
497 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
498 | }; | |
499 | ||
cdba954e ACO |
500 | static bool |
501 | needs_modeset(struct drm_crtc_state *state) | |
502 | { | |
fc596660 | 503 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
504 | } |
505 | ||
e0638cdf PZ |
506 | /** |
507 | * Returns whether any output on the specified pipe is of the specified type | |
508 | */ | |
4093561b | 509 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 510 | { |
409ee761 | 511 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
512 | struct intel_encoder *encoder; |
513 | ||
409ee761 | 514 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
515 | if (encoder->type == type) |
516 | return true; | |
517 | ||
518 | return false; | |
519 | } | |
520 | ||
d0737e1d ACO |
521 | /** |
522 | * Returns whether any output on the specified pipe will have the specified | |
523 | * type after a staged modeset is complete, i.e., the same as | |
524 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
525 | * encoder->crtc. | |
526 | */ | |
a93e255f ACO |
527 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
528 | int type) | |
d0737e1d | 529 | { |
a93e255f | 530 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 531 | struct drm_connector *connector; |
a93e255f | 532 | struct drm_connector_state *connector_state; |
d0737e1d | 533 | struct intel_encoder *encoder; |
a93e255f ACO |
534 | int i, num_connectors = 0; |
535 | ||
da3ced29 | 536 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
537 | if (connector_state->crtc != crtc_state->base.crtc) |
538 | continue; | |
539 | ||
540 | num_connectors++; | |
d0737e1d | 541 | |
a93e255f ACO |
542 | encoder = to_intel_encoder(connector_state->best_encoder); |
543 | if (encoder->type == type) | |
d0737e1d | 544 | return true; |
a93e255f ACO |
545 | } |
546 | ||
547 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
548 | |
549 | return false; | |
550 | } | |
551 | ||
a93e255f ACO |
552 | static const intel_limit_t * |
553 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 554 | { |
a93e255f | 555 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 556 | const intel_limit_t *limit; |
b91ad0ec | 557 | |
a93e255f | 558 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 559 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 560 | if (refclk == 100000) |
b91ad0ec ZW |
561 | limit = &intel_limits_ironlake_dual_lvds_100m; |
562 | else | |
563 | limit = &intel_limits_ironlake_dual_lvds; | |
564 | } else { | |
1b894b59 | 565 | if (refclk == 100000) |
b91ad0ec ZW |
566 | limit = &intel_limits_ironlake_single_lvds_100m; |
567 | else | |
568 | limit = &intel_limits_ironlake_single_lvds; | |
569 | } | |
c6bb3538 | 570 | } else |
b91ad0ec | 571 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
572 | |
573 | return limit; | |
574 | } | |
575 | ||
a93e255f ACO |
576 | static const intel_limit_t * |
577 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 578 | { |
a93e255f | 579 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
580 | const intel_limit_t *limit; |
581 | ||
a93e255f | 582 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 583 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 584 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 585 | else |
e4b36699 | 586 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
587 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
588 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 589 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 590 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 591 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 592 | } else /* The option is for other outputs */ |
e4b36699 | 593 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
594 | |
595 | return limit; | |
596 | } | |
597 | ||
a93e255f ACO |
598 | static const intel_limit_t * |
599 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 600 | { |
a93e255f | 601 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
602 | const intel_limit_t *limit; |
603 | ||
5ab7b0b7 ID |
604 | if (IS_BROXTON(dev)) |
605 | limit = &intel_limits_bxt; | |
606 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 607 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 608 | else if (IS_G4X(dev)) { |
a93e255f | 609 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 610 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 611 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 612 | limit = &intel_limits_pineview_lvds; |
2177832f | 613 | else |
f2b115e6 | 614 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
615 | } else if (IS_CHERRYVIEW(dev)) { |
616 | limit = &intel_limits_chv; | |
a0c4da24 | 617 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 618 | limit = &intel_limits_vlv; |
a6c45cf0 | 619 | } else if (!IS_GEN2(dev)) { |
a93e255f | 620 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
621 | limit = &intel_limits_i9xx_lvds; |
622 | else | |
623 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 624 | } else { |
a93e255f | 625 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 626 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 627 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 628 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
629 | else |
630 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
631 | } |
632 | return limit; | |
633 | } | |
634 | ||
dccbea3b ID |
635 | /* |
636 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
637 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
638 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
639 | * The helpers' return value is the rate of the clock that is fed to the | |
640 | * display engine's pipe which can be the above fast dot clock rate or a | |
641 | * divided-down version of it. | |
642 | */ | |
f2b115e6 | 643 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 644 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 645 | { |
2177832f SL |
646 | clock->m = clock->m2 + 2; |
647 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 648 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 649 | return 0; |
fb03ac01 VS |
650 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
651 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
652 | |
653 | return clock->dot; | |
2177832f SL |
654 | } |
655 | ||
7429e9d4 DV |
656 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
657 | { | |
658 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
659 | } | |
660 | ||
dccbea3b | 661 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 662 | { |
7429e9d4 | 663 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 664 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 665 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 666 | return 0; |
fb03ac01 VS |
667 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
668 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
669 | |
670 | return clock->dot; | |
79e53945 JB |
671 | } |
672 | ||
dccbea3b | 673 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
674 | { |
675 | clock->m = clock->m1 * clock->m2; | |
676 | clock->p = clock->p1 * clock->p2; | |
677 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 678 | return 0; |
589eca67 ID |
679 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
680 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
681 | |
682 | return clock->dot / 5; | |
589eca67 ID |
683 | } |
684 | ||
dccbea3b | 685 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
686 | { |
687 | clock->m = clock->m1 * clock->m2; | |
688 | clock->p = clock->p1 * clock->p2; | |
689 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 690 | return 0; |
ef9348c8 CML |
691 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
692 | clock->n << 22); | |
693 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
694 | |
695 | return clock->dot / 5; | |
ef9348c8 CML |
696 | } |
697 | ||
7c04d1d9 | 698 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
699 | /** |
700 | * Returns whether the given set of divisors are valid for a given refclk with | |
701 | * the given connectors. | |
702 | */ | |
703 | ||
1b894b59 CW |
704 | static bool intel_PLL_is_valid(struct drm_device *dev, |
705 | const intel_limit_t *limit, | |
706 | const intel_clock_t *clock) | |
79e53945 | 707 | { |
f01b7962 VS |
708 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
709 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 710 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 711 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 712 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 713 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 714 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 715 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 716 | |
5ab7b0b7 | 717 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
718 | if (clock->m1 <= clock->m2) |
719 | INTELPllInvalid("m1 <= m2\n"); | |
720 | ||
5ab7b0b7 | 721 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
722 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
723 | INTELPllInvalid("p out of range\n"); | |
724 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
725 | INTELPllInvalid("m out of range\n"); | |
726 | } | |
727 | ||
79e53945 | 728 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 729 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
730 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
731 | * connector, etc., rather than just a single range. | |
732 | */ | |
733 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 734 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
735 | |
736 | return true; | |
737 | } | |
738 | ||
3b1429d9 VS |
739 | static int |
740 | i9xx_select_p2_div(const intel_limit_t *limit, | |
741 | const struct intel_crtc_state *crtc_state, | |
742 | int target) | |
79e53945 | 743 | { |
3b1429d9 | 744 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 745 | |
a93e255f | 746 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 747 | /* |
a210b028 DV |
748 | * For LVDS just rely on its current settings for dual-channel. |
749 | * We haven't figured out how to reliably set up different | |
750 | * single/dual channel state, if we even can. | |
79e53945 | 751 | */ |
1974cad0 | 752 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 753 | return limit->p2.p2_fast; |
79e53945 | 754 | else |
3b1429d9 | 755 | return limit->p2.p2_slow; |
79e53945 JB |
756 | } else { |
757 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 758 | return limit->p2.p2_slow; |
79e53945 | 759 | else |
3b1429d9 | 760 | return limit->p2.p2_fast; |
79e53945 | 761 | } |
3b1429d9 VS |
762 | } |
763 | ||
764 | static bool | |
765 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
766 | struct intel_crtc_state *crtc_state, | |
767 | int target, int refclk, intel_clock_t *match_clock, | |
768 | intel_clock_t *best_clock) | |
769 | { | |
770 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
771 | intel_clock_t clock; | |
772 | int err = target; | |
79e53945 | 773 | |
0206e353 | 774 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 775 | |
3b1429d9 VS |
776 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
777 | ||
42158660 ZY |
778 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
779 | clock.m1++) { | |
780 | for (clock.m2 = limit->m2.min; | |
781 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 782 | if (clock.m2 >= clock.m1) |
42158660 ZY |
783 | break; |
784 | for (clock.n = limit->n.min; | |
785 | clock.n <= limit->n.max; clock.n++) { | |
786 | for (clock.p1 = limit->p1.min; | |
787 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
788 | int this_err; |
789 | ||
dccbea3b | 790 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
791 | if (!intel_PLL_is_valid(dev, limit, |
792 | &clock)) | |
793 | continue; | |
794 | if (match_clock && | |
795 | clock.p != match_clock->p) | |
796 | continue; | |
797 | ||
798 | this_err = abs(clock.dot - target); | |
799 | if (this_err < err) { | |
800 | *best_clock = clock; | |
801 | err = this_err; | |
802 | } | |
803 | } | |
804 | } | |
805 | } | |
806 | } | |
807 | ||
808 | return (err != target); | |
809 | } | |
810 | ||
811 | static bool | |
a93e255f ACO |
812 | pnv_find_best_dpll(const intel_limit_t *limit, |
813 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
814 | int target, int refclk, intel_clock_t *match_clock, |
815 | intel_clock_t *best_clock) | |
79e53945 | 816 | { |
3b1429d9 | 817 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 818 | intel_clock_t clock; |
79e53945 JB |
819 | int err = target; |
820 | ||
0206e353 | 821 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 822 | |
3b1429d9 VS |
823 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
824 | ||
42158660 ZY |
825 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
826 | clock.m1++) { | |
827 | for (clock.m2 = limit->m2.min; | |
828 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
829 | for (clock.n = limit->n.min; |
830 | clock.n <= limit->n.max; clock.n++) { | |
831 | for (clock.p1 = limit->p1.min; | |
832 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
833 | int this_err; |
834 | ||
dccbea3b | 835 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
836 | if (!intel_PLL_is_valid(dev, limit, |
837 | &clock)) | |
79e53945 | 838 | continue; |
cec2f356 SP |
839 | if (match_clock && |
840 | clock.p != match_clock->p) | |
841 | continue; | |
79e53945 JB |
842 | |
843 | this_err = abs(clock.dot - target); | |
844 | if (this_err < err) { | |
845 | *best_clock = clock; | |
846 | err = this_err; | |
847 | } | |
848 | } | |
849 | } | |
850 | } | |
851 | } | |
852 | ||
853 | return (err != target); | |
854 | } | |
855 | ||
d4906093 | 856 | static bool |
a93e255f ACO |
857 | g4x_find_best_dpll(const intel_limit_t *limit, |
858 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
859 | int target, int refclk, intel_clock_t *match_clock, |
860 | intel_clock_t *best_clock) | |
d4906093 | 861 | { |
3b1429d9 | 862 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
863 | intel_clock_t clock; |
864 | int max_n; | |
3b1429d9 | 865 | bool found = false; |
6ba770dc AJ |
866 | /* approximately equals target * 0.00585 */ |
867 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
868 | |
869 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
870 | |
871 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
872 | ||
d4906093 | 873 | max_n = limit->n.max; |
f77f13e2 | 874 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 875 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 876 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
877 | for (clock.m1 = limit->m1.max; |
878 | clock.m1 >= limit->m1.min; clock.m1--) { | |
879 | for (clock.m2 = limit->m2.max; | |
880 | clock.m2 >= limit->m2.min; clock.m2--) { | |
881 | for (clock.p1 = limit->p1.max; | |
882 | clock.p1 >= limit->p1.min; clock.p1--) { | |
883 | int this_err; | |
884 | ||
dccbea3b | 885 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
886 | if (!intel_PLL_is_valid(dev, limit, |
887 | &clock)) | |
d4906093 | 888 | continue; |
1b894b59 CW |
889 | |
890 | this_err = abs(clock.dot - target); | |
d4906093 ML |
891 | if (this_err < err_most) { |
892 | *best_clock = clock; | |
893 | err_most = this_err; | |
894 | max_n = clock.n; | |
895 | found = true; | |
896 | } | |
897 | } | |
898 | } | |
899 | } | |
900 | } | |
2c07245f ZW |
901 | return found; |
902 | } | |
903 | ||
d5dd62bd ID |
904 | /* |
905 | * Check if the calculated PLL configuration is more optimal compared to the | |
906 | * best configuration and error found so far. Return the calculated error. | |
907 | */ | |
908 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
909 | const intel_clock_t *calculated_clock, | |
910 | const intel_clock_t *best_clock, | |
911 | unsigned int best_error_ppm, | |
912 | unsigned int *error_ppm) | |
913 | { | |
9ca3ba01 ID |
914 | /* |
915 | * For CHV ignore the error and consider only the P value. | |
916 | * Prefer a bigger P value based on HW requirements. | |
917 | */ | |
918 | if (IS_CHERRYVIEW(dev)) { | |
919 | *error_ppm = 0; | |
920 | ||
921 | return calculated_clock->p > best_clock->p; | |
922 | } | |
923 | ||
24be4e46 ID |
924 | if (WARN_ON_ONCE(!target_freq)) |
925 | return false; | |
926 | ||
d5dd62bd ID |
927 | *error_ppm = div_u64(1000000ULL * |
928 | abs(target_freq - calculated_clock->dot), | |
929 | target_freq); | |
930 | /* | |
931 | * Prefer a better P value over a better (smaller) error if the error | |
932 | * is small. Ensure this preference for future configurations too by | |
933 | * setting the error to 0. | |
934 | */ | |
935 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
936 | *error_ppm = 0; | |
937 | ||
938 | return true; | |
939 | } | |
940 | ||
941 | return *error_ppm + 10 < best_error_ppm; | |
942 | } | |
943 | ||
a0c4da24 | 944 | static bool |
a93e255f ACO |
945 | vlv_find_best_dpll(const intel_limit_t *limit, |
946 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
947 | int target, int refclk, intel_clock_t *match_clock, |
948 | intel_clock_t *best_clock) | |
a0c4da24 | 949 | { |
a93e255f | 950 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 951 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 952 | intel_clock_t clock; |
69e4f900 | 953 | unsigned int bestppm = 1000000; |
27e639bf VS |
954 | /* min update 19.2 MHz */ |
955 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 956 | bool found = false; |
a0c4da24 | 957 | |
6b4bf1c4 VS |
958 | target *= 5; /* fast clock */ |
959 | ||
960 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
961 | |
962 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 963 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 964 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 965 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 966 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 967 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 968 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 969 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 970 | unsigned int ppm; |
69e4f900 | 971 | |
6b4bf1c4 VS |
972 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
973 | refclk * clock.m1); | |
974 | ||
dccbea3b | 975 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 976 | |
f01b7962 VS |
977 | if (!intel_PLL_is_valid(dev, limit, |
978 | &clock)) | |
43b0ac53 VS |
979 | continue; |
980 | ||
d5dd62bd ID |
981 | if (!vlv_PLL_is_optimal(dev, target, |
982 | &clock, | |
983 | best_clock, | |
984 | bestppm, &ppm)) | |
985 | continue; | |
6b4bf1c4 | 986 | |
d5dd62bd ID |
987 | *best_clock = clock; |
988 | bestppm = ppm; | |
989 | found = true; | |
a0c4da24 JB |
990 | } |
991 | } | |
992 | } | |
993 | } | |
a0c4da24 | 994 | |
49e497ef | 995 | return found; |
a0c4da24 | 996 | } |
a4fc5ed6 | 997 | |
ef9348c8 | 998 | static bool |
a93e255f ACO |
999 | chv_find_best_dpll(const intel_limit_t *limit, |
1000 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1001 | int target, int refclk, intel_clock_t *match_clock, |
1002 | intel_clock_t *best_clock) | |
1003 | { | |
a93e255f | 1004 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1005 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1006 | unsigned int best_error_ppm; |
ef9348c8 CML |
1007 | intel_clock_t clock; |
1008 | uint64_t m2; | |
1009 | int found = false; | |
1010 | ||
1011 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1012 | best_error_ppm = 1000000; |
ef9348c8 CML |
1013 | |
1014 | /* | |
1015 | * Based on hardware doc, the n always set to 1, and m1 always | |
1016 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1017 | * revisit this because n may not 1 anymore. | |
1018 | */ | |
1019 | clock.n = 1, clock.m1 = 2; | |
1020 | target *= 5; /* fast clock */ | |
1021 | ||
1022 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1023 | for (clock.p2 = limit->p2.p2_fast; | |
1024 | clock.p2 >= limit->p2.p2_slow; | |
1025 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1026 | unsigned int error_ppm; |
ef9348c8 CML |
1027 | |
1028 | clock.p = clock.p1 * clock.p2; | |
1029 | ||
1030 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1031 | clock.n) << 22, refclk * clock.m1); | |
1032 | ||
1033 | if (m2 > INT_MAX/clock.m1) | |
1034 | continue; | |
1035 | ||
1036 | clock.m2 = m2; | |
1037 | ||
dccbea3b | 1038 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1039 | |
1040 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1041 | continue; | |
1042 | ||
9ca3ba01 ID |
1043 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1044 | best_error_ppm, &error_ppm)) | |
1045 | continue; | |
1046 | ||
1047 | *best_clock = clock; | |
1048 | best_error_ppm = error_ppm; | |
1049 | found = true; | |
ef9348c8 CML |
1050 | } |
1051 | } | |
1052 | ||
1053 | return found; | |
1054 | } | |
1055 | ||
5ab7b0b7 ID |
1056 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1057 | intel_clock_t *best_clock) | |
1058 | { | |
1059 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1060 | ||
1061 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1062 | target_clock, refclk, NULL, best_clock); | |
1063 | } | |
1064 | ||
20ddf665 VS |
1065 | bool intel_crtc_active(struct drm_crtc *crtc) |
1066 | { | |
1067 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1068 | ||
1069 | /* Be paranoid as we can arrive here with only partial | |
1070 | * state retrieved from the hardware during setup. | |
1071 | * | |
241bfc38 | 1072 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1073 | * as Haswell has gained clock readout/fastboot support. |
1074 | * | |
66e514c1 | 1075 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1076 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1077 | * |
1078 | * FIXME: The intel_crtc->active here should be switched to | |
1079 | * crtc->state->active once we have proper CRTC states wired up | |
1080 | * for atomic. | |
20ddf665 | 1081 | */ |
c3d1f436 | 1082 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1083 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1084 | } |
1085 | ||
a5c961d1 PZ |
1086 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1087 | enum pipe pipe) | |
1088 | { | |
1089 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1090 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1091 | ||
6e3c9717 | 1092 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1093 | } |
1094 | ||
fbf49ea2 VS |
1095 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1096 | { | |
1097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1098 | u32 reg = PIPEDSL(pipe); | |
1099 | u32 line1, line2; | |
1100 | u32 line_mask; | |
1101 | ||
1102 | if (IS_GEN2(dev)) | |
1103 | line_mask = DSL_LINEMASK_GEN2; | |
1104 | else | |
1105 | line_mask = DSL_LINEMASK_GEN3; | |
1106 | ||
1107 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1108 | msleep(5); |
fbf49ea2 VS |
1109 | line2 = I915_READ(reg) & line_mask; |
1110 | ||
1111 | return line1 == line2; | |
1112 | } | |
1113 | ||
ab7ad7f6 KP |
1114 | /* |
1115 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1116 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1117 | * |
1118 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1119 | * spinning on the vblank interrupt status bit, since we won't actually | |
1120 | * see an interrupt when the pipe is disabled. | |
1121 | * | |
ab7ad7f6 KP |
1122 | * On Gen4 and above: |
1123 | * wait for the pipe register state bit to turn off | |
1124 | * | |
1125 | * Otherwise: | |
1126 | * wait for the display line value to settle (it usually | |
1127 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1128 | * |
9d0498a2 | 1129 | */ |
575f7ab7 | 1130 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1131 | { |
575f7ab7 | 1132 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1133 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1134 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1135 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1136 | |
1137 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1138 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1139 | |
1140 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1141 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1142 | 100)) | |
284637d9 | 1143 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1144 | } else { |
ab7ad7f6 | 1145 | /* Wait for the display line to settle */ |
fbf49ea2 | 1146 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1147 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1148 | } |
79e53945 JB |
1149 | } |
1150 | ||
b24e7179 JB |
1151 | static const char *state_string(bool enabled) |
1152 | { | |
1153 | return enabled ? "on" : "off"; | |
1154 | } | |
1155 | ||
1156 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1157 | void assert_pll(struct drm_i915_private *dev_priv, |
1158 | enum pipe pipe, bool state) | |
b24e7179 JB |
1159 | { |
1160 | int reg; | |
1161 | u32 val; | |
1162 | bool cur_state; | |
1163 | ||
1164 | reg = DPLL(pipe); | |
1165 | val = I915_READ(reg); | |
1166 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1167 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1168 | "PLL state assertion failure (expected %s, current %s)\n", |
1169 | state_string(state), state_string(cur_state)); | |
1170 | } | |
b24e7179 | 1171 | |
23538ef1 JN |
1172 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1173 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1174 | { | |
1175 | u32 val; | |
1176 | bool cur_state; | |
1177 | ||
a580516d | 1178 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1179 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1180 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1181 | |
1182 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1183 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1184 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1185 | state_string(state), state_string(cur_state)); | |
1186 | } | |
1187 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1188 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1189 | ||
55607e8a | 1190 | struct intel_shared_dpll * |
e2b78267 DV |
1191 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1192 | { | |
1193 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1194 | ||
6e3c9717 | 1195 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1196 | return NULL; |
1197 | ||
6e3c9717 | 1198 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1199 | } |
1200 | ||
040484af | 1201 | /* For ILK+ */ |
55607e8a DV |
1202 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1203 | struct intel_shared_dpll *pll, | |
1204 | bool state) | |
040484af | 1205 | { |
040484af | 1206 | bool cur_state; |
5358901f | 1207 | struct intel_dpll_hw_state hw_state; |
040484af | 1208 | |
92b27b08 | 1209 | if (WARN (!pll, |
46edb027 | 1210 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1211 | return; |
ee7b9f93 | 1212 | |
5358901f | 1213 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1214 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1215 | "%s assertion failure (expected %s, current %s)\n", |
1216 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1217 | } |
040484af JB |
1218 | |
1219 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1220 | enum pipe pipe, bool state) | |
1221 | { | |
1222 | int reg; | |
1223 | u32 val; | |
1224 | bool cur_state; | |
ad80a810 PZ |
1225 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1226 | pipe); | |
040484af | 1227 | |
affa9354 PZ |
1228 | if (HAS_DDI(dev_priv->dev)) { |
1229 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1230 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1231 | val = I915_READ(reg); |
ad80a810 | 1232 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1233 | } else { |
1234 | reg = FDI_TX_CTL(pipe); | |
1235 | val = I915_READ(reg); | |
1236 | cur_state = !!(val & FDI_TX_ENABLE); | |
1237 | } | |
e2c719b7 | 1238 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1239 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1240 | state_string(state), state_string(cur_state)); | |
1241 | } | |
1242 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1243 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1244 | ||
1245 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1246 | enum pipe pipe, bool state) | |
1247 | { | |
1248 | int reg; | |
1249 | u32 val; | |
1250 | bool cur_state; | |
1251 | ||
d63fa0dc PZ |
1252 | reg = FDI_RX_CTL(pipe); |
1253 | val = I915_READ(reg); | |
1254 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1255 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1256 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1257 | state_string(state), state_string(cur_state)); | |
1258 | } | |
1259 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1260 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1261 | ||
1262 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1263 | enum pipe pipe) | |
1264 | { | |
1265 | int reg; | |
1266 | u32 val; | |
1267 | ||
1268 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1269 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1270 | return; |
1271 | ||
bf507ef7 | 1272 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1273 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1274 | return; |
1275 | ||
040484af JB |
1276 | reg = FDI_TX_CTL(pipe); |
1277 | val = I915_READ(reg); | |
e2c719b7 | 1278 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1279 | } |
1280 | ||
55607e8a DV |
1281 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1282 | enum pipe pipe, bool state) | |
040484af JB |
1283 | { |
1284 | int reg; | |
1285 | u32 val; | |
55607e8a | 1286 | bool cur_state; |
040484af JB |
1287 | |
1288 | reg = FDI_RX_CTL(pipe); | |
1289 | val = I915_READ(reg); | |
55607e8a | 1290 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1291 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1292 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1293 | state_string(state), state_string(cur_state)); | |
040484af JB |
1294 | } |
1295 | ||
b680c37a DV |
1296 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1297 | enum pipe pipe) | |
ea0760cf | 1298 | { |
bedd4dba JN |
1299 | struct drm_device *dev = dev_priv->dev; |
1300 | int pp_reg; | |
ea0760cf JB |
1301 | u32 val; |
1302 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1303 | bool locked = true; |
ea0760cf | 1304 | |
bedd4dba JN |
1305 | if (WARN_ON(HAS_DDI(dev))) |
1306 | return; | |
1307 | ||
1308 | if (HAS_PCH_SPLIT(dev)) { | |
1309 | u32 port_sel; | |
1310 | ||
ea0760cf | 1311 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1312 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1313 | ||
1314 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1315 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1316 | panel_pipe = PIPE_B; | |
1317 | /* XXX: else fix for eDP */ | |
1318 | } else if (IS_VALLEYVIEW(dev)) { | |
1319 | /* presumably write lock depends on pipe, not port select */ | |
1320 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1321 | panel_pipe = pipe; | |
ea0760cf JB |
1322 | } else { |
1323 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1324 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1325 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1326 | } |
1327 | ||
1328 | val = I915_READ(pp_reg); | |
1329 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1330 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1331 | locked = false; |
1332 | ||
e2c719b7 | 1333 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1334 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1335 | pipe_name(pipe)); |
ea0760cf JB |
1336 | } |
1337 | ||
93ce0ba6 JN |
1338 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1339 | enum pipe pipe, bool state) | |
1340 | { | |
1341 | struct drm_device *dev = dev_priv->dev; | |
1342 | bool cur_state; | |
1343 | ||
d9d82081 | 1344 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1345 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1346 | else |
5efb3e28 | 1347 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1348 | |
e2c719b7 | 1349 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1350 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1351 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1352 | } | |
1353 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1354 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1355 | ||
b840d907 JB |
1356 | void assert_pipe(struct drm_i915_private *dev_priv, |
1357 | enum pipe pipe, bool state) | |
b24e7179 JB |
1358 | { |
1359 | int reg; | |
1360 | u32 val; | |
63d7bbe9 | 1361 | bool cur_state; |
702e7a56 PZ |
1362 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1363 | pipe); | |
b24e7179 | 1364 | |
b6b5d049 VS |
1365 | /* if we need the pipe quirk it must be always on */ |
1366 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1367 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1368 | state = true; |
1369 | ||
f458ebbc | 1370 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1371 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1372 | cur_state = false; |
1373 | } else { | |
1374 | reg = PIPECONF(cpu_transcoder); | |
1375 | val = I915_READ(reg); | |
1376 | cur_state = !!(val & PIPECONF_ENABLE); | |
1377 | } | |
1378 | ||
e2c719b7 | 1379 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1380 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1381 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1382 | } |
1383 | ||
931872fc CW |
1384 | static void assert_plane(struct drm_i915_private *dev_priv, |
1385 | enum plane plane, bool state) | |
b24e7179 JB |
1386 | { |
1387 | int reg; | |
1388 | u32 val; | |
931872fc | 1389 | bool cur_state; |
b24e7179 JB |
1390 | |
1391 | reg = DSPCNTR(plane); | |
1392 | val = I915_READ(reg); | |
931872fc | 1393 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1394 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1395 | "plane %c assertion failure (expected %s, current %s)\n", |
1396 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1397 | } |
1398 | ||
931872fc CW |
1399 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1400 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1401 | ||
b24e7179 JB |
1402 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1403 | enum pipe pipe) | |
1404 | { | |
653e1026 | 1405 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1406 | int reg, i; |
1407 | u32 val; | |
1408 | int cur_pipe; | |
1409 | ||
653e1026 VS |
1410 | /* Primary planes are fixed to pipes on gen4+ */ |
1411 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1412 | reg = DSPCNTR(pipe); |
1413 | val = I915_READ(reg); | |
e2c719b7 | 1414 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1415 | "plane %c assertion failure, should be disabled but not\n", |
1416 | plane_name(pipe)); | |
19ec1358 | 1417 | return; |
28c05794 | 1418 | } |
19ec1358 | 1419 | |
b24e7179 | 1420 | /* Need to check both planes against the pipe */ |
055e393f | 1421 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1422 | reg = DSPCNTR(i); |
1423 | val = I915_READ(reg); | |
1424 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1425 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1426 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1427 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1428 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1429 | } |
1430 | } | |
1431 | ||
19332d7a JB |
1432 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1433 | enum pipe pipe) | |
1434 | { | |
20674eef | 1435 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1436 | int reg, sprite; |
19332d7a JB |
1437 | u32 val; |
1438 | ||
7feb8b88 | 1439 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1440 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1441 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1442 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1443 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1444 | sprite, pipe_name(pipe)); | |
1445 | } | |
1446 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1447 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1448 | reg = SPCNTR(pipe, sprite); |
20674eef | 1449 | val = I915_READ(reg); |
e2c719b7 | 1450 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1451 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1452 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1453 | } |
1454 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1455 | reg = SPRCTL(pipe); | |
19332d7a | 1456 | val = I915_READ(reg); |
e2c719b7 | 1457 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1458 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1459 | plane_name(pipe), pipe_name(pipe)); |
1460 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1461 | reg = DVSCNTR(pipe); | |
19332d7a | 1462 | val = I915_READ(reg); |
e2c719b7 | 1463 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1464 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1465 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1466 | } |
1467 | } | |
1468 | ||
08c71e5e VS |
1469 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1470 | { | |
e2c719b7 | 1471 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1472 | drm_crtc_vblank_put(crtc); |
1473 | } | |
1474 | ||
89eff4be | 1475 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1476 | { |
1477 | u32 val; | |
1478 | bool enabled; | |
1479 | ||
e2c719b7 | 1480 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1481 | |
92f2584a JB |
1482 | val = I915_READ(PCH_DREF_CONTROL); |
1483 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1484 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1485 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1486 | } |
1487 | ||
ab9412ba DV |
1488 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1489 | enum pipe pipe) | |
92f2584a JB |
1490 | { |
1491 | int reg; | |
1492 | u32 val; | |
1493 | bool enabled; | |
1494 | ||
ab9412ba | 1495 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1496 | val = I915_READ(reg); |
1497 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1498 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1499 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1500 | pipe_name(pipe)); | |
92f2584a JB |
1501 | } |
1502 | ||
4e634389 KP |
1503 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1504 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1505 | { |
1506 | if ((val & DP_PORT_EN) == 0) | |
1507 | return false; | |
1508 | ||
1509 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1510 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1511 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1512 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1513 | return false; | |
44f37d1f CML |
1514 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1515 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1516 | return false; | |
f0575e92 KP |
1517 | } else { |
1518 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1519 | return false; | |
1520 | } | |
1521 | return true; | |
1522 | } | |
1523 | ||
1519b995 KP |
1524 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1525 | enum pipe pipe, u32 val) | |
1526 | { | |
dc0fa718 | 1527 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1528 | return false; |
1529 | ||
1530 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1531 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1532 | return false; |
44f37d1f CML |
1533 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1534 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1535 | return false; | |
1519b995 | 1536 | } else { |
dc0fa718 | 1537 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1538 | return false; |
1539 | } | |
1540 | return true; | |
1541 | } | |
1542 | ||
1543 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1544 | enum pipe pipe, u32 val) | |
1545 | { | |
1546 | if ((val & LVDS_PORT_EN) == 0) | |
1547 | return false; | |
1548 | ||
1549 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1550 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1551 | return false; | |
1552 | } else { | |
1553 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1554 | return false; | |
1555 | } | |
1556 | return true; | |
1557 | } | |
1558 | ||
1559 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1560 | enum pipe pipe, u32 val) | |
1561 | { | |
1562 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1563 | return false; | |
1564 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1565 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1566 | return false; | |
1567 | } else { | |
1568 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1569 | return false; | |
1570 | } | |
1571 | return true; | |
1572 | } | |
1573 | ||
291906f1 | 1574 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1575 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1576 | { |
47a05eca | 1577 | u32 val = I915_READ(reg); |
e2c719b7 | 1578 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1579 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1580 | reg, pipe_name(pipe)); |
de9a35ab | 1581 | |
e2c719b7 | 1582 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1583 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1584 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1585 | } |
1586 | ||
1587 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1588 | enum pipe pipe, int reg) | |
1589 | { | |
47a05eca | 1590 | u32 val = I915_READ(reg); |
e2c719b7 | 1591 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1592 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1593 | reg, pipe_name(pipe)); |
de9a35ab | 1594 | |
e2c719b7 | 1595 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1596 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1597 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1598 | } |
1599 | ||
1600 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1601 | enum pipe pipe) | |
1602 | { | |
1603 | int reg; | |
1604 | u32 val; | |
291906f1 | 1605 | |
f0575e92 KP |
1606 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1607 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1608 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1609 | |
1610 | reg = PCH_ADPA; | |
1611 | val = I915_READ(reg); | |
e2c719b7 | 1612 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1613 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1614 | pipe_name(pipe)); |
291906f1 JB |
1615 | |
1616 | reg = PCH_LVDS; | |
1617 | val = I915_READ(reg); | |
e2c719b7 | 1618 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1619 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1620 | pipe_name(pipe)); |
291906f1 | 1621 | |
e2debe91 PZ |
1622 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1623 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1624 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1625 | } |
1626 | ||
d288f65f | 1627 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1628 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1629 | { |
426115cf DV |
1630 | struct drm_device *dev = crtc->base.dev; |
1631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1632 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1633 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1634 | |
426115cf | 1635 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1636 | |
1637 | /* No really, not for ILK+ */ | |
1638 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1639 | ||
1640 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1641 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1642 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1643 | |
426115cf DV |
1644 | I915_WRITE(reg, dpll); |
1645 | POSTING_READ(reg); | |
1646 | udelay(150); | |
1647 | ||
1648 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1649 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1650 | ||
d288f65f | 1651 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1652 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1653 | |
1654 | /* We do this three times for luck */ | |
426115cf | 1655 | I915_WRITE(reg, dpll); |
87442f73 DV |
1656 | POSTING_READ(reg); |
1657 | udelay(150); /* wait for warmup */ | |
426115cf | 1658 | I915_WRITE(reg, dpll); |
87442f73 DV |
1659 | POSTING_READ(reg); |
1660 | udelay(150); /* wait for warmup */ | |
426115cf | 1661 | I915_WRITE(reg, dpll); |
87442f73 DV |
1662 | POSTING_READ(reg); |
1663 | udelay(150); /* wait for warmup */ | |
1664 | } | |
1665 | ||
d288f65f | 1666 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1667 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1668 | { |
1669 | struct drm_device *dev = crtc->base.dev; | |
1670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1671 | int pipe = crtc->pipe; | |
1672 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1673 | u32 tmp; |
1674 | ||
1675 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1676 | ||
1677 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1678 | ||
a580516d | 1679 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1680 | |
1681 | /* Enable back the 10bit clock to display controller */ | |
1682 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1683 | tmp |= DPIO_DCLKP_EN; | |
1684 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1685 | ||
54433e91 VS |
1686 | mutex_unlock(&dev_priv->sb_lock); |
1687 | ||
9d556c99 CML |
1688 | /* |
1689 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1690 | */ | |
1691 | udelay(1); | |
1692 | ||
1693 | /* Enable PLL */ | |
d288f65f | 1694 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1695 | |
1696 | /* Check PLL is locked */ | |
a11b0703 | 1697 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1698 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1699 | ||
a11b0703 | 1700 | /* not sure when this should be written */ |
d288f65f | 1701 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1702 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1703 | } |
1704 | ||
1c4e0274 VS |
1705 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1706 | { | |
1707 | struct intel_crtc *crtc; | |
1708 | int count = 0; | |
1709 | ||
1710 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1711 | count += crtc->base.state->active && |
409ee761 | 1712 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1713 | |
1714 | return count; | |
1715 | } | |
1716 | ||
66e3d5c0 | 1717 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1718 | { |
66e3d5c0 DV |
1719 | struct drm_device *dev = crtc->base.dev; |
1720 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1721 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1722 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1723 | |
66e3d5c0 | 1724 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1725 | |
63d7bbe9 | 1726 | /* No really, not for ILK+ */ |
3d13ef2e | 1727 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1728 | |
1729 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1730 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1731 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1732 | |
1c4e0274 VS |
1733 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1734 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1735 | /* | |
1736 | * It appears to be important that we don't enable this | |
1737 | * for the current pipe before otherwise configuring the | |
1738 | * PLL. No idea how this should be handled if multiple | |
1739 | * DVO outputs are enabled simultaneosly. | |
1740 | */ | |
1741 | dpll |= DPLL_DVO_2X_MODE; | |
1742 | I915_WRITE(DPLL(!crtc->pipe), | |
1743 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1744 | } | |
66e3d5c0 DV |
1745 | |
1746 | /* Wait for the clocks to stabilize. */ | |
1747 | POSTING_READ(reg); | |
1748 | udelay(150); | |
1749 | ||
1750 | if (INTEL_INFO(dev)->gen >= 4) { | |
1751 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1752 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1753 | } else { |
1754 | /* The pixel multiplier can only be updated once the | |
1755 | * DPLL is enabled and the clocks are stable. | |
1756 | * | |
1757 | * So write it again. | |
1758 | */ | |
1759 | I915_WRITE(reg, dpll); | |
1760 | } | |
63d7bbe9 JB |
1761 | |
1762 | /* We do this three times for luck */ | |
66e3d5c0 | 1763 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1764 | POSTING_READ(reg); |
1765 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1766 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1767 | POSTING_READ(reg); |
1768 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1769 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1770 | POSTING_READ(reg); |
1771 | udelay(150); /* wait for warmup */ | |
1772 | } | |
1773 | ||
1774 | /** | |
50b44a44 | 1775 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1776 | * @dev_priv: i915 private structure |
1777 | * @pipe: pipe PLL to disable | |
1778 | * | |
1779 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1780 | * | |
1781 | * Note! This is for pre-ILK only. | |
1782 | */ | |
1c4e0274 | 1783 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1784 | { |
1c4e0274 VS |
1785 | struct drm_device *dev = crtc->base.dev; |
1786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1787 | enum pipe pipe = crtc->pipe; | |
1788 | ||
1789 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1790 | if (IS_I830(dev) && | |
409ee761 | 1791 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1792 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1793 | I915_WRITE(DPLL(PIPE_B), |
1794 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1795 | I915_WRITE(DPLL(PIPE_A), | |
1796 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1797 | } | |
1798 | ||
b6b5d049 VS |
1799 | /* Don't disable pipe or pipe PLLs if needed */ |
1800 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1801 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1802 | return; |
1803 | ||
1804 | /* Make sure the pipe isn't still relying on us */ | |
1805 | assert_pipe_disabled(dev_priv, pipe); | |
1806 | ||
b8afb911 | 1807 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1808 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1809 | } |
1810 | ||
f6071166 JB |
1811 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1812 | { | |
b8afb911 | 1813 | u32 val; |
f6071166 JB |
1814 | |
1815 | /* Make sure the pipe isn't still relying on us */ | |
1816 | assert_pipe_disabled(dev_priv, pipe); | |
1817 | ||
e5cbfbfb ID |
1818 | /* |
1819 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1820 | * The latter is needed for VGA hotplug / manual detection. | |
1821 | */ | |
b8afb911 | 1822 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1823 | if (pipe == PIPE_B) |
60bfe44f | 1824 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1825 | I915_WRITE(DPLL(pipe), val); |
1826 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1827 | |
1828 | } | |
1829 | ||
1830 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1831 | { | |
d752048d | 1832 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1833 | u32 val; |
1834 | ||
a11b0703 VS |
1835 | /* Make sure the pipe isn't still relying on us */ |
1836 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1837 | |
a11b0703 | 1838 | /* Set PLL en = 0 */ |
60bfe44f VS |
1839 | val = DPLL_SSC_REF_CLK_CHV | |
1840 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1841 | if (pipe != PIPE_A) |
1842 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1843 | I915_WRITE(DPLL(pipe), val); | |
1844 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1845 | |
a580516d | 1846 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1847 | |
1848 | /* Disable 10bit clock to display controller */ | |
1849 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1850 | val &= ~DPIO_DCLKP_EN; | |
1851 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1852 | ||
a580516d | 1853 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1854 | } |
1855 | ||
e4607fcf | 1856 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1857 | struct intel_digital_port *dport, |
1858 | unsigned int expected_mask) | |
89b667f8 JB |
1859 | { |
1860 | u32 port_mask; | |
00fc31b7 | 1861 | int dpll_reg; |
89b667f8 | 1862 | |
e4607fcf CML |
1863 | switch (dport->port) { |
1864 | case PORT_B: | |
89b667f8 | 1865 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1866 | dpll_reg = DPLL(0); |
e4607fcf CML |
1867 | break; |
1868 | case PORT_C: | |
89b667f8 | 1869 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1870 | dpll_reg = DPLL(0); |
9b6de0a1 | 1871 | expected_mask <<= 4; |
00fc31b7 CML |
1872 | break; |
1873 | case PORT_D: | |
1874 | port_mask = DPLL_PORTD_READY_MASK; | |
1875 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1876 | break; |
1877 | default: | |
1878 | BUG(); | |
1879 | } | |
89b667f8 | 1880 | |
9b6de0a1 VS |
1881 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1882 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1883 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1884 | } |
1885 | ||
b14b1055 DV |
1886 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1887 | { | |
1888 | struct drm_device *dev = crtc->base.dev; | |
1889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1890 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1891 | ||
be19f0ff CW |
1892 | if (WARN_ON(pll == NULL)) |
1893 | return; | |
1894 | ||
3e369b76 | 1895 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1896 | if (pll->active == 0) { |
1897 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1898 | WARN_ON(pll->on); | |
1899 | assert_shared_dpll_disabled(dev_priv, pll); | |
1900 | ||
1901 | pll->mode_set(dev_priv, pll); | |
1902 | } | |
1903 | } | |
1904 | ||
92f2584a | 1905 | /** |
85b3894f | 1906 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1907 | * @dev_priv: i915 private structure |
1908 | * @pipe: pipe PLL to enable | |
1909 | * | |
1910 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1911 | * drives the transcoder clock. | |
1912 | */ | |
85b3894f | 1913 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1914 | { |
3d13ef2e DL |
1915 | struct drm_device *dev = crtc->base.dev; |
1916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1917 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1918 | |
87a875bb | 1919 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1920 | return; |
1921 | ||
3e369b76 | 1922 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1923 | return; |
ee7b9f93 | 1924 | |
74dd6928 | 1925 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1926 | pll->name, pll->active, pll->on, |
e2b78267 | 1927 | crtc->base.base.id); |
92f2584a | 1928 | |
cdbd2316 DV |
1929 | if (pll->active++) { |
1930 | WARN_ON(!pll->on); | |
e9d6944e | 1931 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1932 | return; |
1933 | } | |
f4a091c7 | 1934 | WARN_ON(pll->on); |
ee7b9f93 | 1935 | |
bd2bb1b9 PZ |
1936 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1937 | ||
46edb027 | 1938 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1939 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1940 | pll->on = true; |
92f2584a JB |
1941 | } |
1942 | ||
f6daaec2 | 1943 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1944 | { |
3d13ef2e DL |
1945 | struct drm_device *dev = crtc->base.dev; |
1946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1947 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1948 | |
92f2584a | 1949 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1950 | if (INTEL_INFO(dev)->gen < 5) |
1951 | return; | |
1952 | ||
eddfcbcd ML |
1953 | if (pll == NULL) |
1954 | return; | |
92f2584a | 1955 | |
eddfcbcd | 1956 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1957 | return; |
7a419866 | 1958 | |
46edb027 DV |
1959 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1960 | pll->name, pll->active, pll->on, | |
e2b78267 | 1961 | crtc->base.base.id); |
7a419866 | 1962 | |
48da64a8 | 1963 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1964 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1965 | return; |
1966 | } | |
1967 | ||
e9d6944e | 1968 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1969 | WARN_ON(!pll->on); |
cdbd2316 | 1970 | if (--pll->active) |
7a419866 | 1971 | return; |
ee7b9f93 | 1972 | |
46edb027 | 1973 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1974 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1975 | pll->on = false; |
bd2bb1b9 PZ |
1976 | |
1977 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1978 | } |
1979 | ||
b8a4f404 PZ |
1980 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1981 | enum pipe pipe) | |
040484af | 1982 | { |
23670b32 | 1983 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1984 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1985 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1986 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1987 | |
1988 | /* PCH only available on ILK+ */ | |
55522f37 | 1989 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1990 | |
1991 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1992 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1993 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1994 | |
1995 | /* FDI must be feeding us bits for PCH ports */ | |
1996 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1997 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1998 | ||
23670b32 DV |
1999 | if (HAS_PCH_CPT(dev)) { |
2000 | /* Workaround: Set the timing override bit before enabling the | |
2001 | * pch transcoder. */ | |
2002 | reg = TRANS_CHICKEN2(pipe); | |
2003 | val = I915_READ(reg); | |
2004 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2005 | I915_WRITE(reg, val); | |
59c859d6 | 2006 | } |
23670b32 | 2007 | |
ab9412ba | 2008 | reg = PCH_TRANSCONF(pipe); |
040484af | 2009 | val = I915_READ(reg); |
5f7f726d | 2010 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
2011 | |
2012 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
2013 | /* | |
c5de7c6f VS |
2014 | * Make the BPC in transcoder be consistent with |
2015 | * that in pipeconf reg. For HDMI we must use 8bpc | |
2016 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 2017 | */ |
dfd07d72 | 2018 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
2019 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
2020 | val |= PIPECONF_8BPC; | |
2021 | else | |
2022 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2023 | } |
5f7f726d PZ |
2024 | |
2025 | val &= ~TRANS_INTERLACE_MASK; | |
2026 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2027 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2028 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2029 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2030 | else | |
2031 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2032 | else |
2033 | val |= TRANS_PROGRESSIVE; | |
2034 | ||
040484af JB |
2035 | I915_WRITE(reg, val | TRANS_ENABLE); |
2036 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2037 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2038 | } |
2039 | ||
8fb033d7 | 2040 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2041 | enum transcoder cpu_transcoder) |
040484af | 2042 | { |
8fb033d7 | 2043 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2044 | |
2045 | /* PCH only available on ILK+ */ | |
55522f37 | 2046 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2047 | |
8fb033d7 | 2048 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2049 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2050 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2051 | |
223a6fdf | 2052 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2053 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2054 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2055 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2056 | |
25f3ef11 | 2057 | val = TRANS_ENABLE; |
937bb610 | 2058 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2059 | |
9a76b1c6 PZ |
2060 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2061 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2062 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2063 | else |
2064 | val |= TRANS_PROGRESSIVE; | |
2065 | ||
ab9412ba DV |
2066 | I915_WRITE(LPT_TRANSCONF, val); |
2067 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2068 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2069 | } |
2070 | ||
b8a4f404 PZ |
2071 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2072 | enum pipe pipe) | |
040484af | 2073 | { |
23670b32 DV |
2074 | struct drm_device *dev = dev_priv->dev; |
2075 | uint32_t reg, val; | |
040484af JB |
2076 | |
2077 | /* FDI relies on the transcoder */ | |
2078 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2079 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2080 | ||
291906f1 JB |
2081 | /* Ports must be off as well */ |
2082 | assert_pch_ports_disabled(dev_priv, pipe); | |
2083 | ||
ab9412ba | 2084 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2085 | val = I915_READ(reg); |
2086 | val &= ~TRANS_ENABLE; | |
2087 | I915_WRITE(reg, val); | |
2088 | /* wait for PCH transcoder off, transcoder state */ | |
2089 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2090 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2091 | |
2092 | if (!HAS_PCH_IBX(dev)) { | |
2093 | /* Workaround: Clear the timing override chicken bit again. */ | |
2094 | reg = TRANS_CHICKEN2(pipe); | |
2095 | val = I915_READ(reg); | |
2096 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2097 | I915_WRITE(reg, val); | |
2098 | } | |
040484af JB |
2099 | } |
2100 | ||
ab4d966c | 2101 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2102 | { |
8fb033d7 PZ |
2103 | u32 val; |
2104 | ||
ab9412ba | 2105 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2106 | val &= ~TRANS_ENABLE; |
ab9412ba | 2107 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2108 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2109 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2110 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2111 | |
2112 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2113 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2114 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2115 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2116 | } |
2117 | ||
b24e7179 | 2118 | /** |
309cfea8 | 2119 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2120 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2121 | * |
0372264a | 2122 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2123 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2124 | */ |
e1fdc473 | 2125 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2126 | { |
0372264a PZ |
2127 | struct drm_device *dev = crtc->base.dev; |
2128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2129 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2130 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2131 | pipe); | |
1a240d4d | 2132 | enum pipe pch_transcoder; |
b24e7179 JB |
2133 | int reg; |
2134 | u32 val; | |
2135 | ||
9e2ee2dd VS |
2136 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2137 | ||
58c6eaa2 | 2138 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2139 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2140 | assert_sprites_disabled(dev_priv, pipe); |
2141 | ||
681e5811 | 2142 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2143 | pch_transcoder = TRANSCODER_A; |
2144 | else | |
2145 | pch_transcoder = pipe; | |
2146 | ||
b24e7179 JB |
2147 | /* |
2148 | * A pipe without a PLL won't actually be able to drive bits from | |
2149 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2150 | * need the check. | |
2151 | */ | |
50360403 | 2152 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
409ee761 | 2153 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2154 | assert_dsi_pll_enabled(dev_priv); |
2155 | else | |
2156 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2157 | else { |
6e3c9717 | 2158 | if (crtc->config->has_pch_encoder) { |
040484af | 2159 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2160 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2161 | assert_fdi_tx_pll_enabled(dev_priv, |
2162 | (enum pipe) cpu_transcoder); | |
040484af JB |
2163 | } |
2164 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2165 | } | |
b24e7179 | 2166 | |
702e7a56 | 2167 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2168 | val = I915_READ(reg); |
7ad25d48 | 2169 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2170 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2171 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2172 | return; |
7ad25d48 | 2173 | } |
00d70b15 CW |
2174 | |
2175 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2176 | POSTING_READ(reg); |
b24e7179 JB |
2177 | } |
2178 | ||
2179 | /** | |
309cfea8 | 2180 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2181 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2182 | * |
575f7ab7 VS |
2183 | * Disable the pipe of @crtc, making sure that various hardware |
2184 | * specific requirements are met, if applicable, e.g. plane | |
2185 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2186 | * |
2187 | * Will wait until the pipe has shut down before returning. | |
2188 | */ | |
575f7ab7 | 2189 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2190 | { |
575f7ab7 | 2191 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2192 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2193 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2194 | int reg; |
2195 | u32 val; | |
2196 | ||
9e2ee2dd VS |
2197 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2198 | ||
b24e7179 JB |
2199 | /* |
2200 | * Make sure planes won't keep trying to pump pixels to us, | |
2201 | * or we might hang the display. | |
2202 | */ | |
2203 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2204 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2205 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2206 | |
702e7a56 | 2207 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2208 | val = I915_READ(reg); |
00d70b15 CW |
2209 | if ((val & PIPECONF_ENABLE) == 0) |
2210 | return; | |
2211 | ||
67adc644 VS |
2212 | /* |
2213 | * Double wide has implications for planes | |
2214 | * so best keep it disabled when not needed. | |
2215 | */ | |
6e3c9717 | 2216 | if (crtc->config->double_wide) |
67adc644 VS |
2217 | val &= ~PIPECONF_DOUBLE_WIDE; |
2218 | ||
2219 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2220 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2221 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2222 | val &= ~PIPECONF_ENABLE; |
2223 | ||
2224 | I915_WRITE(reg, val); | |
2225 | if ((val & PIPECONF_ENABLE) == 0) | |
2226 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2227 | } |
2228 | ||
693db184 CW |
2229 | static bool need_vtd_wa(struct drm_device *dev) |
2230 | { | |
2231 | #ifdef CONFIG_INTEL_IOMMU | |
2232 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2233 | return true; | |
2234 | #endif | |
2235 | return false; | |
2236 | } | |
2237 | ||
50470bb0 | 2238 | unsigned int |
6761dd31 | 2239 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
fe47ea0c | 2240 | uint64_t fb_format_modifier, unsigned int plane) |
a57ce0b2 | 2241 | { |
6761dd31 TU |
2242 | unsigned int tile_height; |
2243 | uint32_t pixel_bytes; | |
a57ce0b2 | 2244 | |
b5d0e9bf DL |
2245 | switch (fb_format_modifier) { |
2246 | case DRM_FORMAT_MOD_NONE: | |
2247 | tile_height = 1; | |
2248 | break; | |
2249 | case I915_FORMAT_MOD_X_TILED: | |
2250 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2251 | break; | |
2252 | case I915_FORMAT_MOD_Y_TILED: | |
2253 | tile_height = 32; | |
2254 | break; | |
2255 | case I915_FORMAT_MOD_Yf_TILED: | |
fe47ea0c | 2256 | pixel_bytes = drm_format_plane_cpp(pixel_format, plane); |
6761dd31 | 2257 | switch (pixel_bytes) { |
b5d0e9bf | 2258 | default: |
6761dd31 | 2259 | case 1: |
b5d0e9bf DL |
2260 | tile_height = 64; |
2261 | break; | |
6761dd31 TU |
2262 | case 2: |
2263 | case 4: | |
b5d0e9bf DL |
2264 | tile_height = 32; |
2265 | break; | |
6761dd31 | 2266 | case 8: |
b5d0e9bf DL |
2267 | tile_height = 16; |
2268 | break; | |
6761dd31 | 2269 | case 16: |
b5d0e9bf DL |
2270 | WARN_ONCE(1, |
2271 | "128-bit pixels are not supported for display!"); | |
2272 | tile_height = 16; | |
2273 | break; | |
2274 | } | |
2275 | break; | |
2276 | default: | |
2277 | MISSING_CASE(fb_format_modifier); | |
2278 | tile_height = 1; | |
2279 | break; | |
2280 | } | |
091df6cb | 2281 | |
6761dd31 TU |
2282 | return tile_height; |
2283 | } | |
2284 | ||
2285 | unsigned int | |
2286 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2287 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2288 | { | |
2289 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
fe47ea0c | 2290 | fb_format_modifier, 0)); |
a57ce0b2 JB |
2291 | } |
2292 | ||
f64b98cd TU |
2293 | static int |
2294 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2295 | const struct drm_plane_state *plane_state) | |
2296 | { | |
50470bb0 | 2297 | struct intel_rotation_info *info = &view->rotation_info; |
84fe03f7 | 2298 | unsigned int tile_height, tile_pitch; |
50470bb0 | 2299 | |
f64b98cd TU |
2300 | *view = i915_ggtt_view_normal; |
2301 | ||
50470bb0 TU |
2302 | if (!plane_state) |
2303 | return 0; | |
2304 | ||
121920fa | 2305 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2306 | return 0; |
2307 | ||
9abc4648 | 2308 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2309 | |
2310 | info->height = fb->height; | |
2311 | info->pixel_format = fb->pixel_format; | |
2312 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2313 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2314 | info->fb_modifier = fb->modifier[0]; |
2315 | ||
84fe03f7 | 2316 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
fe47ea0c | 2317 | fb->modifier[0], 0); |
84fe03f7 TU |
2318 | tile_pitch = PAGE_SIZE / tile_height; |
2319 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2320 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); | |
2321 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; | |
2322 | ||
89e3e142 TU |
2323 | if (info->pixel_format == DRM_FORMAT_NV12) { |
2324 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, | |
2325 | fb->modifier[0], 1); | |
2326 | tile_pitch = PAGE_SIZE / tile_height; | |
2327 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2328 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, | |
2329 | tile_height); | |
2330 | info->size_uv = info->width_pages_uv * info->height_pages_uv * | |
2331 | PAGE_SIZE; | |
2332 | } | |
2333 | ||
f64b98cd TU |
2334 | return 0; |
2335 | } | |
2336 | ||
4e9a86b6 VS |
2337 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2338 | { | |
2339 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2340 | return 256 * 1024; | |
985b8bb4 VS |
2341 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
2342 | IS_VALLEYVIEW(dev_priv)) | |
4e9a86b6 VS |
2343 | return 128 * 1024; |
2344 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2345 | return 4 * 1024; | |
2346 | else | |
44c5905e | 2347 | return 0; |
4e9a86b6 VS |
2348 | } |
2349 | ||
127bd2ac | 2350 | int |
850c4cdc TU |
2351 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2352 | struct drm_framebuffer *fb, | |
82bc3b2d | 2353 | const struct drm_plane_state *plane_state, |
91af127f JH |
2354 | struct intel_engine_cs *pipelined, |
2355 | struct drm_i915_gem_request **pipelined_request) | |
6b95a207 | 2356 | { |
850c4cdc | 2357 | struct drm_device *dev = fb->dev; |
ce453d81 | 2358 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2359 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2360 | struct i915_ggtt_view view; |
6b95a207 KH |
2361 | u32 alignment; |
2362 | int ret; | |
2363 | ||
ebcdd39e MR |
2364 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2365 | ||
7b911adc TU |
2366 | switch (fb->modifier[0]) { |
2367 | case DRM_FORMAT_MOD_NONE: | |
4e9a86b6 | 2368 | alignment = intel_linear_alignment(dev_priv); |
6b95a207 | 2369 | break; |
7b911adc | 2370 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2371 | if (INTEL_INFO(dev)->gen >= 9) |
2372 | alignment = 256 * 1024; | |
2373 | else { | |
2374 | /* pin() will align the object as required by fence */ | |
2375 | alignment = 0; | |
2376 | } | |
6b95a207 | 2377 | break; |
7b911adc | 2378 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2379 | case I915_FORMAT_MOD_Yf_TILED: |
2380 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2381 | "Y tiling bo slipped through, driver bug!\n")) | |
2382 | return -EINVAL; | |
2383 | alignment = 1 * 1024 * 1024; | |
2384 | break; | |
6b95a207 | 2385 | default: |
7b911adc TU |
2386 | MISSING_CASE(fb->modifier[0]); |
2387 | return -EINVAL; | |
6b95a207 KH |
2388 | } |
2389 | ||
f64b98cd TU |
2390 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2391 | if (ret) | |
2392 | return ret; | |
2393 | ||
693db184 CW |
2394 | /* Note that the w/a also requires 64 PTE of padding following the |
2395 | * bo. We currently fill all unused PTE with the shadow page and so | |
2396 | * we should always have valid PTE following the scanout preventing | |
2397 | * the VT-d warning. | |
2398 | */ | |
2399 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2400 | alignment = 256 * 1024; | |
2401 | ||
d6dd6843 PZ |
2402 | /* |
2403 | * Global gtt pte registers are special registers which actually forward | |
2404 | * writes to a chunk of system memory. Which means that there is no risk | |
2405 | * that the register values disappear as soon as we call | |
2406 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2407 | * pin/unpin/fence and not more. | |
2408 | */ | |
2409 | intel_runtime_pm_get(dev_priv); | |
2410 | ||
ce453d81 | 2411 | dev_priv->mm.interruptible = false; |
e6617330 | 2412 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
91af127f | 2413 | pipelined_request, &view); |
48b956c5 | 2414 | if (ret) |
ce453d81 | 2415 | goto err_interruptible; |
6b95a207 KH |
2416 | |
2417 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2418 | * fence, whereas 965+ only requires a fence if using | |
2419 | * framebuffer compression. For simplicity, we always install | |
2420 | * a fence as the cost is not that onerous. | |
2421 | */ | |
06d98131 | 2422 | ret = i915_gem_object_get_fence(obj); |
842315ee ML |
2423 | if (ret == -EDEADLK) { |
2424 | /* | |
2425 | * -EDEADLK means there are no free fences | |
2426 | * no pending flips. | |
2427 | * | |
2428 | * This is propagated to atomic, but it uses | |
2429 | * -EDEADLK to force a locking recovery, so | |
2430 | * change the returned error to -EBUSY. | |
2431 | */ | |
2432 | ret = -EBUSY; | |
2433 | goto err_unpin; | |
2434 | } else if (ret) | |
9a5a53b3 | 2435 | goto err_unpin; |
1690e1eb | 2436 | |
9a5a53b3 | 2437 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2438 | |
ce453d81 | 2439 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2440 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2441 | return 0; |
48b956c5 CW |
2442 | |
2443 | err_unpin: | |
f64b98cd | 2444 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2445 | err_interruptible: |
2446 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2447 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2448 | return ret; |
6b95a207 KH |
2449 | } |
2450 | ||
82bc3b2d TU |
2451 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2452 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2453 | { |
82bc3b2d | 2454 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2455 | struct i915_ggtt_view view; |
2456 | int ret; | |
82bc3b2d | 2457 | |
ebcdd39e MR |
2458 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2459 | ||
f64b98cd TU |
2460 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2461 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2462 | ||
1690e1eb | 2463 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2464 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2465 | } |
2466 | ||
c2c75131 DV |
2467 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2468 | * is assumed to be a power-of-two. */ | |
4e9a86b6 VS |
2469 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
2470 | int *x, int *y, | |
bc752862 CW |
2471 | unsigned int tiling_mode, |
2472 | unsigned int cpp, | |
2473 | unsigned int pitch) | |
c2c75131 | 2474 | { |
bc752862 CW |
2475 | if (tiling_mode != I915_TILING_NONE) { |
2476 | unsigned int tile_rows, tiles; | |
c2c75131 | 2477 | |
bc752862 CW |
2478 | tile_rows = *y / 8; |
2479 | *y %= 8; | |
c2c75131 | 2480 | |
bc752862 CW |
2481 | tiles = *x / (512/cpp); |
2482 | *x %= 512/cpp; | |
2483 | ||
2484 | return tile_rows * pitch * 8 + tiles * 4096; | |
2485 | } else { | |
4e9a86b6 | 2486 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2487 | unsigned int offset; |
2488 | ||
2489 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2490 | *y = (offset & alignment) / pitch; |
2491 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2492 | return offset & ~alignment; | |
bc752862 | 2493 | } |
c2c75131 DV |
2494 | } |
2495 | ||
b35d63fa | 2496 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2497 | { |
2498 | switch (format) { | |
2499 | case DISPPLANE_8BPP: | |
2500 | return DRM_FORMAT_C8; | |
2501 | case DISPPLANE_BGRX555: | |
2502 | return DRM_FORMAT_XRGB1555; | |
2503 | case DISPPLANE_BGRX565: | |
2504 | return DRM_FORMAT_RGB565; | |
2505 | default: | |
2506 | case DISPPLANE_BGRX888: | |
2507 | return DRM_FORMAT_XRGB8888; | |
2508 | case DISPPLANE_RGBX888: | |
2509 | return DRM_FORMAT_XBGR8888; | |
2510 | case DISPPLANE_BGRX101010: | |
2511 | return DRM_FORMAT_XRGB2101010; | |
2512 | case DISPPLANE_RGBX101010: | |
2513 | return DRM_FORMAT_XBGR2101010; | |
2514 | } | |
2515 | } | |
2516 | ||
bc8d7dff DL |
2517 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2518 | { | |
2519 | switch (format) { | |
2520 | case PLANE_CTL_FORMAT_RGB_565: | |
2521 | return DRM_FORMAT_RGB565; | |
2522 | default: | |
2523 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2524 | if (rgb_order) { | |
2525 | if (alpha) | |
2526 | return DRM_FORMAT_ABGR8888; | |
2527 | else | |
2528 | return DRM_FORMAT_XBGR8888; | |
2529 | } else { | |
2530 | if (alpha) | |
2531 | return DRM_FORMAT_ARGB8888; | |
2532 | else | |
2533 | return DRM_FORMAT_XRGB8888; | |
2534 | } | |
2535 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2536 | if (rgb_order) | |
2537 | return DRM_FORMAT_XBGR2101010; | |
2538 | else | |
2539 | return DRM_FORMAT_XRGB2101010; | |
2540 | } | |
2541 | } | |
2542 | ||
5724dbd1 | 2543 | static bool |
f6936e29 DV |
2544 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2545 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2546 | { |
2547 | struct drm_device *dev = crtc->base.dev; | |
2548 | struct drm_i915_gem_object *obj = NULL; | |
2549 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2550 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2551 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2552 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2553 | PAGE_SIZE); | |
2554 | ||
2555 | size_aligned -= base_aligned; | |
46f297fb | 2556 | |
ff2652ea CW |
2557 | if (plane_config->size == 0) |
2558 | return false; | |
2559 | ||
f37b5c2b DV |
2560 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2561 | base_aligned, | |
2562 | base_aligned, | |
2563 | size_aligned); | |
46f297fb | 2564 | if (!obj) |
484b41dd | 2565 | return false; |
46f297fb | 2566 | |
49af449b DL |
2567 | obj->tiling_mode = plane_config->tiling; |
2568 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2569 | obj->stride = fb->pitches[0]; |
46f297fb | 2570 | |
6bf129df DL |
2571 | mode_cmd.pixel_format = fb->pixel_format; |
2572 | mode_cmd.width = fb->width; | |
2573 | mode_cmd.height = fb->height; | |
2574 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2575 | mode_cmd.modifier[0] = fb->modifier[0]; |
2576 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2577 | |
2578 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2579 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2580 | &mode_cmd, obj)) { |
46f297fb JB |
2581 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2582 | goto out_unref_obj; | |
2583 | } | |
46f297fb | 2584 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2585 | |
f6936e29 | 2586 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2587 | return true; |
46f297fb JB |
2588 | |
2589 | out_unref_obj: | |
2590 | drm_gem_object_unreference(&obj->base); | |
2591 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2592 | return false; |
2593 | } | |
2594 | ||
afd65eb4 MR |
2595 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2596 | static void | |
2597 | update_state_fb(struct drm_plane *plane) | |
2598 | { | |
2599 | if (plane->fb == plane->state->fb) | |
2600 | return; | |
2601 | ||
2602 | if (plane->state->fb) | |
2603 | drm_framebuffer_unreference(plane->state->fb); | |
2604 | plane->state->fb = plane->fb; | |
2605 | if (plane->state->fb) | |
2606 | drm_framebuffer_reference(plane->state->fb); | |
2607 | } | |
2608 | ||
5724dbd1 | 2609 | static void |
f6936e29 DV |
2610 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2611 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2612 | { |
2613 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2614 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2615 | struct drm_crtc *c; |
2616 | struct intel_crtc *i; | |
2ff8fde1 | 2617 | struct drm_i915_gem_object *obj; |
88595ac9 | 2618 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2619 | struct drm_plane_state *plane_state = primary->state; |
88595ac9 | 2620 | struct drm_framebuffer *fb; |
484b41dd | 2621 | |
2d14030b | 2622 | if (!plane_config->fb) |
484b41dd JB |
2623 | return; |
2624 | ||
f6936e29 | 2625 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2626 | fb = &plane_config->fb->base; |
2627 | goto valid_fb; | |
f55548b5 | 2628 | } |
484b41dd | 2629 | |
2d14030b | 2630 | kfree(plane_config->fb); |
484b41dd JB |
2631 | |
2632 | /* | |
2633 | * Failed to alloc the obj, check to see if we should share | |
2634 | * an fb with another CRTC instead | |
2635 | */ | |
70e1e0ec | 2636 | for_each_crtc(dev, c) { |
484b41dd JB |
2637 | i = to_intel_crtc(c); |
2638 | ||
2639 | if (c == &intel_crtc->base) | |
2640 | continue; | |
2641 | ||
2ff8fde1 MR |
2642 | if (!i->active) |
2643 | continue; | |
2644 | ||
88595ac9 DV |
2645 | fb = c->primary->fb; |
2646 | if (!fb) | |
484b41dd JB |
2647 | continue; |
2648 | ||
88595ac9 | 2649 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2650 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2651 | drm_framebuffer_reference(fb); |
2652 | goto valid_fb; | |
484b41dd JB |
2653 | } |
2654 | } | |
88595ac9 DV |
2655 | |
2656 | return; | |
2657 | ||
2658 | valid_fb: | |
be5651f2 ML |
2659 | plane_state->src_x = plane_state->src_y = 0; |
2660 | plane_state->src_w = fb->width << 16; | |
2661 | plane_state->src_h = fb->height << 16; | |
2662 | ||
2663 | plane_state->crtc_x = plane_state->src_y = 0; | |
2664 | plane_state->crtc_w = fb->width; | |
2665 | plane_state->crtc_h = fb->height; | |
2666 | ||
88595ac9 DV |
2667 | obj = intel_fb_obj(fb); |
2668 | if (obj->tiling_mode != I915_TILING_NONE) | |
2669 | dev_priv->preserve_bios_swizzle = true; | |
2670 | ||
be5651f2 ML |
2671 | drm_framebuffer_reference(fb); |
2672 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2673 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2674 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2675 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2676 | } |
2677 | ||
29b9bde6 DV |
2678 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2679 | struct drm_framebuffer *fb, | |
2680 | int x, int y) | |
81255565 JB |
2681 | { |
2682 | struct drm_device *dev = crtc->dev; | |
2683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2684 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2685 | struct drm_plane *primary = crtc->primary; |
2686 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2687 | struct drm_i915_gem_object *obj; |
81255565 | 2688 | int plane = intel_crtc->plane; |
e506a0c6 | 2689 | unsigned long linear_offset; |
81255565 | 2690 | u32 dspcntr; |
f45651ba | 2691 | u32 reg = DSPCNTR(plane); |
48404c1e | 2692 | int pixel_size; |
f45651ba | 2693 | |
b70709a6 | 2694 | if (!visible || !fb) { |
fdd508a6 VS |
2695 | I915_WRITE(reg, 0); |
2696 | if (INTEL_INFO(dev)->gen >= 4) | |
2697 | I915_WRITE(DSPSURF(plane), 0); | |
2698 | else | |
2699 | I915_WRITE(DSPADDR(plane), 0); | |
2700 | POSTING_READ(reg); | |
2701 | return; | |
2702 | } | |
2703 | ||
c9ba6fad VS |
2704 | obj = intel_fb_obj(fb); |
2705 | if (WARN_ON(obj == NULL)) | |
2706 | return; | |
2707 | ||
2708 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2709 | ||
f45651ba VS |
2710 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2711 | ||
fdd508a6 | 2712 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2713 | |
2714 | if (INTEL_INFO(dev)->gen < 4) { | |
2715 | if (intel_crtc->pipe == PIPE_B) | |
2716 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2717 | ||
2718 | /* pipesrc and dspsize control the size that is scaled from, | |
2719 | * which should always be the user's requested size. | |
2720 | */ | |
2721 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2722 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2723 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2724 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2725 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2726 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2727 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2728 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2729 | I915_WRITE(PRIMPOS(plane), 0); |
2730 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2731 | } |
81255565 | 2732 | |
57779d06 VS |
2733 | switch (fb->pixel_format) { |
2734 | case DRM_FORMAT_C8: | |
81255565 JB |
2735 | dspcntr |= DISPPLANE_8BPP; |
2736 | break; | |
57779d06 | 2737 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2738 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2739 | break; |
57779d06 VS |
2740 | case DRM_FORMAT_RGB565: |
2741 | dspcntr |= DISPPLANE_BGRX565; | |
2742 | break; | |
2743 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2744 | dspcntr |= DISPPLANE_BGRX888; |
2745 | break; | |
2746 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2747 | dspcntr |= DISPPLANE_RGBX888; |
2748 | break; | |
2749 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2750 | dspcntr |= DISPPLANE_BGRX101010; |
2751 | break; | |
2752 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2753 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2754 | break; |
2755 | default: | |
baba133a | 2756 | BUG(); |
81255565 | 2757 | } |
57779d06 | 2758 | |
f45651ba VS |
2759 | if (INTEL_INFO(dev)->gen >= 4 && |
2760 | obj->tiling_mode != I915_TILING_NONE) | |
2761 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2762 | |
de1aa629 VS |
2763 | if (IS_G4X(dev)) |
2764 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2765 | ||
b9897127 | 2766 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2767 | |
c2c75131 DV |
2768 | if (INTEL_INFO(dev)->gen >= 4) { |
2769 | intel_crtc->dspaddr_offset = | |
4e9a86b6 VS |
2770 | intel_gen4_compute_page_offset(dev_priv, |
2771 | &x, &y, obj->tiling_mode, | |
b9897127 | 2772 | pixel_size, |
bc752862 | 2773 | fb->pitches[0]); |
c2c75131 DV |
2774 | linear_offset -= intel_crtc->dspaddr_offset; |
2775 | } else { | |
e506a0c6 | 2776 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2777 | } |
e506a0c6 | 2778 | |
8e7d688b | 2779 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2780 | dspcntr |= DISPPLANE_ROTATE_180; |
2781 | ||
6e3c9717 ACO |
2782 | x += (intel_crtc->config->pipe_src_w - 1); |
2783 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2784 | |
2785 | /* Finding the last pixel of the last line of the display | |
2786 | data and adding to linear_offset*/ | |
2787 | linear_offset += | |
6e3c9717 ACO |
2788 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2789 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2790 | } |
2791 | ||
2db3366b PZ |
2792 | intel_crtc->adjusted_x = x; |
2793 | intel_crtc->adjusted_y = y; | |
2794 | ||
48404c1e SJ |
2795 | I915_WRITE(reg, dspcntr); |
2796 | ||
01f2c773 | 2797 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2798 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2799 | I915_WRITE(DSPSURF(plane), |
2800 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2801 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2802 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2803 | } else |
f343c5f6 | 2804 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2805 | POSTING_READ(reg); |
17638cd6 JB |
2806 | } |
2807 | ||
29b9bde6 DV |
2808 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2809 | struct drm_framebuffer *fb, | |
2810 | int x, int y) | |
17638cd6 JB |
2811 | { |
2812 | struct drm_device *dev = crtc->dev; | |
2813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2814 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2815 | struct drm_plane *primary = crtc->primary; |
2816 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2817 | struct drm_i915_gem_object *obj; |
17638cd6 | 2818 | int plane = intel_crtc->plane; |
e506a0c6 | 2819 | unsigned long linear_offset; |
17638cd6 | 2820 | u32 dspcntr; |
f45651ba | 2821 | u32 reg = DSPCNTR(plane); |
48404c1e | 2822 | int pixel_size; |
f45651ba | 2823 | |
b70709a6 | 2824 | if (!visible || !fb) { |
fdd508a6 VS |
2825 | I915_WRITE(reg, 0); |
2826 | I915_WRITE(DSPSURF(plane), 0); | |
2827 | POSTING_READ(reg); | |
2828 | return; | |
2829 | } | |
2830 | ||
c9ba6fad VS |
2831 | obj = intel_fb_obj(fb); |
2832 | if (WARN_ON(obj == NULL)) | |
2833 | return; | |
2834 | ||
2835 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2836 | ||
f45651ba VS |
2837 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2838 | ||
fdd508a6 | 2839 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2840 | |
2841 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2842 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2843 | |
57779d06 VS |
2844 | switch (fb->pixel_format) { |
2845 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2846 | dspcntr |= DISPPLANE_8BPP; |
2847 | break; | |
57779d06 VS |
2848 | case DRM_FORMAT_RGB565: |
2849 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2850 | break; |
57779d06 | 2851 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2852 | dspcntr |= DISPPLANE_BGRX888; |
2853 | break; | |
2854 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2855 | dspcntr |= DISPPLANE_RGBX888; |
2856 | break; | |
2857 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2858 | dspcntr |= DISPPLANE_BGRX101010; |
2859 | break; | |
2860 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2861 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2862 | break; |
2863 | default: | |
baba133a | 2864 | BUG(); |
17638cd6 JB |
2865 | } |
2866 | ||
2867 | if (obj->tiling_mode != I915_TILING_NONE) | |
2868 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2869 | |
f45651ba | 2870 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2871 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2872 | |
b9897127 | 2873 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2874 | intel_crtc->dspaddr_offset = |
4e9a86b6 VS |
2875 | intel_gen4_compute_page_offset(dev_priv, |
2876 | &x, &y, obj->tiling_mode, | |
b9897127 | 2877 | pixel_size, |
bc752862 | 2878 | fb->pitches[0]); |
c2c75131 | 2879 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2880 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2881 | dspcntr |= DISPPLANE_ROTATE_180; |
2882 | ||
2883 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2884 | x += (intel_crtc->config->pipe_src_w - 1); |
2885 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2886 | |
2887 | /* Finding the last pixel of the last line of the display | |
2888 | data and adding to linear_offset*/ | |
2889 | linear_offset += | |
6e3c9717 ACO |
2890 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2891 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2892 | } |
2893 | } | |
2894 | ||
2db3366b PZ |
2895 | intel_crtc->adjusted_x = x; |
2896 | intel_crtc->adjusted_y = y; | |
2897 | ||
48404c1e | 2898 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2899 | |
01f2c773 | 2900 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2901 | I915_WRITE(DSPSURF(plane), |
2902 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2903 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2904 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2905 | } else { | |
2906 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2907 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2908 | } | |
17638cd6 | 2909 | POSTING_READ(reg); |
17638cd6 JB |
2910 | } |
2911 | ||
b321803d DL |
2912 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2913 | uint32_t pixel_format) | |
2914 | { | |
2915 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2916 | ||
2917 | /* | |
2918 | * The stride is either expressed as a multiple of 64 bytes | |
2919 | * chunks for linear buffers or in number of tiles for tiled | |
2920 | * buffers. | |
2921 | */ | |
2922 | switch (fb_modifier) { | |
2923 | case DRM_FORMAT_MOD_NONE: | |
2924 | return 64; | |
2925 | case I915_FORMAT_MOD_X_TILED: | |
2926 | if (INTEL_INFO(dev)->gen == 2) | |
2927 | return 128; | |
2928 | return 512; | |
2929 | case I915_FORMAT_MOD_Y_TILED: | |
2930 | /* No need to check for old gens and Y tiling since this is | |
2931 | * about the display engine and those will be blocked before | |
2932 | * we get here. | |
2933 | */ | |
2934 | return 128; | |
2935 | case I915_FORMAT_MOD_Yf_TILED: | |
2936 | if (bits_per_pixel == 8) | |
2937 | return 64; | |
2938 | else | |
2939 | return 128; | |
2940 | default: | |
2941 | MISSING_CASE(fb_modifier); | |
2942 | return 64; | |
2943 | } | |
2944 | } | |
2945 | ||
121920fa | 2946 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
dedf278c TU |
2947 | struct drm_i915_gem_object *obj, |
2948 | unsigned int plane) | |
121920fa | 2949 | { |
9abc4648 | 2950 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
dedf278c TU |
2951 | struct i915_vma *vma; |
2952 | unsigned char *offset; | |
121920fa TU |
2953 | |
2954 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2955 | view = &i915_ggtt_view_rotated; |
121920fa | 2956 | |
dedf278c TU |
2957 | vma = i915_gem_obj_to_ggtt_view(obj, view); |
2958 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", | |
2959 | view->type)) | |
2960 | return -1; | |
2961 | ||
2962 | offset = (unsigned char *)vma->node.start; | |
2963 | ||
2964 | if (plane == 1) { | |
2965 | offset += vma->ggtt_view.rotation_info.uv_start_page * | |
2966 | PAGE_SIZE; | |
2967 | } | |
2968 | ||
2969 | return (unsigned long)offset; | |
121920fa TU |
2970 | } |
2971 | ||
e435d6e5 ML |
2972 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2973 | { | |
2974 | struct drm_device *dev = intel_crtc->base.dev; | |
2975 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2976 | ||
2977 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2978 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2979 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2980 | } |
2981 | ||
a1b2278e CK |
2982 | /* |
2983 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2984 | */ | |
0583236e | 2985 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2986 | { |
a1b2278e CK |
2987 | struct intel_crtc_scaler_state *scaler_state; |
2988 | int i; | |
2989 | ||
a1b2278e CK |
2990 | scaler_state = &intel_crtc->config->scaler_state; |
2991 | ||
2992 | /* loop through and disable scalers that aren't in use */ | |
2993 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2994 | if (!scaler_state->scalers[i].in_use) |
2995 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2996 | } |
2997 | } | |
2998 | ||
6156a456 | 2999 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3000 | { |
6156a456 | 3001 | switch (pixel_format) { |
d161cf7a | 3002 | case DRM_FORMAT_C8: |
c34ce3d1 | 3003 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3004 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3005 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3006 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3007 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3008 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3009 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3010 | /* |
3011 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3012 | * to be already pre-multiplied. We need to add a knob (or a different | |
3013 | * DRM_FORMAT) for user-space to configure that. | |
3014 | */ | |
f75fb42a | 3015 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3016 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3017 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3018 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3019 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3020 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3021 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3022 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3023 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3024 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3025 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3026 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3027 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3028 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3029 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3030 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3031 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3032 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3033 | default: |
4249eeef | 3034 | MISSING_CASE(pixel_format); |
70d21f0e | 3035 | } |
8cfcba41 | 3036 | |
c34ce3d1 | 3037 | return 0; |
6156a456 | 3038 | } |
70d21f0e | 3039 | |
6156a456 CK |
3040 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3041 | { | |
6156a456 | 3042 | switch (fb_modifier) { |
30af77c4 | 3043 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3044 | break; |
30af77c4 | 3045 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3046 | return PLANE_CTL_TILED_X; |
b321803d | 3047 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3048 | return PLANE_CTL_TILED_Y; |
b321803d | 3049 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3050 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3051 | default: |
6156a456 | 3052 | MISSING_CASE(fb_modifier); |
70d21f0e | 3053 | } |
8cfcba41 | 3054 | |
c34ce3d1 | 3055 | return 0; |
6156a456 | 3056 | } |
70d21f0e | 3057 | |
6156a456 CK |
3058 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3059 | { | |
3b7a5119 | 3060 | switch (rotation) { |
6156a456 CK |
3061 | case BIT(DRM_ROTATE_0): |
3062 | break; | |
1e8df167 SJ |
3063 | /* |
3064 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3065 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3066 | */ | |
3b7a5119 | 3067 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3068 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3069 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3070 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3071 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3072 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3073 | default: |
3074 | MISSING_CASE(rotation); | |
3075 | } | |
3076 | ||
c34ce3d1 | 3077 | return 0; |
6156a456 CK |
3078 | } |
3079 | ||
3080 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3081 | struct drm_framebuffer *fb, | |
3082 | int x, int y) | |
3083 | { | |
3084 | struct drm_device *dev = crtc->dev; | |
3085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3086 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3087 | struct drm_plane *plane = crtc->primary; |
3088 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3089 | struct drm_i915_gem_object *obj; |
3090 | int pipe = intel_crtc->pipe; | |
3091 | u32 plane_ctl, stride_div, stride; | |
3092 | u32 tile_height, plane_offset, plane_size; | |
3093 | unsigned int rotation; | |
3094 | int x_offset, y_offset; | |
3095 | unsigned long surf_addr; | |
6156a456 CK |
3096 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3097 | struct intel_plane_state *plane_state; | |
3098 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3099 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3100 | int scaler_id = -1; | |
3101 | ||
6156a456 CK |
3102 | plane_state = to_intel_plane_state(plane->state); |
3103 | ||
b70709a6 | 3104 | if (!visible || !fb) { |
6156a456 CK |
3105 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3106 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3107 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3108 | return; | |
3b7a5119 | 3109 | } |
70d21f0e | 3110 | |
6156a456 CK |
3111 | plane_ctl = PLANE_CTL_ENABLE | |
3112 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3113 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3114 | ||
3115 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3116 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3117 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3118 | ||
3119 | rotation = plane->state->rotation; | |
3120 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3121 | ||
b321803d DL |
3122 | obj = intel_fb_obj(fb); |
3123 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3124 | fb->pixel_format); | |
dedf278c | 3125 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3126 | |
6156a456 CK |
3127 | /* |
3128 | * FIXME: intel_plane_state->src, dst aren't set when transitional | |
3129 | * update_plane helpers are called from legacy paths. | |
3130 | * Once full atomic crtc is available, below check can be avoided. | |
3131 | */ | |
3132 | if (drm_rect_width(&plane_state->src)) { | |
3133 | scaler_id = plane_state->scaler_id; | |
3134 | src_x = plane_state->src.x1 >> 16; | |
3135 | src_y = plane_state->src.y1 >> 16; | |
3136 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3137 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3138 | dst_x = plane_state->dst.x1; | |
3139 | dst_y = plane_state->dst.y1; | |
3140 | dst_w = drm_rect_width(&plane_state->dst); | |
3141 | dst_h = drm_rect_height(&plane_state->dst); | |
3142 | ||
3143 | WARN_ON(x != src_x || y != src_y); | |
3144 | } else { | |
3145 | src_w = intel_crtc->config->pipe_src_w; | |
3146 | src_h = intel_crtc->config->pipe_src_h; | |
3147 | } | |
3148 | ||
3b7a5119 SJ |
3149 | if (intel_rotation_90_or_270(rotation)) { |
3150 | /* stride = Surface height in tiles */ | |
2614f17d | 3151 | tile_height = intel_tile_height(dev, fb->pixel_format, |
fe47ea0c | 3152 | fb->modifier[0], 0); |
3b7a5119 | 3153 | stride = DIV_ROUND_UP(fb->height, tile_height); |
6156a456 | 3154 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3155 | y_offset = x; |
6156a456 | 3156 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3157 | } else { |
3158 | stride = fb->pitches[0] / stride_div; | |
3159 | x_offset = x; | |
3160 | y_offset = y; | |
6156a456 | 3161 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3162 | } |
3163 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3164 | |
2db3366b PZ |
3165 | intel_crtc->adjusted_x = x_offset; |
3166 | intel_crtc->adjusted_y = y_offset; | |
3167 | ||
70d21f0e | 3168 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3169 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3170 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3171 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3172 | |
3173 | if (scaler_id >= 0) { | |
3174 | uint32_t ps_ctrl = 0; | |
3175 | ||
3176 | WARN_ON(!dst_w || !dst_h); | |
3177 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3178 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3179 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3180 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3181 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3182 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3183 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3184 | } else { | |
3185 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3186 | } | |
3187 | ||
121920fa | 3188 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3189 | |
3190 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3191 | } | |
3192 | ||
17638cd6 JB |
3193 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3194 | static int | |
3195 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3196 | int x, int y, enum mode_set_atomic state) | |
3197 | { | |
3198 | struct drm_device *dev = crtc->dev; | |
3199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3200 | |
ff2a3117 | 3201 | if (dev_priv->fbc.disable_fbc) |
7733b49b | 3202 | dev_priv->fbc.disable_fbc(dev_priv); |
81255565 | 3203 | |
29b9bde6 DV |
3204 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3205 | ||
3206 | return 0; | |
81255565 JB |
3207 | } |
3208 | ||
7514747d | 3209 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3210 | { |
96a02917 VS |
3211 | struct drm_crtc *crtc; |
3212 | ||
70e1e0ec | 3213 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3215 | enum plane plane = intel_crtc->plane; | |
3216 | ||
3217 | intel_prepare_page_flip(dev, plane); | |
3218 | intel_finish_page_flip_plane(dev, plane); | |
3219 | } | |
7514747d VS |
3220 | } |
3221 | ||
3222 | static void intel_update_primary_planes(struct drm_device *dev) | |
3223 | { | |
7514747d | 3224 | struct drm_crtc *crtc; |
96a02917 | 3225 | |
70e1e0ec | 3226 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3227 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3228 | struct intel_plane_state *plane_state; | |
96a02917 | 3229 | |
11c22da6 ML |
3230 | drm_modeset_lock_crtc(crtc, &plane->base); |
3231 | ||
3232 | plane_state = to_intel_plane_state(plane->base.state); | |
3233 | ||
3234 | if (plane_state->base.fb) | |
3235 | plane->commit_plane(&plane->base, plane_state); | |
3236 | ||
3237 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3238 | } |
3239 | } | |
3240 | ||
7514747d VS |
3241 | void intel_prepare_reset(struct drm_device *dev) |
3242 | { | |
3243 | /* no reset support for gen2 */ | |
3244 | if (IS_GEN2(dev)) | |
3245 | return; | |
3246 | ||
3247 | /* reset doesn't touch the display */ | |
3248 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3249 | return; | |
3250 | ||
3251 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3252 | /* |
3253 | * Disabling the crtcs gracefully seems nicer. Also the | |
3254 | * g33 docs say we should at least disable all the planes. | |
3255 | */ | |
6b72d486 | 3256 | intel_display_suspend(dev); |
7514747d VS |
3257 | } |
3258 | ||
3259 | void intel_finish_reset(struct drm_device *dev) | |
3260 | { | |
3261 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3262 | ||
3263 | /* | |
3264 | * Flips in the rings will be nuked by the reset, | |
3265 | * so complete all pending flips so that user space | |
3266 | * will get its events and not get stuck. | |
3267 | */ | |
3268 | intel_complete_page_flips(dev); | |
3269 | ||
3270 | /* no reset support for gen2 */ | |
3271 | if (IS_GEN2(dev)) | |
3272 | return; | |
3273 | ||
3274 | /* reset doesn't touch the display */ | |
3275 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3276 | /* | |
3277 | * Flips in the rings have been nuked by the reset, | |
3278 | * so update the base address of all primary | |
3279 | * planes to the the last fb to make sure we're | |
3280 | * showing the correct fb after a reset. | |
11c22da6 ML |
3281 | * |
3282 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3283 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3284 | */ |
3285 | intel_update_primary_planes(dev); | |
3286 | return; | |
3287 | } | |
3288 | ||
3289 | /* | |
3290 | * The display has been reset as well, | |
3291 | * so need a full re-initialization. | |
3292 | */ | |
3293 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3294 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3295 | ||
3296 | intel_modeset_init_hw(dev); | |
3297 | ||
3298 | spin_lock_irq(&dev_priv->irq_lock); | |
3299 | if (dev_priv->display.hpd_irq_setup) | |
3300 | dev_priv->display.hpd_irq_setup(dev); | |
3301 | spin_unlock_irq(&dev_priv->irq_lock); | |
3302 | ||
043e9bda | 3303 | intel_display_resume(dev); |
7514747d VS |
3304 | |
3305 | intel_hpd_init(dev_priv); | |
3306 | ||
3307 | drm_modeset_unlock_all(dev); | |
3308 | } | |
3309 | ||
2e2f351d | 3310 | static void |
14667a4b CW |
3311 | intel_finish_fb(struct drm_framebuffer *old_fb) |
3312 | { | |
2ff8fde1 | 3313 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
2e2f351d | 3314 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
14667a4b CW |
3315 | bool was_interruptible = dev_priv->mm.interruptible; |
3316 | int ret; | |
3317 | ||
14667a4b CW |
3318 | /* Big Hammer, we also need to ensure that any pending |
3319 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3320 | * current scanout is retired before unpinning the old | |
2e2f351d CW |
3321 | * framebuffer. Note that we rely on userspace rendering |
3322 | * into the buffer attached to the pipe they are waiting | |
3323 | * on. If not, userspace generates a GPU hang with IPEHR | |
3324 | * point to the MI_WAIT_FOR_EVENT. | |
14667a4b CW |
3325 | * |
3326 | * This should only fail upon a hung GPU, in which case we | |
3327 | * can safely continue. | |
3328 | */ | |
3329 | dev_priv->mm.interruptible = false; | |
2e2f351d | 3330 | ret = i915_gem_object_wait_rendering(obj, true); |
14667a4b CW |
3331 | dev_priv->mm.interruptible = was_interruptible; |
3332 | ||
2e2f351d | 3333 | WARN_ON(ret); |
14667a4b CW |
3334 | } |
3335 | ||
7d5e3799 CW |
3336 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3337 | { | |
3338 | struct drm_device *dev = crtc->dev; | |
3339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3340 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3341 | bool pending; |
3342 | ||
3343 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3344 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3345 | return false; | |
3346 | ||
5e2d7afc | 3347 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3348 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3349 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3350 | |
3351 | return pending; | |
3352 | } | |
3353 | ||
bfd16b2a ML |
3354 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3355 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3356 | { |
3357 | struct drm_device *dev = crtc->base.dev; | |
3358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3359 | struct intel_crtc_state *pipe_config = |
3360 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3361 | |
bfd16b2a ML |
3362 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3363 | crtc->base.mode = crtc->base.state->mode; | |
3364 | ||
3365 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3366 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3367 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3368 | |
44522d85 ML |
3369 | if (HAS_DDI(dev)) |
3370 | intel_set_pipe_csc(&crtc->base); | |
3371 | ||
e30e8f75 GP |
3372 | /* |
3373 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3374 | * that in compute_mode_changes we check the native mode (not the pfit | |
3375 | * mode) to see if we can flip rather than do a full mode set. In the | |
3376 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3377 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3378 | * sized surface. | |
e30e8f75 GP |
3379 | */ |
3380 | ||
e30e8f75 | 3381 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3382 | ((pipe_config->pipe_src_w - 1) << 16) | |
3383 | (pipe_config->pipe_src_h - 1)); | |
3384 | ||
3385 | /* on skylake this is done by detaching scalers */ | |
3386 | if (INTEL_INFO(dev)->gen >= 9) { | |
3387 | skl_detach_scalers(crtc); | |
3388 | ||
3389 | if (pipe_config->pch_pfit.enabled) | |
3390 | skylake_pfit_enable(crtc); | |
3391 | } else if (HAS_PCH_SPLIT(dev)) { | |
3392 | if (pipe_config->pch_pfit.enabled) | |
3393 | ironlake_pfit_enable(crtc); | |
3394 | else if (old_crtc_state->pch_pfit.enabled) | |
3395 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3396 | } |
e30e8f75 GP |
3397 | } |
3398 | ||
5e84e1a4 ZW |
3399 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3400 | { | |
3401 | struct drm_device *dev = crtc->dev; | |
3402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3403 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3404 | int pipe = intel_crtc->pipe; | |
3405 | u32 reg, temp; | |
3406 | ||
3407 | /* enable normal train */ | |
3408 | reg = FDI_TX_CTL(pipe); | |
3409 | temp = I915_READ(reg); | |
61e499bf | 3410 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3411 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3412 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3413 | } else { |
3414 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3415 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3416 | } |
5e84e1a4 ZW |
3417 | I915_WRITE(reg, temp); |
3418 | ||
3419 | reg = FDI_RX_CTL(pipe); | |
3420 | temp = I915_READ(reg); | |
3421 | if (HAS_PCH_CPT(dev)) { | |
3422 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3423 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3424 | } else { | |
3425 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3426 | temp |= FDI_LINK_TRAIN_NONE; | |
3427 | } | |
3428 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3429 | ||
3430 | /* wait one idle pattern time */ | |
3431 | POSTING_READ(reg); | |
3432 | udelay(1000); | |
357555c0 JB |
3433 | |
3434 | /* IVB wants error correction enabled */ | |
3435 | if (IS_IVYBRIDGE(dev)) | |
3436 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3437 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3438 | } |
3439 | ||
8db9d77b ZW |
3440 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3441 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3442 | { | |
3443 | struct drm_device *dev = crtc->dev; | |
3444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3446 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3447 | u32 reg, temp, tries; |
8db9d77b | 3448 | |
1c8562f6 | 3449 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3450 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3451 | |
e1a44743 AJ |
3452 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3453 | for train result */ | |
5eddb70b CW |
3454 | reg = FDI_RX_IMR(pipe); |
3455 | temp = I915_READ(reg); | |
e1a44743 AJ |
3456 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3457 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3458 | I915_WRITE(reg, temp); |
3459 | I915_READ(reg); | |
e1a44743 AJ |
3460 | udelay(150); |
3461 | ||
8db9d77b | 3462 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3463 | reg = FDI_TX_CTL(pipe); |
3464 | temp = I915_READ(reg); | |
627eb5a3 | 3465 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3466 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3467 | temp &= ~FDI_LINK_TRAIN_NONE; |
3468 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3469 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3470 | |
5eddb70b CW |
3471 | reg = FDI_RX_CTL(pipe); |
3472 | temp = I915_READ(reg); | |
8db9d77b ZW |
3473 | temp &= ~FDI_LINK_TRAIN_NONE; |
3474 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3475 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3476 | ||
3477 | POSTING_READ(reg); | |
8db9d77b ZW |
3478 | udelay(150); |
3479 | ||
5b2adf89 | 3480 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3481 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3482 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3483 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3484 | |
5eddb70b | 3485 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3486 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3487 | temp = I915_READ(reg); |
8db9d77b ZW |
3488 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3489 | ||
3490 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3491 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3492 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3493 | break; |
3494 | } | |
8db9d77b | 3495 | } |
e1a44743 | 3496 | if (tries == 5) |
5eddb70b | 3497 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3498 | |
3499 | /* Train 2 */ | |
5eddb70b CW |
3500 | reg = FDI_TX_CTL(pipe); |
3501 | temp = I915_READ(reg); | |
8db9d77b ZW |
3502 | temp &= ~FDI_LINK_TRAIN_NONE; |
3503 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3504 | I915_WRITE(reg, temp); |
8db9d77b | 3505 | |
5eddb70b CW |
3506 | reg = FDI_RX_CTL(pipe); |
3507 | temp = I915_READ(reg); | |
8db9d77b ZW |
3508 | temp &= ~FDI_LINK_TRAIN_NONE; |
3509 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3510 | I915_WRITE(reg, temp); |
8db9d77b | 3511 | |
5eddb70b CW |
3512 | POSTING_READ(reg); |
3513 | udelay(150); | |
8db9d77b | 3514 | |
5eddb70b | 3515 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3516 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3517 | temp = I915_READ(reg); |
8db9d77b ZW |
3518 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3519 | ||
3520 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3521 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3522 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3523 | break; | |
3524 | } | |
8db9d77b | 3525 | } |
e1a44743 | 3526 | if (tries == 5) |
5eddb70b | 3527 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3528 | |
3529 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3530 | |
8db9d77b ZW |
3531 | } |
3532 | ||
0206e353 | 3533 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3534 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3535 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3536 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3537 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3538 | }; | |
3539 | ||
3540 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3541 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3542 | { | |
3543 | struct drm_device *dev = crtc->dev; | |
3544 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3545 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3546 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3547 | u32 reg, temp, i, retry; |
8db9d77b | 3548 | |
e1a44743 AJ |
3549 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3550 | for train result */ | |
5eddb70b CW |
3551 | reg = FDI_RX_IMR(pipe); |
3552 | temp = I915_READ(reg); | |
e1a44743 AJ |
3553 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3554 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3555 | I915_WRITE(reg, temp); |
3556 | ||
3557 | POSTING_READ(reg); | |
e1a44743 AJ |
3558 | udelay(150); |
3559 | ||
8db9d77b | 3560 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3561 | reg = FDI_TX_CTL(pipe); |
3562 | temp = I915_READ(reg); | |
627eb5a3 | 3563 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3564 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3565 | temp &= ~FDI_LINK_TRAIN_NONE; |
3566 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3567 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3568 | /* SNB-B */ | |
3569 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3570 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3571 | |
d74cf324 DV |
3572 | I915_WRITE(FDI_RX_MISC(pipe), |
3573 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3574 | ||
5eddb70b CW |
3575 | reg = FDI_RX_CTL(pipe); |
3576 | temp = I915_READ(reg); | |
8db9d77b ZW |
3577 | if (HAS_PCH_CPT(dev)) { |
3578 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3579 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3580 | } else { | |
3581 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3582 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3583 | } | |
5eddb70b CW |
3584 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3585 | ||
3586 | POSTING_READ(reg); | |
8db9d77b ZW |
3587 | udelay(150); |
3588 | ||
0206e353 | 3589 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3590 | reg = FDI_TX_CTL(pipe); |
3591 | temp = I915_READ(reg); | |
8db9d77b ZW |
3592 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3593 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3594 | I915_WRITE(reg, temp); |
3595 | ||
3596 | POSTING_READ(reg); | |
8db9d77b ZW |
3597 | udelay(500); |
3598 | ||
fa37d39e SP |
3599 | for (retry = 0; retry < 5; retry++) { |
3600 | reg = FDI_RX_IIR(pipe); | |
3601 | temp = I915_READ(reg); | |
3602 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3603 | if (temp & FDI_RX_BIT_LOCK) { | |
3604 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3605 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3606 | break; | |
3607 | } | |
3608 | udelay(50); | |
8db9d77b | 3609 | } |
fa37d39e SP |
3610 | if (retry < 5) |
3611 | break; | |
8db9d77b ZW |
3612 | } |
3613 | if (i == 4) | |
5eddb70b | 3614 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3615 | |
3616 | /* Train 2 */ | |
5eddb70b CW |
3617 | reg = FDI_TX_CTL(pipe); |
3618 | temp = I915_READ(reg); | |
8db9d77b ZW |
3619 | temp &= ~FDI_LINK_TRAIN_NONE; |
3620 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3621 | if (IS_GEN6(dev)) { | |
3622 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3623 | /* SNB-B */ | |
3624 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3625 | } | |
5eddb70b | 3626 | I915_WRITE(reg, temp); |
8db9d77b | 3627 | |
5eddb70b CW |
3628 | reg = FDI_RX_CTL(pipe); |
3629 | temp = I915_READ(reg); | |
8db9d77b ZW |
3630 | if (HAS_PCH_CPT(dev)) { |
3631 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3632 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3633 | } else { | |
3634 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3635 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3636 | } | |
5eddb70b CW |
3637 | I915_WRITE(reg, temp); |
3638 | ||
3639 | POSTING_READ(reg); | |
8db9d77b ZW |
3640 | udelay(150); |
3641 | ||
0206e353 | 3642 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3643 | reg = FDI_TX_CTL(pipe); |
3644 | temp = I915_READ(reg); | |
8db9d77b ZW |
3645 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3646 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3647 | I915_WRITE(reg, temp); |
3648 | ||
3649 | POSTING_READ(reg); | |
8db9d77b ZW |
3650 | udelay(500); |
3651 | ||
fa37d39e SP |
3652 | for (retry = 0; retry < 5; retry++) { |
3653 | reg = FDI_RX_IIR(pipe); | |
3654 | temp = I915_READ(reg); | |
3655 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3656 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3657 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3658 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3659 | break; | |
3660 | } | |
3661 | udelay(50); | |
8db9d77b | 3662 | } |
fa37d39e SP |
3663 | if (retry < 5) |
3664 | break; | |
8db9d77b ZW |
3665 | } |
3666 | if (i == 4) | |
5eddb70b | 3667 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3668 | |
3669 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3670 | } | |
3671 | ||
357555c0 JB |
3672 | /* Manual link training for Ivy Bridge A0 parts */ |
3673 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3674 | { | |
3675 | struct drm_device *dev = crtc->dev; | |
3676 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3677 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3678 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3679 | u32 reg, temp, i, j; |
357555c0 JB |
3680 | |
3681 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3682 | for train result */ | |
3683 | reg = FDI_RX_IMR(pipe); | |
3684 | temp = I915_READ(reg); | |
3685 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3686 | temp &= ~FDI_RX_BIT_LOCK; | |
3687 | I915_WRITE(reg, temp); | |
3688 | ||
3689 | POSTING_READ(reg); | |
3690 | udelay(150); | |
3691 | ||
01a415fd DV |
3692 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3693 | I915_READ(FDI_RX_IIR(pipe))); | |
3694 | ||
139ccd3f JB |
3695 | /* Try each vswing and preemphasis setting twice before moving on */ |
3696 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3697 | /* disable first in case we need to retry */ | |
3698 | reg = FDI_TX_CTL(pipe); | |
3699 | temp = I915_READ(reg); | |
3700 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3701 | temp &= ~FDI_TX_ENABLE; | |
3702 | I915_WRITE(reg, temp); | |
357555c0 | 3703 | |
139ccd3f JB |
3704 | reg = FDI_RX_CTL(pipe); |
3705 | temp = I915_READ(reg); | |
3706 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3707 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3708 | temp &= ~FDI_RX_ENABLE; | |
3709 | I915_WRITE(reg, temp); | |
357555c0 | 3710 | |
139ccd3f | 3711 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3712 | reg = FDI_TX_CTL(pipe); |
3713 | temp = I915_READ(reg); | |
139ccd3f | 3714 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3715 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3716 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3717 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3718 | temp |= snb_b_fdi_train_param[j/2]; |
3719 | temp |= FDI_COMPOSITE_SYNC; | |
3720 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3721 | |
139ccd3f JB |
3722 | I915_WRITE(FDI_RX_MISC(pipe), |
3723 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3724 | |
139ccd3f | 3725 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3726 | temp = I915_READ(reg); |
139ccd3f JB |
3727 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3728 | temp |= FDI_COMPOSITE_SYNC; | |
3729 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3730 | |
139ccd3f JB |
3731 | POSTING_READ(reg); |
3732 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3733 | |
139ccd3f JB |
3734 | for (i = 0; i < 4; i++) { |
3735 | reg = FDI_RX_IIR(pipe); | |
3736 | temp = I915_READ(reg); | |
3737 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3738 | |
139ccd3f JB |
3739 | if (temp & FDI_RX_BIT_LOCK || |
3740 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3741 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3742 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3743 | i); | |
3744 | break; | |
3745 | } | |
3746 | udelay(1); /* should be 0.5us */ | |
3747 | } | |
3748 | if (i == 4) { | |
3749 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3750 | continue; | |
3751 | } | |
357555c0 | 3752 | |
139ccd3f | 3753 | /* Train 2 */ |
357555c0 JB |
3754 | reg = FDI_TX_CTL(pipe); |
3755 | temp = I915_READ(reg); | |
139ccd3f JB |
3756 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3757 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3758 | I915_WRITE(reg, temp); | |
3759 | ||
3760 | reg = FDI_RX_CTL(pipe); | |
3761 | temp = I915_READ(reg); | |
3762 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3763 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3764 | I915_WRITE(reg, temp); |
3765 | ||
3766 | POSTING_READ(reg); | |
139ccd3f | 3767 | udelay(2); /* should be 1.5us */ |
357555c0 | 3768 | |
139ccd3f JB |
3769 | for (i = 0; i < 4; i++) { |
3770 | reg = FDI_RX_IIR(pipe); | |
3771 | temp = I915_READ(reg); | |
3772 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3773 | |
139ccd3f JB |
3774 | if (temp & FDI_RX_SYMBOL_LOCK || |
3775 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3776 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3777 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3778 | i); | |
3779 | goto train_done; | |
3780 | } | |
3781 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3782 | } |
139ccd3f JB |
3783 | if (i == 4) |
3784 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3785 | } |
357555c0 | 3786 | |
139ccd3f | 3787 | train_done: |
357555c0 JB |
3788 | DRM_DEBUG_KMS("FDI train done.\n"); |
3789 | } | |
3790 | ||
88cefb6c | 3791 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3792 | { |
88cefb6c | 3793 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3794 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3795 | int pipe = intel_crtc->pipe; |
5eddb70b | 3796 | u32 reg, temp; |
79e53945 | 3797 | |
c64e311e | 3798 | |
c98e9dcf | 3799 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3800 | reg = FDI_RX_CTL(pipe); |
3801 | temp = I915_READ(reg); | |
627eb5a3 | 3802 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3803 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3804 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3805 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3806 | ||
3807 | POSTING_READ(reg); | |
c98e9dcf JB |
3808 | udelay(200); |
3809 | ||
3810 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3811 | temp = I915_READ(reg); |
3812 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3813 | ||
3814 | POSTING_READ(reg); | |
c98e9dcf JB |
3815 | udelay(200); |
3816 | ||
20749730 PZ |
3817 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3818 | reg = FDI_TX_CTL(pipe); | |
3819 | temp = I915_READ(reg); | |
3820 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3821 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3822 | |
20749730 PZ |
3823 | POSTING_READ(reg); |
3824 | udelay(100); | |
6be4a607 | 3825 | } |
0e23b99d JB |
3826 | } |
3827 | ||
88cefb6c DV |
3828 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3829 | { | |
3830 | struct drm_device *dev = intel_crtc->base.dev; | |
3831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3832 | int pipe = intel_crtc->pipe; | |
3833 | u32 reg, temp; | |
3834 | ||
3835 | /* Switch from PCDclk to Rawclk */ | |
3836 | reg = FDI_RX_CTL(pipe); | |
3837 | temp = I915_READ(reg); | |
3838 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3839 | ||
3840 | /* Disable CPU FDI TX PLL */ | |
3841 | reg = FDI_TX_CTL(pipe); | |
3842 | temp = I915_READ(reg); | |
3843 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3844 | ||
3845 | POSTING_READ(reg); | |
3846 | udelay(100); | |
3847 | ||
3848 | reg = FDI_RX_CTL(pipe); | |
3849 | temp = I915_READ(reg); | |
3850 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3851 | ||
3852 | /* Wait for the clocks to turn off. */ | |
3853 | POSTING_READ(reg); | |
3854 | udelay(100); | |
3855 | } | |
3856 | ||
0fc932b8 JB |
3857 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3858 | { | |
3859 | struct drm_device *dev = crtc->dev; | |
3860 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3861 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3862 | int pipe = intel_crtc->pipe; | |
3863 | u32 reg, temp; | |
3864 | ||
3865 | /* disable CPU FDI tx and PCH FDI rx */ | |
3866 | reg = FDI_TX_CTL(pipe); | |
3867 | temp = I915_READ(reg); | |
3868 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3869 | POSTING_READ(reg); | |
3870 | ||
3871 | reg = FDI_RX_CTL(pipe); | |
3872 | temp = I915_READ(reg); | |
3873 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3874 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3875 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3876 | ||
3877 | POSTING_READ(reg); | |
3878 | udelay(100); | |
3879 | ||
3880 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3881 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3882 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3883 | |
3884 | /* still set train pattern 1 */ | |
3885 | reg = FDI_TX_CTL(pipe); | |
3886 | temp = I915_READ(reg); | |
3887 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3888 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3889 | I915_WRITE(reg, temp); | |
3890 | ||
3891 | reg = FDI_RX_CTL(pipe); | |
3892 | temp = I915_READ(reg); | |
3893 | if (HAS_PCH_CPT(dev)) { | |
3894 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3895 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3896 | } else { | |
3897 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3898 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3899 | } | |
3900 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3901 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3902 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3903 | I915_WRITE(reg, temp); |
3904 | ||
3905 | POSTING_READ(reg); | |
3906 | udelay(100); | |
3907 | } | |
3908 | ||
5dce5b93 CW |
3909 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3910 | { | |
3911 | struct intel_crtc *crtc; | |
3912 | ||
3913 | /* Note that we don't need to be called with mode_config.lock here | |
3914 | * as our list of CRTC objects is static for the lifetime of the | |
3915 | * device and so cannot disappear as we iterate. Similarly, we can | |
3916 | * happily treat the predicates as racy, atomic checks as userspace | |
3917 | * cannot claim and pin a new fb without at least acquring the | |
3918 | * struct_mutex and so serialising with us. | |
3919 | */ | |
d3fcc808 | 3920 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3921 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3922 | continue; | |
3923 | ||
3924 | if (crtc->unpin_work) | |
3925 | intel_wait_for_vblank(dev, crtc->pipe); | |
3926 | ||
3927 | return true; | |
3928 | } | |
3929 | ||
3930 | return false; | |
3931 | } | |
3932 | ||
d6bbafa1 CW |
3933 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3934 | { | |
3935 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3936 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3937 | ||
3938 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3939 | smp_rmb(); | |
3940 | intel_crtc->unpin_work = NULL; | |
3941 | ||
3942 | if (work->event) | |
3943 | drm_send_vblank_event(intel_crtc->base.dev, | |
3944 | intel_crtc->pipe, | |
3945 | work->event); | |
3946 | ||
3947 | drm_crtc_vblank_put(&intel_crtc->base); | |
3948 | ||
3949 | wake_up_all(&dev_priv->pending_flip_queue); | |
3950 | queue_work(dev_priv->wq, &work->work); | |
3951 | ||
3952 | trace_i915_flip_complete(intel_crtc->plane, | |
3953 | work->pending_flip_obj); | |
3954 | } | |
3955 | ||
46a55d30 | 3956 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3957 | { |
0f91128d | 3958 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3959 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3960 | |
2c10d571 | 3961 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3962 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3963 | !intel_crtc_has_pending_flip(crtc), | |
3964 | 60*HZ) == 0)) { | |
3965 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3966 | |
5e2d7afc | 3967 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3968 | if (intel_crtc->unpin_work) { |
3969 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3970 | page_flip_completed(intel_crtc); | |
3971 | } | |
5e2d7afc | 3972 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3973 | } |
5bb61643 | 3974 | |
975d568a CW |
3975 | if (crtc->primary->fb) { |
3976 | mutex_lock(&dev->struct_mutex); | |
3977 | intel_finish_fb(crtc->primary->fb); | |
3978 | mutex_unlock(&dev->struct_mutex); | |
3979 | } | |
e6c3a2a6 CW |
3980 | } |
3981 | ||
e615efe4 ED |
3982 | /* Program iCLKIP clock to the desired frequency */ |
3983 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3984 | { | |
3985 | struct drm_device *dev = crtc->dev; | |
3986 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3987 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3988 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3989 | u32 temp; | |
3990 | ||
a580516d | 3991 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 3992 | |
e615efe4 ED |
3993 | /* It is necessary to ungate the pixclk gate prior to programming |
3994 | * the divisors, and gate it back when it is done. | |
3995 | */ | |
3996 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3997 | ||
3998 | /* Disable SSCCTL */ | |
3999 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
4000 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
4001 | SBI_SSCCTL_DISABLE, | |
4002 | SBI_ICLK); | |
e615efe4 ED |
4003 | |
4004 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 4005 | if (clock == 20000) { |
e615efe4 ED |
4006 | auxdiv = 1; |
4007 | divsel = 0x41; | |
4008 | phaseinc = 0x20; | |
4009 | } else { | |
4010 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
4011 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
4012 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
4013 | * convert the virtual clock precision to KHz here for higher |
4014 | * precision. | |
4015 | */ | |
4016 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4017 | u32 iclk_pi_range = 64; | |
4018 | u32 desired_divisor, msb_divisor_value, pi_value; | |
4019 | ||
12d7ceed | 4020 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
4021 | msb_divisor_value = desired_divisor / iclk_pi_range; |
4022 | pi_value = desired_divisor % iclk_pi_range; | |
4023 | ||
4024 | auxdiv = 0; | |
4025 | divsel = msb_divisor_value - 2; | |
4026 | phaseinc = pi_value; | |
4027 | } | |
4028 | ||
4029 | /* This should not happen with any sane values */ | |
4030 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4031 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4032 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4033 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4034 | ||
4035 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4036 | clock, |
e615efe4 ED |
4037 | auxdiv, |
4038 | divsel, | |
4039 | phasedir, | |
4040 | phaseinc); | |
4041 | ||
4042 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 4043 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4044 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4045 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4046 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4047 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4048 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4049 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4050 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4051 | |
4052 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4053 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4054 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4055 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4056 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4057 | |
4058 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4059 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4060 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4061 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
4062 | |
4063 | /* Wait for initialization time */ | |
4064 | udelay(24); | |
4065 | ||
4066 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 | 4067 | |
a580516d | 4068 | mutex_unlock(&dev_priv->sb_lock); |
e615efe4 ED |
4069 | } |
4070 | ||
275f01b2 DV |
4071 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4072 | enum pipe pch_transcoder) | |
4073 | { | |
4074 | struct drm_device *dev = crtc->base.dev; | |
4075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4076 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4077 | |
4078 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4079 | I915_READ(HTOTAL(cpu_transcoder))); | |
4080 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4081 | I915_READ(HBLANK(cpu_transcoder))); | |
4082 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4083 | I915_READ(HSYNC(cpu_transcoder))); | |
4084 | ||
4085 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4086 | I915_READ(VTOTAL(cpu_transcoder))); | |
4087 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4088 | I915_READ(VBLANK(cpu_transcoder))); | |
4089 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4090 | I915_READ(VSYNC(cpu_transcoder))); | |
4091 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4092 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4093 | } | |
4094 | ||
003632d9 | 4095 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4096 | { |
4097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4098 | uint32_t temp; | |
4099 | ||
4100 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4101 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4102 | return; |
4103 | ||
4104 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4105 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4106 | ||
003632d9 ACO |
4107 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4108 | if (enable) | |
4109 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4110 | ||
4111 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4112 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4113 | POSTING_READ(SOUTH_CHICKEN1); | |
4114 | } | |
4115 | ||
4116 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4117 | { | |
4118 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4119 | |
4120 | switch (intel_crtc->pipe) { | |
4121 | case PIPE_A: | |
4122 | break; | |
4123 | case PIPE_B: | |
6e3c9717 | 4124 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4125 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4126 | else |
003632d9 | 4127 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4128 | |
4129 | break; | |
4130 | case PIPE_C: | |
003632d9 | 4131 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4132 | |
4133 | break; | |
4134 | default: | |
4135 | BUG(); | |
4136 | } | |
4137 | } | |
4138 | ||
f67a559d JB |
4139 | /* |
4140 | * Enable PCH resources required for PCH ports: | |
4141 | * - PCH PLLs | |
4142 | * - FDI training & RX/TX | |
4143 | * - update transcoder timings | |
4144 | * - DP transcoding bits | |
4145 | * - transcoder | |
4146 | */ | |
4147 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4148 | { |
4149 | struct drm_device *dev = crtc->dev; | |
4150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4151 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4152 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4153 | u32 reg, temp; |
2c07245f | 4154 | |
ab9412ba | 4155 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4156 | |
1fbc0d78 DV |
4157 | if (IS_IVYBRIDGE(dev)) |
4158 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4159 | ||
cd986abb DV |
4160 | /* Write the TU size bits before fdi link training, so that error |
4161 | * detection works. */ | |
4162 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4163 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4164 | ||
c98e9dcf | 4165 | /* For PCH output, training FDI link */ |
674cf967 | 4166 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4167 | |
3ad8a208 DV |
4168 | /* We need to program the right clock selection before writing the pixel |
4169 | * mutliplier into the DPLL. */ | |
303b81e0 | 4170 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4171 | u32 sel; |
4b645f14 | 4172 | |
c98e9dcf | 4173 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4174 | temp |= TRANS_DPLL_ENABLE(pipe); |
4175 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4176 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4177 | temp |= sel; |
4178 | else | |
4179 | temp &= ~sel; | |
c98e9dcf | 4180 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4181 | } |
5eddb70b | 4182 | |
3ad8a208 DV |
4183 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4184 | * transcoder, and we actually should do this to not upset any PCH | |
4185 | * transcoder that already use the clock when we share it. | |
4186 | * | |
4187 | * Note that enable_shared_dpll tries to do the right thing, but | |
4188 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4189 | * the right LVDS enable sequence. */ | |
85b3894f | 4190 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4191 | |
d9b6cb56 JB |
4192 | /* set transcoder timing, panel must allow it */ |
4193 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4194 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4195 | |
303b81e0 | 4196 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4197 | |
c98e9dcf | 4198 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4199 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4200 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4201 | reg = TRANS_DP_CTL(pipe); |
4202 | temp = I915_READ(reg); | |
4203 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4204 | TRANS_DP_SYNC_MASK | |
4205 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4206 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4207 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4208 | |
4209 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4210 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4211 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4212 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4213 | |
4214 | switch (intel_trans_dp_port_sel(crtc)) { | |
4215 | case PCH_DP_B: | |
5eddb70b | 4216 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4217 | break; |
4218 | case PCH_DP_C: | |
5eddb70b | 4219 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4220 | break; |
4221 | case PCH_DP_D: | |
5eddb70b | 4222 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4223 | break; |
4224 | default: | |
e95d41e1 | 4225 | BUG(); |
32f9d658 | 4226 | } |
2c07245f | 4227 | |
5eddb70b | 4228 | I915_WRITE(reg, temp); |
6be4a607 | 4229 | } |
b52eb4dc | 4230 | |
b8a4f404 | 4231 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4232 | } |
4233 | ||
1507e5bd PZ |
4234 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4235 | { | |
4236 | struct drm_device *dev = crtc->dev; | |
4237 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4238 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4239 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4240 | |
ab9412ba | 4241 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4242 | |
8c52b5e8 | 4243 | lpt_program_iclkip(crtc); |
1507e5bd | 4244 | |
0540e488 | 4245 | /* Set transcoder timing. */ |
275f01b2 | 4246 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4247 | |
937bb610 | 4248 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4249 | } |
4250 | ||
190f68c5 ACO |
4251 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4252 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4253 | { |
e2b78267 | 4254 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4255 | struct intel_shared_dpll *pll; |
de419ab6 | 4256 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4257 | enum intel_dpll_id i; |
ee7b9f93 | 4258 | |
de419ab6 ML |
4259 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4260 | ||
98b6bd99 DV |
4261 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4262 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4263 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4264 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4265 | |
46edb027 DV |
4266 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4267 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4268 | |
de419ab6 | 4269 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4270 | |
98b6bd99 DV |
4271 | goto found; |
4272 | } | |
4273 | ||
bcddf610 S |
4274 | if (IS_BROXTON(dev_priv->dev)) { |
4275 | /* PLL is attached to port in bxt */ | |
4276 | struct intel_encoder *encoder; | |
4277 | struct intel_digital_port *intel_dig_port; | |
4278 | ||
4279 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4280 | if (WARN_ON(!encoder)) | |
4281 | return NULL; | |
4282 | ||
4283 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4284 | /* 1:1 mapping between ports and PLLs */ | |
4285 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4286 | pll = &dev_priv->shared_dplls[i]; | |
4287 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4288 | crtc->base.base.id, pll->name); | |
de419ab6 | 4289 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4290 | |
4291 | goto found; | |
4292 | } | |
4293 | ||
e72f9fbf DV |
4294 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4295 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4296 | |
4297 | /* Only want to check enabled timings first */ | |
de419ab6 | 4298 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4299 | continue; |
4300 | ||
190f68c5 | 4301 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4302 | &shared_dpll[i].hw_state, |
4303 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4304 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4305 | crtc->base.base.id, pll->name, |
de419ab6 | 4306 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4307 | pll->active); |
ee7b9f93 JB |
4308 | goto found; |
4309 | } | |
4310 | } | |
4311 | ||
4312 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4313 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4314 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4315 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4316 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4317 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4318 | goto found; |
4319 | } | |
4320 | } | |
4321 | ||
4322 | return NULL; | |
4323 | ||
4324 | found: | |
de419ab6 ML |
4325 | if (shared_dpll[i].crtc_mask == 0) |
4326 | shared_dpll[i].hw_state = | |
4327 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4328 | |
190f68c5 | 4329 | crtc_state->shared_dpll = i; |
46edb027 DV |
4330 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4331 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4332 | |
de419ab6 | 4333 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4334 | |
ee7b9f93 JB |
4335 | return pll; |
4336 | } | |
4337 | ||
de419ab6 | 4338 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4339 | { |
de419ab6 ML |
4340 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4341 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4342 | struct intel_shared_dpll *pll; |
4343 | enum intel_dpll_id i; | |
4344 | ||
de419ab6 ML |
4345 | if (!to_intel_atomic_state(state)->dpll_set) |
4346 | return; | |
8bd31e67 | 4347 | |
de419ab6 | 4348 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4349 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4350 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4351 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4352 | } |
4353 | } | |
4354 | ||
a1520318 | 4355 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4356 | { |
4357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4358 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4359 | u32 temp; |
4360 | ||
4361 | temp = I915_READ(dslreg); | |
4362 | udelay(500); | |
4363 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4364 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4365 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4366 | } |
4367 | } | |
4368 | ||
86adf9d7 ML |
4369 | static int |
4370 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4371 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4372 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4373 | { |
86adf9d7 ML |
4374 | struct intel_crtc_scaler_state *scaler_state = |
4375 | &crtc_state->scaler_state; | |
4376 | struct intel_crtc *intel_crtc = | |
4377 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4378 | int need_scaling; |
6156a456 CK |
4379 | |
4380 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4381 | (src_h != dst_w || src_w != dst_h): | |
4382 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4383 | |
4384 | /* | |
4385 | * if plane is being disabled or scaler is no more required or force detach | |
4386 | * - free scaler binded to this plane/crtc | |
4387 | * - in order to do this, update crtc->scaler_usage | |
4388 | * | |
4389 | * Here scaler state in crtc_state is set free so that | |
4390 | * scaler can be assigned to other user. Actual register | |
4391 | * update to free the scaler is done in plane/panel-fit programming. | |
4392 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4393 | */ | |
86adf9d7 | 4394 | if (force_detach || !need_scaling) { |
a1b2278e | 4395 | if (*scaler_id >= 0) { |
86adf9d7 | 4396 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4397 | scaler_state->scalers[*scaler_id].in_use = 0; |
4398 | ||
86adf9d7 ML |
4399 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4400 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4401 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4402 | scaler_state->scaler_users); |
4403 | *scaler_id = -1; | |
4404 | } | |
4405 | return 0; | |
4406 | } | |
4407 | ||
4408 | /* range checks */ | |
4409 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4410 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4411 | ||
4412 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4413 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4414 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4415 | "size is out of scaler range\n", |
86adf9d7 | 4416 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4417 | return -EINVAL; |
4418 | } | |
4419 | ||
86adf9d7 ML |
4420 | /* mark this plane as a scaler user in crtc_state */ |
4421 | scaler_state->scaler_users |= (1 << scaler_user); | |
4422 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4423 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4424 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4425 | scaler_state->scaler_users); | |
4426 | ||
4427 | return 0; | |
4428 | } | |
4429 | ||
4430 | /** | |
4431 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4432 | * | |
4433 | * @state: crtc's scaler state | |
86adf9d7 ML |
4434 | * |
4435 | * Return | |
4436 | * 0 - scaler_usage updated successfully | |
4437 | * error - requested scaling cannot be supported or other error condition | |
4438 | */ | |
e435d6e5 | 4439 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4440 | { |
4441 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4442 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4443 | |
4444 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4445 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4446 | ||
e435d6e5 | 4447 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
86adf9d7 ML |
4448 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
4449 | state->pipe_src_w, state->pipe_src_h, | |
aad941d5 | 4450 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4451 | } |
4452 | ||
4453 | /** | |
4454 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4455 | * | |
4456 | * @state: crtc's scaler state | |
86adf9d7 ML |
4457 | * @plane_state: atomic plane state to update |
4458 | * | |
4459 | * Return | |
4460 | * 0 - scaler_usage updated successfully | |
4461 | * error - requested scaling cannot be supported or other error condition | |
4462 | */ | |
da20eabd ML |
4463 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4464 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4465 | { |
4466 | ||
4467 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4468 | struct intel_plane *intel_plane = |
4469 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4470 | struct drm_framebuffer *fb = plane_state->base.fb; |
4471 | int ret; | |
4472 | ||
4473 | bool force_detach = !fb || !plane_state->visible; | |
4474 | ||
4475 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4476 | intel_plane->base.base.id, intel_crtc->pipe, | |
4477 | drm_plane_index(&intel_plane->base)); | |
4478 | ||
4479 | ret = skl_update_scaler(crtc_state, force_detach, | |
4480 | drm_plane_index(&intel_plane->base), | |
4481 | &plane_state->scaler_id, | |
4482 | plane_state->base.rotation, | |
4483 | drm_rect_width(&plane_state->src) >> 16, | |
4484 | drm_rect_height(&plane_state->src) >> 16, | |
4485 | drm_rect_width(&plane_state->dst), | |
4486 | drm_rect_height(&plane_state->dst)); | |
4487 | ||
4488 | if (ret || plane_state->scaler_id < 0) | |
4489 | return ret; | |
4490 | ||
a1b2278e | 4491 | /* check colorkey */ |
818ed961 | 4492 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4493 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4494 | intel_plane->base.base.id); |
a1b2278e CK |
4495 | return -EINVAL; |
4496 | } | |
4497 | ||
4498 | /* Check src format */ | |
86adf9d7 ML |
4499 | switch (fb->pixel_format) { |
4500 | case DRM_FORMAT_RGB565: | |
4501 | case DRM_FORMAT_XBGR8888: | |
4502 | case DRM_FORMAT_XRGB8888: | |
4503 | case DRM_FORMAT_ABGR8888: | |
4504 | case DRM_FORMAT_ARGB8888: | |
4505 | case DRM_FORMAT_XRGB2101010: | |
4506 | case DRM_FORMAT_XBGR2101010: | |
4507 | case DRM_FORMAT_YUYV: | |
4508 | case DRM_FORMAT_YVYU: | |
4509 | case DRM_FORMAT_UYVY: | |
4510 | case DRM_FORMAT_VYUY: | |
4511 | break; | |
4512 | default: | |
4513 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4514 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4515 | return -EINVAL; | |
a1b2278e CK |
4516 | } |
4517 | ||
a1b2278e CK |
4518 | return 0; |
4519 | } | |
4520 | ||
e435d6e5 ML |
4521 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4522 | { | |
4523 | int i; | |
4524 | ||
4525 | for (i = 0; i < crtc->num_scalers; i++) | |
4526 | skl_detach_scaler(crtc, i); | |
4527 | } | |
4528 | ||
4529 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4530 | { |
4531 | struct drm_device *dev = crtc->base.dev; | |
4532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4533 | int pipe = crtc->pipe; | |
a1b2278e CK |
4534 | struct intel_crtc_scaler_state *scaler_state = |
4535 | &crtc->config->scaler_state; | |
4536 | ||
4537 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4538 | ||
6e3c9717 | 4539 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4540 | int id; |
4541 | ||
4542 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4543 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4544 | return; | |
4545 | } | |
4546 | ||
4547 | id = scaler_state->scaler_id; | |
4548 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4549 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4550 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4551 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4552 | ||
4553 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4554 | } |
4555 | } | |
4556 | ||
b074cec8 JB |
4557 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4558 | { | |
4559 | struct drm_device *dev = crtc->base.dev; | |
4560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4561 | int pipe = crtc->pipe; | |
4562 | ||
6e3c9717 | 4563 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4564 | /* Force use of hard-coded filter coefficients |
4565 | * as some pre-programmed values are broken, | |
4566 | * e.g. x201. | |
4567 | */ | |
4568 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4569 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4570 | PF_PIPE_SEL_IVB(pipe)); | |
4571 | else | |
4572 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4573 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4574 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4575 | } |
4576 | } | |
4577 | ||
20bc8673 | 4578 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4579 | { |
cea165c3 VS |
4580 | struct drm_device *dev = crtc->base.dev; |
4581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4582 | |
6e3c9717 | 4583 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4584 | return; |
4585 | ||
cea165c3 VS |
4586 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4587 | intel_wait_for_vblank(dev, crtc->pipe); | |
4588 | ||
d77e4531 | 4589 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4590 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4591 | mutex_lock(&dev_priv->rps.hw_lock); |
4592 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4593 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4594 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4595 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4596 | * mailbox." Moreover, the mailbox may return a bogus state, |
4597 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4598 | */ |
4599 | } else { | |
4600 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4601 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4602 | * is essentially intel_wait_for_vblank. If we don't have this | |
4603 | * and don't wait for vblanks until the end of crtc_enable, then | |
4604 | * the HW state readout code will complain that the expected | |
4605 | * IPS_CTL value is not the one we read. */ | |
4606 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4607 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4608 | } | |
d77e4531 PZ |
4609 | } |
4610 | ||
20bc8673 | 4611 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4612 | { |
4613 | struct drm_device *dev = crtc->base.dev; | |
4614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4615 | ||
6e3c9717 | 4616 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4617 | return; |
4618 | ||
4619 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4620 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4621 | mutex_lock(&dev_priv->rps.hw_lock); |
4622 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4623 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4624 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4625 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4626 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4627 | } else { |
2a114cc1 | 4628 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4629 | POSTING_READ(IPS_CTL); |
4630 | } | |
d77e4531 PZ |
4631 | |
4632 | /* We need to wait for a vblank before we can disable the plane. */ | |
4633 | intel_wait_for_vblank(dev, crtc->pipe); | |
4634 | } | |
4635 | ||
4636 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4637 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4638 | { | |
4639 | struct drm_device *dev = crtc->dev; | |
4640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4641 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4642 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4643 | int i; |
4644 | bool reenable_ips = false; | |
4645 | ||
4646 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4647 | if (!crtc->state->active) |
d77e4531 PZ |
4648 | return; |
4649 | ||
50360403 | 4650 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
409ee761 | 4651 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4652 | assert_dsi_pll_enabled(dev_priv); |
4653 | else | |
4654 | assert_pll_enabled(dev_priv, pipe); | |
4655 | } | |
4656 | ||
d77e4531 PZ |
4657 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4658 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4659 | */ | |
6e3c9717 | 4660 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4661 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4662 | GAMMA_MODE_MODE_SPLIT)) { | |
4663 | hsw_disable_ips(intel_crtc); | |
4664 | reenable_ips = true; | |
4665 | } | |
4666 | ||
4667 | for (i = 0; i < 256; i++) { | |
f65a9c5b VS |
4668 | u32 palreg; |
4669 | ||
4670 | if (HAS_GMCH_DISPLAY(dev)) | |
4671 | palreg = PALETTE(pipe, i); | |
4672 | else | |
4673 | palreg = LGC_PALETTE(pipe, i); | |
4674 | ||
4675 | I915_WRITE(palreg, | |
d77e4531 PZ |
4676 | (intel_crtc->lut_r[i] << 16) | |
4677 | (intel_crtc->lut_g[i] << 8) | | |
4678 | intel_crtc->lut_b[i]); | |
4679 | } | |
4680 | ||
4681 | if (reenable_ips) | |
4682 | hsw_enable_ips(intel_crtc); | |
4683 | } | |
4684 | ||
7cac945f | 4685 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4686 | { |
7cac945f | 4687 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4688 | struct drm_device *dev = intel_crtc->base.dev; |
4689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4690 | ||
4691 | mutex_lock(&dev->struct_mutex); | |
4692 | dev_priv->mm.interruptible = false; | |
4693 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4694 | dev_priv->mm.interruptible = true; | |
4695 | mutex_unlock(&dev->struct_mutex); | |
4696 | } | |
4697 | ||
4698 | /* Let userspace switch the overlay on again. In most cases userspace | |
4699 | * has to recompute where to put it anyway. | |
4700 | */ | |
4701 | } | |
4702 | ||
87d4300a ML |
4703 | /** |
4704 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4705 | * @crtc: the CRTC whose primary plane was just enabled | |
4706 | * | |
4707 | * Performs potentially sleeping operations that must be done after the primary | |
4708 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4709 | * called due to an explicit primary plane update, or due to an implicit | |
4710 | * re-enable that is caused when a sprite plane is updated to no longer | |
4711 | * completely hide the primary plane. | |
4712 | */ | |
4713 | static void | |
4714 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4715 | { |
4716 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4717 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4718 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4719 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4720 | |
87d4300a ML |
4721 | /* |
4722 | * BDW signals flip done immediately if the plane | |
4723 | * is disabled, even if the plane enable is already | |
4724 | * armed to occur at the next vblank :( | |
4725 | */ | |
4726 | if (IS_BROADWELL(dev)) | |
4727 | intel_wait_for_vblank(dev, pipe); | |
a5c4d7bc | 4728 | |
87d4300a ML |
4729 | /* |
4730 | * FIXME IPS should be fine as long as one plane is | |
4731 | * enabled, but in practice it seems to have problems | |
4732 | * when going from primary only to sprite only and vice | |
4733 | * versa. | |
4734 | */ | |
a5c4d7bc VS |
4735 | hsw_enable_ips(intel_crtc); |
4736 | ||
f99d7069 | 4737 | /* |
87d4300a ML |
4738 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4739 | * So don't enable underrun reporting before at least some planes | |
4740 | * are enabled. | |
4741 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4742 | * but leave the pipe running. | |
f99d7069 | 4743 | */ |
87d4300a ML |
4744 | if (IS_GEN2(dev)) |
4745 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4746 | ||
4747 | /* Underruns don't raise interrupts, so check manually. */ | |
4748 | if (HAS_GMCH_DISPLAY(dev)) | |
4749 | i9xx_check_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4750 | } |
4751 | ||
87d4300a ML |
4752 | /** |
4753 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4754 | * @crtc: the CRTC whose primary plane is to be disabled | |
4755 | * | |
4756 | * Performs potentially sleeping operations that must be done before the | |
4757 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4758 | * be called due to an explicit primary plane update, or due to an implicit | |
4759 | * disable that is caused when a sprite plane completely hides the primary | |
4760 | * plane. | |
4761 | */ | |
4762 | static void | |
4763 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4764 | { |
4765 | struct drm_device *dev = crtc->dev; | |
4766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4768 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4769 | |
87d4300a ML |
4770 | /* |
4771 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4772 | * So diasble underrun reporting before all the planes get disabled. | |
4773 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4774 | * but leave the pipe running. | |
4775 | */ | |
4776 | if (IS_GEN2(dev)) | |
4777 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4778 | |
87d4300a ML |
4779 | /* |
4780 | * Vblank time updates from the shadow to live plane control register | |
4781 | * are blocked if the memory self-refresh mode is active at that | |
4782 | * moment. So to make sure the plane gets truly disabled, disable | |
4783 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4784 | * will be checked/applied by the HW only at the next frame start | |
4785 | * event which is after the vblank start event, so we need to have a | |
4786 | * wait-for-vblank between disabling the plane and the pipe. | |
4787 | */ | |
262cd2e1 | 4788 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4789 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4790 | dev_priv->wm.vlv.cxsr = false; |
4791 | intel_wait_for_vblank(dev, pipe); | |
4792 | } | |
87d4300a | 4793 | |
87d4300a ML |
4794 | /* |
4795 | * FIXME IPS should be fine as long as one plane is | |
4796 | * enabled, but in practice it seems to have problems | |
4797 | * when going from primary only to sprite only and vice | |
4798 | * versa. | |
4799 | */ | |
a5c4d7bc | 4800 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4801 | } |
4802 | ||
ac21b225 ML |
4803 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4804 | { | |
4805 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
4806 | struct drm_device *dev = crtc->base.dev; | |
7733b49b | 4807 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 ML |
4808 | |
4809 | if (atomic->wait_vblank) | |
4810 | intel_wait_for_vblank(dev, crtc->pipe); | |
4811 | ||
4812 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4813 | ||
852eb00d VS |
4814 | if (atomic->disable_cxsr) |
4815 | crtc->wm.cxsr_allowed = true; | |
4816 | ||
f015c551 VS |
4817 | if (crtc->atomic.update_wm_post) |
4818 | intel_update_watermarks(&crtc->base); | |
4819 | ||
c80ac854 | 4820 | if (atomic->update_fbc) |
7733b49b | 4821 | intel_fbc_update(dev_priv); |
ac21b225 ML |
4822 | |
4823 | if (atomic->post_enable_primary) | |
4824 | intel_post_enable_primary(&crtc->base); | |
4825 | ||
ac21b225 ML |
4826 | memset(atomic, 0, sizeof(*atomic)); |
4827 | } | |
4828 | ||
4829 | static void intel_pre_plane_update(struct intel_crtc *crtc) | |
4830 | { | |
4831 | struct drm_device *dev = crtc->base.dev; | |
eddfcbcd | 4832 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 ML |
4833 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
4834 | struct drm_plane *p; | |
4835 | ||
4836 | /* Track fb's for any planes being disabled */ | |
ac21b225 ML |
4837 | drm_for_each_plane_mask(p, dev, atomic->disabled_planes) { |
4838 | struct intel_plane *plane = to_intel_plane(p); | |
ac21b225 ML |
4839 | |
4840 | mutex_lock(&dev->struct_mutex); | |
a9ff8714 VS |
4841 | i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL, |
4842 | plane->frontbuffer_bit); | |
ac21b225 ML |
4843 | mutex_unlock(&dev->struct_mutex); |
4844 | } | |
4845 | ||
4846 | if (atomic->wait_for_flips) | |
4847 | intel_crtc_wait_for_pending_flips(&crtc->base); | |
4848 | ||
c80ac854 | 4849 | if (atomic->disable_fbc) |
25ad93fd | 4850 | intel_fbc_disable_crtc(crtc); |
ac21b225 | 4851 | |
066cf55b RV |
4852 | if (crtc->atomic.disable_ips) |
4853 | hsw_disable_ips(crtc); | |
4854 | ||
ac21b225 ML |
4855 | if (atomic->pre_disable_primary) |
4856 | intel_pre_disable_primary(&crtc->base); | |
852eb00d VS |
4857 | |
4858 | if (atomic->disable_cxsr) { | |
4859 | crtc->wm.cxsr_allowed = false; | |
4860 | intel_set_memory_cxsr(dev_priv, false); | |
4861 | } | |
ac21b225 ML |
4862 | } |
4863 | ||
d032ffa0 | 4864 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4865 | { |
4866 | struct drm_device *dev = crtc->dev; | |
4867 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4868 | struct drm_plane *p; |
87d4300a ML |
4869 | int pipe = intel_crtc->pipe; |
4870 | ||
7cac945f | 4871 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4872 | |
d032ffa0 ML |
4873 | drm_for_each_plane_mask(p, dev, plane_mask) |
4874 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4875 | |
f99d7069 DV |
4876 | /* |
4877 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4878 | * to compute the mask of flip planes precisely. For the time being | |
4879 | * consider this a flip to a NULL plane. | |
4880 | */ | |
4881 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4882 | } |
4883 | ||
f67a559d JB |
4884 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4885 | { | |
4886 | struct drm_device *dev = crtc->dev; | |
4887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4888 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4889 | struct intel_encoder *encoder; |
f67a559d | 4890 | int pipe = intel_crtc->pipe; |
f67a559d | 4891 | |
53d9f4e9 | 4892 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4893 | return; |
4894 | ||
6e3c9717 | 4895 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4896 | intel_prepare_shared_dpll(intel_crtc); |
4897 | ||
6e3c9717 | 4898 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4899 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4900 | |
4901 | intel_set_pipe_timings(intel_crtc); | |
4902 | ||
6e3c9717 | 4903 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4904 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4905 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4906 | } |
4907 | ||
4908 | ironlake_set_pipeconf(crtc); | |
4909 | ||
f67a559d | 4910 | intel_crtc->active = true; |
8664281b | 4911 | |
a72e4c9f DV |
4912 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4913 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4914 | |
f6736a1a | 4915 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4916 | if (encoder->pre_enable) |
4917 | encoder->pre_enable(encoder); | |
f67a559d | 4918 | |
6e3c9717 | 4919 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4920 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4921 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4922 | * enabling. */ | |
88cefb6c | 4923 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4924 | } else { |
4925 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4926 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4927 | } | |
f67a559d | 4928 | |
b074cec8 | 4929 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4930 | |
9c54c0dd JB |
4931 | /* |
4932 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4933 | * clocks enabled | |
4934 | */ | |
4935 | intel_crtc_load_lut(crtc); | |
4936 | ||
f37fcc2a | 4937 | intel_update_watermarks(crtc); |
e1fdc473 | 4938 | intel_enable_pipe(intel_crtc); |
f67a559d | 4939 | |
6e3c9717 | 4940 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4941 | ironlake_pch_enable(crtc); |
c98e9dcf | 4942 | |
f9b61ff6 DV |
4943 | assert_vblank_disabled(crtc); |
4944 | drm_crtc_vblank_on(crtc); | |
4945 | ||
fa5c73b1 DV |
4946 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4947 | encoder->enable(encoder); | |
61b77ddd DV |
4948 | |
4949 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4950 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6be4a607 JB |
4951 | } |
4952 | ||
42db64ef PZ |
4953 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4954 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4955 | { | |
f5adf94e | 4956 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4957 | } |
4958 | ||
4f771f10 PZ |
4959 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4960 | { | |
4961 | struct drm_device *dev = crtc->dev; | |
4962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4963 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4964 | struct intel_encoder *encoder; | |
99d736a2 ML |
4965 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4966 | struct intel_crtc_state *pipe_config = | |
4967 | to_intel_crtc_state(crtc->state); | |
7d4aefd0 | 4968 | bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
4f771f10 | 4969 | |
53d9f4e9 | 4970 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4971 | return; |
4972 | ||
df8ad70c DV |
4973 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4974 | intel_enable_shared_dpll(intel_crtc); | |
4975 | ||
6e3c9717 | 4976 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4977 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4978 | |
4979 | intel_set_pipe_timings(intel_crtc); | |
4980 | ||
6e3c9717 ACO |
4981 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4982 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4983 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4984 | } |
4985 | ||
6e3c9717 | 4986 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4987 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4988 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4989 | } |
4990 | ||
4991 | haswell_set_pipeconf(crtc); | |
4992 | ||
4993 | intel_set_pipe_csc(crtc); | |
4994 | ||
4f771f10 | 4995 | intel_crtc->active = true; |
8664281b | 4996 | |
a72e4c9f | 4997 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
7d4aefd0 SS |
4998 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4999 | if (encoder->pre_pll_enable) | |
5000 | encoder->pre_pll_enable(encoder); | |
4f771f10 PZ |
5001 | if (encoder->pre_enable) |
5002 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5003 | } |
4f771f10 | 5004 | |
6e3c9717 | 5005 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
5006 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5007 | true); | |
4fe9467d ID |
5008 | dev_priv->display.fdi_link_train(crtc); |
5009 | } | |
5010 | ||
7d4aefd0 SS |
5011 | if (!is_dsi) |
5012 | intel_ddi_enable_pipe_clock(intel_crtc); | |
4f771f10 | 5013 | |
1c132b44 | 5014 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5015 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5016 | else |
1c132b44 | 5017 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5018 | |
5019 | /* | |
5020 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5021 | * clocks enabled | |
5022 | */ | |
5023 | intel_crtc_load_lut(crtc); | |
5024 | ||
1f544388 | 5025 | intel_ddi_set_pipe_settings(crtc); |
7d4aefd0 SS |
5026 | if (!is_dsi) |
5027 | intel_ddi_enable_transcoder_func(crtc); | |
4f771f10 | 5028 | |
f37fcc2a | 5029 | intel_update_watermarks(crtc); |
e1fdc473 | 5030 | intel_enable_pipe(intel_crtc); |
42db64ef | 5031 | |
6e3c9717 | 5032 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5033 | lpt_pch_enable(crtc); |
4f771f10 | 5034 | |
7d4aefd0 | 5035 | if (intel_crtc->config->dp_encoder_is_mst && !is_dsi) |
0e32b39c DA |
5036 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5037 | ||
f9b61ff6 DV |
5038 | assert_vblank_disabled(crtc); |
5039 | drm_crtc_vblank_on(crtc); | |
5040 | ||
8807e55b | 5041 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5042 | encoder->enable(encoder); |
8807e55b JN |
5043 | intel_opregion_notify_encoder(encoder, true); |
5044 | } | |
4f771f10 | 5045 | |
e4916946 PZ |
5046 | /* If we change the relative order between pipe/planes enabling, we need |
5047 | * to change the workaround. */ | |
99d736a2 ML |
5048 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5049 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5050 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5051 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5052 | } | |
4f771f10 PZ |
5053 | } |
5054 | ||
bfd16b2a | 5055 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5056 | { |
5057 | struct drm_device *dev = crtc->base.dev; | |
5058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5059 | int pipe = crtc->pipe; | |
5060 | ||
5061 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5062 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5063 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5064 | I915_WRITE(PF_CTL(pipe), 0); |
5065 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5066 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5067 | } | |
5068 | } | |
5069 | ||
6be4a607 JB |
5070 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5071 | { | |
5072 | struct drm_device *dev = crtc->dev; | |
5073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5074 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5075 | struct intel_encoder *encoder; |
6be4a607 | 5076 | int pipe = intel_crtc->pipe; |
5eddb70b | 5077 | u32 reg, temp; |
b52eb4dc | 5078 | |
ea9d758d DV |
5079 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5080 | encoder->disable(encoder); | |
5081 | ||
f9b61ff6 DV |
5082 | drm_crtc_vblank_off(crtc); |
5083 | assert_vblank_disabled(crtc); | |
5084 | ||
6e3c9717 | 5085 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 5086 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 5087 | |
575f7ab7 | 5088 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5089 | |
bfd16b2a | 5090 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5091 | |
5a74f70a VS |
5092 | if (intel_crtc->config->has_pch_encoder) |
5093 | ironlake_fdi_disable(crtc); | |
5094 | ||
bf49ec8c DV |
5095 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5096 | if (encoder->post_disable) | |
5097 | encoder->post_disable(encoder); | |
2c07245f | 5098 | |
6e3c9717 | 5099 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5100 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5101 | |
d925c59a DV |
5102 | if (HAS_PCH_CPT(dev)) { |
5103 | /* disable TRANS_DP_CTL */ | |
5104 | reg = TRANS_DP_CTL(pipe); | |
5105 | temp = I915_READ(reg); | |
5106 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5107 | TRANS_DP_PORT_SEL_MASK); | |
5108 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5109 | I915_WRITE(reg, temp); | |
5110 | ||
5111 | /* disable DPLL_SEL */ | |
5112 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5113 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5114 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5115 | } |
e3421a18 | 5116 | |
d925c59a DV |
5117 | ironlake_fdi_pll_disable(intel_crtc); |
5118 | } | |
6be4a607 | 5119 | } |
1b3c7a47 | 5120 | |
4f771f10 | 5121 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5122 | { |
4f771f10 PZ |
5123 | struct drm_device *dev = crtc->dev; |
5124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5125 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5126 | struct intel_encoder *encoder; |
6e3c9717 | 5127 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7d4aefd0 | 5128 | bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
ee7b9f93 | 5129 | |
8807e55b JN |
5130 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5131 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5132 | encoder->disable(encoder); |
8807e55b | 5133 | } |
4f771f10 | 5134 | |
f9b61ff6 DV |
5135 | drm_crtc_vblank_off(crtc); |
5136 | assert_vblank_disabled(crtc); | |
5137 | ||
6e3c9717 | 5138 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5139 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5140 | false); | |
575f7ab7 | 5141 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5142 | |
6e3c9717 | 5143 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5144 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5145 | ||
7d4aefd0 SS |
5146 | if (!is_dsi) |
5147 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); | |
4f771f10 | 5148 | |
1c132b44 | 5149 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5150 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5151 | else |
bfd16b2a | 5152 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5153 | |
7d4aefd0 SS |
5154 | if (!is_dsi) |
5155 | intel_ddi_disable_pipe_clock(intel_crtc); | |
4f771f10 | 5156 | |
6e3c9717 | 5157 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5158 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5159 | intel_ddi_fdi_disable(crtc); |
83616634 | 5160 | } |
4f771f10 | 5161 | |
97b040aa ID |
5162 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5163 | if (encoder->post_disable) | |
5164 | encoder->post_disable(encoder); | |
4f771f10 PZ |
5165 | } |
5166 | ||
2dd24552 JB |
5167 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5168 | { | |
5169 | struct drm_device *dev = crtc->base.dev; | |
5170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5171 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5172 | |
681a8504 | 5173 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5174 | return; |
5175 | ||
2dd24552 | 5176 | /* |
c0b03411 DV |
5177 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5178 | * according to register description and PRM. | |
2dd24552 | 5179 | */ |
c0b03411 DV |
5180 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5181 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5182 | |
b074cec8 JB |
5183 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5184 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5185 | |
5186 | /* Border color in case we don't scale up to the full screen. Black by | |
5187 | * default, change to something else for debugging. */ | |
5188 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5189 | } |
5190 | ||
d05410f9 DA |
5191 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5192 | { | |
5193 | switch (port) { | |
5194 | case PORT_A: | |
5195 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5196 | case PORT_B: | |
5197 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5198 | case PORT_C: | |
5199 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5200 | case PORT_D: | |
5201 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
d8e19f99 XZ |
5202 | case PORT_E: |
5203 | return POWER_DOMAIN_PORT_DDI_E_2_LANES; | |
d05410f9 DA |
5204 | default: |
5205 | WARN_ON_ONCE(1); | |
5206 | return POWER_DOMAIN_PORT_OTHER; | |
5207 | } | |
5208 | } | |
5209 | ||
77d22dca ID |
5210 | #define for_each_power_domain(domain, mask) \ |
5211 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5212 | if ((1 << (domain)) & (mask)) | |
5213 | ||
319be8ae ID |
5214 | enum intel_display_power_domain |
5215 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5216 | { | |
5217 | struct drm_device *dev = intel_encoder->base.dev; | |
5218 | struct intel_digital_port *intel_dig_port; | |
5219 | ||
5220 | switch (intel_encoder->type) { | |
5221 | case INTEL_OUTPUT_UNKNOWN: | |
5222 | /* Only DDI platforms should ever use this output type */ | |
5223 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5224 | case INTEL_OUTPUT_DISPLAYPORT: | |
5225 | case INTEL_OUTPUT_HDMI: | |
5226 | case INTEL_OUTPUT_EDP: | |
5227 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5228 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5229 | case INTEL_OUTPUT_DP_MST: |
5230 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5231 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5232 | case INTEL_OUTPUT_ANALOG: |
5233 | return POWER_DOMAIN_PORT_CRT; | |
5234 | case INTEL_OUTPUT_DSI: | |
5235 | return POWER_DOMAIN_PORT_DSI; | |
5236 | default: | |
5237 | return POWER_DOMAIN_PORT_OTHER; | |
5238 | } | |
5239 | } | |
5240 | ||
5241 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5242 | { |
319be8ae ID |
5243 | struct drm_device *dev = crtc->dev; |
5244 | struct intel_encoder *intel_encoder; | |
5245 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5246 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5247 | unsigned long mask; |
5248 | enum transcoder transcoder; | |
5249 | ||
292b990e ML |
5250 | if (!crtc->state->active) |
5251 | return 0; | |
5252 | ||
77d22dca ID |
5253 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); |
5254 | ||
5255 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5256 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5257 | if (intel_crtc->config->pch_pfit.enabled || |
5258 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5259 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5260 | ||
319be8ae ID |
5261 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5262 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5263 | ||
77d22dca ID |
5264 | return mask; |
5265 | } | |
5266 | ||
292b990e | 5267 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5268 | { |
292b990e ML |
5269 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5270 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5271 | enum intel_display_power_domain domain; | |
5272 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5273 | |
292b990e ML |
5274 | old_domains = intel_crtc->enabled_power_domains; |
5275 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5276 | |
292b990e ML |
5277 | domains = new_domains & ~old_domains; |
5278 | ||
5279 | for_each_power_domain(domain, domains) | |
5280 | intel_display_power_get(dev_priv, domain); | |
5281 | ||
5282 | return old_domains & ~new_domains; | |
5283 | } | |
5284 | ||
5285 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5286 | unsigned long domains) | |
5287 | { | |
5288 | enum intel_display_power_domain domain; | |
5289 | ||
5290 | for_each_power_domain(domain, domains) | |
5291 | intel_display_power_put(dev_priv, domain); | |
5292 | } | |
77d22dca | 5293 | |
292b990e ML |
5294 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5295 | { | |
5296 | struct drm_device *dev = state->dev; | |
5297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5298 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5299 | struct drm_crtc_state *crtc_state; | |
5300 | struct drm_crtc *crtc; | |
5301 | int i; | |
77d22dca | 5302 | |
292b990e ML |
5303 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5304 | if (needs_modeset(crtc->state)) | |
5305 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5306 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5307 | } |
5308 | ||
27c329ed ML |
5309 | if (dev_priv->display.modeset_commit_cdclk) { |
5310 | unsigned int cdclk = to_intel_atomic_state(state)->cdclk; | |
5311 | ||
5312 | if (cdclk != dev_priv->cdclk_freq && | |
5313 | !WARN_ON(!state->allow_modeset)) | |
5314 | dev_priv->display.modeset_commit_cdclk(state); | |
5315 | } | |
50f6e502 | 5316 | |
292b990e ML |
5317 | for (i = 0; i < I915_MAX_PIPES; i++) |
5318 | if (put_domains[i]) | |
5319 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5320 | } |
5321 | ||
adafdc6f MK |
5322 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5323 | { | |
5324 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5325 | ||
5326 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5327 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5328 | return max_cdclk_freq; | |
5329 | else if (IS_CHERRYVIEW(dev_priv)) | |
5330 | return max_cdclk_freq*95/100; | |
5331 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5332 | return 2*max_cdclk_freq*90/100; | |
5333 | else | |
5334 | return max_cdclk_freq*90/100; | |
5335 | } | |
5336 | ||
560a7ae4 DL |
5337 | static void intel_update_max_cdclk(struct drm_device *dev) |
5338 | { | |
5339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5340 | ||
5341 | if (IS_SKYLAKE(dev)) { | |
5342 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; | |
5343 | ||
5344 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5345 | dev_priv->max_cdclk_freq = 675000; | |
5346 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5347 | dev_priv->max_cdclk_freq = 540000; | |
5348 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5349 | dev_priv->max_cdclk_freq = 450000; | |
5350 | else | |
5351 | dev_priv->max_cdclk_freq = 337500; | |
5352 | } else if (IS_BROADWELL(dev)) { | |
5353 | /* | |
5354 | * FIXME with extra cooling we can allow | |
5355 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5356 | * How can we know if extra cooling is | |
5357 | * available? PCI ID, VTB, something else? | |
5358 | */ | |
5359 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5360 | dev_priv->max_cdclk_freq = 450000; | |
5361 | else if (IS_BDW_ULX(dev)) | |
5362 | dev_priv->max_cdclk_freq = 450000; | |
5363 | else if (IS_BDW_ULT(dev)) | |
5364 | dev_priv->max_cdclk_freq = 540000; | |
5365 | else | |
5366 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5367 | } else if (IS_CHERRYVIEW(dev)) { |
5368 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5369 | } else if (IS_VALLEYVIEW(dev)) { |
5370 | dev_priv->max_cdclk_freq = 400000; | |
5371 | } else { | |
5372 | /* otherwise assume cdclk is fixed */ | |
5373 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5374 | } | |
5375 | ||
adafdc6f MK |
5376 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5377 | ||
560a7ae4 DL |
5378 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5379 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5380 | |
5381 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5382 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5383 | } |
5384 | ||
5385 | static void intel_update_cdclk(struct drm_device *dev) | |
5386 | { | |
5387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5388 | ||
5389 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5390 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5391 | dev_priv->cdclk_freq); | |
5392 | ||
5393 | /* | |
5394 | * Program the gmbus_freq based on the cdclk frequency. | |
5395 | * BSpec erroneously claims we should aim for 4MHz, but | |
5396 | * in fact 1MHz is the correct frequency. | |
5397 | */ | |
5398 | if (IS_VALLEYVIEW(dev)) { | |
5399 | /* | |
5400 | * Program the gmbus_freq based on the cdclk frequency. | |
5401 | * BSpec erroneously claims we should aim for 4MHz, but | |
5402 | * in fact 1MHz is the correct frequency. | |
5403 | */ | |
5404 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5405 | } | |
5406 | ||
5407 | if (dev_priv->max_cdclk_freq == 0) | |
5408 | intel_update_max_cdclk(dev); | |
5409 | } | |
5410 | ||
70d0c574 | 5411 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5412 | { |
5413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5414 | uint32_t divider; | |
5415 | uint32_t ratio; | |
5416 | uint32_t current_freq; | |
5417 | int ret; | |
5418 | ||
5419 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5420 | switch (frequency) { | |
5421 | case 144000: | |
5422 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5423 | ratio = BXT_DE_PLL_RATIO(60); | |
5424 | break; | |
5425 | case 288000: | |
5426 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5427 | ratio = BXT_DE_PLL_RATIO(60); | |
5428 | break; | |
5429 | case 384000: | |
5430 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5431 | ratio = BXT_DE_PLL_RATIO(60); | |
5432 | break; | |
5433 | case 576000: | |
5434 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5435 | ratio = BXT_DE_PLL_RATIO(60); | |
5436 | break; | |
5437 | case 624000: | |
5438 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5439 | ratio = BXT_DE_PLL_RATIO(65); | |
5440 | break; | |
5441 | case 19200: | |
5442 | /* | |
5443 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5444 | * to suppress GCC warning. | |
5445 | */ | |
5446 | ratio = 0; | |
5447 | divider = 0; | |
5448 | break; | |
5449 | default: | |
5450 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5451 | ||
5452 | return; | |
5453 | } | |
5454 | ||
5455 | mutex_lock(&dev_priv->rps.hw_lock); | |
5456 | /* Inform power controller of upcoming frequency change */ | |
5457 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5458 | 0x80000000); | |
5459 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5460 | ||
5461 | if (ret) { | |
5462 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5463 | ret, frequency); | |
5464 | return; | |
5465 | } | |
5466 | ||
5467 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5468 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5469 | current_freq = current_freq * 500 + 1000; | |
5470 | ||
5471 | /* | |
5472 | * DE PLL has to be disabled when | |
5473 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5474 | * - before setting to 624MHz (PLL needs toggling) | |
5475 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5476 | */ | |
5477 | if (frequency == 19200 || frequency == 624000 || | |
5478 | current_freq == 624000) { | |
5479 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5480 | /* Timeout 200us */ | |
5481 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5482 | 1)) | |
5483 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5484 | } | |
5485 | ||
5486 | if (frequency != 19200) { | |
5487 | uint32_t val; | |
5488 | ||
5489 | val = I915_READ(BXT_DE_PLL_CTL); | |
5490 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5491 | val |= ratio; | |
5492 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5493 | ||
5494 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5495 | /* Timeout 200us */ | |
5496 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5497 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5498 | ||
5499 | val = I915_READ(CDCLK_CTL); | |
5500 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5501 | val |= divider; | |
5502 | /* | |
5503 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5504 | * enable otherwise. | |
5505 | */ | |
5506 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5507 | if (frequency >= 500000) | |
5508 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5509 | ||
5510 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5511 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5512 | val |= (frequency - 1000) / 500; | |
5513 | I915_WRITE(CDCLK_CTL, val); | |
5514 | } | |
5515 | ||
5516 | mutex_lock(&dev_priv->rps.hw_lock); | |
5517 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5518 | DIV_ROUND_UP(frequency, 25000)); | |
5519 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5520 | ||
5521 | if (ret) { | |
5522 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5523 | ret, frequency); | |
5524 | return; | |
5525 | } | |
5526 | ||
a47871bd | 5527 | intel_update_cdclk(dev); |
f8437dd1 VK |
5528 | } |
5529 | ||
5530 | void broxton_init_cdclk(struct drm_device *dev) | |
5531 | { | |
5532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5533 | uint32_t val; | |
5534 | ||
5535 | /* | |
5536 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5537 | * or else the reset will hang because there is no PCH to respond. | |
5538 | * Move the handshake programming to initialization sequence. | |
5539 | * Previously was left up to BIOS. | |
5540 | */ | |
5541 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5542 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5543 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5544 | ||
5545 | /* Enable PG1 for cdclk */ | |
5546 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5547 | ||
5548 | /* check if cd clock is enabled */ | |
5549 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5550 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5551 | return; | |
5552 | } | |
5553 | ||
5554 | /* | |
5555 | * FIXME: | |
5556 | * - The initial CDCLK needs to be read from VBT. | |
5557 | * Need to make this change after VBT has changes for BXT. | |
5558 | * - check if setting the max (or any) cdclk freq is really necessary | |
5559 | * here, it belongs to modeset time | |
5560 | */ | |
5561 | broxton_set_cdclk(dev, 624000); | |
5562 | ||
5563 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5564 | POSTING_READ(DBUF_CTL); |
5565 | ||
f8437dd1 VK |
5566 | udelay(10); |
5567 | ||
5568 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5569 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5570 | } | |
5571 | ||
5572 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5573 | { | |
5574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5575 | ||
5576 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5577 | POSTING_READ(DBUF_CTL); |
5578 | ||
f8437dd1 VK |
5579 | udelay(10); |
5580 | ||
5581 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5582 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5583 | ||
5584 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5585 | broxton_set_cdclk(dev, 19200); | |
5586 | ||
5587 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5588 | } | |
5589 | ||
5d96d8af DL |
5590 | static const struct skl_cdclk_entry { |
5591 | unsigned int freq; | |
5592 | unsigned int vco; | |
5593 | } skl_cdclk_frequencies[] = { | |
5594 | { .freq = 308570, .vco = 8640 }, | |
5595 | { .freq = 337500, .vco = 8100 }, | |
5596 | { .freq = 432000, .vco = 8640 }, | |
5597 | { .freq = 450000, .vco = 8100 }, | |
5598 | { .freq = 540000, .vco = 8100 }, | |
5599 | { .freq = 617140, .vco = 8640 }, | |
5600 | { .freq = 675000, .vco = 8100 }, | |
5601 | }; | |
5602 | ||
5603 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5604 | { | |
5605 | return (freq - 1000) / 500; | |
5606 | } | |
5607 | ||
5608 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5609 | { | |
5610 | unsigned int i; | |
5611 | ||
5612 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5613 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5614 | ||
5615 | if (e->freq == freq) | |
5616 | return e->vco; | |
5617 | } | |
5618 | ||
5619 | return 8100; | |
5620 | } | |
5621 | ||
5622 | static void | |
5623 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5624 | { | |
5625 | unsigned int min_freq; | |
5626 | u32 val; | |
5627 | ||
5628 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5629 | val = I915_READ(CDCLK_CTL); | |
5630 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5631 | val |= CDCLK_FREQ_337_308; | |
5632 | ||
5633 | if (required_vco == 8640) | |
5634 | min_freq = 308570; | |
5635 | else | |
5636 | min_freq = 337500; | |
5637 | ||
5638 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5639 | ||
5640 | I915_WRITE(CDCLK_CTL, val); | |
5641 | POSTING_READ(CDCLK_CTL); | |
5642 | ||
5643 | /* | |
5644 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5645 | * taking into account the VCO required to operate the eDP panel at the | |
5646 | * desired frequency. The usual DP link rates operate with a VCO of | |
5647 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5648 | * The modeset code is responsible for the selection of the exact link | |
5649 | * rate later on, with the constraint of choosing a frequency that | |
5650 | * works with required_vco. | |
5651 | */ | |
5652 | val = I915_READ(DPLL_CTRL1); | |
5653 | ||
5654 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5655 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5656 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5657 | if (required_vco == 8640) | |
5658 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5659 | SKL_DPLL0); | |
5660 | else | |
5661 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5662 | SKL_DPLL0); | |
5663 | ||
5664 | I915_WRITE(DPLL_CTRL1, val); | |
5665 | POSTING_READ(DPLL_CTRL1); | |
5666 | ||
5667 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5668 | ||
5669 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5670 | DRM_ERROR("DPLL0 not locked\n"); | |
5671 | } | |
5672 | ||
5673 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5674 | { | |
5675 | int ret; | |
5676 | u32 val; | |
5677 | ||
5678 | /* inform PCU we want to change CDCLK */ | |
5679 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5680 | mutex_lock(&dev_priv->rps.hw_lock); | |
5681 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5682 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5683 | ||
5684 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5685 | } | |
5686 | ||
5687 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5688 | { | |
5689 | unsigned int i; | |
5690 | ||
5691 | for (i = 0; i < 15; i++) { | |
5692 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5693 | return true; | |
5694 | udelay(10); | |
5695 | } | |
5696 | ||
5697 | return false; | |
5698 | } | |
5699 | ||
5700 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5701 | { | |
560a7ae4 | 5702 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5703 | u32 freq_select, pcu_ack; |
5704 | ||
5705 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5706 | ||
5707 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5708 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5709 | return; | |
5710 | } | |
5711 | ||
5712 | /* set CDCLK_CTL */ | |
5713 | switch(freq) { | |
5714 | case 450000: | |
5715 | case 432000: | |
5716 | freq_select = CDCLK_FREQ_450_432; | |
5717 | pcu_ack = 1; | |
5718 | break; | |
5719 | case 540000: | |
5720 | freq_select = CDCLK_FREQ_540; | |
5721 | pcu_ack = 2; | |
5722 | break; | |
5723 | case 308570: | |
5724 | case 337500: | |
5725 | default: | |
5726 | freq_select = CDCLK_FREQ_337_308; | |
5727 | pcu_ack = 0; | |
5728 | break; | |
5729 | case 617140: | |
5730 | case 675000: | |
5731 | freq_select = CDCLK_FREQ_675_617; | |
5732 | pcu_ack = 3; | |
5733 | break; | |
5734 | } | |
5735 | ||
5736 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5737 | POSTING_READ(CDCLK_CTL); | |
5738 | ||
5739 | /* inform PCU of the change */ | |
5740 | mutex_lock(&dev_priv->rps.hw_lock); | |
5741 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5742 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5743 | |
5744 | intel_update_cdclk(dev); | |
5d96d8af DL |
5745 | } |
5746 | ||
5747 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5748 | { | |
5749 | /* disable DBUF power */ | |
5750 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5751 | POSTING_READ(DBUF_CTL); | |
5752 | ||
5753 | udelay(10); | |
5754 | ||
5755 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5756 | DRM_ERROR("DBuf power disable timeout\n"); | |
5757 | ||
4e961e42 AM |
5758 | /* |
5759 | * DMC assumes ownership of LCPLL and will get confused if we touch it. | |
5760 | */ | |
5761 | if (dev_priv->csr.dmc_payload) { | |
5762 | /* disable DPLL0 */ | |
5763 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & | |
5764 | ~LCPLL_PLL_ENABLE); | |
5765 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5766 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5767 | } | |
5d96d8af DL |
5768 | |
5769 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5770 | } | |
5771 | ||
5772 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5773 | { | |
5774 | u32 val; | |
5775 | unsigned int required_vco; | |
5776 | ||
5777 | /* enable PCH reset handshake */ | |
5778 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5779 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); | |
5780 | ||
5781 | /* enable PG1 and Misc I/O */ | |
5782 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5783 | ||
39d9b85a GW |
5784 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5785 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5786 | /* enable DPLL0 */ | |
5787 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5788 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5789 | } |
5790 | ||
5d96d8af DL |
5791 | /* set CDCLK to the frequency the BIOS chose */ |
5792 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5793 | ||
5794 | /* enable DBUF power */ | |
5795 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5796 | POSTING_READ(DBUF_CTL); | |
5797 | ||
5798 | udelay(10); | |
5799 | ||
5800 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5801 | DRM_ERROR("DBuf power enable timeout\n"); | |
5802 | } | |
5803 | ||
30a970c6 JB |
5804 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5805 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5806 | { | |
5807 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5808 | u32 val, cmd; | |
5809 | ||
164dfd28 VK |
5810 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5811 | != dev_priv->cdclk_freq); | |
d60c4473 | 5812 | |
dfcab17e | 5813 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5814 | cmd = 2; |
dfcab17e | 5815 | else if (cdclk == 266667) |
30a970c6 JB |
5816 | cmd = 1; |
5817 | else | |
5818 | cmd = 0; | |
5819 | ||
5820 | mutex_lock(&dev_priv->rps.hw_lock); | |
5821 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5822 | val &= ~DSPFREQGUAR_MASK; | |
5823 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5824 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5825 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5826 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5827 | 50)) { | |
5828 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5829 | } | |
5830 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5831 | ||
54433e91 VS |
5832 | mutex_lock(&dev_priv->sb_lock); |
5833 | ||
dfcab17e | 5834 | if (cdclk == 400000) { |
6bcda4f0 | 5835 | u32 divider; |
30a970c6 | 5836 | |
6bcda4f0 | 5837 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5838 | |
30a970c6 JB |
5839 | /* adjust cdclk divider */ |
5840 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5841 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5842 | val |= divider; |
5843 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5844 | |
5845 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5846 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5847 | 50)) |
5848 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5849 | } |
5850 | ||
30a970c6 JB |
5851 | /* adjust self-refresh exit latency value */ |
5852 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5853 | val &= ~0x7f; | |
5854 | ||
5855 | /* | |
5856 | * For high bandwidth configs, we set a higher latency in the bunit | |
5857 | * so that the core display fetch happens in time to avoid underruns. | |
5858 | */ | |
dfcab17e | 5859 | if (cdclk == 400000) |
30a970c6 JB |
5860 | val |= 4500 / 250; /* 4.5 usec */ |
5861 | else | |
5862 | val |= 3000 / 250; /* 3.0 usec */ | |
5863 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5864 | |
a580516d | 5865 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5866 | |
b6283055 | 5867 | intel_update_cdclk(dev); |
30a970c6 JB |
5868 | } |
5869 | ||
383c5a6a VS |
5870 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5871 | { | |
5872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5873 | u32 val, cmd; | |
5874 | ||
164dfd28 VK |
5875 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5876 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5877 | |
5878 | switch (cdclk) { | |
383c5a6a VS |
5879 | case 333333: |
5880 | case 320000: | |
383c5a6a | 5881 | case 266667: |
383c5a6a | 5882 | case 200000: |
383c5a6a VS |
5883 | break; |
5884 | default: | |
5f77eeb0 | 5885 | MISSING_CASE(cdclk); |
383c5a6a VS |
5886 | return; |
5887 | } | |
5888 | ||
9d0d3fda VS |
5889 | /* |
5890 | * Specs are full of misinformation, but testing on actual | |
5891 | * hardware has shown that we just need to write the desired | |
5892 | * CCK divider into the Punit register. | |
5893 | */ | |
5894 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5895 | ||
383c5a6a VS |
5896 | mutex_lock(&dev_priv->rps.hw_lock); |
5897 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5898 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5899 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5900 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5901 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5902 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5903 | 50)) { | |
5904 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5905 | } | |
5906 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5907 | ||
b6283055 | 5908 | intel_update_cdclk(dev); |
383c5a6a VS |
5909 | } |
5910 | ||
30a970c6 JB |
5911 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5912 | int max_pixclk) | |
5913 | { | |
6bcda4f0 | 5914 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5915 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5916 | |
30a970c6 JB |
5917 | /* |
5918 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5919 | * 200MHz | |
5920 | * 267MHz | |
29dc7ef3 | 5921 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5922 | * 400MHz (VLV only) |
5923 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5924 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5925 | * |
5926 | * We seem to get an unstable or solid color picture at 200MHz. | |
5927 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5928 | * are off. | |
30a970c6 | 5929 | */ |
6cca3195 VS |
5930 | if (!IS_CHERRYVIEW(dev_priv) && |
5931 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5932 | return 400000; |
6cca3195 | 5933 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5934 | return freq_320; |
e37c67a1 | 5935 | else if (max_pixclk > 0) |
dfcab17e | 5936 | return 266667; |
e37c67a1 VS |
5937 | else |
5938 | return 200000; | |
30a970c6 JB |
5939 | } |
5940 | ||
f8437dd1 VK |
5941 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5942 | int max_pixclk) | |
5943 | { | |
5944 | /* | |
5945 | * FIXME: | |
5946 | * - remove the guardband, it's not needed on BXT | |
5947 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5948 | */ | |
5949 | if (max_pixclk > 576000*9/10) | |
5950 | return 624000; | |
5951 | else if (max_pixclk > 384000*9/10) | |
5952 | return 576000; | |
5953 | else if (max_pixclk > 288000*9/10) | |
5954 | return 384000; | |
5955 | else if (max_pixclk > 144000*9/10) | |
5956 | return 288000; | |
5957 | else | |
5958 | return 144000; | |
5959 | } | |
5960 | ||
a821fc46 ACO |
5961 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
5962 | * that's non-NULL, look at current state otherwise. */ | |
5963 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
5964 | struct drm_atomic_state *state) | |
30a970c6 | 5965 | { |
30a970c6 | 5966 | struct intel_crtc *intel_crtc; |
304603f4 | 5967 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5968 | int max_pixclk = 0; |
5969 | ||
d3fcc808 | 5970 | for_each_intel_crtc(dev, intel_crtc) { |
27c329ed | 5971 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
304603f4 ACO |
5972 | if (IS_ERR(crtc_state)) |
5973 | return PTR_ERR(crtc_state); | |
5974 | ||
5975 | if (!crtc_state->base.enable) | |
5976 | continue; | |
5977 | ||
5978 | max_pixclk = max(max_pixclk, | |
5979 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5980 | } |
5981 | ||
5982 | return max_pixclk; | |
5983 | } | |
5984 | ||
27c329ed | 5985 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 5986 | { |
27c329ed ML |
5987 | struct drm_device *dev = state->dev; |
5988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5989 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
30a970c6 | 5990 | |
304603f4 ACO |
5991 | if (max_pixclk < 0) |
5992 | return max_pixclk; | |
30a970c6 | 5993 | |
27c329ed ML |
5994 | to_intel_atomic_state(state)->cdclk = |
5995 | valleyview_calc_cdclk(dev_priv, max_pixclk); | |
0a9ab303 | 5996 | |
27c329ed ML |
5997 | return 0; |
5998 | } | |
304603f4 | 5999 | |
27c329ed ML |
6000 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6001 | { | |
6002 | struct drm_device *dev = state->dev; | |
6003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6004 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
85a96e7a | 6005 | |
27c329ed ML |
6006 | if (max_pixclk < 0) |
6007 | return max_pixclk; | |
85a96e7a | 6008 | |
27c329ed ML |
6009 | to_intel_atomic_state(state)->cdclk = |
6010 | broxton_calc_cdclk(dev_priv, max_pixclk); | |
85a96e7a | 6011 | |
27c329ed | 6012 | return 0; |
30a970c6 JB |
6013 | } |
6014 | ||
1e69cd74 VS |
6015 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6016 | { | |
6017 | unsigned int credits, default_credits; | |
6018 | ||
6019 | if (IS_CHERRYVIEW(dev_priv)) | |
6020 | default_credits = PFI_CREDIT(12); | |
6021 | else | |
6022 | default_credits = PFI_CREDIT(8); | |
6023 | ||
bfa7df01 | 6024 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6025 | /* CHV suggested value is 31 or 63 */ |
6026 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6027 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6028 | else |
6029 | credits = PFI_CREDIT(15); | |
6030 | } else { | |
6031 | credits = default_credits; | |
6032 | } | |
6033 | ||
6034 | /* | |
6035 | * WA - write default credits before re-programming | |
6036 | * FIXME: should we also set the resend bit here? | |
6037 | */ | |
6038 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6039 | default_credits); | |
6040 | ||
6041 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6042 | credits | PFI_CREDIT_RESEND); | |
6043 | ||
6044 | /* | |
6045 | * FIXME is this guaranteed to clear | |
6046 | * immediately or should we poll for it? | |
6047 | */ | |
6048 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6049 | } | |
6050 | ||
27c329ed | 6051 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6052 | { |
a821fc46 | 6053 | struct drm_device *dev = old_state->dev; |
27c329ed | 6054 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
30a970c6 | 6055 | struct drm_i915_private *dev_priv = dev->dev_private; |
30a970c6 | 6056 | |
27c329ed ML |
6057 | /* |
6058 | * FIXME: We can end up here with all power domains off, yet | |
6059 | * with a CDCLK frequency other than the minimum. To account | |
6060 | * for this take the PIPE-A power domain, which covers the HW | |
6061 | * blocks needed for the following programming. This can be | |
6062 | * removed once it's guaranteed that we get here either with | |
6063 | * the minimum CDCLK set, or the required power domains | |
6064 | * enabled. | |
6065 | */ | |
6066 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6067 | |
27c329ed ML |
6068 | if (IS_CHERRYVIEW(dev)) |
6069 | cherryview_set_cdclk(dev, req_cdclk); | |
6070 | else | |
6071 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6072 | |
27c329ed | 6073 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6074 | |
27c329ed | 6075 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6076 | } |
6077 | ||
89b667f8 JB |
6078 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6079 | { | |
6080 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6081 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6082 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6083 | struct intel_encoder *encoder; | |
6084 | int pipe = intel_crtc->pipe; | |
23538ef1 | 6085 | bool is_dsi; |
89b667f8 | 6086 | |
53d9f4e9 | 6087 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6088 | return; |
6089 | ||
409ee761 | 6090 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 6091 | |
6e3c9717 | 6092 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6093 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6094 | |
6095 | intel_set_pipe_timings(intel_crtc); | |
6096 | ||
c14b0485 VS |
6097 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6099 | ||
6100 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6101 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6102 | } | |
6103 | ||
5b18e57c DV |
6104 | i9xx_set_pipeconf(intel_crtc); |
6105 | ||
89b667f8 | 6106 | intel_crtc->active = true; |
89b667f8 | 6107 | |
a72e4c9f | 6108 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6109 | |
89b667f8 JB |
6110 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6111 | if (encoder->pre_pll_enable) | |
6112 | encoder->pre_pll_enable(encoder); | |
6113 | ||
9d556c99 | 6114 | if (!is_dsi) { |
c0b4c660 VS |
6115 | if (IS_CHERRYVIEW(dev)) { |
6116 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6117 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6118 | } else { |
6119 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6120 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6121 | } |
9d556c99 | 6122 | } |
89b667f8 JB |
6123 | |
6124 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6125 | if (encoder->pre_enable) | |
6126 | encoder->pre_enable(encoder); | |
6127 | ||
2dd24552 JB |
6128 | i9xx_pfit_enable(intel_crtc); |
6129 | ||
63cbb074 VS |
6130 | intel_crtc_load_lut(crtc); |
6131 | ||
e1fdc473 | 6132 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6133 | |
4b3a9526 VS |
6134 | assert_vblank_disabled(crtc); |
6135 | drm_crtc_vblank_on(crtc); | |
6136 | ||
f9b61ff6 DV |
6137 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6138 | encoder->enable(encoder); | |
89b667f8 JB |
6139 | } |
6140 | ||
f13c2ef3 DV |
6141 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6142 | { | |
6143 | struct drm_device *dev = crtc->base.dev; | |
6144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6145 | ||
6e3c9717 ACO |
6146 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6147 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6148 | } |
6149 | ||
0b8765c6 | 6150 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6151 | { |
6152 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6153 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6154 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6155 | struct intel_encoder *encoder; |
79e53945 | 6156 | int pipe = intel_crtc->pipe; |
79e53945 | 6157 | |
53d9f4e9 | 6158 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6159 | return; |
6160 | ||
f13c2ef3 DV |
6161 | i9xx_set_pll_dividers(intel_crtc); |
6162 | ||
6e3c9717 | 6163 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6164 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6165 | |
6166 | intel_set_pipe_timings(intel_crtc); | |
6167 | ||
5b18e57c DV |
6168 | i9xx_set_pipeconf(intel_crtc); |
6169 | ||
f7abfe8b | 6170 | intel_crtc->active = true; |
6b383a7f | 6171 | |
4a3436e8 | 6172 | if (!IS_GEN2(dev)) |
a72e4c9f | 6173 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6174 | |
9d6d9f19 MK |
6175 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6176 | if (encoder->pre_enable) | |
6177 | encoder->pre_enable(encoder); | |
6178 | ||
f6736a1a DV |
6179 | i9xx_enable_pll(intel_crtc); |
6180 | ||
2dd24552 JB |
6181 | i9xx_pfit_enable(intel_crtc); |
6182 | ||
63cbb074 VS |
6183 | intel_crtc_load_lut(crtc); |
6184 | ||
f37fcc2a | 6185 | intel_update_watermarks(crtc); |
e1fdc473 | 6186 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6187 | |
4b3a9526 VS |
6188 | assert_vblank_disabled(crtc); |
6189 | drm_crtc_vblank_on(crtc); | |
6190 | ||
f9b61ff6 DV |
6191 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6192 | encoder->enable(encoder); | |
0b8765c6 | 6193 | } |
79e53945 | 6194 | |
87476d63 DV |
6195 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6196 | { | |
6197 | struct drm_device *dev = crtc->base.dev; | |
6198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6199 | |
6e3c9717 | 6200 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6201 | return; |
87476d63 | 6202 | |
328d8e82 | 6203 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6204 | |
328d8e82 DV |
6205 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6206 | I915_READ(PFIT_CONTROL)); | |
6207 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6208 | } |
6209 | ||
0b8765c6 JB |
6210 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6211 | { | |
6212 | struct drm_device *dev = crtc->dev; | |
6213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6215 | struct intel_encoder *encoder; |
0b8765c6 | 6216 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6217 | |
6304cd91 VS |
6218 | /* |
6219 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6220 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6221 | * We also need to wait on all gmch platforms because of the |
6222 | * self-refresh mode constraint explained above. | |
6304cd91 | 6223 | */ |
564ed191 | 6224 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6225 | |
4b3a9526 VS |
6226 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6227 | encoder->disable(encoder); | |
6228 | ||
f9b61ff6 DV |
6229 | drm_crtc_vblank_off(crtc); |
6230 | assert_vblank_disabled(crtc); | |
6231 | ||
575f7ab7 | 6232 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6233 | |
87476d63 | 6234 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6235 | |
89b667f8 JB |
6236 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6237 | if (encoder->post_disable) | |
6238 | encoder->post_disable(encoder); | |
6239 | ||
409ee761 | 6240 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6241 | if (IS_CHERRYVIEW(dev)) |
6242 | chv_disable_pll(dev_priv, pipe); | |
6243 | else if (IS_VALLEYVIEW(dev)) | |
6244 | vlv_disable_pll(dev_priv, pipe); | |
6245 | else | |
1c4e0274 | 6246 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6247 | } |
0b8765c6 | 6248 | |
d6db995f VS |
6249 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6250 | if (encoder->post_pll_disable) | |
6251 | encoder->post_pll_disable(encoder); | |
6252 | ||
4a3436e8 | 6253 | if (!IS_GEN2(dev)) |
a72e4c9f | 6254 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6255 | } |
6256 | ||
b17d48e2 ML |
6257 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6258 | { | |
6259 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6260 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6261 | enum intel_display_power_domain domain; | |
6262 | unsigned long domains; | |
6263 | ||
6264 | if (!intel_crtc->active) | |
6265 | return; | |
6266 | ||
a539205a ML |
6267 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
6268 | intel_crtc_wait_for_pending_flips(crtc); | |
6269 | intel_pre_disable_primary(crtc); | |
6270 | } | |
6271 | ||
d032ffa0 | 6272 | intel_crtc_disable_planes(crtc, crtc->state->plane_mask); |
b17d48e2 | 6273 | dev_priv->display.crtc_disable(crtc); |
37d9078b MR |
6274 | intel_crtc->active = false; |
6275 | intel_update_watermarks(crtc); | |
1f7457b1 | 6276 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6277 | |
6278 | domains = intel_crtc->enabled_power_domains; | |
6279 | for_each_power_domain(domain, domains) | |
6280 | intel_display_power_put(dev_priv, domain); | |
6281 | intel_crtc->enabled_power_domains = 0; | |
6282 | } | |
6283 | ||
6b72d486 ML |
6284 | /* |
6285 | * turn all crtc's off, but do not adjust state | |
6286 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6287 | */ | |
70e0bd74 | 6288 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6289 | { |
70e0bd74 ML |
6290 | struct drm_mode_config *config = &dev->mode_config; |
6291 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6292 | struct drm_atomic_state *state; | |
6b72d486 | 6293 | struct drm_crtc *crtc; |
70e0bd74 ML |
6294 | unsigned crtc_mask = 0; |
6295 | int ret = 0; | |
6296 | ||
6297 | if (WARN_ON(!ctx)) | |
6298 | return 0; | |
6299 | ||
6300 | lockdep_assert_held(&ctx->ww_ctx); | |
6301 | state = drm_atomic_state_alloc(dev); | |
6302 | if (WARN_ON(!state)) | |
6303 | return -ENOMEM; | |
6304 | ||
6305 | state->acquire_ctx = ctx; | |
6306 | state->allow_modeset = true; | |
6307 | ||
6308 | for_each_crtc(dev, crtc) { | |
6309 | struct drm_crtc_state *crtc_state = | |
6310 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6311 | |
70e0bd74 ML |
6312 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6313 | if (ret) | |
6314 | goto free; | |
6315 | ||
6316 | if (!crtc_state->active) | |
6317 | continue; | |
6318 | ||
6319 | crtc_state->active = false; | |
6320 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6321 | } | |
6322 | ||
6323 | if (crtc_mask) { | |
74c090b1 | 6324 | ret = drm_atomic_commit(state); |
70e0bd74 ML |
6325 | |
6326 | if (!ret) { | |
6327 | for_each_crtc(dev, crtc) | |
6328 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6329 | crtc->state->active = true; | |
6330 | ||
6331 | return ret; | |
6332 | } | |
6333 | } | |
6334 | ||
6335 | free: | |
6336 | if (ret) | |
6337 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6338 | drm_atomic_state_free(state); | |
6339 | return ret; | |
ee7b9f93 JB |
6340 | } |
6341 | ||
ea5b213a | 6342 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6343 | { |
4ef69c7a | 6344 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6345 | |
ea5b213a CW |
6346 | drm_encoder_cleanup(encoder); |
6347 | kfree(intel_encoder); | |
7e7d76c3 JB |
6348 | } |
6349 | ||
0a91ca29 DV |
6350 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6351 | * internal consistency). */ | |
b980514c | 6352 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6353 | { |
35dd3c64 ML |
6354 | struct drm_crtc *crtc = connector->base.state->crtc; |
6355 | ||
6356 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6357 | connector->base.base.id, | |
6358 | connector->base.name); | |
6359 | ||
0a91ca29 | 6360 | if (connector->get_hw_state(connector)) { |
e85376cb | 6361 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6362 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6363 | |
35dd3c64 ML |
6364 | I915_STATE_WARN(!crtc, |
6365 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6366 | |
35dd3c64 ML |
6367 | if (!crtc) |
6368 | return; | |
6369 | ||
6370 | I915_STATE_WARN(!crtc->state->active, | |
6371 | "connector is active, but attached crtc isn't\n"); | |
6372 | ||
e85376cb | 6373 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6374 | return; |
6375 | ||
e85376cb | 6376 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6377 | "atomic encoder doesn't match attached encoder\n"); |
6378 | ||
e85376cb | 6379 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6380 | "attached encoder crtc differs from connector crtc\n"); |
6381 | } else { | |
4d688a2a ML |
6382 | I915_STATE_WARN(crtc && crtc->state->active, |
6383 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6384 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6385 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6386 | } |
79e53945 JB |
6387 | } |
6388 | ||
08d9bc92 ACO |
6389 | int intel_connector_init(struct intel_connector *connector) |
6390 | { | |
6391 | struct drm_connector_state *connector_state; | |
6392 | ||
6393 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6394 | if (!connector_state) | |
6395 | return -ENOMEM; | |
6396 | ||
6397 | connector->base.state = connector_state; | |
6398 | return 0; | |
6399 | } | |
6400 | ||
6401 | struct intel_connector *intel_connector_alloc(void) | |
6402 | { | |
6403 | struct intel_connector *connector; | |
6404 | ||
6405 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6406 | if (!connector) | |
6407 | return NULL; | |
6408 | ||
6409 | if (intel_connector_init(connector) < 0) { | |
6410 | kfree(connector); | |
6411 | return NULL; | |
6412 | } | |
6413 | ||
6414 | return connector; | |
6415 | } | |
6416 | ||
f0947c37 DV |
6417 | /* Simple connector->get_hw_state implementation for encoders that support only |
6418 | * one connector and no cloning and hence the encoder state determines the state | |
6419 | * of the connector. */ | |
6420 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6421 | { |
24929352 | 6422 | enum pipe pipe = 0; |
f0947c37 | 6423 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6424 | |
f0947c37 | 6425 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6426 | } |
6427 | ||
6d293983 | 6428 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6429 | { |
6d293983 ACO |
6430 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6431 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6432 | |
6433 | return 0; | |
6434 | } | |
6435 | ||
6d293983 | 6436 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6437 | struct intel_crtc_state *pipe_config) |
1857e1da | 6438 | { |
6d293983 ACO |
6439 | struct drm_atomic_state *state = pipe_config->base.state; |
6440 | struct intel_crtc *other_crtc; | |
6441 | struct intel_crtc_state *other_crtc_state; | |
6442 | ||
1857e1da DV |
6443 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6444 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6445 | if (pipe_config->fdi_lanes > 4) { | |
6446 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6447 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6448 | return -EINVAL; |
1857e1da DV |
6449 | } |
6450 | ||
bafb6553 | 6451 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6452 | if (pipe_config->fdi_lanes > 2) { |
6453 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6454 | pipe_config->fdi_lanes); | |
6d293983 | 6455 | return -EINVAL; |
1857e1da | 6456 | } else { |
6d293983 | 6457 | return 0; |
1857e1da DV |
6458 | } |
6459 | } | |
6460 | ||
6461 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6462 | return 0; |
1857e1da DV |
6463 | |
6464 | /* Ivybridge 3 pipe is really complicated */ | |
6465 | switch (pipe) { | |
6466 | case PIPE_A: | |
6d293983 | 6467 | return 0; |
1857e1da | 6468 | case PIPE_B: |
6d293983 ACO |
6469 | if (pipe_config->fdi_lanes <= 2) |
6470 | return 0; | |
6471 | ||
6472 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6473 | other_crtc_state = | |
6474 | intel_atomic_get_crtc_state(state, other_crtc); | |
6475 | if (IS_ERR(other_crtc_state)) | |
6476 | return PTR_ERR(other_crtc_state); | |
6477 | ||
6478 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6479 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6480 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6481 | return -EINVAL; |
1857e1da | 6482 | } |
6d293983 | 6483 | return 0; |
1857e1da | 6484 | case PIPE_C: |
251cc67c VS |
6485 | if (pipe_config->fdi_lanes > 2) { |
6486 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6487 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6488 | return -EINVAL; |
251cc67c | 6489 | } |
6d293983 ACO |
6490 | |
6491 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6492 | other_crtc_state = | |
6493 | intel_atomic_get_crtc_state(state, other_crtc); | |
6494 | if (IS_ERR(other_crtc_state)) | |
6495 | return PTR_ERR(other_crtc_state); | |
6496 | ||
6497 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6498 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6499 | return -EINVAL; |
1857e1da | 6500 | } |
6d293983 | 6501 | return 0; |
1857e1da DV |
6502 | default: |
6503 | BUG(); | |
6504 | } | |
6505 | } | |
6506 | ||
e29c22c0 DV |
6507 | #define RETRY 1 |
6508 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6509 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6510 | { |
1857e1da | 6511 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6512 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6513 | int lane, link_bw, fdi_dotclock, ret; |
6514 | bool needs_recompute = false; | |
877d48d5 | 6515 | |
e29c22c0 | 6516 | retry: |
877d48d5 DV |
6517 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6518 | * each output octet as 10 bits. The actual frequency | |
6519 | * is stored as a divider into a 100MHz clock, and the | |
6520 | * mode pixel clock is stored in units of 1KHz. | |
6521 | * Hence the bw of each lane in terms of the mode signal | |
6522 | * is: | |
6523 | */ | |
6524 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6525 | ||
241bfc38 | 6526 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6527 | |
2bd89a07 | 6528 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6529 | pipe_config->pipe_bpp); |
6530 | ||
6531 | pipe_config->fdi_lanes = lane; | |
6532 | ||
2bd89a07 | 6533 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6534 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6535 | |
6d293983 ACO |
6536 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6537 | intel_crtc->pipe, pipe_config); | |
6538 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6539 | pipe_config->pipe_bpp -= 2*3; |
6540 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6541 | pipe_config->pipe_bpp); | |
6542 | needs_recompute = true; | |
6543 | pipe_config->bw_constrained = true; | |
6544 | ||
6545 | goto retry; | |
6546 | } | |
6547 | ||
6548 | if (needs_recompute) | |
6549 | return RETRY; | |
6550 | ||
6d293983 | 6551 | return ret; |
877d48d5 DV |
6552 | } |
6553 | ||
8cfb3407 VS |
6554 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6555 | struct intel_crtc_state *pipe_config) | |
6556 | { | |
6557 | if (pipe_config->pipe_bpp > 24) | |
6558 | return false; | |
6559 | ||
6560 | /* HSW can handle pixel rate up to cdclk? */ | |
6561 | if (IS_HASWELL(dev_priv->dev)) | |
6562 | return true; | |
6563 | ||
6564 | /* | |
b432e5cf VS |
6565 | * We compare against max which means we must take |
6566 | * the increased cdclk requirement into account when | |
6567 | * calculating the new cdclk. | |
6568 | * | |
6569 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6570 | */ |
6571 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6572 | dev_priv->max_cdclk_freq * 95 / 100; | |
6573 | } | |
6574 | ||
42db64ef | 6575 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6576 | struct intel_crtc_state *pipe_config) |
42db64ef | 6577 | { |
8cfb3407 VS |
6578 | struct drm_device *dev = crtc->base.dev; |
6579 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6580 | ||
d330a953 | 6581 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6582 | hsw_crtc_supports_ips(crtc) && |
6583 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6584 | } |
6585 | ||
a43f6e0f | 6586 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6587 | struct intel_crtc_state *pipe_config) |
79e53945 | 6588 | { |
a43f6e0f | 6589 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6590 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6591 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6592 | |
ad3a4479 | 6593 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6594 | if (INTEL_INFO(dev)->gen < 4) { |
44913155 | 6595 | int clock_limit = dev_priv->max_cdclk_freq; |
cf532bb2 VS |
6596 | |
6597 | /* | |
6598 | * Enable pixel doubling when the dot clock | |
6599 | * is > 90% of the (display) core speed. | |
6600 | * | |
b397c96b VS |
6601 | * GDG double wide on either pipe, |
6602 | * otherwise pipe A only. | |
cf532bb2 | 6603 | */ |
b397c96b | 6604 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6605 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6606 | clock_limit *= 2; |
cf532bb2 | 6607 | pipe_config->double_wide = true; |
ad3a4479 VS |
6608 | } |
6609 | ||
241bfc38 | 6610 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6611 | return -EINVAL; |
2c07245f | 6612 | } |
89749350 | 6613 | |
1d1d0e27 VS |
6614 | /* |
6615 | * Pipe horizontal size must be even in: | |
6616 | * - DVO ganged mode | |
6617 | * - LVDS dual channel mode | |
6618 | * - Double wide pipe | |
6619 | */ | |
a93e255f | 6620 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6621 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6622 | pipe_config->pipe_src_w &= ~1; | |
6623 | ||
8693a824 DL |
6624 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6625 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6626 | */ |
6627 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6628 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6629 | return -EINVAL; |
44f46b42 | 6630 | |
f5adf94e | 6631 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6632 | hsw_compute_ips_config(crtc, pipe_config); |
6633 | ||
877d48d5 | 6634 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6635 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6636 | |
cf5a15be | 6637 | return 0; |
79e53945 JB |
6638 | } |
6639 | ||
1652d19e VS |
6640 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6641 | { | |
6642 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6643 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6644 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6645 | uint32_t linkrate; | |
6646 | ||
414355a7 | 6647 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6648 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6649 | |
6650 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6651 | return 540000; | |
6652 | ||
6653 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6654 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6655 | |
71cd8423 DL |
6656 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6657 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6658 | /* vco 8640 */ |
6659 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6660 | case CDCLK_FREQ_450_432: | |
6661 | return 432000; | |
6662 | case CDCLK_FREQ_337_308: | |
6663 | return 308570; | |
6664 | case CDCLK_FREQ_675_617: | |
6665 | return 617140; | |
6666 | default: | |
6667 | WARN(1, "Unknown cd freq selection\n"); | |
6668 | } | |
6669 | } else { | |
6670 | /* vco 8100 */ | |
6671 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6672 | case CDCLK_FREQ_450_432: | |
6673 | return 450000; | |
6674 | case CDCLK_FREQ_337_308: | |
6675 | return 337500; | |
6676 | case CDCLK_FREQ_675_617: | |
6677 | return 675000; | |
6678 | default: | |
6679 | WARN(1, "Unknown cd freq selection\n"); | |
6680 | } | |
6681 | } | |
6682 | ||
6683 | /* error case, do as if DPLL0 isn't enabled */ | |
6684 | return 24000; | |
6685 | } | |
6686 | ||
acd3f3d3 BP |
6687 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6688 | { | |
6689 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6690 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6691 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6692 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6693 | int cdclk; | |
6694 | ||
6695 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6696 | return 19200; | |
6697 | ||
6698 | cdclk = 19200 * pll_ratio / 2; | |
6699 | ||
6700 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6701 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6702 | return cdclk; /* 576MHz or 624MHz */ | |
6703 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6704 | return cdclk * 2 / 3; /* 384MHz */ | |
6705 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6706 | return cdclk / 2; /* 288MHz */ | |
6707 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6708 | return cdclk / 4; /* 144MHz */ | |
6709 | } | |
6710 | ||
6711 | /* error case, do as if DE PLL isn't enabled */ | |
6712 | return 19200; | |
6713 | } | |
6714 | ||
1652d19e VS |
6715 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6716 | { | |
6717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6718 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6719 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6720 | ||
6721 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6722 | return 800000; | |
6723 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6724 | return 450000; | |
6725 | else if (freq == LCPLL_CLK_FREQ_450) | |
6726 | return 450000; | |
6727 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6728 | return 540000; | |
6729 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6730 | return 337500; | |
6731 | else | |
6732 | return 675000; | |
6733 | } | |
6734 | ||
6735 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6736 | { | |
6737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6738 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6739 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6740 | ||
6741 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6742 | return 800000; | |
6743 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6744 | return 450000; | |
6745 | else if (freq == LCPLL_CLK_FREQ_450) | |
6746 | return 450000; | |
6747 | else if (IS_HSW_ULT(dev)) | |
6748 | return 337500; | |
6749 | else | |
6750 | return 540000; | |
79e53945 JB |
6751 | } |
6752 | ||
25eb05fc JB |
6753 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6754 | { | |
bfa7df01 VS |
6755 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6756 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6757 | } |
6758 | ||
b37a6434 VS |
6759 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6760 | { | |
6761 | return 450000; | |
6762 | } | |
6763 | ||
e70236a8 JB |
6764 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6765 | { | |
6766 | return 400000; | |
6767 | } | |
79e53945 | 6768 | |
e70236a8 | 6769 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6770 | { |
e907f170 | 6771 | return 333333; |
e70236a8 | 6772 | } |
79e53945 | 6773 | |
e70236a8 JB |
6774 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6775 | { | |
6776 | return 200000; | |
6777 | } | |
79e53945 | 6778 | |
257a7ffc DV |
6779 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6780 | { | |
6781 | u16 gcfgc = 0; | |
6782 | ||
6783 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6784 | ||
6785 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6786 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6787 | return 266667; |
257a7ffc | 6788 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6789 | return 333333; |
257a7ffc | 6790 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6791 | return 444444; |
257a7ffc DV |
6792 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6793 | return 200000; | |
6794 | default: | |
6795 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6796 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6797 | return 133333; |
257a7ffc | 6798 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6799 | return 166667; |
257a7ffc DV |
6800 | } |
6801 | } | |
6802 | ||
e70236a8 JB |
6803 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6804 | { | |
6805 | u16 gcfgc = 0; | |
79e53945 | 6806 | |
e70236a8 JB |
6807 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6808 | ||
6809 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6810 | return 133333; |
e70236a8 JB |
6811 | else { |
6812 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6813 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6814 | return 333333; |
e70236a8 JB |
6815 | default: |
6816 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6817 | return 190000; | |
79e53945 | 6818 | } |
e70236a8 JB |
6819 | } |
6820 | } | |
6821 | ||
6822 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6823 | { | |
e907f170 | 6824 | return 266667; |
e70236a8 JB |
6825 | } |
6826 | ||
1b1d2716 | 6827 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6828 | { |
6829 | u16 hpllcc = 0; | |
1b1d2716 | 6830 | |
65cd2b3f VS |
6831 | /* |
6832 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6833 | * encoding is different :( | |
6834 | * FIXME is this the right way to detect 852GM/852GMV? | |
6835 | */ | |
6836 | if (dev->pdev->revision == 0x1) | |
6837 | return 133333; | |
6838 | ||
1b1d2716 VS |
6839 | pci_bus_read_config_word(dev->pdev->bus, |
6840 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6841 | ||
e70236a8 JB |
6842 | /* Assume that the hardware is in the high speed state. This |
6843 | * should be the default. | |
6844 | */ | |
6845 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6846 | case GC_CLOCK_133_200: | |
1b1d2716 | 6847 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6848 | case GC_CLOCK_100_200: |
6849 | return 200000; | |
6850 | case GC_CLOCK_166_250: | |
6851 | return 250000; | |
6852 | case GC_CLOCK_100_133: | |
e907f170 | 6853 | return 133333; |
1b1d2716 VS |
6854 | case GC_CLOCK_133_266: |
6855 | case GC_CLOCK_133_266_2: | |
6856 | case GC_CLOCK_166_266: | |
6857 | return 266667; | |
e70236a8 | 6858 | } |
79e53945 | 6859 | |
e70236a8 JB |
6860 | /* Shouldn't happen */ |
6861 | return 0; | |
6862 | } | |
79e53945 | 6863 | |
e70236a8 JB |
6864 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6865 | { | |
e907f170 | 6866 | return 133333; |
79e53945 JB |
6867 | } |
6868 | ||
34edce2f VS |
6869 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6870 | { | |
6871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6872 | static const unsigned int blb_vco[8] = { | |
6873 | [0] = 3200000, | |
6874 | [1] = 4000000, | |
6875 | [2] = 5333333, | |
6876 | [3] = 4800000, | |
6877 | [4] = 6400000, | |
6878 | }; | |
6879 | static const unsigned int pnv_vco[8] = { | |
6880 | [0] = 3200000, | |
6881 | [1] = 4000000, | |
6882 | [2] = 5333333, | |
6883 | [3] = 4800000, | |
6884 | [4] = 2666667, | |
6885 | }; | |
6886 | static const unsigned int cl_vco[8] = { | |
6887 | [0] = 3200000, | |
6888 | [1] = 4000000, | |
6889 | [2] = 5333333, | |
6890 | [3] = 6400000, | |
6891 | [4] = 3333333, | |
6892 | [5] = 3566667, | |
6893 | [6] = 4266667, | |
6894 | }; | |
6895 | static const unsigned int elk_vco[8] = { | |
6896 | [0] = 3200000, | |
6897 | [1] = 4000000, | |
6898 | [2] = 5333333, | |
6899 | [3] = 4800000, | |
6900 | }; | |
6901 | static const unsigned int ctg_vco[8] = { | |
6902 | [0] = 3200000, | |
6903 | [1] = 4000000, | |
6904 | [2] = 5333333, | |
6905 | [3] = 6400000, | |
6906 | [4] = 2666667, | |
6907 | [5] = 4266667, | |
6908 | }; | |
6909 | const unsigned int *vco_table; | |
6910 | unsigned int vco; | |
6911 | uint8_t tmp = 0; | |
6912 | ||
6913 | /* FIXME other chipsets? */ | |
6914 | if (IS_GM45(dev)) | |
6915 | vco_table = ctg_vco; | |
6916 | else if (IS_G4X(dev)) | |
6917 | vco_table = elk_vco; | |
6918 | else if (IS_CRESTLINE(dev)) | |
6919 | vco_table = cl_vco; | |
6920 | else if (IS_PINEVIEW(dev)) | |
6921 | vco_table = pnv_vco; | |
6922 | else if (IS_G33(dev)) | |
6923 | vco_table = blb_vco; | |
6924 | else | |
6925 | return 0; | |
6926 | ||
6927 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6928 | ||
6929 | vco = vco_table[tmp & 0x7]; | |
6930 | if (vco == 0) | |
6931 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6932 | else | |
6933 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6934 | ||
6935 | return vco; | |
6936 | } | |
6937 | ||
6938 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6939 | { | |
6940 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6941 | uint16_t tmp = 0; | |
6942 | ||
6943 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6944 | ||
6945 | cdclk_sel = (tmp >> 12) & 0x1; | |
6946 | ||
6947 | switch (vco) { | |
6948 | case 2666667: | |
6949 | case 4000000: | |
6950 | case 5333333: | |
6951 | return cdclk_sel ? 333333 : 222222; | |
6952 | case 3200000: | |
6953 | return cdclk_sel ? 320000 : 228571; | |
6954 | default: | |
6955 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6956 | return 222222; | |
6957 | } | |
6958 | } | |
6959 | ||
6960 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6961 | { | |
6962 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6963 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6964 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6965 | const uint8_t *div_table; | |
6966 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6967 | uint16_t tmp = 0; | |
6968 | ||
6969 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6970 | ||
6971 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6972 | ||
6973 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6974 | goto fail; | |
6975 | ||
6976 | switch (vco) { | |
6977 | case 3200000: | |
6978 | div_table = div_3200; | |
6979 | break; | |
6980 | case 4000000: | |
6981 | div_table = div_4000; | |
6982 | break; | |
6983 | case 5333333: | |
6984 | div_table = div_5333; | |
6985 | break; | |
6986 | default: | |
6987 | goto fail; | |
6988 | } | |
6989 | ||
6990 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6991 | ||
caf4e252 | 6992 | fail: |
34edce2f VS |
6993 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
6994 | return 200000; | |
6995 | } | |
6996 | ||
6997 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
6998 | { | |
6999 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7000 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7001 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7002 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7003 | const uint8_t *div_table; | |
7004 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7005 | uint16_t tmp = 0; | |
7006 | ||
7007 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7008 | ||
7009 | cdclk_sel = (tmp >> 4) & 0x7; | |
7010 | ||
7011 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7012 | goto fail; | |
7013 | ||
7014 | switch (vco) { | |
7015 | case 3200000: | |
7016 | div_table = div_3200; | |
7017 | break; | |
7018 | case 4000000: | |
7019 | div_table = div_4000; | |
7020 | break; | |
7021 | case 4800000: | |
7022 | div_table = div_4800; | |
7023 | break; | |
7024 | case 5333333: | |
7025 | div_table = div_5333; | |
7026 | break; | |
7027 | default: | |
7028 | goto fail; | |
7029 | } | |
7030 | ||
7031 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7032 | ||
caf4e252 | 7033 | fail: |
34edce2f VS |
7034 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7035 | return 190476; | |
7036 | } | |
7037 | ||
2c07245f | 7038 | static void |
a65851af | 7039 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7040 | { |
a65851af VS |
7041 | while (*num > DATA_LINK_M_N_MASK || |
7042 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7043 | *num >>= 1; |
7044 | *den >>= 1; | |
7045 | } | |
7046 | } | |
7047 | ||
a65851af VS |
7048 | static void compute_m_n(unsigned int m, unsigned int n, |
7049 | uint32_t *ret_m, uint32_t *ret_n) | |
7050 | { | |
7051 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7052 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7053 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7054 | } | |
7055 | ||
e69d0bc1 DV |
7056 | void |
7057 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7058 | int pixel_clock, int link_clock, | |
7059 | struct intel_link_m_n *m_n) | |
2c07245f | 7060 | { |
e69d0bc1 | 7061 | m_n->tu = 64; |
a65851af VS |
7062 | |
7063 | compute_m_n(bits_per_pixel * pixel_clock, | |
7064 | link_clock * nlanes * 8, | |
7065 | &m_n->gmch_m, &m_n->gmch_n); | |
7066 | ||
7067 | compute_m_n(pixel_clock, link_clock, | |
7068 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7069 | } |
7070 | ||
a7615030 CW |
7071 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7072 | { | |
d330a953 JN |
7073 | if (i915.panel_use_ssc >= 0) |
7074 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7075 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7076 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7077 | } |
7078 | ||
a93e255f ACO |
7079 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7080 | int num_connectors) | |
c65d77d8 | 7081 | { |
a93e255f | 7082 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7083 | struct drm_i915_private *dev_priv = dev->dev_private; |
7084 | int refclk; | |
7085 | ||
a93e255f ACO |
7086 | WARN_ON(!crtc_state->base.state); |
7087 | ||
5ab7b0b7 | 7088 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7089 | refclk = 100000; |
a93e255f | 7090 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7091 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7092 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7093 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7094 | } else if (!IS_GEN2(dev)) { |
7095 | refclk = 96000; | |
7096 | } else { | |
7097 | refclk = 48000; | |
7098 | } | |
7099 | ||
7100 | return refclk; | |
7101 | } | |
7102 | ||
7429e9d4 | 7103 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7104 | { |
7df00d7a | 7105 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7106 | } |
f47709a9 | 7107 | |
7429e9d4 DV |
7108 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7109 | { | |
7110 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7111 | } |
7112 | ||
f47709a9 | 7113 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7114 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7115 | intel_clock_t *reduced_clock) |
7116 | { | |
f47709a9 | 7117 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7118 | u32 fp, fp2 = 0; |
7119 | ||
7120 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7121 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7122 | if (reduced_clock) |
7429e9d4 | 7123 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7124 | } else { |
190f68c5 | 7125 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7126 | if (reduced_clock) |
7429e9d4 | 7127 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7128 | } |
7129 | ||
190f68c5 | 7130 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7131 | |
f47709a9 | 7132 | crtc->lowfreq_avail = false; |
a93e255f | 7133 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7134 | reduced_clock) { |
190f68c5 | 7135 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7136 | crtc->lowfreq_avail = true; |
a7516a05 | 7137 | } else { |
190f68c5 | 7138 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7139 | } |
7140 | } | |
7141 | ||
5e69f97f CML |
7142 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7143 | pipe) | |
89b667f8 JB |
7144 | { |
7145 | u32 reg_val; | |
7146 | ||
7147 | /* | |
7148 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7149 | * and set it to a reasonable value instead. | |
7150 | */ | |
ab3c759a | 7151 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7152 | reg_val &= 0xffffff00; |
7153 | reg_val |= 0x00000030; | |
ab3c759a | 7154 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7155 | |
ab3c759a | 7156 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7157 | reg_val &= 0x8cffffff; |
7158 | reg_val = 0x8c000000; | |
ab3c759a | 7159 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7160 | |
ab3c759a | 7161 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7162 | reg_val &= 0xffffff00; |
ab3c759a | 7163 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7164 | |
ab3c759a | 7165 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7166 | reg_val &= 0x00ffffff; |
7167 | reg_val |= 0xb0000000; | |
ab3c759a | 7168 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7169 | } |
7170 | ||
b551842d DV |
7171 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7172 | struct intel_link_m_n *m_n) | |
7173 | { | |
7174 | struct drm_device *dev = crtc->base.dev; | |
7175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7176 | int pipe = crtc->pipe; | |
7177 | ||
e3b95f1e DV |
7178 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7179 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7180 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7181 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7182 | } |
7183 | ||
7184 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7185 | struct intel_link_m_n *m_n, |
7186 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7187 | { |
7188 | struct drm_device *dev = crtc->base.dev; | |
7189 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7190 | int pipe = crtc->pipe; | |
6e3c9717 | 7191 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7192 | |
7193 | if (INTEL_INFO(dev)->gen >= 5) { | |
7194 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7195 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7196 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7197 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7198 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7199 | * for gen < 8) and if DRRS is supported (to make sure the | |
7200 | * registers are not unnecessarily accessed). | |
7201 | */ | |
44395bfe | 7202 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7203 | crtc->config->has_drrs) { |
f769cd24 VK |
7204 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7205 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7206 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7207 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7208 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7209 | } | |
b551842d | 7210 | } else { |
e3b95f1e DV |
7211 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7212 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7213 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7214 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7215 | } |
7216 | } | |
7217 | ||
fe3cd48d | 7218 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7219 | { |
fe3cd48d R |
7220 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7221 | ||
7222 | if (m_n == M1_N1) { | |
7223 | dp_m_n = &crtc->config->dp_m_n; | |
7224 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7225 | } else if (m_n == M2_N2) { | |
7226 | ||
7227 | /* | |
7228 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7229 | * needs to be programmed into M1_N1. | |
7230 | */ | |
7231 | dp_m_n = &crtc->config->dp_m2_n2; | |
7232 | } else { | |
7233 | DRM_ERROR("Unsupported divider value\n"); | |
7234 | return; | |
7235 | } | |
7236 | ||
6e3c9717 ACO |
7237 | if (crtc->config->has_pch_encoder) |
7238 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7239 | else |
fe3cd48d | 7240 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7241 | } |
7242 | ||
251ac862 DV |
7243 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7244 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7245 | { |
7246 | u32 dpll, dpll_md; | |
7247 | ||
7248 | /* | |
7249 | * Enable DPIO clock input. We should never disable the reference | |
7250 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7251 | * on it. | |
7252 | */ | |
60bfe44f VS |
7253 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7254 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7255 | /* We should never disable this, set it here for state tracking */ |
7256 | if (crtc->pipe == PIPE_B) | |
7257 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7258 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7259 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7260 | |
d288f65f | 7261 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7262 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7263 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7264 | } |
7265 | ||
d288f65f | 7266 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7267 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7268 | { |
f47709a9 | 7269 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7270 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7271 | int pipe = crtc->pipe; |
bdd4b6a6 | 7272 | u32 mdiv; |
a0c4da24 | 7273 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7274 | u32 coreclk, reg_val; |
a0c4da24 | 7275 | |
a580516d | 7276 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7277 | |
d288f65f VS |
7278 | bestn = pipe_config->dpll.n; |
7279 | bestm1 = pipe_config->dpll.m1; | |
7280 | bestm2 = pipe_config->dpll.m2; | |
7281 | bestp1 = pipe_config->dpll.p1; | |
7282 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7283 | |
89b667f8 JB |
7284 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7285 | ||
7286 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7287 | if (pipe == PIPE_B) |
5e69f97f | 7288 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7289 | |
7290 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7291 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7292 | |
7293 | /* Disable target IRef on PLL */ | |
ab3c759a | 7294 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7295 | reg_val &= 0x00ffffff; |
ab3c759a | 7296 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7297 | |
7298 | /* Disable fast lock */ | |
ab3c759a | 7299 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7300 | |
7301 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7302 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7303 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7304 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7305 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7306 | |
7307 | /* | |
7308 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7309 | * but we don't support that). | |
7310 | * Note: don't use the DAC post divider as it seems unstable. | |
7311 | */ | |
7312 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7313 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7314 | |
a0c4da24 | 7315 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7316 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7317 | |
89b667f8 | 7318 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7319 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7320 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7321 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7322 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7323 | 0x009f0003); |
89b667f8 | 7324 | else |
ab3c759a | 7325 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7326 | 0x00d0000f); |
7327 | ||
681a8504 | 7328 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7329 | /* Use SSC source */ |
bdd4b6a6 | 7330 | if (pipe == PIPE_A) |
ab3c759a | 7331 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7332 | 0x0df40000); |
7333 | else | |
ab3c759a | 7334 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7335 | 0x0df70000); |
7336 | } else { /* HDMI or VGA */ | |
7337 | /* Use bend source */ | |
bdd4b6a6 | 7338 | if (pipe == PIPE_A) |
ab3c759a | 7339 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7340 | 0x0df70000); |
7341 | else | |
ab3c759a | 7342 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7343 | 0x0df40000); |
7344 | } | |
a0c4da24 | 7345 | |
ab3c759a | 7346 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7347 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7348 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7349 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7350 | coreclk |= 0x01000000; |
ab3c759a | 7351 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7352 | |
ab3c759a | 7353 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7354 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7355 | } |
7356 | ||
251ac862 DV |
7357 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7358 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7359 | { |
60bfe44f VS |
7360 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7361 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7362 | DPLL_VCO_ENABLE; |
7363 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7364 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7365 | |
d288f65f VS |
7366 | pipe_config->dpll_hw_state.dpll_md = |
7367 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7368 | } |
7369 | ||
d288f65f | 7370 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7371 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7372 | { |
7373 | struct drm_device *dev = crtc->base.dev; | |
7374 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7375 | int pipe = crtc->pipe; | |
7376 | int dpll_reg = DPLL(crtc->pipe); | |
7377 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 7378 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7379 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7380 | u32 dpio_val; |
9cbe40c1 | 7381 | int vco; |
9d556c99 | 7382 | |
d288f65f VS |
7383 | bestn = pipe_config->dpll.n; |
7384 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7385 | bestm1 = pipe_config->dpll.m1; | |
7386 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7387 | bestp1 = pipe_config->dpll.p1; | |
7388 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7389 | vco = pipe_config->dpll.vco; |
a945ce7e | 7390 | dpio_val = 0; |
9cbe40c1 | 7391 | loopfilter = 0; |
9d556c99 CML |
7392 | |
7393 | /* | |
7394 | * Enable Refclk and SSC | |
7395 | */ | |
a11b0703 | 7396 | I915_WRITE(dpll_reg, |
d288f65f | 7397 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7398 | |
a580516d | 7399 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7400 | |
9d556c99 CML |
7401 | /* p1 and p2 divider */ |
7402 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7403 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7404 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7405 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7406 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7407 | ||
7408 | /* Feedback post-divider - m2 */ | |
7409 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7410 | ||
7411 | /* Feedback refclk divider - n and m1 */ | |
7412 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7413 | DPIO_CHV_M1_DIV_BY_2 | | |
7414 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7415 | ||
7416 | /* M2 fraction division */ | |
25a25dfc | 7417 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7418 | |
7419 | /* M2 fraction division enable */ | |
a945ce7e VP |
7420 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7421 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7422 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7423 | if (bestm2_frac) | |
7424 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7425 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7426 | |
de3a0fde VP |
7427 | /* Program digital lock detect threshold */ |
7428 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7429 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7430 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7431 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7432 | if (!bestm2_frac) | |
7433 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7434 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7435 | ||
9d556c99 | 7436 | /* Loop filter */ |
9cbe40c1 VP |
7437 | if (vco == 5400000) { |
7438 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7439 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7440 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7441 | tribuf_calcntr = 0x9; | |
7442 | } else if (vco <= 6200000) { | |
7443 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7444 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7445 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7446 | tribuf_calcntr = 0x9; | |
7447 | } else if (vco <= 6480000) { | |
7448 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7449 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7450 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7451 | tribuf_calcntr = 0x8; | |
7452 | } else { | |
7453 | /* Not supported. Apply the same limits as in the max case */ | |
7454 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7455 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7456 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7457 | tribuf_calcntr = 0; | |
7458 | } | |
9d556c99 CML |
7459 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7460 | ||
968040b2 | 7461 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7462 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7463 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7464 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7465 | ||
9d556c99 CML |
7466 | /* AFC Recal */ |
7467 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7468 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7469 | DPIO_AFC_RECAL); | |
7470 | ||
a580516d | 7471 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7472 | } |
7473 | ||
d288f65f VS |
7474 | /** |
7475 | * vlv_force_pll_on - forcibly enable just the PLL | |
7476 | * @dev_priv: i915 private structure | |
7477 | * @pipe: pipe PLL to enable | |
7478 | * @dpll: PLL configuration | |
7479 | * | |
7480 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7481 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7482 | * be enabled. | |
7483 | */ | |
7484 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7485 | const struct dpll *dpll) | |
7486 | { | |
7487 | struct intel_crtc *crtc = | |
7488 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7489 | struct intel_crtc_state pipe_config = { |
a93e255f | 7490 | .base.crtc = &crtc->base, |
d288f65f VS |
7491 | .pixel_multiplier = 1, |
7492 | .dpll = *dpll, | |
7493 | }; | |
7494 | ||
7495 | if (IS_CHERRYVIEW(dev)) { | |
251ac862 | 7496 | chv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7497 | chv_prepare_pll(crtc, &pipe_config); |
7498 | chv_enable_pll(crtc, &pipe_config); | |
7499 | } else { | |
251ac862 | 7500 | vlv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7501 | vlv_prepare_pll(crtc, &pipe_config); |
7502 | vlv_enable_pll(crtc, &pipe_config); | |
7503 | } | |
7504 | } | |
7505 | ||
7506 | /** | |
7507 | * vlv_force_pll_off - forcibly disable just the PLL | |
7508 | * @dev_priv: i915 private structure | |
7509 | * @pipe: pipe PLL to disable | |
7510 | * | |
7511 | * Disable the PLL for @pipe. To be used in cases where we need | |
7512 | * the PLL enabled even when @pipe is not going to be enabled. | |
7513 | */ | |
7514 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7515 | { | |
7516 | if (IS_CHERRYVIEW(dev)) | |
7517 | chv_disable_pll(to_i915(dev), pipe); | |
7518 | else | |
7519 | vlv_disable_pll(to_i915(dev), pipe); | |
7520 | } | |
7521 | ||
251ac862 DV |
7522 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7523 | struct intel_crtc_state *crtc_state, | |
7524 | intel_clock_t *reduced_clock, | |
7525 | int num_connectors) | |
eb1cbe48 | 7526 | { |
f47709a9 | 7527 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7528 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7529 | u32 dpll; |
7530 | bool is_sdvo; | |
190f68c5 | 7531 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7532 | |
190f68c5 | 7533 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7534 | |
a93e255f ACO |
7535 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7536 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7537 | |
7538 | dpll = DPLL_VGA_MODE_DIS; | |
7539 | ||
a93e255f | 7540 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7541 | dpll |= DPLLB_MODE_LVDS; |
7542 | else | |
7543 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7544 | |
ef1b460d | 7545 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7546 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7547 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7548 | } |
198a037f DV |
7549 | |
7550 | if (is_sdvo) | |
4a33e48d | 7551 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7552 | |
190f68c5 | 7553 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7554 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7555 | |
7556 | /* compute bitmask from p1 value */ | |
7557 | if (IS_PINEVIEW(dev)) | |
7558 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7559 | else { | |
7560 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7561 | if (IS_G4X(dev) && reduced_clock) | |
7562 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7563 | } | |
7564 | switch (clock->p2) { | |
7565 | case 5: | |
7566 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7567 | break; | |
7568 | case 7: | |
7569 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7570 | break; | |
7571 | case 10: | |
7572 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7573 | break; | |
7574 | case 14: | |
7575 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7576 | break; | |
7577 | } | |
7578 | if (INTEL_INFO(dev)->gen >= 4) | |
7579 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7580 | ||
190f68c5 | 7581 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7582 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7583 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7584 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7585 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7586 | else | |
7587 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7588 | ||
7589 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7590 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7591 | |
eb1cbe48 | 7592 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7593 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7594 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7595 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7596 | } |
7597 | } | |
7598 | ||
251ac862 DV |
7599 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7600 | struct intel_crtc_state *crtc_state, | |
7601 | intel_clock_t *reduced_clock, | |
7602 | int num_connectors) | |
eb1cbe48 | 7603 | { |
f47709a9 | 7604 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7605 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7606 | u32 dpll; |
190f68c5 | 7607 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7608 | |
190f68c5 | 7609 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7610 | |
eb1cbe48 DV |
7611 | dpll = DPLL_VGA_MODE_DIS; |
7612 | ||
a93e255f | 7613 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7614 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7615 | } else { | |
7616 | if (clock->p1 == 2) | |
7617 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7618 | else | |
7619 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7620 | if (clock->p2 == 4) | |
7621 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7622 | } | |
7623 | ||
a93e255f | 7624 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7625 | dpll |= DPLL_DVO_2X_MODE; |
7626 | ||
a93e255f | 7627 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7628 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7629 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7630 | else | |
7631 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7632 | ||
7633 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7634 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7635 | } |
7636 | ||
8a654f3b | 7637 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7638 | { |
7639 | struct drm_device *dev = intel_crtc->base.dev; | |
7640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7641 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7642 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7643 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7644 | uint32_t crtc_vtotal, crtc_vblank_end; |
7645 | int vsyncshift = 0; | |
4d8a62ea DV |
7646 | |
7647 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7648 | * the hw state checker will get angry at the mismatch. */ | |
7649 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7650 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7651 | |
609aeaca | 7652 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7653 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7654 | crtc_vtotal -= 1; |
7655 | crtc_vblank_end -= 1; | |
609aeaca | 7656 | |
409ee761 | 7657 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7658 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7659 | else | |
7660 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7661 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7662 | if (vsyncshift < 0) |
7663 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7664 | } |
7665 | ||
7666 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7667 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7668 | |
fe2b8f9d | 7669 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7670 | (adjusted_mode->crtc_hdisplay - 1) | |
7671 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7672 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7673 | (adjusted_mode->crtc_hblank_start - 1) | |
7674 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7675 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7676 | (adjusted_mode->crtc_hsync_start - 1) | |
7677 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7678 | ||
fe2b8f9d | 7679 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7680 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7681 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7682 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7683 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7684 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7685 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7686 | (adjusted_mode->crtc_vsync_start - 1) | |
7687 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7688 | ||
b5e508d4 PZ |
7689 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7690 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7691 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7692 | * bits. */ | |
7693 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7694 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7695 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7696 | ||
b0e77b9c PZ |
7697 | /* pipesrc controls the size that is scaled from, which should |
7698 | * always be the user's requested size. | |
7699 | */ | |
7700 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7701 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7702 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7703 | } |
7704 | ||
1bd1bd80 | 7705 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7706 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7707 | { |
7708 | struct drm_device *dev = crtc->base.dev; | |
7709 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7710 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7711 | uint32_t tmp; | |
7712 | ||
7713 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7714 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7715 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7716 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7717 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7718 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7719 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7720 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7721 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7722 | |
7723 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7724 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7725 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7726 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7727 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7728 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7729 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7730 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7731 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7732 | |
7733 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7734 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7735 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7736 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7737 | } |
7738 | ||
7739 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7740 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7741 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7742 | ||
2d112de7 ACO |
7743 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7744 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7745 | } |
7746 | ||
f6a83288 | 7747 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7748 | struct intel_crtc_state *pipe_config) |
babea61d | 7749 | { |
2d112de7 ACO |
7750 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7751 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7752 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7753 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7754 | |
2d112de7 ACO |
7755 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7756 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7757 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7758 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7759 | |
2d112de7 | 7760 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7761 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7762 | |
2d112de7 ACO |
7763 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7764 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7765 | |
7766 | mode->hsync = drm_mode_hsync(mode); | |
7767 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7768 | drm_mode_set_name(mode); | |
babea61d JB |
7769 | } |
7770 | ||
84b046f3 DV |
7771 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7772 | { | |
7773 | struct drm_device *dev = intel_crtc->base.dev; | |
7774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7775 | uint32_t pipeconf; | |
7776 | ||
9f11a9e4 | 7777 | pipeconf = 0; |
84b046f3 | 7778 | |
b6b5d049 VS |
7779 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7780 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7781 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7782 | |
6e3c9717 | 7783 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7784 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7785 | |
ff9ce46e DV |
7786 | /* only g4x and later have fancy bpc/dither controls */ |
7787 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7788 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7789 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7790 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7791 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7792 | |
6e3c9717 | 7793 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7794 | case 18: |
7795 | pipeconf |= PIPECONF_6BPC; | |
7796 | break; | |
7797 | case 24: | |
7798 | pipeconf |= PIPECONF_8BPC; | |
7799 | break; | |
7800 | case 30: | |
7801 | pipeconf |= PIPECONF_10BPC; | |
7802 | break; | |
7803 | default: | |
7804 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7805 | BUG(); | |
84b046f3 DV |
7806 | } |
7807 | } | |
7808 | ||
7809 | if (HAS_PIPE_CXSR(dev)) { | |
7810 | if (intel_crtc->lowfreq_avail) { | |
7811 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7812 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7813 | } else { | |
7814 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7815 | } |
7816 | } | |
7817 | ||
6e3c9717 | 7818 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7819 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7820 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7821 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7822 | else | |
7823 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7824 | } else | |
84b046f3 DV |
7825 | pipeconf |= PIPECONF_PROGRESSIVE; |
7826 | ||
6e3c9717 | 7827 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7828 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7829 | |
84b046f3 DV |
7830 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7831 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7832 | } | |
7833 | ||
190f68c5 ACO |
7834 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7835 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7836 | { |
c7653199 | 7837 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7838 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7839 | int refclk, num_connectors = 0; |
c329a4ec DV |
7840 | intel_clock_t clock; |
7841 | bool ok; | |
7842 | bool is_dsi = false; | |
5eddb70b | 7843 | struct intel_encoder *encoder; |
d4906093 | 7844 | const intel_limit_t *limit; |
55bb9992 | 7845 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7846 | struct drm_connector *connector; |
55bb9992 ACO |
7847 | struct drm_connector_state *connector_state; |
7848 | int i; | |
79e53945 | 7849 | |
dd3cd74a ACO |
7850 | memset(&crtc_state->dpll_hw_state, 0, |
7851 | sizeof(crtc_state->dpll_hw_state)); | |
7852 | ||
da3ced29 | 7853 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
7854 | if (connector_state->crtc != &crtc->base) |
7855 | continue; | |
7856 | ||
7857 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7858 | ||
5eddb70b | 7859 | switch (encoder->type) { |
e9fd1c02 JN |
7860 | case INTEL_OUTPUT_DSI: |
7861 | is_dsi = true; | |
7862 | break; | |
6847d71b PZ |
7863 | default: |
7864 | break; | |
79e53945 | 7865 | } |
43565a06 | 7866 | |
c751ce4f | 7867 | num_connectors++; |
79e53945 JB |
7868 | } |
7869 | ||
f2335330 | 7870 | if (is_dsi) |
5b18e57c | 7871 | return 0; |
f2335330 | 7872 | |
190f68c5 | 7873 | if (!crtc_state->clock_set) { |
a93e255f | 7874 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7875 | |
e9fd1c02 JN |
7876 | /* |
7877 | * Returns a set of divisors for the desired target clock with | |
7878 | * the given refclk, or FALSE. The returned values represent | |
7879 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7880 | * 2) / p1 / p2. | |
7881 | */ | |
a93e255f ACO |
7882 | limit = intel_limit(crtc_state, refclk); |
7883 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7884 | crtc_state->port_clock, |
e9fd1c02 | 7885 | refclk, NULL, &clock); |
f2335330 | 7886 | if (!ok) { |
e9fd1c02 JN |
7887 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7888 | return -EINVAL; | |
7889 | } | |
79e53945 | 7890 | |
f2335330 | 7891 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7892 | crtc_state->dpll.n = clock.n; |
7893 | crtc_state->dpll.m1 = clock.m1; | |
7894 | crtc_state->dpll.m2 = clock.m2; | |
7895 | crtc_state->dpll.p1 = clock.p1; | |
7896 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7897 | } |
7026d4ac | 7898 | |
e9fd1c02 | 7899 | if (IS_GEN2(dev)) { |
c329a4ec | 7900 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7901 | num_connectors); |
9d556c99 | 7902 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7903 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7904 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7905 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7906 | } else { |
c329a4ec | 7907 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7908 | num_connectors); |
e9fd1c02 | 7909 | } |
79e53945 | 7910 | |
c8f7a0db | 7911 | return 0; |
f564048e EA |
7912 | } |
7913 | ||
2fa2fe9a | 7914 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7915 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7916 | { |
7917 | struct drm_device *dev = crtc->base.dev; | |
7918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7919 | uint32_t tmp; | |
7920 | ||
dc9e7dec VS |
7921 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7922 | return; | |
7923 | ||
2fa2fe9a | 7924 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7925 | if (!(tmp & PFIT_ENABLE)) |
7926 | return; | |
2fa2fe9a | 7927 | |
06922821 | 7928 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7929 | if (INTEL_INFO(dev)->gen < 4) { |
7930 | if (crtc->pipe != PIPE_B) | |
7931 | return; | |
2fa2fe9a DV |
7932 | } else { |
7933 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7934 | return; | |
7935 | } | |
7936 | ||
06922821 | 7937 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7938 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7939 | if (INTEL_INFO(dev)->gen < 5) | |
7940 | pipe_config->gmch_pfit.lvds_border_bits = | |
7941 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7942 | } | |
7943 | ||
acbec814 | 7944 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7945 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7946 | { |
7947 | struct drm_device *dev = crtc->base.dev; | |
7948 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7949 | int pipe = pipe_config->cpu_transcoder; | |
7950 | intel_clock_t clock; | |
7951 | u32 mdiv; | |
662c6ecb | 7952 | int refclk = 100000; |
acbec814 | 7953 | |
f573de5a SK |
7954 | /* In case of MIPI DPLL will not even be used */ |
7955 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7956 | return; | |
7957 | ||
a580516d | 7958 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7959 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7960 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7961 | |
7962 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7963 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7964 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7965 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7966 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7967 | ||
dccbea3b | 7968 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7969 | } |
7970 | ||
5724dbd1 DL |
7971 | static void |
7972 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7973 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7974 | { |
7975 | struct drm_device *dev = crtc->base.dev; | |
7976 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7977 | u32 val, base, offset; | |
7978 | int pipe = crtc->pipe, plane = crtc->plane; | |
7979 | int fourcc, pixel_format; | |
6761dd31 | 7980 | unsigned int aligned_height; |
b113d5ee | 7981 | struct drm_framebuffer *fb; |
1b842c89 | 7982 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7983 | |
42a7b088 DL |
7984 | val = I915_READ(DSPCNTR(plane)); |
7985 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7986 | return; | |
7987 | ||
d9806c9f | 7988 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7989 | if (!intel_fb) { |
1ad292b5 JB |
7990 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7991 | return; | |
7992 | } | |
7993 | ||
1b842c89 DL |
7994 | fb = &intel_fb->base; |
7995 | ||
18c5247e DV |
7996 | if (INTEL_INFO(dev)->gen >= 4) { |
7997 | if (val & DISPPLANE_TILED) { | |
49af449b | 7998 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7999 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8000 | } | |
8001 | } | |
1ad292b5 JB |
8002 | |
8003 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8004 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8005 | fb->pixel_format = fourcc; |
8006 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8007 | |
8008 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8009 | if (plane_config->tiling) |
1ad292b5 JB |
8010 | offset = I915_READ(DSPTILEOFF(plane)); |
8011 | else | |
8012 | offset = I915_READ(DSPLINOFF(plane)); | |
8013 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8014 | } else { | |
8015 | base = I915_READ(DSPADDR(plane)); | |
8016 | } | |
8017 | plane_config->base = base; | |
8018 | ||
8019 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8020 | fb->width = ((val >> 16) & 0xfff) + 1; |
8021 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8022 | |
8023 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8024 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8025 | |
b113d5ee | 8026 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8027 | fb->pixel_format, |
8028 | fb->modifier[0]); | |
1ad292b5 | 8029 | |
f37b5c2b | 8030 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8031 | |
2844a921 DL |
8032 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8033 | pipe_name(pipe), plane, fb->width, fb->height, | |
8034 | fb->bits_per_pixel, base, fb->pitches[0], | |
8035 | plane_config->size); | |
1ad292b5 | 8036 | |
2d14030b | 8037 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8038 | } |
8039 | ||
70b23a98 | 8040 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8041 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8042 | { |
8043 | struct drm_device *dev = crtc->base.dev; | |
8044 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8045 | int pipe = pipe_config->cpu_transcoder; | |
8046 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8047 | intel_clock_t clock; | |
0d7b6b11 | 8048 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8049 | int refclk = 100000; |
8050 | ||
a580516d | 8051 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8052 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8053 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8054 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8055 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8056 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8057 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8058 | |
8059 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8060 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8061 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8062 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8063 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8064 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8065 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8066 | ||
dccbea3b | 8067 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8068 | } |
8069 | ||
0e8ffe1b | 8070 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8071 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8072 | { |
8073 | struct drm_device *dev = crtc->base.dev; | |
8074 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8075 | uint32_t tmp; | |
8076 | ||
f458ebbc DV |
8077 | if (!intel_display_power_is_enabled(dev_priv, |
8078 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8079 | return false; |
8080 | ||
e143a21c | 8081 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8082 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8083 | |
0e8ffe1b DV |
8084 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8085 | if (!(tmp & PIPECONF_ENABLE)) | |
8086 | return false; | |
8087 | ||
42571aef VS |
8088 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
8089 | switch (tmp & PIPECONF_BPC_MASK) { | |
8090 | case PIPECONF_6BPC: | |
8091 | pipe_config->pipe_bpp = 18; | |
8092 | break; | |
8093 | case PIPECONF_8BPC: | |
8094 | pipe_config->pipe_bpp = 24; | |
8095 | break; | |
8096 | case PIPECONF_10BPC: | |
8097 | pipe_config->pipe_bpp = 30; | |
8098 | break; | |
8099 | default: | |
8100 | break; | |
8101 | } | |
8102 | } | |
8103 | ||
b5a9fa09 DV |
8104 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
8105 | pipe_config->limited_color_range = true; | |
8106 | ||
282740f7 VS |
8107 | if (INTEL_INFO(dev)->gen < 4) |
8108 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8109 | ||
1bd1bd80 DV |
8110 | intel_get_pipe_timings(crtc, pipe_config); |
8111 | ||
2fa2fe9a DV |
8112 | i9xx_get_pfit_config(crtc, pipe_config); |
8113 | ||
6c49f241 DV |
8114 | if (INTEL_INFO(dev)->gen >= 4) { |
8115 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8116 | pipe_config->pixel_multiplier = | |
8117 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8118 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8119 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8120 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8121 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8122 | pipe_config->pixel_multiplier = | |
8123 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8124 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8125 | } else { | |
8126 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8127 | * port and will be fixed up in the encoder->get_config | |
8128 | * function. */ | |
8129 | pipe_config->pixel_multiplier = 1; | |
8130 | } | |
8bcc2795 DV |
8131 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
8132 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
8133 | /* |
8134 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8135 | * on 830. Filter it out here so that we don't | |
8136 | * report errors due to that. | |
8137 | */ | |
8138 | if (IS_I830(dev)) | |
8139 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8140 | ||
8bcc2795 DV |
8141 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8142 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8143 | } else { |
8144 | /* Mask out read-only status bits. */ | |
8145 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8146 | DPLL_PORTC_READY_MASK | | |
8147 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8148 | } |
6c49f241 | 8149 | |
70b23a98 VS |
8150 | if (IS_CHERRYVIEW(dev)) |
8151 | chv_crtc_clock_get(crtc, pipe_config); | |
8152 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8153 | vlv_crtc_clock_get(crtc, pipe_config); |
8154 | else | |
8155 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8156 | |
0f64614d VS |
8157 | /* |
8158 | * Normally the dotclock is filled in by the encoder .get_config() | |
8159 | * but in case the pipe is enabled w/o any ports we need a sane | |
8160 | * default. | |
8161 | */ | |
8162 | pipe_config->base.adjusted_mode.crtc_clock = | |
8163 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8164 | ||
0e8ffe1b DV |
8165 | return true; |
8166 | } | |
8167 | ||
dde86e2d | 8168 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8169 | { |
8170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8171 | struct intel_encoder *encoder; |
74cfd7ac | 8172 | u32 val, final; |
13d83a67 | 8173 | bool has_lvds = false; |
199e5d79 | 8174 | bool has_cpu_edp = false; |
199e5d79 | 8175 | bool has_panel = false; |
99eb6a01 KP |
8176 | bool has_ck505 = false; |
8177 | bool can_ssc = false; | |
13d83a67 JB |
8178 | |
8179 | /* We need to take the global config into account */ | |
b2784e15 | 8180 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8181 | switch (encoder->type) { |
8182 | case INTEL_OUTPUT_LVDS: | |
8183 | has_panel = true; | |
8184 | has_lvds = true; | |
8185 | break; | |
8186 | case INTEL_OUTPUT_EDP: | |
8187 | has_panel = true; | |
2de6905f | 8188 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8189 | has_cpu_edp = true; |
8190 | break; | |
6847d71b PZ |
8191 | default: |
8192 | break; | |
13d83a67 JB |
8193 | } |
8194 | } | |
8195 | ||
99eb6a01 | 8196 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8197 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8198 | can_ssc = has_ck505; |
8199 | } else { | |
8200 | has_ck505 = false; | |
8201 | can_ssc = true; | |
8202 | } | |
8203 | ||
2de6905f ID |
8204 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8205 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8206 | |
8207 | /* Ironlake: try to setup display ref clock before DPLL | |
8208 | * enabling. This is only under driver's control after | |
8209 | * PCH B stepping, previous chipset stepping should be | |
8210 | * ignoring this setting. | |
8211 | */ | |
74cfd7ac CW |
8212 | val = I915_READ(PCH_DREF_CONTROL); |
8213 | ||
8214 | /* As we must carefully and slowly disable/enable each source in turn, | |
8215 | * compute the final state we want first and check if we need to | |
8216 | * make any changes at all. | |
8217 | */ | |
8218 | final = val; | |
8219 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8220 | if (has_ck505) | |
8221 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8222 | else | |
8223 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8224 | ||
8225 | final &= ~DREF_SSC_SOURCE_MASK; | |
8226 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8227 | final &= ~DREF_SSC1_ENABLE; | |
8228 | ||
8229 | if (has_panel) { | |
8230 | final |= DREF_SSC_SOURCE_ENABLE; | |
8231 | ||
8232 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8233 | final |= DREF_SSC1_ENABLE; | |
8234 | ||
8235 | if (has_cpu_edp) { | |
8236 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8237 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8238 | else | |
8239 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8240 | } else | |
8241 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8242 | } else { | |
8243 | final |= DREF_SSC_SOURCE_DISABLE; | |
8244 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8245 | } | |
8246 | ||
8247 | if (final == val) | |
8248 | return; | |
8249 | ||
13d83a67 | 8250 | /* Always enable nonspread source */ |
74cfd7ac | 8251 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8252 | |
99eb6a01 | 8253 | if (has_ck505) |
74cfd7ac | 8254 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8255 | else |
74cfd7ac | 8256 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8257 | |
199e5d79 | 8258 | if (has_panel) { |
74cfd7ac CW |
8259 | val &= ~DREF_SSC_SOURCE_MASK; |
8260 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8261 | |
199e5d79 | 8262 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8263 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8264 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8265 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8266 | } else |
74cfd7ac | 8267 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8268 | |
8269 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8270 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8271 | POSTING_READ(PCH_DREF_CONTROL); |
8272 | udelay(200); | |
8273 | ||
74cfd7ac | 8274 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8275 | |
8276 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8277 | if (has_cpu_edp) { |
99eb6a01 | 8278 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8279 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8280 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8281 | } else |
74cfd7ac | 8282 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8283 | } else |
74cfd7ac | 8284 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8285 | |
74cfd7ac | 8286 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8287 | POSTING_READ(PCH_DREF_CONTROL); |
8288 | udelay(200); | |
8289 | } else { | |
8290 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8291 | ||
74cfd7ac | 8292 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8293 | |
8294 | /* Turn off CPU output */ | |
74cfd7ac | 8295 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8296 | |
74cfd7ac | 8297 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8298 | POSTING_READ(PCH_DREF_CONTROL); |
8299 | udelay(200); | |
8300 | ||
8301 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8302 | val &= ~DREF_SSC_SOURCE_MASK; |
8303 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8304 | |
8305 | /* Turn off SSC1 */ | |
74cfd7ac | 8306 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8307 | |
74cfd7ac | 8308 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8309 | POSTING_READ(PCH_DREF_CONTROL); |
8310 | udelay(200); | |
8311 | } | |
74cfd7ac CW |
8312 | |
8313 | BUG_ON(val != final); | |
13d83a67 JB |
8314 | } |
8315 | ||
f31f2d55 | 8316 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8317 | { |
f31f2d55 | 8318 | uint32_t tmp; |
dde86e2d | 8319 | |
0ff066a9 PZ |
8320 | tmp = I915_READ(SOUTH_CHICKEN2); |
8321 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8322 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8323 | |
0ff066a9 PZ |
8324 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8325 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8326 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8327 | |
0ff066a9 PZ |
8328 | tmp = I915_READ(SOUTH_CHICKEN2); |
8329 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8330 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8331 | |
0ff066a9 PZ |
8332 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8333 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8334 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8335 | } |
8336 | ||
8337 | /* WaMPhyProgramming:hsw */ | |
8338 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8339 | { | |
8340 | uint32_t tmp; | |
dde86e2d PZ |
8341 | |
8342 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8343 | tmp &= ~(0xFF << 24); | |
8344 | tmp |= (0x12 << 24); | |
8345 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8346 | ||
dde86e2d PZ |
8347 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8348 | tmp |= (1 << 11); | |
8349 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8350 | ||
8351 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8352 | tmp |= (1 << 11); | |
8353 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8354 | ||
dde86e2d PZ |
8355 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8356 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8357 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8358 | ||
8359 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8360 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8361 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8362 | ||
0ff066a9 PZ |
8363 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8364 | tmp &= ~(7 << 13); | |
8365 | tmp |= (5 << 13); | |
8366 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8367 | |
0ff066a9 PZ |
8368 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8369 | tmp &= ~(7 << 13); | |
8370 | tmp |= (5 << 13); | |
8371 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8372 | |
8373 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8374 | tmp &= ~0xFF; | |
8375 | tmp |= 0x1C; | |
8376 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8377 | ||
8378 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8379 | tmp &= ~0xFF; | |
8380 | tmp |= 0x1C; | |
8381 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8382 | ||
8383 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8384 | tmp &= ~(0xFF << 16); | |
8385 | tmp |= (0x1C << 16); | |
8386 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8387 | ||
8388 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8389 | tmp &= ~(0xFF << 16); | |
8390 | tmp |= (0x1C << 16); | |
8391 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8392 | ||
0ff066a9 PZ |
8393 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8394 | tmp |= (1 << 27); | |
8395 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8396 | |
0ff066a9 PZ |
8397 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8398 | tmp |= (1 << 27); | |
8399 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8400 | |
0ff066a9 PZ |
8401 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8402 | tmp &= ~(0xF << 28); | |
8403 | tmp |= (4 << 28); | |
8404 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8405 | |
0ff066a9 PZ |
8406 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8407 | tmp &= ~(0xF << 28); | |
8408 | tmp |= (4 << 28); | |
8409 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8410 | } |
8411 | ||
2fa86a1f PZ |
8412 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8413 | * Programming" based on the parameters passed: | |
8414 | * - Sequence to enable CLKOUT_DP | |
8415 | * - Sequence to enable CLKOUT_DP without spread | |
8416 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8417 | */ | |
8418 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8419 | bool with_fdi) | |
f31f2d55 PZ |
8420 | { |
8421 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8422 | uint32_t reg, tmp; |
8423 | ||
8424 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8425 | with_spread = true; | |
c2699524 | 8426 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8427 | with_fdi = false; |
f31f2d55 | 8428 | |
a580516d | 8429 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8430 | |
8431 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8432 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8433 | tmp |= SBI_SSCCTL_PATHALT; | |
8434 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8435 | ||
8436 | udelay(24); | |
8437 | ||
2fa86a1f PZ |
8438 | if (with_spread) { |
8439 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8440 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8441 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8442 | |
2fa86a1f PZ |
8443 | if (with_fdi) { |
8444 | lpt_reset_fdi_mphy(dev_priv); | |
8445 | lpt_program_fdi_mphy(dev_priv); | |
8446 | } | |
8447 | } | |
dde86e2d | 8448 | |
c2699524 | 8449 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8450 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8451 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8452 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8453 | |
a580516d | 8454 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8455 | } |
8456 | ||
47701c3b PZ |
8457 | /* Sequence to disable CLKOUT_DP */ |
8458 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8459 | { | |
8460 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8461 | uint32_t reg, tmp; | |
8462 | ||
a580516d | 8463 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8464 | |
c2699524 | 8465 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8466 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8467 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8468 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8469 | ||
8470 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8471 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8472 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8473 | tmp |= SBI_SSCCTL_PATHALT; | |
8474 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8475 | udelay(32); | |
8476 | } | |
8477 | tmp |= SBI_SSCCTL_DISABLE; | |
8478 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8479 | } | |
8480 | ||
a580516d | 8481 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8482 | } |
8483 | ||
bf8fa3d3 PZ |
8484 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8485 | { | |
bf8fa3d3 PZ |
8486 | struct intel_encoder *encoder; |
8487 | bool has_vga = false; | |
8488 | ||
b2784e15 | 8489 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8490 | switch (encoder->type) { |
8491 | case INTEL_OUTPUT_ANALOG: | |
8492 | has_vga = true; | |
8493 | break; | |
6847d71b PZ |
8494 | default: |
8495 | break; | |
bf8fa3d3 PZ |
8496 | } |
8497 | } | |
8498 | ||
47701c3b PZ |
8499 | if (has_vga) |
8500 | lpt_enable_clkout_dp(dev, true, true); | |
8501 | else | |
8502 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8503 | } |
8504 | ||
dde86e2d PZ |
8505 | /* |
8506 | * Initialize reference clocks when the driver loads | |
8507 | */ | |
8508 | void intel_init_pch_refclk(struct drm_device *dev) | |
8509 | { | |
8510 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8511 | ironlake_init_pch_refclk(dev); | |
8512 | else if (HAS_PCH_LPT(dev)) | |
8513 | lpt_init_pch_refclk(dev); | |
8514 | } | |
8515 | ||
55bb9992 | 8516 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8517 | { |
55bb9992 | 8518 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8519 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8520 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8521 | struct drm_connector *connector; |
55bb9992 | 8522 | struct drm_connector_state *connector_state; |
d9d444cb | 8523 | struct intel_encoder *encoder; |
55bb9992 | 8524 | int num_connectors = 0, i; |
d9d444cb JB |
8525 | bool is_lvds = false; |
8526 | ||
da3ced29 | 8527 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8528 | if (connector_state->crtc != crtc_state->base.crtc) |
8529 | continue; | |
8530 | ||
8531 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8532 | ||
d9d444cb JB |
8533 | switch (encoder->type) { |
8534 | case INTEL_OUTPUT_LVDS: | |
8535 | is_lvds = true; | |
8536 | break; | |
6847d71b PZ |
8537 | default: |
8538 | break; | |
d9d444cb JB |
8539 | } |
8540 | num_connectors++; | |
8541 | } | |
8542 | ||
8543 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8544 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8545 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8546 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8547 | } |
8548 | ||
8549 | return 120000; | |
8550 | } | |
8551 | ||
6ff93609 | 8552 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8553 | { |
c8203565 | 8554 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8555 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8556 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8557 | uint32_t val; |
8558 | ||
78114071 | 8559 | val = 0; |
c8203565 | 8560 | |
6e3c9717 | 8561 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8562 | case 18: |
dfd07d72 | 8563 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8564 | break; |
8565 | case 24: | |
dfd07d72 | 8566 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8567 | break; |
8568 | case 30: | |
dfd07d72 | 8569 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8570 | break; |
8571 | case 36: | |
dfd07d72 | 8572 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8573 | break; |
8574 | default: | |
cc769b62 PZ |
8575 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8576 | BUG(); | |
c8203565 PZ |
8577 | } |
8578 | ||
6e3c9717 | 8579 | if (intel_crtc->config->dither) |
c8203565 PZ |
8580 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8581 | ||
6e3c9717 | 8582 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8583 | val |= PIPECONF_INTERLACED_ILK; |
8584 | else | |
8585 | val |= PIPECONF_PROGRESSIVE; | |
8586 | ||
6e3c9717 | 8587 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8588 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8589 | |
c8203565 PZ |
8590 | I915_WRITE(PIPECONF(pipe), val); |
8591 | POSTING_READ(PIPECONF(pipe)); | |
8592 | } | |
8593 | ||
86d3efce VS |
8594 | /* |
8595 | * Set up the pipe CSC unit. | |
8596 | * | |
8597 | * Currently only full range RGB to limited range RGB conversion | |
8598 | * is supported, but eventually this should handle various | |
8599 | * RGB<->YCbCr scenarios as well. | |
8600 | */ | |
50f3b016 | 8601 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8602 | { |
8603 | struct drm_device *dev = crtc->dev; | |
8604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8605 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8606 | int pipe = intel_crtc->pipe; | |
8607 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8608 | ||
8609 | /* | |
8610 | * TODO: Check what kind of values actually come out of the pipe | |
8611 | * with these coeff/postoff values and adjust to get the best | |
8612 | * accuracy. Perhaps we even need to take the bpc value into | |
8613 | * consideration. | |
8614 | */ | |
8615 | ||
6e3c9717 | 8616 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8617 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8618 | ||
8619 | /* | |
8620 | * GY/GU and RY/RU should be the other way around according | |
8621 | * to BSpec, but reality doesn't agree. Just set them up in | |
8622 | * a way that results in the correct picture. | |
8623 | */ | |
8624 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8625 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8626 | ||
8627 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8628 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8629 | ||
8630 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8631 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8632 | ||
8633 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8634 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8635 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8636 | ||
8637 | if (INTEL_INFO(dev)->gen > 6) { | |
8638 | uint16_t postoff = 0; | |
8639 | ||
6e3c9717 | 8640 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8641 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8642 | |
8643 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8644 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8645 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8646 | ||
8647 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8648 | } else { | |
8649 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8650 | ||
6e3c9717 | 8651 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8652 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8653 | ||
8654 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8655 | } | |
8656 | } | |
8657 | ||
6ff93609 | 8658 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8659 | { |
756f85cf PZ |
8660 | struct drm_device *dev = crtc->dev; |
8661 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8662 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8663 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8664 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8665 | uint32_t val; |
8666 | ||
3eff4faa | 8667 | val = 0; |
ee2b0b38 | 8668 | |
6e3c9717 | 8669 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8670 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8671 | ||
6e3c9717 | 8672 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8673 | val |= PIPECONF_INTERLACED_ILK; |
8674 | else | |
8675 | val |= PIPECONF_PROGRESSIVE; | |
8676 | ||
702e7a56 PZ |
8677 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8678 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8679 | |
8680 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8681 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8682 | |
3cdf122c | 8683 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8684 | val = 0; |
8685 | ||
6e3c9717 | 8686 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8687 | case 18: |
8688 | val |= PIPEMISC_DITHER_6_BPC; | |
8689 | break; | |
8690 | case 24: | |
8691 | val |= PIPEMISC_DITHER_8_BPC; | |
8692 | break; | |
8693 | case 30: | |
8694 | val |= PIPEMISC_DITHER_10_BPC; | |
8695 | break; | |
8696 | case 36: | |
8697 | val |= PIPEMISC_DITHER_12_BPC; | |
8698 | break; | |
8699 | default: | |
8700 | /* Case prevented by pipe_config_set_bpp. */ | |
8701 | BUG(); | |
8702 | } | |
8703 | ||
6e3c9717 | 8704 | if (intel_crtc->config->dither) |
756f85cf PZ |
8705 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8706 | ||
8707 | I915_WRITE(PIPEMISC(pipe), val); | |
8708 | } | |
ee2b0b38 PZ |
8709 | } |
8710 | ||
6591c6e4 | 8711 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8712 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8713 | intel_clock_t *clock, |
8714 | bool *has_reduced_clock, | |
8715 | intel_clock_t *reduced_clock) | |
8716 | { | |
8717 | struct drm_device *dev = crtc->dev; | |
8718 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8719 | int refclk; |
d4906093 | 8720 | const intel_limit_t *limit; |
c329a4ec | 8721 | bool ret; |
79e53945 | 8722 | |
55bb9992 | 8723 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8724 | |
d4906093 ML |
8725 | /* |
8726 | * Returns a set of divisors for the desired target clock with the given | |
8727 | * refclk, or FALSE. The returned values represent the clock equation: | |
8728 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8729 | */ | |
a93e255f ACO |
8730 | limit = intel_limit(crtc_state, refclk); |
8731 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8732 | crtc_state->port_clock, |
ee9300bb | 8733 | refclk, NULL, clock); |
6591c6e4 PZ |
8734 | if (!ret) |
8735 | return false; | |
cda4b7d3 | 8736 | |
6591c6e4 PZ |
8737 | return true; |
8738 | } | |
8739 | ||
d4b1931c PZ |
8740 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8741 | { | |
8742 | /* | |
8743 | * Account for spread spectrum to avoid | |
8744 | * oversubscribing the link. Max center spread | |
8745 | * is 2.5%; use 5% for safety's sake. | |
8746 | */ | |
8747 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8748 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8749 | } |
8750 | ||
7429e9d4 | 8751 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8752 | { |
7429e9d4 | 8753 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8754 | } |
8755 | ||
de13a2e3 | 8756 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8757 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8758 | u32 *fp, |
9a7c7890 | 8759 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8760 | { |
de13a2e3 | 8761 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8762 | struct drm_device *dev = crtc->dev; |
8763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8764 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8765 | struct drm_connector *connector; |
55bb9992 ACO |
8766 | struct drm_connector_state *connector_state; |
8767 | struct intel_encoder *encoder; | |
de13a2e3 | 8768 | uint32_t dpll; |
55bb9992 | 8769 | int factor, num_connectors = 0, i; |
09ede541 | 8770 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8771 | |
da3ced29 | 8772 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8773 | if (connector_state->crtc != crtc_state->base.crtc) |
8774 | continue; | |
8775 | ||
8776 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8777 | ||
8778 | switch (encoder->type) { | |
79e53945 JB |
8779 | case INTEL_OUTPUT_LVDS: |
8780 | is_lvds = true; | |
8781 | break; | |
8782 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8783 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8784 | is_sdvo = true; |
79e53945 | 8785 | break; |
6847d71b PZ |
8786 | default: |
8787 | break; | |
79e53945 | 8788 | } |
43565a06 | 8789 | |
c751ce4f | 8790 | num_connectors++; |
79e53945 | 8791 | } |
79e53945 | 8792 | |
c1858123 | 8793 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8794 | factor = 21; |
8795 | if (is_lvds) { | |
8796 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8797 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8798 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8799 | factor = 25; |
190f68c5 | 8800 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8801 | factor = 20; |
c1858123 | 8802 | |
190f68c5 | 8803 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8804 | *fp |= FP_CB_TUNE; |
2c07245f | 8805 | |
9a7c7890 DV |
8806 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8807 | *fp2 |= FP_CB_TUNE; | |
8808 | ||
5eddb70b | 8809 | dpll = 0; |
2c07245f | 8810 | |
a07d6787 EA |
8811 | if (is_lvds) |
8812 | dpll |= DPLLB_MODE_LVDS; | |
8813 | else | |
8814 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8815 | |
190f68c5 | 8816 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8817 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8818 | |
8819 | if (is_sdvo) | |
4a33e48d | 8820 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8821 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8822 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8823 | |
a07d6787 | 8824 | /* compute bitmask from p1 value */ |
190f68c5 | 8825 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8826 | /* also FPA1 */ |
190f68c5 | 8827 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8828 | |
190f68c5 | 8829 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8830 | case 5: |
8831 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8832 | break; | |
8833 | case 7: | |
8834 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8835 | break; | |
8836 | case 10: | |
8837 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8838 | break; | |
8839 | case 14: | |
8840 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8841 | break; | |
79e53945 JB |
8842 | } |
8843 | ||
b4c09f3b | 8844 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8845 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8846 | else |
8847 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8848 | ||
959e16d6 | 8849 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8850 | } |
8851 | ||
190f68c5 ACO |
8852 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8853 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8854 | { |
c7653199 | 8855 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8856 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8857 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8858 | bool ok, has_reduced_clock = false; |
8b47047b | 8859 | bool is_lvds = false; |
e2b78267 | 8860 | struct intel_shared_dpll *pll; |
de13a2e3 | 8861 | |
dd3cd74a ACO |
8862 | memset(&crtc_state->dpll_hw_state, 0, |
8863 | sizeof(crtc_state->dpll_hw_state)); | |
8864 | ||
409ee761 | 8865 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8866 | |
5dc5298b PZ |
8867 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8868 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8869 | |
190f68c5 | 8870 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8871 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8872 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8873 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8874 | return -EINVAL; | |
79e53945 | 8875 | } |
f47709a9 | 8876 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8877 | if (!crtc_state->clock_set) { |
8878 | crtc_state->dpll.n = clock.n; | |
8879 | crtc_state->dpll.m1 = clock.m1; | |
8880 | crtc_state->dpll.m2 = clock.m2; | |
8881 | crtc_state->dpll.p1 = clock.p1; | |
8882 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8883 | } |
79e53945 | 8884 | |
5dc5298b | 8885 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8886 | if (crtc_state->has_pch_encoder) { |
8887 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8888 | if (has_reduced_clock) |
7429e9d4 | 8889 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8890 | |
190f68c5 | 8891 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8892 | &fp, &reduced_clock, |
8893 | has_reduced_clock ? &fp2 : NULL); | |
8894 | ||
190f68c5 ACO |
8895 | crtc_state->dpll_hw_state.dpll = dpll; |
8896 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8897 | if (has_reduced_clock) |
190f68c5 | 8898 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8899 | else |
190f68c5 | 8900 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8901 | |
190f68c5 | 8902 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8903 | if (pll == NULL) { |
84f44ce7 | 8904 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8905 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8906 | return -EINVAL; |
8907 | } | |
3fb37703 | 8908 | } |
79e53945 | 8909 | |
ab585dea | 8910 | if (is_lvds && has_reduced_clock) |
c7653199 | 8911 | crtc->lowfreq_avail = true; |
bcd644e0 | 8912 | else |
c7653199 | 8913 | crtc->lowfreq_avail = false; |
e2b78267 | 8914 | |
c8f7a0db | 8915 | return 0; |
79e53945 JB |
8916 | } |
8917 | ||
eb14cb74 VS |
8918 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8919 | struct intel_link_m_n *m_n) | |
8920 | { | |
8921 | struct drm_device *dev = crtc->base.dev; | |
8922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8923 | enum pipe pipe = crtc->pipe; | |
8924 | ||
8925 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8926 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8927 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8928 | & ~TU_SIZE_MASK; | |
8929 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8930 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8931 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8932 | } | |
8933 | ||
8934 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8935 | enum transcoder transcoder, | |
b95af8be VK |
8936 | struct intel_link_m_n *m_n, |
8937 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8938 | { |
8939 | struct drm_device *dev = crtc->base.dev; | |
8940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8941 | enum pipe pipe = crtc->pipe; |
72419203 | 8942 | |
eb14cb74 VS |
8943 | if (INTEL_INFO(dev)->gen >= 5) { |
8944 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8945 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8946 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8947 | & ~TU_SIZE_MASK; | |
8948 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8949 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8950 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8951 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8952 | * gen < 8) and if DRRS is supported (to make sure the | |
8953 | * registers are not unnecessarily read). | |
8954 | */ | |
8955 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8956 | crtc->config->has_drrs) { |
b95af8be VK |
8957 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8958 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8959 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8960 | & ~TU_SIZE_MASK; | |
8961 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8962 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8963 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8964 | } | |
eb14cb74 VS |
8965 | } else { |
8966 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8967 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8968 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8969 | & ~TU_SIZE_MASK; | |
8970 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8971 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8972 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8973 | } | |
8974 | } | |
8975 | ||
8976 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8977 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8978 | { |
681a8504 | 8979 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8980 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8981 | else | |
8982 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8983 | &pipe_config->dp_m_n, |
8984 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8985 | } |
72419203 | 8986 | |
eb14cb74 | 8987 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8988 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8989 | { |
8990 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8991 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8992 | } |
8993 | ||
bd2e244f | 8994 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8995 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8996 | { |
8997 | struct drm_device *dev = crtc->base.dev; | |
8998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8999 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9000 | uint32_t ps_ctrl = 0; | |
9001 | int id = -1; | |
9002 | int i; | |
bd2e244f | 9003 | |
a1b2278e CK |
9004 | /* find scaler attached to this pipe */ |
9005 | for (i = 0; i < crtc->num_scalers; i++) { | |
9006 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9007 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9008 | id = i; | |
9009 | pipe_config->pch_pfit.enabled = true; | |
9010 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9011 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9012 | break; | |
9013 | } | |
9014 | } | |
bd2e244f | 9015 | |
a1b2278e CK |
9016 | scaler_state->scaler_id = id; |
9017 | if (id >= 0) { | |
9018 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9019 | } else { | |
9020 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9021 | } |
9022 | } | |
9023 | ||
5724dbd1 DL |
9024 | static void |
9025 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9026 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9027 | { |
9028 | struct drm_device *dev = crtc->base.dev; | |
9029 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9030 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9031 | int pipe = crtc->pipe; |
9032 | int fourcc, pixel_format; | |
6761dd31 | 9033 | unsigned int aligned_height; |
bc8d7dff | 9034 | struct drm_framebuffer *fb; |
1b842c89 | 9035 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9036 | |
d9806c9f | 9037 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9038 | if (!intel_fb) { |
bc8d7dff DL |
9039 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9040 | return; | |
9041 | } | |
9042 | ||
1b842c89 DL |
9043 | fb = &intel_fb->base; |
9044 | ||
bc8d7dff | 9045 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9046 | if (!(val & PLANE_CTL_ENABLE)) |
9047 | goto error; | |
9048 | ||
bc8d7dff DL |
9049 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9050 | fourcc = skl_format_to_fourcc(pixel_format, | |
9051 | val & PLANE_CTL_ORDER_RGBX, | |
9052 | val & PLANE_CTL_ALPHA_MASK); | |
9053 | fb->pixel_format = fourcc; | |
9054 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9055 | ||
40f46283 DL |
9056 | tiling = val & PLANE_CTL_TILED_MASK; |
9057 | switch (tiling) { | |
9058 | case PLANE_CTL_TILED_LINEAR: | |
9059 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9060 | break; | |
9061 | case PLANE_CTL_TILED_X: | |
9062 | plane_config->tiling = I915_TILING_X; | |
9063 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9064 | break; | |
9065 | case PLANE_CTL_TILED_Y: | |
9066 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9067 | break; | |
9068 | case PLANE_CTL_TILED_YF: | |
9069 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9070 | break; | |
9071 | default: | |
9072 | MISSING_CASE(tiling); | |
9073 | goto error; | |
9074 | } | |
9075 | ||
bc8d7dff DL |
9076 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9077 | plane_config->base = base; | |
9078 | ||
9079 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9080 | ||
9081 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9082 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9083 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9084 | ||
9085 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
9086 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9087 | fb->pixel_format); | |
bc8d7dff DL |
9088 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9089 | ||
9090 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9091 | fb->pixel_format, |
9092 | fb->modifier[0]); | |
bc8d7dff | 9093 | |
f37b5c2b | 9094 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9095 | |
9096 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9097 | pipe_name(pipe), fb->width, fb->height, | |
9098 | fb->bits_per_pixel, base, fb->pitches[0], | |
9099 | plane_config->size); | |
9100 | ||
2d14030b | 9101 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9102 | return; |
9103 | ||
9104 | error: | |
9105 | kfree(fb); | |
9106 | } | |
9107 | ||
2fa2fe9a | 9108 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9109 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9110 | { |
9111 | struct drm_device *dev = crtc->base.dev; | |
9112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9113 | uint32_t tmp; | |
9114 | ||
9115 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9116 | ||
9117 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9118 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9119 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9120 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9121 | |
9122 | /* We currently do not free assignements of panel fitters on | |
9123 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9124 | * differentiates them) so just WARN about this case for now. */ | |
9125 | if (IS_GEN7(dev)) { | |
9126 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9127 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9128 | } | |
2fa2fe9a | 9129 | } |
79e53945 JB |
9130 | } |
9131 | ||
5724dbd1 DL |
9132 | static void |
9133 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9134 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9135 | { |
9136 | struct drm_device *dev = crtc->base.dev; | |
9137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9138 | u32 val, base, offset; | |
aeee5a49 | 9139 | int pipe = crtc->pipe; |
4c6baa59 | 9140 | int fourcc, pixel_format; |
6761dd31 | 9141 | unsigned int aligned_height; |
b113d5ee | 9142 | struct drm_framebuffer *fb; |
1b842c89 | 9143 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9144 | |
42a7b088 DL |
9145 | val = I915_READ(DSPCNTR(pipe)); |
9146 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9147 | return; | |
9148 | ||
d9806c9f | 9149 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9150 | if (!intel_fb) { |
4c6baa59 JB |
9151 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9152 | return; | |
9153 | } | |
9154 | ||
1b842c89 DL |
9155 | fb = &intel_fb->base; |
9156 | ||
18c5247e DV |
9157 | if (INTEL_INFO(dev)->gen >= 4) { |
9158 | if (val & DISPPLANE_TILED) { | |
49af449b | 9159 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9160 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9161 | } | |
9162 | } | |
4c6baa59 JB |
9163 | |
9164 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9165 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9166 | fb->pixel_format = fourcc; |
9167 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9168 | |
aeee5a49 | 9169 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9170 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9171 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9172 | } else { |
49af449b | 9173 | if (plane_config->tiling) |
aeee5a49 | 9174 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9175 | else |
aeee5a49 | 9176 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9177 | } |
9178 | plane_config->base = base; | |
9179 | ||
9180 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9181 | fb->width = ((val >> 16) & 0xfff) + 1; |
9182 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9183 | |
9184 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9185 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9186 | |
b113d5ee | 9187 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9188 | fb->pixel_format, |
9189 | fb->modifier[0]); | |
4c6baa59 | 9190 | |
f37b5c2b | 9191 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9192 | |
2844a921 DL |
9193 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9194 | pipe_name(pipe), fb->width, fb->height, | |
9195 | fb->bits_per_pixel, base, fb->pitches[0], | |
9196 | plane_config->size); | |
b113d5ee | 9197 | |
2d14030b | 9198 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9199 | } |
9200 | ||
0e8ffe1b | 9201 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9202 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9203 | { |
9204 | struct drm_device *dev = crtc->base.dev; | |
9205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9206 | uint32_t tmp; | |
9207 | ||
f458ebbc DV |
9208 | if (!intel_display_power_is_enabled(dev_priv, |
9209 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9210 | return false; |
9211 | ||
e143a21c | 9212 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9213 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9214 | |
0e8ffe1b DV |
9215 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9216 | if (!(tmp & PIPECONF_ENABLE)) | |
9217 | return false; | |
9218 | ||
42571aef VS |
9219 | switch (tmp & PIPECONF_BPC_MASK) { |
9220 | case PIPECONF_6BPC: | |
9221 | pipe_config->pipe_bpp = 18; | |
9222 | break; | |
9223 | case PIPECONF_8BPC: | |
9224 | pipe_config->pipe_bpp = 24; | |
9225 | break; | |
9226 | case PIPECONF_10BPC: | |
9227 | pipe_config->pipe_bpp = 30; | |
9228 | break; | |
9229 | case PIPECONF_12BPC: | |
9230 | pipe_config->pipe_bpp = 36; | |
9231 | break; | |
9232 | default: | |
9233 | break; | |
9234 | } | |
9235 | ||
b5a9fa09 DV |
9236 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9237 | pipe_config->limited_color_range = true; | |
9238 | ||
ab9412ba | 9239 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9240 | struct intel_shared_dpll *pll; |
9241 | ||
88adfff1 DV |
9242 | pipe_config->has_pch_encoder = true; |
9243 | ||
627eb5a3 DV |
9244 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9245 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9246 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9247 | |
9248 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9249 | |
c0d43d62 | 9250 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9251 | pipe_config->shared_dpll = |
9252 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9253 | } else { |
9254 | tmp = I915_READ(PCH_DPLL_SEL); | |
9255 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9256 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9257 | else | |
9258 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9259 | } | |
66e985c0 DV |
9260 | |
9261 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9262 | ||
9263 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9264 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9265 | |
9266 | tmp = pipe_config->dpll_hw_state.dpll; | |
9267 | pipe_config->pixel_multiplier = | |
9268 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9269 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9270 | |
9271 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9272 | } else { |
9273 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9274 | } |
9275 | ||
1bd1bd80 DV |
9276 | intel_get_pipe_timings(crtc, pipe_config); |
9277 | ||
2fa2fe9a DV |
9278 | ironlake_get_pfit_config(crtc, pipe_config); |
9279 | ||
0e8ffe1b DV |
9280 | return true; |
9281 | } | |
9282 | ||
be256dc7 PZ |
9283 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9284 | { | |
9285 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9286 | struct intel_crtc *crtc; |
be256dc7 | 9287 | |
d3fcc808 | 9288 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9289 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9290 | pipe_name(crtc->pipe)); |
9291 | ||
e2c719b7 RC |
9292 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9293 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
9294 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
9295 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
9296 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
9297 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9298 | "CPU PWM1 enabled\n"); |
c5107b87 | 9299 | if (IS_HASWELL(dev)) |
e2c719b7 | 9300 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9301 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9302 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9303 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9304 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9305 | "Utility pin enabled\n"); |
e2c719b7 | 9306 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9307 | |
9926ada1 PZ |
9308 | /* |
9309 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9310 | * interrupts remain enabled. We used to check for that, but since it's | |
9311 | * gen-specific and since we only disable LCPLL after we fully disable | |
9312 | * the interrupts, the check below should be enough. | |
9313 | */ | |
e2c719b7 | 9314 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9315 | } |
9316 | ||
9ccd5aeb PZ |
9317 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9318 | { | |
9319 | struct drm_device *dev = dev_priv->dev; | |
9320 | ||
9321 | if (IS_HASWELL(dev)) | |
9322 | return I915_READ(D_COMP_HSW); | |
9323 | else | |
9324 | return I915_READ(D_COMP_BDW); | |
9325 | } | |
9326 | ||
3c4c9b81 PZ |
9327 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9328 | { | |
9329 | struct drm_device *dev = dev_priv->dev; | |
9330 | ||
9331 | if (IS_HASWELL(dev)) { | |
9332 | mutex_lock(&dev_priv->rps.hw_lock); | |
9333 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9334 | val)) | |
f475dadf | 9335 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9336 | mutex_unlock(&dev_priv->rps.hw_lock); |
9337 | } else { | |
9ccd5aeb PZ |
9338 | I915_WRITE(D_COMP_BDW, val); |
9339 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9340 | } |
be256dc7 PZ |
9341 | } |
9342 | ||
9343 | /* | |
9344 | * This function implements pieces of two sequences from BSpec: | |
9345 | * - Sequence for display software to disable LCPLL | |
9346 | * - Sequence for display software to allow package C8+ | |
9347 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9348 | * register. Callers should take care of disabling all the display engine | |
9349 | * functions, doing the mode unset, fixing interrupts, etc. | |
9350 | */ | |
6ff58d53 PZ |
9351 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9352 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9353 | { |
9354 | uint32_t val; | |
9355 | ||
9356 | assert_can_disable_lcpll(dev_priv); | |
9357 | ||
9358 | val = I915_READ(LCPLL_CTL); | |
9359 | ||
9360 | if (switch_to_fclk) { | |
9361 | val |= LCPLL_CD_SOURCE_FCLK; | |
9362 | I915_WRITE(LCPLL_CTL, val); | |
9363 | ||
9364 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9365 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9366 | DRM_ERROR("Switching to FCLK failed\n"); | |
9367 | ||
9368 | val = I915_READ(LCPLL_CTL); | |
9369 | } | |
9370 | ||
9371 | val |= LCPLL_PLL_DISABLE; | |
9372 | I915_WRITE(LCPLL_CTL, val); | |
9373 | POSTING_READ(LCPLL_CTL); | |
9374 | ||
9375 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9376 | DRM_ERROR("LCPLL still locked\n"); | |
9377 | ||
9ccd5aeb | 9378 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9379 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9380 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9381 | ndelay(100); |
9382 | ||
9ccd5aeb PZ |
9383 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9384 | 1)) | |
be256dc7 PZ |
9385 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9386 | ||
9387 | if (allow_power_down) { | |
9388 | val = I915_READ(LCPLL_CTL); | |
9389 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9390 | I915_WRITE(LCPLL_CTL, val); | |
9391 | POSTING_READ(LCPLL_CTL); | |
9392 | } | |
9393 | } | |
9394 | ||
9395 | /* | |
9396 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9397 | * source. | |
9398 | */ | |
6ff58d53 | 9399 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9400 | { |
9401 | uint32_t val; | |
9402 | ||
9403 | val = I915_READ(LCPLL_CTL); | |
9404 | ||
9405 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9406 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9407 | return; | |
9408 | ||
a8a8bd54 PZ |
9409 | /* |
9410 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9411 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9412 | */ |
59bad947 | 9413 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9414 | |
be256dc7 PZ |
9415 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9416 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9417 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9418 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9419 | } |
9420 | ||
9ccd5aeb | 9421 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9422 | val |= D_COMP_COMP_FORCE; |
9423 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9424 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9425 | |
9426 | val = I915_READ(LCPLL_CTL); | |
9427 | val &= ~LCPLL_PLL_DISABLE; | |
9428 | I915_WRITE(LCPLL_CTL, val); | |
9429 | ||
9430 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9431 | DRM_ERROR("LCPLL not locked yet\n"); | |
9432 | ||
9433 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9434 | val = I915_READ(LCPLL_CTL); | |
9435 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9436 | I915_WRITE(LCPLL_CTL, val); | |
9437 | ||
9438 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9439 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9440 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9441 | } | |
215733fa | 9442 | |
59bad947 | 9443 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9444 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9445 | } |
9446 | ||
765dab67 PZ |
9447 | /* |
9448 | * Package states C8 and deeper are really deep PC states that can only be | |
9449 | * reached when all the devices on the system allow it, so even if the graphics | |
9450 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9451 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9452 | * | |
9453 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9454 | * well is disabled and most interrupts are disabled, and these are also | |
9455 | * requirements for runtime PM. When these conditions are met, we manually do | |
9456 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9457 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9458 | * hang the machine. | |
9459 | * | |
9460 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9461 | * the state of some registers, so when we come back from PC8+ we need to | |
9462 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9463 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9464 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9465 | * because of the runtime PM support). | |
9466 | * | |
9467 | * For more, read "Display Sequences for Package C8" on the hardware | |
9468 | * documentation. | |
9469 | */ | |
a14cb6fc | 9470 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9471 | { |
c67a470b PZ |
9472 | struct drm_device *dev = dev_priv->dev; |
9473 | uint32_t val; | |
9474 | ||
c67a470b PZ |
9475 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9476 | ||
c2699524 | 9477 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9478 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9479 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9480 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9481 | } | |
9482 | ||
9483 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9484 | hsw_disable_lcpll(dev_priv, true, true); |
9485 | } | |
9486 | ||
a14cb6fc | 9487 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9488 | { |
9489 | struct drm_device *dev = dev_priv->dev; | |
9490 | uint32_t val; | |
9491 | ||
c67a470b PZ |
9492 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9493 | ||
9494 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9495 | lpt_init_pch_refclk(dev); |
9496 | ||
c2699524 | 9497 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9498 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9499 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9500 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9501 | } | |
9502 | ||
9503 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9504 | } |
9505 | ||
27c329ed | 9506 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9507 | { |
a821fc46 | 9508 | struct drm_device *dev = old_state->dev; |
27c329ed | 9509 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
f8437dd1 | 9510 | |
27c329ed | 9511 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9512 | } |
9513 | ||
b432e5cf | 9514 | /* compute the max rate for new configuration */ |
27c329ed | 9515 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9516 | { |
b432e5cf | 9517 | struct intel_crtc *intel_crtc; |
27c329ed | 9518 | struct intel_crtc_state *crtc_state; |
b432e5cf | 9519 | int max_pixel_rate = 0; |
b432e5cf | 9520 | |
27c329ed ML |
9521 | for_each_intel_crtc(state->dev, intel_crtc) { |
9522 | int pixel_rate; | |
9523 | ||
9524 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
9525 | if (IS_ERR(crtc_state)) | |
9526 | return PTR_ERR(crtc_state); | |
9527 | ||
9528 | if (!crtc_state->base.enable) | |
b432e5cf VS |
9529 | continue; |
9530 | ||
27c329ed | 9531 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9532 | |
9533 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
27c329ed | 9534 | if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled) |
b432e5cf VS |
9535 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9536 | ||
9537 | max_pixel_rate = max(max_pixel_rate, pixel_rate); | |
9538 | } | |
9539 | ||
9540 | return max_pixel_rate; | |
9541 | } | |
9542 | ||
9543 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9544 | { | |
9545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9546 | uint32_t val, data; | |
9547 | int ret; | |
9548 | ||
9549 | if (WARN((I915_READ(LCPLL_CTL) & | |
9550 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9551 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9552 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9553 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9554 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9555 | return; | |
9556 | ||
9557 | mutex_lock(&dev_priv->rps.hw_lock); | |
9558 | ret = sandybridge_pcode_write(dev_priv, | |
9559 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9560 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9561 | if (ret) { | |
9562 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9563 | return; | |
9564 | } | |
9565 | ||
9566 | val = I915_READ(LCPLL_CTL); | |
9567 | val |= LCPLL_CD_SOURCE_FCLK; | |
9568 | I915_WRITE(LCPLL_CTL, val); | |
9569 | ||
9570 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9571 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9572 | DRM_ERROR("Switching to FCLK failed\n"); | |
9573 | ||
9574 | val = I915_READ(LCPLL_CTL); | |
9575 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9576 | ||
9577 | switch (cdclk) { | |
9578 | case 450000: | |
9579 | val |= LCPLL_CLK_FREQ_450; | |
9580 | data = 0; | |
9581 | break; | |
9582 | case 540000: | |
9583 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9584 | data = 1; | |
9585 | break; | |
9586 | case 337500: | |
9587 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9588 | data = 2; | |
9589 | break; | |
9590 | case 675000: | |
9591 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9592 | data = 3; | |
9593 | break; | |
9594 | default: | |
9595 | WARN(1, "invalid cdclk frequency\n"); | |
9596 | return; | |
9597 | } | |
9598 | ||
9599 | I915_WRITE(LCPLL_CTL, val); | |
9600 | ||
9601 | val = I915_READ(LCPLL_CTL); | |
9602 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9603 | I915_WRITE(LCPLL_CTL, val); | |
9604 | ||
9605 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9606 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9607 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9608 | ||
9609 | mutex_lock(&dev_priv->rps.hw_lock); | |
9610 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9611 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9612 | ||
9613 | intel_update_cdclk(dev); | |
9614 | ||
9615 | WARN(cdclk != dev_priv->cdclk_freq, | |
9616 | "cdclk requested %d kHz but got %d kHz\n", | |
9617 | cdclk, dev_priv->cdclk_freq); | |
9618 | } | |
9619 | ||
27c329ed | 9620 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9621 | { |
27c329ed ML |
9622 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
9623 | int max_pixclk = ilk_max_pixel_rate(state); | |
b432e5cf VS |
9624 | int cdclk; |
9625 | ||
9626 | /* | |
9627 | * FIXME should also account for plane ratio | |
9628 | * once 64bpp pixel formats are supported. | |
9629 | */ | |
27c329ed | 9630 | if (max_pixclk > 540000) |
b432e5cf | 9631 | cdclk = 675000; |
27c329ed | 9632 | else if (max_pixclk > 450000) |
b432e5cf | 9633 | cdclk = 540000; |
27c329ed | 9634 | else if (max_pixclk > 337500) |
b432e5cf VS |
9635 | cdclk = 450000; |
9636 | else | |
9637 | cdclk = 337500; | |
9638 | ||
9639 | /* | |
9640 | * FIXME move the cdclk caclulation to | |
9641 | * compute_config() so we can fail gracegully. | |
9642 | */ | |
9643 | if (cdclk > dev_priv->max_cdclk_freq) { | |
9644 | DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n", | |
9645 | cdclk, dev_priv->max_cdclk_freq); | |
9646 | cdclk = dev_priv->max_cdclk_freq; | |
9647 | } | |
9648 | ||
27c329ed | 9649 | to_intel_atomic_state(state)->cdclk = cdclk; |
b432e5cf VS |
9650 | |
9651 | return 0; | |
9652 | } | |
9653 | ||
27c329ed | 9654 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9655 | { |
27c329ed ML |
9656 | struct drm_device *dev = old_state->dev; |
9657 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; | |
b432e5cf | 9658 | |
27c329ed | 9659 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9660 | } |
9661 | ||
190f68c5 ACO |
9662 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9663 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9664 | { |
190f68c5 | 9665 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9666 | return -EINVAL; |
716c2e55 | 9667 | |
c7653199 | 9668 | crtc->lowfreq_avail = false; |
644cef34 | 9669 | |
c8f7a0db | 9670 | return 0; |
79e53945 JB |
9671 | } |
9672 | ||
3760b59c S |
9673 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9674 | enum port port, | |
9675 | struct intel_crtc_state *pipe_config) | |
9676 | { | |
9677 | switch (port) { | |
9678 | case PORT_A: | |
9679 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9680 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9681 | break; | |
9682 | case PORT_B: | |
9683 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9684 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9685 | break; | |
9686 | case PORT_C: | |
9687 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9688 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9689 | break; | |
9690 | default: | |
9691 | DRM_ERROR("Incorrect port type\n"); | |
9692 | } | |
9693 | } | |
9694 | ||
96b7dfb7 S |
9695 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9696 | enum port port, | |
5cec258b | 9697 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9698 | { |
3148ade7 | 9699 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9700 | |
9701 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9702 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9703 | ||
9704 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9705 | case SKL_DPLL0: |
9706 | /* | |
9707 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9708 | * of the shared DPLL framework and thus needs to be read out | |
9709 | * separately | |
9710 | */ | |
9711 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9712 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9713 | break; | |
96b7dfb7 S |
9714 | case SKL_DPLL1: |
9715 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9716 | break; | |
9717 | case SKL_DPLL2: | |
9718 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9719 | break; | |
9720 | case SKL_DPLL3: | |
9721 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9722 | break; | |
96b7dfb7 S |
9723 | } |
9724 | } | |
9725 | ||
7d2c8175 DL |
9726 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9727 | enum port port, | |
5cec258b | 9728 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9729 | { |
9730 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9731 | ||
9732 | switch (pipe_config->ddi_pll_sel) { | |
9733 | case PORT_CLK_SEL_WRPLL1: | |
9734 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9735 | break; | |
9736 | case PORT_CLK_SEL_WRPLL2: | |
9737 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9738 | break; | |
9739 | } | |
9740 | } | |
9741 | ||
26804afd | 9742 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9743 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9744 | { |
9745 | struct drm_device *dev = crtc->base.dev; | |
9746 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9747 | struct intel_shared_dpll *pll; |
26804afd DV |
9748 | enum port port; |
9749 | uint32_t tmp; | |
9750 | ||
9751 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9752 | ||
9753 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9754 | ||
96b7dfb7 S |
9755 | if (IS_SKYLAKE(dev)) |
9756 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
3760b59c S |
9757 | else if (IS_BROXTON(dev)) |
9758 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9759 | else |
9760 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9761 | |
d452c5b6 DV |
9762 | if (pipe_config->shared_dpll >= 0) { |
9763 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9764 | ||
9765 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9766 | &pipe_config->dpll_hw_state)); | |
9767 | } | |
9768 | ||
26804afd DV |
9769 | /* |
9770 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9771 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9772 | * the PCH transcoder is on. | |
9773 | */ | |
ca370455 DL |
9774 | if (INTEL_INFO(dev)->gen < 9 && |
9775 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9776 | pipe_config->has_pch_encoder = true; |
9777 | ||
9778 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9779 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9780 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9781 | ||
9782 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9783 | } | |
9784 | } | |
9785 | ||
0e8ffe1b | 9786 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9787 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9788 | { |
9789 | struct drm_device *dev = crtc->base.dev; | |
9790 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9791 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9792 | uint32_t tmp; |
9793 | ||
f458ebbc | 9794 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9795 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9796 | return false; | |
9797 | ||
e143a21c | 9798 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9799 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9800 | ||
eccb140b DV |
9801 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9802 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9803 | enum pipe trans_edp_pipe; | |
9804 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9805 | default: | |
9806 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9807 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9808 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9809 | trans_edp_pipe = PIPE_A; | |
9810 | break; | |
9811 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9812 | trans_edp_pipe = PIPE_B; | |
9813 | break; | |
9814 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9815 | trans_edp_pipe = PIPE_C; | |
9816 | break; | |
9817 | } | |
9818 | ||
9819 | if (trans_edp_pipe == crtc->pipe) | |
9820 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9821 | } | |
9822 | ||
f458ebbc | 9823 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9824 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9825 | return false; |
9826 | ||
eccb140b | 9827 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9828 | if (!(tmp & PIPECONF_ENABLE)) |
9829 | return false; | |
9830 | ||
26804afd | 9831 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9832 | |
1bd1bd80 DV |
9833 | intel_get_pipe_timings(crtc, pipe_config); |
9834 | ||
a1b2278e CK |
9835 | if (INTEL_INFO(dev)->gen >= 9) { |
9836 | skl_init_scalers(dev, crtc, pipe_config); | |
9837 | } | |
9838 | ||
2fa2fe9a | 9839 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
9840 | |
9841 | if (INTEL_INFO(dev)->gen >= 9) { | |
9842 | pipe_config->scaler_state.scaler_id = -1; | |
9843 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9844 | } | |
9845 | ||
bd2e244f | 9846 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 9847 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 9848 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9849 | else |
1c132b44 | 9850 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9851 | } |
88adfff1 | 9852 | |
e59150dc JB |
9853 | if (IS_HASWELL(dev)) |
9854 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9855 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9856 | |
ebb69c95 CT |
9857 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9858 | pipe_config->pixel_multiplier = | |
9859 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9860 | } else { | |
9861 | pipe_config->pixel_multiplier = 1; | |
9862 | } | |
6c49f241 | 9863 | |
0e8ffe1b DV |
9864 | return true; |
9865 | } | |
9866 | ||
560b85bb CW |
9867 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9868 | { | |
9869 | struct drm_device *dev = crtc->dev; | |
9870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9872 | uint32_t cntl = 0, size = 0; |
560b85bb | 9873 | |
dc41c154 | 9874 | if (base) { |
3dd512fb MR |
9875 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9876 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9877 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9878 | ||
9879 | switch (stride) { | |
9880 | default: | |
9881 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9882 | width, stride); | |
9883 | stride = 256; | |
9884 | /* fallthrough */ | |
9885 | case 256: | |
9886 | case 512: | |
9887 | case 1024: | |
9888 | case 2048: | |
9889 | break; | |
4b0e333e CW |
9890 | } |
9891 | ||
dc41c154 VS |
9892 | cntl |= CURSOR_ENABLE | |
9893 | CURSOR_GAMMA_ENABLE | | |
9894 | CURSOR_FORMAT_ARGB | | |
9895 | CURSOR_STRIDE(stride); | |
9896 | ||
9897 | size = (height << 12) | width; | |
4b0e333e | 9898 | } |
560b85bb | 9899 | |
dc41c154 VS |
9900 | if (intel_crtc->cursor_cntl != 0 && |
9901 | (intel_crtc->cursor_base != base || | |
9902 | intel_crtc->cursor_size != size || | |
9903 | intel_crtc->cursor_cntl != cntl)) { | |
9904 | /* On these chipsets we can only modify the base/size/stride | |
9905 | * whilst the cursor is disabled. | |
9906 | */ | |
0b87c24e VS |
9907 | I915_WRITE(CURCNTR(PIPE_A), 0); |
9908 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 9909 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9910 | } |
560b85bb | 9911 | |
99d1f387 | 9912 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 9913 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
9914 | intel_crtc->cursor_base = base; |
9915 | } | |
4726e0b0 | 9916 | |
dc41c154 VS |
9917 | if (intel_crtc->cursor_size != size) { |
9918 | I915_WRITE(CURSIZE, size); | |
9919 | intel_crtc->cursor_size = size; | |
4b0e333e | 9920 | } |
560b85bb | 9921 | |
4b0e333e | 9922 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
9923 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
9924 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 9925 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9926 | } |
560b85bb CW |
9927 | } |
9928 | ||
560b85bb | 9929 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9930 | { |
9931 | struct drm_device *dev = crtc->dev; | |
9932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9933 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9934 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9935 | uint32_t cntl; |
9936 | ||
9937 | cntl = 0; | |
9938 | if (base) { | |
9939 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 9940 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
9941 | case 64: |
9942 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9943 | break; | |
9944 | case 128: | |
9945 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9946 | break; | |
9947 | case 256: | |
9948 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9949 | break; | |
9950 | default: | |
3dd512fb | 9951 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 9952 | return; |
65a21cd6 | 9953 | } |
4b0e333e | 9954 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
9955 | |
9956 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
9957 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 9958 | } |
65a21cd6 | 9959 | |
8e7d688b | 9960 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
9961 | cntl |= CURSOR_ROTATE_180; |
9962 | ||
4b0e333e CW |
9963 | if (intel_crtc->cursor_cntl != cntl) { |
9964 | I915_WRITE(CURCNTR(pipe), cntl); | |
9965 | POSTING_READ(CURCNTR(pipe)); | |
9966 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9967 | } |
4b0e333e | 9968 | |
65a21cd6 | 9969 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9970 | I915_WRITE(CURBASE(pipe), base); |
9971 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9972 | |
9973 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9974 | } |
9975 | ||
cda4b7d3 | 9976 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
9977 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
9978 | bool on) | |
cda4b7d3 CW |
9979 | { |
9980 | struct drm_device *dev = crtc->dev; | |
9981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9982 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9983 | int pipe = intel_crtc->pipe; | |
9b4101be ML |
9984 | struct drm_plane_state *cursor_state = crtc->cursor->state; |
9985 | int x = cursor_state->crtc_x; | |
9986 | int y = cursor_state->crtc_y; | |
d6e4db15 | 9987 | u32 base = 0, pos = 0; |
cda4b7d3 | 9988 | |
d6e4db15 | 9989 | if (on) |
cda4b7d3 | 9990 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 9991 | |
6e3c9717 | 9992 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
9993 | base = 0; |
9994 | ||
6e3c9717 | 9995 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
9996 | base = 0; |
9997 | ||
9998 | if (x < 0) { | |
9b4101be | 9999 | if (x + cursor_state->crtc_w <= 0) |
cda4b7d3 CW |
10000 | base = 0; |
10001 | ||
10002 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10003 | x = -x; | |
10004 | } | |
10005 | pos |= x << CURSOR_X_SHIFT; | |
10006 | ||
10007 | if (y < 0) { | |
9b4101be | 10008 | if (y + cursor_state->crtc_h <= 0) |
cda4b7d3 CW |
10009 | base = 0; |
10010 | ||
10011 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10012 | y = -y; | |
10013 | } | |
10014 | pos |= y << CURSOR_Y_SHIFT; | |
10015 | ||
4b0e333e | 10016 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
10017 | return; |
10018 | ||
5efb3e28 VS |
10019 | I915_WRITE(CURPOS(pipe), pos); |
10020 | ||
4398ad45 VS |
10021 | /* ILK+ do this automagically */ |
10022 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 10023 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
9b4101be ML |
10024 | base += (cursor_state->crtc_h * |
10025 | cursor_state->crtc_w - 1) * 4; | |
4398ad45 VS |
10026 | } |
10027 | ||
8ac54669 | 10028 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
10029 | i845_update_cursor(crtc, base); |
10030 | else | |
10031 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
10032 | } |
10033 | ||
dc41c154 VS |
10034 | static bool cursor_size_ok(struct drm_device *dev, |
10035 | uint32_t width, uint32_t height) | |
10036 | { | |
10037 | if (width == 0 || height == 0) | |
10038 | return false; | |
10039 | ||
10040 | /* | |
10041 | * 845g/865g are special in that they are only limited by | |
10042 | * the width of their cursors, the height is arbitrary up to | |
10043 | * the precision of the register. Everything else requires | |
10044 | * square cursors, limited to a few power-of-two sizes. | |
10045 | */ | |
10046 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10047 | if ((width & 63) != 0) | |
10048 | return false; | |
10049 | ||
10050 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10051 | return false; | |
10052 | ||
10053 | if (height > 1023) | |
10054 | return false; | |
10055 | } else { | |
10056 | switch (width | height) { | |
10057 | case 256: | |
10058 | case 128: | |
10059 | if (IS_GEN2(dev)) | |
10060 | return false; | |
10061 | case 64: | |
10062 | break; | |
10063 | default: | |
10064 | return false; | |
10065 | } | |
10066 | } | |
10067 | ||
10068 | return true; | |
10069 | } | |
10070 | ||
79e53945 | 10071 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10072 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10073 | { |
7203425a | 10074 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10075 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10076 | |
7203425a | 10077 | for (i = start; i < end; i++) { |
79e53945 JB |
10078 | intel_crtc->lut_r[i] = red[i] >> 8; |
10079 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10080 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10081 | } | |
10082 | ||
10083 | intel_crtc_load_lut(crtc); | |
10084 | } | |
10085 | ||
79e53945 JB |
10086 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10087 | static struct drm_display_mode load_detect_mode = { | |
10088 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10089 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10090 | }; | |
10091 | ||
a8bb6818 DV |
10092 | struct drm_framebuffer * |
10093 | __intel_framebuffer_create(struct drm_device *dev, | |
10094 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10095 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10096 | { |
10097 | struct intel_framebuffer *intel_fb; | |
10098 | int ret; | |
10099 | ||
10100 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
10101 | if (!intel_fb) { | |
6ccb81f2 | 10102 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
10103 | return ERR_PTR(-ENOMEM); |
10104 | } | |
10105 | ||
10106 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10107 | if (ret) |
10108 | goto err; | |
d2dff872 CW |
10109 | |
10110 | return &intel_fb->base; | |
dd4916c5 | 10111 | err: |
6ccb81f2 | 10112 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
10113 | kfree(intel_fb); |
10114 | ||
10115 | return ERR_PTR(ret); | |
d2dff872 CW |
10116 | } |
10117 | ||
b5ea642a | 10118 | static struct drm_framebuffer * |
a8bb6818 DV |
10119 | intel_framebuffer_create(struct drm_device *dev, |
10120 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10121 | struct drm_i915_gem_object *obj) | |
10122 | { | |
10123 | struct drm_framebuffer *fb; | |
10124 | int ret; | |
10125 | ||
10126 | ret = i915_mutex_lock_interruptible(dev); | |
10127 | if (ret) | |
10128 | return ERR_PTR(ret); | |
10129 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10130 | mutex_unlock(&dev->struct_mutex); | |
10131 | ||
10132 | return fb; | |
10133 | } | |
10134 | ||
d2dff872 CW |
10135 | static u32 |
10136 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10137 | { | |
10138 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10139 | return ALIGN(pitch, 64); | |
10140 | } | |
10141 | ||
10142 | static u32 | |
10143 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10144 | { | |
10145 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10146 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10147 | } |
10148 | ||
10149 | static struct drm_framebuffer * | |
10150 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10151 | struct drm_display_mode *mode, | |
10152 | int depth, int bpp) | |
10153 | { | |
10154 | struct drm_i915_gem_object *obj; | |
0fed39bd | 10155 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10156 | |
10157 | obj = i915_gem_alloc_object(dev, | |
10158 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10159 | if (obj == NULL) | |
10160 | return ERR_PTR(-ENOMEM); | |
10161 | ||
10162 | mode_cmd.width = mode->hdisplay; | |
10163 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10164 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10165 | bpp); | |
5ca0c34a | 10166 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
10167 | |
10168 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
10169 | } | |
10170 | ||
10171 | static struct drm_framebuffer * | |
10172 | mode_fits_in_fbdev(struct drm_device *dev, | |
10173 | struct drm_display_mode *mode) | |
10174 | { | |
0695726e | 10175 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10176 | struct drm_i915_private *dev_priv = dev->dev_private; |
10177 | struct drm_i915_gem_object *obj; | |
10178 | struct drm_framebuffer *fb; | |
10179 | ||
4c0e5528 | 10180 | if (!dev_priv->fbdev) |
d2dff872 CW |
10181 | return NULL; |
10182 | ||
4c0e5528 | 10183 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10184 | return NULL; |
10185 | ||
4c0e5528 DV |
10186 | obj = dev_priv->fbdev->fb->obj; |
10187 | BUG_ON(!obj); | |
10188 | ||
8bcd4553 | 10189 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10190 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10191 | fb->bits_per_pixel)) | |
d2dff872 CW |
10192 | return NULL; |
10193 | ||
01f2c773 | 10194 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10195 | return NULL; |
10196 | ||
10197 | return fb; | |
4520f53a DV |
10198 | #else |
10199 | return NULL; | |
10200 | #endif | |
d2dff872 CW |
10201 | } |
10202 | ||
d3a40d1b ACO |
10203 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10204 | struct drm_crtc *crtc, | |
10205 | struct drm_display_mode *mode, | |
10206 | struct drm_framebuffer *fb, | |
10207 | int x, int y) | |
10208 | { | |
10209 | struct drm_plane_state *plane_state; | |
10210 | int hdisplay, vdisplay; | |
10211 | int ret; | |
10212 | ||
10213 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10214 | if (IS_ERR(plane_state)) | |
10215 | return PTR_ERR(plane_state); | |
10216 | ||
10217 | if (mode) | |
10218 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10219 | else | |
10220 | hdisplay = vdisplay = 0; | |
10221 | ||
10222 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10223 | if (ret) | |
10224 | return ret; | |
10225 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10226 | plane_state->crtc_x = 0; | |
10227 | plane_state->crtc_y = 0; | |
10228 | plane_state->crtc_w = hdisplay; | |
10229 | plane_state->crtc_h = vdisplay; | |
10230 | plane_state->src_x = x << 16; | |
10231 | plane_state->src_y = y << 16; | |
10232 | plane_state->src_w = hdisplay << 16; | |
10233 | plane_state->src_h = vdisplay << 16; | |
10234 | ||
10235 | return 0; | |
10236 | } | |
10237 | ||
d2434ab7 | 10238 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10239 | struct drm_display_mode *mode, |
51fd371b RC |
10240 | struct intel_load_detect_pipe *old, |
10241 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10242 | { |
10243 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10244 | struct intel_encoder *intel_encoder = |
10245 | intel_attached_encoder(connector); | |
79e53945 | 10246 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10247 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10248 | struct drm_crtc *crtc = NULL; |
10249 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10250 | struct drm_framebuffer *fb; |
51fd371b | 10251 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10252 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10253 | struct drm_connector_state *connector_state; |
4be07317 | 10254 | struct intel_crtc_state *crtc_state; |
51fd371b | 10255 | int ret, i = -1; |
79e53945 | 10256 | |
d2dff872 | 10257 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10258 | connector->base.id, connector->name, |
8e329a03 | 10259 | encoder->base.id, encoder->name); |
d2dff872 | 10260 | |
51fd371b RC |
10261 | retry: |
10262 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10263 | if (ret) | |
ad3c558f | 10264 | goto fail; |
6e9f798d | 10265 | |
79e53945 JB |
10266 | /* |
10267 | * Algorithm gets a little messy: | |
7a5e4805 | 10268 | * |
79e53945 JB |
10269 | * - if the connector already has an assigned crtc, use it (but make |
10270 | * sure it's on first) | |
7a5e4805 | 10271 | * |
79e53945 JB |
10272 | * - try to find the first unused crtc that can drive this connector, |
10273 | * and use that if we find one | |
79e53945 JB |
10274 | */ |
10275 | ||
10276 | /* See if we already have a CRTC for this connector */ | |
10277 | if (encoder->crtc) { | |
10278 | crtc = encoder->crtc; | |
8261b191 | 10279 | |
51fd371b | 10280 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10281 | if (ret) |
ad3c558f | 10282 | goto fail; |
4d02e2de | 10283 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10284 | if (ret) |
ad3c558f | 10285 | goto fail; |
7b24056b | 10286 | |
24218aac | 10287 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10288 | old->load_detect_temp = false; |
10289 | ||
10290 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10291 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10292 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10293 | |
7173188d | 10294 | return true; |
79e53945 JB |
10295 | } |
10296 | ||
10297 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10298 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10299 | i++; |
10300 | if (!(encoder->possible_crtcs & (1 << i))) | |
10301 | continue; | |
83d65738 | 10302 | if (possible_crtc->state->enable) |
a459249c | 10303 | continue; |
a459249c VS |
10304 | |
10305 | crtc = possible_crtc; | |
10306 | break; | |
79e53945 JB |
10307 | } |
10308 | ||
10309 | /* | |
10310 | * If we didn't find an unused CRTC, don't use any. | |
10311 | */ | |
10312 | if (!crtc) { | |
7173188d | 10313 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10314 | goto fail; |
79e53945 JB |
10315 | } |
10316 | ||
51fd371b RC |
10317 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10318 | if (ret) | |
ad3c558f | 10319 | goto fail; |
4d02e2de DV |
10320 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10321 | if (ret) | |
ad3c558f | 10322 | goto fail; |
79e53945 JB |
10323 | |
10324 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10325 | old->dpms_mode = connector->dpms; |
8261b191 | 10326 | old->load_detect_temp = true; |
d2dff872 | 10327 | old->release_fb = NULL; |
79e53945 | 10328 | |
83a57153 ACO |
10329 | state = drm_atomic_state_alloc(dev); |
10330 | if (!state) | |
10331 | return false; | |
10332 | ||
10333 | state->acquire_ctx = ctx; | |
10334 | ||
944b0c76 ACO |
10335 | connector_state = drm_atomic_get_connector_state(state, connector); |
10336 | if (IS_ERR(connector_state)) { | |
10337 | ret = PTR_ERR(connector_state); | |
10338 | goto fail; | |
10339 | } | |
10340 | ||
10341 | connector_state->crtc = crtc; | |
10342 | connector_state->best_encoder = &intel_encoder->base; | |
10343 | ||
4be07317 ACO |
10344 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10345 | if (IS_ERR(crtc_state)) { | |
10346 | ret = PTR_ERR(crtc_state); | |
10347 | goto fail; | |
10348 | } | |
10349 | ||
49d6fa21 | 10350 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10351 | |
6492711d CW |
10352 | if (!mode) |
10353 | mode = &load_detect_mode; | |
79e53945 | 10354 | |
d2dff872 CW |
10355 | /* We need a framebuffer large enough to accommodate all accesses |
10356 | * that the plane may generate whilst we perform load detection. | |
10357 | * We can not rely on the fbcon either being present (we get called | |
10358 | * during its initialisation to detect all boot displays, or it may | |
10359 | * not even exist) or that it is large enough to satisfy the | |
10360 | * requested mode. | |
10361 | */ | |
94352cf9 DV |
10362 | fb = mode_fits_in_fbdev(dev, mode); |
10363 | if (fb == NULL) { | |
d2dff872 | 10364 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10365 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10366 | old->release_fb = fb; | |
d2dff872 CW |
10367 | } else |
10368 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10369 | if (IS_ERR(fb)) { |
d2dff872 | 10370 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10371 | goto fail; |
79e53945 | 10372 | } |
79e53945 | 10373 | |
d3a40d1b ACO |
10374 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10375 | if (ret) | |
10376 | goto fail; | |
10377 | ||
8c7b5ccb ACO |
10378 | drm_mode_copy(&crtc_state->base.mode, mode); |
10379 | ||
74c090b1 | 10380 | if (drm_atomic_commit(state)) { |
6492711d | 10381 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10382 | if (old->release_fb) |
10383 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10384 | goto fail; |
79e53945 | 10385 | } |
9128b040 | 10386 | crtc->primary->crtc = crtc; |
7173188d | 10387 | |
79e53945 | 10388 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10389 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10390 | return true; |
412b61d8 | 10391 | |
ad3c558f | 10392 | fail: |
e5d958ef ACO |
10393 | drm_atomic_state_free(state); |
10394 | state = NULL; | |
83a57153 | 10395 | |
51fd371b RC |
10396 | if (ret == -EDEADLK) { |
10397 | drm_modeset_backoff(ctx); | |
10398 | goto retry; | |
10399 | } | |
10400 | ||
412b61d8 | 10401 | return false; |
79e53945 JB |
10402 | } |
10403 | ||
d2434ab7 | 10404 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10405 | struct intel_load_detect_pipe *old, |
10406 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10407 | { |
83a57153 | 10408 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10409 | struct intel_encoder *intel_encoder = |
10410 | intel_attached_encoder(connector); | |
4ef69c7a | 10411 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10412 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10413 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10414 | struct drm_atomic_state *state; |
944b0c76 | 10415 | struct drm_connector_state *connector_state; |
4be07317 | 10416 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10417 | int ret; |
79e53945 | 10418 | |
d2dff872 | 10419 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10420 | connector->base.id, connector->name, |
8e329a03 | 10421 | encoder->base.id, encoder->name); |
d2dff872 | 10422 | |
8261b191 | 10423 | if (old->load_detect_temp) { |
83a57153 | 10424 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10425 | if (!state) |
10426 | goto fail; | |
83a57153 ACO |
10427 | |
10428 | state->acquire_ctx = ctx; | |
10429 | ||
944b0c76 ACO |
10430 | connector_state = drm_atomic_get_connector_state(state, connector); |
10431 | if (IS_ERR(connector_state)) | |
10432 | goto fail; | |
10433 | ||
4be07317 ACO |
10434 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10435 | if (IS_ERR(crtc_state)) | |
10436 | goto fail; | |
10437 | ||
944b0c76 ACO |
10438 | connector_state->best_encoder = NULL; |
10439 | connector_state->crtc = NULL; | |
10440 | ||
49d6fa21 | 10441 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10442 | |
d3a40d1b ACO |
10443 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10444 | 0, 0); | |
10445 | if (ret) | |
10446 | goto fail; | |
10447 | ||
74c090b1 | 10448 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10449 | if (ret) |
10450 | goto fail; | |
d2dff872 | 10451 | |
36206361 DV |
10452 | if (old->release_fb) { |
10453 | drm_framebuffer_unregister_private(old->release_fb); | |
10454 | drm_framebuffer_unreference(old->release_fb); | |
10455 | } | |
d2dff872 | 10456 | |
0622a53c | 10457 | return; |
79e53945 JB |
10458 | } |
10459 | ||
c751ce4f | 10460 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10461 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10462 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10463 | |
10464 | return; | |
10465 | fail: | |
10466 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10467 | drm_atomic_state_free(state); | |
79e53945 JB |
10468 | } |
10469 | ||
da4a1efa | 10470 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10471 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10472 | { |
10473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10474 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10475 | ||
10476 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10477 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10478 | else if (HAS_PCH_SPLIT(dev)) |
10479 | return 120000; | |
10480 | else if (!IS_GEN2(dev)) | |
10481 | return 96000; | |
10482 | else | |
10483 | return 48000; | |
10484 | } | |
10485 | ||
79e53945 | 10486 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10487 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10488 | struct intel_crtc_state *pipe_config) |
79e53945 | 10489 | { |
f1f644dc | 10490 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10491 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10492 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10493 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10494 | u32 fp; |
10495 | intel_clock_t clock; | |
dccbea3b | 10496 | int port_clock; |
da4a1efa | 10497 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10498 | |
10499 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10500 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10501 | else |
293623f7 | 10502 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10503 | |
10504 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10505 | if (IS_PINEVIEW(dev)) { |
10506 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10507 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10508 | } else { |
10509 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10510 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10511 | } | |
10512 | ||
a6c45cf0 | 10513 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10514 | if (IS_PINEVIEW(dev)) |
10515 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10516 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10517 | else |
10518 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10519 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10520 | ||
10521 | switch (dpll & DPLL_MODE_MASK) { | |
10522 | case DPLLB_MODE_DAC_SERIAL: | |
10523 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10524 | 5 : 10; | |
10525 | break; | |
10526 | case DPLLB_MODE_LVDS: | |
10527 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10528 | 7 : 14; | |
10529 | break; | |
10530 | default: | |
28c97730 | 10531 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10532 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10533 | return; |
79e53945 JB |
10534 | } |
10535 | ||
ac58c3f0 | 10536 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10537 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10538 | else |
dccbea3b | 10539 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10540 | } else { |
0fb58223 | 10541 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10542 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10543 | |
10544 | if (is_lvds) { | |
10545 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10546 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10547 | |
10548 | if (lvds & LVDS_CLKB_POWER_UP) | |
10549 | clock.p2 = 7; | |
10550 | else | |
10551 | clock.p2 = 14; | |
79e53945 JB |
10552 | } else { |
10553 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10554 | clock.p1 = 2; | |
10555 | else { | |
10556 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10557 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10558 | } | |
10559 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10560 | clock.p2 = 4; | |
10561 | else | |
10562 | clock.p2 = 2; | |
79e53945 | 10563 | } |
da4a1efa | 10564 | |
dccbea3b | 10565 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10566 | } |
10567 | ||
18442d08 VS |
10568 | /* |
10569 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10570 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10571 | * encoder's get_config() function. |
10572 | */ | |
dccbea3b | 10573 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10574 | } |
10575 | ||
6878da05 VS |
10576 | int intel_dotclock_calculate(int link_freq, |
10577 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10578 | { |
f1f644dc JB |
10579 | /* |
10580 | * The calculation for the data clock is: | |
1041a02f | 10581 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10582 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10583 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10584 | * |
10585 | * and the link clock is simpler: | |
1041a02f | 10586 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10587 | */ |
10588 | ||
6878da05 VS |
10589 | if (!m_n->link_n) |
10590 | return 0; | |
f1f644dc | 10591 | |
6878da05 VS |
10592 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10593 | } | |
f1f644dc | 10594 | |
18442d08 | 10595 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10596 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10597 | { |
10598 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10599 | |
18442d08 VS |
10600 | /* read out port_clock from the DPLL */ |
10601 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10602 | |
f1f644dc | 10603 | /* |
18442d08 | 10604 | * This value does not include pixel_multiplier. |
241bfc38 | 10605 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10606 | * agree once we know their relationship in the encoder's |
10607 | * get_config() function. | |
79e53945 | 10608 | */ |
2d112de7 | 10609 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10610 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10611 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10612 | } |
10613 | ||
10614 | /** Returns the currently programmed mode of the given pipe. */ | |
10615 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10616 | struct drm_crtc *crtc) | |
10617 | { | |
548f245b | 10618 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10619 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10620 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10621 | struct drm_display_mode *mode; |
5cec258b | 10622 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10623 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10624 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10625 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10626 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10627 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10628 | |
10629 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10630 | if (!mode) | |
10631 | return NULL; | |
10632 | ||
f1f644dc JB |
10633 | /* |
10634 | * Construct a pipe_config sufficient for getting the clock info | |
10635 | * back out of crtc_clock_get. | |
10636 | * | |
10637 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10638 | * to use a real value here instead. | |
10639 | */ | |
293623f7 | 10640 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10641 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10642 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10643 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10644 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10645 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10646 | ||
773ae034 | 10647 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10648 | mode->hdisplay = (htot & 0xffff) + 1; |
10649 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10650 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10651 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10652 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10653 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10654 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10655 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10656 | ||
10657 | drm_mode_set_name(mode); | |
79e53945 JB |
10658 | |
10659 | return mode; | |
10660 | } | |
10661 | ||
f047e395 CW |
10662 | void intel_mark_busy(struct drm_device *dev) |
10663 | { | |
c67a470b PZ |
10664 | struct drm_i915_private *dev_priv = dev->dev_private; |
10665 | ||
f62a0076 CW |
10666 | if (dev_priv->mm.busy) |
10667 | return; | |
10668 | ||
43694d69 | 10669 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10670 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10671 | if (INTEL_INFO(dev)->gen >= 6) |
10672 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10673 | dev_priv->mm.busy = true; |
f047e395 CW |
10674 | } |
10675 | ||
10676 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10677 | { |
c67a470b | 10678 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10679 | |
f62a0076 CW |
10680 | if (!dev_priv->mm.busy) |
10681 | return; | |
10682 | ||
10683 | dev_priv->mm.busy = false; | |
10684 | ||
3d13ef2e | 10685 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10686 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10687 | |
43694d69 | 10688 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10689 | } |
10690 | ||
79e53945 JB |
10691 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10692 | { | |
10693 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10694 | struct drm_device *dev = crtc->dev; |
10695 | struct intel_unpin_work *work; | |
67e77c5a | 10696 | |
5e2d7afc | 10697 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10698 | work = intel_crtc->unpin_work; |
10699 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10700 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10701 | |
10702 | if (work) { | |
10703 | cancel_work_sync(&work->work); | |
10704 | kfree(work); | |
10705 | } | |
79e53945 JB |
10706 | |
10707 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10708 | |
79e53945 JB |
10709 | kfree(intel_crtc); |
10710 | } | |
10711 | ||
6b95a207 KH |
10712 | static void intel_unpin_work_fn(struct work_struct *__work) |
10713 | { | |
10714 | struct intel_unpin_work *work = | |
10715 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10716 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10717 | struct drm_device *dev = crtc->base.dev; | |
10718 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10719 | |
b4a98e57 | 10720 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10721 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10722 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10723 | |
f06cc1b9 | 10724 | if (work->flip_queued_req) |
146d84f0 | 10725 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10726 | mutex_unlock(&dev->struct_mutex); |
10727 | ||
a9ff8714 | 10728 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
89ed88ba | 10729 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10730 | |
a9ff8714 VS |
10731 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10732 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10733 | |
6b95a207 KH |
10734 | kfree(work); |
10735 | } | |
10736 | ||
1afe3e9d | 10737 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10738 | struct drm_crtc *crtc) |
6b95a207 | 10739 | { |
6b95a207 KH |
10740 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10741 | struct intel_unpin_work *work; | |
6b95a207 KH |
10742 | unsigned long flags; |
10743 | ||
10744 | /* Ignore early vblank irqs */ | |
10745 | if (intel_crtc == NULL) | |
10746 | return; | |
10747 | ||
f326038a DV |
10748 | /* |
10749 | * This is called both by irq handlers and the reset code (to complete | |
10750 | * lost pageflips) so needs the full irqsave spinlocks. | |
10751 | */ | |
6b95a207 KH |
10752 | spin_lock_irqsave(&dev->event_lock, flags); |
10753 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10754 | |
10755 | /* Ensure we don't miss a work->pending update ... */ | |
10756 | smp_rmb(); | |
10757 | ||
10758 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10759 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10760 | return; | |
10761 | } | |
10762 | ||
d6bbafa1 | 10763 | page_flip_completed(intel_crtc); |
0af7e4df | 10764 | |
6b95a207 | 10765 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10766 | } |
10767 | ||
1afe3e9d JB |
10768 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10769 | { | |
fbee40df | 10770 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10771 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10772 | ||
49b14a5c | 10773 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10774 | } |
10775 | ||
10776 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10777 | { | |
fbee40df | 10778 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10779 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10780 | ||
49b14a5c | 10781 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10782 | } |
10783 | ||
75f7f3ec VS |
10784 | /* Is 'a' after or equal to 'b'? */ |
10785 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10786 | { | |
10787 | return !((a - b) & 0x80000000); | |
10788 | } | |
10789 | ||
10790 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10791 | { | |
10792 | struct drm_device *dev = crtc->base.dev; | |
10793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10794 | ||
bdfa7542 VS |
10795 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10796 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10797 | return true; | |
10798 | ||
75f7f3ec VS |
10799 | /* |
10800 | * The relevant registers doen't exist on pre-ctg. | |
10801 | * As the flip done interrupt doesn't trigger for mmio | |
10802 | * flips on gmch platforms, a flip count check isn't | |
10803 | * really needed there. But since ctg has the registers, | |
10804 | * include it in the check anyway. | |
10805 | */ | |
10806 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10807 | return true; | |
10808 | ||
10809 | /* | |
10810 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10811 | * used the same base address. In that case the mmio flip might | |
10812 | * have completed, but the CS hasn't even executed the flip yet. | |
10813 | * | |
10814 | * A flip count check isn't enough as the CS might have updated | |
10815 | * the base address just after start of vblank, but before we | |
10816 | * managed to process the interrupt. This means we'd complete the | |
10817 | * CS flip too soon. | |
10818 | * | |
10819 | * Combining both checks should get us a good enough result. It may | |
10820 | * still happen that the CS flip has been executed, but has not | |
10821 | * yet actually completed. But in case the base address is the same | |
10822 | * anyway, we don't really care. | |
10823 | */ | |
10824 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10825 | crtc->unpin_work->gtt_offset && | |
10826 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10827 | crtc->unpin_work->flip_count); | |
10828 | } | |
10829 | ||
6b95a207 KH |
10830 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10831 | { | |
fbee40df | 10832 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10833 | struct intel_crtc *intel_crtc = |
10834 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10835 | unsigned long flags; | |
10836 | ||
f326038a DV |
10837 | |
10838 | /* | |
10839 | * This is called both by irq handlers and the reset code (to complete | |
10840 | * lost pageflips) so needs the full irqsave spinlocks. | |
10841 | * | |
10842 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10843 | * generate a page-flip completion irq, i.e. every modeset |
10844 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10845 | */ | |
6b95a207 | 10846 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10847 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10848 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10849 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10850 | } | |
10851 | ||
eba905b2 | 10852 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10853 | { |
10854 | /* Ensure that the work item is consistent when activating it ... */ | |
10855 | smp_wmb(); | |
10856 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10857 | /* and that it is marked active as soon as the irq could fire. */ | |
10858 | smp_wmb(); | |
10859 | } | |
10860 | ||
8c9f3aaf JB |
10861 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10862 | struct drm_crtc *crtc, | |
10863 | struct drm_framebuffer *fb, | |
ed8d1975 | 10864 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10865 | struct drm_i915_gem_request *req, |
ed8d1975 | 10866 | uint32_t flags) |
8c9f3aaf | 10867 | { |
6258fbe2 | 10868 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 10869 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10870 | u32 flip_mask; |
10871 | int ret; | |
10872 | ||
5fb9de1a | 10873 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10874 | if (ret) |
4fa62c89 | 10875 | return ret; |
8c9f3aaf JB |
10876 | |
10877 | /* Can't queue multiple flips, so wait for the previous | |
10878 | * one to finish before executing the next. | |
10879 | */ | |
10880 | if (intel_crtc->plane) | |
10881 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10882 | else | |
10883 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10884 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10885 | intel_ring_emit(ring, MI_NOOP); | |
10886 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10887 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10888 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10889 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10890 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
10891 | |
10892 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 10893 | return 0; |
8c9f3aaf JB |
10894 | } |
10895 | ||
10896 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10897 | struct drm_crtc *crtc, | |
10898 | struct drm_framebuffer *fb, | |
ed8d1975 | 10899 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10900 | struct drm_i915_gem_request *req, |
ed8d1975 | 10901 | uint32_t flags) |
8c9f3aaf | 10902 | { |
6258fbe2 | 10903 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 10904 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10905 | u32 flip_mask; |
10906 | int ret; | |
10907 | ||
5fb9de1a | 10908 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10909 | if (ret) |
4fa62c89 | 10910 | return ret; |
8c9f3aaf JB |
10911 | |
10912 | if (intel_crtc->plane) | |
10913 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10914 | else | |
10915 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10916 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10917 | intel_ring_emit(ring, MI_NOOP); | |
10918 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10919 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10920 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10921 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10922 | intel_ring_emit(ring, MI_NOOP); |
10923 | ||
e7d841ca | 10924 | intel_mark_page_flip_active(intel_crtc); |
83d4092b | 10925 | return 0; |
8c9f3aaf JB |
10926 | } |
10927 | ||
10928 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10929 | struct drm_crtc *crtc, | |
10930 | struct drm_framebuffer *fb, | |
ed8d1975 | 10931 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10932 | struct drm_i915_gem_request *req, |
ed8d1975 | 10933 | uint32_t flags) |
8c9f3aaf | 10934 | { |
6258fbe2 | 10935 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
10936 | struct drm_i915_private *dev_priv = dev->dev_private; |
10937 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10938 | uint32_t pf, pipesrc; | |
10939 | int ret; | |
10940 | ||
5fb9de1a | 10941 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 10942 | if (ret) |
4fa62c89 | 10943 | return ret; |
8c9f3aaf JB |
10944 | |
10945 | /* i965+ uses the linear or tiled offsets from the | |
10946 | * Display Registers (which do not change across a page-flip) | |
10947 | * so we need only reprogram the base address. | |
10948 | */ | |
6d90c952 DV |
10949 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10950 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10951 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10952 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 10953 | obj->tiling_mode); |
8c9f3aaf JB |
10954 | |
10955 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10956 | * untested on non-native modes, so ignore it for now. | |
10957 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10958 | */ | |
10959 | pf = 0; | |
10960 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 10961 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10962 | |
10963 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 10964 | return 0; |
8c9f3aaf JB |
10965 | } |
10966 | ||
10967 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10968 | struct drm_crtc *crtc, | |
10969 | struct drm_framebuffer *fb, | |
ed8d1975 | 10970 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10971 | struct drm_i915_gem_request *req, |
ed8d1975 | 10972 | uint32_t flags) |
8c9f3aaf | 10973 | { |
6258fbe2 | 10974 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
10975 | struct drm_i915_private *dev_priv = dev->dev_private; |
10976 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10977 | uint32_t pf, pipesrc; | |
10978 | int ret; | |
10979 | ||
5fb9de1a | 10980 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 10981 | if (ret) |
4fa62c89 | 10982 | return ret; |
8c9f3aaf | 10983 | |
6d90c952 DV |
10984 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10985 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10986 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 10987 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 10988 | |
dc257cf1 DV |
10989 | /* Contrary to the suggestions in the documentation, |
10990 | * "Enable Panel Fitter" does not seem to be required when page | |
10991 | * flipping with a non-native mode, and worse causes a normal | |
10992 | * modeset to fail. | |
10993 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10994 | */ | |
10995 | pf = 0; | |
8c9f3aaf | 10996 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 10997 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10998 | |
10999 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 11000 | return 0; |
8c9f3aaf JB |
11001 | } |
11002 | ||
7c9017e5 JB |
11003 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11004 | struct drm_crtc *crtc, | |
11005 | struct drm_framebuffer *fb, | |
ed8d1975 | 11006 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11007 | struct drm_i915_gem_request *req, |
ed8d1975 | 11008 | uint32_t flags) |
7c9017e5 | 11009 | { |
6258fbe2 | 11010 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11011 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11012 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11013 | int len, ret; |
11014 | ||
eba905b2 | 11015 | switch (intel_crtc->plane) { |
cb05d8de DV |
11016 | case PLANE_A: |
11017 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11018 | break; | |
11019 | case PLANE_B: | |
11020 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11021 | break; | |
11022 | case PLANE_C: | |
11023 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11024 | break; | |
11025 | default: | |
11026 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11027 | return -ENODEV; |
cb05d8de DV |
11028 | } |
11029 | ||
ffe74d75 | 11030 | len = 4; |
f476828a | 11031 | if (ring->id == RCS) { |
ffe74d75 | 11032 | len += 6; |
f476828a DL |
11033 | /* |
11034 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11035 | * 48bits addresses, and we need a NOOP for the batch size to | |
11036 | * stay even. | |
11037 | */ | |
11038 | if (IS_GEN8(dev)) | |
11039 | len += 2; | |
11040 | } | |
ffe74d75 | 11041 | |
f66fab8e VS |
11042 | /* |
11043 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11044 | * "The full packet must be contained within the same cache line." | |
11045 | * | |
11046 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11047 | * cacheline, if we ever start emitting more commands before | |
11048 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11049 | * then do the cacheline alignment, and finally emit the | |
11050 | * MI_DISPLAY_FLIP. | |
11051 | */ | |
bba09b12 | 11052 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11053 | if (ret) |
4fa62c89 | 11054 | return ret; |
f66fab8e | 11055 | |
5fb9de1a | 11056 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11057 | if (ret) |
4fa62c89 | 11058 | return ret; |
7c9017e5 | 11059 | |
ffe74d75 CW |
11060 | /* Unmask the flip-done completion message. Note that the bspec says that |
11061 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11062 | * more than one flip event at any time (or ensure that one flip message | |
11063 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11064 | * Experimentation says that BCS works despite DERRMR masking all | |
11065 | * flip-done completion events and that unmasking all planes at once | |
11066 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11067 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11068 | */ | |
11069 | if (ring->id == RCS) { | |
11070 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
11071 | intel_ring_emit(ring, DERRMR); | |
11072 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11073 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11074 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11075 | if (IS_GEN8(dev)) |
f1afe24f | 11076 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11077 | MI_SRM_LRM_GLOBAL_GTT); |
11078 | else | |
f1afe24f | 11079 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11080 | MI_SRM_LRM_GLOBAL_GTT); |
ffe74d75 CW |
11081 | intel_ring_emit(ring, DERRMR); |
11082 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
11083 | if (IS_GEN8(dev)) { |
11084 | intel_ring_emit(ring, 0); | |
11085 | intel_ring_emit(ring, MI_NOOP); | |
11086 | } | |
ffe74d75 CW |
11087 | } |
11088 | ||
cb05d8de | 11089 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11090 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11091 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11092 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
11093 | |
11094 | intel_mark_page_flip_active(intel_crtc); | |
83d4092b | 11095 | return 0; |
7c9017e5 JB |
11096 | } |
11097 | ||
84c33a64 SG |
11098 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11099 | struct drm_i915_gem_object *obj) | |
11100 | { | |
11101 | /* | |
11102 | * This is not being used for older platforms, because | |
11103 | * non-availability of flip done interrupt forces us to use | |
11104 | * CS flips. Older platforms derive flip done using some clever | |
11105 | * tricks involving the flip_pending status bits and vblank irqs. | |
11106 | * So using MMIO flips there would disrupt this mechanism. | |
11107 | */ | |
11108 | ||
8e09bf83 CW |
11109 | if (ring == NULL) |
11110 | return true; | |
11111 | ||
84c33a64 SG |
11112 | if (INTEL_INFO(ring->dev)->gen < 5) |
11113 | return false; | |
11114 | ||
11115 | if (i915.use_mmio_flip < 0) | |
11116 | return false; | |
11117 | else if (i915.use_mmio_flip > 0) | |
11118 | return true; | |
14bf993e OM |
11119 | else if (i915.enable_execlists) |
11120 | return true; | |
84c33a64 | 11121 | else |
b4716185 | 11122 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11123 | } |
11124 | ||
ff944564 DL |
11125 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
11126 | { | |
11127 | struct drm_device *dev = intel_crtc->base.dev; | |
11128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11129 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 DL |
11130 | const enum pipe pipe = intel_crtc->pipe; |
11131 | u32 ctl, stride; | |
11132 | ||
11133 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11134 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11135 | switch (fb->modifier[0]) { |
11136 | case DRM_FORMAT_MOD_NONE: | |
11137 | break; | |
11138 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11139 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11140 | break; |
11141 | case I915_FORMAT_MOD_Y_TILED: | |
11142 | ctl |= PLANE_CTL_TILED_Y; | |
11143 | break; | |
11144 | case I915_FORMAT_MOD_Yf_TILED: | |
11145 | ctl |= PLANE_CTL_TILED_YF; | |
11146 | break; | |
11147 | default: | |
11148 | MISSING_CASE(fb->modifier[0]); | |
11149 | } | |
ff944564 DL |
11150 | |
11151 | /* | |
11152 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11153 | * linear buffers or in number of tiles for tiled buffers. | |
11154 | */ | |
2ebef630 TU |
11155 | stride = fb->pitches[0] / |
11156 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
11157 | fb->pixel_format); | |
ff944564 DL |
11158 | |
11159 | /* | |
11160 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11161 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11162 | */ | |
11163 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11164 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11165 | ||
11166 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
11167 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
11168 | } | |
11169 | ||
11170 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
11171 | { |
11172 | struct drm_device *dev = intel_crtc->base.dev; | |
11173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11174 | struct intel_framebuffer *intel_fb = | |
11175 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11176 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
11177 | u32 dspcntr; | |
11178 | u32 reg; | |
11179 | ||
84c33a64 SG |
11180 | reg = DSPCNTR(intel_crtc->plane); |
11181 | dspcntr = I915_READ(reg); | |
11182 | ||
c5d97472 DL |
11183 | if (obj->tiling_mode != I915_TILING_NONE) |
11184 | dspcntr |= DISPPLANE_TILED; | |
11185 | else | |
11186 | dspcntr &= ~DISPPLANE_TILED; | |
11187 | ||
84c33a64 SG |
11188 | I915_WRITE(reg, dspcntr); |
11189 | ||
11190 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
11191 | intel_crtc->unpin_work->gtt_offset); | |
11192 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 11193 | |
ff944564 DL |
11194 | } |
11195 | ||
11196 | /* | |
11197 | * XXX: This is the temporary way to update the plane registers until we get | |
11198 | * around to using the usual plane update functions for MMIO flips | |
11199 | */ | |
11200 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
11201 | { | |
11202 | struct drm_device *dev = intel_crtc->base.dev; | |
ff944564 DL |
11203 | |
11204 | intel_mark_page_flip_active(intel_crtc); | |
11205 | ||
34e0adbb | 11206 | intel_pipe_update_start(intel_crtc); |
ff944564 DL |
11207 | |
11208 | if (INTEL_INFO(dev)->gen >= 9) | |
11209 | skl_do_mmio_flip(intel_crtc); | |
11210 | else | |
11211 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
11212 | ilk_do_mmio_flip(intel_crtc); | |
11213 | ||
34e0adbb | 11214 | intel_pipe_update_end(intel_crtc); |
84c33a64 SG |
11215 | } |
11216 | ||
9362c7c5 | 11217 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11218 | { |
b2cfe0ab CW |
11219 | struct intel_mmio_flip *mmio_flip = |
11220 | container_of(work, struct intel_mmio_flip, work); | |
84c33a64 | 11221 | |
eed29a5b DV |
11222 | if (mmio_flip->req) |
11223 | WARN_ON(__i915_wait_request(mmio_flip->req, | |
b2cfe0ab | 11224 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11225 | false, NULL, |
11226 | &mmio_flip->i915->rps.mmioflips)); | |
84c33a64 | 11227 | |
b2cfe0ab CW |
11228 | intel_do_mmio_flip(mmio_flip->crtc); |
11229 | ||
eed29a5b | 11230 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
b2cfe0ab | 11231 | kfree(mmio_flip); |
84c33a64 SG |
11232 | } |
11233 | ||
11234 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11235 | struct drm_crtc *crtc, | |
11236 | struct drm_framebuffer *fb, | |
11237 | struct drm_i915_gem_object *obj, | |
11238 | struct intel_engine_cs *ring, | |
11239 | uint32_t flags) | |
11240 | { | |
b2cfe0ab CW |
11241 | struct intel_mmio_flip *mmio_flip; |
11242 | ||
11243 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11244 | if (mmio_flip == NULL) | |
11245 | return -ENOMEM; | |
84c33a64 | 11246 | |
bcafc4e3 | 11247 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11248 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11249 | mmio_flip->crtc = to_intel_crtc(crtc); |
536f5b5e | 11250 | |
b2cfe0ab CW |
11251 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11252 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11253 | |
84c33a64 SG |
11254 | return 0; |
11255 | } | |
11256 | ||
8c9f3aaf JB |
11257 | static int intel_default_queue_flip(struct drm_device *dev, |
11258 | struct drm_crtc *crtc, | |
11259 | struct drm_framebuffer *fb, | |
ed8d1975 | 11260 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11261 | struct drm_i915_gem_request *req, |
ed8d1975 | 11262 | uint32_t flags) |
8c9f3aaf JB |
11263 | { |
11264 | return -ENODEV; | |
11265 | } | |
11266 | ||
d6bbafa1 CW |
11267 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11268 | struct drm_crtc *crtc) | |
11269 | { | |
11270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11272 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11273 | u32 addr; | |
11274 | ||
11275 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11276 | return true; | |
11277 | ||
908565c2 CW |
11278 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11279 | return false; | |
11280 | ||
d6bbafa1 CW |
11281 | if (!work->enable_stall_check) |
11282 | return false; | |
11283 | ||
11284 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11285 | if (work->flip_queued_req && |
11286 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11287 | return false; |
11288 | ||
1e3feefd | 11289 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11290 | } |
11291 | ||
1e3feefd | 11292 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11293 | return false; |
11294 | ||
11295 | /* Potential stall - if we see that the flip has happened, | |
11296 | * assume a missed interrupt. */ | |
11297 | if (INTEL_INFO(dev)->gen >= 4) | |
11298 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11299 | else | |
11300 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11301 | ||
11302 | /* There is a potential issue here with a false positive after a flip | |
11303 | * to the same address. We could address this by checking for a | |
11304 | * non-incrementing frame counter. | |
11305 | */ | |
11306 | return addr == work->gtt_offset; | |
11307 | } | |
11308 | ||
11309 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11310 | { | |
11311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11312 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11314 | struct intel_unpin_work *work; |
f326038a | 11315 | |
6c51d46f | 11316 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11317 | |
11318 | if (crtc == NULL) | |
11319 | return; | |
11320 | ||
f326038a | 11321 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11322 | work = intel_crtc->unpin_work; |
11323 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11324 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11325 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11326 | page_flip_completed(intel_crtc); |
6ad790c0 | 11327 | work = NULL; |
d6bbafa1 | 11328 | } |
6ad790c0 CW |
11329 | if (work != NULL && |
11330 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11331 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11332 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11333 | } |
11334 | ||
6b95a207 KH |
11335 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11336 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11337 | struct drm_pending_vblank_event *event, |
11338 | uint32_t page_flip_flags) | |
6b95a207 KH |
11339 | { |
11340 | struct drm_device *dev = crtc->dev; | |
11341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11342 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11343 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11344 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11345 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11346 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11347 | struct intel_unpin_work *work; |
a4872ba6 | 11348 | struct intel_engine_cs *ring; |
cf5d8a46 | 11349 | bool mmio_flip; |
91af127f | 11350 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11351 | int ret; |
6b95a207 | 11352 | |
2ff8fde1 MR |
11353 | /* |
11354 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11355 | * check to be safe. In the future we may enable pageflipping from | |
11356 | * a disabled primary plane. | |
11357 | */ | |
11358 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11359 | return -EBUSY; | |
11360 | ||
e6a595d2 | 11361 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11362 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11363 | return -EINVAL; |
11364 | ||
11365 | /* | |
11366 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11367 | * Note that pitch changes could also affect these register. | |
11368 | */ | |
11369 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11370 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11371 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11372 | return -EINVAL; |
11373 | ||
f900db47 CW |
11374 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11375 | goto out_hang; | |
11376 | ||
b14c5679 | 11377 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11378 | if (work == NULL) |
11379 | return -ENOMEM; | |
11380 | ||
6b95a207 | 11381 | work->event = event; |
b4a98e57 | 11382 | work->crtc = crtc; |
ab8d6675 | 11383 | work->old_fb = old_fb; |
6b95a207 KH |
11384 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11385 | ||
87b6b101 | 11386 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11387 | if (ret) |
11388 | goto free_work; | |
11389 | ||
6b95a207 | 11390 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11391 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11392 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11393 | /* Before declaring the flip queue wedged, check if |
11394 | * the hardware completed the operation behind our backs. | |
11395 | */ | |
11396 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11397 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11398 | page_flip_completed(intel_crtc); | |
11399 | } else { | |
11400 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11401 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11402 | |
d6bbafa1 CW |
11403 | drm_crtc_vblank_put(crtc); |
11404 | kfree(work); | |
11405 | return -EBUSY; | |
11406 | } | |
6b95a207 KH |
11407 | } |
11408 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11409 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11410 | |
b4a98e57 CW |
11411 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11412 | flush_workqueue(dev_priv->wq); | |
11413 | ||
75dfca80 | 11414 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11415 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11416 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11417 | |
f4510a27 | 11418 | crtc->primary->fb = fb; |
afd65eb4 | 11419 | update_state_fb(crtc->primary); |
1ed1f968 | 11420 | |
e1f99ce6 | 11421 | work->pending_flip_obj = obj; |
e1f99ce6 | 11422 | |
89ed88ba CW |
11423 | ret = i915_mutex_lock_interruptible(dev); |
11424 | if (ret) | |
11425 | goto cleanup; | |
11426 | ||
b4a98e57 | 11427 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11428 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11429 | |
75f7f3ec | 11430 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 11431 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 11432 | |
4fa62c89 VS |
11433 | if (IS_VALLEYVIEW(dev)) { |
11434 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 11435 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11436 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11437 | ring = NULL; | |
48bf5b2d | 11438 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11439 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11440 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11441 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11442 | if (ring == NULL || ring->id != RCS) |
11443 | ring = &dev_priv->ring[BCS]; | |
11444 | } else { | |
11445 | ring = &dev_priv->ring[RCS]; | |
11446 | } | |
11447 | ||
cf5d8a46 CW |
11448 | mmio_flip = use_mmio_flip(ring, obj); |
11449 | ||
11450 | /* When using CS flips, we want to emit semaphores between rings. | |
11451 | * However, when using mmio flips we will create a task to do the | |
11452 | * synchronisation, so all we want here is to pin the framebuffer | |
11453 | * into the display plane and skip any waits. | |
11454 | */ | |
82bc3b2d | 11455 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 | 11456 | crtc->primary->state, |
91af127f | 11457 | mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request); |
8c9f3aaf JB |
11458 | if (ret) |
11459 | goto cleanup_pending; | |
6b95a207 | 11460 | |
dedf278c TU |
11461 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11462 | obj, 0); | |
11463 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11464 | |
cf5d8a46 | 11465 | if (mmio_flip) { |
84c33a64 SG |
11466 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
11467 | page_flip_flags); | |
d6bbafa1 CW |
11468 | if (ret) |
11469 | goto cleanup_unpin; | |
11470 | ||
f06cc1b9 JH |
11471 | i915_gem_request_assign(&work->flip_queued_req, |
11472 | obj->last_write_req); | |
d6bbafa1 | 11473 | } else { |
6258fbe2 JH |
11474 | if (!request) { |
11475 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); | |
11476 | if (ret) | |
11477 | goto cleanup_unpin; | |
11478 | } | |
11479 | ||
11480 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11481 | page_flip_flags); |
11482 | if (ret) | |
11483 | goto cleanup_unpin; | |
11484 | ||
6258fbe2 | 11485 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11486 | } |
11487 | ||
91af127f | 11488 | if (request) |
75289874 | 11489 | i915_add_request_no_flush(request); |
91af127f | 11490 | |
1e3feefd | 11491 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11492 | work->enable_stall_check = true; |
4fa62c89 | 11493 | |
ab8d6675 | 11494 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11495 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11496 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11497 | |
4e1e26f1 | 11498 | intel_fbc_disable_crtc(intel_crtc); |
a9ff8714 VS |
11499 | intel_frontbuffer_flip_prepare(dev, |
11500 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11501 | |
e5510fac JB |
11502 | trace_i915_flip_request(intel_crtc->plane, obj); |
11503 | ||
6b95a207 | 11504 | return 0; |
96b099fd | 11505 | |
4fa62c89 | 11506 | cleanup_unpin: |
82bc3b2d | 11507 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11508 | cleanup_pending: |
91af127f JH |
11509 | if (request) |
11510 | i915_gem_request_cancel(request); | |
b4a98e57 | 11511 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11512 | mutex_unlock(&dev->struct_mutex); |
11513 | cleanup: | |
f4510a27 | 11514 | crtc->primary->fb = old_fb; |
afd65eb4 | 11515 | update_state_fb(crtc->primary); |
89ed88ba CW |
11516 | |
11517 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11518 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11519 | |
5e2d7afc | 11520 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11521 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11522 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11523 | |
87b6b101 | 11524 | drm_crtc_vblank_put(crtc); |
7317c75e | 11525 | free_work: |
96b099fd CW |
11526 | kfree(work); |
11527 | ||
f900db47 | 11528 | if (ret == -EIO) { |
02e0efb5 ML |
11529 | struct drm_atomic_state *state; |
11530 | struct drm_plane_state *plane_state; | |
11531 | ||
f900db47 | 11532 | out_hang: |
02e0efb5 ML |
11533 | state = drm_atomic_state_alloc(dev); |
11534 | if (!state) | |
11535 | return -ENOMEM; | |
11536 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11537 | ||
11538 | retry: | |
11539 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11540 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11541 | if (!ret) { | |
11542 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11543 | ||
11544 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11545 | if (!ret) | |
11546 | ret = drm_atomic_commit(state); | |
11547 | } | |
11548 | ||
11549 | if (ret == -EDEADLK) { | |
11550 | drm_modeset_backoff(state->acquire_ctx); | |
11551 | drm_atomic_state_clear(state); | |
11552 | goto retry; | |
11553 | } | |
11554 | ||
11555 | if (ret) | |
11556 | drm_atomic_state_free(state); | |
11557 | ||
f0d3dad3 | 11558 | if (ret == 0 && event) { |
5e2d7afc | 11559 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11560 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11561 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11562 | } |
f900db47 | 11563 | } |
96b099fd | 11564 | return ret; |
6b95a207 KH |
11565 | } |
11566 | ||
da20eabd ML |
11567 | |
11568 | /** | |
11569 | * intel_wm_need_update - Check whether watermarks need updating | |
11570 | * @plane: drm plane | |
11571 | * @state: new plane state | |
11572 | * | |
11573 | * Check current plane state versus the new one to determine whether | |
11574 | * watermarks need to be recalculated. | |
11575 | * | |
11576 | * Returns true or false. | |
11577 | */ | |
11578 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11579 | struct drm_plane_state *state) | |
11580 | { | |
7809e5ae MR |
11581 | struct intel_plane_state *new = to_intel_plane_state(state); |
11582 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11583 | ||
11584 | /* Update watermarks on tiling or size changes. */ | |
da20eabd ML |
11585 | if (!plane->state->fb || !state->fb || |
11586 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
7809e5ae MR |
11587 | plane->state->rotation != state->rotation || |
11588 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || | |
11589 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11590 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11591 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
da20eabd ML |
11592 | return true; |
11593 | ||
11594 | return false; | |
11595 | } | |
11596 | ||
7809e5ae MR |
11597 | static bool needs_scaling(struct intel_plane_state *state) |
11598 | { | |
11599 | int src_w = drm_rect_width(&state->src) >> 16; | |
11600 | int src_h = drm_rect_height(&state->src) >> 16; | |
11601 | int dst_w = drm_rect_width(&state->dst); | |
11602 | int dst_h = drm_rect_height(&state->dst); | |
11603 | ||
11604 | return (src_w != dst_w || src_h != dst_h); | |
11605 | } | |
11606 | ||
da20eabd ML |
11607 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11608 | struct drm_plane_state *plane_state) | |
11609 | { | |
11610 | struct drm_crtc *crtc = crtc_state->crtc; | |
11611 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11612 | struct drm_plane *plane = plane_state->plane; | |
11613 | struct drm_device *dev = crtc->dev; | |
11614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11615 | struct intel_plane_state *old_plane_state = | |
11616 | to_intel_plane_state(plane->state); | |
11617 | int idx = intel_crtc->base.base.id, ret; | |
11618 | int i = drm_plane_index(plane); | |
11619 | bool mode_changed = needs_modeset(crtc_state); | |
11620 | bool was_crtc_enabled = crtc->state->active; | |
11621 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11622 | bool turn_off, turn_on, visible, was_visible; |
11623 | struct drm_framebuffer *fb = plane_state->fb; | |
11624 | ||
11625 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11626 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11627 | ret = skl_update_scaler_plane( | |
11628 | to_intel_crtc_state(crtc_state), | |
11629 | to_intel_plane_state(plane_state)); | |
11630 | if (ret) | |
11631 | return ret; | |
11632 | } | |
11633 | ||
11634 | /* | |
11635 | * Disabling a plane is always okay; we just need to update | |
11636 | * fb tracking in a special way since cleanup_fb() won't | |
11637 | * get called by the plane helpers. | |
11638 | */ | |
11639 | if (old_plane_state->base.fb && !fb) | |
11640 | intel_crtc->atomic.disabled_planes |= 1 << i; | |
11641 | ||
da20eabd ML |
11642 | was_visible = old_plane_state->visible; |
11643 | visible = to_intel_plane_state(plane_state)->visible; | |
11644 | ||
11645 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11646 | was_visible = false; | |
11647 | ||
11648 | if (!is_crtc_enabled && WARN_ON(visible)) | |
11649 | visible = false; | |
11650 | ||
11651 | if (!was_visible && !visible) | |
11652 | return 0; | |
11653 | ||
11654 | turn_off = was_visible && (!visible || mode_changed); | |
11655 | turn_on = visible && (!was_visible || mode_changed); | |
11656 | ||
11657 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11658 | plane->base.id, fb ? fb->base.id : -1); | |
11659 | ||
11660 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11661 | plane->base.id, was_visible, visible, | |
11662 | turn_off, turn_on, mode_changed); | |
11663 | ||
852eb00d | 11664 | if (turn_on) { |
f015c551 | 11665 | intel_crtc->atomic.update_wm_pre = true; |
852eb00d VS |
11666 | /* must disable cxsr around plane enable/disable */ |
11667 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11668 | intel_crtc->atomic.disable_cxsr = true; | |
11669 | /* to potentially re-enable cxsr */ | |
11670 | intel_crtc->atomic.wait_vblank = true; | |
11671 | intel_crtc->atomic.update_wm_post = true; | |
11672 | } | |
11673 | } else if (turn_off) { | |
f015c551 | 11674 | intel_crtc->atomic.update_wm_post = true; |
852eb00d VS |
11675 | /* must disable cxsr around plane enable/disable */ |
11676 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11677 | if (is_crtc_enabled) | |
11678 | intel_crtc->atomic.wait_vblank = true; | |
11679 | intel_crtc->atomic.disable_cxsr = true; | |
11680 | } | |
11681 | } else if (intel_wm_need_update(plane, plane_state)) { | |
f015c551 | 11682 | intel_crtc->atomic.update_wm_pre = true; |
852eb00d | 11683 | } |
da20eabd | 11684 | |
8be6ca85 | 11685 | if (visible || was_visible) |
a9ff8714 VS |
11686 | intel_crtc->atomic.fb_bits |= |
11687 | to_intel_plane(plane)->frontbuffer_bit; | |
11688 | ||
da20eabd ML |
11689 | switch (plane->type) { |
11690 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd ML |
11691 | intel_crtc->atomic.wait_for_flips = true; |
11692 | intel_crtc->atomic.pre_disable_primary = turn_off; | |
11693 | intel_crtc->atomic.post_enable_primary = turn_on; | |
11694 | ||
066cf55b RV |
11695 | if (turn_off) { |
11696 | /* | |
11697 | * FIXME: Actually if we will still have any other | |
11698 | * plane enabled on the pipe we could let IPS enabled | |
11699 | * still, but for now lets consider that when we make | |
11700 | * primary invisible by setting DSPCNTR to 0 on | |
11701 | * update_primary_plane function IPS needs to be | |
11702 | * disable. | |
11703 | */ | |
11704 | intel_crtc->atomic.disable_ips = true; | |
11705 | ||
da20eabd | 11706 | intel_crtc->atomic.disable_fbc = true; |
066cf55b | 11707 | } |
da20eabd ML |
11708 | |
11709 | /* | |
11710 | * FBC does not work on some platforms for rotated | |
11711 | * planes, so disable it when rotation is not 0 and | |
11712 | * update it when rotation is set back to 0. | |
11713 | * | |
11714 | * FIXME: This is redundant with the fbc update done in | |
11715 | * the primary plane enable function except that that | |
11716 | * one is done too late. We eventually need to unify | |
11717 | * this. | |
11718 | */ | |
11719 | ||
11720 | if (visible && | |
11721 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11722 | dev_priv->fbc.crtc == intel_crtc && | |
11723 | plane_state->rotation != BIT(DRM_ROTATE_0)) | |
11724 | intel_crtc->atomic.disable_fbc = true; | |
11725 | ||
11726 | /* | |
11727 | * BDW signals flip done immediately if the plane | |
11728 | * is disabled, even if the plane enable is already | |
11729 | * armed to occur at the next vblank :( | |
11730 | */ | |
11731 | if (turn_on && IS_BROADWELL(dev)) | |
11732 | intel_crtc->atomic.wait_vblank = true; | |
11733 | ||
11734 | intel_crtc->atomic.update_fbc |= visible || mode_changed; | |
11735 | break; | |
11736 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11737 | break; |
11738 | case DRM_PLANE_TYPE_OVERLAY: | |
7809e5ae MR |
11739 | /* |
11740 | * WaCxSRDisabledForSpriteScaling:ivb | |
11741 | * | |
11742 | * cstate->update_wm was already set above, so this flag will | |
11743 | * take effect when we commit and program watermarks. | |
11744 | */ | |
11745 | if (IS_IVYBRIDGE(dev) && | |
11746 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11747 | !needs_scaling(old_plane_state)) { | |
11748 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; | |
11749 | } else if (turn_off && !mode_changed) { | |
da20eabd ML |
11750 | intel_crtc->atomic.wait_vblank = true; |
11751 | intel_crtc->atomic.update_sprite_watermarks |= | |
11752 | 1 << i; | |
11753 | } | |
7809e5ae MR |
11754 | |
11755 | break; | |
da20eabd ML |
11756 | } |
11757 | return 0; | |
11758 | } | |
11759 | ||
6d3a1ce7 ML |
11760 | static bool encoders_cloneable(const struct intel_encoder *a, |
11761 | const struct intel_encoder *b) | |
11762 | { | |
11763 | /* masks could be asymmetric, so check both ways */ | |
11764 | return a == b || (a->cloneable & (1 << b->type) && | |
11765 | b->cloneable & (1 << a->type)); | |
11766 | } | |
11767 | ||
11768 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11769 | struct intel_crtc *crtc, | |
11770 | struct intel_encoder *encoder) | |
11771 | { | |
11772 | struct intel_encoder *source_encoder; | |
11773 | struct drm_connector *connector; | |
11774 | struct drm_connector_state *connector_state; | |
11775 | int i; | |
11776 | ||
11777 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11778 | if (connector_state->crtc != &crtc->base) | |
11779 | continue; | |
11780 | ||
11781 | source_encoder = | |
11782 | to_intel_encoder(connector_state->best_encoder); | |
11783 | if (!encoders_cloneable(encoder, source_encoder)) | |
11784 | return false; | |
11785 | } | |
11786 | ||
11787 | return true; | |
11788 | } | |
11789 | ||
11790 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11791 | struct intel_crtc *crtc) | |
11792 | { | |
11793 | struct intel_encoder *encoder; | |
11794 | struct drm_connector *connector; | |
11795 | struct drm_connector_state *connector_state; | |
11796 | int i; | |
11797 | ||
11798 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11799 | if (connector_state->crtc != &crtc->base) | |
11800 | continue; | |
11801 | ||
11802 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11803 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11804 | return false; | |
11805 | } | |
11806 | ||
11807 | return true; | |
11808 | } | |
11809 | ||
11810 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11811 | struct drm_crtc_state *crtc_state) | |
11812 | { | |
cf5a15be | 11813 | struct drm_device *dev = crtc->dev; |
ad421372 | 11814 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11815 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11816 | struct intel_crtc_state *pipe_config = |
11817 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11818 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11819 | int ret; |
6d3a1ce7 ML |
11820 | bool mode_changed = needs_modeset(crtc_state); |
11821 | ||
11822 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11823 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11824 | return -EINVAL; | |
11825 | } | |
11826 | ||
852eb00d VS |
11827 | if (mode_changed && !crtc_state->active) |
11828 | intel_crtc->atomic.update_wm_post = true; | |
eddfcbcd | 11829 | |
ad421372 ML |
11830 | if (mode_changed && crtc_state->enable && |
11831 | dev_priv->display.crtc_compute_clock && | |
11832 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
11833 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
11834 | pipe_config); | |
11835 | if (ret) | |
11836 | return ret; | |
11837 | } | |
11838 | ||
e435d6e5 | 11839 | ret = 0; |
a28170f3 MR |
11840 | if (dev_priv->display.compute_pipe_wm) { |
11841 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
11842 | if (ret) | |
11843 | return ret; | |
11844 | } | |
11845 | ||
e435d6e5 ML |
11846 | if (INTEL_INFO(dev)->gen >= 9) { |
11847 | if (mode_changed) | |
11848 | ret = skl_update_scaler_crtc(pipe_config); | |
11849 | ||
11850 | if (!ret) | |
11851 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11852 | pipe_config); | |
11853 | } | |
11854 | ||
11855 | return ret; | |
6d3a1ce7 ML |
11856 | } |
11857 | ||
65b38e0d | 11858 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11859 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11860 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11861 | .atomic_begin = intel_begin_crtc_commit, |
11862 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11863 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11864 | }; |
11865 | ||
d29b2f9d ACO |
11866 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11867 | { | |
11868 | struct intel_connector *connector; | |
11869 | ||
11870 | for_each_intel_connector(dev, connector) { | |
11871 | if (connector->base.encoder) { | |
11872 | connector->base.state->best_encoder = | |
11873 | connector->base.encoder; | |
11874 | connector->base.state->crtc = | |
11875 | connector->base.encoder->crtc; | |
11876 | } else { | |
11877 | connector->base.state->best_encoder = NULL; | |
11878 | connector->base.state->crtc = NULL; | |
11879 | } | |
11880 | } | |
11881 | } | |
11882 | ||
050f7aeb | 11883 | static void |
eba905b2 | 11884 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11885 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11886 | { |
11887 | int bpp = pipe_config->pipe_bpp; | |
11888 | ||
11889 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11890 | connector->base.base.id, | |
c23cc417 | 11891 | connector->base.name); |
050f7aeb DV |
11892 | |
11893 | /* Don't use an invalid EDID bpc value */ | |
11894 | if (connector->base.display_info.bpc && | |
11895 | connector->base.display_info.bpc * 3 < bpp) { | |
11896 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11897 | bpp, connector->base.display_info.bpc*3); | |
11898 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11899 | } | |
11900 | ||
11901 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11902 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11903 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11904 | bpp); | |
11905 | pipe_config->pipe_bpp = 24; | |
11906 | } | |
11907 | } | |
11908 | ||
4e53c2e0 | 11909 | static int |
050f7aeb | 11910 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11911 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11912 | { |
050f7aeb | 11913 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11914 | struct drm_atomic_state *state; |
da3ced29 ACO |
11915 | struct drm_connector *connector; |
11916 | struct drm_connector_state *connector_state; | |
1486017f | 11917 | int bpp, i; |
4e53c2e0 | 11918 | |
d328c9d7 | 11919 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11920 | bpp = 10*3; |
d328c9d7 DV |
11921 | else if (INTEL_INFO(dev)->gen >= 5) |
11922 | bpp = 12*3; | |
11923 | else | |
11924 | bpp = 8*3; | |
11925 | ||
4e53c2e0 | 11926 | |
4e53c2e0 DV |
11927 | pipe_config->pipe_bpp = bpp; |
11928 | ||
1486017f ACO |
11929 | state = pipe_config->base.state; |
11930 | ||
4e53c2e0 | 11931 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11932 | for_each_connector_in_state(state, connector, connector_state, i) { |
11933 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11934 | continue; |
11935 | ||
da3ced29 ACO |
11936 | connected_sink_compute_bpp(to_intel_connector(connector), |
11937 | pipe_config); | |
4e53c2e0 DV |
11938 | } |
11939 | ||
11940 | return bpp; | |
11941 | } | |
11942 | ||
644db711 DV |
11943 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11944 | { | |
11945 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11946 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11947 | mode->crtc_clock, |
644db711 DV |
11948 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11949 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11950 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11951 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11952 | } | |
11953 | ||
c0b03411 | 11954 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11955 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11956 | const char *context) |
11957 | { | |
6a60cd87 CK |
11958 | struct drm_device *dev = crtc->base.dev; |
11959 | struct drm_plane *plane; | |
11960 | struct intel_plane *intel_plane; | |
11961 | struct intel_plane_state *state; | |
11962 | struct drm_framebuffer *fb; | |
11963 | ||
11964 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11965 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11966 | |
11967 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11968 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11969 | pipe_config->pipe_bpp, pipe_config->dither); | |
11970 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11971 | pipe_config->has_pch_encoder, | |
11972 | pipe_config->fdi_lanes, | |
11973 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11974 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11975 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 11976 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 11977 | pipe_config->has_dp_encoder, |
90a6b7b0 | 11978 | pipe_config->lane_count, |
eb14cb74 VS |
11979 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
11980 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11981 | pipe_config->dp_m_n.tu); | |
b95af8be | 11982 | |
90a6b7b0 | 11983 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 11984 | pipe_config->has_dp_encoder, |
90a6b7b0 | 11985 | pipe_config->lane_count, |
b95af8be VK |
11986 | pipe_config->dp_m2_n2.gmch_m, |
11987 | pipe_config->dp_m2_n2.gmch_n, | |
11988 | pipe_config->dp_m2_n2.link_m, | |
11989 | pipe_config->dp_m2_n2.link_n, | |
11990 | pipe_config->dp_m2_n2.tu); | |
11991 | ||
55072d19 DV |
11992 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11993 | pipe_config->has_audio, | |
11994 | pipe_config->has_infoframe); | |
11995 | ||
c0b03411 | 11996 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11997 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11998 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11999 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12000 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12001 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12002 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12003 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12004 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12005 | crtc->num_scalers, | |
12006 | pipe_config->scaler_state.scaler_users, | |
12007 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12008 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12009 | pipe_config->gmch_pfit.control, | |
12010 | pipe_config->gmch_pfit.pgm_ratios, | |
12011 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12012 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12013 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12014 | pipe_config->pch_pfit.size, |
12015 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12016 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12017 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12018 | |
415ff0f6 | 12019 | if (IS_BROXTON(dev)) { |
05712c15 | 12020 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12021 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12022 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12023 | pipe_config->ddi_pll_sel, |
12024 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12025 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12026 | pipe_config->dpll_hw_state.pll0, |
12027 | pipe_config->dpll_hw_state.pll1, | |
12028 | pipe_config->dpll_hw_state.pll2, | |
12029 | pipe_config->dpll_hw_state.pll3, | |
12030 | pipe_config->dpll_hw_state.pll6, | |
12031 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12032 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12033 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 TU |
12034 | pipe_config->dpll_hw_state.pcsdw12); |
12035 | } else if (IS_SKYLAKE(dev)) { | |
12036 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " | |
12037 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12038 | pipe_config->ddi_pll_sel, | |
12039 | pipe_config->dpll_hw_state.ctrl1, | |
12040 | pipe_config->dpll_hw_state.cfgcr1, | |
12041 | pipe_config->dpll_hw_state.cfgcr2); | |
12042 | } else if (HAS_DDI(dev)) { | |
12043 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n", | |
12044 | pipe_config->ddi_pll_sel, | |
12045 | pipe_config->dpll_hw_state.wrpll); | |
12046 | } else { | |
12047 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12048 | "fp0: 0x%x, fp1: 0x%x\n", | |
12049 | pipe_config->dpll_hw_state.dpll, | |
12050 | pipe_config->dpll_hw_state.dpll_md, | |
12051 | pipe_config->dpll_hw_state.fp0, | |
12052 | pipe_config->dpll_hw_state.fp1); | |
12053 | } | |
12054 | ||
6a60cd87 CK |
12055 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12056 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12057 | intel_plane = to_intel_plane(plane); | |
12058 | if (intel_plane->pipe != crtc->pipe) | |
12059 | continue; | |
12060 | ||
12061 | state = to_intel_plane_state(plane->state); | |
12062 | fb = state->base.fb; | |
12063 | if (!fb) { | |
12064 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12065 | "disabled, scaler_id = %d\n", | |
12066 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12067 | plane->base.id, intel_plane->pipe, | |
12068 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12069 | drm_plane_index(plane), state->scaler_id); | |
12070 | continue; | |
12071 | } | |
12072 | ||
12073 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12074 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12075 | plane->base.id, intel_plane->pipe, | |
12076 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12077 | drm_plane_index(plane)); | |
12078 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12079 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12080 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12081 | state->scaler_id, | |
12082 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12083 | drm_rect_width(&state->src) >> 16, | |
12084 | drm_rect_height(&state->src) >> 16, | |
12085 | state->dst.x1, state->dst.y1, | |
12086 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12087 | } | |
c0b03411 DV |
12088 | } |
12089 | ||
5448a00d | 12090 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12091 | { |
5448a00d ACO |
12092 | struct drm_device *dev = state->dev; |
12093 | struct intel_encoder *encoder; | |
da3ced29 | 12094 | struct drm_connector *connector; |
5448a00d | 12095 | struct drm_connector_state *connector_state; |
00f0b378 | 12096 | unsigned int used_ports = 0; |
5448a00d | 12097 | int i; |
00f0b378 VS |
12098 | |
12099 | /* | |
12100 | * Walk the connector list instead of the encoder | |
12101 | * list to detect the problem on ddi platforms | |
12102 | * where there's just one encoder per digital port. | |
12103 | */ | |
da3ced29 | 12104 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 12105 | if (!connector_state->best_encoder) |
00f0b378 VS |
12106 | continue; |
12107 | ||
5448a00d ACO |
12108 | encoder = to_intel_encoder(connector_state->best_encoder); |
12109 | ||
12110 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12111 | |
12112 | switch (encoder->type) { | |
12113 | unsigned int port_mask; | |
12114 | case INTEL_OUTPUT_UNKNOWN: | |
12115 | if (WARN_ON(!HAS_DDI(dev))) | |
12116 | break; | |
12117 | case INTEL_OUTPUT_DISPLAYPORT: | |
12118 | case INTEL_OUTPUT_HDMI: | |
12119 | case INTEL_OUTPUT_EDP: | |
12120 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12121 | ||
12122 | /* the same port mustn't appear more than once */ | |
12123 | if (used_ports & port_mask) | |
12124 | return false; | |
12125 | ||
12126 | used_ports |= port_mask; | |
12127 | default: | |
12128 | break; | |
12129 | } | |
12130 | } | |
12131 | ||
12132 | return true; | |
12133 | } | |
12134 | ||
83a57153 ACO |
12135 | static void |
12136 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12137 | { | |
12138 | struct drm_crtc_state tmp_state; | |
663a3640 | 12139 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12140 | struct intel_dpll_hw_state dpll_hw_state; |
12141 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12142 | uint32_t ddi_pll_sel; |
c4e2d043 | 12143 | bool force_thru; |
83a57153 | 12144 | |
7546a384 ACO |
12145 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12146 | * kzalloc'd. Code that depends on any field being zero should be | |
12147 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12148 | * only fields that are know to not cause problems are preserved. */ | |
12149 | ||
83a57153 | 12150 | tmp_state = crtc_state->base; |
663a3640 | 12151 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12152 | shared_dpll = crtc_state->shared_dpll; |
12153 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12154 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12155 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12156 | |
83a57153 | 12157 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12158 | |
83a57153 | 12159 | crtc_state->base = tmp_state; |
663a3640 | 12160 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12161 | crtc_state->shared_dpll = shared_dpll; |
12162 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12163 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12164 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12165 | } |
12166 | ||
548ee15b | 12167 | static int |
b8cecdf5 | 12168 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12169 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12170 | { |
b359283a | 12171 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12172 | struct intel_encoder *encoder; |
da3ced29 | 12173 | struct drm_connector *connector; |
0b901879 | 12174 | struct drm_connector_state *connector_state; |
d328c9d7 | 12175 | int base_bpp, ret = -EINVAL; |
0b901879 | 12176 | int i; |
e29c22c0 | 12177 | bool retry = true; |
ee7b9f93 | 12178 | |
83a57153 | 12179 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12180 | |
e143a21c DV |
12181 | pipe_config->cpu_transcoder = |
12182 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12183 | |
2960bc9c ID |
12184 | /* |
12185 | * Sanitize sync polarity flags based on requested ones. If neither | |
12186 | * positive or negative polarity is requested, treat this as meaning | |
12187 | * negative polarity. | |
12188 | */ | |
2d112de7 | 12189 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12190 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12191 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12192 | |
2d112de7 | 12193 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12194 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12195 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12196 | |
d328c9d7 DV |
12197 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12198 | pipe_config); | |
12199 | if (base_bpp < 0) | |
4e53c2e0 DV |
12200 | goto fail; |
12201 | ||
e41a56be VS |
12202 | /* |
12203 | * Determine the real pipe dimensions. Note that stereo modes can | |
12204 | * increase the actual pipe size due to the frame doubling and | |
12205 | * insertion of additional space for blanks between the frame. This | |
12206 | * is stored in the crtc timings. We use the requested mode to do this | |
12207 | * computation to clearly distinguish it from the adjusted mode, which | |
12208 | * can be changed by the connectors in the below retry loop. | |
12209 | */ | |
2d112de7 | 12210 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12211 | &pipe_config->pipe_src_w, |
12212 | &pipe_config->pipe_src_h); | |
e41a56be | 12213 | |
e29c22c0 | 12214 | encoder_retry: |
ef1b460d | 12215 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12216 | pipe_config->port_clock = 0; |
ef1b460d | 12217 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12218 | |
135c81b8 | 12219 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12220 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12221 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12222 | |
7758a113 DV |
12223 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12224 | * adjust it according to limitations or connector properties, and also | |
12225 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12226 | */ |
da3ced29 | 12227 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12228 | if (connector_state->crtc != crtc) |
7758a113 | 12229 | continue; |
7ae89233 | 12230 | |
0b901879 ACO |
12231 | encoder = to_intel_encoder(connector_state->best_encoder); |
12232 | ||
efea6e8e DV |
12233 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12234 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12235 | goto fail; |
12236 | } | |
ee7b9f93 | 12237 | } |
47f1c6c9 | 12238 | |
ff9a6750 DV |
12239 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12240 | * done afterwards in case the encoder adjusts the mode. */ | |
12241 | if (!pipe_config->port_clock) | |
2d112de7 | 12242 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12243 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12244 | |
a43f6e0f | 12245 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12246 | if (ret < 0) { |
7758a113 DV |
12247 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12248 | goto fail; | |
ee7b9f93 | 12249 | } |
e29c22c0 DV |
12250 | |
12251 | if (ret == RETRY) { | |
12252 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12253 | ret = -EINVAL; | |
12254 | goto fail; | |
12255 | } | |
12256 | ||
12257 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12258 | retry = false; | |
12259 | goto encoder_retry; | |
12260 | } | |
12261 | ||
e8fa4270 DV |
12262 | /* Dithering seems to not pass-through bits correctly when it should, so |
12263 | * only enable it on 6bpc panels. */ | |
12264 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12265 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12266 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12267 | |
7758a113 | 12268 | fail: |
548ee15b | 12269 | return ret; |
ee7b9f93 | 12270 | } |
47f1c6c9 | 12271 | |
ea9d758d | 12272 | static void |
4740b0f2 | 12273 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12274 | { |
0a9ab303 ACO |
12275 | struct drm_crtc *crtc; |
12276 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12277 | int i; |
ea9d758d | 12278 | |
7668851f | 12279 | /* Double check state. */ |
8a75d157 | 12280 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12281 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12282 | |
12283 | /* Update hwmode for vblank functions */ | |
12284 | if (crtc->state->active) | |
12285 | crtc->hwmode = crtc->state->adjusted_mode; | |
12286 | else | |
12287 | crtc->hwmode.crtc_clock = 0; | |
ea9d758d | 12288 | } |
ea9d758d DV |
12289 | } |
12290 | ||
3bd26263 | 12291 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12292 | { |
3bd26263 | 12293 | int diff; |
f1f644dc JB |
12294 | |
12295 | if (clock1 == clock2) | |
12296 | return true; | |
12297 | ||
12298 | if (!clock1 || !clock2) | |
12299 | return false; | |
12300 | ||
12301 | diff = abs(clock1 - clock2); | |
12302 | ||
12303 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12304 | return true; | |
12305 | ||
12306 | return false; | |
12307 | } | |
12308 | ||
25c5b266 DV |
12309 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12310 | list_for_each_entry((intel_crtc), \ | |
12311 | &(dev)->mode_config.crtc_list, \ | |
12312 | base.head) \ | |
0973f18f | 12313 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12314 | |
cfb23ed6 ML |
12315 | static bool |
12316 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12317 | unsigned int m2, unsigned int n2, | |
12318 | bool exact) | |
12319 | { | |
12320 | if (m == m2 && n == n2) | |
12321 | return true; | |
12322 | ||
12323 | if (exact || !m || !n || !m2 || !n2) | |
12324 | return false; | |
12325 | ||
12326 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12327 | ||
12328 | if (m > m2) { | |
12329 | while (m > m2) { | |
12330 | m2 <<= 1; | |
12331 | n2 <<= 1; | |
12332 | } | |
12333 | } else if (m < m2) { | |
12334 | while (m < m2) { | |
12335 | m <<= 1; | |
12336 | n <<= 1; | |
12337 | } | |
12338 | } | |
12339 | ||
12340 | return m == m2 && n == n2; | |
12341 | } | |
12342 | ||
12343 | static bool | |
12344 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12345 | struct intel_link_m_n *m2_n2, | |
12346 | bool adjust) | |
12347 | { | |
12348 | if (m_n->tu == m2_n2->tu && | |
12349 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12350 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12351 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12352 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12353 | if (adjust) | |
12354 | *m2_n2 = *m_n; | |
12355 | ||
12356 | return true; | |
12357 | } | |
12358 | ||
12359 | return false; | |
12360 | } | |
12361 | ||
0e8ffe1b | 12362 | static bool |
2fa2fe9a | 12363 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12364 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12365 | struct intel_crtc_state *pipe_config, |
12366 | bool adjust) | |
0e8ffe1b | 12367 | { |
cfb23ed6 ML |
12368 | bool ret = true; |
12369 | ||
12370 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12371 | do { \ | |
12372 | if (!adjust) \ | |
12373 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12374 | else \ | |
12375 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12376 | } while (0) | |
12377 | ||
66e985c0 DV |
12378 | #define PIPE_CONF_CHECK_X(name) \ |
12379 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12380 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12381 | "(expected 0x%08x, found 0x%08x)\n", \ |
12382 | current_config->name, \ | |
12383 | pipe_config->name); \ | |
cfb23ed6 | 12384 | ret = false; \ |
66e985c0 DV |
12385 | } |
12386 | ||
08a24034 DV |
12387 | #define PIPE_CONF_CHECK_I(name) \ |
12388 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12389 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12390 | "(expected %i, found %i)\n", \ |
12391 | current_config->name, \ | |
12392 | pipe_config->name); \ | |
cfb23ed6 ML |
12393 | ret = false; \ |
12394 | } | |
12395 | ||
12396 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12397 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12398 | &pipe_config->name,\ | |
12399 | adjust)) { \ | |
12400 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12401 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12402 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12403 | current_config->name.tu, \ | |
12404 | current_config->name.gmch_m, \ | |
12405 | current_config->name.gmch_n, \ | |
12406 | current_config->name.link_m, \ | |
12407 | current_config->name.link_n, \ | |
12408 | pipe_config->name.tu, \ | |
12409 | pipe_config->name.gmch_m, \ | |
12410 | pipe_config->name.gmch_n, \ | |
12411 | pipe_config->name.link_m, \ | |
12412 | pipe_config->name.link_n); \ | |
12413 | ret = false; \ | |
12414 | } | |
12415 | ||
12416 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12417 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12418 | &pipe_config->name, adjust) && \ | |
12419 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12420 | &pipe_config->name, adjust)) { \ | |
12421 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12422 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12423 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12424 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12425 | current_config->name.tu, \ | |
12426 | current_config->name.gmch_m, \ | |
12427 | current_config->name.gmch_n, \ | |
12428 | current_config->name.link_m, \ | |
12429 | current_config->name.link_n, \ | |
12430 | current_config->alt_name.tu, \ | |
12431 | current_config->alt_name.gmch_m, \ | |
12432 | current_config->alt_name.gmch_n, \ | |
12433 | current_config->alt_name.link_m, \ | |
12434 | current_config->alt_name.link_n, \ | |
12435 | pipe_config->name.tu, \ | |
12436 | pipe_config->name.gmch_m, \ | |
12437 | pipe_config->name.gmch_n, \ | |
12438 | pipe_config->name.link_m, \ | |
12439 | pipe_config->name.link_n); \ | |
12440 | ret = false; \ | |
88adfff1 DV |
12441 | } |
12442 | ||
b95af8be VK |
12443 | /* This is required for BDW+ where there is only one set of registers for |
12444 | * switching between high and low RR. | |
12445 | * This macro can be used whenever a comparison has to be made between one | |
12446 | * hw state and multiple sw state variables. | |
12447 | */ | |
12448 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12449 | if ((current_config->name != pipe_config->name) && \ | |
12450 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12451 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12452 | "(expected %i or %i, found %i)\n", \ |
12453 | current_config->name, \ | |
12454 | current_config->alt_name, \ | |
12455 | pipe_config->name); \ | |
cfb23ed6 | 12456 | ret = false; \ |
b95af8be VK |
12457 | } |
12458 | ||
1bd1bd80 DV |
12459 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12460 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12461 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12462 | "(expected %i, found %i)\n", \ |
12463 | current_config->name & (mask), \ | |
12464 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12465 | ret = false; \ |
1bd1bd80 DV |
12466 | } |
12467 | ||
5e550656 VS |
12468 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12469 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12470 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12471 | "(expected %i, found %i)\n", \ |
12472 | current_config->name, \ | |
12473 | pipe_config->name); \ | |
cfb23ed6 | 12474 | ret = false; \ |
5e550656 VS |
12475 | } |
12476 | ||
bb760063 DV |
12477 | #define PIPE_CONF_QUIRK(quirk) \ |
12478 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12479 | ||
eccb140b DV |
12480 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12481 | ||
08a24034 DV |
12482 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12483 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12484 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12485 | |
eb14cb74 | 12486 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12487 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12488 | |
12489 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12490 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12491 | ||
12492 | PIPE_CONF_CHECK_I(has_drrs); | |
12493 | if (current_config->has_drrs) | |
12494 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12495 | } else | |
12496 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12497 | |
2d112de7 ACO |
12498 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12499 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12500 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12501 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12502 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12503 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12504 | |
2d112de7 ACO |
12505 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12506 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12507 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12508 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12509 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12510 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12511 | |
c93f54cf | 12512 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12513 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
12514 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
12515 | IS_VALLEYVIEW(dev)) | |
12516 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 12517 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12518 | |
9ed109a7 DV |
12519 | PIPE_CONF_CHECK_I(has_audio); |
12520 | ||
2d112de7 | 12521 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12522 | DRM_MODE_FLAG_INTERLACE); |
12523 | ||
bb760063 | 12524 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12525 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12526 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12527 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12528 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12529 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12530 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12531 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12532 | DRM_MODE_FLAG_NVSYNC); |
12533 | } | |
045ac3b5 | 12534 | |
333b8ca8 | 12535 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12536 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12537 | if (INTEL_INFO(dev)->gen < 4) | |
12538 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12539 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12540 | |
bfd16b2a ML |
12541 | if (!adjust) { |
12542 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12543 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12544 | ||
12545 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12546 | if (current_config->pch_pfit.enabled) { | |
12547 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12548 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12549 | } | |
2fa2fe9a | 12550 | |
7aefe2b5 ML |
12551 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12552 | } | |
a1b2278e | 12553 | |
e59150dc JB |
12554 | /* BDW+ don't expose a synchronous way to read the state */ |
12555 | if (IS_HASWELL(dev)) | |
12556 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12557 | |
282740f7 VS |
12558 | PIPE_CONF_CHECK_I(double_wide); |
12559 | ||
26804afd DV |
12560 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12561 | ||
c0d43d62 | 12562 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12563 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12564 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12565 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12566 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12567 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
12568 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12569 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12570 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12571 | |
42571aef VS |
12572 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12573 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12574 | ||
2d112de7 | 12575 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12576 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12577 | |
66e985c0 | 12578 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12579 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12580 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12581 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12582 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12583 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12584 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12585 | |
cfb23ed6 | 12586 | return ret; |
0e8ffe1b DV |
12587 | } |
12588 | ||
08db6652 DL |
12589 | static void check_wm_state(struct drm_device *dev) |
12590 | { | |
12591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12592 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12593 | struct intel_crtc *intel_crtc; | |
12594 | int plane; | |
12595 | ||
12596 | if (INTEL_INFO(dev)->gen < 9) | |
12597 | return; | |
12598 | ||
12599 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12600 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12601 | ||
12602 | for_each_intel_crtc(dev, intel_crtc) { | |
12603 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12604 | const enum pipe pipe = intel_crtc->pipe; | |
12605 | ||
12606 | if (!intel_crtc->active) | |
12607 | continue; | |
12608 | ||
12609 | /* planes */ | |
dd740780 | 12610 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12611 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12612 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12613 | ||
12614 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12615 | continue; | |
12616 | ||
12617 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12618 | "(expected (%u,%u), found (%u,%u))\n", | |
12619 | pipe_name(pipe), plane + 1, | |
12620 | sw_entry->start, sw_entry->end, | |
12621 | hw_entry->start, hw_entry->end); | |
12622 | } | |
12623 | ||
12624 | /* cursor */ | |
4969d33e MR |
12625 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12626 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12627 | |
12628 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12629 | continue; | |
12630 | ||
12631 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12632 | "(expected (%u,%u), found (%u,%u))\n", | |
12633 | pipe_name(pipe), | |
12634 | sw_entry->start, sw_entry->end, | |
12635 | hw_entry->start, hw_entry->end); | |
12636 | } | |
12637 | } | |
12638 | ||
91d1b4bd | 12639 | static void |
35dd3c64 ML |
12640 | check_connector_state(struct drm_device *dev, |
12641 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12642 | { |
35dd3c64 ML |
12643 | struct drm_connector_state *old_conn_state; |
12644 | struct drm_connector *connector; | |
12645 | int i; | |
8af6cf88 | 12646 | |
35dd3c64 ML |
12647 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12648 | struct drm_encoder *encoder = connector->encoder; | |
12649 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12650 | |
8af6cf88 DV |
12651 | /* This also checks the encoder/connector hw state with the |
12652 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12653 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12654 | |
ad3c558f | 12655 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12656 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12657 | } |
91d1b4bd DV |
12658 | } |
12659 | ||
12660 | static void | |
12661 | check_encoder_state(struct drm_device *dev) | |
12662 | { | |
12663 | struct intel_encoder *encoder; | |
12664 | struct intel_connector *connector; | |
8af6cf88 | 12665 | |
b2784e15 | 12666 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12667 | bool enabled = false; |
4d20cd86 | 12668 | enum pipe pipe; |
8af6cf88 DV |
12669 | |
12670 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12671 | encoder->base.base.id, | |
8e329a03 | 12672 | encoder->base.name); |
8af6cf88 | 12673 | |
3a3371ff | 12674 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12675 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12676 | continue; |
12677 | enabled = true; | |
ad3c558f ML |
12678 | |
12679 | I915_STATE_WARN(connector->base.state->crtc != | |
12680 | encoder->base.crtc, | |
12681 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12682 | } |
0e32b39c | 12683 | |
e2c719b7 | 12684 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12685 | "encoder's enabled state mismatch " |
12686 | "(expected %i, found %i)\n", | |
12687 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12688 | |
12689 | if (!encoder->base.crtc) { | |
4d20cd86 | 12690 | bool active; |
7c60d198 | 12691 | |
4d20cd86 ML |
12692 | active = encoder->get_hw_state(encoder, &pipe); |
12693 | I915_STATE_WARN(active, | |
12694 | "encoder detached but still enabled on pipe %c.\n", | |
12695 | pipe_name(pipe)); | |
7c60d198 | 12696 | } |
8af6cf88 | 12697 | } |
91d1b4bd DV |
12698 | } |
12699 | ||
12700 | static void | |
4d20cd86 | 12701 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12702 | { |
fbee40df | 12703 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12704 | struct intel_encoder *encoder; |
4d20cd86 ML |
12705 | struct drm_crtc_state *old_crtc_state; |
12706 | struct drm_crtc *crtc; | |
12707 | int i; | |
8af6cf88 | 12708 | |
4d20cd86 ML |
12709 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12710 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12711 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12712 | bool active; |
8af6cf88 | 12713 | |
bfd16b2a ML |
12714 | if (!needs_modeset(crtc->state) && |
12715 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12716 | continue; |
045ac3b5 | 12717 | |
4d20cd86 ML |
12718 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12719 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12720 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12721 | pipe_config->base.crtc = crtc; | |
12722 | pipe_config->base.state = old_state; | |
8af6cf88 | 12723 | |
4d20cd86 ML |
12724 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12725 | crtc->base.id); | |
8af6cf88 | 12726 | |
4d20cd86 ML |
12727 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12728 | pipe_config); | |
d62cf62a | 12729 | |
b6b5d049 | 12730 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12731 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12732 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12733 | active = crtc->state->active; | |
6c49f241 | 12734 | |
4d20cd86 | 12735 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12736 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12737 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12738 | |
4d20cd86 | 12739 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12740 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12741 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12742 | ||
12743 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12744 | enum pipe pipe; | |
12745 | ||
12746 | active = encoder->get_hw_state(encoder, &pipe); | |
12747 | I915_STATE_WARN(active != crtc->state->active, | |
12748 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12749 | encoder->base.base.id, active, crtc->state->active); | |
12750 | ||
12751 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12752 | "Encoder connected to wrong pipe %c\n", | |
12753 | pipe_name(pipe)); | |
12754 | ||
12755 | if (active) | |
12756 | encoder->get_config(encoder, pipe_config); | |
12757 | } | |
53d9f4e9 | 12758 | |
4d20cd86 | 12759 | if (!crtc->state->active) |
cfb23ed6 ML |
12760 | continue; |
12761 | ||
4d20cd86 ML |
12762 | sw_config = to_intel_crtc_state(crtc->state); |
12763 | if (!intel_pipe_config_compare(dev, sw_config, | |
12764 | pipe_config, false)) { | |
e2c719b7 | 12765 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12766 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12767 | "[hw state]"); |
4d20cd86 | 12768 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12769 | "[sw state]"); |
12770 | } | |
8af6cf88 DV |
12771 | } |
12772 | } | |
12773 | ||
91d1b4bd DV |
12774 | static void |
12775 | check_shared_dpll_state(struct drm_device *dev) | |
12776 | { | |
fbee40df | 12777 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12778 | struct intel_crtc *crtc; |
12779 | struct intel_dpll_hw_state dpll_hw_state; | |
12780 | int i; | |
5358901f DV |
12781 | |
12782 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12783 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12784 | int enabled_crtcs = 0, active_crtcs = 0; | |
12785 | bool active; | |
12786 | ||
12787 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12788 | ||
12789 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12790 | ||
12791 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12792 | ||
e2c719b7 | 12793 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12794 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12795 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12796 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12797 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12798 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12799 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12800 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12801 | "pll on state mismatch (expected %i, found %i)\n", |
12802 | pll->on, active); | |
12803 | ||
d3fcc808 | 12804 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12805 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12806 | enabled_crtcs++; |
12807 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12808 | active_crtcs++; | |
12809 | } | |
e2c719b7 | 12810 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12811 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12812 | pll->active, active_crtcs); | |
e2c719b7 | 12813 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12814 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12815 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12816 | |
e2c719b7 | 12817 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12818 | sizeof(dpll_hw_state)), |
12819 | "pll hw state mismatch\n"); | |
5358901f | 12820 | } |
8af6cf88 DV |
12821 | } |
12822 | ||
ee165b1a ML |
12823 | static void |
12824 | intel_modeset_check_state(struct drm_device *dev, | |
12825 | struct drm_atomic_state *old_state) | |
91d1b4bd | 12826 | { |
08db6652 | 12827 | check_wm_state(dev); |
35dd3c64 | 12828 | check_connector_state(dev, old_state); |
91d1b4bd | 12829 | check_encoder_state(dev); |
4d20cd86 | 12830 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
12831 | check_shared_dpll_state(dev); |
12832 | } | |
12833 | ||
5cec258b | 12834 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12835 | int dotclock) |
12836 | { | |
12837 | /* | |
12838 | * FDI already provided one idea for the dotclock. | |
12839 | * Yell if the encoder disagrees. | |
12840 | */ | |
2d112de7 | 12841 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12842 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12843 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12844 | } |
12845 | ||
80715b2f VS |
12846 | static void update_scanline_offset(struct intel_crtc *crtc) |
12847 | { | |
12848 | struct drm_device *dev = crtc->base.dev; | |
12849 | ||
12850 | /* | |
12851 | * The scanline counter increments at the leading edge of hsync. | |
12852 | * | |
12853 | * On most platforms it starts counting from vtotal-1 on the | |
12854 | * first active line. That means the scanline counter value is | |
12855 | * always one less than what we would expect. Ie. just after | |
12856 | * start of vblank, which also occurs at start of hsync (on the | |
12857 | * last active line), the scanline counter will read vblank_start-1. | |
12858 | * | |
12859 | * On gen2 the scanline counter starts counting from 1 instead | |
12860 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12861 | * to keep the value positive), instead of adding one. | |
12862 | * | |
12863 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12864 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12865 | * there's an extra 1 line difference. So we need to add two instead of | |
12866 | * one to the value. | |
12867 | */ | |
12868 | if (IS_GEN2(dev)) { | |
124abe07 | 12869 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12870 | int vtotal; |
12871 | ||
124abe07 VS |
12872 | vtotal = adjusted_mode->crtc_vtotal; |
12873 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
12874 | vtotal /= 2; |
12875 | ||
12876 | crtc->scanline_offset = vtotal - 1; | |
12877 | } else if (HAS_DDI(dev) && | |
409ee761 | 12878 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12879 | crtc->scanline_offset = 2; |
12880 | } else | |
12881 | crtc->scanline_offset = 1; | |
12882 | } | |
12883 | ||
ad421372 | 12884 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12885 | { |
225da59b | 12886 | struct drm_device *dev = state->dev; |
ed6739ef | 12887 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 12888 | struct intel_shared_dpll_config *shared_dpll = NULL; |
ed6739ef | 12889 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
12890 | struct intel_crtc_state *intel_crtc_state; |
12891 | struct drm_crtc *crtc; | |
12892 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 12893 | int i; |
ed6739ef ACO |
12894 | |
12895 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12896 | return; |
ed6739ef | 12897 | |
0a9ab303 | 12898 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
ad421372 ML |
12899 | int dpll; |
12900 | ||
0a9ab303 | 12901 | intel_crtc = to_intel_crtc(crtc); |
4978cc93 | 12902 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
ad421372 | 12903 | dpll = intel_crtc_state->shared_dpll; |
0a9ab303 | 12904 | |
ad421372 | 12905 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
225da59b ACO |
12906 | continue; |
12907 | ||
ad421372 | 12908 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
0a9ab303 | 12909 | |
ad421372 ML |
12910 | if (!shared_dpll) |
12911 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 12912 | |
ad421372 ML |
12913 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
12914 | } | |
ed6739ef ACO |
12915 | } |
12916 | ||
99d736a2 ML |
12917 | /* |
12918 | * This implements the workaround described in the "notes" section of the mode | |
12919 | * set sequence documentation. When going from no pipes or single pipe to | |
12920 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12921 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12922 | */ | |
12923 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12924 | { | |
12925 | struct drm_crtc_state *crtc_state; | |
12926 | struct intel_crtc *intel_crtc; | |
12927 | struct drm_crtc *crtc; | |
12928 | struct intel_crtc_state *first_crtc_state = NULL; | |
12929 | struct intel_crtc_state *other_crtc_state = NULL; | |
12930 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12931 | int i; | |
12932 | ||
12933 | /* look at all crtc's that are going to be enabled in during modeset */ | |
12934 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12935 | intel_crtc = to_intel_crtc(crtc); | |
12936 | ||
12937 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12938 | continue; | |
12939 | ||
12940 | if (first_crtc_state) { | |
12941 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
12942 | break; | |
12943 | } else { | |
12944 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
12945 | first_pipe = intel_crtc->pipe; | |
12946 | } | |
12947 | } | |
12948 | ||
12949 | /* No workaround needed? */ | |
12950 | if (!first_crtc_state) | |
12951 | return 0; | |
12952 | ||
12953 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
12954 | for_each_intel_crtc(state->dev, intel_crtc) { | |
12955 | struct intel_crtc_state *pipe_config; | |
12956 | ||
12957 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12958 | if (IS_ERR(pipe_config)) | |
12959 | return PTR_ERR(pipe_config); | |
12960 | ||
12961 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
12962 | ||
12963 | if (!pipe_config->base.active || | |
12964 | needs_modeset(&pipe_config->base)) | |
12965 | continue; | |
12966 | ||
12967 | /* 2 or more enabled crtcs means no need for w/a */ | |
12968 | if (enabled_pipe != INVALID_PIPE) | |
12969 | return 0; | |
12970 | ||
12971 | enabled_pipe = intel_crtc->pipe; | |
12972 | } | |
12973 | ||
12974 | if (enabled_pipe != INVALID_PIPE) | |
12975 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
12976 | else if (other_crtc_state) | |
12977 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
12978 | ||
12979 | return 0; | |
12980 | } | |
12981 | ||
27c329ed ML |
12982 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
12983 | { | |
12984 | struct drm_crtc *crtc; | |
12985 | struct drm_crtc_state *crtc_state; | |
12986 | int ret = 0; | |
12987 | ||
12988 | /* add all active pipes to the state */ | |
12989 | for_each_crtc(state->dev, crtc) { | |
12990 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
12991 | if (IS_ERR(crtc_state)) | |
12992 | return PTR_ERR(crtc_state); | |
12993 | ||
12994 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
12995 | continue; | |
12996 | ||
12997 | crtc_state->mode_changed = true; | |
12998 | ||
12999 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13000 | if (ret) | |
13001 | break; | |
13002 | ||
13003 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13004 | if (ret) | |
13005 | break; | |
13006 | } | |
13007 | ||
13008 | return ret; | |
13009 | } | |
13010 | ||
c347a676 | 13011 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd ACO |
13012 | { |
13013 | struct drm_device *dev = state->dev; | |
27c329ed | 13014 | struct drm_i915_private *dev_priv = dev->dev_private; |
054518dd ACO |
13015 | int ret; |
13016 | ||
b359283a ML |
13017 | if (!check_digital_port_conflicts(state)) { |
13018 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13019 | return -EINVAL; | |
13020 | } | |
13021 | ||
054518dd ACO |
13022 | /* |
13023 | * See if the config requires any additional preparation, e.g. | |
13024 | * to adjust global state with pipes off. We need to do this | |
13025 | * here so we can get the modeset_pipe updated config for the new | |
13026 | * mode set on this crtc. For other crtcs we need to use the | |
13027 | * adjusted_mode bits in the crtc directly. | |
13028 | */ | |
27c329ed ML |
13029 | if (dev_priv->display.modeset_calc_cdclk) { |
13030 | unsigned int cdclk; | |
b432e5cf | 13031 | |
27c329ed ML |
13032 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13033 | ||
13034 | cdclk = to_intel_atomic_state(state)->cdclk; | |
13035 | if (!ret && cdclk != dev_priv->cdclk_freq) | |
13036 | ret = intel_modeset_all_pipes(state); | |
13037 | ||
13038 | if (ret < 0) | |
054518dd | 13039 | return ret; |
27c329ed ML |
13040 | } else |
13041 | to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq; | |
054518dd | 13042 | |
ad421372 | 13043 | intel_modeset_clear_plls(state); |
054518dd | 13044 | |
99d736a2 | 13045 | if (IS_HASWELL(dev)) |
ad421372 | 13046 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13047 | |
ad421372 | 13048 | return 0; |
c347a676 ACO |
13049 | } |
13050 | ||
76305b1a MR |
13051 | /* |
13052 | * Handle calculation of various watermark data at the end of the atomic check | |
13053 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13054 | * handlers to ensure that all derived state has been updated. | |
13055 | */ | |
13056 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13057 | { | |
13058 | struct drm_device *dev = state->dev; | |
13059 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13060 | struct drm_crtc *crtc; | |
13061 | struct drm_crtc_state *cstate; | |
13062 | struct drm_plane *plane; | |
13063 | struct drm_plane_state *pstate; | |
13064 | ||
13065 | /* | |
13066 | * Calculate watermark configuration details now that derived | |
13067 | * plane/crtc state is all properly updated. | |
13068 | */ | |
13069 | drm_for_each_crtc(crtc, dev) { | |
13070 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13071 | crtc->state; | |
13072 | ||
13073 | if (cstate->active) | |
13074 | intel_state->wm_config.num_pipes_active++; | |
13075 | } | |
13076 | drm_for_each_legacy_plane(plane, dev) { | |
13077 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13078 | plane->state; | |
13079 | ||
13080 | if (!to_intel_plane_state(pstate)->visible) | |
13081 | continue; | |
13082 | ||
13083 | intel_state->wm_config.sprites_enabled = true; | |
13084 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13085 | pstate->crtc_h != pstate->src_h >> 16) | |
13086 | intel_state->wm_config.sprites_scaled = true; | |
13087 | } | |
13088 | } | |
13089 | ||
74c090b1 ML |
13090 | /** |
13091 | * intel_atomic_check - validate state object | |
13092 | * @dev: drm device | |
13093 | * @state: state to validate | |
13094 | */ | |
13095 | static int intel_atomic_check(struct drm_device *dev, | |
13096 | struct drm_atomic_state *state) | |
c347a676 | 13097 | { |
76305b1a | 13098 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13099 | struct drm_crtc *crtc; |
13100 | struct drm_crtc_state *crtc_state; | |
13101 | int ret, i; | |
61333b60 | 13102 | bool any_ms = false; |
c347a676 | 13103 | |
74c090b1 | 13104 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13105 | if (ret) |
13106 | return ret; | |
13107 | ||
c347a676 | 13108 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13109 | struct intel_crtc_state *pipe_config = |
13110 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13111 | |
13112 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13113 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13114 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13115 | |
61333b60 ML |
13116 | if (!crtc_state->enable) { |
13117 | if (needs_modeset(crtc_state)) | |
13118 | any_ms = true; | |
c347a676 | 13119 | continue; |
61333b60 | 13120 | } |
c347a676 | 13121 | |
26495481 | 13122 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13123 | continue; |
13124 | ||
26495481 DV |
13125 | /* FIXME: For only active_changed we shouldn't need to do any |
13126 | * state recomputation at all. */ | |
13127 | ||
1ed51de9 DV |
13128 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13129 | if (ret) | |
13130 | return ret; | |
b359283a | 13131 | |
cfb23ed6 | 13132 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13133 | if (ret) |
13134 | return ret; | |
13135 | ||
6764e9f8 | 13136 | if (intel_pipe_config_compare(state->dev, |
cfb23ed6 | 13137 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13138 | pipe_config, true)) { |
26495481 | 13139 | crtc_state->mode_changed = false; |
bfd16b2a | 13140 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13141 | } |
13142 | ||
13143 | if (needs_modeset(crtc_state)) { | |
13144 | any_ms = true; | |
cfb23ed6 ML |
13145 | |
13146 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13147 | if (ret) | |
13148 | return ret; | |
13149 | } | |
61333b60 | 13150 | |
26495481 DV |
13151 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13152 | needs_modeset(crtc_state) ? | |
13153 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13154 | } |
13155 | ||
61333b60 ML |
13156 | if (any_ms) { |
13157 | ret = intel_modeset_checks(state); | |
13158 | ||
13159 | if (ret) | |
13160 | return ret; | |
27c329ed | 13161 | } else |
76305b1a | 13162 | intel_state->cdclk = to_i915(state->dev)->cdclk_freq; |
c347a676 | 13163 | |
76305b1a MR |
13164 | ret = drm_atomic_helper_check_planes(state->dev, state); |
13165 | if (ret) | |
13166 | return ret; | |
13167 | ||
13168 | calc_watermark_data(state); | |
13169 | ||
13170 | return 0; | |
054518dd ACO |
13171 | } |
13172 | ||
74c090b1 ML |
13173 | /** |
13174 | * intel_atomic_commit - commit validated state object | |
13175 | * @dev: DRM device | |
13176 | * @state: the top-level driver state object | |
13177 | * @async: asynchronous commit | |
13178 | * | |
13179 | * This function commits a top-level state object that has been validated | |
13180 | * with drm_atomic_helper_check(). | |
13181 | * | |
13182 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13183 | * we can only handle plane-related operations and do not yet support | |
13184 | * asynchronous commit. | |
13185 | * | |
13186 | * RETURNS | |
13187 | * Zero for success or -errno. | |
13188 | */ | |
13189 | static int intel_atomic_commit(struct drm_device *dev, | |
13190 | struct drm_atomic_state *state, | |
13191 | bool async) | |
a6778b3c | 13192 | { |
fbee40df | 13193 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 ACO |
13194 | struct drm_crtc *crtc; |
13195 | struct drm_crtc_state *crtc_state; | |
c0c36b94 | 13196 | int ret = 0; |
0a9ab303 | 13197 | int i; |
61333b60 | 13198 | bool any_ms = false; |
a6778b3c | 13199 | |
74c090b1 ML |
13200 | if (async) { |
13201 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13202 | return -EINVAL; | |
13203 | } | |
13204 | ||
d4afb8cc ACO |
13205 | ret = drm_atomic_helper_prepare_planes(dev, state); |
13206 | if (ret) | |
13207 | return ret; | |
13208 | ||
1c5e19f8 | 13209 | drm_atomic_helper_swap_state(dev, state); |
76305b1a | 13210 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13211 | |
0a9ab303 | 13212 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13214 | ||
61333b60 ML |
13215 | if (!needs_modeset(crtc->state)) |
13216 | continue; | |
13217 | ||
13218 | any_ms = true; | |
a539205a | 13219 | intel_pre_plane_update(intel_crtc); |
460da916 | 13220 | |
a539205a ML |
13221 | if (crtc_state->active) { |
13222 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13223 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd ML |
13224 | intel_crtc->active = false; |
13225 | intel_disable_shared_dpll(intel_crtc); | |
a539205a | 13226 | } |
b8cecdf5 | 13227 | } |
7758a113 | 13228 | |
ea9d758d DV |
13229 | /* Only after disabling all output pipelines that will be changed can we |
13230 | * update the the output configuration. */ | |
4740b0f2 | 13231 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13232 | |
4740b0f2 ML |
13233 | if (any_ms) { |
13234 | intel_shared_dpll_commit(state); | |
13235 | ||
13236 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13237 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13238 | } |
47fab737 | 13239 | |
a6778b3c | 13240 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13241 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13242 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13243 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13244 | bool update_pipe = !modeset && |
13245 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13246 | unsigned long put_domains = 0; | |
f6ac4b2a ML |
13247 | |
13248 | if (modeset && crtc->state->active) { | |
a539205a ML |
13249 | update_scanline_offset(to_intel_crtc(crtc)); |
13250 | dev_priv->display.crtc_enable(crtc); | |
13251 | } | |
80715b2f | 13252 | |
bfd16b2a ML |
13253 | if (update_pipe) { |
13254 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13255 | ||
13256 | /* make sure intel_modeset_check_state runs */ | |
13257 | any_ms = true; | |
13258 | } | |
13259 | ||
f6ac4b2a ML |
13260 | if (!modeset) |
13261 | intel_pre_plane_update(intel_crtc); | |
13262 | ||
a539205a | 13263 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13264 | |
13265 | if (put_domains) | |
13266 | modeset_put_power_domains(dev_priv, put_domains); | |
13267 | ||
f6ac4b2a | 13268 | intel_post_plane_update(intel_crtc); |
80715b2f | 13269 | } |
a6778b3c | 13270 | |
a6778b3c | 13271 | /* FIXME: add subpixel order */ |
83a57153 | 13272 | |
74c090b1 | 13273 | drm_atomic_helper_wait_for_vblanks(dev, state); |
d4afb8cc | 13274 | drm_atomic_helper_cleanup_planes(dev, state); |
2bfb4627 | 13275 | |
74c090b1 | 13276 | if (any_ms) |
ee165b1a ML |
13277 | intel_modeset_check_state(dev, state); |
13278 | ||
13279 | drm_atomic_state_free(state); | |
f30da187 | 13280 | |
74c090b1 | 13281 | return 0; |
7f27126e JB |
13282 | } |
13283 | ||
c0c36b94 CW |
13284 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13285 | { | |
83a57153 ACO |
13286 | struct drm_device *dev = crtc->dev; |
13287 | struct drm_atomic_state *state; | |
e694eb02 | 13288 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13289 | int ret; |
83a57153 ACO |
13290 | |
13291 | state = drm_atomic_state_alloc(dev); | |
13292 | if (!state) { | |
e694eb02 | 13293 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13294 | crtc->base.id); |
13295 | return; | |
13296 | } | |
13297 | ||
e694eb02 | 13298 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13299 | |
e694eb02 ML |
13300 | retry: |
13301 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13302 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13303 | if (!ret) { | |
13304 | if (!crtc_state->active) | |
13305 | goto out; | |
83a57153 | 13306 | |
e694eb02 | 13307 | crtc_state->mode_changed = true; |
74c090b1 | 13308 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13309 | } |
13310 | ||
e694eb02 ML |
13311 | if (ret == -EDEADLK) { |
13312 | drm_atomic_state_clear(state); | |
13313 | drm_modeset_backoff(state->acquire_ctx); | |
13314 | goto retry; | |
4ed9fb37 | 13315 | } |
4be07317 | 13316 | |
2bfb4627 | 13317 | if (ret) |
e694eb02 | 13318 | out: |
2bfb4627 | 13319 | drm_atomic_state_free(state); |
c0c36b94 CW |
13320 | } |
13321 | ||
25c5b266 DV |
13322 | #undef for_each_intel_crtc_masked |
13323 | ||
f6e5b160 | 13324 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13325 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13326 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13327 | .destroy = intel_crtc_destroy, |
13328 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13329 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13330 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13331 | }; |
13332 | ||
5358901f DV |
13333 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13334 | struct intel_shared_dpll *pll, | |
13335 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13336 | { |
5358901f | 13337 | uint32_t val; |
ee7b9f93 | 13338 | |
f458ebbc | 13339 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13340 | return false; |
13341 | ||
5358901f | 13342 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13343 | hw_state->dpll = val; |
13344 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13345 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13346 | |
13347 | return val & DPLL_VCO_ENABLE; | |
13348 | } | |
13349 | ||
15bdd4cf DV |
13350 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13351 | struct intel_shared_dpll *pll) | |
13352 | { | |
3e369b76 ACO |
13353 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13354 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13355 | } |
13356 | ||
e7b903d2 DV |
13357 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13358 | struct intel_shared_dpll *pll) | |
13359 | { | |
e7b903d2 | 13360 | /* PCH refclock must be enabled first */ |
89eff4be | 13361 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13362 | |
3e369b76 | 13363 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13364 | |
13365 | /* Wait for the clocks to stabilize. */ | |
13366 | POSTING_READ(PCH_DPLL(pll->id)); | |
13367 | udelay(150); | |
13368 | ||
13369 | /* The pixel multiplier can only be updated once the | |
13370 | * DPLL is enabled and the clocks are stable. | |
13371 | * | |
13372 | * So write it again. | |
13373 | */ | |
3e369b76 | 13374 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13375 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13376 | udelay(200); |
13377 | } | |
13378 | ||
13379 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13380 | struct intel_shared_dpll *pll) | |
13381 | { | |
13382 | struct drm_device *dev = dev_priv->dev; | |
13383 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13384 | |
13385 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13386 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13387 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13388 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13389 | } |
13390 | ||
15bdd4cf DV |
13391 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13392 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13393 | udelay(200); |
13394 | } | |
13395 | ||
46edb027 DV |
13396 | static char *ibx_pch_dpll_names[] = { |
13397 | "PCH DPLL A", | |
13398 | "PCH DPLL B", | |
13399 | }; | |
13400 | ||
7c74ade1 | 13401 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13402 | { |
e7b903d2 | 13403 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13404 | int i; |
13405 | ||
7c74ade1 | 13406 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13407 | |
e72f9fbf | 13408 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13409 | dev_priv->shared_dplls[i].id = i; |
13410 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13411 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13412 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13413 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13414 | dev_priv->shared_dplls[i].get_hw_state = |
13415 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13416 | } |
13417 | } | |
13418 | ||
7c74ade1 DV |
13419 | static void intel_shared_dpll_init(struct drm_device *dev) |
13420 | { | |
e7b903d2 | 13421 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13422 | |
9cd86933 DV |
13423 | if (HAS_DDI(dev)) |
13424 | intel_ddi_pll_init(dev); | |
13425 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13426 | ibx_pch_dpll_init(dev); |
13427 | else | |
13428 | dev_priv->num_shared_dpll = 0; | |
13429 | ||
13430 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13431 | } |
13432 | ||
6beb8c23 MR |
13433 | /** |
13434 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13435 | * @plane: drm plane to prepare for | |
13436 | * @fb: framebuffer to prepare for presentation | |
13437 | * | |
13438 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13439 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13440 | * bits. Some older platforms need special physical address handling for | |
13441 | * cursor planes. | |
13442 | * | |
13443 | * Returns 0 on success, negative error code on failure. | |
13444 | */ | |
13445 | int | |
13446 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13447 | const struct drm_plane_state *new_state) |
465c120c MR |
13448 | { |
13449 | struct drm_device *dev = plane->dev; | |
844f9111 | 13450 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13451 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 MR |
13452 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
13453 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
6beb8c23 | 13454 | int ret = 0; |
465c120c | 13455 | |
ea2c67bb | 13456 | if (!obj) |
465c120c MR |
13457 | return 0; |
13458 | ||
6beb8c23 | 13459 | mutex_lock(&dev->struct_mutex); |
465c120c | 13460 | |
6beb8c23 MR |
13461 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13462 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13463 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13464 | ret = i915_gem_object_attach_phys(obj, align); | |
13465 | if (ret) | |
13466 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13467 | } else { | |
91af127f | 13468 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL); |
6beb8c23 | 13469 | } |
465c120c | 13470 | |
6beb8c23 | 13471 | if (ret == 0) |
a9ff8714 | 13472 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
fdd508a6 | 13473 | |
4c34574f | 13474 | mutex_unlock(&dev->struct_mutex); |
465c120c | 13475 | |
6beb8c23 MR |
13476 | return ret; |
13477 | } | |
13478 | ||
38f3ce3a MR |
13479 | /** |
13480 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13481 | * @plane: drm plane to clean up for | |
13482 | * @fb: old framebuffer that was on plane | |
13483 | * | |
13484 | * Cleans up a framebuffer that has just been removed from a plane. | |
13485 | */ | |
13486 | void | |
13487 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13488 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13489 | { |
13490 | struct drm_device *dev = plane->dev; | |
844f9111 | 13491 | struct drm_i915_gem_object *obj = intel_fb_obj(old_state->fb); |
38f3ce3a | 13492 | |
844f9111 | 13493 | if (!obj) |
38f3ce3a MR |
13494 | return; |
13495 | ||
13496 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13497 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
13498 | mutex_lock(&dev->struct_mutex); | |
844f9111 | 13499 | intel_unpin_fb_obj(old_state->fb, old_state); |
38f3ce3a MR |
13500 | mutex_unlock(&dev->struct_mutex); |
13501 | } | |
465c120c MR |
13502 | } |
13503 | ||
6156a456 CK |
13504 | int |
13505 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13506 | { | |
13507 | int max_scale; | |
13508 | struct drm_device *dev; | |
13509 | struct drm_i915_private *dev_priv; | |
13510 | int crtc_clock, cdclk; | |
13511 | ||
13512 | if (!intel_crtc || !crtc_state) | |
13513 | return DRM_PLANE_HELPER_NO_SCALING; | |
13514 | ||
13515 | dev = intel_crtc->base.dev; | |
13516 | dev_priv = dev->dev_private; | |
13517 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13518 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 CK |
13519 | |
13520 | if (!crtc_clock || !cdclk) | |
13521 | return DRM_PLANE_HELPER_NO_SCALING; | |
13522 | ||
13523 | /* | |
13524 | * skl max scale is lower of: | |
13525 | * close to 3 but not 3, -1 is for that purpose | |
13526 | * or | |
13527 | * cdclk/crtc_clock | |
13528 | */ | |
13529 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13530 | ||
13531 | return max_scale; | |
13532 | } | |
13533 | ||
465c120c | 13534 | static int |
3c692a41 | 13535 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13536 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13537 | struct intel_plane_state *state) |
13538 | { | |
2b875c22 MR |
13539 | struct drm_crtc *crtc = state->base.crtc; |
13540 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13541 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13542 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13543 | bool can_position = false; | |
465c120c | 13544 | |
061e4b8d ML |
13545 | /* use scaler when colorkey is not required */ |
13546 | if (INTEL_INFO(plane->dev)->gen >= 9 && | |
818ed961 | 13547 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
061e4b8d ML |
13548 | min_scale = 1; |
13549 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
d8106366 | 13550 | can_position = true; |
6156a456 | 13551 | } |
d8106366 | 13552 | |
061e4b8d ML |
13553 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13554 | &state->dst, &state->clip, | |
da20eabd ML |
13555 | min_scale, max_scale, |
13556 | can_position, true, | |
13557 | &state->visible); | |
14af293f GP |
13558 | } |
13559 | ||
13560 | static void | |
13561 | intel_commit_primary_plane(struct drm_plane *plane, | |
13562 | struct intel_plane_state *state) | |
13563 | { | |
2b875c22 MR |
13564 | struct drm_crtc *crtc = state->base.crtc; |
13565 | struct drm_framebuffer *fb = state->base.fb; | |
13566 | struct drm_device *dev = plane->dev; | |
14af293f | 13567 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13568 | struct intel_crtc *intel_crtc; |
14af293f GP |
13569 | struct drm_rect *src = &state->src; |
13570 | ||
ea2c67bb MR |
13571 | crtc = crtc ? crtc : plane->crtc; |
13572 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13573 | |
13574 | plane->fb = fb; | |
9dc806fc MR |
13575 | crtc->x = src->x1 >> 16; |
13576 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13577 | |
a539205a | 13578 | if (!crtc->state->active) |
302d19ac | 13579 | return; |
465c120c | 13580 | |
d4b08630 ML |
13581 | dev_priv->display.update_primary_plane(crtc, fb, |
13582 | state->src.x1 >> 16, | |
13583 | state->src.y1 >> 16); | |
465c120c MR |
13584 | } |
13585 | ||
a8ad0d8e ML |
13586 | static void |
13587 | intel_disable_primary_plane(struct drm_plane *plane, | |
7fabf5ef | 13588 | struct drm_crtc *crtc) |
a8ad0d8e ML |
13589 | { |
13590 | struct drm_device *dev = plane->dev; | |
13591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13592 | ||
a8ad0d8e ML |
13593 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13594 | } | |
13595 | ||
613d2b27 ML |
13596 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13597 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13598 | { |
32b7eeec | 13599 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13600 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13601 | struct intel_crtc_state *old_intel_state = |
13602 | to_intel_crtc_state(old_crtc_state); | |
13603 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13604 | |
f015c551 | 13605 | if (intel_crtc->atomic.update_wm_pre) |
32b7eeec | 13606 | intel_update_watermarks(crtc); |
3c692a41 | 13607 | |
c34c9ee4 | 13608 | /* Perform vblank evasion around commit operation */ |
a539205a | 13609 | if (crtc->state->active) |
34e0adbb | 13610 | intel_pipe_update_start(intel_crtc); |
0583236e | 13611 | |
bfd16b2a ML |
13612 | if (modeset) |
13613 | return; | |
13614 | ||
13615 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13616 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13617 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13618 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13619 | } |
13620 | ||
613d2b27 ML |
13621 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13622 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13623 | { |
32b7eeec | 13624 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13625 | |
8f539a83 | 13626 | if (crtc->state->active) |
34e0adbb | 13627 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13628 | } |
13629 | ||
cf4c7c12 | 13630 | /** |
4a3b8769 MR |
13631 | * intel_plane_destroy - destroy a plane |
13632 | * @plane: plane to destroy | |
cf4c7c12 | 13633 | * |
4a3b8769 MR |
13634 | * Common destruction function for all types of planes (primary, cursor, |
13635 | * sprite). | |
cf4c7c12 | 13636 | */ |
4a3b8769 | 13637 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13638 | { |
13639 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13640 | drm_plane_cleanup(plane); | |
13641 | kfree(intel_plane); | |
13642 | } | |
13643 | ||
65a3fea0 | 13644 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13645 | .update_plane = drm_atomic_helper_update_plane, |
13646 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13647 | .destroy = intel_plane_destroy, |
c196e1d6 | 13648 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13649 | .atomic_get_property = intel_plane_atomic_get_property, |
13650 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13651 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13652 | .atomic_destroy_state = intel_plane_destroy_state, | |
13653 | ||
465c120c MR |
13654 | }; |
13655 | ||
13656 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13657 | int pipe) | |
13658 | { | |
13659 | struct intel_plane *primary; | |
8e7d688b | 13660 | struct intel_plane_state *state; |
465c120c | 13661 | const uint32_t *intel_primary_formats; |
45e3743a | 13662 | unsigned int num_formats; |
465c120c MR |
13663 | |
13664 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13665 | if (primary == NULL) | |
13666 | return NULL; | |
13667 | ||
8e7d688b MR |
13668 | state = intel_create_plane_state(&primary->base); |
13669 | if (!state) { | |
ea2c67bb MR |
13670 | kfree(primary); |
13671 | return NULL; | |
13672 | } | |
8e7d688b | 13673 | primary->base.state = &state->base; |
ea2c67bb | 13674 | |
465c120c MR |
13675 | primary->can_scale = false; |
13676 | primary->max_downscale = 1; | |
6156a456 CK |
13677 | if (INTEL_INFO(dev)->gen >= 9) { |
13678 | primary->can_scale = true; | |
af99ceda | 13679 | state->scaler_id = -1; |
6156a456 | 13680 | } |
465c120c MR |
13681 | primary->pipe = pipe; |
13682 | primary->plane = pipe; | |
a9ff8714 | 13683 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 MR |
13684 | primary->check_plane = intel_check_primary_plane; |
13685 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13686 | primary->disable_plane = intel_disable_primary_plane; |
465c120c MR |
13687 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13688 | primary->plane = !pipe; | |
13689 | ||
6c0fd451 DL |
13690 | if (INTEL_INFO(dev)->gen >= 9) { |
13691 | intel_primary_formats = skl_primary_formats; | |
13692 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13693 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
13694 | intel_primary_formats = i965_primary_formats; |
13695 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
13696 | } else { |
13697 | intel_primary_formats = i8xx_primary_formats; | |
13698 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
13699 | } |
13700 | ||
13701 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13702 | &intel_plane_funcs, |
465c120c MR |
13703 | intel_primary_formats, num_formats, |
13704 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13705 | |
3b7a5119 SJ |
13706 | if (INTEL_INFO(dev)->gen >= 4) |
13707 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13708 | |
ea2c67bb MR |
13709 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13710 | ||
465c120c MR |
13711 | return &primary->base; |
13712 | } | |
13713 | ||
3b7a5119 SJ |
13714 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13715 | { | |
13716 | if (!dev->mode_config.rotation_property) { | |
13717 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13718 | BIT(DRM_ROTATE_180); | |
13719 | ||
13720 | if (INTEL_INFO(dev)->gen >= 9) | |
13721 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13722 | ||
13723 | dev->mode_config.rotation_property = | |
13724 | drm_mode_create_rotation_property(dev, flags); | |
13725 | } | |
13726 | if (dev->mode_config.rotation_property) | |
13727 | drm_object_attach_property(&plane->base.base, | |
13728 | dev->mode_config.rotation_property, | |
13729 | plane->base.state->rotation); | |
13730 | } | |
13731 | ||
3d7d6510 | 13732 | static int |
852e787c | 13733 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13734 | struct intel_crtc_state *crtc_state, |
852e787c | 13735 | struct intel_plane_state *state) |
3d7d6510 | 13736 | { |
061e4b8d | 13737 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 13738 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13739 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
757f9a3e GP |
13740 | unsigned stride; |
13741 | int ret; | |
3d7d6510 | 13742 | |
061e4b8d ML |
13743 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13744 | &state->dst, &state->clip, | |
3d7d6510 MR |
13745 | DRM_PLANE_HELPER_NO_SCALING, |
13746 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13747 | true, true, &state->visible); |
757f9a3e GP |
13748 | if (ret) |
13749 | return ret; | |
13750 | ||
757f9a3e GP |
13751 | /* if we want to turn off the cursor ignore width and height */ |
13752 | if (!obj) | |
da20eabd | 13753 | return 0; |
757f9a3e | 13754 | |
757f9a3e | 13755 | /* Check for which cursor types we support */ |
061e4b8d | 13756 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
13757 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
13758 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13759 | return -EINVAL; |
13760 | } | |
13761 | ||
ea2c67bb MR |
13762 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13763 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13764 | DRM_DEBUG_KMS("buffer is too small\n"); |
13765 | return -ENOMEM; | |
13766 | } | |
13767 | ||
3a656b54 | 13768 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 13769 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 13770 | return -EINVAL; |
32b7eeec MR |
13771 | } |
13772 | ||
da20eabd | 13773 | return 0; |
852e787c | 13774 | } |
3d7d6510 | 13775 | |
a8ad0d8e ML |
13776 | static void |
13777 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 13778 | struct drm_crtc *crtc) |
a8ad0d8e | 13779 | { |
a8ad0d8e ML |
13780 | intel_crtc_update_cursor(crtc, false); |
13781 | } | |
13782 | ||
f4a2cf29 | 13783 | static void |
852e787c GP |
13784 | intel_commit_cursor_plane(struct drm_plane *plane, |
13785 | struct intel_plane_state *state) | |
13786 | { | |
2b875c22 | 13787 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13788 | struct drm_device *dev = plane->dev; |
13789 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13790 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13791 | uint32_t addr; |
852e787c | 13792 | |
ea2c67bb MR |
13793 | crtc = crtc ? crtc : plane->crtc; |
13794 | intel_crtc = to_intel_crtc(crtc); | |
13795 | ||
a912f12f GP |
13796 | if (intel_crtc->cursor_bo == obj) |
13797 | goto update; | |
4ed91096 | 13798 | |
f4a2cf29 | 13799 | if (!obj) |
a912f12f | 13800 | addr = 0; |
f4a2cf29 | 13801 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13802 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13803 | else |
a912f12f | 13804 | addr = obj->phys_handle->busaddr; |
852e787c | 13805 | |
a912f12f GP |
13806 | intel_crtc->cursor_addr = addr; |
13807 | intel_crtc->cursor_bo = obj; | |
852e787c | 13808 | |
302d19ac | 13809 | update: |
a539205a | 13810 | if (crtc->state->active) |
a912f12f | 13811 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13812 | } |
13813 | ||
3d7d6510 MR |
13814 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13815 | int pipe) | |
13816 | { | |
13817 | struct intel_plane *cursor; | |
8e7d688b | 13818 | struct intel_plane_state *state; |
3d7d6510 MR |
13819 | |
13820 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13821 | if (cursor == NULL) | |
13822 | return NULL; | |
13823 | ||
8e7d688b MR |
13824 | state = intel_create_plane_state(&cursor->base); |
13825 | if (!state) { | |
ea2c67bb MR |
13826 | kfree(cursor); |
13827 | return NULL; | |
13828 | } | |
8e7d688b | 13829 | cursor->base.state = &state->base; |
ea2c67bb | 13830 | |
3d7d6510 MR |
13831 | cursor->can_scale = false; |
13832 | cursor->max_downscale = 1; | |
13833 | cursor->pipe = pipe; | |
13834 | cursor->plane = pipe; | |
a9ff8714 | 13835 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 MR |
13836 | cursor->check_plane = intel_check_cursor_plane; |
13837 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 13838 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
13839 | |
13840 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13841 | &intel_plane_funcs, |
3d7d6510 MR |
13842 | intel_cursor_formats, |
13843 | ARRAY_SIZE(intel_cursor_formats), | |
13844 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13845 | |
13846 | if (INTEL_INFO(dev)->gen >= 4) { | |
13847 | if (!dev->mode_config.rotation_property) | |
13848 | dev->mode_config.rotation_property = | |
13849 | drm_mode_create_rotation_property(dev, | |
13850 | BIT(DRM_ROTATE_0) | | |
13851 | BIT(DRM_ROTATE_180)); | |
13852 | if (dev->mode_config.rotation_property) | |
13853 | drm_object_attach_property(&cursor->base.base, | |
13854 | dev->mode_config.rotation_property, | |
8e7d688b | 13855 | state->base.rotation); |
4398ad45 VS |
13856 | } |
13857 | ||
af99ceda CK |
13858 | if (INTEL_INFO(dev)->gen >=9) |
13859 | state->scaler_id = -1; | |
13860 | ||
ea2c67bb MR |
13861 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13862 | ||
3d7d6510 MR |
13863 | return &cursor->base; |
13864 | } | |
13865 | ||
549e2bfb CK |
13866 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13867 | struct intel_crtc_state *crtc_state) | |
13868 | { | |
13869 | int i; | |
13870 | struct intel_scaler *intel_scaler; | |
13871 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13872 | ||
13873 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13874 | intel_scaler = &scaler_state->scalers[i]; | |
13875 | intel_scaler->in_use = 0; | |
549e2bfb CK |
13876 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
13877 | } | |
13878 | ||
13879 | scaler_state->scaler_id = -1; | |
13880 | } | |
13881 | ||
b358d0a6 | 13882 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13883 | { |
fbee40df | 13884 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13885 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13886 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13887 | struct drm_plane *primary = NULL; |
13888 | struct drm_plane *cursor = NULL; | |
465c120c | 13889 | int i, ret; |
79e53945 | 13890 | |
955382f3 | 13891 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13892 | if (intel_crtc == NULL) |
13893 | return; | |
13894 | ||
f5de6e07 ACO |
13895 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13896 | if (!crtc_state) | |
13897 | goto fail; | |
550acefd ACO |
13898 | intel_crtc->config = crtc_state; |
13899 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13900 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13901 | |
549e2bfb CK |
13902 | /* initialize shared scalers */ |
13903 | if (INTEL_INFO(dev)->gen >= 9) { | |
13904 | if (pipe == PIPE_C) | |
13905 | intel_crtc->num_scalers = 1; | |
13906 | else | |
13907 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13908 | ||
13909 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13910 | } | |
13911 | ||
465c120c | 13912 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13913 | if (!primary) |
13914 | goto fail; | |
13915 | ||
13916 | cursor = intel_cursor_plane_create(dev, pipe); | |
13917 | if (!cursor) | |
13918 | goto fail; | |
13919 | ||
465c120c | 13920 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13921 | cursor, &intel_crtc_funcs); |
13922 | if (ret) | |
13923 | goto fail; | |
79e53945 JB |
13924 | |
13925 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13926 | for (i = 0; i < 256; i++) { |
13927 | intel_crtc->lut_r[i] = i; | |
13928 | intel_crtc->lut_g[i] = i; | |
13929 | intel_crtc->lut_b[i] = i; | |
13930 | } | |
13931 | ||
1f1c2e24 VS |
13932 | /* |
13933 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13934 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13935 | */ |
80824003 JB |
13936 | intel_crtc->pipe = pipe; |
13937 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13938 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13939 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13940 | intel_crtc->plane = !pipe; |
80824003 JB |
13941 | } |
13942 | ||
4b0e333e CW |
13943 | intel_crtc->cursor_base = ~0; |
13944 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13945 | intel_crtc->cursor_size = ~0; |
8d7849db | 13946 | |
852eb00d VS |
13947 | intel_crtc->wm.cxsr_allowed = true; |
13948 | ||
22fd0fab JB |
13949 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13950 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13951 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13952 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13953 | ||
79e53945 | 13954 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13955 | |
13956 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13957 | return; |
13958 | ||
13959 | fail: | |
13960 | if (primary) | |
13961 | drm_plane_cleanup(primary); | |
13962 | if (cursor) | |
13963 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13964 | kfree(crtc_state); |
3d7d6510 | 13965 | kfree(intel_crtc); |
79e53945 JB |
13966 | } |
13967 | ||
752aa88a JB |
13968 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13969 | { | |
13970 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13971 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13972 | |
51fd371b | 13973 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13974 | |
d3babd3f | 13975 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13976 | return INVALID_PIPE; |
13977 | ||
13978 | return to_intel_crtc(encoder->crtc)->pipe; | |
13979 | } | |
13980 | ||
08d7b3d1 | 13981 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13982 | struct drm_file *file) |
08d7b3d1 | 13983 | { |
08d7b3d1 | 13984 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13985 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13986 | struct intel_crtc *crtc; |
08d7b3d1 | 13987 | |
7707e653 | 13988 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13989 | |
7707e653 | 13990 | if (!drmmode_crtc) { |
08d7b3d1 | 13991 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13992 | return -ENOENT; |
08d7b3d1 CW |
13993 | } |
13994 | ||
7707e653 | 13995 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13996 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13997 | |
c05422d5 | 13998 | return 0; |
08d7b3d1 CW |
13999 | } |
14000 | ||
66a9278e | 14001 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14002 | { |
66a9278e DV |
14003 | struct drm_device *dev = encoder->base.dev; |
14004 | struct intel_encoder *source_encoder; | |
79e53945 | 14005 | int index_mask = 0; |
79e53945 JB |
14006 | int entry = 0; |
14007 | ||
b2784e15 | 14008 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14009 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14010 | index_mask |= (1 << entry); |
14011 | ||
79e53945 JB |
14012 | entry++; |
14013 | } | |
4ef69c7a | 14014 | |
79e53945 JB |
14015 | return index_mask; |
14016 | } | |
14017 | ||
4d302442 CW |
14018 | static bool has_edp_a(struct drm_device *dev) |
14019 | { | |
14020 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14021 | ||
14022 | if (!IS_MOBILE(dev)) | |
14023 | return false; | |
14024 | ||
14025 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14026 | return false; | |
14027 | ||
e3589908 | 14028 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14029 | return false; |
14030 | ||
14031 | return true; | |
14032 | } | |
14033 | ||
84b4e042 JB |
14034 | static bool intel_crt_present(struct drm_device *dev) |
14035 | { | |
14036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14037 | ||
884497ed DL |
14038 | if (INTEL_INFO(dev)->gen >= 9) |
14039 | return false; | |
14040 | ||
cf404ce4 | 14041 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14042 | return false; |
14043 | ||
14044 | if (IS_CHERRYVIEW(dev)) | |
14045 | return false; | |
14046 | ||
14047 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
14048 | return false; | |
14049 | ||
14050 | return true; | |
14051 | } | |
14052 | ||
79e53945 JB |
14053 | static void intel_setup_outputs(struct drm_device *dev) |
14054 | { | |
725e30ad | 14055 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14056 | struct intel_encoder *encoder; |
cb0953d7 | 14057 | bool dpd_is_edp = false; |
79e53945 | 14058 | |
c9093354 | 14059 | intel_lvds_init(dev); |
79e53945 | 14060 | |
84b4e042 | 14061 | if (intel_crt_present(dev)) |
79935fca | 14062 | intel_crt_init(dev); |
cb0953d7 | 14063 | |
c776eb2e VK |
14064 | if (IS_BROXTON(dev)) { |
14065 | /* | |
14066 | * FIXME: Broxton doesn't support port detection via the | |
14067 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14068 | * detect the ports. | |
14069 | */ | |
14070 | intel_ddi_init(dev, PORT_A); | |
14071 | intel_ddi_init(dev, PORT_B); | |
14072 | intel_ddi_init(dev, PORT_C); | |
14073 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14074 | int found; |
14075 | ||
de31facd JB |
14076 | /* |
14077 | * Haswell uses DDI functions to detect digital outputs. | |
14078 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14079 | * it's there. | |
14080 | */ | |
77179400 | 14081 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14082 | /* WaIgnoreDDIAStrap: skl */ |
5a2376d1 | 14083 | if (found || IS_SKYLAKE(dev)) |
0e72a5b5 ED |
14084 | intel_ddi_init(dev, PORT_A); |
14085 | ||
14086 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14087 | * register */ | |
14088 | found = I915_READ(SFUSE_STRAP); | |
14089 | ||
14090 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14091 | intel_ddi_init(dev, PORT_B); | |
14092 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14093 | intel_ddi_init(dev, PORT_C); | |
14094 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14095 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14096 | /* |
14097 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14098 | */ | |
14099 | if (IS_SKYLAKE(dev) && | |
14100 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || | |
14101 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14102 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14103 | intel_ddi_init(dev, PORT_E); | |
14104 | ||
0e72a5b5 | 14105 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14106 | int found; |
5d8a7752 | 14107 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14108 | |
14109 | if (has_edp_a(dev)) | |
14110 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14111 | |
dc0fa718 | 14112 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14113 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 14114 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 14115 | if (!found) |
e2debe91 | 14116 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14117 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14118 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14119 | } |
14120 | ||
dc0fa718 | 14121 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14122 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14123 | |
dc0fa718 | 14124 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14125 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14126 | |
5eb08b69 | 14127 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14128 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14129 | |
270b3042 | 14130 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14131 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 14132 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
14133 | /* |
14134 | * The DP_DETECTED bit is the latched state of the DDC | |
14135 | * SDA pin at boot. However since eDP doesn't require DDC | |
14136 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14137 | * eDP ports may have been muxed to an alternate function. | |
14138 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14139 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14140 | * detect eDP ports. | |
14141 | */ | |
e66eb81d | 14142 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14143 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14144 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14145 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14146 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14147 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14148 | |
e66eb81d | 14149 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14150 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14151 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14152 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14153 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14154 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14155 | |
9418c1f1 | 14156 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14157 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14158 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14159 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14160 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14161 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14162 | } |
14163 | ||
3cfca973 | 14164 | intel_dsi_init(dev); |
09da55dc | 14165 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14166 | bool found = false; |
7d57382e | 14167 | |
e2debe91 | 14168 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14169 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 14170 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
3fec3d2f | 14171 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14172 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14173 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14174 | } |
27185ae1 | 14175 | |
3fec3d2f | 14176 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14177 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14178 | } |
13520b05 KH |
14179 | |
14180 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14181 | |
e2debe91 | 14182 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14183 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 14184 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 14185 | } |
27185ae1 | 14186 | |
e2debe91 | 14187 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14188 | |
3fec3d2f | 14189 | if (IS_G4X(dev)) { |
b01f2c3a | 14190 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14191 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14192 | } |
3fec3d2f | 14193 | if (IS_G4X(dev)) |
ab9d7c30 | 14194 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14195 | } |
27185ae1 | 14196 | |
3fec3d2f | 14197 | if (IS_G4X(dev) && |
e7281eab | 14198 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14199 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14200 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14201 | intel_dvo_init(dev); |
14202 | ||
103a196f | 14203 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14204 | intel_tv_init(dev); |
14205 | ||
0bc12bcb | 14206 | intel_psr_init(dev); |
7c8f8a70 | 14207 | |
b2784e15 | 14208 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14209 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14210 | encoder->base.possible_clones = | |
66a9278e | 14211 | intel_encoder_clones(encoder); |
79e53945 | 14212 | } |
47356eb6 | 14213 | |
dde86e2d | 14214 | intel_init_pch_refclk(dev); |
270b3042 DV |
14215 | |
14216 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14217 | } |
14218 | ||
14219 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14220 | { | |
60a5ca01 | 14221 | struct drm_device *dev = fb->dev; |
79e53945 | 14222 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14223 | |
ef2d633e | 14224 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14225 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14226 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14227 | drm_gem_object_unreference(&intel_fb->obj->base); |
14228 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14229 | kfree(intel_fb); |
14230 | } | |
14231 | ||
14232 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14233 | struct drm_file *file, |
79e53945 JB |
14234 | unsigned int *handle) |
14235 | { | |
14236 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14237 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14238 | |
05394f39 | 14239 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14240 | } |
14241 | ||
86c98588 RV |
14242 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14243 | struct drm_file *file, | |
14244 | unsigned flags, unsigned color, | |
14245 | struct drm_clip_rect *clips, | |
14246 | unsigned num_clips) | |
14247 | { | |
14248 | struct drm_device *dev = fb->dev; | |
14249 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14250 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14251 | ||
14252 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14253 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14254 | mutex_unlock(&dev->struct_mutex); |
14255 | ||
14256 | return 0; | |
14257 | } | |
14258 | ||
79e53945 JB |
14259 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14260 | .destroy = intel_user_framebuffer_destroy, | |
14261 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14262 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14263 | }; |
14264 | ||
b321803d DL |
14265 | static |
14266 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14267 | uint32_t pixel_format) | |
14268 | { | |
14269 | u32 gen = INTEL_INFO(dev)->gen; | |
14270 | ||
14271 | if (gen >= 9) { | |
14272 | /* "The stride in bytes must not exceed the of the size of 8K | |
14273 | * pixels and 32K bytes." | |
14274 | */ | |
14275 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
14276 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
14277 | return 32*1024; | |
14278 | } else if (gen >= 4) { | |
14279 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14280 | return 16*1024; | |
14281 | else | |
14282 | return 32*1024; | |
14283 | } else if (gen >= 3) { | |
14284 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14285 | return 8*1024; | |
14286 | else | |
14287 | return 16*1024; | |
14288 | } else { | |
14289 | /* XXX DSPC is limited to 4k tiled */ | |
14290 | return 8*1024; | |
14291 | } | |
14292 | } | |
14293 | ||
b5ea642a DV |
14294 | static int intel_framebuffer_init(struct drm_device *dev, |
14295 | struct intel_framebuffer *intel_fb, | |
14296 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14297 | struct drm_i915_gem_object *obj) | |
79e53945 | 14298 | { |
6761dd31 | 14299 | unsigned int aligned_height; |
79e53945 | 14300 | int ret; |
b321803d | 14301 | u32 pitch_limit, stride_alignment; |
79e53945 | 14302 | |
dd4916c5 DV |
14303 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14304 | ||
2a80eada DV |
14305 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14306 | /* Enforce that fb modifier and tiling mode match, but only for | |
14307 | * X-tiled. This is needed for FBC. */ | |
14308 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14309 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14310 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14311 | return -EINVAL; | |
14312 | } | |
14313 | } else { | |
14314 | if (obj->tiling_mode == I915_TILING_X) | |
14315 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14316 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14317 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14318 | return -EINVAL; | |
14319 | } | |
14320 | } | |
14321 | ||
9a8f0a12 TU |
14322 | /* Passed in modifier sanity checking. */ |
14323 | switch (mode_cmd->modifier[0]) { | |
14324 | case I915_FORMAT_MOD_Y_TILED: | |
14325 | case I915_FORMAT_MOD_Yf_TILED: | |
14326 | if (INTEL_INFO(dev)->gen < 9) { | |
14327 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14328 | mode_cmd->modifier[0]); | |
14329 | return -EINVAL; | |
14330 | } | |
14331 | case DRM_FORMAT_MOD_NONE: | |
14332 | case I915_FORMAT_MOD_X_TILED: | |
14333 | break; | |
14334 | default: | |
c0f40428 JB |
14335 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14336 | mode_cmd->modifier[0]); | |
57cd6508 | 14337 | return -EINVAL; |
c16ed4be | 14338 | } |
57cd6508 | 14339 | |
b321803d DL |
14340 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14341 | mode_cmd->pixel_format); | |
14342 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14343 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14344 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14345 | return -EINVAL; |
c16ed4be | 14346 | } |
57cd6508 | 14347 | |
b321803d DL |
14348 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14349 | mode_cmd->pixel_format); | |
a35cdaa0 | 14350 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14351 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14352 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14353 | "tiled" : "linear", |
a35cdaa0 | 14354 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14355 | return -EINVAL; |
c16ed4be | 14356 | } |
5d7bd705 | 14357 | |
2a80eada | 14358 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14359 | mode_cmd->pitches[0] != obj->stride) { |
14360 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14361 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14362 | return -EINVAL; |
c16ed4be | 14363 | } |
5d7bd705 | 14364 | |
57779d06 | 14365 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14366 | switch (mode_cmd->pixel_format) { |
57779d06 | 14367 | case DRM_FORMAT_C8: |
04b3924d VS |
14368 | case DRM_FORMAT_RGB565: |
14369 | case DRM_FORMAT_XRGB8888: | |
14370 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14371 | break; |
14372 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14373 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14374 | DRM_DEBUG("unsupported pixel format: %s\n", |
14375 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14376 | return -EINVAL; |
c16ed4be | 14377 | } |
57779d06 | 14378 | break; |
57779d06 | 14379 | case DRM_FORMAT_ABGR8888: |
6c0fd451 DL |
14380 | if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) { |
14381 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14382 | drm_get_format_name(mode_cmd->pixel_format)); | |
14383 | return -EINVAL; | |
14384 | } | |
14385 | break; | |
14386 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14387 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14388 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14389 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14390 | DRM_DEBUG("unsupported pixel format: %s\n", |
14391 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14392 | return -EINVAL; |
c16ed4be | 14393 | } |
b5626747 | 14394 | break; |
7531208b DL |
14395 | case DRM_FORMAT_ABGR2101010: |
14396 | if (!IS_VALLEYVIEW(dev)) { | |
14397 | DRM_DEBUG("unsupported pixel format: %s\n", | |
14398 | drm_get_format_name(mode_cmd->pixel_format)); | |
14399 | return -EINVAL; | |
14400 | } | |
14401 | break; | |
04b3924d VS |
14402 | case DRM_FORMAT_YUYV: |
14403 | case DRM_FORMAT_UYVY: | |
14404 | case DRM_FORMAT_YVYU: | |
14405 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14406 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14407 | DRM_DEBUG("unsupported pixel format: %s\n", |
14408 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14409 | return -EINVAL; |
c16ed4be | 14410 | } |
57cd6508 CW |
14411 | break; |
14412 | default: | |
4ee62c76 VS |
14413 | DRM_DEBUG("unsupported pixel format: %s\n", |
14414 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14415 | return -EINVAL; |
14416 | } | |
14417 | ||
90f9a336 VS |
14418 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14419 | if (mode_cmd->offsets[0] != 0) | |
14420 | return -EINVAL; | |
14421 | ||
ec2c981e | 14422 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14423 | mode_cmd->pixel_format, |
14424 | mode_cmd->modifier[0]); | |
53155c0a DV |
14425 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14426 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14427 | return -EINVAL; | |
14428 | ||
c7d73f6a DV |
14429 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14430 | intel_fb->obj = obj; | |
80075d49 | 14431 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14432 | |
79e53945 JB |
14433 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14434 | if (ret) { | |
14435 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14436 | return ret; | |
14437 | } | |
14438 | ||
79e53945 JB |
14439 | return 0; |
14440 | } | |
14441 | ||
79e53945 JB |
14442 | static struct drm_framebuffer * |
14443 | intel_user_framebuffer_create(struct drm_device *dev, | |
14444 | struct drm_file *filp, | |
308e5bcb | 14445 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14446 | { |
05394f39 | 14447 | struct drm_i915_gem_object *obj; |
79e53945 | 14448 | |
308e5bcb JB |
14449 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14450 | mode_cmd->handles[0])); | |
c8725226 | 14451 | if (&obj->base == NULL) |
cce13ff7 | 14452 | return ERR_PTR(-ENOENT); |
79e53945 | 14453 | |
d2dff872 | 14454 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14455 | } |
14456 | ||
0695726e | 14457 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14458 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14459 | { |
14460 | } | |
14461 | #endif | |
14462 | ||
79e53945 | 14463 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14464 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14465 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14466 | .atomic_check = intel_atomic_check, |
14467 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14468 | .atomic_state_alloc = intel_atomic_state_alloc, |
14469 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14470 | }; |
14471 | ||
e70236a8 JB |
14472 | /* Set up chip specific display functions */ |
14473 | static void intel_init_display(struct drm_device *dev) | |
14474 | { | |
14475 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14476 | ||
ee9300bb DV |
14477 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14478 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14479 | else if (IS_CHERRYVIEW(dev)) |
14480 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14481 | else if (IS_VALLEYVIEW(dev)) |
14482 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14483 | else if (IS_PINEVIEW(dev)) | |
14484 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14485 | else | |
14486 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14487 | ||
bc8d7dff DL |
14488 | if (INTEL_INFO(dev)->gen >= 9) { |
14489 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14490 | dev_priv->display.get_initial_plane_config = |
14491 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14492 | dev_priv->display.crtc_compute_clock = |
14493 | haswell_crtc_compute_clock; | |
14494 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14495 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14496 | dev_priv->display.update_primary_plane = |
14497 | skylake_update_primary_plane; | |
14498 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14499 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14500 | dev_priv->display.get_initial_plane_config = |
14501 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14502 | dev_priv->display.crtc_compute_clock = |
14503 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14504 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14505 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14506 | dev_priv->display.update_primary_plane = |
14507 | ironlake_update_primary_plane; | |
09b4ddf9 | 14508 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14509 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14510 | dev_priv->display.get_initial_plane_config = |
14511 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14512 | dev_priv->display.crtc_compute_clock = |
14513 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14514 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14515 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
262ca2b0 MR |
14516 | dev_priv->display.update_primary_plane = |
14517 | ironlake_update_primary_plane; | |
89b667f8 JB |
14518 | } else if (IS_VALLEYVIEW(dev)) { |
14519 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14520 | dev_priv->display.get_initial_plane_config = |
14521 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14522 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14523 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14524 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14525 | dev_priv->display.update_primary_plane = |
14526 | i9xx_update_primary_plane; | |
f564048e | 14527 | } else { |
0e8ffe1b | 14528 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14529 | dev_priv->display.get_initial_plane_config = |
14530 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14531 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14532 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14533 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14534 | dev_priv->display.update_primary_plane = |
14535 | i9xx_update_primary_plane; | |
f564048e | 14536 | } |
e70236a8 | 14537 | |
e70236a8 | 14538 | /* Returns the core display clock speed */ |
1652d19e VS |
14539 | if (IS_SKYLAKE(dev)) |
14540 | dev_priv->display.get_display_clock_speed = | |
14541 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14542 | else if (IS_BROXTON(dev)) |
14543 | dev_priv->display.get_display_clock_speed = | |
14544 | broxton_get_display_clock_speed; | |
1652d19e VS |
14545 | else if (IS_BROADWELL(dev)) |
14546 | dev_priv->display.get_display_clock_speed = | |
14547 | broadwell_get_display_clock_speed; | |
14548 | else if (IS_HASWELL(dev)) | |
14549 | dev_priv->display.get_display_clock_speed = | |
14550 | haswell_get_display_clock_speed; | |
14551 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14552 | dev_priv->display.get_display_clock_speed = |
14553 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14554 | else if (IS_GEN5(dev)) |
14555 | dev_priv->display.get_display_clock_speed = | |
14556 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14557 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14558 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14559 | dev_priv->display.get_display_clock_speed = |
14560 | i945_get_display_clock_speed; | |
34edce2f VS |
14561 | else if (IS_GM45(dev)) |
14562 | dev_priv->display.get_display_clock_speed = | |
14563 | gm45_get_display_clock_speed; | |
14564 | else if (IS_CRESTLINE(dev)) | |
14565 | dev_priv->display.get_display_clock_speed = | |
14566 | i965gm_get_display_clock_speed; | |
14567 | else if (IS_PINEVIEW(dev)) | |
14568 | dev_priv->display.get_display_clock_speed = | |
14569 | pnv_get_display_clock_speed; | |
14570 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14571 | dev_priv->display.get_display_clock_speed = | |
14572 | g33_get_display_clock_speed; | |
e70236a8 JB |
14573 | else if (IS_I915G(dev)) |
14574 | dev_priv->display.get_display_clock_speed = | |
14575 | i915_get_display_clock_speed; | |
257a7ffc | 14576 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14577 | dev_priv->display.get_display_clock_speed = |
14578 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14579 | else if (IS_PINEVIEW(dev)) |
14580 | dev_priv->display.get_display_clock_speed = | |
14581 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14582 | else if (IS_I915GM(dev)) |
14583 | dev_priv->display.get_display_clock_speed = | |
14584 | i915gm_get_display_clock_speed; | |
14585 | else if (IS_I865G(dev)) | |
14586 | dev_priv->display.get_display_clock_speed = | |
14587 | i865_get_display_clock_speed; | |
f0f8a9ce | 14588 | else if (IS_I85X(dev)) |
e70236a8 | 14589 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14590 | i85x_get_display_clock_speed; |
623e01e5 VS |
14591 | else { /* 830 */ |
14592 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14593 | dev_priv->display.get_display_clock_speed = |
14594 | i830_get_display_clock_speed; | |
623e01e5 | 14595 | } |
e70236a8 | 14596 | |
7c10a2b5 | 14597 | if (IS_GEN5(dev)) { |
3bb11b53 | 14598 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14599 | } else if (IS_GEN6(dev)) { |
14600 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14601 | } else if (IS_IVYBRIDGE(dev)) { |
14602 | /* FIXME: detect B0+ stepping and use auto training */ | |
14603 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14604 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14605 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
14606 | if (IS_BROADWELL(dev)) { |
14607 | dev_priv->display.modeset_commit_cdclk = | |
14608 | broadwell_modeset_commit_cdclk; | |
14609 | dev_priv->display.modeset_calc_cdclk = | |
14610 | broadwell_modeset_calc_cdclk; | |
14611 | } | |
30a970c6 | 14612 | } else if (IS_VALLEYVIEW(dev)) { |
27c329ed ML |
14613 | dev_priv->display.modeset_commit_cdclk = |
14614 | valleyview_modeset_commit_cdclk; | |
14615 | dev_priv->display.modeset_calc_cdclk = | |
14616 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 14617 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
14618 | dev_priv->display.modeset_commit_cdclk = |
14619 | broxton_modeset_commit_cdclk; | |
14620 | dev_priv->display.modeset_calc_cdclk = | |
14621 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14622 | } |
8c9f3aaf | 14623 | |
8c9f3aaf JB |
14624 | switch (INTEL_INFO(dev)->gen) { |
14625 | case 2: | |
14626 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14627 | break; | |
14628 | ||
14629 | case 3: | |
14630 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14631 | break; | |
14632 | ||
14633 | case 4: | |
14634 | case 5: | |
14635 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14636 | break; | |
14637 | ||
14638 | case 6: | |
14639 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14640 | break; | |
7c9017e5 | 14641 | case 7: |
4e0bbc31 | 14642 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14643 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14644 | break; | |
830c81db | 14645 | case 9: |
ba343e02 TU |
14646 | /* Drop through - unsupported since execlist only. */ |
14647 | default: | |
14648 | /* Default just returns -ENODEV to indicate unsupported */ | |
14649 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14650 | } |
7bd688cd | 14651 | |
e39b999a | 14652 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
14653 | } |
14654 | ||
b690e96c JB |
14655 | /* |
14656 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14657 | * resume, or other times. This quirk makes sure that's the case for | |
14658 | * affected systems. | |
14659 | */ | |
0206e353 | 14660 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14661 | { |
14662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14663 | ||
14664 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14665 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14666 | } |
14667 | ||
b6b5d049 VS |
14668 | static void quirk_pipeb_force(struct drm_device *dev) |
14669 | { | |
14670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14671 | ||
14672 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14673 | DRM_INFO("applying pipe b force quirk\n"); | |
14674 | } | |
14675 | ||
435793df KP |
14676 | /* |
14677 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14678 | */ | |
14679 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14680 | { | |
14681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14682 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14683 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14684 | } |
14685 | ||
4dca20ef | 14686 | /* |
5a15ab5b CE |
14687 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14688 | * brightness value | |
4dca20ef CE |
14689 | */ |
14690 | static void quirk_invert_brightness(struct drm_device *dev) | |
14691 | { | |
14692 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14693 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14694 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14695 | } |
14696 | ||
9c72cc6f SD |
14697 | /* Some VBT's incorrectly indicate no backlight is present */ |
14698 | static void quirk_backlight_present(struct drm_device *dev) | |
14699 | { | |
14700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14701 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14702 | DRM_INFO("applying backlight present quirk\n"); | |
14703 | } | |
14704 | ||
b690e96c JB |
14705 | struct intel_quirk { |
14706 | int device; | |
14707 | int subsystem_vendor; | |
14708 | int subsystem_device; | |
14709 | void (*hook)(struct drm_device *dev); | |
14710 | }; | |
14711 | ||
5f85f176 EE |
14712 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14713 | struct intel_dmi_quirk { | |
14714 | void (*hook)(struct drm_device *dev); | |
14715 | const struct dmi_system_id (*dmi_id_list)[]; | |
14716 | }; | |
14717 | ||
14718 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14719 | { | |
14720 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14721 | return 1; | |
14722 | } | |
14723 | ||
14724 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14725 | { | |
14726 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14727 | { | |
14728 | .callback = intel_dmi_reverse_brightness, | |
14729 | .ident = "NCR Corporation", | |
14730 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14731 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14732 | }, | |
14733 | }, | |
14734 | { } /* terminating entry */ | |
14735 | }, | |
14736 | .hook = quirk_invert_brightness, | |
14737 | }, | |
14738 | }; | |
14739 | ||
c43b5634 | 14740 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14741 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14742 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14743 | ||
b690e96c JB |
14744 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14745 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14746 | ||
5f080c0f VS |
14747 | /* 830 needs to leave pipe A & dpll A up */ |
14748 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14749 | ||
b6b5d049 VS |
14750 | /* 830 needs to leave pipe B & dpll B up */ |
14751 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14752 | ||
435793df KP |
14753 | /* Lenovo U160 cannot use SSC on LVDS */ |
14754 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14755 | |
14756 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14757 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14758 | |
be505f64 AH |
14759 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14760 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14761 | ||
14762 | /* Acer/eMachines G725 */ | |
14763 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14764 | ||
14765 | /* Acer/eMachines e725 */ | |
14766 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14767 | ||
14768 | /* Acer/Packard Bell NCL20 */ | |
14769 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14770 | ||
14771 | /* Acer Aspire 4736Z */ | |
14772 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14773 | |
14774 | /* Acer Aspire 5336 */ | |
14775 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14776 | |
14777 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14778 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14779 | |
dfb3d47b SD |
14780 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14781 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14782 | ||
b2a9601c | 14783 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14784 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14785 | ||
d4967d8c SD |
14786 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14787 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14788 | |
14789 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14790 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14791 | |
14792 | /* Dell Chromebook 11 */ | |
14793 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14794 | }; |
14795 | ||
14796 | static void intel_init_quirks(struct drm_device *dev) | |
14797 | { | |
14798 | struct pci_dev *d = dev->pdev; | |
14799 | int i; | |
14800 | ||
14801 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14802 | struct intel_quirk *q = &intel_quirks[i]; | |
14803 | ||
14804 | if (d->device == q->device && | |
14805 | (d->subsystem_vendor == q->subsystem_vendor || | |
14806 | q->subsystem_vendor == PCI_ANY_ID) && | |
14807 | (d->subsystem_device == q->subsystem_device || | |
14808 | q->subsystem_device == PCI_ANY_ID)) | |
14809 | q->hook(dev); | |
14810 | } | |
5f85f176 EE |
14811 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14812 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14813 | intel_dmi_quirks[i].hook(dev); | |
14814 | } | |
b690e96c JB |
14815 | } |
14816 | ||
9cce37f4 JB |
14817 | /* Disable the VGA plane that we never use */ |
14818 | static void i915_disable_vga(struct drm_device *dev) | |
14819 | { | |
14820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14821 | u8 sr1; | |
766aa1c4 | 14822 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14823 | |
2b37c616 | 14824 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14825 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14826 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14827 | sr1 = inb(VGA_SR_DATA); |
14828 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14829 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14830 | udelay(300); | |
14831 | ||
01f5a626 | 14832 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14833 | POSTING_READ(vga_reg); |
14834 | } | |
14835 | ||
f817586c DV |
14836 | void intel_modeset_init_hw(struct drm_device *dev) |
14837 | { | |
b6283055 | 14838 | intel_update_cdclk(dev); |
a8f78b58 | 14839 | intel_prepare_ddi(dev); |
f817586c | 14840 | intel_init_clock_gating(dev); |
8090c6b9 | 14841 | intel_enable_gt_powersave(dev); |
f817586c DV |
14842 | } |
14843 | ||
79e53945 JB |
14844 | void intel_modeset_init(struct drm_device *dev) |
14845 | { | |
652c393a | 14846 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14847 | int sprite, ret; |
8cc87b75 | 14848 | enum pipe pipe; |
46f297fb | 14849 | struct intel_crtc *crtc; |
79e53945 JB |
14850 | |
14851 | drm_mode_config_init(dev); | |
14852 | ||
14853 | dev->mode_config.min_width = 0; | |
14854 | dev->mode_config.min_height = 0; | |
14855 | ||
019d96cb DA |
14856 | dev->mode_config.preferred_depth = 24; |
14857 | dev->mode_config.prefer_shadow = 1; | |
14858 | ||
25bab385 TU |
14859 | dev->mode_config.allow_fb_modifiers = true; |
14860 | ||
e6ecefaa | 14861 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14862 | |
b690e96c JB |
14863 | intel_init_quirks(dev); |
14864 | ||
1fa61106 ED |
14865 | intel_init_pm(dev); |
14866 | ||
e3c74757 BW |
14867 | if (INTEL_INFO(dev)->num_pipes == 0) |
14868 | return; | |
14869 | ||
69f92f67 LW |
14870 | /* |
14871 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14872 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14873 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14874 | * indicates as much. | |
14875 | */ | |
14876 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
14877 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
14878 | DREF_SSC1_ENABLE); | |
14879 | ||
14880 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14881 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14882 | bios_lvds_use_ssc ? "en" : "dis", | |
14883 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14884 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14885 | } | |
14886 | } | |
14887 | ||
e70236a8 | 14888 | intel_init_display(dev); |
7c10a2b5 | 14889 | intel_init_audio(dev); |
e70236a8 | 14890 | |
a6c45cf0 CW |
14891 | if (IS_GEN2(dev)) { |
14892 | dev->mode_config.max_width = 2048; | |
14893 | dev->mode_config.max_height = 2048; | |
14894 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14895 | dev->mode_config.max_width = 4096; |
14896 | dev->mode_config.max_height = 4096; | |
79e53945 | 14897 | } else { |
a6c45cf0 CW |
14898 | dev->mode_config.max_width = 8192; |
14899 | dev->mode_config.max_height = 8192; | |
79e53945 | 14900 | } |
068be561 | 14901 | |
dc41c154 VS |
14902 | if (IS_845G(dev) || IS_I865G(dev)) { |
14903 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14904 | dev->mode_config.cursor_height = 1023; | |
14905 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14906 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14907 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14908 | } else { | |
14909 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14910 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14911 | } | |
14912 | ||
5d4545ae | 14913 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 14914 | |
28c97730 | 14915 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14916 | INTEL_INFO(dev)->num_pipes, |
14917 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14918 | |
055e393f | 14919 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14920 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14921 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14922 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14923 | if (ret) |
06da8da2 | 14924 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14925 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14926 | } |
79e53945 JB |
14927 | } |
14928 | ||
bfa7df01 VS |
14929 | intel_update_czclk(dev_priv); |
14930 | intel_update_cdclk(dev); | |
14931 | ||
e72f9fbf | 14932 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14933 | |
9cce37f4 JB |
14934 | /* Just disable it once at startup */ |
14935 | i915_disable_vga(dev); | |
79e53945 | 14936 | intel_setup_outputs(dev); |
11be49eb CW |
14937 | |
14938 | /* Just in case the BIOS is doing something questionable. */ | |
7733b49b | 14939 | intel_fbc_disable(dev_priv); |
fa9fa083 | 14940 | |
6e9f798d | 14941 | drm_modeset_lock_all(dev); |
043e9bda | 14942 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 14943 | drm_modeset_unlock_all(dev); |
46f297fb | 14944 | |
d3fcc808 | 14945 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14946 | struct intel_initial_plane_config plane_config = {}; |
14947 | ||
46f297fb JB |
14948 | if (!crtc->active) |
14949 | continue; | |
14950 | ||
46f297fb | 14951 | /* |
46f297fb JB |
14952 | * Note that reserving the BIOS fb up front prevents us |
14953 | * from stuffing other stolen allocations like the ring | |
14954 | * on top. This prevents some ugliness at boot time, and | |
14955 | * can even allow for smooth boot transitions if the BIOS | |
14956 | * fb is large enough for the active pipe configuration. | |
14957 | */ | |
eeebeac5 ML |
14958 | dev_priv->display.get_initial_plane_config(crtc, |
14959 | &plane_config); | |
14960 | ||
14961 | /* | |
14962 | * If the fb is shared between multiple heads, we'll | |
14963 | * just get the first one. | |
14964 | */ | |
14965 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 14966 | } |
2c7111db CW |
14967 | } |
14968 | ||
7fad798e DV |
14969 | static void intel_enable_pipe_a(struct drm_device *dev) |
14970 | { | |
14971 | struct intel_connector *connector; | |
14972 | struct drm_connector *crt = NULL; | |
14973 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14974 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14975 | |
14976 | /* We can't just switch on the pipe A, we need to set things up with a | |
14977 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14978 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14979 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14980 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14981 | crt = &connector->base; | |
14982 | break; | |
14983 | } | |
14984 | } | |
14985 | ||
14986 | if (!crt) | |
14987 | return; | |
14988 | ||
208bf9fd | 14989 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14990 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14991 | } |
14992 | ||
fa555837 DV |
14993 | static bool |
14994 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14995 | { | |
7eb552ae BW |
14996 | struct drm_device *dev = crtc->base.dev; |
14997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14998 | u32 reg, val; |
14999 | ||
7eb552ae | 15000 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15001 | return true; |
15002 | ||
15003 | reg = DSPCNTR(!crtc->plane); | |
15004 | val = I915_READ(reg); | |
15005 | ||
15006 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15007 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15008 | return false; | |
15009 | ||
15010 | return true; | |
15011 | } | |
15012 | ||
02e93c35 VS |
15013 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15014 | { | |
15015 | struct drm_device *dev = crtc->base.dev; | |
15016 | struct intel_encoder *encoder; | |
15017 | ||
15018 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15019 | return true; | |
15020 | ||
15021 | return false; | |
15022 | } | |
15023 | ||
24929352 DV |
15024 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15025 | { | |
15026 | struct drm_device *dev = crtc->base.dev; | |
15027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 15028 | u32 reg; |
24929352 | 15029 | |
24929352 | 15030 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 15031 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
15032 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15033 | ||
d3eaf884 | 15034 | /* restore vblank interrupts to correct state */ |
9625604c | 15035 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15036 | if (crtc->active) { |
f9cd7b88 VS |
15037 | struct intel_plane *plane; |
15038 | ||
9625604c | 15039 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15040 | |
15041 | /* Disable everything but the primary plane */ | |
15042 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15043 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15044 | continue; | |
15045 | ||
15046 | plane->disable_plane(&plane->base, &crtc->base); | |
15047 | } | |
9625604c | 15048 | } |
d3eaf884 | 15049 | |
24929352 | 15050 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15051 | * disable the crtc (and hence change the state) if it is wrong. Note |
15052 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15053 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15054 | bool plane; |
15055 | ||
24929352 DV |
15056 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15057 | crtc->base.base.id); | |
15058 | ||
15059 | /* Pipe has the wrong plane attached and the plane is active. | |
15060 | * Temporarily change the plane mapping and disable everything | |
15061 | * ... */ | |
15062 | plane = crtc->plane; | |
b70709a6 | 15063 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15064 | crtc->plane = !plane; |
b17d48e2 | 15065 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15066 | crtc->plane = plane; |
24929352 | 15067 | } |
24929352 | 15068 | |
7fad798e DV |
15069 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15070 | crtc->pipe == PIPE_A && !crtc->active) { | |
15071 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15072 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15073 | * call below we restore the pipe to the right state, but leave | |
15074 | * the required bits on. */ | |
15075 | intel_enable_pipe_a(dev); | |
15076 | } | |
15077 | ||
24929352 DV |
15078 | /* Adjust the state of the output pipe according to whether we |
15079 | * have active connectors/encoders. */ | |
02e93c35 | 15080 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15081 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15082 | |
53d9f4e9 | 15083 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15084 | struct intel_encoder *encoder; |
24929352 DV |
15085 | |
15086 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15087 | * functions or because of calls to intel_crtc_disable_noatomic, |
15088 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15089 | * pipe A quirk. */ |
15090 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15091 | crtc->base.base.id, | |
83d65738 | 15092 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15093 | crtc->active ? "enabled" : "disabled"); |
15094 | ||
4be40c98 | 15095 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15096 | crtc->base.state->active = crtc->active; |
24929352 DV |
15097 | crtc->base.enabled = crtc->active; |
15098 | ||
15099 | /* Because we only establish the connector -> encoder -> | |
15100 | * crtc links if something is active, this means the | |
15101 | * crtc is now deactivated. Break the links. connector | |
15102 | * -> encoder links are only establish when things are | |
15103 | * actually up, hence no need to break them. */ | |
15104 | WARN_ON(crtc->active); | |
15105 | ||
2d406bb0 | 15106 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15107 | encoder->base.crtc = NULL; |
24929352 | 15108 | } |
c5ab3bc0 | 15109 | |
a3ed6aad | 15110 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15111 | /* |
15112 | * We start out with underrun reporting disabled to avoid races. | |
15113 | * For correct bookkeeping mark this on active crtcs. | |
15114 | * | |
c5ab3bc0 DV |
15115 | * Also on gmch platforms we dont have any hardware bits to |
15116 | * disable the underrun reporting. Which means we need to start | |
15117 | * out with underrun reporting disabled also on inactive pipes, | |
15118 | * since otherwise we'll complain about the garbage we read when | |
15119 | * e.g. coming up after runtime pm. | |
15120 | * | |
4cc31489 DV |
15121 | * No protection against concurrent access is required - at |
15122 | * worst a fifo underrun happens which also sets this to false. | |
15123 | */ | |
15124 | crtc->cpu_fifo_underrun_disabled = true; | |
15125 | crtc->pch_fifo_underrun_disabled = true; | |
15126 | } | |
24929352 DV |
15127 | } |
15128 | ||
15129 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15130 | { | |
15131 | struct intel_connector *connector; | |
15132 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15133 | bool active = false; |
24929352 DV |
15134 | |
15135 | /* We need to check both for a crtc link (meaning that the | |
15136 | * encoder is active and trying to read from a pipe) and the | |
15137 | * pipe itself being active. */ | |
15138 | bool has_active_crtc = encoder->base.crtc && | |
15139 | to_intel_crtc(encoder->base.crtc)->active; | |
15140 | ||
873ffe69 ML |
15141 | for_each_intel_connector(dev, connector) { |
15142 | if (connector->base.encoder != &encoder->base) | |
15143 | continue; | |
15144 | ||
15145 | active = true; | |
15146 | break; | |
15147 | } | |
15148 | ||
15149 | if (active && !has_active_crtc) { | |
24929352 DV |
15150 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15151 | encoder->base.base.id, | |
8e329a03 | 15152 | encoder->base.name); |
24929352 DV |
15153 | |
15154 | /* Connector is active, but has no active pipe. This is | |
15155 | * fallout from our resume register restoring. Disable | |
15156 | * the encoder manually again. */ | |
15157 | if (encoder->base.crtc) { | |
15158 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15159 | encoder->base.base.id, | |
8e329a03 | 15160 | encoder->base.name); |
24929352 | 15161 | encoder->disable(encoder); |
a62d1497 VS |
15162 | if (encoder->post_disable) |
15163 | encoder->post_disable(encoder); | |
24929352 | 15164 | } |
7f1950fb | 15165 | encoder->base.crtc = NULL; |
24929352 DV |
15166 | |
15167 | /* Inconsistent output/port/pipe state happens presumably due to | |
15168 | * a bug in one of the get_hw_state functions. Or someplace else | |
15169 | * in our code, like the register restore mess on resume. Clamp | |
15170 | * things to off as a safer default. */ | |
3a3371ff | 15171 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15172 | if (connector->encoder != encoder) |
15173 | continue; | |
7f1950fb EE |
15174 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15175 | connector->base.encoder = NULL; | |
24929352 DV |
15176 | } |
15177 | } | |
15178 | /* Enabled encoders without active connectors will be fixed in | |
15179 | * the crtc fixup. */ | |
15180 | } | |
15181 | ||
04098753 | 15182 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15183 | { |
15184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 15185 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15186 | |
04098753 ID |
15187 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15188 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15189 | i915_disable_vga(dev); | |
15190 | } | |
15191 | } | |
15192 | ||
15193 | void i915_redisable_vga(struct drm_device *dev) | |
15194 | { | |
15195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15196 | ||
8dc8a27c PZ |
15197 | /* This function can be called both from intel_modeset_setup_hw_state or |
15198 | * at a very early point in our resume sequence, where the power well | |
15199 | * structures are not yet restored. Since this function is at a very | |
15200 | * paranoid "someone might have enabled VGA while we were not looking" | |
15201 | * level, just check if the power well is enabled instead of trying to | |
15202 | * follow the "don't touch the power well if we don't need it" policy | |
15203 | * the rest of the driver uses. */ | |
f458ebbc | 15204 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15205 | return; |
15206 | ||
04098753 | 15207 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15208 | } |
15209 | ||
f9cd7b88 | 15210 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15211 | { |
f9cd7b88 | 15212 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15213 | |
f9cd7b88 | 15214 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15215 | } |
15216 | ||
f9cd7b88 VS |
15217 | /* FIXME read out full plane state for all planes */ |
15218 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15219 | { |
b26d3ea3 | 15220 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15221 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15222 | to_intel_plane_state(primary->state); |
d032ffa0 | 15223 | |
a4611e44 | 15224 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15225 | primary_get_hw_state(to_intel_plane(primary)); |
15226 | ||
15227 | if (plane_state->visible) | |
15228 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15229 | } |
15230 | ||
30e984df | 15231 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15232 | { |
15233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15234 | enum pipe pipe; | |
24929352 DV |
15235 | struct intel_crtc *crtc; |
15236 | struct intel_encoder *encoder; | |
15237 | struct intel_connector *connector; | |
5358901f | 15238 | int i; |
24929352 | 15239 | |
d3fcc808 | 15240 | for_each_intel_crtc(dev, crtc) { |
b06f8b0d | 15241 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state); |
6e3c9717 | 15242 | memset(crtc->config, 0, sizeof(*crtc->config)); |
f7217905 | 15243 | crtc->config->base.crtc = &crtc->base; |
3b117c8f | 15244 | |
0e8ffe1b | 15245 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 15246 | crtc->config); |
24929352 | 15247 | |
49d6fa21 | 15248 | crtc->base.state->active = crtc->active; |
24929352 | 15249 | crtc->base.enabled = crtc->active; |
b70709a6 | 15250 | |
f9cd7b88 | 15251 | readout_plane_state(crtc); |
24929352 DV |
15252 | |
15253 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15254 | crtc->base.base.id, | |
15255 | crtc->active ? "enabled" : "disabled"); | |
15256 | } | |
15257 | ||
5358901f DV |
15258 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15259 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15260 | ||
3e369b76 ACO |
15261 | pll->on = pll->get_hw_state(dev_priv, pll, |
15262 | &pll->config.hw_state); | |
5358901f | 15263 | pll->active = 0; |
3e369b76 | 15264 | pll->config.crtc_mask = 0; |
d3fcc808 | 15265 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15266 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15267 | pll->active++; |
3e369b76 | 15268 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15269 | } |
5358901f | 15270 | } |
5358901f | 15271 | |
1e6f2ddc | 15272 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15273 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15274 | |
3e369b76 | 15275 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15276 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15277 | } |
15278 | ||
b2784e15 | 15279 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15280 | pipe = 0; |
15281 | ||
15282 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15283 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15284 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15285 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15286 | } else { |
15287 | encoder->base.crtc = NULL; | |
15288 | } | |
15289 | ||
6f2bcceb | 15290 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15291 | encoder->base.base.id, |
8e329a03 | 15292 | encoder->base.name, |
24929352 | 15293 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15294 | pipe_name(pipe)); |
24929352 DV |
15295 | } |
15296 | ||
3a3371ff | 15297 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15298 | if (connector->get_hw_state(connector)) { |
15299 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
24929352 DV |
15300 | connector->base.encoder = &connector->encoder->base; |
15301 | } else { | |
15302 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15303 | connector->base.encoder = NULL; | |
15304 | } | |
15305 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15306 | connector->base.base.id, | |
c23cc417 | 15307 | connector->base.name, |
24929352 DV |
15308 | connector->base.encoder ? "enabled" : "disabled"); |
15309 | } | |
7f4c6284 VS |
15310 | |
15311 | for_each_intel_crtc(dev, crtc) { | |
15312 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15313 | ||
15314 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15315 | if (crtc->base.state->active) { | |
15316 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15317 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15318 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15319 | ||
15320 | /* | |
15321 | * The initial mode needs to be set in order to keep | |
15322 | * the atomic core happy. It wants a valid mode if the | |
15323 | * crtc's enabled, so we do the above call. | |
15324 | * | |
15325 | * At this point some state updated by the connectors | |
15326 | * in their ->detect() callback has not run yet, so | |
15327 | * no recalculation can be done yet. | |
15328 | * | |
15329 | * Even if we could do a recalculation and modeset | |
15330 | * right now it would cause a double modeset if | |
15331 | * fbdev or userspace chooses a different initial mode. | |
15332 | * | |
15333 | * If that happens, someone indicated they wanted a | |
15334 | * mode change, which means it's safe to do a full | |
15335 | * recalculation. | |
15336 | */ | |
15337 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15338 | |
15339 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15340 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15341 | } |
15342 | } | |
30e984df DV |
15343 | } |
15344 | ||
043e9bda ML |
15345 | /* Scan out the current hw modeset state, |
15346 | * and sanitizes it to the current state | |
15347 | */ | |
15348 | static void | |
15349 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15350 | { |
15351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15352 | enum pipe pipe; | |
30e984df DV |
15353 | struct intel_crtc *crtc; |
15354 | struct intel_encoder *encoder; | |
35c95375 | 15355 | int i; |
30e984df DV |
15356 | |
15357 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15358 | |
15359 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15360 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15361 | intel_sanitize_encoder(encoder); |
15362 | } | |
15363 | ||
055e393f | 15364 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15365 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15366 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15367 | intel_dump_pipe_config(crtc, crtc->config, |
15368 | "[setup_hw_state]"); | |
24929352 | 15369 | } |
9a935856 | 15370 | |
d29b2f9d ACO |
15371 | intel_modeset_update_connector_atomic_state(dev); |
15372 | ||
35c95375 DV |
15373 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15374 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15375 | ||
15376 | if (!pll->on || pll->active) | |
15377 | continue; | |
15378 | ||
15379 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15380 | ||
15381 | pll->disable(dev_priv, pll); | |
15382 | pll->on = false; | |
15383 | } | |
15384 | ||
26e1fe4f | 15385 | if (IS_VALLEYVIEW(dev)) |
6eb1a681 VS |
15386 | vlv_wm_get_hw_state(dev); |
15387 | else if (IS_GEN9(dev)) | |
3078999f PB |
15388 | skl_wm_get_hw_state(dev); |
15389 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15390 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15391 | |
15392 | for_each_intel_crtc(dev, crtc) { | |
15393 | unsigned long put_domains; | |
15394 | ||
15395 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15396 | if (WARN_ON(put_domains)) | |
15397 | modeset_put_power_domains(dev_priv, put_domains); | |
15398 | } | |
15399 | intel_display_set_init_power(dev_priv, false); | |
043e9bda | 15400 | } |
7d0bc1ea | 15401 | |
043e9bda ML |
15402 | void intel_display_resume(struct drm_device *dev) |
15403 | { | |
15404 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15405 | struct intel_connector *conn; | |
15406 | struct intel_plane *plane; | |
15407 | struct drm_crtc *crtc; | |
15408 | int ret; | |
f30da187 | 15409 | |
043e9bda ML |
15410 | if (!state) |
15411 | return; | |
15412 | ||
15413 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15414 | ||
15415 | /* preserve complete old state, including dpll */ | |
15416 | intel_atomic_get_shared_dpll_state(state); | |
15417 | ||
15418 | for_each_crtc(dev, crtc) { | |
15419 | struct drm_crtc_state *crtc_state = | |
15420 | drm_atomic_get_crtc_state(state, crtc); | |
15421 | ||
15422 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
15423 | if (ret) | |
15424 | goto err; | |
15425 | ||
15426 | /* force a restore */ | |
15427 | crtc_state->mode_changed = true; | |
45e2b5f6 | 15428 | } |
8af6cf88 | 15429 | |
043e9bda ML |
15430 | for_each_intel_plane(dev, plane) { |
15431 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
15432 | if (ret) | |
15433 | goto err; | |
15434 | } | |
15435 | ||
15436 | for_each_intel_connector(dev, conn) { | |
15437 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
15438 | if (ret) | |
15439 | goto err; | |
15440 | } | |
15441 | ||
15442 | intel_modeset_setup_hw_state(dev); | |
15443 | ||
15444 | i915_redisable_vga(dev); | |
74c090b1 | 15445 | ret = drm_atomic_commit(state); |
043e9bda ML |
15446 | if (!ret) |
15447 | return; | |
15448 | ||
15449 | err: | |
15450 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15451 | drm_atomic_state_free(state); | |
2c7111db CW |
15452 | } |
15453 | ||
15454 | void intel_modeset_gem_init(struct drm_device *dev) | |
15455 | { | |
484b41dd | 15456 | struct drm_crtc *c; |
2ff8fde1 | 15457 | struct drm_i915_gem_object *obj; |
e0d6149b | 15458 | int ret; |
484b41dd | 15459 | |
ae48434c ID |
15460 | mutex_lock(&dev->struct_mutex); |
15461 | intel_init_gt_powersave(dev); | |
15462 | mutex_unlock(&dev->struct_mutex); | |
15463 | ||
1833b134 | 15464 | intel_modeset_init_hw(dev); |
02e792fb DV |
15465 | |
15466 | intel_setup_overlay(dev); | |
484b41dd JB |
15467 | |
15468 | /* | |
15469 | * Make sure any fbs we allocated at startup are properly | |
15470 | * pinned & fenced. When we do the allocation it's too early | |
15471 | * for this. | |
15472 | */ | |
70e1e0ec | 15473 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15474 | obj = intel_fb_obj(c->primary->fb); |
15475 | if (obj == NULL) | |
484b41dd JB |
15476 | continue; |
15477 | ||
e0d6149b TU |
15478 | mutex_lock(&dev->struct_mutex); |
15479 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15480 | c->primary->fb, | |
15481 | c->primary->state, | |
91af127f | 15482 | NULL, NULL); |
e0d6149b TU |
15483 | mutex_unlock(&dev->struct_mutex); |
15484 | if (ret) { | |
484b41dd JB |
15485 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15486 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15487 | drm_framebuffer_unreference(c->primary->fb); |
15488 | c->primary->fb = NULL; | |
36750f28 | 15489 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15490 | update_state_fb(c->primary); |
36750f28 | 15491 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15492 | } |
15493 | } | |
0962c3c9 VS |
15494 | |
15495 | intel_backlight_register(dev); | |
79e53945 JB |
15496 | } |
15497 | ||
4932e2c3 ID |
15498 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15499 | { | |
15500 | struct drm_connector *connector = &intel_connector->base; | |
15501 | ||
15502 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15503 | drm_connector_unregister(connector); |
4932e2c3 ID |
15504 | } |
15505 | ||
79e53945 JB |
15506 | void intel_modeset_cleanup(struct drm_device *dev) |
15507 | { | |
652c393a | 15508 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15509 | struct drm_connector *connector; |
652c393a | 15510 | |
2eb5252e ID |
15511 | intel_disable_gt_powersave(dev); |
15512 | ||
0962c3c9 VS |
15513 | intel_backlight_unregister(dev); |
15514 | ||
fd0c0642 DV |
15515 | /* |
15516 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15517 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15518 | * experience fancy races otherwise. |
15519 | */ | |
2aeb7d3a | 15520 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15521 | |
fd0c0642 DV |
15522 | /* |
15523 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15524 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15525 | */ | |
f87ea761 | 15526 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15527 | |
723bfd70 JB |
15528 | intel_unregister_dsm_handler(); |
15529 | ||
7733b49b | 15530 | intel_fbc_disable(dev_priv); |
69341a5e | 15531 | |
1630fe75 CW |
15532 | /* flush any delayed tasks or pending work */ |
15533 | flush_scheduled_work(); | |
15534 | ||
db31af1d JN |
15535 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15536 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15537 | struct intel_connector *intel_connector; |
15538 | ||
15539 | intel_connector = to_intel_connector(connector); | |
15540 | intel_connector->unregister(intel_connector); | |
db31af1d | 15541 | } |
d9255d57 | 15542 | |
79e53945 | 15543 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15544 | |
15545 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15546 | |
15547 | mutex_lock(&dev->struct_mutex); | |
15548 | intel_cleanup_gt_powersave(dev); | |
15549 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15550 | } |
15551 | ||
f1c79df3 ZW |
15552 | /* |
15553 | * Return which encoder is currently attached for connector. | |
15554 | */ | |
df0e9248 | 15555 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15556 | { |
df0e9248 CW |
15557 | return &intel_attached_encoder(connector)->base; |
15558 | } | |
f1c79df3 | 15559 | |
df0e9248 CW |
15560 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15561 | struct intel_encoder *encoder) | |
15562 | { | |
15563 | connector->encoder = encoder; | |
15564 | drm_mode_connector_attach_encoder(&connector->base, | |
15565 | &encoder->base); | |
79e53945 | 15566 | } |
28d52043 DA |
15567 | |
15568 | /* | |
15569 | * set vga decode state - true == enable VGA decode | |
15570 | */ | |
15571 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15572 | { | |
15573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15574 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15575 | u16 gmch_ctrl; |
15576 | ||
75fa041d CW |
15577 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15578 | DRM_ERROR("failed to read control word\n"); | |
15579 | return -EIO; | |
15580 | } | |
15581 | ||
c0cc8a55 CW |
15582 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15583 | return 0; | |
15584 | ||
28d52043 DA |
15585 | if (state) |
15586 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15587 | else | |
15588 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15589 | |
15590 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15591 | DRM_ERROR("failed to write control word\n"); | |
15592 | return -EIO; | |
15593 | } | |
15594 | ||
28d52043 DA |
15595 | return 0; |
15596 | } | |
c4a1d9e4 | 15597 | |
c4a1d9e4 | 15598 | struct intel_display_error_state { |
ff57f1b0 PZ |
15599 | |
15600 | u32 power_well_driver; | |
15601 | ||
63b66e5b CW |
15602 | int num_transcoders; |
15603 | ||
c4a1d9e4 CW |
15604 | struct intel_cursor_error_state { |
15605 | u32 control; | |
15606 | u32 position; | |
15607 | u32 base; | |
15608 | u32 size; | |
52331309 | 15609 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15610 | |
15611 | struct intel_pipe_error_state { | |
ddf9c536 | 15612 | bool power_domain_on; |
c4a1d9e4 | 15613 | u32 source; |
f301b1e1 | 15614 | u32 stat; |
52331309 | 15615 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15616 | |
15617 | struct intel_plane_error_state { | |
15618 | u32 control; | |
15619 | u32 stride; | |
15620 | u32 size; | |
15621 | u32 pos; | |
15622 | u32 addr; | |
15623 | u32 surface; | |
15624 | u32 tile_offset; | |
52331309 | 15625 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15626 | |
15627 | struct intel_transcoder_error_state { | |
ddf9c536 | 15628 | bool power_domain_on; |
63b66e5b CW |
15629 | enum transcoder cpu_transcoder; |
15630 | ||
15631 | u32 conf; | |
15632 | ||
15633 | u32 htotal; | |
15634 | u32 hblank; | |
15635 | u32 hsync; | |
15636 | u32 vtotal; | |
15637 | u32 vblank; | |
15638 | u32 vsync; | |
15639 | } transcoder[4]; | |
c4a1d9e4 CW |
15640 | }; |
15641 | ||
15642 | struct intel_display_error_state * | |
15643 | intel_display_capture_error_state(struct drm_device *dev) | |
15644 | { | |
fbee40df | 15645 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15646 | struct intel_display_error_state *error; |
63b66e5b CW |
15647 | int transcoders[] = { |
15648 | TRANSCODER_A, | |
15649 | TRANSCODER_B, | |
15650 | TRANSCODER_C, | |
15651 | TRANSCODER_EDP, | |
15652 | }; | |
c4a1d9e4 CW |
15653 | int i; |
15654 | ||
63b66e5b CW |
15655 | if (INTEL_INFO(dev)->num_pipes == 0) |
15656 | return NULL; | |
15657 | ||
9d1cb914 | 15658 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15659 | if (error == NULL) |
15660 | return NULL; | |
15661 | ||
190be112 | 15662 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15663 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15664 | ||
055e393f | 15665 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15666 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15667 | __intel_display_power_is_enabled(dev_priv, |
15668 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15669 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15670 | continue; |
15671 | ||
5efb3e28 VS |
15672 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15673 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15674 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15675 | |
15676 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15677 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15678 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15679 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15680 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15681 | } | |
ca291363 PZ |
15682 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15683 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15684 | if (INTEL_INFO(dev)->gen >= 4) { |
15685 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15686 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15687 | } | |
15688 | ||
c4a1d9e4 | 15689 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15690 | |
3abfce77 | 15691 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15692 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15693 | } |
15694 | ||
15695 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15696 | if (HAS_DDI(dev_priv->dev)) | |
15697 | error->num_transcoders++; /* Account for eDP. */ | |
15698 | ||
15699 | for (i = 0; i < error->num_transcoders; i++) { | |
15700 | enum transcoder cpu_transcoder = transcoders[i]; | |
15701 | ||
ddf9c536 | 15702 | error->transcoder[i].power_domain_on = |
f458ebbc | 15703 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15704 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15705 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15706 | continue; |
15707 | ||
63b66e5b CW |
15708 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15709 | ||
15710 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15711 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15712 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15713 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15714 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15715 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15716 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15717 | } |
15718 | ||
15719 | return error; | |
15720 | } | |
15721 | ||
edc3d884 MK |
15722 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15723 | ||
c4a1d9e4 | 15724 | void |
edc3d884 | 15725 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15726 | struct drm_device *dev, |
15727 | struct intel_display_error_state *error) | |
15728 | { | |
055e393f | 15729 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15730 | int i; |
15731 | ||
63b66e5b CW |
15732 | if (!error) |
15733 | return; | |
15734 | ||
edc3d884 | 15735 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15736 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15737 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15738 | error->power_well_driver); |
055e393f | 15739 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15740 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15741 | err_printf(m, " Power: %s\n", |
15742 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15743 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15744 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15745 | |
15746 | err_printf(m, "Plane [%d]:\n", i); | |
15747 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15748 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15749 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15750 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15751 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15752 | } |
4b71a570 | 15753 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15754 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15755 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15756 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15757 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15758 | } |
15759 | ||
edc3d884 MK |
15760 | err_printf(m, "Cursor [%d]:\n", i); |
15761 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15762 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15763 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15764 | } |
63b66e5b CW |
15765 | |
15766 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15767 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15768 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15769 | err_printf(m, " Power: %s\n", |
15770 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15771 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15772 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15773 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15774 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15775 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15776 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15777 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15778 | } | |
c4a1d9e4 | 15779 | } |
e2fcdaa9 VS |
15780 | |
15781 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15782 | { | |
15783 | struct intel_crtc *crtc; | |
15784 | ||
15785 | for_each_intel_crtc(dev, crtc) { | |
15786 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15787 | |
5e2d7afc | 15788 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15789 | |
15790 | work = crtc->unpin_work; | |
15791 | ||
15792 | if (work && work->event && | |
15793 | work->event->base.file_priv == file) { | |
15794 | kfree(work->event); | |
15795 | work->event = NULL; | |
15796 | } | |
15797 | ||
5e2d7afc | 15798 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15799 | } |
15800 | } |