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drm/i915: Bail out once we've found the context object
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
79e53945
JB		 490{
491 struct drm_device *dev = crtc->dev;
79e53945 492 intel_clock_t clock;
79e53945
JB		 493 int err = target;
494
a210b028 495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 496 /*
a210b028
DV		 497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
79e53945 500 */
1974cad0 501 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
0206e353 512 memset(best_clock, 0, sizeof(*best_clock));
79e53945 513
42158660
ZY		 514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
42158660
ZY		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 524 int this_err;
525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
e2b78267
DV		 912static struct intel_shared_dpll *
913intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
914{
915 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
916
a43f6e0f 917 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 918 return NULL;
919
a43f6e0f 920 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 921}
922
040484af 923/* For ILK+ */
e72f9fbf
DV		 924static void assert_shared_dpll(struct drm_i915_private *dev_priv,
925 struct intel_shared_dpll *pll,
e72f9fbf 926 bool state)
040484af 927{
040484af 928 bool cur_state;
5358901f 929 struct intel_dpll_hw_state hw_state;
040484af 930
9d82aa17
ED		 931 if (HAS_PCH_LPT(dev_priv->dev)) {
932 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
933 return;
934 }
935
92b27b08 936 if (WARN (!pll,
46edb027 937 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 938 return;
ee7b9f93 939
5358901f 940 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 941 WARN(cur_state != state,
5358901f
DV		 942 "%s assertion failure (expected %s, current %s)\n",
943 pll->name, state_string(state), state_string(cur_state));
040484af 944}
e9d6944e
DV		 945#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
946#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
040484af
JB		 947
948static void assert_fdi_tx(struct drm_i915_private *dev_priv,
949 enum pipe pipe, bool state)
950{
951 int reg;
952 u32 val;
953 bool cur_state;
ad80a810
PZ		 954 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
955 pipe);
040484af 956
affa9354
PZ		 957 if (HAS_DDI(dev_priv->dev)) {
958 /* DDI does not have a specific FDI_TX register */
ad80a810 959 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 960 val = I915_READ(reg);
ad80a810 961 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 962 } else {
963 reg = FDI_TX_CTL(pipe);
964 val = I915_READ(reg);
965 cur_state = !!(val & FDI_TX_ENABLE);
966 }
040484af
JB		 967 WARN(cur_state != state,
968 "FDI TX state assertion failure (expected %s, current %s)\n",
969 state_string(state), state_string(cur_state));
970}
971#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
972#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
973
974static void assert_fdi_rx(struct drm_i915_private *dev_priv,
975 enum pipe pipe, bool state)
976{
977 int reg;
978 u32 val;
979 bool cur_state;
980
d63fa0dc
PZ		 981 reg = FDI_RX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 984 WARN(cur_state != state,
985 "FDI RX state assertion failure (expected %s, current %s)\n",
986 state_string(state), state_string(cur_state));
987}
988#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
989#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
990
991static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
992 enum pipe pipe)
993{
994 int reg;
995 u32 val;
996
997 /* ILK FDI PLL is always enabled */
998 if (dev_priv->info->gen == 5)
999 return;
1000
bf507ef7 1001 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1002 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1003 return;
1004
040484af
JB		 1005 reg = FDI_TX_CTL(pipe);
1006 val = I915_READ(reg);
1007 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1008}
1009
1010static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1011 enum pipe pipe)
1012{
1013 int reg;
1014 u32 val;
1015
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1019}
1020
ea0760cf
JB		 1021static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1022 enum pipe pipe)
1023{
1024 int pp_reg, lvds_reg;
1025 u32 val;
1026 enum pipe panel_pipe = PIPE_A;
0de3b485 1027 bool locked = true;
ea0760cf
JB		 1028
1029 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1030 pp_reg = PCH_PP_CONTROL;
1031 lvds_reg = PCH_LVDS;
1032 } else {
1033 pp_reg = PP_CONTROL;
1034 lvds_reg = LVDS;
1035 }
1036
1037 val = I915_READ(pp_reg);
1038 if (!(val & PANEL_POWER_ON) ||
1039 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1040 locked = false;
1041
1042 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1043 panel_pipe = PIPE_B;
1044
1045 WARN(panel_pipe == pipe && locked,
1046 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1047 pipe_name(pipe));
ea0760cf
JB		 1048}
1049
b840d907
JB		 1050void assert_pipe(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
b24e7179
JB		 1052{
1053 int reg;
1054 u32 val;
63d7bbe9 1055 bool cur_state;
702e7a56
PZ		 1056 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1057 pipe);
b24e7179 1058
8e636784
DV		 1059 /* if we need the pipe A quirk it must be always on */
1060 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1061 state = true;
1062
b97186f0
PZ		 1063 if (!intel_display_power_enabled(dev_priv->dev,
1064 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1065 cur_state = false;
1066 } else {
1067 reg = PIPECONF(cpu_transcoder);
1068 val = I915_READ(reg);
1069 cur_state = !!(val & PIPECONF_ENABLE);
1070 }
1071
63d7bbe9
JB		 1072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1074 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1075}
1076
931872fc
CW		 1077static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
b24e7179
JB		 1079{
1080 int reg;
1081 u32 val;
931872fc 1082 bool cur_state;
b24e7179
JB		 1083
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
931872fc
CW		 1086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1090}
1091
931872fc
CW		 1092#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
b24e7179
JB		 1095static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096 enum pipe pipe)
1097{
653e1026 1098 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1099 int reg, i;
1100 u32 val;
1101 int cur_pipe;
1102
653e1026
VS		 1103 /* Primary planes are fixed to pipes on gen4+ */
1104 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1105 reg = DSPCNTR(pipe);
1106 val = I915_READ(reg);
1107 WARN((val & DISPLAY_PLANE_ENABLE),
1108 "plane %c assertion failure, should be disabled but not\n",
1109 plane_name(pipe));
19ec1358 1110 return;
28c05794 1111 }
19ec1358 1112
b24e7179 1113 /* Need to check both planes against the pipe */
653e1026 1114 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1115 reg = DSPCNTR(i);
1116 val = I915_READ(reg);
1117 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1118 DISPPLANE_SEL_PIPE_SHIFT;
1119 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1120 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1121 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1122 }
1123}
1124
19332d7a
JB		 1125static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1126 enum pipe pipe)
1127{
20674eef 1128 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1129 int reg, i;
1130 u32 val;
1131
20674eef
VS		 1132 if (IS_VALLEYVIEW(dev)) {
1133 for (i = 0; i < dev_priv->num_plane; i++) {
1134 reg = SPCNTR(pipe, i);
1135 val = I915_READ(reg);
1136 WARN((val & SP_ENABLE),
1137 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1138 sprite_name(pipe, i), pipe_name(pipe));
1139 }
1140 } else if (INTEL_INFO(dev)->gen >= 7) {
1141 reg = SPRCTL(pipe);
19332d7a 1142 val = I915_READ(reg);
20674eef 1143 WARN((val & SPRITE_ENABLE),
06da8da2 1144 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1145 plane_name(pipe), pipe_name(pipe));
1146 } else if (INTEL_INFO(dev)->gen >= 5) {
1147 reg = DVSCNTR(pipe);
19332d7a 1148 val = I915_READ(reg);
20674eef 1149 WARN((val & DVS_ENABLE),
06da8da2 1150 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1151 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1152 }
1153}
1154
92f2584a
JB		 1155static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1156{
1157 u32 val;
1158 bool enabled;
1159
9d82aa17
ED		 1160 if (HAS_PCH_LPT(dev_priv->dev)) {
1161 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1162 return;
1163 }
1164
92f2584a
JB		 1165 val = I915_READ(PCH_DREF_CONTROL);
1166 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1167 DREF_SUPERSPREAD_SOURCE_MASK));
1168 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1169}
1170
ab9412ba
DV		 1171static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
92f2584a
JB		 1173{
1174 int reg;
1175 u32 val;
1176 bool enabled;
1177
ab9412ba 1178 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1179 val = I915_READ(reg);
1180 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1181 WARN(enabled,
1182 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1183 pipe_name(pipe));
92f2584a
JB		 1184}
1185
4e634389
KP		 1186static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1188{
1189 if ((val & DP_PORT_EN) == 0)
1190 return false;
1191
1192 if (HAS_PCH_CPT(dev_priv->dev)) {
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196 return false;
1197 } else {
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199 return false;
1200 }
1201 return true;
1202}
1203
1519b995
KP		 1204static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, u32 val)
1206{
dc0fa718 1207 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1208 return false;
1209
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1212 return false;
1213 } else {
dc0fa718 1214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1215 return false;
1216 }
1217 return true;
1218}
1219
1220static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, u32 val)
1222{
1223 if ((val & LVDS_PORT_EN) == 0)
1224 return false;
1225
1226 if (HAS_PCH_CPT(dev_priv->dev)) {
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228 return false;
1229 } else {
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231 return false;
1232 }
1233 return true;
1234}
1235
1236static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238{
1239 if ((val & ADPA_DAC_ENABLE) == 0)
1240 return false;
1241 if (HAS_PCH_CPT(dev_priv->dev)) {
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243 return false;
1244 } else {
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246 return false;
1247 }
1248 return true;
1249}
1250
291906f1 1251static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1252 enum pipe pipe, int reg, u32 port_sel)
291906f1 1253{
47a05eca 1254 u32 val = I915_READ(reg);
4e634389 1255 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1256 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1257 reg, pipe_name(pipe));
de9a35ab 1258
75c5da27
DV		 1259 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 && (val & DP_PIPEB_SELECT),
de9a35ab 1261 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1262}
1263
1264static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, int reg)
1266{
47a05eca 1267 u32 val = I915_READ(reg);
b70ad586 1268 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1269 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1270 reg, pipe_name(pipe));
de9a35ab 1271
dc0fa718 1272 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1273 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1274 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1275}
1276
1277static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279{
1280 int reg;
1281 u32 val;
291906f1 1282
f0575e92
KP		 1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1286
1287 reg = PCH_ADPA;
1288 val = I915_READ(reg);
b70ad586 1289 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1290 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1291 pipe_name(pipe));
291906f1
JB		 1292
1293 reg = PCH_LVDS;
1294 val = I915_READ(reg);
b70ad586 1295 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1296 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1297 pipe_name(pipe));
291906f1 1298
e2debe91
PZ		 1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1302}
1303
63d7bbe9
JB		 1304/**
1305 * intel_enable_pll - enable a PLL
1306 * @dev_priv: i915 private structure
1307 * @pipe: pipe PLL to enable
1308 *
1309 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1310 * make sure the PLL reg is writable first though, since the panel write
1311 * protect mechanism may be enabled.
1312 *
1313 * Note! This is for pre-ILK only.
7434a255
TR		 1314 *
1315 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1316 */
1317static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321
58c6eaa2
DV		 1322 assert_pipe_disabled(dev_priv, pipe);
1323
63d7bbe9 1324 /* No really, not for ILK+ */
a0c4da24 1325 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1326
1327 /* PLL is protected by panel, make sure we can write it */
1328 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1329 assert_panel_unlocked(dev_priv, pipe);
1330
1331 reg = DPLL(pipe);
1332 val = I915_READ(reg);
1333 val |= DPLL_VCO_ENABLE;
1334
1335 /* We do this three times for luck */
1336 I915_WRITE(reg, val);
1337 POSTING_READ(reg);
1338 udelay(150); /* wait for warmup */
1339 I915_WRITE(reg, val);
1340 POSTING_READ(reg);
1341 udelay(150); /* wait for warmup */
1342 I915_WRITE(reg, val);
1343 POSTING_READ(reg);
1344 udelay(150); /* wait for warmup */
1345}
1346
1347/**
1348 * intel_disable_pll - disable a PLL
1349 * @dev_priv: i915 private structure
1350 * @pipe: pipe PLL to disable
1351 *
1352 * Disable the PLL for @pipe, making sure the pipe is off first.
1353 *
1354 * Note! This is for pre-ILK only.
1355 */
1356static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1357{
1358 int reg;
1359 u32 val;
1360
1361 /* Don't disable pipe A or pipe A PLLs if needed */
1362 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1363 return;
1364
1365 /* Make sure the pipe isn't still relying on us */
1366 assert_pipe_disabled(dev_priv, pipe);
1367
1368 reg = DPLL(pipe);
1369 val = I915_READ(reg);
1370 val &= ~DPLL_VCO_ENABLE;
1371 I915_WRITE(reg, val);
1372 POSTING_READ(reg);
1373}
1374
89b667f8
JB		 1375void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1376{
1377 u32 port_mask;
1378
1379 if (!port)
1380 port_mask = DPLL_PORTB_READY_MASK;
1381 else
1382 port_mask = DPLL_PORTC_READY_MASK;
1383
1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1385 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1386 'B' + port, I915_READ(DPLL(0)));
1387}
1388
92f2584a 1389/**
e72f9fbf 1390 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1391 * @dev_priv: i915 private structure
1392 * @pipe: pipe PLL to enable
1393 *
1394 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1395 * drives the transcoder clock.
1396 */
e2b78267 1397static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1398{
e2b78267
DV		 1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1401
48da64a8 1402 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1403 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1404 if (WARN_ON(pll == NULL))
48da64a8
CW		 1405 return;
1406
1407 if (WARN_ON(pll->refcount == 0))
1408 return;
ee7b9f93 1409
46edb027
DV		 1410 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1411 pll->name, pll->active, pll->on,
e2b78267 1412 crtc->base.base.id);
92f2584a 1413
cdbd2316
DV		 1414 if (pll->active++) {
1415 WARN_ON(!pll->on);
e9d6944e 1416 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1417 return;
1418 }
f4a091c7 1419 WARN_ON(pll->on);
ee7b9f93 1420
46edb027 1421 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1422 pll->enable(dev_priv, pll);
ee7b9f93 1423 pll->on = true;
92f2584a
JB		 1424}
1425
e2b78267 1426static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1427{
e2b78267
DV		 1428 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1429 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1430
92f2584a
JB		 1431 /* PCH only available on ILK+ */
1432 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1433 if (WARN_ON(pll == NULL))
ee7b9f93 1434 return;
92f2584a 1435
48da64a8
CW		 1436 if (WARN_ON(pll->refcount == 0))
1437 return;
7a419866 1438
46edb027
DV		 1439 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1440 pll->name, pll->active, pll->on,
e2b78267 1441 crtc->base.base.id);
7a419866 1442
48da64a8 1443 if (WARN_ON(pll->active == 0)) {
e9d6944e 1444 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1445 return;
1446 }
1447
e9d6944e 1448 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1449 WARN_ON(!pll->on);
cdbd2316 1450 if (--pll->active)
7a419866 1451 return;
ee7b9f93 1452
46edb027 1453 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1454 pll->disable(dev_priv, pll);
ee7b9f93 1455 pll->on = false;
92f2584a
JB		 1456}
1457
b8a4f404
PZ		 1458static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
040484af 1460{
23670b32 1461 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1462 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1464 uint32_t reg, val, pipeconf_val;
040484af
JB		 1465
1466 /* PCH only available on ILK+ */
1467 BUG_ON(dev_priv->info->gen < 5);
1468
1469 /* Make sure PCH DPLL is enabled */
e72f9fbf 1470 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1471 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1472
1473 /* FDI must be feeding us bits for PCH ports */
1474 assert_fdi_tx_enabled(dev_priv, pipe);
1475 assert_fdi_rx_enabled(dev_priv, pipe);
1476
23670b32
DV		 1477 if (HAS_PCH_CPT(dev)) {
1478 /* Workaround: Set the timing override bit before enabling the
1479 * pch transcoder. */
1480 reg = TRANS_CHICKEN2(pipe);
1481 val = I915_READ(reg);
1482 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1483 I915_WRITE(reg, val);
59c859d6 1484 }
23670b32 1485
ab9412ba 1486 reg = PCH_TRANSCONF(pipe);
040484af 1487 val = I915_READ(reg);
5f7f726d 1488 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1489
1490 if (HAS_PCH_IBX(dev_priv->dev)) {
1491 /*
1492 * make the BPC in transcoder be consistent with
1493 * that in pipeconf reg.
1494 */
dfd07d72
DV		 1495 val &= ~PIPECONF_BPC_MASK;
1496 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1497 }
5f7f726d
PZ		 1498
1499 val &= ~TRANS_INTERLACE_MASK;
1500 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1501 if (HAS_PCH_IBX(dev_priv->dev) &&
1502 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1503 val |= TRANS_LEGACY_INTERLACED_ILK;
1504 else
1505 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1506 else
1507 val |= TRANS_PROGRESSIVE;
1508
040484af
JB		 1509 I915_WRITE(reg, val | TRANS_ENABLE);
1510 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1511 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1512}
1513
8fb033d7 1514static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1515 enum transcoder cpu_transcoder)
040484af 1516{
8fb033d7 1517 u32 val, pipeconf_val;
8fb033d7
PZ		 1518
1519 /* PCH only available on ILK+ */
1520 BUG_ON(dev_priv->info->gen < 5);
1521
8fb033d7 1522 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1523 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1524 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1525
223a6fdf
PZ		 1526 /* Workaround: set timing override bit. */
1527 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1528 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1529 I915_WRITE(_TRANSA_CHICKEN2, val);
1530
25f3ef11 1531 val = TRANS_ENABLE;
937bb610 1532 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1533
9a76b1c6
PZ		 1534 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1535 PIPECONF_INTERLACED_ILK)
a35f2679 1536 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1537 else
1538 val |= TRANS_PROGRESSIVE;
1539
ab9412ba
DV		 1540 I915_WRITE(LPT_TRANSCONF, val);
1541 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1542 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1543}
1544
b8a4f404
PZ		 1545static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1546 enum pipe pipe)
040484af 1547{
23670b32
DV		 1548 struct drm_device *dev = dev_priv->dev;
1549 uint32_t reg, val;
040484af
JB		 1550
1551 /* FDI relies on the transcoder */
1552 assert_fdi_tx_disabled(dev_priv, pipe);
1553 assert_fdi_rx_disabled(dev_priv, pipe);
1554
291906f1
JB		 1555 /* Ports must be off as well */
1556 assert_pch_ports_disabled(dev_priv, pipe);
1557
ab9412ba 1558 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1559 val = I915_READ(reg);
1560 val &= ~TRANS_ENABLE;
1561 I915_WRITE(reg, val);
1562 /* wait for PCH transcoder off, transcoder state */
1563 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1564 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1565
1566 if (!HAS_PCH_IBX(dev)) {
1567 /* Workaround: Clear the timing override chicken bit again. */
1568 reg = TRANS_CHICKEN2(pipe);
1569 val = I915_READ(reg);
1570 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1571 I915_WRITE(reg, val);
1572 }
040484af
JB		 1573}
1574
ab4d966c 1575static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1576{
8fb033d7
PZ		 1577 u32 val;
1578
ab9412ba 1579 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1580 val &= ~TRANS_ENABLE;
ab9412ba 1581 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1582 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1583 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1584 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1585
1586 /* Workaround: clear timing override bit. */
1587 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1588 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1589 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1590}
1591
b24e7179 1592/**
309cfea8 1593 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1594 * @dev_priv: i915 private structure
1595 * @pipe: pipe to enable
040484af 1596 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1597 *
1598 * Enable @pipe, making sure that various hardware specific requirements
1599 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1600 *
1601 * @pipe should be %PIPE_A or %PIPE_B.
1602 *
1603 * Will wait until the pipe is actually running (i.e. first vblank) before
1604 * returning.
1605 */
040484af
JB		 1606static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1607 bool pch_port)
b24e7179 1608{
702e7a56
PZ		 1609 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1610 pipe);
1a240d4d 1611 enum pipe pch_transcoder;
b24e7179
JB		 1612 int reg;
1613 u32 val;
1614
58c6eaa2
DV		 1615 assert_planes_disabled(dev_priv, pipe);
1616 assert_sprites_disabled(dev_priv, pipe);
1617
681e5811 1618 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1619 pch_transcoder = TRANSCODER_A;
1620 else
1621 pch_transcoder = pipe;
1622
b24e7179
JB		 1623 /*
1624 * A pipe without a PLL won't actually be able to drive bits from
1625 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1626 * need the check.
1627 */
1628 if (!HAS_PCH_SPLIT(dev_priv->dev))
1629 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1630 else {
1631 if (pch_port) {
1632 /* if driving the PCH, we need FDI enabled */
cc391bbb 1633 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1634 assert_fdi_tx_pll_enabled(dev_priv,
1635 (enum pipe) cpu_transcoder);
040484af
JB		 1636 }
1637 /* FIXME: assert CPU port conditions for SNB+ */
1638 }
b24e7179 1639
702e7a56 1640 reg = PIPECONF(cpu_transcoder);
b24e7179 1641 val = I915_READ(reg);
00d70b15
CW		 1642 if (val & PIPECONF_ENABLE)
1643 return;
1644
1645 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1646 intel_wait_for_vblank(dev_priv->dev, pipe);
1647}
1648
1649/**
309cfea8 1650 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to disable
1653 *
1654 * Disable @pipe, making sure that various hardware specific requirements
1655 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1656 *
1657 * @pipe should be %PIPE_A or %PIPE_B.
1658 *
1659 * Will wait until the pipe has shut down before returning.
1660 */
1661static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1662 enum pipe pipe)
1663{
702e7a56
PZ		 1664 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665 pipe);
b24e7179
JB		 1666 int reg;
1667 u32 val;
1668
1669 /*
1670 * Make sure planes won't keep trying to pump pixels to us,
1671 * or we might hang the display.
1672 */
1673 assert_planes_disabled(dev_priv, pipe);
19332d7a 1674 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1675
1676 /* Don't disable pipe A or pipe A PLLs if needed */
1677 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1678 return;
1679
702e7a56 1680 reg = PIPECONF(cpu_transcoder);
b24e7179 1681 val = I915_READ(reg);
00d70b15
CW		 1682 if ((val & PIPECONF_ENABLE) == 0)
1683 return;
1684
1685 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1686 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1687}
1688
d74362c9
KP		 1689/*
1690 * Plane regs are double buffered, going from enabled->disabled needs a
1691 * trigger in order to latch. The display address reg provides this.
1692 */
6f1d69b0 1693void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1694 enum plane plane)
1695{
14f86147
DL		 1696 if (dev_priv->info->gen >= 4)
1697 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1698 else
1699 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1700}
1701
b24e7179
JB		 1702/**
1703 * intel_enable_plane - enable a display plane on a given pipe
1704 * @dev_priv: i915 private structure
1705 * @plane: plane to enable
1706 * @pipe: pipe being fed
1707 *
1708 * Enable @plane on @pipe, making sure that @pipe is running first.
1709 */
1710static void intel_enable_plane(struct drm_i915_private *dev_priv,
1711 enum plane plane, enum pipe pipe)
1712{
1713 int reg;
1714 u32 val;
1715
1716 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1717 assert_pipe_enabled(dev_priv, pipe);
1718
1719 reg = DSPCNTR(plane);
1720 val = I915_READ(reg);
00d70b15
CW		 1721 if (val & DISPLAY_PLANE_ENABLE)
1722 return;
1723
1724 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1725 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1726 intel_wait_for_vblank(dev_priv->dev, pipe);
1727}
1728
b24e7179
JB		 1729/**
1730 * intel_disable_plane - disable a display plane
1731 * @dev_priv: i915 private structure
1732 * @plane: plane to disable
1733 * @pipe: pipe consuming the data
1734 *
1735 * Disable @plane; should be an independent operation.
1736 */
1737static void intel_disable_plane(struct drm_i915_private *dev_priv,
1738 enum plane plane, enum pipe pipe)
1739{
1740 int reg;
1741 u32 val;
1742
1743 reg = DSPCNTR(plane);
1744 val = I915_READ(reg);
00d70b15
CW		 1745 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1746 return;
1747
1748 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1749 intel_flush_display_plane(dev_priv, plane);
1750 intel_wait_for_vblank(dev_priv->dev, pipe);
1751}
1752
693db184
CW		 1753static bool need_vtd_wa(struct drm_device *dev)
1754{
1755#ifdef CONFIG_INTEL_IOMMU
1756 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1757 return true;
1758#endif
1759 return false;
1760}
1761
127bd2ac 1762int
48b956c5 1763intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1764 struct drm_i915_gem_object *obj,
919926ae 1765 struct intel_ring_buffer *pipelined)
6b95a207 1766{
ce453d81 1767 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1768 u32 alignment;
1769 int ret;
1770
05394f39 1771 switch (obj->tiling_mode) {
6b95a207 1772 case I915_TILING_NONE:
534843da
CW		 1773 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1774 alignment = 128 * 1024;
a6c45cf0 1775 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1776 alignment = 4 * 1024;
1777 else
1778 alignment = 64 * 1024;
6b95a207
KH		 1779 break;
1780 case I915_TILING_X:
1781 /* pin() will align the object as required by fence */
1782 alignment = 0;
1783 break;
1784 case I915_TILING_Y:
8bb6e959
DV		 1785 /* Despite that we check this in framebuffer_init userspace can
1786 * screw us over and change the tiling after the fact. Only
1787 * pinned buffers can't change their tiling. */
1788 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1789 return -EINVAL;
1790 default:
1791 BUG();
1792 }
1793
693db184
CW		 1794 /* Note that the w/a also requires 64 PTE of padding following the
1795 * bo. We currently fill all unused PTE with the shadow page and so
1796 * we should always have valid PTE following the scanout preventing
1797 * the VT-d warning.
1798 */
1799 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1800 alignment = 256 * 1024;
1801
ce453d81 1802 dev_priv->mm.interruptible = false;
2da3b9b9 1803 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1804 if (ret)
ce453d81 1805 goto err_interruptible;
6b95a207
KH		 1806
1807 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1808 * fence, whereas 965+ only requires a fence if using
1809 * framebuffer compression. For simplicity, we always install
1810 * a fence as the cost is not that onerous.
1811 */
06d98131 1812 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1813 if (ret)
1814 goto err_unpin;
1690e1eb 1815
9a5a53b3 1816 i915_gem_object_pin_fence(obj);
6b95a207 1817
ce453d81 1818 dev_priv->mm.interruptible = true;
6b95a207 1819 return 0;
48b956c5
CW		 1820
1821err_unpin:
1822 i915_gem_object_unpin(obj);
ce453d81
CW		 1823err_interruptible:
1824 dev_priv->mm.interruptible = true;
48b956c5 1825 return ret;
6b95a207
KH		 1826}
1827
1690e1eb
CW		 1828void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1829{
1830 i915_gem_object_unpin_fence(obj);
1831 i915_gem_object_unpin(obj);
1832}
1833
c2c75131
DV		 1834/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1835 * is assumed to be a power-of-two. */
bc752862
CW		 1836unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1837 unsigned int tiling_mode,
1838 unsigned int cpp,
1839 unsigned int pitch)
c2c75131 1840{
bc752862
CW		 1841 if (tiling_mode != I915_TILING_NONE) {
1842 unsigned int tile_rows, tiles;
c2c75131 1843
bc752862
CW		 1844 tile_rows = *y / 8;
1845 *y %= 8;
c2c75131 1846
bc752862
CW		 1847 tiles = *x / (512/cpp);
1848 *x %= 512/cpp;
1849
1850 return tile_rows * pitch * 8 + tiles * 4096;
1851 } else {
1852 unsigned int offset;
1853
1854 offset = *y * pitch + *x * cpp;
1855 *y = 0;
1856 *x = (offset & 4095) / cpp;
1857 return offset & -4096;
1858 }
c2c75131
DV		 1859}
1860
17638cd6
JB		 1861static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1862 int x, int y)
81255565
JB		 1863{
1864 struct drm_device *dev = crtc->dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1867 struct intel_framebuffer *intel_fb;
05394f39 1868 struct drm_i915_gem_object *obj;
81255565 1869 int plane = intel_crtc->plane;
e506a0c6 1870 unsigned long linear_offset;
81255565 1871 u32 dspcntr;
5eddb70b 1872 u32 reg;
81255565
JB		 1873
1874 switch (plane) {
1875 case 0:
1876 case 1:
1877 break;
1878 default:
84f44ce7 1879 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1880 return -EINVAL;
1881 }
1882
1883 intel_fb = to_intel_framebuffer(fb);
1884 obj = intel_fb->obj;
81255565 1885
5eddb70b
CW		 1886 reg = DSPCNTR(plane);
1887 dspcntr = I915_READ(reg);
81255565
JB		 1888 /* Mask out pixel format bits in case we change it */
1889 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1890 switch (fb->pixel_format) {
1891 case DRM_FORMAT_C8:
81255565
JB		 1892 dspcntr |= DISPPLANE_8BPP;
1893 break;
57779d06
VS		 1894 case DRM_FORMAT_XRGB1555:
1895 case DRM_FORMAT_ARGB1555:
1896 dspcntr |= DISPPLANE_BGRX555;
81255565 1897 break;
57779d06
VS		 1898 case DRM_FORMAT_RGB565:
1899 dspcntr |= DISPPLANE_BGRX565;
1900 break;
1901 case DRM_FORMAT_XRGB8888:
1902 case DRM_FORMAT_ARGB8888:
1903 dspcntr |= DISPPLANE_BGRX888;
1904 break;
1905 case DRM_FORMAT_XBGR8888:
1906 case DRM_FORMAT_ABGR8888:
1907 dspcntr |= DISPPLANE_RGBX888;
1908 break;
1909 case DRM_FORMAT_XRGB2101010:
1910 case DRM_FORMAT_ARGB2101010:
1911 dspcntr |= DISPPLANE_BGRX101010;
1912 break;
1913 case DRM_FORMAT_XBGR2101010:
1914 case DRM_FORMAT_ABGR2101010:
1915 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1916 break;
1917 default:
baba133a 1918 BUG();
81255565 1919 }
57779d06 1920
a6c45cf0 1921 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1922 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1923 dspcntr |= DISPPLANE_TILED;
1924 else
1925 dspcntr &= ~DISPPLANE_TILED;
1926 }
1927
de1aa629
VS		 1928 if (IS_G4X(dev))
1929 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1930
5eddb70b 1931 I915_WRITE(reg, dspcntr);
81255565 1932
e506a0c6 1933 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1934
c2c75131
DV		 1935 if (INTEL_INFO(dev)->gen >= 4) {
1936 intel_crtc->dspaddr_offset =
bc752862
CW		 1937 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1938 fb->bits_per_pixel / 8,
1939 fb->pitches[0]);
c2c75131
DV		 1940 linear_offset -= intel_crtc->dspaddr_offset;
1941 } else {
e506a0c6 1942 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1943 }
e506a0c6
DV		 1944
1945 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1946 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1947 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1948 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1949 I915_MODIFY_DISPBASE(DSPSURF(plane),
1950 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1951 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1952 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1953 } else
e506a0c6 1954 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1955 POSTING_READ(reg);
81255565 1956
17638cd6
JB		 1957 return 0;
1958}
1959
1960static int ironlake_update_plane(struct drm_crtc *crtc,
1961 struct drm_framebuffer *fb, int x, int y)
1962{
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
1967 struct drm_i915_gem_object *obj;
1968 int plane = intel_crtc->plane;
e506a0c6 1969 unsigned long linear_offset;
17638cd6
JB		 1970 u32 dspcntr;
1971 u32 reg;
1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
27f8227b 1976 case 2:
17638cd6
JB		 1977 break;
1978 default:
84f44ce7 1979 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1980 return -EINVAL;
1981 }
1982
1983 intel_fb = to_intel_framebuffer(fb);
1984 obj = intel_fb->obj;
1985
1986 reg = DSPCNTR(plane);
1987 dspcntr = I915_READ(reg);
1988 /* Mask out pixel format bits in case we change it */
1989 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1990 switch (fb->pixel_format) {
1991 case DRM_FORMAT_C8:
17638cd6
JB		 1992 dspcntr |= DISPPLANE_8BPP;
1993 break;
57779d06
VS		 1994 case DRM_FORMAT_RGB565:
1995 dspcntr |= DISPPLANE_BGRX565;
17638cd6 1996 break;
57779d06
VS		 1997 case DRM_FORMAT_XRGB8888:
1998 case DRM_FORMAT_ARGB8888:
1999 dspcntr |= DISPPLANE_BGRX888;
2000 break;
2001 case DRM_FORMAT_XBGR8888:
2002 case DRM_FORMAT_ABGR8888:
2003 dspcntr |= DISPPLANE_RGBX888;
2004 break;
2005 case DRM_FORMAT_XRGB2101010:
2006 case DRM_FORMAT_ARGB2101010:
2007 dspcntr |= DISPPLANE_BGRX101010;
2008 break;
2009 case DRM_FORMAT_XBGR2101010:
2010 case DRM_FORMAT_ABGR2101010:
2011 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2012 break;
2013 default:
baba133a 2014 BUG();
17638cd6
JB		 2015 }
2016
2017 if (obj->tiling_mode != I915_TILING_NONE)
2018 dspcntr |= DISPPLANE_TILED;
2019 else
2020 dspcntr &= ~DISPPLANE_TILED;
2021
2022 /* must disable */
2023 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2024
2025 I915_WRITE(reg, dspcntr);
2026
e506a0c6 2027 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2028 intel_crtc->dspaddr_offset =
bc752862
CW		 2029 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2030 fb->bits_per_pixel / 8,
2031 fb->pitches[0]);
c2c75131 2032 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2033
e506a0c6
DV		 2034 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2035 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2036 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2037 I915_MODIFY_DISPBASE(DSPSURF(plane),
2038 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2039 if (IS_HASWELL(dev)) {
2040 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2041 } else {
2042 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2043 I915_WRITE(DSPLINOFF(plane), linear_offset);
2044 }
17638cd6
JB		 2045 POSTING_READ(reg);
2046
2047 return 0;
2048}
2049
2050/* Assume fb object is pinned & idle & fenced and just update base pointers */
2051static int
2052intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2053 int x, int y, enum mode_set_atomic state)
2054{
2055 struct drm_device *dev = crtc->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2057
6b8e6ed0
CW		 2058 if (dev_priv->display.disable_fbc)
2059 dev_priv->display.disable_fbc(dev);
3dec0095 2060 intel_increase_pllclock(crtc);
81255565 2061
6b8e6ed0 2062 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2063}
2064
96a02917
VS		 2065void intel_display_handle_reset(struct drm_device *dev)
2066{
2067 struct drm_i915_private *dev_priv = dev->dev_private;
2068 struct drm_crtc *crtc;
2069
2070 /*
2071 * Flips in the rings have been nuked by the reset,
2072 * so complete all pending flips so that user space
2073 * will get its events and not get stuck.
2074 *
2075 * Also update the base address of all primary
2076 * planes to the the last fb to make sure we're
2077 * showing the correct fb after a reset.
2078 *
2079 * Need to make two loops over the crtcs so that we
2080 * don't try to grab a crtc mutex before the
2081 * pending_flip_queue really got woken up.
2082 */
2083
2084 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2086 enum plane plane = intel_crtc->plane;
2087
2088 intel_prepare_page_flip(dev, plane);
2089 intel_finish_page_flip_plane(dev, plane);
2090 }
2091
2092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094
2095 mutex_lock(&crtc->mutex);
2096 if (intel_crtc->active)
2097 dev_priv->display.update_plane(crtc, crtc->fb,
2098 crtc->x, crtc->y);
2099 mutex_unlock(&crtc->mutex);
2100 }
2101}
2102
14667a4b
CW		 2103static int
2104intel_finish_fb(struct drm_framebuffer *old_fb)
2105{
2106 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2107 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2108 bool was_interruptible = dev_priv->mm.interruptible;
2109 int ret;
2110
14667a4b
CW		 2111 /* Big Hammer, we also need to ensure that any pending
2112 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2113 * current scanout is retired before unpinning the old
2114 * framebuffer.
2115 *
2116 * This should only fail upon a hung GPU, in which case we
2117 * can safely continue.
2118 */
2119 dev_priv->mm.interruptible = false;
2120 ret = i915_gem_object_finish_gpu(obj);
2121 dev_priv->mm.interruptible = was_interruptible;
2122
2123 return ret;
2124}
2125
198598d0
VS		 2126static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2127{
2128 struct drm_device *dev = crtc->dev;
2129 struct drm_i915_master_private *master_priv;
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131
2132 if (!dev->primary->master)
2133 return;
2134
2135 master_priv = dev->primary->master->driver_priv;
2136 if (!master_priv->sarea_priv)
2137 return;
2138
2139 switch (intel_crtc->pipe) {
2140 case 0:
2141 master_priv->sarea_priv->pipeA_x = x;
2142 master_priv->sarea_priv->pipeA_y = y;
2143 break;
2144 case 1:
2145 master_priv->sarea_priv->pipeB_x = x;
2146 master_priv->sarea_priv->pipeB_y = y;
2147 break;
2148 default:
2149 break;
2150 }
2151}
2152
5c3b82e2 2153static int
3c4fdcfb 2154intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2155 struct drm_framebuffer *fb)
79e53945
JB		 2156{
2157 struct drm_device *dev = crtc->dev;
6b8e6ed0 2158 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2160 struct drm_framebuffer *old_fb;
5c3b82e2 2161 int ret;
79e53945
JB		 2162
2163 /* no fb bound */
94352cf9 2164 if (!fb) {
a5071c2f 2165 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2166 return 0;
2167 }
2168
7eb552ae 2169 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2170 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2171 plane_name(intel_crtc->plane),
2172 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2173 return -EINVAL;
79e53945
JB		 2174 }
2175
5c3b82e2 2176 mutex_lock(&dev->struct_mutex);
265db958 2177 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2178 to_intel_framebuffer(fb)->obj,
919926ae 2179 NULL);
5c3b82e2
CW		 2180 if (ret != 0) {
2181 mutex_unlock(&dev->struct_mutex);
a5071c2f 2182 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2183 return ret;
2184 }
79e53945 2185
94352cf9 2186 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2187 if (ret) {
94352cf9 2188 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2189 mutex_unlock(&dev->struct_mutex);
a5071c2f 2190 DRM_ERROR("failed to update base address\n");
4e6cfefc 2191 return ret;
79e53945 2192 }
3c4fdcfb 2193
94352cf9
DV		 2194 old_fb = crtc->fb;
2195 crtc->fb = fb;
6c4c86f5
DV		 2196 crtc->x = x;
2197 crtc->y = y;
94352cf9 2198
b7f1de28 2199 if (old_fb) {
d7697eea
DV		 2200 if (intel_crtc->active && old_fb != fb)
2201 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2202 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2203 }
652c393a 2204
6b8e6ed0 2205 intel_update_fbc(dev);
5c3b82e2 2206 mutex_unlock(&dev->struct_mutex);
79e53945 2207
198598d0 2208 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2209
2210 return 0;
79e53945
JB		 2211}
2212
5e84e1a4
ZW		 2213static void intel_fdi_normal_train(struct drm_crtc *crtc)
2214{
2215 struct drm_device *dev = crtc->dev;
2216 struct drm_i915_private *dev_priv = dev->dev_private;
2217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2218 int pipe = intel_crtc->pipe;
2219 u32 reg, temp;
2220
2221 /* enable normal train */
2222 reg = FDI_TX_CTL(pipe);
2223 temp = I915_READ(reg);
61e499bf 2224 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2225 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2226 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2227 } else {
2228 temp &= ~FDI_LINK_TRAIN_NONE;
2229 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2230 }
5e84e1a4
ZW		 2231 I915_WRITE(reg, temp);
2232
2233 reg = FDI_RX_CTL(pipe);
2234 temp = I915_READ(reg);
2235 if (HAS_PCH_CPT(dev)) {
2236 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2237 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2238 } else {
2239 temp &= ~FDI_LINK_TRAIN_NONE;
2240 temp |= FDI_LINK_TRAIN_NONE;
2241 }
2242 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2243
2244 /* wait one idle pattern time */
2245 POSTING_READ(reg);
2246 udelay(1000);
357555c0
JB		 2247
2248 /* IVB wants error correction enabled */
2249 if (IS_IVYBRIDGE(dev))
2250 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2251 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2252}
2253
1e833f40
DV		 2254static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2255{
2256 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2257}
2258
01a415fd
DV		 2259static void ivb_modeset_global_resources(struct drm_device *dev)
2260{
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct intel_crtc *pipe_B_crtc =
2263 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2264 struct intel_crtc *pipe_C_crtc =
2265 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2266 uint32_t temp;
2267
1e833f40
DV		 2268 /*
2269 * When everything is off disable fdi C so that we could enable fdi B
2270 * with all lanes. Note that we don't care about enabled pipes without
2271 * an enabled pch encoder.
2272 */
2273 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2274 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2275 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2276 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2277
2278 temp = I915_READ(SOUTH_CHICKEN1);
2279 temp &= ~FDI_BC_BIFURCATION_SELECT;
2280 DRM_DEBUG_KMS("disabling fdi C rx\n");
2281 I915_WRITE(SOUTH_CHICKEN1, temp);
2282 }
2283}
2284
8db9d77b
ZW		 2285/* The FDI link training functions for ILK/Ibexpeak. */
2286static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2287{
2288 struct drm_device *dev = crtc->dev;
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2291 int pipe = intel_crtc->pipe;
0fc932b8 2292 int plane = intel_crtc->plane;
5eddb70b 2293 u32 reg, temp, tries;
8db9d77b 2294
0fc932b8
JB		 2295 /* FDI needs bits from pipe & plane first */
2296 assert_pipe_enabled(dev_priv, pipe);
2297 assert_plane_enabled(dev_priv, plane);
2298
e1a44743
AJ		 2299 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2300 for train result */
5eddb70b
CW		 2301 reg = FDI_RX_IMR(pipe);
2302 temp = I915_READ(reg);
e1a44743
AJ		 2303 temp &= ~FDI_RX_SYMBOL_LOCK;
2304 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2305 I915_WRITE(reg, temp);
2306 I915_READ(reg);
e1a44743
AJ		 2307 udelay(150);
2308
8db9d77b 2309 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2310 reg = FDI_TX_CTL(pipe);
2311 temp = I915_READ(reg);
627eb5a3
DV		 2312 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2313 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2314 temp &= ~FDI_LINK_TRAIN_NONE;
2315 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2316 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2317
5eddb70b
CW		 2318 reg = FDI_RX_CTL(pipe);
2319 temp = I915_READ(reg);
8db9d77b
ZW		 2320 temp &= ~FDI_LINK_TRAIN_NONE;
2321 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2323
2324 POSTING_READ(reg);
8db9d77b
ZW		 2325 udelay(150);
2326
5b2adf89 2327 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2328 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2329 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2330 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2331
5eddb70b 2332 reg = FDI_RX_IIR(pipe);
e1a44743 2333 for (tries = 0; tries < 5; tries++) {
5eddb70b 2334 temp = I915_READ(reg);
8db9d77b
ZW		 2335 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2336
2337 if ((temp & FDI_RX_BIT_LOCK)) {
2338 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2339 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2340 break;
2341 }
8db9d77b 2342 }
e1a44743 2343 if (tries == 5)
5eddb70b 2344 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2345
2346 /* Train 2 */
5eddb70b
CW		 2347 reg = FDI_TX_CTL(pipe);
2348 temp = I915_READ(reg);
8db9d77b
ZW		 2349 temp &= ~FDI_LINK_TRAIN_NONE;
2350 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2351 I915_WRITE(reg, temp);
8db9d77b 2352
5eddb70b
CW		 2353 reg = FDI_RX_CTL(pipe);
2354 temp = I915_READ(reg);
8db9d77b
ZW		 2355 temp &= ~FDI_LINK_TRAIN_NONE;
2356 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2357 I915_WRITE(reg, temp);
8db9d77b 2358
5eddb70b
CW		 2359 POSTING_READ(reg);
2360 udelay(150);
8db9d77b 2361
5eddb70b 2362 reg = FDI_RX_IIR(pipe);
e1a44743 2363 for (tries = 0; tries < 5; tries++) {
5eddb70b 2364 temp = I915_READ(reg);
8db9d77b
ZW		 2365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2366
2367 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2368 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2369 DRM_DEBUG_KMS("FDI train 2 done.\n");
2370 break;
2371 }
8db9d77b 2372 }
e1a44743 2373 if (tries == 5)
5eddb70b 2374 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2375
2376 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2377
8db9d77b
ZW		 2378}
2379
0206e353 2380static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2381 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2382 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2383 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2384 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2385};
2386
2387/* The FDI link training functions for SNB/Cougarpoint. */
2388static void gen6_fdi_link_train(struct drm_crtc *crtc)
2389{
2390 struct drm_device *dev = crtc->dev;
2391 struct drm_i915_private *dev_priv = dev->dev_private;
2392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2393 int pipe = intel_crtc->pipe;
fa37d39e 2394 u32 reg, temp, i, retry;
8db9d77b 2395
e1a44743
AJ		 2396 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2397 for train result */
5eddb70b
CW		 2398 reg = FDI_RX_IMR(pipe);
2399 temp = I915_READ(reg);
e1a44743
AJ		 2400 temp &= ~FDI_RX_SYMBOL_LOCK;
2401 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2402 I915_WRITE(reg, temp);
2403
2404 POSTING_READ(reg);
e1a44743
AJ		 2405 udelay(150);
2406
8db9d77b 2407 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2408 reg = FDI_TX_CTL(pipe);
2409 temp = I915_READ(reg);
627eb5a3
DV		 2410 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2411 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2412 temp &= ~FDI_LINK_TRAIN_NONE;
2413 temp |= FDI_LINK_TRAIN_PATTERN_1;
2414 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2415 /* SNB-B */
2416 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2417 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2418
d74cf324
DV		 2419 I915_WRITE(FDI_RX_MISC(pipe),
2420 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2421
5eddb70b
CW		 2422 reg = FDI_RX_CTL(pipe);
2423 temp = I915_READ(reg);
8db9d77b
ZW		 2424 if (HAS_PCH_CPT(dev)) {
2425 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2426 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2427 } else {
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_1;
2430 }
5eddb70b
CW		 2431 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2432
2433 POSTING_READ(reg);
8db9d77b
ZW		 2434 udelay(150);
2435
0206e353 2436 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2437 reg = FDI_TX_CTL(pipe);
2438 temp = I915_READ(reg);
8db9d77b
ZW		 2439 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2440 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2441 I915_WRITE(reg, temp);
2442
2443 POSTING_READ(reg);
8db9d77b
ZW		 2444 udelay(500);
2445
fa37d39e
SP		 2446 for (retry = 0; retry < 5; retry++) {
2447 reg = FDI_RX_IIR(pipe);
2448 temp = I915_READ(reg);
2449 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2450 if (temp & FDI_RX_BIT_LOCK) {
2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2452 DRM_DEBUG_KMS("FDI train 1 done.\n");
2453 break;
2454 }
2455 udelay(50);
8db9d77b 2456 }
fa37d39e
SP		 2457 if (retry < 5)
2458 break;
8db9d77b
ZW		 2459 }
2460 if (i == 4)
5eddb70b 2461 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2462
2463 /* Train 2 */
5eddb70b
CW		 2464 reg = FDI_TX_CTL(pipe);
2465 temp = I915_READ(reg);
8db9d77b
ZW		 2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_2;
2468 if (IS_GEN6(dev)) {
2469 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2470 /* SNB-B */
2471 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2472 }
5eddb70b 2473 I915_WRITE(reg, temp);
8db9d77b 2474
5eddb70b
CW		 2475 reg = FDI_RX_CTL(pipe);
2476 temp = I915_READ(reg);
8db9d77b
ZW		 2477 if (HAS_PCH_CPT(dev)) {
2478 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2480 } else {
2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
2483 }
5eddb70b
CW		 2484 I915_WRITE(reg, temp);
2485
2486 POSTING_READ(reg);
8db9d77b
ZW		 2487 udelay(150);
2488
0206e353 2489 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2490 reg = FDI_TX_CTL(pipe);
2491 temp = I915_READ(reg);
8db9d77b
ZW		 2492 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2494 I915_WRITE(reg, temp);
2495
2496 POSTING_READ(reg);
8db9d77b
ZW		 2497 udelay(500);
2498
fa37d39e
SP		 2499 for (retry = 0; retry < 5; retry++) {
2500 reg = FDI_RX_IIR(pipe);
2501 temp = I915_READ(reg);
2502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503 if (temp & FDI_RX_SYMBOL_LOCK) {
2504 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2505 DRM_DEBUG_KMS("FDI train 2 done.\n");
2506 break;
2507 }
2508 udelay(50);
8db9d77b 2509 }
fa37d39e
SP		 2510 if (retry < 5)
2511 break;
8db9d77b
ZW		 2512 }
2513 if (i == 4)
5eddb70b 2514 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2515
2516 DRM_DEBUG_KMS("FDI train done.\n");
2517}
2518
357555c0
JB		 2519/* Manual link training for Ivy Bridge A0 parts */
2520static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2521{
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
2526 u32 reg, temp, i;
2527
2528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2529 for train result */
2530 reg = FDI_RX_IMR(pipe);
2531 temp = I915_READ(reg);
2532 temp &= ~FDI_RX_SYMBOL_LOCK;
2533 temp &= ~FDI_RX_BIT_LOCK;
2534 I915_WRITE(reg, temp);
2535
2536 POSTING_READ(reg);
2537 udelay(150);
2538
01a415fd
DV		 2539 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2540 I915_READ(FDI_RX_IIR(pipe)));
2541
357555c0
JB		 2542 /* enable CPU FDI TX and PCH FDI RX */
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
627eb5a3
DV		 2545 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2546 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2547 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2548 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2551 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2552 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2553
d74cf324
DV		 2554 I915_WRITE(FDI_RX_MISC(pipe),
2555 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2556
357555c0
JB		 2557 reg = FDI_RX_CTL(pipe);
2558 temp = I915_READ(reg);
2559 temp &= ~FDI_LINK_TRAIN_AUTO;
2560 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2561 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2562 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
0206e353 2568 for (i = 0; i < 4; i++) {
357555c0
JB		 2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(500);
2577
2578 reg = FDI_RX_IIR(pipe);
2579 temp = I915_READ(reg);
2580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2581
2582 if (temp & FDI_RX_BIT_LOCK ||
2583 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2585 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2586 break;
2587 }
2588 }
2589 if (i == 4)
2590 DRM_ERROR("FDI train 1 fail!\n");
2591
2592 /* Train 2 */
2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
2595 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2598 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2599 I915_WRITE(reg, temp);
2600
2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
2603 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2604 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2605 I915_WRITE(reg, temp);
2606
2607 POSTING_READ(reg);
2608 udelay(150);
2609
0206e353 2610 for (i = 0; i < 4; i++) {
357555c0
JB		 2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2614 temp |= snb_b_fdi_train_param[i];
2615 I915_WRITE(reg, temp);
2616
2617 POSTING_READ(reg);
2618 udelay(500);
2619
2620 reg = FDI_RX_IIR(pipe);
2621 temp = I915_READ(reg);
2622 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2623
2624 if (temp & FDI_RX_SYMBOL_LOCK) {
2625 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2626 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2627 break;
2628 }
2629 }
2630 if (i == 4)
2631 DRM_ERROR("FDI train 2 fail!\n");
2632
2633 DRM_DEBUG_KMS("FDI train done.\n");
2634}
2635
88cefb6c 2636static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2637{
88cefb6c 2638 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2639 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2640 int pipe = intel_crtc->pipe;
5eddb70b 2641 u32 reg, temp;
79e53945 2642
c64e311e 2643
c98e9dcf 2644 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2645 reg = FDI_RX_CTL(pipe);
2646 temp = I915_READ(reg);
627eb5a3
DV		 2647 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2648 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2649 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2650 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2651
2652 POSTING_READ(reg);
c98e9dcf
JB		 2653 udelay(200);
2654
2655 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2656 temp = I915_READ(reg);
2657 I915_WRITE(reg, temp | FDI_PCDCLK);
2658
2659 POSTING_READ(reg);
c98e9dcf
JB		 2660 udelay(200);
2661
20749730
PZ		 2662 /* Enable CPU FDI TX PLL, always on for Ironlake */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2666 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2667
20749730
PZ		 2668 POSTING_READ(reg);
2669 udelay(100);
6be4a607 2670 }
0e23b99d
JB		 2671}
2672
88cefb6c
DV		 2673static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2674{
2675 struct drm_device *dev = intel_crtc->base.dev;
2676 struct drm_i915_private *dev_priv = dev->dev_private;
2677 int pipe = intel_crtc->pipe;
2678 u32 reg, temp;
2679
2680 /* Switch from PCDclk to Rawclk */
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2684
2685 /* Disable CPU FDI TX PLL */
2686 reg = FDI_TX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2689
2690 POSTING_READ(reg);
2691 udelay(100);
2692
2693 reg = FDI_RX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2696
2697 /* Wait for the clocks to turn off. */
2698 POSTING_READ(reg);
2699 udelay(100);
2700}
2701
0fc932b8
JB		 2702static void ironlake_fdi_disable(struct drm_crtc *crtc)
2703{
2704 struct drm_device *dev = crtc->dev;
2705 struct drm_i915_private *dev_priv = dev->dev_private;
2706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2707 int pipe = intel_crtc->pipe;
2708 u32 reg, temp;
2709
2710 /* disable CPU FDI tx and PCH FDI rx */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2714 POSTING_READ(reg);
2715
2716 reg = FDI_RX_CTL(pipe);
2717 temp = I915_READ(reg);
2718 temp &= ~(0x7 << 16);
dfd07d72 2719 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2720 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2721
2722 POSTING_READ(reg);
2723 udelay(100);
2724
2725 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2726 if (HAS_PCH_IBX(dev)) {
2727 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2728 }
0fc932b8
JB		 2729
2730 /* still set train pattern 1 */
2731 reg = FDI_TX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~FDI_LINK_TRAIN_NONE;
2734 temp |= FDI_LINK_TRAIN_PATTERN_1;
2735 I915_WRITE(reg, temp);
2736
2737 reg = FDI_RX_CTL(pipe);
2738 temp = I915_READ(reg);
2739 if (HAS_PCH_CPT(dev)) {
2740 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2741 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2742 } else {
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_PATTERN_1;
2745 }
2746 /* BPC in FDI rx is consistent with that in PIPECONF */
2747 temp &= ~(0x07 << 16);
dfd07d72 2748 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2749 I915_WRITE(reg, temp);
2750
2751 POSTING_READ(reg);
2752 udelay(100);
2753}
2754
5bb61643
CW		 2755static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2756{
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2760 unsigned long flags;
2761 bool pending;
2762
10d83730
VS		 2763 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2764 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2765 return false;
2766
2767 spin_lock_irqsave(&dev->event_lock, flags);
2768 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2769 spin_unlock_irqrestore(&dev->event_lock, flags);
2770
2771 return pending;
2772}
2773
e6c3a2a6
CW		 2774static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2775{
0f91128d 2776 struct drm_device *dev = crtc->dev;
5bb61643 2777 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2778
2779 if (crtc->fb == NULL)
2780 return;
2781
2c10d571
DV		 2782 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2783
5bb61643
CW		 2784 wait_event(dev_priv->pending_flip_queue,
2785 !intel_crtc_has_pending_flip(crtc));
2786
0f91128d
CW		 2787 mutex_lock(&dev->struct_mutex);
2788 intel_finish_fb(crtc->fb);
2789 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2790}
2791
e615efe4
ED		 2792/* Program iCLKIP clock to the desired frequency */
2793static void lpt_program_iclkip(struct drm_crtc *crtc)
2794{
2795 struct drm_device *dev = crtc->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2798 u32 temp;
2799
09153000
DV		 2800 mutex_lock(&dev_priv->dpio_lock);
2801
e615efe4
ED		 2802 /* It is necessary to ungate the pixclk gate prior to programming
2803 * the divisors, and gate it back when it is done.
2804 */
2805 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2806
2807 /* Disable SSCCTL */
2808 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2809 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2810 SBI_SSCCTL_DISABLE,
2811 SBI_ICLK);
e615efe4
ED		 2812
2813 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2814 if (crtc->mode.clock == 20000) {
2815 auxdiv = 1;
2816 divsel = 0x41;
2817 phaseinc = 0x20;
2818 } else {
2819 /* The iCLK virtual clock root frequency is in MHz,
2820 * but the crtc->mode.clock in in KHz. To get the divisors,
2821 * it is necessary to divide one by another, so we
2822 * convert the virtual clock precision to KHz here for higher
2823 * precision.
2824 */
2825 u32 iclk_virtual_root_freq = 172800 * 1000;
2826 u32 iclk_pi_range = 64;
2827 u32 desired_divisor, msb_divisor_value, pi_value;
2828
2829 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2830 msb_divisor_value = desired_divisor / iclk_pi_range;
2831 pi_value = desired_divisor % iclk_pi_range;
2832
2833 auxdiv = 0;
2834 divsel = msb_divisor_value - 2;
2835 phaseinc = pi_value;
2836 }
2837
2838 /* This should not happen with any sane values */
2839 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2840 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2841 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2842 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2843
2844 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2845 crtc->mode.clock,
2846 auxdiv,
2847 divsel,
2848 phasedir,
2849 phaseinc);
2850
2851 /* Program SSCDIVINTPHASE6 */
988d6ee8 2852 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2853 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2854 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2855 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2856 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2857 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2858 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2859 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2860
2861 /* Program SSCAUXDIV */
988d6ee8 2862 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2863 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2864 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2865 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2866
2867 /* Enable modulator and associated divider */
988d6ee8 2868 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2869 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2870 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2871
2872 /* Wait for initialization time */
2873 udelay(24);
2874
2875 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2876
2877 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2878}
2879
275f01b2
DV		 2880static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2881 enum pipe pch_transcoder)
2882{
2883 struct drm_device *dev = crtc->base.dev;
2884 struct drm_i915_private *dev_priv = dev->dev_private;
2885 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2886
2887 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2888 I915_READ(HTOTAL(cpu_transcoder)));
2889 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2890 I915_READ(HBLANK(cpu_transcoder)));
2891 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2892 I915_READ(HSYNC(cpu_transcoder)));
2893
2894 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2895 I915_READ(VTOTAL(cpu_transcoder)));
2896 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2897 I915_READ(VBLANK(cpu_transcoder)));
2898 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2899 I915_READ(VSYNC(cpu_transcoder)));
2900 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2901 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2902}
2903
f67a559d
JB		 2904/*
2905 * Enable PCH resources required for PCH ports:
2906 * - PCH PLLs
2907 * - FDI training & RX/TX
2908 * - update transcoder timings
2909 * - DP transcoding bits
2910 * - transcoder
2911 */
2912static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2913{
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2917 int pipe = intel_crtc->pipe;
ee7b9f93 2918 u32 reg, temp;
2c07245f 2919
ab9412ba 2920 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2921
cd986abb
DV		 2922 /* Write the TU size bits before fdi link training, so that error
2923 * detection works. */
2924 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2925 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2926
c98e9dcf 2927 /* For PCH output, training FDI link */
674cf967 2928 dev_priv->display.fdi_link_train(crtc);
2c07245f 2929
572deb37
DV		 2930 /* XXX: pch pll's can be enabled any time before we enable the PCH
2931 * transcoder, and we actually should do this to not upset any PCH
2932 * transcoder that already use the clock when we share it.
2933 *
e72f9fbf
DV		 2934 * Note that enable_shared_dpll tries to do the right thing, but
2935 * get_shared_dpll unconditionally resets the pll - we need that to have
2936 * the right LVDS enable sequence. */
2937 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2938
303b81e0 2939 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2940 u32 sel;
4b645f14 2941
c98e9dcf 2942 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2943 temp |= TRANS_DPLL_ENABLE(pipe);
2944 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2945 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2946 temp |= sel;
2947 else
2948 temp &= ~sel;
c98e9dcf 2949 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2950 }
5eddb70b 2951
d9b6cb56
JB		 2952 /* set transcoder timing, panel must allow it */
2953 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2954 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2955
303b81e0 2956 intel_fdi_normal_train(crtc);
5e84e1a4 2957
c98e9dcf
JB		 2958 /* For PCH DP, enable TRANS_DP_CTL */
2959 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2960 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2961 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2962 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2963 reg = TRANS_DP_CTL(pipe);
2964 temp = I915_READ(reg);
2965 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2966 TRANS_DP_SYNC_MASK |
2967 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2968 temp |= (TRANS_DP_OUTPUT_ENABLE |
2969 TRANS_DP_ENH_FRAMING);
9325c9f0 2970 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2971
2972 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2973 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2974 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2975 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2976
2977 switch (intel_trans_dp_port_sel(crtc)) {
2978 case PCH_DP_B:
5eddb70b 2979 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2980 break;
2981 case PCH_DP_C:
5eddb70b 2982 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2983 break;
2984 case PCH_DP_D:
5eddb70b 2985 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2986 break;
2987 default:
e95d41e1 2988 BUG();
32f9d658 2989 }
2c07245f 2990
5eddb70b 2991 I915_WRITE(reg, temp);
6be4a607 2992 }
b52eb4dc 2993
b8a4f404 2994 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 2995}
2996
1507e5bd
PZ		 2997static void lpt_pch_enable(struct drm_crtc *crtc)
2998{
2999 struct drm_device *dev = crtc->dev;
3000 struct drm_i915_private *dev_priv = dev->dev_private;
3001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3002 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3003
ab9412ba 3004 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3005
8c52b5e8 3006 lpt_program_iclkip(crtc);
1507e5bd 3007
0540e488 3008 /* Set transcoder timing. */
275f01b2 3009 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3010
937bb610 3011 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3012}
3013
e2b78267 3014static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3015{
e2b78267 3016 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3017
3018 if (pll == NULL)
3019 return;
3020
3021 if (pll->refcount == 0) {
46edb027 3022 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3023 return;
3024 }
3025
f4a091c7
DV		 3026 if (--pll->refcount == 0) {
3027 WARN_ON(pll->on);
3028 WARN_ON(pll->active);
3029 }
3030
a43f6e0f 3031 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3032}
3033
e2b78267 3034static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
ee7b9f93 3035{
e2b78267
DV		 3036 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3037 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3038 enum intel_dpll_id i;
ee7b9f93 3039
ee7b9f93 3040 if (pll) {
46edb027
DV		 3041 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3042 crtc->base.base.id, pll->name);
e2b78267 3043 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3044 }
3045
98b6bd99
DV		 3046 if (HAS_PCH_IBX(dev_priv->dev)) {
3047 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
e2b78267 3048 i = crtc->pipe;
e72f9fbf 3049 pll = &dev_priv->shared_dplls[i];
98b6bd99 3050
46edb027
DV		 3051 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3052 crtc->base.base.id, pll->name);
98b6bd99
DV		 3053
3054 goto found;
3055 }
3056
e72f9fbf
DV		 3057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3058 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3059
3060 /* Only want to check enabled timings first */
3061 if (pll->refcount == 0)
3062 continue;
3063
e9a632a5
DV		 3064 if (dpll == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3065 fp == I915_READ(PCH_FP0(pll->id))) {
46edb027 3066 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3067 crtc->base.base.id,
46edb027 3068 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3069
3070 goto found;
3071 }
3072 }
3073
3074 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3075 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3076 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3077 if (pll->refcount == 0) {
46edb027
DV		 3078 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3079 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3080 goto found;
3081 }
3082 }
3083
3084 return NULL;
3085
3086found:
a43f6e0f 3087 crtc->config.shared_dpll = i;
46edb027
DV		 3088 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3089 pipe_name(crtc->pipe));
ee7b9f93 3090
cdbd2316 3091 if (pll->active == 0) {
66e985c0
DV		 3092 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3093 sizeof(pll->hw_state));
3094
46edb027 3095 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3096 WARN_ON(pll->on);
e9d6944e 3097 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3098
cdbd2316 3099 /* Wait for the clocks to stabilize before rewriting the regs */
e9a632a5
DV		 3100 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3101 POSTING_READ(PCH_DPLL(pll->id));
cdbd2316
DV		 3102 udelay(150);
3103
e9a632a5
DV		 3104 I915_WRITE(PCH_FP0(pll->id), fp);
3105 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
cdbd2316
DV		 3106 }
3107 pll->refcount++;
e04c7350 3108
ee7b9f93
JB		 3109 return pll;
3110}
3111
a1520318 3112static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3113{
3114 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3115 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3116 u32 temp;
3117
3118 temp = I915_READ(dslreg);
3119 udelay(500);
3120 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3121 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3122 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3123 }
3124}
3125
b074cec8
JB		 3126static void ironlake_pfit_enable(struct intel_crtc *crtc)
3127{
3128 struct drm_device *dev = crtc->base.dev;
3129 struct drm_i915_private *dev_priv = dev->dev_private;
3130 int pipe = crtc->pipe;
3131
0ef37f3f 3132 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3133 /* Force use of hard-coded filter coefficients
3134 * as some pre-programmed values are broken,
3135 * e.g. x201.
3136 */
3137 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3138 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3139 PF_PIPE_SEL_IVB(pipe));
3140 else
3141 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3142 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3143 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3144 }
3145}
3146
bb53d4ae
VS		 3147static void intel_enable_planes(struct drm_crtc *crtc)
3148{
3149 struct drm_device *dev = crtc->dev;
3150 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3151 struct intel_plane *intel_plane;
3152
3153 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3154 if (intel_plane->pipe == pipe)
3155 intel_plane_restore(&intel_plane->base);
3156}
3157
3158static void intel_disable_planes(struct drm_crtc *crtc)
3159{
3160 struct drm_device *dev = crtc->dev;
3161 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3162 struct intel_plane *intel_plane;
3163
3164 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3165 if (intel_plane->pipe == pipe)
3166 intel_plane_disable(&intel_plane->base);
3167}
3168
f67a559d
JB		 3169static void ironlake_crtc_enable(struct drm_crtc *crtc)
3170{
3171 struct drm_device *dev = crtc->dev;
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3174 struct intel_encoder *encoder;
f67a559d
JB		 3175 int pipe = intel_crtc->pipe;
3176 int plane = intel_crtc->plane;
3177 u32 temp;
f67a559d 3178
08a48469
DV		 3179 WARN_ON(!crtc->enabled);
3180
f67a559d
JB		 3181 if (intel_crtc->active)
3182 return;
3183
3184 intel_crtc->active = true;
8664281b
PZ		 3185
3186 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3187 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3188
f67a559d
JB		 3189 intel_update_watermarks(dev);
3190
3191 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3192 temp = I915_READ(PCH_LVDS);
3193 if ((temp & LVDS_PORT_EN) == 0)
3194 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3195 }
3196
f67a559d 3197
5bfe2ac0 3198 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3199 /* Note: FDI PLL enabling _must_ be done before we enable the
3200 * cpu pipes, hence this is separate from all the other fdi/pch
3201 * enabling. */
88cefb6c 3202 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3203 } else {
3204 assert_fdi_tx_disabled(dev_priv, pipe);
3205 assert_fdi_rx_disabled(dev_priv, pipe);
3206 }
f67a559d 3207
bf49ec8c
DV		 3208 for_each_encoder_on_crtc(dev, crtc, encoder)
3209 if (encoder->pre_enable)
3210 encoder->pre_enable(encoder);
f67a559d 3211
b074cec8 3212 ironlake_pfit_enable(intel_crtc);
f67a559d 3213
9c54c0dd
JB		 3214 /*
3215 * On ILK+ LUT must be loaded before the pipe is running but with
3216 * clocks enabled
3217 */
3218 intel_crtc_load_lut(crtc);
3219
5bfe2ac0
DV		 3220 intel_enable_pipe(dev_priv, pipe,
3221 intel_crtc->config.has_pch_encoder);
f67a559d 3222 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3223 intel_enable_planes(crtc);
5c38d48c 3224 intel_crtc_update_cursor(crtc, true);
f67a559d 3225
5bfe2ac0 3226 if (intel_crtc->config.has_pch_encoder)
f67a559d 3227 ironlake_pch_enable(crtc);
c98e9dcf 3228
d1ebd816 3229 mutex_lock(&dev->struct_mutex);
bed4a673 3230 intel_update_fbc(dev);
d1ebd816
BW		 3231 mutex_unlock(&dev->struct_mutex);
3232
fa5c73b1
DV		 3233 for_each_encoder_on_crtc(dev, crtc, encoder)
3234 encoder->enable(encoder);
61b77ddd
DV		 3235
3236 if (HAS_PCH_CPT(dev))
a1520318 3237 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3238
3239 /*
3240 * There seems to be a race in PCH platform hw (at least on some
3241 * outputs) where an enabled pipe still completes any pageflip right
3242 * away (as if the pipe is off) instead of waiting for vblank. As soon
3243 * as the first vblank happend, everything works as expected. Hence just
3244 * wait for one vblank before returning to avoid strange things
3245 * happening.
3246 */
3247 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3248}
3249
42db64ef
PZ		 3250/* IPS only exists on ULT machines and is tied to pipe A. */
3251static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3252{
f5adf94e 3253 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3254}
3255
3256static void hsw_enable_ips(struct intel_crtc *crtc)
3257{
3258 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3259
3260 if (!crtc->config.ips_enabled)
3261 return;
3262
3263 /* We can only enable IPS after we enable a plane and wait for a vblank.
3264 * We guarantee that the plane is enabled by calling intel_enable_ips
3265 * only after intel_enable_plane. And intel_enable_plane already waits
3266 * for a vblank, so all we need to do here is to enable the IPS bit. */
3267 assert_plane_enabled(dev_priv, crtc->plane);
3268 I915_WRITE(IPS_CTL, IPS_ENABLE);
3269}
3270
3271static void hsw_disable_ips(struct intel_crtc *crtc)
3272{
3273 struct drm_device *dev = crtc->base.dev;
3274 struct drm_i915_private *dev_priv = dev->dev_private;
3275
3276 if (!crtc->config.ips_enabled)
3277 return;
3278
3279 assert_plane_enabled(dev_priv, crtc->plane);
3280 I915_WRITE(IPS_CTL, 0);
3281
3282 /* We need to wait for a vblank before we can disable the plane. */
3283 intel_wait_for_vblank(dev, crtc->pipe);
3284}
3285
4f771f10
PZ		 3286static void haswell_crtc_enable(struct drm_crtc *crtc)
3287{
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3291 struct intel_encoder *encoder;
3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
4f771f10
PZ		 3294
3295 WARN_ON(!crtc->enabled);
3296
3297 if (intel_crtc->active)
3298 return;
3299
3300 intel_crtc->active = true;
8664281b
PZ		 3301
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 if (intel_crtc->config.has_pch_encoder)
3304 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3305
4f771f10
PZ		 3306 intel_update_watermarks(dev);
3307
5bfe2ac0 3308 if (intel_crtc->config.has_pch_encoder)
04945641 3309 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3310
3311 for_each_encoder_on_crtc(dev, crtc, encoder)
3312 if (encoder->pre_enable)
3313 encoder->pre_enable(encoder);
3314
1f544388 3315 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3316
b074cec8 3317 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3318
3319 /*
3320 * On ILK+ LUT must be loaded before the pipe is running but with
3321 * clocks enabled
3322 */
3323 intel_crtc_load_lut(crtc);
3324
1f544388 3325 intel_ddi_set_pipe_settings(crtc);
8228c251 3326 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3327
5bfe2ac0
DV		 3328 intel_enable_pipe(dev_priv, pipe,
3329 intel_crtc->config.has_pch_encoder);
4f771f10 3330 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3331 intel_enable_planes(crtc);
5c38d48c 3332 intel_crtc_update_cursor(crtc, true);
4f771f10 3333
42db64ef
PZ		 3334 hsw_enable_ips(intel_crtc);
3335
5bfe2ac0 3336 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3337 lpt_pch_enable(crtc);
4f771f10
PZ		 3338
3339 mutex_lock(&dev->struct_mutex);
3340 intel_update_fbc(dev);
3341 mutex_unlock(&dev->struct_mutex);
3342
4f771f10
PZ		 3343 for_each_encoder_on_crtc(dev, crtc, encoder)
3344 encoder->enable(encoder);
3345
4f771f10
PZ		 3346 /*
3347 * There seems to be a race in PCH platform hw (at least on some
3348 * outputs) where an enabled pipe still completes any pageflip right
3349 * away (as if the pipe is off) instead of waiting for vblank. As soon
3350 * as the first vblank happend, everything works as expected. Hence just
3351 * wait for one vblank before returning to avoid strange things
3352 * happening.
3353 */
3354 intel_wait_for_vblank(dev, intel_crtc->pipe);
3355}
3356
3f8dce3a
DV		 3357static void ironlake_pfit_disable(struct intel_crtc *crtc)
3358{
3359 struct drm_device *dev = crtc->base.dev;
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 int pipe = crtc->pipe;
3362
3363 /* To avoid upsetting the power well on haswell only disable the pfit if
3364 * it's in use. The hw state code will make sure we get this right. */
3365 if (crtc->config.pch_pfit.size) {
3366 I915_WRITE(PF_CTL(pipe), 0);
3367 I915_WRITE(PF_WIN_POS(pipe), 0);
3368 I915_WRITE(PF_WIN_SZ(pipe), 0);
3369 }
3370}
3371
6be4a607
JB		 3372static void ironlake_crtc_disable(struct drm_crtc *crtc)
3373{
3374 struct drm_device *dev = crtc->dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3377 struct intel_encoder *encoder;
6be4a607
JB		 3378 int pipe = intel_crtc->pipe;
3379 int plane = intel_crtc->plane;
5eddb70b 3380 u32 reg, temp;
b52eb4dc 3381
ef9c3aee 3382
f7abfe8b
CW		 3383 if (!intel_crtc->active)
3384 return;
3385
ea9d758d
DV		 3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->disable(encoder);
3388
e6c3a2a6 3389 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3390 drm_vblank_off(dev, pipe);
913d8d11 3391
973d04f9
CW		 3392 if (dev_priv->cfb_plane == plane)
3393 intel_disable_fbc(dev);
2c07245f 3394
0d5b8c61 3395 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3396 intel_disable_planes(crtc);
0d5b8c61
VS		 3397 intel_disable_plane(dev_priv, plane, pipe);
3398
d925c59a
DV		 3399 if (intel_crtc->config.has_pch_encoder)
3400 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3401
b24e7179 3402 intel_disable_pipe(dev_priv, pipe);
32f9d658 3403
3f8dce3a 3404 ironlake_pfit_disable(intel_crtc);
2c07245f 3405
bf49ec8c
DV		 3406 for_each_encoder_on_crtc(dev, crtc, encoder)
3407 if (encoder->post_disable)
3408 encoder->post_disable(encoder);
2c07245f 3409
d925c59a
DV		 3410 if (intel_crtc->config.has_pch_encoder) {
3411 ironlake_fdi_disable(crtc);
913d8d11 3412
d925c59a
DV		 3413 ironlake_disable_pch_transcoder(dev_priv, pipe);
3414 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3415
d925c59a
DV		 3416 if (HAS_PCH_CPT(dev)) {
3417 /* disable TRANS_DP_CTL */
3418 reg = TRANS_DP_CTL(pipe);
3419 temp = I915_READ(reg);
3420 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3421 TRANS_DP_PORT_SEL_MASK);
3422 temp |= TRANS_DP_PORT_SEL_NONE;
3423 I915_WRITE(reg, temp);
3424
3425 /* disable DPLL_SEL */
3426 temp = I915_READ(PCH_DPLL_SEL);
11887397 3427 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3428 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3429 }
e3421a18 3430
d925c59a 3431 /* disable PCH DPLL */
e72f9fbf 3432 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3433
d925c59a
DV		 3434 ironlake_fdi_pll_disable(intel_crtc);
3435 }
6b383a7f 3436
f7abfe8b 3437 intel_crtc->active = false;
6b383a7f 3438 intel_update_watermarks(dev);
d1ebd816
BW		 3439
3440 mutex_lock(&dev->struct_mutex);
6b383a7f 3441 intel_update_fbc(dev);
d1ebd816 3442 mutex_unlock(&dev->struct_mutex);
6be4a607 3443}
1b3c7a47 3444
4f771f10 3445static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3446{
4f771f10
PZ		 3447 struct drm_device *dev = crtc->dev;
3448 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3450 struct intel_encoder *encoder;
3451 int pipe = intel_crtc->pipe;
3452 int plane = intel_crtc->plane;
3b117c8f 3453 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3454
4f771f10
PZ		 3455 if (!intel_crtc->active)
3456 return;
3457
3458 for_each_encoder_on_crtc(dev, crtc, encoder)
3459 encoder->disable(encoder);
3460
3461 intel_crtc_wait_for_pending_flips(crtc);
3462 drm_vblank_off(dev, pipe);
4f771f10 3463
891348b2 3464 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3465 if (dev_priv->cfb_plane == plane)
3466 intel_disable_fbc(dev);
3467
42db64ef
PZ		 3468 hsw_disable_ips(intel_crtc);
3469
0d5b8c61 3470 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3471 intel_disable_planes(crtc);
891348b2
RV		 3472 intel_disable_plane(dev_priv, plane, pipe);
3473
8664281b
PZ		 3474 if (intel_crtc->config.has_pch_encoder)
3475 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3476 intel_disable_pipe(dev_priv, pipe);
3477
ad80a810 3478 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3479
3f8dce3a 3480 ironlake_pfit_disable(intel_crtc);
4f771f10 3481
1f544388 3482 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3483
3484 for_each_encoder_on_crtc(dev, crtc, encoder)
3485 if (encoder->post_disable)
3486 encoder->post_disable(encoder);
3487
88adfff1 3488 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3489 lpt_disable_pch_transcoder(dev_priv);
8664281b 3490 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3491 intel_ddi_fdi_disable(crtc);
83616634 3492 }
4f771f10
PZ		 3493
3494 intel_crtc->active = false;
3495 intel_update_watermarks(dev);
3496
3497 mutex_lock(&dev->struct_mutex);
3498 intel_update_fbc(dev);
3499 mutex_unlock(&dev->struct_mutex);
3500}
3501
ee7b9f93
JB		 3502static void ironlake_crtc_off(struct drm_crtc *crtc)
3503{
3504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3505 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3506}
3507
6441ab5f
PZ		 3508static void haswell_crtc_off(struct drm_crtc *crtc)
3509{
3510 intel_ddi_put_crtc_pll(crtc);
3511}
3512
02e792fb
DV		 3513static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3514{
02e792fb 3515 if (!enable && intel_crtc->overlay) {
23f09ce3 3516 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3517 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3518
23f09ce3 3519 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3520 dev_priv->mm.interruptible = false;
3521 (void) intel_overlay_switch_off(intel_crtc->overlay);
3522 dev_priv->mm.interruptible = true;
23f09ce3 3523 mutex_unlock(&dev->struct_mutex);
02e792fb 3524 }
02e792fb 3525
5dcdbcb0
CW		 3526 /* Let userspace switch the overlay on again. In most cases userspace
3527 * has to recompute where to put it anyway.
3528 */
02e792fb
DV		 3529}
3530
61bc95c1
EE		 3531/**
3532 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3533 * cursor plane briefly if not already running after enabling the display
3534 * plane.
3535 * This workaround avoids occasional blank screens when self refresh is
3536 * enabled.
3537 */
3538static void
3539g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3540{
3541 u32 cntl = I915_READ(CURCNTR(pipe));
3542
3543 if ((cntl & CURSOR_MODE) == 0) {
3544 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3545
3546 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3547 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3548 intel_wait_for_vblank(dev_priv->dev, pipe);
3549 I915_WRITE(CURCNTR(pipe), cntl);
3550 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3551 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3552 }
3553}
3554
2dd24552
JB		 3555static void i9xx_pfit_enable(struct intel_crtc *crtc)
3556{
3557 struct drm_device *dev = crtc->base.dev;
3558 struct drm_i915_private *dev_priv = dev->dev_private;
3559 struct intel_crtc_config *pipe_config = &crtc->config;
3560
328d8e82 3561 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3562 return;
3563
2dd24552 3564 /*
c0b03411
DV		 3565 * The panel fitter should only be adjusted whilst the pipe is disabled,
3566 * according to register description and PRM.
2dd24552 3567 */
c0b03411
DV		 3568 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3569 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3570
b074cec8
JB		 3571 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3572 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3573
3574 /* Border color in case we don't scale up to the full screen. Black by
3575 * default, change to something else for debugging. */
3576 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3577}
3578
89b667f8
JB		 3579static void valleyview_crtc_enable(struct drm_crtc *crtc)
3580{
3581 struct drm_device *dev = crtc->dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3584 struct intel_encoder *encoder;
3585 int pipe = intel_crtc->pipe;
3586 int plane = intel_crtc->plane;
3587
3588 WARN_ON(!crtc->enabled);
3589
3590 if (intel_crtc->active)
3591 return;
3592
3593 intel_crtc->active = true;
3594 intel_update_watermarks(dev);
3595
3596 mutex_lock(&dev_priv->dpio_lock);
3597
3598 for_each_encoder_on_crtc(dev, crtc, encoder)
3599 if (encoder->pre_pll_enable)
3600 encoder->pre_pll_enable(encoder);
3601
3602 intel_enable_pll(dev_priv, pipe);
3603
3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 if (encoder->pre_enable)
3606 encoder->pre_enable(encoder);
3607
3608 /* VLV wants encoder enabling _before_ the pipe is up. */
3609 for_each_encoder_on_crtc(dev, crtc, encoder)
3610 encoder->enable(encoder);
3611
2dd24552
JB		 3612 i9xx_pfit_enable(intel_crtc);
3613
63cbb074
VS		 3614 intel_crtc_load_lut(crtc);
3615
89b667f8
JB		 3616 intel_enable_pipe(dev_priv, pipe, false);
3617 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3618 intel_enable_planes(crtc);
5c38d48c 3619 intel_crtc_update_cursor(crtc, true);
89b667f8 3620
89b667f8
JB		 3621 intel_update_fbc(dev);
3622
89b667f8
JB		 3623 mutex_unlock(&dev_priv->dpio_lock);
3624}
3625
0b8765c6 3626static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3627{
3628 struct drm_device *dev = crtc->dev;
79e53945
JB		 3629 struct drm_i915_private *dev_priv = dev->dev_private;
3630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3631 struct intel_encoder *encoder;
79e53945 3632 int pipe = intel_crtc->pipe;
80824003 3633 int plane = intel_crtc->plane;
79e53945 3634
08a48469
DV		 3635 WARN_ON(!crtc->enabled);
3636
f7abfe8b
CW		 3637 if (intel_crtc->active)
3638 return;
3639
3640 intel_crtc->active = true;
6b383a7f
CW		 3641 intel_update_watermarks(dev);
3642
63d7bbe9 3643 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3644
3645 for_each_encoder_on_crtc(dev, crtc, encoder)
3646 if (encoder->pre_enable)
3647 encoder->pre_enable(encoder);
3648
2dd24552
JB		 3649 i9xx_pfit_enable(intel_crtc);
3650
63cbb074
VS		 3651 intel_crtc_load_lut(crtc);
3652
040484af 3653 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3654 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3655 intel_enable_planes(crtc);
22e407d7 3656 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3657 if (IS_G4X(dev))
3658 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3659 intel_crtc_update_cursor(crtc, true);
79e53945 3660
0b8765c6
JB		 3661 /* Give the overlay scaler a chance to enable if it's on this pipe */
3662 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3663
f440eb13 3664 intel_update_fbc(dev);
ef9c3aee 3665
fa5c73b1
DV		 3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 encoder->enable(encoder);
0b8765c6 3668}
79e53945 3669
87476d63
DV		 3670static void i9xx_pfit_disable(struct intel_crtc *crtc)
3671{
3672 struct drm_device *dev = crtc->base.dev;
3673 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3674
328d8e82
DV		 3675 if (!crtc->config.gmch_pfit.control)
3676 return;
87476d63 3677
328d8e82 3678 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3679
328d8e82
DV		 3680 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3681 I915_READ(PFIT_CONTROL));
3682 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3683}
3684
0b8765c6
JB		 3685static void i9xx_crtc_disable(struct drm_crtc *crtc)
3686{
3687 struct drm_device *dev = crtc->dev;
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3690 struct intel_encoder *encoder;
0b8765c6
JB		 3691 int pipe = intel_crtc->pipe;
3692 int plane = intel_crtc->plane;
ef9c3aee 3693
f7abfe8b
CW		 3694 if (!intel_crtc->active)
3695 return;
3696
ea9d758d
DV		 3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 encoder->disable(encoder);
3699
0b8765c6 3700 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3701 intel_crtc_wait_for_pending_flips(crtc);
3702 drm_vblank_off(dev, pipe);
0b8765c6 3703
973d04f9
CW		 3704 if (dev_priv->cfb_plane == plane)
3705 intel_disable_fbc(dev);
79e53945 3706
0d5b8c61
VS		 3707 intel_crtc_dpms_overlay(intel_crtc, false);
3708 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3709 intel_disable_planes(crtc);
b24e7179 3710 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3711
b24e7179 3712 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3713
87476d63 3714 i9xx_pfit_disable(intel_crtc);
24a1f16d 3715
89b667f8
JB		 3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->post_disable)
3718 encoder->post_disable(encoder);
3719
63d7bbe9 3720 intel_disable_pll(dev_priv, pipe);
0b8765c6 3721
f7abfe8b 3722 intel_crtc->active = false;
6b383a7f
CW		 3723 intel_update_fbc(dev);
3724 intel_update_watermarks(dev);
0b8765c6
JB		 3725}
3726
ee7b9f93
JB		 3727static void i9xx_crtc_off(struct drm_crtc *crtc)
3728{
3729}
3730
976f8a20
DV		 3731static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3732 bool enabled)
2c07245f
ZW		 3733{
3734 struct drm_device *dev = crtc->dev;
3735 struct drm_i915_master_private *master_priv;
3736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3737 int pipe = intel_crtc->pipe;
79e53945
JB		 3738
3739 if (!dev->primary->master)
3740 return;
3741
3742 master_priv = dev->primary->master->driver_priv;
3743 if (!master_priv->sarea_priv)
3744 return;
3745
79e53945
JB		 3746 switch (pipe) {
3747 case 0:
3748 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3749 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3750 break;
3751 case 1:
3752 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3753 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3754 break;
3755 default:
9db4a9c7 3756 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3757 break;
3758 }
79e53945
JB		 3759}
3760
976f8a20
DV		 3761/**
3762 * Sets the power management mode of the pipe and plane.
3763 */
3764void intel_crtc_update_dpms(struct drm_crtc *crtc)
3765{
3766 struct drm_device *dev = crtc->dev;
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768 struct intel_encoder *intel_encoder;
3769 bool enable = false;
3770
3771 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3772 enable |= intel_encoder->connectors_active;
3773
3774 if (enable)
3775 dev_priv->display.crtc_enable(crtc);
3776 else
3777 dev_priv->display.crtc_disable(crtc);
3778
3779 intel_crtc_update_sarea(crtc, enable);
3780}
3781
cdd59983
CW		 3782static void intel_crtc_disable(struct drm_crtc *crtc)
3783{
cdd59983 3784 struct drm_device *dev = crtc->dev;
976f8a20 3785 struct drm_connector *connector;
ee7b9f93 3786 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3788
976f8a20
DV		 3789 /* crtc should still be enabled when we disable it. */
3790 WARN_ON(!crtc->enabled);
3791
3792 dev_priv->display.crtc_disable(crtc);
c77bf565 3793 intel_crtc->eld_vld = false;
976f8a20 3794 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3795 dev_priv->display.off(crtc);
3796
931872fc
CW		 3797 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3798 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3799
3800 if (crtc->fb) {
3801 mutex_lock(&dev->struct_mutex);
1690e1eb 3802 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3803 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3804 crtc->fb = NULL;
3805 }
3806
3807 /* Update computed state. */
3808 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3809 if (!connector->encoder || !connector->encoder->crtc)
3810 continue;
3811
3812 if (connector->encoder->crtc != crtc)
3813 continue;
3814
3815 connector->dpms = DRM_MODE_DPMS_OFF;
3816 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3817 }
3818}
3819
a261b246 3820void intel_modeset_disable(struct drm_device *dev)
79e53945 3821{
a261b246
DV		 3822 struct drm_crtc *crtc;
3823
3824 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3825 if (crtc->enabled)
3826 intel_crtc_disable(crtc);
3827 }
79e53945
JB		 3828}
3829
ea5b213a 3830void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3831{
4ef69c7a 3832 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3833
ea5b213a
CW		 3834 drm_encoder_cleanup(encoder);
3835 kfree(intel_encoder);
7e7d76c3
JB		 3836}
3837
5ab432ef
DV		 3838/* Simple dpms helper for encodres with just one connector, no cloning and only
3839 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3840 * state of the entire output pipe. */
3841void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3842{
5ab432ef
DV		 3843 if (mode == DRM_MODE_DPMS_ON) {
3844 encoder->connectors_active = true;
3845
b2cabb0e 3846 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3847 } else {
3848 encoder->connectors_active = false;
3849
b2cabb0e 3850 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3851 }
79e53945
JB		 3852}
3853
0a91ca29
DV		 3854/* Cross check the actual hw state with our own modeset state tracking (and it's
3855 * internal consistency). */
b980514c 3856static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3857{
0a91ca29
DV		 3858 if (connector->get_hw_state(connector)) {
3859 struct intel_encoder *encoder = connector->encoder;
3860 struct drm_crtc *crtc;
3861 bool encoder_enabled;
3862 enum pipe pipe;
3863
3864 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3865 connector->base.base.id,
3866 drm_get_connector_name(&connector->base));
3867
3868 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3869 "wrong connector dpms state\n");
3870 WARN(connector->base.encoder != &encoder->base,
3871 "active connector not linked to encoder\n");
3872 WARN(!encoder->connectors_active,
3873 "encoder->connectors_active not set\n");
3874
3875 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3876 WARN(!encoder_enabled, "encoder not enabled\n");
3877 if (WARN_ON(!encoder->base.crtc))
3878 return;
3879
3880 crtc = encoder->base.crtc;
3881
3882 WARN(!crtc->enabled, "crtc not enabled\n");
3883 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3884 WARN(pipe != to_intel_crtc(crtc)->pipe,
3885 "encoder active on the wrong pipe\n");
3886 }
79e53945
JB		 3887}
3888
5ab432ef
DV		 3889/* Even simpler default implementation, if there's really no special case to
3890 * consider. */
3891void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3892{
5ab432ef 3893 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3894
5ab432ef
DV		 3895 /* All the simple cases only support two dpms states. */
3896 if (mode != DRM_MODE_DPMS_ON)
3897 mode = DRM_MODE_DPMS_OFF;
d4270e57 3898
5ab432ef
DV		 3899 if (mode == connector->dpms)
3900 return;
3901
3902 connector->dpms = mode;
3903
3904 /* Only need to change hw state when actually enabled */
3905 if (encoder->base.crtc)
3906 intel_encoder_dpms(encoder, mode);
3907 else
8af6cf88 3908 WARN_ON(encoder->connectors_active != false);
0a91ca29 3909
b980514c 3910 intel_modeset_check_state(connector->dev);
79e53945
JB		 3911}
3912
f0947c37
DV		 3913/* Simple connector->get_hw_state implementation for encoders that support only
3914 * one connector and no cloning and hence the encoder state determines the state
3915 * of the connector. */
3916bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3917{
24929352 3918 enum pipe pipe = 0;
f0947c37 3919 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3920
f0947c37 3921 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3922}
3923
1857e1da
DV		 3924static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3925 struct intel_crtc_config *pipe_config)
3926{
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 struct intel_crtc *pipe_B_crtc =
3929 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3930
3931 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3932 pipe_name(pipe), pipe_config->fdi_lanes);
3933 if (pipe_config->fdi_lanes > 4) {
3934 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3935 pipe_name(pipe), pipe_config->fdi_lanes);
3936 return false;
3937 }
3938
3939 if (IS_HASWELL(dev)) {
3940 if (pipe_config->fdi_lanes > 2) {
3941 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3942 pipe_config->fdi_lanes);
3943 return false;
3944 } else {
3945 return true;
3946 }
3947 }
3948
3949 if (INTEL_INFO(dev)->num_pipes == 2)
3950 return true;
3951
3952 /* Ivybridge 3 pipe is really complicated */
3953 switch (pipe) {
3954 case PIPE_A:
3955 return true;
3956 case PIPE_B:
3957 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3958 pipe_config->fdi_lanes > 2) {
3959 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3960 pipe_name(pipe), pipe_config->fdi_lanes);
3961 return false;
3962 }
3963 return true;
3964 case PIPE_C:
1e833f40 3965 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3966 pipe_B_crtc->config.fdi_lanes <= 2) {
3967 if (pipe_config->fdi_lanes > 2) {
3968 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3969 pipe_name(pipe), pipe_config->fdi_lanes);
3970 return false;
3971 }
3972 } else {
3973 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3974 return false;
3975 }
3976 return true;
3977 default:
3978 BUG();
3979 }
3980}
3981
e29c22c0
DV		 3982#define RETRY 1
3983static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3984 struct intel_crtc_config *pipe_config)
877d48d5 3985{
1857e1da 3986 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 3987 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 3988 int lane, link_bw, fdi_dotclock;
e29c22c0 3989 bool setup_ok, needs_recompute = false;
877d48d5 3990
e29c22c0 3991retry:
877d48d5
DV		 3992 /* FDI is a binary signal running at ~2.7GHz, encoding
3993 * each output octet as 10 bits. The actual frequency
3994 * is stored as a divider into a 100MHz clock, and the
3995 * mode pixel clock is stored in units of 1KHz.
3996 * Hence the bw of each lane in terms of the mode signal
3997 * is:
3998 */
3999 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4000
ff9a6750 4001 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4002 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4003
2bd89a07 4004 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4005 pipe_config->pipe_bpp);
4006
4007 pipe_config->fdi_lanes = lane;
4008
2bd89a07 4009 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4010 link_bw, &pipe_config->fdi_m_n);
1857e1da 4011
e29c22c0
DV		 4012 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4013 intel_crtc->pipe, pipe_config);
4014 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4015 pipe_config->pipe_bpp -= 2*3;
4016 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4017 pipe_config->pipe_bpp);
4018 needs_recompute = true;
4019 pipe_config->bw_constrained = true;
4020
4021 goto retry;
4022 }
4023
4024 if (needs_recompute)
4025 return RETRY;
4026
4027 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4028}
4029
42db64ef
PZ		 4030static void hsw_compute_ips_config(struct intel_crtc *crtc,
4031 struct intel_crtc_config *pipe_config)
4032{
3c4ca58c
PZ		 4033 pipe_config->ips_enabled = i915_enable_ips &&
4034 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4035 pipe_config->pipe_bpp == 24;
4036}
4037
a43f6e0f 4038static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4039 struct intel_crtc_config *pipe_config)
79e53945 4040{
a43f6e0f 4041 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4042 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4043
bad720ff 4044 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4045 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4046 if (pipe_config->requested_mode.clock * 3
4047 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4048 return -EINVAL;
2c07245f 4049 }
89749350 4050
f9bef081
DV		 4051 /* All interlaced capable intel hw wants timings in frames. Note though
4052 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4053 * timings, so we need to be careful not to clobber these.*/
7ae89233 4054 if (!pipe_config->timings_set)
f9bef081 4055 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4056
8693a824
DL		 4057 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4058 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4059 */
4060 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4061 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4062 return -EINVAL;
44f46b42 4063
bd080ee5 4064 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4065 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4066 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4067 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4068 * for lvds. */
4069 pipe_config->pipe_bpp = 8*3;
4070 }
4071
f5adf94e 4072 if (HAS_IPS(dev))
a43f6e0f
DV		 4073 hsw_compute_ips_config(crtc, pipe_config);
4074
4075 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4076 * clock survives for now. */
4077 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4078 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4079
877d48d5 4080 if (pipe_config->has_pch_encoder)
a43f6e0f 4081 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4082
e29c22c0 4083 return 0;
79e53945
JB		 4084}
4085
25eb05fc
JB		 4086static int valleyview_get_display_clock_speed(struct drm_device *dev)
4087{
4088 return 400000; /* FIXME */
4089}
4090
e70236a8
JB		 4091static int i945_get_display_clock_speed(struct drm_device *dev)
4092{
4093 return 400000;
4094}
79e53945 4095
e70236a8 4096static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4097{
e70236a8
JB		 4098 return 333000;
4099}
79e53945 4100
e70236a8
JB		 4101static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4102{
4103 return 200000;
4104}
79e53945 4105
e70236a8
JB		 4106static int i915gm_get_display_clock_speed(struct drm_device *dev)
4107{
4108 u16 gcfgc = 0;
79e53945 4109
e70236a8
JB		 4110 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4111
4112 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4113 return 133000;
4114 else {
4115 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4116 case GC_DISPLAY_CLOCK_333_MHZ:
4117 return 333000;
4118 default:
4119 case GC_DISPLAY_CLOCK_190_200_MHZ:
4120 return 190000;
79e53945 4121 }
e70236a8
JB		 4122 }
4123}
4124
4125static int i865_get_display_clock_speed(struct drm_device *dev)
4126{
4127 return 266000;
4128}
4129
4130static int i855_get_display_clock_speed(struct drm_device *dev)
4131{
4132 u16 hpllcc = 0;
4133 /* Assume that the hardware is in the high speed state. This
4134 * should be the default.
4135 */
4136 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4137 case GC_CLOCK_133_200:
4138 case GC_CLOCK_100_200:
4139 return 200000;
4140 case GC_CLOCK_166_250:
4141 return 250000;
4142 case GC_CLOCK_100_133:
79e53945 4143 return 133000;
e70236a8 4144 }
79e53945 4145
e70236a8
JB		 4146 /* Shouldn't happen */
4147 return 0;
4148}
79e53945 4149
e70236a8
JB		 4150static int i830_get_display_clock_speed(struct drm_device *dev)
4151{
4152 return 133000;
79e53945
JB		 4153}
4154
2c07245f 4155static void
a65851af 4156intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4157{
a65851af
VS		 4158 while (*num > DATA_LINK_M_N_MASK ||
4159 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4160 *num >>= 1;
4161 *den >>= 1;
4162 }
4163}
4164
a65851af
VS		 4165static void compute_m_n(unsigned int m, unsigned int n,
4166 uint32_t *ret_m, uint32_t *ret_n)
4167{
4168 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4169 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4170 intel_reduce_m_n_ratio(ret_m, ret_n);
4171}
4172
e69d0bc1
DV		 4173void
4174intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4175 int pixel_clock, int link_clock,
4176 struct intel_link_m_n *m_n)
2c07245f 4177{
e69d0bc1 4178 m_n->tu = 64;
a65851af
VS		 4179
4180 compute_m_n(bits_per_pixel * pixel_clock,
4181 link_clock * nlanes * 8,
4182 &m_n->gmch_m, &m_n->gmch_n);
4183
4184 compute_m_n(pixel_clock, link_clock,
4185 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4186}
4187
a7615030
CW		 4188static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4189{
72bbe58c
KP		 4190 if (i915_panel_use_ssc >= 0)
4191 return i915_panel_use_ssc != 0;
41aa3448 4192 return dev_priv->vbt.lvds_use_ssc
435793df 4193 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4194}
4195
a0c4da24
JB		 4196static int vlv_get_refclk(struct drm_crtc *crtc)
4197{
4198 struct drm_device *dev = crtc->dev;
4199 struct drm_i915_private *dev_priv = dev->dev_private;
4200 int refclk = 27000; /* for DP & HDMI */
4201
4202 return 100000; /* only one validated so far */
4203
4204 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4205 refclk = 96000;
4206 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4207 if (intel_panel_use_ssc(dev_priv))
4208 refclk = 100000;
4209 else
4210 refclk = 96000;
4211 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4212 refclk = 100000;
4213 }
4214
4215 return refclk;
4216}
4217
c65d77d8
JB		 4218static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4219{
4220 struct drm_device *dev = crtc->dev;
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4222 int refclk;
4223
a0c4da24
JB		 4224 if (IS_VALLEYVIEW(dev)) {
4225 refclk = vlv_get_refclk(crtc);
4226 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4227 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4228 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4229 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4230 refclk / 1000);
4231 } else if (!IS_GEN2(dev)) {
4232 refclk = 96000;
4233 } else {
4234 refclk = 48000;
4235 }
4236
4237 return refclk;
4238}
4239
7429e9d4 4240static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4241{
7df00d7a 4242 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4243}
f47709a9 4244
7429e9d4
DV		 4245static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4246{
4247 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4248}
4249
f47709a9 4250static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4251 intel_clock_t *reduced_clock)
4252{
f47709a9 4253 struct drm_device *dev = crtc->base.dev;
a7516a05 4254 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4255 int pipe = crtc->pipe;
a7516a05
JB		 4256 u32 fp, fp2 = 0;
4257
4258 if (IS_PINEVIEW(dev)) {
7429e9d4 4259 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4260 if (reduced_clock)
7429e9d4 4261 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4262 } else {
7429e9d4 4263 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4264 if (reduced_clock)
7429e9d4 4265 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4266 }
4267
4268 I915_WRITE(FP0(pipe), fp);
4269
f47709a9
DV		 4270 crtc->lowfreq_avail = false;
4271 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4272 reduced_clock && i915_powersave) {
4273 I915_WRITE(FP1(pipe), fp2);
f47709a9 4274 crtc->lowfreq_avail = true;
a7516a05
JB		 4275 } else {
4276 I915_WRITE(FP1(pipe), fp);
4277 }
4278}
4279
89b667f8
JB		 4280static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4281{
4282 u32 reg_val;
4283
4284 /*
4285 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4286 * and set it to a reasonable value instead.
4287 */
ae99258f 4288 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4289 reg_val &= 0xffffff00;
4290 reg_val |= 0x00000030;
ae99258f 4291 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4292
ae99258f 4293 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4294 reg_val &= 0x8cffffff;
4295 reg_val = 0x8c000000;
ae99258f 4296 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4297
ae99258f 4298 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4299 reg_val &= 0xffffff00;
ae99258f 4300 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4301
ae99258f 4302 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4303 reg_val &= 0x00ffffff;
4304 reg_val |= 0xb0000000;
ae99258f 4305 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4306}
4307
b551842d
DV		 4308static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4309 struct intel_link_m_n *m_n)
4310{
4311 struct drm_device *dev = crtc->base.dev;
4312 struct drm_i915_private *dev_priv = dev->dev_private;
4313 int pipe = crtc->pipe;
4314
e3b95f1e
DV		 4315 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4316 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4317 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4318 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4319}
4320
4321static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4322 struct intel_link_m_n *m_n)
4323{
4324 struct drm_device *dev = crtc->base.dev;
4325 struct drm_i915_private *dev_priv = dev->dev_private;
4326 int pipe = crtc->pipe;
4327 enum transcoder transcoder = crtc->config.cpu_transcoder;
4328
4329 if (INTEL_INFO(dev)->gen >= 5) {
4330 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4331 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4332 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4333 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4334 } else {
e3b95f1e
DV		 4335 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4336 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4337 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4338 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4339 }
4340}
4341
03afc4a2
DV		 4342static void intel_dp_set_m_n(struct intel_crtc *crtc)
4343{
4344 if (crtc->config.has_pch_encoder)
4345 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4346 else
4347 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4348}
4349
f47709a9 4350static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4351{
f47709a9 4352 struct drm_device *dev = crtc->base.dev;
a0c4da24 4353 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4354 struct intel_encoder *encoder;
f47709a9 4355 int pipe = crtc->pipe;
89b667f8 4356 u32 dpll, mdiv;
a0c4da24 4357 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4358 bool is_hdmi;
198a037f 4359 u32 coreclk, reg_val, dpll_md;
a0c4da24 4360
09153000
DV		 4361 mutex_lock(&dev_priv->dpio_lock);
4362
89b667f8 4363 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4364
f47709a9
DV		 4365 bestn = crtc->config.dpll.n;
4366 bestm1 = crtc->config.dpll.m1;
4367 bestm2 = crtc->config.dpll.m2;
4368 bestp1 = crtc->config.dpll.p1;
4369 bestp2 = crtc->config.dpll.p2;
a0c4da24 4370
89b667f8
JB		 4371 /* See eDP HDMI DPIO driver vbios notes doc */
4372
4373 /* PLL B needs special handling */
4374 if (pipe)
4375 vlv_pllb_recal_opamp(dev_priv);
4376
4377 /* Set up Tx target for periodic Rcomp update */
ae99258f 4378 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4379
4380 /* Disable target IRef on PLL */
ae99258f 4381 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4382 reg_val &= 0x00ffffff;
ae99258f 4383 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4384
4385 /* Disable fast lock */
ae99258f 4386 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4387
4388 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4389 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4390 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4391 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4392 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4393
4394 /*
4395 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4396 * but we don't support that).
4397 * Note: don't use the DAC post divider as it seems unstable.
4398 */
4399 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4400 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4401
a0c4da24 4402 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4403 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4404
89b667f8 4405 /* Set HBR and RBR LPF coefficients */
ff9a6750 4406 if (crtc->config.port_clock == 162000 ||
99750bd4 4407 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4408 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4409 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4410 0x005f0021);
4411 else
4abb2c39 4412 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4413 0x00d0000f);
4414
4415 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4416 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4417 /* Use SSC source */
4418 if (!pipe)
ae99258f 4419 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4420 0x0df40000);
4421 else
ae99258f 4422 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4423 0x0df70000);
4424 } else { /* HDMI or VGA */
4425 /* Use bend source */
4426 if (!pipe)
ae99258f 4427 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4428 0x0df70000);
4429 else
ae99258f 4430 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4431 0x0df40000);
4432 }
a0c4da24 4433
ae99258f 4434 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4435 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4436 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4437 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4438 coreclk |= 0x01000000;
ae99258f 4439 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4440
ae99258f 4441 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4442
89b667f8
JB		 4443 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4444 if (encoder->pre_pll_enable)
4445 encoder->pre_pll_enable(encoder);
a0c4da24 4446
89b667f8
JB		 4447 /* Enable DPIO clock input */
4448 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4449 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4450 if (pipe)
4451 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4452
4453 dpll |= DPLL_VCO_ENABLE;
4454 I915_WRITE(DPLL(pipe), dpll);
4455 POSTING_READ(DPLL(pipe));
2a8f64ca 4456 udelay(150);
a0c4da24 4457
a0c4da24
JB		 4458 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4459 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4460
ef1b460d
DV		 4461 dpll_md = (crtc->config.pixel_multiplier - 1)
4462 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4463 I915_WRITE(DPLL_MD(pipe), dpll_md);
2a8f64ca 4464 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4465
89b667f8
JB		 4466 if (crtc->config.has_dp_encoder)
4467 intel_dp_set_m_n(crtc);
09153000
DV		 4468
4469 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4470}
4471
f47709a9
DV		 4472static void i9xx_update_pll(struct intel_crtc *crtc,
4473 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4474 int num_connectors)
4475{
f47709a9 4476 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4477 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4478 struct intel_encoder *encoder;
f47709a9 4479 int pipe = crtc->pipe;
eb1cbe48
DV		 4480 u32 dpll;
4481 bool is_sdvo;
f47709a9 4482 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4483
f47709a9 4484 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4485
f47709a9
DV		 4486 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4487 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4488
4489 dpll = DPLL_VGA_MODE_DIS;
4490
f47709a9 4491 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4492 dpll |= DPLLB_MODE_LVDS;
4493 else
4494 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4495
ef1b460d 4496 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4497 dpll |= (crtc->config.pixel_multiplier - 1)
4498 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4499 }
198a037f
DV		 4500
4501 if (is_sdvo)
4502 dpll |= DPLL_DVO_HIGH_SPEED;
4503
f47709a9 4504 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4505 dpll |= DPLL_DVO_HIGH_SPEED;
4506
4507 /* compute bitmask from p1 value */
4508 if (IS_PINEVIEW(dev))
4509 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4510 else {
4511 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512 if (IS_G4X(dev) && reduced_clock)
4513 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4514 }
4515 switch (clock->p2) {
4516 case 5:
4517 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4518 break;
4519 case 7:
4520 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4521 break;
4522 case 10:
4523 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4524 break;
4525 case 14:
4526 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4527 break;
4528 }
4529 if (INTEL_INFO(dev)->gen >= 4)
4530 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4531
09ede541 4532 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4533 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4534 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4535 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4536 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4537 else
4538 dpll |= PLL_REF_INPUT_DREFCLK;
4539
4540 dpll |= DPLL_VCO_ENABLE;
4541 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4542 POSTING_READ(DPLL(pipe));
4543 udelay(150);
4544
f47709a9 4545 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4546 if (encoder->pre_pll_enable)
4547 encoder->pre_pll_enable(encoder);
eb1cbe48 4548
f47709a9
DV		 4549 if (crtc->config.has_dp_encoder)
4550 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4551
4552 I915_WRITE(DPLL(pipe), dpll);
4553
4554 /* Wait for the clocks to stabilize. */
4555 POSTING_READ(DPLL(pipe));
4556 udelay(150);
4557
4558 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4559 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4560 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
198a037f 4561 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4562 } else {
4563 /* The pixel multiplier can only be updated once the
4564 * DPLL is enabled and the clocks are stable.
4565 *
4566 * So write it again.
4567 */
4568 I915_WRITE(DPLL(pipe), dpll);
4569 }
4570}
4571
f47709a9 4572static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4573 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4574 int num_connectors)
4575{
f47709a9 4576 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4577 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4578 struct intel_encoder *encoder;
f47709a9 4579 int pipe = crtc->pipe;
eb1cbe48 4580 u32 dpll;
f47709a9 4581 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4582
f47709a9 4583 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4584
eb1cbe48
DV		 4585 dpll = DPLL_VGA_MODE_DIS;
4586
f47709a9 4587 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4588 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4589 } else {
4590 if (clock->p1 == 2)
4591 dpll |= PLL_P1_DIVIDE_BY_TWO;
4592 else
4593 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4594 if (clock->p2 == 4)
4595 dpll |= PLL_P2_DIVIDE_BY_4;
4596 }
4597
f47709a9 4598 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4599 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4600 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4601 else
4602 dpll |= PLL_REF_INPUT_DREFCLK;
4603
4604 dpll |= DPLL_VCO_ENABLE;
4605 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4606 POSTING_READ(DPLL(pipe));
4607 udelay(150);
4608
f47709a9 4609 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4610 if (encoder->pre_pll_enable)
4611 encoder->pre_pll_enable(encoder);
eb1cbe48 4612
5b5896e4
DV		 4613 I915_WRITE(DPLL(pipe), dpll);
4614
4615 /* Wait for the clocks to stabilize. */
4616 POSTING_READ(DPLL(pipe));
4617 udelay(150);
4618
eb1cbe48
DV		 4619 /* The pixel multiplier can only be updated once the
4620 * DPLL is enabled and the clocks are stable.
4621 *
4622 * So write it again.
4623 */
4624 I915_WRITE(DPLL(pipe), dpll);
4625}
4626
8a654f3b 4627static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4628{
4629 struct drm_device *dev = intel_crtc->base.dev;
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4632 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4633 struct drm_display_mode *adjusted_mode =
4634 &intel_crtc->config.adjusted_mode;
4635 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4636 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4637
4638 /* We need to be careful not to changed the adjusted mode, for otherwise
4639 * the hw state checker will get angry at the mismatch. */
4640 crtc_vtotal = adjusted_mode->crtc_vtotal;
4641 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4642
4643 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4644 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4645 crtc_vtotal -= 1;
4646 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4647 vsyncshift = adjusted_mode->crtc_hsync_start
4648 - adjusted_mode->crtc_htotal / 2;
4649 } else {
4650 vsyncshift = 0;
4651 }
4652
4653 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4654 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4655
fe2b8f9d 4656 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4657 (adjusted_mode->crtc_hdisplay - 1) |
4658 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4659 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4660 (adjusted_mode->crtc_hblank_start - 1) |
4661 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4662 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4663 (adjusted_mode->crtc_hsync_start - 1) |
4664 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4665
fe2b8f9d 4666 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4667 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4668 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4669 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4670 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4671 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4672 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4673 (adjusted_mode->crtc_vsync_start - 1) |
4674 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4675
b5e508d4
PZ		 4676 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4677 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4678 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4679 * bits. */
4680 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4681 (pipe == PIPE_B || pipe == PIPE_C))
4682 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4683
b0e77b9c
PZ		 4684 /* pipesrc controls the size that is scaled from, which should
4685 * always be the user's requested size.
4686 */
4687 I915_WRITE(PIPESRC(pipe),
4688 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4689}
4690
1bd1bd80
DV		 4691static void intel_get_pipe_timings(struct intel_crtc *crtc,
4692 struct intel_crtc_config *pipe_config)
4693{
4694 struct drm_device *dev = crtc->base.dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4697 uint32_t tmp;
4698
4699 tmp = I915_READ(HTOTAL(cpu_transcoder));
4700 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4701 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4702 tmp = I915_READ(HBLANK(cpu_transcoder));
4703 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4704 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4705 tmp = I915_READ(HSYNC(cpu_transcoder));
4706 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4707 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4708
4709 tmp = I915_READ(VTOTAL(cpu_transcoder));
4710 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4711 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4712 tmp = I915_READ(VBLANK(cpu_transcoder));
4713 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4714 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4715 tmp = I915_READ(VSYNC(cpu_transcoder));
4716 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4717 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4718
4719 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4720 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4721 pipe_config->adjusted_mode.crtc_vtotal += 1;
4722 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4723 }
4724
4725 tmp = I915_READ(PIPESRC(crtc->pipe));
4726 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4727 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4728}
4729
84b046f3
DV		 4730static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4731{
4732 struct drm_device *dev = intel_crtc->base.dev;
4733 struct drm_i915_private *dev_priv = dev->dev_private;
4734 uint32_t pipeconf;
4735
9f11a9e4 4736 pipeconf = 0;
84b046f3
DV		 4737
4738 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4739 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4740 * core speed.
4741 *
4742 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4743 * pipe == 0 check?
4744 */
4745 if (intel_crtc->config.requested_mode.clock >
4746 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4747 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4748 }
4749
ff9ce46e
DV		 4750 /* only g4x and later have fancy bpc/dither controls */
4751 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4752 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4753 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4754 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4755 PIPECONF_DITHER_TYPE_SP;
84b046f3 4756
ff9ce46e
DV		 4757 switch (intel_crtc->config.pipe_bpp) {
4758 case 18:
4759 pipeconf |= PIPECONF_6BPC;
4760 break;
4761 case 24:
4762 pipeconf |= PIPECONF_8BPC;
4763 break;
4764 case 30:
4765 pipeconf |= PIPECONF_10BPC;
4766 break;
4767 default:
4768 /* Case prevented by intel_choose_pipe_bpp_dither. */
4769 BUG();
84b046f3
DV		 4770 }
4771 }
4772
4773 if (HAS_PIPE_CXSR(dev)) {
4774 if (intel_crtc->lowfreq_avail) {
4775 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4776 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4777 } else {
4778 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4779 }
4780 }
4781
84b046f3
DV		 4782 if (!IS_GEN2(dev) &&
4783 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4784 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4785 else
4786 pipeconf |= PIPECONF_PROGRESSIVE;
4787
9f11a9e4
DV		 4788 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4789 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4790
84b046f3
DV		 4791 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4792 POSTING_READ(PIPECONF(intel_crtc->pipe));
4793}
4794
f564048e 4795static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4796 int x, int y,
94352cf9 4797 struct drm_framebuffer *fb)
79e53945
JB		 4798{
4799 struct drm_device *dev = crtc->dev;
4800 struct drm_i915_private *dev_priv = dev->dev_private;
4801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4802 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4803 int pipe = intel_crtc->pipe;
80824003 4804 int plane = intel_crtc->plane;
c751ce4f 4805 int refclk, num_connectors = 0;
652c393a 4806 intel_clock_t clock, reduced_clock;
84b046f3 4807 u32 dspcntr;
a16af721
DV		 4808 bool ok, has_reduced_clock = false;
4809 bool is_lvds = false;
5eddb70b 4810 struct intel_encoder *encoder;
d4906093 4811 const intel_limit_t *limit;
5c3b82e2 4812 int ret;
79e53945 4813
6c2b7c12 4814 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4815 switch (encoder->type) {
79e53945
JB		 4816 case INTEL_OUTPUT_LVDS:
4817 is_lvds = true;
4818 break;
79e53945 4819 }
43565a06 4820
c751ce4f 4821 num_connectors++;
79e53945
JB		 4822 }
4823
c65d77d8 4824 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4825
d4906093
ML		 4826 /*
4827 * Returns a set of divisors for the desired target clock with the given
4828 * refclk, or FALSE. The returned values represent the clock equation:
4829 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4830 */
1b894b59 4831 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4832 ok = dev_priv->display.find_dpll(limit, crtc,
4833 intel_crtc->config.port_clock,
ee9300bb
DV		 4834 refclk, NULL, &clock);
4835 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4836 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4837 return -EINVAL;
79e53945
JB		 4838 }
4839
cda4b7d3 4840 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4841 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4842
ddc9003c 4843 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4844 /*
4845 * Ensure we match the reduced clock's P to the target clock.
4846 * If the clocks don't match, we can't switch the display clock
4847 * by using the FP0/FP1. In such case we will disable the LVDS
4848 * downclock feature.
4849 */
ee9300bb
DV		 4850 has_reduced_clock =
4851 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4852 dev_priv->lvds_downclock,
ee9300bb 4853 refclk, &clock,
5eddb70b 4854 &reduced_clock);
7026d4ac 4855 }
f47709a9
DV		 4856 /* Compat-code for transition, will disappear. */
4857 if (!intel_crtc->config.clock_set) {
4858 intel_crtc->config.dpll.n = clock.n;
4859 intel_crtc->config.dpll.m1 = clock.m1;
4860 intel_crtc->config.dpll.m2 = clock.m2;
4861 intel_crtc->config.dpll.p1 = clock.p1;
4862 intel_crtc->config.dpll.p2 = clock.p2;
4863 }
7026d4ac 4864
eb1cbe48 4865 if (IS_GEN2(dev))
8a654f3b 4866 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4867 has_reduced_clock ? &reduced_clock : NULL,
4868 num_connectors);
a0c4da24 4869 else if (IS_VALLEYVIEW(dev))
f47709a9 4870 vlv_update_pll(intel_crtc);
79e53945 4871 else
f47709a9 4872 i9xx_update_pll(intel_crtc,
eb1cbe48 4873 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4874 num_connectors);
79e53945 4875
79e53945
JB		 4876 /* Set up the display plane register */
4877 dspcntr = DISPPLANE_GAMMA_ENABLE;
4878
da6ecc5d
JB		 4879 if (!IS_VALLEYVIEW(dev)) {
4880 if (pipe == 0)
4881 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4882 else
4883 dspcntr |= DISPPLANE_SEL_PIPE_B;
4884 }
79e53945 4885
8a654f3b 4886 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4887
4888 /* pipesrc and dspsize control the size that is scaled from,
4889 * which should always be the user's requested size.
79e53945 4890 */
929c77fb
EA		 4891 I915_WRITE(DSPSIZE(plane),
4892 ((mode->vdisplay - 1) << 16) |
4893 (mode->hdisplay - 1));
4894 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4895
84b046f3
DV		 4896 i9xx_set_pipeconf(intel_crtc);
4897
f564048e
EA		 4898 I915_WRITE(DSPCNTR(plane), dspcntr);
4899 POSTING_READ(DSPCNTR(plane));
4900
94352cf9 4901 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4902
4903 intel_update_watermarks(dev);
4904
f564048e
EA		 4905 return ret;
4906}
4907
2fa2fe9a
DV		 4908static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4909 struct intel_crtc_config *pipe_config)
4910{
4911 struct drm_device *dev = crtc->base.dev;
4912 struct drm_i915_private *dev_priv = dev->dev_private;
4913 uint32_t tmp;
4914
4915 tmp = I915_READ(PFIT_CONTROL);
4916
4917 if (INTEL_INFO(dev)->gen < 4) {
4918 if (crtc->pipe != PIPE_B)
4919 return;
4920
4921 /* gen2/3 store dither state in pfit control, needs to match */
4922 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4923 } else {
4924 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4925 return;
4926 }
4927
4928 if (!(tmp & PFIT_ENABLE))
4929 return;
4930
4931 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4932 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4933 if (INTEL_INFO(dev)->gen < 5)
4934 pipe_config->gmch_pfit.lvds_border_bits =
4935 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4936}
4937
0e8ffe1b
DV		 4938static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4939 struct intel_crtc_config *pipe_config)
4940{
4941 struct drm_device *dev = crtc->base.dev;
4942 struct drm_i915_private *dev_priv = dev->dev_private;
4943 uint32_t tmp;
4944
eccb140b 4945 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 4946 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4947
0e8ffe1b
DV		 4948 tmp = I915_READ(PIPECONF(crtc->pipe));
4949 if (!(tmp & PIPECONF_ENABLE))
4950 return false;
4951
1bd1bd80
DV		 4952 intel_get_pipe_timings(crtc, pipe_config);
4953
2fa2fe9a
DV		 4954 i9xx_get_pfit_config(crtc, pipe_config);
4955
6c49f241
DV		 4956 if (INTEL_INFO(dev)->gen >= 4) {
4957 tmp = I915_READ(DPLL_MD(crtc->pipe));
4958 pipe_config->pixel_multiplier =
4959 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4960 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
4961 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4962 tmp = I915_READ(DPLL(crtc->pipe));
4963 pipe_config->pixel_multiplier =
4964 ((tmp & SDVO_MULTIPLIER_MASK)
4965 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4966 } else {
4967 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4968 * port and will be fixed up in the encoder->get_config
4969 * function. */
4970 pipe_config->pixel_multiplier = 1;
4971 }
4972
0e8ffe1b
DV		 4973 return true;
4974}
4975
dde86e2d 4976static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4977{
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4980 struct intel_encoder *encoder;
74cfd7ac 4981 u32 val, final;
13d83a67 4982 bool has_lvds = false;
199e5d79 4983 bool has_cpu_edp = false;
199e5d79 4984 bool has_panel = false;
99eb6a01
KP		 4985 bool has_ck505 = false;
4986 bool can_ssc = false;
13d83a67
JB		 4987
4988 /* We need to take the global config into account */
199e5d79
KP		 4989 list_for_each_entry(encoder, &mode_config->encoder_list,
4990 base.head) {
4991 switch (encoder->type) {
4992 case INTEL_OUTPUT_LVDS:
4993 has_panel = true;
4994 has_lvds = true;
4995 break;
4996 case INTEL_OUTPUT_EDP:
4997 has_panel = true;
2de6905f 4998 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 4999 has_cpu_edp = true;
5000 break;
13d83a67
JB		 5001 }
5002 }
5003
99eb6a01 5004 if (HAS_PCH_IBX(dev)) {
41aa3448 5005 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5006 can_ssc = has_ck505;
5007 } else {
5008 has_ck505 = false;
5009 can_ssc = true;
5010 }
5011
2de6905f
ID		 5012 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5013 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5014
5015 /* Ironlake: try to setup display ref clock before DPLL
5016 * enabling. This is only under driver's control after
5017 * PCH B stepping, previous chipset stepping should be
5018 * ignoring this setting.
5019 */
74cfd7ac
CW		 5020 val = I915_READ(PCH_DREF_CONTROL);
5021
5022 /* As we must carefully and slowly disable/enable each source in turn,
5023 * compute the final state we want first and check if we need to
5024 * make any changes at all.
5025 */
5026 final = val;
5027 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5028 if (has_ck505)
5029 final |= DREF_NONSPREAD_CK505_ENABLE;
5030 else
5031 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5032
5033 final &= ~DREF_SSC_SOURCE_MASK;
5034 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5035 final &= ~DREF_SSC1_ENABLE;
5036
5037 if (has_panel) {
5038 final |= DREF_SSC_SOURCE_ENABLE;
5039
5040 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5041 final |= DREF_SSC1_ENABLE;
5042
5043 if (has_cpu_edp) {
5044 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5045 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5046 else
5047 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5048 } else
5049 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5050 } else {
5051 final |= DREF_SSC_SOURCE_DISABLE;
5052 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5053 }
5054
5055 if (final == val)
5056 return;
5057
13d83a67 5058 /* Always enable nonspread source */
74cfd7ac 5059 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5060
99eb6a01 5061 if (has_ck505)
74cfd7ac 5062 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5063 else
74cfd7ac 5064 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5065
199e5d79 5066 if (has_panel) {
74cfd7ac
CW		 5067 val &= ~DREF_SSC_SOURCE_MASK;
5068 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5069
199e5d79 5070 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5071 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5072 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5073 val |= DREF_SSC1_ENABLE;
e77166b5 5074 } else
74cfd7ac 5075 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5076
5077 /* Get SSC going before enabling the outputs */
74cfd7ac 5078 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5079 POSTING_READ(PCH_DREF_CONTROL);
5080 udelay(200);
5081
74cfd7ac 5082 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5083
5084 /* Enable CPU source on CPU attached eDP */
199e5d79 5085 if (has_cpu_edp) {
99eb6a01 5086 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5087 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5088 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5089 }
13d83a67 5090 else
74cfd7ac 5091 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5092 } else
74cfd7ac 5093 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5094
74cfd7ac 5095 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5096 POSTING_READ(PCH_DREF_CONTROL);
5097 udelay(200);
5098 } else {
5099 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5100
74cfd7ac 5101 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5102
5103 /* Turn off CPU output */
74cfd7ac 5104 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5105
74cfd7ac 5106 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5107 POSTING_READ(PCH_DREF_CONTROL);
5108 udelay(200);
5109
5110 /* Turn off the SSC source */
74cfd7ac
CW		 5111 val &= ~DREF_SSC_SOURCE_MASK;
5112 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5113
5114 /* Turn off SSC1 */
74cfd7ac 5115 val &= ~DREF_SSC1_ENABLE;
199e5d79 5116
74cfd7ac 5117 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5118 POSTING_READ(PCH_DREF_CONTROL);
5119 udelay(200);
5120 }
74cfd7ac
CW		 5121
5122 BUG_ON(val != final);
13d83a67
JB		 5123}
5124
dde86e2d
PZ		 5125/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5126static void lpt_init_pch_refclk(struct drm_device *dev)
5127{
5128 struct drm_i915_private *dev_priv = dev->dev_private;
5129 struct drm_mode_config *mode_config = &dev->mode_config;
5130 struct intel_encoder *encoder;
5131 bool has_vga = false;
5132 bool is_sdv = false;
5133 u32 tmp;
5134
5135 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5136 switch (encoder->type) {
5137 case INTEL_OUTPUT_ANALOG:
5138 has_vga = true;
5139 break;
5140 }
5141 }
5142
5143 if (!has_vga)
5144 return;
5145
c00db246
DV		 5146 mutex_lock(&dev_priv->dpio_lock);
5147
dde86e2d
PZ		 5148 /* XXX: Rip out SDV support once Haswell ships for real. */
5149 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5150 is_sdv = true;
5151
5152 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5153 tmp &= ~SBI_SSCCTL_DISABLE;
5154 tmp |= SBI_SSCCTL_PATHALT;
5155 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5156
5157 udelay(24);
5158
5159 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5160 tmp &= ~SBI_SSCCTL_PATHALT;
5161 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5162
5163 if (!is_sdv) {
5164 tmp = I915_READ(SOUTH_CHICKEN2);
5165 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5166 I915_WRITE(SOUTH_CHICKEN2, tmp);
5167
5168 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5169 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5170 DRM_ERROR("FDI mPHY reset assert timeout\n");
5171
5172 tmp = I915_READ(SOUTH_CHICKEN2);
5173 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5174 I915_WRITE(SOUTH_CHICKEN2, tmp);
5175
5176 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5177 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5178 100))
5179 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5180 }
5181
5182 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5183 tmp &= ~(0xFF << 24);
5184 tmp |= (0x12 << 24);
5185 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5186
dde86e2d
PZ		 5187 if (is_sdv) {
5188 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5189 tmp |= 0x7FFF;
5190 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5191 }
5192
5193 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5194 tmp |= (1 << 11);
5195 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5196
5197 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5198 tmp |= (1 << 11);
5199 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5200
5201 if (is_sdv) {
5202 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5203 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5204 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5205
5206 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5207 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5208 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5209
5210 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5211 tmp |= (0x3F << 8);
5212 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5213
5214 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5215 tmp |= (0x3F << 8);
5216 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5217 }
5218
5219 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5220 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5221 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5222
5223 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5224 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5225 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5226
5227 if (!is_sdv) {
5228 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5229 tmp &= ~(7 << 13);
5230 tmp |= (5 << 13);
5231 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5232
5233 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5234 tmp &= ~(7 << 13);
5235 tmp |= (5 << 13);
5236 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5237 }
5238
5239 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5240 tmp &= ~0xFF;
5241 tmp |= 0x1C;
5242 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5243
5244 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5245 tmp &= ~0xFF;
5246 tmp |= 0x1C;
5247 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5248
5249 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5250 tmp &= ~(0xFF << 16);
5251 tmp |= (0x1C << 16);
5252 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5253
5254 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5255 tmp &= ~(0xFF << 16);
5256 tmp |= (0x1C << 16);
5257 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5258
5259 if (!is_sdv) {
5260 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5261 tmp |= (1 << 27);
5262 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5263
5264 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5265 tmp |= (1 << 27);
5266 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5267
5268 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5269 tmp &= ~(0xF << 28);
5270 tmp |= (4 << 28);
5271 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5272
5273 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5274 tmp &= ~(0xF << 28);
5275 tmp |= (4 << 28);
5276 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5277 }
5278
5279 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5280 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5281 tmp |= SBI_DBUFF0_ENABLE;
5282 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5283
5284 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5285}
5286
5287/*
5288 * Initialize reference clocks when the driver loads
5289 */
5290void intel_init_pch_refclk(struct drm_device *dev)
5291{
5292 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5293 ironlake_init_pch_refclk(dev);
5294 else if (HAS_PCH_LPT(dev))
5295 lpt_init_pch_refclk(dev);
5296}
5297
d9d444cb
JB		 5298static int ironlake_get_refclk(struct drm_crtc *crtc)
5299{
5300 struct drm_device *dev = crtc->dev;
5301 struct drm_i915_private *dev_priv = dev->dev_private;
5302 struct intel_encoder *encoder;
d9d444cb
JB		 5303 int num_connectors = 0;
5304 bool is_lvds = false;
5305
6c2b7c12 5306 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5307 switch (encoder->type) {
5308 case INTEL_OUTPUT_LVDS:
5309 is_lvds = true;
5310 break;
d9d444cb
JB		 5311 }
5312 num_connectors++;
5313 }
5314
5315 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5316 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5317 dev_priv->vbt.lvds_ssc_freq);
5318 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5319 }
5320
5321 return 120000;
5322}
5323
6ff93609 5324static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5325{
c8203565 5326 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5328 int pipe = intel_crtc->pipe;
c8203565
PZ		 5329 uint32_t val;
5330
78114071 5331 val = 0;
c8203565 5332
965e0c48 5333 switch (intel_crtc->config.pipe_bpp) {
c8203565 5334 case 18:
dfd07d72 5335 val |= PIPECONF_6BPC;
c8203565
PZ		 5336 break;
5337 case 24:
dfd07d72 5338 val |= PIPECONF_8BPC;
c8203565
PZ		 5339 break;
5340 case 30:
dfd07d72 5341 val |= PIPECONF_10BPC;
c8203565
PZ		 5342 break;
5343 case 36:
dfd07d72 5344 val |= PIPECONF_12BPC;
c8203565
PZ		 5345 break;
5346 default:
cc769b62
PZ		 5347 /* Case prevented by intel_choose_pipe_bpp_dither. */
5348 BUG();
c8203565
PZ		 5349 }
5350
d8b32247 5351 if (intel_crtc->config.dither)
c8203565
PZ		 5352 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5353
6ff93609 5354 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5355 val |= PIPECONF_INTERLACED_ILK;
5356 else
5357 val |= PIPECONF_PROGRESSIVE;
5358
50f3b016 5359 if (intel_crtc->config.limited_color_range)
3685a8f3 5360 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5361
c8203565
PZ		 5362 I915_WRITE(PIPECONF(pipe), val);
5363 POSTING_READ(PIPECONF(pipe));
5364}
5365
86d3efce
VS		 5366/*
5367 * Set up the pipe CSC unit.
5368 *
5369 * Currently only full range RGB to limited range RGB conversion
5370 * is supported, but eventually this should handle various
5371 * RGB<->YCbCr scenarios as well.
5372 */
50f3b016 5373static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5374{
5375 struct drm_device *dev = crtc->dev;
5376 struct drm_i915_private *dev_priv = dev->dev_private;
5377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5378 int pipe = intel_crtc->pipe;
5379 uint16_t coeff = 0x7800; /* 1.0 */
5380
5381 /*
5382 * TODO: Check what kind of values actually come out of the pipe
5383 * with these coeff/postoff values and adjust to get the best
5384 * accuracy. Perhaps we even need to take the bpc value into
5385 * consideration.
5386 */
5387
50f3b016 5388 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5389 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5390
5391 /*
5392 * GY/GU and RY/RU should be the other way around according
5393 * to BSpec, but reality doesn't agree. Just set them up in
5394 * a way that results in the correct picture.
5395 */
5396 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5397 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5398
5399 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5400 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5401
5402 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5403 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5404
5405 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5406 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5407 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5408
5409 if (INTEL_INFO(dev)->gen > 6) {
5410 uint16_t postoff = 0;
5411
50f3b016 5412 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5413 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5414
5415 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5416 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5417 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5418
5419 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5420 } else {
5421 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5422
50f3b016 5423 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5424 mode |= CSC_BLACK_SCREEN_OFFSET;
5425
5426 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5427 }
5428}
5429
6ff93609 5430static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5431{
5432 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5434 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5435 uint32_t val;
5436
3eff4faa 5437 val = 0;
ee2b0b38 5438
d8b32247 5439 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5440 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5441
6ff93609 5442 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5443 val |= PIPECONF_INTERLACED_ILK;
5444 else
5445 val |= PIPECONF_PROGRESSIVE;
5446
702e7a56
PZ		 5447 I915_WRITE(PIPECONF(cpu_transcoder), val);
5448 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5449
5450 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5451 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5452}
5453
6591c6e4 5454static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5455 intel_clock_t *clock,
5456 bool *has_reduced_clock,
5457 intel_clock_t *reduced_clock)
5458{
5459 struct drm_device *dev = crtc->dev;
5460 struct drm_i915_private *dev_priv = dev->dev_private;
5461 struct intel_encoder *intel_encoder;
5462 int refclk;
d4906093 5463 const intel_limit_t *limit;
a16af721 5464 bool ret, is_lvds = false;
79e53945 5465
6591c6e4
PZ		 5466 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5467 switch (intel_encoder->type) {
79e53945
JB		 5468 case INTEL_OUTPUT_LVDS:
5469 is_lvds = true;
5470 break;
79e53945
JB		 5471 }
5472 }
5473
d9d444cb 5474 refclk = ironlake_get_refclk(crtc);
79e53945 5475
d4906093
ML		 5476 /*
5477 * Returns a set of divisors for the desired target clock with the given
5478 * refclk, or FALSE. The returned values represent the clock equation:
5479 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5480 */
1b894b59 5481 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5482 ret = dev_priv->display.find_dpll(limit, crtc,
5483 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5484 refclk, NULL, clock);
6591c6e4
PZ		 5485 if (!ret)
5486 return false;
cda4b7d3 5487
ddc9003c 5488 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5489 /*
5490 * Ensure we match the reduced clock's P to the target clock.
5491 * If the clocks don't match, we can't switch the display clock
5492 * by using the FP0/FP1. In such case we will disable the LVDS
5493 * downclock feature.
5494 */
ee9300bb
DV		 5495 *has_reduced_clock =
5496 dev_priv->display.find_dpll(limit, crtc,
5497 dev_priv->lvds_downclock,
5498 refclk, clock,
5499 reduced_clock);
652c393a 5500 }
61e9653f 5501
6591c6e4
PZ		 5502 return true;
5503}
5504
01a415fd
DV		 5505static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5506{
5507 struct drm_i915_private *dev_priv = dev->dev_private;
5508 uint32_t temp;
5509
5510 temp = I915_READ(SOUTH_CHICKEN1);
5511 if (temp & FDI_BC_BIFURCATION_SELECT)
5512 return;
5513
5514 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5515 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5516
5517 temp |= FDI_BC_BIFURCATION_SELECT;
5518 DRM_DEBUG_KMS("enabling fdi C rx\n");
5519 I915_WRITE(SOUTH_CHICKEN1, temp);
5520 POSTING_READ(SOUTH_CHICKEN1);
5521}
5522
ebfd86fd 5523static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5524{
5525 struct drm_device *dev = intel_crtc->base.dev;
5526 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5527
5528 switch (intel_crtc->pipe) {
5529 case PIPE_A:
ebfd86fd 5530 break;
01a415fd 5531 case PIPE_B:
ebfd86fd 5532 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5533 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5534 else
5535 cpt_enable_fdi_bc_bifurcation(dev);
5536
ebfd86fd 5537 break;
01a415fd 5538 case PIPE_C:
01a415fd
DV		 5539 cpt_enable_fdi_bc_bifurcation(dev);
5540
ebfd86fd 5541 break;
01a415fd
DV		 5542 default:
5543 BUG();
5544 }
5545}
5546
d4b1931c
PZ		 5547int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5548{
5549 /*
5550 * Account for spread spectrum to avoid
5551 * oversubscribing the link. Max center spread
5552 * is 2.5%; use 5% for safety's sake.
5553 */
5554 u32 bps = target_clock * bpp * 21 / 20;
5555 return bps / (link_bw * 8) + 1;
5556}
5557
7429e9d4 5558static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5559{
7429e9d4 5560 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5561}
5562
de13a2e3 5563static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5564 u32 *fp,
9a7c7890 5565 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5566{
de13a2e3 5567 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5568 struct drm_device *dev = crtc->dev;
5569 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5570 struct intel_encoder *intel_encoder;
5571 uint32_t dpll;
6cc5f341 5572 int factor, num_connectors = 0;
09ede541 5573 bool is_lvds = false, is_sdvo = false;
79e53945 5574
de13a2e3
PZ		 5575 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5576 switch (intel_encoder->type) {
79e53945
JB		 5577 case INTEL_OUTPUT_LVDS:
5578 is_lvds = true;
5579 break;
5580 case INTEL_OUTPUT_SDVO:
7d57382e 5581 case INTEL_OUTPUT_HDMI:
79e53945 5582 is_sdvo = true;
79e53945 5583 break;
79e53945 5584 }
43565a06 5585
c751ce4f 5586 num_connectors++;
79e53945 5587 }
79e53945 5588
c1858123 5589 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5590 factor = 21;
5591 if (is_lvds) {
5592 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5593 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5594 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5595 factor = 25;
09ede541 5596 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5597 factor = 20;
c1858123 5598
7429e9d4 5599 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5600 *fp |= FP_CB_TUNE;
2c07245f 5601
9a7c7890
DV		 5602 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5603 *fp2 |= FP_CB_TUNE;
5604
5eddb70b 5605 dpll = 0;
2c07245f 5606
a07d6787
EA		 5607 if (is_lvds)
5608 dpll |= DPLLB_MODE_LVDS;
5609 else
5610 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5611
ef1b460d
DV		 5612 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5613 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5614
5615 if (is_sdvo)
5616 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5617 if (intel_crtc->config.has_dp_encoder)
a07d6787 5618 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5619
a07d6787 5620 /* compute bitmask from p1 value */
7429e9d4 5621 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5622 /* also FPA1 */
7429e9d4 5623 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5624
7429e9d4 5625 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5626 case 5:
5627 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5628 break;
5629 case 7:
5630 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5631 break;
5632 case 10:
5633 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5634 break;
5635 case 14:
5636 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5637 break;
79e53945
JB		 5638 }
5639
b4c09f3b 5640 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5641 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5642 else
5643 dpll |= PLL_REF_INPUT_DREFCLK;
5644
959e16d6 5645 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5646}
5647
5648static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5649 int x, int y,
5650 struct drm_framebuffer *fb)
5651{
5652 struct drm_device *dev = crtc->dev;
5653 struct drm_i915_private *dev_priv = dev->dev_private;
5654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5655 int pipe = intel_crtc->pipe;
5656 int plane = intel_crtc->plane;
5657 int num_connectors = 0;
5658 intel_clock_t clock, reduced_clock;
cbbab5bd 5659 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5660 bool ok, has_reduced_clock = false;
8b47047b 5661 bool is_lvds = false;
de13a2e3 5662 struct intel_encoder *encoder;
e2b78267 5663 struct intel_shared_dpll *pll;
de13a2e3 5664 int ret;
de13a2e3
PZ		 5665
5666 for_each_encoder_on_crtc(dev, crtc, encoder) {
5667 switch (encoder->type) {
5668 case INTEL_OUTPUT_LVDS:
5669 is_lvds = true;
5670 break;
de13a2e3
PZ		 5671 }
5672
5673 num_connectors++;
a07d6787 5674 }
79e53945 5675
5dc5298b
PZ		 5676 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5677 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5678
ff9a6750 5679 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5680 &has_reduced_clock, &reduced_clock);
ee9300bb 5681 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5682 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5683 return -EINVAL;
79e53945 5684 }
f47709a9
DV		 5685 /* Compat-code for transition, will disappear. */
5686 if (!intel_crtc->config.clock_set) {
5687 intel_crtc->config.dpll.n = clock.n;
5688 intel_crtc->config.dpll.m1 = clock.m1;
5689 intel_crtc->config.dpll.m2 = clock.m2;
5690 intel_crtc->config.dpll.p1 = clock.p1;
5691 intel_crtc->config.dpll.p2 = clock.p2;
5692 }
79e53945 5693
de13a2e3
PZ		 5694 /* Ensure that the cursor is valid for the new mode before changing... */
5695 intel_crtc_update_cursor(crtc, true);
5696
5dc5298b 5697 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5698 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5699 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5700 if (has_reduced_clock)
7429e9d4 5701 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5702
7429e9d4 5703 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5704 &fp, &reduced_clock,
5705 has_reduced_clock ? &fp2 : NULL);
5706
959e16d6 5707 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5708 intel_crtc->config.dpll_hw_state.fp0 = fp;
5709 if (has_reduced_clock)
5710 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5711 else
5712 intel_crtc->config.dpll_hw_state.fp1 = fp;
5713
e72f9fbf 5714 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
ee7b9f93 5715 if (pll == NULL) {
84f44ce7
VS		 5716 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5717 pipe_name(pipe));
4b645f14
JB		 5718 return -EINVAL;
5719 }
ee7b9f93 5720 } else
e72f9fbf 5721 intel_put_shared_dpll(intel_crtc);
79e53945 5722
03afc4a2
DV		 5723 if (intel_crtc->config.has_dp_encoder)
5724 intel_dp_set_m_n(intel_crtc);
79e53945 5725
dafd226c
DV		 5726 for_each_encoder_on_crtc(dev, crtc, encoder)
5727 if (encoder->pre_pll_enable)
5728 encoder->pre_pll_enable(encoder);
79e53945 5729
bcd644e0
DV		 5730 if (is_lvds && has_reduced_clock && i915_powersave)
5731 intel_crtc->lowfreq_avail = true;
5732 else
5733 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5734
5735 if (intel_crtc->config.has_pch_encoder) {
5736 pll = intel_crtc_to_shared_dpll(intel_crtc);
5737
e9a632a5 5738 I915_WRITE(PCH_DPLL(pll->id), dpll);
5eddb70b 5739
32f9d658 5740 /* Wait for the clocks to stabilize. */
e9a632a5 5741 POSTING_READ(PCH_DPLL(pll->id));
32f9d658
ZW		 5742 udelay(150);
5743
8febb297
EA		 5744 /* The pixel multiplier can only be updated once the
5745 * DPLL is enabled and the clocks are stable.
5746 *
5747 * So write it again.
5748 */
e9a632a5 5749 I915_WRITE(PCH_DPLL(pll->id), dpll);
79e53945 5750
bcd644e0 5751 if (has_reduced_clock)
e9a632a5 5752 I915_WRITE(PCH_FP1(pll->id), fp2);
bcd644e0 5753 else
e9a632a5 5754 I915_WRITE(PCH_FP1(pll->id), fp);
652c393a
JB		 5755 }
5756
8a654f3b 5757 intel_set_pipe_timings(intel_crtc);
5eddb70b 5758
ca3a0ff8 5759 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5760 intel_cpu_transcoder_set_m_n(intel_crtc,
5761 &intel_crtc->config.fdi_m_n);
5762 }
2c07245f 5763
ebfd86fd
DV		 5764 if (IS_IVYBRIDGE(dev))
5765 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5766
6ff93609 5767 ironlake_set_pipeconf(crtc);
79e53945 5768
a1f9e77e
PZ		 5769 /* Set up the display plane register */
5770 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5771 POSTING_READ(DSPCNTR(plane));
79e53945 5772
94352cf9 5773 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5774
5775 intel_update_watermarks(dev);
5776
1857e1da 5777 return ret;
79e53945
JB		 5778}
5779
72419203
DV		 5780static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5781 struct intel_crtc_config *pipe_config)
5782{
5783 struct drm_device *dev = crtc->base.dev;
5784 struct drm_i915_private *dev_priv = dev->dev_private;
5785 enum transcoder transcoder = pipe_config->cpu_transcoder;
5786
5787 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5788 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5789 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5790 & ~TU_SIZE_MASK;
5791 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5792 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5793 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5794}
5795
2fa2fe9a
DV		 5796static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5797 struct intel_crtc_config *pipe_config)
5798{
5799 struct drm_device *dev = crtc->base.dev;
5800 struct drm_i915_private *dev_priv = dev->dev_private;
5801 uint32_t tmp;
5802
5803 tmp = I915_READ(PF_CTL(crtc->pipe));
5804
5805 if (tmp & PF_ENABLE) {
5806 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5807 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5808
5809 /* We currently do not free assignements of panel fitters on
5810 * ivb/hsw (since we don't use the higher upscaling modes which
5811 * differentiates them) so just WARN about this case for now. */
5812 if (IS_GEN7(dev)) {
5813 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5814 PF_PIPE_SEL_IVB(crtc->pipe));
5815 }
2fa2fe9a 5816 }
79e53945
JB		 5817}
5818
0e8ffe1b
DV		 5819static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5820 struct intel_crtc_config *pipe_config)
5821{
5822 struct drm_device *dev = crtc->base.dev;
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5824 uint32_t tmp;
5825
eccb140b 5826 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5827 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5828
0e8ffe1b
DV		 5829 tmp = I915_READ(PIPECONF(crtc->pipe));
5830 if (!(tmp & PIPECONF_ENABLE))
5831 return false;
5832
ab9412ba 5833 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5834 struct intel_shared_dpll *pll;
5835
88adfff1
DV		 5836 pipe_config->has_pch_encoder = true;
5837
627eb5a3
DV		 5838 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5839 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5840 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5841
5842 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241
DV		 5843
5844 /* XXX: Can't properly read out the pch dpll pixel multiplier
5845 * since we don't have state tracking for pch clocks yet. */
5846 pipe_config->pixel_multiplier = 1;
c0d43d62
DV		 5847
5848 if (HAS_PCH_IBX(dev_priv->dev)) {
5849 pipe_config->shared_dpll = crtc->pipe;
5850 } else {
5851 tmp = I915_READ(PCH_DPLL_SEL);
5852 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5853 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5854 else
5855 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5856 }
66e985c0
DV		 5857
5858 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5859
5860 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5861 &pipe_config->dpll_hw_state));
6c49f241
DV		 5862 } else {
5863 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5864 }
5865
1bd1bd80
DV		 5866 intel_get_pipe_timings(crtc, pipe_config);
5867
2fa2fe9a
DV		 5868 ironlake_get_pfit_config(crtc, pipe_config);
5869
0e8ffe1b
DV		 5870 return true;
5871}
5872
d6dd9eb1
DV		 5873static void haswell_modeset_global_resources(struct drm_device *dev)
5874{
d6dd9eb1
DV		 5875 bool enable = false;
5876 struct intel_crtc *crtc;
d6dd9eb1
DV		 5877
5878 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5879 if (!crtc->base.enabled)
5880 continue;
d6dd9eb1 5881
e7a639c4
DV		 5882 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5883 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5884 enable = true;
5885 }
5886
d6dd9eb1
DV		 5887 intel_set_power_well(dev, enable);
5888}
5889
09b4ddf9 5890static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5891 int x, int y,
5892 struct drm_framebuffer *fb)
5893{
5894 struct drm_device *dev = crtc->dev;
5895 struct drm_i915_private *dev_priv = dev->dev_private;
5896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5897 int plane = intel_crtc->plane;
09b4ddf9 5898 int ret;
09b4ddf9 5899
ff9a6750 5900 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5901 return -EINVAL;
5902
09b4ddf9
PZ		 5903 /* Ensure that the cursor is valid for the new mode before changing... */
5904 intel_crtc_update_cursor(crtc, true);
5905
03afc4a2
DV		 5906 if (intel_crtc->config.has_dp_encoder)
5907 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5908
5909 intel_crtc->lowfreq_avail = false;
09b4ddf9 5910
8a654f3b 5911 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5912
ca3a0ff8 5913 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5914 intel_cpu_transcoder_set_m_n(intel_crtc,
5915 &intel_crtc->config.fdi_m_n);
5916 }
09b4ddf9 5917
6ff93609 5918 haswell_set_pipeconf(crtc);
09b4ddf9 5919
50f3b016 5920 intel_set_pipe_csc(crtc);
86d3efce 5921
09b4ddf9 5922 /* Set up the display plane register */
86d3efce 5923 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5924 POSTING_READ(DSPCNTR(plane));
5925
5926 ret = intel_pipe_set_base(crtc, x, y, fb);
5927
5928 intel_update_watermarks(dev);
5929
1f803ee5 5930 return ret;
79e53945
JB		 5931}
5932
0e8ffe1b
DV		 5933static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5934 struct intel_crtc_config *pipe_config)
5935{
5936 struct drm_device *dev = crtc->base.dev;
5937 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5938 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5939 uint32_t tmp;
5940
eccb140b 5941 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62
DV		 5942 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5943
eccb140b
DV		 5944 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5945 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5946 enum pipe trans_edp_pipe;
5947 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5948 default:
5949 WARN(1, "unknown pipe linked to edp transcoder\n");
5950 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5951 case TRANS_DDI_EDP_INPUT_A_ON:
5952 trans_edp_pipe = PIPE_A;
5953 break;
5954 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5955 trans_edp_pipe = PIPE_B;
5956 break;
5957 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5958 trans_edp_pipe = PIPE_C;
5959 break;
5960 }
5961
5962 if (trans_edp_pipe == crtc->pipe)
5963 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5964 }
5965
b97186f0 5966 if (!intel_display_power_enabled(dev,
eccb140b 5967 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5968 return false;
5969
eccb140b 5970 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5971 if (!(tmp & PIPECONF_ENABLE))
5972 return false;
5973
88adfff1 5974 /*
f196e6be 5975 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5976 * DDI E. So just check whether this pipe is wired to DDI E and whether
5977 * the PCH transcoder is on.
5978 */
eccb140b 5979 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5980 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5981 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5982 pipe_config->has_pch_encoder = true;
5983
627eb5a3
DV		 5984 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5985 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5986 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5987
5988 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5989 }
5990
1bd1bd80
DV		 5991 intel_get_pipe_timings(crtc, pipe_config);
5992
2fa2fe9a
DV		 5993 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5994 if (intel_display_power_enabled(dev, pfit_domain))
5995 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 5996
42db64ef
PZ		 5997 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5998 (I915_READ(IPS_CTL) & IPS_ENABLE);
5999
6c49f241
DV		 6000 pipe_config->pixel_multiplier = 1;
6001
0e8ffe1b
DV		 6002 return true;
6003}
6004
f564048e 6005static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6006 int x, int y,
94352cf9 6007 struct drm_framebuffer *fb)
f564048e
EA		 6008{
6009 struct drm_device *dev = crtc->dev;
6010 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6011 struct drm_encoder_helper_funcs *encoder_funcs;
6012 struct intel_encoder *encoder;
0b701d27 6013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6014 struct drm_display_mode *adjusted_mode =
6015 &intel_crtc->config.adjusted_mode;
6016 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6017 int pipe = intel_crtc->pipe;
f564048e
EA		 6018 int ret;
6019
0b701d27 6020 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6021
b8cecdf5
DV		 6022 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6023
79e53945 6024 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6025
9256aa19
DV		 6026 if (ret != 0)
6027 return ret;
6028
6029 for_each_encoder_on_crtc(dev, crtc, encoder) {
6030 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6031 encoder->base.base.id,
6032 drm_get_encoder_name(&encoder->base),
6033 mode->base.id, mode->name);
6cc5f341
DV		 6034 if (encoder->mode_set) {
6035 encoder->mode_set(encoder);
6036 } else {
6037 encoder_funcs = encoder->base.helper_private;
6038 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6039 }
9256aa19
DV		 6040 }
6041
6042 return 0;
79e53945
JB		 6043}
6044
3a9627f4
WF		 6045static bool intel_eld_uptodate(struct drm_connector *connector,
6046 int reg_eldv, uint32_t bits_eldv,
6047 int reg_elda, uint32_t bits_elda,
6048 int reg_edid)
6049{
6050 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6051 uint8_t *eld = connector->eld;
6052 uint32_t i;
6053
6054 i = I915_READ(reg_eldv);
6055 i &= bits_eldv;
6056
6057 if (!eld[0])
6058 return !i;
6059
6060 if (!i)
6061 return false;
6062
6063 i = I915_READ(reg_elda);
6064 i &= ~bits_elda;
6065 I915_WRITE(reg_elda, i);
6066
6067 for (i = 0; i < eld[2]; i++)
6068 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6069 return false;
6070
6071 return true;
6072}
6073
e0dac65e
WF		 6074static void g4x_write_eld(struct drm_connector *connector,
6075 struct drm_crtc *crtc)
6076{
6077 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6078 uint8_t *eld = connector->eld;
6079 uint32_t eldv;
6080 uint32_t len;
6081 uint32_t i;
6082
6083 i = I915_READ(G4X_AUD_VID_DID);
6084
6085 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6086 eldv = G4X_ELDV_DEVCL_DEVBLC;
6087 else
6088 eldv = G4X_ELDV_DEVCTG;
6089
3a9627f4
WF		 6090 if (intel_eld_uptodate(connector,
6091 G4X_AUD_CNTL_ST, eldv,
6092 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6093 G4X_HDMIW_HDMIEDID))
6094 return;
6095
e0dac65e
WF		 6096 i = I915_READ(G4X_AUD_CNTL_ST);
6097 i &= ~(eldv | G4X_ELD_ADDR);
6098 len = (i >> 9) & 0x1f; /* ELD buffer size */
6099 I915_WRITE(G4X_AUD_CNTL_ST, i);
6100
6101 if (!eld[0])
6102 return;
6103
6104 len = min_t(uint8_t, eld[2], len);
6105 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6106 for (i = 0; i < len; i++)
6107 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6108
6109 i = I915_READ(G4X_AUD_CNTL_ST);
6110 i |= eldv;
6111 I915_WRITE(G4X_AUD_CNTL_ST, i);
6112}
6113
83358c85
WX		 6114static void haswell_write_eld(struct drm_connector *connector,
6115 struct drm_crtc *crtc)
6116{
6117 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6118 uint8_t *eld = connector->eld;
6119 struct drm_device *dev = crtc->dev;
7b9f35a6 6120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6121 uint32_t eldv;
6122 uint32_t i;
6123 int len;
6124 int pipe = to_intel_crtc(crtc)->pipe;
6125 int tmp;
6126
6127 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6128 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6129 int aud_config = HSW_AUD_CFG(pipe);
6130 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6131
6132
6133 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6134
6135 /* Audio output enable */
6136 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6137 tmp = I915_READ(aud_cntrl_st2);
6138 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6139 I915_WRITE(aud_cntrl_st2, tmp);
6140
6141 /* Wait for 1 vertical blank */
6142 intel_wait_for_vblank(dev, pipe);
6143
6144 /* Set ELD valid state */
6145 tmp = I915_READ(aud_cntrl_st2);
6146 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6147 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6148 I915_WRITE(aud_cntrl_st2, tmp);
6149 tmp = I915_READ(aud_cntrl_st2);
6150 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6151
6152 /* Enable HDMI mode */
6153 tmp = I915_READ(aud_config);
6154 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6155 /* clear N_programing_enable and N_value_index */
6156 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6157 I915_WRITE(aud_config, tmp);
6158
6159 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6160
6161 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6162 intel_crtc->eld_vld = true;
83358c85
WX		 6163
6164 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6165 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6166 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6167 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6168 } else
6169 I915_WRITE(aud_config, 0);
6170
6171 if (intel_eld_uptodate(connector,
6172 aud_cntrl_st2, eldv,
6173 aud_cntl_st, IBX_ELD_ADDRESS,
6174 hdmiw_hdmiedid))
6175 return;
6176
6177 i = I915_READ(aud_cntrl_st2);
6178 i &= ~eldv;
6179 I915_WRITE(aud_cntrl_st2, i);
6180
6181 if (!eld[0])
6182 return;
6183
6184 i = I915_READ(aud_cntl_st);
6185 i &= ~IBX_ELD_ADDRESS;
6186 I915_WRITE(aud_cntl_st, i);
6187 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6188 DRM_DEBUG_DRIVER("port num:%d\n", i);
6189
6190 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6191 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6192 for (i = 0; i < len; i++)
6193 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6194
6195 i = I915_READ(aud_cntrl_st2);
6196 i |= eldv;
6197 I915_WRITE(aud_cntrl_st2, i);
6198
6199}
6200
e0dac65e
WF		 6201static void ironlake_write_eld(struct drm_connector *connector,
6202 struct drm_crtc *crtc)
6203{
6204 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6205 uint8_t *eld = connector->eld;
6206 uint32_t eldv;
6207 uint32_t i;
6208 int len;
6209 int hdmiw_hdmiedid;
b6daa025 6210 int aud_config;
e0dac65e
WF		 6211 int aud_cntl_st;
6212 int aud_cntrl_st2;
9b138a83 6213 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6214
b3f33cbf 6215 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6216 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6217 aud_config = IBX_AUD_CFG(pipe);
6218 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6219 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6220 } else {
9b138a83
WX		 6221 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6222 aud_config = CPT_AUD_CFG(pipe);
6223 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6224 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6225 }
6226
9b138a83 6227 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6228
6229 i = I915_READ(aud_cntl_st);
9b138a83 6230 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6231 if (!i) {
6232 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6233 /* operate blindly on all ports */
1202b4c6
WF		 6234 eldv = IBX_ELD_VALIDB;
6235 eldv |= IBX_ELD_VALIDB << 4;
6236 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6237 } else {
2582a850 6238 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6239 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6240 }
6241
3a9627f4
WF		 6242 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6243 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6244 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6245 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6246 } else
6247 I915_WRITE(aud_config, 0);
e0dac65e 6248
3a9627f4
WF		 6249 if (intel_eld_uptodate(connector,
6250 aud_cntrl_st2, eldv,
6251 aud_cntl_st, IBX_ELD_ADDRESS,
6252 hdmiw_hdmiedid))
6253 return;
6254
e0dac65e
WF		 6255 i = I915_READ(aud_cntrl_st2);
6256 i &= ~eldv;
6257 I915_WRITE(aud_cntrl_st2, i);
6258
6259 if (!eld[0])
6260 return;
6261
e0dac65e 6262 i = I915_READ(aud_cntl_st);
1202b4c6 6263 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6264 I915_WRITE(aud_cntl_st, i);
6265
6266 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6267 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6268 for (i = 0; i < len; i++)
6269 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6270
6271 i = I915_READ(aud_cntrl_st2);
6272 i |= eldv;
6273 I915_WRITE(aud_cntrl_st2, i);
6274}
6275
6276void intel_write_eld(struct drm_encoder *encoder,
6277 struct drm_display_mode *mode)
6278{
6279 struct drm_crtc *crtc = encoder->crtc;
6280 struct drm_connector *connector;
6281 struct drm_device *dev = encoder->dev;
6282 struct drm_i915_private *dev_priv = dev->dev_private;
6283
6284 connector = drm_select_eld(encoder, mode);
6285 if (!connector)
6286 return;
6287
6288 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6289 connector->base.id,
6290 drm_get_connector_name(connector),
6291 connector->encoder->base.id,
6292 drm_get_encoder_name(connector->encoder));
6293
6294 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6295
6296 if (dev_priv->display.write_eld)
6297 dev_priv->display.write_eld(connector, crtc);
6298}
6299
79e53945
JB		 6300/** Loads the palette/gamma unit for the CRTC with the prepared values */
6301void intel_crtc_load_lut(struct drm_crtc *crtc)
6302{
6303 struct drm_device *dev = crtc->dev;
6304 struct drm_i915_private *dev_priv = dev->dev_private;
6305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6306 enum pipe pipe = intel_crtc->pipe;
6307 int palreg = PALETTE(pipe);
79e53945 6308 int i;
42db64ef 6309 bool reenable_ips = false;
79e53945
JB		 6310
6311 /* The clocks have to be on to load the palette. */
aed3f09d 6312 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6313 return;
6314
14420bd0
VS		 6315 if (!HAS_PCH_SPLIT(dev_priv->dev))
6316 assert_pll_enabled(dev_priv, pipe);
6317
f2b115e6 6318 /* use legacy palette for Ironlake */
bad720ff 6319 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6320 palreg = LGC_PALETTE(pipe);
6321
6322 /* Workaround : Do not read or write the pipe palette/gamma data while
6323 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6324 */
6325 if (intel_crtc->config.ips_enabled &&
6326 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6327 GAMMA_MODE_MODE_SPLIT)) {
6328 hsw_disable_ips(intel_crtc);
6329 reenable_ips = true;
6330 }
2c07245f 6331
79e53945
JB		 6332 for (i = 0; i < 256; i++) {
6333 I915_WRITE(palreg + 4 * i,
6334 (intel_crtc->lut_r[i] << 16) |
6335 (intel_crtc->lut_g[i] << 8) |
6336 intel_crtc->lut_b[i]);
6337 }
42db64ef
PZ		 6338
6339 if (reenable_ips)
6340 hsw_enable_ips(intel_crtc);
79e53945
JB		 6341}
6342
560b85bb
CW		 6343static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6344{
6345 struct drm_device *dev = crtc->dev;
6346 struct drm_i915_private *dev_priv = dev->dev_private;
6347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6348 bool visible = base != 0;
6349 u32 cntl;
6350
6351 if (intel_crtc->cursor_visible == visible)
6352 return;
6353
9db4a9c7 6354 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6355 if (visible) {
6356 /* On these chipsets we can only modify the base whilst
6357 * the cursor is disabled.
6358 */
9db4a9c7 6359 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6360
6361 cntl &= ~(CURSOR_FORMAT_MASK);
6362 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6363 cntl |= CURSOR_ENABLE |
6364 CURSOR_GAMMA_ENABLE |
6365 CURSOR_FORMAT_ARGB;
6366 } else
6367 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6368 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6369
6370 intel_crtc->cursor_visible = visible;
6371}
6372
6373static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6374{
6375 struct drm_device *dev = crtc->dev;
6376 struct drm_i915_private *dev_priv = dev->dev_private;
6377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6378 int pipe = intel_crtc->pipe;
6379 bool visible = base != 0;
6380
6381 if (intel_crtc->cursor_visible != visible) {
548f245b 6382 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6383 if (base) {
6384 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6385 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6386 cntl |= pipe << 28; /* Connect to correct pipe */
6387 } else {
6388 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6389 cntl |= CURSOR_MODE_DISABLE;
6390 }
9db4a9c7 6391 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6392
6393 intel_crtc->cursor_visible = visible;
6394 }
6395 /* and commit changes on next vblank */
9db4a9c7 6396 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6397}
6398
65a21cd6
JB		 6399static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6400{
6401 struct drm_device *dev = crtc->dev;
6402 struct drm_i915_private *dev_priv = dev->dev_private;
6403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6404 int pipe = intel_crtc->pipe;
6405 bool visible = base != 0;
6406
6407 if (intel_crtc->cursor_visible != visible) {
6408 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6409 if (base) {
6410 cntl &= ~CURSOR_MODE;
6411 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6412 } else {
6413 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6414 cntl |= CURSOR_MODE_DISABLE;
6415 }
86d3efce
VS		 6416 if (IS_HASWELL(dev))
6417 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6418 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6419
6420 intel_crtc->cursor_visible = visible;
6421 }
6422 /* and commit changes on next vblank */
6423 I915_WRITE(CURBASE_IVB(pipe), base);
6424}
6425
cda4b7d3 6426/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6427static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6428 bool on)
cda4b7d3
CW		 6429{
6430 struct drm_device *dev = crtc->dev;
6431 struct drm_i915_private *dev_priv = dev->dev_private;
6432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6433 int pipe = intel_crtc->pipe;
6434 int x = intel_crtc->cursor_x;
6435 int y = intel_crtc->cursor_y;
560b85bb 6436 u32 base, pos;
cda4b7d3
CW		 6437 bool visible;
6438
6439 pos = 0;
6440
6b383a7f 6441 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6442 base = intel_crtc->cursor_addr;
6443 if (x > (int) crtc->fb->width)
6444 base = 0;
6445
6446 if (y > (int) crtc->fb->height)
6447 base = 0;
6448 } else
6449 base = 0;
6450
6451 if (x < 0) {
6452 if (x + intel_crtc->cursor_width < 0)
6453 base = 0;
6454
6455 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6456 x = -x;
6457 }
6458 pos |= x << CURSOR_X_SHIFT;
6459
6460 if (y < 0) {
6461 if (y + intel_crtc->cursor_height < 0)
6462 base = 0;
6463
6464 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6465 y = -y;
6466 }
6467 pos |= y << CURSOR_Y_SHIFT;
6468
6469 visible = base != 0;
560b85bb 6470 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6471 return;
6472
0cd83aa9 6473 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6474 I915_WRITE(CURPOS_IVB(pipe), pos);
6475 ivb_update_cursor(crtc, base);
6476 } else {
6477 I915_WRITE(CURPOS(pipe), pos);
6478 if (IS_845G(dev) || IS_I865G(dev))
6479 i845_update_cursor(crtc, base);
6480 else
6481 i9xx_update_cursor(crtc, base);
6482 }
cda4b7d3
CW		 6483}
6484
79e53945 6485static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6486 struct drm_file *file,
79e53945
JB		 6487 uint32_t handle,
6488 uint32_t width, uint32_t height)
6489{
6490 struct drm_device *dev = crtc->dev;
6491 struct drm_i915_private *dev_priv = dev->dev_private;
6492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6493 struct drm_i915_gem_object *obj;
cda4b7d3 6494 uint32_t addr;
3f8bc370 6495 int ret;
79e53945 6496
79e53945
JB		 6497 /* if we want to turn off the cursor ignore width and height */
6498 if (!handle) {
28c97730 6499 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6500 addr = 0;
05394f39 6501 obj = NULL;
5004417d 6502 mutex_lock(&dev->struct_mutex);
3f8bc370 6503 goto finish;
79e53945
JB		 6504 }
6505
6506 /* Currently we only support 64x64 cursors */
6507 if (width != 64 || height != 64) {
6508 DRM_ERROR("we currently only support 64x64 cursors\n");
6509 return -EINVAL;
6510 }
6511
05394f39 6512 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6513 if (&obj->base == NULL)
79e53945
JB		 6514 return -ENOENT;
6515
05394f39 6516 if (obj->base.size < width * height * 4) {
79e53945 6517 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6518 ret = -ENOMEM;
6519 goto fail;
79e53945
JB		 6520 }
6521
71acb5eb 6522 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6523 mutex_lock(&dev->struct_mutex);
b295d1b6 6524 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6525 unsigned alignment;
6526
d9e86c0e
CW		 6527 if (obj->tiling_mode) {
6528 DRM_ERROR("cursor cannot be tiled\n");
6529 ret = -EINVAL;
6530 goto fail_locked;
6531 }
6532
693db184
CW		 6533 /* Note that the w/a also requires 2 PTE of padding following
6534 * the bo. We currently fill all unused PTE with the shadow
6535 * page and so we should always have valid PTE following the
6536 * cursor preventing the VT-d warning.
6537 */
6538 alignment = 0;
6539 if (need_vtd_wa(dev))
6540 alignment = 64*1024;
6541
6542 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6543 if (ret) {
6544 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6545 goto fail_locked;
e7b526bb
CW		 6546 }
6547
d9e86c0e
CW		 6548 ret = i915_gem_object_put_fence(obj);
6549 if (ret) {
2da3b9b9 6550 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6551 goto fail_unpin;
6552 }
6553
05394f39 6554 addr = obj->gtt_offset;
71acb5eb 6555 } else {
6eeefaf3 6556 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6557 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6558 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6559 align);
71acb5eb
DA		 6560 if (ret) {
6561 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6562 goto fail_locked;
71acb5eb 6563 }
05394f39 6564 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6565 }
6566
a6c45cf0 6567 if (IS_GEN2(dev))
14b60391
JB		 6568 I915_WRITE(CURSIZE, (height << 12) | width);
6569
3f8bc370 6570 finish:
3f8bc370 6571 if (intel_crtc->cursor_bo) {
b295d1b6 6572 if (dev_priv->info->cursor_needs_physical) {
05394f39 6573 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6574 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6575 } else
6576 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6577 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6578 }
80824003 6579
7f9872e0 6580 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6581
6582 intel_crtc->cursor_addr = addr;
05394f39 6583 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6584 intel_crtc->cursor_width = width;
6585 intel_crtc->cursor_height = height;
6586
40ccc72b 6587 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6588
79e53945 6589 return 0;
e7b526bb 6590fail_unpin:
05394f39 6591 i915_gem_object_unpin(obj);
7f9872e0 6592fail_locked:
34b8686e 6593 mutex_unlock(&dev->struct_mutex);
bc9025bd 6594fail:
05394f39 6595 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6596 return ret;
79e53945
JB		 6597}
6598
6599static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6600{
79e53945 6601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6602
cda4b7d3
CW		 6603 intel_crtc->cursor_x = x;
6604 intel_crtc->cursor_y = y;
652c393a 6605
40ccc72b 6606 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6607
6608 return 0;
6609}
6610
6611/** Sets the color ramps on behalf of RandR */
6612void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6613 u16 blue, int regno)
6614{
6615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6616
6617 intel_crtc->lut_r[regno] = red >> 8;
6618 intel_crtc->lut_g[regno] = green >> 8;
6619 intel_crtc->lut_b[regno] = blue >> 8;
6620}
6621
b8c00ac5
DA		 6622void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6623 u16 *blue, int regno)
6624{
6625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6626
6627 *red = intel_crtc->lut_r[regno] << 8;
6628 *green = intel_crtc->lut_g[regno] << 8;
6629 *blue = intel_crtc->lut_b[regno] << 8;
6630}
6631
79e53945 6632static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6633 u16 *blue, uint32_t start, uint32_t size)
79e53945 6634{
7203425a 6635 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6637
7203425a 6638 for (i = start; i < end; i++) {
79e53945
JB		 6639 intel_crtc->lut_r[i] = red[i] >> 8;
6640 intel_crtc->lut_g[i] = green[i] >> 8;
6641 intel_crtc->lut_b[i] = blue[i] >> 8;
6642 }
6643
6644 intel_crtc_load_lut(crtc);
6645}
6646
79e53945
JB		 6647/* VESA 640x480x72Hz mode to set on the pipe */
6648static struct drm_display_mode load_detect_mode = {
6649 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6650 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6651};
6652
d2dff872
CW		 6653static struct drm_framebuffer *
6654intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6655 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6656 struct drm_i915_gem_object *obj)
6657{
6658 struct intel_framebuffer *intel_fb;
6659 int ret;
6660
6661 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6662 if (!intel_fb) {
6663 drm_gem_object_unreference_unlocked(&obj->base);
6664 return ERR_PTR(-ENOMEM);
6665 }
6666
6667 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6668 if (ret) {
6669 drm_gem_object_unreference_unlocked(&obj->base);
6670 kfree(intel_fb);
6671 return ERR_PTR(ret);
6672 }
6673
6674 return &intel_fb->base;
6675}
6676
6677static u32
6678intel_framebuffer_pitch_for_width(int width, int bpp)
6679{
6680 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6681 return ALIGN(pitch, 64);
6682}
6683
6684static u32
6685intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6686{
6687 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6688 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6689}
6690
6691static struct drm_framebuffer *
6692intel_framebuffer_create_for_mode(struct drm_device *dev,
6693 struct drm_display_mode *mode,
6694 int depth, int bpp)
6695{
6696 struct drm_i915_gem_object *obj;
0fed39bd 6697 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6698
6699 obj = i915_gem_alloc_object(dev,
6700 intel_framebuffer_size_for_mode(mode, bpp));
6701 if (obj == NULL)
6702 return ERR_PTR(-ENOMEM);
6703
6704 mode_cmd.width = mode->hdisplay;
6705 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6706 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6707 bpp);
5ca0c34a 6708 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6709
6710 return intel_framebuffer_create(dev, &mode_cmd, obj);
6711}
6712
6713static struct drm_framebuffer *
6714mode_fits_in_fbdev(struct drm_device *dev,
6715 struct drm_display_mode *mode)
6716{
6717 struct drm_i915_private *dev_priv = dev->dev_private;
6718 struct drm_i915_gem_object *obj;
6719 struct drm_framebuffer *fb;
6720
6721 if (dev_priv->fbdev == NULL)
6722 return NULL;
6723
6724 obj = dev_priv->fbdev->ifb.obj;
6725 if (obj == NULL)
6726 return NULL;
6727
6728 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6729 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6730 fb->bits_per_pixel))
d2dff872
CW		 6731 return NULL;
6732
01f2c773 6733 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6734 return NULL;
6735
6736 return fb;
6737}
6738
d2434ab7 6739bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6740 struct drm_display_mode *mode,
8261b191 6741 struct intel_load_detect_pipe *old)
79e53945
JB		 6742{
6743 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6744 struct intel_encoder *intel_encoder =
6745 intel_attached_encoder(connector);
79e53945 6746 struct drm_crtc *possible_crtc;
4ef69c7a 6747 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6748 struct drm_crtc *crtc = NULL;
6749 struct drm_device *dev = encoder->dev;
94352cf9 6750 struct drm_framebuffer *fb;
79e53945
JB		 6751 int i = -1;
6752
d2dff872
CW		 6753 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6754 connector->base.id, drm_get_connector_name(connector),
6755 encoder->base.id, drm_get_encoder_name(encoder));
6756
79e53945
JB		 6757 /*
6758 * Algorithm gets a little messy:
7a5e4805 6759 *
79e53945
JB		 6760 * - if the connector already has an assigned crtc, use it (but make
6761 * sure it's on first)
7a5e4805 6762 *
79e53945
JB		 6763 * - try to find the first unused crtc that can drive this connector,
6764 * and use that if we find one
79e53945
JB		 6765 */
6766
6767 /* See if we already have a CRTC for this connector */
6768 if (encoder->crtc) {
6769 crtc = encoder->crtc;
8261b191 6770
7b24056b
DV		 6771 mutex_lock(&crtc->mutex);
6772
24218aac 6773 old->dpms_mode = connector->dpms;
8261b191
CW		 6774 old->load_detect_temp = false;
6775
6776 /* Make sure the crtc and connector are running */
24218aac
DV		 6777 if (connector->dpms != DRM_MODE_DPMS_ON)
6778 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6779
7173188d 6780 return true;
79e53945
JB		 6781 }
6782
6783 /* Find an unused one (if possible) */
6784 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6785 i++;
6786 if (!(encoder->possible_crtcs & (1 << i)))
6787 continue;
6788 if (!possible_crtc->enabled) {
6789 crtc = possible_crtc;
6790 break;
6791 }
79e53945
JB		 6792 }
6793
6794 /*
6795 * If we didn't find an unused CRTC, don't use any.
6796 */
6797 if (!crtc) {
7173188d
CW		 6798 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6799 return false;
79e53945
JB		 6800 }
6801
7b24056b 6802 mutex_lock(&crtc->mutex);
fc303101
DV		 6803 intel_encoder->new_crtc = to_intel_crtc(crtc);
6804 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6805
6806 intel_crtc = to_intel_crtc(crtc);
24218aac 6807 old->dpms_mode = connector->dpms;
8261b191 6808 old->load_detect_temp = true;
d2dff872 6809 old->release_fb = NULL;
79e53945 6810
6492711d
CW		 6811 if (!mode)
6812 mode = &load_detect_mode;
79e53945 6813
d2dff872
CW		 6814 /* We need a framebuffer large enough to accommodate all accesses
6815 * that the plane may generate whilst we perform load detection.
6816 * We can not rely on the fbcon either being present (we get called
6817 * during its initialisation to detect all boot displays, or it may
6818 * not even exist) or that it is large enough to satisfy the
6819 * requested mode.
6820 */
94352cf9
DV		 6821 fb = mode_fits_in_fbdev(dev, mode);
6822 if (fb == NULL) {
d2dff872 6823 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6824 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6825 old->release_fb = fb;
d2dff872
CW		 6826 } else
6827 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6828 if (IS_ERR(fb)) {
d2dff872 6829 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6830 mutex_unlock(&crtc->mutex);
0e8b3d3e 6831 return false;
79e53945 6832 }
79e53945 6833
c0c36b94 6834 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6835 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6836 if (old->release_fb)
6837 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6838 mutex_unlock(&crtc->mutex);
0e8b3d3e 6839 return false;
79e53945 6840 }
7173188d 6841
79e53945 6842 /* let the connector get through one full cycle before testing */
9d0498a2 6843 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6844 return true;
79e53945
JB		 6845}
6846
d2434ab7 6847void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6848 struct intel_load_detect_pipe *old)
79e53945 6849{
d2434ab7
DV		 6850 struct intel_encoder *intel_encoder =
6851 intel_attached_encoder(connector);
4ef69c7a 6852 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6853 struct drm_crtc *crtc = encoder->crtc;
79e53945 6854
d2dff872
CW		 6855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6856 connector->base.id, drm_get_connector_name(connector),
6857 encoder->base.id, drm_get_encoder_name(encoder));
6858
8261b191 6859 if (old->load_detect_temp) {
fc303101
DV		 6860 to_intel_connector(connector)->new_encoder = NULL;
6861 intel_encoder->new_crtc = NULL;
6862 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6863
36206361
DV		 6864 if (old->release_fb) {
6865 drm_framebuffer_unregister_private(old->release_fb);
6866 drm_framebuffer_unreference(old->release_fb);
6867 }
d2dff872 6868
67c96400 6869 mutex_unlock(&crtc->mutex);
0622a53c 6870 return;
79e53945
JB		 6871 }
6872
c751ce4f 6873 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6874 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6875 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6876
6877 mutex_unlock(&crtc->mutex);
79e53945
JB		 6878}
6879
6880/* Returns the clock of the currently programmed mode of the given pipe. */
6881static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6882{
6883 struct drm_i915_private *dev_priv = dev->dev_private;
6884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6885 int pipe = intel_crtc->pipe;
548f245b 6886 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6887 u32 fp;
6888 intel_clock_t clock;
6889
6890 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6891 fp = I915_READ(FP0(pipe));
79e53945 6892 else
39adb7a5 6893 fp = I915_READ(FP1(pipe));
79e53945
JB		 6894
6895 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6896 if (IS_PINEVIEW(dev)) {
6897 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6898 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6899 } else {
6900 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6901 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6902 }
6903
a6c45cf0 6904 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6905 if (IS_PINEVIEW(dev))
6906 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6907 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6908 else
6909 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6910 DPLL_FPA01_P1_POST_DIV_SHIFT);
6911
6912 switch (dpll & DPLL_MODE_MASK) {
6913 case DPLLB_MODE_DAC_SERIAL:
6914 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6915 5 : 10;
6916 break;
6917 case DPLLB_MODE_LVDS:
6918 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6919 7 : 14;
6920 break;
6921 default:
28c97730 6922 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6923 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6924 return 0;
6925 }
6926
ac58c3f0
DV		 6927 if (IS_PINEVIEW(dev))
6928 pineview_clock(96000, &clock);
6929 else
6930 i9xx_clock(96000, &clock);
79e53945
JB		 6931 } else {
6932 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6933
6934 if (is_lvds) {
6935 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6936 DPLL_FPA01_P1_POST_DIV_SHIFT);
6937 clock.p2 = 14;
6938
6939 if ((dpll & PLL_REF_INPUT_MASK) ==
6940 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6941 /* XXX: might not be 66MHz */
ac58c3f0 6942 i9xx_clock(66000, &clock);
79e53945 6943 } else
ac58c3f0 6944 i9xx_clock(48000, &clock);
79e53945
JB		 6945 } else {
6946 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6947 clock.p1 = 2;
6948 else {
6949 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6950 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6951 }
6952 if (dpll & PLL_P2_DIVIDE_BY_4)
6953 clock.p2 = 4;
6954 else
6955 clock.p2 = 2;
6956
ac58c3f0 6957 i9xx_clock(48000, &clock);
79e53945
JB		 6958 }
6959 }
6960
6961 /* XXX: It would be nice to validate the clocks, but we can't reuse
6962 * i830PllIsValid() because it relies on the xf86_config connector
6963 * configuration being accurate, which it isn't necessarily.
6964 */
6965
6966 return clock.dot;
6967}
6968
6969/** Returns the currently programmed mode of the given pipe. */
6970struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6971 struct drm_crtc *crtc)
6972{
548f245b 6973 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6975 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6976 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6977 int htot = I915_READ(HTOTAL(cpu_transcoder));
6978 int hsync = I915_READ(HSYNC(cpu_transcoder));
6979 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6980 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6981
6982 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6983 if (!mode)
6984 return NULL;
6985
6986 mode->clock = intel_crtc_clock_get(dev, crtc);
6987 mode->hdisplay = (htot & 0xffff) + 1;
6988 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6989 mode->hsync_start = (hsync & 0xffff) + 1;
6990 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6991 mode->vdisplay = (vtot & 0xffff) + 1;
6992 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6993 mode->vsync_start = (vsync & 0xffff) + 1;
6994 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6995
6996 drm_mode_set_name(mode);
79e53945
JB		 6997
6998 return mode;
6999}
7000
3dec0095 7001static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7002{
7003 struct drm_device *dev = crtc->dev;
7004 drm_i915_private_t *dev_priv = dev->dev_private;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7007 int dpll_reg = DPLL(pipe);
7008 int dpll;
652c393a 7009
bad720ff 7010 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7011 return;
7012
7013 if (!dev_priv->lvds_downclock_avail)
7014 return;
7015
dbdc6479 7016 dpll = I915_READ(dpll_reg);
652c393a 7017 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7018 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7019
8ac5a6d5 7020 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7021
7022 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7023 I915_WRITE(dpll_reg, dpll);
9d0498a2 7024 intel_wait_for_vblank(dev, pipe);
dbdc6479 7025
652c393a
JB		 7026 dpll = I915_READ(dpll_reg);
7027 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7028 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7029 }
652c393a
JB		 7030}
7031
7032static void intel_decrease_pllclock(struct drm_crtc *crtc)
7033{
7034 struct drm_device *dev = crtc->dev;
7035 drm_i915_private_t *dev_priv = dev->dev_private;
7036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7037
bad720ff 7038 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7039 return;
7040
7041 if (!dev_priv->lvds_downclock_avail)
7042 return;
7043
7044 /*
7045 * Since this is called by a timer, we should never get here in
7046 * the manual case.
7047 */
7048 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7049 int pipe = intel_crtc->pipe;
7050 int dpll_reg = DPLL(pipe);
7051 int dpll;
f6e5b160 7052
44d98a61 7053 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7054
8ac5a6d5 7055 assert_panel_unlocked(dev_priv, pipe);
652c393a 7056
dc257cf1 7057 dpll = I915_READ(dpll_reg);
652c393a
JB		 7058 dpll |= DISPLAY_RATE_SELECT_FPA1;
7059 I915_WRITE(dpll_reg, dpll);
9d0498a2 7060 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7061 dpll = I915_READ(dpll_reg);
7062 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7063 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7064 }
7065
7066}
7067
f047e395
CW		 7068void intel_mark_busy(struct drm_device *dev)
7069{
f047e395
CW		 7070 i915_update_gfx_val(dev->dev_private);
7071}
7072
7073void intel_mark_idle(struct drm_device *dev)
652c393a 7074{
652c393a 7075 struct drm_crtc *crtc;
652c393a
JB		 7076
7077 if (!i915_powersave)
7078 return;
7079
652c393a 7080 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7081 if (!crtc->fb)
7082 continue;
7083
725a5b54 7084 intel_decrease_pllclock(crtc);
652c393a 7085 }
652c393a
JB		 7086}
7087
c65355bb
CW		 7088void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7089 struct intel_ring_buffer *ring)
652c393a 7090{
f047e395
CW		 7091 struct drm_device *dev = obj->base.dev;
7092 struct drm_crtc *crtc;
652c393a 7093
f047e395 7094 if (!i915_powersave)
acb87dfb
CW		 7095 return;
7096
652c393a
JB		 7097 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7098 if (!crtc->fb)
7099 continue;
7100
c65355bb
CW		 7101 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7102 continue;
7103
7104 intel_increase_pllclock(crtc);
7105 if (ring && intel_fbc_enabled(dev))
7106 ring->fbc_dirty = true;
652c393a
JB		 7107 }
7108}
7109
79e53945
JB		 7110static void intel_crtc_destroy(struct drm_crtc *crtc)
7111{
7112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7113 struct drm_device *dev = crtc->dev;
7114 struct intel_unpin_work *work;
7115 unsigned long flags;
7116
7117 spin_lock_irqsave(&dev->event_lock, flags);
7118 work = intel_crtc->unpin_work;
7119 intel_crtc->unpin_work = NULL;
7120 spin_unlock_irqrestore(&dev->event_lock, flags);
7121
7122 if (work) {
7123 cancel_work_sync(&work->work);
7124 kfree(work);
7125 }
79e53945 7126
40ccc72b
MK		 7127 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7128
79e53945 7129 drm_crtc_cleanup(crtc);
67e77c5a 7130
79e53945
JB		 7131 kfree(intel_crtc);
7132}
7133
6b95a207
KH		 7134static void intel_unpin_work_fn(struct work_struct *__work)
7135{
7136 struct intel_unpin_work *work =
7137 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7138 struct drm_device *dev = work->crtc->dev;
6b95a207 7139
b4a98e57 7140 mutex_lock(&dev->struct_mutex);
1690e1eb 7141 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7142 drm_gem_object_unreference(&work->pending_flip_obj->base);
7143 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7144
b4a98e57
CW		 7145 intel_update_fbc(dev);
7146 mutex_unlock(&dev->struct_mutex);
7147
7148 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7149 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7150
6b95a207
KH		 7151 kfree(work);
7152}
7153
1afe3e9d 7154static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7155 struct drm_crtc *crtc)
6b95a207
KH		 7156{
7157 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7159 struct intel_unpin_work *work;
6b95a207
KH		 7160 unsigned long flags;
7161
7162 /* Ignore early vblank irqs */
7163 if (intel_crtc == NULL)
7164 return;
7165
7166 spin_lock_irqsave(&dev->event_lock, flags);
7167 work = intel_crtc->unpin_work;
e7d841ca
CW		 7168
7169 /* Ensure we don't miss a work->pending update ... */
7170 smp_rmb();
7171
7172 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7173 spin_unlock_irqrestore(&dev->event_lock, flags);
7174 return;
7175 }
7176
e7d841ca
CW		 7177 /* and that the unpin work is consistent wrt ->pending. */
7178 smp_rmb();
7179
6b95a207 7180 intel_crtc->unpin_work = NULL;
6b95a207 7181
45a066eb
RC		 7182 if (work->event)
7183 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7184
0af7e4df
MK		 7185 drm_vblank_put(dev, intel_crtc->pipe);
7186
6b95a207
KH		 7187 spin_unlock_irqrestore(&dev->event_lock, flags);
7188
2c10d571 7189 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7190
7191 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7192
7193 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7194}
7195
1afe3e9d
JB		 7196void intel_finish_page_flip(struct drm_device *dev, int pipe)
7197{
7198 drm_i915_private_t *dev_priv = dev->dev_private;
7199 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7200
49b14a5c 7201 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7202}
7203
7204void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7205{
7206 drm_i915_private_t *dev_priv = dev->dev_private;
7207 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7208
49b14a5c 7209 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7210}
7211
6b95a207
KH		 7212void intel_prepare_page_flip(struct drm_device *dev, int plane)
7213{
7214 drm_i915_private_t *dev_priv = dev->dev_private;
7215 struct intel_crtc *intel_crtc =
7216 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7217 unsigned long flags;
7218
e7d841ca
CW		 7219 /* NB: An MMIO update of the plane base pointer will also
7220 * generate a page-flip completion irq, i.e. every modeset
7221 * is also accompanied by a spurious intel_prepare_page_flip().
7222 */
6b95a207 7223 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7224 if (intel_crtc->unpin_work)
7225 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7226 spin_unlock_irqrestore(&dev->event_lock, flags);
7227}
7228
e7d841ca
CW		 7229inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7230{
7231 /* Ensure that the work item is consistent when activating it ... */
7232 smp_wmb();
7233 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7234 /* and that it is marked active as soon as the irq could fire. */
7235 smp_wmb();
7236}
7237
8c9f3aaf
JB		 7238static int intel_gen2_queue_flip(struct drm_device *dev,
7239 struct drm_crtc *crtc,
7240 struct drm_framebuffer *fb,
7241 struct drm_i915_gem_object *obj)
7242{
7243 struct drm_i915_private *dev_priv = dev->dev_private;
7244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7245 u32 flip_mask;
6d90c952 7246 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7247 int ret;
7248
6d90c952 7249 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7250 if (ret)
83d4092b 7251 goto err;
8c9f3aaf 7252
6d90c952 7253 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7254 if (ret)
83d4092b 7255 goto err_unpin;
8c9f3aaf
JB		 7256
7257 /* Can't queue multiple flips, so wait for the previous
7258 * one to finish before executing the next.
7259 */
7260 if (intel_crtc->plane)
7261 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7262 else
7263 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7264 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7265 intel_ring_emit(ring, MI_NOOP);
7266 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7267 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7268 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7269 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7270 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7271
7272 intel_mark_page_flip_active(intel_crtc);
6d90c952 7273 intel_ring_advance(ring);
83d4092b
CW		 7274 return 0;
7275
7276err_unpin:
7277 intel_unpin_fb_obj(obj);
7278err:
8c9f3aaf
JB		 7279 return ret;
7280}
7281
7282static int intel_gen3_queue_flip(struct drm_device *dev,
7283 struct drm_crtc *crtc,
7284 struct drm_framebuffer *fb,
7285 struct drm_i915_gem_object *obj)
7286{
7287 struct drm_i915_private *dev_priv = dev->dev_private;
7288 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7289 u32 flip_mask;
6d90c952 7290 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7291 int ret;
7292
6d90c952 7293 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7294 if (ret)
83d4092b 7295 goto err;
8c9f3aaf 7296
6d90c952 7297 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7298 if (ret)
83d4092b 7299 goto err_unpin;
8c9f3aaf
JB		 7300
7301 if (intel_crtc->plane)
7302 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7303 else
7304 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7305 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7306 intel_ring_emit(ring, MI_NOOP);
7307 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7308 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7309 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7310 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7311 intel_ring_emit(ring, MI_NOOP);
7312
e7d841ca 7313 intel_mark_page_flip_active(intel_crtc);
6d90c952 7314 intel_ring_advance(ring);
83d4092b
CW		 7315 return 0;
7316
7317err_unpin:
7318 intel_unpin_fb_obj(obj);
7319err:
8c9f3aaf
JB		 7320 return ret;
7321}
7322
7323static int intel_gen4_queue_flip(struct drm_device *dev,
7324 struct drm_crtc *crtc,
7325 struct drm_framebuffer *fb,
7326 struct drm_i915_gem_object *obj)
7327{
7328 struct drm_i915_private *dev_priv = dev->dev_private;
7329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7330 uint32_t pf, pipesrc;
6d90c952 7331 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7332 int ret;
7333
6d90c952 7334 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7335 if (ret)
83d4092b 7336 goto err;
8c9f3aaf 7337
6d90c952 7338 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7339 if (ret)
83d4092b 7340 goto err_unpin;
8c9f3aaf
JB		 7341
7342 /* i965+ uses the linear or tiled offsets from the
7343 * Display Registers (which do not change across a page-flip)
7344 * so we need only reprogram the base address.
7345 */
6d90c952
DV		 7346 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7347 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7348 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7349 intel_ring_emit(ring,
7350 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7351 obj->tiling_mode);
8c9f3aaf
JB		 7352
7353 /* XXX Enabling the panel-fitter across page-flip is so far
7354 * untested on non-native modes, so ignore it for now.
7355 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7356 */
7357 pf = 0;
7358 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7359 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7360
7361 intel_mark_page_flip_active(intel_crtc);
6d90c952 7362 intel_ring_advance(ring);
83d4092b
CW		 7363 return 0;
7364
7365err_unpin:
7366 intel_unpin_fb_obj(obj);
7367err:
8c9f3aaf
JB		 7368 return ret;
7369}
7370
7371static int intel_gen6_queue_flip(struct drm_device *dev,
7372 struct drm_crtc *crtc,
7373 struct drm_framebuffer *fb,
7374 struct drm_i915_gem_object *obj)
7375{
7376 struct drm_i915_private *dev_priv = dev->dev_private;
7377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7378 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7379 uint32_t pf, pipesrc;
7380 int ret;
7381
6d90c952 7382 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7383 if (ret)
83d4092b 7384 goto err;
8c9f3aaf 7385
6d90c952 7386 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7387 if (ret)
83d4092b 7388 goto err_unpin;
8c9f3aaf 7389
6d90c952
DV		 7390 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7391 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7392 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7393 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7394
dc257cf1
DV		 7395 /* Contrary to the suggestions in the documentation,
7396 * "Enable Panel Fitter" does not seem to be required when page
7397 * flipping with a non-native mode, and worse causes a normal
7398 * modeset to fail.
7399 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7400 */
7401 pf = 0;
8c9f3aaf 7402 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7403 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7404
7405 intel_mark_page_flip_active(intel_crtc);
6d90c952 7406 intel_ring_advance(ring);
83d4092b
CW		 7407 return 0;
7408
7409err_unpin:
7410 intel_unpin_fb_obj(obj);
7411err:
8c9f3aaf
JB		 7412 return ret;
7413}
7414
7c9017e5
JB		 7415/*
7416 * On gen7 we currently use the blit ring because (in early silicon at least)
7417 * the render ring doesn't give us interrpts for page flip completion, which
7418 * means clients will hang after the first flip is queued. Fortunately the
7419 * blit ring generates interrupts properly, so use it instead.
7420 */
7421static int intel_gen7_queue_flip(struct drm_device *dev,
7422 struct drm_crtc *crtc,
7423 struct drm_framebuffer *fb,
7424 struct drm_i915_gem_object *obj)
7425{
7426 struct drm_i915_private *dev_priv = dev->dev_private;
7427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7428 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7429 uint32_t plane_bit = 0;
7c9017e5
JB		 7430 int ret;
7431
7432 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7433 if (ret)
83d4092b 7434 goto err;
7c9017e5 7435
cb05d8de
DV		 7436 switch(intel_crtc->plane) {
7437 case PLANE_A:
7438 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7439 break;
7440 case PLANE_B:
7441 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7442 break;
7443 case PLANE_C:
7444 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7445 break;
7446 default:
7447 WARN_ONCE(1, "unknown plane in flip command\n");
7448 ret = -ENODEV;
ab3951eb 7449 goto err_unpin;
cb05d8de
DV		 7450 }
7451
7c9017e5
JB		 7452 ret = intel_ring_begin(ring, 4);
7453 if (ret)
83d4092b 7454 goto err_unpin;
7c9017e5 7455
cb05d8de 7456 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7457 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7458 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7459 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7460
7461 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7462 intel_ring_advance(ring);
83d4092b
CW		 7463 return 0;
7464
7465err_unpin:
7466 intel_unpin_fb_obj(obj);
7467err:
7c9017e5
JB		 7468 return ret;
7469}
7470
8c9f3aaf
JB		 7471static int intel_default_queue_flip(struct drm_device *dev,
7472 struct drm_crtc *crtc,
7473 struct drm_framebuffer *fb,
7474 struct drm_i915_gem_object *obj)
7475{
7476 return -ENODEV;
7477}
7478
6b95a207
KH		 7479static int intel_crtc_page_flip(struct drm_crtc *crtc,
7480 struct drm_framebuffer *fb,
7481 struct drm_pending_vblank_event *event)
7482{
7483 struct drm_device *dev = crtc->dev;
7484 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7485 struct drm_framebuffer *old_fb = crtc->fb;
7486 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7488 struct intel_unpin_work *work;
8c9f3aaf 7489 unsigned long flags;
52e68630 7490 int ret;
6b95a207 7491
e6a595d2
VS		 7492 /* Can't change pixel format via MI display flips. */
7493 if (fb->pixel_format != crtc->fb->pixel_format)
7494 return -EINVAL;
7495
7496 /*
7497 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7498 * Note that pitch changes could also affect these register.
7499 */
7500 if (INTEL_INFO(dev)->gen > 3 &&
7501 (fb->offsets[0] != crtc->fb->offsets[0] ||
7502 fb->pitches[0] != crtc->fb->pitches[0]))
7503 return -EINVAL;
7504
6b95a207
KH		 7505 work = kzalloc(sizeof *work, GFP_KERNEL);
7506 if (work == NULL)
7507 return -ENOMEM;
7508
6b95a207 7509 work->event = event;
b4a98e57 7510 work->crtc = crtc;
4a35f83b 7511 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7512 INIT_WORK(&work->work, intel_unpin_work_fn);
7513
7317c75e
JB		 7514 ret = drm_vblank_get(dev, intel_crtc->pipe);
7515 if (ret)
7516 goto free_work;
7517
6b95a207
KH		 7518 /* We borrow the event spin lock for protecting unpin_work */
7519 spin_lock_irqsave(&dev->event_lock, flags);
7520 if (intel_crtc->unpin_work) {
7521 spin_unlock_irqrestore(&dev->event_lock, flags);
7522 kfree(work);
7317c75e 7523 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7524
7525 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7526 return -EBUSY;
7527 }
7528 intel_crtc->unpin_work = work;
7529 spin_unlock_irqrestore(&dev->event_lock, flags);
7530
b4a98e57
CW		 7531 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7532 flush_workqueue(dev_priv->wq);
7533
79158103
CW		 7534 ret = i915_mutex_lock_interruptible(dev);
7535 if (ret)
7536 goto cleanup;
6b95a207 7537
75dfca80 7538 /* Reference the objects for the scheduled work. */
05394f39
CW		 7539 drm_gem_object_reference(&work->old_fb_obj->base);
7540 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7541
7542 crtc->fb = fb;
96b099fd 7543
e1f99ce6 7544 work->pending_flip_obj = obj;
e1f99ce6 7545
4e5359cd
SF		 7546 work->enable_stall_check = true;
7547
b4a98e57 7548 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7549 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7550
8c9f3aaf
JB		 7551 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7552 if (ret)
7553 goto cleanup_pending;
6b95a207 7554
7782de3b 7555 intel_disable_fbc(dev);
c65355bb 7556 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7557 mutex_unlock(&dev->struct_mutex);
7558
e5510fac
JB		 7559 trace_i915_flip_request(intel_crtc->plane, obj);
7560
6b95a207 7561 return 0;
96b099fd 7562
8c9f3aaf 7563cleanup_pending:
b4a98e57 7564 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7565 crtc->fb = old_fb;
05394f39
CW		 7566 drm_gem_object_unreference(&work->old_fb_obj->base);
7567 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7568 mutex_unlock(&dev->struct_mutex);
7569
79158103 7570cleanup:
96b099fd
CW		 7571 spin_lock_irqsave(&dev->event_lock, flags);
7572 intel_crtc->unpin_work = NULL;
7573 spin_unlock_irqrestore(&dev->event_lock, flags);
7574
7317c75e
JB		 7575 drm_vblank_put(dev, intel_crtc->pipe);
7576free_work:
96b099fd
CW		 7577 kfree(work);
7578
7579 return ret;
6b95a207
KH		 7580}
7581
f6e5b160 7582static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7583 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7584 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7585};
7586
50f56119
DV		 7587static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7588 struct drm_crtc *crtc)
7589{
7590 struct drm_device *dev;
7591 struct drm_crtc *tmp;
7592 int crtc_mask = 1;
47f1c6c9 7593
50f56119 7594 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7595
50f56119 7596 dev = crtc->dev;
47f1c6c9 7597
50f56119
DV		 7598 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7599 if (tmp == crtc)
7600 break;
7601 crtc_mask <<= 1;
7602 }
47f1c6c9 7603
50f56119
DV		 7604 if (encoder->possible_crtcs & crtc_mask)
7605 return true;
7606 return false;
47f1c6c9 7607}
79e53945 7608
9a935856
DV		 7609/**
7610 * intel_modeset_update_staged_output_state
7611 *
7612 * Updates the staged output configuration state, e.g. after we've read out the
7613 * current hw state.
7614 */
7615static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7616{
9a935856
DV		 7617 struct intel_encoder *encoder;
7618 struct intel_connector *connector;
f6e5b160 7619
9a935856
DV		 7620 list_for_each_entry(connector, &dev->mode_config.connector_list,
7621 base.head) {
7622 connector->new_encoder =
7623 to_intel_encoder(connector->base.encoder);
7624 }
f6e5b160 7625
9a935856
DV		 7626 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7627 base.head) {
7628 encoder->new_crtc =
7629 to_intel_crtc(encoder->base.crtc);
7630 }
f6e5b160
CW		 7631}
7632
9a935856
DV		 7633/**
7634 * intel_modeset_commit_output_state
7635 *
7636 * This function copies the stage display pipe configuration to the real one.
7637 */
7638static void intel_modeset_commit_output_state(struct drm_device *dev)
7639{
7640 struct intel_encoder *encoder;
7641 struct intel_connector *connector;
f6e5b160 7642
9a935856
DV		 7643 list_for_each_entry(connector, &dev->mode_config.connector_list,
7644 base.head) {
7645 connector->base.encoder = &connector->new_encoder->base;
7646 }
f6e5b160 7647
9a935856
DV		 7648 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7649 base.head) {
7650 encoder->base.crtc = &encoder->new_crtc->base;
7651 }
7652}
7653
050f7aeb
DV		 7654static void
7655connected_sink_compute_bpp(struct intel_connector * connector,
7656 struct intel_crtc_config *pipe_config)
7657{
7658 int bpp = pipe_config->pipe_bpp;
7659
7660 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7661 connector->base.base.id,
7662 drm_get_connector_name(&connector->base));
7663
7664 /* Don't use an invalid EDID bpc value */
7665 if (connector->base.display_info.bpc &&
7666 connector->base.display_info.bpc * 3 < bpp) {
7667 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7668 bpp, connector->base.display_info.bpc*3);
7669 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7670 }
7671
7672 /* Clamp bpp to 8 on screens without EDID 1.4 */
7673 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7674 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7675 bpp);
7676 pipe_config->pipe_bpp = 24;
7677 }
7678}
7679
4e53c2e0 7680static int
050f7aeb
DV		 7681compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7682 struct drm_framebuffer *fb,
7683 struct intel_crtc_config *pipe_config)
4e53c2e0 7684{
050f7aeb
DV		 7685 struct drm_device *dev = crtc->base.dev;
7686 struct intel_connector *connector;
4e53c2e0
DV		 7687 int bpp;
7688
d42264b1
DV		 7689 switch (fb->pixel_format) {
7690 case DRM_FORMAT_C8:
4e53c2e0
DV		 7691 bpp = 8*3; /* since we go through a colormap */
7692 break;
d42264b1
DV		 7693 case DRM_FORMAT_XRGB1555:
7694 case DRM_FORMAT_ARGB1555:
7695 /* checked in intel_framebuffer_init already */
7696 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7697 return -EINVAL;
7698 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7699 bpp = 6*3; /* min is 18bpp */
7700 break;
d42264b1
DV		 7701 case DRM_FORMAT_XBGR8888:
7702 case DRM_FORMAT_ABGR8888:
7703 /* checked in intel_framebuffer_init already */
7704 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7705 return -EINVAL;
7706 case DRM_FORMAT_XRGB8888:
7707 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7708 bpp = 8*3;
7709 break;
d42264b1
DV		 7710 case DRM_FORMAT_XRGB2101010:
7711 case DRM_FORMAT_ARGB2101010:
7712 case DRM_FORMAT_XBGR2101010:
7713 case DRM_FORMAT_ABGR2101010:
7714 /* checked in intel_framebuffer_init already */
7715 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7716 return -EINVAL;
4e53c2e0
DV		 7717 bpp = 10*3;
7718 break;
baba133a 7719 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7720 default:
7721 DRM_DEBUG_KMS("unsupported depth\n");
7722 return -EINVAL;
7723 }
7724
4e53c2e0
DV		 7725 pipe_config->pipe_bpp = bpp;
7726
7727 /* Clamp display bpp to EDID value */
7728 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7729 base.head) {
1b829e05
DV		 7730 if (!connector->new_encoder ||
7731 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7732 continue;
7733
050f7aeb 7734 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7735 }
7736
7737 return bpp;
7738}
7739
c0b03411
DV		 7740static void intel_dump_pipe_config(struct intel_crtc *crtc,
7741 struct intel_crtc_config *pipe_config,
7742 const char *context)
7743{
7744 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7745 context, pipe_name(crtc->pipe));
7746
7747 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7748 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7749 pipe_config->pipe_bpp, pipe_config->dither);
7750 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7751 pipe_config->has_pch_encoder,
7752 pipe_config->fdi_lanes,
7753 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7754 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7755 pipe_config->fdi_m_n.tu);
7756 DRM_DEBUG_KMS("requested mode:\n");
7757 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7758 DRM_DEBUG_KMS("adjusted mode:\n");
7759 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7760 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7761 pipe_config->gmch_pfit.control,
7762 pipe_config->gmch_pfit.pgm_ratios,
7763 pipe_config->gmch_pfit.lvds_border_bits);
7764 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7765 pipe_config->pch_pfit.pos,
7766 pipe_config->pch_pfit.size);
42db64ef 7767 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7768}
7769
accfc0c5
DV		 7770static bool check_encoder_cloning(struct drm_crtc *crtc)
7771{
7772 int num_encoders = 0;
7773 bool uncloneable_encoders = false;
7774 struct intel_encoder *encoder;
7775
7776 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7777 base.head) {
7778 if (&encoder->new_crtc->base != crtc)
7779 continue;
7780
7781 num_encoders++;
7782 if (!encoder->cloneable)
7783 uncloneable_encoders = true;
7784 }
7785
7786 return !(num_encoders > 1 && uncloneable_encoders);
7787}
7788
b8cecdf5
DV		 7789static struct intel_crtc_config *
7790intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7791 struct drm_framebuffer *fb,
b8cecdf5 7792 struct drm_display_mode *mode)
ee7b9f93 7793{
7758a113 7794 struct drm_device *dev = crtc->dev;
7758a113
DV		 7795 struct drm_encoder_helper_funcs *encoder_funcs;
7796 struct intel_encoder *encoder;
b8cecdf5 7797 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7798 int plane_bpp, ret = -EINVAL;
7799 bool retry = true;
ee7b9f93 7800
accfc0c5
DV		 7801 if (!check_encoder_cloning(crtc)) {
7802 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7803 return ERR_PTR(-EINVAL);
7804 }
7805
b8cecdf5
DV		 7806 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7807 if (!pipe_config)
7758a113
DV		 7808 return ERR_PTR(-ENOMEM);
7809
b8cecdf5
DV		 7810 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7811 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7812 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
c0d43d62 7813 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7814
050f7aeb
DV		 7815 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7816 * plane pixel format and any sink constraints into account. Returns the
7817 * source plane bpp so that dithering can be selected on mismatches
7818 * after encoders and crtc also have had their say. */
7819 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7820 fb, pipe_config);
4e53c2e0
DV		 7821 if (plane_bpp < 0)
7822 goto fail;
7823
e29c22c0 7824encoder_retry:
ef1b460d 7825 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7826 pipe_config->port_clock = 0;
ef1b460d 7827 pipe_config->pixel_multiplier = 1;
ff9a6750 7828
7758a113
DV		 7829 /* Pass our mode to the connectors and the CRTC to give them a chance to
7830 * adjust it according to limitations or connector properties, and also
7831 * a chance to reject the mode entirely.
47f1c6c9 7832 */
7758a113
DV		 7833 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7834 base.head) {
47f1c6c9 7835
7758a113
DV		 7836 if (&encoder->new_crtc->base != crtc)
7837 continue;
7ae89233
DV		 7838
7839 if (encoder->compute_config) {
7840 if (!(encoder->compute_config(encoder, pipe_config))) {
7841 DRM_DEBUG_KMS("Encoder config failure\n");
7842 goto fail;
7843 }
7844
7845 continue;
7846 }
7847
7758a113 7848 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7849 if (!(encoder_funcs->mode_fixup(&encoder->base,
7850 &pipe_config->requested_mode,
7851 &pipe_config->adjusted_mode))) {
7758a113
DV		 7852 DRM_DEBUG_KMS("Encoder fixup failed\n");
7853 goto fail;
7854 }
ee7b9f93 7855 }
47f1c6c9 7856
ff9a6750
DV		 7857 /* Set default port clock if not overwritten by the encoder. Needs to be
7858 * done afterwards in case the encoder adjusts the mode. */
7859 if (!pipe_config->port_clock)
7860 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7861
a43f6e0f 7862 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7863 if (ret < 0) {
7758a113
DV		 7864 DRM_DEBUG_KMS("CRTC fixup failed\n");
7865 goto fail;
ee7b9f93 7866 }
e29c22c0
DV		 7867
7868 if (ret == RETRY) {
7869 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7870 ret = -EINVAL;
7871 goto fail;
7872 }
7873
7874 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7875 retry = false;
7876 goto encoder_retry;
7877 }
7878
4e53c2e0
DV		 7879 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7880 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7881 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7882
b8cecdf5 7883 return pipe_config;
7758a113 7884fail:
b8cecdf5 7885 kfree(pipe_config);
e29c22c0 7886 return ERR_PTR(ret);
ee7b9f93 7887}
47f1c6c9 7888
e2e1ed41
DV		 7889/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7890 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7891static void
7892intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7893 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7894{
7895 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7896 struct drm_device *dev = crtc->dev;
7897 struct intel_encoder *encoder;
7898 struct intel_connector *connector;
7899 struct drm_crtc *tmp_crtc;
79e53945 7900
e2e1ed41 7901 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7902
e2e1ed41
DV		 7903 /* Check which crtcs have changed outputs connected to them, these need
7904 * to be part of the prepare_pipes mask. We don't (yet) support global
7905 * modeset across multiple crtcs, so modeset_pipes will only have one
7906 * bit set at most. */
7907 list_for_each_entry(connector, &dev->mode_config.connector_list,
7908 base.head) {
7909 if (connector->base.encoder == &connector->new_encoder->base)
7910 continue;
79e53945 7911
e2e1ed41
DV		 7912 if (connector->base.encoder) {
7913 tmp_crtc = connector->base.encoder->crtc;
7914
7915 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7916 }
7917
7918 if (connector->new_encoder)
7919 *prepare_pipes |=
7920 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7921 }
7922
e2e1ed41
DV		 7923 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7924 base.head) {
7925 if (encoder->base.crtc == &encoder->new_crtc->base)
7926 continue;
7927
7928 if (encoder->base.crtc) {
7929 tmp_crtc = encoder->base.crtc;
7930
7931 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7932 }
7933
7934 if (encoder->new_crtc)
7935 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7936 }
7937
e2e1ed41
DV		 7938 /* Check for any pipes that will be fully disabled ... */
7939 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7940 base.head) {
7941 bool used = false;
22fd0fab 7942
e2e1ed41
DV		 7943 /* Don't try to disable disabled crtcs. */
7944 if (!intel_crtc->base.enabled)
7945 continue;
7e7d76c3 7946
e2e1ed41
DV		 7947 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7948 base.head) {
7949 if (encoder->new_crtc == intel_crtc)
7950 used = true;
7951 }
7952
7953 if (!used)
7954 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7955 }
7956
e2e1ed41
DV		 7957
7958 /* set_mode is also used to update properties on life display pipes. */
7959 intel_crtc = to_intel_crtc(crtc);
7960 if (crtc->enabled)
7961 *prepare_pipes |= 1 << intel_crtc->pipe;
7962
b6c5164d
DV		 7963 /*
7964 * For simplicity do a full modeset on any pipe where the output routing
7965 * changed. We could be more clever, but that would require us to be
7966 * more careful with calling the relevant encoder->mode_set functions.
7967 */
e2e1ed41
DV		 7968 if (*prepare_pipes)
7969 *modeset_pipes = *prepare_pipes;
7970
7971 /* ... and mask these out. */
7972 *modeset_pipes &= ~(*disable_pipes);
7973 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7974
7975 /*
7976 * HACK: We don't (yet) fully support global modesets. intel_set_config
7977 * obies this rule, but the modeset restore mode of
7978 * intel_modeset_setup_hw_state does not.
7979 */
7980 *modeset_pipes &= 1 << intel_crtc->pipe;
7981 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7982
7983 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7984 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7985}
79e53945 7986
ea9d758d 7987static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7988{
ea9d758d 7989 struct drm_encoder *encoder;
f6e5b160 7990 struct drm_device *dev = crtc->dev;
f6e5b160 7991
ea9d758d
DV		 7992 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7993 if (encoder->crtc == crtc)
7994 return true;
7995
7996 return false;
7997}
7998
7999static void
8000intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8001{
8002 struct intel_encoder *intel_encoder;
8003 struct intel_crtc *intel_crtc;
8004 struct drm_connector *connector;
8005
8006 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8007 base.head) {
8008 if (!intel_encoder->base.crtc)
8009 continue;
8010
8011 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8012
8013 if (prepare_pipes & (1 << intel_crtc->pipe))
8014 intel_encoder->connectors_active = false;
8015 }
8016
8017 intel_modeset_commit_output_state(dev);
8018
8019 /* Update computed state. */
8020 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8021 base.head) {
8022 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8023 }
8024
8025 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8026 if (!connector->encoder || !connector->encoder->crtc)
8027 continue;
8028
8029 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8030
8031 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8032 struct drm_property *dpms_property =
8033 dev->mode_config.dpms_property;
8034
ea9d758d 8035 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8036 drm_object_property_set_value(&connector->base,
68d34720
DV		 8037 dpms_property,
8038 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8039
8040 intel_encoder = to_intel_encoder(connector->encoder);
8041 intel_encoder->connectors_active = true;
8042 }
8043 }
8044
8045}
8046
25c5b266
DV		 8047#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8048 list_for_each_entry((intel_crtc), \
8049 &(dev)->mode_config.crtc_list, \
8050 base.head) \
0973f18f 8051 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8052
0e8ffe1b 8053static bool
2fa2fe9a
DV		 8054intel_pipe_config_compare(struct drm_device *dev,
8055 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8056 struct intel_crtc_config *pipe_config)
8057{
66e985c0
DV		 8058#define PIPE_CONF_CHECK_X(name) \
8059 if (current_config->name != pipe_config->name) { \
8060 DRM_ERROR("mismatch in " #name " " \
8061 "(expected 0x%08x, found 0x%08x)\n", \
8062 current_config->name, \
8063 pipe_config->name); \
8064 return false; \
8065 }
8066
08a24034
DV		 8067#define PIPE_CONF_CHECK_I(name) \
8068 if (current_config->name != pipe_config->name) { \
8069 DRM_ERROR("mismatch in " #name " " \
8070 "(expected %i, found %i)\n", \
8071 current_config->name, \
8072 pipe_config->name); \
8073 return false; \
88adfff1
DV		 8074 }
8075
1bd1bd80
DV		 8076#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8077 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8078 DRM_ERROR("mismatch in " #name " " \
8079 "(expected %i, found %i)\n", \
8080 current_config->name & (mask), \
8081 pipe_config->name & (mask)); \
8082 return false; \
8083 }
8084
bb760063
DV		 8085#define PIPE_CONF_QUIRK(quirk) \
8086 ((current_config->quirks | pipe_config->quirks) & (quirk))
8087
eccb140b
DV		 8088 PIPE_CONF_CHECK_I(cpu_transcoder);
8089
08a24034
DV		 8090 PIPE_CONF_CHECK_I(has_pch_encoder);
8091 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8092 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8093 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8094 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8095 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8096 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8097
1bd1bd80
DV		 8098 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8099 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8100 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8101 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8102 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8103 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8104
8105 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8106 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8107 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8108 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8109 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8110 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8111
6c49f241
DV		 8112 if (!HAS_PCH_SPLIT(dev))
8113 PIPE_CONF_CHECK_I(pixel_multiplier);
8114
1bd1bd80
DV		 8115 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8116 DRM_MODE_FLAG_INTERLACE);
8117
bb760063
DV		 8118 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8119 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8120 DRM_MODE_FLAG_PHSYNC);
8121 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8122 DRM_MODE_FLAG_NHSYNC);
8123 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8124 DRM_MODE_FLAG_PVSYNC);
8125 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8126 DRM_MODE_FLAG_NVSYNC);
8127 }
045ac3b5 8128
1bd1bd80
DV		 8129 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8130 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8131
2fa2fe9a
DV		 8132 PIPE_CONF_CHECK_I(gmch_pfit.control);
8133 /* pfit ratios are autocomputed by the hw on gen4+ */
8134 if (INTEL_INFO(dev)->gen < 4)
8135 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8136 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8137 PIPE_CONF_CHECK_I(pch_pfit.pos);
8138 PIPE_CONF_CHECK_I(pch_pfit.size);
8139
42db64ef
PZ		 8140 PIPE_CONF_CHECK_I(ips_enabled);
8141
c0d43d62 8142 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0
DV		 8143 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8144 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8145 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8146
66e985c0 8147#undef PIPE_CONF_CHECK_X
08a24034 8148#undef PIPE_CONF_CHECK_I
1bd1bd80 8149#undef PIPE_CONF_CHECK_FLAGS
bb760063 8150#undef PIPE_CONF_QUIRK
88adfff1 8151
0e8ffe1b
DV		 8152 return true;
8153}
8154
91d1b4bd
DV		 8155static void
8156check_connector_state(struct drm_device *dev)
8af6cf88 8157{
8af6cf88
DV		 8158 struct intel_connector *connector;
8159
8160 list_for_each_entry(connector, &dev->mode_config.connector_list,
8161 base.head) {
8162 /* This also checks the encoder/connector hw state with the
8163 * ->get_hw_state callbacks. */
8164 intel_connector_check_state(connector);
8165
8166 WARN(&connector->new_encoder->base != connector->base.encoder,
8167 "connector's staged encoder doesn't match current encoder\n");
8168 }
91d1b4bd
DV		 8169}
8170
8171static void
8172check_encoder_state(struct drm_device *dev)
8173{
8174 struct intel_encoder *encoder;
8175 struct intel_connector *connector;
8af6cf88
DV		 8176
8177 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8178 base.head) {
8179 bool enabled = false;
8180 bool active = false;
8181 enum pipe pipe, tracked_pipe;
8182
8183 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8184 encoder->base.base.id,
8185 drm_get_encoder_name(&encoder->base));
8186
8187 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8188 "encoder's stage crtc doesn't match current crtc\n");
8189 WARN(encoder->connectors_active && !encoder->base.crtc,
8190 "encoder's active_connectors set, but no crtc\n");
8191
8192 list_for_each_entry(connector, &dev->mode_config.connector_list,
8193 base.head) {
8194 if (connector->base.encoder != &encoder->base)
8195 continue;
8196 enabled = true;
8197 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8198 active = true;
8199 }
8200 WARN(!!encoder->base.crtc != enabled,
8201 "encoder's enabled state mismatch "
8202 "(expected %i, found %i)\n",
8203 !!encoder->base.crtc, enabled);
8204 WARN(active && !encoder->base.crtc,
8205 "active encoder with no crtc\n");
8206
8207 WARN(encoder->connectors_active != active,
8208 "encoder's computed active state doesn't match tracked active state "
8209 "(expected %i, found %i)\n", active, encoder->connectors_active);
8210
8211 active = encoder->get_hw_state(encoder, &pipe);
8212 WARN(active != encoder->connectors_active,
8213 "encoder's hw state doesn't match sw tracking "
8214 "(expected %i, found %i)\n",
8215 encoder->connectors_active, active);
8216
8217 if (!encoder->base.crtc)
8218 continue;
8219
8220 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8221 WARN(active && pipe != tracked_pipe,
8222 "active encoder's pipe doesn't match"
8223 "(expected %i, found %i)\n",
8224 tracked_pipe, pipe);
8225
8226 }
91d1b4bd
DV		 8227}
8228
8229static void
8230check_crtc_state(struct drm_device *dev)
8231{
8232 drm_i915_private_t *dev_priv = dev->dev_private;
8233 struct intel_crtc *crtc;
8234 struct intel_encoder *encoder;
8235 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8236
8237 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8238 base.head) {
8239 bool enabled = false;
8240 bool active = false;
8241
045ac3b5
JB		 8242 memset(&pipe_config, 0, sizeof(pipe_config));
8243
8af6cf88
DV		 8244 DRM_DEBUG_KMS("[CRTC:%d]\n",
8245 crtc->base.base.id);
8246
8247 WARN(crtc->active && !crtc->base.enabled,
8248 "active crtc, but not enabled in sw tracking\n");
8249
8250 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8251 base.head) {
8252 if (encoder->base.crtc != &crtc->base)
8253 continue;
8254 enabled = true;
8255 if (encoder->connectors_active)
8256 active = true;
8257 }
6c49f241 8258
8af6cf88
DV		 8259 WARN(active != crtc->active,
8260 "crtc's computed active state doesn't match tracked active state "
8261 "(expected %i, found %i)\n", active, crtc->active);
8262 WARN(enabled != crtc->base.enabled,
8263 "crtc's computed enabled state doesn't match tracked enabled state "
8264 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8265
0e8ffe1b
DV		 8266 active = dev_priv->display.get_pipe_config(crtc,
8267 &pipe_config);
d62cf62a
DV		 8268
8269 /* hw state is inconsistent with the pipe A quirk */
8270 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8271 active = crtc->active;
8272
6c49f241
DV		 8273 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8274 base.head) {
8275 if (encoder->base.crtc != &crtc->base)
8276 continue;
8277 if (encoder->get_config)
8278 encoder->get_config(encoder, &pipe_config);
8279 }
8280
0e8ffe1b
DV		 8281 WARN(crtc->active != active,
8282 "crtc active state doesn't match with hw state "
8283 "(expected %i, found %i)\n", crtc->active, active);
8284
c0b03411
DV		 8285 if (active &&
8286 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8287 WARN(1, "pipe state doesn't match!\n");
8288 intel_dump_pipe_config(crtc, &pipe_config,
8289 "[hw state]");
8290 intel_dump_pipe_config(crtc, &crtc->config,
8291 "[sw state]");
8292 }
8af6cf88
DV		 8293 }
8294}
8295
91d1b4bd
DV		 8296static void
8297check_shared_dpll_state(struct drm_device *dev)
8298{
8299 drm_i915_private_t *dev_priv = dev->dev_private;
8300 struct intel_crtc *crtc;
8301 struct intel_dpll_hw_state dpll_hw_state;
8302 int i;
5358901f
DV		 8303
8304 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8305 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8306 int enabled_crtcs = 0, active_crtcs = 0;
8307 bool active;
8308
8309 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8310
8311 DRM_DEBUG_KMS("%s\n", pll->name);
8312
8313 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8314
8315 WARN(pll->active > pll->refcount,
8316 "more active pll users than references: %i vs %i\n",
8317 pll->active, pll->refcount);
8318 WARN(pll->active && !pll->on,
8319 "pll in active use but not on in sw tracking\n");
8320 WARN(pll->on != active,
8321 "pll on state mismatch (expected %i, found %i)\n",
8322 pll->on, active);
8323
8324 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8325 base.head) {
8326 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8327 enabled_crtcs++;
8328 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8329 active_crtcs++;
8330 }
8331 WARN(pll->active != active_crtcs,
8332 "pll active crtcs mismatch (expected %i, found %i)\n",
8333 pll->active, active_crtcs);
8334 WARN(pll->refcount != enabled_crtcs,
8335 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8336 pll->refcount, enabled_crtcs);
66e985c0
DV		 8337
8338 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8339 sizeof(dpll_hw_state)),
8340 "pll hw state mismatch\n");
5358901f 8341 }
8af6cf88
DV		 8342}
8343
91d1b4bd
DV		 8344void
8345intel_modeset_check_state(struct drm_device *dev)
8346{
8347 check_connector_state(dev);
8348 check_encoder_state(dev);
8349 check_crtc_state(dev);
8350 check_shared_dpll_state(dev);
8351}
8352
f30da187
DV		 8353static int __intel_set_mode(struct drm_crtc *crtc,
8354 struct drm_display_mode *mode,
8355 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8356{
8357 struct drm_device *dev = crtc->dev;
dbf2b54e 8358 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8359 struct drm_display_mode *saved_mode, *saved_hwmode;
8360 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8361 struct intel_crtc *intel_crtc;
8362 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8363 int ret = 0;
a6778b3c 8364
3ac18232 8365 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8366 if (!saved_mode)
8367 return -ENOMEM;
3ac18232 8368 saved_hwmode = saved_mode + 1;
a6778b3c 8369
e2e1ed41 8370 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8371 &prepare_pipes, &disable_pipes);
8372
3ac18232
TG		 8373 *saved_hwmode = crtc->hwmode;
8374 *saved_mode = crtc->mode;
a6778b3c 8375
25c5b266
DV		 8376 /* Hack: Because we don't (yet) support global modeset on multiple
8377 * crtcs, we don't keep track of the new mode for more than one crtc.
8378 * Hence simply check whether any bit is set in modeset_pipes in all the
8379 * pieces of code that are not yet converted to deal with mutliple crtcs
8380 * changing their mode at the same time. */
25c5b266 8381 if (modeset_pipes) {
4e53c2e0 8382 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8383 if (IS_ERR(pipe_config)) {
8384 ret = PTR_ERR(pipe_config);
8385 pipe_config = NULL;
8386
3ac18232 8387 goto out;
25c5b266 8388 }
c0b03411
DV		 8389 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8390 "[modeset]");
25c5b266 8391 }
a6778b3c 8392
460da916
DV		 8393 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8394 intel_crtc_disable(&intel_crtc->base);
8395
ea9d758d
DV		 8396 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8397 if (intel_crtc->base.enabled)
8398 dev_priv->display.crtc_disable(&intel_crtc->base);
8399 }
a6778b3c 8400
6c4c86f5
DV		 8401 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8402 * to set it here already despite that we pass it down the callchain.
f6e5b160 8403 */
b8cecdf5 8404 if (modeset_pipes) {
25c5b266 8405 crtc->mode = *mode;
b8cecdf5
DV		 8406 /* mode_set/enable/disable functions rely on a correct pipe
8407 * config. */
8408 to_intel_crtc(crtc)->config = *pipe_config;
8409 }
7758a113 8410
ea9d758d
DV		 8411 /* Only after disabling all output pipelines that will be changed can we
8412 * update the the output configuration. */
8413 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8414
47fab737
DV		 8415 if (dev_priv->display.modeset_global_resources)
8416 dev_priv->display.modeset_global_resources(dev);
8417
a6778b3c
DV		 8418 /* Set up the DPLL and any encoders state that needs to adjust or depend
8419 * on the DPLL.
f6e5b160 8420 */
25c5b266 8421 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8422 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8423 x, y, fb);
8424 if (ret)
8425 goto done;
a6778b3c
DV		 8426 }
8427
8428 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8429 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8430 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8431
25c5b266
DV		 8432 if (modeset_pipes) {
8433 /* Store real post-adjustment hardware mode. */
b8cecdf5 8434 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8435
25c5b266
DV		 8436 /* Calculate and store various constants which
8437 * are later needed by vblank and swap-completion
8438 * timestamping. They are derived from true hwmode.
8439 */
8440 drm_calc_timestamping_constants(crtc);
8441 }
a6778b3c
DV		 8442
8443 /* FIXME: add subpixel order */
8444done:
c0c36b94 8445 if (ret && crtc->enabled) {
3ac18232
TG		 8446 crtc->hwmode = *saved_hwmode;
8447 crtc->mode = *saved_mode;
a6778b3c
DV		 8448 }
8449
3ac18232 8450out:
b8cecdf5 8451 kfree(pipe_config);
3ac18232 8452 kfree(saved_mode);
a6778b3c 8453 return ret;
f6e5b160
CW		 8454}
8455
f30da187
DV		 8456int intel_set_mode(struct drm_crtc *crtc,
8457 struct drm_display_mode *mode,
8458 int x, int y, struct drm_framebuffer *fb)
8459{
8460 int ret;
8461
8462 ret = __intel_set_mode(crtc, mode, x, y, fb);
8463
8464 if (ret == 0)
8465 intel_modeset_check_state(crtc->dev);
8466
8467 return ret;
8468}
8469
c0c36b94
CW		 8470void intel_crtc_restore_mode(struct drm_crtc *crtc)
8471{
8472 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8473}
8474
25c5b266
DV		 8475#undef for_each_intel_crtc_masked
8476
d9e55608
DV		 8477static void intel_set_config_free(struct intel_set_config *config)
8478{
8479 if (!config)
8480 return;
8481
1aa4b628
DV		 8482 kfree(config->save_connector_encoders);
8483 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8484 kfree(config);
8485}
8486
85f9eb71
DV		 8487static int intel_set_config_save_state(struct drm_device *dev,
8488 struct intel_set_config *config)
8489{
85f9eb71
DV		 8490 struct drm_encoder *encoder;
8491 struct drm_connector *connector;
8492 int count;
8493
1aa4b628
DV		 8494 config->save_encoder_crtcs =
8495 kcalloc(dev->mode_config.num_encoder,
8496 sizeof(struct drm_crtc *), GFP_KERNEL);
8497 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8498 return -ENOMEM;
8499
1aa4b628
DV		 8500 config->save_connector_encoders =
8501 kcalloc(dev->mode_config.num_connector,
8502 sizeof(struct drm_encoder *), GFP_KERNEL);
8503 if (!config->save_connector_encoders)
85f9eb71
DV		 8504 return -ENOMEM;
8505
8506 /* Copy data. Note that driver private data is not affected.
8507 * Should anything bad happen only the expected state is
8508 * restored, not the drivers personal bookkeeping.
8509 */
85f9eb71
DV		 8510 count = 0;
8511 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8512 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8513 }
8514
8515 count = 0;
8516 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8517 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8518 }
8519
8520 return 0;
8521}
8522
8523static void intel_set_config_restore_state(struct drm_device *dev,
8524 struct intel_set_config *config)
8525{
9a935856
DV		 8526 struct intel_encoder *encoder;
8527 struct intel_connector *connector;
85f9eb71
DV		 8528 int count;
8529
85f9eb71 8530 count = 0;
9a935856
DV		 8531 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8532 encoder->new_crtc =
8533 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8534 }
8535
8536 count = 0;
9a935856
DV		 8537 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8538 connector->new_encoder =
8539 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8540 }
8541}
8542
e3de42b6
ID		 8543static bool
8544is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8545 int num_connectors)
8546{
8547 int i;
8548
8549 for (i = 0; i < num_connectors; i++)
8550 if (connectors[i].encoder &&
8551 connectors[i].encoder->crtc == crtc &&
8552 connectors[i].dpms != DRM_MODE_DPMS_ON)
8553 return true;
8554
8555 return false;
8556}
8557
5e2b584e
DV		 8558static void
8559intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8560 struct intel_set_config *config)
8561{
8562
8563 /* We should be able to check here if the fb has the same properties
8564 * and then just flip_or_move it */
e3de42b6
ID		 8565 if (set->connectors != NULL &&
8566 is_crtc_connector_off(set->crtc, *set->connectors,
8567 set->num_connectors)) {
8568 config->mode_changed = true;
8569 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8570 /* If we have no fb then treat it as a full mode set */
8571 if (set->crtc->fb == NULL) {
8572 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8573 config->mode_changed = true;
8574 } else if (set->fb == NULL) {
8575 config->mode_changed = true;
72f4901e
DV		 8576 } else if (set->fb->pixel_format !=
8577 set->crtc->fb->pixel_format) {
5e2b584e 8578 config->mode_changed = true;
e3de42b6 8579 } else {
5e2b584e 8580 config->fb_changed = true;
e3de42b6 8581 }
5e2b584e
DV		 8582 }
8583
835c5873 8584 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8585 config->fb_changed = true;
8586
8587 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8588 DRM_DEBUG_KMS("modes are different, full mode set\n");
8589 drm_mode_debug_printmodeline(&set->crtc->mode);
8590 drm_mode_debug_printmodeline(set->mode);
8591 config->mode_changed = true;
8592 }
8593}
8594
2e431051 8595static int
9a935856
DV		 8596intel_modeset_stage_output_state(struct drm_device *dev,
8597 struct drm_mode_set *set,
8598 struct intel_set_config *config)
50f56119 8599{
85f9eb71 8600 struct drm_crtc *new_crtc;
9a935856
DV		 8601 struct intel_connector *connector;
8602 struct intel_encoder *encoder;
2e431051 8603 int count, ro;
50f56119 8604
9abdda74 8605 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8606 * of connectors. For paranoia, double-check this. */
8607 WARN_ON(!set->fb && (set->num_connectors != 0));
8608 WARN_ON(set->fb && (set->num_connectors == 0));
8609
50f56119 8610 count = 0;
9a935856
DV		 8611 list_for_each_entry(connector, &dev->mode_config.connector_list,
8612 base.head) {
8613 /* Otherwise traverse passed in connector list and get encoders
8614 * for them. */
50f56119 8615 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8616 if (set->connectors[ro] == &connector->base) {
8617 connector->new_encoder = connector->encoder;
50f56119
DV		 8618 break;
8619 }
8620 }
8621
9a935856
DV		 8622 /* If we disable the crtc, disable all its connectors. Also, if
8623 * the connector is on the changing crtc but not on the new
8624 * connector list, disable it. */
8625 if ((!set->fb || ro == set->num_connectors) &&
8626 connector->base.encoder &&
8627 connector->base.encoder->crtc == set->crtc) {
8628 connector->new_encoder = NULL;
8629
8630 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8631 connector->base.base.id,
8632 drm_get_connector_name(&connector->base));
8633 }
8634
8635
8636 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8637 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8638 config->mode_changed = true;
50f56119
DV		 8639 }
8640 }
9a935856 8641 /* connector->new_encoder is now updated for all connectors. */
50f56119 8642
9a935856 8643 /* Update crtc of enabled connectors. */
50f56119 8644 count = 0;
9a935856
DV		 8645 list_for_each_entry(connector, &dev->mode_config.connector_list,
8646 base.head) {
8647 if (!connector->new_encoder)
50f56119
DV		 8648 continue;
8649
9a935856 8650 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8651
8652 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8653 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8654 new_crtc = set->crtc;
8655 }
8656
8657 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8658 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8659 new_crtc)) {
5e2b584e 8660 return -EINVAL;
50f56119 8661 }
9a935856
DV		 8662 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8663
8664 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8665 connector->base.base.id,
8666 drm_get_connector_name(&connector->base),
8667 new_crtc->base.id);
8668 }
8669
8670 /* Check for any encoders that needs to be disabled. */
8671 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8672 base.head) {
8673 list_for_each_entry(connector,
8674 &dev->mode_config.connector_list,
8675 base.head) {
8676 if (connector->new_encoder == encoder) {
8677 WARN_ON(!connector->new_encoder->new_crtc);
8678
8679 goto next_encoder;
8680 }
8681 }
8682 encoder->new_crtc = NULL;
8683next_encoder:
8684 /* Only now check for crtc changes so we don't miss encoders
8685 * that will be disabled. */
8686 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8687 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8688 config->mode_changed = true;
50f56119
DV		 8689 }
8690 }
9a935856 8691 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8692
2e431051
DV		 8693 return 0;
8694}
8695
8696static int intel_crtc_set_config(struct drm_mode_set *set)
8697{
8698 struct drm_device *dev;
2e431051
DV		 8699 struct drm_mode_set save_set;
8700 struct intel_set_config *config;
8701 int ret;
2e431051 8702
8d3e375e
DV		 8703 BUG_ON(!set);
8704 BUG_ON(!set->crtc);
8705 BUG_ON(!set->crtc->helper_private);
2e431051 8706
7e53f3a4
DV		 8707 /* Enforce sane interface api - has been abused by the fb helper. */
8708 BUG_ON(!set->mode && set->fb);
8709 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8710
2e431051
DV		 8711 if (set->fb) {
8712 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8713 set->crtc->base.id, set->fb->base.id,
8714 (int)set->num_connectors, set->x, set->y);
8715 } else {
8716 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8717 }
8718
8719 dev = set->crtc->dev;
8720
8721 ret = -ENOMEM;
8722 config = kzalloc(sizeof(*config), GFP_KERNEL);
8723 if (!config)
8724 goto out_config;
8725
8726 ret = intel_set_config_save_state(dev, config);
8727 if (ret)
8728 goto out_config;
8729
8730 save_set.crtc = set->crtc;
8731 save_set.mode = &set->crtc->mode;
8732 save_set.x = set->crtc->x;
8733 save_set.y = set->crtc->y;
8734 save_set.fb = set->crtc->fb;
8735
8736 /* Compute whether we need a full modeset, only an fb base update or no
8737 * change at all. In the future we might also check whether only the
8738 * mode changed, e.g. for LVDS where we only change the panel fitter in
8739 * such cases. */
8740 intel_set_config_compute_mode_changes(set, config);
8741
9a935856 8742 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8743 if (ret)
8744 goto fail;
8745
5e2b584e 8746 if (config->mode_changed) {
c0c36b94
CW		 8747 ret = intel_set_mode(set->crtc, set->mode,
8748 set->x, set->y, set->fb);
5e2b584e 8749 } else if (config->fb_changed) {
4878cae2
VS		 8750 intel_crtc_wait_for_pending_flips(set->crtc);
8751
4f660f49 8752 ret = intel_pipe_set_base(set->crtc,
94352cf9 8753 set->x, set->y, set->fb);
50f56119
DV		 8754 }
8755
2d05eae1 8756 if (ret) {
bf67dfeb
DV		 8757 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8758 set->crtc->base.id, ret);
50f56119 8759fail:
2d05eae1 8760 intel_set_config_restore_state(dev, config);
50f56119 8761
2d05eae1
CW		 8762 /* Try to restore the config */
8763 if (config->mode_changed &&
8764 intel_set_mode(save_set.crtc, save_set.mode,
8765 save_set.x, save_set.y, save_set.fb))
8766 DRM_ERROR("failed to restore config after modeset failure\n");
8767 }
50f56119 8768
d9e55608
DV		 8769out_config:
8770 intel_set_config_free(config);
50f56119
DV		 8771 return ret;
8772}
f6e5b160
CW		 8773
8774static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8775 .cursor_set = intel_crtc_cursor_set,
8776 .cursor_move = intel_crtc_cursor_move,
8777 .gamma_set = intel_crtc_gamma_set,
50f56119 8778 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8779 .destroy = intel_crtc_destroy,
8780 .page_flip = intel_crtc_page_flip,
8781};
8782
79f689aa
PZ		 8783static void intel_cpu_pll_init(struct drm_device *dev)
8784{
affa9354 8785 if (HAS_DDI(dev))
79f689aa
PZ		 8786 intel_ddi_pll_init(dev);
8787}
8788
5358901f
DV		 8789static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8790 struct intel_shared_dpll *pll,
8791 struct intel_dpll_hw_state *hw_state)
ee7b9f93 8792{
5358901f 8793 uint32_t val;
ee7b9f93 8794
5358901f 8795 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 8796 hw_state->dpll = val;
8797 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8798 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 8799
8800 return val & DPLL_VCO_ENABLE;
8801}
8802
e7b903d2
DV		 8803static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8804 struct intel_shared_dpll *pll)
8805{
8806 uint32_t reg, val;
8807
8808 /* PCH refclock must be enabled first */
8809 assert_pch_refclk_enabled(dev_priv);
8810
8811 reg = PCH_DPLL(pll->id);
8812 val = I915_READ(reg);
8813 val |= DPLL_VCO_ENABLE;
8814 I915_WRITE(reg, val);
8815 POSTING_READ(reg);
8816 udelay(200);
8817}
8818
8819static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8820 struct intel_shared_dpll *pll)
8821{
8822 struct drm_device *dev = dev_priv->dev;
8823 struct intel_crtc *crtc;
8824 uint32_t reg, val;
8825
8826 /* Make sure no transcoder isn't still depending on us. */
8827 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8828 if (intel_crtc_to_shared_dpll(crtc) == pll)
8829 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 8830 }
8831
e7b903d2
DV		 8832 reg = PCH_DPLL(pll->id);
8833 val = I915_READ(reg);
8834 val &= ~DPLL_VCO_ENABLE;
8835 I915_WRITE(reg, val);
8836 POSTING_READ(reg);
8837 udelay(200);
8838}
8839
46edb027
DV		 8840static char *ibx_pch_dpll_names[] = {
8841 "PCH DPLL A",
8842 "PCH DPLL B",
8843};
8844
7c74ade1 8845static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8846{
e7b903d2 8847 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8848 int i;
8849
7c74ade1 8850 dev_priv->num_shared_dpll = 2;
ee7b9f93 8851
e72f9fbf 8852 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8853 dev_priv->shared_dplls[i].id = i;
8854 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
e7b903d2
DV		 8855 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8856 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 8857 dev_priv->shared_dplls[i].get_hw_state =
8858 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 8859 }
8860}
8861
7c74ade1
DV		 8862static void intel_shared_dpll_init(struct drm_device *dev)
8863{
e7b903d2 8864 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 8865
8866 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8867 ibx_pch_dpll_init(dev);
8868 else
8869 dev_priv->num_shared_dpll = 0;
8870
8871 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8872 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8873 dev_priv->num_shared_dpll);
8874}
8875
b358d0a6 8876static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8877{
22fd0fab 8878 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8879 struct intel_crtc *intel_crtc;
8880 int i;
8881
8882 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8883 if (intel_crtc == NULL)
8884 return;
8885
8886 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8887
8888 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8889 for (i = 0; i < 256; i++) {
8890 intel_crtc->lut_r[i] = i;
8891 intel_crtc->lut_g[i] = i;
8892 intel_crtc->lut_b[i] = i;
8893 }
8894
80824003
JB		 8895 /* Swap pipes & planes for FBC on pre-965 */
8896 intel_crtc->pipe = pipe;
8897 intel_crtc->plane = pipe;
e2e767ab 8898 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8899 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8900 intel_crtc->plane = !pipe;
80824003
JB		 8901 }
8902
22fd0fab
JB		 8903 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8904 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8905 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8906 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8907
79e53945 8908 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8909}
8910
08d7b3d1 8911int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8912 struct drm_file *file)
08d7b3d1 8913{
08d7b3d1 8914 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8915 struct drm_mode_object *drmmode_obj;
8916 struct intel_crtc *crtc;
08d7b3d1 8917
1cff8f6b
DV		 8918 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8919 return -ENODEV;
08d7b3d1 8920
c05422d5
DV		 8921 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8922 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8923
c05422d5 8924 if (!drmmode_obj) {
08d7b3d1
CW		 8925 DRM_ERROR("no such CRTC id\n");
8926 return -EINVAL;
8927 }
8928
c05422d5
DV		 8929 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8930 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8931
c05422d5 8932 return 0;
08d7b3d1
CW		 8933}
8934
66a9278e 8935static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8936{
66a9278e
DV		 8937 struct drm_device *dev = encoder->base.dev;
8938 struct intel_encoder *source_encoder;
79e53945 8939 int index_mask = 0;
79e53945
JB		 8940 int entry = 0;
8941
66a9278e
DV		 8942 list_for_each_entry(source_encoder,
8943 &dev->mode_config.encoder_list, base.head) {
8944
8945 if (encoder == source_encoder)
79e53945 8946 index_mask |= (1 << entry);
66a9278e
DV		 8947
8948 /* Intel hw has only one MUX where enocoders could be cloned. */
8949 if (encoder->cloneable && source_encoder->cloneable)
8950 index_mask |= (1 << entry);
8951
79e53945
JB		 8952 entry++;
8953 }
4ef69c7a 8954
79e53945
JB		 8955 return index_mask;
8956}
8957
4d302442
CW		 8958static bool has_edp_a(struct drm_device *dev)
8959{
8960 struct drm_i915_private *dev_priv = dev->dev_private;
8961
8962 if (!IS_MOBILE(dev))
8963 return false;
8964
8965 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8966 return false;
8967
8968 if (IS_GEN5(dev) &&
8969 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8970 return false;
8971
8972 return true;
8973}
8974
79e53945
JB		 8975static void intel_setup_outputs(struct drm_device *dev)
8976{
725e30ad 8977 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8978 struct intel_encoder *encoder;
cb0953d7 8979 bool dpd_is_edp = false;
79e53945 8980
c9093354 8981 intel_lvds_init(dev);
79e53945 8982
c40c0f5b 8983 if (!IS_ULT(dev))
79935fca 8984 intel_crt_init(dev);
cb0953d7 8985
affa9354 8986 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8987 int found;
8988
8989 /* Haswell uses DDI functions to detect digital outputs */
8990 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8991 /* DDI A only supports eDP */
8992 if (found)
8993 intel_ddi_init(dev, PORT_A);
8994
8995 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8996 * register */
8997 found = I915_READ(SFUSE_STRAP);
8998
8999 if (found & SFUSE_STRAP_DDIB_DETECTED)
9000 intel_ddi_init(dev, PORT_B);
9001 if (found & SFUSE_STRAP_DDIC_DETECTED)
9002 intel_ddi_init(dev, PORT_C);
9003 if (found & SFUSE_STRAP_DDID_DETECTED)
9004 intel_ddi_init(dev, PORT_D);
9005 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9006 int found;
270b3042
DV		 9007 dpd_is_edp = intel_dpd_is_edp(dev);
9008
9009 if (has_edp_a(dev))
9010 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9011
dc0fa718 9012 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9013 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9014 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9015 if (!found)
e2debe91 9016 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9017 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9018 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9019 }
9020
dc0fa718 9021 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9022 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9023
dc0fa718 9024 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9025 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9026
5eb08b69 9027 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9028 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9029
270b3042 9030 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9031 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9032 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9033 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9034 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9035 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9036
dc0fa718 9037 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9038 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9039 PORT_B);
67cfc203
VS		 9040 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9041 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9042 }
103a196f 9043 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9044 bool found = false;
7d57382e 9045
e2debe91 9046 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9047 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9048 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9049 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9050 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9051 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9052 }
27185ae1 9053
e7281eab 9054 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9055 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9056 }
13520b05
KH		 9057
9058 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9059
e2debe91 9060 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9061 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9062 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9063 }
27185ae1 9064
e2debe91 9065 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9066
b01f2c3a
JB		 9067 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9068 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9069 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9070 }
e7281eab 9071 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9072 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9073 }
27185ae1 9074
b01f2c3a 9075 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9076 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9077 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9078 } else if (IS_GEN2(dev))
79e53945
JB		 9079 intel_dvo_init(dev);
9080
103a196f 9081 if (SUPPORTS_TV(dev))
79e53945
JB		 9082 intel_tv_init(dev);
9083
4ef69c7a
CW		 9084 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9085 encoder->base.possible_crtcs = encoder->crtc_mask;
9086 encoder->base.possible_clones =
66a9278e 9087 intel_encoder_clones(encoder);
79e53945 9088 }
47356eb6 9089
dde86e2d 9090 intel_init_pch_refclk(dev);
270b3042
DV		 9091
9092 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9093}
9094
9095static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9096{
9097 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9098
9099 drm_framebuffer_cleanup(fb);
05394f39 9100 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9101
9102 kfree(intel_fb);
9103}
9104
9105static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9106 struct drm_file *file,
79e53945
JB		 9107 unsigned int *handle)
9108{
9109 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9110 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9111
05394f39 9112 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9113}
9114
9115static const struct drm_framebuffer_funcs intel_fb_funcs = {
9116 .destroy = intel_user_framebuffer_destroy,
9117 .create_handle = intel_user_framebuffer_create_handle,
9118};
9119
38651674
DA		 9120int intel_framebuffer_init(struct drm_device *dev,
9121 struct intel_framebuffer *intel_fb,
308e5bcb 9122 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9123 struct drm_i915_gem_object *obj)
79e53945 9124{
a35cdaa0 9125 int pitch_limit;
79e53945
JB		 9126 int ret;
9127
c16ed4be
CW		 9128 if (obj->tiling_mode == I915_TILING_Y) {
9129 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9130 return -EINVAL;
c16ed4be 9131 }
57cd6508 9132
c16ed4be
CW		 9133 if (mode_cmd->pitches[0] & 63) {
9134 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9135 mode_cmd->pitches[0]);
57cd6508 9136 return -EINVAL;
c16ed4be 9137 }
57cd6508 9138
a35cdaa0
CW		 9139 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9140 pitch_limit = 32*1024;
9141 } else if (INTEL_INFO(dev)->gen >= 4) {
9142 if (obj->tiling_mode)
9143 pitch_limit = 16*1024;
9144 else
9145 pitch_limit = 32*1024;
9146 } else if (INTEL_INFO(dev)->gen >= 3) {
9147 if (obj->tiling_mode)
9148 pitch_limit = 8*1024;
9149 else
9150 pitch_limit = 16*1024;
9151 } else
9152 /* XXX DSPC is limited to 4k tiled */
9153 pitch_limit = 8*1024;
9154
9155 if (mode_cmd->pitches[0] > pitch_limit) {
9156 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9157 obj->tiling_mode ? "tiled" : "linear",
9158 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9159 return -EINVAL;
c16ed4be 9160 }
5d7bd705
VS		 9161
9162 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9163 mode_cmd->pitches[0] != obj->stride) {
9164 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9165 mode_cmd->pitches[0], obj->stride);
5d7bd705 9166 return -EINVAL;
c16ed4be 9167 }
5d7bd705 9168
57779d06 9169 /* Reject formats not supported by any plane early. */
308e5bcb 9170 switch (mode_cmd->pixel_format) {
57779d06 9171 case DRM_FORMAT_C8:
04b3924d
VS		 9172 case DRM_FORMAT_RGB565:
9173 case DRM_FORMAT_XRGB8888:
9174 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9175 break;
9176 case DRM_FORMAT_XRGB1555:
9177 case DRM_FORMAT_ARGB1555:
c16ed4be 9178 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9179 DRM_DEBUG("unsupported pixel format: %s\n",
9180 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9181 return -EINVAL;
c16ed4be 9182 }
57779d06
VS		 9183 break;
9184 case DRM_FORMAT_XBGR8888:
9185 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9186 case DRM_FORMAT_XRGB2101010:
9187 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9188 case DRM_FORMAT_XBGR2101010:
9189 case DRM_FORMAT_ABGR2101010:
c16ed4be 9190 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9191 DRM_DEBUG("unsupported pixel format: %s\n",
9192 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9193 return -EINVAL;
c16ed4be 9194 }
b5626747 9195 break;
04b3924d
VS		 9196 case DRM_FORMAT_YUYV:
9197 case DRM_FORMAT_UYVY:
9198 case DRM_FORMAT_YVYU:
9199 case DRM_FORMAT_VYUY:
c16ed4be 9200 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9201 DRM_DEBUG("unsupported pixel format: %s\n",
9202 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9203 return -EINVAL;
c16ed4be 9204 }
57cd6508
CW		 9205 break;
9206 default:
4ee62c76
VS		 9207 DRM_DEBUG("unsupported pixel format: %s\n",
9208 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9209 return -EINVAL;
9210 }
9211
90f9a336
VS		 9212 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9213 if (mode_cmd->offsets[0] != 0)
9214 return -EINVAL;
9215
c7d73f6a
DV		 9216 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9217 intel_fb->obj = obj;
9218
79e53945
JB		 9219 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9220 if (ret) {
9221 DRM_ERROR("framebuffer init failed %d\n", ret);
9222 return ret;
9223 }
9224
79e53945
JB		 9225 return 0;
9226}
9227
79e53945
JB		 9228static struct drm_framebuffer *
9229intel_user_framebuffer_create(struct drm_device *dev,
9230 struct drm_file *filp,
308e5bcb 9231 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9232{
05394f39 9233 struct drm_i915_gem_object *obj;
79e53945 9234
308e5bcb
JB		 9235 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9236 mode_cmd->handles[0]));
c8725226 9237 if (&obj->base == NULL)
cce13ff7 9238 return ERR_PTR(-ENOENT);
79e53945 9239
d2dff872 9240 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9241}
9242
79e53945 9243static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9244 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9245 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9246};
9247
e70236a8
JB		 9248/* Set up chip specific display functions */
9249static void intel_init_display(struct drm_device *dev)
9250{
9251 struct drm_i915_private *dev_priv = dev->dev_private;
9252
ee9300bb
DV		 9253 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9254 dev_priv->display.find_dpll = g4x_find_best_dpll;
9255 else if (IS_VALLEYVIEW(dev))
9256 dev_priv->display.find_dpll = vlv_find_best_dpll;
9257 else if (IS_PINEVIEW(dev))
9258 dev_priv->display.find_dpll = pnv_find_best_dpll;
9259 else
9260 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9261
affa9354 9262 if (HAS_DDI(dev)) {
0e8ffe1b 9263 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9264 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9265 dev_priv->display.crtc_enable = haswell_crtc_enable;
9266 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9267 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9268 dev_priv->display.update_plane = ironlake_update_plane;
9269 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9270 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9271 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9272 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9273 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9274 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9275 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9276 } else if (IS_VALLEYVIEW(dev)) {
9277 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9278 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9279 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9280 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9281 dev_priv->display.off = i9xx_crtc_off;
9282 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9283 } else {
0e8ffe1b 9284 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9285 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9286 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9287 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9288 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9289 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9290 }
e70236a8 9291
e70236a8 9292 /* Returns the core display clock speed */
25eb05fc
JB		 9293 if (IS_VALLEYVIEW(dev))
9294 dev_priv->display.get_display_clock_speed =
9295 valleyview_get_display_clock_speed;
9296 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9297 dev_priv->display.get_display_clock_speed =
9298 i945_get_display_clock_speed;
9299 else if (IS_I915G(dev))
9300 dev_priv->display.get_display_clock_speed =
9301 i915_get_display_clock_speed;
f2b115e6 9302 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9303 dev_priv->display.get_display_clock_speed =
9304 i9xx_misc_get_display_clock_speed;
9305 else if (IS_I915GM(dev))
9306 dev_priv->display.get_display_clock_speed =
9307 i915gm_get_display_clock_speed;
9308 else if (IS_I865G(dev))
9309 dev_priv->display.get_display_clock_speed =
9310 i865_get_display_clock_speed;
f0f8a9ce 9311 else if (IS_I85X(dev))
e70236a8
JB		 9312 dev_priv->display.get_display_clock_speed =
9313 i855_get_display_clock_speed;
9314 else /* 852, 830 */
9315 dev_priv->display.get_display_clock_speed =
9316 i830_get_display_clock_speed;
9317
7f8a8569 9318 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9319 if (IS_GEN5(dev)) {
674cf967 9320 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9321 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9322 } else if (IS_GEN6(dev)) {
674cf967 9323 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9324 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9325 } else if (IS_IVYBRIDGE(dev)) {
9326 /* FIXME: detect B0+ stepping and use auto training */
9327 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9328 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9329 dev_priv->display.modeset_global_resources =
9330 ivb_modeset_global_resources;
c82e4d26
ED		 9331 } else if (IS_HASWELL(dev)) {
9332 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9333 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9334 dev_priv->display.modeset_global_resources =
9335 haswell_modeset_global_resources;
a0e63c22 9336 }
6067aaea 9337 } else if (IS_G4X(dev)) {
e0dac65e 9338 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9339 }
8c9f3aaf
JB		 9340
9341 /* Default just returns -ENODEV to indicate unsupported */
9342 dev_priv->display.queue_flip = intel_default_queue_flip;
9343
9344 switch (INTEL_INFO(dev)->gen) {
9345 case 2:
9346 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9347 break;
9348
9349 case 3:
9350 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9351 break;
9352
9353 case 4:
9354 case 5:
9355 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9356 break;
9357
9358 case 6:
9359 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9360 break;
7c9017e5
JB		 9361 case 7:
9362 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9363 break;
8c9f3aaf 9364 }
e70236a8
JB		 9365}
9366
b690e96c
JB		 9367/*
9368 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9369 * resume, or other times. This quirk makes sure that's the case for
9370 * affected systems.
9371 */
0206e353 9372static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9373{
9374 struct drm_i915_private *dev_priv = dev->dev_private;
9375
9376 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9377 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9378}
9379
435793df
KP		 9380/*
9381 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9382 */
9383static void quirk_ssc_force_disable(struct drm_device *dev)
9384{
9385 struct drm_i915_private *dev_priv = dev->dev_private;
9386 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9387 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9388}
9389
4dca20ef 9390/*
5a15ab5b
CE		 9391 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9392 * brightness value
4dca20ef
CE		 9393 */
9394static void quirk_invert_brightness(struct drm_device *dev)
9395{
9396 struct drm_i915_private *dev_priv = dev->dev_private;
9397 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9398 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9399}
9400
b690e96c
JB		 9401struct intel_quirk {
9402 int device;
9403 int subsystem_vendor;
9404 int subsystem_device;
9405 void (*hook)(struct drm_device *dev);
9406};
9407
5f85f176
EE		 9408/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9409struct intel_dmi_quirk {
9410 void (*hook)(struct drm_device *dev);
9411 const struct dmi_system_id (*dmi_id_list)[];
9412};
9413
9414static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9415{
9416 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9417 return 1;
9418}
9419
9420static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9421 {
9422 .dmi_id_list = &(const struct dmi_system_id[]) {
9423 {
9424 .callback = intel_dmi_reverse_brightness,
9425 .ident = "NCR Corporation",
9426 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9427 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9428 },
9429 },
9430 { } /* terminating entry */
9431 },
9432 .hook = quirk_invert_brightness,
9433 },
9434};
9435
c43b5634 9436static struct intel_quirk intel_quirks[] = {
b690e96c 9437 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9438 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9439
b690e96c
JB		 9440 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9441 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9442
b690e96c
JB		 9443 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9444 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9445
ccd0d36e 9446 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9447 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9448 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9449
9450 /* Lenovo U160 cannot use SSC on LVDS */
9451 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9452
9453 /* Sony Vaio Y cannot use SSC on LVDS */
9454 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9455
9456 /* Acer Aspire 5734Z must invert backlight brightness */
9457 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9458
9459 /* Acer/eMachines G725 */
9460 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9461
9462 /* Acer/eMachines e725 */
9463 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9464
9465 /* Acer/Packard Bell NCL20 */
9466 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9467
9468 /* Acer Aspire 4736Z */
9469 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9470};
9471
9472static void intel_init_quirks(struct drm_device *dev)
9473{
9474 struct pci_dev *d = dev->pdev;
9475 int i;
9476
9477 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9478 struct intel_quirk *q = &intel_quirks[i];
9479
9480 if (d->device == q->device &&
9481 (d->subsystem_vendor == q->subsystem_vendor ||
9482 q->subsystem_vendor == PCI_ANY_ID) &&
9483 (d->subsystem_device == q->subsystem_device ||
9484 q->subsystem_device == PCI_ANY_ID))
9485 q->hook(dev);
9486 }
5f85f176
EE		 9487 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9488 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9489 intel_dmi_quirks[i].hook(dev);
9490 }
b690e96c
JB		 9491}
9492
9cce37f4
JB		 9493/* Disable the VGA plane that we never use */
9494static void i915_disable_vga(struct drm_device *dev)
9495{
9496 struct drm_i915_private *dev_priv = dev->dev_private;
9497 u8 sr1;
766aa1c4 9498 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9499
9500 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9501 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9502 sr1 = inb(VGA_SR_DATA);
9503 outb(sr1 | 1<<5, VGA_SR_DATA);
9504 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9505 udelay(300);
9506
9507 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9508 POSTING_READ(vga_reg);
9509}
9510
f817586c
DV		 9511void intel_modeset_init_hw(struct drm_device *dev)
9512{
fa42e23c 9513 intel_init_power_well(dev);
0232e927 9514
a8f78b58
ED		 9515 intel_prepare_ddi(dev);
9516
f817586c
DV		 9517 intel_init_clock_gating(dev);
9518
79f5b2c7 9519 mutex_lock(&dev->struct_mutex);
8090c6b9 9520 intel_enable_gt_powersave(dev);
79f5b2c7 9521 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9522}
9523
7d708ee4
ID		 9524void intel_modeset_suspend_hw(struct drm_device *dev)
9525{
9526 intel_suspend_hw(dev);
9527}
9528
79e53945
JB		 9529void intel_modeset_init(struct drm_device *dev)
9530{
652c393a 9531 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9532 int i, j, ret;
79e53945
JB		 9533
9534 drm_mode_config_init(dev);
9535
9536 dev->mode_config.min_width = 0;
9537 dev->mode_config.min_height = 0;
9538
019d96cb
DA		 9539 dev->mode_config.preferred_depth = 24;
9540 dev->mode_config.prefer_shadow = 1;
9541
e6ecefaa 9542 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9543
b690e96c
JB		 9544 intel_init_quirks(dev);
9545
1fa61106
ED		 9546 intel_init_pm(dev);
9547
e3c74757
BW		 9548 if (INTEL_INFO(dev)->num_pipes == 0)
9549 return;
9550
e70236a8
JB		 9551 intel_init_display(dev);
9552
a6c45cf0
CW		 9553 if (IS_GEN2(dev)) {
9554 dev->mode_config.max_width = 2048;
9555 dev->mode_config.max_height = 2048;
9556 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9557 dev->mode_config.max_width = 4096;
9558 dev->mode_config.max_height = 4096;
79e53945 9559 } else {
a6c45cf0
CW		 9560 dev->mode_config.max_width = 8192;
9561 dev->mode_config.max_height = 8192;
79e53945 9562 }
5d4545ae 9563 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9564
28c97730 9565 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9566 INTEL_INFO(dev)->num_pipes,
9567 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9568
7eb552ae 9569 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9570 intel_crtc_init(dev, i);
7f1f3851
JB		 9571 for (j = 0; j < dev_priv->num_plane; j++) {
9572 ret = intel_plane_init(dev, i, j);
9573 if (ret)
06da8da2
VS		 9574 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9575 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9576 }
79e53945
JB		 9577 }
9578
79f689aa 9579 intel_cpu_pll_init(dev);
e72f9fbf 9580 intel_shared_dpll_init(dev);
ee7b9f93 9581
9cce37f4
JB		 9582 /* Just disable it once at startup */
9583 i915_disable_vga(dev);
79e53945 9584 intel_setup_outputs(dev);
11be49eb
CW		 9585
9586 /* Just in case the BIOS is doing something questionable. */
9587 intel_disable_fbc(dev);
2c7111db
CW		 9588}
9589
24929352
DV		 9590static void
9591intel_connector_break_all_links(struct intel_connector *connector)
9592{
9593 connector->base.dpms = DRM_MODE_DPMS_OFF;
9594 connector->base.encoder = NULL;
9595 connector->encoder->connectors_active = false;
9596 connector->encoder->base.crtc = NULL;
9597}
9598
7fad798e
DV		 9599static void intel_enable_pipe_a(struct drm_device *dev)
9600{
9601 struct intel_connector *connector;
9602 struct drm_connector *crt = NULL;
9603 struct intel_load_detect_pipe load_detect_temp;
9604
9605 /* We can't just switch on the pipe A, we need to set things up with a
9606 * proper mode and output configuration. As a gross hack, enable pipe A
9607 * by enabling the load detect pipe once. */
9608 list_for_each_entry(connector,
9609 &dev->mode_config.connector_list,
9610 base.head) {
9611 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9612 crt = &connector->base;
9613 break;
9614 }
9615 }
9616
9617 if (!crt)
9618 return;
9619
9620 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9621 intel_release_load_detect_pipe(crt, &load_detect_temp);
9622
652c393a 9623
7fad798e
DV		 9624}
9625
fa555837
DV		 9626static bool
9627intel_check_plane_mapping(struct intel_crtc *crtc)
9628{
7eb552ae
BW		 9629 struct drm_device *dev = crtc->base.dev;
9630 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9631 u32 reg, val;
9632
7eb552ae 9633 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9634 return true;
9635
9636 reg = DSPCNTR(!crtc->plane);
9637 val = I915_READ(reg);
9638
9639 if ((val & DISPLAY_PLANE_ENABLE) &&
9640 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9641 return false;
9642
9643 return true;
9644}
9645
24929352
DV		 9646static void intel_sanitize_crtc(struct intel_crtc *crtc)
9647{
9648 struct drm_device *dev = crtc->base.dev;
9649 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9650 u32 reg;
24929352 9651
24929352 9652 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9653 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9654 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9655
9656 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9657 * disable the crtc (and hence change the state) if it is wrong. Note
9658 * that gen4+ has a fixed plane -> pipe mapping. */
9659 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9660 struct intel_connector *connector;
9661 bool plane;
9662
24929352
DV		 9663 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9664 crtc->base.base.id);
9665
9666 /* Pipe has the wrong plane attached and the plane is active.
9667 * Temporarily change the plane mapping and disable everything
9668 * ... */
9669 plane = crtc->plane;
9670 crtc->plane = !plane;
9671 dev_priv->display.crtc_disable(&crtc->base);
9672 crtc->plane = plane;
9673
9674 /* ... and break all links. */
9675 list_for_each_entry(connector, &dev->mode_config.connector_list,
9676 base.head) {
9677 if (connector->encoder->base.crtc != &crtc->base)
9678 continue;
9679
9680 intel_connector_break_all_links(connector);
9681 }
9682
9683 WARN_ON(crtc->active);
9684 crtc->base.enabled = false;
9685 }
24929352 9686
7fad798e
DV		 9687 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9688 crtc->pipe == PIPE_A && !crtc->active) {
9689 /* BIOS forgot to enable pipe A, this mostly happens after
9690 * resume. Force-enable the pipe to fix this, the update_dpms
9691 * call below we restore the pipe to the right state, but leave
9692 * the required bits on. */
9693 intel_enable_pipe_a(dev);
9694 }
9695
24929352
DV		 9696 /* Adjust the state of the output pipe according to whether we
9697 * have active connectors/encoders. */
9698 intel_crtc_update_dpms(&crtc->base);
9699
9700 if (crtc->active != crtc->base.enabled) {
9701 struct intel_encoder *encoder;
9702
9703 /* This can happen either due to bugs in the get_hw_state
9704 * functions or because the pipe is force-enabled due to the
9705 * pipe A quirk. */
9706 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9707 crtc->base.base.id,
9708 crtc->base.enabled ? "enabled" : "disabled",
9709 crtc->active ? "enabled" : "disabled");
9710
9711 crtc->base.enabled = crtc->active;
9712
9713 /* Because we only establish the connector -> encoder ->
9714 * crtc links if something is active, this means the
9715 * crtc is now deactivated. Break the links. connector
9716 * -> encoder links are only establish when things are
9717 * actually up, hence no need to break them. */
9718 WARN_ON(crtc->active);
9719
9720 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9721 WARN_ON(encoder->connectors_active);
9722 encoder->base.crtc = NULL;
9723 }
9724 }
9725}
9726
9727static void intel_sanitize_encoder(struct intel_encoder *encoder)
9728{
9729 struct intel_connector *connector;
9730 struct drm_device *dev = encoder->base.dev;
9731
9732 /* We need to check both for a crtc link (meaning that the
9733 * encoder is active and trying to read from a pipe) and the
9734 * pipe itself being active. */
9735 bool has_active_crtc = encoder->base.crtc &&
9736 to_intel_crtc(encoder->base.crtc)->active;
9737
9738 if (encoder->connectors_active && !has_active_crtc) {
9739 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9740 encoder->base.base.id,
9741 drm_get_encoder_name(&encoder->base));
9742
9743 /* Connector is active, but has no active pipe. This is
9744 * fallout from our resume register restoring. Disable
9745 * the encoder manually again. */
9746 if (encoder->base.crtc) {
9747 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9748 encoder->base.base.id,
9749 drm_get_encoder_name(&encoder->base));
9750 encoder->disable(encoder);
9751 }
9752
9753 /* Inconsistent output/port/pipe state happens presumably due to
9754 * a bug in one of the get_hw_state functions. Or someplace else
9755 * in our code, like the register restore mess on resume. Clamp
9756 * things to off as a safer default. */
9757 list_for_each_entry(connector,
9758 &dev->mode_config.connector_list,
9759 base.head) {
9760 if (connector->encoder != encoder)
9761 continue;
9762
9763 intel_connector_break_all_links(connector);
9764 }
9765 }
9766 /* Enabled encoders without active connectors will be fixed in
9767 * the crtc fixup. */
9768}
9769
44cec740 9770void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9771{
9772 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9773 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9774
9775 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9776 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9777 i915_disable_vga(dev);
0fde901f
KM		 9778 }
9779}
9780
30e984df 9781static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9782{
9783 struct drm_i915_private *dev_priv = dev->dev_private;
9784 enum pipe pipe;
24929352
DV		 9785 struct intel_crtc *crtc;
9786 struct intel_encoder *encoder;
9787 struct intel_connector *connector;
5358901f 9788 int i;
24929352 9789
0e8ffe1b
DV		 9790 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9791 base.head) {
88adfff1 9792 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9793
0e8ffe1b
DV		 9794 crtc->active = dev_priv->display.get_pipe_config(crtc,
9795 &crtc->config);
24929352
DV		 9796
9797 crtc->base.enabled = crtc->active;
9798
9799 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9800 crtc->base.base.id,
9801 crtc->active ? "enabled" : "disabled");
9802 }
9803
5358901f 9804 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9805 if (HAS_DDI(dev))
6441ab5f
PZ		 9806 intel_ddi_setup_hw_pll_state(dev);
9807
5358901f
DV		 9808 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9809 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9810
9811 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9812 pll->active = 0;
9813 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9814 base.head) {
9815 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9816 pll->active++;
9817 }
9818 pll->refcount = pll->active;
9819
9820 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9821 pll->name, pll->refcount);
9822 }
9823
24929352
DV		 9824 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9825 base.head) {
9826 pipe = 0;
9827
9828 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9829 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9830 encoder->base.crtc = &crtc->base;
9831 if (encoder->get_config)
9832 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9833 } else {
9834 encoder->base.crtc = NULL;
9835 }
9836
9837 encoder->connectors_active = false;
9838 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9839 encoder->base.base.id,
9840 drm_get_encoder_name(&encoder->base),
9841 encoder->base.crtc ? "enabled" : "disabled",
9842 pipe);
9843 }
9844
9845 list_for_each_entry(connector, &dev->mode_config.connector_list,
9846 base.head) {
9847 if (connector->get_hw_state(connector)) {
9848 connector->base.dpms = DRM_MODE_DPMS_ON;
9849 connector->encoder->connectors_active = true;
9850 connector->base.encoder = &connector->encoder->base;
9851 } else {
9852 connector->base.dpms = DRM_MODE_DPMS_OFF;
9853 connector->base.encoder = NULL;
9854 }
9855 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9856 connector->base.base.id,
9857 drm_get_connector_name(&connector->base),
9858 connector->base.encoder ? "enabled" : "disabled");
9859 }
30e984df
DV		 9860}
9861
9862/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9863 * and i915 state tracking structures. */
9864void intel_modeset_setup_hw_state(struct drm_device *dev,
9865 bool force_restore)
9866{
9867 struct drm_i915_private *dev_priv = dev->dev_private;
9868 enum pipe pipe;
9869 struct drm_plane *plane;
9870 struct intel_crtc *crtc;
9871 struct intel_encoder *encoder;
9872
9873 intel_modeset_readout_hw_state(dev);
24929352
DV		 9874
9875 /* HW state is read out, now we need to sanitize this mess. */
9876 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9877 base.head) {
9878 intel_sanitize_encoder(encoder);
9879 }
9880
9881 for_each_pipe(pipe) {
9882 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9883 intel_sanitize_crtc(crtc);
c0b03411 9884 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9885 }
9a935856 9886
45e2b5f6 9887 if (force_restore) {
f30da187
DV		 9888 /*
9889 * We need to use raw interfaces for restoring state to avoid
9890 * checking (bogus) intermediate states.
9891 */
45e2b5f6 9892 for_each_pipe(pipe) {
b5644d05
JB		 9893 struct drm_crtc *crtc =
9894 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9895
9896 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9897 crtc->fb);
45e2b5f6 9898 }
b5644d05
JB		 9899 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9900 intel_plane_restore(plane);
0fde901f
KM		 9901
9902 i915_redisable_vga(dev);
45e2b5f6
DV		 9903 } else {
9904 intel_modeset_update_staged_output_state(dev);
9905 }
8af6cf88
DV		 9906
9907 intel_modeset_check_state(dev);
2e938892
DV		 9908
9909 drm_mode_config_reset(dev);
2c7111db
CW		 9910}
9911
9912void intel_modeset_gem_init(struct drm_device *dev)
9913{
1833b134 9914 intel_modeset_init_hw(dev);
02e792fb
DV		 9915
9916 intel_setup_overlay(dev);
24929352 9917
45e2b5f6 9918 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9919}
9920
9921void intel_modeset_cleanup(struct drm_device *dev)
9922{
652c393a
JB		 9923 struct drm_i915_private *dev_priv = dev->dev_private;
9924 struct drm_crtc *crtc;
9925 struct intel_crtc *intel_crtc;
9926
fd0c0642
DV		 9927 /*
9928 * Interrupts and polling as the first thing to avoid creating havoc.
9929 * Too much stuff here (turning of rps, connectors, ...) would
9930 * experience fancy races otherwise.
9931 */
9932 drm_irq_uninstall(dev);
9933 cancel_work_sync(&dev_priv->hotplug_work);
9934 /*
9935 * Due to the hpd irq storm handling the hotplug work can re-arm the
9936 * poll handlers. Hence disable polling after hpd handling is shut down.
9937 */
f87ea761 9938 drm_kms_helper_poll_fini(dev);
fd0c0642 9939
652c393a
JB		 9940 mutex_lock(&dev->struct_mutex);
9941
723bfd70
JB		 9942 intel_unregister_dsm_handler();
9943
652c393a
JB		 9944 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9945 /* Skip inactive CRTCs */
9946 if (!crtc->fb)
9947 continue;
9948
9949 intel_crtc = to_intel_crtc(crtc);
3dec0095 9950 intel_increase_pllclock(crtc);
652c393a
JB		 9951 }
9952
973d04f9 9953 intel_disable_fbc(dev);
e70236a8 9954
8090c6b9 9955 intel_disable_gt_powersave(dev);
0cdab21f 9956
930ebb46
DV		 9957 ironlake_teardown_rc6(dev);
9958
69341a5e
KH		 9959 mutex_unlock(&dev->struct_mutex);
9960
1630fe75
CW		 9961 /* flush any delayed tasks or pending work */
9962 flush_scheduled_work();
9963
dc652f90
JN		 9964 /* destroy backlight, if any, before the connectors */
9965 intel_panel_destroy_backlight(dev);
9966
79e53945 9967 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9968
9969 intel_cleanup_overlay(dev);
79e53945
JB		 9970}
9971
f1c79df3
ZW		 9972/*
9973 * Return which encoder is currently attached for connector.
9974 */
df0e9248 9975struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9976{
df0e9248
CW		 9977 return &intel_attached_encoder(connector)->base;
9978}
f1c79df3 9979
df0e9248
CW		 9980void intel_connector_attach_encoder(struct intel_connector *connector,
9981 struct intel_encoder *encoder)
9982{
9983 connector->encoder = encoder;
9984 drm_mode_connector_attach_encoder(&connector->base,
9985 &encoder->base);
79e53945 9986}
28d52043
DA		 9987
9988/*
9989 * set vga decode state - true == enable VGA decode
9990 */
9991int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9992{
9993 struct drm_i915_private *dev_priv = dev->dev_private;
9994 u16 gmch_ctrl;
9995
9996 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9997 if (state)
9998 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9999 else
10000 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10001 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10002 return 0;
10003}
c4a1d9e4
CW		 10004
10005#ifdef CONFIG_DEBUG_FS
10006#include <linux/seq_file.h>
10007
10008struct intel_display_error_state {
ff57f1b0
PZ		 10009
10010 u32 power_well_driver;
10011
c4a1d9e4
CW		 10012 struct intel_cursor_error_state {
10013 u32 control;
10014 u32 position;
10015 u32 base;
10016 u32 size;
52331309 10017 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10018
10019 struct intel_pipe_error_state {
ff57f1b0 10020 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10021 u32 conf;
10022 u32 source;
10023
10024 u32 htotal;
10025 u32 hblank;
10026 u32 hsync;
10027 u32 vtotal;
10028 u32 vblank;
10029 u32 vsync;
52331309 10030 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10031
10032 struct intel_plane_error_state {
10033 u32 control;
10034 u32 stride;
10035 u32 size;
10036 u32 pos;
10037 u32 addr;
10038 u32 surface;
10039 u32 tile_offset;
52331309 10040 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10041};
10042
10043struct intel_display_error_state *
10044intel_display_capture_error_state(struct drm_device *dev)
10045{
0206e353 10046 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10047 struct intel_display_error_state *error;
702e7a56 10048 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10049 int i;
10050
10051 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10052 if (error == NULL)
10053 return NULL;
10054
ff57f1b0
PZ		 10055 if (HAS_POWER_WELL(dev))
10056 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10057
52331309 10058 for_each_pipe(i) {
702e7a56 10059 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10060 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10061
a18c4c3d
PZ		 10062 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10063 error->cursor[i].control = I915_READ(CURCNTR(i));
10064 error->cursor[i].position = I915_READ(CURPOS(i));
10065 error->cursor[i].base = I915_READ(CURBASE(i));
10066 } else {
10067 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10068 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10069 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10070 }
c4a1d9e4
CW		 10071
10072 error->plane[i].control = I915_READ(DSPCNTR(i));
10073 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10074 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10075 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10076 error->plane[i].pos = I915_READ(DSPPOS(i));
10077 }
ca291363
PZ		 10078 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10079 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10080 if (INTEL_INFO(dev)->gen >= 4) {
10081 error->plane[i].surface = I915_READ(DSPSURF(i));
10082 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10083 }
10084
702e7a56 10085 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10086 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10087 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10088 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10089 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10090 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10091 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10092 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10093 }
10094
12d217c7
PZ		 10095 /* In the code above we read the registers without checking if the power
10096 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10097 * prevent the next I915_WRITE from detecting it and printing an error
10098 * message. */
10099 if (HAS_POWER_WELL(dev))
10100 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10101
c4a1d9e4
CW		 10102 return error;
10103}
10104
edc3d884
MK		 10105#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10106
c4a1d9e4 10107void
edc3d884 10108intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10109 struct drm_device *dev,
10110 struct intel_display_error_state *error)
10111{
10112 int i;
10113
edc3d884 10114 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10115 if (HAS_POWER_WELL(dev))
edc3d884 10116 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10117 error->power_well_driver);
52331309 10118 for_each_pipe(i) {
edc3d884
MK		 10119 err_printf(m, "Pipe [%d]:\n", i);
10120 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10121 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10122 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10123 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10124 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10125 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10126 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10127 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10128 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10129 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10130
10131 err_printf(m, "Plane [%d]:\n", i);
10132 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10133 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10134 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10135 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10136 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10137 }
4b71a570 10138 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10139 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10140 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10141 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10142 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10143 }
10144
edc3d884
MK		 10145 err_printf(m, "Cursor [%d]:\n", i);
10146 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10147 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10148 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10149 }
10150}
10151#endif
Linux kernel - Deliverables
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