projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: disable CLKOUT_DP when it's not needed
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
79e53945 53typedef struct {
0206e353 54 int min, max;
79e53945
JB		 55} intel_range_t;
56
57typedef struct {
0206e353
AJ		 58 int dot_limit;
59 int p2_slow, p2_fast;
79e53945
JB		 60} intel_p2_t;
61
62#define INTEL_P2_NUM 2
d4906093
ML		 63typedef struct intel_limit intel_limit_t;
64struct intel_limit {
0206e353
AJ		 65 intel_range_t dot, vco, n, m, m1, m2, p, p1;
66 intel_p2_t p2;
d4906093 67};
79e53945 68
2377b741
JB		 69/* FDI */
70#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
339static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 340 .dot = { .min = 25000, .max = 270000 },
341 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 342 .n = { .min = 1, .max = 7 },
74a4dd2e 343 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 344 .m1 = { .min = 2, .max = 3 },
345 .m2 = { .min = 11, .max = 156 },
346 .p = { .min = 10, .max = 30 },
75e53986 347 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 348 .p2 = { .dot_limit = 270000,
349 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 350};
351
1b894b59
CW		 352static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
353 int refclk)
2c07245f 354{
b91ad0ec 355 struct drm_device *dev = crtc->dev;
2c07245f 356 const intel_limit_t *limit;
b91ad0ec
ZW		 357
358 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 359 if (intel_is_dual_link_lvds(dev)) {
1b894b59 360 if (refclk == 100000)
b91ad0ec
ZW		 361 limit = &intel_limits_ironlake_dual_lvds_100m;
362 else
363 limit = &intel_limits_ironlake_dual_lvds;
364 } else {
1b894b59 365 if (refclk == 100000)
b91ad0ec
ZW		 366 limit = &intel_limits_ironlake_single_lvds_100m;
367 else
368 limit = &intel_limits_ironlake_single_lvds;
369 }
c6bb3538 370 } else
b91ad0ec 371 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 372
373 return limit;
374}
375
044c7c41
ML		 376static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
377{
378 struct drm_device *dev = crtc->dev;
044c7c41
ML		 379 const intel_limit_t *limit;
380
381 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 382 if (intel_is_dual_link_lvds(dev))
e4b36699 383 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 384 else
e4b36699 385 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 386 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
387 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 388 limit = &intel_limits_g4x_hdmi;
044c7c41 389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 390 limit = &intel_limits_g4x_sdvo;
044c7c41 391 } else /* The option is for other outputs */
e4b36699 392 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 393
394 return limit;
395}
396
1b894b59 397static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 398{
399 struct drm_device *dev = crtc->dev;
400 const intel_limit_t *limit;
401
bad720ff 402 if (HAS_PCH_SPLIT(dev))
1b894b59 403 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 404 else if (IS_G4X(dev)) {
044c7c41 405 limit = intel_g4x_limit(crtc);
f2b115e6 406 } else if (IS_PINEVIEW(dev)) {
2177832f 407 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 408 limit = &intel_limits_pineview_lvds;
2177832f 409 else
f2b115e6 410 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 411 } else if (IS_VALLEYVIEW(dev)) {
412 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
413 limit = &intel_limits_vlv_dac;
414 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
415 limit = &intel_limits_vlv_hdmi;
416 else
417 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 418 } else if (!IS_GEN2(dev)) {
419 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
420 limit = &intel_limits_i9xx_lvds;
421 else
422 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 423 } else {
424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 425 limit = &intel_limits_i8xx_lvds;
5d536e28 426 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 427 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 428 else
429 limit = &intel_limits_i8xx_dac;
79e53945
JB		 430 }
431 return limit;
432}
433
f2b115e6
AJ		 434/* m1 is reserved as 0 in Pineview, n is a ring counter */
435static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 436{
2177832f
SL		 437 clock->m = clock->m2 + 2;
438 clock->p = clock->p1 * clock->p2;
439 clock->vco = refclk * clock->m / clock->n;
440 clock->dot = clock->vco / clock->p;
441}
442
7429e9d4
DV		 443static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
444{
445 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
446}
447
ac58c3f0 448static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 449{
7429e9d4 450 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 451 clock->p = clock->p1 * clock->p2;
452 clock->vco = refclk * clock->m / (clock->n + 2);
453 clock->dot = clock->vco / clock->p;
454}
455
79e53945
JB		 456/**
457 * Returns whether any output on the specified pipe is of the specified type
458 */
4ef69c7a 459bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 460{
4ef69c7a 461 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 462 struct intel_encoder *encoder;
463
6c2b7c12
DV		 464 for_each_encoder_on_crtc(dev, crtc, encoder)
465 if (encoder->type == type)
4ef69c7a
CW		 466 return true;
467
468 return false;
79e53945
JB		 469}
470
7c04d1d9 471#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 472/**
473 * Returns whether the given set of divisors are valid for a given refclk with
474 * the given connectors.
475 */
476
1b894b59
CW		 477static bool intel_PLL_is_valid(struct drm_device *dev,
478 const intel_limit_t *limit,
479 const intel_clock_t *clock)
79e53945 480{
79e53945 481 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 482 INTELPllInvalid("p1 out of range\n");
79e53945 483 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 484 INTELPllInvalid("p out of range\n");
79e53945 485 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 486 INTELPllInvalid("m2 out of range\n");
79e53945 487 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 488 INTELPllInvalid("m1 out of range\n");
f2b115e6 489 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 490 INTELPllInvalid("m1 <= m2\n");
79e53945 491 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 492 INTELPllInvalid("m out of range\n");
79e53945 493 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 494 INTELPllInvalid("n out of range\n");
79e53945 495 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 496 INTELPllInvalid("vco out of range\n");
79e53945
JB		 497 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
498 * connector, etc., rather than just a single range.
499 */
500 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 501 INTELPllInvalid("dot out of range\n");
79e53945
JB		 502
503 return true;
504}
505
d4906093 506static bool
ee9300bb 507i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 508 int target, int refclk, intel_clock_t *match_clock,
509 intel_clock_t *best_clock)
79e53945
JB		 510{
511 struct drm_device *dev = crtc->dev;
79e53945 512 intel_clock_t clock;
79e53945
JB		 513 int err = target;
514
a210b028 515 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 516 /*
a210b028
DV		 517 * For LVDS just rely on its current settings for dual-channel.
518 * We haven't figured out how to reliably set up different
519 * single/dual channel state, if we even can.
79e53945 520 */
1974cad0 521 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 522 clock.p2 = limit->p2.p2_fast;
523 else
524 clock.p2 = limit->p2.p2_slow;
525 } else {
526 if (target < limit->p2.dot_limit)
527 clock.p2 = limit->p2.p2_slow;
528 else
529 clock.p2 = limit->p2.p2_fast;
530 }
531
0206e353 532 memset(best_clock, 0, sizeof(*best_clock));
79e53945 533
42158660
ZY		 534 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
535 clock.m1++) {
536 for (clock.m2 = limit->m2.min;
537 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 538 if (clock.m2 >= clock.m1)
42158660
ZY		 539 break;
540 for (clock.n = limit->n.min;
541 clock.n <= limit->n.max; clock.n++) {
542 for (clock.p1 = limit->p1.min;
543 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 544 int this_err;
545
ac58c3f0
DV		 546 i9xx_clock(refclk, &clock);
547 if (!intel_PLL_is_valid(dev, limit,
548 &clock))
549 continue;
550 if (match_clock &&
551 clock.p != match_clock->p)
552 continue;
553
554 this_err = abs(clock.dot - target);
555 if (this_err < err) {
556 *best_clock = clock;
557 err = this_err;
558 }
559 }
560 }
561 }
562 }
563
564 return (err != target);
565}
566
567static bool
ee9300bb
DV		 568pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
569 int target, int refclk, intel_clock_t *match_clock,
570 intel_clock_t *best_clock)
79e53945
JB		 571{
572 struct drm_device *dev = crtc->dev;
79e53945 573 intel_clock_t clock;
79e53945
JB		 574 int err = target;
575
a210b028 576 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 577 /*
a210b028
DV		 578 * For LVDS just rely on its current settings for dual-channel.
579 * We haven't figured out how to reliably set up different
580 * single/dual channel state, if we even can.
79e53945 581 */
1974cad0 582 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 583 clock.p2 = limit->p2.p2_fast;
584 else
585 clock.p2 = limit->p2.p2_slow;
586 } else {
587 if (target < limit->p2.dot_limit)
588 clock.p2 = limit->p2.p2_slow;
589 else
590 clock.p2 = limit->p2.p2_fast;
591 }
592
0206e353 593 memset(best_clock, 0, sizeof(*best_clock));
79e53945 594
42158660
ZY		 595 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
596 clock.m1++) {
597 for (clock.m2 = limit->m2.min;
598 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 599 for (clock.n = limit->n.min;
600 clock.n <= limit->n.max; clock.n++) {
601 for (clock.p1 = limit->p1.min;
602 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 603 int this_err;
604
ac58c3f0 605 pineview_clock(refclk, &clock);
1b894b59
CW		 606 if (!intel_PLL_is_valid(dev, limit,
607 &clock))
79e53945 608 continue;
cec2f356
SP		 609 if (match_clock &&
610 clock.p != match_clock->p)
611 continue;
79e53945
JB		 612
613 this_err = abs(clock.dot - target);
614 if (this_err < err) {
615 *best_clock = clock;
616 err = this_err;
617 }
618 }
619 }
620 }
621 }
622
623 return (err != target);
624}
625
d4906093 626static bool
ee9300bb
DV		 627g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
628 int target, int refclk, intel_clock_t *match_clock,
629 intel_clock_t *best_clock)
d4906093
ML		 630{
631 struct drm_device *dev = crtc->dev;
d4906093
ML		 632 intel_clock_t clock;
633 int max_n;
634 bool found;
6ba770dc
AJ		 635 /* approximately equals target * 0.00585 */
636 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 637 found = false;
638
639 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 640 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 641 clock.p2 = limit->p2.p2_fast;
642 else
643 clock.p2 = limit->p2.p2_slow;
644 } else {
645 if (target < limit->p2.dot_limit)
646 clock.p2 = limit->p2.p2_slow;
647 else
648 clock.p2 = limit->p2.p2_fast;
649 }
650
651 memset(best_clock, 0, sizeof(*best_clock));
652 max_n = limit->n.max;
f77f13e2 653 /* based on hardware requirement, prefer smaller n to precision */
d4906093 654 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 655 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 656 for (clock.m1 = limit->m1.max;
657 clock.m1 >= limit->m1.min; clock.m1--) {
658 for (clock.m2 = limit->m2.max;
659 clock.m2 >= limit->m2.min; clock.m2--) {
660 for (clock.p1 = limit->p1.max;
661 clock.p1 >= limit->p1.min; clock.p1--) {
662 int this_err;
663
ac58c3f0 664 i9xx_clock(refclk, &clock);
1b894b59
CW		 665 if (!intel_PLL_is_valid(dev, limit,
666 &clock))
d4906093 667 continue;
1b894b59
CW		 668
669 this_err = abs(clock.dot - target);
d4906093
ML		 670 if (this_err < err_most) {
671 *best_clock = clock;
672 err_most = this_err;
673 max_n = clock.n;
674 found = true;
675 }
676 }
677 }
678 }
679 }
2c07245f
ZW		 680 return found;
681}
682
a0c4da24 683static bool
ee9300bb
DV		 684vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
685 int target, int refclk, intel_clock_t *match_clock,
686 intel_clock_t *best_clock)
a0c4da24
JB		 687{
688 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
689 u32 m, n, fastclk;
690 u32 updrate, minupdate, fracbits, p;
691 unsigned long bestppm, ppm, absppm;
692 int dotclk, flag;
693
af447bd3 694 flag = 0;
a0c4da24
JB		 695 dotclk = target * 1000;
696 bestppm = 1000000;
697 ppm = absppm = 0;
698 fastclk = dotclk / (2*100);
699 updrate = 0;
700 minupdate = 19200;
701 fracbits = 1;
702 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
703 bestm1 = bestm2 = bestp1 = bestp2 = 0;
704
705 /* based on hardware requirement, prefer smaller n to precision */
706 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
707 updrate = refclk / n;
708 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
709 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
710 if (p2 > 10)
711 p2 = p2 - 1;
712 p = p1 * p2;
713 /* based on hardware requirement, prefer bigger m1,m2 values */
714 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
715 m2 = (((2*(fastclk * p * n / m1 )) +
716 refclk) / (2*refclk));
717 m = m1 * m2;
718 vco = updrate * m;
719 if (vco >= limit->vco.min && vco < limit->vco.max) {
720 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
721 absppm = (ppm > 0) ? ppm : (-ppm);
722 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
723 bestppm = 0;
724 flag = 1;
725 }
726 if (absppm < bestppm - 10) {
727 bestppm = absppm;
728 flag = 1;
729 }
730 if (flag) {
731 bestn = n;
732 bestm1 = m1;
733 bestm2 = m2;
734 bestp1 = p1;
735 bestp2 = p2;
736 flag = 0;
737 }
738 }
739 }
740 }
741 }
742 }
743 best_clock->n = bestn;
744 best_clock->m1 = bestm1;
745 best_clock->m2 = bestm2;
746 best_clock->p1 = bestp1;
747 best_clock->p2 = bestp2;
748
749 return true;
750}
a4fc5ed6 751
a5c961d1
PZ		 752enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
753 enum pipe pipe)
754{
755 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
757
3b117c8f 758 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 759}
760
a928d536
PZ		 761static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
762{
763 struct drm_i915_private *dev_priv = dev->dev_private;
764 u32 frame, frame_reg = PIPEFRAME(pipe);
765
766 frame = I915_READ(frame_reg);
767
768 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
769 DRM_DEBUG_KMS("vblank wait timed out\n");
770}
771
9d0498a2
JB		 772/**
773 * intel_wait_for_vblank - wait for vblank on a given pipe
774 * @dev: drm device
775 * @pipe: pipe to wait for
776 *
777 * Wait for vblank to occur on a given pipe. Needed for various bits of
778 * mode setting code.
779 */
780void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 781{
9d0498a2 782 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 783 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 784
a928d536
PZ		 785 if (INTEL_INFO(dev)->gen >= 5) {
786 ironlake_wait_for_vblank(dev, pipe);
787 return;
788 }
789
300387c0
CW		 790 /* Clear existing vblank status. Note this will clear any other
791 * sticky status fields as well.
792 *
793 * This races with i915_driver_irq_handler() with the result
794 * that either function could miss a vblank event. Here it is not
795 * fatal, as we will either wait upon the next vblank interrupt or
796 * timeout. Generally speaking intel_wait_for_vblank() is only
797 * called during modeset at which time the GPU should be idle and
798 * should *not* be performing page flips and thus not waiting on
799 * vblanks...
800 * Currently, the result of us stealing a vblank from the irq
801 * handler is that a single frame will be skipped during swapbuffers.
802 */
803 I915_WRITE(pipestat_reg,
804 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
805
9d0498a2 806 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 807 if (wait_for(I915_READ(pipestat_reg) &
808 PIPE_VBLANK_INTERRUPT_STATUS,
809 50))
9d0498a2
JB		 810 DRM_DEBUG_KMS("vblank wait timed out\n");
811}
812
ab7ad7f6
KP		 813/*
814 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 815 * @dev: drm device
816 * @pipe: pipe to wait for
817 *
818 * After disabling a pipe, we can't wait for vblank in the usual way,
819 * spinning on the vblank interrupt status bit, since we won't actually
820 * see an interrupt when the pipe is disabled.
821 *
ab7ad7f6
KP		 822 * On Gen4 and above:
823 * wait for the pipe register state bit to turn off
824 *
825 * Otherwise:
826 * wait for the display line value to settle (it usually
827 * ends up stopping at the start of the next frame).
58e10eb9 828 *
9d0498a2 829 */
58e10eb9 830void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 831{
832 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 833 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
834 pipe);
ab7ad7f6
KP		 835
836 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 837 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 838
839 /* Wait for the Pipe State to go off */
58e10eb9
CW		 840 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
841 100))
284637d9 842 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 843 } else {
837ba00f 844 u32 last_line, line_mask;
58e10eb9 845 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 846 unsigned long timeout = jiffies + msecs_to_jiffies(100);
847
837ba00f
PZ		 848 if (IS_GEN2(dev))
849 line_mask = DSL_LINEMASK_GEN2;
850 else
851 line_mask = DSL_LINEMASK_GEN3;
852
ab7ad7f6
KP		 853 /* Wait for the display line to settle */
854 do {
837ba00f 855 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 856 mdelay(5);
837ba00f 857 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 858 time_after(timeout, jiffies));
859 if (time_after(jiffies, timeout))
284637d9 860 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 861 }
79e53945
JB		 862}
863
b0ea7d37
DL		 864/*
865 * ibx_digital_port_connected - is the specified port connected?
866 * @dev_priv: i915 private structure
867 * @port: the port to test
868 *
869 * Returns true if @port is connected, false otherwise.
870 */
871bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
872 struct intel_digital_port *port)
873{
874 u32 bit;
875
c36346e3
DL		 876 if (HAS_PCH_IBX(dev_priv->dev)) {
877 switch(port->port) {
878 case PORT_B:
879 bit = SDE_PORTB_HOTPLUG;
880 break;
881 case PORT_C:
882 bit = SDE_PORTC_HOTPLUG;
883 break;
884 case PORT_D:
885 bit = SDE_PORTD_HOTPLUG;
886 break;
887 default:
888 return true;
889 }
890 } else {
891 switch(port->port) {
892 case PORT_B:
893 bit = SDE_PORTB_HOTPLUG_CPT;
894 break;
895 case PORT_C:
896 bit = SDE_PORTC_HOTPLUG_CPT;
897 break;
898 case PORT_D:
899 bit = SDE_PORTD_HOTPLUG_CPT;
900 break;
901 default:
902 return true;
903 }
b0ea7d37
DL		 904 }
905
906 return I915_READ(SDEISR) & bit;
907}
908
b24e7179
JB		 909static const char *state_string(bool enabled)
910{
911 return enabled ? "on" : "off";
912}
913
914/* Only for pre-ILK configs */
55607e8a
DV		 915void assert_pll(struct drm_i915_private *dev_priv,
916 enum pipe pipe, bool state)
b24e7179
JB		 917{
918 int reg;
919 u32 val;
920 bool cur_state;
921
922 reg = DPLL(pipe);
923 val = I915_READ(reg);
924 cur_state = !!(val & DPLL_VCO_ENABLE);
925 WARN(cur_state != state,
926 "PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state), state_string(cur_state));
928}
b24e7179 929
55607e8a 930struct intel_shared_dpll *
e2b78267
DV		 931intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
932{
933 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
934
a43f6e0f 935 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 936 return NULL;
937
a43f6e0f 938 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 939}
940
040484af 941/* For ILK+ */
55607e8a
DV		 942void assert_shared_dpll(struct drm_i915_private *dev_priv,
943 struct intel_shared_dpll *pll,
944 bool state)
040484af 945{
040484af 946 bool cur_state;
5358901f 947 struct intel_dpll_hw_state hw_state;
040484af 948
9d82aa17
ED		 949 if (HAS_PCH_LPT(dev_priv->dev)) {
950 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
951 return;
952 }
953
92b27b08 954 if (WARN (!pll,
46edb027 955 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 956 return;
ee7b9f93 957
5358901f 958 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 959 WARN(cur_state != state,
5358901f
DV		 960 "%s assertion failure (expected %s, current %s)\n",
961 pll->name, state_string(state), state_string(cur_state));
040484af 962}
040484af
JB		 963
964static void assert_fdi_tx(struct drm_i915_private *dev_priv,
965 enum pipe pipe, bool state)
966{
967 int reg;
968 u32 val;
969 bool cur_state;
ad80a810
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
040484af 972
affa9354
PZ		 973 if (HAS_DDI(dev_priv->dev)) {
974 /* DDI does not have a specific FDI_TX register */
ad80a810 975 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 976 val = I915_READ(reg);
ad80a810 977 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 978 } else {
979 reg = FDI_TX_CTL(pipe);
980 val = I915_READ(reg);
981 cur_state = !!(val & FDI_TX_ENABLE);
982 }
040484af
JB		 983 WARN(cur_state != state,
984 "FDI TX state assertion failure (expected %s, current %s)\n",
985 state_string(state), state_string(cur_state));
986}
987#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
988#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
989
990static void assert_fdi_rx(struct drm_i915_private *dev_priv,
991 enum pipe pipe, bool state)
992{
993 int reg;
994 u32 val;
995 bool cur_state;
996
d63fa0dc
PZ		 997 reg = FDI_RX_CTL(pipe);
998 val = I915_READ(reg);
999 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1000 WARN(cur_state != state,
1001 "FDI RX state assertion failure (expected %s, current %s)\n",
1002 state_string(state), state_string(cur_state));
1003}
1004#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1005#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1006
1007static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1008 enum pipe pipe)
1009{
1010 int reg;
1011 u32 val;
1012
1013 /* ILK FDI PLL is always enabled */
1014 if (dev_priv->info->gen == 5)
1015 return;
1016
bf507ef7 1017 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1018 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1019 return;
1020
040484af
JB		 1021 reg = FDI_TX_CTL(pipe);
1022 val = I915_READ(reg);
1023 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1024}
1025
55607e8a
DV		 1026void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1027 enum pipe pipe, bool state)
040484af
JB		 1028{
1029 int reg;
1030 u32 val;
55607e8a 1031 bool cur_state;
040484af
JB		 1032
1033 reg = FDI_RX_CTL(pipe);
1034 val = I915_READ(reg);
55607e8a
DV		 1035 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1036 WARN(cur_state != state,
1037 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1038 state_string(state), state_string(cur_state));
040484af
JB		 1039}
1040
ea0760cf
JB		 1041static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1042 enum pipe pipe)
1043{
1044 int pp_reg, lvds_reg;
1045 u32 val;
1046 enum pipe panel_pipe = PIPE_A;
0de3b485 1047 bool locked = true;
ea0760cf
JB		 1048
1049 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1050 pp_reg = PCH_PP_CONTROL;
1051 lvds_reg = PCH_LVDS;
1052 } else {
1053 pp_reg = PP_CONTROL;
1054 lvds_reg = LVDS;
1055 }
1056
1057 val = I915_READ(pp_reg);
1058 if (!(val & PANEL_POWER_ON) ||
1059 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1060 locked = false;
1061
1062 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1063 panel_pipe = PIPE_B;
1064
1065 WARN(panel_pipe == pipe && locked,
1066 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1067 pipe_name(pipe));
ea0760cf
JB		 1068}
1069
b840d907
JB		 1070void assert_pipe(struct drm_i915_private *dev_priv,
1071 enum pipe pipe, bool state)
b24e7179
JB		 1072{
1073 int reg;
1074 u32 val;
63d7bbe9 1075 bool cur_state;
702e7a56
PZ		 1076 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077 pipe);
b24e7179 1078
8e636784
DV		 1079 /* if we need the pipe A quirk it must be always on */
1080 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1081 state = true;
1082
b97186f0
PZ		 1083 if (!intel_display_power_enabled(dev_priv->dev,
1084 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1085 cur_state = false;
1086 } else {
1087 reg = PIPECONF(cpu_transcoder);
1088 val = I915_READ(reg);
1089 cur_state = !!(val & PIPECONF_ENABLE);
1090 }
1091
63d7bbe9
JB		 1092 WARN(cur_state != state,
1093 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1094 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1095}
1096
931872fc
CW		 1097static void assert_plane(struct drm_i915_private *dev_priv,
1098 enum plane plane, bool state)
b24e7179
JB		 1099{
1100 int reg;
1101 u32 val;
931872fc 1102 bool cur_state;
b24e7179
JB		 1103
1104 reg = DSPCNTR(plane);
1105 val = I915_READ(reg);
931872fc
CW		 1106 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1107 WARN(cur_state != state,
1108 "plane %c assertion failure (expected %s, current %s)\n",
1109 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1110}
1111
931872fc
CW		 1112#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1113#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1114
b24e7179
JB		 1115static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1116 enum pipe pipe)
1117{
653e1026 1118 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1119 int reg, i;
1120 u32 val;
1121 int cur_pipe;
1122
653e1026
VS		 1123 /* Primary planes are fixed to pipes on gen4+ */
1124 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1125 reg = DSPCNTR(pipe);
1126 val = I915_READ(reg);
1127 WARN((val & DISPLAY_PLANE_ENABLE),
1128 "plane %c assertion failure, should be disabled but not\n",
1129 plane_name(pipe));
19ec1358 1130 return;
28c05794 1131 }
19ec1358 1132
b24e7179 1133 /* Need to check both planes against the pipe */
08e2a7de 1134 for_each_pipe(i) {
b24e7179
JB		 1135 reg = DSPCNTR(i);
1136 val = I915_READ(reg);
1137 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1138 DISPPLANE_SEL_PIPE_SHIFT;
1139 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1140 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1141 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1142 }
1143}
1144
19332d7a
JB		 1145static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
20674eef 1148 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1149 int reg, i;
1150 u32 val;
1151
20674eef
VS		 1152 if (IS_VALLEYVIEW(dev)) {
1153 for (i = 0; i < dev_priv->num_plane; i++) {
1154 reg = SPCNTR(pipe, i);
1155 val = I915_READ(reg);
1156 WARN((val & SP_ENABLE),
1157 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1158 sprite_name(pipe, i), pipe_name(pipe));
1159 }
1160 } else if (INTEL_INFO(dev)->gen >= 7) {
1161 reg = SPRCTL(pipe);
19332d7a 1162 val = I915_READ(reg);
20674eef 1163 WARN((val & SPRITE_ENABLE),
06da8da2 1164 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1165 plane_name(pipe), pipe_name(pipe));
1166 } else if (INTEL_INFO(dev)->gen >= 5) {
1167 reg = DVSCNTR(pipe);
19332d7a 1168 val = I915_READ(reg);
20674eef 1169 WARN((val & DVS_ENABLE),
06da8da2 1170 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1171 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1172 }
1173}
1174
92f2584a
JB		 1175static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1176{
1177 u32 val;
1178 bool enabled;
1179
9d82aa17
ED		 1180 if (HAS_PCH_LPT(dev_priv->dev)) {
1181 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1182 return;
1183 }
1184
92f2584a
JB		 1185 val = I915_READ(PCH_DREF_CONTROL);
1186 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1187 DREF_SUPERSPREAD_SOURCE_MASK));
1188 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1189}
1190
ab9412ba
DV		 1191static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe)
92f2584a
JB		 1193{
1194 int reg;
1195 u32 val;
1196 bool enabled;
1197
ab9412ba 1198 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1199 val = I915_READ(reg);
1200 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1201 WARN(enabled,
1202 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1203 pipe_name(pipe));
92f2584a
JB		 1204}
1205
4e634389
KP		 1206static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1208{
1209 if ((val & DP_PORT_EN) == 0)
1210 return false;
1211
1212 if (HAS_PCH_CPT(dev_priv->dev)) {
1213 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1214 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1215 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1216 return false;
1217 } else {
1218 if ((val & DP_PIPE_MASK) != (pipe << 30))
1219 return false;
1220 }
1221 return true;
1222}
1223
1519b995
KP		 1224static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 val)
1226{
dc0fa718 1227 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1228 return false;
1229
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1231 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1232 return false;
1233 } else {
dc0fa718 1234 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1235 return false;
1236 }
1237 return true;
1238}
1239
1240static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1241 enum pipe pipe, u32 val)
1242{
1243 if ((val & LVDS_PORT_EN) == 0)
1244 return false;
1245
1246 if (HAS_PCH_CPT(dev_priv->dev)) {
1247 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248 return false;
1249 } else {
1250 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1251 return false;
1252 }
1253 return true;
1254}
1255
1256static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe, u32 val)
1258{
1259 if ((val & ADPA_DAC_ENABLE) == 0)
1260 return false;
1261 if (HAS_PCH_CPT(dev_priv->dev)) {
1262 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1263 return false;
1264 } else {
1265 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1266 return false;
1267 }
1268 return true;
1269}
1270
291906f1 1271static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1272 enum pipe pipe, int reg, u32 port_sel)
291906f1 1273{
47a05eca 1274 u32 val = I915_READ(reg);
4e634389 1275 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1276 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1277 reg, pipe_name(pipe));
de9a35ab 1278
75c5da27
DV		 1279 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1280 && (val & DP_PIPEB_SELECT),
de9a35ab 1281 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1282}
1283
1284static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1285 enum pipe pipe, int reg)
1286{
47a05eca 1287 u32 val = I915_READ(reg);
b70ad586 1288 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1289 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1290 reg, pipe_name(pipe));
de9a35ab 1291
dc0fa718 1292 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1293 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1294 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1295}
1296
1297static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1298 enum pipe pipe)
1299{
1300 int reg;
1301 u32 val;
291906f1 1302
f0575e92
KP		 1303 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1304 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1306
1307 reg = PCH_ADPA;
1308 val = I915_READ(reg);
b70ad586 1309 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1310 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1311 pipe_name(pipe));
291906f1
JB		 1312
1313 reg = PCH_LVDS;
1314 val = I915_READ(reg);
b70ad586 1315 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1316 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1317 pipe_name(pipe));
291906f1 1318
e2debe91
PZ		 1319 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1320 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1322}
1323
426115cf 1324static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1325{
426115cf
DV		 1326 struct drm_device *dev = crtc->base.dev;
1327 struct drm_i915_private *dev_priv = dev->dev_private;
1328 int reg = DPLL(crtc->pipe);
1329 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1330
426115cf 1331 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1332
1333 /* No really, not for ILK+ */
1334 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1335
1336 /* PLL is protected by panel, make sure we can write it */
1337 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1338 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1339
426115cf
DV		 1340 I915_WRITE(reg, dpll);
1341 POSTING_READ(reg);
1342 udelay(150);
1343
1344 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1345 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1346
1347 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1348 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1349
1350 /* We do this three times for luck */
426115cf 1351 I915_WRITE(reg, dpll);
87442f73
DV		 1352 POSTING_READ(reg);
1353 udelay(150); /* wait for warmup */
426115cf 1354 I915_WRITE(reg, dpll);
87442f73
DV		 1355 POSTING_READ(reg);
1356 udelay(150); /* wait for warmup */
426115cf 1357 I915_WRITE(reg, dpll);
87442f73
DV		 1358 POSTING_READ(reg);
1359 udelay(150); /* wait for warmup */
1360}
1361
66e3d5c0 1362static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1363{
66e3d5c0
DV		 1364 struct drm_device *dev = crtc->base.dev;
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366 int reg = DPLL(crtc->pipe);
1367 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1368
66e3d5c0 1369 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1370
63d7bbe9 1371 /* No really, not for ILK+ */
87442f73 1372 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1373
1374 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1375 if (IS_MOBILE(dev) && !IS_I830(dev))
1376 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1377
66e3d5c0
DV		 1378 I915_WRITE(reg, dpll);
1379
1380 /* Wait for the clocks to stabilize. */
1381 POSTING_READ(reg);
1382 udelay(150);
1383
1384 if (INTEL_INFO(dev)->gen >= 4) {
1385 I915_WRITE(DPLL_MD(crtc->pipe),
1386 crtc->config.dpll_hw_state.dpll_md);
1387 } else {
1388 /* The pixel multiplier can only be updated once the
1389 * DPLL is enabled and the clocks are stable.
1390 *
1391 * So write it again.
1392 */
1393 I915_WRITE(reg, dpll);
1394 }
63d7bbe9
JB		 1395
1396 /* We do this three times for luck */
66e3d5c0 1397 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1398 POSTING_READ(reg);
1399 udelay(150); /* wait for warmup */
66e3d5c0 1400 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1401 POSTING_READ(reg);
1402 udelay(150); /* wait for warmup */
66e3d5c0 1403 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1404 POSTING_READ(reg);
1405 udelay(150); /* wait for warmup */
1406}
1407
1408/**
50b44a44 1409 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1410 * @dev_priv: i915 private structure
1411 * @pipe: pipe PLL to disable
1412 *
1413 * Disable the PLL for @pipe, making sure the pipe is off first.
1414 *
1415 * Note! This is for pre-ILK only.
1416 */
50b44a44 1417static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1418{
63d7bbe9
JB		 1419 /* Don't disable pipe A or pipe A PLLs if needed */
1420 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1421 return;
1422
1423 /* Make sure the pipe isn't still relying on us */
1424 assert_pipe_disabled(dev_priv, pipe);
1425
50b44a44
DV		 1426 I915_WRITE(DPLL(pipe), 0);
1427 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1428}
1429
89b667f8
JB		 1430void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1431{
1432 u32 port_mask;
1433
1434 if (!port)
1435 port_mask = DPLL_PORTB_READY_MASK;
1436 else
1437 port_mask = DPLL_PORTC_READY_MASK;
1438
1439 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1440 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1441 'B' + port, I915_READ(DPLL(0)));
1442}
1443
92f2584a 1444/**
e72f9fbf 1445 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1446 * @dev_priv: i915 private structure
1447 * @pipe: pipe PLL to enable
1448 *
1449 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1450 * drives the transcoder clock.
1451 */
e2b78267 1452static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1453{
e2b78267
DV		 1454 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1455 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1456
48da64a8 1457 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1458 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1459 if (WARN_ON(pll == NULL))
48da64a8
CW		 1460 return;
1461
1462 if (WARN_ON(pll->refcount == 0))
1463 return;
ee7b9f93 1464
46edb027
DV		 1465 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1466 pll->name, pll->active, pll->on,
e2b78267 1467 crtc->base.base.id);
92f2584a 1468
cdbd2316
DV		 1469 if (pll->active++) {
1470 WARN_ON(!pll->on);
e9d6944e 1471 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1472 return;
1473 }
f4a091c7 1474 WARN_ON(pll->on);
ee7b9f93 1475
46edb027 1476 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1477 pll->enable(dev_priv, pll);
ee7b9f93 1478 pll->on = true;
92f2584a
JB		 1479}
1480
e2b78267 1481static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1482{
e2b78267
DV		 1483 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1484 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1485
92f2584a
JB		 1486 /* PCH only available on ILK+ */
1487 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1488 if (WARN_ON(pll == NULL))
ee7b9f93 1489 return;
92f2584a 1490
48da64a8
CW		 1491 if (WARN_ON(pll->refcount == 0))
1492 return;
7a419866 1493
46edb027
DV		 1494 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1495 pll->name, pll->active, pll->on,
e2b78267 1496 crtc->base.base.id);
7a419866 1497
48da64a8 1498 if (WARN_ON(pll->active == 0)) {
e9d6944e 1499 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1500 return;
1501 }
1502
e9d6944e 1503 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1504 WARN_ON(!pll->on);
cdbd2316 1505 if (--pll->active)
7a419866 1506 return;
ee7b9f93 1507
46edb027 1508 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1509 pll->disable(dev_priv, pll);
ee7b9f93 1510 pll->on = false;
92f2584a
JB		 1511}
1512
b8a4f404
PZ		 1513static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1514 enum pipe pipe)
040484af 1515{
23670b32 1516 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1517 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1519 uint32_t reg, val, pipeconf_val;
040484af
JB		 1520
1521 /* PCH only available on ILK+ */
1522 BUG_ON(dev_priv->info->gen < 5);
1523
1524 /* Make sure PCH DPLL is enabled */
e72f9fbf 1525 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1526 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1527
1528 /* FDI must be feeding us bits for PCH ports */
1529 assert_fdi_tx_enabled(dev_priv, pipe);
1530 assert_fdi_rx_enabled(dev_priv, pipe);
1531
23670b32
DV		 1532 if (HAS_PCH_CPT(dev)) {
1533 /* Workaround: Set the timing override bit before enabling the
1534 * pch transcoder. */
1535 reg = TRANS_CHICKEN2(pipe);
1536 val = I915_READ(reg);
1537 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1538 I915_WRITE(reg, val);
59c859d6 1539 }
23670b32 1540
ab9412ba 1541 reg = PCH_TRANSCONF(pipe);
040484af 1542 val = I915_READ(reg);
5f7f726d 1543 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1544
1545 if (HAS_PCH_IBX(dev_priv->dev)) {
1546 /*
1547 * make the BPC in transcoder be consistent with
1548 * that in pipeconf reg.
1549 */
dfd07d72
DV		 1550 val &= ~PIPECONF_BPC_MASK;
1551 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1552 }
5f7f726d
PZ		 1553
1554 val &= ~TRANS_INTERLACE_MASK;
1555 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1556 if (HAS_PCH_IBX(dev_priv->dev) &&
1557 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1558 val |= TRANS_LEGACY_INTERLACED_ILK;
1559 else
1560 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1561 else
1562 val |= TRANS_PROGRESSIVE;
1563
040484af
JB		 1564 I915_WRITE(reg, val | TRANS_ENABLE);
1565 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1566 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1567}
1568
8fb033d7 1569static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1570 enum transcoder cpu_transcoder)
040484af 1571{
8fb033d7 1572 u32 val, pipeconf_val;
8fb033d7
PZ		 1573
1574 /* PCH only available on ILK+ */
1575 BUG_ON(dev_priv->info->gen < 5);
1576
8fb033d7 1577 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1578 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1579 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1580
223a6fdf
PZ		 1581 /* Workaround: set timing override bit. */
1582 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1583 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1584 I915_WRITE(_TRANSA_CHICKEN2, val);
1585
25f3ef11 1586 val = TRANS_ENABLE;
937bb610 1587 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1588
9a76b1c6
PZ		 1589 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1590 PIPECONF_INTERLACED_ILK)
a35f2679 1591 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1592 else
1593 val |= TRANS_PROGRESSIVE;
1594
ab9412ba
DV		 1595 I915_WRITE(LPT_TRANSCONF, val);
1596 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1597 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1598}
1599
b8a4f404
PZ		 1600static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1601 enum pipe pipe)
040484af 1602{
23670b32
DV		 1603 struct drm_device *dev = dev_priv->dev;
1604 uint32_t reg, val;
040484af
JB		 1605
1606 /* FDI relies on the transcoder */
1607 assert_fdi_tx_disabled(dev_priv, pipe);
1608 assert_fdi_rx_disabled(dev_priv, pipe);
1609
291906f1
JB		 1610 /* Ports must be off as well */
1611 assert_pch_ports_disabled(dev_priv, pipe);
1612
ab9412ba 1613 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1614 val = I915_READ(reg);
1615 val &= ~TRANS_ENABLE;
1616 I915_WRITE(reg, val);
1617 /* wait for PCH transcoder off, transcoder state */
1618 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1619 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1620
1621 if (!HAS_PCH_IBX(dev)) {
1622 /* Workaround: Clear the timing override chicken bit again. */
1623 reg = TRANS_CHICKEN2(pipe);
1624 val = I915_READ(reg);
1625 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1626 I915_WRITE(reg, val);
1627 }
040484af
JB		 1628}
1629
ab4d966c 1630static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1631{
8fb033d7
PZ		 1632 u32 val;
1633
ab9412ba 1634 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1635 val &= ~TRANS_ENABLE;
ab9412ba 1636 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1637 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1638 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1639 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1640
1641 /* Workaround: clear timing override bit. */
1642 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1643 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1644 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1645}
1646
b24e7179 1647/**
309cfea8 1648 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1649 * @dev_priv: i915 private structure
1650 * @pipe: pipe to enable
040484af 1651 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1652 *
1653 * Enable @pipe, making sure that various hardware specific requirements
1654 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1655 *
1656 * @pipe should be %PIPE_A or %PIPE_B.
1657 *
1658 * Will wait until the pipe is actually running (i.e. first vblank) before
1659 * returning.
1660 */
040484af
JB		 1661static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1662 bool pch_port)
b24e7179 1663{
702e7a56
PZ		 1664 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1665 pipe);
1a240d4d 1666 enum pipe pch_transcoder;
b24e7179
JB		 1667 int reg;
1668 u32 val;
1669
58c6eaa2
DV		 1670 assert_planes_disabled(dev_priv, pipe);
1671 assert_sprites_disabled(dev_priv, pipe);
1672
681e5811 1673 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1674 pch_transcoder = TRANSCODER_A;
1675 else
1676 pch_transcoder = pipe;
1677
b24e7179
JB		 1678 /*
1679 * A pipe without a PLL won't actually be able to drive bits from
1680 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1681 * need the check.
1682 */
1683 if (!HAS_PCH_SPLIT(dev_priv->dev))
1684 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1685 else {
1686 if (pch_port) {
1687 /* if driving the PCH, we need FDI enabled */
cc391bbb 1688 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1689 assert_fdi_tx_pll_enabled(dev_priv,
1690 (enum pipe) cpu_transcoder);
040484af
JB		 1691 }
1692 /* FIXME: assert CPU port conditions for SNB+ */
1693 }
b24e7179 1694
702e7a56 1695 reg = PIPECONF(cpu_transcoder);
b24e7179 1696 val = I915_READ(reg);
00d70b15
CW		 1697 if (val & PIPECONF_ENABLE)
1698 return;
1699
1700 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1701 intel_wait_for_vblank(dev_priv->dev, pipe);
1702}
1703
1704/**
309cfea8 1705 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1706 * @dev_priv: i915 private structure
1707 * @pipe: pipe to disable
1708 *
1709 * Disable @pipe, making sure that various hardware specific requirements
1710 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1711 *
1712 * @pipe should be %PIPE_A or %PIPE_B.
1713 *
1714 * Will wait until the pipe has shut down before returning.
1715 */
1716static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1717 enum pipe pipe)
1718{
702e7a56
PZ		 1719 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1720 pipe);
b24e7179
JB		 1721 int reg;
1722 u32 val;
1723
1724 /*
1725 * Make sure planes won't keep trying to pump pixels to us,
1726 * or we might hang the display.
1727 */
1728 assert_planes_disabled(dev_priv, pipe);
19332d7a 1729 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1730
1731 /* Don't disable pipe A or pipe A PLLs if needed */
1732 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1733 return;
1734
702e7a56 1735 reg = PIPECONF(cpu_transcoder);
b24e7179 1736 val = I915_READ(reg);
00d70b15
CW		 1737 if ((val & PIPECONF_ENABLE) == 0)
1738 return;
1739
1740 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1741 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1742}
1743
d74362c9
KP		 1744/*
1745 * Plane regs are double buffered, going from enabled->disabled needs a
1746 * trigger in order to latch. The display address reg provides this.
1747 */
6f1d69b0 1748void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1749 enum plane plane)
1750{
14f86147
DL		 1751 if (dev_priv->info->gen >= 4)
1752 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1753 else
1754 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1755}
1756
b24e7179
JB		 1757/**
1758 * intel_enable_plane - enable a display plane on a given pipe
1759 * @dev_priv: i915 private structure
1760 * @plane: plane to enable
1761 * @pipe: pipe being fed
1762 *
1763 * Enable @plane on @pipe, making sure that @pipe is running first.
1764 */
1765static void intel_enable_plane(struct drm_i915_private *dev_priv,
1766 enum plane plane, enum pipe pipe)
1767{
1768 int reg;
1769 u32 val;
1770
1771 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1772 assert_pipe_enabled(dev_priv, pipe);
1773
1774 reg = DSPCNTR(plane);
1775 val = I915_READ(reg);
00d70b15
CW		 1776 if (val & DISPLAY_PLANE_ENABLE)
1777 return;
1778
1779 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1780 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1781 intel_wait_for_vblank(dev_priv->dev, pipe);
1782}
1783
b24e7179
JB		 1784/**
1785 * intel_disable_plane - disable a display plane
1786 * @dev_priv: i915 private structure
1787 * @plane: plane to disable
1788 * @pipe: pipe consuming the data
1789 *
1790 * Disable @plane; should be an independent operation.
1791 */
1792static void intel_disable_plane(struct drm_i915_private *dev_priv,
1793 enum plane plane, enum pipe pipe)
1794{
1795 int reg;
1796 u32 val;
1797
1798 reg = DSPCNTR(plane);
1799 val = I915_READ(reg);
00d70b15
CW		 1800 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1801 return;
1802
1803 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1804 intel_flush_display_plane(dev_priv, plane);
1805 intel_wait_for_vblank(dev_priv->dev, pipe);
1806}
1807
693db184
CW		 1808static bool need_vtd_wa(struct drm_device *dev)
1809{
1810#ifdef CONFIG_INTEL_IOMMU
1811 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1812 return true;
1813#endif
1814 return false;
1815}
1816
127bd2ac 1817int
48b956c5 1818intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1819 struct drm_i915_gem_object *obj,
919926ae 1820 struct intel_ring_buffer *pipelined)
6b95a207 1821{
ce453d81 1822 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1823 u32 alignment;
1824 int ret;
1825
05394f39 1826 switch (obj->tiling_mode) {
6b95a207 1827 case I915_TILING_NONE:
534843da
CW		 1828 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1829 alignment = 128 * 1024;
a6c45cf0 1830 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1831 alignment = 4 * 1024;
1832 else
1833 alignment = 64 * 1024;
6b95a207
KH		 1834 break;
1835 case I915_TILING_X:
1836 /* pin() will align the object as required by fence */
1837 alignment = 0;
1838 break;
1839 case I915_TILING_Y:
8bb6e959
DV		 1840 /* Despite that we check this in framebuffer_init userspace can
1841 * screw us over and change the tiling after the fact. Only
1842 * pinned buffers can't change their tiling. */
1843 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1844 return -EINVAL;
1845 default:
1846 BUG();
1847 }
1848
693db184
CW		 1849 /* Note that the w/a also requires 64 PTE of padding following the
1850 * bo. We currently fill all unused PTE with the shadow page and so
1851 * we should always have valid PTE following the scanout preventing
1852 * the VT-d warning.
1853 */
1854 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1855 alignment = 256 * 1024;
1856
ce453d81 1857 dev_priv->mm.interruptible = false;
2da3b9b9 1858 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1859 if (ret)
ce453d81 1860 goto err_interruptible;
6b95a207
KH		 1861
1862 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1863 * fence, whereas 965+ only requires a fence if using
1864 * framebuffer compression. For simplicity, we always install
1865 * a fence as the cost is not that onerous.
1866 */
06d98131 1867 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1868 if (ret)
1869 goto err_unpin;
1690e1eb 1870
9a5a53b3 1871 i915_gem_object_pin_fence(obj);
6b95a207 1872
ce453d81 1873 dev_priv->mm.interruptible = true;
6b95a207 1874 return 0;
48b956c5
CW		 1875
1876err_unpin:
1877 i915_gem_object_unpin(obj);
ce453d81
CW		 1878err_interruptible:
1879 dev_priv->mm.interruptible = true;
48b956c5 1880 return ret;
6b95a207
KH		 1881}
1882
1690e1eb
CW		 1883void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1884{
1885 i915_gem_object_unpin_fence(obj);
1886 i915_gem_object_unpin(obj);
1887}
1888
c2c75131
DV		 1889/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1890 * is assumed to be a power-of-two. */
bc752862
CW		 1891unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1892 unsigned int tiling_mode,
1893 unsigned int cpp,
1894 unsigned int pitch)
c2c75131 1895{
bc752862
CW		 1896 if (tiling_mode != I915_TILING_NONE) {
1897 unsigned int tile_rows, tiles;
c2c75131 1898
bc752862
CW		 1899 tile_rows = *y / 8;
1900 *y %= 8;
c2c75131 1901
bc752862
CW		 1902 tiles = *x / (512/cpp);
1903 *x %= 512/cpp;
1904
1905 return tile_rows * pitch * 8 + tiles * 4096;
1906 } else {
1907 unsigned int offset;
1908
1909 offset = *y * pitch + *x * cpp;
1910 *y = 0;
1911 *x = (offset & 4095) / cpp;
1912 return offset & -4096;
1913 }
c2c75131
DV		 1914}
1915
17638cd6
JB		 1916static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1917 int x, int y)
81255565
JB		 1918{
1919 struct drm_device *dev = crtc->dev;
1920 struct drm_i915_private *dev_priv = dev->dev_private;
1921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1922 struct intel_framebuffer *intel_fb;
05394f39 1923 struct drm_i915_gem_object *obj;
81255565 1924 int plane = intel_crtc->plane;
e506a0c6 1925 unsigned long linear_offset;
81255565 1926 u32 dspcntr;
5eddb70b 1927 u32 reg;
81255565
JB		 1928
1929 switch (plane) {
1930 case 0:
1931 case 1:
1932 break;
1933 default:
84f44ce7 1934 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1935 return -EINVAL;
1936 }
1937
1938 intel_fb = to_intel_framebuffer(fb);
1939 obj = intel_fb->obj;
81255565 1940
5eddb70b
CW		 1941 reg = DSPCNTR(plane);
1942 dspcntr = I915_READ(reg);
81255565
JB		 1943 /* Mask out pixel format bits in case we change it */
1944 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1945 switch (fb->pixel_format) {
1946 case DRM_FORMAT_C8:
81255565
JB		 1947 dspcntr |= DISPPLANE_8BPP;
1948 break;
57779d06
VS		 1949 case DRM_FORMAT_XRGB1555:
1950 case DRM_FORMAT_ARGB1555:
1951 dspcntr |= DISPPLANE_BGRX555;
81255565 1952 break;
57779d06
VS		 1953 case DRM_FORMAT_RGB565:
1954 dspcntr |= DISPPLANE_BGRX565;
1955 break;
1956 case DRM_FORMAT_XRGB8888:
1957 case DRM_FORMAT_ARGB8888:
1958 dspcntr |= DISPPLANE_BGRX888;
1959 break;
1960 case DRM_FORMAT_XBGR8888:
1961 case DRM_FORMAT_ABGR8888:
1962 dspcntr |= DISPPLANE_RGBX888;
1963 break;
1964 case DRM_FORMAT_XRGB2101010:
1965 case DRM_FORMAT_ARGB2101010:
1966 dspcntr |= DISPPLANE_BGRX101010;
1967 break;
1968 case DRM_FORMAT_XBGR2101010:
1969 case DRM_FORMAT_ABGR2101010:
1970 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1971 break;
1972 default:
baba133a 1973 BUG();
81255565 1974 }
57779d06 1975
a6c45cf0 1976 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1977 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1978 dspcntr |= DISPPLANE_TILED;
1979 else
1980 dspcntr &= ~DISPPLANE_TILED;
1981 }
1982
de1aa629
VS		 1983 if (IS_G4X(dev))
1984 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1985
5eddb70b 1986 I915_WRITE(reg, dspcntr);
81255565 1987
e506a0c6 1988 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1989
c2c75131
DV		 1990 if (INTEL_INFO(dev)->gen >= 4) {
1991 intel_crtc->dspaddr_offset =
bc752862
CW		 1992 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1993 fb->bits_per_pixel / 8,
1994 fb->pitches[0]);
c2c75131
DV		 1995 linear_offset -= intel_crtc->dspaddr_offset;
1996 } else {
e506a0c6 1997 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1998 }
e506a0c6 1999
f343c5f6
BW		 2000 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2001 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2002 fb->pitches[0]);
01f2c773 2003 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2004 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2005 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2006 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2007 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2008 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2009 } else
f343c5f6 2010 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2011 POSTING_READ(reg);
81255565 2012
17638cd6
JB		 2013 return 0;
2014}
2015
2016static int ironlake_update_plane(struct drm_crtc *crtc,
2017 struct drm_framebuffer *fb, int x, int y)
2018{
2019 struct drm_device *dev = crtc->dev;
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2022 struct intel_framebuffer *intel_fb;
2023 struct drm_i915_gem_object *obj;
2024 int plane = intel_crtc->plane;
e506a0c6 2025 unsigned long linear_offset;
17638cd6
JB		 2026 u32 dspcntr;
2027 u32 reg;
2028
2029 switch (plane) {
2030 case 0:
2031 case 1:
27f8227b 2032 case 2:
17638cd6
JB		 2033 break;
2034 default:
84f44ce7 2035 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2036 return -EINVAL;
2037 }
2038
2039 intel_fb = to_intel_framebuffer(fb);
2040 obj = intel_fb->obj;
2041
2042 reg = DSPCNTR(plane);
2043 dspcntr = I915_READ(reg);
2044 /* Mask out pixel format bits in case we change it */
2045 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2046 switch (fb->pixel_format) {
2047 case DRM_FORMAT_C8:
17638cd6
JB		 2048 dspcntr |= DISPPLANE_8BPP;
2049 break;
57779d06
VS		 2050 case DRM_FORMAT_RGB565:
2051 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2052 break;
57779d06
VS		 2053 case DRM_FORMAT_XRGB8888:
2054 case DRM_FORMAT_ARGB8888:
2055 dspcntr |= DISPPLANE_BGRX888;
2056 break;
2057 case DRM_FORMAT_XBGR8888:
2058 case DRM_FORMAT_ABGR8888:
2059 dspcntr |= DISPPLANE_RGBX888;
2060 break;
2061 case DRM_FORMAT_XRGB2101010:
2062 case DRM_FORMAT_ARGB2101010:
2063 dspcntr |= DISPPLANE_BGRX101010;
2064 break;
2065 case DRM_FORMAT_XBGR2101010:
2066 case DRM_FORMAT_ABGR2101010:
2067 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2068 break;
2069 default:
baba133a 2070 BUG();
17638cd6
JB		 2071 }
2072
2073 if (obj->tiling_mode != I915_TILING_NONE)
2074 dspcntr |= DISPPLANE_TILED;
2075 else
2076 dspcntr &= ~DISPPLANE_TILED;
2077
2078 /* must disable */
2079 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2080
2081 I915_WRITE(reg, dspcntr);
2082
e506a0c6 2083 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2084 intel_crtc->dspaddr_offset =
bc752862
CW		 2085 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2086 fb->bits_per_pixel / 8,
2087 fb->pitches[0]);
c2c75131 2088 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2089
f343c5f6
BW		 2090 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2091 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2092 fb->pitches[0]);
01f2c773 2093 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2094 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2095 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2096 if (IS_HASWELL(dev)) {
2097 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2098 } else {
2099 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2100 I915_WRITE(DSPLINOFF(plane), linear_offset);
2101 }
17638cd6
JB		 2102 POSTING_READ(reg);
2103
2104 return 0;
2105}
2106
2107/* Assume fb object is pinned & idle & fenced and just update base pointers */
2108static int
2109intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2110 int x, int y, enum mode_set_atomic state)
2111{
2112 struct drm_device *dev = crtc->dev;
2113 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2114
6b8e6ed0
CW		 2115 if (dev_priv->display.disable_fbc)
2116 dev_priv->display.disable_fbc(dev);
3dec0095 2117 intel_increase_pllclock(crtc);
81255565 2118
6b8e6ed0 2119 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2120}
2121
96a02917
VS		 2122void intel_display_handle_reset(struct drm_device *dev)
2123{
2124 struct drm_i915_private *dev_priv = dev->dev_private;
2125 struct drm_crtc *crtc;
2126
2127 /*
2128 * Flips in the rings have been nuked by the reset,
2129 * so complete all pending flips so that user space
2130 * will get its events and not get stuck.
2131 *
2132 * Also update the base address of all primary
2133 * planes to the the last fb to make sure we're
2134 * showing the correct fb after a reset.
2135 *
2136 * Need to make two loops over the crtcs so that we
2137 * don't try to grab a crtc mutex before the
2138 * pending_flip_queue really got woken up.
2139 */
2140
2141 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143 enum plane plane = intel_crtc->plane;
2144
2145 intel_prepare_page_flip(dev, plane);
2146 intel_finish_page_flip_plane(dev, plane);
2147 }
2148
2149 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2151
2152 mutex_lock(&crtc->mutex);
2153 if (intel_crtc->active)
2154 dev_priv->display.update_plane(crtc, crtc->fb,
2155 crtc->x, crtc->y);
2156 mutex_unlock(&crtc->mutex);
2157 }
2158}
2159
14667a4b
CW		 2160static int
2161intel_finish_fb(struct drm_framebuffer *old_fb)
2162{
2163 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2164 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2165 bool was_interruptible = dev_priv->mm.interruptible;
2166 int ret;
2167
14667a4b
CW		 2168 /* Big Hammer, we also need to ensure that any pending
2169 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2170 * current scanout is retired before unpinning the old
2171 * framebuffer.
2172 *
2173 * This should only fail upon a hung GPU, in which case we
2174 * can safely continue.
2175 */
2176 dev_priv->mm.interruptible = false;
2177 ret = i915_gem_object_finish_gpu(obj);
2178 dev_priv->mm.interruptible = was_interruptible;
2179
2180 return ret;
2181}
2182
198598d0
VS		 2183static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2184{
2185 struct drm_device *dev = crtc->dev;
2186 struct drm_i915_master_private *master_priv;
2187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188
2189 if (!dev->primary->master)
2190 return;
2191
2192 master_priv = dev->primary->master->driver_priv;
2193 if (!master_priv->sarea_priv)
2194 return;
2195
2196 switch (intel_crtc->pipe) {
2197 case 0:
2198 master_priv->sarea_priv->pipeA_x = x;
2199 master_priv->sarea_priv->pipeA_y = y;
2200 break;
2201 case 1:
2202 master_priv->sarea_priv->pipeB_x = x;
2203 master_priv->sarea_priv->pipeB_y = y;
2204 break;
2205 default:
2206 break;
2207 }
2208}
2209
5c3b82e2 2210static int
3c4fdcfb 2211intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2212 struct drm_framebuffer *fb)
79e53945
JB		 2213{
2214 struct drm_device *dev = crtc->dev;
6b8e6ed0 2215 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2217 struct drm_framebuffer *old_fb;
5c3b82e2 2218 int ret;
79e53945
JB		 2219
2220 /* no fb bound */
94352cf9 2221 if (!fb) {
a5071c2f 2222 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2223 return 0;
2224 }
2225
7eb552ae 2226 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2227 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2228 plane_name(intel_crtc->plane),
2229 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2230 return -EINVAL;
79e53945
JB		 2231 }
2232
5c3b82e2 2233 mutex_lock(&dev->struct_mutex);
265db958 2234 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2235 to_intel_framebuffer(fb)->obj,
919926ae 2236 NULL);
5c3b82e2
CW		 2237 if (ret != 0) {
2238 mutex_unlock(&dev->struct_mutex);
a5071c2f 2239 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2240 return ret;
2241 }
79e53945 2242
4d6a3e63
JB		 2243 /* Update pipe size and adjust fitter if needed */
2244 if (i915_fastboot) {
2245 I915_WRITE(PIPESRC(intel_crtc->pipe),
2246 ((crtc->mode.hdisplay - 1) << 16) |
2247 (crtc->mode.vdisplay - 1));
2248 if (!intel_crtc->config.pch_pfit.size &&
2249 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2250 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2251 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2252 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2253 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2254 }
2255 }
2256
94352cf9 2257 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2258 if (ret) {
94352cf9 2259 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2260 mutex_unlock(&dev->struct_mutex);
a5071c2f 2261 DRM_ERROR("failed to update base address\n");
4e6cfefc 2262 return ret;
79e53945 2263 }
3c4fdcfb 2264
94352cf9
DV		 2265 old_fb = crtc->fb;
2266 crtc->fb = fb;
6c4c86f5
DV		 2267 crtc->x = x;
2268 crtc->y = y;
94352cf9 2269
b7f1de28 2270 if (old_fb) {
d7697eea
DV		 2271 if (intel_crtc->active && old_fb != fb)
2272 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2273 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2274 }
652c393a 2275
6b8e6ed0 2276 intel_update_fbc(dev);
4906557e 2277 intel_edp_psr_update(dev);
5c3b82e2 2278 mutex_unlock(&dev->struct_mutex);
79e53945 2279
198598d0 2280 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2281
2282 return 0;
79e53945
JB		 2283}
2284
5e84e1a4
ZW		 2285static void intel_fdi_normal_train(struct drm_crtc *crtc)
2286{
2287 struct drm_device *dev = crtc->dev;
2288 struct drm_i915_private *dev_priv = dev->dev_private;
2289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2290 int pipe = intel_crtc->pipe;
2291 u32 reg, temp;
2292
2293 /* enable normal train */
2294 reg = FDI_TX_CTL(pipe);
2295 temp = I915_READ(reg);
61e499bf 2296 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2297 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2298 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2299 } else {
2300 temp &= ~FDI_LINK_TRAIN_NONE;
2301 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2302 }
5e84e1a4
ZW		 2303 I915_WRITE(reg, temp);
2304
2305 reg = FDI_RX_CTL(pipe);
2306 temp = I915_READ(reg);
2307 if (HAS_PCH_CPT(dev)) {
2308 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2309 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2310 } else {
2311 temp &= ~FDI_LINK_TRAIN_NONE;
2312 temp |= FDI_LINK_TRAIN_NONE;
2313 }
2314 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2315
2316 /* wait one idle pattern time */
2317 POSTING_READ(reg);
2318 udelay(1000);
357555c0
JB		 2319
2320 /* IVB wants error correction enabled */
2321 if (IS_IVYBRIDGE(dev))
2322 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2323 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2324}
2325
1e833f40
DV		 2326static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2327{
2328 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2329}
2330
01a415fd
DV		 2331static void ivb_modeset_global_resources(struct drm_device *dev)
2332{
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct intel_crtc *pipe_B_crtc =
2335 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2336 struct intel_crtc *pipe_C_crtc =
2337 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2338 uint32_t temp;
2339
1e833f40
DV		 2340 /*
2341 * When everything is off disable fdi C so that we could enable fdi B
2342 * with all lanes. Note that we don't care about enabled pipes without
2343 * an enabled pch encoder.
2344 */
2345 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2346 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2347 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2348 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2349
2350 temp = I915_READ(SOUTH_CHICKEN1);
2351 temp &= ~FDI_BC_BIFURCATION_SELECT;
2352 DRM_DEBUG_KMS("disabling fdi C rx\n");
2353 I915_WRITE(SOUTH_CHICKEN1, temp);
2354 }
2355}
2356
8db9d77b
ZW		 2357/* The FDI link training functions for ILK/Ibexpeak. */
2358static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2359{
2360 struct drm_device *dev = crtc->dev;
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2363 int pipe = intel_crtc->pipe;
0fc932b8 2364 int plane = intel_crtc->plane;
5eddb70b 2365 u32 reg, temp, tries;
8db9d77b 2366
0fc932b8
JB		 2367 /* FDI needs bits from pipe & plane first */
2368 assert_pipe_enabled(dev_priv, pipe);
2369 assert_plane_enabled(dev_priv, plane);
2370
e1a44743
AJ		 2371 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2372 for train result */
5eddb70b
CW		 2373 reg = FDI_RX_IMR(pipe);
2374 temp = I915_READ(reg);
e1a44743
AJ		 2375 temp &= ~FDI_RX_SYMBOL_LOCK;
2376 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2377 I915_WRITE(reg, temp);
2378 I915_READ(reg);
e1a44743
AJ		 2379 udelay(150);
2380
8db9d77b 2381 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2382 reg = FDI_TX_CTL(pipe);
2383 temp = I915_READ(reg);
627eb5a3
DV		 2384 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2385 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2386 temp &= ~FDI_LINK_TRAIN_NONE;
2387 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2388 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2389
5eddb70b
CW		 2390 reg = FDI_RX_CTL(pipe);
2391 temp = I915_READ(reg);
8db9d77b
ZW		 2392 temp &= ~FDI_LINK_TRAIN_NONE;
2393 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2394 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2395
2396 POSTING_READ(reg);
8db9d77b
ZW		 2397 udelay(150);
2398
5b2adf89 2399 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2400 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2401 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2402 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2403
5eddb70b 2404 reg = FDI_RX_IIR(pipe);
e1a44743 2405 for (tries = 0; tries < 5; tries++) {
5eddb70b 2406 temp = I915_READ(reg);
8db9d77b
ZW		 2407 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2408
2409 if ((temp & FDI_RX_BIT_LOCK)) {
2410 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2411 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2412 break;
2413 }
8db9d77b 2414 }
e1a44743 2415 if (tries == 5)
5eddb70b 2416 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2417
2418 /* Train 2 */
5eddb70b
CW		 2419 reg = FDI_TX_CTL(pipe);
2420 temp = I915_READ(reg);
8db9d77b
ZW		 2421 temp &= ~FDI_LINK_TRAIN_NONE;
2422 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2423 I915_WRITE(reg, temp);
8db9d77b 2424
5eddb70b
CW		 2425 reg = FDI_RX_CTL(pipe);
2426 temp = I915_READ(reg);
8db9d77b
ZW		 2427 temp &= ~FDI_LINK_TRAIN_NONE;
2428 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2429 I915_WRITE(reg, temp);
8db9d77b 2430
5eddb70b
CW		 2431 POSTING_READ(reg);
2432 udelay(150);
8db9d77b 2433
5eddb70b 2434 reg = FDI_RX_IIR(pipe);
e1a44743 2435 for (tries = 0; tries < 5; tries++) {
5eddb70b 2436 temp = I915_READ(reg);
8db9d77b
ZW		 2437 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2438
2439 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2440 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2441 DRM_DEBUG_KMS("FDI train 2 done.\n");
2442 break;
2443 }
8db9d77b 2444 }
e1a44743 2445 if (tries == 5)
5eddb70b 2446 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2447
2448 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2449
8db9d77b
ZW		 2450}
2451
0206e353 2452static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2453 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2454 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2455 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2456 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2457};
2458
2459/* The FDI link training functions for SNB/Cougarpoint. */
2460static void gen6_fdi_link_train(struct drm_crtc *crtc)
2461{
2462 struct drm_device *dev = crtc->dev;
2463 struct drm_i915_private *dev_priv = dev->dev_private;
2464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2465 int pipe = intel_crtc->pipe;
fa37d39e 2466 u32 reg, temp, i, retry;
8db9d77b 2467
e1a44743
AJ		 2468 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2469 for train result */
5eddb70b
CW		 2470 reg = FDI_RX_IMR(pipe);
2471 temp = I915_READ(reg);
e1a44743
AJ		 2472 temp &= ~FDI_RX_SYMBOL_LOCK;
2473 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2474 I915_WRITE(reg, temp);
2475
2476 POSTING_READ(reg);
e1a44743
AJ		 2477 udelay(150);
2478
8db9d77b 2479 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2480 reg = FDI_TX_CTL(pipe);
2481 temp = I915_READ(reg);
627eb5a3
DV		 2482 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2483 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2484 temp &= ~FDI_LINK_TRAIN_NONE;
2485 temp |= FDI_LINK_TRAIN_PATTERN_1;
2486 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2487 /* SNB-B */
2488 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2489 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2490
d74cf324
DV		 2491 I915_WRITE(FDI_RX_MISC(pipe),
2492 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2493
5eddb70b
CW		 2494 reg = FDI_RX_CTL(pipe);
2495 temp = I915_READ(reg);
8db9d77b
ZW		 2496 if (HAS_PCH_CPT(dev)) {
2497 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2498 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2499 } else {
2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 }
5eddb70b
CW		 2503 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2504
2505 POSTING_READ(reg);
8db9d77b
ZW		 2506 udelay(150);
2507
0206e353 2508 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2509 reg = FDI_TX_CTL(pipe);
2510 temp = I915_READ(reg);
8db9d77b
ZW		 2511 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2512 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2513 I915_WRITE(reg, temp);
2514
2515 POSTING_READ(reg);
8db9d77b
ZW		 2516 udelay(500);
2517
fa37d39e
SP		 2518 for (retry = 0; retry < 5; retry++) {
2519 reg = FDI_RX_IIR(pipe);
2520 temp = I915_READ(reg);
2521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522 if (temp & FDI_RX_BIT_LOCK) {
2523 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2524 DRM_DEBUG_KMS("FDI train 1 done.\n");
2525 break;
2526 }
2527 udelay(50);
8db9d77b 2528 }
fa37d39e
SP		 2529 if (retry < 5)
2530 break;
8db9d77b
ZW		 2531 }
2532 if (i == 4)
5eddb70b 2533 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2534
2535 /* Train 2 */
5eddb70b
CW		 2536 reg = FDI_TX_CTL(pipe);
2537 temp = I915_READ(reg);
8db9d77b
ZW		 2538 temp &= ~FDI_LINK_TRAIN_NONE;
2539 temp |= FDI_LINK_TRAIN_PATTERN_2;
2540 if (IS_GEN6(dev)) {
2541 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2542 /* SNB-B */
2543 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2544 }
5eddb70b 2545 I915_WRITE(reg, temp);
8db9d77b 2546
5eddb70b
CW		 2547 reg = FDI_RX_CTL(pipe);
2548 temp = I915_READ(reg);
8db9d77b
ZW		 2549 if (HAS_PCH_CPT(dev)) {
2550 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2551 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2552 } else {
2553 temp &= ~FDI_LINK_TRAIN_NONE;
2554 temp |= FDI_LINK_TRAIN_PATTERN_2;
2555 }
5eddb70b
CW		 2556 I915_WRITE(reg, temp);
2557
2558 POSTING_READ(reg);
8db9d77b
ZW		 2559 udelay(150);
2560
0206e353 2561 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2562 reg = FDI_TX_CTL(pipe);
2563 temp = I915_READ(reg);
8db9d77b
ZW		 2564 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2566 I915_WRITE(reg, temp);
2567
2568 POSTING_READ(reg);
8db9d77b
ZW		 2569 udelay(500);
2570
fa37d39e
SP		 2571 for (retry = 0; retry < 5; retry++) {
2572 reg = FDI_RX_IIR(pipe);
2573 temp = I915_READ(reg);
2574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2575 if (temp & FDI_RX_SYMBOL_LOCK) {
2576 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2577 DRM_DEBUG_KMS("FDI train 2 done.\n");
2578 break;
2579 }
2580 udelay(50);
8db9d77b 2581 }
fa37d39e
SP		 2582 if (retry < 5)
2583 break;
8db9d77b
ZW		 2584 }
2585 if (i == 4)
5eddb70b 2586 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2587
2588 DRM_DEBUG_KMS("FDI train done.\n");
2589}
2590
357555c0
JB		 2591/* Manual link training for Ivy Bridge A0 parts */
2592static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2593{
2594 struct drm_device *dev = crtc->dev;
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2597 int pipe = intel_crtc->pipe;
2598 u32 reg, temp, i;
2599
2600 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2601 for train result */
2602 reg = FDI_RX_IMR(pipe);
2603 temp = I915_READ(reg);
2604 temp &= ~FDI_RX_SYMBOL_LOCK;
2605 temp &= ~FDI_RX_BIT_LOCK;
2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
2609 udelay(150);
2610
01a415fd
DV		 2611 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2612 I915_READ(FDI_RX_IIR(pipe)));
2613
357555c0
JB		 2614 /* enable CPU FDI TX and PCH FDI RX */
2615 reg = FDI_TX_CTL(pipe);
2616 temp = I915_READ(reg);
627eb5a3
DV		 2617 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2618 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2619 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2620 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2623 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2624 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2625
d74cf324
DV		 2626 I915_WRITE(FDI_RX_MISC(pipe),
2627 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2628
357555c0
JB		 2629 reg = FDI_RX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 temp &= ~FDI_LINK_TRAIN_AUTO;
2632 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2633 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2634 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2635 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2636
2637 POSTING_READ(reg);
2638 udelay(150);
2639
0206e353 2640 for (i = 0; i < 4; i++) {
357555c0
JB		 2641 reg = FDI_TX_CTL(pipe);
2642 temp = I915_READ(reg);
2643 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2644 temp |= snb_b_fdi_train_param[i];
2645 I915_WRITE(reg, temp);
2646
2647 POSTING_READ(reg);
2648 udelay(500);
2649
2650 reg = FDI_RX_IIR(pipe);
2651 temp = I915_READ(reg);
2652 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2653
2654 if (temp & FDI_RX_BIT_LOCK ||
2655 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2656 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2657 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2658 break;
2659 }
2660 }
2661 if (i == 4)
2662 DRM_ERROR("FDI train 1 fail!\n");
2663
2664 /* Train 2 */
2665 reg = FDI_TX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2668 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2669 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2670 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2671 I915_WRITE(reg, temp);
2672
2673 reg = FDI_RX_CTL(pipe);
2674 temp = I915_READ(reg);
2675 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2676 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2677 I915_WRITE(reg, temp);
2678
2679 POSTING_READ(reg);
2680 udelay(150);
2681
0206e353 2682 for (i = 0; i < 4; i++) {
357555c0
JB		 2683 reg = FDI_TX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2686 temp |= snb_b_fdi_train_param[i];
2687 I915_WRITE(reg, temp);
2688
2689 POSTING_READ(reg);
2690 udelay(500);
2691
2692 reg = FDI_RX_IIR(pipe);
2693 temp = I915_READ(reg);
2694 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2695
2696 if (temp & FDI_RX_SYMBOL_LOCK) {
2697 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2698 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2699 break;
2700 }
2701 }
2702 if (i == 4)
2703 DRM_ERROR("FDI train 2 fail!\n");
2704
2705 DRM_DEBUG_KMS("FDI train done.\n");
2706}
2707
88cefb6c 2708static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2709{
88cefb6c 2710 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2711 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2712 int pipe = intel_crtc->pipe;
5eddb70b 2713 u32 reg, temp;
79e53945 2714
c64e311e 2715
c98e9dcf 2716 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2717 reg = FDI_RX_CTL(pipe);
2718 temp = I915_READ(reg);
627eb5a3
DV		 2719 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2720 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2721 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2722 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2723
2724 POSTING_READ(reg);
c98e9dcf
JB		 2725 udelay(200);
2726
2727 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2728 temp = I915_READ(reg);
2729 I915_WRITE(reg, temp | FDI_PCDCLK);
2730
2731 POSTING_READ(reg);
c98e9dcf
JB		 2732 udelay(200);
2733
20749730
PZ		 2734 /* Enable CPU FDI TX PLL, always on for Ironlake */
2735 reg = FDI_TX_CTL(pipe);
2736 temp = I915_READ(reg);
2737 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2738 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2739
20749730
PZ		 2740 POSTING_READ(reg);
2741 udelay(100);
6be4a607 2742 }
0e23b99d
JB		 2743}
2744
88cefb6c
DV		 2745static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2746{
2747 struct drm_device *dev = intel_crtc->base.dev;
2748 struct drm_i915_private *dev_priv = dev->dev_private;
2749 int pipe = intel_crtc->pipe;
2750 u32 reg, temp;
2751
2752 /* Switch from PCDclk to Rawclk */
2753 reg = FDI_RX_CTL(pipe);
2754 temp = I915_READ(reg);
2755 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2756
2757 /* Disable CPU FDI TX PLL */
2758 reg = FDI_TX_CTL(pipe);
2759 temp = I915_READ(reg);
2760 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2761
2762 POSTING_READ(reg);
2763 udelay(100);
2764
2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
2767 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2768
2769 /* Wait for the clocks to turn off. */
2770 POSTING_READ(reg);
2771 udelay(100);
2772}
2773
0fc932b8
JB		 2774static void ironlake_fdi_disable(struct drm_crtc *crtc)
2775{
2776 struct drm_device *dev = crtc->dev;
2777 struct drm_i915_private *dev_priv = dev->dev_private;
2778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2779 int pipe = intel_crtc->pipe;
2780 u32 reg, temp;
2781
2782 /* disable CPU FDI tx and PCH FDI rx */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2786 POSTING_READ(reg);
2787
2788 reg = FDI_RX_CTL(pipe);
2789 temp = I915_READ(reg);
2790 temp &= ~(0x7 << 16);
dfd07d72 2791 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2792 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2793
2794 POSTING_READ(reg);
2795 udelay(100);
2796
2797 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2798 if (HAS_PCH_IBX(dev)) {
2799 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2800 }
0fc932b8
JB		 2801
2802 /* still set train pattern 1 */
2803 reg = FDI_TX_CTL(pipe);
2804 temp = I915_READ(reg);
2805 temp &= ~FDI_LINK_TRAIN_NONE;
2806 temp |= FDI_LINK_TRAIN_PATTERN_1;
2807 I915_WRITE(reg, temp);
2808
2809 reg = FDI_RX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 if (HAS_PCH_CPT(dev)) {
2812 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2813 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2814 } else {
2815 temp &= ~FDI_LINK_TRAIN_NONE;
2816 temp |= FDI_LINK_TRAIN_PATTERN_1;
2817 }
2818 /* BPC in FDI rx is consistent with that in PIPECONF */
2819 temp &= ~(0x07 << 16);
dfd07d72 2820 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2821 I915_WRITE(reg, temp);
2822
2823 POSTING_READ(reg);
2824 udelay(100);
2825}
2826
5bb61643
CW		 2827static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2828{
2829 struct drm_device *dev = crtc->dev;
2830 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2832 unsigned long flags;
2833 bool pending;
2834
10d83730
VS		 2835 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2836 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2837 return false;
2838
2839 spin_lock_irqsave(&dev->event_lock, flags);
2840 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2841 spin_unlock_irqrestore(&dev->event_lock, flags);
2842
2843 return pending;
2844}
2845
e6c3a2a6
CW		 2846static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2847{
0f91128d 2848 struct drm_device *dev = crtc->dev;
5bb61643 2849 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2850
2851 if (crtc->fb == NULL)
2852 return;
2853
2c10d571
DV		 2854 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2855
5bb61643
CW		 2856 wait_event(dev_priv->pending_flip_queue,
2857 !intel_crtc_has_pending_flip(crtc));
2858
0f91128d
CW		 2859 mutex_lock(&dev->struct_mutex);
2860 intel_finish_fb(crtc->fb);
2861 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2862}
2863
e615efe4
ED		 2864/* Program iCLKIP clock to the desired frequency */
2865static void lpt_program_iclkip(struct drm_crtc *crtc)
2866{
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2870 u32 temp;
2871
09153000
DV		 2872 mutex_lock(&dev_priv->dpio_lock);
2873
e615efe4
ED		 2874 /* It is necessary to ungate the pixclk gate prior to programming
2875 * the divisors, and gate it back when it is done.
2876 */
2877 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2878
2879 /* Disable SSCCTL */
2880 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2881 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2882 SBI_SSCCTL_DISABLE,
2883 SBI_ICLK);
e615efe4
ED		 2884
2885 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2886 if (crtc->mode.clock == 20000) {
2887 auxdiv = 1;
2888 divsel = 0x41;
2889 phaseinc = 0x20;
2890 } else {
2891 /* The iCLK virtual clock root frequency is in MHz,
2892 * but the crtc->mode.clock in in KHz. To get the divisors,
2893 * it is necessary to divide one by another, so we
2894 * convert the virtual clock precision to KHz here for higher
2895 * precision.
2896 */
2897 u32 iclk_virtual_root_freq = 172800 * 1000;
2898 u32 iclk_pi_range = 64;
2899 u32 desired_divisor, msb_divisor_value, pi_value;
2900
2901 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2902 msb_divisor_value = desired_divisor / iclk_pi_range;
2903 pi_value = desired_divisor % iclk_pi_range;
2904
2905 auxdiv = 0;
2906 divsel = msb_divisor_value - 2;
2907 phaseinc = pi_value;
2908 }
2909
2910 /* This should not happen with any sane values */
2911 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2912 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2913 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2914 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2915
2916 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2917 crtc->mode.clock,
2918 auxdiv,
2919 divsel,
2920 phasedir,
2921 phaseinc);
2922
2923 /* Program SSCDIVINTPHASE6 */
988d6ee8 2924 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2925 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2926 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2927 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2928 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2929 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2930 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2931 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2932
2933 /* Program SSCAUXDIV */
988d6ee8 2934 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2935 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2936 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2937 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2938
2939 /* Enable modulator and associated divider */
988d6ee8 2940 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2941 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2942 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2943
2944 /* Wait for initialization time */
2945 udelay(24);
2946
2947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2948
2949 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2950}
2951
275f01b2
DV		 2952static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2953 enum pipe pch_transcoder)
2954{
2955 struct drm_device *dev = crtc->base.dev;
2956 struct drm_i915_private *dev_priv = dev->dev_private;
2957 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2958
2959 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2960 I915_READ(HTOTAL(cpu_transcoder)));
2961 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2962 I915_READ(HBLANK(cpu_transcoder)));
2963 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2964 I915_READ(HSYNC(cpu_transcoder)));
2965
2966 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2967 I915_READ(VTOTAL(cpu_transcoder)));
2968 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2969 I915_READ(VBLANK(cpu_transcoder)));
2970 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2971 I915_READ(VSYNC(cpu_transcoder)));
2972 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2973 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2974}
2975
f67a559d
JB		 2976/*
2977 * Enable PCH resources required for PCH ports:
2978 * - PCH PLLs
2979 * - FDI training & RX/TX
2980 * - update transcoder timings
2981 * - DP transcoding bits
2982 * - transcoder
2983 */
2984static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2985{
2986 struct drm_device *dev = crtc->dev;
2987 struct drm_i915_private *dev_priv = dev->dev_private;
2988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2989 int pipe = intel_crtc->pipe;
ee7b9f93 2990 u32 reg, temp;
2c07245f 2991
ab9412ba 2992 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2993
cd986abb
DV		 2994 /* Write the TU size bits before fdi link training, so that error
2995 * detection works. */
2996 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2997 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2998
c98e9dcf 2999 /* For PCH output, training FDI link */
674cf967 3000 dev_priv->display.fdi_link_train(crtc);
2c07245f 3001
3ad8a208
DV		 3002 /* We need to program the right clock selection before writing the pixel
3003 * mutliplier into the DPLL. */
303b81e0 3004 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3005 u32 sel;
4b645f14 3006
c98e9dcf 3007 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3008 temp |= TRANS_DPLL_ENABLE(pipe);
3009 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3010 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3011 temp |= sel;
3012 else
3013 temp &= ~sel;
c98e9dcf 3014 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3015 }
5eddb70b 3016
3ad8a208
DV		 3017 /* XXX: pch pll's can be enabled any time before we enable the PCH
3018 * transcoder, and we actually should do this to not upset any PCH
3019 * transcoder that already use the clock when we share it.
3020 *
3021 * Note that enable_shared_dpll tries to do the right thing, but
3022 * get_shared_dpll unconditionally resets the pll - we need that to have
3023 * the right LVDS enable sequence. */
3024 ironlake_enable_shared_dpll(intel_crtc);
3025
d9b6cb56
JB		 3026 /* set transcoder timing, panel must allow it */
3027 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3028 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3029
303b81e0 3030 intel_fdi_normal_train(crtc);
5e84e1a4 3031
c98e9dcf
JB		 3032 /* For PCH DP, enable TRANS_DP_CTL */
3033 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3034 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3035 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3036 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3037 reg = TRANS_DP_CTL(pipe);
3038 temp = I915_READ(reg);
3039 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3040 TRANS_DP_SYNC_MASK |
3041 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3042 temp |= (TRANS_DP_OUTPUT_ENABLE |
3043 TRANS_DP_ENH_FRAMING);
9325c9f0 3044 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3045
3046 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3047 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3048 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3049 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3050
3051 switch (intel_trans_dp_port_sel(crtc)) {
3052 case PCH_DP_B:
5eddb70b 3053 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3054 break;
3055 case PCH_DP_C:
5eddb70b 3056 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3057 break;
3058 case PCH_DP_D:
5eddb70b 3059 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3060 break;
3061 default:
e95d41e1 3062 BUG();
32f9d658 3063 }
2c07245f 3064
5eddb70b 3065 I915_WRITE(reg, temp);
6be4a607 3066 }
b52eb4dc 3067
b8a4f404 3068 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3069}
3070
1507e5bd
PZ		 3071static void lpt_pch_enable(struct drm_crtc *crtc)
3072{
3073 struct drm_device *dev = crtc->dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3076 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3077
ab9412ba 3078 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3079
8c52b5e8 3080 lpt_program_iclkip(crtc);
1507e5bd 3081
0540e488 3082 /* Set transcoder timing. */
275f01b2 3083 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3084
937bb610 3085 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3086}
3087
e2b78267 3088static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3089{
e2b78267 3090 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3091
3092 if (pll == NULL)
3093 return;
3094
3095 if (pll->refcount == 0) {
46edb027 3096 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3097 return;
3098 }
3099
f4a091c7
DV		 3100 if (--pll->refcount == 0) {
3101 WARN_ON(pll->on);
3102 WARN_ON(pll->active);
3103 }
3104
a43f6e0f 3105 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3106}
3107
b89a1d39 3108static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3109{
e2b78267
DV		 3110 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3111 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3112 enum intel_dpll_id i;
ee7b9f93 3113
ee7b9f93 3114 if (pll) {
46edb027
DV		 3115 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3116 crtc->base.base.id, pll->name);
e2b78267 3117 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3118 }
3119
98b6bd99
DV		 3120 if (HAS_PCH_IBX(dev_priv->dev)) {
3121 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3122 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3123 pll = &dev_priv->shared_dplls[i];
98b6bd99 3124
46edb027
DV		 3125 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3126 crtc->base.base.id, pll->name);
98b6bd99
DV		 3127
3128 goto found;
3129 }
3130
e72f9fbf
DV		 3131 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3132 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3133
3134 /* Only want to check enabled timings first */
3135 if (pll->refcount == 0)
3136 continue;
3137
b89a1d39
DV		 3138 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3139 sizeof(pll->hw_state)) == 0) {
46edb027 3140 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3141 crtc->base.base.id,
46edb027 3142 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3143
3144 goto found;
3145 }
3146 }
3147
3148 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3149 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3150 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3151 if (pll->refcount == 0) {
46edb027
DV		 3152 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3153 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3154 goto found;
3155 }
3156 }
3157
3158 return NULL;
3159
3160found:
a43f6e0f 3161 crtc->config.shared_dpll = i;
46edb027
DV		 3162 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3163 pipe_name(crtc->pipe));
ee7b9f93 3164
cdbd2316 3165 if (pll->active == 0) {
66e985c0
DV		 3166 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3167 sizeof(pll->hw_state));
3168
46edb027 3169 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3170 WARN_ON(pll->on);
e9d6944e 3171 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3172
15bdd4cf 3173 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3174 }
3175 pll->refcount++;
e04c7350 3176
ee7b9f93
JB		 3177 return pll;
3178}
3179
a1520318 3180static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3181{
3182 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3183 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3184 u32 temp;
3185
3186 temp = I915_READ(dslreg);
3187 udelay(500);
3188 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3189 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3190 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3191 }
3192}
3193
b074cec8
JB		 3194static void ironlake_pfit_enable(struct intel_crtc *crtc)
3195{
3196 struct drm_device *dev = crtc->base.dev;
3197 struct drm_i915_private *dev_priv = dev->dev_private;
3198 int pipe = crtc->pipe;
3199
0ef37f3f 3200 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3201 /* Force use of hard-coded filter coefficients
3202 * as some pre-programmed values are broken,
3203 * e.g. x201.
3204 */
3205 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3206 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3207 PF_PIPE_SEL_IVB(pipe));
3208 else
3209 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3210 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3211 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3212 }
3213}
3214
bb53d4ae
VS		 3215static void intel_enable_planes(struct drm_crtc *crtc)
3216{
3217 struct drm_device *dev = crtc->dev;
3218 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3219 struct intel_plane *intel_plane;
3220
3221 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3222 if (intel_plane->pipe == pipe)
3223 intel_plane_restore(&intel_plane->base);
3224}
3225
3226static void intel_disable_planes(struct drm_crtc *crtc)
3227{
3228 struct drm_device *dev = crtc->dev;
3229 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3230 struct intel_plane *intel_plane;
3231
3232 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3233 if (intel_plane->pipe == pipe)
3234 intel_plane_disable(&intel_plane->base);
3235}
3236
f67a559d
JB		 3237static void ironlake_crtc_enable(struct drm_crtc *crtc)
3238{
3239 struct drm_device *dev = crtc->dev;
3240 struct drm_i915_private *dev_priv = dev->dev_private;
3241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3242 struct intel_encoder *encoder;
f67a559d
JB		 3243 int pipe = intel_crtc->pipe;
3244 int plane = intel_crtc->plane;
f67a559d 3245
08a48469
DV		 3246 WARN_ON(!crtc->enabled);
3247
f67a559d
JB		 3248 if (intel_crtc->active)
3249 return;
3250
3251 intel_crtc->active = true;
8664281b
PZ		 3252
3253 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3254 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3255
f67a559d
JB		 3256 intel_update_watermarks(dev);
3257
f6736a1a 3258 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3259 if (encoder->pre_enable)
3260 encoder->pre_enable(encoder);
f67a559d 3261
5bfe2ac0 3262 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3263 /* Note: FDI PLL enabling _must_ be done before we enable the
3264 * cpu pipes, hence this is separate from all the other fdi/pch
3265 * enabling. */
88cefb6c 3266 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3267 } else {
3268 assert_fdi_tx_disabled(dev_priv, pipe);
3269 assert_fdi_rx_disabled(dev_priv, pipe);
3270 }
f67a559d 3271
b074cec8 3272 ironlake_pfit_enable(intel_crtc);
f67a559d 3273
9c54c0dd
JB		 3274 /*
3275 * On ILK+ LUT must be loaded before the pipe is running but with
3276 * clocks enabled
3277 */
3278 intel_crtc_load_lut(crtc);
3279
5bfe2ac0
DV		 3280 intel_enable_pipe(dev_priv, pipe,
3281 intel_crtc->config.has_pch_encoder);
f67a559d 3282 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3283 intel_enable_planes(crtc);
5c38d48c 3284 intel_crtc_update_cursor(crtc, true);
f67a559d 3285
5bfe2ac0 3286 if (intel_crtc->config.has_pch_encoder)
f67a559d 3287 ironlake_pch_enable(crtc);
c98e9dcf 3288
d1ebd816 3289 mutex_lock(&dev->struct_mutex);
bed4a673 3290 intel_update_fbc(dev);
d1ebd816
BW		 3291 mutex_unlock(&dev->struct_mutex);
3292
fa5c73b1
DV		 3293 for_each_encoder_on_crtc(dev, crtc, encoder)
3294 encoder->enable(encoder);
61b77ddd
DV		 3295
3296 if (HAS_PCH_CPT(dev))
a1520318 3297 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3298
3299 /*
3300 * There seems to be a race in PCH platform hw (at least on some
3301 * outputs) where an enabled pipe still completes any pageflip right
3302 * away (as if the pipe is off) instead of waiting for vblank. As soon
3303 * as the first vblank happend, everything works as expected. Hence just
3304 * wait for one vblank before returning to avoid strange things
3305 * happening.
3306 */
3307 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3308}
3309
42db64ef
PZ		 3310/* IPS only exists on ULT machines and is tied to pipe A. */
3311static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3312{
f5adf94e 3313 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3314}
3315
3316static void hsw_enable_ips(struct intel_crtc *crtc)
3317{
3318 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3319
3320 if (!crtc->config.ips_enabled)
3321 return;
3322
3323 /* We can only enable IPS after we enable a plane and wait for a vblank.
3324 * We guarantee that the plane is enabled by calling intel_enable_ips
3325 * only after intel_enable_plane. And intel_enable_plane already waits
3326 * for a vblank, so all we need to do here is to enable the IPS bit. */
3327 assert_plane_enabled(dev_priv, crtc->plane);
3328 I915_WRITE(IPS_CTL, IPS_ENABLE);
3329}
3330
3331static void hsw_disable_ips(struct intel_crtc *crtc)
3332{
3333 struct drm_device *dev = crtc->base.dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335
3336 if (!crtc->config.ips_enabled)
3337 return;
3338
3339 assert_plane_enabled(dev_priv, crtc->plane);
3340 I915_WRITE(IPS_CTL, 0);
3341
3342 /* We need to wait for a vblank before we can disable the plane. */
3343 intel_wait_for_vblank(dev, crtc->pipe);
3344}
3345
4f771f10
PZ		 3346static void haswell_crtc_enable(struct drm_crtc *crtc)
3347{
3348 struct drm_device *dev = crtc->dev;
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351 struct intel_encoder *encoder;
3352 int pipe = intel_crtc->pipe;
3353 int plane = intel_crtc->plane;
4f771f10
PZ		 3354
3355 WARN_ON(!crtc->enabled);
3356
3357 if (intel_crtc->active)
3358 return;
3359
3360 intel_crtc->active = true;
8664281b
PZ		 3361
3362 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3363 if (intel_crtc->config.has_pch_encoder)
3364 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3365
4f771f10
PZ		 3366 intel_update_watermarks(dev);
3367
5bfe2ac0 3368 if (intel_crtc->config.has_pch_encoder)
04945641 3369 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3370
3371 for_each_encoder_on_crtc(dev, crtc, encoder)
3372 if (encoder->pre_enable)
3373 encoder->pre_enable(encoder);
3374
1f544388 3375 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3376
b074cec8 3377 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3378
3379 /*
3380 * On ILK+ LUT must be loaded before the pipe is running but with
3381 * clocks enabled
3382 */
3383 intel_crtc_load_lut(crtc);
3384
1f544388 3385 intel_ddi_set_pipe_settings(crtc);
8228c251 3386 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3387
5bfe2ac0
DV		 3388 intel_enable_pipe(dev_priv, pipe,
3389 intel_crtc->config.has_pch_encoder);
4f771f10 3390 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3391 intel_enable_planes(crtc);
5c38d48c 3392 intel_crtc_update_cursor(crtc, true);
4f771f10 3393
42db64ef
PZ		 3394 hsw_enable_ips(intel_crtc);
3395
5bfe2ac0 3396 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3397 lpt_pch_enable(crtc);
4f771f10
PZ		 3398
3399 mutex_lock(&dev->struct_mutex);
3400 intel_update_fbc(dev);
3401 mutex_unlock(&dev->struct_mutex);
3402
4f771f10
PZ		 3403 for_each_encoder_on_crtc(dev, crtc, encoder)
3404 encoder->enable(encoder);
3405
4f771f10
PZ		 3406 /*
3407 * There seems to be a race in PCH platform hw (at least on some
3408 * outputs) where an enabled pipe still completes any pageflip right
3409 * away (as if the pipe is off) instead of waiting for vblank. As soon
3410 * as the first vblank happend, everything works as expected. Hence just
3411 * wait for one vblank before returning to avoid strange things
3412 * happening.
3413 */
3414 intel_wait_for_vblank(dev, intel_crtc->pipe);
3415}
3416
3f8dce3a
DV		 3417static void ironlake_pfit_disable(struct intel_crtc *crtc)
3418{
3419 struct drm_device *dev = crtc->base.dev;
3420 struct drm_i915_private *dev_priv = dev->dev_private;
3421 int pipe = crtc->pipe;
3422
3423 /* To avoid upsetting the power well on haswell only disable the pfit if
3424 * it's in use. The hw state code will make sure we get this right. */
3425 if (crtc->config.pch_pfit.size) {
3426 I915_WRITE(PF_CTL(pipe), 0);
3427 I915_WRITE(PF_WIN_POS(pipe), 0);
3428 I915_WRITE(PF_WIN_SZ(pipe), 0);
3429 }
3430}
3431
6be4a607
JB		 3432static void ironlake_crtc_disable(struct drm_crtc *crtc)
3433{
3434 struct drm_device *dev = crtc->dev;
3435 struct drm_i915_private *dev_priv = dev->dev_private;
3436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3437 struct intel_encoder *encoder;
6be4a607
JB		 3438 int pipe = intel_crtc->pipe;
3439 int plane = intel_crtc->plane;
5eddb70b 3440 u32 reg, temp;
b52eb4dc 3441
ef9c3aee 3442
f7abfe8b
CW		 3443 if (!intel_crtc->active)
3444 return;
3445
ea9d758d
DV		 3446 for_each_encoder_on_crtc(dev, crtc, encoder)
3447 encoder->disable(encoder);
3448
e6c3a2a6 3449 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3450 drm_vblank_off(dev, pipe);
913d8d11 3451
5c3fe8b0 3452 if (dev_priv->fbc.plane == plane)
973d04f9 3453 intel_disable_fbc(dev);
2c07245f 3454
0d5b8c61 3455 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3456 intel_disable_planes(crtc);
0d5b8c61
VS		 3457 intel_disable_plane(dev_priv, plane, pipe);
3458
d925c59a
DV		 3459 if (intel_crtc->config.has_pch_encoder)
3460 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3461
b24e7179 3462 intel_disable_pipe(dev_priv, pipe);
32f9d658 3463
3f8dce3a 3464 ironlake_pfit_disable(intel_crtc);
2c07245f 3465
bf49ec8c
DV		 3466 for_each_encoder_on_crtc(dev, crtc, encoder)
3467 if (encoder->post_disable)
3468 encoder->post_disable(encoder);
2c07245f 3469
d925c59a
DV		 3470 if (intel_crtc->config.has_pch_encoder) {
3471 ironlake_fdi_disable(crtc);
913d8d11 3472
d925c59a
DV		 3473 ironlake_disable_pch_transcoder(dev_priv, pipe);
3474 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3475
d925c59a
DV		 3476 if (HAS_PCH_CPT(dev)) {
3477 /* disable TRANS_DP_CTL */
3478 reg = TRANS_DP_CTL(pipe);
3479 temp = I915_READ(reg);
3480 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3481 TRANS_DP_PORT_SEL_MASK);
3482 temp |= TRANS_DP_PORT_SEL_NONE;
3483 I915_WRITE(reg, temp);
3484
3485 /* disable DPLL_SEL */
3486 temp = I915_READ(PCH_DPLL_SEL);
11887397 3487 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3488 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3489 }
e3421a18 3490
d925c59a 3491 /* disable PCH DPLL */
e72f9fbf 3492 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3493
d925c59a
DV		 3494 ironlake_fdi_pll_disable(intel_crtc);
3495 }
6b383a7f 3496
f7abfe8b 3497 intel_crtc->active = false;
6b383a7f 3498 intel_update_watermarks(dev);
d1ebd816
BW		 3499
3500 mutex_lock(&dev->struct_mutex);
6b383a7f 3501 intel_update_fbc(dev);
d1ebd816 3502 mutex_unlock(&dev->struct_mutex);
6be4a607 3503}
1b3c7a47 3504
4f771f10 3505static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3506{
4f771f10
PZ		 3507 struct drm_device *dev = crtc->dev;
3508 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3510 struct intel_encoder *encoder;
3511 int pipe = intel_crtc->pipe;
3512 int plane = intel_crtc->plane;
3b117c8f 3513 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3514
4f771f10
PZ		 3515 if (!intel_crtc->active)
3516 return;
3517
3518 for_each_encoder_on_crtc(dev, crtc, encoder)
3519 encoder->disable(encoder);
3520
3521 intel_crtc_wait_for_pending_flips(crtc);
3522 drm_vblank_off(dev, pipe);
4f771f10 3523
891348b2 3524 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3525 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3526 intel_disable_fbc(dev);
3527
42db64ef
PZ		 3528 hsw_disable_ips(intel_crtc);
3529
0d5b8c61 3530 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3531 intel_disable_planes(crtc);
891348b2
RV		 3532 intel_disable_plane(dev_priv, plane, pipe);
3533
8664281b
PZ		 3534 if (intel_crtc->config.has_pch_encoder)
3535 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3536 intel_disable_pipe(dev_priv, pipe);
3537
ad80a810 3538 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3539
3f8dce3a 3540 ironlake_pfit_disable(intel_crtc);
4f771f10 3541
1f544388 3542 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3543
3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3547
88adfff1 3548 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3549 lpt_disable_pch_transcoder(dev_priv);
8664281b 3550 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3551 intel_ddi_fdi_disable(crtc);
83616634 3552 }
4f771f10
PZ		 3553
3554 intel_crtc->active = false;
3555 intel_update_watermarks(dev);
3556
3557 mutex_lock(&dev->struct_mutex);
3558 intel_update_fbc(dev);
3559 mutex_unlock(&dev->struct_mutex);
3560}
3561
ee7b9f93
JB		 3562static void ironlake_crtc_off(struct drm_crtc *crtc)
3563{
3564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3565 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3566}
3567
6441ab5f
PZ		 3568static void haswell_crtc_off(struct drm_crtc *crtc)
3569{
3570 intel_ddi_put_crtc_pll(crtc);
3571}
3572
02e792fb
DV		 3573static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3574{
02e792fb 3575 if (!enable && intel_crtc->overlay) {
23f09ce3 3576 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3577 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3578
23f09ce3 3579 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3580 dev_priv->mm.interruptible = false;
3581 (void) intel_overlay_switch_off(intel_crtc->overlay);
3582 dev_priv->mm.interruptible = true;
23f09ce3 3583 mutex_unlock(&dev->struct_mutex);
02e792fb 3584 }
02e792fb 3585
5dcdbcb0
CW		 3586 /* Let userspace switch the overlay on again. In most cases userspace
3587 * has to recompute where to put it anyway.
3588 */
02e792fb
DV		 3589}
3590
61bc95c1
EE		 3591/**
3592 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3593 * cursor plane briefly if not already running after enabling the display
3594 * plane.
3595 * This workaround avoids occasional blank screens when self refresh is
3596 * enabled.
3597 */
3598static void
3599g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3600{
3601 u32 cntl = I915_READ(CURCNTR(pipe));
3602
3603 if ((cntl & CURSOR_MODE) == 0) {
3604 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3605
3606 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3607 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3608 intel_wait_for_vblank(dev_priv->dev, pipe);
3609 I915_WRITE(CURCNTR(pipe), cntl);
3610 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3611 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3612 }
3613}
3614
2dd24552
JB		 3615static void i9xx_pfit_enable(struct intel_crtc *crtc)
3616{
3617 struct drm_device *dev = crtc->base.dev;
3618 struct drm_i915_private *dev_priv = dev->dev_private;
3619 struct intel_crtc_config *pipe_config = &crtc->config;
3620
328d8e82 3621 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3622 return;
3623
2dd24552 3624 /*
c0b03411
DV		 3625 * The panel fitter should only be adjusted whilst the pipe is disabled,
3626 * according to register description and PRM.
2dd24552 3627 */
c0b03411
DV		 3628 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3629 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3630
b074cec8
JB		 3631 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3632 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3633
3634 /* Border color in case we don't scale up to the full screen. Black by
3635 * default, change to something else for debugging. */
3636 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3637}
3638
89b667f8
JB		 3639static void valleyview_crtc_enable(struct drm_crtc *crtc)
3640{
3641 struct drm_device *dev = crtc->dev;
3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644 struct intel_encoder *encoder;
3645 int pipe = intel_crtc->pipe;
3646 int plane = intel_crtc->plane;
3647
3648 WARN_ON(!crtc->enabled);
3649
3650 if (intel_crtc->active)
3651 return;
3652
3653 intel_crtc->active = true;
3654 intel_update_watermarks(dev);
3655
3656 mutex_lock(&dev_priv->dpio_lock);
3657
3658 for_each_encoder_on_crtc(dev, crtc, encoder)
3659 if (encoder->pre_pll_enable)
3660 encoder->pre_pll_enable(encoder);
3661
426115cf 3662 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3663
3664 for_each_encoder_on_crtc(dev, crtc, encoder)
3665 if (encoder->pre_enable)
3666 encoder->pre_enable(encoder);
3667
3668 /* VLV wants encoder enabling _before_ the pipe is up. */
3669 for_each_encoder_on_crtc(dev, crtc, encoder)
3670 encoder->enable(encoder);
3671
2dd24552
JB		 3672 i9xx_pfit_enable(intel_crtc);
3673
63cbb074
VS		 3674 intel_crtc_load_lut(crtc);
3675
89b667f8
JB		 3676 intel_enable_pipe(dev_priv, pipe, false);
3677 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3678 intel_enable_planes(crtc);
5c38d48c 3679 intel_crtc_update_cursor(crtc, true);
89b667f8 3680
89b667f8
JB		 3681 intel_update_fbc(dev);
3682
89b667f8
JB		 3683 mutex_unlock(&dev_priv->dpio_lock);
3684}
3685
0b8765c6 3686static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3687{
3688 struct drm_device *dev = crtc->dev;
79e53945
JB		 3689 struct drm_i915_private *dev_priv = dev->dev_private;
3690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3691 struct intel_encoder *encoder;
79e53945 3692 int pipe = intel_crtc->pipe;
80824003 3693 int plane = intel_crtc->plane;
79e53945 3694
08a48469
DV		 3695 WARN_ON(!crtc->enabled);
3696
f7abfe8b
CW		 3697 if (intel_crtc->active)
3698 return;
3699
3700 intel_crtc->active = true;
6b383a7f
CW		 3701 intel_update_watermarks(dev);
3702
9d6d9f19
MK		 3703 for_each_encoder_on_crtc(dev, crtc, encoder)
3704 if (encoder->pre_enable)
3705 encoder->pre_enable(encoder);
3706
f6736a1a
DV		 3707 i9xx_enable_pll(intel_crtc);
3708
2dd24552
JB		 3709 i9xx_pfit_enable(intel_crtc);
3710
63cbb074
VS		 3711 intel_crtc_load_lut(crtc);
3712
040484af 3713 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3714 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3715 intel_enable_planes(crtc);
22e407d7 3716 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3717 if (IS_G4X(dev))
3718 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3719 intel_crtc_update_cursor(crtc, true);
79e53945 3720
0b8765c6
JB		 3721 /* Give the overlay scaler a chance to enable if it's on this pipe */
3722 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3723
f440eb13 3724 intel_update_fbc(dev);
ef9c3aee 3725
fa5c73b1
DV		 3726 for_each_encoder_on_crtc(dev, crtc, encoder)
3727 encoder->enable(encoder);
0b8765c6 3728}
79e53945 3729
87476d63
DV		 3730static void i9xx_pfit_disable(struct intel_crtc *crtc)
3731{
3732 struct drm_device *dev = crtc->base.dev;
3733 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3734
328d8e82
DV		 3735 if (!crtc->config.gmch_pfit.control)
3736 return;
87476d63 3737
328d8e82 3738 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3739
328d8e82
DV		 3740 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3741 I915_READ(PFIT_CONTROL));
3742 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3743}
3744
0b8765c6
JB		 3745static void i9xx_crtc_disable(struct drm_crtc *crtc)
3746{
3747 struct drm_device *dev = crtc->dev;
3748 struct drm_i915_private *dev_priv = dev->dev_private;
3749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3750 struct intel_encoder *encoder;
0b8765c6
JB		 3751 int pipe = intel_crtc->pipe;
3752 int plane = intel_crtc->plane;
ef9c3aee 3753
f7abfe8b
CW		 3754 if (!intel_crtc->active)
3755 return;
3756
ea9d758d
DV		 3757 for_each_encoder_on_crtc(dev, crtc, encoder)
3758 encoder->disable(encoder);
3759
0b8765c6 3760 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3761 intel_crtc_wait_for_pending_flips(crtc);
3762 drm_vblank_off(dev, pipe);
0b8765c6 3763
5c3fe8b0 3764 if (dev_priv->fbc.plane == plane)
973d04f9 3765 intel_disable_fbc(dev);
79e53945 3766
0d5b8c61
VS		 3767 intel_crtc_dpms_overlay(intel_crtc, false);
3768 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3769 intel_disable_planes(crtc);
b24e7179 3770 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3771
b24e7179 3772 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3773
87476d63 3774 i9xx_pfit_disable(intel_crtc);
24a1f16d 3775
89b667f8
JB		 3776 for_each_encoder_on_crtc(dev, crtc, encoder)
3777 if (encoder->post_disable)
3778 encoder->post_disable(encoder);
3779
50b44a44 3780 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3781
f7abfe8b 3782 intel_crtc->active = false;
6b383a7f
CW		 3783 intel_update_fbc(dev);
3784 intel_update_watermarks(dev);
0b8765c6
JB		 3785}
3786
ee7b9f93
JB		 3787static void i9xx_crtc_off(struct drm_crtc *crtc)
3788{
3789}
3790
976f8a20
DV		 3791static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3792 bool enabled)
2c07245f
ZW		 3793{
3794 struct drm_device *dev = crtc->dev;
3795 struct drm_i915_master_private *master_priv;
3796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3797 int pipe = intel_crtc->pipe;
79e53945
JB		 3798
3799 if (!dev->primary->master)
3800 return;
3801
3802 master_priv = dev->primary->master->driver_priv;
3803 if (!master_priv->sarea_priv)
3804 return;
3805
79e53945
JB		 3806 switch (pipe) {
3807 case 0:
3808 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3809 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3810 break;
3811 case 1:
3812 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3813 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3814 break;
3815 default:
9db4a9c7 3816 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3817 break;
3818 }
79e53945
JB		 3819}
3820
976f8a20
DV		 3821/**
3822 * Sets the power management mode of the pipe and plane.
3823 */
3824void intel_crtc_update_dpms(struct drm_crtc *crtc)
3825{
3826 struct drm_device *dev = crtc->dev;
3827 struct drm_i915_private *dev_priv = dev->dev_private;
3828 struct intel_encoder *intel_encoder;
3829 bool enable = false;
3830
3831 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3832 enable |= intel_encoder->connectors_active;
3833
3834 if (enable)
3835 dev_priv->display.crtc_enable(crtc);
3836 else
3837 dev_priv->display.crtc_disable(crtc);
3838
3839 intel_crtc_update_sarea(crtc, enable);
3840}
3841
cdd59983
CW		 3842static void intel_crtc_disable(struct drm_crtc *crtc)
3843{
cdd59983 3844 struct drm_device *dev = crtc->dev;
976f8a20 3845 struct drm_connector *connector;
ee7b9f93 3846 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3848
976f8a20
DV		 3849 /* crtc should still be enabled when we disable it. */
3850 WARN_ON(!crtc->enabled);
3851
3852 dev_priv->display.crtc_disable(crtc);
c77bf565 3853 intel_crtc->eld_vld = false;
976f8a20 3854 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3855 dev_priv->display.off(crtc);
3856
931872fc
CW		 3857 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3858 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3859
3860 if (crtc->fb) {
3861 mutex_lock(&dev->struct_mutex);
1690e1eb 3862 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3863 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3864 crtc->fb = NULL;
3865 }
3866
3867 /* Update computed state. */
3868 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3869 if (!connector->encoder || !connector->encoder->crtc)
3870 continue;
3871
3872 if (connector->encoder->crtc != crtc)
3873 continue;
3874
3875 connector->dpms = DRM_MODE_DPMS_OFF;
3876 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3877 }
3878}
3879
a261b246 3880void intel_modeset_disable(struct drm_device *dev)
79e53945 3881{
a261b246
DV		 3882 struct drm_crtc *crtc;
3883
3884 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3885 if (crtc->enabled)
3886 intel_crtc_disable(crtc);
3887 }
79e53945
JB		 3888}
3889
ea5b213a 3890void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3891{
4ef69c7a 3892 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3893
ea5b213a
CW		 3894 drm_encoder_cleanup(encoder);
3895 kfree(intel_encoder);
7e7d76c3
JB		 3896}
3897
5ab432ef
DV		 3898/* Simple dpms helper for encodres with just one connector, no cloning and only
3899 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3900 * state of the entire output pipe. */
3901void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3902{
5ab432ef
DV		 3903 if (mode == DRM_MODE_DPMS_ON) {
3904 encoder->connectors_active = true;
3905
b2cabb0e 3906 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3907 } else {
3908 encoder->connectors_active = false;
3909
b2cabb0e 3910 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3911 }
79e53945
JB		 3912}
3913
0a91ca29
DV		 3914/* Cross check the actual hw state with our own modeset state tracking (and it's
3915 * internal consistency). */
b980514c 3916static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3917{
0a91ca29
DV		 3918 if (connector->get_hw_state(connector)) {
3919 struct intel_encoder *encoder = connector->encoder;
3920 struct drm_crtc *crtc;
3921 bool encoder_enabled;
3922 enum pipe pipe;
3923
3924 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3925 connector->base.base.id,
3926 drm_get_connector_name(&connector->base));
3927
3928 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3929 "wrong connector dpms state\n");
3930 WARN(connector->base.encoder != &encoder->base,
3931 "active connector not linked to encoder\n");
3932 WARN(!encoder->connectors_active,
3933 "encoder->connectors_active not set\n");
3934
3935 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3936 WARN(!encoder_enabled, "encoder not enabled\n");
3937 if (WARN_ON(!encoder->base.crtc))
3938 return;
3939
3940 crtc = encoder->base.crtc;
3941
3942 WARN(!crtc->enabled, "crtc not enabled\n");
3943 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3944 WARN(pipe != to_intel_crtc(crtc)->pipe,
3945 "encoder active on the wrong pipe\n");
3946 }
79e53945
JB		 3947}
3948
5ab432ef
DV		 3949/* Even simpler default implementation, if there's really no special case to
3950 * consider. */
3951void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3952{
5ab432ef 3953 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3954
5ab432ef
DV		 3955 /* All the simple cases only support two dpms states. */
3956 if (mode != DRM_MODE_DPMS_ON)
3957 mode = DRM_MODE_DPMS_OFF;
d4270e57 3958
5ab432ef
DV		 3959 if (mode == connector->dpms)
3960 return;
3961
3962 connector->dpms = mode;
3963
3964 /* Only need to change hw state when actually enabled */
3965 if (encoder->base.crtc)
3966 intel_encoder_dpms(encoder, mode);
3967 else
8af6cf88 3968 WARN_ON(encoder->connectors_active != false);
0a91ca29 3969
b980514c 3970 intel_modeset_check_state(connector->dev);
79e53945
JB		 3971}
3972
f0947c37
DV		 3973/* Simple connector->get_hw_state implementation for encoders that support only
3974 * one connector and no cloning and hence the encoder state determines the state
3975 * of the connector. */
3976bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3977{
24929352 3978 enum pipe pipe = 0;
f0947c37 3979 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3980
f0947c37 3981 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3982}
3983
1857e1da
DV		 3984static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3985 struct intel_crtc_config *pipe_config)
3986{
3987 struct drm_i915_private *dev_priv = dev->dev_private;
3988 struct intel_crtc *pipe_B_crtc =
3989 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3990
3991 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3992 pipe_name(pipe), pipe_config->fdi_lanes);
3993 if (pipe_config->fdi_lanes > 4) {
3994 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3995 pipe_name(pipe), pipe_config->fdi_lanes);
3996 return false;
3997 }
3998
3999 if (IS_HASWELL(dev)) {
4000 if (pipe_config->fdi_lanes > 2) {
4001 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4002 pipe_config->fdi_lanes);
4003 return false;
4004 } else {
4005 return true;
4006 }
4007 }
4008
4009 if (INTEL_INFO(dev)->num_pipes == 2)
4010 return true;
4011
4012 /* Ivybridge 3 pipe is really complicated */
4013 switch (pipe) {
4014 case PIPE_A:
4015 return true;
4016 case PIPE_B:
4017 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4018 pipe_config->fdi_lanes > 2) {
4019 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4020 pipe_name(pipe), pipe_config->fdi_lanes);
4021 return false;
4022 }
4023 return true;
4024 case PIPE_C:
1e833f40 4025 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4026 pipe_B_crtc->config.fdi_lanes <= 2) {
4027 if (pipe_config->fdi_lanes > 2) {
4028 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4029 pipe_name(pipe), pipe_config->fdi_lanes);
4030 return false;
4031 }
4032 } else {
4033 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4034 return false;
4035 }
4036 return true;
4037 default:
4038 BUG();
4039 }
4040}
4041
e29c22c0
DV		 4042#define RETRY 1
4043static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4044 struct intel_crtc_config *pipe_config)
877d48d5 4045{
1857e1da 4046 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4047 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4048 int lane, link_bw, fdi_dotclock;
e29c22c0 4049 bool setup_ok, needs_recompute = false;
877d48d5 4050
e29c22c0 4051retry:
877d48d5
DV		 4052 /* FDI is a binary signal running at ~2.7GHz, encoding
4053 * each output octet as 10 bits. The actual frequency
4054 * is stored as a divider into a 100MHz clock, and the
4055 * mode pixel clock is stored in units of 1KHz.
4056 * Hence the bw of each lane in terms of the mode signal
4057 * is:
4058 */
4059 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4060
ff9a6750 4061 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4062 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4063
2bd89a07 4064 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4065 pipe_config->pipe_bpp);
4066
4067 pipe_config->fdi_lanes = lane;
4068
2bd89a07 4069 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4070 link_bw, &pipe_config->fdi_m_n);
1857e1da 4071
e29c22c0
DV		 4072 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4073 intel_crtc->pipe, pipe_config);
4074 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4075 pipe_config->pipe_bpp -= 2*3;
4076 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4077 pipe_config->pipe_bpp);
4078 needs_recompute = true;
4079 pipe_config->bw_constrained = true;
4080
4081 goto retry;
4082 }
4083
4084 if (needs_recompute)
4085 return RETRY;
4086
4087 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4088}
4089
42db64ef
PZ		 4090static void hsw_compute_ips_config(struct intel_crtc *crtc,
4091 struct intel_crtc_config *pipe_config)
4092{
3c4ca58c
PZ		 4093 pipe_config->ips_enabled = i915_enable_ips &&
4094 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4095 pipe_config->pipe_bpp == 24;
4096}
4097
a43f6e0f 4098static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4099 struct intel_crtc_config *pipe_config)
79e53945 4100{
a43f6e0f 4101 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4102 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4103
bad720ff 4104 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4105 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4106 if (pipe_config->requested_mode.clock * 3
4107 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4108 return -EINVAL;
2c07245f 4109 }
89749350 4110
f9bef081
DV		 4111 /* All interlaced capable intel hw wants timings in frames. Note though
4112 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4113 * timings, so we need to be careful not to clobber these.*/
7ae89233 4114 if (!pipe_config->timings_set)
f9bef081 4115 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4116
8693a824
DL		 4117 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4118 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4119 */
4120 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4121 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4122 return -EINVAL;
44f46b42 4123
bd080ee5 4124 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4125 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4126 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4127 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4128 * for lvds. */
4129 pipe_config->pipe_bpp = 8*3;
4130 }
4131
f5adf94e 4132 if (HAS_IPS(dev))
a43f6e0f
DV		 4133 hsw_compute_ips_config(crtc, pipe_config);
4134
4135 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4136 * clock survives for now. */
4137 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4138 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4139
877d48d5 4140 if (pipe_config->has_pch_encoder)
a43f6e0f 4141 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4142
e29c22c0 4143 return 0;
79e53945
JB		 4144}
4145
25eb05fc
JB		 4146static int valleyview_get_display_clock_speed(struct drm_device *dev)
4147{
4148 return 400000; /* FIXME */
4149}
4150
e70236a8
JB		 4151static int i945_get_display_clock_speed(struct drm_device *dev)
4152{
4153 return 400000;
4154}
79e53945 4155
e70236a8 4156static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4157{
e70236a8
JB		 4158 return 333000;
4159}
79e53945 4160
e70236a8
JB		 4161static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4162{
4163 return 200000;
4164}
79e53945 4165
e70236a8
JB		 4166static int i915gm_get_display_clock_speed(struct drm_device *dev)
4167{
4168 u16 gcfgc = 0;
79e53945 4169
e70236a8
JB		 4170 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4171
4172 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4173 return 133000;
4174 else {
4175 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4176 case GC_DISPLAY_CLOCK_333_MHZ:
4177 return 333000;
4178 default:
4179 case GC_DISPLAY_CLOCK_190_200_MHZ:
4180 return 190000;
79e53945 4181 }
e70236a8
JB		 4182 }
4183}
4184
4185static int i865_get_display_clock_speed(struct drm_device *dev)
4186{
4187 return 266000;
4188}
4189
4190static int i855_get_display_clock_speed(struct drm_device *dev)
4191{
4192 u16 hpllcc = 0;
4193 /* Assume that the hardware is in the high speed state. This
4194 * should be the default.
4195 */
4196 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4197 case GC_CLOCK_133_200:
4198 case GC_CLOCK_100_200:
4199 return 200000;
4200 case GC_CLOCK_166_250:
4201 return 250000;
4202 case GC_CLOCK_100_133:
79e53945 4203 return 133000;
e70236a8 4204 }
79e53945 4205
e70236a8
JB		 4206 /* Shouldn't happen */
4207 return 0;
4208}
79e53945 4209
e70236a8
JB		 4210static int i830_get_display_clock_speed(struct drm_device *dev)
4211{
4212 return 133000;
79e53945
JB		 4213}
4214
2c07245f 4215static void
a65851af 4216intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4217{
a65851af
VS		 4218 while (*num > DATA_LINK_M_N_MASK ||
4219 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4220 *num >>= 1;
4221 *den >>= 1;
4222 }
4223}
4224
a65851af
VS		 4225static void compute_m_n(unsigned int m, unsigned int n,
4226 uint32_t *ret_m, uint32_t *ret_n)
4227{
4228 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4229 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4230 intel_reduce_m_n_ratio(ret_m, ret_n);
4231}
4232
e69d0bc1
DV		 4233void
4234intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4235 int pixel_clock, int link_clock,
4236 struct intel_link_m_n *m_n)
2c07245f 4237{
e69d0bc1 4238 m_n->tu = 64;
a65851af
VS		 4239
4240 compute_m_n(bits_per_pixel * pixel_clock,
4241 link_clock * nlanes * 8,
4242 &m_n->gmch_m, &m_n->gmch_n);
4243
4244 compute_m_n(pixel_clock, link_clock,
4245 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4246}
4247
a7615030
CW		 4248static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4249{
72bbe58c
KP		 4250 if (i915_panel_use_ssc >= 0)
4251 return i915_panel_use_ssc != 0;
41aa3448 4252 return dev_priv->vbt.lvds_use_ssc
435793df 4253 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4254}
4255
a0c4da24
JB		 4256static int vlv_get_refclk(struct drm_crtc *crtc)
4257{
4258 struct drm_device *dev = crtc->dev;
4259 struct drm_i915_private *dev_priv = dev->dev_private;
4260 int refclk = 27000; /* for DP & HDMI */
4261
4262 return 100000; /* only one validated so far */
4263
4264 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4265 refclk = 96000;
4266 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4267 if (intel_panel_use_ssc(dev_priv))
4268 refclk = 100000;
4269 else
4270 refclk = 96000;
4271 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4272 refclk = 100000;
4273 }
4274
4275 return refclk;
4276}
4277
c65d77d8
JB		 4278static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4279{
4280 struct drm_device *dev = crtc->dev;
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4282 int refclk;
4283
a0c4da24
JB		 4284 if (IS_VALLEYVIEW(dev)) {
4285 refclk = vlv_get_refclk(crtc);
4286 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4287 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4288 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4289 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4290 refclk / 1000);
4291 } else if (!IS_GEN2(dev)) {
4292 refclk = 96000;
4293 } else {
4294 refclk = 48000;
4295 }
4296
4297 return refclk;
4298}
4299
7429e9d4 4300static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4301{
7df00d7a 4302 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4303}
f47709a9 4304
7429e9d4
DV		 4305static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4306{
4307 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4308}
4309
f47709a9 4310static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4311 intel_clock_t *reduced_clock)
4312{
f47709a9 4313 struct drm_device *dev = crtc->base.dev;
a7516a05 4314 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4315 int pipe = crtc->pipe;
a7516a05
JB		 4316 u32 fp, fp2 = 0;
4317
4318 if (IS_PINEVIEW(dev)) {
7429e9d4 4319 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4320 if (reduced_clock)
7429e9d4 4321 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4322 } else {
7429e9d4 4323 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4324 if (reduced_clock)
7429e9d4 4325 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4326 }
4327
4328 I915_WRITE(FP0(pipe), fp);
8bcc2795 4329 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4330
f47709a9
DV		 4331 crtc->lowfreq_avail = false;
4332 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4333 reduced_clock && i915_powersave) {
4334 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4335 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4336 crtc->lowfreq_avail = true;
a7516a05
JB		 4337 } else {
4338 I915_WRITE(FP1(pipe), fp);
8bcc2795 4339 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4340 }
4341}
4342
89b667f8
JB		 4343static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4344{
4345 u32 reg_val;
4346
4347 /*
4348 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4349 * and set it to a reasonable value instead.
4350 */
ae99258f 4351 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4352 reg_val &= 0xffffff00;
4353 reg_val |= 0x00000030;
ae99258f 4354 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4355
ae99258f 4356 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4357 reg_val &= 0x8cffffff;
4358 reg_val = 0x8c000000;
ae99258f 4359 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4360
ae99258f 4361 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4362 reg_val &= 0xffffff00;
ae99258f 4363 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4364
ae99258f 4365 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4366 reg_val &= 0x00ffffff;
4367 reg_val |= 0xb0000000;
ae99258f 4368 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4369}
4370
b551842d
DV		 4371static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4372 struct intel_link_m_n *m_n)
4373{
4374 struct drm_device *dev = crtc->base.dev;
4375 struct drm_i915_private *dev_priv = dev->dev_private;
4376 int pipe = crtc->pipe;
4377
e3b95f1e
DV		 4378 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4379 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4380 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4381 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4382}
4383
4384static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4385 struct intel_link_m_n *m_n)
4386{
4387 struct drm_device *dev = crtc->base.dev;
4388 struct drm_i915_private *dev_priv = dev->dev_private;
4389 int pipe = crtc->pipe;
4390 enum transcoder transcoder = crtc->config.cpu_transcoder;
4391
4392 if (INTEL_INFO(dev)->gen >= 5) {
4393 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4394 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4395 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4396 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4397 } else {
e3b95f1e
DV		 4398 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4399 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4400 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4401 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4402 }
4403}
4404
03afc4a2
DV		 4405static void intel_dp_set_m_n(struct intel_crtc *crtc)
4406{
4407 if (crtc->config.has_pch_encoder)
4408 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4409 else
4410 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4411}
4412
f47709a9 4413static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4414{
f47709a9 4415 struct drm_device *dev = crtc->base.dev;
a0c4da24 4416 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4417 int pipe = crtc->pipe;
89b667f8 4418 u32 dpll, mdiv;
a0c4da24 4419 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4420 bool is_hdmi;
198a037f 4421 u32 coreclk, reg_val, dpll_md;
a0c4da24 4422
09153000
DV		 4423 mutex_lock(&dev_priv->dpio_lock);
4424
89b667f8 4425 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4426
f47709a9
DV		 4427 bestn = crtc->config.dpll.n;
4428 bestm1 = crtc->config.dpll.m1;
4429 bestm2 = crtc->config.dpll.m2;
4430 bestp1 = crtc->config.dpll.p1;
4431 bestp2 = crtc->config.dpll.p2;
a0c4da24 4432
89b667f8
JB		 4433 /* See eDP HDMI DPIO driver vbios notes doc */
4434
4435 /* PLL B needs special handling */
4436 if (pipe)
4437 vlv_pllb_recal_opamp(dev_priv);
4438
4439 /* Set up Tx target for periodic Rcomp update */
ae99258f 4440 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4441
4442 /* Disable target IRef on PLL */
ae99258f 4443 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4444 reg_val &= 0x00ffffff;
ae99258f 4445 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4446
4447 /* Disable fast lock */
ae99258f 4448 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4449
4450 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4451 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4452 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4453 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4454 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4455
4456 /*
4457 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4458 * but we don't support that).
4459 * Note: don't use the DAC post divider as it seems unstable.
4460 */
4461 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4462 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4463
a0c4da24 4464 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4465 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4466
89b667f8 4467 /* Set HBR and RBR LPF coefficients */
ff9a6750 4468 if (crtc->config.port_clock == 162000 ||
99750bd4 4469 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4470 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4471 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
885b0120 4472 0x009f0003);
89b667f8 4473 else
4abb2c39 4474 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4475 0x00d0000f);
4476
4477 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4478 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4479 /* Use SSC source */
4480 if (!pipe)
ae99258f 4481 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4482 0x0df40000);
4483 else
ae99258f 4484 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4485 0x0df70000);
4486 } else { /* HDMI or VGA */
4487 /* Use bend source */
4488 if (!pipe)
ae99258f 4489 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4490 0x0df70000);
4491 else
ae99258f 4492 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4493 0x0df40000);
4494 }
a0c4da24 4495
ae99258f 4496 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4497 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4498 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4499 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4500 coreclk |= 0x01000000;
ae99258f 4501 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4502
ae99258f 4503 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4504
89b667f8
JB		 4505 /* Enable DPIO clock input */
4506 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4507 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4508 if (pipe)
4509 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4510
4511 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4512 crtc->config.dpll_hw_state.dpll = dpll;
4513
ef1b460d
DV		 4514 dpll_md = (crtc->config.pixel_multiplier - 1)
4515 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4516 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4517
89b667f8
JB		 4518 if (crtc->config.has_dp_encoder)
4519 intel_dp_set_m_n(crtc);
09153000
DV		 4520
4521 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4522}
4523
f47709a9
DV		 4524static void i9xx_update_pll(struct intel_crtc *crtc,
4525 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4526 int num_connectors)
4527{
f47709a9 4528 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4529 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4530 u32 dpll;
4531 bool is_sdvo;
f47709a9 4532 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4533
f47709a9 4534 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4535
f47709a9
DV		 4536 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4537 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4538
4539 dpll = DPLL_VGA_MODE_DIS;
4540
f47709a9 4541 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4542 dpll |= DPLLB_MODE_LVDS;
4543 else
4544 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4545
ef1b460d 4546 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4547 dpll |= (crtc->config.pixel_multiplier - 1)
4548 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4549 }
198a037f
DV		 4550
4551 if (is_sdvo)
4a33e48d 4552 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4553
f47709a9 4554 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4555 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4556
4557 /* compute bitmask from p1 value */
4558 if (IS_PINEVIEW(dev))
4559 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4560 else {
4561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4562 if (IS_G4X(dev) && reduced_clock)
4563 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4564 }
4565 switch (clock->p2) {
4566 case 5:
4567 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4568 break;
4569 case 7:
4570 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4571 break;
4572 case 10:
4573 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4574 break;
4575 case 14:
4576 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4577 break;
4578 }
4579 if (INTEL_INFO(dev)->gen >= 4)
4580 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4581
09ede541 4582 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4583 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4584 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4585 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4586 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4587 else
4588 dpll |= PLL_REF_INPUT_DREFCLK;
4589
4590 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4591 crtc->config.dpll_hw_state.dpll = dpll;
4592
eb1cbe48 4593 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4594 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4595 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4596 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4597 }
66e3d5c0
DV		 4598
4599 if (crtc->config.has_dp_encoder)
4600 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4601}
4602
f47709a9 4603static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4604 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4605 int num_connectors)
4606{
f47709a9 4607 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4608 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4609 u32 dpll;
f47709a9 4610 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4611
f47709a9 4612 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4613
eb1cbe48
DV		 4614 dpll = DPLL_VGA_MODE_DIS;
4615
f47709a9 4616 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4617 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4618 } else {
4619 if (clock->p1 == 2)
4620 dpll |= PLL_P1_DIVIDE_BY_TWO;
4621 else
4622 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4623 if (clock->p2 == 4)
4624 dpll |= PLL_P2_DIVIDE_BY_4;
4625 }
4626
4a33e48d
DV		 4627 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4628 dpll |= DPLL_DVO_2X_MODE;
4629
f47709a9 4630 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4631 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4632 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4633 else
4634 dpll |= PLL_REF_INPUT_DREFCLK;
4635
4636 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4637 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4638}
4639
8a654f3b 4640static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4641{
4642 struct drm_device *dev = intel_crtc->base.dev;
4643 struct drm_i915_private *dev_priv = dev->dev_private;
4644 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4645 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4646 struct drm_display_mode *adjusted_mode =
4647 &intel_crtc->config.adjusted_mode;
4648 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4649 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4650
4651 /* We need to be careful not to changed the adjusted mode, for otherwise
4652 * the hw state checker will get angry at the mismatch. */
4653 crtc_vtotal = adjusted_mode->crtc_vtotal;
4654 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4655
4656 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4657 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4658 crtc_vtotal -= 1;
4659 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4660 vsyncshift = adjusted_mode->crtc_hsync_start
4661 - adjusted_mode->crtc_htotal / 2;
4662 } else {
4663 vsyncshift = 0;
4664 }
4665
4666 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4667 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4668
fe2b8f9d 4669 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4670 (adjusted_mode->crtc_hdisplay - 1) |
4671 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4672 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4673 (adjusted_mode->crtc_hblank_start - 1) |
4674 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4675 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4676 (adjusted_mode->crtc_hsync_start - 1) |
4677 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4678
fe2b8f9d 4679 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4680 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4681 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4682 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4683 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4684 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4685 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4686 (adjusted_mode->crtc_vsync_start - 1) |
4687 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4688
b5e508d4
PZ		 4689 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4690 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4691 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4692 * bits. */
4693 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4694 (pipe == PIPE_B || pipe == PIPE_C))
4695 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4696
b0e77b9c
PZ		 4697 /* pipesrc controls the size that is scaled from, which should
4698 * always be the user's requested size.
4699 */
4700 I915_WRITE(PIPESRC(pipe),
4701 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4702}
4703
1bd1bd80
DV		 4704static void intel_get_pipe_timings(struct intel_crtc *crtc,
4705 struct intel_crtc_config *pipe_config)
4706{
4707 struct drm_device *dev = crtc->base.dev;
4708 struct drm_i915_private *dev_priv = dev->dev_private;
4709 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4710 uint32_t tmp;
4711
4712 tmp = I915_READ(HTOTAL(cpu_transcoder));
4713 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4714 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4715 tmp = I915_READ(HBLANK(cpu_transcoder));
4716 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4717 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4718 tmp = I915_READ(HSYNC(cpu_transcoder));
4719 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4720 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4721
4722 tmp = I915_READ(VTOTAL(cpu_transcoder));
4723 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4724 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4725 tmp = I915_READ(VBLANK(cpu_transcoder));
4726 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4727 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4728 tmp = I915_READ(VSYNC(cpu_transcoder));
4729 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4730 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4731
4732 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4733 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4734 pipe_config->adjusted_mode.crtc_vtotal += 1;
4735 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4736 }
4737
4738 tmp = I915_READ(PIPESRC(crtc->pipe));
4739 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4740 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4741}
4742
babea61d
JB		 4743static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4744 struct intel_crtc_config *pipe_config)
4745{
4746 struct drm_crtc *crtc = &intel_crtc->base;
4747
4748 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4749 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4750 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4751 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4752
4753 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4754 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4755 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4756 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4757
4758 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4759
4760 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4761 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4762}
4763
84b046f3
DV		 4764static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4765{
4766 struct drm_device *dev = intel_crtc->base.dev;
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4768 uint32_t pipeconf;
4769
9f11a9e4 4770 pipeconf = 0;
84b046f3
DV		 4771
4772 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4773 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4774 * core speed.
4775 *
4776 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4777 * pipe == 0 check?
4778 */
4779 if (intel_crtc->config.requested_mode.clock >
4780 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4781 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4782 }
4783
ff9ce46e
DV		 4784 /* only g4x and later have fancy bpc/dither controls */
4785 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4786 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4787 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4788 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4789 PIPECONF_DITHER_TYPE_SP;
84b046f3 4790
ff9ce46e
DV		 4791 switch (intel_crtc->config.pipe_bpp) {
4792 case 18:
4793 pipeconf |= PIPECONF_6BPC;
4794 break;
4795 case 24:
4796 pipeconf |= PIPECONF_8BPC;
4797 break;
4798 case 30:
4799 pipeconf |= PIPECONF_10BPC;
4800 break;
4801 default:
4802 /* Case prevented by intel_choose_pipe_bpp_dither. */
4803 BUG();
84b046f3
DV		 4804 }
4805 }
4806
4807 if (HAS_PIPE_CXSR(dev)) {
4808 if (intel_crtc->lowfreq_avail) {
4809 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4810 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4811 } else {
4812 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4813 }
4814 }
4815
84b046f3
DV		 4816 if (!IS_GEN2(dev) &&
4817 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4818 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4819 else
4820 pipeconf |= PIPECONF_PROGRESSIVE;
4821
9f11a9e4
DV		 4822 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4823 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4824
84b046f3
DV		 4825 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4826 POSTING_READ(PIPECONF(intel_crtc->pipe));
4827}
4828
f564048e 4829static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4830 int x, int y,
94352cf9 4831 struct drm_framebuffer *fb)
79e53945
JB		 4832{
4833 struct drm_device *dev = crtc->dev;
4834 struct drm_i915_private *dev_priv = dev->dev_private;
4835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4836 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4837 int pipe = intel_crtc->pipe;
80824003 4838 int plane = intel_crtc->plane;
c751ce4f 4839 int refclk, num_connectors = 0;
652c393a 4840 intel_clock_t clock, reduced_clock;
84b046f3 4841 u32 dspcntr;
a16af721
DV		 4842 bool ok, has_reduced_clock = false;
4843 bool is_lvds = false;
5eddb70b 4844 struct intel_encoder *encoder;
d4906093 4845 const intel_limit_t *limit;
5c3b82e2 4846 int ret;
79e53945 4847
6c2b7c12 4848 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4849 switch (encoder->type) {
79e53945
JB		 4850 case INTEL_OUTPUT_LVDS:
4851 is_lvds = true;
4852 break;
79e53945 4853 }
43565a06 4854
c751ce4f 4855 num_connectors++;
79e53945
JB		 4856 }
4857
c65d77d8 4858 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4859
d4906093
ML		 4860 /*
4861 * Returns a set of divisors for the desired target clock with the given
4862 * refclk, or FALSE. The returned values represent the clock equation:
4863 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4864 */
1b894b59 4865 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4866 ok = dev_priv->display.find_dpll(limit, crtc,
4867 intel_crtc->config.port_clock,
ee9300bb
DV		 4868 refclk, NULL, &clock);
4869 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4870 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4871 return -EINVAL;
79e53945
JB		 4872 }
4873
cda4b7d3 4874 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4875 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4876
ddc9003c 4877 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4878 /*
4879 * Ensure we match the reduced clock's P to the target clock.
4880 * If the clocks don't match, we can't switch the display clock
4881 * by using the FP0/FP1. In such case we will disable the LVDS
4882 * downclock feature.
4883 */
ee9300bb
DV		 4884 has_reduced_clock =
4885 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4886 dev_priv->lvds_downclock,
ee9300bb 4887 refclk, &clock,
5eddb70b 4888 &reduced_clock);
7026d4ac 4889 }
f47709a9
DV		 4890 /* Compat-code for transition, will disappear. */
4891 if (!intel_crtc->config.clock_set) {
4892 intel_crtc->config.dpll.n = clock.n;
4893 intel_crtc->config.dpll.m1 = clock.m1;
4894 intel_crtc->config.dpll.m2 = clock.m2;
4895 intel_crtc->config.dpll.p1 = clock.p1;
4896 intel_crtc->config.dpll.p2 = clock.p2;
4897 }
7026d4ac 4898
eb1cbe48 4899 if (IS_GEN2(dev))
8a654f3b 4900 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4901 has_reduced_clock ? &reduced_clock : NULL,
4902 num_connectors);
a0c4da24 4903 else if (IS_VALLEYVIEW(dev))
f47709a9 4904 vlv_update_pll(intel_crtc);
79e53945 4905 else
f47709a9 4906 i9xx_update_pll(intel_crtc,
eb1cbe48 4907 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4908 num_connectors);
79e53945 4909
79e53945
JB		 4910 /* Set up the display plane register */
4911 dspcntr = DISPPLANE_GAMMA_ENABLE;
4912
da6ecc5d
JB		 4913 if (!IS_VALLEYVIEW(dev)) {
4914 if (pipe == 0)
4915 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4916 else
4917 dspcntr |= DISPPLANE_SEL_PIPE_B;
4918 }
79e53945 4919
8a654f3b 4920 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4921
4922 /* pipesrc and dspsize control the size that is scaled from,
4923 * which should always be the user's requested size.
79e53945 4924 */
929c77fb
EA		 4925 I915_WRITE(DSPSIZE(plane),
4926 ((mode->vdisplay - 1) << 16) |
4927 (mode->hdisplay - 1));
4928 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4929
84b046f3
DV		 4930 i9xx_set_pipeconf(intel_crtc);
4931
f564048e
EA		 4932 I915_WRITE(DSPCNTR(plane), dspcntr);
4933 POSTING_READ(DSPCNTR(plane));
4934
94352cf9 4935 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4936
4937 intel_update_watermarks(dev);
4938
f564048e
EA		 4939 return ret;
4940}
4941
2fa2fe9a
DV		 4942static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4943 struct intel_crtc_config *pipe_config)
4944{
4945 struct drm_device *dev = crtc->base.dev;
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947 uint32_t tmp;
4948
4949 tmp = I915_READ(PFIT_CONTROL);
4950
4951 if (INTEL_INFO(dev)->gen < 4) {
4952 if (crtc->pipe != PIPE_B)
4953 return;
4954
4955 /* gen2/3 store dither state in pfit control, needs to match */
4956 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4957 } else {
4958 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4959 return;
4960 }
4961
4962 if (!(tmp & PFIT_ENABLE))
4963 return;
4964
4965 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4966 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4967 if (INTEL_INFO(dev)->gen < 5)
4968 pipe_config->gmch_pfit.lvds_border_bits =
4969 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4970}
4971
0e8ffe1b
DV		 4972static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4973 struct intel_crtc_config *pipe_config)
4974{
4975 struct drm_device *dev = crtc->base.dev;
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 uint32_t tmp;
4978
e143a21c 4979 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 4980 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4981
0e8ffe1b
DV		 4982 tmp = I915_READ(PIPECONF(crtc->pipe));
4983 if (!(tmp & PIPECONF_ENABLE))
4984 return false;
4985
1bd1bd80
DV		 4986 intel_get_pipe_timings(crtc, pipe_config);
4987
2fa2fe9a
DV		 4988 i9xx_get_pfit_config(crtc, pipe_config);
4989
6c49f241
DV		 4990 if (INTEL_INFO(dev)->gen >= 4) {
4991 tmp = I915_READ(DPLL_MD(crtc->pipe));
4992 pipe_config->pixel_multiplier =
4993 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4994 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 4995 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 4996 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4997 tmp = I915_READ(DPLL(crtc->pipe));
4998 pipe_config->pixel_multiplier =
4999 ((tmp & SDVO_MULTIPLIER_MASK)
5000 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5001 } else {
5002 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5003 * port and will be fixed up in the encoder->get_config
5004 * function. */
5005 pipe_config->pixel_multiplier = 1;
5006 }
8bcc2795
DV		 5007 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5008 if (!IS_VALLEYVIEW(dev)) {
5009 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5010 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5011 } else {
5012 /* Mask out read-only status bits. */
5013 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5014 DPLL_PORTC_READY_MASK |
5015 DPLL_PORTB_READY_MASK);
8bcc2795 5016 }
6c49f241 5017
0e8ffe1b
DV		 5018 return true;
5019}
5020
dde86e2d 5021static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5022{
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5025 struct intel_encoder *encoder;
74cfd7ac 5026 u32 val, final;
13d83a67 5027 bool has_lvds = false;
199e5d79 5028 bool has_cpu_edp = false;
199e5d79 5029 bool has_panel = false;
99eb6a01
KP		 5030 bool has_ck505 = false;
5031 bool can_ssc = false;
13d83a67
JB		 5032
5033 /* We need to take the global config into account */
199e5d79
KP		 5034 list_for_each_entry(encoder, &mode_config->encoder_list,
5035 base.head) {
5036 switch (encoder->type) {
5037 case INTEL_OUTPUT_LVDS:
5038 has_panel = true;
5039 has_lvds = true;
5040 break;
5041 case INTEL_OUTPUT_EDP:
5042 has_panel = true;
2de6905f 5043 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5044 has_cpu_edp = true;
5045 break;
13d83a67
JB		 5046 }
5047 }
5048
99eb6a01 5049 if (HAS_PCH_IBX(dev)) {
41aa3448 5050 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5051 can_ssc = has_ck505;
5052 } else {
5053 has_ck505 = false;
5054 can_ssc = true;
5055 }
5056
2de6905f
ID		 5057 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5058 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5059
5060 /* Ironlake: try to setup display ref clock before DPLL
5061 * enabling. This is only under driver's control after
5062 * PCH B stepping, previous chipset stepping should be
5063 * ignoring this setting.
5064 */
74cfd7ac
CW		 5065 val = I915_READ(PCH_DREF_CONTROL);
5066
5067 /* As we must carefully and slowly disable/enable each source in turn,
5068 * compute the final state we want first and check if we need to
5069 * make any changes at all.
5070 */
5071 final = val;
5072 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5073 if (has_ck505)
5074 final |= DREF_NONSPREAD_CK505_ENABLE;
5075 else
5076 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5077
5078 final &= ~DREF_SSC_SOURCE_MASK;
5079 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5080 final &= ~DREF_SSC1_ENABLE;
5081
5082 if (has_panel) {
5083 final |= DREF_SSC_SOURCE_ENABLE;
5084
5085 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5086 final |= DREF_SSC1_ENABLE;
5087
5088 if (has_cpu_edp) {
5089 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5090 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5091 else
5092 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5093 } else
5094 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5095 } else {
5096 final |= DREF_SSC_SOURCE_DISABLE;
5097 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5098 }
5099
5100 if (final == val)
5101 return;
5102
13d83a67 5103 /* Always enable nonspread source */
74cfd7ac 5104 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5105
99eb6a01 5106 if (has_ck505)
74cfd7ac 5107 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5108 else
74cfd7ac 5109 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5110
199e5d79 5111 if (has_panel) {
74cfd7ac
CW		 5112 val &= ~DREF_SSC_SOURCE_MASK;
5113 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5114
199e5d79 5115 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5116 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5117 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5118 val |= DREF_SSC1_ENABLE;
e77166b5 5119 } else
74cfd7ac 5120 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5121
5122 /* Get SSC going before enabling the outputs */
74cfd7ac 5123 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5124 POSTING_READ(PCH_DREF_CONTROL);
5125 udelay(200);
5126
74cfd7ac 5127 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5128
5129 /* Enable CPU source on CPU attached eDP */
199e5d79 5130 if (has_cpu_edp) {
99eb6a01 5131 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5132 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5133 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5134 }
13d83a67 5135 else
74cfd7ac 5136 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5137 } else
74cfd7ac 5138 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5139
74cfd7ac 5140 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5141 POSTING_READ(PCH_DREF_CONTROL);
5142 udelay(200);
5143 } else {
5144 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5145
74cfd7ac 5146 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5147
5148 /* Turn off CPU output */
74cfd7ac 5149 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5150
74cfd7ac 5151 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5152 POSTING_READ(PCH_DREF_CONTROL);
5153 udelay(200);
5154
5155 /* Turn off the SSC source */
74cfd7ac
CW		 5156 val &= ~DREF_SSC_SOURCE_MASK;
5157 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5158
5159 /* Turn off SSC1 */
74cfd7ac 5160 val &= ~DREF_SSC1_ENABLE;
199e5d79 5161
74cfd7ac 5162 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5163 POSTING_READ(PCH_DREF_CONTROL);
5164 udelay(200);
5165 }
74cfd7ac
CW		 5166
5167 BUG_ON(val != final);
13d83a67
JB		 5168}
5169
f31f2d55 5170static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5171{
f31f2d55 5172 uint32_t tmp;
dde86e2d 5173
0ff066a9
PZ		 5174 tmp = I915_READ(SOUTH_CHICKEN2);
5175 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5176 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5177
0ff066a9
PZ		 5178 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5179 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5180 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5181
0ff066a9
PZ		 5182 tmp = I915_READ(SOUTH_CHICKEN2);
5183 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5184 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5185
0ff066a9
PZ		 5186 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5187 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5188 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5189}
5190
5191/* WaMPhyProgramming:hsw */
5192static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5193{
5194 uint32_t tmp;
dde86e2d
PZ		 5195
5196 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5197 tmp &= ~(0xFF << 24);
5198 tmp |= (0x12 << 24);
5199 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5200
dde86e2d
PZ		 5201 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5202 tmp |= (1 << 11);
5203 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5204
5205 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5206 tmp |= (1 << 11);
5207 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5208
dde86e2d
PZ		 5209 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5210 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5211 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5212
5213 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5214 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5215 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5216
0ff066a9
PZ		 5217 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5218 tmp &= ~(7 << 13);
5219 tmp |= (5 << 13);
5220 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5221
0ff066a9
PZ		 5222 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5223 tmp &= ~(7 << 13);
5224 tmp |= (5 << 13);
5225 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5226
5227 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5228 tmp &= ~0xFF;
5229 tmp |= 0x1C;
5230 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5231
5232 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5233 tmp &= ~0xFF;
5234 tmp |= 0x1C;
5235 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5236
5237 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5238 tmp &= ~(0xFF << 16);
5239 tmp |= (0x1C << 16);
5240 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5241
5242 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5243 tmp &= ~(0xFF << 16);
5244 tmp |= (0x1C << 16);
5245 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5246
0ff066a9
PZ		 5247 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5248 tmp |= (1 << 27);
5249 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5250
0ff066a9
PZ		 5251 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5252 tmp |= (1 << 27);
5253 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5254
0ff066a9
PZ		 5255 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5256 tmp &= ~(0xF << 28);
5257 tmp |= (4 << 28);
5258 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5259
0ff066a9
PZ		 5260 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5261 tmp &= ~(0xF << 28);
5262 tmp |= (4 << 28);
5263 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5264}
5265
2fa86a1f
PZ		 5266/* Implements 3 different sequences from BSpec chapter "Display iCLK
5267 * Programming" based on the parameters passed:
5268 * - Sequence to enable CLKOUT_DP
5269 * - Sequence to enable CLKOUT_DP without spread
5270 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5271 */
5272static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5273 bool with_fdi)
f31f2d55
PZ		 5274{
5275 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5276 uint32_t reg, tmp;
5277
5278 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5279 with_spread = true;
5280 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5281 with_fdi, "LP PCH doesn't have FDI\n"))
5282 with_fdi = false;
f31f2d55
PZ		 5283
5284 mutex_lock(&dev_priv->dpio_lock);
5285
5286 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5287 tmp &= ~SBI_SSCCTL_DISABLE;
5288 tmp |= SBI_SSCCTL_PATHALT;
5289 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5290
5291 udelay(24);
5292
2fa86a1f
PZ		 5293 if (with_spread) {
5294 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5295 tmp &= ~SBI_SSCCTL_PATHALT;
5296 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5297
2fa86a1f
PZ		 5298 if (with_fdi) {
5299 lpt_reset_fdi_mphy(dev_priv);
5300 lpt_program_fdi_mphy(dev_priv);
5301 }
5302 }
dde86e2d 5303
2fa86a1f
PZ		 5304 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5305 SBI_GEN0 : SBI_DBUFF0;
5306 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5307 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5308 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5309
5310 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5311}
5312
47701c3b
PZ		 5313/* Sequence to disable CLKOUT_DP */
5314static void lpt_disable_clkout_dp(struct drm_device *dev)
5315{
5316 struct drm_i915_private *dev_priv = dev->dev_private;
5317 uint32_t reg, tmp;
5318
5319 mutex_lock(&dev_priv->dpio_lock);
5320
5321 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5322 SBI_GEN0 : SBI_DBUFF0;
5323 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5324 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5325 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5326
5327 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5328 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5329 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5330 tmp |= SBI_SSCCTL_PATHALT;
5331 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5332 udelay(32);
5333 }
5334 tmp |= SBI_SSCCTL_DISABLE;
5335 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5336 }
5337
5338 mutex_unlock(&dev_priv->dpio_lock);
5339}
5340
bf8fa3d3
PZ		 5341static void lpt_init_pch_refclk(struct drm_device *dev)
5342{
5343 struct drm_mode_config *mode_config = &dev->mode_config;
5344 struct intel_encoder *encoder;
5345 bool has_vga = false;
5346
5347 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5348 switch (encoder->type) {
5349 case INTEL_OUTPUT_ANALOG:
5350 has_vga = true;
5351 break;
5352 }
5353 }
5354
47701c3b
PZ		 5355 if (has_vga)
5356 lpt_enable_clkout_dp(dev, true, true);
5357 else
5358 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5359}
5360
dde86e2d
PZ		 5361/*
5362 * Initialize reference clocks when the driver loads
5363 */
5364void intel_init_pch_refclk(struct drm_device *dev)
5365{
5366 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5367 ironlake_init_pch_refclk(dev);
5368 else if (HAS_PCH_LPT(dev))
5369 lpt_init_pch_refclk(dev);
5370}
5371
d9d444cb
JB		 5372static int ironlake_get_refclk(struct drm_crtc *crtc)
5373{
5374 struct drm_device *dev = crtc->dev;
5375 struct drm_i915_private *dev_priv = dev->dev_private;
5376 struct intel_encoder *encoder;
d9d444cb
JB		 5377 int num_connectors = 0;
5378 bool is_lvds = false;
5379
6c2b7c12 5380 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5381 switch (encoder->type) {
5382 case INTEL_OUTPUT_LVDS:
5383 is_lvds = true;
5384 break;
d9d444cb
JB		 5385 }
5386 num_connectors++;
5387 }
5388
5389 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5390 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5391 dev_priv->vbt.lvds_ssc_freq);
5392 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5393 }
5394
5395 return 120000;
5396}
5397
6ff93609 5398static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5399{
c8203565 5400 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5402 int pipe = intel_crtc->pipe;
c8203565
PZ		 5403 uint32_t val;
5404
78114071 5405 val = 0;
c8203565 5406
965e0c48 5407 switch (intel_crtc->config.pipe_bpp) {
c8203565 5408 case 18:
dfd07d72 5409 val |= PIPECONF_6BPC;
c8203565
PZ		 5410 break;
5411 case 24:
dfd07d72 5412 val |= PIPECONF_8BPC;
c8203565
PZ		 5413 break;
5414 case 30:
dfd07d72 5415 val |= PIPECONF_10BPC;
c8203565
PZ		 5416 break;
5417 case 36:
dfd07d72 5418 val |= PIPECONF_12BPC;
c8203565
PZ		 5419 break;
5420 default:
cc769b62
PZ		 5421 /* Case prevented by intel_choose_pipe_bpp_dither. */
5422 BUG();
c8203565
PZ		 5423 }
5424
d8b32247 5425 if (intel_crtc->config.dither)
c8203565
PZ		 5426 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5427
6ff93609 5428 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5429 val |= PIPECONF_INTERLACED_ILK;
5430 else
5431 val |= PIPECONF_PROGRESSIVE;
5432
50f3b016 5433 if (intel_crtc->config.limited_color_range)
3685a8f3 5434 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5435
c8203565
PZ		 5436 I915_WRITE(PIPECONF(pipe), val);
5437 POSTING_READ(PIPECONF(pipe));
5438}
5439
86d3efce
VS		 5440/*
5441 * Set up the pipe CSC unit.
5442 *
5443 * Currently only full range RGB to limited range RGB conversion
5444 * is supported, but eventually this should handle various
5445 * RGB<->YCbCr scenarios as well.
5446 */
50f3b016 5447static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5448{
5449 struct drm_device *dev = crtc->dev;
5450 struct drm_i915_private *dev_priv = dev->dev_private;
5451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5452 int pipe = intel_crtc->pipe;
5453 uint16_t coeff = 0x7800; /* 1.0 */
5454
5455 /*
5456 * TODO: Check what kind of values actually come out of the pipe
5457 * with these coeff/postoff values and adjust to get the best
5458 * accuracy. Perhaps we even need to take the bpc value into
5459 * consideration.
5460 */
5461
50f3b016 5462 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5463 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5464
5465 /*
5466 * GY/GU and RY/RU should be the other way around according
5467 * to BSpec, but reality doesn't agree. Just set them up in
5468 * a way that results in the correct picture.
5469 */
5470 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5471 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5472
5473 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5474 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5475
5476 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5477 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5478
5479 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5480 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5481 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5482
5483 if (INTEL_INFO(dev)->gen > 6) {
5484 uint16_t postoff = 0;
5485
50f3b016 5486 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5487 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5488
5489 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5490 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5491 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5492
5493 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5494 } else {
5495 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5496
50f3b016 5497 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5498 mode |= CSC_BLACK_SCREEN_OFFSET;
5499
5500 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5501 }
5502}
5503
6ff93609 5504static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5505{
5506 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5508 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5509 uint32_t val;
5510
3eff4faa 5511 val = 0;
ee2b0b38 5512
d8b32247 5513 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5514 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5515
6ff93609 5516 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5517 val |= PIPECONF_INTERLACED_ILK;
5518 else
5519 val |= PIPECONF_PROGRESSIVE;
5520
702e7a56
PZ		 5521 I915_WRITE(PIPECONF(cpu_transcoder), val);
5522 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5523
5524 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5525 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5526}
5527
6591c6e4 5528static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5529 intel_clock_t *clock,
5530 bool *has_reduced_clock,
5531 intel_clock_t *reduced_clock)
5532{
5533 struct drm_device *dev = crtc->dev;
5534 struct drm_i915_private *dev_priv = dev->dev_private;
5535 struct intel_encoder *intel_encoder;
5536 int refclk;
d4906093 5537 const intel_limit_t *limit;
a16af721 5538 bool ret, is_lvds = false;
79e53945 5539
6591c6e4
PZ		 5540 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5541 switch (intel_encoder->type) {
79e53945
JB		 5542 case INTEL_OUTPUT_LVDS:
5543 is_lvds = true;
5544 break;
79e53945
JB		 5545 }
5546 }
5547
d9d444cb 5548 refclk = ironlake_get_refclk(crtc);
79e53945 5549
d4906093
ML		 5550 /*
5551 * Returns a set of divisors for the desired target clock with the given
5552 * refclk, or FALSE. The returned values represent the clock equation:
5553 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5554 */
1b894b59 5555 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5556 ret = dev_priv->display.find_dpll(limit, crtc,
5557 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5558 refclk, NULL, clock);
6591c6e4
PZ		 5559 if (!ret)
5560 return false;
cda4b7d3 5561
ddc9003c 5562 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5563 /*
5564 * Ensure we match the reduced clock's P to the target clock.
5565 * If the clocks don't match, we can't switch the display clock
5566 * by using the FP0/FP1. In such case we will disable the LVDS
5567 * downclock feature.
5568 */
ee9300bb
DV		 5569 *has_reduced_clock =
5570 dev_priv->display.find_dpll(limit, crtc,
5571 dev_priv->lvds_downclock,
5572 refclk, clock,
5573 reduced_clock);
652c393a 5574 }
61e9653f 5575
6591c6e4
PZ		 5576 return true;
5577}
5578
01a415fd
DV		 5579static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5580{
5581 struct drm_i915_private *dev_priv = dev->dev_private;
5582 uint32_t temp;
5583
5584 temp = I915_READ(SOUTH_CHICKEN1);
5585 if (temp & FDI_BC_BIFURCATION_SELECT)
5586 return;
5587
5588 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5589 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5590
5591 temp |= FDI_BC_BIFURCATION_SELECT;
5592 DRM_DEBUG_KMS("enabling fdi C rx\n");
5593 I915_WRITE(SOUTH_CHICKEN1, temp);
5594 POSTING_READ(SOUTH_CHICKEN1);
5595}
5596
ebfd86fd 5597static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5598{
5599 struct drm_device *dev = intel_crtc->base.dev;
5600 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5601
5602 switch (intel_crtc->pipe) {
5603 case PIPE_A:
ebfd86fd 5604 break;
01a415fd 5605 case PIPE_B:
ebfd86fd 5606 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5607 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5608 else
5609 cpt_enable_fdi_bc_bifurcation(dev);
5610
ebfd86fd 5611 break;
01a415fd 5612 case PIPE_C:
01a415fd
DV		 5613 cpt_enable_fdi_bc_bifurcation(dev);
5614
ebfd86fd 5615 break;
01a415fd
DV		 5616 default:
5617 BUG();
5618 }
5619}
5620
d4b1931c
PZ		 5621int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5622{
5623 /*
5624 * Account for spread spectrum to avoid
5625 * oversubscribing the link. Max center spread
5626 * is 2.5%; use 5% for safety's sake.
5627 */
5628 u32 bps = target_clock * bpp * 21 / 20;
5629 return bps / (link_bw * 8) + 1;
5630}
5631
7429e9d4 5632static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5633{
7429e9d4 5634 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5635}
5636
de13a2e3 5637static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5638 u32 *fp,
9a7c7890 5639 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5640{
de13a2e3 5641 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5642 struct drm_device *dev = crtc->dev;
5643 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5644 struct intel_encoder *intel_encoder;
5645 uint32_t dpll;
6cc5f341 5646 int factor, num_connectors = 0;
09ede541 5647 bool is_lvds = false, is_sdvo = false;
79e53945 5648
de13a2e3
PZ		 5649 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5650 switch (intel_encoder->type) {
79e53945
JB		 5651 case INTEL_OUTPUT_LVDS:
5652 is_lvds = true;
5653 break;
5654 case INTEL_OUTPUT_SDVO:
7d57382e 5655 case INTEL_OUTPUT_HDMI:
79e53945 5656 is_sdvo = true;
79e53945 5657 break;
79e53945 5658 }
43565a06 5659
c751ce4f 5660 num_connectors++;
79e53945 5661 }
79e53945 5662
c1858123 5663 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5664 factor = 21;
5665 if (is_lvds) {
5666 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5667 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5668 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5669 factor = 25;
09ede541 5670 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5671 factor = 20;
c1858123 5672
7429e9d4 5673 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5674 *fp |= FP_CB_TUNE;
2c07245f 5675
9a7c7890
DV		 5676 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5677 *fp2 |= FP_CB_TUNE;
5678
5eddb70b 5679 dpll = 0;
2c07245f 5680
a07d6787
EA		 5681 if (is_lvds)
5682 dpll |= DPLLB_MODE_LVDS;
5683 else
5684 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5685
ef1b460d
DV		 5686 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5687 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5688
5689 if (is_sdvo)
4a33e48d 5690 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5691 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5692 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5693
a07d6787 5694 /* compute bitmask from p1 value */
7429e9d4 5695 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5696 /* also FPA1 */
7429e9d4 5697 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5698
7429e9d4 5699 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5700 case 5:
5701 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5702 break;
5703 case 7:
5704 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5705 break;
5706 case 10:
5707 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5708 break;
5709 case 14:
5710 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5711 break;
79e53945
JB		 5712 }
5713
b4c09f3b 5714 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5715 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5716 else
5717 dpll |= PLL_REF_INPUT_DREFCLK;
5718
959e16d6 5719 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5720}
5721
5722static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5723 int x, int y,
5724 struct drm_framebuffer *fb)
5725{
5726 struct drm_device *dev = crtc->dev;
5727 struct drm_i915_private *dev_priv = dev->dev_private;
5728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5729 int pipe = intel_crtc->pipe;
5730 int plane = intel_crtc->plane;
5731 int num_connectors = 0;
5732 intel_clock_t clock, reduced_clock;
cbbab5bd 5733 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5734 bool ok, has_reduced_clock = false;
8b47047b 5735 bool is_lvds = false;
de13a2e3 5736 struct intel_encoder *encoder;
e2b78267 5737 struct intel_shared_dpll *pll;
de13a2e3 5738 int ret;
de13a2e3
PZ		 5739
5740 for_each_encoder_on_crtc(dev, crtc, encoder) {
5741 switch (encoder->type) {
5742 case INTEL_OUTPUT_LVDS:
5743 is_lvds = true;
5744 break;
de13a2e3
PZ		 5745 }
5746
5747 num_connectors++;
a07d6787 5748 }
79e53945 5749
5dc5298b
PZ		 5750 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5751 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5752
ff9a6750 5753 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5754 &has_reduced_clock, &reduced_clock);
ee9300bb 5755 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5756 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5757 return -EINVAL;
79e53945 5758 }
f47709a9
DV		 5759 /* Compat-code for transition, will disappear. */
5760 if (!intel_crtc->config.clock_set) {
5761 intel_crtc->config.dpll.n = clock.n;
5762 intel_crtc->config.dpll.m1 = clock.m1;
5763 intel_crtc->config.dpll.m2 = clock.m2;
5764 intel_crtc->config.dpll.p1 = clock.p1;
5765 intel_crtc->config.dpll.p2 = clock.p2;
5766 }
79e53945 5767
de13a2e3
PZ		 5768 /* Ensure that the cursor is valid for the new mode before changing... */
5769 intel_crtc_update_cursor(crtc, true);
5770
5dc5298b 5771 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5772 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5773 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5774 if (has_reduced_clock)
7429e9d4 5775 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5776
7429e9d4 5777 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5778 &fp, &reduced_clock,
5779 has_reduced_clock ? &fp2 : NULL);
5780
959e16d6 5781 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5782 intel_crtc->config.dpll_hw_state.fp0 = fp;
5783 if (has_reduced_clock)
5784 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5785 else
5786 intel_crtc->config.dpll_hw_state.fp1 = fp;
5787
b89a1d39 5788 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5789 if (pll == NULL) {
84f44ce7
VS		 5790 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5791 pipe_name(pipe));
4b645f14
JB		 5792 return -EINVAL;
5793 }
ee7b9f93 5794 } else
e72f9fbf 5795 intel_put_shared_dpll(intel_crtc);
79e53945 5796
03afc4a2
DV		 5797 if (intel_crtc->config.has_dp_encoder)
5798 intel_dp_set_m_n(intel_crtc);
79e53945 5799
bcd644e0
DV		 5800 if (is_lvds && has_reduced_clock && i915_powersave)
5801 intel_crtc->lowfreq_avail = true;
5802 else
5803 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5804
5805 if (intel_crtc->config.has_pch_encoder) {
5806 pll = intel_crtc_to_shared_dpll(intel_crtc);
5807
652c393a
JB		 5808 }
5809
8a654f3b 5810 intel_set_pipe_timings(intel_crtc);
5eddb70b 5811
ca3a0ff8 5812 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5813 intel_cpu_transcoder_set_m_n(intel_crtc,
5814 &intel_crtc->config.fdi_m_n);
5815 }
2c07245f 5816
ebfd86fd
DV		 5817 if (IS_IVYBRIDGE(dev))
5818 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5819
6ff93609 5820 ironlake_set_pipeconf(crtc);
79e53945 5821
a1f9e77e
PZ		 5822 /* Set up the display plane register */
5823 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5824 POSTING_READ(DSPCNTR(plane));
79e53945 5825
94352cf9 5826 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5827
5828 intel_update_watermarks(dev);
5829
1857e1da 5830 return ret;
79e53945
JB		 5831}
5832
72419203
DV		 5833static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5834 struct intel_crtc_config *pipe_config)
5835{
5836 struct drm_device *dev = crtc->base.dev;
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838 enum transcoder transcoder = pipe_config->cpu_transcoder;
5839
5840 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5841 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5842 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5843 & ~TU_SIZE_MASK;
5844 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5845 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5846 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5847}
5848
2fa2fe9a
DV		 5849static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5850 struct intel_crtc_config *pipe_config)
5851{
5852 struct drm_device *dev = crtc->base.dev;
5853 struct drm_i915_private *dev_priv = dev->dev_private;
5854 uint32_t tmp;
5855
5856 tmp = I915_READ(PF_CTL(crtc->pipe));
5857
5858 if (tmp & PF_ENABLE) {
5859 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5860 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5861
5862 /* We currently do not free assignements of panel fitters on
5863 * ivb/hsw (since we don't use the higher upscaling modes which
5864 * differentiates them) so just WARN about this case for now. */
5865 if (IS_GEN7(dev)) {
5866 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5867 PF_PIPE_SEL_IVB(crtc->pipe));
5868 }
2fa2fe9a 5869 }
79e53945
JB		 5870}
5871
0e8ffe1b
DV		 5872static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5873 struct intel_crtc_config *pipe_config)
5874{
5875 struct drm_device *dev = crtc->base.dev;
5876 struct drm_i915_private *dev_priv = dev->dev_private;
5877 uint32_t tmp;
5878
e143a21c 5879 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5880 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5881
0e8ffe1b
DV		 5882 tmp = I915_READ(PIPECONF(crtc->pipe));
5883 if (!(tmp & PIPECONF_ENABLE))
5884 return false;
5885
ab9412ba 5886 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5887 struct intel_shared_dpll *pll;
5888
88adfff1
DV		 5889 pipe_config->has_pch_encoder = true;
5890
627eb5a3
DV		 5891 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5892 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5893 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5894
5895 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5896
c0d43d62 5897 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 5898 pipe_config->shared_dpll =
5899 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 5900 } else {
5901 tmp = I915_READ(PCH_DPLL_SEL);
5902 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5903 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5904 else
5905 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5906 }
66e985c0
DV		 5907
5908 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5909
5910 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5911 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5912
5913 tmp = pipe_config->dpll_hw_state.dpll;
5914 pipe_config->pixel_multiplier =
5915 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5916 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5917 } else {
5918 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5919 }
5920
1bd1bd80
DV		 5921 intel_get_pipe_timings(crtc, pipe_config);
5922
2fa2fe9a
DV		 5923 ironlake_get_pfit_config(crtc, pipe_config);
5924
0e8ffe1b
DV		 5925 return true;
5926}
5927
d6dd9eb1
DV		 5928static void haswell_modeset_global_resources(struct drm_device *dev)
5929{
d6dd9eb1
DV		 5930 bool enable = false;
5931 struct intel_crtc *crtc;
d6dd9eb1
DV		 5932
5933 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5934 if (!crtc->base.enabled)
5935 continue;
d6dd9eb1 5936
e7a639c4
DV		 5937 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5938 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5939 enable = true;
5940 }
5941
d6dd9eb1
DV		 5942 intel_set_power_well(dev, enable);
5943}
5944
09b4ddf9 5945static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5946 int x, int y,
5947 struct drm_framebuffer *fb)
5948{
5949 struct drm_device *dev = crtc->dev;
5950 struct drm_i915_private *dev_priv = dev->dev_private;
5951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5952 int plane = intel_crtc->plane;
09b4ddf9 5953 int ret;
09b4ddf9 5954
ff9a6750 5955 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5956 return -EINVAL;
5957
09b4ddf9
PZ		 5958 /* Ensure that the cursor is valid for the new mode before changing... */
5959 intel_crtc_update_cursor(crtc, true);
5960
03afc4a2
DV		 5961 if (intel_crtc->config.has_dp_encoder)
5962 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5963
5964 intel_crtc->lowfreq_avail = false;
09b4ddf9 5965
8a654f3b 5966 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5967
ca3a0ff8 5968 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5969 intel_cpu_transcoder_set_m_n(intel_crtc,
5970 &intel_crtc->config.fdi_m_n);
5971 }
09b4ddf9 5972
6ff93609 5973 haswell_set_pipeconf(crtc);
09b4ddf9 5974
50f3b016 5975 intel_set_pipe_csc(crtc);
86d3efce 5976
09b4ddf9 5977 /* Set up the display plane register */
86d3efce 5978 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5979 POSTING_READ(DSPCNTR(plane));
5980
5981 ret = intel_pipe_set_base(crtc, x, y, fb);
5982
5983 intel_update_watermarks(dev);
5984
1f803ee5 5985 return ret;
79e53945
JB		 5986}
5987
0e8ffe1b
DV		 5988static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5989 struct intel_crtc_config *pipe_config)
5990{
5991 struct drm_device *dev = crtc->base.dev;
5992 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5993 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5994 uint32_t tmp;
5995
e143a21c 5996 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 5997 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5998
eccb140b
DV		 5999 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6000 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6001 enum pipe trans_edp_pipe;
6002 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6003 default:
6004 WARN(1, "unknown pipe linked to edp transcoder\n");
6005 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6006 case TRANS_DDI_EDP_INPUT_A_ON:
6007 trans_edp_pipe = PIPE_A;
6008 break;
6009 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6010 trans_edp_pipe = PIPE_B;
6011 break;
6012 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6013 trans_edp_pipe = PIPE_C;
6014 break;
6015 }
6016
6017 if (trans_edp_pipe == crtc->pipe)
6018 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6019 }
6020
b97186f0 6021 if (!intel_display_power_enabled(dev,
eccb140b 6022 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6023 return false;
6024
eccb140b 6025 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6026 if (!(tmp & PIPECONF_ENABLE))
6027 return false;
6028
88adfff1 6029 /*
f196e6be 6030 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6031 * DDI E. So just check whether this pipe is wired to DDI E and whether
6032 * the PCH transcoder is on.
6033 */
eccb140b 6034 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6035 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6036 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6037 pipe_config->has_pch_encoder = true;
6038
627eb5a3
DV		 6039 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6040 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6041 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6042
6043 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6044 }
6045
1bd1bd80
DV		 6046 intel_get_pipe_timings(crtc, pipe_config);
6047
2fa2fe9a
DV		 6048 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6049 if (intel_display_power_enabled(dev, pfit_domain))
6050 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6051
42db64ef
PZ		 6052 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6053 (I915_READ(IPS_CTL) & IPS_ENABLE);
6054
6c49f241
DV		 6055 pipe_config->pixel_multiplier = 1;
6056
0e8ffe1b
DV		 6057 return true;
6058}
6059
f564048e 6060static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6061 int x, int y,
94352cf9 6062 struct drm_framebuffer *fb)
f564048e
EA		 6063{
6064 struct drm_device *dev = crtc->dev;
6065 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6066 struct drm_encoder_helper_funcs *encoder_funcs;
6067 struct intel_encoder *encoder;
0b701d27 6068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6069 struct drm_display_mode *adjusted_mode =
6070 &intel_crtc->config.adjusted_mode;
6071 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6072 int pipe = intel_crtc->pipe;
f564048e
EA		 6073 int ret;
6074
0b701d27 6075 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6076
b8cecdf5
DV		 6077 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6078
79e53945 6079 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6080
9256aa19
DV		 6081 if (ret != 0)
6082 return ret;
6083
6084 for_each_encoder_on_crtc(dev, crtc, encoder) {
6085 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6086 encoder->base.base.id,
6087 drm_get_encoder_name(&encoder->base),
6088 mode->base.id, mode->name);
6cc5f341
DV		 6089 if (encoder->mode_set) {
6090 encoder->mode_set(encoder);
6091 } else {
6092 encoder_funcs = encoder->base.helper_private;
6093 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6094 }
9256aa19
DV		 6095 }
6096
6097 return 0;
79e53945
JB		 6098}
6099
3a9627f4
WF		 6100static bool intel_eld_uptodate(struct drm_connector *connector,
6101 int reg_eldv, uint32_t bits_eldv,
6102 int reg_elda, uint32_t bits_elda,
6103 int reg_edid)
6104{
6105 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6106 uint8_t *eld = connector->eld;
6107 uint32_t i;
6108
6109 i = I915_READ(reg_eldv);
6110 i &= bits_eldv;
6111
6112 if (!eld[0])
6113 return !i;
6114
6115 if (!i)
6116 return false;
6117
6118 i = I915_READ(reg_elda);
6119 i &= ~bits_elda;
6120 I915_WRITE(reg_elda, i);
6121
6122 for (i = 0; i < eld[2]; i++)
6123 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6124 return false;
6125
6126 return true;
6127}
6128
e0dac65e
WF		 6129static void g4x_write_eld(struct drm_connector *connector,
6130 struct drm_crtc *crtc)
6131{
6132 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6133 uint8_t *eld = connector->eld;
6134 uint32_t eldv;
6135 uint32_t len;
6136 uint32_t i;
6137
6138 i = I915_READ(G4X_AUD_VID_DID);
6139
6140 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6141 eldv = G4X_ELDV_DEVCL_DEVBLC;
6142 else
6143 eldv = G4X_ELDV_DEVCTG;
6144
3a9627f4
WF		 6145 if (intel_eld_uptodate(connector,
6146 G4X_AUD_CNTL_ST, eldv,
6147 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6148 G4X_HDMIW_HDMIEDID))
6149 return;
6150
e0dac65e
WF		 6151 i = I915_READ(G4X_AUD_CNTL_ST);
6152 i &= ~(eldv | G4X_ELD_ADDR);
6153 len = (i >> 9) & 0x1f; /* ELD buffer size */
6154 I915_WRITE(G4X_AUD_CNTL_ST, i);
6155
6156 if (!eld[0])
6157 return;
6158
6159 len = min_t(uint8_t, eld[2], len);
6160 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6161 for (i = 0; i < len; i++)
6162 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6163
6164 i = I915_READ(G4X_AUD_CNTL_ST);
6165 i |= eldv;
6166 I915_WRITE(G4X_AUD_CNTL_ST, i);
6167}
6168
83358c85
WX		 6169static void haswell_write_eld(struct drm_connector *connector,
6170 struct drm_crtc *crtc)
6171{
6172 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6173 uint8_t *eld = connector->eld;
6174 struct drm_device *dev = crtc->dev;
7b9f35a6 6175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6176 uint32_t eldv;
6177 uint32_t i;
6178 int len;
6179 int pipe = to_intel_crtc(crtc)->pipe;
6180 int tmp;
6181
6182 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6183 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6184 int aud_config = HSW_AUD_CFG(pipe);
6185 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6186
6187
6188 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6189
6190 /* Audio output enable */
6191 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6192 tmp = I915_READ(aud_cntrl_st2);
6193 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6194 I915_WRITE(aud_cntrl_st2, tmp);
6195
6196 /* Wait for 1 vertical blank */
6197 intel_wait_for_vblank(dev, pipe);
6198
6199 /* Set ELD valid state */
6200 tmp = I915_READ(aud_cntrl_st2);
6201 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6202 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6203 I915_WRITE(aud_cntrl_st2, tmp);
6204 tmp = I915_READ(aud_cntrl_st2);
6205 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6206
6207 /* Enable HDMI mode */
6208 tmp = I915_READ(aud_config);
6209 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6210 /* clear N_programing_enable and N_value_index */
6211 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6212 I915_WRITE(aud_config, tmp);
6213
6214 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6215
6216 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6217 intel_crtc->eld_vld = true;
83358c85
WX		 6218
6219 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6220 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6221 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6222 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6223 } else
6224 I915_WRITE(aud_config, 0);
6225
6226 if (intel_eld_uptodate(connector,
6227 aud_cntrl_st2, eldv,
6228 aud_cntl_st, IBX_ELD_ADDRESS,
6229 hdmiw_hdmiedid))
6230 return;
6231
6232 i = I915_READ(aud_cntrl_st2);
6233 i &= ~eldv;
6234 I915_WRITE(aud_cntrl_st2, i);
6235
6236 if (!eld[0])
6237 return;
6238
6239 i = I915_READ(aud_cntl_st);
6240 i &= ~IBX_ELD_ADDRESS;
6241 I915_WRITE(aud_cntl_st, i);
6242 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6243 DRM_DEBUG_DRIVER("port num:%d\n", i);
6244
6245 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6246 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6247 for (i = 0; i < len; i++)
6248 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6249
6250 i = I915_READ(aud_cntrl_st2);
6251 i |= eldv;
6252 I915_WRITE(aud_cntrl_st2, i);
6253
6254}
6255
e0dac65e
WF		 6256static void ironlake_write_eld(struct drm_connector *connector,
6257 struct drm_crtc *crtc)
6258{
6259 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6260 uint8_t *eld = connector->eld;
6261 uint32_t eldv;
6262 uint32_t i;
6263 int len;
6264 int hdmiw_hdmiedid;
b6daa025 6265 int aud_config;
e0dac65e
WF		 6266 int aud_cntl_st;
6267 int aud_cntrl_st2;
9b138a83 6268 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6269
b3f33cbf 6270 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6271 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6272 aud_config = IBX_AUD_CFG(pipe);
6273 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6274 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6275 } else {
9b138a83
WX		 6276 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6277 aud_config = CPT_AUD_CFG(pipe);
6278 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6279 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6280 }
6281
9b138a83 6282 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6283
6284 i = I915_READ(aud_cntl_st);
9b138a83 6285 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6286 if (!i) {
6287 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6288 /* operate blindly on all ports */
1202b4c6
WF		 6289 eldv = IBX_ELD_VALIDB;
6290 eldv |= IBX_ELD_VALIDB << 4;
6291 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6292 } else {
2582a850 6293 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6294 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6295 }
6296
3a9627f4
WF		 6297 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6298 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6299 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6300 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6301 } else
6302 I915_WRITE(aud_config, 0);
e0dac65e 6303
3a9627f4
WF		 6304 if (intel_eld_uptodate(connector,
6305 aud_cntrl_st2, eldv,
6306 aud_cntl_st, IBX_ELD_ADDRESS,
6307 hdmiw_hdmiedid))
6308 return;
6309
e0dac65e
WF		 6310 i = I915_READ(aud_cntrl_st2);
6311 i &= ~eldv;
6312 I915_WRITE(aud_cntrl_st2, i);
6313
6314 if (!eld[0])
6315 return;
6316
e0dac65e 6317 i = I915_READ(aud_cntl_st);
1202b4c6 6318 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6319 I915_WRITE(aud_cntl_st, i);
6320
6321 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6322 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6323 for (i = 0; i < len; i++)
6324 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6325
6326 i = I915_READ(aud_cntrl_st2);
6327 i |= eldv;
6328 I915_WRITE(aud_cntrl_st2, i);
6329}
6330
6331void intel_write_eld(struct drm_encoder *encoder,
6332 struct drm_display_mode *mode)
6333{
6334 struct drm_crtc *crtc = encoder->crtc;
6335 struct drm_connector *connector;
6336 struct drm_device *dev = encoder->dev;
6337 struct drm_i915_private *dev_priv = dev->dev_private;
6338
6339 connector = drm_select_eld(encoder, mode);
6340 if (!connector)
6341 return;
6342
6343 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6344 connector->base.id,
6345 drm_get_connector_name(connector),
6346 connector->encoder->base.id,
6347 drm_get_encoder_name(connector->encoder));
6348
6349 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6350
6351 if (dev_priv->display.write_eld)
6352 dev_priv->display.write_eld(connector, crtc);
6353}
6354
79e53945
JB		 6355/** Loads the palette/gamma unit for the CRTC with the prepared values */
6356void intel_crtc_load_lut(struct drm_crtc *crtc)
6357{
6358 struct drm_device *dev = crtc->dev;
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6361 enum pipe pipe = intel_crtc->pipe;
6362 int palreg = PALETTE(pipe);
79e53945 6363 int i;
42db64ef 6364 bool reenable_ips = false;
79e53945
JB		 6365
6366 /* The clocks have to be on to load the palette. */
aed3f09d 6367 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6368 return;
6369
14420bd0
VS		 6370 if (!HAS_PCH_SPLIT(dev_priv->dev))
6371 assert_pll_enabled(dev_priv, pipe);
6372
f2b115e6 6373 /* use legacy palette for Ironlake */
bad720ff 6374 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6375 palreg = LGC_PALETTE(pipe);
6376
6377 /* Workaround : Do not read or write the pipe palette/gamma data while
6378 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6379 */
6380 if (intel_crtc->config.ips_enabled &&
6381 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6382 GAMMA_MODE_MODE_SPLIT)) {
6383 hsw_disable_ips(intel_crtc);
6384 reenable_ips = true;
6385 }
2c07245f 6386
79e53945
JB		 6387 for (i = 0; i < 256; i++) {
6388 I915_WRITE(palreg + 4 * i,
6389 (intel_crtc->lut_r[i] << 16) |
6390 (intel_crtc->lut_g[i] << 8) |
6391 intel_crtc->lut_b[i]);
6392 }
42db64ef
PZ		 6393
6394 if (reenable_ips)
6395 hsw_enable_ips(intel_crtc);
79e53945
JB		 6396}
6397
560b85bb
CW		 6398static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6399{
6400 struct drm_device *dev = crtc->dev;
6401 struct drm_i915_private *dev_priv = dev->dev_private;
6402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6403 bool visible = base != 0;
6404 u32 cntl;
6405
6406 if (intel_crtc->cursor_visible == visible)
6407 return;
6408
9db4a9c7 6409 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6410 if (visible) {
6411 /* On these chipsets we can only modify the base whilst
6412 * the cursor is disabled.
6413 */
9db4a9c7 6414 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6415
6416 cntl &= ~(CURSOR_FORMAT_MASK);
6417 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6418 cntl |= CURSOR_ENABLE |
6419 CURSOR_GAMMA_ENABLE |
6420 CURSOR_FORMAT_ARGB;
6421 } else
6422 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6423 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6424
6425 intel_crtc->cursor_visible = visible;
6426}
6427
6428static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6429{
6430 struct drm_device *dev = crtc->dev;
6431 struct drm_i915_private *dev_priv = dev->dev_private;
6432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6433 int pipe = intel_crtc->pipe;
6434 bool visible = base != 0;
6435
6436 if (intel_crtc->cursor_visible != visible) {
548f245b 6437 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6438 if (base) {
6439 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6440 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6441 cntl |= pipe << 28; /* Connect to correct pipe */
6442 } else {
6443 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6444 cntl |= CURSOR_MODE_DISABLE;
6445 }
9db4a9c7 6446 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6447
6448 intel_crtc->cursor_visible = visible;
6449 }
6450 /* and commit changes on next vblank */
9db4a9c7 6451 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6452}
6453
65a21cd6
JB		 6454static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6455{
6456 struct drm_device *dev = crtc->dev;
6457 struct drm_i915_private *dev_priv = dev->dev_private;
6458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6459 int pipe = intel_crtc->pipe;
6460 bool visible = base != 0;
6461
6462 if (intel_crtc->cursor_visible != visible) {
6463 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6464 if (base) {
6465 cntl &= ~CURSOR_MODE;
6466 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6467 } else {
6468 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6469 cntl |= CURSOR_MODE_DISABLE;
6470 }
86d3efce
VS		 6471 if (IS_HASWELL(dev))
6472 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6473 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6474
6475 intel_crtc->cursor_visible = visible;
6476 }
6477 /* and commit changes on next vblank */
6478 I915_WRITE(CURBASE_IVB(pipe), base);
6479}
6480
cda4b7d3 6481/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6482static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6483 bool on)
cda4b7d3
CW		 6484{
6485 struct drm_device *dev = crtc->dev;
6486 struct drm_i915_private *dev_priv = dev->dev_private;
6487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6488 int pipe = intel_crtc->pipe;
6489 int x = intel_crtc->cursor_x;
6490 int y = intel_crtc->cursor_y;
560b85bb 6491 u32 base, pos;
cda4b7d3
CW		 6492 bool visible;
6493
6494 pos = 0;
6495
6b383a7f 6496 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6497 base = intel_crtc->cursor_addr;
6498 if (x > (int) crtc->fb->width)
6499 base = 0;
6500
6501 if (y > (int) crtc->fb->height)
6502 base = 0;
6503 } else
6504 base = 0;
6505
6506 if (x < 0) {
6507 if (x + intel_crtc->cursor_width < 0)
6508 base = 0;
6509
6510 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6511 x = -x;
6512 }
6513 pos |= x << CURSOR_X_SHIFT;
6514
6515 if (y < 0) {
6516 if (y + intel_crtc->cursor_height < 0)
6517 base = 0;
6518
6519 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6520 y = -y;
6521 }
6522 pos |= y << CURSOR_Y_SHIFT;
6523
6524 visible = base != 0;
560b85bb 6525 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6526 return;
6527
0cd83aa9 6528 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6529 I915_WRITE(CURPOS_IVB(pipe), pos);
6530 ivb_update_cursor(crtc, base);
6531 } else {
6532 I915_WRITE(CURPOS(pipe), pos);
6533 if (IS_845G(dev) || IS_I865G(dev))
6534 i845_update_cursor(crtc, base);
6535 else
6536 i9xx_update_cursor(crtc, base);
6537 }
cda4b7d3
CW		 6538}
6539
79e53945 6540static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6541 struct drm_file *file,
79e53945
JB		 6542 uint32_t handle,
6543 uint32_t width, uint32_t height)
6544{
6545 struct drm_device *dev = crtc->dev;
6546 struct drm_i915_private *dev_priv = dev->dev_private;
6547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6548 struct drm_i915_gem_object *obj;
cda4b7d3 6549 uint32_t addr;
3f8bc370 6550 int ret;
79e53945 6551
79e53945
JB		 6552 /* if we want to turn off the cursor ignore width and height */
6553 if (!handle) {
28c97730 6554 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6555 addr = 0;
05394f39 6556 obj = NULL;
5004417d 6557 mutex_lock(&dev->struct_mutex);
3f8bc370 6558 goto finish;
79e53945
JB		 6559 }
6560
6561 /* Currently we only support 64x64 cursors */
6562 if (width != 64 || height != 64) {
6563 DRM_ERROR("we currently only support 64x64 cursors\n");
6564 return -EINVAL;
6565 }
6566
05394f39 6567 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6568 if (&obj->base == NULL)
79e53945
JB		 6569 return -ENOENT;
6570
05394f39 6571 if (obj->base.size < width * height * 4) {
79e53945 6572 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6573 ret = -ENOMEM;
6574 goto fail;
79e53945
JB		 6575 }
6576
71acb5eb 6577 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6578 mutex_lock(&dev->struct_mutex);
b295d1b6 6579 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6580 unsigned alignment;
6581
d9e86c0e
CW		 6582 if (obj->tiling_mode) {
6583 DRM_ERROR("cursor cannot be tiled\n");
6584 ret = -EINVAL;
6585 goto fail_locked;
6586 }
6587
693db184
CW		 6588 /* Note that the w/a also requires 2 PTE of padding following
6589 * the bo. We currently fill all unused PTE with the shadow
6590 * page and so we should always have valid PTE following the
6591 * cursor preventing the VT-d warning.
6592 */
6593 alignment = 0;
6594 if (need_vtd_wa(dev))
6595 alignment = 64*1024;
6596
6597 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6598 if (ret) {
6599 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6600 goto fail_locked;
e7b526bb
CW		 6601 }
6602
d9e86c0e
CW		 6603 ret = i915_gem_object_put_fence(obj);
6604 if (ret) {
2da3b9b9 6605 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6606 goto fail_unpin;
6607 }
6608
f343c5f6 6609 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 6610 } else {
6eeefaf3 6611 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6612 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6613 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6614 align);
71acb5eb
DA		 6615 if (ret) {
6616 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6617 goto fail_locked;
71acb5eb 6618 }
05394f39 6619 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6620 }
6621
a6c45cf0 6622 if (IS_GEN2(dev))
14b60391
JB		 6623 I915_WRITE(CURSIZE, (height << 12) | width);
6624
3f8bc370 6625 finish:
3f8bc370 6626 if (intel_crtc->cursor_bo) {
b295d1b6 6627 if (dev_priv->info->cursor_needs_physical) {
05394f39 6628 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6629 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6630 } else
6631 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6632 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6633 }
80824003 6634
7f9872e0 6635 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6636
6637 intel_crtc->cursor_addr = addr;
05394f39 6638 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6639 intel_crtc->cursor_width = width;
6640 intel_crtc->cursor_height = height;
6641
40ccc72b 6642 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6643
79e53945 6644 return 0;
e7b526bb 6645fail_unpin:
05394f39 6646 i915_gem_object_unpin(obj);
7f9872e0 6647fail_locked:
34b8686e 6648 mutex_unlock(&dev->struct_mutex);
bc9025bd 6649fail:
05394f39 6650 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6651 return ret;
79e53945
JB		 6652}
6653
6654static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6655{
79e53945 6656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6657
cda4b7d3
CW		 6658 intel_crtc->cursor_x = x;
6659 intel_crtc->cursor_y = y;
652c393a 6660
40ccc72b 6661 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6662
6663 return 0;
6664}
6665
6666/** Sets the color ramps on behalf of RandR */
6667void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6668 u16 blue, int regno)
6669{
6670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6671
6672 intel_crtc->lut_r[regno] = red >> 8;
6673 intel_crtc->lut_g[regno] = green >> 8;
6674 intel_crtc->lut_b[regno] = blue >> 8;
6675}
6676
b8c00ac5
DA		 6677void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6678 u16 *blue, int regno)
6679{
6680 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6681
6682 *red = intel_crtc->lut_r[regno] << 8;
6683 *green = intel_crtc->lut_g[regno] << 8;
6684 *blue = intel_crtc->lut_b[regno] << 8;
6685}
6686
79e53945 6687static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6688 u16 *blue, uint32_t start, uint32_t size)
79e53945 6689{
7203425a 6690 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6692
7203425a 6693 for (i = start; i < end; i++) {
79e53945
JB		 6694 intel_crtc->lut_r[i] = red[i] >> 8;
6695 intel_crtc->lut_g[i] = green[i] >> 8;
6696 intel_crtc->lut_b[i] = blue[i] >> 8;
6697 }
6698
6699 intel_crtc_load_lut(crtc);
6700}
6701
79e53945
JB		 6702/* VESA 640x480x72Hz mode to set on the pipe */
6703static struct drm_display_mode load_detect_mode = {
6704 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6705 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6706};
6707
d2dff872
CW		 6708static struct drm_framebuffer *
6709intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6710 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6711 struct drm_i915_gem_object *obj)
6712{
6713 struct intel_framebuffer *intel_fb;
6714 int ret;
6715
6716 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6717 if (!intel_fb) {
6718 drm_gem_object_unreference_unlocked(&obj->base);
6719 return ERR_PTR(-ENOMEM);
6720 }
6721
6722 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6723 if (ret) {
6724 drm_gem_object_unreference_unlocked(&obj->base);
6725 kfree(intel_fb);
6726 return ERR_PTR(ret);
6727 }
6728
6729 return &intel_fb->base;
6730}
6731
6732static u32
6733intel_framebuffer_pitch_for_width(int width, int bpp)
6734{
6735 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6736 return ALIGN(pitch, 64);
6737}
6738
6739static u32
6740intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6741{
6742 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6743 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6744}
6745
6746static struct drm_framebuffer *
6747intel_framebuffer_create_for_mode(struct drm_device *dev,
6748 struct drm_display_mode *mode,
6749 int depth, int bpp)
6750{
6751 struct drm_i915_gem_object *obj;
0fed39bd 6752 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6753
6754 obj = i915_gem_alloc_object(dev,
6755 intel_framebuffer_size_for_mode(mode, bpp));
6756 if (obj == NULL)
6757 return ERR_PTR(-ENOMEM);
6758
6759 mode_cmd.width = mode->hdisplay;
6760 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6761 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6762 bpp);
5ca0c34a 6763 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6764
6765 return intel_framebuffer_create(dev, &mode_cmd, obj);
6766}
6767
6768static struct drm_framebuffer *
6769mode_fits_in_fbdev(struct drm_device *dev,
6770 struct drm_display_mode *mode)
6771{
6772 struct drm_i915_private *dev_priv = dev->dev_private;
6773 struct drm_i915_gem_object *obj;
6774 struct drm_framebuffer *fb;
6775
6776 if (dev_priv->fbdev == NULL)
6777 return NULL;
6778
6779 obj = dev_priv->fbdev->ifb.obj;
6780 if (obj == NULL)
6781 return NULL;
6782
6783 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6784 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6785 fb->bits_per_pixel))
d2dff872
CW		 6786 return NULL;
6787
01f2c773 6788 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6789 return NULL;
6790
6791 return fb;
6792}
6793
d2434ab7 6794bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6795 struct drm_display_mode *mode,
8261b191 6796 struct intel_load_detect_pipe *old)
79e53945
JB		 6797{
6798 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6799 struct intel_encoder *intel_encoder =
6800 intel_attached_encoder(connector);
79e53945 6801 struct drm_crtc *possible_crtc;
4ef69c7a 6802 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6803 struct drm_crtc *crtc = NULL;
6804 struct drm_device *dev = encoder->dev;
94352cf9 6805 struct drm_framebuffer *fb;
79e53945
JB		 6806 int i = -1;
6807
d2dff872
CW		 6808 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6809 connector->base.id, drm_get_connector_name(connector),
6810 encoder->base.id, drm_get_encoder_name(encoder));
6811
79e53945
JB		 6812 /*
6813 * Algorithm gets a little messy:
7a5e4805 6814 *
79e53945
JB		 6815 * - if the connector already has an assigned crtc, use it (but make
6816 * sure it's on first)
7a5e4805 6817 *
79e53945
JB		 6818 * - try to find the first unused crtc that can drive this connector,
6819 * and use that if we find one
79e53945
JB		 6820 */
6821
6822 /* See if we already have a CRTC for this connector */
6823 if (encoder->crtc) {
6824 crtc = encoder->crtc;
8261b191 6825
7b24056b
DV		 6826 mutex_lock(&crtc->mutex);
6827
24218aac 6828 old->dpms_mode = connector->dpms;
8261b191
CW		 6829 old->load_detect_temp = false;
6830
6831 /* Make sure the crtc and connector are running */
24218aac
DV		 6832 if (connector->dpms != DRM_MODE_DPMS_ON)
6833 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6834
7173188d 6835 return true;
79e53945
JB		 6836 }
6837
6838 /* Find an unused one (if possible) */
6839 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6840 i++;
6841 if (!(encoder->possible_crtcs & (1 << i)))
6842 continue;
6843 if (!possible_crtc->enabled) {
6844 crtc = possible_crtc;
6845 break;
6846 }
79e53945
JB		 6847 }
6848
6849 /*
6850 * If we didn't find an unused CRTC, don't use any.
6851 */
6852 if (!crtc) {
7173188d
CW		 6853 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6854 return false;
79e53945
JB		 6855 }
6856
7b24056b 6857 mutex_lock(&crtc->mutex);
fc303101
DV		 6858 intel_encoder->new_crtc = to_intel_crtc(crtc);
6859 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6860
6861 intel_crtc = to_intel_crtc(crtc);
24218aac 6862 old->dpms_mode = connector->dpms;
8261b191 6863 old->load_detect_temp = true;
d2dff872 6864 old->release_fb = NULL;
79e53945 6865
6492711d
CW		 6866 if (!mode)
6867 mode = &load_detect_mode;
79e53945 6868
d2dff872
CW		 6869 /* We need a framebuffer large enough to accommodate all accesses
6870 * that the plane may generate whilst we perform load detection.
6871 * We can not rely on the fbcon either being present (we get called
6872 * during its initialisation to detect all boot displays, or it may
6873 * not even exist) or that it is large enough to satisfy the
6874 * requested mode.
6875 */
94352cf9
DV		 6876 fb = mode_fits_in_fbdev(dev, mode);
6877 if (fb == NULL) {
d2dff872 6878 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6879 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6880 old->release_fb = fb;
d2dff872
CW		 6881 } else
6882 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6883 if (IS_ERR(fb)) {
d2dff872 6884 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6885 mutex_unlock(&crtc->mutex);
0e8b3d3e 6886 return false;
79e53945 6887 }
79e53945 6888
c0c36b94 6889 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6890 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6891 if (old->release_fb)
6892 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6893 mutex_unlock(&crtc->mutex);
0e8b3d3e 6894 return false;
79e53945 6895 }
7173188d 6896
79e53945 6897 /* let the connector get through one full cycle before testing */
9d0498a2 6898 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6899 return true;
79e53945
JB		 6900}
6901
d2434ab7 6902void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6903 struct intel_load_detect_pipe *old)
79e53945 6904{
d2434ab7
DV		 6905 struct intel_encoder *intel_encoder =
6906 intel_attached_encoder(connector);
4ef69c7a 6907 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6908 struct drm_crtc *crtc = encoder->crtc;
79e53945 6909
d2dff872
CW		 6910 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6911 connector->base.id, drm_get_connector_name(connector),
6912 encoder->base.id, drm_get_encoder_name(encoder));
6913
8261b191 6914 if (old->load_detect_temp) {
fc303101
DV		 6915 to_intel_connector(connector)->new_encoder = NULL;
6916 intel_encoder->new_crtc = NULL;
6917 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6918
36206361
DV		 6919 if (old->release_fb) {
6920 drm_framebuffer_unregister_private(old->release_fb);
6921 drm_framebuffer_unreference(old->release_fb);
6922 }
d2dff872 6923
67c96400 6924 mutex_unlock(&crtc->mutex);
0622a53c 6925 return;
79e53945
JB		 6926 }
6927
c751ce4f 6928 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6929 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6930 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6931
6932 mutex_unlock(&crtc->mutex);
79e53945
JB		 6933}
6934
6935/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 6936static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6937 struct intel_crtc_config *pipe_config)
79e53945 6938{
f1f644dc 6939 struct drm_device *dev = crtc->base.dev;
79e53945 6940 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 6941 int pipe = pipe_config->cpu_transcoder;
548f245b 6942 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6943 u32 fp;
6944 intel_clock_t clock;
6945
6946 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6947 fp = I915_READ(FP0(pipe));
79e53945 6948 else
39adb7a5 6949 fp = I915_READ(FP1(pipe));
79e53945
JB		 6950
6951 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6952 if (IS_PINEVIEW(dev)) {
6953 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6954 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6955 } else {
6956 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6957 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6958 }
6959
a6c45cf0 6960 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6961 if (IS_PINEVIEW(dev))
6962 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6963 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6964 else
6965 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6966 DPLL_FPA01_P1_POST_DIV_SHIFT);
6967
6968 switch (dpll & DPLL_MODE_MASK) {
6969 case DPLLB_MODE_DAC_SERIAL:
6970 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6971 5 : 10;
6972 break;
6973 case DPLLB_MODE_LVDS:
6974 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6975 7 : 14;
6976 break;
6977 default:
28c97730 6978 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 6979 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 6980 pipe_config->adjusted_mode.clock = 0;
6981 return;
79e53945
JB		 6982 }
6983
ac58c3f0
DV		 6984 if (IS_PINEVIEW(dev))
6985 pineview_clock(96000, &clock);
6986 else
6987 i9xx_clock(96000, &clock);
79e53945
JB		 6988 } else {
6989 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6990
6991 if (is_lvds) {
6992 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6993 DPLL_FPA01_P1_POST_DIV_SHIFT);
6994 clock.p2 = 14;
6995
6996 if ((dpll & PLL_REF_INPUT_MASK) ==
6997 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6998 /* XXX: might not be 66MHz */
ac58c3f0 6999 i9xx_clock(66000, &clock);
79e53945 7000 } else
ac58c3f0 7001 i9xx_clock(48000, &clock);
79e53945
JB		 7002 } else {
7003 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7004 clock.p1 = 2;
7005 else {
7006 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7007 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7008 }
7009 if (dpll & PLL_P2_DIVIDE_BY_4)
7010 clock.p2 = 4;
7011 else
7012 clock.p2 = 2;
7013
ac58c3f0 7014 i9xx_clock(48000, &clock);
79e53945
JB		 7015 }
7016 }
7017
f1f644dc
JB		 7018 pipe_config->adjusted_mode.clock = clock.dot *
7019 pipe_config->pixel_multiplier;
7020}
7021
7022static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7023 struct intel_crtc_config *pipe_config)
7024{
7025 struct drm_device *dev = crtc->base.dev;
7026 struct drm_i915_private *dev_priv = dev->dev_private;
7027 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7028 int link_freq, repeat;
7029 u64 clock;
7030 u32 link_m, link_n;
7031
7032 repeat = pipe_config->pixel_multiplier;
7033
7034 /*
7035 * The calculation for the data clock is:
7036 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7037 * But we want to avoid losing precison if possible, so:
7038 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7039 *
7040 * and the link clock is simpler:
7041 * link_clock = (m * link_clock * repeat) / n
7042 */
7043
7044 /*
7045 * We need to get the FDI or DP link clock here to derive
7046 * the M/N dividers.
7047 *
7048 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7049 * For DP, it's either 1.62GHz or 2.7GHz.
7050 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7051 */
f1f644dc
JB		 7052 if (pipe_config->has_pch_encoder)
7053 link_freq = intel_fdi_link_freq(dev) * 10000;
7054 else
7055 link_freq = pipe_config->port_clock;
7056
7057 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7058 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7059
7060 if (!link_m || !link_n)
7061 return;
79e53945 7062
f1f644dc
JB		 7063 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7064 do_div(clock, link_n);
7065
7066 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 7067}
7068
7069/** Returns the currently programmed mode of the given pipe. */
7070struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7071 struct drm_crtc *crtc)
7072{
548f245b 7073 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7075 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7076 struct drm_display_mode *mode;
f1f644dc 7077 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7078 int htot = I915_READ(HTOTAL(cpu_transcoder));
7079 int hsync = I915_READ(HSYNC(cpu_transcoder));
7080 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7081 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7082
7083 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7084 if (!mode)
7085 return NULL;
7086
f1f644dc
JB		 7087 /*
7088 * Construct a pipe_config sufficient for getting the clock info
7089 * back out of crtc_clock_get.
7090 *
7091 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7092 * to use a real value here instead.
7093 */
e143a21c 7094 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB		 7095 pipe_config.pixel_multiplier = 1;
7096 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7097
7098 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7099 mode->hdisplay = (htot & 0xffff) + 1;
7100 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7101 mode->hsync_start = (hsync & 0xffff) + 1;
7102 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7103 mode->vdisplay = (vtot & 0xffff) + 1;
7104 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7105 mode->vsync_start = (vsync & 0xffff) + 1;
7106 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7107
7108 drm_mode_set_name(mode);
79e53945
JB		 7109
7110 return mode;
7111}
7112
3dec0095 7113static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7114{
7115 struct drm_device *dev = crtc->dev;
7116 drm_i915_private_t *dev_priv = dev->dev_private;
7117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7118 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7119 int dpll_reg = DPLL(pipe);
7120 int dpll;
652c393a 7121
bad720ff 7122 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7123 return;
7124
7125 if (!dev_priv->lvds_downclock_avail)
7126 return;
7127
dbdc6479 7128 dpll = I915_READ(dpll_reg);
652c393a 7129 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7130 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7131
8ac5a6d5 7132 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7133
7134 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7135 I915_WRITE(dpll_reg, dpll);
9d0498a2 7136 intel_wait_for_vblank(dev, pipe);
dbdc6479 7137
652c393a
JB		 7138 dpll = I915_READ(dpll_reg);
7139 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7140 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7141 }
652c393a
JB		 7142}
7143
7144static void intel_decrease_pllclock(struct drm_crtc *crtc)
7145{
7146 struct drm_device *dev = crtc->dev;
7147 drm_i915_private_t *dev_priv = dev->dev_private;
7148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7149
bad720ff 7150 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7151 return;
7152
7153 if (!dev_priv->lvds_downclock_avail)
7154 return;
7155
7156 /*
7157 * Since this is called by a timer, we should never get here in
7158 * the manual case.
7159 */
7160 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7161 int pipe = intel_crtc->pipe;
7162 int dpll_reg = DPLL(pipe);
7163 int dpll;
f6e5b160 7164
44d98a61 7165 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7166
8ac5a6d5 7167 assert_panel_unlocked(dev_priv, pipe);
652c393a 7168
dc257cf1 7169 dpll = I915_READ(dpll_reg);
652c393a
JB		 7170 dpll |= DISPLAY_RATE_SELECT_FPA1;
7171 I915_WRITE(dpll_reg, dpll);
9d0498a2 7172 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7173 dpll = I915_READ(dpll_reg);
7174 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7175 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7176 }
7177
7178}
7179
f047e395
CW		 7180void intel_mark_busy(struct drm_device *dev)
7181{
f047e395
CW		 7182 i915_update_gfx_val(dev->dev_private);
7183}
7184
7185void intel_mark_idle(struct drm_device *dev)
652c393a 7186{
652c393a 7187 struct drm_crtc *crtc;
652c393a
JB		 7188
7189 if (!i915_powersave)
7190 return;
7191
652c393a 7192 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7193 if (!crtc->fb)
7194 continue;
7195
725a5b54 7196 intel_decrease_pllclock(crtc);
652c393a 7197 }
652c393a
JB		 7198}
7199
c65355bb
CW		 7200void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7201 struct intel_ring_buffer *ring)
652c393a 7202{
f047e395
CW		 7203 struct drm_device *dev = obj->base.dev;
7204 struct drm_crtc *crtc;
652c393a 7205
f047e395 7206 if (!i915_powersave)
acb87dfb
CW		 7207 return;
7208
652c393a
JB		 7209 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7210 if (!crtc->fb)
7211 continue;
7212
c65355bb
CW		 7213 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7214 continue;
7215
7216 intel_increase_pllclock(crtc);
7217 if (ring && intel_fbc_enabled(dev))
7218 ring->fbc_dirty = true;
652c393a
JB		 7219 }
7220}
7221
79e53945
JB		 7222static void intel_crtc_destroy(struct drm_crtc *crtc)
7223{
7224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7225 struct drm_device *dev = crtc->dev;
7226 struct intel_unpin_work *work;
7227 unsigned long flags;
7228
7229 spin_lock_irqsave(&dev->event_lock, flags);
7230 work = intel_crtc->unpin_work;
7231 intel_crtc->unpin_work = NULL;
7232 spin_unlock_irqrestore(&dev->event_lock, flags);
7233
7234 if (work) {
7235 cancel_work_sync(&work->work);
7236 kfree(work);
7237 }
79e53945 7238
40ccc72b
MK		 7239 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7240
79e53945 7241 drm_crtc_cleanup(crtc);
67e77c5a 7242
79e53945
JB		 7243 kfree(intel_crtc);
7244}
7245
6b95a207
KH		 7246static void intel_unpin_work_fn(struct work_struct *__work)
7247{
7248 struct intel_unpin_work *work =
7249 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7250 struct drm_device *dev = work->crtc->dev;
6b95a207 7251
b4a98e57 7252 mutex_lock(&dev->struct_mutex);
1690e1eb 7253 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7254 drm_gem_object_unreference(&work->pending_flip_obj->base);
7255 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7256
b4a98e57
CW		 7257 intel_update_fbc(dev);
7258 mutex_unlock(&dev->struct_mutex);
7259
7260 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7261 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7262
6b95a207
KH		 7263 kfree(work);
7264}
7265
1afe3e9d 7266static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7267 struct drm_crtc *crtc)
6b95a207
KH		 7268{
7269 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7271 struct intel_unpin_work *work;
6b95a207
KH		 7272 unsigned long flags;
7273
7274 /* Ignore early vblank irqs */
7275 if (intel_crtc == NULL)
7276 return;
7277
7278 spin_lock_irqsave(&dev->event_lock, flags);
7279 work = intel_crtc->unpin_work;
e7d841ca
CW		 7280
7281 /* Ensure we don't miss a work->pending update ... */
7282 smp_rmb();
7283
7284 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7285 spin_unlock_irqrestore(&dev->event_lock, flags);
7286 return;
7287 }
7288
e7d841ca
CW		 7289 /* and that the unpin work is consistent wrt ->pending. */
7290 smp_rmb();
7291
6b95a207 7292 intel_crtc->unpin_work = NULL;
6b95a207 7293
45a066eb
RC		 7294 if (work->event)
7295 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7296
0af7e4df
MK		 7297 drm_vblank_put(dev, intel_crtc->pipe);
7298
6b95a207
KH		 7299 spin_unlock_irqrestore(&dev->event_lock, flags);
7300
2c10d571 7301 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7302
7303 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7304
7305 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7306}
7307
1afe3e9d
JB		 7308void intel_finish_page_flip(struct drm_device *dev, int pipe)
7309{
7310 drm_i915_private_t *dev_priv = dev->dev_private;
7311 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7312
49b14a5c 7313 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7314}
7315
7316void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7317{
7318 drm_i915_private_t *dev_priv = dev->dev_private;
7319 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7320
49b14a5c 7321 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7322}
7323
6b95a207
KH		 7324void intel_prepare_page_flip(struct drm_device *dev, int plane)
7325{
7326 drm_i915_private_t *dev_priv = dev->dev_private;
7327 struct intel_crtc *intel_crtc =
7328 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7329 unsigned long flags;
7330
e7d841ca
CW		 7331 /* NB: An MMIO update of the plane base pointer will also
7332 * generate a page-flip completion irq, i.e. every modeset
7333 * is also accompanied by a spurious intel_prepare_page_flip().
7334 */
6b95a207 7335 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7336 if (intel_crtc->unpin_work)
7337 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7338 spin_unlock_irqrestore(&dev->event_lock, flags);
7339}
7340
e7d841ca
CW		 7341inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7342{
7343 /* Ensure that the work item is consistent when activating it ... */
7344 smp_wmb();
7345 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7346 /* and that it is marked active as soon as the irq could fire. */
7347 smp_wmb();
7348}
7349
8c9f3aaf
JB		 7350static int intel_gen2_queue_flip(struct drm_device *dev,
7351 struct drm_crtc *crtc,
7352 struct drm_framebuffer *fb,
7353 struct drm_i915_gem_object *obj)
7354{
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7357 u32 flip_mask;
6d90c952 7358 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7359 int ret;
7360
6d90c952 7361 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7362 if (ret)
83d4092b 7363 goto err;
8c9f3aaf 7364
6d90c952 7365 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7366 if (ret)
83d4092b 7367 goto err_unpin;
8c9f3aaf
JB		 7368
7369 /* Can't queue multiple flips, so wait for the previous
7370 * one to finish before executing the next.
7371 */
7372 if (intel_crtc->plane)
7373 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7374 else
7375 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7376 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7377 intel_ring_emit(ring, MI_NOOP);
7378 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7379 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7380 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7381 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7382 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7383
7384 intel_mark_page_flip_active(intel_crtc);
6d90c952 7385 intel_ring_advance(ring);
83d4092b
CW		 7386 return 0;
7387
7388err_unpin:
7389 intel_unpin_fb_obj(obj);
7390err:
8c9f3aaf
JB		 7391 return ret;
7392}
7393
7394static int intel_gen3_queue_flip(struct drm_device *dev,
7395 struct drm_crtc *crtc,
7396 struct drm_framebuffer *fb,
7397 struct drm_i915_gem_object *obj)
7398{
7399 struct drm_i915_private *dev_priv = dev->dev_private;
7400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7401 u32 flip_mask;
6d90c952 7402 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7403 int ret;
7404
6d90c952 7405 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7406 if (ret)
83d4092b 7407 goto err;
8c9f3aaf 7408
6d90c952 7409 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7410 if (ret)
83d4092b 7411 goto err_unpin;
8c9f3aaf
JB		 7412
7413 if (intel_crtc->plane)
7414 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7415 else
7416 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7417 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7418 intel_ring_emit(ring, MI_NOOP);
7419 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7420 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7421 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7422 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7423 intel_ring_emit(ring, MI_NOOP);
7424
e7d841ca 7425 intel_mark_page_flip_active(intel_crtc);
6d90c952 7426 intel_ring_advance(ring);
83d4092b
CW		 7427 return 0;
7428
7429err_unpin:
7430 intel_unpin_fb_obj(obj);
7431err:
8c9f3aaf
JB		 7432 return ret;
7433}
7434
7435static int intel_gen4_queue_flip(struct drm_device *dev,
7436 struct drm_crtc *crtc,
7437 struct drm_framebuffer *fb,
7438 struct drm_i915_gem_object *obj)
7439{
7440 struct drm_i915_private *dev_priv = dev->dev_private;
7441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7442 uint32_t pf, pipesrc;
6d90c952 7443 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7444 int ret;
7445
6d90c952 7446 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7447 if (ret)
83d4092b 7448 goto err;
8c9f3aaf 7449
6d90c952 7450 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7451 if (ret)
83d4092b 7452 goto err_unpin;
8c9f3aaf
JB		 7453
7454 /* i965+ uses the linear or tiled offsets from the
7455 * Display Registers (which do not change across a page-flip)
7456 * so we need only reprogram the base address.
7457 */
6d90c952
DV		 7458 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7459 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7460 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7461 intel_ring_emit(ring,
f343c5f6 7462 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7463 obj->tiling_mode);
8c9f3aaf
JB		 7464
7465 /* XXX Enabling the panel-fitter across page-flip is so far
7466 * untested on non-native modes, so ignore it for now.
7467 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7468 */
7469 pf = 0;
7470 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7471 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7472
7473 intel_mark_page_flip_active(intel_crtc);
6d90c952 7474 intel_ring_advance(ring);
83d4092b
CW		 7475 return 0;
7476
7477err_unpin:
7478 intel_unpin_fb_obj(obj);
7479err:
8c9f3aaf
JB		 7480 return ret;
7481}
7482
7483static int intel_gen6_queue_flip(struct drm_device *dev,
7484 struct drm_crtc *crtc,
7485 struct drm_framebuffer *fb,
7486 struct drm_i915_gem_object *obj)
7487{
7488 struct drm_i915_private *dev_priv = dev->dev_private;
7489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7490 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7491 uint32_t pf, pipesrc;
7492 int ret;
7493
6d90c952 7494 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7495 if (ret)
83d4092b 7496 goto err;
8c9f3aaf 7497
6d90c952 7498 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7499 if (ret)
83d4092b 7500 goto err_unpin;
8c9f3aaf 7501
6d90c952
DV		 7502 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7503 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7504 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7505 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7506
dc257cf1
DV		 7507 /* Contrary to the suggestions in the documentation,
7508 * "Enable Panel Fitter" does not seem to be required when page
7509 * flipping with a non-native mode, and worse causes a normal
7510 * modeset to fail.
7511 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7512 */
7513 pf = 0;
8c9f3aaf 7514 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7515 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7516
7517 intel_mark_page_flip_active(intel_crtc);
6d90c952 7518 intel_ring_advance(ring);
83d4092b
CW		 7519 return 0;
7520
7521err_unpin:
7522 intel_unpin_fb_obj(obj);
7523err:
8c9f3aaf
JB		 7524 return ret;
7525}
7526
7c9017e5
JB		 7527/*
7528 * On gen7 we currently use the blit ring because (in early silicon at least)
7529 * the render ring doesn't give us interrpts for page flip completion, which
7530 * means clients will hang after the first flip is queued. Fortunately the
7531 * blit ring generates interrupts properly, so use it instead.
7532 */
7533static int intel_gen7_queue_flip(struct drm_device *dev,
7534 struct drm_crtc *crtc,
7535 struct drm_framebuffer *fb,
7536 struct drm_i915_gem_object *obj)
7537{
7538 struct drm_i915_private *dev_priv = dev->dev_private;
7539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7540 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7541 uint32_t plane_bit = 0;
7c9017e5
JB		 7542 int ret;
7543
7544 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7545 if (ret)
83d4092b 7546 goto err;
7c9017e5 7547
cb05d8de
DV		 7548 switch(intel_crtc->plane) {
7549 case PLANE_A:
7550 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7551 break;
7552 case PLANE_B:
7553 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7554 break;
7555 case PLANE_C:
7556 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7557 break;
7558 default:
7559 WARN_ONCE(1, "unknown plane in flip command\n");
7560 ret = -ENODEV;
ab3951eb 7561 goto err_unpin;
cb05d8de
DV		 7562 }
7563
7c9017e5
JB		 7564 ret = intel_ring_begin(ring, 4);
7565 if (ret)
83d4092b 7566 goto err_unpin;
7c9017e5 7567
cb05d8de 7568 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7569 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 7570 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 7571 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7572
7573 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7574 intel_ring_advance(ring);
83d4092b
CW		 7575 return 0;
7576
7577err_unpin:
7578 intel_unpin_fb_obj(obj);
7579err:
7c9017e5
JB		 7580 return ret;
7581}
7582
8c9f3aaf
JB		 7583static int intel_default_queue_flip(struct drm_device *dev,
7584 struct drm_crtc *crtc,
7585 struct drm_framebuffer *fb,
7586 struct drm_i915_gem_object *obj)
7587{
7588 return -ENODEV;
7589}
7590
6b95a207
KH		 7591static int intel_crtc_page_flip(struct drm_crtc *crtc,
7592 struct drm_framebuffer *fb,
7593 struct drm_pending_vblank_event *event)
7594{
7595 struct drm_device *dev = crtc->dev;
7596 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7597 struct drm_framebuffer *old_fb = crtc->fb;
7598 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7599 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7600 struct intel_unpin_work *work;
8c9f3aaf 7601 unsigned long flags;
52e68630 7602 int ret;
6b95a207 7603
e6a595d2
VS		 7604 /* Can't change pixel format via MI display flips. */
7605 if (fb->pixel_format != crtc->fb->pixel_format)
7606 return -EINVAL;
7607
7608 /*
7609 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7610 * Note that pitch changes could also affect these register.
7611 */
7612 if (INTEL_INFO(dev)->gen > 3 &&
7613 (fb->offsets[0] != crtc->fb->offsets[0] ||
7614 fb->pitches[0] != crtc->fb->pitches[0]))
7615 return -EINVAL;
7616
6b95a207
KH		 7617 work = kzalloc(sizeof *work, GFP_KERNEL);
7618 if (work == NULL)
7619 return -ENOMEM;
7620
6b95a207 7621 work->event = event;
b4a98e57 7622 work->crtc = crtc;
4a35f83b 7623 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7624 INIT_WORK(&work->work, intel_unpin_work_fn);
7625
7317c75e
JB		 7626 ret = drm_vblank_get(dev, intel_crtc->pipe);
7627 if (ret)
7628 goto free_work;
7629
6b95a207
KH		 7630 /* We borrow the event spin lock for protecting unpin_work */
7631 spin_lock_irqsave(&dev->event_lock, flags);
7632 if (intel_crtc->unpin_work) {
7633 spin_unlock_irqrestore(&dev->event_lock, flags);
7634 kfree(work);
7317c75e 7635 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7636
7637 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7638 return -EBUSY;
7639 }
7640 intel_crtc->unpin_work = work;
7641 spin_unlock_irqrestore(&dev->event_lock, flags);
7642
b4a98e57
CW		 7643 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7644 flush_workqueue(dev_priv->wq);
7645
79158103
CW		 7646 ret = i915_mutex_lock_interruptible(dev);
7647 if (ret)
7648 goto cleanup;
6b95a207 7649
75dfca80 7650 /* Reference the objects for the scheduled work. */
05394f39
CW		 7651 drm_gem_object_reference(&work->old_fb_obj->base);
7652 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7653
7654 crtc->fb = fb;
96b099fd 7655
e1f99ce6 7656 work->pending_flip_obj = obj;
e1f99ce6 7657
4e5359cd
SF		 7658 work->enable_stall_check = true;
7659
b4a98e57 7660 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7661 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7662
8c9f3aaf
JB		 7663 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7664 if (ret)
7665 goto cleanup_pending;
6b95a207 7666
7782de3b 7667 intel_disable_fbc(dev);
c65355bb 7668 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7669 mutex_unlock(&dev->struct_mutex);
7670
e5510fac
JB		 7671 trace_i915_flip_request(intel_crtc->plane, obj);
7672
6b95a207 7673 return 0;
96b099fd 7674
8c9f3aaf 7675cleanup_pending:
b4a98e57 7676 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7677 crtc->fb = old_fb;
05394f39
CW		 7678 drm_gem_object_unreference(&work->old_fb_obj->base);
7679 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7680 mutex_unlock(&dev->struct_mutex);
7681
79158103 7682cleanup:
96b099fd
CW		 7683 spin_lock_irqsave(&dev->event_lock, flags);
7684 intel_crtc->unpin_work = NULL;
7685 spin_unlock_irqrestore(&dev->event_lock, flags);
7686
7317c75e
JB		 7687 drm_vblank_put(dev, intel_crtc->pipe);
7688free_work:
96b099fd
CW		 7689 kfree(work);
7690
7691 return ret;
6b95a207
KH		 7692}
7693
f6e5b160 7694static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7695 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7696 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7697};
7698
50f56119
DV		 7699static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7700 struct drm_crtc *crtc)
7701{
7702 struct drm_device *dev;
7703 struct drm_crtc *tmp;
7704 int crtc_mask = 1;
47f1c6c9 7705
50f56119 7706 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7707
50f56119 7708 dev = crtc->dev;
47f1c6c9 7709
50f56119
DV		 7710 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7711 if (tmp == crtc)
7712 break;
7713 crtc_mask <<= 1;
7714 }
47f1c6c9 7715
50f56119
DV		 7716 if (encoder->possible_crtcs & crtc_mask)
7717 return true;
7718 return false;
47f1c6c9 7719}
79e53945 7720
9a935856
DV		 7721/**
7722 * intel_modeset_update_staged_output_state
7723 *
7724 * Updates the staged output configuration state, e.g. after we've read out the
7725 * current hw state.
7726 */
7727static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7728{
9a935856
DV		 7729 struct intel_encoder *encoder;
7730 struct intel_connector *connector;
f6e5b160 7731
9a935856
DV		 7732 list_for_each_entry(connector, &dev->mode_config.connector_list,
7733 base.head) {
7734 connector->new_encoder =
7735 to_intel_encoder(connector->base.encoder);
7736 }
f6e5b160 7737
9a935856
DV		 7738 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7739 base.head) {
7740 encoder->new_crtc =
7741 to_intel_crtc(encoder->base.crtc);
7742 }
f6e5b160
CW		 7743}
7744
9a935856
DV		 7745/**
7746 * intel_modeset_commit_output_state
7747 *
7748 * This function copies the stage display pipe configuration to the real one.
7749 */
7750static void intel_modeset_commit_output_state(struct drm_device *dev)
7751{
7752 struct intel_encoder *encoder;
7753 struct intel_connector *connector;
f6e5b160 7754
9a935856
DV		 7755 list_for_each_entry(connector, &dev->mode_config.connector_list,
7756 base.head) {
7757 connector->base.encoder = &connector->new_encoder->base;
7758 }
f6e5b160 7759
9a935856
DV		 7760 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7761 base.head) {
7762 encoder->base.crtc = &encoder->new_crtc->base;
7763 }
7764}
7765
050f7aeb
DV		 7766static void
7767connected_sink_compute_bpp(struct intel_connector * connector,
7768 struct intel_crtc_config *pipe_config)
7769{
7770 int bpp = pipe_config->pipe_bpp;
7771
7772 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7773 connector->base.base.id,
7774 drm_get_connector_name(&connector->base));
7775
7776 /* Don't use an invalid EDID bpc value */
7777 if (connector->base.display_info.bpc &&
7778 connector->base.display_info.bpc * 3 < bpp) {
7779 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7780 bpp, connector->base.display_info.bpc*3);
7781 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7782 }
7783
7784 /* Clamp bpp to 8 on screens without EDID 1.4 */
7785 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7786 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7787 bpp);
7788 pipe_config->pipe_bpp = 24;
7789 }
7790}
7791
4e53c2e0 7792static int
050f7aeb
DV		 7793compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7794 struct drm_framebuffer *fb,
7795 struct intel_crtc_config *pipe_config)
4e53c2e0 7796{
050f7aeb
DV		 7797 struct drm_device *dev = crtc->base.dev;
7798 struct intel_connector *connector;
4e53c2e0
DV		 7799 int bpp;
7800
d42264b1
DV		 7801 switch (fb->pixel_format) {
7802 case DRM_FORMAT_C8:
4e53c2e0
DV		 7803 bpp = 8*3; /* since we go through a colormap */
7804 break;
d42264b1
DV		 7805 case DRM_FORMAT_XRGB1555:
7806 case DRM_FORMAT_ARGB1555:
7807 /* checked in intel_framebuffer_init already */
7808 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7809 return -EINVAL;
7810 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7811 bpp = 6*3; /* min is 18bpp */
7812 break;
d42264b1
DV		 7813 case DRM_FORMAT_XBGR8888:
7814 case DRM_FORMAT_ABGR8888:
7815 /* checked in intel_framebuffer_init already */
7816 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7817 return -EINVAL;
7818 case DRM_FORMAT_XRGB8888:
7819 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7820 bpp = 8*3;
7821 break;
d42264b1
DV		 7822 case DRM_FORMAT_XRGB2101010:
7823 case DRM_FORMAT_ARGB2101010:
7824 case DRM_FORMAT_XBGR2101010:
7825 case DRM_FORMAT_ABGR2101010:
7826 /* checked in intel_framebuffer_init already */
7827 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7828 return -EINVAL;
4e53c2e0
DV		 7829 bpp = 10*3;
7830 break;
baba133a 7831 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7832 default:
7833 DRM_DEBUG_KMS("unsupported depth\n");
7834 return -EINVAL;
7835 }
7836
4e53c2e0
DV		 7837 pipe_config->pipe_bpp = bpp;
7838
7839 /* Clamp display bpp to EDID value */
7840 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7841 base.head) {
1b829e05
DV		 7842 if (!connector->new_encoder ||
7843 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7844 continue;
7845
050f7aeb 7846 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7847 }
7848
7849 return bpp;
7850}
7851
c0b03411
DV		 7852static void intel_dump_pipe_config(struct intel_crtc *crtc,
7853 struct intel_crtc_config *pipe_config,
7854 const char *context)
7855{
7856 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7857 context, pipe_name(crtc->pipe));
7858
7859 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7860 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7861 pipe_config->pipe_bpp, pipe_config->dither);
7862 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7863 pipe_config->has_pch_encoder,
7864 pipe_config->fdi_lanes,
7865 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7866 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7867 pipe_config->fdi_m_n.tu);
7868 DRM_DEBUG_KMS("requested mode:\n");
7869 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7870 DRM_DEBUG_KMS("adjusted mode:\n");
7871 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7872 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7873 pipe_config->gmch_pfit.control,
7874 pipe_config->gmch_pfit.pgm_ratios,
7875 pipe_config->gmch_pfit.lvds_border_bits);
7876 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7877 pipe_config->pch_pfit.pos,
7878 pipe_config->pch_pfit.size);
42db64ef 7879 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7880}
7881
accfc0c5
DV		 7882static bool check_encoder_cloning(struct drm_crtc *crtc)
7883{
7884 int num_encoders = 0;
7885 bool uncloneable_encoders = false;
7886 struct intel_encoder *encoder;
7887
7888 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7889 base.head) {
7890 if (&encoder->new_crtc->base != crtc)
7891 continue;
7892
7893 num_encoders++;
7894 if (!encoder->cloneable)
7895 uncloneable_encoders = true;
7896 }
7897
7898 return !(num_encoders > 1 && uncloneable_encoders);
7899}
7900
b8cecdf5
DV		 7901static struct intel_crtc_config *
7902intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7903 struct drm_framebuffer *fb,
b8cecdf5 7904 struct drm_display_mode *mode)
ee7b9f93 7905{
7758a113 7906 struct drm_device *dev = crtc->dev;
7758a113
DV		 7907 struct drm_encoder_helper_funcs *encoder_funcs;
7908 struct intel_encoder *encoder;
b8cecdf5 7909 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7910 int plane_bpp, ret = -EINVAL;
7911 bool retry = true;
ee7b9f93 7912
accfc0c5
DV		 7913 if (!check_encoder_cloning(crtc)) {
7914 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7915 return ERR_PTR(-EINVAL);
7916 }
7917
b8cecdf5
DV		 7918 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7919 if (!pipe_config)
7758a113
DV		 7920 return ERR_PTR(-ENOMEM);
7921
b8cecdf5
DV		 7922 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7923 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 7924 pipe_config->cpu_transcoder =
7925 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 7926 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7927
050f7aeb
DV		 7928 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7929 * plane pixel format and any sink constraints into account. Returns the
7930 * source plane bpp so that dithering can be selected on mismatches
7931 * after encoders and crtc also have had their say. */
7932 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7933 fb, pipe_config);
4e53c2e0
DV		 7934 if (plane_bpp < 0)
7935 goto fail;
7936
e29c22c0 7937encoder_retry:
ef1b460d 7938 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7939 pipe_config->port_clock = 0;
ef1b460d 7940 pipe_config->pixel_multiplier = 1;
ff9a6750 7941
7758a113
DV		 7942 /* Pass our mode to the connectors and the CRTC to give them a chance to
7943 * adjust it according to limitations or connector properties, and also
7944 * a chance to reject the mode entirely.
47f1c6c9 7945 */
7758a113
DV		 7946 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7947 base.head) {
47f1c6c9 7948
7758a113
DV		 7949 if (&encoder->new_crtc->base != crtc)
7950 continue;
7ae89233
DV		 7951
7952 if (encoder->compute_config) {
7953 if (!(encoder->compute_config(encoder, pipe_config))) {
7954 DRM_DEBUG_KMS("Encoder config failure\n");
7955 goto fail;
7956 }
7957
7958 continue;
7959 }
7960
7758a113 7961 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7962 if (!(encoder_funcs->mode_fixup(&encoder->base,
7963 &pipe_config->requested_mode,
7964 &pipe_config->adjusted_mode))) {
7758a113
DV		 7965 DRM_DEBUG_KMS("Encoder fixup failed\n");
7966 goto fail;
7967 }
ee7b9f93 7968 }
47f1c6c9 7969
ff9a6750
DV		 7970 /* Set default port clock if not overwritten by the encoder. Needs to be
7971 * done afterwards in case the encoder adjusts the mode. */
7972 if (!pipe_config->port_clock)
7973 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7974
a43f6e0f 7975 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7976 if (ret < 0) {
7758a113
DV		 7977 DRM_DEBUG_KMS("CRTC fixup failed\n");
7978 goto fail;
ee7b9f93 7979 }
e29c22c0
DV		 7980
7981 if (ret == RETRY) {
7982 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7983 ret = -EINVAL;
7984 goto fail;
7985 }
7986
7987 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7988 retry = false;
7989 goto encoder_retry;
7990 }
7991
4e53c2e0
DV		 7992 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7993 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7994 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7995
b8cecdf5 7996 return pipe_config;
7758a113 7997fail:
b8cecdf5 7998 kfree(pipe_config);
e29c22c0 7999 return ERR_PTR(ret);
ee7b9f93 8000}
47f1c6c9 8001
e2e1ed41
DV		 8002/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8003 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8004static void
8005intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8006 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8007{
8008 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8009 struct drm_device *dev = crtc->dev;
8010 struct intel_encoder *encoder;
8011 struct intel_connector *connector;
8012 struct drm_crtc *tmp_crtc;
79e53945 8013
e2e1ed41 8014 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8015
e2e1ed41
DV		 8016 /* Check which crtcs have changed outputs connected to them, these need
8017 * to be part of the prepare_pipes mask. We don't (yet) support global
8018 * modeset across multiple crtcs, so modeset_pipes will only have one
8019 * bit set at most. */
8020 list_for_each_entry(connector, &dev->mode_config.connector_list,
8021 base.head) {
8022 if (connector->base.encoder == &connector->new_encoder->base)
8023 continue;
79e53945 8024
e2e1ed41
DV		 8025 if (connector->base.encoder) {
8026 tmp_crtc = connector->base.encoder->crtc;
8027
8028 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8029 }
8030
8031 if (connector->new_encoder)
8032 *prepare_pipes |=
8033 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8034 }
8035
e2e1ed41
DV		 8036 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8037 base.head) {
8038 if (encoder->base.crtc == &encoder->new_crtc->base)
8039 continue;
8040
8041 if (encoder->base.crtc) {
8042 tmp_crtc = encoder->base.crtc;
8043
8044 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8045 }
8046
8047 if (encoder->new_crtc)
8048 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8049 }
8050
e2e1ed41
DV		 8051 /* Check for any pipes that will be fully disabled ... */
8052 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8053 base.head) {
8054 bool used = false;
22fd0fab 8055
e2e1ed41
DV		 8056 /* Don't try to disable disabled crtcs. */
8057 if (!intel_crtc->base.enabled)
8058 continue;
7e7d76c3 8059
e2e1ed41
DV		 8060 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8061 base.head) {
8062 if (encoder->new_crtc == intel_crtc)
8063 used = true;
8064 }
8065
8066 if (!used)
8067 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8068 }
8069
e2e1ed41
DV		 8070
8071 /* set_mode is also used to update properties on life display pipes. */
8072 intel_crtc = to_intel_crtc(crtc);
8073 if (crtc->enabled)
8074 *prepare_pipes |= 1 << intel_crtc->pipe;
8075
b6c5164d
DV		 8076 /*
8077 * For simplicity do a full modeset on any pipe where the output routing
8078 * changed. We could be more clever, but that would require us to be
8079 * more careful with calling the relevant encoder->mode_set functions.
8080 */
e2e1ed41
DV		 8081 if (*prepare_pipes)
8082 *modeset_pipes = *prepare_pipes;
8083
8084 /* ... and mask these out. */
8085 *modeset_pipes &= ~(*disable_pipes);
8086 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8087
8088 /*
8089 * HACK: We don't (yet) fully support global modesets. intel_set_config
8090 * obies this rule, but the modeset restore mode of
8091 * intel_modeset_setup_hw_state does not.
8092 */
8093 *modeset_pipes &= 1 << intel_crtc->pipe;
8094 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8095
8096 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8097 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8098}
79e53945 8099
ea9d758d 8100static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8101{
ea9d758d 8102 struct drm_encoder *encoder;
f6e5b160 8103 struct drm_device *dev = crtc->dev;
f6e5b160 8104
ea9d758d
DV		 8105 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8106 if (encoder->crtc == crtc)
8107 return true;
8108
8109 return false;
8110}
8111
8112static void
8113intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8114{
8115 struct intel_encoder *intel_encoder;
8116 struct intel_crtc *intel_crtc;
8117 struct drm_connector *connector;
8118
8119 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8120 base.head) {
8121 if (!intel_encoder->base.crtc)
8122 continue;
8123
8124 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8125
8126 if (prepare_pipes & (1 << intel_crtc->pipe))
8127 intel_encoder->connectors_active = false;
8128 }
8129
8130 intel_modeset_commit_output_state(dev);
8131
8132 /* Update computed state. */
8133 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8134 base.head) {
8135 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8136 }
8137
8138 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8139 if (!connector->encoder || !connector->encoder->crtc)
8140 continue;
8141
8142 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8143
8144 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8145 struct drm_property *dpms_property =
8146 dev->mode_config.dpms_property;
8147
ea9d758d 8148 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8149 drm_object_property_set_value(&connector->base,
68d34720
DV		 8150 dpms_property,
8151 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8152
8153 intel_encoder = to_intel_encoder(connector->encoder);
8154 intel_encoder->connectors_active = true;
8155 }
8156 }
8157
8158}
8159
f1f644dc
JB		 8160static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8161 struct intel_crtc_config *new)
8162{
8163 int clock1, clock2, diff;
8164
8165 clock1 = cur->adjusted_mode.clock;
8166 clock2 = new->adjusted_mode.clock;
8167
8168 if (clock1 == clock2)
8169 return true;
8170
8171 if (!clock1 || !clock2)
8172 return false;
8173
8174 diff = abs(clock1 - clock2);
8175
8176 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8177 return true;
8178
8179 return false;
8180}
8181
25c5b266
DV		 8182#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8183 list_for_each_entry((intel_crtc), \
8184 &(dev)->mode_config.crtc_list, \
8185 base.head) \
0973f18f 8186 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8187
0e8ffe1b 8188static bool
2fa2fe9a
DV		 8189intel_pipe_config_compare(struct drm_device *dev,
8190 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8191 struct intel_crtc_config *pipe_config)
8192{
66e985c0
DV		 8193#define PIPE_CONF_CHECK_X(name) \
8194 if (current_config->name != pipe_config->name) { \
8195 DRM_ERROR("mismatch in " #name " " \
8196 "(expected 0x%08x, found 0x%08x)\n", \
8197 current_config->name, \
8198 pipe_config->name); \
8199 return false; \
8200 }
8201
08a24034
DV		 8202#define PIPE_CONF_CHECK_I(name) \
8203 if (current_config->name != pipe_config->name) { \
8204 DRM_ERROR("mismatch in " #name " " \
8205 "(expected %i, found %i)\n", \
8206 current_config->name, \
8207 pipe_config->name); \
8208 return false; \
88adfff1
DV		 8209 }
8210
1bd1bd80
DV		 8211#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8212 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8213 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8214 "(expected %i, found %i)\n", \
8215 current_config->name & (mask), \
8216 pipe_config->name & (mask)); \
8217 return false; \
8218 }
8219
bb760063
DV		 8220#define PIPE_CONF_QUIRK(quirk) \
8221 ((current_config->quirks | pipe_config->quirks) & (quirk))
8222
eccb140b
DV		 8223 PIPE_CONF_CHECK_I(cpu_transcoder);
8224
08a24034
DV		 8225 PIPE_CONF_CHECK_I(has_pch_encoder);
8226 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8227 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8228 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8229 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8230 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8231 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8232
1bd1bd80
DV		 8233 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8234 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8235 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8236 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8237 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8238 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8239
8240 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8241 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8242 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8243 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8244 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8245 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8246
c93f54cf 8247 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8248
1bd1bd80
DV		 8249 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8250 DRM_MODE_FLAG_INTERLACE);
8251
bb760063
DV		 8252 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8253 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8254 DRM_MODE_FLAG_PHSYNC);
8255 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8256 DRM_MODE_FLAG_NHSYNC);
8257 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8258 DRM_MODE_FLAG_PVSYNC);
8259 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8260 DRM_MODE_FLAG_NVSYNC);
8261 }
045ac3b5 8262
1bd1bd80
DV		 8263 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8264 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8265
2fa2fe9a
DV		 8266 PIPE_CONF_CHECK_I(gmch_pfit.control);
8267 /* pfit ratios are autocomputed by the hw on gen4+ */
8268 if (INTEL_INFO(dev)->gen < 4)
8269 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8270 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8271 PIPE_CONF_CHECK_I(pch_pfit.pos);
8272 PIPE_CONF_CHECK_I(pch_pfit.size);
8273
42db64ef
PZ		 8274 PIPE_CONF_CHECK_I(ips_enabled);
8275
c0d43d62 8276 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8277 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8278 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8279 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8280 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8281
66e985c0 8282#undef PIPE_CONF_CHECK_X
08a24034 8283#undef PIPE_CONF_CHECK_I
1bd1bd80 8284#undef PIPE_CONF_CHECK_FLAGS
bb760063 8285#undef PIPE_CONF_QUIRK
88adfff1 8286
f1f644dc
JB		 8287 if (!IS_HASWELL(dev)) {
8288 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8289 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8290 current_config->adjusted_mode.clock,
8291 pipe_config->adjusted_mode.clock);
8292 return false;
8293 }
8294 }
8295
0e8ffe1b
DV		 8296 return true;
8297}
8298
91d1b4bd
DV		 8299static void
8300check_connector_state(struct drm_device *dev)
8af6cf88 8301{
8af6cf88
DV		 8302 struct intel_connector *connector;
8303
8304 list_for_each_entry(connector, &dev->mode_config.connector_list,
8305 base.head) {
8306 /* This also checks the encoder/connector hw state with the
8307 * ->get_hw_state callbacks. */
8308 intel_connector_check_state(connector);
8309
8310 WARN(&connector->new_encoder->base != connector->base.encoder,
8311 "connector's staged encoder doesn't match current encoder\n");
8312 }
91d1b4bd
DV		 8313}
8314
8315static void
8316check_encoder_state(struct drm_device *dev)
8317{
8318 struct intel_encoder *encoder;
8319 struct intel_connector *connector;
8af6cf88
DV		 8320
8321 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8322 base.head) {
8323 bool enabled = false;
8324 bool active = false;
8325 enum pipe pipe, tracked_pipe;
8326
8327 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8328 encoder->base.base.id,
8329 drm_get_encoder_name(&encoder->base));
8330
8331 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8332 "encoder's stage crtc doesn't match current crtc\n");
8333 WARN(encoder->connectors_active && !encoder->base.crtc,
8334 "encoder's active_connectors set, but no crtc\n");
8335
8336 list_for_each_entry(connector, &dev->mode_config.connector_list,
8337 base.head) {
8338 if (connector->base.encoder != &encoder->base)
8339 continue;
8340 enabled = true;
8341 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8342 active = true;
8343 }
8344 WARN(!!encoder->base.crtc != enabled,
8345 "encoder's enabled state mismatch "
8346 "(expected %i, found %i)\n",
8347 !!encoder->base.crtc, enabled);
8348 WARN(active && !encoder->base.crtc,
8349 "active encoder with no crtc\n");
8350
8351 WARN(encoder->connectors_active != active,
8352 "encoder's computed active state doesn't match tracked active state "
8353 "(expected %i, found %i)\n", active, encoder->connectors_active);
8354
8355 active = encoder->get_hw_state(encoder, &pipe);
8356 WARN(active != encoder->connectors_active,
8357 "encoder's hw state doesn't match sw tracking "
8358 "(expected %i, found %i)\n",
8359 encoder->connectors_active, active);
8360
8361 if (!encoder->base.crtc)
8362 continue;
8363
8364 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8365 WARN(active && pipe != tracked_pipe,
8366 "active encoder's pipe doesn't match"
8367 "(expected %i, found %i)\n",
8368 tracked_pipe, pipe);
8369
8370 }
91d1b4bd
DV		 8371}
8372
8373static void
8374check_crtc_state(struct drm_device *dev)
8375{
8376 drm_i915_private_t *dev_priv = dev->dev_private;
8377 struct intel_crtc *crtc;
8378 struct intel_encoder *encoder;
8379 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8380
8381 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8382 base.head) {
8383 bool enabled = false;
8384 bool active = false;
8385
045ac3b5
JB		 8386 memset(&pipe_config, 0, sizeof(pipe_config));
8387
8af6cf88
DV		 8388 DRM_DEBUG_KMS("[CRTC:%d]\n",
8389 crtc->base.base.id);
8390
8391 WARN(crtc->active && !crtc->base.enabled,
8392 "active crtc, but not enabled in sw tracking\n");
8393
8394 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8395 base.head) {
8396 if (encoder->base.crtc != &crtc->base)
8397 continue;
8398 enabled = true;
8399 if (encoder->connectors_active)
8400 active = true;
8401 }
6c49f241 8402
8af6cf88
DV		 8403 WARN(active != crtc->active,
8404 "crtc's computed active state doesn't match tracked active state "
8405 "(expected %i, found %i)\n", active, crtc->active);
8406 WARN(enabled != crtc->base.enabled,
8407 "crtc's computed enabled state doesn't match tracked enabled state "
8408 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8409
0e8ffe1b
DV		 8410 active = dev_priv->display.get_pipe_config(crtc,
8411 &pipe_config);
d62cf62a
DV		 8412
8413 /* hw state is inconsistent with the pipe A quirk */
8414 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8415 active = crtc->active;
8416
6c49f241
DV		 8417 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8418 base.head) {
8419 if (encoder->base.crtc != &crtc->base)
8420 continue;
510d5f2f 8421 if (encoder->get_config)
6c49f241
DV		 8422 encoder->get_config(encoder, &pipe_config);
8423 }
8424
510d5f2f
JB		 8425 if (dev_priv->display.get_clock)
8426 dev_priv->display.get_clock(crtc, &pipe_config);
8427
0e8ffe1b
DV		 8428 WARN(crtc->active != active,
8429 "crtc active state doesn't match with hw state "
8430 "(expected %i, found %i)\n", crtc->active, active);
8431
c0b03411
DV		 8432 if (active &&
8433 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8434 WARN(1, "pipe state doesn't match!\n");
8435 intel_dump_pipe_config(crtc, &pipe_config,
8436 "[hw state]");
8437 intel_dump_pipe_config(crtc, &crtc->config,
8438 "[sw state]");
8439 }
8af6cf88
DV		 8440 }
8441}
8442
91d1b4bd
DV		 8443static void
8444check_shared_dpll_state(struct drm_device *dev)
8445{
8446 drm_i915_private_t *dev_priv = dev->dev_private;
8447 struct intel_crtc *crtc;
8448 struct intel_dpll_hw_state dpll_hw_state;
8449 int i;
5358901f
DV		 8450
8451 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8452 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8453 int enabled_crtcs = 0, active_crtcs = 0;
8454 bool active;
8455
8456 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8457
8458 DRM_DEBUG_KMS("%s\n", pll->name);
8459
8460 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8461
8462 WARN(pll->active > pll->refcount,
8463 "more active pll users than references: %i vs %i\n",
8464 pll->active, pll->refcount);
8465 WARN(pll->active && !pll->on,
8466 "pll in active use but not on in sw tracking\n");
8467 WARN(pll->on != active,
8468 "pll on state mismatch (expected %i, found %i)\n",
8469 pll->on, active);
8470
8471 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8472 base.head) {
8473 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8474 enabled_crtcs++;
8475 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8476 active_crtcs++;
8477 }
8478 WARN(pll->active != active_crtcs,
8479 "pll active crtcs mismatch (expected %i, found %i)\n",
8480 pll->active, active_crtcs);
8481 WARN(pll->refcount != enabled_crtcs,
8482 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8483 pll->refcount, enabled_crtcs);
66e985c0
DV		 8484
8485 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8486 sizeof(dpll_hw_state)),
8487 "pll hw state mismatch\n");
5358901f 8488 }
8af6cf88
DV		 8489}
8490
91d1b4bd
DV		 8491void
8492intel_modeset_check_state(struct drm_device *dev)
8493{
8494 check_connector_state(dev);
8495 check_encoder_state(dev);
8496 check_crtc_state(dev);
8497 check_shared_dpll_state(dev);
8498}
8499
f30da187
DV		 8500static int __intel_set_mode(struct drm_crtc *crtc,
8501 struct drm_display_mode *mode,
8502 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8503{
8504 struct drm_device *dev = crtc->dev;
dbf2b54e 8505 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8506 struct drm_display_mode *saved_mode, *saved_hwmode;
8507 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8508 struct intel_crtc *intel_crtc;
8509 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8510 int ret = 0;
a6778b3c 8511
3ac18232 8512 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8513 if (!saved_mode)
8514 return -ENOMEM;
3ac18232 8515 saved_hwmode = saved_mode + 1;
a6778b3c 8516
e2e1ed41 8517 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8518 &prepare_pipes, &disable_pipes);
8519
3ac18232
TG		 8520 *saved_hwmode = crtc->hwmode;
8521 *saved_mode = crtc->mode;
a6778b3c 8522
25c5b266
DV		 8523 /* Hack: Because we don't (yet) support global modeset on multiple
8524 * crtcs, we don't keep track of the new mode for more than one crtc.
8525 * Hence simply check whether any bit is set in modeset_pipes in all the
8526 * pieces of code that are not yet converted to deal with mutliple crtcs
8527 * changing their mode at the same time. */
25c5b266 8528 if (modeset_pipes) {
4e53c2e0 8529 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8530 if (IS_ERR(pipe_config)) {
8531 ret = PTR_ERR(pipe_config);
8532 pipe_config = NULL;
8533
3ac18232 8534 goto out;
25c5b266 8535 }
c0b03411
DV		 8536 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8537 "[modeset]");
25c5b266 8538 }
a6778b3c 8539
460da916
DV		 8540 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8541 intel_crtc_disable(&intel_crtc->base);
8542
ea9d758d
DV		 8543 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8544 if (intel_crtc->base.enabled)
8545 dev_priv->display.crtc_disable(&intel_crtc->base);
8546 }
a6778b3c 8547
6c4c86f5
DV		 8548 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8549 * to set it here already despite that we pass it down the callchain.
f6e5b160 8550 */
b8cecdf5 8551 if (modeset_pipes) {
25c5b266 8552 crtc->mode = *mode;
b8cecdf5
DV		 8553 /* mode_set/enable/disable functions rely on a correct pipe
8554 * config. */
8555 to_intel_crtc(crtc)->config = *pipe_config;
8556 }
7758a113 8557
ea9d758d
DV		 8558 /* Only after disabling all output pipelines that will be changed can we
8559 * update the the output configuration. */
8560 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8561
47fab737
DV		 8562 if (dev_priv->display.modeset_global_resources)
8563 dev_priv->display.modeset_global_resources(dev);
8564
a6778b3c
DV		 8565 /* Set up the DPLL and any encoders state that needs to adjust or depend
8566 * on the DPLL.
f6e5b160 8567 */
25c5b266 8568 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8569 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8570 x, y, fb);
8571 if (ret)
8572 goto done;
a6778b3c
DV		 8573 }
8574
8575 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8576 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8577 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8578
25c5b266
DV		 8579 if (modeset_pipes) {
8580 /* Store real post-adjustment hardware mode. */
b8cecdf5 8581 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8582
25c5b266
DV		 8583 /* Calculate and store various constants which
8584 * are later needed by vblank and swap-completion
8585 * timestamping. They are derived from true hwmode.
8586 */
8587 drm_calc_timestamping_constants(crtc);
8588 }
a6778b3c
DV		 8589
8590 /* FIXME: add subpixel order */
8591done:
c0c36b94 8592 if (ret && crtc->enabled) {
3ac18232
TG		 8593 crtc->hwmode = *saved_hwmode;
8594 crtc->mode = *saved_mode;
a6778b3c
DV		 8595 }
8596
3ac18232 8597out:
b8cecdf5 8598 kfree(pipe_config);
3ac18232 8599 kfree(saved_mode);
a6778b3c 8600 return ret;
f6e5b160
CW		 8601}
8602
f30da187
DV		 8603int intel_set_mode(struct drm_crtc *crtc,
8604 struct drm_display_mode *mode,
8605 int x, int y, struct drm_framebuffer *fb)
8606{
8607 int ret;
8608
8609 ret = __intel_set_mode(crtc, mode, x, y, fb);
8610
8611 if (ret == 0)
8612 intel_modeset_check_state(crtc->dev);
8613
8614 return ret;
8615}
8616
c0c36b94
CW		 8617void intel_crtc_restore_mode(struct drm_crtc *crtc)
8618{
8619 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8620}
8621
25c5b266
DV		 8622#undef for_each_intel_crtc_masked
8623
d9e55608
DV		 8624static void intel_set_config_free(struct intel_set_config *config)
8625{
8626 if (!config)
8627 return;
8628
1aa4b628
DV		 8629 kfree(config->save_connector_encoders);
8630 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8631 kfree(config);
8632}
8633
85f9eb71
DV		 8634static int intel_set_config_save_state(struct drm_device *dev,
8635 struct intel_set_config *config)
8636{
85f9eb71
DV		 8637 struct drm_encoder *encoder;
8638 struct drm_connector *connector;
8639 int count;
8640
1aa4b628
DV		 8641 config->save_encoder_crtcs =
8642 kcalloc(dev->mode_config.num_encoder,
8643 sizeof(struct drm_crtc *), GFP_KERNEL);
8644 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8645 return -ENOMEM;
8646
1aa4b628
DV		 8647 config->save_connector_encoders =
8648 kcalloc(dev->mode_config.num_connector,
8649 sizeof(struct drm_encoder *), GFP_KERNEL);
8650 if (!config->save_connector_encoders)
85f9eb71
DV		 8651 return -ENOMEM;
8652
8653 /* Copy data. Note that driver private data is not affected.
8654 * Should anything bad happen only the expected state is
8655 * restored, not the drivers personal bookkeeping.
8656 */
85f9eb71
DV		 8657 count = 0;
8658 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8659 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8660 }
8661
8662 count = 0;
8663 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8664 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8665 }
8666
8667 return 0;
8668}
8669
8670static void intel_set_config_restore_state(struct drm_device *dev,
8671 struct intel_set_config *config)
8672{
9a935856
DV		 8673 struct intel_encoder *encoder;
8674 struct intel_connector *connector;
85f9eb71
DV		 8675 int count;
8676
85f9eb71 8677 count = 0;
9a935856
DV		 8678 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8679 encoder->new_crtc =
8680 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8681 }
8682
8683 count = 0;
9a935856
DV		 8684 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8685 connector->new_encoder =
8686 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8687 }
8688}
8689
e3de42b6
ID		 8690static bool
8691is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8692 int num_connectors)
8693{
8694 int i;
8695
8696 for (i = 0; i < num_connectors; i++)
8697 if (connectors[i].encoder &&
8698 connectors[i].encoder->crtc == crtc &&
8699 connectors[i].dpms != DRM_MODE_DPMS_ON)
8700 return true;
8701
8702 return false;
8703}
8704
5e2b584e
DV		 8705static void
8706intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8707 struct intel_set_config *config)
8708{
8709
8710 /* We should be able to check here if the fb has the same properties
8711 * and then just flip_or_move it */
e3de42b6
ID		 8712 if (set->connectors != NULL &&
8713 is_crtc_connector_off(set->crtc, *set->connectors,
8714 set->num_connectors)) {
8715 config->mode_changed = true;
8716 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8717 /* If we have no fb then treat it as a full mode set */
8718 if (set->crtc->fb == NULL) {
319d9827
JB		 8719 struct intel_crtc *intel_crtc =
8720 to_intel_crtc(set->crtc);
8721
8722 if (intel_crtc->active && i915_fastboot) {
8723 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8724 config->fb_changed = true;
8725 } else {
8726 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8727 config->mode_changed = true;
8728 }
5e2b584e
DV		 8729 } else if (set->fb == NULL) {
8730 config->mode_changed = true;
72f4901e
DV		 8731 } else if (set->fb->pixel_format !=
8732 set->crtc->fb->pixel_format) {
5e2b584e 8733 config->mode_changed = true;
e3de42b6 8734 } else {
5e2b584e 8735 config->fb_changed = true;
e3de42b6 8736 }
5e2b584e
DV		 8737 }
8738
835c5873 8739 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8740 config->fb_changed = true;
8741
8742 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8743 DRM_DEBUG_KMS("modes are different, full mode set\n");
8744 drm_mode_debug_printmodeline(&set->crtc->mode);
8745 drm_mode_debug_printmodeline(set->mode);
8746 config->mode_changed = true;
8747 }
8748}
8749
2e431051 8750static int
9a935856
DV		 8751intel_modeset_stage_output_state(struct drm_device *dev,
8752 struct drm_mode_set *set,
8753 struct intel_set_config *config)
50f56119 8754{
85f9eb71 8755 struct drm_crtc *new_crtc;
9a935856
DV		 8756 struct intel_connector *connector;
8757 struct intel_encoder *encoder;
2e431051 8758 int count, ro;
50f56119 8759
9abdda74 8760 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8761 * of connectors. For paranoia, double-check this. */
8762 WARN_ON(!set->fb && (set->num_connectors != 0));
8763 WARN_ON(set->fb && (set->num_connectors == 0));
8764
50f56119 8765 count = 0;
9a935856
DV		 8766 list_for_each_entry(connector, &dev->mode_config.connector_list,
8767 base.head) {
8768 /* Otherwise traverse passed in connector list and get encoders
8769 * for them. */
50f56119 8770 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8771 if (set->connectors[ro] == &connector->base) {
8772 connector->new_encoder = connector->encoder;
50f56119
DV		 8773 break;
8774 }
8775 }
8776
9a935856
DV		 8777 /* If we disable the crtc, disable all its connectors. Also, if
8778 * the connector is on the changing crtc but not on the new
8779 * connector list, disable it. */
8780 if ((!set->fb || ro == set->num_connectors) &&
8781 connector->base.encoder &&
8782 connector->base.encoder->crtc == set->crtc) {
8783 connector->new_encoder = NULL;
8784
8785 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8786 connector->base.base.id,
8787 drm_get_connector_name(&connector->base));
8788 }
8789
8790
8791 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8792 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8793 config->mode_changed = true;
50f56119
DV		 8794 }
8795 }
9a935856 8796 /* connector->new_encoder is now updated for all connectors. */
50f56119 8797
9a935856 8798 /* Update crtc of enabled connectors. */
50f56119 8799 count = 0;
9a935856
DV		 8800 list_for_each_entry(connector, &dev->mode_config.connector_list,
8801 base.head) {
8802 if (!connector->new_encoder)
50f56119
DV		 8803 continue;
8804
9a935856 8805 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8806
8807 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8808 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8809 new_crtc = set->crtc;
8810 }
8811
8812 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8813 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8814 new_crtc)) {
5e2b584e 8815 return -EINVAL;
50f56119 8816 }
9a935856
DV		 8817 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8818
8819 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8820 connector->base.base.id,
8821 drm_get_connector_name(&connector->base),
8822 new_crtc->base.id);
8823 }
8824
8825 /* Check for any encoders that needs to be disabled. */
8826 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8827 base.head) {
8828 list_for_each_entry(connector,
8829 &dev->mode_config.connector_list,
8830 base.head) {
8831 if (connector->new_encoder == encoder) {
8832 WARN_ON(!connector->new_encoder->new_crtc);
8833
8834 goto next_encoder;
8835 }
8836 }
8837 encoder->new_crtc = NULL;
8838next_encoder:
8839 /* Only now check for crtc changes so we don't miss encoders
8840 * that will be disabled. */
8841 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8842 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8843 config->mode_changed = true;
50f56119
DV		 8844 }
8845 }
9a935856 8846 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8847
2e431051
DV		 8848 return 0;
8849}
8850
8851static int intel_crtc_set_config(struct drm_mode_set *set)
8852{
8853 struct drm_device *dev;
2e431051
DV		 8854 struct drm_mode_set save_set;
8855 struct intel_set_config *config;
8856 int ret;
2e431051 8857
8d3e375e
DV		 8858 BUG_ON(!set);
8859 BUG_ON(!set->crtc);
8860 BUG_ON(!set->crtc->helper_private);
2e431051 8861
7e53f3a4
DV		 8862 /* Enforce sane interface api - has been abused by the fb helper. */
8863 BUG_ON(!set->mode && set->fb);
8864 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8865
2e431051
DV		 8866 if (set->fb) {
8867 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8868 set->crtc->base.id, set->fb->base.id,
8869 (int)set->num_connectors, set->x, set->y);
8870 } else {
8871 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8872 }
8873
8874 dev = set->crtc->dev;
8875
8876 ret = -ENOMEM;
8877 config = kzalloc(sizeof(*config), GFP_KERNEL);
8878 if (!config)
8879 goto out_config;
8880
8881 ret = intel_set_config_save_state(dev, config);
8882 if (ret)
8883 goto out_config;
8884
8885 save_set.crtc = set->crtc;
8886 save_set.mode = &set->crtc->mode;
8887 save_set.x = set->crtc->x;
8888 save_set.y = set->crtc->y;
8889 save_set.fb = set->crtc->fb;
8890
8891 /* Compute whether we need a full modeset, only an fb base update or no
8892 * change at all. In the future we might also check whether only the
8893 * mode changed, e.g. for LVDS where we only change the panel fitter in
8894 * such cases. */
8895 intel_set_config_compute_mode_changes(set, config);
8896
9a935856 8897 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8898 if (ret)
8899 goto fail;
8900
5e2b584e 8901 if (config->mode_changed) {
c0c36b94
CW		 8902 ret = intel_set_mode(set->crtc, set->mode,
8903 set->x, set->y, set->fb);
5e2b584e 8904 } else if (config->fb_changed) {
4878cae2
VS		 8905 intel_crtc_wait_for_pending_flips(set->crtc);
8906
4f660f49 8907 ret = intel_pipe_set_base(set->crtc,
94352cf9 8908 set->x, set->y, set->fb);
50f56119
DV		 8909 }
8910
2d05eae1 8911 if (ret) {
bf67dfeb
DV		 8912 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8913 set->crtc->base.id, ret);
50f56119 8914fail:
2d05eae1 8915 intel_set_config_restore_state(dev, config);
50f56119 8916
2d05eae1
CW		 8917 /* Try to restore the config */
8918 if (config->mode_changed &&
8919 intel_set_mode(save_set.crtc, save_set.mode,
8920 save_set.x, save_set.y, save_set.fb))
8921 DRM_ERROR("failed to restore config after modeset failure\n");
8922 }
50f56119 8923
d9e55608
DV		 8924out_config:
8925 intel_set_config_free(config);
50f56119
DV		 8926 return ret;
8927}
f6e5b160
CW		 8928
8929static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8930 .cursor_set = intel_crtc_cursor_set,
8931 .cursor_move = intel_crtc_cursor_move,
8932 .gamma_set = intel_crtc_gamma_set,
50f56119 8933 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8934 .destroy = intel_crtc_destroy,
8935 .page_flip = intel_crtc_page_flip,
8936};
8937
79f689aa
PZ		 8938static void intel_cpu_pll_init(struct drm_device *dev)
8939{
affa9354 8940 if (HAS_DDI(dev))
79f689aa
PZ		 8941 intel_ddi_pll_init(dev);
8942}
8943
5358901f
DV		 8944static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8945 struct intel_shared_dpll *pll,
8946 struct intel_dpll_hw_state *hw_state)
ee7b9f93 8947{
5358901f 8948 uint32_t val;
ee7b9f93 8949
5358901f 8950 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 8951 hw_state->dpll = val;
8952 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8953 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 8954
8955 return val & DPLL_VCO_ENABLE;
8956}
8957
15bdd4cf
DV		 8958static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8959 struct intel_shared_dpll *pll)
8960{
8961 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8962 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8963}
8964
e7b903d2
DV		 8965static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8966 struct intel_shared_dpll *pll)
8967{
e7b903d2
DV		 8968 /* PCH refclock must be enabled first */
8969 assert_pch_refclk_enabled(dev_priv);
8970
15bdd4cf
DV		 8971 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8972
8973 /* Wait for the clocks to stabilize. */
8974 POSTING_READ(PCH_DPLL(pll->id));
8975 udelay(150);
8976
8977 /* The pixel multiplier can only be updated once the
8978 * DPLL is enabled and the clocks are stable.
8979 *
8980 * So write it again.
8981 */
8982 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8983 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8984 udelay(200);
8985}
8986
8987static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8988 struct intel_shared_dpll *pll)
8989{
8990 struct drm_device *dev = dev_priv->dev;
8991 struct intel_crtc *crtc;
e7b903d2
DV		 8992
8993 /* Make sure no transcoder isn't still depending on us. */
8994 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8995 if (intel_crtc_to_shared_dpll(crtc) == pll)
8996 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 8997 }
8998
15bdd4cf
DV		 8999 I915_WRITE(PCH_DPLL(pll->id), 0);
9000 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9001 udelay(200);
9002}
9003
46edb027
DV		 9004static char *ibx_pch_dpll_names[] = {
9005 "PCH DPLL A",
9006 "PCH DPLL B",
9007};
9008
7c74ade1 9009static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9010{
e7b903d2 9011 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9012 int i;
9013
7c74ade1 9014 dev_priv->num_shared_dpll = 2;
ee7b9f93 9015
e72f9fbf 9016 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9017 dev_priv->shared_dplls[i].id = i;
9018 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9019 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9020 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9021 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9022 dev_priv->shared_dplls[i].get_hw_state =
9023 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9024 }
9025}
9026
7c74ade1
DV		 9027static void intel_shared_dpll_init(struct drm_device *dev)
9028{
e7b903d2 9029 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9030
9031 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9032 ibx_pch_dpll_init(dev);
9033 else
9034 dev_priv->num_shared_dpll = 0;
9035
9036 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9037 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9038 dev_priv->num_shared_dpll);
9039}
9040
b358d0a6 9041static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9042{
22fd0fab 9043 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9044 struct intel_crtc *intel_crtc;
9045 int i;
9046
9047 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9048 if (intel_crtc == NULL)
9049 return;
9050
9051 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9052
9053 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9054 for (i = 0; i < 256; i++) {
9055 intel_crtc->lut_r[i] = i;
9056 intel_crtc->lut_g[i] = i;
9057 intel_crtc->lut_b[i] = i;
9058 }
9059
80824003
JB		 9060 /* Swap pipes & planes for FBC on pre-965 */
9061 intel_crtc->pipe = pipe;
9062 intel_crtc->plane = pipe;
e2e767ab 9063 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9064 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9065 intel_crtc->plane = !pipe;
80824003
JB		 9066 }
9067
22fd0fab
JB		 9068 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9069 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9070 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9071 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9072
79e53945 9073 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9074}
9075
08d7b3d1 9076int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9077 struct drm_file *file)
08d7b3d1 9078{
08d7b3d1 9079 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9080 struct drm_mode_object *drmmode_obj;
9081 struct intel_crtc *crtc;
08d7b3d1 9082
1cff8f6b
DV		 9083 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9084 return -ENODEV;
08d7b3d1 9085
c05422d5
DV		 9086 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9087 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9088
c05422d5 9089 if (!drmmode_obj) {
08d7b3d1
CW		 9090 DRM_ERROR("no such CRTC id\n");
9091 return -EINVAL;
9092 }
9093
c05422d5
DV		 9094 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9095 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9096
c05422d5 9097 return 0;
08d7b3d1
CW		 9098}
9099
66a9278e 9100static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9101{
66a9278e
DV		 9102 struct drm_device *dev = encoder->base.dev;
9103 struct intel_encoder *source_encoder;
79e53945 9104 int index_mask = 0;
79e53945
JB		 9105 int entry = 0;
9106
66a9278e
DV		 9107 list_for_each_entry(source_encoder,
9108 &dev->mode_config.encoder_list, base.head) {
9109
9110 if (encoder == source_encoder)
79e53945 9111 index_mask |= (1 << entry);
66a9278e
DV		 9112
9113 /* Intel hw has only one MUX where enocoders could be cloned. */
9114 if (encoder->cloneable && source_encoder->cloneable)
9115 index_mask |= (1 << entry);
9116
79e53945
JB		 9117 entry++;
9118 }
4ef69c7a 9119
79e53945
JB		 9120 return index_mask;
9121}
9122
4d302442
CW		 9123static bool has_edp_a(struct drm_device *dev)
9124{
9125 struct drm_i915_private *dev_priv = dev->dev_private;
9126
9127 if (!IS_MOBILE(dev))
9128 return false;
9129
9130 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9131 return false;
9132
9133 if (IS_GEN5(dev) &&
9134 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9135 return false;
9136
9137 return true;
9138}
9139
79e53945
JB		 9140static void intel_setup_outputs(struct drm_device *dev)
9141{
725e30ad 9142 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9143 struct intel_encoder *encoder;
cb0953d7 9144 bool dpd_is_edp = false;
79e53945 9145
c9093354 9146 intel_lvds_init(dev);
79e53945 9147
c40c0f5b 9148 if (!IS_ULT(dev))
79935fca 9149 intel_crt_init(dev);
cb0953d7 9150
affa9354 9151 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9152 int found;
9153
9154 /* Haswell uses DDI functions to detect digital outputs */
9155 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9156 /* DDI A only supports eDP */
9157 if (found)
9158 intel_ddi_init(dev, PORT_A);
9159
9160 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9161 * register */
9162 found = I915_READ(SFUSE_STRAP);
9163
9164 if (found & SFUSE_STRAP_DDIB_DETECTED)
9165 intel_ddi_init(dev, PORT_B);
9166 if (found & SFUSE_STRAP_DDIC_DETECTED)
9167 intel_ddi_init(dev, PORT_C);
9168 if (found & SFUSE_STRAP_DDID_DETECTED)
9169 intel_ddi_init(dev, PORT_D);
9170 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9171 int found;
270b3042
DV		 9172 dpd_is_edp = intel_dpd_is_edp(dev);
9173
9174 if (has_edp_a(dev))
9175 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9176
dc0fa718 9177 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9178 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9179 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9180 if (!found)
e2debe91 9181 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9182 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9183 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9184 }
9185
dc0fa718 9186 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9187 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9188
dc0fa718 9189 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9190 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9191
5eb08b69 9192 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9193 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9194
270b3042 9195 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9196 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9197 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9198 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9199 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9200 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9201
dc0fa718 9202 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9203 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9204 PORT_B);
67cfc203
VS		 9205 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9206 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9207 }
103a196f 9208 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9209 bool found = false;
7d57382e 9210
e2debe91 9211 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9212 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9213 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9214 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9215 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9216 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9217 }
27185ae1 9218
e7281eab 9219 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9220 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9221 }
13520b05
KH		 9222
9223 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9224
e2debe91 9225 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9226 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9227 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9228 }
27185ae1 9229
e2debe91 9230 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9231
b01f2c3a
JB		 9232 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9233 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9234 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9235 }
e7281eab 9236 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9237 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9238 }
27185ae1 9239
b01f2c3a 9240 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9241 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9242 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9243 } else if (IS_GEN2(dev))
79e53945
JB		 9244 intel_dvo_init(dev);
9245
103a196f 9246 if (SUPPORTS_TV(dev))
79e53945
JB		 9247 intel_tv_init(dev);
9248
4ef69c7a
CW		 9249 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9250 encoder->base.possible_crtcs = encoder->crtc_mask;
9251 encoder->base.possible_clones =
66a9278e 9252 intel_encoder_clones(encoder);
79e53945 9253 }
47356eb6 9254
dde86e2d 9255 intel_init_pch_refclk(dev);
270b3042
DV		 9256
9257 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9258}
9259
9260static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9261{
9262 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9263
9264 drm_framebuffer_cleanup(fb);
05394f39 9265 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9266
9267 kfree(intel_fb);
9268}
9269
9270static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9271 struct drm_file *file,
79e53945
JB		 9272 unsigned int *handle)
9273{
9274 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9275 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9276
05394f39 9277 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9278}
9279
9280static const struct drm_framebuffer_funcs intel_fb_funcs = {
9281 .destroy = intel_user_framebuffer_destroy,
9282 .create_handle = intel_user_framebuffer_create_handle,
9283};
9284
38651674
DA		 9285int intel_framebuffer_init(struct drm_device *dev,
9286 struct intel_framebuffer *intel_fb,
308e5bcb 9287 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9288 struct drm_i915_gem_object *obj)
79e53945 9289{
a35cdaa0 9290 int pitch_limit;
79e53945
JB		 9291 int ret;
9292
c16ed4be
CW		 9293 if (obj->tiling_mode == I915_TILING_Y) {
9294 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9295 return -EINVAL;
c16ed4be 9296 }
57cd6508 9297
c16ed4be
CW		 9298 if (mode_cmd->pitches[0] & 63) {
9299 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9300 mode_cmd->pitches[0]);
57cd6508 9301 return -EINVAL;
c16ed4be 9302 }
57cd6508 9303
a35cdaa0
CW		 9304 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9305 pitch_limit = 32*1024;
9306 } else if (INTEL_INFO(dev)->gen >= 4) {
9307 if (obj->tiling_mode)
9308 pitch_limit = 16*1024;
9309 else
9310 pitch_limit = 32*1024;
9311 } else if (INTEL_INFO(dev)->gen >= 3) {
9312 if (obj->tiling_mode)
9313 pitch_limit = 8*1024;
9314 else
9315 pitch_limit = 16*1024;
9316 } else
9317 /* XXX DSPC is limited to 4k tiled */
9318 pitch_limit = 8*1024;
9319
9320 if (mode_cmd->pitches[0] > pitch_limit) {
9321 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9322 obj->tiling_mode ? "tiled" : "linear",
9323 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9324 return -EINVAL;
c16ed4be 9325 }
5d7bd705
VS		 9326
9327 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9328 mode_cmd->pitches[0] != obj->stride) {
9329 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9330 mode_cmd->pitches[0], obj->stride);
5d7bd705 9331 return -EINVAL;
c16ed4be 9332 }
5d7bd705 9333
57779d06 9334 /* Reject formats not supported by any plane early. */
308e5bcb 9335 switch (mode_cmd->pixel_format) {
57779d06 9336 case DRM_FORMAT_C8:
04b3924d
VS		 9337 case DRM_FORMAT_RGB565:
9338 case DRM_FORMAT_XRGB8888:
9339 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9340 break;
9341 case DRM_FORMAT_XRGB1555:
9342 case DRM_FORMAT_ARGB1555:
c16ed4be 9343 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9344 DRM_DEBUG("unsupported pixel format: %s\n",
9345 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9346 return -EINVAL;
c16ed4be 9347 }
57779d06
VS		 9348 break;
9349 case DRM_FORMAT_XBGR8888:
9350 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9351 case DRM_FORMAT_XRGB2101010:
9352 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9353 case DRM_FORMAT_XBGR2101010:
9354 case DRM_FORMAT_ABGR2101010:
c16ed4be 9355 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9356 DRM_DEBUG("unsupported pixel format: %s\n",
9357 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9358 return -EINVAL;
c16ed4be 9359 }
b5626747 9360 break;
04b3924d
VS		 9361 case DRM_FORMAT_YUYV:
9362 case DRM_FORMAT_UYVY:
9363 case DRM_FORMAT_YVYU:
9364 case DRM_FORMAT_VYUY:
c16ed4be 9365 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9366 DRM_DEBUG("unsupported pixel format: %s\n",
9367 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9368 return -EINVAL;
c16ed4be 9369 }
57cd6508
CW		 9370 break;
9371 default:
4ee62c76
VS		 9372 DRM_DEBUG("unsupported pixel format: %s\n",
9373 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9374 return -EINVAL;
9375 }
9376
90f9a336
VS		 9377 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9378 if (mode_cmd->offsets[0] != 0)
9379 return -EINVAL;
9380
c7d73f6a
DV		 9381 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9382 intel_fb->obj = obj;
9383
79e53945
JB		 9384 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9385 if (ret) {
9386 DRM_ERROR("framebuffer init failed %d\n", ret);
9387 return ret;
9388 }
9389
79e53945
JB		 9390 return 0;
9391}
9392
79e53945
JB		 9393static struct drm_framebuffer *
9394intel_user_framebuffer_create(struct drm_device *dev,
9395 struct drm_file *filp,
308e5bcb 9396 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9397{
05394f39 9398 struct drm_i915_gem_object *obj;
79e53945 9399
308e5bcb
JB		 9400 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9401 mode_cmd->handles[0]));
c8725226 9402 if (&obj->base == NULL)
cce13ff7 9403 return ERR_PTR(-ENOENT);
79e53945 9404
d2dff872 9405 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9406}
9407
79e53945 9408static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9409 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9410 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9411};
9412
e70236a8
JB		 9413/* Set up chip specific display functions */
9414static void intel_init_display(struct drm_device *dev)
9415{
9416 struct drm_i915_private *dev_priv = dev->dev_private;
9417
ee9300bb
DV		 9418 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9419 dev_priv->display.find_dpll = g4x_find_best_dpll;
9420 else if (IS_VALLEYVIEW(dev))
9421 dev_priv->display.find_dpll = vlv_find_best_dpll;
9422 else if (IS_PINEVIEW(dev))
9423 dev_priv->display.find_dpll = pnv_find_best_dpll;
9424 else
9425 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9426
affa9354 9427 if (HAS_DDI(dev)) {
0e8ffe1b 9428 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9429 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9430 dev_priv->display.crtc_enable = haswell_crtc_enable;
9431 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9432 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9433 dev_priv->display.update_plane = ironlake_update_plane;
9434 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9435 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9436 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9437 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9438 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9439 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9440 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9441 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9442 } else if (IS_VALLEYVIEW(dev)) {
9443 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9444 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9445 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9446 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9447 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9448 dev_priv->display.off = i9xx_crtc_off;
9449 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9450 } else {
0e8ffe1b 9451 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9452 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9453 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9454 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9455 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9456 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9457 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9458 }
e70236a8 9459
e70236a8 9460 /* Returns the core display clock speed */
25eb05fc
JB		 9461 if (IS_VALLEYVIEW(dev))
9462 dev_priv->display.get_display_clock_speed =
9463 valleyview_get_display_clock_speed;
9464 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9465 dev_priv->display.get_display_clock_speed =
9466 i945_get_display_clock_speed;
9467 else if (IS_I915G(dev))
9468 dev_priv->display.get_display_clock_speed =
9469 i915_get_display_clock_speed;
f2b115e6 9470 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9471 dev_priv->display.get_display_clock_speed =
9472 i9xx_misc_get_display_clock_speed;
9473 else if (IS_I915GM(dev))
9474 dev_priv->display.get_display_clock_speed =
9475 i915gm_get_display_clock_speed;
9476 else if (IS_I865G(dev))
9477 dev_priv->display.get_display_clock_speed =
9478 i865_get_display_clock_speed;
f0f8a9ce 9479 else if (IS_I85X(dev))
e70236a8
JB		 9480 dev_priv->display.get_display_clock_speed =
9481 i855_get_display_clock_speed;
9482 else /* 852, 830 */
9483 dev_priv->display.get_display_clock_speed =
9484 i830_get_display_clock_speed;
9485
7f8a8569 9486 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9487 if (IS_GEN5(dev)) {
674cf967 9488 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9489 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9490 } else if (IS_GEN6(dev)) {
674cf967 9491 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9492 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9493 } else if (IS_IVYBRIDGE(dev)) {
9494 /* FIXME: detect B0+ stepping and use auto training */
9495 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9496 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9497 dev_priv->display.modeset_global_resources =
9498 ivb_modeset_global_resources;
c82e4d26
ED		 9499 } else if (IS_HASWELL(dev)) {
9500 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9501 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9502 dev_priv->display.modeset_global_resources =
9503 haswell_modeset_global_resources;
a0e63c22 9504 }
6067aaea 9505 } else if (IS_G4X(dev)) {
e0dac65e 9506 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9507 }
8c9f3aaf
JB		 9508
9509 /* Default just returns -ENODEV to indicate unsupported */
9510 dev_priv->display.queue_flip = intel_default_queue_flip;
9511
9512 switch (INTEL_INFO(dev)->gen) {
9513 case 2:
9514 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9515 break;
9516
9517 case 3:
9518 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9519 break;
9520
9521 case 4:
9522 case 5:
9523 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9524 break;
9525
9526 case 6:
9527 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9528 break;
7c9017e5
JB		 9529 case 7:
9530 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9531 break;
8c9f3aaf 9532 }
e70236a8
JB		 9533}
9534
b690e96c
JB		 9535/*
9536 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9537 * resume, or other times. This quirk makes sure that's the case for
9538 * affected systems.
9539 */
0206e353 9540static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9541{
9542 struct drm_i915_private *dev_priv = dev->dev_private;
9543
9544 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9545 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9546}
9547
435793df
KP		 9548/*
9549 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9550 */
9551static void quirk_ssc_force_disable(struct drm_device *dev)
9552{
9553 struct drm_i915_private *dev_priv = dev->dev_private;
9554 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9555 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9556}
9557
4dca20ef 9558/*
5a15ab5b
CE		 9559 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9560 * brightness value
4dca20ef
CE		 9561 */
9562static void quirk_invert_brightness(struct drm_device *dev)
9563{
9564 struct drm_i915_private *dev_priv = dev->dev_private;
9565 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9566 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9567}
9568
b690e96c
JB		 9569struct intel_quirk {
9570 int device;
9571 int subsystem_vendor;
9572 int subsystem_device;
9573 void (*hook)(struct drm_device *dev);
9574};
9575
5f85f176
EE		 9576/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9577struct intel_dmi_quirk {
9578 void (*hook)(struct drm_device *dev);
9579 const struct dmi_system_id (*dmi_id_list)[];
9580};
9581
9582static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9583{
9584 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9585 return 1;
9586}
9587
9588static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9589 {
9590 .dmi_id_list = &(const struct dmi_system_id[]) {
9591 {
9592 .callback = intel_dmi_reverse_brightness,
9593 .ident = "NCR Corporation",
9594 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9595 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9596 },
9597 },
9598 { } /* terminating entry */
9599 },
9600 .hook = quirk_invert_brightness,
9601 },
9602};
9603
c43b5634 9604static struct intel_quirk intel_quirks[] = {
b690e96c 9605 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9606 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9607
b690e96c
JB		 9608 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9609 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9610
b690e96c
JB		 9611 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9612 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9613
ccd0d36e 9614 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9615 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9616 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9617
9618 /* Lenovo U160 cannot use SSC on LVDS */
9619 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9620
9621 /* Sony Vaio Y cannot use SSC on LVDS */
9622 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9623
9624 /* Acer Aspire 5734Z must invert backlight brightness */
9625 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9626
9627 /* Acer/eMachines G725 */
9628 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9629
9630 /* Acer/eMachines e725 */
9631 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9632
9633 /* Acer/Packard Bell NCL20 */
9634 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9635
9636 /* Acer Aspire 4736Z */
9637 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9638};
9639
9640static void intel_init_quirks(struct drm_device *dev)
9641{
9642 struct pci_dev *d = dev->pdev;
9643 int i;
9644
9645 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9646 struct intel_quirk *q = &intel_quirks[i];
9647
9648 if (d->device == q->device &&
9649 (d->subsystem_vendor == q->subsystem_vendor ||
9650 q->subsystem_vendor == PCI_ANY_ID) &&
9651 (d->subsystem_device == q->subsystem_device ||
9652 q->subsystem_device == PCI_ANY_ID))
9653 q->hook(dev);
9654 }
5f85f176
EE		 9655 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9656 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9657 intel_dmi_quirks[i].hook(dev);
9658 }
b690e96c
JB		 9659}
9660
9cce37f4
JB		 9661/* Disable the VGA plane that we never use */
9662static void i915_disable_vga(struct drm_device *dev)
9663{
9664 struct drm_i915_private *dev_priv = dev->dev_private;
9665 u8 sr1;
766aa1c4 9666 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9667
9668 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9669 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9670 sr1 = inb(VGA_SR_DATA);
9671 outb(sr1 | 1<<5, VGA_SR_DATA);
9672 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9673 udelay(300);
9674
9675 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9676 POSTING_READ(vga_reg);
9677}
9678
f817586c
DV		 9679void intel_modeset_init_hw(struct drm_device *dev)
9680{
fa42e23c 9681 intel_init_power_well(dev);
0232e927 9682
a8f78b58
ED		 9683 intel_prepare_ddi(dev);
9684
f817586c
DV		 9685 intel_init_clock_gating(dev);
9686
79f5b2c7 9687 mutex_lock(&dev->struct_mutex);
8090c6b9 9688 intel_enable_gt_powersave(dev);
79f5b2c7 9689 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9690}
9691
7d708ee4
ID		 9692void intel_modeset_suspend_hw(struct drm_device *dev)
9693{
9694 intel_suspend_hw(dev);
9695}
9696
79e53945
JB		 9697void intel_modeset_init(struct drm_device *dev)
9698{
652c393a 9699 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9700 int i, j, ret;
79e53945
JB		 9701
9702 drm_mode_config_init(dev);
9703
9704 dev->mode_config.min_width = 0;
9705 dev->mode_config.min_height = 0;
9706
019d96cb
DA		 9707 dev->mode_config.preferred_depth = 24;
9708 dev->mode_config.prefer_shadow = 1;
9709
e6ecefaa 9710 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9711
b690e96c
JB		 9712 intel_init_quirks(dev);
9713
1fa61106
ED		 9714 intel_init_pm(dev);
9715
e3c74757
BW		 9716 if (INTEL_INFO(dev)->num_pipes == 0)
9717 return;
9718
e70236a8
JB		 9719 intel_init_display(dev);
9720
a6c45cf0
CW		 9721 if (IS_GEN2(dev)) {
9722 dev->mode_config.max_width = 2048;
9723 dev->mode_config.max_height = 2048;
9724 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9725 dev->mode_config.max_width = 4096;
9726 dev->mode_config.max_height = 4096;
79e53945 9727 } else {
a6c45cf0
CW		 9728 dev->mode_config.max_width = 8192;
9729 dev->mode_config.max_height = 8192;
79e53945 9730 }
5d4545ae 9731 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9732
28c97730 9733 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9734 INTEL_INFO(dev)->num_pipes,
9735 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9736
08e2a7de 9737 for_each_pipe(i) {
79e53945 9738 intel_crtc_init(dev, i);
7f1f3851
JB		 9739 for (j = 0; j < dev_priv->num_plane; j++) {
9740 ret = intel_plane_init(dev, i, j);
9741 if (ret)
06da8da2
VS		 9742 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9743 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9744 }
79e53945
JB		 9745 }
9746
79f689aa 9747 intel_cpu_pll_init(dev);
e72f9fbf 9748 intel_shared_dpll_init(dev);
ee7b9f93 9749
9cce37f4
JB		 9750 /* Just disable it once at startup */
9751 i915_disable_vga(dev);
79e53945 9752 intel_setup_outputs(dev);
11be49eb
CW		 9753
9754 /* Just in case the BIOS is doing something questionable. */
9755 intel_disable_fbc(dev);
2c7111db
CW		 9756}
9757
24929352
DV		 9758static void
9759intel_connector_break_all_links(struct intel_connector *connector)
9760{
9761 connector->base.dpms = DRM_MODE_DPMS_OFF;
9762 connector->base.encoder = NULL;
9763 connector->encoder->connectors_active = false;
9764 connector->encoder->base.crtc = NULL;
9765}
9766
7fad798e
DV		 9767static void intel_enable_pipe_a(struct drm_device *dev)
9768{
9769 struct intel_connector *connector;
9770 struct drm_connector *crt = NULL;
9771 struct intel_load_detect_pipe load_detect_temp;
9772
9773 /* We can't just switch on the pipe A, we need to set things up with a
9774 * proper mode and output configuration. As a gross hack, enable pipe A
9775 * by enabling the load detect pipe once. */
9776 list_for_each_entry(connector,
9777 &dev->mode_config.connector_list,
9778 base.head) {
9779 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9780 crt = &connector->base;
9781 break;
9782 }
9783 }
9784
9785 if (!crt)
9786 return;
9787
9788 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9789 intel_release_load_detect_pipe(crt, &load_detect_temp);
9790
652c393a 9791
7fad798e
DV		 9792}
9793
fa555837
DV		 9794static bool
9795intel_check_plane_mapping(struct intel_crtc *crtc)
9796{
7eb552ae
BW		 9797 struct drm_device *dev = crtc->base.dev;
9798 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9799 u32 reg, val;
9800
7eb552ae 9801 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9802 return true;
9803
9804 reg = DSPCNTR(!crtc->plane);
9805 val = I915_READ(reg);
9806
9807 if ((val & DISPLAY_PLANE_ENABLE) &&
9808 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9809 return false;
9810
9811 return true;
9812}
9813
24929352
DV		 9814static void intel_sanitize_crtc(struct intel_crtc *crtc)
9815{
9816 struct drm_device *dev = crtc->base.dev;
9817 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9818 u32 reg;
24929352 9819
24929352 9820 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9821 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9822 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9823
9824 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9825 * disable the crtc (and hence change the state) if it is wrong. Note
9826 * that gen4+ has a fixed plane -> pipe mapping. */
9827 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9828 struct intel_connector *connector;
9829 bool plane;
9830
24929352
DV		 9831 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9832 crtc->base.base.id);
9833
9834 /* Pipe has the wrong plane attached and the plane is active.
9835 * Temporarily change the plane mapping and disable everything
9836 * ... */
9837 plane = crtc->plane;
9838 crtc->plane = !plane;
9839 dev_priv->display.crtc_disable(&crtc->base);
9840 crtc->plane = plane;
9841
9842 /* ... and break all links. */
9843 list_for_each_entry(connector, &dev->mode_config.connector_list,
9844 base.head) {
9845 if (connector->encoder->base.crtc != &crtc->base)
9846 continue;
9847
9848 intel_connector_break_all_links(connector);
9849 }
9850
9851 WARN_ON(crtc->active);
9852 crtc->base.enabled = false;
9853 }
24929352 9854
7fad798e
DV		 9855 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9856 crtc->pipe == PIPE_A && !crtc->active) {
9857 /* BIOS forgot to enable pipe A, this mostly happens after
9858 * resume. Force-enable the pipe to fix this, the update_dpms
9859 * call below we restore the pipe to the right state, but leave
9860 * the required bits on. */
9861 intel_enable_pipe_a(dev);
9862 }
9863
24929352
DV		 9864 /* Adjust the state of the output pipe according to whether we
9865 * have active connectors/encoders. */
9866 intel_crtc_update_dpms(&crtc->base);
9867
9868 if (crtc->active != crtc->base.enabled) {
9869 struct intel_encoder *encoder;
9870
9871 /* This can happen either due to bugs in the get_hw_state
9872 * functions or because the pipe is force-enabled due to the
9873 * pipe A quirk. */
9874 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9875 crtc->base.base.id,
9876 crtc->base.enabled ? "enabled" : "disabled",
9877 crtc->active ? "enabled" : "disabled");
9878
9879 crtc->base.enabled = crtc->active;
9880
9881 /* Because we only establish the connector -> encoder ->
9882 * crtc links if something is active, this means the
9883 * crtc is now deactivated. Break the links. connector
9884 * -> encoder links are only establish when things are
9885 * actually up, hence no need to break them. */
9886 WARN_ON(crtc->active);
9887
9888 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9889 WARN_ON(encoder->connectors_active);
9890 encoder->base.crtc = NULL;
9891 }
9892 }
9893}
9894
9895static void intel_sanitize_encoder(struct intel_encoder *encoder)
9896{
9897 struct intel_connector *connector;
9898 struct drm_device *dev = encoder->base.dev;
9899
9900 /* We need to check both for a crtc link (meaning that the
9901 * encoder is active and trying to read from a pipe) and the
9902 * pipe itself being active. */
9903 bool has_active_crtc = encoder->base.crtc &&
9904 to_intel_crtc(encoder->base.crtc)->active;
9905
9906 if (encoder->connectors_active && !has_active_crtc) {
9907 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9908 encoder->base.base.id,
9909 drm_get_encoder_name(&encoder->base));
9910
9911 /* Connector is active, but has no active pipe. This is
9912 * fallout from our resume register restoring. Disable
9913 * the encoder manually again. */
9914 if (encoder->base.crtc) {
9915 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9916 encoder->base.base.id,
9917 drm_get_encoder_name(&encoder->base));
9918 encoder->disable(encoder);
9919 }
9920
9921 /* Inconsistent output/port/pipe state happens presumably due to
9922 * a bug in one of the get_hw_state functions. Or someplace else
9923 * in our code, like the register restore mess on resume. Clamp
9924 * things to off as a safer default. */
9925 list_for_each_entry(connector,
9926 &dev->mode_config.connector_list,
9927 base.head) {
9928 if (connector->encoder != encoder)
9929 continue;
9930
9931 intel_connector_break_all_links(connector);
9932 }
9933 }
9934 /* Enabled encoders without active connectors will be fixed in
9935 * the crtc fixup. */
9936}
9937
44cec740 9938void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9939{
9940 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9941 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9942
9943 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9944 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9945 i915_disable_vga(dev);
0fde901f
KM		 9946 }
9947}
9948
30e984df 9949static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9950{
9951 struct drm_i915_private *dev_priv = dev->dev_private;
9952 enum pipe pipe;
24929352
DV		 9953 struct intel_crtc *crtc;
9954 struct intel_encoder *encoder;
9955 struct intel_connector *connector;
5358901f 9956 int i;
24929352 9957
0e8ffe1b
DV		 9958 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9959 base.head) {
88adfff1 9960 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9961
0e8ffe1b
DV		 9962 crtc->active = dev_priv->display.get_pipe_config(crtc,
9963 &crtc->config);
24929352
DV		 9964
9965 crtc->base.enabled = crtc->active;
9966
9967 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9968 crtc->base.base.id,
9969 crtc->active ? "enabled" : "disabled");
9970 }
9971
5358901f 9972 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9973 if (HAS_DDI(dev))
6441ab5f
PZ		 9974 intel_ddi_setup_hw_pll_state(dev);
9975
5358901f
DV		 9976 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9977 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9978
9979 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9980 pll->active = 0;
9981 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9982 base.head) {
9983 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9984 pll->active++;
9985 }
9986 pll->refcount = pll->active;
9987
9988 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9989 pll->name, pll->refcount);
9990 }
9991
24929352
DV		 9992 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9993 base.head) {
9994 pipe = 0;
9995
9996 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9997 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9998 encoder->base.crtc = &crtc->base;
510d5f2f 9999 if (encoder->get_config)
045ac3b5 10000 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10001 } else {
10002 encoder->base.crtc = NULL;
10003 }
10004
10005 encoder->connectors_active = false;
10006 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10007 encoder->base.base.id,
10008 drm_get_encoder_name(&encoder->base),
10009 encoder->base.crtc ? "enabled" : "disabled",
10010 pipe);
10011 }
10012
510d5f2f
JB		 10013 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10014 base.head) {
10015 if (!crtc->active)
10016 continue;
10017 if (dev_priv->display.get_clock)
10018 dev_priv->display.get_clock(crtc,
10019 &crtc->config);
10020 }
10021
24929352
DV		 10022 list_for_each_entry(connector, &dev->mode_config.connector_list,
10023 base.head) {
10024 if (connector->get_hw_state(connector)) {
10025 connector->base.dpms = DRM_MODE_DPMS_ON;
10026 connector->encoder->connectors_active = true;
10027 connector->base.encoder = &connector->encoder->base;
10028 } else {
10029 connector->base.dpms = DRM_MODE_DPMS_OFF;
10030 connector->base.encoder = NULL;
10031 }
10032 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10033 connector->base.base.id,
10034 drm_get_connector_name(&connector->base),
10035 connector->base.encoder ? "enabled" : "disabled");
10036 }
30e984df
DV		 10037}
10038
10039/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10040 * and i915 state tracking structures. */
10041void intel_modeset_setup_hw_state(struct drm_device *dev,
10042 bool force_restore)
10043{
10044 struct drm_i915_private *dev_priv = dev->dev_private;
10045 enum pipe pipe;
10046 struct drm_plane *plane;
10047 struct intel_crtc *crtc;
10048 struct intel_encoder *encoder;
10049
10050 intel_modeset_readout_hw_state(dev);
24929352 10051
babea61d
JB		 10052 /*
10053 * Now that we have the config, copy it to each CRTC struct
10054 * Note that this could go away if we move to using crtc_config
10055 * checking everywhere.
10056 */
10057 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10058 base.head) {
10059 if (crtc->active && i915_fastboot) {
10060 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10061
10062 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10063 crtc->base.base.id);
10064 drm_mode_debug_printmodeline(&crtc->base.mode);
10065 }
10066 }
10067
24929352
DV		 10068 /* HW state is read out, now we need to sanitize this mess. */
10069 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10070 base.head) {
10071 intel_sanitize_encoder(encoder);
10072 }
10073
10074 for_each_pipe(pipe) {
10075 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10076 intel_sanitize_crtc(crtc);
c0b03411 10077 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10078 }
9a935856 10079
45e2b5f6 10080 if (force_restore) {
f30da187
DV		 10081 /*
10082 * We need to use raw interfaces for restoring state to avoid
10083 * checking (bogus) intermediate states.
10084 */
45e2b5f6 10085 for_each_pipe(pipe) {
b5644d05
JB		 10086 struct drm_crtc *crtc =
10087 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10088
10089 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10090 crtc->fb);
45e2b5f6 10091 }
b5644d05
JB		 10092 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10093 intel_plane_restore(plane);
0fde901f
KM		 10094
10095 i915_redisable_vga(dev);
45e2b5f6
DV		 10096 } else {
10097 intel_modeset_update_staged_output_state(dev);
10098 }
8af6cf88
DV		 10099
10100 intel_modeset_check_state(dev);
2e938892
DV		 10101
10102 drm_mode_config_reset(dev);
2c7111db
CW		 10103}
10104
10105void intel_modeset_gem_init(struct drm_device *dev)
10106{
1833b134 10107 intel_modeset_init_hw(dev);
02e792fb
DV		 10108
10109 intel_setup_overlay(dev);
24929352 10110
45e2b5f6 10111 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10112}
10113
10114void intel_modeset_cleanup(struct drm_device *dev)
10115{
652c393a
JB		 10116 struct drm_i915_private *dev_priv = dev->dev_private;
10117 struct drm_crtc *crtc;
10118 struct intel_crtc *intel_crtc;
10119
fd0c0642
DV		 10120 /*
10121 * Interrupts and polling as the first thing to avoid creating havoc.
10122 * Too much stuff here (turning of rps, connectors, ...) would
10123 * experience fancy races otherwise.
10124 */
10125 drm_irq_uninstall(dev);
10126 cancel_work_sync(&dev_priv->hotplug_work);
10127 /*
10128 * Due to the hpd irq storm handling the hotplug work can re-arm the
10129 * poll handlers. Hence disable polling after hpd handling is shut down.
10130 */
f87ea761 10131 drm_kms_helper_poll_fini(dev);
fd0c0642 10132
652c393a
JB		 10133 mutex_lock(&dev->struct_mutex);
10134
723bfd70
JB		 10135 intel_unregister_dsm_handler();
10136
652c393a
JB		 10137 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10138 /* Skip inactive CRTCs */
10139 if (!crtc->fb)
10140 continue;
10141
10142 intel_crtc = to_intel_crtc(crtc);
3dec0095 10143 intel_increase_pllclock(crtc);
652c393a
JB		 10144 }
10145
973d04f9 10146 intel_disable_fbc(dev);
e70236a8 10147
8090c6b9 10148 intel_disable_gt_powersave(dev);
0cdab21f 10149
930ebb46
DV		 10150 ironlake_teardown_rc6(dev);
10151
69341a5e
KH		 10152 mutex_unlock(&dev->struct_mutex);
10153
1630fe75
CW		 10154 /* flush any delayed tasks or pending work */
10155 flush_scheduled_work();
10156
dc652f90
JN		 10157 /* destroy backlight, if any, before the connectors */
10158 intel_panel_destroy_backlight(dev);
10159
79e53945 10160 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10161
10162 intel_cleanup_overlay(dev);
79e53945
JB		 10163}
10164
f1c79df3
ZW		 10165/*
10166 * Return which encoder is currently attached for connector.
10167 */
df0e9248 10168struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10169{
df0e9248
CW		 10170 return &intel_attached_encoder(connector)->base;
10171}
f1c79df3 10172
df0e9248
CW		 10173void intel_connector_attach_encoder(struct intel_connector *connector,
10174 struct intel_encoder *encoder)
10175{
10176 connector->encoder = encoder;
10177 drm_mode_connector_attach_encoder(&connector->base,
10178 &encoder->base);
79e53945 10179}
28d52043
DA		 10180
10181/*
10182 * set vga decode state - true == enable VGA decode
10183 */
10184int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10185{
10186 struct drm_i915_private *dev_priv = dev->dev_private;
10187 u16 gmch_ctrl;
10188
10189 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10190 if (state)
10191 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10192 else
10193 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10194 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10195 return 0;
10196}
c4a1d9e4 10197
c4a1d9e4 10198struct intel_display_error_state {
ff57f1b0
PZ		 10199
10200 u32 power_well_driver;
10201
c4a1d9e4
CW		 10202 struct intel_cursor_error_state {
10203 u32 control;
10204 u32 position;
10205 u32 base;
10206 u32 size;
52331309 10207 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10208
10209 struct intel_pipe_error_state {
ff57f1b0 10210 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10211 u32 conf;
10212 u32 source;
10213
10214 u32 htotal;
10215 u32 hblank;
10216 u32 hsync;
10217 u32 vtotal;
10218 u32 vblank;
10219 u32 vsync;
52331309 10220 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10221
10222 struct intel_plane_error_state {
10223 u32 control;
10224 u32 stride;
10225 u32 size;
10226 u32 pos;
10227 u32 addr;
10228 u32 surface;
10229 u32 tile_offset;
52331309 10230 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10231};
10232
10233struct intel_display_error_state *
10234intel_display_capture_error_state(struct drm_device *dev)
10235{
0206e353 10236 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10237 struct intel_display_error_state *error;
702e7a56 10238 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10239 int i;
10240
10241 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10242 if (error == NULL)
10243 return NULL;
10244
ff57f1b0
PZ		 10245 if (HAS_POWER_WELL(dev))
10246 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10247
52331309 10248 for_each_pipe(i) {
702e7a56 10249 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10250 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10251
a18c4c3d
PZ		 10252 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10253 error->cursor[i].control = I915_READ(CURCNTR(i));
10254 error->cursor[i].position = I915_READ(CURPOS(i));
10255 error->cursor[i].base = I915_READ(CURBASE(i));
10256 } else {
10257 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10258 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10259 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10260 }
c4a1d9e4
CW		 10261
10262 error->plane[i].control = I915_READ(DSPCNTR(i));
10263 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10264 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10265 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10266 error->plane[i].pos = I915_READ(DSPPOS(i));
10267 }
ca291363
PZ		 10268 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10269 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10270 if (INTEL_INFO(dev)->gen >= 4) {
10271 error->plane[i].surface = I915_READ(DSPSURF(i));
10272 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10273 }
10274
702e7a56 10275 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10276 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10277 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10278 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10279 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10280 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10281 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10282 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10283 }
10284
12d217c7
PZ		 10285 /* In the code above we read the registers without checking if the power
10286 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10287 * prevent the next I915_WRITE from detecting it and printing an error
10288 * message. */
10289 if (HAS_POWER_WELL(dev))
10290 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10291
c4a1d9e4
CW		 10292 return error;
10293}
10294
edc3d884
MK		 10295#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10296
c4a1d9e4 10297void
edc3d884 10298intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10299 struct drm_device *dev,
10300 struct intel_display_error_state *error)
10301{
10302 int i;
10303
edc3d884 10304 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10305 if (HAS_POWER_WELL(dev))
edc3d884 10306 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10307 error->power_well_driver);
52331309 10308 for_each_pipe(i) {
edc3d884
MK		 10309 err_printf(m, "Pipe [%d]:\n", i);
10310 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10311 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10312 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10313 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10314 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10315 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10316 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10317 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10318 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10319 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10320
10321 err_printf(m, "Plane [%d]:\n", i);
10322 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10323 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10324 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10325 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10326 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10327 }
4b71a570 10328 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10329 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10330 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10331 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10332 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10333 }
10334
edc3d884
MK		 10335 err_printf(m, "Cursor [%d]:\n", i);
10336 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10337 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10338 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10339 }
10340}
Linux kernel - Deliverables
This page took 1.667978 seconds and 5 git commands to generate.