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drm/i915: Really wait for pending flips when panning
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 157 .m1 = { .min = 8, .max = 18 },
158 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 171 .m1 = { .min = 8, .max = 18 },
172 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
09153000 419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 420
57f350b6
JB		 421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
09153000 423 return 0;
57f350b6
JB		 424 }
425
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
428 DPIO_BYTE);
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
09153000 431 return 0;
57f350b6 432 }
57f350b6 433
09153000 434 return I915_READ(DPIO_DATA);
57f350b6
JB		 435}
436
a0c4da24
JB		 437static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
438 u32 val)
439{
09153000 440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 441
a0c4da24
JB		 442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
09153000 444 return;
a0c4da24
JB		 445 }
446
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
450 DPIO_BYTE);
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 453}
454
57f350b6
JB		 455static void vlv_init_dpio(struct drm_device *dev)
456{
457 struct drm_i915_private *dev_priv = dev->dev_private;
458
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
464}
465
1b894b59
CW		 466static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
2c07245f 468{
b91ad0ec 469 struct drm_device *dev = crtc->dev;
2c07245f 470 const intel_limit_t *limit;
b91ad0ec
ZW		 471
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 473 if (intel_is_dual_link_lvds(dev)) {
b91ad0ec 474 /* LVDS dual channel */
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_dual_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_dual_lvds;
479 } else {
1b894b59 480 if (refclk == 100000)
b91ad0ec
ZW		 481 limit = &intel_limits_ironlake_single_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_single_lvds;
484 }
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 487 limit = &intel_limits_ironlake_display_port;
2c07245f 488 else
b91ad0ec 489 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 490
491 return limit;
492}
493
044c7c41
ML		 494static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
495{
496 struct drm_device *dev = crtc->dev;
044c7c41
ML		 497 const intel_limit_t *limit;
498
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 500 if (intel_is_dual_link_lvds(dev))
044c7c41 501 /* LVDS with dual channel */
e4b36699 502 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 503 else
504 /* LVDS with dual channel */
e4b36699 505 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 508 limit = &intel_limits_g4x_hdmi;
044c7c41 509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 510 limit = &intel_limits_g4x_sdvo;
0206e353 511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 512 limit = &intel_limits_g4x_display_port;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
1b894b59 519static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
523
bad720ff 524 if (HAS_PCH_SPLIT(dev))
1b894b59 525 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 526 else if (IS_G4X(dev)) {
044c7c41 527 limit = intel_g4x_limit(crtc);
f2b115e6 528 } else if (IS_PINEVIEW(dev)) {
2177832f 529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 530 limit = &intel_limits_pineview_lvds;
2177832f 531 else
f2b115e6 532 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
538 else
539 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 545 } else {
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
79e53945 548 else
e4b36699 549 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 550 }
551 return limit;
552}
553
f2b115e6
AJ		 554/* m1 is reserved as 0 in Pineview, n is a ring counter */
555static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 556{
2177832f
SL		 557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
561}
562
563static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
564{
f2b115e6
AJ		 565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
2177832f
SL		 567 return;
568 }
79e53945
JB		 569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
573}
574
79e53945
JB		 575/**
576 * Returns whether any output on the specified pipe is of the specified type
577 */
4ef69c7a 578bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 579{
4ef69c7a 580 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 581 struct intel_encoder *encoder;
582
6c2b7c12
DV		 583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
4ef69c7a
CW		 585 return true;
586
587 return false;
79e53945
JB		 588}
589
7c04d1d9 590#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 591/**
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
594 */
595
1b894b59
CW		 596static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
79e53945 599{
79e53945 600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 601 INTELPllInvalid("p1 out of range\n");
79e53945 602 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 603 INTELPllInvalid("p out of range\n");
79e53945 604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 605 INTELPllInvalid("m2 out of range\n");
79e53945 606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 607 INTELPllInvalid("m1 out of range\n");
f2b115e6 608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 609 INTELPllInvalid("m1 <= m2\n");
79e53945 610 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 611 INTELPllInvalid("m out of range\n");
79e53945 612 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 613 INTELPllInvalid("n out of range\n");
79e53945 614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 615 INTELPllInvalid("vco out of range\n");
79e53945
JB		 616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
618 */
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 620 INTELPllInvalid("dot out of range\n");
79e53945
JB		 621
622 return true;
623}
624
d4906093
ML		 625static bool
626intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
d4906093 629
79e53945
JB		 630{
631 struct drm_device *dev = crtc->dev;
79e53945 632 intel_clock_t clock;
79e53945
JB		 633 int err = target;
634
a210b028 635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 636 /*
a210b028
DV		 637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
79e53945 640 */
1974cad0 641 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
0206e353 652 memset(best_clock, 0, sizeof(*best_clock));
79e53945 653
42158660
ZY		 654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 665 int this_err;
666
2177832f 667 intel_clock(dev, refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
79e53945 670 continue;
cec2f356
SP		 671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
79e53945
JB		 674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686}
687
d4906093
ML		 688static bool
689intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
d4906093
ML		 692{
693 struct drm_device *dev = crtc->dev;
d4906093
ML		 694 intel_clock_t clock;
695 int max_n;
696 bool found;
6ba770dc
AJ		 697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 702 int lvds_reg;
703
c619eed4 704 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
1974cad0 708 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
f77f13e2 721 /* based on hardware requirement, prefer smaller n to precision */
d4906093 722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 723 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
2177832f 732 intel_clock(dev, refclk, &clock);
1b894b59
CW		 733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
d4906093 735 continue;
cec2f356
SP		 736 if (match_clock &&
737 clock.p != match_clock->p)
738 continue;
1b894b59
CW		 739
740 this_err = abs(clock.dot - target);
d4906093
ML		 741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
2c07245f
ZW		 751 return found;
752}
753
5eb08b69 754static bool
f2b115e6 755intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
5eb08b69
ZW		 758{
759 struct drm_device *dev = crtc->dev;
760 intel_clock_t clock;
4547668a 761
5eb08b69
ZW		 762 if (target < 200000) {
763 clock.n = 1;
764 clock.p1 = 2;
765 clock.p2 = 10;
766 clock.m1 = 12;
767 clock.m2 = 9;
768 } else {
769 clock.n = 2;
770 clock.p1 = 1;
771 clock.p2 = 10;
772 clock.m1 = 14;
773 clock.m2 = 8;
774 }
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
777 return true;
778}
779
a4fc5ed6
KP		 780/* DisplayPort has only two frequencies, 162MHz and 270MHz */
781static bool
782intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
a4fc5ed6 785{
5eddb70b
CW		 786 intel_clock_t clock;
787 if (target < 200000) {
788 clock.p1 = 2;
789 clock.p2 = 10;
790 clock.n = 2;
791 clock.m1 = 23;
792 clock.m2 = 8;
793 } else {
794 clock.p1 = 1;
795 clock.p2 = 10;
796 clock.n = 1;
797 clock.m1 = 14;
798 clock.m2 = 2;
799 }
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
803 clock.vco = 0;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
805 return true;
a4fc5ed6 806}
a0c4da24
JB		 807static bool
808intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811{
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
813 u32 m, n, fastclk;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
816 int dotclk, flag;
817
af447bd3 818 flag = 0;
a0c4da24
JB		 819 dotclk = target * 1000;
820 bestppm = 1000000;
821 ppm = absppm = 0;
822 fastclk = dotclk / (2*100);
823 updrate = 0;
824 minupdate = 19200;
825 fracbits = 1;
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
828
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
834 if (p2 > 10)
835 p2 = p2 - 1;
836 p = p1 * p2;
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
841 m = m1 * m2;
842 vco = updrate * m;
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
847 bestppm = 0;
848 flag = 1;
849 }
850 if (absppm < bestppm - 10) {
851 bestppm = absppm;
852 flag = 1;
853 }
854 if (flag) {
855 bestn = n;
856 bestm1 = m1;
857 bestm2 = m2;
858 bestp1 = p1;
859 bestp2 = p2;
860 flag = 0;
861 }
862 }
863 }
864 }
865 }
866 }
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
872
873 return true;
874}
a4fc5ed6 875
a5c961d1
PZ		 876enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878{
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->cpu_transcoder;
883}
884
a928d536
PZ		 885static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
886{
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
894}
895
9d0498a2
JB		 896/**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 905{
9d0498a2 906 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 907 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 908
a928d536
PZ		 909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
911 return;
912 }
913
300387c0
CW		 914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
9d0498a2 930 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
9d0498a2
JB		 934 DRM_DEBUG_KMS("vblank wait timed out\n");
935}
936
ab7ad7f6
KP		 937/*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 939 * @dev: drm device
940 * @pipe: pipe to wait for
941 *
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
945 *
ab7ad7f6
KP		 946 * On Gen4 and above:
947 * wait for the pipe register state bit to turn off
948 *
949 * Otherwise:
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
58e10eb9 952 *
9d0498a2 953 */
58e10eb9 954void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 955{
956 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 pipe);
ab7ad7f6
KP		 959
960 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 961 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 962
963 /* Wait for the Pipe State to go off */
58e10eb9
CW		 964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
284637d9 966 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 967 } else {
837ba00f 968 u32 last_line, line_mask;
58e10eb9 969 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
971
837ba00f
PZ		 972 if (IS_GEN2(dev))
973 line_mask = DSL_LINEMASK_GEN2;
974 else
975 line_mask = DSL_LINEMASK_GEN3;
976
ab7ad7f6
KP		 977 /* Wait for the display line to settle */
978 do {
837ba00f 979 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 980 mdelay(5);
837ba00f 981 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
284637d9 984 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 985 }
79e53945
JB		 986}
987
b0ea7d37
DL		 988/*
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
992 *
993 * Returns true if @port is connected, false otherwise.
994 */
995bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
997{
998 u32 bit;
999
c36346e3
DL		 1000 if (HAS_PCH_IBX(dev_priv->dev)) {
1001 switch(port->port) {
1002 case PORT_B:
1003 bit = SDE_PORTB_HOTPLUG;
1004 break;
1005 case PORT_C:
1006 bit = SDE_PORTC_HOTPLUG;
1007 break;
1008 case PORT_D:
1009 bit = SDE_PORTD_HOTPLUG;
1010 break;
1011 default:
1012 return true;
1013 }
1014 } else {
1015 switch(port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG_CPT;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG_CPT;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG_CPT;
1024 break;
1025 default:
1026 return true;
1027 }
b0ea7d37
DL		 1028 }
1029
1030 return I915_READ(SDEISR) & bit;
1031}
1032
b24e7179
JB		 1033static const char *state_string(bool enabled)
1034{
1035 return enabled ? "on" : "off";
1036}
1037
1038/* Only for pre-ILK configs */
1039static void assert_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1041{
1042 int reg;
1043 u32 val;
1044 bool cur_state;
1045
1046 reg = DPLL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & DPLL_VCO_ENABLE);
1049 WARN(cur_state != state,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1052}
1053#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
040484af
JB		 1056/* For ILK+ */
1057static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1058 struct intel_pch_pll *pll,
1059 struct intel_crtc *crtc,
1060 bool state)
040484af 1061{
040484af
JB		 1062 u32 val;
1063 bool cur_state;
1064
9d82aa17
ED		 1065 if (HAS_PCH_LPT(dev_priv->dev)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067 return;
1068 }
1069
92b27b08
CW		 1070 if (WARN (!pll,
1071 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1072 return;
ee7b9f93 1073
92b27b08
CW		 1074 val = I915_READ(pll->pll_reg);
1075 cur_state = !!(val & DPLL_VCO_ENABLE);
1076 WARN(cur_state != state,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1082 u32 pch_dpll;
1083
1084 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1085 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state, crtc->pipe, pch_dpll)) {
1089 cur_state = !!(val >> (4*crtc->pipe + 3));
1090 WARN(cur_state != state,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll->pll_reg == _PCH_DPLL_B,
1093 state_string(state),
1094 crtc->pipe,
1095 val);
1096 }
d3ccbe86 1097 }
040484af 1098}
92b27b08
CW		 1099#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
ad80a810
PZ		 1108 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 pipe);
040484af 1110
affa9354
PZ		 1111 if (HAS_DDI(dev_priv->dev)) {
1112 /* DDI does not have a specific FDI_TX register */
ad80a810 1113 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1114 val = I915_READ(reg);
ad80a810 1115 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1116 } else {
1117 reg = FDI_TX_CTL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & FDI_TX_ENABLE);
1120 }
040484af
JB		 1121 WARN(cur_state != state,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1130{
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
d63fa0dc
PZ		 1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1153 return;
1154
bf507ef7 1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1156 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1157 return;
1158
040484af
JB		 1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162}
1163
1164static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166{
1167 int reg;
1168 u32 val;
1169
1170 reg = FDI_RX_CTL(pipe);
1171 val = I915_READ(reg);
1172 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173}
1174
ea0760cf
JB		 1175static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int pp_reg, lvds_reg;
1179 u32 val;
1180 enum pipe panel_pipe = PIPE_A;
0de3b485 1181 bool locked = true;
ea0760cf
JB		 1182
1183 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184 pp_reg = PCH_PP_CONTROL;
1185 lvds_reg = PCH_LVDS;
1186 } else {
1187 pp_reg = PP_CONTROL;
1188 lvds_reg = LVDS;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197 panel_pipe = PIPE_B;
1198
1199 WARN(panel_pipe == pipe && locked,
1200 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1201 pipe_name(pipe));
ea0760cf
JB		 1202}
1203
b840d907
JB		 1204void assert_pipe(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, bool state)
b24e7179
JB		 1206{
1207 int reg;
1208 u32 val;
63d7bbe9 1209 bool cur_state;
702e7a56
PZ		 1210 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211 pipe);
b24e7179 1212
8e636784
DV		 1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215 state = true;
1216
69310161
PZ		 1217 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1219 cur_state = false;
1220 } else {
1221 reg = PIPECONF(cpu_transcoder);
1222 val = I915_READ(reg);
1223 cur_state = !!(val & PIPECONF_ENABLE);
1224 }
1225
63d7bbe9
JB		 1226 WARN(cur_state != state,
1227 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1228 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1229}
1230
931872fc
CW		 1231static void assert_plane(struct drm_i915_private *dev_priv,
1232 enum plane plane, bool state)
b24e7179
JB		 1233{
1234 int reg;
1235 u32 val;
931872fc 1236 bool cur_state;
b24e7179
JB		 1237
1238 reg = DSPCNTR(plane);
1239 val = I915_READ(reg);
931872fc
CW		 1240 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1241 WARN(cur_state != state,
1242 "plane %c assertion failure (expected %s, current %s)\n",
1243 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1244}
1245
931872fc
CW		 1246#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1247#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1248
b24e7179
JB		 1249static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1250 enum pipe pipe)
1251{
1252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
19ec1358 1256 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1257 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
1260 WARN((val & DISPLAY_PLANE_ENABLE),
1261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
19ec1358 1263 return;
28c05794 1264 }
19ec1358 1265
b24e7179
JB		 1266 /* Need to check both planes against the pipe */
1267 for (i = 0; i < 2; i++) {
1268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1275 }
1276}
1277
92f2584a
JB		 1278static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1279{
1280 u32 val;
1281 bool enabled;
1282
9d82aa17
ED		 1283 if (HAS_PCH_LPT(dev_priv->dev)) {
1284 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 return;
1286 }
1287
92f2584a
JB		 1288 val = I915_READ(PCH_DREF_CONTROL);
1289 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1290 DREF_SUPERSPREAD_SOURCE_MASK));
1291 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1292}
1293
1294static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296{
1297 int reg;
1298 u32 val;
1299 bool enabled;
1300
1301 reg = TRANSCONF(pipe);
1302 val = I915_READ(reg);
1303 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1304 WARN(enabled,
1305 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 pipe_name(pipe));
92f2584a
JB		 1307}
1308
4e634389
KP		 1309static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1311{
1312 if ((val & DP_PORT_EN) == 0)
1313 return false;
1314
1315 if (HAS_PCH_CPT(dev_priv->dev)) {
1316 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1317 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1318 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325}
1326
1519b995
KP		 1327static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329{
1330 if ((val & PORT_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv->dev)) {
1334 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1335 return false;
1336 } else {
1337 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1338 return false;
1339 }
1340 return true;
1341}
1342
1343static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1344 enum pipe pipe, u32 val)
1345{
1346 if ((val & LVDS_PORT_EN) == 0)
1347 return false;
1348
1349 if (HAS_PCH_CPT(dev_priv->dev)) {
1350 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351 return false;
1352 } else {
1353 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1354 return false;
1355 }
1356 return true;
1357}
1358
1359static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
1362 if ((val & ADPA_DAC_ENABLE) == 0)
1363 return false;
1364 if (HAS_PCH_CPT(dev_priv->dev)) {
1365 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1366 return false;
1367 } else {
1368 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1369 return false;
1370 }
1371 return true;
1372}
1373
291906f1 1374static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1375 enum pipe pipe, int reg, u32 port_sel)
291906f1 1376{
47a05eca 1377 u32 val = I915_READ(reg);
4e634389 1378 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1379 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1380 reg, pipe_name(pipe));
de9a35ab 1381
75c5da27
DV		 1382 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1383 && (val & DP_PIPEB_SELECT),
de9a35ab 1384 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1385}
1386
1387static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, int reg)
1389{
47a05eca 1390 u32 val = I915_READ(reg);
b70ad586 1391 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1392 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1396 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1397 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe)
1402{
1403 int reg;
1404 u32 val;
291906f1 1405
f0575e92
KP		 1406 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1407 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1408 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1409
1410 reg = PCH_ADPA;
1411 val = I915_READ(reg);
b70ad586 1412 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1413 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1414 pipe_name(pipe));
291906f1
JB		 1415
1416 reg = PCH_LVDS;
1417 val = I915_READ(reg);
b70ad586 1418 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1419 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1420 pipe_name(pipe));
291906f1
JB		 1421
1422 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1423 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425}
1426
63d7bbe9
JB		 1427/**
1428 * intel_enable_pll - enable a PLL
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1433 * make sure the PLL reg is writable first though, since the panel write
1434 * protect mechanism may be enabled.
1435 *
1436 * Note! This is for pre-ILK only.
7434a255
TR		 1437 *
1438 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1439 */
1440static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1441{
1442 int reg;
1443 u32 val;
1444
1445 /* No really, not for ILK+ */
a0c4da24 1446 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1447
1448 /* PLL is protected by panel, make sure we can write it */
1449 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450 assert_panel_unlocked(dev_priv, pipe);
1451
1452 reg = DPLL(pipe);
1453 val = I915_READ(reg);
1454 val |= DPLL_VCO_ENABLE;
1455
1456 /* We do this three times for luck */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463 I915_WRITE(reg, val);
1464 POSTING_READ(reg);
1465 udelay(150); /* wait for warmup */
1466}
1467
1468/**
1469 * intel_disable_pll - disable a PLL
1470 * @dev_priv: i915 private structure
1471 * @pipe: pipe PLL to disable
1472 *
1473 * Disable the PLL for @pipe, making sure the pipe is off first.
1474 *
1475 * Note! This is for pre-ILK only.
1476 */
1477static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478{
1479 int reg;
1480 u32 val;
1481
1482 /* Don't disable pipe A or pipe A PLLs if needed */
1483 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1484 return;
1485
1486 /* Make sure the pipe isn't still relying on us */
1487 assert_pipe_disabled(dev_priv, pipe);
1488
1489 reg = DPLL(pipe);
1490 val = I915_READ(reg);
1491 val &= ~DPLL_VCO_ENABLE;
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494}
1495
a416edef
ED		 1496/* SBI access */
1497static void
988d6ee8
PZ		 1498intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1499 enum intel_sbi_destination destination)
a416edef 1500{
988d6ee8 1501 u32 tmp;
a416edef 1502
09153000 1503 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1504
39fb50f6 1505 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1506 100)) {
1507 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1508 return;
a416edef
ED		 1509 }
1510
988d6ee8
PZ		 1511 I915_WRITE(SBI_ADDR, (reg << 16));
1512 I915_WRITE(SBI_DATA, value);
1513
1514 if (destination == SBI_ICLK)
1515 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1516 else
1517 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1518 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1519
39fb50f6 1520 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1521 100)) {
1522 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1523 return;
a416edef 1524 }
a416edef
ED		 1525}
1526
1527static u32
988d6ee8
PZ		 1528intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1529 enum intel_sbi_destination destination)
a416edef 1530{
39fb50f6 1531 u32 value = 0;
09153000 1532 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1533
39fb50f6 1534 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1535 100)) {
1536 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1537 return 0;
a416edef
ED		 1538 }
1539
988d6ee8
PZ		 1540 I915_WRITE(SBI_ADDR, (reg << 16));
1541
1542 if (destination == SBI_ICLK)
1543 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1544 else
1545 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1546 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1547
39fb50f6 1548 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1549 100)) {
1550 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1551 return 0;
a416edef
ED		 1552 }
1553
09153000 1554 return I915_READ(SBI_DATA);
a416edef
ED		 1555}
1556
92f2584a 1557/**
b6b4e185 1558 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1559 * @dev_priv: i915 private structure
1560 * @pipe: pipe PLL to enable
1561 *
1562 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1563 * drives the transcoder clock.
1564 */
b6b4e185 1565static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1566{
ee7b9f93 1567 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1568 struct intel_pch_pll *pll;
92f2584a
JB		 1569 int reg;
1570 u32 val;
1571
48da64a8 1572 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1573 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1574 pll = intel_crtc->pch_pll;
1575 if (pll == NULL)
1576 return;
1577
1578 if (WARN_ON(pll->refcount == 0))
1579 return;
ee7b9f93
JB		 1580
1581 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1582 pll->pll_reg, pll->active, pll->on,
1583 intel_crtc->base.base.id);
92f2584a
JB		 1584
1585 /* PCH refclock must be enabled first */
1586 assert_pch_refclk_enabled(dev_priv);
1587
ee7b9f93 1588 if (pll->active++ && pll->on) {
92b27b08 1589 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1590 return;
1591 }
1592
1593 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1594
1595 reg = pll->pll_reg;
92f2584a
JB		 1596 val = I915_READ(reg);
1597 val |= DPLL_VCO_ENABLE;
1598 I915_WRITE(reg, val);
1599 POSTING_READ(reg);
1600 udelay(200);
ee7b9f93
JB		 1601
1602 pll->on = true;
92f2584a
JB		 1603}
1604
ee7b9f93 1605static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1606{
ee7b9f93
JB		 1607 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1608 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1609 int reg;
ee7b9f93 1610 u32 val;
4c609cb8 1611
92f2584a
JB		 1612 /* PCH only available on ILK+ */
1613 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1614 if (pll == NULL)
1615 return;
92f2584a 1616
48da64a8
CW		 1617 if (WARN_ON(pll->refcount == 0))
1618 return;
7a419866 1619
ee7b9f93
JB		 1620 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1621 pll->pll_reg, pll->active, pll->on,
1622 intel_crtc->base.base.id);
7a419866 1623
48da64a8 1624 if (WARN_ON(pll->active == 0)) {
92b27b08 1625 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1626 return;
1627 }
1628
ee7b9f93 1629 if (--pll->active) {
92b27b08 1630 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1631 return;
ee7b9f93
JB		 1632 }
1633
1634 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635
1636 /* Make sure transcoder isn't still depending on us */
1637 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1638
ee7b9f93 1639 reg = pll->pll_reg;
92f2584a
JB		 1640 val = I915_READ(reg);
1641 val &= ~DPLL_VCO_ENABLE;
1642 I915_WRITE(reg, val);
1643 POSTING_READ(reg);
1644 udelay(200);
ee7b9f93
JB		 1645
1646 pll->on = false;
92f2584a
JB		 1647}
1648
b8a4f404
PZ		 1649static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1650 enum pipe pipe)
040484af 1651{
23670b32 1652 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1654 uint32_t reg, val, pipeconf_val;
040484af
JB		 1655
1656 /* PCH only available on ILK+ */
1657 BUG_ON(dev_priv->info->gen < 5);
1658
1659 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1660 assert_pch_pll_enabled(dev_priv,
1661 to_intel_crtc(crtc)->pch_pll,
1662 to_intel_crtc(crtc));
040484af
JB		 1663
1664 /* FDI must be feeding us bits for PCH ports */
1665 assert_fdi_tx_enabled(dev_priv, pipe);
1666 assert_fdi_rx_enabled(dev_priv, pipe);
1667
23670b32
DV		 1668 if (HAS_PCH_CPT(dev)) {
1669 /* Workaround: Set the timing override bit before enabling the
1670 * pch transcoder. */
1671 reg = TRANS_CHICKEN2(pipe);
1672 val = I915_READ(reg);
1673 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1674 I915_WRITE(reg, val);
59c859d6 1675 }
23670b32 1676
040484af
JB		 1677 reg = TRANSCONF(pipe);
1678 val = I915_READ(reg);
5f7f726d 1679 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1680
1681 if (HAS_PCH_IBX(dev_priv->dev)) {
1682 /*
1683 * make the BPC in transcoder be consistent with
1684 * that in pipeconf reg.
1685 */
dfd07d72
DV		 1686 val &= ~PIPECONF_BPC_MASK;
1687 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1688 }
5f7f726d
PZ		 1689
1690 val &= ~TRANS_INTERLACE_MASK;
1691 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1692 if (HAS_PCH_IBX(dev_priv->dev) &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1694 val |= TRANS_LEGACY_INTERLACED_ILK;
1695 else
1696 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1697 else
1698 val |= TRANS_PROGRESSIVE;
1699
040484af
JB		 1700 I915_WRITE(reg, val | TRANS_ENABLE);
1701 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1702 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1703}
1704
8fb033d7 1705static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1706 enum transcoder cpu_transcoder)
040484af 1707{
8fb033d7 1708 u32 val, pipeconf_val;
8fb033d7
PZ		 1709
1710 /* PCH only available on ILK+ */
1711 BUG_ON(dev_priv->info->gen < 5);
1712
8fb033d7 1713 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1714 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1715 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1716
223a6fdf
PZ		 1717 /* Workaround: set timing override bit. */
1718 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1719 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1720 I915_WRITE(_TRANSA_CHICKEN2, val);
1721
25f3ef11 1722 val = TRANS_ENABLE;
937bb610 1723 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1724
9a76b1c6
PZ		 1725 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1726 PIPECONF_INTERLACED_ILK)
a35f2679 1727 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1728 else
1729 val |= TRANS_PROGRESSIVE;
1730
25f3ef11 1731 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1732 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1733 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1734}
1735
b8a4f404
PZ		 1736static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1737 enum pipe pipe)
040484af 1738{
23670b32
DV		 1739 struct drm_device *dev = dev_priv->dev;
1740 uint32_t reg, val;
040484af
JB		 1741
1742 /* FDI relies on the transcoder */
1743 assert_fdi_tx_disabled(dev_priv, pipe);
1744 assert_fdi_rx_disabled(dev_priv, pipe);
1745
291906f1
JB		 1746 /* Ports must be off as well */
1747 assert_pch_ports_disabled(dev_priv, pipe);
1748
040484af
JB		 1749 reg = TRANSCONF(pipe);
1750 val = I915_READ(reg);
1751 val &= ~TRANS_ENABLE;
1752 I915_WRITE(reg, val);
1753 /* wait for PCH transcoder off, transcoder state */
1754 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1755 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1756
1757 if (!HAS_PCH_IBX(dev)) {
1758 /* Workaround: Clear the timing override chicken bit again. */
1759 reg = TRANS_CHICKEN2(pipe);
1760 val = I915_READ(reg);
1761 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1762 I915_WRITE(reg, val);
1763 }
040484af
JB		 1764}
1765
ab4d966c 1766static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1767{
8fb033d7
PZ		 1768 u32 val;
1769
8a52fd9f 1770 val = I915_READ(_TRANSACONF);
8fb033d7 1771 val &= ~TRANS_ENABLE;
8a52fd9f 1772 I915_WRITE(_TRANSACONF, val);
8fb033d7 1773 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1774 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1775 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1776
1777 /* Workaround: clear timing override bit. */
1778 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1779 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1780 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1781}
1782
b24e7179 1783/**
309cfea8 1784 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1785 * @dev_priv: i915 private structure
1786 * @pipe: pipe to enable
040484af 1787 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1788 *
1789 * Enable @pipe, making sure that various hardware specific requirements
1790 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1791 *
1792 * @pipe should be %PIPE_A or %PIPE_B.
1793 *
1794 * Will wait until the pipe is actually running (i.e. first vblank) before
1795 * returning.
1796 */
040484af
JB		 1797static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1798 bool pch_port)
b24e7179 1799{
702e7a56
PZ		 1800 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1801 pipe);
1a240d4d 1802 enum pipe pch_transcoder;
b24e7179
JB		 1803 int reg;
1804 u32 val;
1805
681e5811 1806 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1807 pch_transcoder = TRANSCODER_A;
1808 else
1809 pch_transcoder = pipe;
1810
b24e7179
JB		 1811 /*
1812 * A pipe without a PLL won't actually be able to drive bits from
1813 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1814 * need the check.
1815 */
1816 if (!HAS_PCH_SPLIT(dev_priv->dev))
1817 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1818 else {
1819 if (pch_port) {
1820 /* if driving the PCH, we need FDI enabled */
cc391bbb 1821 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1822 assert_fdi_tx_pll_enabled(dev_priv,
1823 (enum pipe) cpu_transcoder);
040484af
JB		 1824 }
1825 /* FIXME: assert CPU port conditions for SNB+ */
1826 }
b24e7179 1827
702e7a56 1828 reg = PIPECONF(cpu_transcoder);
b24e7179 1829 val = I915_READ(reg);
00d70b15
CW		 1830 if (val & PIPECONF_ENABLE)
1831 return;
1832
1833 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1835}
1836
1837/**
309cfea8 1838 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1839 * @dev_priv: i915 private structure
1840 * @pipe: pipe to disable
1841 *
1842 * Disable @pipe, making sure that various hardware specific requirements
1843 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844 *
1845 * @pipe should be %PIPE_A or %PIPE_B.
1846 *
1847 * Will wait until the pipe has shut down before returning.
1848 */
1849static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850 enum pipe pipe)
1851{
702e7a56
PZ		 1852 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853 pipe);
b24e7179
JB		 1854 int reg;
1855 u32 val;
1856
1857 /*
1858 * Make sure planes won't keep trying to pump pixels to us,
1859 * or we might hang the display.
1860 */
1861 assert_planes_disabled(dev_priv, pipe);
1862
1863 /* Don't disable pipe A or pipe A PLLs if needed */
1864 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865 return;
1866
702e7a56 1867 reg = PIPECONF(cpu_transcoder);
b24e7179 1868 val = I915_READ(reg);
00d70b15
CW		 1869 if ((val & PIPECONF_ENABLE) == 0)
1870 return;
1871
1872 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1873 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874}
1875
d74362c9
KP		 1876/*
1877 * Plane regs are double buffered, going from enabled->disabled needs a
1878 * trigger in order to latch. The display address reg provides this.
1879 */
6f1d69b0 1880void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1881 enum plane plane)
1882{
14f86147
DL		 1883 if (dev_priv->info->gen >= 4)
1884 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885 else
1886 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1887}
1888
b24e7179
JB		 1889/**
1890 * intel_enable_plane - enable a display plane on a given pipe
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to enable
1893 * @pipe: pipe being fed
1894 *
1895 * Enable @plane on @pipe, making sure that @pipe is running first.
1896 */
1897static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1899{
1900 int reg;
1901 u32 val;
1902
1903 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904 assert_pipe_enabled(dev_priv, pipe);
1905
1906 reg = DSPCNTR(plane);
1907 val = I915_READ(reg);
00d70b15
CW		 1908 if (val & DISPLAY_PLANE_ENABLE)
1909 return;
1910
1911 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1912 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1913 intel_wait_for_vblank(dev_priv->dev, pipe);
1914}
1915
b24e7179
JB		 1916/**
1917 * intel_disable_plane - disable a display plane
1918 * @dev_priv: i915 private structure
1919 * @plane: plane to disable
1920 * @pipe: pipe consuming the data
1921 *
1922 * Disable @plane; should be an independent operation.
1923 */
1924static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925 enum plane plane, enum pipe pipe)
1926{
1927 int reg;
1928 u32 val;
1929
1930 reg = DSPCNTR(plane);
1931 val = I915_READ(reg);
00d70b15
CW		 1932 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933 return;
1934
1935 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1936 intel_flush_display_plane(dev_priv, plane);
1937 intel_wait_for_vblank(dev_priv->dev, pipe);
1938}
1939
127bd2ac 1940int
48b956c5 1941intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1942 struct drm_i915_gem_object *obj,
919926ae 1943 struct intel_ring_buffer *pipelined)
6b95a207 1944{
ce453d81 1945 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1946 u32 alignment;
1947 int ret;
1948
05394f39 1949 switch (obj->tiling_mode) {
6b95a207 1950 case I915_TILING_NONE:
534843da
CW		 1951 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952 alignment = 128 * 1024;
a6c45cf0 1953 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1954 alignment = 4 * 1024;
1955 else
1956 alignment = 64 * 1024;
6b95a207
KH		 1957 break;
1958 case I915_TILING_X:
1959 /* pin() will align the object as required by fence */
1960 alignment = 0;
1961 break;
1962 case I915_TILING_Y:
1963 /* FIXME: Is this true? */
1964 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965 return -EINVAL;
1966 default:
1967 BUG();
1968 }
1969
ce453d81 1970 dev_priv->mm.interruptible = false;
2da3b9b9 1971 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1972 if (ret)
ce453d81 1973 goto err_interruptible;
6b95a207
KH		 1974
1975 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976 * fence, whereas 965+ only requires a fence if using
1977 * framebuffer compression. For simplicity, we always install
1978 * a fence as the cost is not that onerous.
1979 */
06d98131 1980 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1981 if (ret)
1982 goto err_unpin;
1690e1eb 1983
9a5a53b3 1984 i915_gem_object_pin_fence(obj);
6b95a207 1985
ce453d81 1986 dev_priv->mm.interruptible = true;
6b95a207 1987 return 0;
48b956c5
CW		 1988
1989err_unpin:
1990 i915_gem_object_unpin(obj);
ce453d81
CW		 1991err_interruptible:
1992 dev_priv->mm.interruptible = true;
48b956c5 1993 return ret;
6b95a207
KH		 1994}
1995
1690e1eb
CW		 1996void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997{
1998 i915_gem_object_unpin_fence(obj);
1999 i915_gem_object_unpin(obj);
2000}
2001
c2c75131
DV		 2002/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003 * is assumed to be a power-of-two. */
5a35e99e
DL		 2004unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2005 unsigned int bpp,
2006 unsigned int pitch)
c2c75131
DV		 2007{
2008 int tile_rows, tiles;
2009
2010 tile_rows = *y / 8;
2011 *y %= 8;
2012 tiles = *x / (512/bpp);
2013 *x %= 512/bpp;
2014
2015 return tile_rows * pitch * 8 + tiles * 4096;
2016}
2017
17638cd6
JB		 2018static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2019 int x, int y)
81255565
JB		 2020{
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
05394f39 2025 struct drm_i915_gem_object *obj;
81255565 2026 int plane = intel_crtc->plane;
e506a0c6 2027 unsigned long linear_offset;
81255565 2028 u32 dspcntr;
5eddb70b 2029 u32 reg;
81255565
JB		 2030
2031 switch (plane) {
2032 case 0:
2033 case 1:
2034 break;
2035 default:
2036 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2037 return -EINVAL;
2038 }
2039
2040 intel_fb = to_intel_framebuffer(fb);
2041 obj = intel_fb->obj;
81255565 2042
5eddb70b
CW		 2043 reg = DSPCNTR(plane);
2044 dspcntr = I915_READ(reg);
81255565
JB		 2045 /* Mask out pixel format bits in case we change it */
2046 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2047 switch (fb->pixel_format) {
2048 case DRM_FORMAT_C8:
81255565
JB		 2049 dspcntr |= DISPPLANE_8BPP;
2050 break;
57779d06
VS		 2051 case DRM_FORMAT_XRGB1555:
2052 case DRM_FORMAT_ARGB1555:
2053 dspcntr |= DISPPLANE_BGRX555;
81255565 2054 break;
57779d06
VS		 2055 case DRM_FORMAT_RGB565:
2056 dspcntr |= DISPPLANE_BGRX565;
2057 break;
2058 case DRM_FORMAT_XRGB8888:
2059 case DRM_FORMAT_ARGB8888:
2060 dspcntr |= DISPPLANE_BGRX888;
2061 break;
2062 case DRM_FORMAT_XBGR8888:
2063 case DRM_FORMAT_ABGR8888:
2064 dspcntr |= DISPPLANE_RGBX888;
2065 break;
2066 case DRM_FORMAT_XRGB2101010:
2067 case DRM_FORMAT_ARGB2101010:
2068 dspcntr |= DISPPLANE_BGRX101010;
2069 break;
2070 case DRM_FORMAT_XBGR2101010:
2071 case DRM_FORMAT_ABGR2101010:
2072 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2073 break;
2074 default:
57779d06 2075 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2076 return -EINVAL;
2077 }
57779d06 2078
a6c45cf0 2079 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2080 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084 }
2085
5eddb70b 2086 I915_WRITE(reg, dspcntr);
81255565 2087
e506a0c6 2088 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2089
c2c75131
DV		 2090 if (INTEL_INFO(dev)->gen >= 4) {
2091 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2092 intel_gen4_compute_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
c2c75131
DV		 2095 linear_offset -= intel_crtc->dspaddr_offset;
2096 } else {
e506a0c6 2097 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2098 }
e506a0c6
DV		 2099
2100 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2103 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2104 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2108 } else
e506a0c6 2109 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2110 POSTING_READ(reg);
81255565 2111
17638cd6
JB		 2112 return 0;
2113}
2114
2115static int ironlake_update_plane(struct drm_crtc *crtc,
2116 struct drm_framebuffer *fb, int x, int y)
2117{
2118 struct drm_device *dev = crtc->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 struct intel_framebuffer *intel_fb;
2122 struct drm_i915_gem_object *obj;
2123 int plane = intel_crtc->plane;
e506a0c6 2124 unsigned long linear_offset;
17638cd6
JB		 2125 u32 dspcntr;
2126 u32 reg;
2127
2128 switch (plane) {
2129 case 0:
2130 case 1:
27f8227b 2131 case 2:
17638cd6
JB		 2132 break;
2133 default:
2134 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2135 return -EINVAL;
2136 }
2137
2138 intel_fb = to_intel_framebuffer(fb);
2139 obj = intel_fb->obj;
2140
2141 reg = DSPCNTR(plane);
2142 dspcntr = I915_READ(reg);
2143 /* Mask out pixel format bits in case we change it */
2144 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2145 switch (fb->pixel_format) {
2146 case DRM_FORMAT_C8:
17638cd6
JB		 2147 dspcntr |= DISPPLANE_8BPP;
2148 break;
57779d06
VS		 2149 case DRM_FORMAT_RGB565:
2150 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2151 break;
57779d06
VS		 2152 case DRM_FORMAT_XRGB8888:
2153 case DRM_FORMAT_ARGB8888:
2154 dspcntr |= DISPPLANE_BGRX888;
2155 break;
2156 case DRM_FORMAT_XBGR8888:
2157 case DRM_FORMAT_ABGR8888:
2158 dspcntr |= DISPPLANE_RGBX888;
2159 break;
2160 case DRM_FORMAT_XRGB2101010:
2161 case DRM_FORMAT_ARGB2101010:
2162 dspcntr |= DISPPLANE_BGRX101010;
2163 break;
2164 case DRM_FORMAT_XBGR2101010:
2165 case DRM_FORMAT_ABGR2101010:
2166 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2167 break;
2168 default:
57779d06 2169 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2170 return -EINVAL;
2171 }
2172
2173 if (obj->tiling_mode != I915_TILING_NONE)
2174 dspcntr |= DISPPLANE_TILED;
2175 else
2176 dspcntr &= ~DISPPLANE_TILED;
2177
2178 /* must disable */
2179 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2180
2181 I915_WRITE(reg, dspcntr);
2182
e506a0c6 2183 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2184 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2185 intel_gen4_compute_offset_xtiled(&x, &y,
2186 fb->bits_per_pixel / 8,
2187 fb->pitches[0]);
c2c75131 2188 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2189
e506a0c6
DV		 2190 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2192 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2193 I915_MODIFY_DISPBASE(DSPSURF(plane),
2194 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2195 if (IS_HASWELL(dev)) {
2196 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2197 } else {
2198 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199 I915_WRITE(DSPLINOFF(plane), linear_offset);
2200 }
17638cd6
JB		 2201 POSTING_READ(reg);
2202
2203 return 0;
2204}
2205
2206/* Assume fb object is pinned & idle & fenced and just update base pointers */
2207static int
2208intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209 int x, int y, enum mode_set_atomic state)
2210{
2211 struct drm_device *dev = crtc->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2213
6b8e6ed0
CW		 2214 if (dev_priv->display.disable_fbc)
2215 dev_priv->display.disable_fbc(dev);
3dec0095 2216 intel_increase_pllclock(crtc);
81255565 2217
6b8e6ed0 2218 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2219}
2220
14667a4b
CW		 2221static int
2222intel_finish_fb(struct drm_framebuffer *old_fb)
2223{
2224 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2226 bool was_interruptible = dev_priv->mm.interruptible;
2227 int ret;
2228
14667a4b
CW		 2229 /* Big Hammer, we also need to ensure that any pending
2230 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2231 * current scanout is retired before unpinning the old
2232 * framebuffer.
2233 *
2234 * This should only fail upon a hung GPU, in which case we
2235 * can safely continue.
2236 */
2237 dev_priv->mm.interruptible = false;
2238 ret = i915_gem_object_finish_gpu(obj);
2239 dev_priv->mm.interruptible = was_interruptible;
2240
2241 return ret;
2242}
2243
198598d0
VS		 2244static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2245{
2246 struct drm_device *dev = crtc->dev;
2247 struct drm_i915_master_private *master_priv;
2248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2249
2250 if (!dev->primary->master)
2251 return;
2252
2253 master_priv = dev->primary->master->driver_priv;
2254 if (!master_priv->sarea_priv)
2255 return;
2256
2257 switch (intel_crtc->pipe) {
2258 case 0:
2259 master_priv->sarea_priv->pipeA_x = x;
2260 master_priv->sarea_priv->pipeA_y = y;
2261 break;
2262 case 1:
2263 master_priv->sarea_priv->pipeB_x = x;
2264 master_priv->sarea_priv->pipeB_y = y;
2265 break;
2266 default:
2267 break;
2268 }
2269}
2270
5c3b82e2 2271static int
3c4fdcfb 2272intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2273 struct drm_framebuffer *fb)
79e53945
JB		 2274{
2275 struct drm_device *dev = crtc->dev;
6b8e6ed0 2276 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2278 struct drm_framebuffer *old_fb;
5c3b82e2 2279 int ret;
79e53945
JB		 2280
2281 /* no fb bound */
94352cf9 2282 if (!fb) {
a5071c2f 2283 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2284 return 0;
2285 }
2286
5826eca5
ED		 2287 if(intel_crtc->plane > dev_priv->num_pipe) {
2288 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2289 intel_crtc->plane,
2290 dev_priv->num_pipe);
5c3b82e2 2291 return -EINVAL;
79e53945
JB		 2292 }
2293
5c3b82e2 2294 mutex_lock(&dev->struct_mutex);
265db958 2295 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2296 to_intel_framebuffer(fb)->obj,
919926ae 2297 NULL);
5c3b82e2
CW		 2298 if (ret != 0) {
2299 mutex_unlock(&dev->struct_mutex);
a5071c2f 2300 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2301 return ret;
2302 }
79e53945 2303
94352cf9 2304 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2305 if (ret) {
94352cf9 2306 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2307 mutex_unlock(&dev->struct_mutex);
a5071c2f 2308 DRM_ERROR("failed to update base address\n");
4e6cfefc 2309 return ret;
79e53945 2310 }
3c4fdcfb 2311
94352cf9
DV		 2312 old_fb = crtc->fb;
2313 crtc->fb = fb;
6c4c86f5
DV		 2314 crtc->x = x;
2315 crtc->y = y;
94352cf9 2316
b7f1de28
CW		 2317 if (old_fb) {
2318 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2319 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2320 }
652c393a 2321
6b8e6ed0 2322 intel_update_fbc(dev);
5c3b82e2 2323 mutex_unlock(&dev->struct_mutex);
79e53945 2324
198598d0 2325 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2326
2327 return 0;
79e53945
JB		 2328}
2329
5e84e1a4
ZW		 2330static void intel_fdi_normal_train(struct drm_crtc *crtc)
2331{
2332 struct drm_device *dev = crtc->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2335 int pipe = intel_crtc->pipe;
2336 u32 reg, temp;
2337
2338 /* enable normal train */
2339 reg = FDI_TX_CTL(pipe);
2340 temp = I915_READ(reg);
61e499bf 2341 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2342 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2343 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2344 } else {
2345 temp &= ~FDI_LINK_TRAIN_NONE;
2346 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2347 }
5e84e1a4
ZW		 2348 I915_WRITE(reg, temp);
2349
2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
2352 if (HAS_PCH_CPT(dev)) {
2353 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2354 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2355 } else {
2356 temp &= ~FDI_LINK_TRAIN_NONE;
2357 temp |= FDI_LINK_TRAIN_NONE;
2358 }
2359 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2360
2361 /* wait one idle pattern time */
2362 POSTING_READ(reg);
2363 udelay(1000);
357555c0
JB		 2364
2365 /* IVB wants error correction enabled */
2366 if (IS_IVYBRIDGE(dev))
2367 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2368 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2369}
2370
01a415fd
DV		 2371static void ivb_modeset_global_resources(struct drm_device *dev)
2372{
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct intel_crtc *pipe_B_crtc =
2375 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2376 struct intel_crtc *pipe_C_crtc =
2377 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2378 uint32_t temp;
2379
2380 /* When everything is off disable fdi C so that we could enable fdi B
2381 * with all lanes. XXX: This misses the case where a pipe is not using
2382 * any pch resources and so doesn't need any fdi lanes. */
2383 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2384 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2385 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2386
2387 temp = I915_READ(SOUTH_CHICKEN1);
2388 temp &= ~FDI_BC_BIFURCATION_SELECT;
2389 DRM_DEBUG_KMS("disabling fdi C rx\n");
2390 I915_WRITE(SOUTH_CHICKEN1, temp);
2391 }
2392}
2393
8db9d77b
ZW		 2394/* The FDI link training functions for ILK/Ibexpeak. */
2395static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2396{
2397 struct drm_device *dev = crtc->dev;
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2400 int pipe = intel_crtc->pipe;
0fc932b8 2401 int plane = intel_crtc->plane;
5eddb70b 2402 u32 reg, temp, tries;
8db9d77b 2403
0fc932b8
JB		 2404 /* FDI needs bits from pipe & plane first */
2405 assert_pipe_enabled(dev_priv, pipe);
2406 assert_plane_enabled(dev_priv, plane);
2407
e1a44743
AJ		 2408 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2409 for train result */
5eddb70b
CW		 2410 reg = FDI_RX_IMR(pipe);
2411 temp = I915_READ(reg);
e1a44743
AJ		 2412 temp &= ~FDI_RX_SYMBOL_LOCK;
2413 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2414 I915_WRITE(reg, temp);
2415 I915_READ(reg);
e1a44743
AJ		 2416 udelay(150);
2417
8db9d77b 2418 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2419 reg = FDI_TX_CTL(pipe);
2420 temp = I915_READ(reg);
77ffb597
AJ		 2421 temp &= ~(7 << 19);
2422 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2423 temp &= ~FDI_LINK_TRAIN_NONE;
2424 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2425 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2426
5eddb70b
CW		 2427 reg = FDI_RX_CTL(pipe);
2428 temp = I915_READ(reg);
8db9d77b
ZW		 2429 temp &= ~FDI_LINK_TRAIN_NONE;
2430 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2431 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2432
2433 POSTING_READ(reg);
8db9d77b
ZW		 2434 udelay(150);
2435
5b2adf89 2436 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2437 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2438 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2439 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2440
5eddb70b 2441 reg = FDI_RX_IIR(pipe);
e1a44743 2442 for (tries = 0; tries < 5; tries++) {
5eddb70b 2443 temp = I915_READ(reg);
8db9d77b
ZW		 2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if ((temp & FDI_RX_BIT_LOCK)) {
2447 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2448 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2449 break;
2450 }
8db9d77b 2451 }
e1a44743 2452 if (tries == 5)
5eddb70b 2453 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2454
2455 /* Train 2 */
5eddb70b
CW		 2456 reg = FDI_TX_CTL(pipe);
2457 temp = I915_READ(reg);
8db9d77b
ZW		 2458 temp &= ~FDI_LINK_TRAIN_NONE;
2459 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2460 I915_WRITE(reg, temp);
8db9d77b 2461
5eddb70b
CW		 2462 reg = FDI_RX_CTL(pipe);
2463 temp = I915_READ(reg);
8db9d77b
ZW		 2464 temp &= ~FDI_LINK_TRAIN_NONE;
2465 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2466 I915_WRITE(reg, temp);
8db9d77b 2467
5eddb70b
CW		 2468 POSTING_READ(reg);
2469 udelay(150);
8db9d77b 2470
5eddb70b 2471 reg = FDI_RX_IIR(pipe);
e1a44743 2472 for (tries = 0; tries < 5; tries++) {
5eddb70b 2473 temp = I915_READ(reg);
8db9d77b
ZW		 2474 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2475
2476 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2477 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2478 DRM_DEBUG_KMS("FDI train 2 done.\n");
2479 break;
2480 }
8db9d77b 2481 }
e1a44743 2482 if (tries == 5)
5eddb70b 2483 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2484
2485 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2486
8db9d77b
ZW		 2487}
2488
0206e353 2489static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2490 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2491 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2492 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2493 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2494};
2495
2496/* The FDI link training functions for SNB/Cougarpoint. */
2497static void gen6_fdi_link_train(struct drm_crtc *crtc)
2498{
2499 struct drm_device *dev = crtc->dev;
2500 struct drm_i915_private *dev_priv = dev->dev_private;
2501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2502 int pipe = intel_crtc->pipe;
fa37d39e 2503 u32 reg, temp, i, retry;
8db9d77b 2504
e1a44743
AJ		 2505 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2506 for train result */
5eddb70b
CW		 2507 reg = FDI_RX_IMR(pipe);
2508 temp = I915_READ(reg);
e1a44743
AJ		 2509 temp &= ~FDI_RX_SYMBOL_LOCK;
2510 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2511 I915_WRITE(reg, temp);
2512
2513 POSTING_READ(reg);
e1a44743
AJ		 2514 udelay(150);
2515
8db9d77b 2516 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2517 reg = FDI_TX_CTL(pipe);
2518 temp = I915_READ(reg);
77ffb597
AJ		 2519 temp &= ~(7 << 19);
2520 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2521 temp &= ~FDI_LINK_TRAIN_NONE;
2522 temp |= FDI_LINK_TRAIN_PATTERN_1;
2523 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2524 /* SNB-B */
2525 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2526 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2527
d74cf324
DV		 2528 I915_WRITE(FDI_RX_MISC(pipe),
2529 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2530
5eddb70b
CW		 2531 reg = FDI_RX_CTL(pipe);
2532 temp = I915_READ(reg);
8db9d77b
ZW		 2533 if (HAS_PCH_CPT(dev)) {
2534 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2535 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2536 } else {
2537 temp &= ~FDI_LINK_TRAIN_NONE;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1;
2539 }
5eddb70b
CW		 2540 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2541
2542 POSTING_READ(reg);
8db9d77b
ZW		 2543 udelay(150);
2544
0206e353 2545 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2546 reg = FDI_TX_CTL(pipe);
2547 temp = I915_READ(reg);
8db9d77b
ZW		 2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2550 I915_WRITE(reg, temp);
2551
2552 POSTING_READ(reg);
8db9d77b
ZW		 2553 udelay(500);
2554
fa37d39e
SP		 2555 for (retry = 0; retry < 5; retry++) {
2556 reg = FDI_RX_IIR(pipe);
2557 temp = I915_READ(reg);
2558 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2559 if (temp & FDI_RX_BIT_LOCK) {
2560 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2561 DRM_DEBUG_KMS("FDI train 1 done.\n");
2562 break;
2563 }
2564 udelay(50);
8db9d77b 2565 }
fa37d39e
SP		 2566 if (retry < 5)
2567 break;
8db9d77b
ZW		 2568 }
2569 if (i == 4)
5eddb70b 2570 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2571
2572 /* Train 2 */
5eddb70b
CW		 2573 reg = FDI_TX_CTL(pipe);
2574 temp = I915_READ(reg);
8db9d77b
ZW		 2575 temp &= ~FDI_LINK_TRAIN_NONE;
2576 temp |= FDI_LINK_TRAIN_PATTERN_2;
2577 if (IS_GEN6(dev)) {
2578 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2579 /* SNB-B */
2580 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2581 }
5eddb70b 2582 I915_WRITE(reg, temp);
8db9d77b 2583
5eddb70b
CW		 2584 reg = FDI_RX_CTL(pipe);
2585 temp = I915_READ(reg);
8db9d77b
ZW		 2586 if (HAS_PCH_CPT(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2588 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2589 } else {
2590 temp &= ~FDI_LINK_TRAIN_NONE;
2591 temp |= FDI_LINK_TRAIN_PATTERN_2;
2592 }
5eddb70b
CW		 2593 I915_WRITE(reg, temp);
2594
2595 POSTING_READ(reg);
8db9d77b
ZW		 2596 udelay(150);
2597
0206e353 2598 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2599 reg = FDI_TX_CTL(pipe);
2600 temp = I915_READ(reg);
8db9d77b
ZW		 2601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2602 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2603 I915_WRITE(reg, temp);
2604
2605 POSTING_READ(reg);
8db9d77b
ZW		 2606 udelay(500);
2607
fa37d39e
SP		 2608 for (retry = 0; retry < 5; retry++) {
2609 reg = FDI_RX_IIR(pipe);
2610 temp = I915_READ(reg);
2611 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2612 if (temp & FDI_RX_SYMBOL_LOCK) {
2613 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2614 DRM_DEBUG_KMS("FDI train 2 done.\n");
2615 break;
2616 }
2617 udelay(50);
8db9d77b 2618 }
fa37d39e
SP		 2619 if (retry < 5)
2620 break;
8db9d77b
ZW		 2621 }
2622 if (i == 4)
5eddb70b 2623 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2624
2625 DRM_DEBUG_KMS("FDI train done.\n");
2626}
2627
357555c0
JB		 2628/* Manual link training for Ivy Bridge A0 parts */
2629static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2630{
2631 struct drm_device *dev = crtc->dev;
2632 struct drm_i915_private *dev_priv = dev->dev_private;
2633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2634 int pipe = intel_crtc->pipe;
2635 u32 reg, temp, i;
2636
2637 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2638 for train result */
2639 reg = FDI_RX_IMR(pipe);
2640 temp = I915_READ(reg);
2641 temp &= ~FDI_RX_SYMBOL_LOCK;
2642 temp &= ~FDI_RX_BIT_LOCK;
2643 I915_WRITE(reg, temp);
2644
2645 POSTING_READ(reg);
2646 udelay(150);
2647
01a415fd
DV		 2648 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2649 I915_READ(FDI_RX_IIR(pipe)));
2650
357555c0
JB		 2651 /* enable CPU FDI TX and PCH FDI RX */
2652 reg = FDI_TX_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~(7 << 19);
2655 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2656 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2657 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2658 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2659 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2660 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2661 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2662
d74cf324
DV		 2663 I915_WRITE(FDI_RX_MISC(pipe),
2664 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2665
357555c0
JB		 2666 reg = FDI_RX_CTL(pipe);
2667 temp = I915_READ(reg);
2668 temp &= ~FDI_LINK_TRAIN_AUTO;
2669 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2670 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2671 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2672 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2673
2674 POSTING_READ(reg);
2675 udelay(150);
2676
0206e353 2677 for (i = 0; i < 4; i++) {
357555c0
JB		 2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2681 temp |= snb_b_fdi_train_param[i];
2682 I915_WRITE(reg, temp);
2683
2684 POSTING_READ(reg);
2685 udelay(500);
2686
2687 reg = FDI_RX_IIR(pipe);
2688 temp = I915_READ(reg);
2689 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2690
2691 if (temp & FDI_RX_BIT_LOCK ||
2692 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2693 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2694 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2695 break;
2696 }
2697 }
2698 if (i == 4)
2699 DRM_ERROR("FDI train 1 fail!\n");
2700
2701 /* Train 2 */
2702 reg = FDI_TX_CTL(pipe);
2703 temp = I915_READ(reg);
2704 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2705 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2706 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2707 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2708 I915_WRITE(reg, temp);
2709
2710 reg = FDI_RX_CTL(pipe);
2711 temp = I915_READ(reg);
2712 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2713 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2714 I915_WRITE(reg, temp);
2715
2716 POSTING_READ(reg);
2717 udelay(150);
2718
0206e353 2719 for (i = 0; i < 4; i++) {
357555c0
JB		 2720 reg = FDI_TX_CTL(pipe);
2721 temp = I915_READ(reg);
2722 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2723 temp |= snb_b_fdi_train_param[i];
2724 I915_WRITE(reg, temp);
2725
2726 POSTING_READ(reg);
2727 udelay(500);
2728
2729 reg = FDI_RX_IIR(pipe);
2730 temp = I915_READ(reg);
2731 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2732
2733 if (temp & FDI_RX_SYMBOL_LOCK) {
2734 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2735 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2736 break;
2737 }
2738 }
2739 if (i == 4)
2740 DRM_ERROR("FDI train 2 fail!\n");
2741
2742 DRM_DEBUG_KMS("FDI train done.\n");
2743}
2744
88cefb6c 2745static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2746{
88cefb6c 2747 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2748 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2749 int pipe = intel_crtc->pipe;
5eddb70b 2750 u32 reg, temp;
79e53945 2751
c64e311e 2752
c98e9dcf 2753 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2754 reg = FDI_RX_CTL(pipe);
2755 temp = I915_READ(reg);
2756 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2757 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2758 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2759 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2760
2761 POSTING_READ(reg);
c98e9dcf
JB		 2762 udelay(200);
2763
2764 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2765 temp = I915_READ(reg);
2766 I915_WRITE(reg, temp | FDI_PCDCLK);
2767
2768 POSTING_READ(reg);
c98e9dcf
JB		 2769 udelay(200);
2770
20749730
PZ		 2771 /* Enable CPU FDI TX PLL, always on for Ironlake */
2772 reg = FDI_TX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2775 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2776
20749730
PZ		 2777 POSTING_READ(reg);
2778 udelay(100);
6be4a607 2779 }
0e23b99d
JB		 2780}
2781
88cefb6c
DV		 2782static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2783{
2784 struct drm_device *dev = intel_crtc->base.dev;
2785 struct drm_i915_private *dev_priv = dev->dev_private;
2786 int pipe = intel_crtc->pipe;
2787 u32 reg, temp;
2788
2789 /* Switch from PCDclk to Rawclk */
2790 reg = FDI_RX_CTL(pipe);
2791 temp = I915_READ(reg);
2792 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2793
2794 /* Disable CPU FDI TX PLL */
2795 reg = FDI_TX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2798
2799 POSTING_READ(reg);
2800 udelay(100);
2801
2802 reg = FDI_RX_CTL(pipe);
2803 temp = I915_READ(reg);
2804 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2805
2806 /* Wait for the clocks to turn off. */
2807 POSTING_READ(reg);
2808 udelay(100);
2809}
2810
0fc932b8
JB		 2811static void ironlake_fdi_disable(struct drm_crtc *crtc)
2812{
2813 struct drm_device *dev = crtc->dev;
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2816 int pipe = intel_crtc->pipe;
2817 u32 reg, temp;
2818
2819 /* disable CPU FDI tx and PCH FDI rx */
2820 reg = FDI_TX_CTL(pipe);
2821 temp = I915_READ(reg);
2822 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2823 POSTING_READ(reg);
2824
2825 reg = FDI_RX_CTL(pipe);
2826 temp = I915_READ(reg);
2827 temp &= ~(0x7 << 16);
dfd07d72 2828 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2829 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2830
2831 POSTING_READ(reg);
2832 udelay(100);
2833
2834 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2835 if (HAS_PCH_IBX(dev)) {
2836 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2837 }
0fc932b8
JB		 2838
2839 /* still set train pattern 1 */
2840 reg = FDI_TX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844 I915_WRITE(reg, temp);
2845
2846 reg = FDI_RX_CTL(pipe);
2847 temp = I915_READ(reg);
2848 if (HAS_PCH_CPT(dev)) {
2849 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2850 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2851 } else {
2852 temp &= ~FDI_LINK_TRAIN_NONE;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1;
2854 }
2855 /* BPC in FDI rx is consistent with that in PIPECONF */
2856 temp &= ~(0x07 << 16);
dfd07d72 2857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2858 I915_WRITE(reg, temp);
2859
2860 POSTING_READ(reg);
2861 udelay(100);
2862}
2863
5bb61643
CW		 2864static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2865{
2866 struct drm_device *dev = crtc->dev;
2867 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2869 unsigned long flags;
2870 bool pending;
2871
10d83730
VS		 2872 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2873 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2874 return false;
2875
2876 spin_lock_irqsave(&dev->event_lock, flags);
2877 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2878 spin_unlock_irqrestore(&dev->event_lock, flags);
2879
2880 return pending;
2881}
2882
e6c3a2a6
CW		 2883static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2884{
0f91128d 2885 struct drm_device *dev = crtc->dev;
5bb61643 2886 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2887
2888 if (crtc->fb == NULL)
2889 return;
2890
2c10d571
DV		 2891 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2892
5bb61643
CW		 2893 wait_event(dev_priv->pending_flip_queue,
2894 !intel_crtc_has_pending_flip(crtc));
2895
0f91128d
CW		 2896 mutex_lock(&dev->struct_mutex);
2897 intel_finish_fb(crtc->fb);
2898 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2899}
2900
fc316cbe 2901static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2902{
2903 struct drm_device *dev = crtc->dev;
228d3e36 2904 struct intel_encoder *intel_encoder;
040484af
JB		 2905
2906 /*
2907 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2908 * must be driven by its own crtc; no sharing is possible.
2909 */
228d3e36 2910 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2911 switch (intel_encoder->type) {
040484af 2912 case INTEL_OUTPUT_EDP:
228d3e36 2913 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2914 return false;
2915 continue;
2916 }
2917 }
2918
2919 return true;
2920}
2921
fc316cbe
PZ		 2922static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2923{
2924 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2925}
2926
e615efe4
ED		 2927/* Program iCLKIP clock to the desired frequency */
2928static void lpt_program_iclkip(struct drm_crtc *crtc)
2929{
2930 struct drm_device *dev = crtc->dev;
2931 struct drm_i915_private *dev_priv = dev->dev_private;
2932 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2933 u32 temp;
2934
09153000
DV		 2935 mutex_lock(&dev_priv->dpio_lock);
2936
e615efe4
ED		 2937 /* It is necessary to ungate the pixclk gate prior to programming
2938 * the divisors, and gate it back when it is done.
2939 */
2940 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2941
2942 /* Disable SSCCTL */
2943 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2944 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2945 SBI_SSCCTL_DISABLE,
2946 SBI_ICLK);
e615efe4
ED		 2947
2948 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2949 if (crtc->mode.clock == 20000) {
2950 auxdiv = 1;
2951 divsel = 0x41;
2952 phaseinc = 0x20;
2953 } else {
2954 /* The iCLK virtual clock root frequency is in MHz,
2955 * but the crtc->mode.clock in in KHz. To get the divisors,
2956 * it is necessary to divide one by another, so we
2957 * convert the virtual clock precision to KHz here for higher
2958 * precision.
2959 */
2960 u32 iclk_virtual_root_freq = 172800 * 1000;
2961 u32 iclk_pi_range = 64;
2962 u32 desired_divisor, msb_divisor_value, pi_value;
2963
2964 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2965 msb_divisor_value = desired_divisor / iclk_pi_range;
2966 pi_value = desired_divisor % iclk_pi_range;
2967
2968 auxdiv = 0;
2969 divsel = msb_divisor_value - 2;
2970 phaseinc = pi_value;
2971 }
2972
2973 /* This should not happen with any sane values */
2974 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2975 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2976 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2977 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2978
2979 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2980 crtc->mode.clock,
2981 auxdiv,
2982 divsel,
2983 phasedir,
2984 phaseinc);
2985
2986 /* Program SSCDIVINTPHASE6 */
988d6ee8 2987 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2988 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2989 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2990 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2991 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2992 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2993 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2994 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2995
2996 /* Program SSCAUXDIV */
988d6ee8 2997 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2998 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2999 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3000 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3001
3002 /* Enable modulator and associated divider */
988d6ee8 3003 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3004 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3005 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3006
3007 /* Wait for initialization time */
3008 udelay(24);
3009
3010 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3011
3012 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3013}
3014
f67a559d
JB		 3015/*
3016 * Enable PCH resources required for PCH ports:
3017 * - PCH PLLs
3018 * - FDI training & RX/TX
3019 * - update transcoder timings
3020 * - DP transcoding bits
3021 * - transcoder
3022 */
3023static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3024{
3025 struct drm_device *dev = crtc->dev;
3026 struct drm_i915_private *dev_priv = dev->dev_private;
3027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3028 int pipe = intel_crtc->pipe;
ee7b9f93 3029 u32 reg, temp;
2c07245f 3030
e7e164db
CW		 3031 assert_transcoder_disabled(dev_priv, pipe);
3032
cd986abb
DV		 3033 /* Write the TU size bits before fdi link training, so that error
3034 * detection works. */
3035 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3036 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3037
c98e9dcf 3038 /* For PCH output, training FDI link */
674cf967 3039 dev_priv->display.fdi_link_train(crtc);
2c07245f 3040
572deb37
DV		 3041 /* XXX: pch pll's can be enabled any time before we enable the PCH
3042 * transcoder, and we actually should do this to not upset any PCH
3043 * transcoder that already use the clock when we share it.
3044 *
3045 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3046 * unconditionally resets the pll - we need that to have the right LVDS
3047 * enable sequence. */
b6b4e185 3048 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3049
303b81e0 3050 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3051 u32 sel;
4b645f14 3052
c98e9dcf 3053 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3054 switch (pipe) {
3055 default:
3056 case 0:
3057 temp |= TRANSA_DPLL_ENABLE;
3058 sel = TRANSA_DPLLB_SEL;
3059 break;
3060 case 1:
3061 temp |= TRANSB_DPLL_ENABLE;
3062 sel = TRANSB_DPLLB_SEL;
3063 break;
3064 case 2:
3065 temp |= TRANSC_DPLL_ENABLE;
3066 sel = TRANSC_DPLLB_SEL;
3067 break;
d64311ab 3068 }
ee7b9f93
JB		 3069 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3070 temp |= sel;
3071 else
3072 temp &= ~sel;
c98e9dcf 3073 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3074 }
5eddb70b 3075
d9b6cb56
JB		 3076 /* set transcoder timing, panel must allow it */
3077 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3078 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3079 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3080 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3081
5eddb70b
CW		 3082 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3083 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3084 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3085 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3086
303b81e0 3087 intel_fdi_normal_train(crtc);
5e84e1a4 3088
c98e9dcf
JB		 3089 /* For PCH DP, enable TRANS_DP_CTL */
3090 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3091 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3092 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3093 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3094 reg = TRANS_DP_CTL(pipe);
3095 temp = I915_READ(reg);
3096 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3097 TRANS_DP_SYNC_MASK |
3098 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3099 temp |= (TRANS_DP_OUTPUT_ENABLE |
3100 TRANS_DP_ENH_FRAMING);
9325c9f0 3101 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3102
3103 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3104 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3105 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3106 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3107
3108 switch (intel_trans_dp_port_sel(crtc)) {
3109 case PCH_DP_B:
5eddb70b 3110 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3111 break;
3112 case PCH_DP_C:
5eddb70b 3113 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3114 break;
3115 case PCH_DP_D:
5eddb70b 3116 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3117 break;
3118 default:
e95d41e1 3119 BUG();
32f9d658 3120 }
2c07245f 3121
5eddb70b 3122 I915_WRITE(reg, temp);
6be4a607 3123 }
b52eb4dc 3124
b8a4f404 3125 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3126}
3127
1507e5bd
PZ		 3128static void lpt_pch_enable(struct drm_crtc *crtc)
3129{
3130 struct drm_device *dev = crtc->dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3133 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3134
daed2dbb 3135 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3136
8c52b5e8 3137 lpt_program_iclkip(crtc);
1507e5bd 3138
0540e488 3139 /* Set transcoder timing. */
daed2dbb
PZ		 3140 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3141 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3142 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3143
daed2dbb
PZ		 3144 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3145 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3146 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3147 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3148
937bb610 3149 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3150}
3151
ee7b9f93
JB		 3152static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3153{
3154 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3155
3156 if (pll == NULL)
3157 return;
3158
3159 if (pll->refcount == 0) {
3160 WARN(1, "bad PCH PLL refcount\n");
3161 return;
3162 }
3163
3164 --pll->refcount;
3165 intel_crtc->pch_pll = NULL;
3166}
3167
3168static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3169{
3170 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3171 struct intel_pch_pll *pll;
3172 int i;
3173
3174 pll = intel_crtc->pch_pll;
3175 if (pll) {
3176 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3177 intel_crtc->base.base.id, pll->pll_reg);
3178 goto prepare;
3179 }
3180
98b6bd99
DV		 3181 if (HAS_PCH_IBX(dev_priv->dev)) {
3182 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3183 i = intel_crtc->pipe;
3184 pll = &dev_priv->pch_plls[i];
3185
3186 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3187 intel_crtc->base.base.id, pll->pll_reg);
3188
3189 goto found;
3190 }
3191
ee7b9f93
JB		 3192 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3193 pll = &dev_priv->pch_plls[i];
3194
3195 /* Only want to check enabled timings first */
3196 if (pll->refcount == 0)
3197 continue;
3198
3199 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3200 fp == I915_READ(pll->fp0_reg)) {
3201 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3202 intel_crtc->base.base.id,
3203 pll->pll_reg, pll->refcount, pll->active);
3204
3205 goto found;
3206 }
3207 }
3208
3209 /* Ok no matching timings, maybe there's a free one? */
3210 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3211 pll = &dev_priv->pch_plls[i];
3212 if (pll->refcount == 0) {
3213 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3214 intel_crtc->base.base.id, pll->pll_reg);
3215 goto found;
3216 }
3217 }
3218
3219 return NULL;
3220
3221found:
3222 intel_crtc->pch_pll = pll;
3223 pll->refcount++;
3224 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3225prepare: /* separate function? */
3226 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3227
e04c7350
CW		 3228 /* Wait for the clocks to stabilize before rewriting the regs */
3229 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3230 POSTING_READ(pll->pll_reg);
3231 udelay(150);
e04c7350
CW		 3232
3233 I915_WRITE(pll->fp0_reg, fp);
3234 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3235 pll->on = false;
3236 return pll;
3237}
3238
d4270e57
JB		 3239void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3240{
3241 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3242 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3243 u32 temp;
3244
3245 temp = I915_READ(dslreg);
3246 udelay(500);
3247 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3248 if (wait_for(I915_READ(dslreg) != temp, 5))
3249 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3250 }
3251}
3252
f67a559d
JB		 3253static void ironlake_crtc_enable(struct drm_crtc *crtc)
3254{
3255 struct drm_device *dev = crtc->dev;
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3258 struct intel_encoder *encoder;
f67a559d
JB		 3259 int pipe = intel_crtc->pipe;
3260 int plane = intel_crtc->plane;
3261 u32 temp;
3262 bool is_pch_port;
3263
08a48469
DV		 3264 WARN_ON(!crtc->enabled);
3265
f67a559d
JB		 3266 if (intel_crtc->active)
3267 return;
3268
3269 intel_crtc->active = true;
3270 intel_update_watermarks(dev);
3271
3272 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3273 temp = I915_READ(PCH_LVDS);
3274 if ((temp & LVDS_PORT_EN) == 0)
3275 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3276 }
3277
fc316cbe 3278 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3279
46b6f814 3280 if (is_pch_port) {
fff367c7
DV		 3281 /* Note: FDI PLL enabling _must_ be done before we enable the
3282 * cpu pipes, hence this is separate from all the other fdi/pch
3283 * enabling. */
88cefb6c 3284 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3285 } else {
3286 assert_fdi_tx_disabled(dev_priv, pipe);
3287 assert_fdi_rx_disabled(dev_priv, pipe);
3288 }
f67a559d 3289
bf49ec8c
DV		 3290 for_each_encoder_on_crtc(dev, crtc, encoder)
3291 if (encoder->pre_enable)
3292 encoder->pre_enable(encoder);
f67a559d
JB		 3293
3294 /* Enable panel fitting for LVDS */
3295 if (dev_priv->pch_pf_size &&
547dc041
JN		 3296 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3297 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3298 /* Force use of hard-coded filter coefficients
3299 * as some pre-programmed values are broken,
3300 * e.g. x201.
3301 */
13888d78
PZ		 3302 if (IS_IVYBRIDGE(dev))
3303 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3304 PF_PIPE_SEL_IVB(pipe));
3305 else
3306 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3307 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3308 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3309 }
3310
9c54c0dd
JB		 3311 /*
3312 * On ILK+ LUT must be loaded before the pipe is running but with
3313 * clocks enabled
3314 */
3315 intel_crtc_load_lut(crtc);
3316
f67a559d
JB		 3317 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3318 intel_enable_plane(dev_priv, plane, pipe);
3319
3320 if (is_pch_port)
3321 ironlake_pch_enable(crtc);
c98e9dcf 3322
d1ebd816 3323 mutex_lock(&dev->struct_mutex);
bed4a673 3324 intel_update_fbc(dev);
d1ebd816
BW		 3325 mutex_unlock(&dev->struct_mutex);
3326
6b383a7f 3327 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3328
fa5c73b1
DV		 3329 for_each_encoder_on_crtc(dev, crtc, encoder)
3330 encoder->enable(encoder);
61b77ddd
DV		 3331
3332 if (HAS_PCH_CPT(dev))
3333 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3334
3335 /*
3336 * There seems to be a race in PCH platform hw (at least on some
3337 * outputs) where an enabled pipe still completes any pageflip right
3338 * away (as if the pipe is off) instead of waiting for vblank. As soon
3339 * as the first vblank happend, everything works as expected. Hence just
3340 * wait for one vblank before returning to avoid strange things
3341 * happening.
3342 */
3343 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3344}
3345
4f771f10
PZ		 3346static void haswell_crtc_enable(struct drm_crtc *crtc)
3347{
3348 struct drm_device *dev = crtc->dev;
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351 struct intel_encoder *encoder;
3352 int pipe = intel_crtc->pipe;
3353 int plane = intel_crtc->plane;
4f771f10
PZ		 3354 bool is_pch_port;
3355
3356 WARN_ON(!crtc->enabled);
3357
3358 if (intel_crtc->active)
3359 return;
3360
3361 intel_crtc->active = true;
3362 intel_update_watermarks(dev);
3363
fc316cbe 3364 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3365
83616634 3366 if (is_pch_port)
04945641 3367 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3368
3369 for_each_encoder_on_crtc(dev, crtc, encoder)
3370 if (encoder->pre_enable)
3371 encoder->pre_enable(encoder);
3372
1f544388 3373 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3374
1f544388 3375 /* Enable panel fitting for eDP */
547dc041
JN		 3376 if (dev_priv->pch_pf_size &&
3377 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3378 /* Force use of hard-coded filter coefficients
3379 * as some pre-programmed values are broken,
3380 * e.g. x201.
3381 */
54075a7d
PZ		 3382 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3383 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3384 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3385 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3386 }
3387
3388 /*
3389 * On ILK+ LUT must be loaded before the pipe is running but with
3390 * clocks enabled
3391 */
3392 intel_crtc_load_lut(crtc);
3393
1f544388
PZ		 3394 intel_ddi_set_pipe_settings(crtc);
3395 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3396
3397 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3398 intel_enable_plane(dev_priv, plane, pipe);
3399
3400 if (is_pch_port)
1507e5bd 3401 lpt_pch_enable(crtc);
4f771f10
PZ		 3402
3403 mutex_lock(&dev->struct_mutex);
3404 intel_update_fbc(dev);
3405 mutex_unlock(&dev->struct_mutex);
3406
3407 intel_crtc_update_cursor(crtc, true);
3408
3409 for_each_encoder_on_crtc(dev, crtc, encoder)
3410 encoder->enable(encoder);
3411
4f771f10
PZ		 3412 /*
3413 * There seems to be a race in PCH platform hw (at least on some
3414 * outputs) where an enabled pipe still completes any pageflip right
3415 * away (as if the pipe is off) instead of waiting for vblank. As soon
3416 * as the first vblank happend, everything works as expected. Hence just
3417 * wait for one vblank before returning to avoid strange things
3418 * happening.
3419 */
3420 intel_wait_for_vblank(dev, intel_crtc->pipe);
3421}
3422
6be4a607
JB		 3423static void ironlake_crtc_disable(struct drm_crtc *crtc)
3424{
3425 struct drm_device *dev = crtc->dev;
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3428 struct intel_encoder *encoder;
6be4a607
JB		 3429 int pipe = intel_crtc->pipe;
3430 int plane = intel_crtc->plane;
5eddb70b 3431 u32 reg, temp;
b52eb4dc 3432
ef9c3aee 3433
f7abfe8b
CW		 3434 if (!intel_crtc->active)
3435 return;
3436
ea9d758d
DV		 3437 for_each_encoder_on_crtc(dev, crtc, encoder)
3438 encoder->disable(encoder);
3439
e6c3a2a6 3440 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3441 drm_vblank_off(dev, pipe);
6b383a7f 3442 intel_crtc_update_cursor(crtc, false);
5eddb70b 3443
b24e7179 3444 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3445
973d04f9
CW		 3446 if (dev_priv->cfb_plane == plane)
3447 intel_disable_fbc(dev);
2c07245f 3448
b24e7179 3449 intel_disable_pipe(dev_priv, pipe);
32f9d658 3450
6be4a607 3451 /* Disable PF */
9db4a9c7
JB		 3452 I915_WRITE(PF_CTL(pipe), 0);
3453 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3454
bf49ec8c
DV		 3455 for_each_encoder_on_crtc(dev, crtc, encoder)
3456 if (encoder->post_disable)
3457 encoder->post_disable(encoder);
2c07245f 3458
0fc932b8 3459 ironlake_fdi_disable(crtc);
249c0e64 3460
b8a4f404 3461 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3462
6be4a607
JB		 3463 if (HAS_PCH_CPT(dev)) {
3464 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3465 reg = TRANS_DP_CTL(pipe);
3466 temp = I915_READ(reg);
3467 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3468 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3469 I915_WRITE(reg, temp);
6be4a607
JB		 3470
3471 /* disable DPLL_SEL */
3472 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3473 switch (pipe) {
3474 case 0:
d64311ab 3475 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3476 break;
3477 case 1:
6be4a607 3478 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3479 break;
3480 case 2:
4b645f14 3481 /* C shares PLL A or B */
d64311ab 3482 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3483 break;
3484 default:
3485 BUG(); /* wtf */
3486 }
6be4a607 3487 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3488 }
e3421a18 3489
6be4a607 3490 /* disable PCH DPLL */
ee7b9f93 3491 intel_disable_pch_pll(intel_crtc);
8db9d77b 3492
88cefb6c 3493 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3494
f7abfe8b 3495 intel_crtc->active = false;
6b383a7f 3496 intel_update_watermarks(dev);
d1ebd816
BW		 3497
3498 mutex_lock(&dev->struct_mutex);
6b383a7f 3499 intel_update_fbc(dev);
d1ebd816 3500 mutex_unlock(&dev->struct_mutex);
6be4a607 3501}
1b3c7a47 3502
4f771f10 3503static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3504{
4f771f10
PZ		 3505 struct drm_device *dev = crtc->dev;
3506 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3508 struct intel_encoder *encoder;
3509 int pipe = intel_crtc->pipe;
3510 int plane = intel_crtc->plane;
ad80a810 3511 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3512 bool is_pch_port;
ee7b9f93 3513
4f771f10
PZ		 3514 if (!intel_crtc->active)
3515 return;
3516
83616634
PZ		 3517 is_pch_port = haswell_crtc_driving_pch(crtc);
3518
4f771f10
PZ		 3519 for_each_encoder_on_crtc(dev, crtc, encoder)
3520 encoder->disable(encoder);
3521
3522 intel_crtc_wait_for_pending_flips(crtc);
3523 drm_vblank_off(dev, pipe);
3524 intel_crtc_update_cursor(crtc, false);
3525
3526 intel_disable_plane(dev_priv, plane, pipe);
3527
3528 if (dev_priv->cfb_plane == plane)
3529 intel_disable_fbc(dev);
3530
3531 intel_disable_pipe(dev_priv, pipe);
3532
ad80a810 3533 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3534
3535 /* Disable PF */
3536 I915_WRITE(PF_CTL(pipe), 0);
3537 I915_WRITE(PF_WIN_SZ(pipe), 0);
3538
1f544388 3539 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3540
3541 for_each_encoder_on_crtc(dev, crtc, encoder)
3542 if (encoder->post_disable)
3543 encoder->post_disable(encoder);
3544
83616634 3545 if (is_pch_port) {
ab4d966c 3546 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3547 intel_ddi_fdi_disable(crtc);
83616634 3548 }
4f771f10
PZ		 3549
3550 intel_crtc->active = false;
3551 intel_update_watermarks(dev);
3552
3553 mutex_lock(&dev->struct_mutex);
3554 intel_update_fbc(dev);
3555 mutex_unlock(&dev->struct_mutex);
3556}
3557
ee7b9f93
JB		 3558static void ironlake_crtc_off(struct drm_crtc *crtc)
3559{
3560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3561 intel_put_pch_pll(intel_crtc);
3562}
3563
6441ab5f
PZ		 3564static void haswell_crtc_off(struct drm_crtc *crtc)
3565{
a5c961d1
PZ		 3566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3567
3568 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3569 * start using it. */
1a240d4d 3570 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3571
6441ab5f
PZ		 3572 intel_ddi_put_crtc_pll(crtc);
3573}
3574
02e792fb
DV		 3575static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3576{
02e792fb 3577 if (!enable && intel_crtc->overlay) {
23f09ce3 3578 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3579 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3580
23f09ce3 3581 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3582 dev_priv->mm.interruptible = false;
3583 (void) intel_overlay_switch_off(intel_crtc->overlay);
3584 dev_priv->mm.interruptible = true;
23f09ce3 3585 mutex_unlock(&dev->struct_mutex);
02e792fb 3586 }
02e792fb 3587
5dcdbcb0
CW		 3588 /* Let userspace switch the overlay on again. In most cases userspace
3589 * has to recompute where to put it anyway.
3590 */
02e792fb
DV		 3591}
3592
0b8765c6 3593static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3594{
3595 struct drm_device *dev = crtc->dev;
79e53945
JB		 3596 struct drm_i915_private *dev_priv = dev->dev_private;
3597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3598 struct intel_encoder *encoder;
79e53945 3599 int pipe = intel_crtc->pipe;
80824003 3600 int plane = intel_crtc->plane;
79e53945 3601
08a48469
DV		 3602 WARN_ON(!crtc->enabled);
3603
f7abfe8b
CW		 3604 if (intel_crtc->active)
3605 return;
3606
3607 intel_crtc->active = true;
6b383a7f
CW		 3608 intel_update_watermarks(dev);
3609
63d7bbe9 3610 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3611
3612 for_each_encoder_on_crtc(dev, crtc, encoder)
3613 if (encoder->pre_enable)
3614 encoder->pre_enable(encoder);
3615
040484af 3616 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3617 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3618
0b8765c6 3619 intel_crtc_load_lut(crtc);
bed4a673 3620 intel_update_fbc(dev);
79e53945 3621
0b8765c6
JB		 3622 /* Give the overlay scaler a chance to enable if it's on this pipe */
3623 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3624 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3625
fa5c73b1
DV		 3626 for_each_encoder_on_crtc(dev, crtc, encoder)
3627 encoder->enable(encoder);
0b8765c6 3628}
79e53945 3629
0b8765c6
JB		 3630static void i9xx_crtc_disable(struct drm_crtc *crtc)
3631{
3632 struct drm_device *dev = crtc->dev;
3633 struct drm_i915_private *dev_priv = dev->dev_private;
3634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3635 struct intel_encoder *encoder;
0b8765c6
JB		 3636 int pipe = intel_crtc->pipe;
3637 int plane = intel_crtc->plane;
24a1f16d 3638 u32 pctl;
b690e96c 3639
ef9c3aee 3640
f7abfe8b
CW		 3641 if (!intel_crtc->active)
3642 return;
3643
ea9d758d
DV		 3644 for_each_encoder_on_crtc(dev, crtc, encoder)
3645 encoder->disable(encoder);
3646
0b8765c6 3647 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3648 intel_crtc_wait_for_pending_flips(crtc);
3649 drm_vblank_off(dev, pipe);
0b8765c6 3650 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3651 intel_crtc_update_cursor(crtc, false);
0b8765c6 3652
973d04f9
CW		 3653 if (dev_priv->cfb_plane == plane)
3654 intel_disable_fbc(dev);
79e53945 3655
b24e7179 3656 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3657 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3658
3659 /* Disable pannel fitter if it is on this pipe. */
3660 pctl = I915_READ(PFIT_CONTROL);
3661 if ((pctl & PFIT_ENABLE) &&
3662 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3663 I915_WRITE(PFIT_CONTROL, 0);
3664
63d7bbe9 3665 intel_disable_pll(dev_priv, pipe);
0b8765c6 3666
f7abfe8b 3667 intel_crtc->active = false;
6b383a7f
CW		 3668 intel_update_fbc(dev);
3669 intel_update_watermarks(dev);
0b8765c6
JB		 3670}
3671
ee7b9f93
JB		 3672static void i9xx_crtc_off(struct drm_crtc *crtc)
3673{
3674}
3675
976f8a20
DV		 3676static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3677 bool enabled)
2c07245f
ZW		 3678{
3679 struct drm_device *dev = crtc->dev;
3680 struct drm_i915_master_private *master_priv;
3681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3682 int pipe = intel_crtc->pipe;
79e53945
JB		 3683
3684 if (!dev->primary->master)
3685 return;
3686
3687 master_priv = dev->primary->master->driver_priv;
3688 if (!master_priv->sarea_priv)
3689 return;
3690
79e53945
JB		 3691 switch (pipe) {
3692 case 0:
3693 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3694 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3695 break;
3696 case 1:
3697 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3698 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3699 break;
3700 default:
9db4a9c7 3701 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3702 break;
3703 }
79e53945
JB		 3704}
3705
976f8a20
DV		 3706/**
3707 * Sets the power management mode of the pipe and plane.
3708 */
3709void intel_crtc_update_dpms(struct drm_crtc *crtc)
3710{
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_encoder *intel_encoder;
3714 bool enable = false;
3715
3716 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3717 enable |= intel_encoder->connectors_active;
3718
3719 if (enable)
3720 dev_priv->display.crtc_enable(crtc);
3721 else
3722 dev_priv->display.crtc_disable(crtc);
3723
3724 intel_crtc_update_sarea(crtc, enable);
3725}
3726
3727static void intel_crtc_noop(struct drm_crtc *crtc)
3728{
3729}
3730
cdd59983
CW		 3731static void intel_crtc_disable(struct drm_crtc *crtc)
3732{
cdd59983 3733 struct drm_device *dev = crtc->dev;
976f8a20 3734 struct drm_connector *connector;
ee7b9f93 3735 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3737
976f8a20
DV		 3738 /* crtc should still be enabled when we disable it. */
3739 WARN_ON(!crtc->enabled);
3740
7b9f35a6 3741 intel_crtc->eld_vld = false;
976f8a20
DV		 3742 dev_priv->display.crtc_disable(crtc);
3743 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3744 dev_priv->display.off(crtc);
3745
931872fc
CW		 3746 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3747 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3748
3749 if (crtc->fb) {
3750 mutex_lock(&dev->struct_mutex);
1690e1eb 3751 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3752 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3753 crtc->fb = NULL;
3754 }
3755
3756 /* Update computed state. */
3757 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3758 if (!connector->encoder || !connector->encoder->crtc)
3759 continue;
3760
3761 if (connector->encoder->crtc != crtc)
3762 continue;
3763
3764 connector->dpms = DRM_MODE_DPMS_OFF;
3765 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3766 }
3767}
3768
a261b246 3769void intel_modeset_disable(struct drm_device *dev)
79e53945 3770{
a261b246
DV		 3771 struct drm_crtc *crtc;
3772
3773 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3774 if (crtc->enabled)
3775 intel_crtc_disable(crtc);
3776 }
79e53945
JB		 3777}
3778
1f703855 3779void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3780{
7e7d76c3
JB		 3781}
3782
ea5b213a 3783void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3784{
4ef69c7a 3785 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3786
ea5b213a
CW		 3787 drm_encoder_cleanup(encoder);
3788 kfree(intel_encoder);
7e7d76c3
JB		 3789}
3790
5ab432ef
DV		 3791/* Simple dpms helper for encodres with just one connector, no cloning and only
3792 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3793 * state of the entire output pipe. */
3794void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3795{
5ab432ef
DV		 3796 if (mode == DRM_MODE_DPMS_ON) {
3797 encoder->connectors_active = true;
3798
b2cabb0e 3799 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3800 } else {
3801 encoder->connectors_active = false;
3802
b2cabb0e 3803 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3804 }
79e53945
JB		 3805}
3806
0a91ca29
DV		 3807/* Cross check the actual hw state with our own modeset state tracking (and it's
3808 * internal consistency). */
b980514c 3809static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3810{
0a91ca29
DV		 3811 if (connector->get_hw_state(connector)) {
3812 struct intel_encoder *encoder = connector->encoder;
3813 struct drm_crtc *crtc;
3814 bool encoder_enabled;
3815 enum pipe pipe;
3816
3817 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3818 connector->base.base.id,
3819 drm_get_connector_name(&connector->base));
3820
3821 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3822 "wrong connector dpms state\n");
3823 WARN(connector->base.encoder != &encoder->base,
3824 "active connector not linked to encoder\n");
3825 WARN(!encoder->connectors_active,
3826 "encoder->connectors_active not set\n");
3827
3828 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3829 WARN(!encoder_enabled, "encoder not enabled\n");
3830 if (WARN_ON(!encoder->base.crtc))
3831 return;
3832
3833 crtc = encoder->base.crtc;
3834
3835 WARN(!crtc->enabled, "crtc not enabled\n");
3836 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3837 WARN(pipe != to_intel_crtc(crtc)->pipe,
3838 "encoder active on the wrong pipe\n");
3839 }
79e53945
JB		 3840}
3841
5ab432ef
DV		 3842/* Even simpler default implementation, if there's really no special case to
3843 * consider. */
3844void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3845{
5ab432ef 3846 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3847
5ab432ef
DV		 3848 /* All the simple cases only support two dpms states. */
3849 if (mode != DRM_MODE_DPMS_ON)
3850 mode = DRM_MODE_DPMS_OFF;
d4270e57 3851
5ab432ef
DV		 3852 if (mode == connector->dpms)
3853 return;
3854
3855 connector->dpms = mode;
3856
3857 /* Only need to change hw state when actually enabled */
3858 if (encoder->base.crtc)
3859 intel_encoder_dpms(encoder, mode);
3860 else
8af6cf88 3861 WARN_ON(encoder->connectors_active != false);
0a91ca29 3862
b980514c 3863 intel_modeset_check_state(connector->dev);
79e53945
JB		 3864}
3865
f0947c37
DV		 3866/* Simple connector->get_hw_state implementation for encoders that support only
3867 * one connector and no cloning and hence the encoder state determines the state
3868 * of the connector. */
3869bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3870{
24929352 3871 enum pipe pipe = 0;
f0947c37 3872 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3873
f0947c37 3874 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3875}
3876
79e53945 3877static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3878 const struct drm_display_mode *mode,
79e53945
JB		 3879 struct drm_display_mode *adjusted_mode)
3880{
2c07245f 3881 struct drm_device *dev = crtc->dev;
89749350 3882
bad720ff 3883 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3884 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3885 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3886 return false;
2c07245f 3887 }
89749350 3888
f9bef081
DV		 3889 /* All interlaced capable intel hw wants timings in frames. Note though
3890 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3891 * timings, so we need to be careful not to clobber these.*/
3892 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3893 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3894
44f46b42
CW		 3895 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3896 * with a hsync front porch of 0.
3897 */
3898 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3899 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3900 return false;
3901
79e53945
JB		 3902 return true;
3903}
3904
25eb05fc
JB		 3905static int valleyview_get_display_clock_speed(struct drm_device *dev)
3906{
3907 return 400000; /* FIXME */
3908}
3909
e70236a8
JB		 3910static int i945_get_display_clock_speed(struct drm_device *dev)
3911{
3912 return 400000;
3913}
79e53945 3914
e70236a8 3915static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3916{
e70236a8
JB		 3917 return 333000;
3918}
79e53945 3919
e70236a8
JB		 3920static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3921{
3922 return 200000;
3923}
79e53945 3924
e70236a8
JB		 3925static int i915gm_get_display_clock_speed(struct drm_device *dev)
3926{
3927 u16 gcfgc = 0;
79e53945 3928
e70236a8
JB		 3929 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3930
3931 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3932 return 133000;
3933 else {
3934 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3935 case GC_DISPLAY_CLOCK_333_MHZ:
3936 return 333000;
3937 default:
3938 case GC_DISPLAY_CLOCK_190_200_MHZ:
3939 return 190000;
79e53945 3940 }
e70236a8
JB		 3941 }
3942}
3943
3944static int i865_get_display_clock_speed(struct drm_device *dev)
3945{
3946 return 266000;
3947}
3948
3949static int i855_get_display_clock_speed(struct drm_device *dev)
3950{
3951 u16 hpllcc = 0;
3952 /* Assume that the hardware is in the high speed state. This
3953 * should be the default.
3954 */
3955 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3956 case GC_CLOCK_133_200:
3957 case GC_CLOCK_100_200:
3958 return 200000;
3959 case GC_CLOCK_166_250:
3960 return 250000;
3961 case GC_CLOCK_100_133:
79e53945 3962 return 133000;
e70236a8 3963 }
79e53945 3964
e70236a8
JB		 3965 /* Shouldn't happen */
3966 return 0;
3967}
79e53945 3968
e70236a8
JB		 3969static int i830_get_display_clock_speed(struct drm_device *dev)
3970{
3971 return 133000;
79e53945
JB		 3972}
3973
2c07245f 3974static void
e69d0bc1 3975intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 3976{
3977 while (*num > 0xffffff || *den > 0xffffff) {
3978 *num >>= 1;
3979 *den >>= 1;
3980 }
3981}
3982
e69d0bc1
DV		 3983void
3984intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3985 int pixel_clock, int link_clock,
3986 struct intel_link_m_n *m_n)
2c07245f 3987{
e69d0bc1 3988 m_n->tu = 64;
22ed1113
CW		 3989 m_n->gmch_m = bits_per_pixel * pixel_clock;
3990 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 3991 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 3992 m_n->link_m = pixel_clock;
3993 m_n->link_n = link_clock;
e69d0bc1 3994 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 3995}
3996
a7615030
CW		 3997static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3998{
72bbe58c
KP		 3999 if (i915_panel_use_ssc >= 0)
4000 return i915_panel_use_ssc != 0;
4001 return dev_priv->lvds_use_ssc
435793df 4002 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4003}
4004
5a354204
JB		 4005/**
4006 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4007 * @crtc: CRTC structure
3b5c78a3 4008 * @mode: requested mode
5a354204
JB		 4009 *
4010 * A pipe may be connected to one or more outputs. Based on the depth of the
4011 * attached framebuffer, choose a good color depth to use on the pipe.
4012 *
4013 * If possible, match the pipe depth to the fb depth. In some cases, this
4014 * isn't ideal, because the connected output supports a lesser or restricted
4015 * set of depths. Resolve that here:
4016 * LVDS typically supports only 6bpc, so clamp down in that case
4017 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4018 * Displays may support a restricted set as well, check EDID and clamp as
4019 * appropriate.
3b5c78a3 4020 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4021 *
4022 * RETURNS:
4023 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4024 * true if they don't match).
4025 */
4026static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4027 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4028 unsigned int *pipe_bpp,
4029 struct drm_display_mode *mode)
5a354204
JB		 4030{
4031 struct drm_device *dev = crtc->dev;
4032 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4033 struct drm_connector *connector;
6c2b7c12 4034 struct intel_encoder *intel_encoder;
5a354204
JB		 4035 unsigned int display_bpc = UINT_MAX, bpc;
4036
4037 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4038 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4039
4040 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4041 unsigned int lvds_bpc;
4042
4043 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4044 LVDS_A3_POWER_UP)
4045 lvds_bpc = 8;
4046 else
4047 lvds_bpc = 6;
4048
4049 if (lvds_bpc < display_bpc) {
82820490 4050 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4051 display_bpc = lvds_bpc;
4052 }
4053 continue;
4054 }
4055
5a354204
JB		 4056 /* Not one of the known troublemakers, check the EDID */
4057 list_for_each_entry(connector, &dev->mode_config.connector_list,
4058 head) {
6c2b7c12 4059 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4060 continue;
4061
62ac41a6
JB		 4062 /* Don't use an invalid EDID bpc value */
4063 if (connector->display_info.bpc &&
4064 connector->display_info.bpc < display_bpc) {
82820490 4065 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4066 display_bpc = connector->display_info.bpc;
4067 }
4068 }
4069
2f4f649a
JN		 4070 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4071 /* Use VBT settings if we have an eDP panel */
4072 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4073
9a30a61f 4074 if (edp_bpc && edp_bpc < display_bpc) {
2f4f649a
JN		 4075 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4076 display_bpc = edp_bpc;
4077 }
4078 continue;
4079 }
4080
5a354204
JB		 4081 /*
4082 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4083 * through, clamp it down. (Note: >12bpc will be caught below.)
4084 */
4085 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4086 if (display_bpc > 8 && display_bpc < 12) {
82820490 4087 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4088 display_bpc = 12;
4089 } else {
82820490 4090 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4091 display_bpc = 8;
4092 }
4093 }
4094 }
4095
3b5c78a3
AJ		 4096 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4097 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4098 display_bpc = 6;
4099 }
4100
5a354204
JB		 4101 /*
4102 * We could just drive the pipe at the highest bpc all the time and
4103 * enable dithering as needed, but that costs bandwidth. So choose
4104 * the minimum value that expresses the full color range of the fb but
4105 * also stays within the max display bpc discovered above.
4106 */
4107
94352cf9 4108 switch (fb->depth) {
5a354204
JB		 4109 case 8:
4110 bpc = 8; /* since we go through a colormap */
4111 break;
4112 case 15:
4113 case 16:
4114 bpc = 6; /* min is 18bpp */
4115 break;
4116 case 24:
578393cd 4117 bpc = 8;
5a354204
JB		 4118 break;
4119 case 30:
578393cd 4120 bpc = 10;
5a354204
JB		 4121 break;
4122 case 48:
578393cd 4123 bpc = 12;
5a354204
JB		 4124 break;
4125 default:
4126 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4127 bpc = min((unsigned int)8, display_bpc);
4128 break;
4129 }
4130
578393cd
KP		 4131 display_bpc = min(display_bpc, bpc);
4132
82820490
AJ		 4133 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4134 bpc, display_bpc);
5a354204 4135
578393cd 4136 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4137
4138 return display_bpc != bpc;
4139}
4140
a0c4da24
JB		 4141static int vlv_get_refclk(struct drm_crtc *crtc)
4142{
4143 struct drm_device *dev = crtc->dev;
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 int refclk = 27000; /* for DP & HDMI */
4146
4147 return 100000; /* only one validated so far */
4148
4149 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4150 refclk = 96000;
4151 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4152 if (intel_panel_use_ssc(dev_priv))
4153 refclk = 100000;
4154 else
4155 refclk = 96000;
4156 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4157 refclk = 100000;
4158 }
4159
4160 return refclk;
4161}
4162
c65d77d8
JB		 4163static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4164{
4165 struct drm_device *dev = crtc->dev;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167 int refclk;
4168
a0c4da24
JB		 4169 if (IS_VALLEYVIEW(dev)) {
4170 refclk = vlv_get_refclk(crtc);
4171 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4172 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4173 refclk = dev_priv->lvds_ssc_freq * 1000;
4174 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4175 refclk / 1000);
4176 } else if (!IS_GEN2(dev)) {
4177 refclk = 96000;
4178 } else {
4179 refclk = 48000;
4180 }
4181
4182 return refclk;
4183}
4184
4185static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4186 intel_clock_t *clock)
4187{
4188 /* SDVO TV has fixed PLL values depend on its clock range,
4189 this mirrors vbios setting. */
4190 if (adjusted_mode->clock >= 100000
4191 && adjusted_mode->clock < 140500) {
4192 clock->p1 = 2;
4193 clock->p2 = 10;
4194 clock->n = 3;
4195 clock->m1 = 16;
4196 clock->m2 = 8;
4197 } else if (adjusted_mode->clock >= 140500
4198 && adjusted_mode->clock <= 200000) {
4199 clock->p1 = 1;
4200 clock->p2 = 10;
4201 clock->n = 6;
4202 clock->m1 = 12;
4203 clock->m2 = 8;
4204 }
4205}
4206
a7516a05
JB		 4207static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4208 intel_clock_t *clock,
4209 intel_clock_t *reduced_clock)
4210{
4211 struct drm_device *dev = crtc->dev;
4212 struct drm_i915_private *dev_priv = dev->dev_private;
4213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4214 int pipe = intel_crtc->pipe;
4215 u32 fp, fp2 = 0;
4216
4217 if (IS_PINEVIEW(dev)) {
4218 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4219 if (reduced_clock)
4220 fp2 = (1 << reduced_clock->n) << 16 |
4221 reduced_clock->m1 << 8 | reduced_clock->m2;
4222 } else {
4223 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4224 if (reduced_clock)
4225 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4226 reduced_clock->m2;
4227 }
4228
4229 I915_WRITE(FP0(pipe), fp);
4230
4231 intel_crtc->lowfreq_avail = false;
4232 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4233 reduced_clock && i915_powersave) {
4234 I915_WRITE(FP1(pipe), fp2);
4235 intel_crtc->lowfreq_avail = true;
4236 } else {
4237 I915_WRITE(FP1(pipe), fp);
4238 }
4239}
4240
a0c4da24
JB		 4241static void vlv_update_pll(struct drm_crtc *crtc,
4242 struct drm_display_mode *mode,
4243 struct drm_display_mode *adjusted_mode,
4244 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4245 int num_connectors)
a0c4da24
JB		 4246{
4247 struct drm_device *dev = crtc->dev;
4248 struct drm_i915_private *dev_priv = dev->dev_private;
4249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4250 int pipe = intel_crtc->pipe;
4251 u32 dpll, mdiv, pdiv;
4252 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4253 bool is_sdvo;
4254 u32 temp;
a0c4da24 4255
09153000
DV		 4256 mutex_lock(&dev_priv->dpio_lock);
4257
2a8f64ca
VP		 4258 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4259 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4260
2a8f64ca
VP		 4261 dpll = DPLL_VGA_MODE_DIS;
4262 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4263 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4264 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4265
4266 I915_WRITE(DPLL(pipe), dpll);
4267 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4268
4269 bestn = clock->n;
4270 bestm1 = clock->m1;
4271 bestm2 = clock->m2;
4272 bestp1 = clock->p1;
4273 bestp2 = clock->p2;
4274
2a8f64ca
VP		 4275 /*
4276 * In Valleyview PLL and program lane counter registers are exposed
4277 * through DPIO interface
4278 */
a0c4da24
JB		 4279 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4280 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4281 mdiv |= ((bestn << DPIO_N_SHIFT));
4282 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4283 mdiv |= (1 << DPIO_K_SHIFT);
4284 mdiv |= DPIO_ENABLE_CALIBRATION;
4285 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4286
4287 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4288
2a8f64ca 4289 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4290 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4291 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4292 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4293 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4294
2a8f64ca 4295 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4296
4297 dpll |= DPLL_VCO_ENABLE;
4298 I915_WRITE(DPLL(pipe), dpll);
4299 POSTING_READ(DPLL(pipe));
4300 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4301 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4302
2a8f64ca
VP		 4303 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4304
4305 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4306 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4307
4308 I915_WRITE(DPLL(pipe), dpll);
4309
4310 /* Wait for the clocks to stabilize. */
4311 POSTING_READ(DPLL(pipe));
4312 udelay(150);
a0c4da24 4313
2a8f64ca
VP		 4314 temp = 0;
4315 if (is_sdvo) {
4316 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4317 if (temp > 1)
4318 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4319 else
4320 temp = 0;
a0c4da24 4321 }
2a8f64ca
VP		 4322 I915_WRITE(DPLL_MD(pipe), temp);
4323 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4324
2a8f64ca
VP		 4325 /* Now program lane control registers */
4326 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4327 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4328 {
4329 temp = 0x1000C4;
4330 if(pipe == 1)
4331 temp |= (1 << 21);
4332 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4333 }
4334 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4335 {
4336 temp = 0x1000C4;
4337 if(pipe == 1)
4338 temp |= (1 << 21);
4339 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4340 }
09153000
DV		 4341
4342 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4343}
4344
eb1cbe48
DV		 4345static void i9xx_update_pll(struct drm_crtc *crtc,
4346 struct drm_display_mode *mode,
4347 struct drm_display_mode *adjusted_mode,
4348 intel_clock_t *clock, intel_clock_t *reduced_clock,
4349 int num_connectors)
4350{
4351 struct drm_device *dev = crtc->dev;
4352 struct drm_i915_private *dev_priv = dev->dev_private;
4353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4354 struct intel_encoder *encoder;
eb1cbe48
DV		 4355 int pipe = intel_crtc->pipe;
4356 u32 dpll;
4357 bool is_sdvo;
4358
2a8f64ca
VP		 4359 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4360
eb1cbe48
DV		 4361 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4362 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4363
4364 dpll = DPLL_VGA_MODE_DIS;
4365
4366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4367 dpll |= DPLLB_MODE_LVDS;
4368 else
4369 dpll |= DPLLB_MODE_DAC_SERIAL;
4370 if (is_sdvo) {
4371 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4372 if (pixel_multiplier > 1) {
4373 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4374 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4375 }
4376 dpll |= DPLL_DVO_HIGH_SPEED;
4377 }
4378 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4379 dpll |= DPLL_DVO_HIGH_SPEED;
4380
4381 /* compute bitmask from p1 value */
4382 if (IS_PINEVIEW(dev))
4383 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4384 else {
4385 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4386 if (IS_G4X(dev) && reduced_clock)
4387 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4388 }
4389 switch (clock->p2) {
4390 case 5:
4391 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4392 break;
4393 case 7:
4394 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4395 break;
4396 case 10:
4397 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4398 break;
4399 case 14:
4400 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4401 break;
4402 }
4403 if (INTEL_INFO(dev)->gen >= 4)
4404 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4405
4406 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4407 dpll |= PLL_REF_INPUT_TVCLKINBC;
4408 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4409 /* XXX: just matching BIOS for now */
4410 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4411 dpll |= 3;
4412 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4413 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4414 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4415 else
4416 dpll |= PLL_REF_INPUT_DREFCLK;
4417
4418 dpll |= DPLL_VCO_ENABLE;
4419 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4420 POSTING_READ(DPLL(pipe));
4421 udelay(150);
4422
dafd226c
DV		 4423 for_each_encoder_on_crtc(dev, crtc, encoder)
4424 if (encoder->pre_pll_enable)
4425 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4426
4427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4428 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4429
4430 I915_WRITE(DPLL(pipe), dpll);
4431
4432 /* Wait for the clocks to stabilize. */
4433 POSTING_READ(DPLL(pipe));
4434 udelay(150);
4435
4436 if (INTEL_INFO(dev)->gen >= 4) {
4437 u32 temp = 0;
4438 if (is_sdvo) {
4439 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4440 if (temp > 1)
4441 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4442 else
4443 temp = 0;
4444 }
4445 I915_WRITE(DPLL_MD(pipe), temp);
4446 } else {
4447 /* The pixel multiplier can only be updated once the
4448 * DPLL is enabled and the clocks are stable.
4449 *
4450 * So write it again.
4451 */
4452 I915_WRITE(DPLL(pipe), dpll);
4453 }
4454}
4455
4456static void i8xx_update_pll(struct drm_crtc *crtc,
4457 struct drm_display_mode *adjusted_mode,
2a8f64ca 4458 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4459 int num_connectors)
4460{
4461 struct drm_device *dev = crtc->dev;
4462 struct drm_i915_private *dev_priv = dev->dev_private;
4463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4464 struct intel_encoder *encoder;
eb1cbe48
DV		 4465 int pipe = intel_crtc->pipe;
4466 u32 dpll;
4467
2a8f64ca
VP		 4468 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4469
eb1cbe48
DV		 4470 dpll = DPLL_VGA_MODE_DIS;
4471
4472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4473 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4474 } else {
4475 if (clock->p1 == 2)
4476 dpll |= PLL_P1_DIVIDE_BY_TWO;
4477 else
4478 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4479 if (clock->p2 == 4)
4480 dpll |= PLL_P2_DIVIDE_BY_4;
4481 }
4482
4483 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4484 /* XXX: just matching BIOS for now */
4485 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4486 dpll |= 3;
4487 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4488 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4489 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4490 else
4491 dpll |= PLL_REF_INPUT_DREFCLK;
4492
4493 dpll |= DPLL_VCO_ENABLE;
4494 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4495 POSTING_READ(DPLL(pipe));
4496 udelay(150);
4497
dafd226c
DV		 4498 for_each_encoder_on_crtc(dev, crtc, encoder)
4499 if (encoder->pre_pll_enable)
4500 encoder->pre_pll_enable(encoder);
eb1cbe48 4501
5b5896e4
DV		 4502 I915_WRITE(DPLL(pipe), dpll);
4503
4504 /* Wait for the clocks to stabilize. */
4505 POSTING_READ(DPLL(pipe));
4506 udelay(150);
4507
eb1cbe48
DV		 4508 /* The pixel multiplier can only be updated once the
4509 * DPLL is enabled and the clocks are stable.
4510 *
4511 * So write it again.
4512 */
4513 I915_WRITE(DPLL(pipe), dpll);
4514}
4515
b0e77b9c
PZ		 4516static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4517 struct drm_display_mode *mode,
4518 struct drm_display_mode *adjusted_mode)
4519{
4520 struct drm_device *dev = intel_crtc->base.dev;
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4522 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4523 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4524 uint32_t vsyncshift;
4525
4526 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4527 /* the chip adds 2 halflines automatically */
4528 adjusted_mode->crtc_vtotal -= 1;
4529 adjusted_mode->crtc_vblank_end -= 1;
4530 vsyncshift = adjusted_mode->crtc_hsync_start
4531 - adjusted_mode->crtc_htotal / 2;
4532 } else {
4533 vsyncshift = 0;
4534 }
4535
4536 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4537 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4538
fe2b8f9d 4539 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4540 (adjusted_mode->crtc_hdisplay - 1) |
4541 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4542 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4543 (adjusted_mode->crtc_hblank_start - 1) |
4544 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4545 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4546 (adjusted_mode->crtc_hsync_start - 1) |
4547 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4548
fe2b8f9d 4549 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4550 (adjusted_mode->crtc_vdisplay - 1) |
4551 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4552 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4553 (adjusted_mode->crtc_vblank_start - 1) |
4554 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4555 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4556 (adjusted_mode->crtc_vsync_start - 1) |
4557 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4558
b5e508d4
PZ		 4559 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4560 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4561 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4562 * bits. */
4563 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4564 (pipe == PIPE_B || pipe == PIPE_C))
4565 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4566
b0e77b9c
PZ		 4567 /* pipesrc controls the size that is scaled from, which should
4568 * always be the user's requested size.
4569 */
4570 I915_WRITE(PIPESRC(pipe),
4571 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4572}
4573
f564048e
EA		 4574static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4575 struct drm_display_mode *mode,
4576 struct drm_display_mode *adjusted_mode,
4577 int x, int y,
94352cf9 4578 struct drm_framebuffer *fb)
79e53945
JB		 4579{
4580 struct drm_device *dev = crtc->dev;
4581 struct drm_i915_private *dev_priv = dev->dev_private;
4582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4583 int pipe = intel_crtc->pipe;
80824003 4584 int plane = intel_crtc->plane;
c751ce4f 4585 int refclk, num_connectors = 0;
652c393a 4586 intel_clock_t clock, reduced_clock;
b0e77b9c 4587 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4588 bool ok, has_reduced_clock = false, is_sdvo = false;
4589 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4590 struct intel_encoder *encoder;
d4906093 4591 const intel_limit_t *limit;
5c3b82e2 4592 int ret;
79e53945 4593
6c2b7c12 4594 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4595 switch (encoder->type) {
79e53945
JB		 4596 case INTEL_OUTPUT_LVDS:
4597 is_lvds = true;
4598 break;
4599 case INTEL_OUTPUT_SDVO:
7d57382e 4600 case INTEL_OUTPUT_HDMI:
79e53945 4601 is_sdvo = true;
5eddb70b 4602 if (encoder->needs_tv_clock)
e2f0ba97 4603 is_tv = true;
79e53945 4604 break;
79e53945
JB		 4605 case INTEL_OUTPUT_TVOUT:
4606 is_tv = true;
4607 break;
a4fc5ed6
KP		 4608 case INTEL_OUTPUT_DISPLAYPORT:
4609 is_dp = true;
4610 break;
79e53945 4611 }
43565a06 4612
c751ce4f 4613 num_connectors++;
79e53945
JB		 4614 }
4615
c65d77d8 4616 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4617
d4906093
ML		 4618 /*
4619 * Returns a set of divisors for the desired target clock with the given
4620 * refclk, or FALSE. The returned values represent the clock equation:
4621 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4622 */
1b894b59 4623 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4624 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4625 &clock);
79e53945
JB		 4626 if (!ok) {
4627 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4628 return -EINVAL;
79e53945
JB		 4629 }
4630
cda4b7d3 4631 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4632 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4633
ddc9003c 4634 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4635 /*
4636 * Ensure we match the reduced clock's P to the target clock.
4637 * If the clocks don't match, we can't switch the display clock
4638 * by using the FP0/FP1. In such case we will disable the LVDS
4639 * downclock feature.
4640 */
ddc9003c 4641 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4642 dev_priv->lvds_downclock,
4643 refclk,
cec2f356 4644 &clock,
5eddb70b 4645 &reduced_clock);
7026d4ac
ZW		 4646 }
4647
c65d77d8
JB		 4648 if (is_sdvo && is_tv)
4649 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4650
eb1cbe48 4651 if (IS_GEN2(dev))
2a8f64ca
VP		 4652 i8xx_update_pll(crtc, adjusted_mode, &clock,
4653 has_reduced_clock ? &reduced_clock : NULL,
4654 num_connectors);
a0c4da24 4655 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4656 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4657 has_reduced_clock ? &reduced_clock : NULL,
4658 num_connectors);
79e53945 4659 else
eb1cbe48
DV		 4660 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4661 has_reduced_clock ? &reduced_clock : NULL,
4662 num_connectors);
79e53945
JB		 4663
4664 /* setup pipeconf */
5eddb70b 4665 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4666
4667 /* Set up the display plane register */
4668 dspcntr = DISPPLANE_GAMMA_ENABLE;
4669
929c77fb
EA		 4670 if (pipe == 0)
4671 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4672 else
4673 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4674
a6c45cf0 4675 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4676 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4677 * core speed.
4678 *
4679 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4680 * pipe == 0 check?
4681 */
e70236a8
JB		 4682 if (mode->clock >
4683 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4684 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4685 else
5eddb70b 4686 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4687 }
4688
3b5c78a3 4689 /* default to 8bpc */
dfd07d72 4690 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4691 if (is_dp) {
0c96c65b 4692 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4693 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4694 PIPECONF_DITHER_EN |
4695 PIPECONF_DITHER_TYPE_SP;
4696 }
4697 }
4698
19c03924
GB		 4699 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4700 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4701 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4702 PIPECONF_ENABLE |
4703 I965_PIPECONF_ACTIVE;
4704 }
4705 }
4706
28c97730 4707 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4708 drm_mode_debug_printmodeline(mode);
4709
a7516a05
JB		 4710 if (HAS_PIPE_CXSR(dev)) {
4711 if (intel_crtc->lowfreq_avail) {
28c97730 4712 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4713 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4714 } else {
28c97730 4715 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4716 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4717 }
4718 }
4719
617cf884 4720 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4721 if (!IS_GEN2(dev) &&
b0e77b9c 4722 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4723 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4724 else
617cf884 4725 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4726
b0e77b9c 4727 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4728
4729 /* pipesrc and dspsize control the size that is scaled from,
4730 * which should always be the user's requested size.
79e53945 4731 */
929c77fb
EA		 4732 I915_WRITE(DSPSIZE(plane),
4733 ((mode->vdisplay - 1) << 16) |
4734 (mode->hdisplay - 1));
4735 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4736
f564048e
EA		 4737 I915_WRITE(PIPECONF(pipe), pipeconf);
4738 POSTING_READ(PIPECONF(pipe));
929c77fb 4739 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4740
4741 intel_wait_for_vblank(dev, pipe);
4742
f564048e
EA		 4743 I915_WRITE(DSPCNTR(plane), dspcntr);
4744 POSTING_READ(DSPCNTR(plane));
4745
94352cf9 4746 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4747
4748 intel_update_watermarks(dev);
4749
f564048e
EA		 4750 return ret;
4751}
4752
dde86e2d 4753static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4754{
4755 struct drm_i915_private *dev_priv = dev->dev_private;
4756 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4757 struct intel_encoder *encoder;
13d83a67
JB		 4758 u32 temp;
4759 bool has_lvds = false;
199e5d79
KP		 4760 bool has_cpu_edp = false;
4761 bool has_pch_edp = false;
4762 bool has_panel = false;
99eb6a01
KP		 4763 bool has_ck505 = false;
4764 bool can_ssc = false;
13d83a67
JB		 4765
4766 /* We need to take the global config into account */
199e5d79
KP		 4767 list_for_each_entry(encoder, &mode_config->encoder_list,
4768 base.head) {
4769 switch (encoder->type) {
4770 case INTEL_OUTPUT_LVDS:
4771 has_panel = true;
4772 has_lvds = true;
4773 break;
4774 case INTEL_OUTPUT_EDP:
4775 has_panel = true;
4776 if (intel_encoder_is_pch_edp(&encoder->base))
4777 has_pch_edp = true;
4778 else
4779 has_cpu_edp = true;
4780 break;
13d83a67
JB		 4781 }
4782 }
4783
99eb6a01
KP		 4784 if (HAS_PCH_IBX(dev)) {
4785 has_ck505 = dev_priv->display_clock_mode;
4786 can_ssc = has_ck505;
4787 } else {
4788 has_ck505 = false;
4789 can_ssc = true;
4790 }
4791
4792 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4793 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4794 has_ck505);
13d83a67
JB		 4795
4796 /* Ironlake: try to setup display ref clock before DPLL
4797 * enabling. This is only under driver's control after
4798 * PCH B stepping, previous chipset stepping should be
4799 * ignoring this setting.
4800 */
4801 temp = I915_READ(PCH_DREF_CONTROL);
4802 /* Always enable nonspread source */
4803 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4804
99eb6a01
KP		 4805 if (has_ck505)
4806 temp |= DREF_NONSPREAD_CK505_ENABLE;
4807 else
4808 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4809
199e5d79
KP		 4810 if (has_panel) {
4811 temp &= ~DREF_SSC_SOURCE_MASK;
4812 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4813
199e5d79 4814 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4815 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4816 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4817 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4818 } else
4819 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4820
4821 /* Get SSC going before enabling the outputs */
4822 I915_WRITE(PCH_DREF_CONTROL, temp);
4823 POSTING_READ(PCH_DREF_CONTROL);
4824 udelay(200);
4825
13d83a67
JB		 4826 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4827
4828 /* Enable CPU source on CPU attached eDP */
199e5d79 4829 if (has_cpu_edp) {
99eb6a01 4830 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4831 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4832 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4833 }
13d83a67
JB		 4834 else
4835 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4836 } else
4837 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4838
4839 I915_WRITE(PCH_DREF_CONTROL, temp);
4840 POSTING_READ(PCH_DREF_CONTROL);
4841 udelay(200);
4842 } else {
4843 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4844
4845 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4846
4847 /* Turn off CPU output */
4848 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4849
4850 I915_WRITE(PCH_DREF_CONTROL, temp);
4851 POSTING_READ(PCH_DREF_CONTROL);
4852 udelay(200);
4853
4854 /* Turn off the SSC source */
4855 temp &= ~DREF_SSC_SOURCE_MASK;
4856 temp |= DREF_SSC_SOURCE_DISABLE;
4857
4858 /* Turn off SSC1 */
4859 temp &= ~ DREF_SSC1_ENABLE;
4860
13d83a67
JB		 4861 I915_WRITE(PCH_DREF_CONTROL, temp);
4862 POSTING_READ(PCH_DREF_CONTROL);
4863 udelay(200);
4864 }
4865}
4866
dde86e2d
PZ		 4867/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4868static void lpt_init_pch_refclk(struct drm_device *dev)
4869{
4870 struct drm_i915_private *dev_priv = dev->dev_private;
4871 struct drm_mode_config *mode_config = &dev->mode_config;
4872 struct intel_encoder *encoder;
4873 bool has_vga = false;
4874 bool is_sdv = false;
4875 u32 tmp;
4876
4877 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4878 switch (encoder->type) {
4879 case INTEL_OUTPUT_ANALOG:
4880 has_vga = true;
4881 break;
4882 }
4883 }
4884
4885 if (!has_vga)
4886 return;
4887
c00db246
DV		 4888 mutex_lock(&dev_priv->dpio_lock);
4889
dde86e2d
PZ		 4890 /* XXX: Rip out SDV support once Haswell ships for real. */
4891 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4892 is_sdv = true;
4893
4894 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4895 tmp &= ~SBI_SSCCTL_DISABLE;
4896 tmp |= SBI_SSCCTL_PATHALT;
4897 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4898
4899 udelay(24);
4900
4901 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4902 tmp &= ~SBI_SSCCTL_PATHALT;
4903 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4904
4905 if (!is_sdv) {
4906 tmp = I915_READ(SOUTH_CHICKEN2);
4907 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4908 I915_WRITE(SOUTH_CHICKEN2, tmp);
4909
4910 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4911 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4912 DRM_ERROR("FDI mPHY reset assert timeout\n");
4913
4914 tmp = I915_READ(SOUTH_CHICKEN2);
4915 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4916 I915_WRITE(SOUTH_CHICKEN2, tmp);
4917
4918 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4919 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4920 100))
4921 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4922 }
4923
4924 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4925 tmp &= ~(0xFF << 24);
4926 tmp |= (0x12 << 24);
4927 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4928
4929 if (!is_sdv) {
4930 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4931 tmp &= ~(0x3 << 6);
4932 tmp |= (1 << 6) | (1 << 0);
4933 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4934 }
4935
4936 if (is_sdv) {
4937 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4938 tmp |= 0x7FFF;
4939 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4940 }
4941
4942 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4943 tmp |= (1 << 11);
4944 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4945
4946 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4947 tmp |= (1 << 11);
4948 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4949
4950 if (is_sdv) {
4951 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4952 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4953 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4954
4955 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4956 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4957 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4958
4959 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4960 tmp |= (0x3F << 8);
4961 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4962
4963 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4964 tmp |= (0x3F << 8);
4965 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4966 }
4967
4968 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4969 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4970 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4971
4972 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4973 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4974 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4975
4976 if (!is_sdv) {
4977 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4978 tmp &= ~(7 << 13);
4979 tmp |= (5 << 13);
4980 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4981
4982 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4983 tmp &= ~(7 << 13);
4984 tmp |= (5 << 13);
4985 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4986 }
4987
4988 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4989 tmp &= ~0xFF;
4990 tmp |= 0x1C;
4991 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4992
4993 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4994 tmp &= ~0xFF;
4995 tmp |= 0x1C;
4996 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
4997
4998 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
4999 tmp &= ~(0xFF << 16);
5000 tmp |= (0x1C << 16);
5001 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5002
5003 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5004 tmp &= ~(0xFF << 16);
5005 tmp |= (0x1C << 16);
5006 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5007
5008 if (!is_sdv) {
5009 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5010 tmp |= (1 << 27);
5011 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5012
5013 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5014 tmp |= (1 << 27);
5015 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5016
5017 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5018 tmp &= ~(0xF << 28);
5019 tmp |= (4 << 28);
5020 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5021
5022 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5023 tmp &= ~(0xF << 28);
5024 tmp |= (4 << 28);
5025 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5026 }
5027
5028 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5029 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5030 tmp |= SBI_DBUFF0_ENABLE;
5031 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5032
5033 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5034}
5035
5036/*
5037 * Initialize reference clocks when the driver loads
5038 */
5039void intel_init_pch_refclk(struct drm_device *dev)
5040{
5041 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5042 ironlake_init_pch_refclk(dev);
5043 else if (HAS_PCH_LPT(dev))
5044 lpt_init_pch_refclk(dev);
5045}
5046
d9d444cb
JB		 5047static int ironlake_get_refclk(struct drm_crtc *crtc)
5048{
5049 struct drm_device *dev = crtc->dev;
5050 struct drm_i915_private *dev_priv = dev->dev_private;
5051 struct intel_encoder *encoder;
d9d444cb
JB		 5052 struct intel_encoder *edp_encoder = NULL;
5053 int num_connectors = 0;
5054 bool is_lvds = false;
5055
6c2b7c12 5056 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5057 switch (encoder->type) {
5058 case INTEL_OUTPUT_LVDS:
5059 is_lvds = true;
5060 break;
5061 case INTEL_OUTPUT_EDP:
5062 edp_encoder = encoder;
5063 break;
5064 }
5065 num_connectors++;
5066 }
5067
5068 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5069 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5070 dev_priv->lvds_ssc_freq);
5071 return dev_priv->lvds_ssc_freq * 1000;
5072 }
5073
5074 return 120000;
5075}
5076
c8203565 5077static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5078 struct drm_display_mode *adjusted_mode,
c8203565 5079 bool dither)
79e53945 5080{
c8203565 5081 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5083 int pipe = intel_crtc->pipe;
c8203565
PZ		 5084 uint32_t val;
5085
5086 val = I915_READ(PIPECONF(pipe));
5087
dfd07d72 5088 val &= ~PIPECONF_BPC_MASK;
c8203565
PZ		 5089 switch (intel_crtc->bpp) {
5090 case 18:
dfd07d72 5091 val |= PIPECONF_6BPC;
c8203565
PZ		 5092 break;
5093 case 24:
dfd07d72 5094 val |= PIPECONF_8BPC;
c8203565
PZ		 5095 break;
5096 case 30:
dfd07d72 5097 val |= PIPECONF_10BPC;
c8203565
PZ		 5098 break;
5099 case 36:
dfd07d72 5100 val |= PIPECONF_12BPC;
c8203565
PZ		 5101 break;
5102 default:
cc769b62
PZ		 5103 /* Case prevented by intel_choose_pipe_bpp_dither. */
5104 BUG();
c8203565
PZ		 5105 }
5106
5107 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5108 if (dither)
5109 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5110
5111 val &= ~PIPECONF_INTERLACE_MASK;
5112 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5113 val |= PIPECONF_INTERLACED_ILK;
5114 else
5115 val |= PIPECONF_PROGRESSIVE;
5116
3685a8f3
VS		 5117 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5118 val |= PIPECONF_COLOR_RANGE_SELECT;
5119 else
5120 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5121
c8203565
PZ		 5122 I915_WRITE(PIPECONF(pipe), val);
5123 POSTING_READ(PIPECONF(pipe));
5124}
5125
86d3efce
VS		 5126/*
5127 * Set up the pipe CSC unit.
5128 *
5129 * Currently only full range RGB to limited range RGB conversion
5130 * is supported, but eventually this should handle various
5131 * RGB<->YCbCr scenarios as well.
5132 */
5133static void intel_set_pipe_csc(struct drm_crtc *crtc,
5134 const struct drm_display_mode *adjusted_mode)
5135{
5136 struct drm_device *dev = crtc->dev;
5137 struct drm_i915_private *dev_priv = dev->dev_private;
5138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5139 int pipe = intel_crtc->pipe;
5140 uint16_t coeff = 0x7800; /* 1.0 */
5141
5142 /*
5143 * TODO: Check what kind of values actually come out of the pipe
5144 * with these coeff/postoff values and adjust to get the best
5145 * accuracy. Perhaps we even need to take the bpc value into
5146 * consideration.
5147 */
5148
5149 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5150 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5151
5152 /*
5153 * GY/GU and RY/RU should be the other way around according
5154 * to BSpec, but reality doesn't agree. Just set them up in
5155 * a way that results in the correct picture.
5156 */
5157 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5158 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5159
5160 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5161 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5162
5163 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5164 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5165
5166 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5167 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5168 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5169
5170 if (INTEL_INFO(dev)->gen > 6) {
5171 uint16_t postoff = 0;
5172
5173 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5174 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5175
5176 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5177 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5178 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5179
5180 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5181 } else {
5182 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5183
5184 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5185 mode |= CSC_BLACK_SCREEN_OFFSET;
5186
5187 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5188 }
5189}
5190
ee2b0b38
PZ		 5191static void haswell_set_pipeconf(struct drm_crtc *crtc,
5192 struct drm_display_mode *adjusted_mode,
5193 bool dither)
5194{
5195 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5197 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5198 uint32_t val;
5199
702e7a56 5200 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5201
5202 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5203 if (dither)
5204 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5205
5206 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5207 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5208 val |= PIPECONF_INTERLACED_ILK;
5209 else
5210 val |= PIPECONF_PROGRESSIVE;
5211
702e7a56
PZ		 5212 I915_WRITE(PIPECONF(cpu_transcoder), val);
5213 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5214}
5215
6591c6e4
PZ		 5216static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5217 struct drm_display_mode *adjusted_mode,
5218 intel_clock_t *clock,
5219 bool *has_reduced_clock,
5220 intel_clock_t *reduced_clock)
5221{
5222 struct drm_device *dev = crtc->dev;
5223 struct drm_i915_private *dev_priv = dev->dev_private;
5224 struct intel_encoder *intel_encoder;
5225 int refclk;
d4906093 5226 const intel_limit_t *limit;
6591c6e4 5227 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5228
6591c6e4
PZ		 5229 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5230 switch (intel_encoder->type) {
79e53945
JB		 5231 case INTEL_OUTPUT_LVDS:
5232 is_lvds = true;
5233 break;
5234 case INTEL_OUTPUT_SDVO:
7d57382e 5235 case INTEL_OUTPUT_HDMI:
79e53945 5236 is_sdvo = true;
6591c6e4 5237 if (intel_encoder->needs_tv_clock)
e2f0ba97 5238 is_tv = true;
79e53945 5239 break;
79e53945
JB		 5240 case INTEL_OUTPUT_TVOUT:
5241 is_tv = true;
5242 break;
79e53945
JB		 5243 }
5244 }
5245
d9d444cb 5246 refclk = ironlake_get_refclk(crtc);
79e53945 5247
d4906093
ML		 5248 /*
5249 * Returns a set of divisors for the desired target clock with the given
5250 * refclk, or FALSE. The returned values represent the clock equation:
5251 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5252 */
1b894b59 5253 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5254 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5255 clock);
5256 if (!ret)
5257 return false;
cda4b7d3 5258
ddc9003c 5259 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5260 /*
5261 * Ensure we match the reduced clock's P to the target clock.
5262 * If the clocks don't match, we can't switch the display clock
5263 * by using the FP0/FP1. In such case we will disable the LVDS
5264 * downclock feature.
5265 */
6591c6e4
PZ		 5266 *has_reduced_clock = limit->find_pll(limit, crtc,
5267 dev_priv->lvds_downclock,
5268 refclk,
5269 clock,
5270 reduced_clock);
652c393a 5271 }
61e9653f
DV		 5272
5273 if (is_sdvo && is_tv)
6591c6e4
PZ		 5274 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5275
5276 return true;
5277}
5278
01a415fd
DV		 5279static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5280{
5281 struct drm_i915_private *dev_priv = dev->dev_private;
5282 uint32_t temp;
5283
5284 temp = I915_READ(SOUTH_CHICKEN1);
5285 if (temp & FDI_BC_BIFURCATION_SELECT)
5286 return;
5287
5288 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5289 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5290
5291 temp |= FDI_BC_BIFURCATION_SELECT;
5292 DRM_DEBUG_KMS("enabling fdi C rx\n");
5293 I915_WRITE(SOUTH_CHICKEN1, temp);
5294 POSTING_READ(SOUTH_CHICKEN1);
5295}
5296
5297static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5298{
5299 struct drm_device *dev = intel_crtc->base.dev;
5300 struct drm_i915_private *dev_priv = dev->dev_private;
5301 struct intel_crtc *pipe_B_crtc =
5302 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5303
5304 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5305 intel_crtc->pipe, intel_crtc->fdi_lanes);
5306 if (intel_crtc->fdi_lanes > 4) {
5307 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5308 intel_crtc->pipe, intel_crtc->fdi_lanes);
5309 /* Clamp lanes to avoid programming the hw with bogus values. */
5310 intel_crtc->fdi_lanes = 4;
5311
5312 return false;
5313 }
5314
5315 if (dev_priv->num_pipe == 2)
5316 return true;
5317
5318 switch (intel_crtc->pipe) {
5319 case PIPE_A:
5320 return true;
5321 case PIPE_B:
5322 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5323 intel_crtc->fdi_lanes > 2) {
5324 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5325 intel_crtc->pipe, intel_crtc->fdi_lanes);
5326 /* Clamp lanes to avoid programming the hw with bogus values. */
5327 intel_crtc->fdi_lanes = 2;
5328
5329 return false;
5330 }
5331
5332 if (intel_crtc->fdi_lanes > 2)
5333 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5334 else
5335 cpt_enable_fdi_bc_bifurcation(dev);
5336
5337 return true;
5338 case PIPE_C:
5339 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5340 if (intel_crtc->fdi_lanes > 2) {
5341 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5342 intel_crtc->pipe, intel_crtc->fdi_lanes);
5343 /* Clamp lanes to avoid programming the hw with bogus values. */
5344 intel_crtc->fdi_lanes = 2;
5345
5346 return false;
5347 }
5348 } else {
5349 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5350 return false;
5351 }
5352
5353 cpt_enable_fdi_bc_bifurcation(dev);
5354
5355 return true;
5356 default:
5357 BUG();
5358 }
5359}
5360
d4b1931c
PZ		 5361int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5362{
5363 /*
5364 * Account for spread spectrum to avoid
5365 * oversubscribing the link. Max center spread
5366 * is 2.5%; use 5% for safety's sake.
5367 */
5368 u32 bps = target_clock * bpp * 21 / 20;
5369 return bps / (link_bw * 8) + 1;
5370}
5371
f48d8f23
PZ		 5372static void ironlake_set_m_n(struct drm_crtc *crtc,
5373 struct drm_display_mode *mode,
5374 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5375{
5376 struct drm_device *dev = crtc->dev;
5377 struct drm_i915_private *dev_priv = dev->dev_private;
5378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5379 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5380 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5381 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5382 int target_clock, pixel_multiplier, lane, link_bw;
5383 bool is_dp = false, is_cpu_edp = false;
79e53945 5384
f48d8f23
PZ		 5385 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5386 switch (intel_encoder->type) {
a4fc5ed6
KP		 5387 case INTEL_OUTPUT_DISPLAYPORT:
5388 is_dp = true;
5389 break;
32f9d658 5390 case INTEL_OUTPUT_EDP:
e3aef172 5391 is_dp = true;
f48d8f23 5392 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5393 is_cpu_edp = true;
f48d8f23 5394 edp_encoder = intel_encoder;
32f9d658 5395 break;
79e53945 5396 }
79e53945 5397 }
61e9653f 5398
2c07245f 5399 /* FDI link */
8febb297
EA		 5400 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5401 lane = 0;
5402 /* CPU eDP doesn't require FDI link, so just set DP M/N
5403 according to current link config */
e3aef172 5404 if (is_cpu_edp) {
e3aef172 5405 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5406 } else {
8febb297
EA		 5407 /* FDI is a binary signal running at ~2.7GHz, encoding
5408 * each output octet as 10 bits. The actual frequency
5409 * is stored as a divider into a 100MHz clock, and the
5410 * mode pixel clock is stored in units of 1KHz.
5411 * Hence the bw of each lane in terms of the mode signal
5412 * is:
5413 */
5414 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5415 }
58a27471 5416
94bf2ced
DV		 5417 /* [e]DP over FDI requires target mode clock instead of link clock. */
5418 if (edp_encoder)
5419 target_clock = intel_edp_target_clock(edp_encoder, mode);
5420 else if (is_dp)
5421 target_clock = mode->clock;
5422 else
5423 target_clock = adjusted_mode->clock;
5424
d4b1931c
PZ		 5425 if (!lane)
5426 lane = ironlake_get_lanes_required(target_clock, link_bw,
5427 intel_crtc->bpp);
2c07245f 5428
8febb297
EA		 5429 intel_crtc->fdi_lanes = lane;
5430
5431 if (pixel_multiplier > 1)
5432 link_bw *= pixel_multiplier;
e69d0bc1 5433 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5434
afe2fcf5
PZ		 5435 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5436 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5437 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5438 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5439}
5440
de13a2e3
PZ		 5441static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5442 struct drm_display_mode *adjusted_mode,
5443 intel_clock_t *clock, u32 fp)
79e53945 5444{
de13a2e3 5445 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5446 struct drm_device *dev = crtc->dev;
5447 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5448 struct intel_encoder *intel_encoder;
5449 uint32_t dpll;
5450 int factor, pixel_multiplier, num_connectors = 0;
5451 bool is_lvds = false, is_sdvo = false, is_tv = false;
5452 bool is_dp = false, is_cpu_edp = false;
79e53945 5453
de13a2e3
PZ		 5454 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5455 switch (intel_encoder->type) {
79e53945
JB		 5456 case INTEL_OUTPUT_LVDS:
5457 is_lvds = true;
5458 break;
5459 case INTEL_OUTPUT_SDVO:
7d57382e 5460 case INTEL_OUTPUT_HDMI:
79e53945 5461 is_sdvo = true;
de13a2e3 5462 if (intel_encoder->needs_tv_clock)
e2f0ba97 5463 is_tv = true;
79e53945 5464 break;
79e53945
JB		 5465 case INTEL_OUTPUT_TVOUT:
5466 is_tv = true;
5467 break;
a4fc5ed6
KP		 5468 case INTEL_OUTPUT_DISPLAYPORT:
5469 is_dp = true;
5470 break;
32f9d658 5471 case INTEL_OUTPUT_EDP:
e3aef172 5472 is_dp = true;
de13a2e3 5473 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5474 is_cpu_edp = true;
32f9d658 5475 break;
79e53945 5476 }
43565a06 5477
c751ce4f 5478 num_connectors++;
79e53945 5479 }
79e53945 5480
c1858123 5481 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5482 factor = 21;
5483 if (is_lvds) {
5484 if ((intel_panel_use_ssc(dev_priv) &&
5485 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5486 intel_is_dual_link_lvds(dev))
8febb297
EA		 5487 factor = 25;
5488 } else if (is_sdvo && is_tv)
5489 factor = 20;
c1858123 5490
de13a2e3 5491 if (clock->m < factor * clock->n)
8febb297 5492 fp |= FP_CB_TUNE;
2c07245f 5493
5eddb70b 5494 dpll = 0;
2c07245f 5495
a07d6787
EA		 5496 if (is_lvds)
5497 dpll |= DPLLB_MODE_LVDS;
5498 else
5499 dpll |= DPLLB_MODE_DAC_SERIAL;
5500 if (is_sdvo) {
de13a2e3 5501 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5502 if (pixel_multiplier > 1) {
5503 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5504 }
a07d6787
EA		 5505 dpll |= DPLL_DVO_HIGH_SPEED;
5506 }
e3aef172 5507 if (is_dp && !is_cpu_edp)
a07d6787 5508 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5509
a07d6787 5510 /* compute bitmask from p1 value */
de13a2e3 5511 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5512 /* also FPA1 */
de13a2e3 5513 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5514
de13a2e3 5515 switch (clock->p2) {
a07d6787
EA		 5516 case 5:
5517 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5518 break;
5519 case 7:
5520 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5521 break;
5522 case 10:
5523 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5524 break;
5525 case 14:
5526 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5527 break;
79e53945
JB		 5528 }
5529
43565a06
KH		 5530 if (is_sdvo && is_tv)
5531 dpll |= PLL_REF_INPUT_TVCLKINBC;
5532 else if (is_tv)
79e53945 5533 /* XXX: just matching BIOS for now */
43565a06 5534 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5535 dpll |= 3;
a7615030 5536 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5537 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5538 else
5539 dpll |= PLL_REF_INPUT_DREFCLK;
5540
de13a2e3
PZ		 5541 return dpll;
5542}
5543
5544static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5545 struct drm_display_mode *mode,
5546 struct drm_display_mode *adjusted_mode,
5547 int x, int y,
5548 struct drm_framebuffer *fb)
5549{
5550 struct drm_device *dev = crtc->dev;
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5553 int pipe = intel_crtc->pipe;
5554 int plane = intel_crtc->plane;
5555 int num_connectors = 0;
5556 intel_clock_t clock, reduced_clock;
5557 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5558 bool ok, has_reduced_clock = false;
5559 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5560 struct intel_encoder *encoder;
de13a2e3 5561 int ret;
01a415fd 5562 bool dither, fdi_config_ok;
de13a2e3
PZ		 5563
5564 for_each_encoder_on_crtc(dev, crtc, encoder) {
5565 switch (encoder->type) {
5566 case INTEL_OUTPUT_LVDS:
5567 is_lvds = true;
5568 break;
de13a2e3
PZ		 5569 case INTEL_OUTPUT_DISPLAYPORT:
5570 is_dp = true;
5571 break;
5572 case INTEL_OUTPUT_EDP:
5573 is_dp = true;
e2f12b07 5574 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5575 is_cpu_edp = true;
5576 break;
5577 }
5578
5579 num_connectors++;
a07d6787 5580 }
79e53945 5581
5dc5298b
PZ		 5582 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5583 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5584
de13a2e3
PZ		 5585 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5586 &has_reduced_clock, &reduced_clock);
5587 if (!ok) {
5588 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5589 return -EINVAL;
79e53945
JB		 5590 }
5591
de13a2e3
PZ		 5592 /* Ensure that the cursor is valid for the new mode before changing... */
5593 intel_crtc_update_cursor(crtc, true);
5594
5595 /* determine panel color depth */
c8241969
JN		 5596 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5597 adjusted_mode);
de13a2e3
PZ		 5598 if (is_lvds && dev_priv->lvds_dither)
5599 dither = true;
5600
5601 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5602 if (has_reduced_clock)
5603 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5604 reduced_clock.m2;
5605
5606 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5607
f7cb34d4 5608 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5609 drm_mode_debug_printmodeline(mode);
5610
5dc5298b
PZ		 5611 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5612 if (!is_cpu_edp) {
ee7b9f93 5613 struct intel_pch_pll *pll;
4b645f14 5614
ee7b9f93
JB		 5615 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5616 if (pll == NULL) {
5617 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5618 pipe);
4b645f14
JB		 5619 return -EINVAL;
5620 }
ee7b9f93
JB		 5621 } else
5622 intel_put_pch_pll(intel_crtc);
79e53945 5623
2f0c2ad1 5624 if (is_dp && !is_cpu_edp)
a4fc5ed6 5625 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5626
dafd226c
DV		 5627 for_each_encoder_on_crtc(dev, crtc, encoder)
5628 if (encoder->pre_pll_enable)
5629 encoder->pre_pll_enable(encoder);
79e53945 5630
ee7b9f93
JB		 5631 if (intel_crtc->pch_pll) {
5632 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5633
32f9d658 5634 /* Wait for the clocks to stabilize. */
ee7b9f93 5635 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5636 udelay(150);
5637
8febb297
EA		 5638 /* The pixel multiplier can only be updated once the
5639 * DPLL is enabled and the clocks are stable.
5640 *
5641 * So write it again.
5642 */
ee7b9f93 5643 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5644 }
79e53945 5645
5eddb70b 5646 intel_crtc->lowfreq_avail = false;
ee7b9f93 5647 if (intel_crtc->pch_pll) {
4b645f14 5648 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5649 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5650 intel_crtc->lowfreq_avail = true;
4b645f14 5651 } else {
ee7b9f93 5652 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5653 }
5654 }
5655
b0e77b9c 5656 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5657
01a415fd
DV		 5658 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5659 * ironlake_check_fdi_lanes. */
f48d8f23 5660 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5661
01a415fd 5662 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5663
c8203565 5664 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5665
9d0498a2 5666 intel_wait_for_vblank(dev, pipe);
79e53945 5667
a1f9e77e
PZ		 5668 /* Set up the display plane register */
5669 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5670 POSTING_READ(DSPCNTR(plane));
79e53945 5671
94352cf9 5672 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5673
5674 intel_update_watermarks(dev);
5675
1f8eeabf
ED		 5676 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5677
01a415fd 5678 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5679}
5680
d6dd9eb1
DV		 5681static void haswell_modeset_global_resources(struct drm_device *dev)
5682{
5683 struct drm_i915_private *dev_priv = dev->dev_private;
5684 bool enable = false;
5685 struct intel_crtc *crtc;
5686 struct intel_encoder *encoder;
5687
5688 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5689 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5690 enable = true;
5691 /* XXX: Should check for edp transcoder here, but thanks to init
5692 * sequence that's not yet available. Just in case desktop eDP
5693 * on PORT D is possible on haswell, too. */
5694 }
5695
5696 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5697 base.head) {
5698 if (encoder->type != INTEL_OUTPUT_EDP &&
5699 encoder->connectors_active)
5700 enable = true;
5701 }
5702
5703 /* Even the eDP panel fitter is outside the always-on well. */
5704 if (dev_priv->pch_pf_size)
5705 enable = true;
5706
5707 intel_set_power_well(dev, enable);
5708}
5709
09b4ddf9
PZ		 5710static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5711 struct drm_display_mode *mode,
5712 struct drm_display_mode *adjusted_mode,
5713 int x, int y,
5714 struct drm_framebuffer *fb)
5715{
5716 struct drm_device *dev = crtc->dev;
5717 struct drm_i915_private *dev_priv = dev->dev_private;
5718 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5719 int pipe = intel_crtc->pipe;
5720 int plane = intel_crtc->plane;
5721 int num_connectors = 0;
ed7ef439 5722 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5723 struct intel_encoder *encoder;
09b4ddf9
PZ		 5724 int ret;
5725 bool dither;
5726
5727 for_each_encoder_on_crtc(dev, crtc, encoder) {
5728 switch (encoder->type) {
09b4ddf9
PZ		 5729 case INTEL_OUTPUT_DISPLAYPORT:
5730 is_dp = true;
5731 break;
5732 case INTEL_OUTPUT_EDP:
5733 is_dp = true;
5734 if (!intel_encoder_is_pch_edp(&encoder->base))
5735 is_cpu_edp = true;
5736 break;
5737 }
5738
5739 num_connectors++;
5740 }
5741
5dc5298b
PZ		 5742 /* We are not sure yet this won't happen. */
5743 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5744 INTEL_PCH_TYPE(dev));
5745
5746 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5747 num_connectors, pipe_name(pipe));
5748
702e7a56 5749 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5750 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5751
5752 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5753
6441ab5f
PZ		 5754 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5755 return -EINVAL;
5756
09b4ddf9
PZ		 5757 /* Ensure that the cursor is valid for the new mode before changing... */
5758 intel_crtc_update_cursor(crtc, true);
5759
5760 /* determine panel color depth */
c8241969
JN		 5761 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5762 adjusted_mode);
09b4ddf9 5763
09b4ddf9
PZ		 5764 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5765 drm_mode_debug_printmodeline(mode);
5766
ed7ef439 5767 if (is_dp && !is_cpu_edp)
09b4ddf9 5768 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5769
5770 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5771
5772 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5773
1eb8dfec
PZ		 5774 if (!is_dp || is_cpu_edp)
5775 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5776
ee2b0b38 5777 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5778
86d3efce
VS		 5779 intel_set_pipe_csc(crtc, adjusted_mode);
5780
09b4ddf9 5781 /* Set up the display plane register */
86d3efce 5782 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5783 POSTING_READ(DSPCNTR(plane));
5784
5785 ret = intel_pipe_set_base(crtc, x, y, fb);
5786
5787 intel_update_watermarks(dev);
5788
5789 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5790
1f803ee5 5791 return ret;
79e53945
JB		 5792}
5793
f564048e
EA		 5794static int intel_crtc_mode_set(struct drm_crtc *crtc,
5795 struct drm_display_mode *mode,
5796 struct drm_display_mode *adjusted_mode,
5797 int x, int y,
94352cf9 5798 struct drm_framebuffer *fb)
f564048e
EA		 5799{
5800 struct drm_device *dev = crtc->dev;
5801 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5802 struct drm_encoder_helper_funcs *encoder_funcs;
5803 struct intel_encoder *encoder;
0b701d27
EA		 5804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5805 int pipe = intel_crtc->pipe;
f564048e
EA		 5806 int ret;
5807
cc464b2a
PZ		 5808 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5809 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5810 else
5811 intel_crtc->cpu_transcoder = pipe;
5812
0b701d27 5813 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5814
f564048e 5815 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5816 x, y, fb);
79e53945 5817 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5818
9256aa19
DV		 5819 if (ret != 0)
5820 return ret;
5821
5822 for_each_encoder_on_crtc(dev, crtc, encoder) {
5823 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5824 encoder->base.base.id,
5825 drm_get_encoder_name(&encoder->base),
5826 mode->base.id, mode->name);
5827 encoder_funcs = encoder->base.helper_private;
5828 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5829 }
5830
5831 return 0;
79e53945
JB		 5832}
5833
3a9627f4
WF		 5834static bool intel_eld_uptodate(struct drm_connector *connector,
5835 int reg_eldv, uint32_t bits_eldv,
5836 int reg_elda, uint32_t bits_elda,
5837 int reg_edid)
5838{
5839 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5840 uint8_t *eld = connector->eld;
5841 uint32_t i;
5842
5843 i = I915_READ(reg_eldv);
5844 i &= bits_eldv;
5845
5846 if (!eld[0])
5847 return !i;
5848
5849 if (!i)
5850 return false;
5851
5852 i = I915_READ(reg_elda);
5853 i &= ~bits_elda;
5854 I915_WRITE(reg_elda, i);
5855
5856 for (i = 0; i < eld[2]; i++)
5857 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5858 return false;
5859
5860 return true;
5861}
5862
e0dac65e
WF		 5863static void g4x_write_eld(struct drm_connector *connector,
5864 struct drm_crtc *crtc)
5865{
5866 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5867 uint8_t *eld = connector->eld;
5868 uint32_t eldv;
5869 uint32_t len;
5870 uint32_t i;
5871
5872 i = I915_READ(G4X_AUD_VID_DID);
5873
5874 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5875 eldv = G4X_ELDV_DEVCL_DEVBLC;
5876 else
5877 eldv = G4X_ELDV_DEVCTG;
5878
3a9627f4
WF		 5879 if (intel_eld_uptodate(connector,
5880 G4X_AUD_CNTL_ST, eldv,
5881 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5882 G4X_HDMIW_HDMIEDID))
5883 return;
5884
e0dac65e
WF		 5885 i = I915_READ(G4X_AUD_CNTL_ST);
5886 i &= ~(eldv | G4X_ELD_ADDR);
5887 len = (i >> 9) & 0x1f; /* ELD buffer size */
5888 I915_WRITE(G4X_AUD_CNTL_ST, i);
5889
5890 if (!eld[0])
5891 return;
5892
5893 len = min_t(uint8_t, eld[2], len);
5894 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5895 for (i = 0; i < len; i++)
5896 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5897
5898 i = I915_READ(G4X_AUD_CNTL_ST);
5899 i |= eldv;
5900 I915_WRITE(G4X_AUD_CNTL_ST, i);
5901}
5902
83358c85
WX		 5903static void haswell_write_eld(struct drm_connector *connector,
5904 struct drm_crtc *crtc)
5905{
5906 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5907 uint8_t *eld = connector->eld;
5908 struct drm_device *dev = crtc->dev;
7b9f35a6 5909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5910 uint32_t eldv;
5911 uint32_t i;
5912 int len;
5913 int pipe = to_intel_crtc(crtc)->pipe;
5914 int tmp;
5915
5916 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5917 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5918 int aud_config = HSW_AUD_CFG(pipe);
5919 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5920
5921
5922 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5923
5924 /* Audio output enable */
5925 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5926 tmp = I915_READ(aud_cntrl_st2);
5927 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5928 I915_WRITE(aud_cntrl_st2, tmp);
5929
5930 /* Wait for 1 vertical blank */
5931 intel_wait_for_vblank(dev, pipe);
5932
5933 /* Set ELD valid state */
5934 tmp = I915_READ(aud_cntrl_st2);
5935 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5936 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5937 I915_WRITE(aud_cntrl_st2, tmp);
5938 tmp = I915_READ(aud_cntrl_st2);
5939 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5940
5941 /* Enable HDMI mode */
5942 tmp = I915_READ(aud_config);
5943 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5944 /* clear N_programing_enable and N_value_index */
5945 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5946 I915_WRITE(aud_config, tmp);
5947
5948 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5949
5950 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5951 intel_crtc->eld_vld = true;
83358c85
WX		 5952
5953 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5954 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5955 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5956 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5957 } else
5958 I915_WRITE(aud_config, 0);
5959
5960 if (intel_eld_uptodate(connector,
5961 aud_cntrl_st2, eldv,
5962 aud_cntl_st, IBX_ELD_ADDRESS,
5963 hdmiw_hdmiedid))
5964 return;
5965
5966 i = I915_READ(aud_cntrl_st2);
5967 i &= ~eldv;
5968 I915_WRITE(aud_cntrl_st2, i);
5969
5970 if (!eld[0])
5971 return;
5972
5973 i = I915_READ(aud_cntl_st);
5974 i &= ~IBX_ELD_ADDRESS;
5975 I915_WRITE(aud_cntl_st, i);
5976 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5977 DRM_DEBUG_DRIVER("port num:%d\n", i);
5978
5979 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5980 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5981 for (i = 0; i < len; i++)
5982 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5983
5984 i = I915_READ(aud_cntrl_st2);
5985 i |= eldv;
5986 I915_WRITE(aud_cntrl_st2, i);
5987
5988}
5989
e0dac65e
WF		 5990static void ironlake_write_eld(struct drm_connector *connector,
5991 struct drm_crtc *crtc)
5992{
5993 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5994 uint8_t *eld = connector->eld;
5995 uint32_t eldv;
5996 uint32_t i;
5997 int len;
5998 int hdmiw_hdmiedid;
b6daa025 5999 int aud_config;
e0dac65e
WF		 6000 int aud_cntl_st;
6001 int aud_cntrl_st2;
9b138a83 6002 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6003
b3f33cbf 6004 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6005 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6006 aud_config = IBX_AUD_CFG(pipe);
6007 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6008 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6009 } else {
9b138a83
WX		 6010 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6011 aud_config = CPT_AUD_CFG(pipe);
6012 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6013 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6014 }
6015
9b138a83 6016 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6017
6018 i = I915_READ(aud_cntl_st);
9b138a83 6019 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6020 if (!i) {
6021 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6022 /* operate blindly on all ports */
1202b4c6
WF		 6023 eldv = IBX_ELD_VALIDB;
6024 eldv |= IBX_ELD_VALIDB << 4;
6025 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6026 } else {
6027 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6028 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6029 }
6030
3a9627f4
WF		 6031 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6032 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6033 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6034 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6035 } else
6036 I915_WRITE(aud_config, 0);
e0dac65e 6037
3a9627f4
WF		 6038 if (intel_eld_uptodate(connector,
6039 aud_cntrl_st2, eldv,
6040 aud_cntl_st, IBX_ELD_ADDRESS,
6041 hdmiw_hdmiedid))
6042 return;
6043
e0dac65e
WF		 6044 i = I915_READ(aud_cntrl_st2);
6045 i &= ~eldv;
6046 I915_WRITE(aud_cntrl_st2, i);
6047
6048 if (!eld[0])
6049 return;
6050
e0dac65e 6051 i = I915_READ(aud_cntl_st);
1202b4c6 6052 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6053 I915_WRITE(aud_cntl_st, i);
6054
6055 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6056 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6057 for (i = 0; i < len; i++)
6058 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6059
6060 i = I915_READ(aud_cntrl_st2);
6061 i |= eldv;
6062 I915_WRITE(aud_cntrl_st2, i);
6063}
6064
6065void intel_write_eld(struct drm_encoder *encoder,
6066 struct drm_display_mode *mode)
6067{
6068 struct drm_crtc *crtc = encoder->crtc;
6069 struct drm_connector *connector;
6070 struct drm_device *dev = encoder->dev;
6071 struct drm_i915_private *dev_priv = dev->dev_private;
6072
6073 connector = drm_select_eld(encoder, mode);
6074 if (!connector)
6075 return;
6076
6077 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6078 connector->base.id,
6079 drm_get_connector_name(connector),
6080 connector->encoder->base.id,
6081 drm_get_encoder_name(connector->encoder));
6082
6083 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6084
6085 if (dev_priv->display.write_eld)
6086 dev_priv->display.write_eld(connector, crtc);
6087}
6088
79e53945
JB		 6089/** Loads the palette/gamma unit for the CRTC with the prepared values */
6090void intel_crtc_load_lut(struct drm_crtc *crtc)
6091{
6092 struct drm_device *dev = crtc->dev;
6093 struct drm_i915_private *dev_priv = dev->dev_private;
6094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6095 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6096 int i;
6097
6098 /* The clocks have to be on to load the palette. */
aed3f09d 6099 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6100 return;
6101
f2b115e6 6102 /* use legacy palette for Ironlake */
bad720ff 6103 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6104 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6105
79e53945
JB		 6106 for (i = 0; i < 256; i++) {
6107 I915_WRITE(palreg + 4 * i,
6108 (intel_crtc->lut_r[i] << 16) |
6109 (intel_crtc->lut_g[i] << 8) |
6110 intel_crtc->lut_b[i]);
6111 }
6112}
6113
560b85bb
CW		 6114static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6115{
6116 struct drm_device *dev = crtc->dev;
6117 struct drm_i915_private *dev_priv = dev->dev_private;
6118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6119 bool visible = base != 0;
6120 u32 cntl;
6121
6122 if (intel_crtc->cursor_visible == visible)
6123 return;
6124
9db4a9c7 6125 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6126 if (visible) {
6127 /* On these chipsets we can only modify the base whilst
6128 * the cursor is disabled.
6129 */
9db4a9c7 6130 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6131
6132 cntl &= ~(CURSOR_FORMAT_MASK);
6133 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6134 cntl |= CURSOR_ENABLE |
6135 CURSOR_GAMMA_ENABLE |
6136 CURSOR_FORMAT_ARGB;
6137 } else
6138 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6139 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6140
6141 intel_crtc->cursor_visible = visible;
6142}
6143
6144static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6145{
6146 struct drm_device *dev = crtc->dev;
6147 struct drm_i915_private *dev_priv = dev->dev_private;
6148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6149 int pipe = intel_crtc->pipe;
6150 bool visible = base != 0;
6151
6152 if (intel_crtc->cursor_visible != visible) {
548f245b 6153 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6154 if (base) {
6155 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6156 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6157 cntl |= pipe << 28; /* Connect to correct pipe */
6158 } else {
6159 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6160 cntl |= CURSOR_MODE_DISABLE;
6161 }
9db4a9c7 6162 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6163
6164 intel_crtc->cursor_visible = visible;
6165 }
6166 /* and commit changes on next vblank */
9db4a9c7 6167 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6168}
6169
65a21cd6
JB		 6170static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6171{
6172 struct drm_device *dev = crtc->dev;
6173 struct drm_i915_private *dev_priv = dev->dev_private;
6174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6175 int pipe = intel_crtc->pipe;
6176 bool visible = base != 0;
6177
6178 if (intel_crtc->cursor_visible != visible) {
6179 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6180 if (base) {
6181 cntl &= ~CURSOR_MODE;
6182 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6183 } else {
6184 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6185 cntl |= CURSOR_MODE_DISABLE;
6186 }
86d3efce
VS		 6187 if (IS_HASWELL(dev))
6188 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6189 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6190
6191 intel_crtc->cursor_visible = visible;
6192 }
6193 /* and commit changes on next vblank */
6194 I915_WRITE(CURBASE_IVB(pipe), base);
6195}
6196
cda4b7d3 6197/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6198static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6199 bool on)
cda4b7d3
CW		 6200{
6201 struct drm_device *dev = crtc->dev;
6202 struct drm_i915_private *dev_priv = dev->dev_private;
6203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6204 int pipe = intel_crtc->pipe;
6205 int x = intel_crtc->cursor_x;
6206 int y = intel_crtc->cursor_y;
560b85bb 6207 u32 base, pos;
cda4b7d3
CW		 6208 bool visible;
6209
6210 pos = 0;
6211
6b383a7f 6212 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6213 base = intel_crtc->cursor_addr;
6214 if (x > (int) crtc->fb->width)
6215 base = 0;
6216
6217 if (y > (int) crtc->fb->height)
6218 base = 0;
6219 } else
6220 base = 0;
6221
6222 if (x < 0) {
6223 if (x + intel_crtc->cursor_width < 0)
6224 base = 0;
6225
6226 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6227 x = -x;
6228 }
6229 pos |= x << CURSOR_X_SHIFT;
6230
6231 if (y < 0) {
6232 if (y + intel_crtc->cursor_height < 0)
6233 base = 0;
6234
6235 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6236 y = -y;
6237 }
6238 pos |= y << CURSOR_Y_SHIFT;
6239
6240 visible = base != 0;
560b85bb 6241 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6242 return;
6243
0cd83aa9 6244 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6245 I915_WRITE(CURPOS_IVB(pipe), pos);
6246 ivb_update_cursor(crtc, base);
6247 } else {
6248 I915_WRITE(CURPOS(pipe), pos);
6249 if (IS_845G(dev) || IS_I865G(dev))
6250 i845_update_cursor(crtc, base);
6251 else
6252 i9xx_update_cursor(crtc, base);
6253 }
cda4b7d3
CW		 6254}
6255
79e53945 6256static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6257 struct drm_file *file,
79e53945
JB		 6258 uint32_t handle,
6259 uint32_t width, uint32_t height)
6260{
6261 struct drm_device *dev = crtc->dev;
6262 struct drm_i915_private *dev_priv = dev->dev_private;
6263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6264 struct drm_i915_gem_object *obj;
cda4b7d3 6265 uint32_t addr;
3f8bc370 6266 int ret;
79e53945 6267
79e53945
JB		 6268 /* if we want to turn off the cursor ignore width and height */
6269 if (!handle) {
28c97730 6270 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6271 addr = 0;
05394f39 6272 obj = NULL;
5004417d 6273 mutex_lock(&dev->struct_mutex);
3f8bc370 6274 goto finish;
79e53945
JB		 6275 }
6276
6277 /* Currently we only support 64x64 cursors */
6278 if (width != 64 || height != 64) {
6279 DRM_ERROR("we currently only support 64x64 cursors\n");
6280 return -EINVAL;
6281 }
6282
05394f39 6283 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6284 if (&obj->base == NULL)
79e53945
JB		 6285 return -ENOENT;
6286
05394f39 6287 if (obj->base.size < width * height * 4) {
79e53945 6288 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6289 ret = -ENOMEM;
6290 goto fail;
79e53945
JB		 6291 }
6292
71acb5eb 6293 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6294 mutex_lock(&dev->struct_mutex);
b295d1b6 6295 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6296 if (obj->tiling_mode) {
6297 DRM_ERROR("cursor cannot be tiled\n");
6298 ret = -EINVAL;
6299 goto fail_locked;
6300 }
6301
2da3b9b9 6302 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6303 if (ret) {
6304 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6305 goto fail_locked;
e7b526bb
CW		 6306 }
6307
d9e86c0e
CW		 6308 ret = i915_gem_object_put_fence(obj);
6309 if (ret) {
2da3b9b9 6310 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6311 goto fail_unpin;
6312 }
6313
05394f39 6314 addr = obj->gtt_offset;
71acb5eb 6315 } else {
6eeefaf3 6316 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6317 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6318 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6319 align);
71acb5eb
DA		 6320 if (ret) {
6321 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6322 goto fail_locked;
71acb5eb 6323 }
05394f39 6324 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6325 }
6326
a6c45cf0 6327 if (IS_GEN2(dev))
14b60391
JB		 6328 I915_WRITE(CURSIZE, (height << 12) | width);
6329
3f8bc370 6330 finish:
3f8bc370 6331 if (intel_crtc->cursor_bo) {
b295d1b6 6332 if (dev_priv->info->cursor_needs_physical) {
05394f39 6333 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6334 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6335 } else
6336 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6337 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6338 }
80824003 6339
7f9872e0 6340 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6341
6342 intel_crtc->cursor_addr = addr;
05394f39 6343 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6344 intel_crtc->cursor_width = width;
6345 intel_crtc->cursor_height = height;
6346
6b383a7f 6347 intel_crtc_update_cursor(crtc, true);
3f8bc370 6348
79e53945 6349 return 0;
e7b526bb 6350fail_unpin:
05394f39 6351 i915_gem_object_unpin(obj);
7f9872e0 6352fail_locked:
34b8686e 6353 mutex_unlock(&dev->struct_mutex);
bc9025bd 6354fail:
05394f39 6355 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6356 return ret;
79e53945
JB		 6357}
6358
6359static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6360{
79e53945 6361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6362
cda4b7d3
CW		 6363 intel_crtc->cursor_x = x;
6364 intel_crtc->cursor_y = y;
652c393a 6365
6b383a7f 6366 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6367
6368 return 0;
6369}
6370
6371/** Sets the color ramps on behalf of RandR */
6372void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6373 u16 blue, int regno)
6374{
6375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6376
6377 intel_crtc->lut_r[regno] = red >> 8;
6378 intel_crtc->lut_g[regno] = green >> 8;
6379 intel_crtc->lut_b[regno] = blue >> 8;
6380}
6381
b8c00ac5
DA		 6382void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6383 u16 *blue, int regno)
6384{
6385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386
6387 *red = intel_crtc->lut_r[regno] << 8;
6388 *green = intel_crtc->lut_g[regno] << 8;
6389 *blue = intel_crtc->lut_b[regno] << 8;
6390}
6391
79e53945 6392static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6393 u16 *blue, uint32_t start, uint32_t size)
79e53945 6394{
7203425a 6395 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6397
7203425a 6398 for (i = start; i < end; i++) {
79e53945
JB		 6399 intel_crtc->lut_r[i] = red[i] >> 8;
6400 intel_crtc->lut_g[i] = green[i] >> 8;
6401 intel_crtc->lut_b[i] = blue[i] >> 8;
6402 }
6403
6404 intel_crtc_load_lut(crtc);
6405}
6406
6407/**
6408 * Get a pipe with a simple mode set on it for doing load-based monitor
6409 * detection.
6410 *
6411 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6412 * its requirements. The pipe will be connected to no other encoders.
79e53945 6413 *
c751ce4f 6414 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6415 * configured for it. In the future, it could choose to temporarily disable
6416 * some outputs to free up a pipe for its use.
6417 *
6418 * \return crtc, or NULL if no pipes are available.
6419 */
6420
6421/* VESA 640x480x72Hz mode to set on the pipe */
6422static struct drm_display_mode load_detect_mode = {
6423 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6424 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6425};
6426
d2dff872
CW		 6427static struct drm_framebuffer *
6428intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6429 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6430 struct drm_i915_gem_object *obj)
6431{
6432 struct intel_framebuffer *intel_fb;
6433 int ret;
6434
6435 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6436 if (!intel_fb) {
6437 drm_gem_object_unreference_unlocked(&obj->base);
6438 return ERR_PTR(-ENOMEM);
6439 }
6440
6441 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6442 if (ret) {
6443 drm_gem_object_unreference_unlocked(&obj->base);
6444 kfree(intel_fb);
6445 return ERR_PTR(ret);
6446 }
6447
6448 return &intel_fb->base;
6449}
6450
6451static u32
6452intel_framebuffer_pitch_for_width(int width, int bpp)
6453{
6454 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6455 return ALIGN(pitch, 64);
6456}
6457
6458static u32
6459intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6460{
6461 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6462 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6463}
6464
6465static struct drm_framebuffer *
6466intel_framebuffer_create_for_mode(struct drm_device *dev,
6467 struct drm_display_mode *mode,
6468 int depth, int bpp)
6469{
6470 struct drm_i915_gem_object *obj;
0fed39bd 6471 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6472
6473 obj = i915_gem_alloc_object(dev,
6474 intel_framebuffer_size_for_mode(mode, bpp));
6475 if (obj == NULL)
6476 return ERR_PTR(-ENOMEM);
6477
6478 mode_cmd.width = mode->hdisplay;
6479 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6480 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6481 bpp);
5ca0c34a 6482 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6483
6484 return intel_framebuffer_create(dev, &mode_cmd, obj);
6485}
6486
6487static struct drm_framebuffer *
6488mode_fits_in_fbdev(struct drm_device *dev,
6489 struct drm_display_mode *mode)
6490{
6491 struct drm_i915_private *dev_priv = dev->dev_private;
6492 struct drm_i915_gem_object *obj;
6493 struct drm_framebuffer *fb;
6494
6495 if (dev_priv->fbdev == NULL)
6496 return NULL;
6497
6498 obj = dev_priv->fbdev->ifb.obj;
6499 if (obj == NULL)
6500 return NULL;
6501
6502 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6503 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6504 fb->bits_per_pixel))
d2dff872
CW		 6505 return NULL;
6506
01f2c773 6507 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6508 return NULL;
6509
6510 return fb;
6511}
6512
d2434ab7 6513bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6514 struct drm_display_mode *mode,
8261b191 6515 struct intel_load_detect_pipe *old)
79e53945
JB		 6516{
6517 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6518 struct intel_encoder *intel_encoder =
6519 intel_attached_encoder(connector);
79e53945 6520 struct drm_crtc *possible_crtc;
4ef69c7a 6521 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6522 struct drm_crtc *crtc = NULL;
6523 struct drm_device *dev = encoder->dev;
94352cf9 6524 struct drm_framebuffer *fb;
79e53945
JB		 6525 int i = -1;
6526
d2dff872
CW		 6527 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6528 connector->base.id, drm_get_connector_name(connector),
6529 encoder->base.id, drm_get_encoder_name(encoder));
6530
79e53945
JB		 6531 /*
6532 * Algorithm gets a little messy:
7a5e4805 6533 *
79e53945
JB		 6534 * - if the connector already has an assigned crtc, use it (but make
6535 * sure it's on first)
7a5e4805 6536 *
79e53945
JB		 6537 * - try to find the first unused crtc that can drive this connector,
6538 * and use that if we find one
79e53945
JB		 6539 */
6540
6541 /* See if we already have a CRTC for this connector */
6542 if (encoder->crtc) {
6543 crtc = encoder->crtc;
8261b191 6544
7b24056b
DV		 6545 mutex_lock(&crtc->mutex);
6546
24218aac 6547 old->dpms_mode = connector->dpms;
8261b191
CW		 6548 old->load_detect_temp = false;
6549
6550 /* Make sure the crtc and connector are running */
24218aac
DV		 6551 if (connector->dpms != DRM_MODE_DPMS_ON)
6552 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6553
7173188d 6554 return true;
79e53945
JB		 6555 }
6556
6557 /* Find an unused one (if possible) */
6558 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6559 i++;
6560 if (!(encoder->possible_crtcs & (1 << i)))
6561 continue;
6562 if (!possible_crtc->enabled) {
6563 crtc = possible_crtc;
6564 break;
6565 }
79e53945
JB		 6566 }
6567
6568 /*
6569 * If we didn't find an unused CRTC, don't use any.
6570 */
6571 if (!crtc) {
7173188d
CW		 6572 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6573 return false;
79e53945
JB		 6574 }
6575
7b24056b 6576 mutex_lock(&crtc->mutex);
fc303101
DV		 6577 intel_encoder->new_crtc = to_intel_crtc(crtc);
6578 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6579
6580 intel_crtc = to_intel_crtc(crtc);
24218aac 6581 old->dpms_mode = connector->dpms;
8261b191 6582 old->load_detect_temp = true;
d2dff872 6583 old->release_fb = NULL;
79e53945 6584
6492711d
CW		 6585 if (!mode)
6586 mode = &load_detect_mode;
79e53945 6587
d2dff872
CW		 6588 /* We need a framebuffer large enough to accommodate all accesses
6589 * that the plane may generate whilst we perform load detection.
6590 * We can not rely on the fbcon either being present (we get called
6591 * during its initialisation to detect all boot displays, or it may
6592 * not even exist) or that it is large enough to satisfy the
6593 * requested mode.
6594 */
94352cf9
DV		 6595 fb = mode_fits_in_fbdev(dev, mode);
6596 if (fb == NULL) {
d2dff872 6597 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6598 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6599 old->release_fb = fb;
d2dff872
CW		 6600 } else
6601 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6602 if (IS_ERR(fb)) {
d2dff872 6603 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6604 mutex_unlock(&crtc->mutex);
0e8b3d3e 6605 return false;
79e53945 6606 }
79e53945 6607
c0c36b94 6608 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6609 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6610 if (old->release_fb)
6611 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6612 mutex_unlock(&crtc->mutex);
0e8b3d3e 6613 return false;
79e53945 6614 }
7173188d 6615
79e53945 6616 /* let the connector get through one full cycle before testing */
9d0498a2 6617 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6618 return true;
79e53945
JB		 6619}
6620
d2434ab7 6621void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6622 struct intel_load_detect_pipe *old)
79e53945 6623{
d2434ab7
DV		 6624 struct intel_encoder *intel_encoder =
6625 intel_attached_encoder(connector);
4ef69c7a 6626 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6627 struct drm_crtc *crtc = encoder->crtc;
79e53945 6628
d2dff872
CW		 6629 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6630 connector->base.id, drm_get_connector_name(connector),
6631 encoder->base.id, drm_get_encoder_name(encoder));
6632
8261b191 6633 if (old->load_detect_temp) {
fc303101
DV		 6634 to_intel_connector(connector)->new_encoder = NULL;
6635 intel_encoder->new_crtc = NULL;
6636 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6637
36206361
DV		 6638 if (old->release_fb) {
6639 drm_framebuffer_unregister_private(old->release_fb);
6640 drm_framebuffer_unreference(old->release_fb);
6641 }
d2dff872 6642
67c96400 6643 mutex_unlock(&crtc->mutex);
0622a53c 6644 return;
79e53945
JB		 6645 }
6646
c751ce4f 6647 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6648 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6649 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6650
6651 mutex_unlock(&crtc->mutex);
79e53945
JB		 6652}
6653
6654/* Returns the clock of the currently programmed mode of the given pipe. */
6655static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6656{
6657 struct drm_i915_private *dev_priv = dev->dev_private;
6658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6659 int pipe = intel_crtc->pipe;
548f245b 6660 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6661 u32 fp;
6662 intel_clock_t clock;
6663
6664 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6665 fp = I915_READ(FP0(pipe));
79e53945 6666 else
39adb7a5 6667 fp = I915_READ(FP1(pipe));
79e53945
JB		 6668
6669 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6670 if (IS_PINEVIEW(dev)) {
6671 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6672 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6673 } else {
6674 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6675 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6676 }
6677
a6c45cf0 6678 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6679 if (IS_PINEVIEW(dev))
6680 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6681 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6682 else
6683 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6684 DPLL_FPA01_P1_POST_DIV_SHIFT);
6685
6686 switch (dpll & DPLL_MODE_MASK) {
6687 case DPLLB_MODE_DAC_SERIAL:
6688 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6689 5 : 10;
6690 break;
6691 case DPLLB_MODE_LVDS:
6692 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6693 7 : 14;
6694 break;
6695 default:
28c97730 6696 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6697 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6698 return 0;
6699 }
6700
6701 /* XXX: Handle the 100Mhz refclk */
2177832f 6702 intel_clock(dev, 96000, &clock);
79e53945
JB		 6703 } else {
6704 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6705
6706 if (is_lvds) {
6707 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6708 DPLL_FPA01_P1_POST_DIV_SHIFT);
6709 clock.p2 = 14;
6710
6711 if ((dpll & PLL_REF_INPUT_MASK) ==
6712 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6713 /* XXX: might not be 66MHz */
2177832f 6714 intel_clock(dev, 66000, &clock);
79e53945 6715 } else
2177832f 6716 intel_clock(dev, 48000, &clock);
79e53945
JB		 6717 } else {
6718 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6719 clock.p1 = 2;
6720 else {
6721 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6722 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6723 }
6724 if (dpll & PLL_P2_DIVIDE_BY_4)
6725 clock.p2 = 4;
6726 else
6727 clock.p2 = 2;
6728
2177832f 6729 intel_clock(dev, 48000, &clock);
79e53945
JB		 6730 }
6731 }
6732
6733 /* XXX: It would be nice to validate the clocks, but we can't reuse
6734 * i830PllIsValid() because it relies on the xf86_config connector
6735 * configuration being accurate, which it isn't necessarily.
6736 */
6737
6738 return clock.dot;
6739}
6740
6741/** Returns the currently programmed mode of the given pipe. */
6742struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6743 struct drm_crtc *crtc)
6744{
548f245b 6745 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6747 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6748 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6749 int htot = I915_READ(HTOTAL(cpu_transcoder));
6750 int hsync = I915_READ(HSYNC(cpu_transcoder));
6751 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6752 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6753
6754 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6755 if (!mode)
6756 return NULL;
6757
6758 mode->clock = intel_crtc_clock_get(dev, crtc);
6759 mode->hdisplay = (htot & 0xffff) + 1;
6760 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6761 mode->hsync_start = (hsync & 0xffff) + 1;
6762 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6763 mode->vdisplay = (vtot & 0xffff) + 1;
6764 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6765 mode->vsync_start = (vsync & 0xffff) + 1;
6766 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6767
6768 drm_mode_set_name(mode);
79e53945
JB		 6769
6770 return mode;
6771}
6772
3dec0095 6773static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6774{
6775 struct drm_device *dev = crtc->dev;
6776 drm_i915_private_t *dev_priv = dev->dev_private;
6777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6778 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6779 int dpll_reg = DPLL(pipe);
6780 int dpll;
652c393a 6781
bad720ff 6782 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6783 return;
6784
6785 if (!dev_priv->lvds_downclock_avail)
6786 return;
6787
dbdc6479 6788 dpll = I915_READ(dpll_reg);
652c393a 6789 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6790 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6791
8ac5a6d5 6792 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6793
6794 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6795 I915_WRITE(dpll_reg, dpll);
9d0498a2 6796 intel_wait_for_vblank(dev, pipe);
dbdc6479 6797
652c393a
JB		 6798 dpll = I915_READ(dpll_reg);
6799 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6800 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6801 }
652c393a
JB		 6802}
6803
6804static void intel_decrease_pllclock(struct drm_crtc *crtc)
6805{
6806 struct drm_device *dev = crtc->dev;
6807 drm_i915_private_t *dev_priv = dev->dev_private;
6808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6809
bad720ff 6810 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6811 return;
6812
6813 if (!dev_priv->lvds_downclock_avail)
6814 return;
6815
6816 /*
6817 * Since this is called by a timer, we should never get here in
6818 * the manual case.
6819 */
6820 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6821 int pipe = intel_crtc->pipe;
6822 int dpll_reg = DPLL(pipe);
6823 int dpll;
f6e5b160 6824
44d98a61 6825 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6826
8ac5a6d5 6827 assert_panel_unlocked(dev_priv, pipe);
652c393a 6828
dc257cf1 6829 dpll = I915_READ(dpll_reg);
652c393a
JB		 6830 dpll |= DISPLAY_RATE_SELECT_FPA1;
6831 I915_WRITE(dpll_reg, dpll);
9d0498a2 6832 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6833 dpll = I915_READ(dpll_reg);
6834 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6835 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6836 }
6837
6838}
6839
f047e395
CW		 6840void intel_mark_busy(struct drm_device *dev)
6841{
f047e395
CW		 6842 i915_update_gfx_val(dev->dev_private);
6843}
6844
6845void intel_mark_idle(struct drm_device *dev)
652c393a 6846{
652c393a 6847 struct drm_crtc *crtc;
652c393a
JB		 6848
6849 if (!i915_powersave)
6850 return;
6851
652c393a 6852 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6853 if (!crtc->fb)
6854 continue;
6855
725a5b54 6856 intel_decrease_pllclock(crtc);
652c393a 6857 }
652c393a
JB		 6858}
6859
725a5b54 6860void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6861{
f047e395
CW		 6862 struct drm_device *dev = obj->base.dev;
6863 struct drm_crtc *crtc;
652c393a 6864
f047e395 6865 if (!i915_powersave)
acb87dfb
CW		 6866 return;
6867
652c393a
JB		 6868 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6869 if (!crtc->fb)
6870 continue;
6871
f047e395 6872 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6873 intel_increase_pllclock(crtc);
652c393a
JB		 6874 }
6875}
6876
79e53945
JB		 6877static void intel_crtc_destroy(struct drm_crtc *crtc)
6878{
6879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6880 struct drm_device *dev = crtc->dev;
6881 struct intel_unpin_work *work;
6882 unsigned long flags;
6883
6884 spin_lock_irqsave(&dev->event_lock, flags);
6885 work = intel_crtc->unpin_work;
6886 intel_crtc->unpin_work = NULL;
6887 spin_unlock_irqrestore(&dev->event_lock, flags);
6888
6889 if (work) {
6890 cancel_work_sync(&work->work);
6891 kfree(work);
6892 }
79e53945
JB		 6893
6894 drm_crtc_cleanup(crtc);
67e77c5a 6895
79e53945
JB		 6896 kfree(intel_crtc);
6897}
6898
6b95a207
KH		 6899static void intel_unpin_work_fn(struct work_struct *__work)
6900{
6901 struct intel_unpin_work *work =
6902 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6903 struct drm_device *dev = work->crtc->dev;
6b95a207 6904
b4a98e57 6905 mutex_lock(&dev->struct_mutex);
1690e1eb 6906 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6907 drm_gem_object_unreference(&work->pending_flip_obj->base);
6908 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6909
b4a98e57
CW		 6910 intel_update_fbc(dev);
6911 mutex_unlock(&dev->struct_mutex);
6912
6913 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6914 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6915
6b95a207
KH		 6916 kfree(work);
6917}
6918
1afe3e9d 6919static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6920 struct drm_crtc *crtc)
6b95a207
KH		 6921{
6922 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6924 struct intel_unpin_work *work;
05394f39 6925 struct drm_i915_gem_object *obj;
6b95a207
KH		 6926 unsigned long flags;
6927
6928 /* Ignore early vblank irqs */
6929 if (intel_crtc == NULL)
6930 return;
6931
6932 spin_lock_irqsave(&dev->event_lock, flags);
6933 work = intel_crtc->unpin_work;
e7d841ca
CW		 6934
6935 /* Ensure we don't miss a work->pending update ... */
6936 smp_rmb();
6937
6938 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6939 spin_unlock_irqrestore(&dev->event_lock, flags);
6940 return;
6941 }
6942
e7d841ca
CW		 6943 /* and that the unpin work is consistent wrt ->pending. */
6944 smp_rmb();
6945
6b95a207 6946 intel_crtc->unpin_work = NULL;
6b95a207 6947
45a066eb
RC		 6948 if (work->event)
6949 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6950
0af7e4df
MK		 6951 drm_vblank_put(dev, intel_crtc->pipe);
6952
6b95a207
KH		 6953 spin_unlock_irqrestore(&dev->event_lock, flags);
6954
05394f39 6955 obj = work->old_fb_obj;
d9e86c0e 6956
2c10d571 6957 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6958
6959 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6960
6961 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6962}
6963
1afe3e9d
JB		 6964void intel_finish_page_flip(struct drm_device *dev, int pipe)
6965{
6966 drm_i915_private_t *dev_priv = dev->dev_private;
6967 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6968
49b14a5c 6969 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6970}
6971
6972void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6973{
6974 drm_i915_private_t *dev_priv = dev->dev_private;
6975 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6976
49b14a5c 6977 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6978}
6979
6b95a207
KH		 6980void intel_prepare_page_flip(struct drm_device *dev, int plane)
6981{
6982 drm_i915_private_t *dev_priv = dev->dev_private;
6983 struct intel_crtc *intel_crtc =
6984 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6985 unsigned long flags;
6986
e7d841ca
CW		 6987 /* NB: An MMIO update of the plane base pointer will also
6988 * generate a page-flip completion irq, i.e. every modeset
6989 * is also accompanied by a spurious intel_prepare_page_flip().
6990 */
6b95a207 6991 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 6992 if (intel_crtc->unpin_work)
6993 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 6994 spin_unlock_irqrestore(&dev->event_lock, flags);
6995}
6996
e7d841ca
CW		 6997inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6998{
6999 /* Ensure that the work item is consistent when activating it ... */
7000 smp_wmb();
7001 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7002 /* and that it is marked active as soon as the irq could fire. */
7003 smp_wmb();
7004}
7005
8c9f3aaf
JB		 7006static int intel_gen2_queue_flip(struct drm_device *dev,
7007 struct drm_crtc *crtc,
7008 struct drm_framebuffer *fb,
7009 struct drm_i915_gem_object *obj)
7010{
7011 struct drm_i915_private *dev_priv = dev->dev_private;
7012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7013 u32 flip_mask;
6d90c952 7014 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7015 int ret;
7016
6d90c952 7017 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7018 if (ret)
83d4092b 7019 goto err;
8c9f3aaf 7020
6d90c952 7021 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7022 if (ret)
83d4092b 7023 goto err_unpin;
8c9f3aaf
JB		 7024
7025 /* Can't queue multiple flips, so wait for the previous
7026 * one to finish before executing the next.
7027 */
7028 if (intel_crtc->plane)
7029 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7030 else
7031 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7032 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7033 intel_ring_emit(ring, MI_NOOP);
7034 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7035 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7036 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7037 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7038 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7039
7040 intel_mark_page_flip_active(intel_crtc);
6d90c952 7041 intel_ring_advance(ring);
83d4092b
CW		 7042 return 0;
7043
7044err_unpin:
7045 intel_unpin_fb_obj(obj);
7046err:
8c9f3aaf
JB		 7047 return ret;
7048}
7049
7050static int intel_gen3_queue_flip(struct drm_device *dev,
7051 struct drm_crtc *crtc,
7052 struct drm_framebuffer *fb,
7053 struct drm_i915_gem_object *obj)
7054{
7055 struct drm_i915_private *dev_priv = dev->dev_private;
7056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7057 u32 flip_mask;
6d90c952 7058 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7059 int ret;
7060
6d90c952 7061 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7062 if (ret)
83d4092b 7063 goto err;
8c9f3aaf 7064
6d90c952 7065 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7066 if (ret)
83d4092b 7067 goto err_unpin;
8c9f3aaf
JB		 7068
7069 if (intel_crtc->plane)
7070 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7071 else
7072 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7073 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7074 intel_ring_emit(ring, MI_NOOP);
7075 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7076 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7077 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7078 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7079 intel_ring_emit(ring, MI_NOOP);
7080
e7d841ca 7081 intel_mark_page_flip_active(intel_crtc);
6d90c952 7082 intel_ring_advance(ring);
83d4092b
CW		 7083 return 0;
7084
7085err_unpin:
7086 intel_unpin_fb_obj(obj);
7087err:
8c9f3aaf
JB		 7088 return ret;
7089}
7090
7091static int intel_gen4_queue_flip(struct drm_device *dev,
7092 struct drm_crtc *crtc,
7093 struct drm_framebuffer *fb,
7094 struct drm_i915_gem_object *obj)
7095{
7096 struct drm_i915_private *dev_priv = dev->dev_private;
7097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7098 uint32_t pf, pipesrc;
6d90c952 7099 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7100 int ret;
7101
6d90c952 7102 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7103 if (ret)
83d4092b 7104 goto err;
8c9f3aaf 7105
6d90c952 7106 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7107 if (ret)
83d4092b 7108 goto err_unpin;
8c9f3aaf
JB		 7109
7110 /* i965+ uses the linear or tiled offsets from the
7111 * Display Registers (which do not change across a page-flip)
7112 * so we need only reprogram the base address.
7113 */
6d90c952
DV		 7114 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7115 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7116 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7117 intel_ring_emit(ring,
7118 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7119 obj->tiling_mode);
8c9f3aaf
JB		 7120
7121 /* XXX Enabling the panel-fitter across page-flip is so far
7122 * untested on non-native modes, so ignore it for now.
7123 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7124 */
7125 pf = 0;
7126 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7127 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7128
7129 intel_mark_page_flip_active(intel_crtc);
6d90c952 7130 intel_ring_advance(ring);
83d4092b
CW		 7131 return 0;
7132
7133err_unpin:
7134 intel_unpin_fb_obj(obj);
7135err:
8c9f3aaf
JB		 7136 return ret;
7137}
7138
7139static int intel_gen6_queue_flip(struct drm_device *dev,
7140 struct drm_crtc *crtc,
7141 struct drm_framebuffer *fb,
7142 struct drm_i915_gem_object *obj)
7143{
7144 struct drm_i915_private *dev_priv = dev->dev_private;
7145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7146 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7147 uint32_t pf, pipesrc;
7148 int ret;
7149
6d90c952 7150 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7151 if (ret)
83d4092b 7152 goto err;
8c9f3aaf 7153
6d90c952 7154 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7155 if (ret)
83d4092b 7156 goto err_unpin;
8c9f3aaf 7157
6d90c952
DV		 7158 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7159 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7160 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7161 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7162
dc257cf1
DV		 7163 /* Contrary to the suggestions in the documentation,
7164 * "Enable Panel Fitter" does not seem to be required when page
7165 * flipping with a non-native mode, and worse causes a normal
7166 * modeset to fail.
7167 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7168 */
7169 pf = 0;
8c9f3aaf 7170 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7171 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7172
7173 intel_mark_page_flip_active(intel_crtc);
6d90c952 7174 intel_ring_advance(ring);
83d4092b
CW		 7175 return 0;
7176
7177err_unpin:
7178 intel_unpin_fb_obj(obj);
7179err:
8c9f3aaf
JB		 7180 return ret;
7181}
7182
7c9017e5
JB		 7183/*
7184 * On gen7 we currently use the blit ring because (in early silicon at least)
7185 * the render ring doesn't give us interrpts for page flip completion, which
7186 * means clients will hang after the first flip is queued. Fortunately the
7187 * blit ring generates interrupts properly, so use it instead.
7188 */
7189static int intel_gen7_queue_flip(struct drm_device *dev,
7190 struct drm_crtc *crtc,
7191 struct drm_framebuffer *fb,
7192 struct drm_i915_gem_object *obj)
7193{
7194 struct drm_i915_private *dev_priv = dev->dev_private;
7195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7196 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7197 uint32_t plane_bit = 0;
7c9017e5
JB		 7198 int ret;
7199
7200 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7201 if (ret)
83d4092b 7202 goto err;
7c9017e5 7203
cb05d8de
DV		 7204 switch(intel_crtc->plane) {
7205 case PLANE_A:
7206 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7207 break;
7208 case PLANE_B:
7209 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7210 break;
7211 case PLANE_C:
7212 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7213 break;
7214 default:
7215 WARN_ONCE(1, "unknown plane in flip command\n");
7216 ret = -ENODEV;
ab3951eb 7217 goto err_unpin;
cb05d8de
DV		 7218 }
7219
7c9017e5
JB		 7220 ret = intel_ring_begin(ring, 4);
7221 if (ret)
83d4092b 7222 goto err_unpin;
7c9017e5 7223
cb05d8de 7224 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7225 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7226 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7227 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7228
7229 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7230 intel_ring_advance(ring);
83d4092b
CW		 7231 return 0;
7232
7233err_unpin:
7234 intel_unpin_fb_obj(obj);
7235err:
7c9017e5
JB		 7236 return ret;
7237}
7238
8c9f3aaf
JB		 7239static int intel_default_queue_flip(struct drm_device *dev,
7240 struct drm_crtc *crtc,
7241 struct drm_framebuffer *fb,
7242 struct drm_i915_gem_object *obj)
7243{
7244 return -ENODEV;
7245}
7246
6b95a207
KH		 7247static int intel_crtc_page_flip(struct drm_crtc *crtc,
7248 struct drm_framebuffer *fb,
7249 struct drm_pending_vblank_event *event)
7250{
7251 struct drm_device *dev = crtc->dev;
7252 struct drm_i915_private *dev_priv = dev->dev_private;
7253 struct intel_framebuffer *intel_fb;
05394f39 7254 struct drm_i915_gem_object *obj;
6b95a207
KH		 7255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7256 struct intel_unpin_work *work;
8c9f3aaf 7257 unsigned long flags;
52e68630 7258 int ret;
6b95a207 7259
e6a595d2
VS		 7260 /* Can't change pixel format via MI display flips. */
7261 if (fb->pixel_format != crtc->fb->pixel_format)
7262 return -EINVAL;
7263
7264 /*
7265 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7266 * Note that pitch changes could also affect these register.
7267 */
7268 if (INTEL_INFO(dev)->gen > 3 &&
7269 (fb->offsets[0] != crtc->fb->offsets[0] ||
7270 fb->pitches[0] != crtc->fb->pitches[0]))
7271 return -EINVAL;
7272
6b95a207
KH		 7273 work = kzalloc(sizeof *work, GFP_KERNEL);
7274 if (work == NULL)
7275 return -ENOMEM;
7276
6b95a207 7277 work->event = event;
b4a98e57 7278 work->crtc = crtc;
6b95a207 7279 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7280 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7281 INIT_WORK(&work->work, intel_unpin_work_fn);
7282
7317c75e
JB		 7283 ret = drm_vblank_get(dev, intel_crtc->pipe);
7284 if (ret)
7285 goto free_work;
7286
6b95a207
KH		 7287 /* We borrow the event spin lock for protecting unpin_work */
7288 spin_lock_irqsave(&dev->event_lock, flags);
7289 if (intel_crtc->unpin_work) {
7290 spin_unlock_irqrestore(&dev->event_lock, flags);
7291 kfree(work);
7317c75e 7292 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7293
7294 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7295 return -EBUSY;
7296 }
7297 intel_crtc->unpin_work = work;
7298 spin_unlock_irqrestore(&dev->event_lock, flags);
7299
7300 intel_fb = to_intel_framebuffer(fb);
7301 obj = intel_fb->obj;
7302
b4a98e57
CW		 7303 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7304 flush_workqueue(dev_priv->wq);
7305
79158103
CW		 7306 ret = i915_mutex_lock_interruptible(dev);
7307 if (ret)
7308 goto cleanup;
6b95a207 7309
75dfca80 7310 /* Reference the objects for the scheduled work. */
05394f39
CW		 7311 drm_gem_object_reference(&work->old_fb_obj->base);
7312 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7313
7314 crtc->fb = fb;
96b099fd 7315
e1f99ce6 7316 work->pending_flip_obj = obj;
e1f99ce6 7317
4e5359cd
SF		 7318 work->enable_stall_check = true;
7319
b4a98e57 7320 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7321 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7322
8c9f3aaf
JB		 7323 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7324 if (ret)
7325 goto cleanup_pending;
6b95a207 7326
7782de3b 7327 intel_disable_fbc(dev);
f047e395 7328 intel_mark_fb_busy(obj);
6b95a207
KH		 7329 mutex_unlock(&dev->struct_mutex);
7330
e5510fac
JB		 7331 trace_i915_flip_request(intel_crtc->plane, obj);
7332
6b95a207 7333 return 0;
96b099fd 7334
8c9f3aaf 7335cleanup_pending:
b4a98e57 7336 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7337 drm_gem_object_unreference(&work->old_fb_obj->base);
7338 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7339 mutex_unlock(&dev->struct_mutex);
7340
79158103 7341cleanup:
96b099fd
CW		 7342 spin_lock_irqsave(&dev->event_lock, flags);
7343 intel_crtc->unpin_work = NULL;
7344 spin_unlock_irqrestore(&dev->event_lock, flags);
7345
7317c75e
JB		 7346 drm_vblank_put(dev, intel_crtc->pipe);
7347free_work:
96b099fd
CW		 7348 kfree(work);
7349
7350 return ret;
6b95a207
KH		 7351}
7352
f6e5b160 7353static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7354 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7355 .load_lut = intel_crtc_load_lut,
976f8a20 7356 .disable = intel_crtc_noop,
f6e5b160
CW		 7357};
7358
6ed0f796 7359bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7360{
6ed0f796
DV		 7361 struct intel_encoder *other_encoder;
7362 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7363
6ed0f796
DV		 7364 if (WARN_ON(!crtc))
7365 return false;
7366
7367 list_for_each_entry(other_encoder,
7368 &crtc->dev->mode_config.encoder_list,
7369 base.head) {
7370
7371 if (&other_encoder->new_crtc->base != crtc ||
7372 encoder == other_encoder)
7373 continue;
7374 else
7375 return true;
f47166d2
CW		 7376 }
7377
6ed0f796
DV		 7378 return false;
7379}
47f1c6c9 7380
50f56119
DV		 7381static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7382 struct drm_crtc *crtc)
7383{
7384 struct drm_device *dev;
7385 struct drm_crtc *tmp;
7386 int crtc_mask = 1;
47f1c6c9 7387
50f56119 7388 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7389
50f56119 7390 dev = crtc->dev;
47f1c6c9 7391
50f56119
DV		 7392 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7393 if (tmp == crtc)
7394 break;
7395 crtc_mask <<= 1;
7396 }
47f1c6c9 7397
50f56119
DV		 7398 if (encoder->possible_crtcs & crtc_mask)
7399 return true;
7400 return false;
47f1c6c9 7401}
79e53945 7402
9a935856
DV		 7403/**
7404 * intel_modeset_update_staged_output_state
7405 *
7406 * Updates the staged output configuration state, e.g. after we've read out the
7407 * current hw state.
7408 */
7409static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7410{
9a935856
DV		 7411 struct intel_encoder *encoder;
7412 struct intel_connector *connector;
f6e5b160 7413
9a935856
DV		 7414 list_for_each_entry(connector, &dev->mode_config.connector_list,
7415 base.head) {
7416 connector->new_encoder =
7417 to_intel_encoder(connector->base.encoder);
7418 }
f6e5b160 7419
9a935856
DV		 7420 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7421 base.head) {
7422 encoder->new_crtc =
7423 to_intel_crtc(encoder->base.crtc);
7424 }
f6e5b160
CW		 7425}
7426
9a935856
DV		 7427/**
7428 * intel_modeset_commit_output_state
7429 *
7430 * This function copies the stage display pipe configuration to the real one.
7431 */
7432static void intel_modeset_commit_output_state(struct drm_device *dev)
7433{
7434 struct intel_encoder *encoder;
7435 struct intel_connector *connector;
f6e5b160 7436
9a935856
DV		 7437 list_for_each_entry(connector, &dev->mode_config.connector_list,
7438 base.head) {
7439 connector->base.encoder = &connector->new_encoder->base;
7440 }
f6e5b160 7441
9a935856
DV		 7442 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7443 base.head) {
7444 encoder->base.crtc = &encoder->new_crtc->base;
7445 }
7446}
7447
7758a113
DV		 7448static struct drm_display_mode *
7449intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7450 struct drm_display_mode *mode)
ee7b9f93 7451{
7758a113
DV		 7452 struct drm_device *dev = crtc->dev;
7453 struct drm_display_mode *adjusted_mode;
7454 struct drm_encoder_helper_funcs *encoder_funcs;
7455 struct intel_encoder *encoder;
ee7b9f93 7456
7758a113
DV		 7457 adjusted_mode = drm_mode_duplicate(dev, mode);
7458 if (!adjusted_mode)
7459 return ERR_PTR(-ENOMEM);
7460
7461 /* Pass our mode to the connectors and the CRTC to give them a chance to
7462 * adjust it according to limitations or connector properties, and also
7463 * a chance to reject the mode entirely.
47f1c6c9 7464 */
7758a113
DV		 7465 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7466 base.head) {
47f1c6c9 7467
7758a113
DV		 7468 if (&encoder->new_crtc->base != crtc)
7469 continue;
7470 encoder_funcs = encoder->base.helper_private;
7471 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7472 adjusted_mode))) {
7473 DRM_DEBUG_KMS("Encoder fixup failed\n");
7474 goto fail;
7475 }
ee7b9f93 7476 }
47f1c6c9 7477
7758a113
DV		 7478 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7479 DRM_DEBUG_KMS("CRTC fixup failed\n");
7480 goto fail;
ee7b9f93 7481 }
7758a113 7482 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7483
7758a113
DV		 7484 return adjusted_mode;
7485fail:
7486 drm_mode_destroy(dev, adjusted_mode);
7487 return ERR_PTR(-EINVAL);
ee7b9f93 7488}
47f1c6c9 7489
e2e1ed41
DV		 7490/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7491 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7492static void
7493intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7494 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7495{
7496 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7497 struct drm_device *dev = crtc->dev;
7498 struct intel_encoder *encoder;
7499 struct intel_connector *connector;
7500 struct drm_crtc *tmp_crtc;
79e53945 7501
e2e1ed41 7502 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7503
e2e1ed41
DV		 7504 /* Check which crtcs have changed outputs connected to them, these need
7505 * to be part of the prepare_pipes mask. We don't (yet) support global
7506 * modeset across multiple crtcs, so modeset_pipes will only have one
7507 * bit set at most. */
7508 list_for_each_entry(connector, &dev->mode_config.connector_list,
7509 base.head) {
7510 if (connector->base.encoder == &connector->new_encoder->base)
7511 continue;
79e53945 7512
e2e1ed41
DV		 7513 if (connector->base.encoder) {
7514 tmp_crtc = connector->base.encoder->crtc;
7515
7516 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7517 }
7518
7519 if (connector->new_encoder)
7520 *prepare_pipes |=
7521 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7522 }
7523
e2e1ed41
DV		 7524 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7525 base.head) {
7526 if (encoder->base.crtc == &encoder->new_crtc->base)
7527 continue;
7528
7529 if (encoder->base.crtc) {
7530 tmp_crtc = encoder->base.crtc;
7531
7532 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7533 }
7534
7535 if (encoder->new_crtc)
7536 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7537 }
7538
e2e1ed41
DV		 7539 /* Check for any pipes that will be fully disabled ... */
7540 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7541 base.head) {
7542 bool used = false;
22fd0fab 7543
e2e1ed41
DV		 7544 /* Don't try to disable disabled crtcs. */
7545 if (!intel_crtc->base.enabled)
7546 continue;
7e7d76c3 7547
e2e1ed41
DV		 7548 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7549 base.head) {
7550 if (encoder->new_crtc == intel_crtc)
7551 used = true;
7552 }
7553
7554 if (!used)
7555 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7556 }
7557
e2e1ed41
DV		 7558
7559 /* set_mode is also used to update properties on life display pipes. */
7560 intel_crtc = to_intel_crtc(crtc);
7561 if (crtc->enabled)
7562 *prepare_pipes |= 1 << intel_crtc->pipe;
7563
7564 /* We only support modeset on one single crtc, hence we need to do that
7565 * only for the passed in crtc iff we change anything else than just
7566 * disable crtcs.
7567 *
7568 * This is actually not true, to be fully compatible with the old crtc
7569 * helper we automatically disable _any_ output (i.e. doesn't need to be
7570 * connected to the crtc we're modesetting on) if it's disconnected.
7571 * Which is a rather nutty api (since changed the output configuration
7572 * without userspace's explicit request can lead to confusion), but
7573 * alas. Hence we currently need to modeset on all pipes we prepare. */
7574 if (*prepare_pipes)
7575 *modeset_pipes = *prepare_pipes;
7576
7577 /* ... and mask these out. */
7578 *modeset_pipes &= ~(*disable_pipes);
7579 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7580}
79e53945 7581
ea9d758d 7582static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7583{
ea9d758d 7584 struct drm_encoder *encoder;
f6e5b160 7585 struct drm_device *dev = crtc->dev;
f6e5b160 7586
ea9d758d
DV		 7587 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7588 if (encoder->crtc == crtc)
7589 return true;
7590
7591 return false;
7592}
7593
7594static void
7595intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7596{
7597 struct intel_encoder *intel_encoder;
7598 struct intel_crtc *intel_crtc;
7599 struct drm_connector *connector;
7600
7601 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7602 base.head) {
7603 if (!intel_encoder->base.crtc)
7604 continue;
7605
7606 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7607
7608 if (prepare_pipes & (1 << intel_crtc->pipe))
7609 intel_encoder->connectors_active = false;
7610 }
7611
7612 intel_modeset_commit_output_state(dev);
7613
7614 /* Update computed state. */
7615 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7616 base.head) {
7617 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7618 }
7619
7620 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7621 if (!connector->encoder || !connector->encoder->crtc)
7622 continue;
7623
7624 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7625
7626 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7627 struct drm_property *dpms_property =
7628 dev->mode_config.dpms_property;
7629
ea9d758d 7630 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7631 drm_object_property_set_value(&connector->base,
68d34720
DV		 7632 dpms_property,
7633 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7634
7635 intel_encoder = to_intel_encoder(connector->encoder);
7636 intel_encoder->connectors_active = true;
7637 }
7638 }
7639
7640}
7641
25c5b266
DV		 7642#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7643 list_for_each_entry((intel_crtc), \
7644 &(dev)->mode_config.crtc_list, \
7645 base.head) \
7646 if (mask & (1 <<(intel_crtc)->pipe)) \
7647
b980514c 7648void
8af6cf88
DV		 7649intel_modeset_check_state(struct drm_device *dev)
7650{
7651 struct intel_crtc *crtc;
7652 struct intel_encoder *encoder;
7653 struct intel_connector *connector;
7654
7655 list_for_each_entry(connector, &dev->mode_config.connector_list,
7656 base.head) {
7657 /* This also checks the encoder/connector hw state with the
7658 * ->get_hw_state callbacks. */
7659 intel_connector_check_state(connector);
7660
7661 WARN(&connector->new_encoder->base != connector->base.encoder,
7662 "connector's staged encoder doesn't match current encoder\n");
7663 }
7664
7665 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7666 base.head) {
7667 bool enabled = false;
7668 bool active = false;
7669 enum pipe pipe, tracked_pipe;
7670
7671 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7672 encoder->base.base.id,
7673 drm_get_encoder_name(&encoder->base));
7674
7675 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7676 "encoder's stage crtc doesn't match current crtc\n");
7677 WARN(encoder->connectors_active && !encoder->base.crtc,
7678 "encoder's active_connectors set, but no crtc\n");
7679
7680 list_for_each_entry(connector, &dev->mode_config.connector_list,
7681 base.head) {
7682 if (connector->base.encoder != &encoder->base)
7683 continue;
7684 enabled = true;
7685 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7686 active = true;
7687 }
7688 WARN(!!encoder->base.crtc != enabled,
7689 "encoder's enabled state mismatch "
7690 "(expected %i, found %i)\n",
7691 !!encoder->base.crtc, enabled);
7692 WARN(active && !encoder->base.crtc,
7693 "active encoder with no crtc\n");
7694
7695 WARN(encoder->connectors_active != active,
7696 "encoder's computed active state doesn't match tracked active state "
7697 "(expected %i, found %i)\n", active, encoder->connectors_active);
7698
7699 active = encoder->get_hw_state(encoder, &pipe);
7700 WARN(active != encoder->connectors_active,
7701 "encoder's hw state doesn't match sw tracking "
7702 "(expected %i, found %i)\n",
7703 encoder->connectors_active, active);
7704
7705 if (!encoder->base.crtc)
7706 continue;
7707
7708 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7709 WARN(active && pipe != tracked_pipe,
7710 "active encoder's pipe doesn't match"
7711 "(expected %i, found %i)\n",
7712 tracked_pipe, pipe);
7713
7714 }
7715
7716 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7717 base.head) {
7718 bool enabled = false;
7719 bool active = false;
7720
7721 DRM_DEBUG_KMS("[CRTC:%d]\n",
7722 crtc->base.base.id);
7723
7724 WARN(crtc->active && !crtc->base.enabled,
7725 "active crtc, but not enabled in sw tracking\n");
7726
7727 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7728 base.head) {
7729 if (encoder->base.crtc != &crtc->base)
7730 continue;
7731 enabled = true;
7732 if (encoder->connectors_active)
7733 active = true;
7734 }
7735 WARN(active != crtc->active,
7736 "crtc's computed active state doesn't match tracked active state "
7737 "(expected %i, found %i)\n", active, crtc->active);
7738 WARN(enabled != crtc->base.enabled,
7739 "crtc's computed enabled state doesn't match tracked enabled state "
7740 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7741
7742 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7743 }
7744}
7745
c0c36b94
CW		 7746int intel_set_mode(struct drm_crtc *crtc,
7747 struct drm_display_mode *mode,
7748 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7749{
7750 struct drm_device *dev = crtc->dev;
dbf2b54e 7751 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7752 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7753 struct intel_crtc *intel_crtc;
7754 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7755 int ret = 0;
a6778b3c 7756
3ac18232 7757 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7758 if (!saved_mode)
7759 return -ENOMEM;
3ac18232 7760 saved_hwmode = saved_mode + 1;
a6778b3c 7761
e2e1ed41 7762 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7763 &prepare_pipes, &disable_pipes);
7764
7765 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7766 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7767
976f8a20
DV		 7768 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7769 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7770
3ac18232
TG		 7771 *saved_hwmode = crtc->hwmode;
7772 *saved_mode = crtc->mode;
a6778b3c 7773
25c5b266
DV		 7774 /* Hack: Because we don't (yet) support global modeset on multiple
7775 * crtcs, we don't keep track of the new mode for more than one crtc.
7776 * Hence simply check whether any bit is set in modeset_pipes in all the
7777 * pieces of code that are not yet converted to deal with mutliple crtcs
7778 * changing their mode at the same time. */
7779 adjusted_mode = NULL;
7780 if (modeset_pipes) {
7781 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7782 if (IS_ERR(adjusted_mode)) {
c0c36b94 7783 ret = PTR_ERR(adjusted_mode);
3ac18232 7784 goto out;
25c5b266 7785 }
25c5b266 7786 }
a6778b3c 7787
ea9d758d
DV		 7788 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7789 if (intel_crtc->base.enabled)
7790 dev_priv->display.crtc_disable(&intel_crtc->base);
7791 }
a6778b3c 7792
6c4c86f5
DV		 7793 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7794 * to set it here already despite that we pass it down the callchain.
f6e5b160 7795 */
6c4c86f5 7796 if (modeset_pipes)
25c5b266 7797 crtc->mode = *mode;
7758a113 7798
ea9d758d
DV		 7799 /* Only after disabling all output pipelines that will be changed can we
7800 * update the the output configuration. */
7801 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7802
47fab737
DV		 7803 if (dev_priv->display.modeset_global_resources)
7804 dev_priv->display.modeset_global_resources(dev);
7805
a6778b3c
DV		 7806 /* Set up the DPLL and any encoders state that needs to adjust or depend
7807 * on the DPLL.
f6e5b160 7808 */
25c5b266 7809 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94
CW		 7810 ret = intel_crtc_mode_set(&intel_crtc->base,
7811 mode, adjusted_mode,
7812 x, y, fb);
7813 if (ret)
7814 goto done;
a6778b3c
DV		 7815 }
7816
7817 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7818 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7819 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7820
25c5b266
DV		 7821 if (modeset_pipes) {
7822 /* Store real post-adjustment hardware mode. */
7823 crtc->hwmode = *adjusted_mode;
a6778b3c 7824
25c5b266
DV		 7825 /* Calculate and store various constants which
7826 * are later needed by vblank and swap-completion
7827 * timestamping. They are derived from true hwmode.
7828 */
7829 drm_calc_timestamping_constants(crtc);
7830 }
a6778b3c
DV		 7831
7832 /* FIXME: add subpixel order */
7833done:
7834 drm_mode_destroy(dev, adjusted_mode);
c0c36b94 7835 if (ret && crtc->enabled) {
3ac18232
TG		 7836 crtc->hwmode = *saved_hwmode;
7837 crtc->mode = *saved_mode;
8af6cf88
DV		 7838 } else {
7839 intel_modeset_check_state(dev);
a6778b3c
DV		 7840 }
7841
3ac18232
TG		 7842out:
7843 kfree(saved_mode);
a6778b3c 7844 return ret;
f6e5b160
CW		 7845}
7846
c0c36b94
CW		 7847void intel_crtc_restore_mode(struct drm_crtc *crtc)
7848{
7849 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7850}
7851
25c5b266
DV		 7852#undef for_each_intel_crtc_masked
7853
d9e55608
DV		 7854static void intel_set_config_free(struct intel_set_config *config)
7855{
7856 if (!config)
7857 return;
7858
1aa4b628
DV		 7859 kfree(config->save_connector_encoders);
7860 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7861 kfree(config);
7862}
7863
85f9eb71
DV		 7864static int intel_set_config_save_state(struct drm_device *dev,
7865 struct intel_set_config *config)
7866{
85f9eb71
DV		 7867 struct drm_encoder *encoder;
7868 struct drm_connector *connector;
7869 int count;
7870
1aa4b628
DV		 7871 config->save_encoder_crtcs =
7872 kcalloc(dev->mode_config.num_encoder,
7873 sizeof(struct drm_crtc *), GFP_KERNEL);
7874 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7875 return -ENOMEM;
7876
1aa4b628
DV		 7877 config->save_connector_encoders =
7878 kcalloc(dev->mode_config.num_connector,
7879 sizeof(struct drm_encoder *), GFP_KERNEL);
7880 if (!config->save_connector_encoders)
85f9eb71
DV		 7881 return -ENOMEM;
7882
7883 /* Copy data. Note that driver private data is not affected.
7884 * Should anything bad happen only the expected state is
7885 * restored, not the drivers personal bookkeeping.
7886 */
85f9eb71
DV		 7887 count = 0;
7888 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7889 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7890 }
7891
7892 count = 0;
7893 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7894 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7895 }
7896
7897 return 0;
7898}
7899
7900static void intel_set_config_restore_state(struct drm_device *dev,
7901 struct intel_set_config *config)
7902{
9a935856
DV		 7903 struct intel_encoder *encoder;
7904 struct intel_connector *connector;
85f9eb71
DV		 7905 int count;
7906
85f9eb71 7907 count = 0;
9a935856
DV		 7908 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7909 encoder->new_crtc =
7910 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7911 }
7912
7913 count = 0;
9a935856
DV		 7914 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7915 connector->new_encoder =
7916 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7917 }
7918}
7919
5e2b584e
DV		 7920static void
7921intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7922 struct intel_set_config *config)
7923{
7924
7925 /* We should be able to check here if the fb has the same properties
7926 * and then just flip_or_move it */
7927 if (set->crtc->fb != set->fb) {
7928 /* If we have no fb then treat it as a full mode set */
7929 if (set->crtc->fb == NULL) {
7930 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7931 config->mode_changed = true;
7932 } else if (set->fb == NULL) {
7933 config->mode_changed = true;
7934 } else if (set->fb->depth != set->crtc->fb->depth) {
7935 config->mode_changed = true;
7936 } else if (set->fb->bits_per_pixel !=
7937 set->crtc->fb->bits_per_pixel) {
7938 config->mode_changed = true;
7939 } else
7940 config->fb_changed = true;
7941 }
7942
835c5873 7943 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7944 config->fb_changed = true;
7945
7946 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7947 DRM_DEBUG_KMS("modes are different, full mode set\n");
7948 drm_mode_debug_printmodeline(&set->crtc->mode);
7949 drm_mode_debug_printmodeline(set->mode);
7950 config->mode_changed = true;
7951 }
7952}
7953
2e431051 7954static int
9a935856
DV		 7955intel_modeset_stage_output_state(struct drm_device *dev,
7956 struct drm_mode_set *set,
7957 struct intel_set_config *config)
50f56119 7958{
85f9eb71 7959 struct drm_crtc *new_crtc;
9a935856
DV		 7960 struct intel_connector *connector;
7961 struct intel_encoder *encoder;
2e431051 7962 int count, ro;
50f56119 7963
9abdda74 7964 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 7965 * of connectors. For paranoia, double-check this. */
7966 WARN_ON(!set->fb && (set->num_connectors != 0));
7967 WARN_ON(set->fb && (set->num_connectors == 0));
7968
50f56119 7969 count = 0;
9a935856
DV		 7970 list_for_each_entry(connector, &dev->mode_config.connector_list,
7971 base.head) {
7972 /* Otherwise traverse passed in connector list and get encoders
7973 * for them. */
50f56119 7974 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7975 if (set->connectors[ro] == &connector->base) {
7976 connector->new_encoder = connector->encoder;
50f56119
DV		 7977 break;
7978 }
7979 }
7980
9a935856
DV		 7981 /* If we disable the crtc, disable all its connectors. Also, if
7982 * the connector is on the changing crtc but not on the new
7983 * connector list, disable it. */
7984 if ((!set->fb || ro == set->num_connectors) &&
7985 connector->base.encoder &&
7986 connector->base.encoder->crtc == set->crtc) {
7987 connector->new_encoder = NULL;
7988
7989 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7990 connector->base.base.id,
7991 drm_get_connector_name(&connector->base));
7992 }
7993
7994
7995 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7996 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7997 config->mode_changed = true;
50f56119
DV		 7998 }
7999 }
9a935856 8000 /* connector->new_encoder is now updated for all connectors. */
50f56119 8001
9a935856 8002 /* Update crtc of enabled connectors. */
50f56119 8003 count = 0;
9a935856
DV		 8004 list_for_each_entry(connector, &dev->mode_config.connector_list,
8005 base.head) {
8006 if (!connector->new_encoder)
50f56119
DV		 8007 continue;
8008
9a935856 8009 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8010
8011 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8012 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8013 new_crtc = set->crtc;
8014 }
8015
8016 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8017 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8018 new_crtc)) {
5e2b584e 8019 return -EINVAL;
50f56119 8020 }
9a935856
DV		 8021 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8022
8023 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8024 connector->base.base.id,
8025 drm_get_connector_name(&connector->base),
8026 new_crtc->base.id);
8027 }
8028
8029 /* Check for any encoders that needs to be disabled. */
8030 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8031 base.head) {
8032 list_for_each_entry(connector,
8033 &dev->mode_config.connector_list,
8034 base.head) {
8035 if (connector->new_encoder == encoder) {
8036 WARN_ON(!connector->new_encoder->new_crtc);
8037
8038 goto next_encoder;
8039 }
8040 }
8041 encoder->new_crtc = NULL;
8042next_encoder:
8043 /* Only now check for crtc changes so we don't miss encoders
8044 * that will be disabled. */
8045 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8046 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8047 config->mode_changed = true;
50f56119
DV		 8048 }
8049 }
9a935856 8050 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8051
2e431051
DV		 8052 return 0;
8053}
8054
8055static int intel_crtc_set_config(struct drm_mode_set *set)
8056{
8057 struct drm_device *dev;
2e431051
DV		 8058 struct drm_mode_set save_set;
8059 struct intel_set_config *config;
8060 int ret;
2e431051 8061
8d3e375e
DV		 8062 BUG_ON(!set);
8063 BUG_ON(!set->crtc);
8064 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8065
8066 if (!set->mode)
8067 set->fb = NULL;
8068
431e50f7
DV		 8069 /* The fb helper likes to play gross jokes with ->mode_set_config.
8070 * Unfortunately the crtc helper doesn't do much at all for this case,
8071 * so we have to cope with this madness until the fb helper is fixed up. */
8072 if (set->fb && set->num_connectors == 0)
8073 return 0;
8074
2e431051
DV		 8075 if (set->fb) {
8076 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8077 set->crtc->base.id, set->fb->base.id,
8078 (int)set->num_connectors, set->x, set->y);
8079 } else {
8080 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8081 }
8082
8083 dev = set->crtc->dev;
8084
8085 ret = -ENOMEM;
8086 config = kzalloc(sizeof(*config), GFP_KERNEL);
8087 if (!config)
8088 goto out_config;
8089
8090 ret = intel_set_config_save_state(dev, config);
8091 if (ret)
8092 goto out_config;
8093
8094 save_set.crtc = set->crtc;
8095 save_set.mode = &set->crtc->mode;
8096 save_set.x = set->crtc->x;
8097 save_set.y = set->crtc->y;
8098 save_set.fb = set->crtc->fb;
8099
8100 /* Compute whether we need a full modeset, only an fb base update or no
8101 * change at all. In the future we might also check whether only the
8102 * mode changed, e.g. for LVDS where we only change the panel fitter in
8103 * such cases. */
8104 intel_set_config_compute_mode_changes(set, config);
8105
9a935856 8106 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8107 if (ret)
8108 goto fail;
8109
5e2b584e 8110 if (config->mode_changed) {
87f1faa6 8111 if (set->mode) {
50f56119
DV		 8112 DRM_DEBUG_KMS("attempting to set mode from"
8113 " userspace\n");
8114 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8115 }
8116
c0c36b94
CW		 8117 ret = intel_set_mode(set->crtc, set->mode,
8118 set->x, set->y, set->fb);
8119 if (ret) {
8120 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8121 set->crtc->base.id, ret);
87f1faa6
DV		 8122 goto fail;
8123 }
5e2b584e 8124 } else if (config->fb_changed) {
4878cae2
VS		 8125 intel_crtc_wait_for_pending_flips(set->crtc);
8126
4f660f49 8127 ret = intel_pipe_set_base(set->crtc,
94352cf9 8128 set->x, set->y, set->fb);
50f56119
DV		 8129 }
8130
d9e55608
DV		 8131 intel_set_config_free(config);
8132
50f56119
DV		 8133 return 0;
8134
8135fail:
85f9eb71 8136 intel_set_config_restore_state(dev, config);
50f56119
DV		 8137
8138 /* Try to restore the config */
5e2b584e 8139 if (config->mode_changed &&
c0c36b94
CW		 8140 intel_set_mode(save_set.crtc, save_set.mode,
8141 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8142 DRM_ERROR("failed to restore config after modeset failure\n");
8143
d9e55608
DV		 8144out_config:
8145 intel_set_config_free(config);
50f56119
DV		 8146 return ret;
8147}
f6e5b160
CW		 8148
8149static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8150 .cursor_set = intel_crtc_cursor_set,
8151 .cursor_move = intel_crtc_cursor_move,
8152 .gamma_set = intel_crtc_gamma_set,
50f56119 8153 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8154 .destroy = intel_crtc_destroy,
8155 .page_flip = intel_crtc_page_flip,
8156};
8157
79f689aa
PZ		 8158static void intel_cpu_pll_init(struct drm_device *dev)
8159{
affa9354 8160 if (HAS_DDI(dev))
79f689aa
PZ		 8161 intel_ddi_pll_init(dev);
8162}
8163
ee7b9f93
JB		 8164static void intel_pch_pll_init(struct drm_device *dev)
8165{
8166 drm_i915_private_t *dev_priv = dev->dev_private;
8167 int i;
8168
8169 if (dev_priv->num_pch_pll == 0) {
8170 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8171 return;
8172 }
8173
8174 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8175 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8176 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8177 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8178 }
8179}
8180
b358d0a6 8181static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8182{
22fd0fab 8183 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8184 struct intel_crtc *intel_crtc;
8185 int i;
8186
8187 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8188 if (intel_crtc == NULL)
8189 return;
8190
8191 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8192
8193 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8194 for (i = 0; i < 256; i++) {
8195 intel_crtc->lut_r[i] = i;
8196 intel_crtc->lut_g[i] = i;
8197 intel_crtc->lut_b[i] = i;
8198 }
8199
80824003
JB		 8200 /* Swap pipes & planes for FBC on pre-965 */
8201 intel_crtc->pipe = pipe;
8202 intel_crtc->plane = pipe;
a5c961d1 8203 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8204 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8205 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8206 intel_crtc->plane = !pipe;
80824003
JB		 8207 }
8208
22fd0fab
JB		 8209 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8210 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8211 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8212 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8213
5a354204 8214 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8215
79e53945 8216 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8217}
8218
08d7b3d1 8219int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8220 struct drm_file *file)
08d7b3d1 8221{
08d7b3d1 8222 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8223 struct drm_mode_object *drmmode_obj;
8224 struct intel_crtc *crtc;
08d7b3d1 8225
1cff8f6b
DV		 8226 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8227 return -ENODEV;
08d7b3d1 8228
c05422d5
DV		 8229 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8230 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8231
c05422d5 8232 if (!drmmode_obj) {
08d7b3d1
CW		 8233 DRM_ERROR("no such CRTC id\n");
8234 return -EINVAL;
8235 }
8236
c05422d5
DV		 8237 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8238 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8239
c05422d5 8240 return 0;
08d7b3d1
CW		 8241}
8242
66a9278e 8243static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8244{
66a9278e
DV		 8245 struct drm_device *dev = encoder->base.dev;
8246 struct intel_encoder *source_encoder;
79e53945 8247 int index_mask = 0;
79e53945
JB		 8248 int entry = 0;
8249
66a9278e
DV		 8250 list_for_each_entry(source_encoder,
8251 &dev->mode_config.encoder_list, base.head) {
8252
8253 if (encoder == source_encoder)
79e53945 8254 index_mask |= (1 << entry);
66a9278e
DV		 8255
8256 /* Intel hw has only one MUX where enocoders could be cloned. */
8257 if (encoder->cloneable && source_encoder->cloneable)
8258 index_mask |= (1 << entry);
8259
79e53945
JB		 8260 entry++;
8261 }
4ef69c7a 8262
79e53945
JB		 8263 return index_mask;
8264}
8265
4d302442
CW		 8266static bool has_edp_a(struct drm_device *dev)
8267{
8268 struct drm_i915_private *dev_priv = dev->dev_private;
8269
8270 if (!IS_MOBILE(dev))
8271 return false;
8272
8273 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8274 return false;
8275
8276 if (IS_GEN5(dev) &&
8277 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8278 return false;
8279
8280 return true;
8281}
8282
79e53945
JB		 8283static void intel_setup_outputs(struct drm_device *dev)
8284{
725e30ad 8285 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8286 struct intel_encoder *encoder;
cb0953d7 8287 bool dpd_is_edp = false;
f3cfcba6 8288 bool has_lvds;
79e53945 8289
f3cfcba6 8290 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8291 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8292 /* disable the panel fitter on everything but LVDS */
8293 I915_WRITE(PFIT_CONTROL, 0);
8294 }
79e53945 8295
affa9354 8296 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8297 intel_crt_init(dev);
cb0953d7 8298
affa9354 8299 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8300 int found;
8301
8302 /* Haswell uses DDI functions to detect digital outputs */
8303 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8304 /* DDI A only supports eDP */
8305 if (found)
8306 intel_ddi_init(dev, PORT_A);
8307
8308 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8309 * register */
8310 found = I915_READ(SFUSE_STRAP);
8311
8312 if (found & SFUSE_STRAP_DDIB_DETECTED)
8313 intel_ddi_init(dev, PORT_B);
8314 if (found & SFUSE_STRAP_DDIC_DETECTED)
8315 intel_ddi_init(dev, PORT_C);
8316 if (found & SFUSE_STRAP_DDID_DETECTED)
8317 intel_ddi_init(dev, PORT_D);
8318 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8319 int found;
270b3042
DV		 8320 dpd_is_edp = intel_dpd_is_edp(dev);
8321
8322 if (has_edp_a(dev))
8323 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8324
30ad48b7 8325 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8326 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8327 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8328 if (!found)
08d644ad 8329 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8330 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8331 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8332 }
8333
8334 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8335 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8336
b708a1d5 8337 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8338 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8339
5eb08b69 8340 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8341 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8342
270b3042 8343 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8344 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8345 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8346 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8347 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8348 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8349
67cfc203
VS		 8350 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8351 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8352 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8353 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d
JB		 8354 }
8355
67cfc203
VS		 8356 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8357 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
5eb08b69 8358
103a196f 8359 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8360 bool found = false;
7d57382e 8361
725e30ad 8362 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8363 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8364 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8365 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8366 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8367 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8368 }
27185ae1 8369
b01f2c3a
JB		 8370 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8371 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8372 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8373 }
725e30ad 8374 }
13520b05
KH		 8375
8376 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8377
b01f2c3a
JB		 8378 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8379 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8380 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8381 }
27185ae1
ML		 8382
8383 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8384
b01f2c3a
JB		 8385 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8386 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8387 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8388 }
8389 if (SUPPORTS_INTEGRATED_DP(dev)) {
8390 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8391 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8392 }
725e30ad 8393 }
27185ae1 8394
b01f2c3a
JB		 8395 if (SUPPORTS_INTEGRATED_DP(dev) &&
8396 (I915_READ(DP_D) & DP_DETECTED)) {
8397 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8398 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8399 }
bad720ff 8400 } else if (IS_GEN2(dev))
79e53945
JB		 8401 intel_dvo_init(dev);
8402
103a196f 8403 if (SUPPORTS_TV(dev))
79e53945
JB		 8404 intel_tv_init(dev);
8405
4ef69c7a
CW		 8406 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8407 encoder->base.possible_crtcs = encoder->crtc_mask;
8408 encoder->base.possible_clones =
66a9278e 8409 intel_encoder_clones(encoder);
79e53945 8410 }
47356eb6 8411
dde86e2d 8412 intel_init_pch_refclk(dev);
270b3042
DV		 8413
8414 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8415}
8416
8417static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8418{
8419 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8420
8421 drm_framebuffer_cleanup(fb);
05394f39 8422 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8423
8424 kfree(intel_fb);
8425}
8426
8427static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8428 struct drm_file *file,
79e53945
JB		 8429 unsigned int *handle)
8430{
8431 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8432 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8433
05394f39 8434 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8435}
8436
8437static const struct drm_framebuffer_funcs intel_fb_funcs = {
8438 .destroy = intel_user_framebuffer_destroy,
8439 .create_handle = intel_user_framebuffer_create_handle,
8440};
8441
38651674
DA		 8442int intel_framebuffer_init(struct drm_device *dev,
8443 struct intel_framebuffer *intel_fb,
308e5bcb 8444 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8445 struct drm_i915_gem_object *obj)
79e53945 8446{
79e53945
JB		 8447 int ret;
8448
c16ed4be
CW		 8449 if (obj->tiling_mode == I915_TILING_Y) {
8450 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8451 return -EINVAL;
c16ed4be 8452 }
57cd6508 8453
c16ed4be
CW		 8454 if (mode_cmd->pitches[0] & 63) {
8455 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8456 mode_cmd->pitches[0]);
57cd6508 8457 return -EINVAL;
c16ed4be 8458 }
57cd6508 8459
5d7bd705 8460 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8461 if (mode_cmd->pitches[0] > 32768) {
8462 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8463 mode_cmd->pitches[0]);
5d7bd705 8464 return -EINVAL;
c16ed4be 8465 }
5d7bd705
VS		 8466
8467 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8468 mode_cmd->pitches[0] != obj->stride) {
8469 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8470 mode_cmd->pitches[0], obj->stride);
5d7bd705 8471 return -EINVAL;
c16ed4be 8472 }
5d7bd705 8473
57779d06 8474 /* Reject formats not supported by any plane early. */
308e5bcb 8475 switch (mode_cmd->pixel_format) {
57779d06 8476 case DRM_FORMAT_C8:
04b3924d
VS		 8477 case DRM_FORMAT_RGB565:
8478 case DRM_FORMAT_XRGB8888:
8479 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8480 break;
8481 case DRM_FORMAT_XRGB1555:
8482 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8483 if (INTEL_INFO(dev)->gen > 3) {
8484 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8485 return -EINVAL;
c16ed4be 8486 }
57779d06
VS		 8487 break;
8488 case DRM_FORMAT_XBGR8888:
8489 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8490 case DRM_FORMAT_XRGB2101010:
8491 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8492 case DRM_FORMAT_XBGR2101010:
8493 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8494 if (INTEL_INFO(dev)->gen < 4) {
8495 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8496 return -EINVAL;
c16ed4be 8497 }
b5626747 8498 break;
04b3924d
VS		 8499 case DRM_FORMAT_YUYV:
8500 case DRM_FORMAT_UYVY:
8501 case DRM_FORMAT_YVYU:
8502 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8503 if (INTEL_INFO(dev)->gen < 5) {
8504 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8505 return -EINVAL;
c16ed4be 8506 }
57cd6508
CW		 8507 break;
8508 default:
c16ed4be 8509 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8510 return -EINVAL;
8511 }
8512
90f9a336
VS		 8513 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8514 if (mode_cmd->offsets[0] != 0)
8515 return -EINVAL;
8516
c7d73f6a
DV		 8517 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8518 intel_fb->obj = obj;
8519
79e53945
JB		 8520 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8521 if (ret) {
8522 DRM_ERROR("framebuffer init failed %d\n", ret);
8523 return ret;
8524 }
8525
79e53945
JB		 8526 return 0;
8527}
8528
79e53945
JB		 8529static struct drm_framebuffer *
8530intel_user_framebuffer_create(struct drm_device *dev,
8531 struct drm_file *filp,
308e5bcb 8532 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8533{
05394f39 8534 struct drm_i915_gem_object *obj;
79e53945 8535
308e5bcb
JB		 8536 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8537 mode_cmd->handles[0]));
c8725226 8538 if (&obj->base == NULL)
cce13ff7 8539 return ERR_PTR(-ENOENT);
79e53945 8540
d2dff872 8541 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8542}
8543
79e53945 8544static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8545 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8546 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8547};
8548
e70236a8
JB		 8549/* Set up chip specific display functions */
8550static void intel_init_display(struct drm_device *dev)
8551{
8552 struct drm_i915_private *dev_priv = dev->dev_private;
8553
8554 /* We always want a DPMS function */
affa9354 8555 if (HAS_DDI(dev)) {
09b4ddf9 8556 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8557 dev_priv->display.crtc_enable = haswell_crtc_enable;
8558 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8559 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8560 dev_priv->display.update_plane = ironlake_update_plane;
8561 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8562 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8563 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8564 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8565 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8566 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8567 } else {
f564048e 8568 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8569 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8570 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8571 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8572 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8573 }
e70236a8 8574
e70236a8 8575 /* Returns the core display clock speed */
25eb05fc
JB		 8576 if (IS_VALLEYVIEW(dev))
8577 dev_priv->display.get_display_clock_speed =
8578 valleyview_get_display_clock_speed;
8579 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8580 dev_priv->display.get_display_clock_speed =
8581 i945_get_display_clock_speed;
8582 else if (IS_I915G(dev))
8583 dev_priv->display.get_display_clock_speed =
8584 i915_get_display_clock_speed;
f2b115e6 8585 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8586 dev_priv->display.get_display_clock_speed =
8587 i9xx_misc_get_display_clock_speed;
8588 else if (IS_I915GM(dev))
8589 dev_priv->display.get_display_clock_speed =
8590 i915gm_get_display_clock_speed;
8591 else if (IS_I865G(dev))
8592 dev_priv->display.get_display_clock_speed =
8593 i865_get_display_clock_speed;
f0f8a9ce 8594 else if (IS_I85X(dev))
e70236a8
JB		 8595 dev_priv->display.get_display_clock_speed =
8596 i855_get_display_clock_speed;
8597 else /* 852, 830 */
8598 dev_priv->display.get_display_clock_speed =
8599 i830_get_display_clock_speed;
8600
7f8a8569 8601 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8602 if (IS_GEN5(dev)) {
674cf967 8603 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8604 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8605 } else if (IS_GEN6(dev)) {
674cf967 8606 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8607 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8608 } else if (IS_IVYBRIDGE(dev)) {
8609 /* FIXME: detect B0+ stepping and use auto training */
8610 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8611 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8612 dev_priv->display.modeset_global_resources =
8613 ivb_modeset_global_resources;
c82e4d26
ED		 8614 } else if (IS_HASWELL(dev)) {
8615 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8616 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8617 dev_priv->display.modeset_global_resources =
8618 haswell_modeset_global_resources;
a0e63c22 8619 }
6067aaea 8620 } else if (IS_G4X(dev)) {
e0dac65e 8621 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8622 }
8c9f3aaf
JB		 8623
8624 /* Default just returns -ENODEV to indicate unsupported */
8625 dev_priv->display.queue_flip = intel_default_queue_flip;
8626
8627 switch (INTEL_INFO(dev)->gen) {
8628 case 2:
8629 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8630 break;
8631
8632 case 3:
8633 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8634 break;
8635
8636 case 4:
8637 case 5:
8638 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8639 break;
8640
8641 case 6:
8642 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8643 break;
7c9017e5
JB		 8644 case 7:
8645 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8646 break;
8c9f3aaf 8647 }
e70236a8
JB		 8648}
8649
b690e96c
JB		 8650/*
8651 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8652 * resume, or other times. This quirk makes sure that's the case for
8653 * affected systems.
8654 */
0206e353 8655static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8656{
8657 struct drm_i915_private *dev_priv = dev->dev_private;
8658
8659 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8660 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8661}
8662
435793df
KP		 8663/*
8664 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8665 */
8666static void quirk_ssc_force_disable(struct drm_device *dev)
8667{
8668 struct drm_i915_private *dev_priv = dev->dev_private;
8669 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8670 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8671}
8672
4dca20ef 8673/*
5a15ab5b
CE		 8674 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8675 * brightness value
4dca20ef
CE		 8676 */
8677static void quirk_invert_brightness(struct drm_device *dev)
8678{
8679 struct drm_i915_private *dev_priv = dev->dev_private;
8680 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8681 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8682}
8683
b690e96c
JB		 8684struct intel_quirk {
8685 int device;
8686 int subsystem_vendor;
8687 int subsystem_device;
8688 void (*hook)(struct drm_device *dev);
8689};
8690
5f85f176
EE		 8691/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8692struct intel_dmi_quirk {
8693 void (*hook)(struct drm_device *dev);
8694 const struct dmi_system_id (*dmi_id_list)[];
8695};
8696
8697static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8698{
8699 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8700 return 1;
8701}
8702
8703static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8704 {
8705 .dmi_id_list = &(const struct dmi_system_id[]) {
8706 {
8707 .callback = intel_dmi_reverse_brightness,
8708 .ident = "NCR Corporation",
8709 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8710 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8711 },
8712 },
8713 { } /* terminating entry */
8714 },
8715 .hook = quirk_invert_brightness,
8716 },
8717};
8718
c43b5634 8719static struct intel_quirk intel_quirks[] = {
b690e96c 8720 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8721 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8722
b690e96c
JB		 8723 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8724 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8725
b690e96c
JB		 8726 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8727 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8728
ccd0d36e 8729 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8730 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8731 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8732
8733 /* Lenovo U160 cannot use SSC on LVDS */
8734 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8735
8736 /* Sony Vaio Y cannot use SSC on LVDS */
8737 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8738
8739 /* Acer Aspire 5734Z must invert backlight brightness */
8740 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8741
8742 /* Acer/eMachines G725 */
8743 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8744
8745 /* Acer/eMachines e725 */
8746 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8747
8748 /* Acer/Packard Bell NCL20 */
8749 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8750
8751 /* Acer Aspire 4736Z */
8752 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8753};
8754
8755static void intel_init_quirks(struct drm_device *dev)
8756{
8757 struct pci_dev *d = dev->pdev;
8758 int i;
8759
8760 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8761 struct intel_quirk *q = &intel_quirks[i];
8762
8763 if (d->device == q->device &&
8764 (d->subsystem_vendor == q->subsystem_vendor ||
8765 q->subsystem_vendor == PCI_ANY_ID) &&
8766 (d->subsystem_device == q->subsystem_device ||
8767 q->subsystem_device == PCI_ANY_ID))
8768 q->hook(dev);
8769 }
5f85f176
EE		 8770 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8771 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8772 intel_dmi_quirks[i].hook(dev);
8773 }
b690e96c
JB		 8774}
8775
9cce37f4
JB		 8776/* Disable the VGA plane that we never use */
8777static void i915_disable_vga(struct drm_device *dev)
8778{
8779 struct drm_i915_private *dev_priv = dev->dev_private;
8780 u8 sr1;
766aa1c4 8781 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8782
8783 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8784 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8785 sr1 = inb(VGA_SR_DATA);
8786 outb(sr1 | 1<<5, VGA_SR_DATA);
8787 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8788 udelay(300);
8789
8790 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8791 POSTING_READ(vga_reg);
8792}
8793
f817586c
DV		 8794void intel_modeset_init_hw(struct drm_device *dev)
8795{
fa42e23c 8796 intel_init_power_well(dev);
0232e927 8797
a8f78b58
ED		 8798 intel_prepare_ddi(dev);
8799
f817586c
DV		 8800 intel_init_clock_gating(dev);
8801
79f5b2c7 8802 mutex_lock(&dev->struct_mutex);
8090c6b9 8803 intel_enable_gt_powersave(dev);
79f5b2c7 8804 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8805}
8806
79e53945
JB		 8807void intel_modeset_init(struct drm_device *dev)
8808{
652c393a 8809 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8810 int i, ret;
79e53945
JB		 8811
8812 drm_mode_config_init(dev);
8813
8814 dev->mode_config.min_width = 0;
8815 dev->mode_config.min_height = 0;
8816
019d96cb
DA		 8817 dev->mode_config.preferred_depth = 24;
8818 dev->mode_config.prefer_shadow = 1;
8819
e6ecefaa 8820 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8821
b690e96c
JB		 8822 intel_init_quirks(dev);
8823
1fa61106
ED		 8824 intel_init_pm(dev);
8825
e70236a8
JB		 8826 intel_init_display(dev);
8827
a6c45cf0
CW		 8828 if (IS_GEN2(dev)) {
8829 dev->mode_config.max_width = 2048;
8830 dev->mode_config.max_height = 2048;
8831 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8832 dev->mode_config.max_width = 4096;
8833 dev->mode_config.max_height = 4096;
79e53945 8834 } else {
a6c45cf0
CW		 8835 dev->mode_config.max_width = 8192;
8836 dev->mode_config.max_height = 8192;
79e53945 8837 }
5d4545ae 8838 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8839
28c97730 8840 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8841 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8842
a3524f1b 8843 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8844 intel_crtc_init(dev, i);
00c2064b
JB		 8845 ret = intel_plane_init(dev, i);
8846 if (ret)
8847 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8848 }
8849
79f689aa 8850 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8851 intel_pch_pll_init(dev);
8852
9cce37f4
JB		 8853 /* Just disable it once at startup */
8854 i915_disable_vga(dev);
79e53945 8855 intel_setup_outputs(dev);
11be49eb
CW		 8856
8857 /* Just in case the BIOS is doing something questionable. */
8858 intel_disable_fbc(dev);
2c7111db
CW		 8859}
8860
24929352
DV		 8861static void
8862intel_connector_break_all_links(struct intel_connector *connector)
8863{
8864 connector->base.dpms = DRM_MODE_DPMS_OFF;
8865 connector->base.encoder = NULL;
8866 connector->encoder->connectors_active = false;
8867 connector->encoder->base.crtc = NULL;
8868}
8869
7fad798e
DV		 8870static void intel_enable_pipe_a(struct drm_device *dev)
8871{
8872 struct intel_connector *connector;
8873 struct drm_connector *crt = NULL;
8874 struct intel_load_detect_pipe load_detect_temp;
8875
8876 /* We can't just switch on the pipe A, we need to set things up with a
8877 * proper mode and output configuration. As a gross hack, enable pipe A
8878 * by enabling the load detect pipe once. */
8879 list_for_each_entry(connector,
8880 &dev->mode_config.connector_list,
8881 base.head) {
8882 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8883 crt = &connector->base;
8884 break;
8885 }
8886 }
8887
8888 if (!crt)
8889 return;
8890
8891 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8892 intel_release_load_detect_pipe(crt, &load_detect_temp);
8893
652c393a 8894
7fad798e
DV		 8895}
8896
fa555837
DV		 8897static bool
8898intel_check_plane_mapping(struct intel_crtc *crtc)
8899{
8900 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8901 u32 reg, val;
8902
8903 if (dev_priv->num_pipe == 1)
8904 return true;
8905
8906 reg = DSPCNTR(!crtc->plane);
8907 val = I915_READ(reg);
8908
8909 if ((val & DISPLAY_PLANE_ENABLE) &&
8910 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8911 return false;
8912
8913 return true;
8914}
8915
24929352
DV		 8916static void intel_sanitize_crtc(struct intel_crtc *crtc)
8917{
8918 struct drm_device *dev = crtc->base.dev;
8919 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8920 u32 reg;
24929352 8921
24929352 8922 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8923 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8924 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8925
8926 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8927 * disable the crtc (and hence change the state) if it is wrong. Note
8928 * that gen4+ has a fixed plane -> pipe mapping. */
8929 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8930 struct intel_connector *connector;
8931 bool plane;
8932
24929352
DV		 8933 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8934 crtc->base.base.id);
8935
8936 /* Pipe has the wrong plane attached and the plane is active.
8937 * Temporarily change the plane mapping and disable everything
8938 * ... */
8939 plane = crtc->plane;
8940 crtc->plane = !plane;
8941 dev_priv->display.crtc_disable(&crtc->base);
8942 crtc->plane = plane;
8943
8944 /* ... and break all links. */
8945 list_for_each_entry(connector, &dev->mode_config.connector_list,
8946 base.head) {
8947 if (connector->encoder->base.crtc != &crtc->base)
8948 continue;
8949
8950 intel_connector_break_all_links(connector);
8951 }
8952
8953 WARN_ON(crtc->active);
8954 crtc->base.enabled = false;
8955 }
24929352 8956
7fad798e
DV		 8957 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8958 crtc->pipe == PIPE_A && !crtc->active) {
8959 /* BIOS forgot to enable pipe A, this mostly happens after
8960 * resume. Force-enable the pipe to fix this, the update_dpms
8961 * call below we restore the pipe to the right state, but leave
8962 * the required bits on. */
8963 intel_enable_pipe_a(dev);
8964 }
8965
24929352
DV		 8966 /* Adjust the state of the output pipe according to whether we
8967 * have active connectors/encoders. */
8968 intel_crtc_update_dpms(&crtc->base);
8969
8970 if (crtc->active != crtc->base.enabled) {
8971 struct intel_encoder *encoder;
8972
8973 /* This can happen either due to bugs in the get_hw_state
8974 * functions or because the pipe is force-enabled due to the
8975 * pipe A quirk. */
8976 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8977 crtc->base.base.id,
8978 crtc->base.enabled ? "enabled" : "disabled",
8979 crtc->active ? "enabled" : "disabled");
8980
8981 crtc->base.enabled = crtc->active;
8982
8983 /* Because we only establish the connector -> encoder ->
8984 * crtc links if something is active, this means the
8985 * crtc is now deactivated. Break the links. connector
8986 * -> encoder links are only establish when things are
8987 * actually up, hence no need to break them. */
8988 WARN_ON(crtc->active);
8989
8990 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8991 WARN_ON(encoder->connectors_active);
8992 encoder->base.crtc = NULL;
8993 }
8994 }
8995}
8996
8997static void intel_sanitize_encoder(struct intel_encoder *encoder)
8998{
8999 struct intel_connector *connector;
9000 struct drm_device *dev = encoder->base.dev;
9001
9002 /* We need to check both for a crtc link (meaning that the
9003 * encoder is active and trying to read from a pipe) and the
9004 * pipe itself being active. */
9005 bool has_active_crtc = encoder->base.crtc &&
9006 to_intel_crtc(encoder->base.crtc)->active;
9007
9008 if (encoder->connectors_active && !has_active_crtc) {
9009 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9010 encoder->base.base.id,
9011 drm_get_encoder_name(&encoder->base));
9012
9013 /* Connector is active, but has no active pipe. This is
9014 * fallout from our resume register restoring. Disable
9015 * the encoder manually again. */
9016 if (encoder->base.crtc) {
9017 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9018 encoder->base.base.id,
9019 drm_get_encoder_name(&encoder->base));
9020 encoder->disable(encoder);
9021 }
9022
9023 /* Inconsistent output/port/pipe state happens presumably due to
9024 * a bug in one of the get_hw_state functions. Or someplace else
9025 * in our code, like the register restore mess on resume. Clamp
9026 * things to off as a safer default. */
9027 list_for_each_entry(connector,
9028 &dev->mode_config.connector_list,
9029 base.head) {
9030 if (connector->encoder != encoder)
9031 continue;
9032
9033 intel_connector_break_all_links(connector);
9034 }
9035 }
9036 /* Enabled encoders without active connectors will be fixed in
9037 * the crtc fixup. */
9038}
9039
44cec740 9040void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9041{
9042 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9043 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9044
9045 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9046 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9047 i915_disable_vga(dev);
0fde901f
KM		 9048 }
9049}
9050
24929352
DV		 9051/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9052 * and i915 state tracking structures. */
45e2b5f6
DV		 9053void intel_modeset_setup_hw_state(struct drm_device *dev,
9054 bool force_restore)
24929352
DV		 9055{
9056 struct drm_i915_private *dev_priv = dev->dev_private;
9057 enum pipe pipe;
9058 u32 tmp;
9059 struct intel_crtc *crtc;
9060 struct intel_encoder *encoder;
9061 struct intel_connector *connector;
9062
affa9354 9063 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9064 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9065
9066 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9067 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9068 case TRANS_DDI_EDP_INPUT_A_ON:
9069 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9070 pipe = PIPE_A;
9071 break;
9072 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9073 pipe = PIPE_B;
9074 break;
9075 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9076 pipe = PIPE_C;
9077 break;
9078 }
9079
9080 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9081 crtc->cpu_transcoder = TRANSCODER_EDP;
9082
9083 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9084 pipe_name(pipe));
9085 }
9086 }
9087
24929352
DV		 9088 for_each_pipe(pipe) {
9089 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9090
702e7a56 9091 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9092 if (tmp & PIPECONF_ENABLE)
9093 crtc->active = true;
9094 else
9095 crtc->active = false;
9096
9097 crtc->base.enabled = crtc->active;
9098
9099 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9100 crtc->base.base.id,
9101 crtc->active ? "enabled" : "disabled");
9102 }
9103
affa9354 9104 if (HAS_DDI(dev))
6441ab5f
PZ		 9105 intel_ddi_setup_hw_pll_state(dev);
9106
24929352
DV		 9107 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9108 base.head) {
9109 pipe = 0;
9110
9111 if (encoder->get_hw_state(encoder, &pipe)) {
9112 encoder->base.crtc =
9113 dev_priv->pipe_to_crtc_mapping[pipe];
9114 } else {
9115 encoder->base.crtc = NULL;
9116 }
9117
9118 encoder->connectors_active = false;
9119 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9120 encoder->base.base.id,
9121 drm_get_encoder_name(&encoder->base),
9122 encoder->base.crtc ? "enabled" : "disabled",
9123 pipe);
9124 }
9125
9126 list_for_each_entry(connector, &dev->mode_config.connector_list,
9127 base.head) {
9128 if (connector->get_hw_state(connector)) {
9129 connector->base.dpms = DRM_MODE_DPMS_ON;
9130 connector->encoder->connectors_active = true;
9131 connector->base.encoder = &connector->encoder->base;
9132 } else {
9133 connector->base.dpms = DRM_MODE_DPMS_OFF;
9134 connector->base.encoder = NULL;
9135 }
9136 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9137 connector->base.base.id,
9138 drm_get_connector_name(&connector->base),
9139 connector->base.encoder ? "enabled" : "disabled");
9140 }
9141
9142 /* HW state is read out, now we need to sanitize this mess. */
9143 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9144 base.head) {
9145 intel_sanitize_encoder(encoder);
9146 }
9147
9148 for_each_pipe(pipe) {
9149 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9150 intel_sanitize_crtc(crtc);
9151 }
9a935856 9152
45e2b5f6
DV		 9153 if (force_restore) {
9154 for_each_pipe(pipe) {
c0c36b94 9155 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
45e2b5f6 9156 }
0fde901f
KM		 9157
9158 i915_redisable_vga(dev);
45e2b5f6
DV		 9159 } else {
9160 intel_modeset_update_staged_output_state(dev);
9161 }
8af6cf88
DV		 9162
9163 intel_modeset_check_state(dev);
2e938892
DV		 9164
9165 drm_mode_config_reset(dev);
2c7111db
CW		 9166}
9167
9168void intel_modeset_gem_init(struct drm_device *dev)
9169{
1833b134 9170 intel_modeset_init_hw(dev);
02e792fb
DV		 9171
9172 intel_setup_overlay(dev);
24929352 9173
45e2b5f6 9174 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9175}
9176
9177void intel_modeset_cleanup(struct drm_device *dev)
9178{
652c393a
JB		 9179 struct drm_i915_private *dev_priv = dev->dev_private;
9180 struct drm_crtc *crtc;
9181 struct intel_crtc *intel_crtc;
9182
f87ea761 9183 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9184 mutex_lock(&dev->struct_mutex);
9185
723bfd70
JB		 9186 intel_unregister_dsm_handler();
9187
9188
652c393a
JB		 9189 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9190 /* Skip inactive CRTCs */
9191 if (!crtc->fb)
9192 continue;
9193
9194 intel_crtc = to_intel_crtc(crtc);
3dec0095 9195 intel_increase_pllclock(crtc);
652c393a
JB		 9196 }
9197
973d04f9 9198 intel_disable_fbc(dev);
e70236a8 9199
8090c6b9 9200 intel_disable_gt_powersave(dev);
0cdab21f 9201
930ebb46
DV		 9202 ironlake_teardown_rc6(dev);
9203
57f350b6
JB		 9204 if (IS_VALLEYVIEW(dev))
9205 vlv_init_dpio(dev);
9206
69341a5e
KH		 9207 mutex_unlock(&dev->struct_mutex);
9208
6c0d9350
DV		 9209 /* Disable the irq before mode object teardown, for the irq might
9210 * enqueue unpin/hotplug work. */
9211 drm_irq_uninstall(dev);
9212 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9213 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9214
1630fe75
CW		 9215 /* flush any delayed tasks or pending work */
9216 flush_scheduled_work();
9217
79e53945 9218 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9219
9220 intel_cleanup_overlay(dev);
79e53945
JB		 9221}
9222
f1c79df3
ZW		 9223/*
9224 * Return which encoder is currently attached for connector.
9225 */
df0e9248 9226struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9227{
df0e9248
CW		 9228 return &intel_attached_encoder(connector)->base;
9229}
f1c79df3 9230
df0e9248
CW		 9231void intel_connector_attach_encoder(struct intel_connector *connector,
9232 struct intel_encoder *encoder)
9233{
9234 connector->encoder = encoder;
9235 drm_mode_connector_attach_encoder(&connector->base,
9236 &encoder->base);
79e53945 9237}
28d52043
DA		 9238
9239/*
9240 * set vga decode state - true == enable VGA decode
9241 */
9242int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9243{
9244 struct drm_i915_private *dev_priv = dev->dev_private;
9245 u16 gmch_ctrl;
9246
9247 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9248 if (state)
9249 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9250 else
9251 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9252 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9253 return 0;
9254}
c4a1d9e4
CW		 9255
9256#ifdef CONFIG_DEBUG_FS
9257#include <linux/seq_file.h>
9258
9259struct intel_display_error_state {
9260 struct intel_cursor_error_state {
9261 u32 control;
9262 u32 position;
9263 u32 base;
9264 u32 size;
52331309 9265 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9266
9267 struct intel_pipe_error_state {
9268 u32 conf;
9269 u32 source;
9270
9271 u32 htotal;
9272 u32 hblank;
9273 u32 hsync;
9274 u32 vtotal;
9275 u32 vblank;
9276 u32 vsync;
52331309 9277 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9278
9279 struct intel_plane_error_state {
9280 u32 control;
9281 u32 stride;
9282 u32 size;
9283 u32 pos;
9284 u32 addr;
9285 u32 surface;
9286 u32 tile_offset;
52331309 9287 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9288};
9289
9290struct intel_display_error_state *
9291intel_display_capture_error_state(struct drm_device *dev)
9292{
0206e353 9293 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9294 struct intel_display_error_state *error;
702e7a56 9295 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9296 int i;
9297
9298 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9299 if (error == NULL)
9300 return NULL;
9301
52331309 9302 for_each_pipe(i) {
702e7a56
PZ		 9303 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9304
c4a1d9e4
CW		 9305 error->cursor[i].control = I915_READ(CURCNTR(i));
9306 error->cursor[i].position = I915_READ(CURPOS(i));
9307 error->cursor[i].base = I915_READ(CURBASE(i));
9308
9309 error->plane[i].control = I915_READ(DSPCNTR(i));
9310 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9311 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9312 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9313 error->plane[i].addr = I915_READ(DSPADDR(i));
9314 if (INTEL_INFO(dev)->gen >= 4) {
9315 error->plane[i].surface = I915_READ(DSPSURF(i));
9316 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9317 }
9318
702e7a56 9319 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9320 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9321 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9322 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9323 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9324 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9325 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9326 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9327 }
9328
9329 return error;
9330}
9331
9332void
9333intel_display_print_error_state(struct seq_file *m,
9334 struct drm_device *dev,
9335 struct intel_display_error_state *error)
9336{
52331309 9337 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9338 int i;
9339
52331309
DL		 9340 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9341 for_each_pipe(i) {
c4a1d9e4
CW		 9342 seq_printf(m, "Pipe [%d]:\n", i);
9343 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9344 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9345 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9346 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9347 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9348 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9349 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9350 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9351
9352 seq_printf(m, "Plane [%d]:\n", i);
9353 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9354 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9355 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9356 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9357 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9358 if (INTEL_INFO(dev)->gen >= 4) {
9359 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9360 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9361 }
9362
9363 seq_printf(m, "Cursor [%d]:\n", i);
9364 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9365 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9366 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9367 }
9368}
9369#endif
Linux kernel - Deliverables
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