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drm/i915: fix typo s/PatherPoint/PantherPoint/
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
a0c4da24
JB		 312static const intel_limit_t intel_limits_vlv_dac = {
313 .dot = { .min = 25000, .max = 270000 },
314 .vco = { .min = 4000000, .max = 6000000 },
315 .n = { .min = 1, .max = 7 },
316 .m = { .min = 22, .max = 450 }, /* guess */
317 .m1 = { .min = 2, .max = 3 },
318 .m2 = { .min = 11, .max = 156 },
319 .p = { .min = 10, .max = 30 },
75e53986 320 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 321 .p2 = { .dot_limit = 270000,
322 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 323};
324
325static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 326 .dot = { .min = 25000, .max = 270000 },
327 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 328 .n = { .min = 1, .max = 7 },
329 .m = { .min = 60, .max = 300 }, /* guess */
330 .m1 = { .min = 2, .max = 3 },
331 .m2 = { .min = 11, .max = 156 },
332 .p = { .min = 10, .max = 30 },
333 .p1 = { .min = 2, .max = 3 },
334 .p2 = { .dot_limit = 270000,
335 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 336};
337
e0638cdf
PZ		 338/**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342{
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351}
352
1b894b59
CW		 353static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
2c07245f 355{
b91ad0ec 356 struct drm_device *dev = crtc->dev;
2c07245f 357 const intel_limit_t *limit;
b91ad0ec
ZW		 358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 360 if (intel_is_dual_link_lvds(dev)) {
1b894b59 361 if (refclk == 100000)
b91ad0ec
ZW		 362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
1b894b59 366 if (refclk == 100000)
b91ad0ec
ZW		 367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
c6bb3538 371 } else
b91ad0ec 372 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 373
374 return limit;
375}
376
044c7c41
ML		 377static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378{
379 struct drm_device *dev = crtc->dev;
044c7c41
ML		 380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 383 if (intel_is_dual_link_lvds(dev))
e4b36699 384 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 385 else
e4b36699 386 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 389 limit = &intel_limits_g4x_hdmi;
044c7c41 390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 391 limit = &intel_limits_g4x_sdvo;
044c7c41 392 } else /* The option is for other outputs */
e4b36699 393 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 394
395 return limit;
396}
397
1b894b59 398static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 399{
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
bad720ff 403 if (HAS_PCH_SPLIT(dev))
1b894b59 404 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 405 else if (IS_G4X(dev)) {
044c7c41 406 limit = intel_g4x_limit(crtc);
f2b115e6 407 } else if (IS_PINEVIEW(dev)) {
2177832f 408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 409 limit = &intel_limits_pineview_lvds;
2177832f 410 else
f2b115e6 411 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 412 } else if (IS_VALLEYVIEW(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
414 limit = &intel_limits_vlv_dac;
a0c4da24 415 else
65ce4bf5 416 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
420 else
421 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 422 } else {
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 424 limit = &intel_limits_i8xx_lvds;
5d536e28 425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 426 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 427 else
428 limit = &intel_limits_i8xx_dac;
79e53945
JB		 429 }
430 return limit;
431}
432
f2b115e6
AJ		 433/* m1 is reserved as 0 in Pineview, n is a ring counter */
434static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 435{
2177832f
SL		 436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 clock->vco = refclk * clock->m / clock->n;
439 clock->dot = clock->vco / clock->p;
440}
441
7429e9d4
DV		 442static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
443{
444 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
445}
446
ac58c3f0 447static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 448{
7429e9d4 449 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 450 clock->p = clock->p1 * clock->p2;
451 clock->vco = refclk * clock->m / (clock->n + 2);
452 clock->dot = clock->vco / clock->p;
453}
454
7c04d1d9 455#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 456/**
457 * Returns whether the given set of divisors are valid for a given refclk with
458 * the given connectors.
459 */
460
1b894b59
CW		 461static bool intel_PLL_is_valid(struct drm_device *dev,
462 const intel_limit_t *limit,
463 const intel_clock_t *clock)
79e53945 464{
79e53945 465 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 466 INTELPllInvalid("p1 out of range\n");
79e53945 467 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 468 INTELPllInvalid("p out of range\n");
79e53945 469 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 470 INTELPllInvalid("m2 out of range\n");
79e53945 471 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 472 INTELPllInvalid("m1 out of range\n");
f2b115e6 473 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 474 INTELPllInvalid("m1 <= m2\n");
79e53945 475 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 476 INTELPllInvalid("m out of range\n");
79e53945 477 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 478 INTELPllInvalid("n out of range\n");
79e53945 479 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 480 INTELPllInvalid("vco out of range\n");
79e53945
JB		 481 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
482 * connector, etc., rather than just a single range.
483 */
484 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 485 INTELPllInvalid("dot out of range\n");
79e53945
JB		 486
487 return true;
488}
489
d4906093 490static bool
ee9300bb 491i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 492 int target, int refclk, intel_clock_t *match_clock,
493 intel_clock_t *best_clock)
79e53945
JB		 494{
495 struct drm_device *dev = crtc->dev;
79e53945 496 intel_clock_t clock;
79e53945
JB		 497 int err = target;
498
a210b028 499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 500 /*
a210b028
DV		 501 * For LVDS just rely on its current settings for dual-channel.
502 * We haven't figured out how to reliably set up different
503 * single/dual channel state, if we even can.
79e53945 504 */
1974cad0 505 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 506 clock.p2 = limit->p2.p2_fast;
507 else
508 clock.p2 = limit->p2.p2_slow;
509 } else {
510 if (target < limit->p2.dot_limit)
511 clock.p2 = limit->p2.p2_slow;
512 else
513 clock.p2 = limit->p2.p2_fast;
514 }
515
0206e353 516 memset(best_clock, 0, sizeof(*best_clock));
79e53945 517
42158660
ZY		 518 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
519 clock.m1++) {
520 for (clock.m2 = limit->m2.min;
521 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 522 if (clock.m2 >= clock.m1)
42158660
ZY		 523 break;
524 for (clock.n = limit->n.min;
525 clock.n <= limit->n.max; clock.n++) {
526 for (clock.p1 = limit->p1.min;
527 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 528 int this_err;
529
ac58c3f0
DV		 530 i9xx_clock(refclk, &clock);
531 if (!intel_PLL_is_valid(dev, limit,
532 &clock))
533 continue;
534 if (match_clock &&
535 clock.p != match_clock->p)
536 continue;
537
538 this_err = abs(clock.dot - target);
539 if (this_err < err) {
540 *best_clock = clock;
541 err = this_err;
542 }
543 }
544 }
545 }
546 }
547
548 return (err != target);
549}
550
551static bool
ee9300bb
DV		 552pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
553 int target, int refclk, intel_clock_t *match_clock,
554 intel_clock_t *best_clock)
79e53945
JB		 555{
556 struct drm_device *dev = crtc->dev;
79e53945 557 intel_clock_t clock;
79e53945
JB		 558 int err = target;
559
a210b028 560 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 561 /*
a210b028
DV		 562 * For LVDS just rely on its current settings for dual-channel.
563 * We haven't figured out how to reliably set up different
564 * single/dual channel state, if we even can.
79e53945 565 */
1974cad0 566 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 567 clock.p2 = limit->p2.p2_fast;
568 else
569 clock.p2 = limit->p2.p2_slow;
570 } else {
571 if (target < limit->p2.dot_limit)
572 clock.p2 = limit->p2.p2_slow;
573 else
574 clock.p2 = limit->p2.p2_fast;
575 }
576
0206e353 577 memset(best_clock, 0, sizeof(*best_clock));
79e53945 578
42158660
ZY		 579 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
580 clock.m1++) {
581 for (clock.m2 = limit->m2.min;
582 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 583 for (clock.n = limit->n.min;
584 clock.n <= limit->n.max; clock.n++) {
585 for (clock.p1 = limit->p1.min;
586 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 587 int this_err;
588
ac58c3f0 589 pineview_clock(refclk, &clock);
1b894b59
CW		 590 if (!intel_PLL_is_valid(dev, limit,
591 &clock))
79e53945 592 continue;
cec2f356
SP		 593 if (match_clock &&
594 clock.p != match_clock->p)
595 continue;
79e53945
JB		 596
597 this_err = abs(clock.dot - target);
598 if (this_err < err) {
599 *best_clock = clock;
600 err = this_err;
601 }
602 }
603 }
604 }
605 }
606
607 return (err != target);
608}
609
d4906093 610static bool
ee9300bb
DV		 611g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
612 int target, int refclk, intel_clock_t *match_clock,
613 intel_clock_t *best_clock)
d4906093
ML		 614{
615 struct drm_device *dev = crtc->dev;
d4906093
ML		 616 intel_clock_t clock;
617 int max_n;
618 bool found;
6ba770dc
AJ		 619 /* approximately equals target * 0.00585 */
620 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 621 found = false;
622
623 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 624 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 625 clock.p2 = limit->p2.p2_fast;
626 else
627 clock.p2 = limit->p2.p2_slow;
628 } else {
629 if (target < limit->p2.dot_limit)
630 clock.p2 = limit->p2.p2_slow;
631 else
632 clock.p2 = limit->p2.p2_fast;
633 }
634
635 memset(best_clock, 0, sizeof(*best_clock));
636 max_n = limit->n.max;
f77f13e2 637 /* based on hardware requirement, prefer smaller n to precision */
d4906093 638 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 639 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 640 for (clock.m1 = limit->m1.max;
641 clock.m1 >= limit->m1.min; clock.m1--) {
642 for (clock.m2 = limit->m2.max;
643 clock.m2 >= limit->m2.min; clock.m2--) {
644 for (clock.p1 = limit->p1.max;
645 clock.p1 >= limit->p1.min; clock.p1--) {
646 int this_err;
647
ac58c3f0 648 i9xx_clock(refclk, &clock);
1b894b59
CW		 649 if (!intel_PLL_is_valid(dev, limit,
650 &clock))
d4906093 651 continue;
1b894b59
CW		 652
653 this_err = abs(clock.dot - target);
d4906093
ML		 654 if (this_err < err_most) {
655 *best_clock = clock;
656 err_most = this_err;
657 max_n = clock.n;
658 found = true;
659 }
660 }
661 }
662 }
663 }
2c07245f
ZW		 664 return found;
665}
666
a0c4da24 667static bool
ee9300bb
DV		 668vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *match_clock,
670 intel_clock_t *best_clock)
a0c4da24
JB		 671{
672 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
673 u32 m, n, fastclk;
f3f08572 674 u32 updrate, minupdate, p;
a0c4da24
JB		 675 unsigned long bestppm, ppm, absppm;
676 int dotclk, flag;
677
af447bd3 678 flag = 0;
a0c4da24
JB		 679 dotclk = target * 1000;
680 bestppm = 1000000;
681 ppm = absppm = 0;
682 fastclk = dotclk / (2*100);
683 updrate = 0;
684 minupdate = 19200;
a0c4da24
JB		 685 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
686 bestm1 = bestm2 = bestp1 = bestp2 = 0;
687
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
690 updrate = refclk / n;
691 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
692 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
693 if (p2 > 10)
694 p2 = p2 - 1;
695 p = p1 * p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
5de56df5 698 m2 = DIV_ROUND_CLOSEST(fastclk * p * n, refclk * m1);
a0c4da24
JB		 699 m = m1 * m2;
700 vco = updrate * m;
43b0ac53
VS		 701
702 if (vco < limit->vco.min || vco >= limit->vco.max)
703 continue;
704
705 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
706 absppm = (ppm > 0) ? ppm : (-ppm);
707 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
708 bestppm = 0;
709 flag = 1;
710 }
711 if (absppm < bestppm - 10) {
712 bestppm = absppm;
713 flag = 1;
714 }
715 if (flag) {
716 bestn = n;
717 bestm1 = m1;
718 bestm2 = m2;
719 bestp1 = p1;
720 bestp2 = p2;
721 flag = 0;
a0c4da24
JB		 722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
20ddf665
VS		 736bool intel_crtc_active(struct drm_crtc *crtc)
737{
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
742 *
241bfc38 743 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 744 * as Haswell has gained clock readout/fastboot support.
745 *
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
748 */
749 return intel_crtc->active && crtc->fb &&
241bfc38 750 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 751}
752
a5c961d1
PZ		 753enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 enum pipe pipe)
755{
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758
3b117c8f 759 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 760}
761
a928d536
PZ		 762static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
766
767 frame = I915_READ(frame_reg);
768
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
771}
772
9d0498a2
JB		 773/**
774 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @dev: drm device
776 * @pipe: pipe to wait for
777 *
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 * mode setting code.
780 */
781void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 782{
9d0498a2 783 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 784 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 785
a928d536
PZ		 786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
788 return;
789 }
790
300387c0
CW		 791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
793 *
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
800 * vblanks...
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
803 */
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
806
9d0498a2 807 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
810 50))
9d0498a2
JB		 811 DRM_DEBUG_KMS("vblank wait timed out\n");
812}
813
ab7ad7f6
KP		 814/*
815 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 816 * @dev: drm device
817 * @pipe: pipe to wait for
818 *
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
822 *
ab7ad7f6
KP		 823 * On Gen4 and above:
824 * wait for the pipe register state bit to turn off
825 *
826 * Otherwise:
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
58e10eb9 829 *
9d0498a2 830 */
58e10eb9 831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 832{
833 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
835 pipe);
ab7ad7f6
KP		 836
837 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 838 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 839
840 /* Wait for the Pipe State to go off */
58e10eb9
CW		 841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
842 100))
284637d9 843 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 844 } else {
837ba00f 845 u32 last_line, line_mask;
58e10eb9 846 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
848
837ba00f
PZ		 849 if (IS_GEN2(dev))
850 line_mask = DSL_LINEMASK_GEN2;
851 else
852 line_mask = DSL_LINEMASK_GEN3;
853
ab7ad7f6
KP		 854 /* Wait for the display line to settle */
855 do {
837ba00f 856 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 857 mdelay(5);
837ba00f 858 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
284637d9 861 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 862 }
79e53945
JB		 863}
864
b0ea7d37
DL		 865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
c36346e3
DL		 877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
b0ea7d37
DL		 905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
b24e7179
JB		 910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
55607e8a
DV		 916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
b24e7179
JB		 918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
b24e7179 930
23538ef1
JN		 931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
55607e8a 949struct intel_shared_dpll *
e2b78267
DV		 950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
a43f6e0f 954 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 955 return NULL;
956
a43f6e0f 957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 958}
959
040484af 960/* For ILK+ */
55607e8a
DV		 961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
040484af 964{
040484af 965 bool cur_state;
5358901f 966 struct intel_dpll_hw_state hw_state;
040484af 967
9d82aa17
ED		 968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
92b27b08 973 if (WARN (!pll,
46edb027 974 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 975 return;
ee7b9f93 976
5358901f 977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 978 WARN(cur_state != state,
5358901f
DV		 979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
040484af 981}
040484af
JB		 982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
ad80a810
PZ		 989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
040484af 991
affa9354
PZ		 992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
ad80a810 994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 995 val = I915_READ(reg);
ad80a810 996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
d63fa0dc
PZ		 1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
bf507ef7 1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1037 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1038 return;
1039
040484af
JB		 1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
55607e8a
DV		 1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
040484af
JB		 1047{
1048 int reg;
1049 u32 val;
55607e8a 1050 bool cur_state;
040484af
JB		 1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
55607e8a
DV		 1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
040484af
JB		 1058}
1059
ea0760cf
JB		 1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
0de3b485 1066 bool locked = true;
ea0760cf
JB		 1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1086 pipe_name(pipe));
ea0760cf
JB		 1087}
1088
93ce0ba6
JN		 1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
b840d907
JB		 1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
b24e7179
JB		 1111{
1112 int reg;
1113 u32 val;
63d7bbe9 1114 bool cur_state;
702e7a56
PZ		 1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
b24e7179 1117
8e636784
DV		 1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
b97186f0
PZ		 1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
63d7bbe9
JB		 1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1133 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
b24e7179
JB		 1138{
1139 int reg;
1140 u32 val;
931872fc 1141 bool cur_state;
b24e7179
JB		 1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
931872fc
CW		 1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1149}
1150
931872fc
CW		 1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
b24e7179
JB		 1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
653e1026 1157 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
653e1026
VS		 1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
19ec1358 1169 return;
28c05794 1170 }
19ec1358 1171
b24e7179 1172 /* Need to check both planes against the pipe */
08e2a7de 1173 for_each_pipe(i) {
b24e7179
JB		 1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1181 }
1182}
1183
19332d7a
JB		 1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
20674eef 1187 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1188 int reg, i;
1189 u32 val;
1190
20674eef
VS		 1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & SPRITE_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
19332d7a 1207 val = I915_READ(reg);
20674eef 1208 WARN((val & DVS_ENABLE),
06da8da2 1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1210 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1211 }
1212}
1213
92f2584a
JB		 1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
9d82aa17
ED		 1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
92f2584a
JB		 1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
ab9412ba
DV		 1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
92f2584a
JB		 1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
ab9412ba 1237 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
92f2584a
JB		 1243}
1244
4e634389
KP		 1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1519b995
KP		 1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
dc0fa718 1266 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1271 return false;
1272 } else {
dc0fa718 1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
291906f1 1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1311 enum pipe pipe, int reg, u32 port_sel)
291906f1 1312{
47a05eca 1313 u32 val = I915_READ(reg);
4e634389 1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1316 reg, pipe_name(pipe));
de9a35ab 1317
75c5da27
DV		 1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
de9a35ab 1320 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
47a05eca 1326 u32 val = I915_READ(reg);
b70ad586 1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 reg, pipe_name(pipe));
de9a35ab 1330
dc0fa718 1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1332 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1333 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
291906f1 1341
f0575e92
KP		 1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1
JB		 1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
b70ad586 1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1356 pipe_name(pipe));
291906f1 1357
e2debe91
PZ		 1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1361}
1362
426115cf 1363static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1364{
426115cf
DV		 1365 struct drm_device *dev = crtc->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int reg = DPLL(crtc->pipe);
1368 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1369
426115cf 1370 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1371
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1377 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1378
426115cf
DV		 1379 I915_WRITE(reg, dpll);
1380 POSTING_READ(reg);
1381 udelay(150);
1382
1383 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1388
1389 /* We do this three times for luck */
426115cf 1390 I915_WRITE(reg, dpll);
87442f73
DV		 1391 POSTING_READ(reg);
1392 udelay(150); /* wait for warmup */
426115cf 1393 I915_WRITE(reg, dpll);
87442f73
DV		 1394 POSTING_READ(reg);
1395 udelay(150); /* wait for warmup */
426115cf 1396 I915_WRITE(reg, dpll);
87442f73
DV		 1397 POSTING_READ(reg);
1398 udelay(150); /* wait for warmup */
1399}
1400
66e3d5c0 1401static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1402{
66e3d5c0
DV		 1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1407
66e3d5c0 1408 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1409
63d7bbe9 1410 /* No really, not for ILK+ */
87442f73 1411 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1412
1413 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1414 if (IS_MOBILE(dev) && !IS_I830(dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1416
66e3d5c0
DV		 1417 I915_WRITE(reg, dpll);
1418
1419 /* Wait for the clocks to stabilize. */
1420 POSTING_READ(reg);
1421 udelay(150);
1422
1423 if (INTEL_INFO(dev)->gen >= 4) {
1424 I915_WRITE(DPLL_MD(crtc->pipe),
1425 crtc->config.dpll_hw_state.dpll_md);
1426 } else {
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1429 *
1430 * So write it again.
1431 */
1432 I915_WRITE(reg, dpll);
1433 }
63d7bbe9
JB		 1434
1435 /* We do this three times for luck */
66e3d5c0 1436 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1437 POSTING_READ(reg);
1438 udelay(150); /* wait for warmup */
66e3d5c0 1439 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1440 POSTING_READ(reg);
1441 udelay(150); /* wait for warmup */
66e3d5c0 1442 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1443 POSTING_READ(reg);
1444 udelay(150); /* wait for warmup */
1445}
1446
1447/**
50b44a44 1448 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1451 *
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1453 *
1454 * Note! This is for pre-ILK only.
1455 */
50b44a44 1456static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1457{
63d7bbe9
JB		 1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460 return;
1461
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv, pipe);
1464
50b44a44
DV		 1465 I915_WRITE(DPLL(pipe), 0);
1466 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1467}
1468
89b667f8
JB		 1469void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1470{
1471 u32 port_mask;
1472
1473 if (!port)
1474 port_mask = DPLL_PORTB_READY_MASK;
1475 else
1476 port_mask = DPLL_PORTC_READY_MASK;
1477
1478 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1479 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480 'B' + port, I915_READ(DPLL(0)));
1481}
1482
92f2584a 1483/**
e72f9fbf 1484 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1485 * @dev_priv: i915 private structure
1486 * @pipe: pipe PLL to enable
1487 *
1488 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489 * drives the transcoder clock.
1490 */
e2b78267 1491static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1492{
e2b78267
DV		 1493 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1494 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1495
48da64a8 1496 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1497 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1498 if (WARN_ON(pll == NULL))
48da64a8
CW		 1499 return;
1500
1501 if (WARN_ON(pll->refcount == 0))
1502 return;
ee7b9f93 1503
46edb027
DV		 1504 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505 pll->name, pll->active, pll->on,
e2b78267 1506 crtc->base.base.id);
92f2584a 1507
cdbd2316
DV		 1508 if (pll->active++) {
1509 WARN_ON(!pll->on);
e9d6944e 1510 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1511 return;
1512 }
f4a091c7 1513 WARN_ON(pll->on);
ee7b9f93 1514
46edb027 1515 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1516 pll->enable(dev_priv, pll);
ee7b9f93 1517 pll->on = true;
92f2584a
JB		 1518}
1519
e2b78267 1520static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1521{
e2b78267
DV		 1522 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1523 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1524
92f2584a
JB		 1525 /* PCH only available on ILK+ */
1526 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1527 if (WARN_ON(pll == NULL))
ee7b9f93 1528 return;
92f2584a 1529
48da64a8
CW		 1530 if (WARN_ON(pll->refcount == 0))
1531 return;
7a419866 1532
46edb027
DV		 1533 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534 pll->name, pll->active, pll->on,
e2b78267 1535 crtc->base.base.id);
7a419866 1536
48da64a8 1537 if (WARN_ON(pll->active == 0)) {
e9d6944e 1538 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1539 return;
1540 }
1541
e9d6944e 1542 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1543 WARN_ON(!pll->on);
cdbd2316 1544 if (--pll->active)
7a419866 1545 return;
ee7b9f93 1546
46edb027 1547 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1548 pll->disable(dev_priv, pll);
ee7b9f93 1549 pll->on = false;
92f2584a
JB		 1550}
1551
b8a4f404
PZ		 1552static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553 enum pipe pipe)
040484af 1554{
23670b32 1555 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1556 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1558 uint32_t reg, val, pipeconf_val;
040484af
JB		 1559
1560 /* PCH only available on ILK+ */
1561 BUG_ON(dev_priv->info->gen < 5);
1562
1563 /* Make sure PCH DPLL is enabled */
e72f9fbf 1564 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1565 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1566
1567 /* FDI must be feeding us bits for PCH ports */
1568 assert_fdi_tx_enabled(dev_priv, pipe);
1569 assert_fdi_rx_enabled(dev_priv, pipe);
1570
23670b32
DV		 1571 if (HAS_PCH_CPT(dev)) {
1572 /* Workaround: Set the timing override bit before enabling the
1573 * pch transcoder. */
1574 reg = TRANS_CHICKEN2(pipe);
1575 val = I915_READ(reg);
1576 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1577 I915_WRITE(reg, val);
59c859d6 1578 }
23670b32 1579
ab9412ba 1580 reg = PCH_TRANSCONF(pipe);
040484af 1581 val = I915_READ(reg);
5f7f726d 1582 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1583
1584 if (HAS_PCH_IBX(dev_priv->dev)) {
1585 /*
1586 * make the BPC in transcoder be consistent with
1587 * that in pipeconf reg.
1588 */
dfd07d72
DV		 1589 val &= ~PIPECONF_BPC_MASK;
1590 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1591 }
5f7f726d
PZ		 1592
1593 val &= ~TRANS_INTERLACE_MASK;
1594 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1595 if (HAS_PCH_IBX(dev_priv->dev) &&
1596 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1597 val |= TRANS_LEGACY_INTERLACED_ILK;
1598 else
1599 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1600 else
1601 val |= TRANS_PROGRESSIVE;
1602
040484af
JB		 1603 I915_WRITE(reg, val | TRANS_ENABLE);
1604 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1605 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1606}
1607
8fb033d7 1608static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1609 enum transcoder cpu_transcoder)
040484af 1610{
8fb033d7 1611 u32 val, pipeconf_val;
8fb033d7
PZ		 1612
1613 /* PCH only available on ILK+ */
1614 BUG_ON(dev_priv->info->gen < 5);
1615
8fb033d7 1616 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1617 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1618 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1619
223a6fdf
PZ		 1620 /* Workaround: set timing override bit. */
1621 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1623 I915_WRITE(_TRANSA_CHICKEN2, val);
1624
25f3ef11 1625 val = TRANS_ENABLE;
937bb610 1626 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1627
9a76b1c6
PZ		 1628 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1629 PIPECONF_INTERLACED_ILK)
a35f2679 1630 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1631 else
1632 val |= TRANS_PROGRESSIVE;
1633
ab9412ba
DV		 1634 I915_WRITE(LPT_TRANSCONF, val);
1635 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1636 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1637}
1638
b8a4f404
PZ		 1639static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1640 enum pipe pipe)
040484af 1641{
23670b32
DV		 1642 struct drm_device *dev = dev_priv->dev;
1643 uint32_t reg, val;
040484af
JB		 1644
1645 /* FDI relies on the transcoder */
1646 assert_fdi_tx_disabled(dev_priv, pipe);
1647 assert_fdi_rx_disabled(dev_priv, pipe);
1648
291906f1
JB		 1649 /* Ports must be off as well */
1650 assert_pch_ports_disabled(dev_priv, pipe);
1651
ab9412ba 1652 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1653 val = I915_READ(reg);
1654 val &= ~TRANS_ENABLE;
1655 I915_WRITE(reg, val);
1656 /* wait for PCH transcoder off, transcoder state */
1657 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1658 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1659
1660 if (!HAS_PCH_IBX(dev)) {
1661 /* Workaround: Clear the timing override chicken bit again. */
1662 reg = TRANS_CHICKEN2(pipe);
1663 val = I915_READ(reg);
1664 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1665 I915_WRITE(reg, val);
1666 }
040484af
JB		 1667}
1668
ab4d966c 1669static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1670{
8fb033d7
PZ		 1671 u32 val;
1672
ab9412ba 1673 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1674 val &= ~TRANS_ENABLE;
ab9412ba 1675 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1676 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1677 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1678 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1679
1680 /* Workaround: clear timing override bit. */
1681 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1682 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1683 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1684}
1685
b24e7179 1686/**
309cfea8 1687 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1688 * @dev_priv: i915 private structure
1689 * @pipe: pipe to enable
040484af 1690 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1691 *
1692 * Enable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe is actually running (i.e. first vblank) before
1698 * returning.
1699 */
040484af 1700static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1701 bool pch_port, bool dsi)
b24e7179 1702{
702e7a56
PZ		 1703 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1704 pipe);
1a240d4d 1705 enum pipe pch_transcoder;
b24e7179
JB		 1706 int reg;
1707 u32 val;
1708
58c6eaa2 1709 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1710 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1711 assert_sprites_disabled(dev_priv, pipe);
1712
681e5811 1713 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1714 pch_transcoder = TRANSCODER_A;
1715 else
1716 pch_transcoder = pipe;
1717
b24e7179
JB		 1718 /*
1719 * A pipe without a PLL won't actually be able to drive bits from
1720 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1721 * need the check.
1722 */
1723 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1724 if (dsi)
1725 assert_dsi_pll_enabled(dev_priv);
1726 else
1727 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1728 else {
1729 if (pch_port) {
1730 /* if driving the PCH, we need FDI enabled */
cc391bbb 1731 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1732 assert_fdi_tx_pll_enabled(dev_priv,
1733 (enum pipe) cpu_transcoder);
040484af
JB		 1734 }
1735 /* FIXME: assert CPU port conditions for SNB+ */
1736 }
b24e7179 1737
702e7a56 1738 reg = PIPECONF(cpu_transcoder);
b24e7179 1739 val = I915_READ(reg);
00d70b15
CW		 1740 if (val & PIPECONF_ENABLE)
1741 return;
1742
1743 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1744 intel_wait_for_vblank(dev_priv->dev, pipe);
1745}
1746
1747/**
309cfea8 1748 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1749 * @dev_priv: i915 private structure
1750 * @pipe: pipe to disable
1751 *
1752 * Disable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe has shut down before returning.
1758 */
1759static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1760 enum pipe pipe)
1761{
702e7a56
PZ		 1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
b24e7179
JB		 1764 int reg;
1765 u32 val;
1766
1767 /*
1768 * Make sure planes won't keep trying to pump pixels to us,
1769 * or we might hang the display.
1770 */
1771 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1772 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1773 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1774
1775 /* Don't disable pipe A or pipe A PLLs if needed */
1776 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1777 return;
1778
702e7a56 1779 reg = PIPECONF(cpu_transcoder);
b24e7179 1780 val = I915_READ(reg);
00d70b15
CW		 1781 if ((val & PIPECONF_ENABLE) == 0)
1782 return;
1783
1784 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1785 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1786}
1787
d74362c9
KP		 1788/*
1789 * Plane regs are double buffered, going from enabled->disabled needs a
1790 * trigger in order to latch. The display address reg provides this.
1791 */
6f1d69b0 1792void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1793 enum plane plane)
1794{
14f86147
DL		 1795 if (dev_priv->info->gen >= 4)
1796 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1797 else
1798 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1799}
1800
b24e7179
JB		 1801/**
1802 * intel_enable_plane - enable a display plane on a given pipe
1803 * @dev_priv: i915 private structure
1804 * @plane: plane to enable
1805 * @pipe: pipe being fed
1806 *
1807 * Enable @plane on @pipe, making sure that @pipe is running first.
1808 */
1809static void intel_enable_plane(struct drm_i915_private *dev_priv,
1810 enum plane plane, enum pipe pipe)
1811{
1812 int reg;
1813 u32 val;
1814
1815 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816 assert_pipe_enabled(dev_priv, pipe);
1817
1818 reg = DSPCNTR(plane);
1819 val = I915_READ(reg);
00d70b15
CW		 1820 if (val & DISPLAY_PLANE_ENABLE)
1821 return;
1822
1823 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1824 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1825 intel_wait_for_vblank(dev_priv->dev, pipe);
1826}
1827
b24e7179
JB		 1828/**
1829 * intel_disable_plane - disable a display plane
1830 * @dev_priv: i915 private structure
1831 * @plane: plane to disable
1832 * @pipe: pipe consuming the data
1833 *
1834 * Disable @plane; should be an independent operation.
1835 */
1836static void intel_disable_plane(struct drm_i915_private *dev_priv,
1837 enum plane plane, enum pipe pipe)
1838{
1839 int reg;
1840 u32 val;
1841
1842 reg = DSPCNTR(plane);
1843 val = I915_READ(reg);
00d70b15
CW		 1844 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1845 return;
1846
1847 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1848 intel_flush_display_plane(dev_priv, plane);
1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1850}
1851
693db184
CW		 1852static bool need_vtd_wa(struct drm_device *dev)
1853{
1854#ifdef CONFIG_INTEL_IOMMU
1855 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1856 return true;
1857#endif
1858 return false;
1859}
1860
127bd2ac 1861int
48b956c5 1862intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1863 struct drm_i915_gem_object *obj,
919926ae 1864 struct intel_ring_buffer *pipelined)
6b95a207 1865{
ce453d81 1866 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1867 u32 alignment;
1868 int ret;
1869
05394f39 1870 switch (obj->tiling_mode) {
6b95a207 1871 case I915_TILING_NONE:
534843da
CW		 1872 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1873 alignment = 128 * 1024;
a6c45cf0 1874 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1875 alignment = 4 * 1024;
1876 else
1877 alignment = 64 * 1024;
6b95a207
KH		 1878 break;
1879 case I915_TILING_X:
1880 /* pin() will align the object as required by fence */
1881 alignment = 0;
1882 break;
1883 case I915_TILING_Y:
8bb6e959
DV		 1884 /* Despite that we check this in framebuffer_init userspace can
1885 * screw us over and change the tiling after the fact. Only
1886 * pinned buffers can't change their tiling. */
1887 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1888 return -EINVAL;
1889 default:
1890 BUG();
1891 }
1892
693db184
CW		 1893 /* Note that the w/a also requires 64 PTE of padding following the
1894 * bo. We currently fill all unused PTE with the shadow page and so
1895 * we should always have valid PTE following the scanout preventing
1896 * the VT-d warning.
1897 */
1898 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1899 alignment = 256 * 1024;
1900
ce453d81 1901 dev_priv->mm.interruptible = false;
2da3b9b9 1902 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1903 if (ret)
ce453d81 1904 goto err_interruptible;
6b95a207
KH		 1905
1906 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907 * fence, whereas 965+ only requires a fence if using
1908 * framebuffer compression. For simplicity, we always install
1909 * a fence as the cost is not that onerous.
1910 */
06d98131 1911 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1912 if (ret)
1913 goto err_unpin;
1690e1eb 1914
9a5a53b3 1915 i915_gem_object_pin_fence(obj);
6b95a207 1916
ce453d81 1917 dev_priv->mm.interruptible = true;
6b95a207 1918 return 0;
48b956c5
CW		 1919
1920err_unpin:
cc98b413 1921 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1922err_interruptible:
1923 dev_priv->mm.interruptible = true;
48b956c5 1924 return ret;
6b95a207
KH		 1925}
1926
1690e1eb
CW		 1927void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1928{
1929 i915_gem_object_unpin_fence(obj);
cc98b413 1930 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1931}
1932
c2c75131
DV		 1933/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934 * is assumed to be a power-of-two. */
bc752862
CW		 1935unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1936 unsigned int tiling_mode,
1937 unsigned int cpp,
1938 unsigned int pitch)
c2c75131 1939{
bc752862
CW		 1940 if (tiling_mode != I915_TILING_NONE) {
1941 unsigned int tile_rows, tiles;
c2c75131 1942
bc752862
CW		 1943 tile_rows = *y / 8;
1944 *y %= 8;
c2c75131 1945
bc752862
CW		 1946 tiles = *x / (512/cpp);
1947 *x %= 512/cpp;
1948
1949 return tile_rows * pitch * 8 + tiles * 4096;
1950 } else {
1951 unsigned int offset;
1952
1953 offset = *y * pitch + *x * cpp;
1954 *y = 0;
1955 *x = (offset & 4095) / cpp;
1956 return offset & -4096;
1957 }
c2c75131
DV		 1958}
1959
17638cd6
JB		 1960static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1961 int x, int y)
81255565
JB		 1962{
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
05394f39 1967 struct drm_i915_gem_object *obj;
81255565 1968 int plane = intel_crtc->plane;
e506a0c6 1969 unsigned long linear_offset;
81255565 1970 u32 dspcntr;
5eddb70b 1971 u32 reg;
81255565
JB		 1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
1976 break;
1977 default:
84f44ce7 1978 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1979 return -EINVAL;
1980 }
1981
1982 intel_fb = to_intel_framebuffer(fb);
1983 obj = intel_fb->obj;
81255565 1984
5eddb70b
CW		 1985 reg = DSPCNTR(plane);
1986 dspcntr = I915_READ(reg);
81255565
JB		 1987 /* Mask out pixel format bits in case we change it */
1988 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1989 switch (fb->pixel_format) {
1990 case DRM_FORMAT_C8:
81255565
JB		 1991 dspcntr |= DISPPLANE_8BPP;
1992 break;
57779d06
VS		 1993 case DRM_FORMAT_XRGB1555:
1994 case DRM_FORMAT_ARGB1555:
1995 dspcntr |= DISPPLANE_BGRX555;
81255565 1996 break;
57779d06
VS		 1997 case DRM_FORMAT_RGB565:
1998 dspcntr |= DISPPLANE_BGRX565;
1999 break;
2000 case DRM_FORMAT_XRGB8888:
2001 case DRM_FORMAT_ARGB8888:
2002 dspcntr |= DISPPLANE_BGRX888;
2003 break;
2004 case DRM_FORMAT_XBGR8888:
2005 case DRM_FORMAT_ABGR8888:
2006 dspcntr |= DISPPLANE_RGBX888;
2007 break;
2008 case DRM_FORMAT_XRGB2101010:
2009 case DRM_FORMAT_ARGB2101010:
2010 dspcntr |= DISPPLANE_BGRX101010;
2011 break;
2012 case DRM_FORMAT_XBGR2101010:
2013 case DRM_FORMAT_ABGR2101010:
2014 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2015 break;
2016 default:
baba133a 2017 BUG();
81255565 2018 }
57779d06 2019
a6c45cf0 2020 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2021 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2022 dspcntr |= DISPPLANE_TILED;
2023 else
2024 dspcntr &= ~DISPPLANE_TILED;
2025 }
2026
de1aa629
VS		 2027 if (IS_G4X(dev))
2028 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2029
5eddb70b 2030 I915_WRITE(reg, dspcntr);
81255565 2031
e506a0c6 2032 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2033
c2c75131
DV		 2034 if (INTEL_INFO(dev)->gen >= 4) {
2035 intel_crtc->dspaddr_offset =
bc752862
CW		 2036 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2037 fb->bits_per_pixel / 8,
2038 fb->pitches[0]);
c2c75131
DV		 2039 linear_offset -= intel_crtc->dspaddr_offset;
2040 } else {
e506a0c6 2041 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2042 }
e506a0c6 2043
f343c5f6
BW		 2044 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2046 fb->pitches[0]);
01f2c773 2047 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2048 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2049 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2050 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2051 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2052 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2053 } else
f343c5f6 2054 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2055 POSTING_READ(reg);
81255565 2056
17638cd6
JB		 2057 return 0;
2058}
2059
2060static int ironlake_update_plane(struct drm_crtc *crtc,
2061 struct drm_framebuffer *fb, int x, int y)
2062{
2063 struct drm_device *dev = crtc->dev;
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2066 struct intel_framebuffer *intel_fb;
2067 struct drm_i915_gem_object *obj;
2068 int plane = intel_crtc->plane;
e506a0c6 2069 unsigned long linear_offset;
17638cd6
JB		 2070 u32 dspcntr;
2071 u32 reg;
2072
2073 switch (plane) {
2074 case 0:
2075 case 1:
27f8227b 2076 case 2:
17638cd6
JB		 2077 break;
2078 default:
84f44ce7 2079 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2080 return -EINVAL;
2081 }
2082
2083 intel_fb = to_intel_framebuffer(fb);
2084 obj = intel_fb->obj;
2085
2086 reg = DSPCNTR(plane);
2087 dspcntr = I915_READ(reg);
2088 /* Mask out pixel format bits in case we change it */
2089 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2090 switch (fb->pixel_format) {
2091 case DRM_FORMAT_C8:
17638cd6
JB		 2092 dspcntr |= DISPPLANE_8BPP;
2093 break;
57779d06
VS		 2094 case DRM_FORMAT_RGB565:
2095 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2096 break;
57779d06
VS		 2097 case DRM_FORMAT_XRGB8888:
2098 case DRM_FORMAT_ARGB8888:
2099 dspcntr |= DISPPLANE_BGRX888;
2100 break;
2101 case DRM_FORMAT_XBGR8888:
2102 case DRM_FORMAT_ABGR8888:
2103 dspcntr |= DISPPLANE_RGBX888;
2104 break;
2105 case DRM_FORMAT_XRGB2101010:
2106 case DRM_FORMAT_ARGB2101010:
2107 dspcntr |= DISPPLANE_BGRX101010;
2108 break;
2109 case DRM_FORMAT_XBGR2101010:
2110 case DRM_FORMAT_ABGR2101010:
2111 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2112 break;
2113 default:
baba133a 2114 BUG();
17638cd6
JB		 2115 }
2116
2117 if (obj->tiling_mode != I915_TILING_NONE)
2118 dspcntr |= DISPPLANE_TILED;
2119 else
2120 dspcntr &= ~DISPPLANE_TILED;
2121
1f5d76db
PZ		 2122 if (IS_HASWELL(dev))
2123 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2124 else
2125 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2126
2127 I915_WRITE(reg, dspcntr);
2128
e506a0c6 2129 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2130 intel_crtc->dspaddr_offset =
bc752862
CW		 2131 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2132 fb->bits_per_pixel / 8,
2133 fb->pitches[0]);
c2c75131 2134 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2135
f343c5f6
BW		 2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2138 fb->pitches[0]);
01f2c773 2139 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2140 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2141 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2142 if (IS_HASWELL(dev)) {
2143 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2144 } else {
2145 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2146 I915_WRITE(DSPLINOFF(plane), linear_offset);
2147 }
17638cd6
JB		 2148 POSTING_READ(reg);
2149
2150 return 0;
2151}
2152
2153/* Assume fb object is pinned & idle & fenced and just update base pointers */
2154static int
2155intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2156 int x, int y, enum mode_set_atomic state)
2157{
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2160
6b8e6ed0
CW		 2161 if (dev_priv->display.disable_fbc)
2162 dev_priv->display.disable_fbc(dev);
3dec0095 2163 intel_increase_pllclock(crtc);
81255565 2164
6b8e6ed0 2165 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2166}
2167
96a02917
VS		 2168void intel_display_handle_reset(struct drm_device *dev)
2169{
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 struct drm_crtc *crtc;
2172
2173 /*
2174 * Flips in the rings have been nuked by the reset,
2175 * so complete all pending flips so that user space
2176 * will get its events and not get stuck.
2177 *
2178 * Also update the base address of all primary
2179 * planes to the the last fb to make sure we're
2180 * showing the correct fb after a reset.
2181 *
2182 * Need to make two loops over the crtcs so that we
2183 * don't try to grab a crtc mutex before the
2184 * pending_flip_queue really got woken up.
2185 */
2186
2187 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2189 enum plane plane = intel_crtc->plane;
2190
2191 intel_prepare_page_flip(dev, plane);
2192 intel_finish_page_flip_plane(dev, plane);
2193 }
2194
2195 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198 mutex_lock(&crtc->mutex);
2199 if (intel_crtc->active)
2200 dev_priv->display.update_plane(crtc, crtc->fb,
2201 crtc->x, crtc->y);
2202 mutex_unlock(&crtc->mutex);
2203 }
2204}
2205
14667a4b
CW		 2206static int
2207intel_finish_fb(struct drm_framebuffer *old_fb)
2208{
2209 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2210 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2211 bool was_interruptible = dev_priv->mm.interruptible;
2212 int ret;
2213
14667a4b
CW		 2214 /* Big Hammer, we also need to ensure that any pending
2215 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216 * current scanout is retired before unpinning the old
2217 * framebuffer.
2218 *
2219 * This should only fail upon a hung GPU, in which case we
2220 * can safely continue.
2221 */
2222 dev_priv->mm.interruptible = false;
2223 ret = i915_gem_object_finish_gpu(obj);
2224 dev_priv->mm.interruptible = was_interruptible;
2225
2226 return ret;
2227}
2228
198598d0
VS		 2229static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2230{
2231 struct drm_device *dev = crtc->dev;
2232 struct drm_i915_master_private *master_priv;
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 if (!dev->primary->master)
2236 return;
2237
2238 master_priv = dev->primary->master->driver_priv;
2239 if (!master_priv->sarea_priv)
2240 return;
2241
2242 switch (intel_crtc->pipe) {
2243 case 0:
2244 master_priv->sarea_priv->pipeA_x = x;
2245 master_priv->sarea_priv->pipeA_y = y;
2246 break;
2247 case 1:
2248 master_priv->sarea_priv->pipeB_x = x;
2249 master_priv->sarea_priv->pipeB_y = y;
2250 break;
2251 default:
2252 break;
2253 }
2254}
2255
5c3b82e2 2256static int
3c4fdcfb 2257intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2258 struct drm_framebuffer *fb)
79e53945
JB		 2259{
2260 struct drm_device *dev = crtc->dev;
6b8e6ed0 2261 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2263 struct drm_framebuffer *old_fb;
5c3b82e2 2264 int ret;
79e53945
JB		 2265
2266 /* no fb bound */
94352cf9 2267 if (!fb) {
a5071c2f 2268 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2269 return 0;
2270 }
2271
7eb552ae 2272 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2273 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274 plane_name(intel_crtc->plane),
2275 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2276 return -EINVAL;
79e53945
JB		 2277 }
2278
5c3b82e2 2279 mutex_lock(&dev->struct_mutex);
265db958 2280 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2281 to_intel_framebuffer(fb)->obj,
919926ae 2282 NULL);
5c3b82e2
CW		 2283 if (ret != 0) {
2284 mutex_unlock(&dev->struct_mutex);
a5071c2f 2285 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2286 return ret;
2287 }
79e53945 2288
4d6a3e63
JB		 2289 /* Update pipe size and adjust fitter if needed */
2290 if (i915_fastboot) {
2291 I915_WRITE(PIPESRC(intel_crtc->pipe),
2292 ((crtc->mode.hdisplay - 1) << 16) |
2293 (crtc->mode.vdisplay - 1));
fd4daa9c 2294 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2295 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2296 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2297 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2298 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2299 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2300 }
2301 }
2302
94352cf9 2303 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2304 if (ret) {
94352cf9 2305 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2306 mutex_unlock(&dev->struct_mutex);
a5071c2f 2307 DRM_ERROR("failed to update base address\n");
4e6cfefc 2308 return ret;
79e53945 2309 }
3c4fdcfb 2310
94352cf9
DV		 2311 old_fb = crtc->fb;
2312 crtc->fb = fb;
6c4c86f5
DV		 2313 crtc->x = x;
2314 crtc->y = y;
94352cf9 2315
b7f1de28 2316 if (old_fb) {
d7697eea
DV		 2317 if (intel_crtc->active && old_fb != fb)
2318 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2319 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2320 }
652c393a 2321
6b8e6ed0 2322 intel_update_fbc(dev);
4906557e 2323 intel_edp_psr_update(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
1e833f40
DV		 2372static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373{
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375}
2376
01a415fd
DV		 2377static void ivb_modeset_global_resources(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
1e833f40
DV		 2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
8db9d77b
ZW		 2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
0fc932b8 2410 int plane = intel_crtc->plane;
5eddb70b 2411 u32 reg, temp, tries;
8db9d77b 2412
0fc932b8
JB		 2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
e1a44743
AJ		 2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
5eddb70b
CW		 2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
e1a44743
AJ		 2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
e1a44743
AJ		 2425 udelay(150);
2426
8db9d77b 2427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
627eb5a3
DV		 2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
8db9d77b
ZW		 2443 udelay(150);
2444
5b2adf89 2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 POSTING_READ(reg);
2478 udelay(150);
8db9d77b 2479
5eddb70b 2480 reg = FDI_RX_IIR(pipe);
e1a44743 2481 for (tries = 0; tries < 5; tries++) {
5eddb70b 2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
8db9d77b 2490 }
e1a44743 2491 if (tries == 5)
5eddb70b 2492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2493
2494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2495
8db9d77b
ZW		 2496}
2497
0206e353 2498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
fa37d39e 2512 u32 reg, temp, i, retry;
8db9d77b 2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
e1a44743
AJ		 2523 udelay(150);
2524
8db9d77b 2525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
627eb5a3
DV		 2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2536
d74cf324
DV		 2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
0206e353 2554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(500);
2563
fa37d39e
SP		 2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
8db9d77b 2574 }
fa37d39e
SP		 2575 if (retry < 5)
2576 break;
8db9d77b
ZW		 2577 }
2578 if (i == 4)
5eddb70b 2579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2580
2581 /* Train 2 */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
5eddb70b 2591 I915_WRITE(reg, temp);
8db9d77b 2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
357555c0
JB		 2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
139ccd3f 2644 u32 reg, temp, i, j;
357555c0
JB		 2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
01a415fd
DV		 2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
139ccd3f
JB		 2660 /* Try each vswing and preemphasis setting twice before moving on */
2661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2662 /* disable first in case we need to retry */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp &= ~FDI_TX_ENABLE;
2667 I915_WRITE(reg, temp);
357555c0 2668
139ccd3f
JB		 2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp &= ~FDI_RX_ENABLE;
2674 I915_WRITE(reg, temp);
357555c0 2675
139ccd3f 2676 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
139ccd3f
JB		 2679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2683 temp |= snb_b_fdi_train_param[j/2];
2684 temp |= FDI_COMPOSITE_SYNC;
2685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2686
139ccd3f
JB		 2687 I915_WRITE(FDI_RX_MISC(pipe),
2688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2689
139ccd3f 2690 reg = FDI_RX_CTL(pipe);
357555c0 2691 temp = I915_READ(reg);
139ccd3f
JB		 2692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2693 temp |= FDI_COMPOSITE_SYNC;
2694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2695
139ccd3f
JB		 2696 POSTING_READ(reg);
2697 udelay(1); /* should be 0.5us */
357555c0 2698
139ccd3f
JB		 2699 for (i = 0; i < 4; i++) {
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2703
139ccd3f
JB		 2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2708 i);
2709 break;
2710 }
2711 udelay(1); /* should be 0.5us */
2712 }
2713 if (i == 4) {
2714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2715 continue;
2716 }
357555c0 2717
139ccd3f 2718 /* Train 2 */
357555c0
JB		 2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
139ccd3f
JB		 2721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2723 I915_WRITE(reg, temp);
2724
2725 reg = FDI_RX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2729 I915_WRITE(reg, temp);
2730
2731 POSTING_READ(reg);
139ccd3f 2732 udelay(2); /* should be 1.5us */
357555c0 2733
139ccd3f
JB		 2734 for (i = 0; i < 4; i++) {
2735 reg = FDI_RX_IIR(pipe);
2736 temp = I915_READ(reg);
2737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2738
139ccd3f
JB		 2739 if (temp & FDI_RX_SYMBOL_LOCK ||
2740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2743 i);
2744 goto train_done;
2745 }
2746 udelay(2); /* should be 1.5us */
357555c0 2747 }
139ccd3f
JB		 2748 if (i == 4)
2749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2750 }
357555c0 2751
139ccd3f 2752train_done:
357555c0
JB		 2753 DRM_DEBUG_KMS("FDI train done.\n");
2754}
2755
88cefb6c 2756static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2757{
88cefb6c 2758 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2759 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2760 int pipe = intel_crtc->pipe;
5eddb70b 2761 u32 reg, temp;
79e53945 2762
c64e311e 2763
c98e9dcf 2764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
627eb5a3
DV		 2767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2771
2772 POSTING_READ(reg);
c98e9dcf
JB		 2773 udelay(200);
2774
2775 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2776 temp = I915_READ(reg);
2777 I915_WRITE(reg, temp | FDI_PCDCLK);
2778
2779 POSTING_READ(reg);
c98e9dcf
JB		 2780 udelay(200);
2781
20749730
PZ		 2782 /* Enable CPU FDI TX PLL, always on for Ironlake */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2787
20749730
PZ		 2788 POSTING_READ(reg);
2789 udelay(100);
6be4a607 2790 }
0e23b99d
JB		 2791}
2792
88cefb6c
DV		 2793static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2794{
2795 struct drm_device *dev = intel_crtc->base.dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 int pipe = intel_crtc->pipe;
2798 u32 reg, temp;
2799
2800 /* Switch from PCDclk to Rawclk */
2801 reg = FDI_RX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2804
2805 /* Disable CPU FDI TX PLL */
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2809
2810 POSTING_READ(reg);
2811 udelay(100);
2812
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2816
2817 /* Wait for the clocks to turn off. */
2818 POSTING_READ(reg);
2819 udelay(100);
2820}
2821
0fc932b8
JB		 2822static void ironlake_fdi_disable(struct drm_crtc *crtc)
2823{
2824 struct drm_device *dev = crtc->dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827 int pipe = intel_crtc->pipe;
2828 u32 reg, temp;
2829
2830 /* disable CPU FDI tx and PCH FDI rx */
2831 reg = FDI_TX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2834 POSTING_READ(reg);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 temp &= ~(0x7 << 16);
dfd07d72 2839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2841
2842 POSTING_READ(reg);
2843 udelay(100);
2844
2845 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2846 if (HAS_PCH_IBX(dev)) {
2847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2848 }
0fc932b8
JB		 2849
2850 /* still set train pattern 1 */
2851 reg = FDI_TX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 I915_WRITE(reg, temp);
2856
2857 reg = FDI_RX_CTL(pipe);
2858 temp = I915_READ(reg);
2859 if (HAS_PCH_CPT(dev)) {
2860 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2861 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2862 } else {
2863 temp &= ~FDI_LINK_TRAIN_NONE;
2864 temp |= FDI_LINK_TRAIN_PATTERN_1;
2865 }
2866 /* BPC in FDI rx is consistent with that in PIPECONF */
2867 temp &= ~(0x07 << 16);
dfd07d72 2868 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2869 I915_WRITE(reg, temp);
2870
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
5bb61643
CW		 2875static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2880 unsigned long flags;
2881 bool pending;
2882
10d83730
VS		 2883 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2884 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2885 return false;
2886
2887 spin_lock_irqsave(&dev->event_lock, flags);
2888 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2889 spin_unlock_irqrestore(&dev->event_lock, flags);
2890
2891 return pending;
2892}
2893
e6c3a2a6
CW		 2894static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2895{
0f91128d 2896 struct drm_device *dev = crtc->dev;
5bb61643 2897 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2898
2899 if (crtc->fb == NULL)
2900 return;
2901
2c10d571
DV		 2902 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2903
5bb61643
CW		 2904 wait_event(dev_priv->pending_flip_queue,
2905 !intel_crtc_has_pending_flip(crtc));
2906
0f91128d
CW		 2907 mutex_lock(&dev->struct_mutex);
2908 intel_finish_fb(crtc->fb);
2909 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2910}
2911
e615efe4
ED		 2912/* Program iCLKIP clock to the desired frequency */
2913static void lpt_program_iclkip(struct drm_crtc *crtc)
2914{
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2917 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2918 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2919 u32 temp;
2920
09153000
DV		 2921 mutex_lock(&dev_priv->dpio_lock);
2922
e615efe4
ED		 2923 /* It is necessary to ungate the pixclk gate prior to programming
2924 * the divisors, and gate it back when it is done.
2925 */
2926 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2927
2928 /* Disable SSCCTL */
2929 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2930 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2931 SBI_SSCCTL_DISABLE,
2932 SBI_ICLK);
e615efe4
ED		 2933
2934 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2935 if (clock == 20000) {
e615efe4
ED		 2936 auxdiv = 1;
2937 divsel = 0x41;
2938 phaseinc = 0x20;
2939 } else {
2940 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2941 * but the adjusted_mode->crtc_clock in in KHz. To get the
2942 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2943 * convert the virtual clock precision to KHz here for higher
2944 * precision.
2945 */
2946 u32 iclk_virtual_root_freq = 172800 * 1000;
2947 u32 iclk_pi_range = 64;
2948 u32 desired_divisor, msb_divisor_value, pi_value;
2949
12d7ceed 2950 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2951 msb_divisor_value = desired_divisor / iclk_pi_range;
2952 pi_value = desired_divisor % iclk_pi_range;
2953
2954 auxdiv = 0;
2955 divsel = msb_divisor_value - 2;
2956 phaseinc = pi_value;
2957 }
2958
2959 /* This should not happen with any sane values */
2960 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2961 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2962 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2963 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2964
2965 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2966 clock,
e615efe4
ED		 2967 auxdiv,
2968 divsel,
2969 phasedir,
2970 phaseinc);
2971
2972 /* Program SSCDIVINTPHASE6 */
988d6ee8 2973 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2974 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2975 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2976 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2977 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2978 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2979 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2980 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2981
2982 /* Program SSCAUXDIV */
988d6ee8 2983 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2984 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2986 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2987
2988 /* Enable modulator and associated divider */
988d6ee8 2989 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2990 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2991 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2992
2993 /* Wait for initialization time */
2994 udelay(24);
2995
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2997
2998 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2999}
3000
275f01b2
DV		 3001static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3002 enum pipe pch_transcoder)
3003{
3004 struct drm_device *dev = crtc->base.dev;
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3007
3008 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3009 I915_READ(HTOTAL(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3011 I915_READ(HBLANK(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3013 I915_READ(HSYNC(cpu_transcoder)));
3014
3015 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3016 I915_READ(VTOTAL(cpu_transcoder)));
3017 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3018 I915_READ(VBLANK(cpu_transcoder)));
3019 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3020 I915_READ(VSYNC(cpu_transcoder)));
3021 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3022 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3023}
3024
f67a559d
JB		 3025/*
3026 * Enable PCH resources required for PCH ports:
3027 * - PCH PLLs
3028 * - FDI training & RX/TX
3029 * - update transcoder timings
3030 * - DP transcoding bits
3031 * - transcoder
3032 */
3033static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038 int pipe = intel_crtc->pipe;
ee7b9f93 3039 u32 reg, temp;
2c07245f 3040
ab9412ba 3041 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3042
cd986abb
DV		 3043 /* Write the TU size bits before fdi link training, so that error
3044 * detection works. */
3045 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3046 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3047
c98e9dcf 3048 /* For PCH output, training FDI link */
674cf967 3049 dev_priv->display.fdi_link_train(crtc);
2c07245f 3050
3ad8a208
DV		 3051 /* We need to program the right clock selection before writing the pixel
3052 * mutliplier into the DPLL. */
303b81e0 3053 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3054 u32 sel;
4b645f14 3055
c98e9dcf 3056 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3057 temp |= TRANS_DPLL_ENABLE(pipe);
3058 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3059 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3060 temp |= sel;
3061 else
3062 temp &= ~sel;
c98e9dcf 3063 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3064 }
5eddb70b 3065
3ad8a208
DV		 3066 /* XXX: pch pll's can be enabled any time before we enable the PCH
3067 * transcoder, and we actually should do this to not upset any PCH
3068 * transcoder that already use the clock when we share it.
3069 *
3070 * Note that enable_shared_dpll tries to do the right thing, but
3071 * get_shared_dpll unconditionally resets the pll - we need that to have
3072 * the right LVDS enable sequence. */
3073 ironlake_enable_shared_dpll(intel_crtc);
3074
d9b6cb56
JB		 3075 /* set transcoder timing, panel must allow it */
3076 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3077 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3078
303b81e0 3079 intel_fdi_normal_train(crtc);
5e84e1a4 3080
c98e9dcf
JB		 3081 /* For PCH DP, enable TRANS_DP_CTL */
3082 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3083 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3085 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3086 reg = TRANS_DP_CTL(pipe);
3087 temp = I915_READ(reg);
3088 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3089 TRANS_DP_SYNC_MASK |
3090 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3091 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092 TRANS_DP_ENH_FRAMING);
9325c9f0 3093 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3094
3095 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3096 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3097 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3098 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3099
3100 switch (intel_trans_dp_port_sel(crtc)) {
3101 case PCH_DP_B:
5eddb70b 3102 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3103 break;
3104 case PCH_DP_C:
5eddb70b 3105 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3106 break;
3107 case PCH_DP_D:
5eddb70b 3108 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3109 break;
3110 default:
e95d41e1 3111 BUG();
32f9d658 3112 }
2c07245f 3113
5eddb70b 3114 I915_WRITE(reg, temp);
6be4a607 3115 }
b52eb4dc 3116
b8a4f404 3117 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3118}
3119
1507e5bd
PZ		 3120static void lpt_pch_enable(struct drm_crtc *crtc)
3121{
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3125 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3126
ab9412ba 3127 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3128
8c52b5e8 3129 lpt_program_iclkip(crtc);
1507e5bd 3130
0540e488 3131 /* Set transcoder timing. */
275f01b2 3132 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3133
937bb610 3134 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3135}
3136
e2b78267 3137static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3138{
e2b78267 3139 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3140
3141 if (pll == NULL)
3142 return;
3143
3144 if (pll->refcount == 0) {
46edb027 3145 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3146 return;
3147 }
3148
f4a091c7
DV		 3149 if (--pll->refcount == 0) {
3150 WARN_ON(pll->on);
3151 WARN_ON(pll->active);
3152 }
3153
a43f6e0f 3154 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3155}
3156
b89a1d39 3157static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3158{
e2b78267
DV		 3159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3160 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3161 enum intel_dpll_id i;
ee7b9f93 3162
ee7b9f93 3163 if (pll) {
46edb027
DV		 3164 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165 crtc->base.base.id, pll->name);
e2b78267 3166 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3167 }
3168
98b6bd99
DV		 3169 if (HAS_PCH_IBX(dev_priv->dev)) {
3170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3171 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3172 pll = &dev_priv->shared_dplls[i];
98b6bd99 3173
46edb027
DV		 3174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175 crtc->base.base.id, pll->name);
98b6bd99
DV		 3176
3177 goto found;
3178 }
3179
e72f9fbf
DV		 3180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3182
3183 /* Only want to check enabled timings first */
3184 if (pll->refcount == 0)
3185 continue;
3186
b89a1d39
DV		 3187 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3188 sizeof(pll->hw_state)) == 0) {
46edb027 3189 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3190 crtc->base.base.id,
46edb027 3191 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3192
3193 goto found;
3194 }
3195 }
3196
3197 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3198 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3199 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3200 if (pll->refcount == 0) {
46edb027
DV		 3201 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3203 goto found;
3204 }
3205 }
3206
3207 return NULL;
3208
3209found:
a43f6e0f 3210 crtc->config.shared_dpll = i;
46edb027
DV		 3211 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3212 pipe_name(crtc->pipe));
ee7b9f93 3213
cdbd2316 3214 if (pll->active == 0) {
66e985c0
DV		 3215 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3216 sizeof(pll->hw_state));
3217
46edb027 3218 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3219 WARN_ON(pll->on);
e9d6944e 3220 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3221
15bdd4cf 3222 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3223 }
3224 pll->refcount++;
e04c7350 3225
ee7b9f93
JB		 3226 return pll;
3227}
3228
a1520318 3229static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3230{
3231 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3232 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3233 u32 temp;
3234
3235 temp = I915_READ(dslreg);
3236 udelay(500);
3237 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3238 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3239 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3240 }
3241}
3242
b074cec8
JB		 3243static void ironlake_pfit_enable(struct intel_crtc *crtc)
3244{
3245 struct drm_device *dev = crtc->base.dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 int pipe = crtc->pipe;
3248
fd4daa9c 3249 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3250 /* Force use of hard-coded filter coefficients
3251 * as some pre-programmed values are broken,
3252 * e.g. x201.
3253 */
3254 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3256 PF_PIPE_SEL_IVB(pipe));
3257 else
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3259 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3260 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3261 }
3262}
3263
bb53d4ae
VS		 3264static void intel_enable_planes(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3268 struct intel_plane *intel_plane;
3269
3270 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3271 if (intel_plane->pipe == pipe)
3272 intel_plane_restore(&intel_plane->base);
3273}
3274
3275static void intel_disable_planes(struct drm_crtc *crtc)
3276{
3277 struct drm_device *dev = crtc->dev;
3278 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3279 struct intel_plane *intel_plane;
3280
3281 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3282 if (intel_plane->pipe == pipe)
3283 intel_plane_disable(&intel_plane->base);
3284}
3285
d77e4531
PZ		 3286static void hsw_enable_ips(struct intel_crtc *crtc)
3287{
3288 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3289
3290 if (!crtc->config.ips_enabled)
3291 return;
3292
3293 /* We can only enable IPS after we enable a plane and wait for a vblank.
3294 * We guarantee that the plane is enabled by calling intel_enable_ips
3295 * only after intel_enable_plane. And intel_enable_plane already waits
3296 * for a vblank, so all we need to do here is to enable the IPS bit. */
3297 assert_plane_enabled(dev_priv, crtc->plane);
3298 I915_WRITE(IPS_CTL, IPS_ENABLE);
3299}
3300
3301static void hsw_disable_ips(struct intel_crtc *crtc)
3302{
3303 struct drm_device *dev = crtc->base.dev;
3304 struct drm_i915_private *dev_priv = dev->dev_private;
3305
3306 if (!crtc->config.ips_enabled)
3307 return;
3308
3309 assert_plane_enabled(dev_priv, crtc->plane);
3310 I915_WRITE(IPS_CTL, 0);
3311 POSTING_READ(IPS_CTL);
3312
3313 /* We need to wait for a vblank before we can disable the plane. */
3314 intel_wait_for_vblank(dev, crtc->pipe);
3315}
3316
3317/** Loads the palette/gamma unit for the CRTC with the prepared values */
3318static void intel_crtc_load_lut(struct drm_crtc *crtc)
3319{
3320 struct drm_device *dev = crtc->dev;
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3323 enum pipe pipe = intel_crtc->pipe;
3324 int palreg = PALETTE(pipe);
3325 int i;
3326 bool reenable_ips = false;
3327
3328 /* The clocks have to be on to load the palette. */
3329 if (!crtc->enabled || !intel_crtc->active)
3330 return;
3331
3332 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3333 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3334 assert_dsi_pll_enabled(dev_priv);
3335 else
3336 assert_pll_enabled(dev_priv, pipe);
3337 }
3338
3339 /* use legacy palette for Ironlake */
3340 if (HAS_PCH_SPLIT(dev))
3341 palreg = LGC_PALETTE(pipe);
3342
3343 /* Workaround : Do not read or write the pipe palette/gamma data while
3344 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3345 */
3346 if (intel_crtc->config.ips_enabled &&
3347 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3348 GAMMA_MODE_MODE_SPLIT)) {
3349 hsw_disable_ips(intel_crtc);
3350 reenable_ips = true;
3351 }
3352
3353 for (i = 0; i < 256; i++) {
3354 I915_WRITE(palreg + 4 * i,
3355 (intel_crtc->lut_r[i] << 16) |
3356 (intel_crtc->lut_g[i] << 8) |
3357 intel_crtc->lut_b[i]);
3358 }
3359
3360 if (reenable_ips)
3361 hsw_enable_ips(intel_crtc);
3362}
3363
f67a559d
JB		 3364static void ironlake_crtc_enable(struct drm_crtc *crtc)
3365{
3366 struct drm_device *dev = crtc->dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3369 struct intel_encoder *encoder;
f67a559d
JB		 3370 int pipe = intel_crtc->pipe;
3371 int plane = intel_crtc->plane;
f67a559d 3372
08a48469
DV		 3373 WARN_ON(!crtc->enabled);
3374
f67a559d
JB		 3375 if (intel_crtc->active)
3376 return;
3377
3378 intel_crtc->active = true;
8664281b
PZ		 3379
3380 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3381 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3382
f6736a1a 3383 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3384 if (encoder->pre_enable)
3385 encoder->pre_enable(encoder);
f67a559d 3386
5bfe2ac0 3387 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3388 /* Note: FDI PLL enabling _must_ be done before we enable the
3389 * cpu pipes, hence this is separate from all the other fdi/pch
3390 * enabling. */
88cefb6c 3391 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3392 } else {
3393 assert_fdi_tx_disabled(dev_priv, pipe);
3394 assert_fdi_rx_disabled(dev_priv, pipe);
3395 }
f67a559d 3396
b074cec8 3397 ironlake_pfit_enable(intel_crtc);
f67a559d 3398
9c54c0dd
JB		 3399 /*
3400 * On ILK+ LUT must be loaded before the pipe is running but with
3401 * clocks enabled
3402 */
3403 intel_crtc_load_lut(crtc);
3404
f37fcc2a 3405 intel_update_watermarks(crtc);
5bfe2ac0 3406 intel_enable_pipe(dev_priv, pipe,
23538ef1 3407 intel_crtc->config.has_pch_encoder, false);
f67a559d 3408 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3409 intel_enable_planes(crtc);
5c38d48c 3410 intel_crtc_update_cursor(crtc, true);
f67a559d 3411
5bfe2ac0 3412 if (intel_crtc->config.has_pch_encoder)
f67a559d 3413 ironlake_pch_enable(crtc);
c98e9dcf 3414
d1ebd816 3415 mutex_lock(&dev->struct_mutex);
bed4a673 3416 intel_update_fbc(dev);
d1ebd816
BW		 3417 mutex_unlock(&dev->struct_mutex);
3418
fa5c73b1
DV		 3419 for_each_encoder_on_crtc(dev, crtc, encoder)
3420 encoder->enable(encoder);
61b77ddd
DV		 3421
3422 if (HAS_PCH_CPT(dev))
a1520318 3423 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3424
3425 /*
3426 * There seems to be a race in PCH platform hw (at least on some
3427 * outputs) where an enabled pipe still completes any pageflip right
3428 * away (as if the pipe is off) instead of waiting for vblank. As soon
3429 * as the first vblank happend, everything works as expected. Hence just
3430 * wait for one vblank before returning to avoid strange things
3431 * happening.
3432 */
3433 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3434}
3435
42db64ef
PZ		 3436/* IPS only exists on ULT machines and is tied to pipe A. */
3437static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3438{
f5adf94e 3439 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3440}
3441
4f771f10
PZ		 3442static void haswell_crtc_enable(struct drm_crtc *crtc)
3443{
3444 struct drm_device *dev = crtc->dev;
3445 struct drm_i915_private *dev_priv = dev->dev_private;
3446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3447 struct intel_encoder *encoder;
3448 int pipe = intel_crtc->pipe;
3449 int plane = intel_crtc->plane;
4f771f10
PZ		 3450
3451 WARN_ON(!crtc->enabled);
3452
3453 if (intel_crtc->active)
3454 return;
3455
3456 intel_crtc->active = true;
8664281b
PZ		 3457
3458 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3459 if (intel_crtc->config.has_pch_encoder)
3460 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3461
5bfe2ac0 3462 if (intel_crtc->config.has_pch_encoder)
04945641 3463 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3464
3465 for_each_encoder_on_crtc(dev, crtc, encoder)
3466 if (encoder->pre_enable)
3467 encoder->pre_enable(encoder);
3468
1f544388 3469 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3470
b074cec8 3471 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3472
3473 /*
3474 * On ILK+ LUT must be loaded before the pipe is running but with
3475 * clocks enabled
3476 */
3477 intel_crtc_load_lut(crtc);
3478
1f544388 3479 intel_ddi_set_pipe_settings(crtc);
8228c251 3480 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3481
f37fcc2a 3482 intel_update_watermarks(crtc);
5bfe2ac0 3483 intel_enable_pipe(dev_priv, pipe,
23538ef1 3484 intel_crtc->config.has_pch_encoder, false);
4f771f10 3485 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3486 intel_enable_planes(crtc);
5c38d48c 3487 intel_crtc_update_cursor(crtc, true);
4f771f10 3488
42db64ef
PZ		 3489 hsw_enable_ips(intel_crtc);
3490
5bfe2ac0 3491 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3492 lpt_pch_enable(crtc);
4f771f10
PZ		 3493
3494 mutex_lock(&dev->struct_mutex);
3495 intel_update_fbc(dev);
3496 mutex_unlock(&dev->struct_mutex);
3497
8807e55b 3498 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3499 encoder->enable(encoder);
8807e55b
JN		 3500 intel_opregion_notify_encoder(encoder, true);
3501 }
4f771f10 3502
4f771f10
PZ		 3503 /*
3504 * There seems to be a race in PCH platform hw (at least on some
3505 * outputs) where an enabled pipe still completes any pageflip right
3506 * away (as if the pipe is off) instead of waiting for vblank. As soon
3507 * as the first vblank happend, everything works as expected. Hence just
3508 * wait for one vblank before returning to avoid strange things
3509 * happening.
3510 */
3511 intel_wait_for_vblank(dev, intel_crtc->pipe);
3512}
3513
3f8dce3a
DV		 3514static void ironlake_pfit_disable(struct intel_crtc *crtc)
3515{
3516 struct drm_device *dev = crtc->base.dev;
3517 struct drm_i915_private *dev_priv = dev->dev_private;
3518 int pipe = crtc->pipe;
3519
3520 /* To avoid upsetting the power well on haswell only disable the pfit if
3521 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3522 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3523 I915_WRITE(PF_CTL(pipe), 0);
3524 I915_WRITE(PF_WIN_POS(pipe), 0);
3525 I915_WRITE(PF_WIN_SZ(pipe), 0);
3526 }
3527}
3528
6be4a607
JB		 3529static void ironlake_crtc_disable(struct drm_crtc *crtc)
3530{
3531 struct drm_device *dev = crtc->dev;
3532 struct drm_i915_private *dev_priv = dev->dev_private;
3533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3534 struct intel_encoder *encoder;
6be4a607
JB		 3535 int pipe = intel_crtc->pipe;
3536 int plane = intel_crtc->plane;
5eddb70b 3537 u32 reg, temp;
b52eb4dc 3538
ef9c3aee 3539
f7abfe8b
CW		 3540 if (!intel_crtc->active)
3541 return;
3542
ea9d758d
DV		 3543 for_each_encoder_on_crtc(dev, crtc, encoder)
3544 encoder->disable(encoder);
3545
e6c3a2a6 3546 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3547 drm_vblank_off(dev, pipe);
913d8d11 3548
5c3fe8b0 3549 if (dev_priv->fbc.plane == plane)
973d04f9 3550 intel_disable_fbc(dev);
2c07245f 3551
0d5b8c61 3552 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3553 intel_disable_planes(crtc);
0d5b8c61
VS		 3554 intel_disable_plane(dev_priv, plane, pipe);
3555
d925c59a
DV		 3556 if (intel_crtc->config.has_pch_encoder)
3557 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3558
b24e7179 3559 intel_disable_pipe(dev_priv, pipe);
32f9d658 3560
3f8dce3a 3561 ironlake_pfit_disable(intel_crtc);
2c07245f 3562
bf49ec8c
DV		 3563 for_each_encoder_on_crtc(dev, crtc, encoder)
3564 if (encoder->post_disable)
3565 encoder->post_disable(encoder);
2c07245f 3566
d925c59a
DV		 3567 if (intel_crtc->config.has_pch_encoder) {
3568 ironlake_fdi_disable(crtc);
913d8d11 3569
d925c59a
DV		 3570 ironlake_disable_pch_transcoder(dev_priv, pipe);
3571 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3572
d925c59a
DV		 3573 if (HAS_PCH_CPT(dev)) {
3574 /* disable TRANS_DP_CTL */
3575 reg = TRANS_DP_CTL(pipe);
3576 temp = I915_READ(reg);
3577 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3578 TRANS_DP_PORT_SEL_MASK);
3579 temp |= TRANS_DP_PORT_SEL_NONE;
3580 I915_WRITE(reg, temp);
3581
3582 /* disable DPLL_SEL */
3583 temp = I915_READ(PCH_DPLL_SEL);
11887397 3584 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3585 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3586 }
e3421a18 3587
d925c59a 3588 /* disable PCH DPLL */
e72f9fbf 3589 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3590
d925c59a
DV		 3591 ironlake_fdi_pll_disable(intel_crtc);
3592 }
6b383a7f 3593
f7abfe8b 3594 intel_crtc->active = false;
46ba614c 3595 intel_update_watermarks(crtc);
d1ebd816
BW		 3596
3597 mutex_lock(&dev->struct_mutex);
6b383a7f 3598 intel_update_fbc(dev);
d1ebd816 3599 mutex_unlock(&dev->struct_mutex);
6be4a607 3600}
1b3c7a47 3601
4f771f10 3602static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3603{
4f771f10
PZ		 3604 struct drm_device *dev = crtc->dev;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3607 struct intel_encoder *encoder;
3608 int pipe = intel_crtc->pipe;
3609 int plane = intel_crtc->plane;
3b117c8f 3610 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3611
4f771f10
PZ		 3612 if (!intel_crtc->active)
3613 return;
3614
8807e55b
JN		 3615 for_each_encoder_on_crtc(dev, crtc, encoder) {
3616 intel_opregion_notify_encoder(encoder, false);
4f771f10 3617 encoder->disable(encoder);
8807e55b 3618 }
4f771f10
PZ		 3619
3620 intel_crtc_wait_for_pending_flips(crtc);
3621 drm_vblank_off(dev, pipe);
4f771f10 3622
891348b2 3623 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3624 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3625 intel_disable_fbc(dev);
3626
42db64ef
PZ		 3627 hsw_disable_ips(intel_crtc);
3628
0d5b8c61 3629 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3630 intel_disable_planes(crtc);
891348b2
RV		 3631 intel_disable_plane(dev_priv, plane, pipe);
3632
8664281b
PZ		 3633 if (intel_crtc->config.has_pch_encoder)
3634 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3635 intel_disable_pipe(dev_priv, pipe);
3636
ad80a810 3637 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3638
3f8dce3a 3639 ironlake_pfit_disable(intel_crtc);
4f771f10 3640
1f544388 3641 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3642
3643 for_each_encoder_on_crtc(dev, crtc, encoder)
3644 if (encoder->post_disable)
3645 encoder->post_disable(encoder);
3646
88adfff1 3647 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3648 lpt_disable_pch_transcoder(dev_priv);
8664281b 3649 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3650 intel_ddi_fdi_disable(crtc);
83616634 3651 }
4f771f10
PZ		 3652
3653 intel_crtc->active = false;
46ba614c 3654 intel_update_watermarks(crtc);
4f771f10
PZ		 3655
3656 mutex_lock(&dev->struct_mutex);
3657 intel_update_fbc(dev);
3658 mutex_unlock(&dev->struct_mutex);
3659}
3660
ee7b9f93
JB		 3661static void ironlake_crtc_off(struct drm_crtc *crtc)
3662{
3663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3664 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3665}
3666
6441ab5f
PZ		 3667static void haswell_crtc_off(struct drm_crtc *crtc)
3668{
3669 intel_ddi_put_crtc_pll(crtc);
3670}
3671
02e792fb
DV		 3672static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3673{
02e792fb 3674 if (!enable && intel_crtc->overlay) {
23f09ce3 3675 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3676 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3677
23f09ce3 3678 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3679 dev_priv->mm.interruptible = false;
3680 (void) intel_overlay_switch_off(intel_crtc->overlay);
3681 dev_priv->mm.interruptible = true;
23f09ce3 3682 mutex_unlock(&dev->struct_mutex);
02e792fb 3683 }
02e792fb 3684
5dcdbcb0
CW		 3685 /* Let userspace switch the overlay on again. In most cases userspace
3686 * has to recompute where to put it anyway.
3687 */
02e792fb
DV		 3688}
3689
61bc95c1
EE		 3690/**
3691 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3692 * cursor plane briefly if not already running after enabling the display
3693 * plane.
3694 * This workaround avoids occasional blank screens when self refresh is
3695 * enabled.
3696 */
3697static void
3698g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3699{
3700 u32 cntl = I915_READ(CURCNTR(pipe));
3701
3702 if ((cntl & CURSOR_MODE) == 0) {
3703 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3704
3705 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3706 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3707 intel_wait_for_vblank(dev_priv->dev, pipe);
3708 I915_WRITE(CURCNTR(pipe), cntl);
3709 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3710 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3711 }
3712}
3713
2dd24552
JB		 3714static void i9xx_pfit_enable(struct intel_crtc *crtc)
3715{
3716 struct drm_device *dev = crtc->base.dev;
3717 struct drm_i915_private *dev_priv = dev->dev_private;
3718 struct intel_crtc_config *pipe_config = &crtc->config;
3719
328d8e82 3720 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3721 return;
3722
2dd24552 3723 /*
c0b03411
DV		 3724 * The panel fitter should only be adjusted whilst the pipe is disabled,
3725 * according to register description and PRM.
2dd24552 3726 */
c0b03411
DV		 3727 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3728 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3729
b074cec8
JB		 3730 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3731 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3732
3733 /* Border color in case we don't scale up to the full screen. Black by
3734 * default, change to something else for debugging. */
3735 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3736}
3737
89b667f8
JB		 3738static void valleyview_crtc_enable(struct drm_crtc *crtc)
3739{
3740 struct drm_device *dev = crtc->dev;
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743 struct intel_encoder *encoder;
3744 int pipe = intel_crtc->pipe;
3745 int plane = intel_crtc->plane;
23538ef1 3746 bool is_dsi;
89b667f8
JB		 3747
3748 WARN_ON(!crtc->enabled);
3749
3750 if (intel_crtc->active)
3751 return;
3752
3753 intel_crtc->active = true;
89b667f8 3754
89b667f8
JB		 3755 for_each_encoder_on_crtc(dev, crtc, encoder)
3756 if (encoder->pre_pll_enable)
3757 encoder->pre_pll_enable(encoder);
3758
23538ef1
JN		 3759 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3760
e9fd1c02
JN		 3761 if (!is_dsi)
3762 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3763
3764 for_each_encoder_on_crtc(dev, crtc, encoder)
3765 if (encoder->pre_enable)
3766 encoder->pre_enable(encoder);
3767
2dd24552
JB		 3768 i9xx_pfit_enable(intel_crtc);
3769
63cbb074
VS		 3770 intel_crtc_load_lut(crtc);
3771
f37fcc2a 3772 intel_update_watermarks(crtc);
23538ef1 3773 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3774 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3775 intel_enable_planes(crtc);
5c38d48c 3776 intel_crtc_update_cursor(crtc, true);
89b667f8 3777
89b667f8 3778 intel_update_fbc(dev);
5004945f
JN		 3779
3780 for_each_encoder_on_crtc(dev, crtc, encoder)
3781 encoder->enable(encoder);
89b667f8
JB		 3782}
3783
0b8765c6 3784static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3785{
3786 struct drm_device *dev = crtc->dev;
79e53945
JB		 3787 struct drm_i915_private *dev_priv = dev->dev_private;
3788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3789 struct intel_encoder *encoder;
79e53945 3790 int pipe = intel_crtc->pipe;
80824003 3791 int plane = intel_crtc->plane;
79e53945 3792
08a48469
DV		 3793 WARN_ON(!crtc->enabled);
3794
f7abfe8b
CW		 3795 if (intel_crtc->active)
3796 return;
3797
3798 intel_crtc->active = true;
6b383a7f 3799
9d6d9f19
MK		 3800 for_each_encoder_on_crtc(dev, crtc, encoder)
3801 if (encoder->pre_enable)
3802 encoder->pre_enable(encoder);
3803
f6736a1a
DV		 3804 i9xx_enable_pll(intel_crtc);
3805
2dd24552
JB		 3806 i9xx_pfit_enable(intel_crtc);
3807
63cbb074
VS		 3808 intel_crtc_load_lut(crtc);
3809
f37fcc2a 3810 intel_update_watermarks(crtc);
23538ef1 3811 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3812 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3813 intel_enable_planes(crtc);
22e407d7 3814 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3815 if (IS_G4X(dev))
3816 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3817 intel_crtc_update_cursor(crtc, true);
79e53945 3818
0b8765c6
JB		 3819 /* Give the overlay scaler a chance to enable if it's on this pipe */
3820 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3821
f440eb13 3822 intel_update_fbc(dev);
ef9c3aee 3823
fa5c73b1
DV		 3824 for_each_encoder_on_crtc(dev, crtc, encoder)
3825 encoder->enable(encoder);
0b8765c6 3826}
79e53945 3827
87476d63
DV		 3828static void i9xx_pfit_disable(struct intel_crtc *crtc)
3829{
3830 struct drm_device *dev = crtc->base.dev;
3831 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3832
328d8e82
DV		 3833 if (!crtc->config.gmch_pfit.control)
3834 return;
87476d63 3835
328d8e82 3836 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3837
328d8e82
DV		 3838 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3839 I915_READ(PFIT_CONTROL));
3840 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3841}
3842
0b8765c6
JB		 3843static void i9xx_crtc_disable(struct drm_crtc *crtc)
3844{
3845 struct drm_device *dev = crtc->dev;
3846 struct drm_i915_private *dev_priv = dev->dev_private;
3847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3848 struct intel_encoder *encoder;
0b8765c6
JB		 3849 int pipe = intel_crtc->pipe;
3850 int plane = intel_crtc->plane;
ef9c3aee 3851
f7abfe8b
CW		 3852 if (!intel_crtc->active)
3853 return;
3854
ea9d758d
DV		 3855 for_each_encoder_on_crtc(dev, crtc, encoder)
3856 encoder->disable(encoder);
3857
0b8765c6 3858 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3859 intel_crtc_wait_for_pending_flips(crtc);
3860 drm_vblank_off(dev, pipe);
0b8765c6 3861
5c3fe8b0 3862 if (dev_priv->fbc.plane == plane)
973d04f9 3863 intel_disable_fbc(dev);
79e53945 3864
0d5b8c61
VS		 3865 intel_crtc_dpms_overlay(intel_crtc, false);
3866 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3867 intel_disable_planes(crtc);
b24e7179 3868 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3869
b24e7179 3870 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3871
87476d63 3872 i9xx_pfit_disable(intel_crtc);
24a1f16d 3873
89b667f8
JB		 3874 for_each_encoder_on_crtc(dev, crtc, encoder)
3875 if (encoder->post_disable)
3876 encoder->post_disable(encoder);
3877
e9fd1c02
JN		 3878 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3879 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3880
f7abfe8b 3881 intel_crtc->active = false;
46ba614c 3882 intel_update_watermarks(crtc);
f37fcc2a 3883
6b383a7f 3884 intel_update_fbc(dev);
0b8765c6
JB		 3885}
3886
ee7b9f93
JB		 3887static void i9xx_crtc_off(struct drm_crtc *crtc)
3888{
3889}
3890
976f8a20
DV		 3891static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3892 bool enabled)
2c07245f
ZW		 3893{
3894 struct drm_device *dev = crtc->dev;
3895 struct drm_i915_master_private *master_priv;
3896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3897 int pipe = intel_crtc->pipe;
79e53945
JB		 3898
3899 if (!dev->primary->master)
3900 return;
3901
3902 master_priv = dev->primary->master->driver_priv;
3903 if (!master_priv->sarea_priv)
3904 return;
3905
79e53945
JB		 3906 switch (pipe) {
3907 case 0:
3908 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3909 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3910 break;
3911 case 1:
3912 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3913 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3914 break;
3915 default:
9db4a9c7 3916 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3917 break;
3918 }
79e53945
JB		 3919}
3920
976f8a20
DV		 3921/**
3922 * Sets the power management mode of the pipe and plane.
3923 */
3924void intel_crtc_update_dpms(struct drm_crtc *crtc)
3925{
3926 struct drm_device *dev = crtc->dev;
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 struct intel_encoder *intel_encoder;
3929 bool enable = false;
3930
3931 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3932 enable |= intel_encoder->connectors_active;
3933
3934 if (enable)
3935 dev_priv->display.crtc_enable(crtc);
3936 else
3937 dev_priv->display.crtc_disable(crtc);
3938
3939 intel_crtc_update_sarea(crtc, enable);
3940}
3941
cdd59983
CW		 3942static void intel_crtc_disable(struct drm_crtc *crtc)
3943{
cdd59983 3944 struct drm_device *dev = crtc->dev;
976f8a20 3945 struct drm_connector *connector;
ee7b9f93 3946 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3948
976f8a20
DV		 3949 /* crtc should still be enabled when we disable it. */
3950 WARN_ON(!crtc->enabled);
3951
3952 dev_priv->display.crtc_disable(crtc);
c77bf565 3953 intel_crtc->eld_vld = false;
976f8a20 3954 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3955 dev_priv->display.off(crtc);
3956
931872fc 3957 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3958 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3959 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3960
3961 if (crtc->fb) {
3962 mutex_lock(&dev->struct_mutex);
1690e1eb 3963 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3964 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3965 crtc->fb = NULL;
3966 }
3967
3968 /* Update computed state. */
3969 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3970 if (!connector->encoder || !connector->encoder->crtc)
3971 continue;
3972
3973 if (connector->encoder->crtc != crtc)
3974 continue;
3975
3976 connector->dpms = DRM_MODE_DPMS_OFF;
3977 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3978 }
3979}
3980
ea5b213a 3981void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3982{
4ef69c7a 3983 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3984
ea5b213a
CW		 3985 drm_encoder_cleanup(encoder);
3986 kfree(intel_encoder);
7e7d76c3
JB		 3987}
3988
9237329d 3989/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3990 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3991 * state of the entire output pipe. */
9237329d 3992static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3993{
5ab432ef
DV		 3994 if (mode == DRM_MODE_DPMS_ON) {
3995 encoder->connectors_active = true;
3996
b2cabb0e 3997 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3998 } else {
3999 encoder->connectors_active = false;
4000
b2cabb0e 4001 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4002 }
79e53945
JB		 4003}
4004
0a91ca29
DV		 4005/* Cross check the actual hw state with our own modeset state tracking (and it's
4006 * internal consistency). */
b980514c 4007static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4008{
0a91ca29
DV		 4009 if (connector->get_hw_state(connector)) {
4010 struct intel_encoder *encoder = connector->encoder;
4011 struct drm_crtc *crtc;
4012 bool encoder_enabled;
4013 enum pipe pipe;
4014
4015 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4016 connector->base.base.id,
4017 drm_get_connector_name(&connector->base));
4018
4019 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4020 "wrong connector dpms state\n");
4021 WARN(connector->base.encoder != &encoder->base,
4022 "active connector not linked to encoder\n");
4023 WARN(!encoder->connectors_active,
4024 "encoder->connectors_active not set\n");
4025
4026 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4027 WARN(!encoder_enabled, "encoder not enabled\n");
4028 if (WARN_ON(!encoder->base.crtc))
4029 return;
4030
4031 crtc = encoder->base.crtc;
4032
4033 WARN(!crtc->enabled, "crtc not enabled\n");
4034 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4035 WARN(pipe != to_intel_crtc(crtc)->pipe,
4036 "encoder active on the wrong pipe\n");
4037 }
79e53945
JB		 4038}
4039
5ab432ef
DV		 4040/* Even simpler default implementation, if there's really no special case to
4041 * consider. */
4042void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4043{
5ab432ef 4044 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4045
5ab432ef
DV		 4046 /* All the simple cases only support two dpms states. */
4047 if (mode != DRM_MODE_DPMS_ON)
4048 mode = DRM_MODE_DPMS_OFF;
d4270e57 4049
5ab432ef
DV		 4050 if (mode == connector->dpms)
4051 return;
4052
4053 connector->dpms = mode;
4054
4055 /* Only need to change hw state when actually enabled */
4056 if (encoder->base.crtc)
4057 intel_encoder_dpms(encoder, mode);
4058 else
8af6cf88 4059 WARN_ON(encoder->connectors_active != false);
0a91ca29 4060
b980514c 4061 intel_modeset_check_state(connector->dev);
79e53945
JB		 4062}
4063
f0947c37
DV		 4064/* Simple connector->get_hw_state implementation for encoders that support only
4065 * one connector and no cloning and hence the encoder state determines the state
4066 * of the connector. */
4067bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4068{
24929352 4069 enum pipe pipe = 0;
f0947c37 4070 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4071
f0947c37 4072 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4073}
4074
1857e1da
DV		 4075static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4076 struct intel_crtc_config *pipe_config)
4077{
4078 struct drm_i915_private *dev_priv = dev->dev_private;
4079 struct intel_crtc *pipe_B_crtc =
4080 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4081
4082 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4083 pipe_name(pipe), pipe_config->fdi_lanes);
4084 if (pipe_config->fdi_lanes > 4) {
4085 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4086 pipe_name(pipe), pipe_config->fdi_lanes);
4087 return false;
4088 }
4089
4090 if (IS_HASWELL(dev)) {
4091 if (pipe_config->fdi_lanes > 2) {
4092 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4093 pipe_config->fdi_lanes);
4094 return false;
4095 } else {
4096 return true;
4097 }
4098 }
4099
4100 if (INTEL_INFO(dev)->num_pipes == 2)
4101 return true;
4102
4103 /* Ivybridge 3 pipe is really complicated */
4104 switch (pipe) {
4105 case PIPE_A:
4106 return true;
4107 case PIPE_B:
4108 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4109 pipe_config->fdi_lanes > 2) {
4110 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4111 pipe_name(pipe), pipe_config->fdi_lanes);
4112 return false;
4113 }
4114 return true;
4115 case PIPE_C:
1e833f40 4116 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4117 pipe_B_crtc->config.fdi_lanes <= 2) {
4118 if (pipe_config->fdi_lanes > 2) {
4119 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4120 pipe_name(pipe), pipe_config->fdi_lanes);
4121 return false;
4122 }
4123 } else {
4124 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4125 return false;
4126 }
4127 return true;
4128 default:
4129 BUG();
4130 }
4131}
4132
e29c22c0
DV		 4133#define RETRY 1
4134static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4135 struct intel_crtc_config *pipe_config)
877d48d5 4136{
1857e1da 4137 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4138 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4139 int lane, link_bw, fdi_dotclock;
e29c22c0 4140 bool setup_ok, needs_recompute = false;
877d48d5 4141
e29c22c0 4142retry:
877d48d5
DV		 4143 /* FDI is a binary signal running at ~2.7GHz, encoding
4144 * each output octet as 10 bits. The actual frequency
4145 * is stored as a divider into a 100MHz clock, and the
4146 * mode pixel clock is stored in units of 1KHz.
4147 * Hence the bw of each lane in terms of the mode signal
4148 * is:
4149 */
4150 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4151
241bfc38 4152 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4153
2bd89a07 4154 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4155 pipe_config->pipe_bpp);
4156
4157 pipe_config->fdi_lanes = lane;
4158
2bd89a07 4159 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4160 link_bw, &pipe_config->fdi_m_n);
1857e1da 4161
e29c22c0
DV		 4162 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4163 intel_crtc->pipe, pipe_config);
4164 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4165 pipe_config->pipe_bpp -= 2*3;
4166 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4167 pipe_config->pipe_bpp);
4168 needs_recompute = true;
4169 pipe_config->bw_constrained = true;
4170
4171 goto retry;
4172 }
4173
4174 if (needs_recompute)
4175 return RETRY;
4176
4177 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4178}
4179
42db64ef
PZ		 4180static void hsw_compute_ips_config(struct intel_crtc *crtc,
4181 struct intel_crtc_config *pipe_config)
4182{
3c4ca58c
PZ		 4183 pipe_config->ips_enabled = i915_enable_ips &&
4184 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4185 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4186}
4187
a43f6e0f 4188static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4189 struct intel_crtc_config *pipe_config)
79e53945 4190{
a43f6e0f 4191 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4192 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4193
ad3a4479 4194 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4195 if (INTEL_INFO(dev)->gen < 4) {
4196 struct drm_i915_private *dev_priv = dev->dev_private;
4197 int clock_limit =
4198 dev_priv->display.get_display_clock_speed(dev);
4199
4200 /*
4201 * Enable pixel doubling when the dot clock
4202 * is > 90% of the (display) core speed.
4203 *
b397c96b
VS		 4204 * GDG double wide on either pipe,
4205 * otherwise pipe A only.
cf532bb2 4206 */
b397c96b 4207 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4208 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4209 clock_limit *= 2;
cf532bb2 4210 pipe_config->double_wide = true;
ad3a4479
VS		 4211 }
4212
241bfc38 4213 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4214 return -EINVAL;
2c07245f 4215 }
89749350 4216
1d1d0e27
VS		 4217 /*
4218 * Pipe horizontal size must be even in:
4219 * - DVO ganged mode
4220 * - LVDS dual channel mode
4221 * - Double wide pipe
4222 */
4223 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4224 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4225 pipe_config->pipe_src_w &= ~1;
4226
8693a824
DL		 4227 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4228 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4229 */
4230 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4231 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4232 return -EINVAL;
44f46b42 4233
bd080ee5 4234 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4235 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4236 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4237 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4238 * for lvds. */
4239 pipe_config->pipe_bpp = 8*3;
4240 }
4241
f5adf94e 4242 if (HAS_IPS(dev))
a43f6e0f
DV		 4243 hsw_compute_ips_config(crtc, pipe_config);
4244
4245 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4246 * clock survives for now. */
4247 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4248 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4249
877d48d5 4250 if (pipe_config->has_pch_encoder)
a43f6e0f 4251 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4252
e29c22c0 4253 return 0;
79e53945
JB		 4254}
4255
25eb05fc
JB		 4256static int valleyview_get_display_clock_speed(struct drm_device *dev)
4257{
4258 return 400000; /* FIXME */
4259}
4260
e70236a8
JB		 4261static int i945_get_display_clock_speed(struct drm_device *dev)
4262{
4263 return 400000;
4264}
79e53945 4265
e70236a8 4266static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4267{
e70236a8
JB		 4268 return 333000;
4269}
79e53945 4270
e70236a8
JB		 4271static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4272{
4273 return 200000;
4274}
79e53945 4275
257a7ffc
DV		 4276static int pnv_get_display_clock_speed(struct drm_device *dev)
4277{
4278 u16 gcfgc = 0;
4279
4280 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4281
4282 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4283 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4284 return 267000;
4285 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4286 return 333000;
4287 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4288 return 444000;
4289 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4290 return 200000;
4291 default:
4292 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4293 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4294 return 133000;
4295 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4296 return 167000;
4297 }
4298}
4299
e70236a8
JB		 4300static int i915gm_get_display_clock_speed(struct drm_device *dev)
4301{
4302 u16 gcfgc = 0;
79e53945 4303
e70236a8
JB		 4304 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4305
4306 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4307 return 133000;
4308 else {
4309 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4310 case GC_DISPLAY_CLOCK_333_MHZ:
4311 return 333000;
4312 default:
4313 case GC_DISPLAY_CLOCK_190_200_MHZ:
4314 return 190000;
79e53945 4315 }
e70236a8
JB		 4316 }
4317}
4318
4319static int i865_get_display_clock_speed(struct drm_device *dev)
4320{
4321 return 266000;
4322}
4323
4324static int i855_get_display_clock_speed(struct drm_device *dev)
4325{
4326 u16 hpllcc = 0;
4327 /* Assume that the hardware is in the high speed state. This
4328 * should be the default.
4329 */
4330 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4331 case GC_CLOCK_133_200:
4332 case GC_CLOCK_100_200:
4333 return 200000;
4334 case GC_CLOCK_166_250:
4335 return 250000;
4336 case GC_CLOCK_100_133:
79e53945 4337 return 133000;
e70236a8 4338 }
79e53945 4339
e70236a8
JB		 4340 /* Shouldn't happen */
4341 return 0;
4342}
79e53945 4343
e70236a8
JB		 4344static int i830_get_display_clock_speed(struct drm_device *dev)
4345{
4346 return 133000;
79e53945
JB		 4347}
4348
2c07245f 4349static void
a65851af 4350intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4351{
a65851af
VS		 4352 while (*num > DATA_LINK_M_N_MASK ||
4353 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4354 *num >>= 1;
4355 *den >>= 1;
4356 }
4357}
4358
a65851af
VS		 4359static void compute_m_n(unsigned int m, unsigned int n,
4360 uint32_t *ret_m, uint32_t *ret_n)
4361{
4362 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4363 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4364 intel_reduce_m_n_ratio(ret_m, ret_n);
4365}
4366
e69d0bc1
DV		 4367void
4368intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4369 int pixel_clock, int link_clock,
4370 struct intel_link_m_n *m_n)
2c07245f 4371{
e69d0bc1 4372 m_n->tu = 64;
a65851af
VS		 4373
4374 compute_m_n(bits_per_pixel * pixel_clock,
4375 link_clock * nlanes * 8,
4376 &m_n->gmch_m, &m_n->gmch_n);
4377
4378 compute_m_n(pixel_clock, link_clock,
4379 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4380}
4381
a7615030
CW		 4382static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4383{
72bbe58c
KP		 4384 if (i915_panel_use_ssc >= 0)
4385 return i915_panel_use_ssc != 0;
41aa3448 4386 return dev_priv->vbt.lvds_use_ssc
435793df 4387 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4388}
4389
c65d77d8
JB		 4390static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4391{
4392 struct drm_device *dev = crtc->dev;
4393 struct drm_i915_private *dev_priv = dev->dev_private;
4394 int refclk;
4395
a0c4da24 4396 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4397 refclk = 100000;
a0c4da24 4398 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4399 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4400 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4401 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4402 refclk / 1000);
4403 } else if (!IS_GEN2(dev)) {
4404 refclk = 96000;
4405 } else {
4406 refclk = 48000;
4407 }
4408
4409 return refclk;
4410}
4411
7429e9d4 4412static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4413{
7df00d7a 4414 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4415}
f47709a9 4416
7429e9d4
DV		 4417static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4418{
4419 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4420}
4421
f47709a9 4422static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4423 intel_clock_t *reduced_clock)
4424{
f47709a9 4425 struct drm_device *dev = crtc->base.dev;
a7516a05 4426 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4427 int pipe = crtc->pipe;
a7516a05
JB		 4428 u32 fp, fp2 = 0;
4429
4430 if (IS_PINEVIEW(dev)) {
7429e9d4 4431 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4432 if (reduced_clock)
7429e9d4 4433 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4434 } else {
7429e9d4 4435 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4436 if (reduced_clock)
7429e9d4 4437 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4438 }
4439
4440 I915_WRITE(FP0(pipe), fp);
8bcc2795 4441 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4442
f47709a9
DV		 4443 crtc->lowfreq_avail = false;
4444 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4445 reduced_clock && i915_powersave) {
4446 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4447 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4448 crtc->lowfreq_avail = true;
a7516a05
JB		 4449 } else {
4450 I915_WRITE(FP1(pipe), fp);
8bcc2795 4451 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4452 }
4453}
4454
5e69f97f
CML		 4455static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4456 pipe)
89b667f8
JB		 4457{
4458 u32 reg_val;
4459
4460 /*
4461 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4462 * and set it to a reasonable value instead.
4463 */
5e69f97f 4464 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4465 reg_val &= 0xffffff00;
4466 reg_val |= 0x00000030;
5e69f97f 4467 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4468
5e69f97f 4469 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4470 reg_val &= 0x8cffffff;
4471 reg_val = 0x8c000000;
5e69f97f 4472 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4473
5e69f97f 4474 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4475 reg_val &= 0xffffff00;
5e69f97f 4476 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4477
5e69f97f 4478 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4479 reg_val &= 0x00ffffff;
4480 reg_val |= 0xb0000000;
5e69f97f 4481 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4482}
4483
b551842d
DV		 4484static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4485 struct intel_link_m_n *m_n)
4486{
4487 struct drm_device *dev = crtc->base.dev;
4488 struct drm_i915_private *dev_priv = dev->dev_private;
4489 int pipe = crtc->pipe;
4490
e3b95f1e
DV		 4491 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4492 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4493 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4494 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4495}
4496
4497static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4498 struct intel_link_m_n *m_n)
4499{
4500 struct drm_device *dev = crtc->base.dev;
4501 struct drm_i915_private *dev_priv = dev->dev_private;
4502 int pipe = crtc->pipe;
4503 enum transcoder transcoder = crtc->config.cpu_transcoder;
4504
4505 if (INTEL_INFO(dev)->gen >= 5) {
4506 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4507 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4508 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4509 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4510 } else {
e3b95f1e
DV		 4511 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4512 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4513 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4514 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4515 }
4516}
4517
03afc4a2
DV		 4518static void intel_dp_set_m_n(struct intel_crtc *crtc)
4519{
4520 if (crtc->config.has_pch_encoder)
4521 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4522 else
4523 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4524}
4525
f47709a9 4526static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4527{
f47709a9 4528 struct drm_device *dev = crtc->base.dev;
a0c4da24 4529 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4530 int pipe = crtc->pipe;
89b667f8 4531 u32 dpll, mdiv;
a0c4da24 4532 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4533 u32 coreclk, reg_val, dpll_md;
a0c4da24 4534
09153000
DV		 4535 mutex_lock(&dev_priv->dpio_lock);
4536
f47709a9
DV		 4537 bestn = crtc->config.dpll.n;
4538 bestm1 = crtc->config.dpll.m1;
4539 bestm2 = crtc->config.dpll.m2;
4540 bestp1 = crtc->config.dpll.p1;
4541 bestp2 = crtc->config.dpll.p2;
a0c4da24 4542
89b667f8
JB		 4543 /* See eDP HDMI DPIO driver vbios notes doc */
4544
4545 /* PLL B needs special handling */
4546 if (pipe)
5e69f97f 4547 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4548
4549 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4550 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4551
4552 /* Disable target IRef on PLL */
5e69f97f 4553 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4554 reg_val &= 0x00ffffff;
5e69f97f 4555 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4556
4557 /* Disable fast lock */
5e69f97f 4558 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4559
4560 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4561 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4562 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4563 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4564 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4565
4566 /*
4567 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4568 * but we don't support that).
4569 * Note: don't use the DAC post divider as it seems unstable.
4570 */
4571 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4572 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4573
a0c4da24 4574 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4575 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4576
89b667f8 4577 /* Set HBR and RBR LPF coefficients */
ff9a6750 4578 if (crtc->config.port_clock == 162000 ||
99750bd4 4579 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4580 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4581 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4582 0x009f0003);
89b667f8 4583 else
5e69f97f 4584 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4585 0x00d0000f);
4586
4587 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4588 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4589 /* Use SSC source */
4590 if (!pipe)
5e69f97f 4591 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4592 0x0df40000);
4593 else
5e69f97f 4594 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4595 0x0df70000);
4596 } else { /* HDMI or VGA */
4597 /* Use bend source */
4598 if (!pipe)
5e69f97f 4599 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4600 0x0df70000);
4601 else
5e69f97f 4602 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4603 0x0df40000);
4604 }
a0c4da24 4605
5e69f97f 4606 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4607 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4608 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4609 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4610 coreclk |= 0x01000000;
5e69f97f 4611 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4612
5e69f97f 4613 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4614
89b667f8
JB		 4615 /* Enable DPIO clock input */
4616 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4617 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4618 if (pipe)
4619 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4620
4621 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4622 crtc->config.dpll_hw_state.dpll = dpll;
4623
ef1b460d
DV		 4624 dpll_md = (crtc->config.pixel_multiplier - 1)
4625 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4626 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4627
89b667f8
JB		 4628 if (crtc->config.has_dp_encoder)
4629 intel_dp_set_m_n(crtc);
09153000
DV		 4630
4631 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4632}
4633
f47709a9
DV		 4634static void i9xx_update_pll(struct intel_crtc *crtc,
4635 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4636 int num_connectors)
4637{
f47709a9 4638 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4639 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4640 u32 dpll;
4641 bool is_sdvo;
f47709a9 4642 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4643
f47709a9 4644 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4645
f47709a9
DV		 4646 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4647 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4648
4649 dpll = DPLL_VGA_MODE_DIS;
4650
f47709a9 4651 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4652 dpll |= DPLLB_MODE_LVDS;
4653 else
4654 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4655
ef1b460d 4656 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4657 dpll |= (crtc->config.pixel_multiplier - 1)
4658 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4659 }
198a037f
DV		 4660
4661 if (is_sdvo)
4a33e48d 4662 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4663
f47709a9 4664 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4665 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4666
4667 /* compute bitmask from p1 value */
4668 if (IS_PINEVIEW(dev))
4669 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4670 else {
4671 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4672 if (IS_G4X(dev) && reduced_clock)
4673 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4674 }
4675 switch (clock->p2) {
4676 case 5:
4677 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4678 break;
4679 case 7:
4680 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4681 break;
4682 case 10:
4683 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4684 break;
4685 case 14:
4686 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4687 break;
4688 }
4689 if (INTEL_INFO(dev)->gen >= 4)
4690 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4691
09ede541 4692 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4693 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4694 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4695 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4696 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4697 else
4698 dpll |= PLL_REF_INPUT_DREFCLK;
4699
4700 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4701 crtc->config.dpll_hw_state.dpll = dpll;
4702
eb1cbe48 4703 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4704 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4705 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4706 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4707 }
66e3d5c0
DV		 4708
4709 if (crtc->config.has_dp_encoder)
4710 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4711}
4712
f47709a9 4713static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4714 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4715 int num_connectors)
4716{
f47709a9 4717 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4718 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4719 u32 dpll;
f47709a9 4720 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4721
f47709a9 4722 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4723
eb1cbe48
DV		 4724 dpll = DPLL_VGA_MODE_DIS;
4725
f47709a9 4726 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4727 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4728 } else {
4729 if (clock->p1 == 2)
4730 dpll |= PLL_P1_DIVIDE_BY_TWO;
4731 else
4732 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4733 if (clock->p2 == 4)
4734 dpll |= PLL_P2_DIVIDE_BY_4;
4735 }
4736
4a33e48d
DV		 4737 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4738 dpll |= DPLL_DVO_2X_MODE;
4739
f47709a9 4740 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4741 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4742 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4743 else
4744 dpll |= PLL_REF_INPUT_DREFCLK;
4745
4746 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4747 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4748}
4749
8a654f3b 4750static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4751{
4752 struct drm_device *dev = intel_crtc->base.dev;
4753 struct drm_i915_private *dev_priv = dev->dev_private;
4754 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4755 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4756 struct drm_display_mode *adjusted_mode =
4757 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4758 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4759
4760 /* We need to be careful not to changed the adjusted mode, for otherwise
4761 * the hw state checker will get angry at the mismatch. */
4762 crtc_vtotal = adjusted_mode->crtc_vtotal;
4763 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4764
4765 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4766 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4767 crtc_vtotal -= 1;
4768 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4769 vsyncshift = adjusted_mode->crtc_hsync_start
4770 - adjusted_mode->crtc_htotal / 2;
4771 } else {
4772 vsyncshift = 0;
4773 }
4774
4775 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4776 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4777
fe2b8f9d 4778 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4779 (adjusted_mode->crtc_hdisplay - 1) |
4780 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4781 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4782 (adjusted_mode->crtc_hblank_start - 1) |
4783 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4784 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4785 (adjusted_mode->crtc_hsync_start - 1) |
4786 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4787
fe2b8f9d 4788 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4789 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4790 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4791 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4792 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4793 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4794 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4795 (adjusted_mode->crtc_vsync_start - 1) |
4796 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4797
b5e508d4
PZ		 4798 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4799 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4800 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4801 * bits. */
4802 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4803 (pipe == PIPE_B || pipe == PIPE_C))
4804 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4805
b0e77b9c
PZ		 4806 /* pipesrc controls the size that is scaled from, which should
4807 * always be the user's requested size.
4808 */
4809 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4810 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4811 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4812}
4813
1bd1bd80
DV		 4814static void intel_get_pipe_timings(struct intel_crtc *crtc,
4815 struct intel_crtc_config *pipe_config)
4816{
4817 struct drm_device *dev = crtc->base.dev;
4818 struct drm_i915_private *dev_priv = dev->dev_private;
4819 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4820 uint32_t tmp;
4821
4822 tmp = I915_READ(HTOTAL(cpu_transcoder));
4823 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4824 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4825 tmp = I915_READ(HBLANK(cpu_transcoder));
4826 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4827 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4828 tmp = I915_READ(HSYNC(cpu_transcoder));
4829 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4830 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4831
4832 tmp = I915_READ(VTOTAL(cpu_transcoder));
4833 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4834 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4835 tmp = I915_READ(VBLANK(cpu_transcoder));
4836 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4837 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4838 tmp = I915_READ(VSYNC(cpu_transcoder));
4839 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4840 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4841
4842 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4843 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4844 pipe_config->adjusted_mode.crtc_vtotal += 1;
4845 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4846 }
4847
4848 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4849 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4850 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4851
4852 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4853 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4854}
4855
babea61d
JB		 4856static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4857 struct intel_crtc_config *pipe_config)
4858{
4859 struct drm_crtc *crtc = &intel_crtc->base;
4860
4861 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4862 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4863 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4864 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4865
4866 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4867 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4868 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4869 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4870
4871 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4872
241bfc38 4873 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4874 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4875}
4876
84b046f3
DV		 4877static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4878{
4879 struct drm_device *dev = intel_crtc->base.dev;
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 uint32_t pipeconf;
4882
9f11a9e4 4883 pipeconf = 0;
84b046f3 4884
67c72a12
DV		 4885 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4886 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4887 pipeconf |= PIPECONF_ENABLE;
4888
cf532bb2
VS		 4889 if (intel_crtc->config.double_wide)
4890 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4891
ff9ce46e
DV		 4892 /* only g4x and later have fancy bpc/dither controls */
4893 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4894 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4895 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4896 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4897 PIPECONF_DITHER_TYPE_SP;
84b046f3 4898
ff9ce46e
DV		 4899 switch (intel_crtc->config.pipe_bpp) {
4900 case 18:
4901 pipeconf |= PIPECONF_6BPC;
4902 break;
4903 case 24:
4904 pipeconf |= PIPECONF_8BPC;
4905 break;
4906 case 30:
4907 pipeconf |= PIPECONF_10BPC;
4908 break;
4909 default:
4910 /* Case prevented by intel_choose_pipe_bpp_dither. */
4911 BUG();
84b046f3
DV		 4912 }
4913 }
4914
4915 if (HAS_PIPE_CXSR(dev)) {
4916 if (intel_crtc->lowfreq_avail) {
4917 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4918 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4919 } else {
4920 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4921 }
4922 }
4923
84b046f3
DV		 4924 if (!IS_GEN2(dev) &&
4925 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4926 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4927 else
4928 pipeconf |= PIPECONF_PROGRESSIVE;
4929
9f11a9e4
DV		 4930 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4931 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4932
84b046f3
DV		 4933 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4934 POSTING_READ(PIPECONF(intel_crtc->pipe));
4935}
4936
f564048e 4937static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4938 int x, int y,
94352cf9 4939 struct drm_framebuffer *fb)
79e53945
JB		 4940{
4941 struct drm_device *dev = crtc->dev;
4942 struct drm_i915_private *dev_priv = dev->dev_private;
4943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4944 int pipe = intel_crtc->pipe;
80824003 4945 int plane = intel_crtc->plane;
c751ce4f 4946 int refclk, num_connectors = 0;
652c393a 4947 intel_clock_t clock, reduced_clock;
84b046f3 4948 u32 dspcntr;
a16af721 4949 bool ok, has_reduced_clock = false;
e9fd1c02 4950 bool is_lvds = false, is_dsi = false;
5eddb70b 4951 struct intel_encoder *encoder;
d4906093 4952 const intel_limit_t *limit;
5c3b82e2 4953 int ret;
79e53945 4954
6c2b7c12 4955 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4956 switch (encoder->type) {
79e53945
JB		 4957 case INTEL_OUTPUT_LVDS:
4958 is_lvds = true;
4959 break;
e9fd1c02
JN		 4960 case INTEL_OUTPUT_DSI:
4961 is_dsi = true;
4962 break;
79e53945 4963 }
43565a06 4964
c751ce4f 4965 num_connectors++;
79e53945
JB		 4966 }
4967
f2335330
JN		 4968 if (is_dsi)
4969 goto skip_dpll;
4970
4971 if (!intel_crtc->config.clock_set) {
4972 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4973
e9fd1c02
JN		 4974 /*
4975 * Returns a set of divisors for the desired target clock with
4976 * the given refclk, or FALSE. The returned values represent
4977 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4978 * 2) / p1 / p2.
4979 */
4980 limit = intel_limit(crtc, refclk);
4981 ok = dev_priv->display.find_dpll(limit, crtc,
4982 intel_crtc->config.port_clock,
4983 refclk, NULL, &clock);
f2335330 4984 if (!ok) {
e9fd1c02
JN		 4985 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4986 return -EINVAL;
4987 }
79e53945 4988
f2335330
JN		 4989 if (is_lvds && dev_priv->lvds_downclock_avail) {
4990 /*
4991 * Ensure we match the reduced clock's P to the target
4992 * clock. If the clocks don't match, we can't switch
4993 * the display clock by using the FP0/FP1. In such case
4994 * we will disable the LVDS downclock feature.
4995 */
4996 has_reduced_clock =
4997 dev_priv->display.find_dpll(limit, crtc,
4998 dev_priv->lvds_downclock,
4999 refclk, &clock,
5000 &reduced_clock);
5001 }
5002 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5003 intel_crtc->config.dpll.n = clock.n;
5004 intel_crtc->config.dpll.m1 = clock.m1;
5005 intel_crtc->config.dpll.m2 = clock.m2;
5006 intel_crtc->config.dpll.p1 = clock.p1;
5007 intel_crtc->config.dpll.p2 = clock.p2;
5008 }
7026d4ac 5009
e9fd1c02 5010 if (IS_GEN2(dev)) {
8a654f3b 5011 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5012 has_reduced_clock ? &reduced_clock : NULL,
5013 num_connectors);
e9fd1c02 5014 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5015 vlv_update_pll(intel_crtc);
e9fd1c02 5016 } else {
f47709a9 5017 i9xx_update_pll(intel_crtc,
eb1cbe48 5018 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5019 num_connectors);
e9fd1c02 5020 }
79e53945 5021
f2335330 5022skip_dpll:
79e53945
JB		 5023 /* Set up the display plane register */
5024 dspcntr = DISPPLANE_GAMMA_ENABLE;
5025
da6ecc5d
JB		 5026 if (!IS_VALLEYVIEW(dev)) {
5027 if (pipe == 0)
5028 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5029 else
5030 dspcntr |= DISPPLANE_SEL_PIPE_B;
5031 }
79e53945 5032
8a654f3b 5033 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5034
5035 /* pipesrc and dspsize control the size that is scaled from,
5036 * which should always be the user's requested size.
79e53945 5037 */
929c77fb 5038 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5039 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5040 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5041 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5042
84b046f3
DV		 5043 i9xx_set_pipeconf(intel_crtc);
5044
f564048e
EA		 5045 I915_WRITE(DSPCNTR(plane), dspcntr);
5046 POSTING_READ(DSPCNTR(plane));
5047
94352cf9 5048 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5049
f564048e
EA		 5050 return ret;
5051}
5052
2fa2fe9a
DV		 5053static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5054 struct intel_crtc_config *pipe_config)
5055{
5056 struct drm_device *dev = crtc->base.dev;
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 uint32_t tmp;
5059
5060 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5061 if (!(tmp & PFIT_ENABLE))
5062 return;
2fa2fe9a 5063
06922821 5064 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5065 if (INTEL_INFO(dev)->gen < 4) {
5066 if (crtc->pipe != PIPE_B)
5067 return;
2fa2fe9a
DV		 5068 } else {
5069 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5070 return;
5071 }
5072
06922821 5073 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5074 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5075 if (INTEL_INFO(dev)->gen < 5)
5076 pipe_config->gmch_pfit.lvds_border_bits =
5077 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5078}
5079
acbec814
JB		 5080static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5081 struct intel_crtc_config *pipe_config)
5082{
5083 struct drm_device *dev = crtc->base.dev;
5084 struct drm_i915_private *dev_priv = dev->dev_private;
5085 int pipe = pipe_config->cpu_transcoder;
5086 intel_clock_t clock;
5087 u32 mdiv;
662c6ecb 5088 int refclk = 100000;
acbec814
JB		 5089
5090 mutex_lock(&dev_priv->dpio_lock);
5091 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5092 mutex_unlock(&dev_priv->dpio_lock);
5093
5094 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5095 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5096 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5097 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5098 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5099
662c6ecb
CW		 5100 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5101 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5102
5103 pipe_config->port_clock = clock.dot / 10;
5104}
5105
0e8ffe1b
DV		 5106static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5107 struct intel_crtc_config *pipe_config)
5108{
5109 struct drm_device *dev = crtc->base.dev;
5110 struct drm_i915_private *dev_priv = dev->dev_private;
5111 uint32_t tmp;
5112
e143a21c 5113 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5114 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5115
0e8ffe1b
DV		 5116 tmp = I915_READ(PIPECONF(crtc->pipe));
5117 if (!(tmp & PIPECONF_ENABLE))
5118 return false;
5119
42571aef
VS		 5120 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5121 switch (tmp & PIPECONF_BPC_MASK) {
5122 case PIPECONF_6BPC:
5123 pipe_config->pipe_bpp = 18;
5124 break;
5125 case PIPECONF_8BPC:
5126 pipe_config->pipe_bpp = 24;
5127 break;
5128 case PIPECONF_10BPC:
5129 pipe_config->pipe_bpp = 30;
5130 break;
5131 default:
5132 break;
5133 }
5134 }
5135
282740f7
VS		 5136 if (INTEL_INFO(dev)->gen < 4)
5137 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5138
1bd1bd80
DV		 5139 intel_get_pipe_timings(crtc, pipe_config);
5140
2fa2fe9a
DV		 5141 i9xx_get_pfit_config(crtc, pipe_config);
5142
6c49f241
DV		 5143 if (INTEL_INFO(dev)->gen >= 4) {
5144 tmp = I915_READ(DPLL_MD(crtc->pipe));
5145 pipe_config->pixel_multiplier =
5146 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5147 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5148 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5149 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5150 tmp = I915_READ(DPLL(crtc->pipe));
5151 pipe_config->pixel_multiplier =
5152 ((tmp & SDVO_MULTIPLIER_MASK)
5153 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5154 } else {
5155 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5156 * port and will be fixed up in the encoder->get_config
5157 * function. */
5158 pipe_config->pixel_multiplier = 1;
5159 }
8bcc2795
DV		 5160 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5161 if (!IS_VALLEYVIEW(dev)) {
5162 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5163 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5164 } else {
5165 /* Mask out read-only status bits. */
5166 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5167 DPLL_PORTC_READY_MASK |
5168 DPLL_PORTB_READY_MASK);
8bcc2795 5169 }
6c49f241 5170
acbec814
JB		 5171 if (IS_VALLEYVIEW(dev))
5172 vlv_crtc_clock_get(crtc, pipe_config);
5173 else
5174 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5175
0e8ffe1b
DV		 5176 return true;
5177}
5178
dde86e2d 5179static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5180{
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5183 struct intel_encoder *encoder;
74cfd7ac 5184 u32 val, final;
13d83a67 5185 bool has_lvds = false;
199e5d79 5186 bool has_cpu_edp = false;
199e5d79 5187 bool has_panel = false;
99eb6a01
KP		 5188 bool has_ck505 = false;
5189 bool can_ssc = false;
13d83a67
JB		 5190
5191 /* We need to take the global config into account */
199e5d79
KP		 5192 list_for_each_entry(encoder, &mode_config->encoder_list,
5193 base.head) {
5194 switch (encoder->type) {
5195 case INTEL_OUTPUT_LVDS:
5196 has_panel = true;
5197 has_lvds = true;
5198 break;
5199 case INTEL_OUTPUT_EDP:
5200 has_panel = true;
2de6905f 5201 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5202 has_cpu_edp = true;
5203 break;
13d83a67
JB		 5204 }
5205 }
5206
99eb6a01 5207 if (HAS_PCH_IBX(dev)) {
41aa3448 5208 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5209 can_ssc = has_ck505;
5210 } else {
5211 has_ck505 = false;
5212 can_ssc = true;
5213 }
5214
2de6905f
ID		 5215 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5216 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5217
5218 /* Ironlake: try to setup display ref clock before DPLL
5219 * enabling. This is only under driver's control after
5220 * PCH B stepping, previous chipset stepping should be
5221 * ignoring this setting.
5222 */
74cfd7ac
CW		 5223 val = I915_READ(PCH_DREF_CONTROL);
5224
5225 /* As we must carefully and slowly disable/enable each source in turn,
5226 * compute the final state we want first and check if we need to
5227 * make any changes at all.
5228 */
5229 final = val;
5230 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5231 if (has_ck505)
5232 final |= DREF_NONSPREAD_CK505_ENABLE;
5233 else
5234 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5235
5236 final &= ~DREF_SSC_SOURCE_MASK;
5237 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5238 final &= ~DREF_SSC1_ENABLE;
5239
5240 if (has_panel) {
5241 final |= DREF_SSC_SOURCE_ENABLE;
5242
5243 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5244 final |= DREF_SSC1_ENABLE;
5245
5246 if (has_cpu_edp) {
5247 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5248 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5249 else
5250 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5251 } else
5252 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5253 } else {
5254 final |= DREF_SSC_SOURCE_DISABLE;
5255 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5256 }
5257
5258 if (final == val)
5259 return;
5260
13d83a67 5261 /* Always enable nonspread source */
74cfd7ac 5262 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5263
99eb6a01 5264 if (has_ck505)
74cfd7ac 5265 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5266 else
74cfd7ac 5267 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5268
199e5d79 5269 if (has_panel) {
74cfd7ac
CW		 5270 val &= ~DREF_SSC_SOURCE_MASK;
5271 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5272
199e5d79 5273 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5274 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5275 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5276 val |= DREF_SSC1_ENABLE;
e77166b5 5277 } else
74cfd7ac 5278 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5279
5280 /* Get SSC going before enabling the outputs */
74cfd7ac 5281 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5282 POSTING_READ(PCH_DREF_CONTROL);
5283 udelay(200);
5284
74cfd7ac 5285 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5286
5287 /* Enable CPU source on CPU attached eDP */
199e5d79 5288 if (has_cpu_edp) {
99eb6a01 5289 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5290 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5291 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5292 }
13d83a67 5293 else
74cfd7ac 5294 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5295 } else
74cfd7ac 5296 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5297
74cfd7ac 5298 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5299 POSTING_READ(PCH_DREF_CONTROL);
5300 udelay(200);
5301 } else {
5302 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5303
74cfd7ac 5304 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5305
5306 /* Turn off CPU output */
74cfd7ac 5307 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5308
74cfd7ac 5309 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5310 POSTING_READ(PCH_DREF_CONTROL);
5311 udelay(200);
5312
5313 /* Turn off the SSC source */
74cfd7ac
CW		 5314 val &= ~DREF_SSC_SOURCE_MASK;
5315 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5316
5317 /* Turn off SSC1 */
74cfd7ac 5318 val &= ~DREF_SSC1_ENABLE;
199e5d79 5319
74cfd7ac 5320 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5321 POSTING_READ(PCH_DREF_CONTROL);
5322 udelay(200);
5323 }
74cfd7ac
CW		 5324
5325 BUG_ON(val != final);
13d83a67
JB		 5326}
5327
f31f2d55 5328static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5329{
f31f2d55 5330 uint32_t tmp;
dde86e2d 5331
0ff066a9
PZ		 5332 tmp = I915_READ(SOUTH_CHICKEN2);
5333 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5334 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5335
0ff066a9
PZ		 5336 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5337 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5338 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5339
0ff066a9
PZ		 5340 tmp = I915_READ(SOUTH_CHICKEN2);
5341 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5342 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5343
0ff066a9
PZ		 5344 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5345 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5346 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5347}
5348
5349/* WaMPhyProgramming:hsw */
5350static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5351{
5352 uint32_t tmp;
dde86e2d
PZ		 5353
5354 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5355 tmp &= ~(0xFF << 24);
5356 tmp |= (0x12 << 24);
5357 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5358
dde86e2d
PZ		 5359 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5360 tmp |= (1 << 11);
5361 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5362
5363 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5364 tmp |= (1 << 11);
5365 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5366
dde86e2d
PZ		 5367 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5368 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5369 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5370
5371 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5372 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5373 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5374
0ff066a9
PZ		 5375 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5376 tmp &= ~(7 << 13);
5377 tmp |= (5 << 13);
5378 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5379
0ff066a9
PZ		 5380 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5381 tmp &= ~(7 << 13);
5382 tmp |= (5 << 13);
5383 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5384
5385 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5386 tmp &= ~0xFF;
5387 tmp |= 0x1C;
5388 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5389
5390 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5391 tmp &= ~0xFF;
5392 tmp |= 0x1C;
5393 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5394
5395 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5396 tmp &= ~(0xFF << 16);
5397 tmp |= (0x1C << 16);
5398 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5399
5400 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5401 tmp &= ~(0xFF << 16);
5402 tmp |= (0x1C << 16);
5403 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5404
0ff066a9
PZ		 5405 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5406 tmp |= (1 << 27);
5407 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5408
0ff066a9
PZ		 5409 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5410 tmp |= (1 << 27);
5411 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5412
0ff066a9
PZ		 5413 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5414 tmp &= ~(0xF << 28);
5415 tmp |= (4 << 28);
5416 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5417
0ff066a9
PZ		 5418 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5419 tmp &= ~(0xF << 28);
5420 tmp |= (4 << 28);
5421 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5422}
5423
2fa86a1f
PZ		 5424/* Implements 3 different sequences from BSpec chapter "Display iCLK
5425 * Programming" based on the parameters passed:
5426 * - Sequence to enable CLKOUT_DP
5427 * - Sequence to enable CLKOUT_DP without spread
5428 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5429 */
5430static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5431 bool with_fdi)
f31f2d55
PZ		 5432{
5433 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5434 uint32_t reg, tmp;
5435
5436 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5437 with_spread = true;
5438 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5439 with_fdi, "LP PCH doesn't have FDI\n"))
5440 with_fdi = false;
f31f2d55
PZ		 5441
5442 mutex_lock(&dev_priv->dpio_lock);
5443
5444 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5445 tmp &= ~SBI_SSCCTL_DISABLE;
5446 tmp |= SBI_SSCCTL_PATHALT;
5447 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5448
5449 udelay(24);
5450
2fa86a1f
PZ		 5451 if (with_spread) {
5452 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5453 tmp &= ~SBI_SSCCTL_PATHALT;
5454 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5455
2fa86a1f
PZ		 5456 if (with_fdi) {
5457 lpt_reset_fdi_mphy(dev_priv);
5458 lpt_program_fdi_mphy(dev_priv);
5459 }
5460 }
dde86e2d 5461
2fa86a1f
PZ		 5462 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5463 SBI_GEN0 : SBI_DBUFF0;
5464 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5465 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5466 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5467
5468 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5469}
5470
47701c3b
PZ		 5471/* Sequence to disable CLKOUT_DP */
5472static void lpt_disable_clkout_dp(struct drm_device *dev)
5473{
5474 struct drm_i915_private *dev_priv = dev->dev_private;
5475 uint32_t reg, tmp;
5476
5477 mutex_lock(&dev_priv->dpio_lock);
5478
5479 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5480 SBI_GEN0 : SBI_DBUFF0;
5481 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5482 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5483 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5484
5485 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5486 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5487 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5488 tmp |= SBI_SSCCTL_PATHALT;
5489 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5490 udelay(32);
5491 }
5492 tmp |= SBI_SSCCTL_DISABLE;
5493 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5494 }
5495
5496 mutex_unlock(&dev_priv->dpio_lock);
5497}
5498
bf8fa3d3
PZ		 5499static void lpt_init_pch_refclk(struct drm_device *dev)
5500{
5501 struct drm_mode_config *mode_config = &dev->mode_config;
5502 struct intel_encoder *encoder;
5503 bool has_vga = false;
5504
5505 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5506 switch (encoder->type) {
5507 case INTEL_OUTPUT_ANALOG:
5508 has_vga = true;
5509 break;
5510 }
5511 }
5512
47701c3b
PZ		 5513 if (has_vga)
5514 lpt_enable_clkout_dp(dev, true, true);
5515 else
5516 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5517}
5518
dde86e2d
PZ		 5519/*
5520 * Initialize reference clocks when the driver loads
5521 */
5522void intel_init_pch_refclk(struct drm_device *dev)
5523{
5524 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5525 ironlake_init_pch_refclk(dev);
5526 else if (HAS_PCH_LPT(dev))
5527 lpt_init_pch_refclk(dev);
5528}
5529
d9d444cb
JB		 5530static int ironlake_get_refclk(struct drm_crtc *crtc)
5531{
5532 struct drm_device *dev = crtc->dev;
5533 struct drm_i915_private *dev_priv = dev->dev_private;
5534 struct intel_encoder *encoder;
d9d444cb
JB		 5535 int num_connectors = 0;
5536 bool is_lvds = false;
5537
6c2b7c12 5538 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5539 switch (encoder->type) {
5540 case INTEL_OUTPUT_LVDS:
5541 is_lvds = true;
5542 break;
d9d444cb
JB		 5543 }
5544 num_connectors++;
5545 }
5546
5547 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5548 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5549 dev_priv->vbt.lvds_ssc_freq);
5550 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5551 }
5552
5553 return 120000;
5554}
5555
6ff93609 5556static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5557{
c8203565 5558 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5560 int pipe = intel_crtc->pipe;
c8203565
PZ		 5561 uint32_t val;
5562
78114071 5563 val = 0;
c8203565 5564
965e0c48 5565 switch (intel_crtc->config.pipe_bpp) {
c8203565 5566 case 18:
dfd07d72 5567 val |= PIPECONF_6BPC;
c8203565
PZ		 5568 break;
5569 case 24:
dfd07d72 5570 val |= PIPECONF_8BPC;
c8203565
PZ		 5571 break;
5572 case 30:
dfd07d72 5573 val |= PIPECONF_10BPC;
c8203565
PZ		 5574 break;
5575 case 36:
dfd07d72 5576 val |= PIPECONF_12BPC;
c8203565
PZ		 5577 break;
5578 default:
cc769b62
PZ		 5579 /* Case prevented by intel_choose_pipe_bpp_dither. */
5580 BUG();
c8203565
PZ		 5581 }
5582
d8b32247 5583 if (intel_crtc->config.dither)
c8203565
PZ		 5584 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5585
6ff93609 5586 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5587 val |= PIPECONF_INTERLACED_ILK;
5588 else
5589 val |= PIPECONF_PROGRESSIVE;
5590
50f3b016 5591 if (intel_crtc->config.limited_color_range)
3685a8f3 5592 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5593
c8203565
PZ		 5594 I915_WRITE(PIPECONF(pipe), val);
5595 POSTING_READ(PIPECONF(pipe));
5596}
5597
86d3efce
VS		 5598/*
5599 * Set up the pipe CSC unit.
5600 *
5601 * Currently only full range RGB to limited range RGB conversion
5602 * is supported, but eventually this should handle various
5603 * RGB<->YCbCr scenarios as well.
5604 */
50f3b016 5605static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5606{
5607 struct drm_device *dev = crtc->dev;
5608 struct drm_i915_private *dev_priv = dev->dev_private;
5609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5610 int pipe = intel_crtc->pipe;
5611 uint16_t coeff = 0x7800; /* 1.0 */
5612
5613 /*
5614 * TODO: Check what kind of values actually come out of the pipe
5615 * with these coeff/postoff values and adjust to get the best
5616 * accuracy. Perhaps we even need to take the bpc value into
5617 * consideration.
5618 */
5619
50f3b016 5620 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5621 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5622
5623 /*
5624 * GY/GU and RY/RU should be the other way around according
5625 * to BSpec, but reality doesn't agree. Just set them up in
5626 * a way that results in the correct picture.
5627 */
5628 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5629 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5630
5631 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5632 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5633
5634 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5635 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5636
5637 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5638 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5639 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5640
5641 if (INTEL_INFO(dev)->gen > 6) {
5642 uint16_t postoff = 0;
5643
50f3b016 5644 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5645 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5646
5647 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5648 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5649 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5650
5651 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5652 } else {
5653 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5654
50f3b016 5655 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5656 mode |= CSC_BLACK_SCREEN_OFFSET;
5657
5658 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5659 }
5660}
5661
6ff93609 5662static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5663{
5664 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5666 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5667 uint32_t val;
5668
3eff4faa 5669 val = 0;
ee2b0b38 5670
d8b32247 5671 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5672 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5673
6ff93609 5674 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5675 val |= PIPECONF_INTERLACED_ILK;
5676 else
5677 val |= PIPECONF_PROGRESSIVE;
5678
702e7a56
PZ		 5679 I915_WRITE(PIPECONF(cpu_transcoder), val);
5680 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5681
5682 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5683 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5684}
5685
6591c6e4 5686static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5687 intel_clock_t *clock,
5688 bool *has_reduced_clock,
5689 intel_clock_t *reduced_clock)
5690{
5691 struct drm_device *dev = crtc->dev;
5692 struct drm_i915_private *dev_priv = dev->dev_private;
5693 struct intel_encoder *intel_encoder;
5694 int refclk;
d4906093 5695 const intel_limit_t *limit;
a16af721 5696 bool ret, is_lvds = false;
79e53945 5697
6591c6e4
PZ		 5698 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5699 switch (intel_encoder->type) {
79e53945
JB		 5700 case INTEL_OUTPUT_LVDS:
5701 is_lvds = true;
5702 break;
79e53945
JB		 5703 }
5704 }
5705
d9d444cb 5706 refclk = ironlake_get_refclk(crtc);
79e53945 5707
d4906093
ML		 5708 /*
5709 * Returns a set of divisors for the desired target clock with the given
5710 * refclk, or FALSE. The returned values represent the clock equation:
5711 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5712 */
1b894b59 5713 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5714 ret = dev_priv->display.find_dpll(limit, crtc,
5715 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5716 refclk, NULL, clock);
6591c6e4
PZ		 5717 if (!ret)
5718 return false;
cda4b7d3 5719
ddc9003c 5720 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5721 /*
5722 * Ensure we match the reduced clock's P to the target clock.
5723 * If the clocks don't match, we can't switch the display clock
5724 * by using the FP0/FP1. In such case we will disable the LVDS
5725 * downclock feature.
5726 */
ee9300bb
DV		 5727 *has_reduced_clock =
5728 dev_priv->display.find_dpll(limit, crtc,
5729 dev_priv->lvds_downclock,
5730 refclk, clock,
5731 reduced_clock);
652c393a 5732 }
61e9653f 5733
6591c6e4
PZ		 5734 return true;
5735}
5736
01a415fd
DV		 5737static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5738{
5739 struct drm_i915_private *dev_priv = dev->dev_private;
5740 uint32_t temp;
5741
5742 temp = I915_READ(SOUTH_CHICKEN1);
5743 if (temp & FDI_BC_BIFURCATION_SELECT)
5744 return;
5745
5746 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5747 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5748
5749 temp |= FDI_BC_BIFURCATION_SELECT;
5750 DRM_DEBUG_KMS("enabling fdi C rx\n");
5751 I915_WRITE(SOUTH_CHICKEN1, temp);
5752 POSTING_READ(SOUTH_CHICKEN1);
5753}
5754
ebfd86fd 5755static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5756{
5757 struct drm_device *dev = intel_crtc->base.dev;
5758 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5759
5760 switch (intel_crtc->pipe) {
5761 case PIPE_A:
ebfd86fd 5762 break;
01a415fd 5763 case PIPE_B:
ebfd86fd 5764 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5765 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5766 else
5767 cpt_enable_fdi_bc_bifurcation(dev);
5768
ebfd86fd 5769 break;
01a415fd 5770 case PIPE_C:
01a415fd
DV		 5771 cpt_enable_fdi_bc_bifurcation(dev);
5772
ebfd86fd 5773 break;
01a415fd
DV		 5774 default:
5775 BUG();
5776 }
5777}
5778
d4b1931c
PZ		 5779int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5780{
5781 /*
5782 * Account for spread spectrum to avoid
5783 * oversubscribing the link. Max center spread
5784 * is 2.5%; use 5% for safety's sake.
5785 */
5786 u32 bps = target_clock * bpp * 21 / 20;
5787 return bps / (link_bw * 8) + 1;
5788}
5789
7429e9d4 5790static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5791{
7429e9d4 5792 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5793}
5794
de13a2e3 5795static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5796 u32 *fp,
9a7c7890 5797 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5798{
de13a2e3 5799 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5800 struct drm_device *dev = crtc->dev;
5801 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5802 struct intel_encoder *intel_encoder;
5803 uint32_t dpll;
6cc5f341 5804 int factor, num_connectors = 0;
09ede541 5805 bool is_lvds = false, is_sdvo = false;
79e53945 5806
de13a2e3
PZ		 5807 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5808 switch (intel_encoder->type) {
79e53945
JB		 5809 case INTEL_OUTPUT_LVDS:
5810 is_lvds = true;
5811 break;
5812 case INTEL_OUTPUT_SDVO:
7d57382e 5813 case INTEL_OUTPUT_HDMI:
79e53945 5814 is_sdvo = true;
79e53945 5815 break;
79e53945 5816 }
43565a06 5817
c751ce4f 5818 num_connectors++;
79e53945 5819 }
79e53945 5820
c1858123 5821 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5822 factor = 21;
5823 if (is_lvds) {
5824 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5825 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5826 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5827 factor = 25;
09ede541 5828 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5829 factor = 20;
c1858123 5830
7429e9d4 5831 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5832 *fp |= FP_CB_TUNE;
2c07245f 5833
9a7c7890
DV		 5834 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5835 *fp2 |= FP_CB_TUNE;
5836
5eddb70b 5837 dpll = 0;
2c07245f 5838
a07d6787
EA		 5839 if (is_lvds)
5840 dpll |= DPLLB_MODE_LVDS;
5841 else
5842 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5843
ef1b460d
DV		 5844 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5845 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5846
5847 if (is_sdvo)
4a33e48d 5848 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5849 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5850 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5851
a07d6787 5852 /* compute bitmask from p1 value */
7429e9d4 5853 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5854 /* also FPA1 */
7429e9d4 5855 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5856
7429e9d4 5857 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5858 case 5:
5859 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5860 break;
5861 case 7:
5862 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5863 break;
5864 case 10:
5865 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5866 break;
5867 case 14:
5868 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5869 break;
79e53945
JB		 5870 }
5871
b4c09f3b 5872 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5873 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5874 else
5875 dpll |= PLL_REF_INPUT_DREFCLK;
5876
959e16d6 5877 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5878}
5879
5880static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5881 int x, int y,
5882 struct drm_framebuffer *fb)
5883{
5884 struct drm_device *dev = crtc->dev;
5885 struct drm_i915_private *dev_priv = dev->dev_private;
5886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5887 int pipe = intel_crtc->pipe;
5888 int plane = intel_crtc->plane;
5889 int num_connectors = 0;
5890 intel_clock_t clock, reduced_clock;
cbbab5bd 5891 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5892 bool ok, has_reduced_clock = false;
8b47047b 5893 bool is_lvds = false;
de13a2e3 5894 struct intel_encoder *encoder;
e2b78267 5895 struct intel_shared_dpll *pll;
de13a2e3 5896 int ret;
de13a2e3
PZ		 5897
5898 for_each_encoder_on_crtc(dev, crtc, encoder) {
5899 switch (encoder->type) {
5900 case INTEL_OUTPUT_LVDS:
5901 is_lvds = true;
5902 break;
de13a2e3
PZ		 5903 }
5904
5905 num_connectors++;
a07d6787 5906 }
79e53945 5907
5dc5298b
PZ		 5908 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5909 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5910
ff9a6750 5911 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5912 &has_reduced_clock, &reduced_clock);
ee9300bb 5913 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5914 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5915 return -EINVAL;
79e53945 5916 }
f47709a9
DV		 5917 /* Compat-code for transition, will disappear. */
5918 if (!intel_crtc->config.clock_set) {
5919 intel_crtc->config.dpll.n = clock.n;
5920 intel_crtc->config.dpll.m1 = clock.m1;
5921 intel_crtc->config.dpll.m2 = clock.m2;
5922 intel_crtc->config.dpll.p1 = clock.p1;
5923 intel_crtc->config.dpll.p2 = clock.p2;
5924 }
79e53945 5925
5dc5298b 5926 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5927 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5928 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5929 if (has_reduced_clock)
7429e9d4 5930 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5931
7429e9d4 5932 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5933 &fp, &reduced_clock,
5934 has_reduced_clock ? &fp2 : NULL);
5935
959e16d6 5936 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5937 intel_crtc->config.dpll_hw_state.fp0 = fp;
5938 if (has_reduced_clock)
5939 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5940 else
5941 intel_crtc->config.dpll_hw_state.fp1 = fp;
5942
b89a1d39 5943 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5944 if (pll == NULL) {
84f44ce7
VS		 5945 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5946 pipe_name(pipe));
4b645f14
JB		 5947 return -EINVAL;
5948 }
ee7b9f93 5949 } else
e72f9fbf 5950 intel_put_shared_dpll(intel_crtc);
79e53945 5951
03afc4a2
DV		 5952 if (intel_crtc->config.has_dp_encoder)
5953 intel_dp_set_m_n(intel_crtc);
79e53945 5954
bcd644e0
DV		 5955 if (is_lvds && has_reduced_clock && i915_powersave)
5956 intel_crtc->lowfreq_avail = true;
5957 else
5958 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5959
5960 if (intel_crtc->config.has_pch_encoder) {
5961 pll = intel_crtc_to_shared_dpll(intel_crtc);
5962
652c393a
JB		 5963 }
5964
8a654f3b 5965 intel_set_pipe_timings(intel_crtc);
5eddb70b 5966
ca3a0ff8 5967 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5968 intel_cpu_transcoder_set_m_n(intel_crtc,
5969 &intel_crtc->config.fdi_m_n);
5970 }
2c07245f 5971
ebfd86fd
DV		 5972 if (IS_IVYBRIDGE(dev))
5973 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5974
6ff93609 5975 ironlake_set_pipeconf(crtc);
79e53945 5976
a1f9e77e
PZ		 5977 /* Set up the display plane register */
5978 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5979 POSTING_READ(DSPCNTR(plane));
79e53945 5980
94352cf9 5981 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5982
1857e1da 5983 return ret;
79e53945
JB		 5984}
5985
eb14cb74
VS		 5986static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5987 struct intel_link_m_n *m_n)
5988{
5989 struct drm_device *dev = crtc->base.dev;
5990 struct drm_i915_private *dev_priv = dev->dev_private;
5991 enum pipe pipe = crtc->pipe;
5992
5993 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5994 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5995 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5996 & ~TU_SIZE_MASK;
5997 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5998 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5999 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6000}
6001
6002static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6003 enum transcoder transcoder,
6004 struct intel_link_m_n *m_n)
72419203
DV		 6005{
6006 struct drm_device *dev = crtc->base.dev;
6007 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6008 enum pipe pipe = crtc->pipe;
72419203 6009
eb14cb74
VS		 6010 if (INTEL_INFO(dev)->gen >= 5) {
6011 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6012 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6013 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6014 & ~TU_SIZE_MASK;
6015 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6016 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6017 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6018 } else {
6019 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6020 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6021 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6022 & ~TU_SIZE_MASK;
6023 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6024 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6025 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6026 }
6027}
6028
6029void intel_dp_get_m_n(struct intel_crtc *crtc,
6030 struct intel_crtc_config *pipe_config)
6031{
6032 if (crtc->config.has_pch_encoder)
6033 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6034 else
6035 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6036 &pipe_config->dp_m_n);
6037}
72419203 6038
eb14cb74
VS		 6039static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6040 struct intel_crtc_config *pipe_config)
6041{
6042 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6043 &pipe_config->fdi_m_n);
72419203
DV		 6044}
6045
2fa2fe9a
DV		 6046static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6047 struct intel_crtc_config *pipe_config)
6048{
6049 struct drm_device *dev = crtc->base.dev;
6050 struct drm_i915_private *dev_priv = dev->dev_private;
6051 uint32_t tmp;
6052
6053 tmp = I915_READ(PF_CTL(crtc->pipe));
6054
6055 if (tmp & PF_ENABLE) {
fd4daa9c 6056 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6057 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6058 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6059
6060 /* We currently do not free assignements of panel fitters on
6061 * ivb/hsw (since we don't use the higher upscaling modes which
6062 * differentiates them) so just WARN about this case for now. */
6063 if (IS_GEN7(dev)) {
6064 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6065 PF_PIPE_SEL_IVB(crtc->pipe));
6066 }
2fa2fe9a 6067 }
79e53945
JB		 6068}
6069
0e8ffe1b
DV		 6070static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6071 struct intel_crtc_config *pipe_config)
6072{
6073 struct drm_device *dev = crtc->base.dev;
6074 struct drm_i915_private *dev_priv = dev->dev_private;
6075 uint32_t tmp;
6076
e143a21c 6077 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6078 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6079
0e8ffe1b
DV		 6080 tmp = I915_READ(PIPECONF(crtc->pipe));
6081 if (!(tmp & PIPECONF_ENABLE))
6082 return false;
6083
42571aef
VS		 6084 switch (tmp & PIPECONF_BPC_MASK) {
6085 case PIPECONF_6BPC:
6086 pipe_config->pipe_bpp = 18;
6087 break;
6088 case PIPECONF_8BPC:
6089 pipe_config->pipe_bpp = 24;
6090 break;
6091 case PIPECONF_10BPC:
6092 pipe_config->pipe_bpp = 30;
6093 break;
6094 case PIPECONF_12BPC:
6095 pipe_config->pipe_bpp = 36;
6096 break;
6097 default:
6098 break;
6099 }
6100
ab9412ba 6101 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6102 struct intel_shared_dpll *pll;
6103
88adfff1
DV		 6104 pipe_config->has_pch_encoder = true;
6105
627eb5a3
DV		 6106 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6107 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6108 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6109
6110 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6111
c0d43d62 6112 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6113 pipe_config->shared_dpll =
6114 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6115 } else {
6116 tmp = I915_READ(PCH_DPLL_SEL);
6117 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6118 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6119 else
6120 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6121 }
66e985c0
DV		 6122
6123 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6124
6125 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6126 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6127
6128 tmp = pipe_config->dpll_hw_state.dpll;
6129 pipe_config->pixel_multiplier =
6130 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6131 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6132
6133 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6134 } else {
6135 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6136 }
6137
1bd1bd80
DV		 6138 intel_get_pipe_timings(crtc, pipe_config);
6139
2fa2fe9a
DV		 6140 ironlake_get_pfit_config(crtc, pipe_config);
6141
0e8ffe1b
DV		 6142 return true;
6143}
6144
be256dc7
PZ		 6145static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6146{
6147 struct drm_device *dev = dev_priv->dev;
6148 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6149 struct intel_crtc *crtc;
6150 unsigned long irqflags;
bd633a7c 6151 uint32_t val;
be256dc7
PZ		 6152
6153 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6154 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6155 pipe_name(crtc->pipe));
6156
6157 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6158 WARN(plls->spll_refcount, "SPLL enabled\n");
6159 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6160 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6161 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6162 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6163 "CPU PWM1 enabled\n");
6164 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6165 "CPU PWM2 enabled\n");
6166 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6167 "PCH PWM1 enabled\n");
6168 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6169 "Utility pin enabled\n");
6170 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6171
6172 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6173 val = I915_READ(DEIMR);
6174 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6175 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6176 val = I915_READ(SDEIMR);
bd633a7c 6177 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6178 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6179 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6180}
6181
6182/*
6183 * This function implements pieces of two sequences from BSpec:
6184 * - Sequence for display software to disable LCPLL
6185 * - Sequence for display software to allow package C8+
6186 * The steps implemented here are just the steps that actually touch the LCPLL
6187 * register. Callers should take care of disabling all the display engine
6188 * functions, doing the mode unset, fixing interrupts, etc.
6189 */
6ff58d53
PZ		 6190static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6191 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6192{
6193 uint32_t val;
6194
6195 assert_can_disable_lcpll(dev_priv);
6196
6197 val = I915_READ(LCPLL_CTL);
6198
6199 if (switch_to_fclk) {
6200 val |= LCPLL_CD_SOURCE_FCLK;
6201 I915_WRITE(LCPLL_CTL, val);
6202
6203 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6204 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6205 DRM_ERROR("Switching to FCLK failed\n");
6206
6207 val = I915_READ(LCPLL_CTL);
6208 }
6209
6210 val |= LCPLL_PLL_DISABLE;
6211 I915_WRITE(LCPLL_CTL, val);
6212 POSTING_READ(LCPLL_CTL);
6213
6214 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6215 DRM_ERROR("LCPLL still locked\n");
6216
6217 val = I915_READ(D_COMP);
6218 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6219 mutex_lock(&dev_priv->rps.hw_lock);
6220 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6221 DRM_ERROR("Failed to disable D_COMP\n");
6222 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6223 POSTING_READ(D_COMP);
6224 ndelay(100);
6225
6226 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6227 DRM_ERROR("D_COMP RCOMP still in progress\n");
6228
6229 if (allow_power_down) {
6230 val = I915_READ(LCPLL_CTL);
6231 val |= LCPLL_POWER_DOWN_ALLOW;
6232 I915_WRITE(LCPLL_CTL, val);
6233 POSTING_READ(LCPLL_CTL);
6234 }
6235}
6236
6237/*
6238 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6239 * source.
6240 */
6ff58d53 6241static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6242{
6243 uint32_t val;
6244
6245 val = I915_READ(LCPLL_CTL);
6246
6247 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6248 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6249 return;
6250
215733fa
PZ		 6251 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6252 * we'll hang the machine! */
6253 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6254
be256dc7
PZ		 6255 if (val & LCPLL_POWER_DOWN_ALLOW) {
6256 val &= ~LCPLL_POWER_DOWN_ALLOW;
6257 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6258 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6259 }
6260
6261 val = I915_READ(D_COMP);
6262 val |= D_COMP_COMP_FORCE;
6263 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6264 mutex_lock(&dev_priv->rps.hw_lock);
6265 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6266 DRM_ERROR("Failed to enable D_COMP\n");
6267 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6268 POSTING_READ(D_COMP);
be256dc7
PZ		 6269
6270 val = I915_READ(LCPLL_CTL);
6271 val &= ~LCPLL_PLL_DISABLE;
6272 I915_WRITE(LCPLL_CTL, val);
6273
6274 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6275 DRM_ERROR("LCPLL not locked yet\n");
6276
6277 if (val & LCPLL_CD_SOURCE_FCLK) {
6278 val = I915_READ(LCPLL_CTL);
6279 val &= ~LCPLL_CD_SOURCE_FCLK;
6280 I915_WRITE(LCPLL_CTL, val);
6281
6282 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6283 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6284 DRM_ERROR("Switching back to LCPLL failed\n");
6285 }
215733fa
PZ		 6286
6287 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6288}
6289
c67a470b
PZ		 6290void hsw_enable_pc8_work(struct work_struct *__work)
6291{
6292 struct drm_i915_private *dev_priv =
6293 container_of(to_delayed_work(__work), struct drm_i915_private,
6294 pc8.enable_work);
6295 struct drm_device *dev = dev_priv->dev;
6296 uint32_t val;
6297
6298 if (dev_priv->pc8.enabled)
6299 return;
6300
6301 DRM_DEBUG_KMS("Enabling package C8+\n");
6302
6303 dev_priv->pc8.enabled = true;
6304
6305 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6306 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6307 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6308 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6309 }
6310
6311 lpt_disable_clkout_dp(dev);
6312 hsw_pc8_disable_interrupts(dev);
6313 hsw_disable_lcpll(dev_priv, true, true);
6314}
6315
6316static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6317{
6318 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6319 WARN(dev_priv->pc8.disable_count < 1,
6320 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6321
6322 dev_priv->pc8.disable_count--;
6323 if (dev_priv->pc8.disable_count != 0)
6324 return;
6325
6326 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6327 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6328}
6329
6330static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6331{
6332 struct drm_device *dev = dev_priv->dev;
6333 uint32_t val;
6334
6335 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6336 WARN(dev_priv->pc8.disable_count < 0,
6337 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6338
6339 dev_priv->pc8.disable_count++;
6340 if (dev_priv->pc8.disable_count != 1)
6341 return;
6342
6343 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6344 if (!dev_priv->pc8.enabled)
6345 return;
6346
6347 DRM_DEBUG_KMS("Disabling package C8+\n");
6348
6349 hsw_restore_lcpll(dev_priv);
6350 hsw_pc8_restore_interrupts(dev);
6351 lpt_init_pch_refclk(dev);
6352
6353 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6354 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6355 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6356 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6357 }
6358
6359 intel_prepare_ddi(dev);
6360 i915_gem_init_swizzling(dev);
6361 mutex_lock(&dev_priv->rps.hw_lock);
6362 gen6_update_ring_freq(dev);
6363 mutex_unlock(&dev_priv->rps.hw_lock);
6364 dev_priv->pc8.enabled = false;
6365}
6366
6367void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6368{
6369 mutex_lock(&dev_priv->pc8.lock);
6370 __hsw_enable_package_c8(dev_priv);
6371 mutex_unlock(&dev_priv->pc8.lock);
6372}
6373
6374void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6375{
6376 mutex_lock(&dev_priv->pc8.lock);
6377 __hsw_disable_package_c8(dev_priv);
6378 mutex_unlock(&dev_priv->pc8.lock);
6379}
6380
6381static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6382{
6383 struct drm_device *dev = dev_priv->dev;
6384 struct intel_crtc *crtc;
6385 uint32_t val;
6386
6387 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6388 if (crtc->base.enabled)
6389 return false;
6390
6391 /* This case is still possible since we have the i915.disable_power_well
6392 * parameter and also the KVMr or something else might be requesting the
6393 * power well. */
6394 val = I915_READ(HSW_PWR_WELL_DRIVER);
6395 if (val != 0) {
6396 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6397 return false;
6398 }
6399
6400 return true;
6401}
6402
6403/* Since we're called from modeset_global_resources there's no way to
6404 * symmetrically increase and decrease the refcount, so we use
6405 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6406 * or not.
6407 */
6408static void hsw_update_package_c8(struct drm_device *dev)
6409{
6410 struct drm_i915_private *dev_priv = dev->dev_private;
6411 bool allow;
6412
6413 if (!i915_enable_pc8)
6414 return;
6415
6416 mutex_lock(&dev_priv->pc8.lock);
6417
6418 allow = hsw_can_enable_package_c8(dev_priv);
6419
6420 if (allow == dev_priv->pc8.requirements_met)
6421 goto done;
6422
6423 dev_priv->pc8.requirements_met = allow;
6424
6425 if (allow)
6426 __hsw_enable_package_c8(dev_priv);
6427 else
6428 __hsw_disable_package_c8(dev_priv);
6429
6430done:
6431 mutex_unlock(&dev_priv->pc8.lock);
6432}
6433
6434static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6435{
6436 if (!dev_priv->pc8.gpu_idle) {
6437 dev_priv->pc8.gpu_idle = true;
6438 hsw_enable_package_c8(dev_priv);
6439 }
6440}
6441
6442static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6443{
6444 if (dev_priv->pc8.gpu_idle) {
6445 dev_priv->pc8.gpu_idle = false;
6446 hsw_disable_package_c8(dev_priv);
6447 }
be256dc7
PZ		 6448}
6449
d6dd9eb1
DV		 6450static void haswell_modeset_global_resources(struct drm_device *dev)
6451{
d6dd9eb1
DV		 6452 bool enable = false;
6453 struct intel_crtc *crtc;
d6dd9eb1
DV		 6454
6455 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6456 if (!crtc->base.enabled)
6457 continue;
d6dd9eb1 6458
fd4daa9c 6459 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6460 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6461 enable = true;
6462 }
6463
d6dd9eb1 6464 intel_set_power_well(dev, enable);
c67a470b
PZ		 6465
6466 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6467}
6468
09b4ddf9 6469static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6470 int x, int y,
6471 struct drm_framebuffer *fb)
6472{
6473 struct drm_device *dev = crtc->dev;
6474 struct drm_i915_private *dev_priv = dev->dev_private;
6475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6476 int plane = intel_crtc->plane;
09b4ddf9 6477 int ret;
09b4ddf9 6478
ff9a6750 6479 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6480 return -EINVAL;
6481
03afc4a2
DV		 6482 if (intel_crtc->config.has_dp_encoder)
6483 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6484
6485 intel_crtc->lowfreq_avail = false;
09b4ddf9 6486
8a654f3b 6487 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6488
ca3a0ff8 6489 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6490 intel_cpu_transcoder_set_m_n(intel_crtc,
6491 &intel_crtc->config.fdi_m_n);
6492 }
09b4ddf9 6493
6ff93609 6494 haswell_set_pipeconf(crtc);
09b4ddf9 6495
50f3b016 6496 intel_set_pipe_csc(crtc);
86d3efce 6497
09b4ddf9 6498 /* Set up the display plane register */
86d3efce 6499 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6500 POSTING_READ(DSPCNTR(plane));
6501
6502 ret = intel_pipe_set_base(crtc, x, y, fb);
6503
1f803ee5 6504 return ret;
79e53945
JB		 6505}
6506
0e8ffe1b
DV		 6507static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6508 struct intel_crtc_config *pipe_config)
6509{
6510 struct drm_device *dev = crtc->base.dev;
6511 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6512 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6513 uint32_t tmp;
6514
e143a21c 6515 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6516 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6517
eccb140b
DV		 6518 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6519 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6520 enum pipe trans_edp_pipe;
6521 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6522 default:
6523 WARN(1, "unknown pipe linked to edp transcoder\n");
6524 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6525 case TRANS_DDI_EDP_INPUT_A_ON:
6526 trans_edp_pipe = PIPE_A;
6527 break;
6528 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6529 trans_edp_pipe = PIPE_B;
6530 break;
6531 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6532 trans_edp_pipe = PIPE_C;
6533 break;
6534 }
6535
6536 if (trans_edp_pipe == crtc->pipe)
6537 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6538 }
6539
b97186f0 6540 if (!intel_display_power_enabled(dev,
eccb140b 6541 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6542 return false;
6543
eccb140b 6544 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6545 if (!(tmp & PIPECONF_ENABLE))
6546 return false;
6547
88adfff1 6548 /*
f196e6be 6549 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6550 * DDI E. So just check whether this pipe is wired to DDI E and whether
6551 * the PCH transcoder is on.
6552 */
eccb140b 6553 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6554 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6555 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6556 pipe_config->has_pch_encoder = true;
6557
627eb5a3
DV		 6558 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6559 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6560 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6561
6562 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6563 }
6564
1bd1bd80
DV		 6565 intel_get_pipe_timings(crtc, pipe_config);
6566
2fa2fe9a
DV		 6567 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6568 if (intel_display_power_enabled(dev, pfit_domain))
6569 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6570
42db64ef
PZ		 6571 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6572 (I915_READ(IPS_CTL) & IPS_ENABLE);
6573
6c49f241
DV		 6574 pipe_config->pixel_multiplier = 1;
6575
0e8ffe1b
DV		 6576 return true;
6577}
6578
f564048e 6579static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6580 int x, int y,
94352cf9 6581 struct drm_framebuffer *fb)
f564048e
EA		 6582{
6583 struct drm_device *dev = crtc->dev;
6584 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6585 struct intel_encoder *encoder;
0b701d27 6586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6587 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6588 int pipe = intel_crtc->pipe;
f564048e
EA		 6589 int ret;
6590
0b701d27 6591 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6592
b8cecdf5
DV		 6593 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6594
79e53945 6595 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6596
9256aa19
DV		 6597 if (ret != 0)
6598 return ret;
6599
6600 for_each_encoder_on_crtc(dev, crtc, encoder) {
6601 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6602 encoder->base.base.id,
6603 drm_get_encoder_name(&encoder->base),
6604 mode->base.id, mode->name);
36f2d1f1 6605 encoder->mode_set(encoder);
9256aa19
DV		 6606 }
6607
6608 return 0;
79e53945
JB		 6609}
6610
3a9627f4
WF		 6611static bool intel_eld_uptodate(struct drm_connector *connector,
6612 int reg_eldv, uint32_t bits_eldv,
6613 int reg_elda, uint32_t bits_elda,
6614 int reg_edid)
6615{
6616 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6617 uint8_t *eld = connector->eld;
6618 uint32_t i;
6619
6620 i = I915_READ(reg_eldv);
6621 i &= bits_eldv;
6622
6623 if (!eld[0])
6624 return !i;
6625
6626 if (!i)
6627 return false;
6628
6629 i = I915_READ(reg_elda);
6630 i &= ~bits_elda;
6631 I915_WRITE(reg_elda, i);
6632
6633 for (i = 0; i < eld[2]; i++)
6634 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6635 return false;
6636
6637 return true;
6638}
6639
e0dac65e
WF		 6640static void g4x_write_eld(struct drm_connector *connector,
6641 struct drm_crtc *crtc)
6642{
6643 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6644 uint8_t *eld = connector->eld;
6645 uint32_t eldv;
6646 uint32_t len;
6647 uint32_t i;
6648
6649 i = I915_READ(G4X_AUD_VID_DID);
6650
6651 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6652 eldv = G4X_ELDV_DEVCL_DEVBLC;
6653 else
6654 eldv = G4X_ELDV_DEVCTG;
6655
3a9627f4
WF		 6656 if (intel_eld_uptodate(connector,
6657 G4X_AUD_CNTL_ST, eldv,
6658 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6659 G4X_HDMIW_HDMIEDID))
6660 return;
6661
e0dac65e
WF		 6662 i = I915_READ(G4X_AUD_CNTL_ST);
6663 i &= ~(eldv | G4X_ELD_ADDR);
6664 len = (i >> 9) & 0x1f; /* ELD buffer size */
6665 I915_WRITE(G4X_AUD_CNTL_ST, i);
6666
6667 if (!eld[0])
6668 return;
6669
6670 len = min_t(uint8_t, eld[2], len);
6671 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6672 for (i = 0; i < len; i++)
6673 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6674
6675 i = I915_READ(G4X_AUD_CNTL_ST);
6676 i |= eldv;
6677 I915_WRITE(G4X_AUD_CNTL_ST, i);
6678}
6679
83358c85
WX		 6680static void haswell_write_eld(struct drm_connector *connector,
6681 struct drm_crtc *crtc)
6682{
6683 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6684 uint8_t *eld = connector->eld;
6685 struct drm_device *dev = crtc->dev;
7b9f35a6 6686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6687 uint32_t eldv;
6688 uint32_t i;
6689 int len;
6690 int pipe = to_intel_crtc(crtc)->pipe;
6691 int tmp;
6692
6693 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6694 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6695 int aud_config = HSW_AUD_CFG(pipe);
6696 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6697
6698
6699 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6700
6701 /* Audio output enable */
6702 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6703 tmp = I915_READ(aud_cntrl_st2);
6704 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6705 I915_WRITE(aud_cntrl_st2, tmp);
6706
6707 /* Wait for 1 vertical blank */
6708 intel_wait_for_vblank(dev, pipe);
6709
6710 /* Set ELD valid state */
6711 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6712 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6713 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6714 I915_WRITE(aud_cntrl_st2, tmp);
6715 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6716 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6717
6718 /* Enable HDMI mode */
6719 tmp = I915_READ(aud_config);
7e7cb34f 6720 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6721 /* clear N_programing_enable and N_value_index */
6722 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6723 I915_WRITE(aud_config, tmp);
6724
6725 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6726
6727 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6728 intel_crtc->eld_vld = true;
83358c85
WX		 6729
6730 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6731 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6732 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6733 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6734 } else
6735 I915_WRITE(aud_config, 0);
6736
6737 if (intel_eld_uptodate(connector,
6738 aud_cntrl_st2, eldv,
6739 aud_cntl_st, IBX_ELD_ADDRESS,
6740 hdmiw_hdmiedid))
6741 return;
6742
6743 i = I915_READ(aud_cntrl_st2);
6744 i &= ~eldv;
6745 I915_WRITE(aud_cntrl_st2, i);
6746
6747 if (!eld[0])
6748 return;
6749
6750 i = I915_READ(aud_cntl_st);
6751 i &= ~IBX_ELD_ADDRESS;
6752 I915_WRITE(aud_cntl_st, i);
6753 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6754 DRM_DEBUG_DRIVER("port num:%d\n", i);
6755
6756 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6757 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6758 for (i = 0; i < len; i++)
6759 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6760
6761 i = I915_READ(aud_cntrl_st2);
6762 i |= eldv;
6763 I915_WRITE(aud_cntrl_st2, i);
6764
6765}
6766
e0dac65e
WF		 6767static void ironlake_write_eld(struct drm_connector *connector,
6768 struct drm_crtc *crtc)
6769{
6770 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6771 uint8_t *eld = connector->eld;
6772 uint32_t eldv;
6773 uint32_t i;
6774 int len;
6775 int hdmiw_hdmiedid;
b6daa025 6776 int aud_config;
e0dac65e
WF		 6777 int aud_cntl_st;
6778 int aud_cntrl_st2;
9b138a83 6779 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6780
b3f33cbf 6781 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6782 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6783 aud_config = IBX_AUD_CFG(pipe);
6784 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6785 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6786 } else {
9b138a83
WX		 6787 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6788 aud_config = CPT_AUD_CFG(pipe);
6789 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6790 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6791 }
6792
9b138a83 6793 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6794
6795 i = I915_READ(aud_cntl_st);
9b138a83 6796 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6797 if (!i) {
6798 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6799 /* operate blindly on all ports */
1202b4c6
WF		 6800 eldv = IBX_ELD_VALIDB;
6801 eldv |= IBX_ELD_VALIDB << 4;
6802 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6803 } else {
2582a850 6804 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6805 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6806 }
6807
3a9627f4
WF		 6808 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6809 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6810 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6811 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6812 } else
6813 I915_WRITE(aud_config, 0);
e0dac65e 6814
3a9627f4
WF		 6815 if (intel_eld_uptodate(connector,
6816 aud_cntrl_st2, eldv,
6817 aud_cntl_st, IBX_ELD_ADDRESS,
6818 hdmiw_hdmiedid))
6819 return;
6820
e0dac65e
WF		 6821 i = I915_READ(aud_cntrl_st2);
6822 i &= ~eldv;
6823 I915_WRITE(aud_cntrl_st2, i);
6824
6825 if (!eld[0])
6826 return;
6827
e0dac65e 6828 i = I915_READ(aud_cntl_st);
1202b4c6 6829 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6830 I915_WRITE(aud_cntl_st, i);
6831
6832 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6833 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6834 for (i = 0; i < len; i++)
6835 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6836
6837 i = I915_READ(aud_cntrl_st2);
6838 i |= eldv;
6839 I915_WRITE(aud_cntrl_st2, i);
6840}
6841
6842void intel_write_eld(struct drm_encoder *encoder,
6843 struct drm_display_mode *mode)
6844{
6845 struct drm_crtc *crtc = encoder->crtc;
6846 struct drm_connector *connector;
6847 struct drm_device *dev = encoder->dev;
6848 struct drm_i915_private *dev_priv = dev->dev_private;
6849
6850 connector = drm_select_eld(encoder, mode);
6851 if (!connector)
6852 return;
6853
6854 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6855 connector->base.id,
6856 drm_get_connector_name(connector),
6857 connector->encoder->base.id,
6858 drm_get_encoder_name(connector->encoder));
6859
6860 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6861
6862 if (dev_priv->display.write_eld)
6863 dev_priv->display.write_eld(connector, crtc);
6864}
6865
560b85bb
CW		 6866static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6867{
6868 struct drm_device *dev = crtc->dev;
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6871 bool visible = base != 0;
6872 u32 cntl;
6873
6874 if (intel_crtc->cursor_visible == visible)
6875 return;
6876
9db4a9c7 6877 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6878 if (visible) {
6879 /* On these chipsets we can only modify the base whilst
6880 * the cursor is disabled.
6881 */
9db4a9c7 6882 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6883
6884 cntl &= ~(CURSOR_FORMAT_MASK);
6885 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6886 cntl |= CURSOR_ENABLE |
6887 CURSOR_GAMMA_ENABLE |
6888 CURSOR_FORMAT_ARGB;
6889 } else
6890 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6891 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6892
6893 intel_crtc->cursor_visible = visible;
6894}
6895
6896static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6897{
6898 struct drm_device *dev = crtc->dev;
6899 struct drm_i915_private *dev_priv = dev->dev_private;
6900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6901 int pipe = intel_crtc->pipe;
6902 bool visible = base != 0;
6903
6904 if (intel_crtc->cursor_visible != visible) {
548f245b 6905 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6906 if (base) {
6907 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6908 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6909 cntl |= pipe << 28; /* Connect to correct pipe */
6910 } else {
6911 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6912 cntl |= CURSOR_MODE_DISABLE;
6913 }
9db4a9c7 6914 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6915
6916 intel_crtc->cursor_visible = visible;
6917 }
6918 /* and commit changes on next vblank */
9db4a9c7 6919 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6920}
6921
65a21cd6
JB		 6922static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6923{
6924 struct drm_device *dev = crtc->dev;
6925 struct drm_i915_private *dev_priv = dev->dev_private;
6926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6927 int pipe = intel_crtc->pipe;
6928 bool visible = base != 0;
6929
6930 if (intel_crtc->cursor_visible != visible) {
6931 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6932 if (base) {
6933 cntl &= ~CURSOR_MODE;
6934 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6935 } else {
6936 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6937 cntl |= CURSOR_MODE_DISABLE;
6938 }
1f5d76db 6939 if (IS_HASWELL(dev)) {
86d3efce 6940 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6941 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6942 }
65a21cd6
JB		 6943 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6944
6945 intel_crtc->cursor_visible = visible;
6946 }
6947 /* and commit changes on next vblank */
6948 I915_WRITE(CURBASE_IVB(pipe), base);
6949}
6950
cda4b7d3 6951/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6952static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6953 bool on)
cda4b7d3
CW		 6954{
6955 struct drm_device *dev = crtc->dev;
6956 struct drm_i915_private *dev_priv = dev->dev_private;
6957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6958 int pipe = intel_crtc->pipe;
6959 int x = intel_crtc->cursor_x;
6960 int y = intel_crtc->cursor_y;
d6e4db15 6961 u32 base = 0, pos = 0;
cda4b7d3
CW		 6962 bool visible;
6963
d6e4db15 6964 if (on)
cda4b7d3 6965 base = intel_crtc->cursor_addr;
cda4b7d3 6966
d6e4db15
VS		 6967 if (x >= intel_crtc->config.pipe_src_w)
6968 base = 0;
6969
6970 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 6971 base = 0;
6972
6973 if (x < 0) {
efc9064e 6974 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 6975 base = 0;
6976
6977 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6978 x = -x;
6979 }
6980 pos |= x << CURSOR_X_SHIFT;
6981
6982 if (y < 0) {
efc9064e 6983 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 6984 base = 0;
6985
6986 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6987 y = -y;
6988 }
6989 pos |= y << CURSOR_Y_SHIFT;
6990
6991 visible = base != 0;
560b85bb 6992 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6993 return;
6994
0cd83aa9 6995 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6996 I915_WRITE(CURPOS_IVB(pipe), pos);
6997 ivb_update_cursor(crtc, base);
6998 } else {
6999 I915_WRITE(CURPOS(pipe), pos);
7000 if (IS_845G(dev) || IS_I865G(dev))
7001 i845_update_cursor(crtc, base);
7002 else
7003 i9xx_update_cursor(crtc, base);
7004 }
cda4b7d3
CW		 7005}
7006
79e53945 7007static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7008 struct drm_file *file,
79e53945
JB		 7009 uint32_t handle,
7010 uint32_t width, uint32_t height)
7011{
7012 struct drm_device *dev = crtc->dev;
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7015 struct drm_i915_gem_object *obj;
cda4b7d3 7016 uint32_t addr;
3f8bc370 7017 int ret;
79e53945 7018
79e53945
JB		 7019 /* if we want to turn off the cursor ignore width and height */
7020 if (!handle) {
28c97730 7021 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7022 addr = 0;
05394f39 7023 obj = NULL;
5004417d 7024 mutex_lock(&dev->struct_mutex);
3f8bc370 7025 goto finish;
79e53945
JB		 7026 }
7027
7028 /* Currently we only support 64x64 cursors */
7029 if (width != 64 || height != 64) {
7030 DRM_ERROR("we currently only support 64x64 cursors\n");
7031 return -EINVAL;
7032 }
7033
05394f39 7034 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7035 if (&obj->base == NULL)
79e53945
JB		 7036 return -ENOENT;
7037
05394f39 7038 if (obj->base.size < width * height * 4) {
79e53945 7039 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7040 ret = -ENOMEM;
7041 goto fail;
79e53945
JB		 7042 }
7043
71acb5eb 7044 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7045 mutex_lock(&dev->struct_mutex);
b295d1b6 7046 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7047 unsigned alignment;
7048
d9e86c0e
CW		 7049 if (obj->tiling_mode) {
7050 DRM_ERROR("cursor cannot be tiled\n");
7051 ret = -EINVAL;
7052 goto fail_locked;
7053 }
7054
693db184
CW		 7055 /* Note that the w/a also requires 2 PTE of padding following
7056 * the bo. We currently fill all unused PTE with the shadow
7057 * page and so we should always have valid PTE following the
7058 * cursor preventing the VT-d warning.
7059 */
7060 alignment = 0;
7061 if (need_vtd_wa(dev))
7062 alignment = 64*1024;
7063
7064 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7065 if (ret) {
7066 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7067 goto fail_locked;
e7b526bb
CW		 7068 }
7069
d9e86c0e
CW		 7070 ret = i915_gem_object_put_fence(obj);
7071 if (ret) {
2da3b9b9 7072 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7073 goto fail_unpin;
7074 }
7075
f343c5f6 7076 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7077 } else {
6eeefaf3 7078 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7079 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7080 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7081 align);
71acb5eb
DA		 7082 if (ret) {
7083 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7084 goto fail_locked;
71acb5eb 7085 }
05394f39 7086 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7087 }
7088
a6c45cf0 7089 if (IS_GEN2(dev))
14b60391
JB		 7090 I915_WRITE(CURSIZE, (height << 12) | width);
7091
3f8bc370 7092 finish:
3f8bc370 7093 if (intel_crtc->cursor_bo) {
b295d1b6 7094 if (dev_priv->info->cursor_needs_physical) {
05394f39 7095 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7096 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7097 } else
cc98b413 7098 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7099 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7100 }
80824003 7101
7f9872e0 7102 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7103
7104 intel_crtc->cursor_addr = addr;
05394f39 7105 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7106 intel_crtc->cursor_width = width;
7107 intel_crtc->cursor_height = height;
7108
f2f5f771
VS		 7109 if (intel_crtc->active)
7110 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7111
79e53945 7112 return 0;
e7b526bb 7113fail_unpin:
cc98b413 7114 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7115fail_locked:
34b8686e 7116 mutex_unlock(&dev->struct_mutex);
bc9025bd 7117fail:
05394f39 7118 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7119 return ret;
79e53945
JB		 7120}
7121
7122static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7123{
79e53945 7124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7125
cda4b7d3
CW		 7126 intel_crtc->cursor_x = x;
7127 intel_crtc->cursor_y = y;
652c393a 7128
f2f5f771
VS		 7129 if (intel_crtc->active)
7130 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7131
7132 return 0;
b8c00ac5
DA		 7133}
7134
79e53945 7135static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7136 u16 *blue, uint32_t start, uint32_t size)
79e53945 7137{
7203425a 7138 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7140
7203425a 7141 for (i = start; i < end; i++) {
79e53945
JB		 7142 intel_crtc->lut_r[i] = red[i] >> 8;
7143 intel_crtc->lut_g[i] = green[i] >> 8;
7144 intel_crtc->lut_b[i] = blue[i] >> 8;
7145 }
7146
7147 intel_crtc_load_lut(crtc);
7148}
7149
79e53945
JB		 7150/* VESA 640x480x72Hz mode to set on the pipe */
7151static struct drm_display_mode load_detect_mode = {
7152 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7153 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7154};
7155
d2dff872
CW		 7156static struct drm_framebuffer *
7157intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7158 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7159 struct drm_i915_gem_object *obj)
7160{
7161 struct intel_framebuffer *intel_fb;
7162 int ret;
7163
7164 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7165 if (!intel_fb) {
7166 drm_gem_object_unreference_unlocked(&obj->base);
7167 return ERR_PTR(-ENOMEM);
7168 }
7169
7170 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7171 if (ret) {
7172 drm_gem_object_unreference_unlocked(&obj->base);
7173 kfree(intel_fb);
7174 return ERR_PTR(ret);
7175 }
7176
7177 return &intel_fb->base;
7178}
7179
7180static u32
7181intel_framebuffer_pitch_for_width(int width, int bpp)
7182{
7183 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7184 return ALIGN(pitch, 64);
7185}
7186
7187static u32
7188intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7189{
7190 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7191 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7192}
7193
7194static struct drm_framebuffer *
7195intel_framebuffer_create_for_mode(struct drm_device *dev,
7196 struct drm_display_mode *mode,
7197 int depth, int bpp)
7198{
7199 struct drm_i915_gem_object *obj;
0fed39bd 7200 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7201
7202 obj = i915_gem_alloc_object(dev,
7203 intel_framebuffer_size_for_mode(mode, bpp));
7204 if (obj == NULL)
7205 return ERR_PTR(-ENOMEM);
7206
7207 mode_cmd.width = mode->hdisplay;
7208 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7209 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7210 bpp);
5ca0c34a 7211 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7212
7213 return intel_framebuffer_create(dev, &mode_cmd, obj);
7214}
7215
7216static struct drm_framebuffer *
7217mode_fits_in_fbdev(struct drm_device *dev,
7218 struct drm_display_mode *mode)
7219{
7220 struct drm_i915_private *dev_priv = dev->dev_private;
7221 struct drm_i915_gem_object *obj;
7222 struct drm_framebuffer *fb;
7223
7224 if (dev_priv->fbdev == NULL)
7225 return NULL;
7226
7227 obj = dev_priv->fbdev->ifb.obj;
7228 if (obj == NULL)
7229 return NULL;
7230
7231 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7232 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7233 fb->bits_per_pixel))
d2dff872
CW		 7234 return NULL;
7235
01f2c773 7236 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7237 return NULL;
7238
7239 return fb;
7240}
7241
d2434ab7 7242bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7243 struct drm_display_mode *mode,
8261b191 7244 struct intel_load_detect_pipe *old)
79e53945
JB		 7245{
7246 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7247 struct intel_encoder *intel_encoder =
7248 intel_attached_encoder(connector);
79e53945 7249 struct drm_crtc *possible_crtc;
4ef69c7a 7250 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7251 struct drm_crtc *crtc = NULL;
7252 struct drm_device *dev = encoder->dev;
94352cf9 7253 struct drm_framebuffer *fb;
79e53945
JB		 7254 int i = -1;
7255
d2dff872
CW		 7256 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7257 connector->base.id, drm_get_connector_name(connector),
7258 encoder->base.id, drm_get_encoder_name(encoder));
7259
79e53945
JB		 7260 /*
7261 * Algorithm gets a little messy:
7a5e4805 7262 *
79e53945
JB		 7263 * - if the connector already has an assigned crtc, use it (but make
7264 * sure it's on first)
7a5e4805 7265 *
79e53945
JB		 7266 * - try to find the first unused crtc that can drive this connector,
7267 * and use that if we find one
79e53945
JB		 7268 */
7269
7270 /* See if we already have a CRTC for this connector */
7271 if (encoder->crtc) {
7272 crtc = encoder->crtc;
8261b191 7273
7b24056b
DV		 7274 mutex_lock(&crtc->mutex);
7275
24218aac 7276 old->dpms_mode = connector->dpms;
8261b191
CW		 7277 old->load_detect_temp = false;
7278
7279 /* Make sure the crtc and connector are running */
24218aac
DV		 7280 if (connector->dpms != DRM_MODE_DPMS_ON)
7281 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7282
7173188d 7283 return true;
79e53945
JB		 7284 }
7285
7286 /* Find an unused one (if possible) */
7287 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7288 i++;
7289 if (!(encoder->possible_crtcs & (1 << i)))
7290 continue;
7291 if (!possible_crtc->enabled) {
7292 crtc = possible_crtc;
7293 break;
7294 }
79e53945
JB		 7295 }
7296
7297 /*
7298 * If we didn't find an unused CRTC, don't use any.
7299 */
7300 if (!crtc) {
7173188d
CW		 7301 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7302 return false;
79e53945
JB		 7303 }
7304
7b24056b 7305 mutex_lock(&crtc->mutex);
fc303101
DV		 7306 intel_encoder->new_crtc = to_intel_crtc(crtc);
7307 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7308
7309 intel_crtc = to_intel_crtc(crtc);
24218aac 7310 old->dpms_mode = connector->dpms;
8261b191 7311 old->load_detect_temp = true;
d2dff872 7312 old->release_fb = NULL;
79e53945 7313
6492711d
CW		 7314 if (!mode)
7315 mode = &load_detect_mode;
79e53945 7316
d2dff872
CW		 7317 /* We need a framebuffer large enough to accommodate all accesses
7318 * that the plane may generate whilst we perform load detection.
7319 * We can not rely on the fbcon either being present (we get called
7320 * during its initialisation to detect all boot displays, or it may
7321 * not even exist) or that it is large enough to satisfy the
7322 * requested mode.
7323 */
94352cf9
DV		 7324 fb = mode_fits_in_fbdev(dev, mode);
7325 if (fb == NULL) {
d2dff872 7326 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7327 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7328 old->release_fb = fb;
d2dff872
CW		 7329 } else
7330 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7331 if (IS_ERR(fb)) {
d2dff872 7332 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7333 mutex_unlock(&crtc->mutex);
0e8b3d3e 7334 return false;
79e53945 7335 }
79e53945 7336
c0c36b94 7337 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7338 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7339 if (old->release_fb)
7340 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7341 mutex_unlock(&crtc->mutex);
0e8b3d3e 7342 return false;
79e53945 7343 }
7173188d 7344
79e53945 7345 /* let the connector get through one full cycle before testing */
9d0498a2 7346 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7347 return true;
79e53945
JB		 7348}
7349
d2434ab7 7350void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7351 struct intel_load_detect_pipe *old)
79e53945 7352{
d2434ab7
DV		 7353 struct intel_encoder *intel_encoder =
7354 intel_attached_encoder(connector);
4ef69c7a 7355 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7356 struct drm_crtc *crtc = encoder->crtc;
79e53945 7357
d2dff872
CW		 7358 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7359 connector->base.id, drm_get_connector_name(connector),
7360 encoder->base.id, drm_get_encoder_name(encoder));
7361
8261b191 7362 if (old->load_detect_temp) {
fc303101
DV		 7363 to_intel_connector(connector)->new_encoder = NULL;
7364 intel_encoder->new_crtc = NULL;
7365 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7366
36206361
DV		 7367 if (old->release_fb) {
7368 drm_framebuffer_unregister_private(old->release_fb);
7369 drm_framebuffer_unreference(old->release_fb);
7370 }
d2dff872 7371
67c96400 7372 mutex_unlock(&crtc->mutex);
0622a53c 7373 return;
79e53945
JB		 7374 }
7375
c751ce4f 7376 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7377 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7378 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7379
7380 mutex_unlock(&crtc->mutex);
79e53945
JB		 7381}
7382
da4a1efa
VS		 7383static int i9xx_pll_refclk(struct drm_device *dev,
7384 const struct intel_crtc_config *pipe_config)
7385{
7386 struct drm_i915_private *dev_priv = dev->dev_private;
7387 u32 dpll = pipe_config->dpll_hw_state.dpll;
7388
7389 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7390 return dev_priv->vbt.lvds_ssc_freq * 1000;
7391 else if (HAS_PCH_SPLIT(dev))
7392 return 120000;
7393 else if (!IS_GEN2(dev))
7394 return 96000;
7395 else
7396 return 48000;
7397}
7398
79e53945 7399/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7400static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7401 struct intel_crtc_config *pipe_config)
79e53945 7402{
f1f644dc 7403 struct drm_device *dev = crtc->base.dev;
79e53945 7404 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7405 int pipe = pipe_config->cpu_transcoder;
293623f7 7406 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7407 u32 fp;
7408 intel_clock_t clock;
da4a1efa 7409 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7410
7411 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7412 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7413 else
293623f7 7414 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7415
7416 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7417 if (IS_PINEVIEW(dev)) {
7418 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7419 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7420 } else {
7421 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7422 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7423 }
7424
a6c45cf0 7425 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7426 if (IS_PINEVIEW(dev))
7427 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7428 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7429 else
7430 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7431 DPLL_FPA01_P1_POST_DIV_SHIFT);
7432
7433 switch (dpll & DPLL_MODE_MASK) {
7434 case DPLLB_MODE_DAC_SERIAL:
7435 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7436 5 : 10;
7437 break;
7438 case DPLLB_MODE_LVDS:
7439 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7440 7 : 14;
7441 break;
7442 default:
28c97730 7443 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7444 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7445 return;
79e53945
JB		 7446 }
7447
ac58c3f0 7448 if (IS_PINEVIEW(dev))
da4a1efa 7449 pineview_clock(refclk, &clock);
ac58c3f0 7450 else
da4a1efa 7451 i9xx_clock(refclk, &clock);
79e53945
JB		 7452 } else {
7453 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7454
7455 if (is_lvds) {
7456 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7457 DPLL_FPA01_P1_POST_DIV_SHIFT);
7458 clock.p2 = 14;
79e53945
JB		 7459 } else {
7460 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7461 clock.p1 = 2;
7462 else {
7463 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7464 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7465 }
7466 if (dpll & PLL_P2_DIVIDE_BY_4)
7467 clock.p2 = 4;
7468 else
7469 clock.p2 = 2;
79e53945 7470 }
da4a1efa
VS		 7471
7472 i9xx_clock(refclk, &clock);
79e53945
JB		 7473 }
7474
18442d08
VS		 7475 /*
7476 * This value includes pixel_multiplier. We will use
241bfc38 7477 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7478 * encoder's get_config() function.
7479 */
7480 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7481}
7482
6878da05
VS		 7483int intel_dotclock_calculate(int link_freq,
7484 const struct intel_link_m_n *m_n)
f1f644dc 7485{
f1f644dc
JB		 7486 /*
7487 * The calculation for the data clock is:
1041a02f 7488 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7489 * But we want to avoid losing precison if possible, so:
1041a02f 7490 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7491 *
7492 * and the link clock is simpler:
1041a02f 7493 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7494 */
7495
6878da05
VS		 7496 if (!m_n->link_n)
7497 return 0;
f1f644dc 7498
6878da05
VS		 7499 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7500}
f1f644dc 7501
18442d08
VS		 7502static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7503 struct intel_crtc_config *pipe_config)
6878da05
VS		 7504{
7505 struct drm_device *dev = crtc->base.dev;
79e53945 7506
18442d08
VS		 7507 /* read out port_clock from the DPLL */
7508 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7509
f1f644dc 7510 /*
18442d08 7511 * This value does not include pixel_multiplier.
241bfc38 7512 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7513 * agree once we know their relationship in the encoder's
7514 * get_config() function.
79e53945 7515 */
241bfc38 7516 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7517 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7518 &pipe_config->fdi_m_n);
79e53945
JB		 7519}
7520
7521/** Returns the currently programmed mode of the given pipe. */
7522struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7523 struct drm_crtc *crtc)
7524{
548f245b 7525 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7526 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7527 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7528 struct drm_display_mode *mode;
f1f644dc 7529 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7530 int htot = I915_READ(HTOTAL(cpu_transcoder));
7531 int hsync = I915_READ(HSYNC(cpu_transcoder));
7532 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7533 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7534 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7535
7536 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7537 if (!mode)
7538 return NULL;
7539
f1f644dc
JB		 7540 /*
7541 * Construct a pipe_config sufficient for getting the clock info
7542 * back out of crtc_clock_get.
7543 *
7544 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7545 * to use a real value here instead.
7546 */
293623f7 7547 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7548 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7549 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7550 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7551 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7552 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7553
773ae034 7554 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7555 mode->hdisplay = (htot & 0xffff) + 1;
7556 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7557 mode->hsync_start = (hsync & 0xffff) + 1;
7558 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7559 mode->vdisplay = (vtot & 0xffff) + 1;
7560 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7561 mode->vsync_start = (vsync & 0xffff) + 1;
7562 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7563
7564 drm_mode_set_name(mode);
79e53945
JB		 7565
7566 return mode;
7567}
7568
3dec0095 7569static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7570{
7571 struct drm_device *dev = crtc->dev;
7572 drm_i915_private_t *dev_priv = dev->dev_private;
7573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7574 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7575 int dpll_reg = DPLL(pipe);
7576 int dpll;
652c393a 7577
bad720ff 7578 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7579 return;
7580
7581 if (!dev_priv->lvds_downclock_avail)
7582 return;
7583
dbdc6479 7584 dpll = I915_READ(dpll_reg);
652c393a 7585 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7586 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7587
8ac5a6d5 7588 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7589
7590 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7591 I915_WRITE(dpll_reg, dpll);
9d0498a2 7592 intel_wait_for_vblank(dev, pipe);
dbdc6479 7593
652c393a
JB		 7594 dpll = I915_READ(dpll_reg);
7595 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7596 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7597 }
652c393a
JB		 7598}
7599
7600static void intel_decrease_pllclock(struct drm_crtc *crtc)
7601{
7602 struct drm_device *dev = crtc->dev;
7603 drm_i915_private_t *dev_priv = dev->dev_private;
7604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7605
bad720ff 7606 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7607 return;
7608
7609 if (!dev_priv->lvds_downclock_avail)
7610 return;
7611
7612 /*
7613 * Since this is called by a timer, we should never get here in
7614 * the manual case.
7615 */
7616 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7617 int pipe = intel_crtc->pipe;
7618 int dpll_reg = DPLL(pipe);
7619 int dpll;
f6e5b160 7620
44d98a61 7621 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7622
8ac5a6d5 7623 assert_panel_unlocked(dev_priv, pipe);
652c393a 7624
dc257cf1 7625 dpll = I915_READ(dpll_reg);
652c393a
JB		 7626 dpll |= DISPLAY_RATE_SELECT_FPA1;
7627 I915_WRITE(dpll_reg, dpll);
9d0498a2 7628 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7629 dpll = I915_READ(dpll_reg);
7630 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7631 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7632 }
7633
7634}
7635
f047e395
CW		 7636void intel_mark_busy(struct drm_device *dev)
7637{
c67a470b
PZ		 7638 struct drm_i915_private *dev_priv = dev->dev_private;
7639
7640 hsw_package_c8_gpu_busy(dev_priv);
7641 i915_update_gfx_val(dev_priv);
f047e395
CW		 7642}
7643
7644void intel_mark_idle(struct drm_device *dev)
652c393a 7645{
c67a470b 7646 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7647 struct drm_crtc *crtc;
652c393a 7648
c67a470b
PZ		 7649 hsw_package_c8_gpu_idle(dev_priv);
7650
652c393a
JB		 7651 if (!i915_powersave)
7652 return;
7653
652c393a 7654 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7655 if (!crtc->fb)
7656 continue;
7657
725a5b54 7658 intel_decrease_pllclock(crtc);
652c393a 7659 }
652c393a
JB		 7660}
7661
c65355bb
CW		 7662void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7663 struct intel_ring_buffer *ring)
652c393a 7664{
f047e395
CW		 7665 struct drm_device *dev = obj->base.dev;
7666 struct drm_crtc *crtc;
652c393a 7667
f047e395 7668 if (!i915_powersave)
acb87dfb
CW		 7669 return;
7670
652c393a
JB		 7671 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7672 if (!crtc->fb)
7673 continue;
7674
c65355bb
CW		 7675 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7676 continue;
7677
7678 intel_increase_pllclock(crtc);
7679 if (ring && intel_fbc_enabled(dev))
7680 ring->fbc_dirty = true;
652c393a
JB		 7681 }
7682}
7683
79e53945
JB		 7684static void intel_crtc_destroy(struct drm_crtc *crtc)
7685{
7686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7687 struct drm_device *dev = crtc->dev;
7688 struct intel_unpin_work *work;
7689 unsigned long flags;
7690
7691 spin_lock_irqsave(&dev->event_lock, flags);
7692 work = intel_crtc->unpin_work;
7693 intel_crtc->unpin_work = NULL;
7694 spin_unlock_irqrestore(&dev->event_lock, flags);
7695
7696 if (work) {
7697 cancel_work_sync(&work->work);
7698 kfree(work);
7699 }
79e53945 7700
40ccc72b
MK		 7701 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7702
79e53945 7703 drm_crtc_cleanup(crtc);
67e77c5a 7704
79e53945
JB		 7705 kfree(intel_crtc);
7706}
7707
6b95a207
KH		 7708static void intel_unpin_work_fn(struct work_struct *__work)
7709{
7710 struct intel_unpin_work *work =
7711 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7712 struct drm_device *dev = work->crtc->dev;
6b95a207 7713
b4a98e57 7714 mutex_lock(&dev->struct_mutex);
1690e1eb 7715 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7716 drm_gem_object_unreference(&work->pending_flip_obj->base);
7717 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7718
b4a98e57
CW		 7719 intel_update_fbc(dev);
7720 mutex_unlock(&dev->struct_mutex);
7721
7722 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7723 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7724
6b95a207
KH		 7725 kfree(work);
7726}
7727
1afe3e9d 7728static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7729 struct drm_crtc *crtc)
6b95a207
KH		 7730{
7731 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7733 struct intel_unpin_work *work;
6b95a207
KH		 7734 unsigned long flags;
7735
7736 /* Ignore early vblank irqs */
7737 if (intel_crtc == NULL)
7738 return;
7739
7740 spin_lock_irqsave(&dev->event_lock, flags);
7741 work = intel_crtc->unpin_work;
e7d841ca
CW		 7742
7743 /* Ensure we don't miss a work->pending update ... */
7744 smp_rmb();
7745
7746 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7747 spin_unlock_irqrestore(&dev->event_lock, flags);
7748 return;
7749 }
7750
e7d841ca
CW		 7751 /* and that the unpin work is consistent wrt ->pending. */
7752 smp_rmb();
7753
6b95a207 7754 intel_crtc->unpin_work = NULL;
6b95a207 7755
45a066eb
RC		 7756 if (work->event)
7757 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7758
0af7e4df
MK		 7759 drm_vblank_put(dev, intel_crtc->pipe);
7760
6b95a207
KH		 7761 spin_unlock_irqrestore(&dev->event_lock, flags);
7762
2c10d571 7763 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7764
7765 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7766
7767 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7768}
7769
1afe3e9d
JB		 7770void intel_finish_page_flip(struct drm_device *dev, int pipe)
7771{
7772 drm_i915_private_t *dev_priv = dev->dev_private;
7773 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7774
49b14a5c 7775 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7776}
7777
7778void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7779{
7780 drm_i915_private_t *dev_priv = dev->dev_private;
7781 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7782
49b14a5c 7783 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7784}
7785
6b95a207
KH		 7786void intel_prepare_page_flip(struct drm_device *dev, int plane)
7787{
7788 drm_i915_private_t *dev_priv = dev->dev_private;
7789 struct intel_crtc *intel_crtc =
7790 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7791 unsigned long flags;
7792
e7d841ca
CW		 7793 /* NB: An MMIO update of the plane base pointer will also
7794 * generate a page-flip completion irq, i.e. every modeset
7795 * is also accompanied by a spurious intel_prepare_page_flip().
7796 */
6b95a207 7797 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7798 if (intel_crtc->unpin_work)
7799 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7800 spin_unlock_irqrestore(&dev->event_lock, flags);
7801}
7802
e7d841ca
CW		 7803inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7804{
7805 /* Ensure that the work item is consistent when activating it ... */
7806 smp_wmb();
7807 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7808 /* and that it is marked active as soon as the irq could fire. */
7809 smp_wmb();
7810}
7811
8c9f3aaf
JB		 7812static int intel_gen2_queue_flip(struct drm_device *dev,
7813 struct drm_crtc *crtc,
7814 struct drm_framebuffer *fb,
ed8d1975
KP		 7815 struct drm_i915_gem_object *obj,
7816 uint32_t flags)
8c9f3aaf
JB		 7817{
7818 struct drm_i915_private *dev_priv = dev->dev_private;
7819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7820 u32 flip_mask;
6d90c952 7821 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7822 int ret;
7823
6d90c952 7824 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7825 if (ret)
83d4092b 7826 goto err;
8c9f3aaf 7827
6d90c952 7828 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7829 if (ret)
83d4092b 7830 goto err_unpin;
8c9f3aaf
JB		 7831
7832 /* Can't queue multiple flips, so wait for the previous
7833 * one to finish before executing the next.
7834 */
7835 if (intel_crtc->plane)
7836 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7837 else
7838 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7839 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7840 intel_ring_emit(ring, MI_NOOP);
7841 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7842 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7843 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7844 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7845 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7846
7847 intel_mark_page_flip_active(intel_crtc);
09246732 7848 __intel_ring_advance(ring);
83d4092b
CW		 7849 return 0;
7850
7851err_unpin:
7852 intel_unpin_fb_obj(obj);
7853err:
8c9f3aaf
JB		 7854 return ret;
7855}
7856
7857static int intel_gen3_queue_flip(struct drm_device *dev,
7858 struct drm_crtc *crtc,
7859 struct drm_framebuffer *fb,
ed8d1975
KP		 7860 struct drm_i915_gem_object *obj,
7861 uint32_t flags)
8c9f3aaf
JB		 7862{
7863 struct drm_i915_private *dev_priv = dev->dev_private;
7864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7865 u32 flip_mask;
6d90c952 7866 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7867 int ret;
7868
6d90c952 7869 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7870 if (ret)
83d4092b 7871 goto err;
8c9f3aaf 7872
6d90c952 7873 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7874 if (ret)
83d4092b 7875 goto err_unpin;
8c9f3aaf
JB		 7876
7877 if (intel_crtc->plane)
7878 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7879 else
7880 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7881 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7882 intel_ring_emit(ring, MI_NOOP);
7883 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7884 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7885 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7886 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7887 intel_ring_emit(ring, MI_NOOP);
7888
e7d841ca 7889 intel_mark_page_flip_active(intel_crtc);
09246732 7890 __intel_ring_advance(ring);
83d4092b
CW		 7891 return 0;
7892
7893err_unpin:
7894 intel_unpin_fb_obj(obj);
7895err:
8c9f3aaf
JB		 7896 return ret;
7897}
7898
7899static int intel_gen4_queue_flip(struct drm_device *dev,
7900 struct drm_crtc *crtc,
7901 struct drm_framebuffer *fb,
ed8d1975
KP		 7902 struct drm_i915_gem_object *obj,
7903 uint32_t flags)
8c9f3aaf
JB		 7904{
7905 struct drm_i915_private *dev_priv = dev->dev_private;
7906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7907 uint32_t pf, pipesrc;
6d90c952 7908 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7909 int ret;
7910
6d90c952 7911 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7912 if (ret)
83d4092b 7913 goto err;
8c9f3aaf 7914
6d90c952 7915 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7916 if (ret)
83d4092b 7917 goto err_unpin;
8c9f3aaf
JB		 7918
7919 /* i965+ uses the linear or tiled offsets from the
7920 * Display Registers (which do not change across a page-flip)
7921 * so we need only reprogram the base address.
7922 */
6d90c952
DV		 7923 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7924 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7925 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7926 intel_ring_emit(ring,
f343c5f6 7927 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7928 obj->tiling_mode);
8c9f3aaf
JB		 7929
7930 /* XXX Enabling the panel-fitter across page-flip is so far
7931 * untested on non-native modes, so ignore it for now.
7932 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7933 */
7934 pf = 0;
7935 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7936 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7937
7938 intel_mark_page_flip_active(intel_crtc);
09246732 7939 __intel_ring_advance(ring);
83d4092b
CW		 7940 return 0;
7941
7942err_unpin:
7943 intel_unpin_fb_obj(obj);
7944err:
8c9f3aaf
JB		 7945 return ret;
7946}
7947
7948static int intel_gen6_queue_flip(struct drm_device *dev,
7949 struct drm_crtc *crtc,
7950 struct drm_framebuffer *fb,
ed8d1975
KP		 7951 struct drm_i915_gem_object *obj,
7952 uint32_t flags)
8c9f3aaf
JB		 7953{
7954 struct drm_i915_private *dev_priv = dev->dev_private;
7955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7956 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7957 uint32_t pf, pipesrc;
7958 int ret;
7959
6d90c952 7960 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7961 if (ret)
83d4092b 7962 goto err;
8c9f3aaf 7963
6d90c952 7964 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7965 if (ret)
83d4092b 7966 goto err_unpin;
8c9f3aaf 7967
6d90c952
DV		 7968 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7969 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7970 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7971 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7972
dc257cf1
DV		 7973 /* Contrary to the suggestions in the documentation,
7974 * "Enable Panel Fitter" does not seem to be required when page
7975 * flipping with a non-native mode, and worse causes a normal
7976 * modeset to fail.
7977 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7978 */
7979 pf = 0;
8c9f3aaf 7980 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7981 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7982
7983 intel_mark_page_flip_active(intel_crtc);
09246732 7984 __intel_ring_advance(ring);
83d4092b
CW		 7985 return 0;
7986
7987err_unpin:
7988 intel_unpin_fb_obj(obj);
7989err:
8c9f3aaf
JB		 7990 return ret;
7991}
7992
7c9017e5
JB		 7993static int intel_gen7_queue_flip(struct drm_device *dev,
7994 struct drm_crtc *crtc,
7995 struct drm_framebuffer *fb,
ed8d1975
KP		 7996 struct drm_i915_gem_object *obj,
7997 uint32_t flags)
7c9017e5
JB		 7998{
7999 struct drm_i915_private *dev_priv = dev->dev_private;
8000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8001 struct intel_ring_buffer *ring;
cb05d8de 8002 uint32_t plane_bit = 0;
ffe74d75
CW		 8003 int len, ret;
8004
8005 ring = obj->ring;
1c5fd085 8006 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8007 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8008
8009 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8010 if (ret)
83d4092b 8011 goto err;
7c9017e5 8012
cb05d8de
DV		 8013 switch(intel_crtc->plane) {
8014 case PLANE_A:
8015 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8016 break;
8017 case PLANE_B:
8018 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8019 break;
8020 case PLANE_C:
8021 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8022 break;
8023 default:
8024 WARN_ONCE(1, "unknown plane in flip command\n");
8025 ret = -ENODEV;
ab3951eb 8026 goto err_unpin;
cb05d8de
DV		 8027 }
8028
ffe74d75
CW		 8029 len = 4;
8030 if (ring->id == RCS)
8031 len += 6;
8032
8033 ret = intel_ring_begin(ring, len);
7c9017e5 8034 if (ret)
83d4092b 8035 goto err_unpin;
7c9017e5 8036
ffe74d75
CW		 8037 /* Unmask the flip-done completion message. Note that the bspec says that
8038 * we should do this for both the BCS and RCS, and that we must not unmask
8039 * more than one flip event at any time (or ensure that one flip message
8040 * can be sent by waiting for flip-done prior to queueing new flips).
8041 * Experimentation says that BCS works despite DERRMR masking all
8042 * flip-done completion events and that unmasking all planes at once
8043 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8044 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8045 */
8046 if (ring->id == RCS) {
8047 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8048 intel_ring_emit(ring, DERRMR);
8049 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8050 DERRMR_PIPEB_PRI_FLIP_DONE |
8051 DERRMR_PIPEC_PRI_FLIP_DONE));
8052 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8053 intel_ring_emit(ring, DERRMR);
8054 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8055 }
8056
cb05d8de 8057 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8058 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8059 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8060 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8061
8062 intel_mark_page_flip_active(intel_crtc);
09246732 8063 __intel_ring_advance(ring);
83d4092b
CW		 8064 return 0;
8065
8066err_unpin:
8067 intel_unpin_fb_obj(obj);
8068err:
7c9017e5
JB		 8069 return ret;
8070}
8071
8c9f3aaf
JB		 8072static int intel_default_queue_flip(struct drm_device *dev,
8073 struct drm_crtc *crtc,
8074 struct drm_framebuffer *fb,
ed8d1975
KP		 8075 struct drm_i915_gem_object *obj,
8076 uint32_t flags)
8c9f3aaf
JB		 8077{
8078 return -ENODEV;
8079}
8080
6b95a207
KH		 8081static int intel_crtc_page_flip(struct drm_crtc *crtc,
8082 struct drm_framebuffer *fb,
ed8d1975
KP		 8083 struct drm_pending_vblank_event *event,
8084 uint32_t page_flip_flags)
6b95a207
KH		 8085{
8086 struct drm_device *dev = crtc->dev;
8087 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8088 struct drm_framebuffer *old_fb = crtc->fb;
8089 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8091 struct intel_unpin_work *work;
8c9f3aaf 8092 unsigned long flags;
52e68630 8093 int ret;
6b95a207 8094
e6a595d2
VS		 8095 /* Can't change pixel format via MI display flips. */
8096 if (fb->pixel_format != crtc->fb->pixel_format)
8097 return -EINVAL;
8098
8099 /*
8100 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8101 * Note that pitch changes could also affect these register.
8102 */
8103 if (INTEL_INFO(dev)->gen > 3 &&
8104 (fb->offsets[0] != crtc->fb->offsets[0] ||
8105 fb->pitches[0] != crtc->fb->pitches[0]))
8106 return -EINVAL;
8107
b14c5679 8108 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8109 if (work == NULL)
8110 return -ENOMEM;
8111
6b95a207 8112 work->event = event;
b4a98e57 8113 work->crtc = crtc;
4a35f83b 8114 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8115 INIT_WORK(&work->work, intel_unpin_work_fn);
8116
7317c75e
JB		 8117 ret = drm_vblank_get(dev, intel_crtc->pipe);
8118 if (ret)
8119 goto free_work;
8120
6b95a207
KH		 8121 /* We borrow the event spin lock for protecting unpin_work */
8122 spin_lock_irqsave(&dev->event_lock, flags);
8123 if (intel_crtc->unpin_work) {
8124 spin_unlock_irqrestore(&dev->event_lock, flags);
8125 kfree(work);
7317c75e 8126 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8127
8128 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8129 return -EBUSY;
8130 }
8131 intel_crtc->unpin_work = work;
8132 spin_unlock_irqrestore(&dev->event_lock, flags);
8133
b4a98e57
CW		 8134 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8135 flush_workqueue(dev_priv->wq);
8136
79158103
CW		 8137 ret = i915_mutex_lock_interruptible(dev);
8138 if (ret)
8139 goto cleanup;
6b95a207 8140
75dfca80 8141 /* Reference the objects for the scheduled work. */
05394f39
CW		 8142 drm_gem_object_reference(&work->old_fb_obj->base);
8143 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8144
8145 crtc->fb = fb;
96b099fd 8146
e1f99ce6 8147 work->pending_flip_obj = obj;
e1f99ce6 8148
4e5359cd
SF		 8149 work->enable_stall_check = true;
8150
b4a98e57 8151 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8152 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8153
ed8d1975 8154 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8155 if (ret)
8156 goto cleanup_pending;
6b95a207 8157
7782de3b 8158 intel_disable_fbc(dev);
c65355bb 8159 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8160 mutex_unlock(&dev->struct_mutex);
8161
e5510fac
JB		 8162 trace_i915_flip_request(intel_crtc->plane, obj);
8163
6b95a207 8164 return 0;
96b099fd 8165
8c9f3aaf 8166cleanup_pending:
b4a98e57 8167 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8168 crtc->fb = old_fb;
05394f39
CW		 8169 drm_gem_object_unreference(&work->old_fb_obj->base);
8170 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8171 mutex_unlock(&dev->struct_mutex);
8172
79158103 8173cleanup:
96b099fd
CW		 8174 spin_lock_irqsave(&dev->event_lock, flags);
8175 intel_crtc->unpin_work = NULL;
8176 spin_unlock_irqrestore(&dev->event_lock, flags);
8177
7317c75e
JB		 8178 drm_vblank_put(dev, intel_crtc->pipe);
8179free_work:
96b099fd
CW		 8180 kfree(work);
8181
8182 return ret;
6b95a207
KH		 8183}
8184
f6e5b160 8185static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8186 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8187 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8188};
8189
50f56119
DV		 8190static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8191 struct drm_crtc *crtc)
8192{
8193 struct drm_device *dev;
8194 struct drm_crtc *tmp;
8195 int crtc_mask = 1;
47f1c6c9 8196
50f56119 8197 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8198
50f56119 8199 dev = crtc->dev;
47f1c6c9 8200
50f56119
DV		 8201 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8202 if (tmp == crtc)
8203 break;
8204 crtc_mask <<= 1;
8205 }
47f1c6c9 8206
50f56119
DV		 8207 if (encoder->possible_crtcs & crtc_mask)
8208 return true;
8209 return false;
47f1c6c9 8210}
79e53945 8211
9a935856
DV		 8212/**
8213 * intel_modeset_update_staged_output_state
8214 *
8215 * Updates the staged output configuration state, e.g. after we've read out the
8216 * current hw state.
8217 */
8218static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8219{
9a935856
DV		 8220 struct intel_encoder *encoder;
8221 struct intel_connector *connector;
f6e5b160 8222
9a935856
DV		 8223 list_for_each_entry(connector, &dev->mode_config.connector_list,
8224 base.head) {
8225 connector->new_encoder =
8226 to_intel_encoder(connector->base.encoder);
8227 }
f6e5b160 8228
9a935856
DV		 8229 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8230 base.head) {
8231 encoder->new_crtc =
8232 to_intel_crtc(encoder->base.crtc);
8233 }
f6e5b160
CW		 8234}
8235
9a935856
DV		 8236/**
8237 * intel_modeset_commit_output_state
8238 *
8239 * This function copies the stage display pipe configuration to the real one.
8240 */
8241static void intel_modeset_commit_output_state(struct drm_device *dev)
8242{
8243 struct intel_encoder *encoder;
8244 struct intel_connector *connector;
f6e5b160 8245
9a935856
DV		 8246 list_for_each_entry(connector, &dev->mode_config.connector_list,
8247 base.head) {
8248 connector->base.encoder = &connector->new_encoder->base;
8249 }
f6e5b160 8250
9a935856
DV		 8251 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8252 base.head) {
8253 encoder->base.crtc = &encoder->new_crtc->base;
8254 }
8255}
8256
050f7aeb
DV		 8257static void
8258connected_sink_compute_bpp(struct intel_connector * connector,
8259 struct intel_crtc_config *pipe_config)
8260{
8261 int bpp = pipe_config->pipe_bpp;
8262
8263 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8264 connector->base.base.id,
8265 drm_get_connector_name(&connector->base));
8266
8267 /* Don't use an invalid EDID bpc value */
8268 if (connector->base.display_info.bpc &&
8269 connector->base.display_info.bpc * 3 < bpp) {
8270 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8271 bpp, connector->base.display_info.bpc*3);
8272 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8273 }
8274
8275 /* Clamp bpp to 8 on screens without EDID 1.4 */
8276 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8277 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8278 bpp);
8279 pipe_config->pipe_bpp = 24;
8280 }
8281}
8282
4e53c2e0 8283static int
050f7aeb
DV		 8284compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8285 struct drm_framebuffer *fb,
8286 struct intel_crtc_config *pipe_config)
4e53c2e0 8287{
050f7aeb
DV		 8288 struct drm_device *dev = crtc->base.dev;
8289 struct intel_connector *connector;
4e53c2e0
DV		 8290 int bpp;
8291
d42264b1
DV		 8292 switch (fb->pixel_format) {
8293 case DRM_FORMAT_C8:
4e53c2e0
DV		 8294 bpp = 8*3; /* since we go through a colormap */
8295 break;
d42264b1
DV		 8296 case DRM_FORMAT_XRGB1555:
8297 case DRM_FORMAT_ARGB1555:
8298 /* checked in intel_framebuffer_init already */
8299 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8300 return -EINVAL;
8301 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8302 bpp = 6*3; /* min is 18bpp */
8303 break;
d42264b1
DV		 8304 case DRM_FORMAT_XBGR8888:
8305 case DRM_FORMAT_ABGR8888:
8306 /* checked in intel_framebuffer_init already */
8307 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8308 return -EINVAL;
8309 case DRM_FORMAT_XRGB8888:
8310 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8311 bpp = 8*3;
8312 break;
d42264b1
DV		 8313 case DRM_FORMAT_XRGB2101010:
8314 case DRM_FORMAT_ARGB2101010:
8315 case DRM_FORMAT_XBGR2101010:
8316 case DRM_FORMAT_ABGR2101010:
8317 /* checked in intel_framebuffer_init already */
8318 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8319 return -EINVAL;
4e53c2e0
DV		 8320 bpp = 10*3;
8321 break;
baba133a 8322 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8323 default:
8324 DRM_DEBUG_KMS("unsupported depth\n");
8325 return -EINVAL;
8326 }
8327
4e53c2e0
DV		 8328 pipe_config->pipe_bpp = bpp;
8329
8330 /* Clamp display bpp to EDID value */
8331 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8332 base.head) {
1b829e05
DV		 8333 if (!connector->new_encoder ||
8334 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8335 continue;
8336
050f7aeb 8337 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8338 }
8339
8340 return bpp;
8341}
8342
644db711
DV		 8343static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8344{
8345 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8346 "type: 0x%x flags: 0x%x\n",
1342830c 8347 mode->crtc_clock,
644db711
DV		 8348 mode->crtc_hdisplay, mode->crtc_hsync_start,
8349 mode->crtc_hsync_end, mode->crtc_htotal,
8350 mode->crtc_vdisplay, mode->crtc_vsync_start,
8351 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8352}
8353
c0b03411
DV		 8354static void intel_dump_pipe_config(struct intel_crtc *crtc,
8355 struct intel_crtc_config *pipe_config,
8356 const char *context)
8357{
8358 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8359 context, pipe_name(crtc->pipe));
8360
8361 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8362 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8363 pipe_config->pipe_bpp, pipe_config->dither);
8364 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8365 pipe_config->has_pch_encoder,
8366 pipe_config->fdi_lanes,
8367 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8368 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8369 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8370 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8371 pipe_config->has_dp_encoder,
8372 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8373 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8374 pipe_config->dp_m_n.tu);
c0b03411
DV		 8375 DRM_DEBUG_KMS("requested mode:\n");
8376 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8377 DRM_DEBUG_KMS("adjusted mode:\n");
8378 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8379 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8380 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8381 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8382 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8383 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8384 pipe_config->gmch_pfit.control,
8385 pipe_config->gmch_pfit.pgm_ratios,
8386 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8387 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8388 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8389 pipe_config->pch_pfit.size,
8390 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8391 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8392 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8393}
8394
accfc0c5
DV		 8395static bool check_encoder_cloning(struct drm_crtc *crtc)
8396{
8397 int num_encoders = 0;
8398 bool uncloneable_encoders = false;
8399 struct intel_encoder *encoder;
8400
8401 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8402 base.head) {
8403 if (&encoder->new_crtc->base != crtc)
8404 continue;
8405
8406 num_encoders++;
8407 if (!encoder->cloneable)
8408 uncloneable_encoders = true;
8409 }
8410
8411 return !(num_encoders > 1 && uncloneable_encoders);
8412}
8413
b8cecdf5
DV		 8414static struct intel_crtc_config *
8415intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8416 struct drm_framebuffer *fb,
b8cecdf5 8417 struct drm_display_mode *mode)
ee7b9f93 8418{
7758a113 8419 struct drm_device *dev = crtc->dev;
7758a113 8420 struct intel_encoder *encoder;
b8cecdf5 8421 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8422 int plane_bpp, ret = -EINVAL;
8423 bool retry = true;
ee7b9f93 8424
accfc0c5
DV		 8425 if (!check_encoder_cloning(crtc)) {
8426 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8427 return ERR_PTR(-EINVAL);
8428 }
8429
b8cecdf5
DV		 8430 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8431 if (!pipe_config)
7758a113
DV		 8432 return ERR_PTR(-ENOMEM);
8433
b8cecdf5
DV		 8434 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8435 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8436
e143a21c
DV		 8437 pipe_config->cpu_transcoder =
8438 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8439 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8440
2960bc9c
ID		 8441 /*
8442 * Sanitize sync polarity flags based on requested ones. If neither
8443 * positive or negative polarity is requested, treat this as meaning
8444 * negative polarity.
8445 */
8446 if (!(pipe_config->adjusted_mode.flags &
8447 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8448 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8449
8450 if (!(pipe_config->adjusted_mode.flags &
8451 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8452 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8453
050f7aeb
DV		 8454 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8455 * plane pixel format and any sink constraints into account. Returns the
8456 * source plane bpp so that dithering can be selected on mismatches
8457 * after encoders and crtc also have had their say. */
8458 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8459 fb, pipe_config);
4e53c2e0
DV		 8460 if (plane_bpp < 0)
8461 goto fail;
8462
e29c22c0 8463encoder_retry:
ef1b460d 8464 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8465 pipe_config->port_clock = 0;
ef1b460d 8466 pipe_config->pixel_multiplier = 1;
ff9a6750 8467
135c81b8 8468 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8469 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8470
350a10ca
DL		 8471 /* set_crtcinfo() may have adjusted hdisplay/vdisplay */
8472 pipe_config->pipe_src_w = pipe_config->adjusted_mode.crtc_hdisplay;
8473 pipe_config->pipe_src_h = pipe_config->adjusted_mode.crtc_vdisplay;
8474
7758a113
DV		 8475 /* Pass our mode to the connectors and the CRTC to give them a chance to
8476 * adjust it according to limitations or connector properties, and also
8477 * a chance to reject the mode entirely.
47f1c6c9 8478 */
7758a113
DV		 8479 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8480 base.head) {
47f1c6c9 8481
7758a113
DV		 8482 if (&encoder->new_crtc->base != crtc)
8483 continue;
7ae89233 8484
efea6e8e
DV		 8485 if (!(encoder->compute_config(encoder, pipe_config))) {
8486 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8487 goto fail;
8488 }
ee7b9f93 8489 }
47f1c6c9 8490
ff9a6750
DV		 8491 /* Set default port clock if not overwritten by the encoder. Needs to be
8492 * done afterwards in case the encoder adjusts the mode. */
8493 if (!pipe_config->port_clock)
241bfc38
DL		 8494 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8495 * pipe_config->pixel_multiplier;
ff9a6750 8496
a43f6e0f 8497 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8498 if (ret < 0) {
7758a113
DV		 8499 DRM_DEBUG_KMS("CRTC fixup failed\n");
8500 goto fail;
ee7b9f93 8501 }
e29c22c0
DV		 8502
8503 if (ret == RETRY) {
8504 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8505 ret = -EINVAL;
8506 goto fail;
8507 }
8508
8509 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8510 retry = false;
8511 goto encoder_retry;
8512 }
8513
4e53c2e0
DV		 8514 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8515 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8516 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8517
b8cecdf5 8518 return pipe_config;
7758a113 8519fail:
b8cecdf5 8520 kfree(pipe_config);
e29c22c0 8521 return ERR_PTR(ret);
ee7b9f93 8522}
47f1c6c9 8523
e2e1ed41
DV		 8524/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8525 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8526static void
8527intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8528 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8529{
8530 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8531 struct drm_device *dev = crtc->dev;
8532 struct intel_encoder *encoder;
8533 struct intel_connector *connector;
8534 struct drm_crtc *tmp_crtc;
79e53945 8535
e2e1ed41 8536 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8537
e2e1ed41
DV		 8538 /* Check which crtcs have changed outputs connected to them, these need
8539 * to be part of the prepare_pipes mask. We don't (yet) support global
8540 * modeset across multiple crtcs, so modeset_pipes will only have one
8541 * bit set at most. */
8542 list_for_each_entry(connector, &dev->mode_config.connector_list,
8543 base.head) {
8544 if (connector->base.encoder == &connector->new_encoder->base)
8545 continue;
79e53945 8546
e2e1ed41
DV		 8547 if (connector->base.encoder) {
8548 tmp_crtc = connector->base.encoder->crtc;
8549
8550 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8551 }
8552
8553 if (connector->new_encoder)
8554 *prepare_pipes |=
8555 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8556 }
8557
e2e1ed41
DV		 8558 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8559 base.head) {
8560 if (encoder->base.crtc == &encoder->new_crtc->base)
8561 continue;
8562
8563 if (encoder->base.crtc) {
8564 tmp_crtc = encoder->base.crtc;
8565
8566 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8567 }
8568
8569 if (encoder->new_crtc)
8570 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8571 }
8572
e2e1ed41
DV		 8573 /* Check for any pipes that will be fully disabled ... */
8574 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8575 base.head) {
8576 bool used = false;
22fd0fab 8577
e2e1ed41
DV		 8578 /* Don't try to disable disabled crtcs. */
8579 if (!intel_crtc->base.enabled)
8580 continue;
7e7d76c3 8581
e2e1ed41
DV		 8582 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8583 base.head) {
8584 if (encoder->new_crtc == intel_crtc)
8585 used = true;
8586 }
8587
8588 if (!used)
8589 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8590 }
8591
e2e1ed41
DV		 8592
8593 /* set_mode is also used to update properties on life display pipes. */
8594 intel_crtc = to_intel_crtc(crtc);
8595 if (crtc->enabled)
8596 *prepare_pipes |= 1 << intel_crtc->pipe;
8597
b6c5164d
DV		 8598 /*
8599 * For simplicity do a full modeset on any pipe where the output routing
8600 * changed. We could be more clever, but that would require us to be
8601 * more careful with calling the relevant encoder->mode_set functions.
8602 */
e2e1ed41
DV		 8603 if (*prepare_pipes)
8604 *modeset_pipes = *prepare_pipes;
8605
8606 /* ... and mask these out. */
8607 *modeset_pipes &= ~(*disable_pipes);
8608 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8609
8610 /*
8611 * HACK: We don't (yet) fully support global modesets. intel_set_config
8612 * obies this rule, but the modeset restore mode of
8613 * intel_modeset_setup_hw_state does not.
8614 */
8615 *modeset_pipes &= 1 << intel_crtc->pipe;
8616 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8617
8618 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8619 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8620}
79e53945 8621
ea9d758d 8622static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8623{
ea9d758d 8624 struct drm_encoder *encoder;
f6e5b160 8625 struct drm_device *dev = crtc->dev;
f6e5b160 8626
ea9d758d
DV		 8627 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8628 if (encoder->crtc == crtc)
8629 return true;
8630
8631 return false;
8632}
8633
8634static void
8635intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8636{
8637 struct intel_encoder *intel_encoder;
8638 struct intel_crtc *intel_crtc;
8639 struct drm_connector *connector;
8640
8641 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8642 base.head) {
8643 if (!intel_encoder->base.crtc)
8644 continue;
8645
8646 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8647
8648 if (prepare_pipes & (1 << intel_crtc->pipe))
8649 intel_encoder->connectors_active = false;
8650 }
8651
8652 intel_modeset_commit_output_state(dev);
8653
8654 /* Update computed state. */
8655 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8656 base.head) {
8657 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8658 }
8659
8660 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8661 if (!connector->encoder || !connector->encoder->crtc)
8662 continue;
8663
8664 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8665
8666 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8667 struct drm_property *dpms_property =
8668 dev->mode_config.dpms_property;
8669
ea9d758d 8670 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8671 drm_object_property_set_value(&connector->base,
68d34720
DV		 8672 dpms_property,
8673 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8674
8675 intel_encoder = to_intel_encoder(connector->encoder);
8676 intel_encoder->connectors_active = true;
8677 }
8678 }
8679
8680}
8681
3bd26263 8682static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8683{
3bd26263 8684 int diff;
f1f644dc
JB		 8685
8686 if (clock1 == clock2)
8687 return true;
8688
8689 if (!clock1 || !clock2)
8690 return false;
8691
8692 diff = abs(clock1 - clock2);
8693
8694 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8695 return true;
8696
8697 return false;
8698}
8699
25c5b266
DV		 8700#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8701 list_for_each_entry((intel_crtc), \
8702 &(dev)->mode_config.crtc_list, \
8703 base.head) \
0973f18f 8704 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8705
0e8ffe1b 8706static bool
2fa2fe9a
DV		 8707intel_pipe_config_compare(struct drm_device *dev,
8708 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8709 struct intel_crtc_config *pipe_config)
8710{
66e985c0
DV		 8711#define PIPE_CONF_CHECK_X(name) \
8712 if (current_config->name != pipe_config->name) { \
8713 DRM_ERROR("mismatch in " #name " " \
8714 "(expected 0x%08x, found 0x%08x)\n", \
8715 current_config->name, \
8716 pipe_config->name); \
8717 return false; \
8718 }
8719
08a24034
DV		 8720#define PIPE_CONF_CHECK_I(name) \
8721 if (current_config->name != pipe_config->name) { \
8722 DRM_ERROR("mismatch in " #name " " \
8723 "(expected %i, found %i)\n", \
8724 current_config->name, \
8725 pipe_config->name); \
8726 return false; \
88adfff1
DV		 8727 }
8728
1bd1bd80
DV		 8729#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8730 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8731 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8732 "(expected %i, found %i)\n", \
8733 current_config->name & (mask), \
8734 pipe_config->name & (mask)); \
8735 return false; \
8736 }
8737
5e550656
VS		 8738#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8739 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8740 DRM_ERROR("mismatch in " #name " " \
8741 "(expected %i, found %i)\n", \
8742 current_config->name, \
8743 pipe_config->name); \
8744 return false; \
8745 }
8746
bb760063
DV		 8747#define PIPE_CONF_QUIRK(quirk) \
8748 ((current_config->quirks | pipe_config->quirks) & (quirk))
8749
eccb140b
DV		 8750 PIPE_CONF_CHECK_I(cpu_transcoder);
8751
08a24034
DV		 8752 PIPE_CONF_CHECK_I(has_pch_encoder);
8753 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8754 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8755 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8756 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8757 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8758 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8759
eb14cb74
VS		 8760 PIPE_CONF_CHECK_I(has_dp_encoder);
8761 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8762 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8763 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8764 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8765 PIPE_CONF_CHECK_I(dp_m_n.tu);
8766
1bd1bd80
DV		 8767 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8768 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8769 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8770 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8771 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8772 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8773
8774 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8775 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8776 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8777 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8778 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8779 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8780
c93f54cf 8781 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8782
1bd1bd80
DV		 8783 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8784 DRM_MODE_FLAG_INTERLACE);
8785
bb760063
DV		 8786 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8787 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8788 DRM_MODE_FLAG_PHSYNC);
8789 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8790 DRM_MODE_FLAG_NHSYNC);
8791 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8792 DRM_MODE_FLAG_PVSYNC);
8793 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8794 DRM_MODE_FLAG_NVSYNC);
8795 }
045ac3b5 8796
37327abd
VS		 8797 PIPE_CONF_CHECK_I(pipe_src_w);
8798 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8799
2fa2fe9a
DV		 8800 PIPE_CONF_CHECK_I(gmch_pfit.control);
8801 /* pfit ratios are autocomputed by the hw on gen4+ */
8802 if (INTEL_INFO(dev)->gen < 4)
8803 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8804 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8805 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8806 if (current_config->pch_pfit.enabled) {
8807 PIPE_CONF_CHECK_I(pch_pfit.pos);
8808 PIPE_CONF_CHECK_I(pch_pfit.size);
8809 }
2fa2fe9a 8810
42db64ef
PZ		 8811 PIPE_CONF_CHECK_I(ips_enabled);
8812
282740f7
VS		 8813 PIPE_CONF_CHECK_I(double_wide);
8814
c0d43d62 8815 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8816 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8817 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8818 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8819 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8820
42571aef
VS		 8821 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8822 PIPE_CONF_CHECK_I(pipe_bpp);
8823
d71b8d4a 8824 if (!IS_HASWELL(dev)) {
241bfc38 8825 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8826 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8827 }
5e550656 8828
66e985c0 8829#undef PIPE_CONF_CHECK_X
08a24034 8830#undef PIPE_CONF_CHECK_I
1bd1bd80 8831#undef PIPE_CONF_CHECK_FLAGS
5e550656 8832#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8833#undef PIPE_CONF_QUIRK
88adfff1 8834
0e8ffe1b
DV		 8835 return true;
8836}
8837
91d1b4bd
DV		 8838static void
8839check_connector_state(struct drm_device *dev)
8af6cf88 8840{
8af6cf88
DV		 8841 struct intel_connector *connector;
8842
8843 list_for_each_entry(connector, &dev->mode_config.connector_list,
8844 base.head) {
8845 /* This also checks the encoder/connector hw state with the
8846 * ->get_hw_state callbacks. */
8847 intel_connector_check_state(connector);
8848
8849 WARN(&connector->new_encoder->base != connector->base.encoder,
8850 "connector's staged encoder doesn't match current encoder\n");
8851 }
91d1b4bd
DV		 8852}
8853
8854static void
8855check_encoder_state(struct drm_device *dev)
8856{
8857 struct intel_encoder *encoder;
8858 struct intel_connector *connector;
8af6cf88
DV		 8859
8860 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8861 base.head) {
8862 bool enabled = false;
8863 bool active = false;
8864 enum pipe pipe, tracked_pipe;
8865
8866 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8867 encoder->base.base.id,
8868 drm_get_encoder_name(&encoder->base));
8869
8870 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8871 "encoder's stage crtc doesn't match current crtc\n");
8872 WARN(encoder->connectors_active && !encoder->base.crtc,
8873 "encoder's active_connectors set, but no crtc\n");
8874
8875 list_for_each_entry(connector, &dev->mode_config.connector_list,
8876 base.head) {
8877 if (connector->base.encoder != &encoder->base)
8878 continue;
8879 enabled = true;
8880 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8881 active = true;
8882 }
8883 WARN(!!encoder->base.crtc != enabled,
8884 "encoder's enabled state mismatch "
8885 "(expected %i, found %i)\n",
8886 !!encoder->base.crtc, enabled);
8887 WARN(active && !encoder->base.crtc,
8888 "active encoder with no crtc\n");
8889
8890 WARN(encoder->connectors_active != active,
8891 "encoder's computed active state doesn't match tracked active state "
8892 "(expected %i, found %i)\n", active, encoder->connectors_active);
8893
8894 active = encoder->get_hw_state(encoder, &pipe);
8895 WARN(active != encoder->connectors_active,
8896 "encoder's hw state doesn't match sw tracking "
8897 "(expected %i, found %i)\n",
8898 encoder->connectors_active, active);
8899
8900 if (!encoder->base.crtc)
8901 continue;
8902
8903 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8904 WARN(active && pipe != tracked_pipe,
8905 "active encoder's pipe doesn't match"
8906 "(expected %i, found %i)\n",
8907 tracked_pipe, pipe);
8908
8909 }
91d1b4bd
DV		 8910}
8911
8912static void
8913check_crtc_state(struct drm_device *dev)
8914{
8915 drm_i915_private_t *dev_priv = dev->dev_private;
8916 struct intel_crtc *crtc;
8917 struct intel_encoder *encoder;
8918 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8919
8920 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8921 base.head) {
8922 bool enabled = false;
8923 bool active = false;
8924
045ac3b5
JB		 8925 memset(&pipe_config, 0, sizeof(pipe_config));
8926
8af6cf88
DV		 8927 DRM_DEBUG_KMS("[CRTC:%d]\n",
8928 crtc->base.base.id);
8929
8930 WARN(crtc->active && !crtc->base.enabled,
8931 "active crtc, but not enabled in sw tracking\n");
8932
8933 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8934 base.head) {
8935 if (encoder->base.crtc != &crtc->base)
8936 continue;
8937 enabled = true;
8938 if (encoder->connectors_active)
8939 active = true;
8940 }
6c49f241 8941
8af6cf88
DV		 8942 WARN(active != crtc->active,
8943 "crtc's computed active state doesn't match tracked active state "
8944 "(expected %i, found %i)\n", active, crtc->active);
8945 WARN(enabled != crtc->base.enabled,
8946 "crtc's computed enabled state doesn't match tracked enabled state "
8947 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8948
0e8ffe1b
DV		 8949 active = dev_priv->display.get_pipe_config(crtc,
8950 &pipe_config);
d62cf62a
DV		 8951
8952 /* hw state is inconsistent with the pipe A quirk */
8953 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8954 active = crtc->active;
8955
6c49f241
DV		 8956 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8957 base.head) {
3eaba51c 8958 enum pipe pipe;
6c49f241
DV		 8959 if (encoder->base.crtc != &crtc->base)
8960 continue;
3eaba51c
VS		 8961 if (encoder->get_config &&
8962 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8963 encoder->get_config(encoder, &pipe_config);
8964 }
8965
0e8ffe1b
DV		 8966 WARN(crtc->active != active,
8967 "crtc active state doesn't match with hw state "
8968 "(expected %i, found %i)\n", crtc->active, active);
8969
c0b03411
DV		 8970 if (active &&
8971 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8972 WARN(1, "pipe state doesn't match!\n");
8973 intel_dump_pipe_config(crtc, &pipe_config,
8974 "[hw state]");
8975 intel_dump_pipe_config(crtc, &crtc->config,
8976 "[sw state]");
8977 }
8af6cf88
DV		 8978 }
8979}
8980
91d1b4bd
DV		 8981static void
8982check_shared_dpll_state(struct drm_device *dev)
8983{
8984 drm_i915_private_t *dev_priv = dev->dev_private;
8985 struct intel_crtc *crtc;
8986 struct intel_dpll_hw_state dpll_hw_state;
8987 int i;
5358901f
DV		 8988
8989 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8990 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8991 int enabled_crtcs = 0, active_crtcs = 0;
8992 bool active;
8993
8994 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8995
8996 DRM_DEBUG_KMS("%s\n", pll->name);
8997
8998 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8999
9000 WARN(pll->active > pll->refcount,
9001 "more active pll users than references: %i vs %i\n",
9002 pll->active, pll->refcount);
9003 WARN(pll->active && !pll->on,
9004 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9005 WARN(pll->on && !pll->active,
9006 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9007 WARN(pll->on != active,
9008 "pll on state mismatch (expected %i, found %i)\n",
9009 pll->on, active);
9010
9011 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9012 base.head) {
9013 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9014 enabled_crtcs++;
9015 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9016 active_crtcs++;
9017 }
9018 WARN(pll->active != active_crtcs,
9019 "pll active crtcs mismatch (expected %i, found %i)\n",
9020 pll->active, active_crtcs);
9021 WARN(pll->refcount != enabled_crtcs,
9022 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9023 pll->refcount, enabled_crtcs);
66e985c0
DV		 9024
9025 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9026 sizeof(dpll_hw_state)),
9027 "pll hw state mismatch\n");
5358901f 9028 }
8af6cf88
DV		 9029}
9030
91d1b4bd
DV		 9031void
9032intel_modeset_check_state(struct drm_device *dev)
9033{
9034 check_connector_state(dev);
9035 check_encoder_state(dev);
9036 check_crtc_state(dev);
9037 check_shared_dpll_state(dev);
9038}
9039
18442d08
VS		 9040void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9041 int dotclock)
9042{
9043 /*
9044 * FDI already provided one idea for the dotclock.
9045 * Yell if the encoder disagrees.
9046 */
241bfc38 9047 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9048 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9049 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9050}
9051
f30da187
DV		 9052static int __intel_set_mode(struct drm_crtc *crtc,
9053 struct drm_display_mode *mode,
9054 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9055{
9056 struct drm_device *dev = crtc->dev;
dbf2b54e 9057 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9058 struct drm_display_mode *saved_mode, *saved_hwmode;
9059 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9060 struct intel_crtc *intel_crtc;
9061 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9062 int ret = 0;
a6778b3c 9063
a1e22653 9064 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9065 if (!saved_mode)
9066 return -ENOMEM;
3ac18232 9067 saved_hwmode = saved_mode + 1;
a6778b3c 9068
e2e1ed41 9069 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9070 &prepare_pipes, &disable_pipes);
9071
3ac18232
TG		 9072 *saved_hwmode = crtc->hwmode;
9073 *saved_mode = crtc->mode;
a6778b3c 9074
25c5b266
DV		 9075 /* Hack: Because we don't (yet) support global modeset on multiple
9076 * crtcs, we don't keep track of the new mode for more than one crtc.
9077 * Hence simply check whether any bit is set in modeset_pipes in all the
9078 * pieces of code that are not yet converted to deal with mutliple crtcs
9079 * changing their mode at the same time. */
25c5b266 9080 if (modeset_pipes) {
4e53c2e0 9081 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9082 if (IS_ERR(pipe_config)) {
9083 ret = PTR_ERR(pipe_config);
9084 pipe_config = NULL;
9085
3ac18232 9086 goto out;
25c5b266 9087 }
c0b03411
DV		 9088 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9089 "[modeset]");
25c5b266 9090 }
a6778b3c 9091
460da916
DV		 9092 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9093 intel_crtc_disable(&intel_crtc->base);
9094
ea9d758d
DV		 9095 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9096 if (intel_crtc->base.enabled)
9097 dev_priv->display.crtc_disable(&intel_crtc->base);
9098 }
a6778b3c 9099
6c4c86f5
DV		 9100 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9101 * to set it here already despite that we pass it down the callchain.
f6e5b160 9102 */
b8cecdf5 9103 if (modeset_pipes) {
25c5b266 9104 crtc->mode = *mode;
b8cecdf5
DV		 9105 /* mode_set/enable/disable functions rely on a correct pipe
9106 * config. */
9107 to_intel_crtc(crtc)->config = *pipe_config;
9108 }
7758a113 9109
ea9d758d
DV		 9110 /* Only after disabling all output pipelines that will be changed can we
9111 * update the the output configuration. */
9112 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9113
47fab737
DV		 9114 if (dev_priv->display.modeset_global_resources)
9115 dev_priv->display.modeset_global_resources(dev);
9116
a6778b3c
DV		 9117 /* Set up the DPLL and any encoders state that needs to adjust or depend
9118 * on the DPLL.
f6e5b160 9119 */
25c5b266 9120 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9121 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9122 x, y, fb);
9123 if (ret)
9124 goto done;
a6778b3c
DV		 9125 }
9126
9127 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9128 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9129 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9130
25c5b266
DV		 9131 if (modeset_pipes) {
9132 /* Store real post-adjustment hardware mode. */
b8cecdf5 9133 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9134
25c5b266
DV		 9135 /* Calculate and store various constants which
9136 * are later needed by vblank and swap-completion
9137 * timestamping. They are derived from true hwmode.
9138 */
9139 drm_calc_timestamping_constants(crtc);
9140 }
a6778b3c
DV		 9141
9142 /* FIXME: add subpixel order */
9143done:
c0c36b94 9144 if (ret && crtc->enabled) {
3ac18232
TG		 9145 crtc->hwmode = *saved_hwmode;
9146 crtc->mode = *saved_mode;
a6778b3c
DV		 9147 }
9148
3ac18232 9149out:
b8cecdf5 9150 kfree(pipe_config);
3ac18232 9151 kfree(saved_mode);
a6778b3c 9152 return ret;
f6e5b160
CW		 9153}
9154
e7457a9a
DL		 9155static int intel_set_mode(struct drm_crtc *crtc,
9156 struct drm_display_mode *mode,
9157 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9158{
9159 int ret;
9160
9161 ret = __intel_set_mode(crtc, mode, x, y, fb);
9162
9163 if (ret == 0)
9164 intel_modeset_check_state(crtc->dev);
9165
9166 return ret;
9167}
9168
c0c36b94
CW		 9169void intel_crtc_restore_mode(struct drm_crtc *crtc)
9170{
9171 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9172}
9173
25c5b266
DV		 9174#undef for_each_intel_crtc_masked
9175
d9e55608
DV		 9176static void intel_set_config_free(struct intel_set_config *config)
9177{
9178 if (!config)
9179 return;
9180
1aa4b628
DV		 9181 kfree(config->save_connector_encoders);
9182 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9183 kfree(config);
9184}
9185
85f9eb71
DV		 9186static int intel_set_config_save_state(struct drm_device *dev,
9187 struct intel_set_config *config)
9188{
85f9eb71
DV		 9189 struct drm_encoder *encoder;
9190 struct drm_connector *connector;
9191 int count;
9192
1aa4b628
DV		 9193 config->save_encoder_crtcs =
9194 kcalloc(dev->mode_config.num_encoder,
9195 sizeof(struct drm_crtc *), GFP_KERNEL);
9196 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9197 return -ENOMEM;
9198
1aa4b628
DV		 9199 config->save_connector_encoders =
9200 kcalloc(dev->mode_config.num_connector,
9201 sizeof(struct drm_encoder *), GFP_KERNEL);
9202 if (!config->save_connector_encoders)
85f9eb71
DV		 9203 return -ENOMEM;
9204
9205 /* Copy data. Note that driver private data is not affected.
9206 * Should anything bad happen only the expected state is
9207 * restored, not the drivers personal bookkeeping.
9208 */
85f9eb71
DV		 9209 count = 0;
9210 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9211 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9212 }
9213
9214 count = 0;
9215 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9216 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9217 }
9218
9219 return 0;
9220}
9221
9222static void intel_set_config_restore_state(struct drm_device *dev,
9223 struct intel_set_config *config)
9224{
9a935856
DV		 9225 struct intel_encoder *encoder;
9226 struct intel_connector *connector;
85f9eb71
DV		 9227 int count;
9228
85f9eb71 9229 count = 0;
9a935856
DV		 9230 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9231 encoder->new_crtc =
9232 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9233 }
9234
9235 count = 0;
9a935856
DV		 9236 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9237 connector->new_encoder =
9238 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9239 }
9240}
9241
e3de42b6 9242static bool
2e57f47d 9243is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9244{
9245 int i;
9246
2e57f47d
CW		 9247 if (set->num_connectors == 0)
9248 return false;
9249
9250 if (WARN_ON(set->connectors == NULL))
9251 return false;
9252
9253 for (i = 0; i < set->num_connectors; i++)
9254 if (set->connectors[i]->encoder &&
9255 set->connectors[i]->encoder->crtc == set->crtc &&
9256 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9257 return true;
9258
9259 return false;
9260}
9261
5e2b584e
DV		 9262static void
9263intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9264 struct intel_set_config *config)
9265{
9266
9267 /* We should be able to check here if the fb has the same properties
9268 * and then just flip_or_move it */
2e57f47d
CW		 9269 if (is_crtc_connector_off(set)) {
9270 config->mode_changed = true;
e3de42b6 9271 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9272 /* If we have no fb then treat it as a full mode set */
9273 if (set->crtc->fb == NULL) {
319d9827
JB		 9274 struct intel_crtc *intel_crtc =
9275 to_intel_crtc(set->crtc);
9276
9277 if (intel_crtc->active && i915_fastboot) {
9278 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9279 config->fb_changed = true;
9280 } else {
9281 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9282 config->mode_changed = true;
9283 }
5e2b584e
DV		 9284 } else if (set->fb == NULL) {
9285 config->mode_changed = true;
72f4901e
DV		 9286 } else if (set->fb->pixel_format !=
9287 set->crtc->fb->pixel_format) {
5e2b584e 9288 config->mode_changed = true;
e3de42b6 9289 } else {
5e2b584e 9290 config->fb_changed = true;
e3de42b6 9291 }
5e2b584e
DV		 9292 }
9293
835c5873 9294 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9295 config->fb_changed = true;
9296
9297 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9298 DRM_DEBUG_KMS("modes are different, full mode set\n");
9299 drm_mode_debug_printmodeline(&set->crtc->mode);
9300 drm_mode_debug_printmodeline(set->mode);
9301 config->mode_changed = true;
9302 }
a1d95703
CW		 9303
9304 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9305 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9306}
9307
2e431051 9308static int
9a935856
DV		 9309intel_modeset_stage_output_state(struct drm_device *dev,
9310 struct drm_mode_set *set,
9311 struct intel_set_config *config)
50f56119 9312{
85f9eb71 9313 struct drm_crtc *new_crtc;
9a935856
DV		 9314 struct intel_connector *connector;
9315 struct intel_encoder *encoder;
f3f08572 9316 int ro;
50f56119 9317
9abdda74 9318 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9319 * of connectors. For paranoia, double-check this. */
9320 WARN_ON(!set->fb && (set->num_connectors != 0));
9321 WARN_ON(set->fb && (set->num_connectors == 0));
9322
9a935856
DV		 9323 list_for_each_entry(connector, &dev->mode_config.connector_list,
9324 base.head) {
9325 /* Otherwise traverse passed in connector list and get encoders
9326 * for them. */
50f56119 9327 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9328 if (set->connectors[ro] == &connector->base) {
9329 connector->new_encoder = connector->encoder;
50f56119
DV		 9330 break;
9331 }
9332 }
9333
9a935856
DV		 9334 /* If we disable the crtc, disable all its connectors. Also, if
9335 * the connector is on the changing crtc but not on the new
9336 * connector list, disable it. */
9337 if ((!set->fb || ro == set->num_connectors) &&
9338 connector->base.encoder &&
9339 connector->base.encoder->crtc == set->crtc) {
9340 connector->new_encoder = NULL;
9341
9342 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9343 connector->base.base.id,
9344 drm_get_connector_name(&connector->base));
9345 }
9346
9347
9348 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9349 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9350 config->mode_changed = true;
50f56119
DV		 9351 }
9352 }
9a935856 9353 /* connector->new_encoder is now updated for all connectors. */
50f56119 9354
9a935856 9355 /* Update crtc of enabled connectors. */
9a935856
DV		 9356 list_for_each_entry(connector, &dev->mode_config.connector_list,
9357 base.head) {
9358 if (!connector->new_encoder)
50f56119
DV		 9359 continue;
9360
9a935856 9361 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9362
9363 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9364 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9365 new_crtc = set->crtc;
9366 }
9367
9368 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9369 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9370 new_crtc)) {
5e2b584e 9371 return -EINVAL;
50f56119 9372 }
9a935856
DV		 9373 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9374
9375 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9376 connector->base.base.id,
9377 drm_get_connector_name(&connector->base),
9378 new_crtc->base.id);
9379 }
9380
9381 /* Check for any encoders that needs to be disabled. */
9382 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9383 base.head) {
9384 list_for_each_entry(connector,
9385 &dev->mode_config.connector_list,
9386 base.head) {
9387 if (connector->new_encoder == encoder) {
9388 WARN_ON(!connector->new_encoder->new_crtc);
9389
9390 goto next_encoder;
9391 }
9392 }
9393 encoder->new_crtc = NULL;
9394next_encoder:
9395 /* Only now check for crtc changes so we don't miss encoders
9396 * that will be disabled. */
9397 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9398 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9399 config->mode_changed = true;
50f56119
DV		 9400 }
9401 }
9a935856 9402 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9403
2e431051
DV		 9404 return 0;
9405}
9406
9407static int intel_crtc_set_config(struct drm_mode_set *set)
9408{
9409 struct drm_device *dev;
2e431051
DV		 9410 struct drm_mode_set save_set;
9411 struct intel_set_config *config;
9412 int ret;
2e431051 9413
8d3e375e
DV		 9414 BUG_ON(!set);
9415 BUG_ON(!set->crtc);
9416 BUG_ON(!set->crtc->helper_private);
2e431051 9417
7e53f3a4
DV		 9418 /* Enforce sane interface api - has been abused by the fb helper. */
9419 BUG_ON(!set->mode && set->fb);
9420 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9421
2e431051
DV		 9422 if (set->fb) {
9423 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9424 set->crtc->base.id, set->fb->base.id,
9425 (int)set->num_connectors, set->x, set->y);
9426 } else {
9427 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9428 }
9429
9430 dev = set->crtc->dev;
9431
9432 ret = -ENOMEM;
9433 config = kzalloc(sizeof(*config), GFP_KERNEL);
9434 if (!config)
9435 goto out_config;
9436
9437 ret = intel_set_config_save_state(dev, config);
9438 if (ret)
9439 goto out_config;
9440
9441 save_set.crtc = set->crtc;
9442 save_set.mode = &set->crtc->mode;
9443 save_set.x = set->crtc->x;
9444 save_set.y = set->crtc->y;
9445 save_set.fb = set->crtc->fb;
9446
9447 /* Compute whether we need a full modeset, only an fb base update or no
9448 * change at all. In the future we might also check whether only the
9449 * mode changed, e.g. for LVDS where we only change the panel fitter in
9450 * such cases. */
9451 intel_set_config_compute_mode_changes(set, config);
9452
9a935856 9453 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9454 if (ret)
9455 goto fail;
9456
5e2b584e 9457 if (config->mode_changed) {
c0c36b94
CW		 9458 ret = intel_set_mode(set->crtc, set->mode,
9459 set->x, set->y, set->fb);
5e2b584e 9460 } else if (config->fb_changed) {
4878cae2
VS		 9461 intel_crtc_wait_for_pending_flips(set->crtc);
9462
4f660f49 9463 ret = intel_pipe_set_base(set->crtc,
94352cf9 9464 set->x, set->y, set->fb);
50f56119
DV		 9465 }
9466
2d05eae1 9467 if (ret) {
bf67dfeb
DV		 9468 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9469 set->crtc->base.id, ret);
50f56119 9470fail:
2d05eae1 9471 intel_set_config_restore_state(dev, config);
50f56119 9472
2d05eae1
CW		 9473 /* Try to restore the config */
9474 if (config->mode_changed &&
9475 intel_set_mode(save_set.crtc, save_set.mode,
9476 save_set.x, save_set.y, save_set.fb))
9477 DRM_ERROR("failed to restore config after modeset failure\n");
9478 }
50f56119 9479
d9e55608
DV		 9480out_config:
9481 intel_set_config_free(config);
50f56119
DV		 9482 return ret;
9483}
f6e5b160
CW		 9484
9485static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9486 .cursor_set = intel_crtc_cursor_set,
9487 .cursor_move = intel_crtc_cursor_move,
9488 .gamma_set = intel_crtc_gamma_set,
50f56119 9489 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9490 .destroy = intel_crtc_destroy,
9491 .page_flip = intel_crtc_page_flip,
9492};
9493
79f689aa
PZ		 9494static void intel_cpu_pll_init(struct drm_device *dev)
9495{
affa9354 9496 if (HAS_DDI(dev))
79f689aa
PZ		 9497 intel_ddi_pll_init(dev);
9498}
9499
5358901f
DV		 9500static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9501 struct intel_shared_dpll *pll,
9502 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9503{
5358901f 9504 uint32_t val;
ee7b9f93 9505
5358901f 9506 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9507 hw_state->dpll = val;
9508 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9509 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9510
9511 return val & DPLL_VCO_ENABLE;
9512}
9513
15bdd4cf
DV		 9514static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9515 struct intel_shared_dpll *pll)
9516{
9517 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9518 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9519}
9520
e7b903d2
DV		 9521static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9522 struct intel_shared_dpll *pll)
9523{
e7b903d2
DV		 9524 /* PCH refclock must be enabled first */
9525 assert_pch_refclk_enabled(dev_priv);
9526
15bdd4cf
DV		 9527 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9528
9529 /* Wait for the clocks to stabilize. */
9530 POSTING_READ(PCH_DPLL(pll->id));
9531 udelay(150);
9532
9533 /* The pixel multiplier can only be updated once the
9534 * DPLL is enabled and the clocks are stable.
9535 *
9536 * So write it again.
9537 */
9538 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9539 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9540 udelay(200);
9541}
9542
9543static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9544 struct intel_shared_dpll *pll)
9545{
9546 struct drm_device *dev = dev_priv->dev;
9547 struct intel_crtc *crtc;
e7b903d2
DV		 9548
9549 /* Make sure no transcoder isn't still depending on us. */
9550 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9551 if (intel_crtc_to_shared_dpll(crtc) == pll)
9552 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9553 }
9554
15bdd4cf
DV		 9555 I915_WRITE(PCH_DPLL(pll->id), 0);
9556 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9557 udelay(200);
9558}
9559
46edb027
DV		 9560static char *ibx_pch_dpll_names[] = {
9561 "PCH DPLL A",
9562 "PCH DPLL B",
9563};
9564
7c74ade1 9565static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9566{
e7b903d2 9567 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9568 int i;
9569
7c74ade1 9570 dev_priv->num_shared_dpll = 2;
ee7b9f93 9571
e72f9fbf 9572 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9573 dev_priv->shared_dplls[i].id = i;
9574 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9575 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9576 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9577 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9578 dev_priv->shared_dplls[i].get_hw_state =
9579 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9580 }
9581}
9582
7c74ade1
DV		 9583static void intel_shared_dpll_init(struct drm_device *dev)
9584{
e7b903d2 9585 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9586
9587 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9588 ibx_pch_dpll_init(dev);
9589 else
9590 dev_priv->num_shared_dpll = 0;
9591
9592 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9593 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9594 dev_priv->num_shared_dpll);
9595}
9596
b358d0a6 9597static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9598{
22fd0fab 9599 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9600 struct intel_crtc *intel_crtc;
9601 int i;
9602
955382f3 9603 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9604 if (intel_crtc == NULL)
9605 return;
9606
9607 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9608
9609 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9610 for (i = 0; i < 256; i++) {
9611 intel_crtc->lut_r[i] = i;
9612 intel_crtc->lut_g[i] = i;
9613 intel_crtc->lut_b[i] = i;
9614 }
9615
80824003
JB		 9616 /* Swap pipes & planes for FBC on pre-965 */
9617 intel_crtc->pipe = pipe;
9618 intel_crtc->plane = pipe;
e2e767ab 9619 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9620 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9621 intel_crtc->plane = !pipe;
80824003
JB		 9622 }
9623
22fd0fab
JB		 9624 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9625 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9626 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9627 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9628
79e53945 9629 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9630}
9631
08d7b3d1 9632int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9633 struct drm_file *file)
08d7b3d1 9634{
08d7b3d1 9635 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9636 struct drm_mode_object *drmmode_obj;
9637 struct intel_crtc *crtc;
08d7b3d1 9638
1cff8f6b
DV		 9639 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9640 return -ENODEV;
08d7b3d1 9641
c05422d5
DV		 9642 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9643 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9644
c05422d5 9645 if (!drmmode_obj) {
08d7b3d1
CW		 9646 DRM_ERROR("no such CRTC id\n");
9647 return -EINVAL;
9648 }
9649
c05422d5
DV		 9650 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9651 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9652
c05422d5 9653 return 0;
08d7b3d1
CW		 9654}
9655
66a9278e 9656static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9657{
66a9278e
DV		 9658 struct drm_device *dev = encoder->base.dev;
9659 struct intel_encoder *source_encoder;
79e53945 9660 int index_mask = 0;
79e53945
JB		 9661 int entry = 0;
9662
66a9278e
DV		 9663 list_for_each_entry(source_encoder,
9664 &dev->mode_config.encoder_list, base.head) {
9665
9666 if (encoder == source_encoder)
79e53945 9667 index_mask |= (1 << entry);
66a9278e
DV		 9668
9669 /* Intel hw has only one MUX where enocoders could be cloned. */
9670 if (encoder->cloneable && source_encoder->cloneable)
9671 index_mask |= (1 << entry);
9672
79e53945
JB		 9673 entry++;
9674 }
4ef69c7a 9675
79e53945
JB		 9676 return index_mask;
9677}
9678
4d302442
CW		 9679static bool has_edp_a(struct drm_device *dev)
9680{
9681 struct drm_i915_private *dev_priv = dev->dev_private;
9682
9683 if (!IS_MOBILE(dev))
9684 return false;
9685
9686 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9687 return false;
9688
9689 if (IS_GEN5(dev) &&
9690 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9691 return false;
9692
9693 return true;
9694}
9695
79e53945
JB		 9696static void intel_setup_outputs(struct drm_device *dev)
9697{
725e30ad 9698 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9699 struct intel_encoder *encoder;
cb0953d7 9700 bool dpd_is_edp = false;
79e53945 9701
c9093354 9702 intel_lvds_init(dev);
79e53945 9703
c40c0f5b 9704 if (!IS_ULT(dev))
79935fca 9705 intel_crt_init(dev);
cb0953d7 9706
affa9354 9707 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9708 int found;
9709
9710 /* Haswell uses DDI functions to detect digital outputs */
9711 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9712 /* DDI A only supports eDP */
9713 if (found)
9714 intel_ddi_init(dev, PORT_A);
9715
9716 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9717 * register */
9718 found = I915_READ(SFUSE_STRAP);
9719
9720 if (found & SFUSE_STRAP_DDIB_DETECTED)
9721 intel_ddi_init(dev, PORT_B);
9722 if (found & SFUSE_STRAP_DDIC_DETECTED)
9723 intel_ddi_init(dev, PORT_C);
9724 if (found & SFUSE_STRAP_DDID_DETECTED)
9725 intel_ddi_init(dev, PORT_D);
9726 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9727 int found;
270b3042
DV		 9728 dpd_is_edp = intel_dpd_is_edp(dev);
9729
9730 if (has_edp_a(dev))
9731 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9732
dc0fa718 9733 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9734 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9735 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9736 if (!found)
e2debe91 9737 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9738 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9739 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9740 }
9741
dc0fa718 9742 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9743 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9744
dc0fa718 9745 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9746 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9747
5eb08b69 9748 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9749 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9750
270b3042 9751 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9752 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9753 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9754 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9755 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9756 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9757 PORT_C);
9758 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9759 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9760 PORT_C);
9761 }
19c03924 9762
dc0fa718 9763 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9764 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9765 PORT_B);
67cfc203
VS		 9766 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9767 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9768 }
3cfca973
JN		 9769
9770 intel_dsi_init(dev);
103a196f 9771 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9772 bool found = false;
7d57382e 9773
e2debe91 9774 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9775 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9776 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9777 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9778 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9779 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9780 }
27185ae1 9781
e7281eab 9782 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9783 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9784 }
13520b05
KH		 9785
9786 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9787
e2debe91 9788 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9789 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9790 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9791 }
27185ae1 9792
e2debe91 9793 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9794
b01f2c3a
JB		 9795 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9796 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9797 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9798 }
e7281eab 9799 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9800 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9801 }
27185ae1 9802
b01f2c3a 9803 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9804 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9805 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9806 } else if (IS_GEN2(dev))
79e53945
JB		 9807 intel_dvo_init(dev);
9808
103a196f 9809 if (SUPPORTS_TV(dev))
79e53945
JB		 9810 intel_tv_init(dev);
9811
4ef69c7a
CW		 9812 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9813 encoder->base.possible_crtcs = encoder->crtc_mask;
9814 encoder->base.possible_clones =
66a9278e 9815 intel_encoder_clones(encoder);
79e53945 9816 }
47356eb6 9817
dde86e2d 9818 intel_init_pch_refclk(dev);
270b3042
DV		 9819
9820 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9821}
9822
ddfe1567
CW		 9823void intel_framebuffer_fini(struct intel_framebuffer *fb)
9824{
9825 drm_framebuffer_cleanup(&fb->base);
9826 drm_gem_object_unreference_unlocked(&fb->obj->base);
9827}
9828
79e53945
JB		 9829static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9830{
9831 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9832
ddfe1567 9833 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9834 kfree(intel_fb);
9835}
9836
9837static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9838 struct drm_file *file,
79e53945
JB		 9839 unsigned int *handle)
9840{
9841 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9842 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9843
05394f39 9844 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9845}
9846
9847static const struct drm_framebuffer_funcs intel_fb_funcs = {
9848 .destroy = intel_user_framebuffer_destroy,
9849 .create_handle = intel_user_framebuffer_create_handle,
9850};
9851
38651674
DA		 9852int intel_framebuffer_init(struct drm_device *dev,
9853 struct intel_framebuffer *intel_fb,
308e5bcb 9854 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9855 struct drm_i915_gem_object *obj)
79e53945 9856{
a35cdaa0 9857 int pitch_limit;
79e53945
JB		 9858 int ret;
9859
c16ed4be
CW		 9860 if (obj->tiling_mode == I915_TILING_Y) {
9861 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9862 return -EINVAL;
c16ed4be 9863 }
57cd6508 9864
c16ed4be
CW		 9865 if (mode_cmd->pitches[0] & 63) {
9866 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9867 mode_cmd->pitches[0]);
57cd6508 9868 return -EINVAL;
c16ed4be 9869 }
57cd6508 9870
a35cdaa0
CW		 9871 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9872 pitch_limit = 32*1024;
9873 } else if (INTEL_INFO(dev)->gen >= 4) {
9874 if (obj->tiling_mode)
9875 pitch_limit = 16*1024;
9876 else
9877 pitch_limit = 32*1024;
9878 } else if (INTEL_INFO(dev)->gen >= 3) {
9879 if (obj->tiling_mode)
9880 pitch_limit = 8*1024;
9881 else
9882 pitch_limit = 16*1024;
9883 } else
9884 /* XXX DSPC is limited to 4k tiled */
9885 pitch_limit = 8*1024;
9886
9887 if (mode_cmd->pitches[0] > pitch_limit) {
9888 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9889 obj->tiling_mode ? "tiled" : "linear",
9890 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9891 return -EINVAL;
c16ed4be 9892 }
5d7bd705
VS		 9893
9894 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9895 mode_cmd->pitches[0] != obj->stride) {
9896 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9897 mode_cmd->pitches[0], obj->stride);
5d7bd705 9898 return -EINVAL;
c16ed4be 9899 }
5d7bd705 9900
57779d06 9901 /* Reject formats not supported by any plane early. */
308e5bcb 9902 switch (mode_cmd->pixel_format) {
57779d06 9903 case DRM_FORMAT_C8:
04b3924d
VS		 9904 case DRM_FORMAT_RGB565:
9905 case DRM_FORMAT_XRGB8888:
9906 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9907 break;
9908 case DRM_FORMAT_XRGB1555:
9909 case DRM_FORMAT_ARGB1555:
c16ed4be 9910 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9911 DRM_DEBUG("unsupported pixel format: %s\n",
9912 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9913 return -EINVAL;
c16ed4be 9914 }
57779d06
VS		 9915 break;
9916 case DRM_FORMAT_XBGR8888:
9917 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9918 case DRM_FORMAT_XRGB2101010:
9919 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9920 case DRM_FORMAT_XBGR2101010:
9921 case DRM_FORMAT_ABGR2101010:
c16ed4be 9922 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9923 DRM_DEBUG("unsupported pixel format: %s\n",
9924 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9925 return -EINVAL;
c16ed4be 9926 }
b5626747 9927 break;
04b3924d
VS		 9928 case DRM_FORMAT_YUYV:
9929 case DRM_FORMAT_UYVY:
9930 case DRM_FORMAT_YVYU:
9931 case DRM_FORMAT_VYUY:
c16ed4be 9932 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9933 DRM_DEBUG("unsupported pixel format: %s\n",
9934 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9935 return -EINVAL;
c16ed4be 9936 }
57cd6508
CW		 9937 break;
9938 default:
4ee62c76
VS		 9939 DRM_DEBUG("unsupported pixel format: %s\n",
9940 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9941 return -EINVAL;
9942 }
9943
90f9a336
VS		 9944 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9945 if (mode_cmd->offsets[0] != 0)
9946 return -EINVAL;
9947
c7d73f6a
DV		 9948 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9949 intel_fb->obj = obj;
9950
79e53945
JB		 9951 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9952 if (ret) {
9953 DRM_ERROR("framebuffer init failed %d\n", ret);
9954 return ret;
9955 }
9956
79e53945
JB		 9957 return 0;
9958}
9959
79e53945
JB		 9960static struct drm_framebuffer *
9961intel_user_framebuffer_create(struct drm_device *dev,
9962 struct drm_file *filp,
308e5bcb 9963 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9964{
05394f39 9965 struct drm_i915_gem_object *obj;
79e53945 9966
308e5bcb
JB		 9967 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9968 mode_cmd->handles[0]));
c8725226 9969 if (&obj->base == NULL)
cce13ff7 9970 return ERR_PTR(-ENOENT);
79e53945 9971
d2dff872 9972 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9973}
9974
79e53945 9975static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9976 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9977 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9978};
9979
e70236a8
JB		 9980/* Set up chip specific display functions */
9981static void intel_init_display(struct drm_device *dev)
9982{
9983 struct drm_i915_private *dev_priv = dev->dev_private;
9984
ee9300bb
DV		 9985 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9986 dev_priv->display.find_dpll = g4x_find_best_dpll;
9987 else if (IS_VALLEYVIEW(dev))
9988 dev_priv->display.find_dpll = vlv_find_best_dpll;
9989 else if (IS_PINEVIEW(dev))
9990 dev_priv->display.find_dpll = pnv_find_best_dpll;
9991 else
9992 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9993
affa9354 9994 if (HAS_DDI(dev)) {
0e8ffe1b 9995 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9996 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9997 dev_priv->display.crtc_enable = haswell_crtc_enable;
9998 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9999 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10000 dev_priv->display.update_plane = ironlake_update_plane;
10001 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10002 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10003 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10004 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10005 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10006 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10007 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10008 } else if (IS_VALLEYVIEW(dev)) {
10009 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10010 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10011 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10012 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10013 dev_priv->display.off = i9xx_crtc_off;
10014 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10015 } else {
0e8ffe1b 10016 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10017 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10018 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10019 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10020 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10021 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10022 }
e70236a8 10023
e70236a8 10024 /* Returns the core display clock speed */
25eb05fc
JB		 10025 if (IS_VALLEYVIEW(dev))
10026 dev_priv->display.get_display_clock_speed =
10027 valleyview_get_display_clock_speed;
10028 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10029 dev_priv->display.get_display_clock_speed =
10030 i945_get_display_clock_speed;
10031 else if (IS_I915G(dev))
10032 dev_priv->display.get_display_clock_speed =
10033 i915_get_display_clock_speed;
257a7ffc 10034 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10035 dev_priv->display.get_display_clock_speed =
10036 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10037 else if (IS_PINEVIEW(dev))
10038 dev_priv->display.get_display_clock_speed =
10039 pnv_get_display_clock_speed;
e70236a8
JB		 10040 else if (IS_I915GM(dev))
10041 dev_priv->display.get_display_clock_speed =
10042 i915gm_get_display_clock_speed;
10043 else if (IS_I865G(dev))
10044 dev_priv->display.get_display_clock_speed =
10045 i865_get_display_clock_speed;
f0f8a9ce 10046 else if (IS_I85X(dev))
e70236a8
JB		 10047 dev_priv->display.get_display_clock_speed =
10048 i855_get_display_clock_speed;
10049 else /* 852, 830 */
10050 dev_priv->display.get_display_clock_speed =
10051 i830_get_display_clock_speed;
10052
7f8a8569 10053 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10054 if (IS_GEN5(dev)) {
674cf967 10055 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10056 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10057 } else if (IS_GEN6(dev)) {
674cf967 10058 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10059 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10060 } else if (IS_IVYBRIDGE(dev)) {
10061 /* FIXME: detect B0+ stepping and use auto training */
10062 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10063 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10064 dev_priv->display.modeset_global_resources =
10065 ivb_modeset_global_resources;
c82e4d26
ED		 10066 } else if (IS_HASWELL(dev)) {
10067 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10068 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10069 dev_priv->display.modeset_global_resources =
10070 haswell_modeset_global_resources;
a0e63c22 10071 }
6067aaea 10072 } else if (IS_G4X(dev)) {
e0dac65e 10073 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10074 }
8c9f3aaf
JB		 10075
10076 /* Default just returns -ENODEV to indicate unsupported */
10077 dev_priv->display.queue_flip = intel_default_queue_flip;
10078
10079 switch (INTEL_INFO(dev)->gen) {
10080 case 2:
10081 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10082 break;
10083
10084 case 3:
10085 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10086 break;
10087
10088 case 4:
10089 case 5:
10090 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10091 break;
10092
10093 case 6:
10094 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10095 break;
7c9017e5
JB		 10096 case 7:
10097 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10098 break;
8c9f3aaf 10099 }
e70236a8
JB		 10100}
10101
b690e96c
JB		 10102/*
10103 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10104 * resume, or other times. This quirk makes sure that's the case for
10105 * affected systems.
10106 */
0206e353 10107static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10108{
10109 struct drm_i915_private *dev_priv = dev->dev_private;
10110
10111 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10112 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10113}
10114
435793df
KP		 10115/*
10116 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10117 */
10118static void quirk_ssc_force_disable(struct drm_device *dev)
10119{
10120 struct drm_i915_private *dev_priv = dev->dev_private;
10121 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10122 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10123}
10124
4dca20ef 10125/*
5a15ab5b
CE		 10126 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10127 * brightness value
4dca20ef
CE		 10128 */
10129static void quirk_invert_brightness(struct drm_device *dev)
10130{
10131 struct drm_i915_private *dev_priv = dev->dev_private;
10132 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10133 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10134}
10135
e85843be
KM		 10136/*
10137 * Some machines (Dell XPS13) suffer broken backlight controls if
10138 * BLM_PCH_PWM_ENABLE is set.
10139 */
10140static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10141{
10142 struct drm_i915_private *dev_priv = dev->dev_private;
10143 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10144 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10145}
10146
b690e96c
JB		 10147struct intel_quirk {
10148 int device;
10149 int subsystem_vendor;
10150 int subsystem_device;
10151 void (*hook)(struct drm_device *dev);
10152};
10153
5f85f176
EE		 10154/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10155struct intel_dmi_quirk {
10156 void (*hook)(struct drm_device *dev);
10157 const struct dmi_system_id (*dmi_id_list)[];
10158};
10159
10160static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10161{
10162 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10163 return 1;
10164}
10165
10166static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10167 {
10168 .dmi_id_list = &(const struct dmi_system_id[]) {
10169 {
10170 .callback = intel_dmi_reverse_brightness,
10171 .ident = "NCR Corporation",
10172 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10173 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10174 },
10175 },
10176 { } /* terminating entry */
10177 },
10178 .hook = quirk_invert_brightness,
10179 },
10180};
10181
c43b5634 10182static struct intel_quirk intel_quirks[] = {
b690e96c 10183 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10184 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10185
b690e96c
JB		 10186 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10187 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10188
b690e96c
JB		 10189 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10190 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10191
ccd0d36e 10192 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10193 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10194 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10195
10196 /* Lenovo U160 cannot use SSC on LVDS */
10197 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10198
10199 /* Sony Vaio Y cannot use SSC on LVDS */
10200 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10201
ee1452d7
JN		 10202 /*
10203 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10204 * seem to use inverted backlight PWM.
10205 */
10206 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10207
10208 /* Dell XPS13 HD Sandy Bridge */
10209 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10210 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10211 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10212};
10213
10214static void intel_init_quirks(struct drm_device *dev)
10215{
10216 struct pci_dev *d = dev->pdev;
10217 int i;
10218
10219 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10220 struct intel_quirk *q = &intel_quirks[i];
10221
10222 if (d->device == q->device &&
10223 (d->subsystem_vendor == q->subsystem_vendor ||
10224 q->subsystem_vendor == PCI_ANY_ID) &&
10225 (d->subsystem_device == q->subsystem_device ||
10226 q->subsystem_device == PCI_ANY_ID))
10227 q->hook(dev);
10228 }
5f85f176
EE		 10229 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10230 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10231 intel_dmi_quirks[i].hook(dev);
10232 }
b690e96c
JB		 10233}
10234
9cce37f4
JB		 10235/* Disable the VGA plane that we never use */
10236static void i915_disable_vga(struct drm_device *dev)
10237{
10238 struct drm_i915_private *dev_priv = dev->dev_private;
10239 u8 sr1;
766aa1c4 10240 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10241
10242 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10243 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10244 sr1 = inb(VGA_SR_DATA);
10245 outb(sr1 | 1<<5, VGA_SR_DATA);
10246 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10247 udelay(300);
10248
10249 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10250 POSTING_READ(vga_reg);
10251}
10252
6e1b4fda 10253static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10254{
10255 /* Enable VGA memory on Intel HD */
10256 if (HAS_PCH_SPLIT(dev)) {
10257 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10258 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10259 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10260 VGA_RSRC_LEGACY_MEM |
10261 VGA_RSRC_NORMAL_IO |
10262 VGA_RSRC_NORMAL_MEM);
10263 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10264 }
10265}
10266
6e1b4fda
VS		 10267void i915_disable_vga_mem(struct drm_device *dev)
10268{
10269 /* Disable VGA memory on Intel HD */
10270 if (HAS_PCH_SPLIT(dev)) {
10271 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10272 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10273 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10274 VGA_RSRC_NORMAL_IO |
10275 VGA_RSRC_NORMAL_MEM);
10276 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10277 }
10278}
10279
f817586c
DV		 10280void intel_modeset_init_hw(struct drm_device *dev)
10281{
a8f78b58
ED		 10282 intel_prepare_ddi(dev);
10283
f817586c
DV		 10284 intel_init_clock_gating(dev);
10285
79f5b2c7 10286 mutex_lock(&dev->struct_mutex);
8090c6b9 10287 intel_enable_gt_powersave(dev);
79f5b2c7 10288 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10289}
10290
7d708ee4
ID		 10291void intel_modeset_suspend_hw(struct drm_device *dev)
10292{
10293 intel_suspend_hw(dev);
10294}
10295
79e53945
JB		 10296void intel_modeset_init(struct drm_device *dev)
10297{
652c393a 10298 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10299 int i, j, ret;
79e53945
JB		 10300
10301 drm_mode_config_init(dev);
10302
10303 dev->mode_config.min_width = 0;
10304 dev->mode_config.min_height = 0;
10305
019d96cb
DA		 10306 dev->mode_config.preferred_depth = 24;
10307 dev->mode_config.prefer_shadow = 1;
10308
e6ecefaa 10309 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10310
b690e96c
JB		 10311 intel_init_quirks(dev);
10312
1fa61106
ED		 10313 intel_init_pm(dev);
10314
e3c74757
BW		 10315 if (INTEL_INFO(dev)->num_pipes == 0)
10316 return;
10317
e70236a8
JB		 10318 intel_init_display(dev);
10319
a6c45cf0
CW		 10320 if (IS_GEN2(dev)) {
10321 dev->mode_config.max_width = 2048;
10322 dev->mode_config.max_height = 2048;
10323 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10324 dev->mode_config.max_width = 4096;
10325 dev->mode_config.max_height = 4096;
79e53945 10326 } else {
a6c45cf0
CW		 10327 dev->mode_config.max_width = 8192;
10328 dev->mode_config.max_height = 8192;
79e53945 10329 }
5d4545ae 10330 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10331
28c97730 10332 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10333 INTEL_INFO(dev)->num_pipes,
10334 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10335
08e2a7de 10336 for_each_pipe(i) {
79e53945 10337 intel_crtc_init(dev, i);
7f1f3851
JB		 10338 for (j = 0; j < dev_priv->num_plane; j++) {
10339 ret = intel_plane_init(dev, i, j);
10340 if (ret)
06da8da2
VS		 10341 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10342 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10343 }
79e53945
JB		 10344 }
10345
79f689aa 10346 intel_cpu_pll_init(dev);
e72f9fbf 10347 intel_shared_dpll_init(dev);
ee7b9f93 10348
9cce37f4
JB		 10349 /* Just disable it once at startup */
10350 i915_disable_vga(dev);
79e53945 10351 intel_setup_outputs(dev);
11be49eb
CW		 10352
10353 /* Just in case the BIOS is doing something questionable. */
10354 intel_disable_fbc(dev);
2c7111db
CW		 10355}
10356
24929352
DV		 10357static void
10358intel_connector_break_all_links(struct intel_connector *connector)
10359{
10360 connector->base.dpms = DRM_MODE_DPMS_OFF;
10361 connector->base.encoder = NULL;
10362 connector->encoder->connectors_active = false;
10363 connector->encoder->base.crtc = NULL;
10364}
10365
7fad798e
DV		 10366static void intel_enable_pipe_a(struct drm_device *dev)
10367{
10368 struct intel_connector *connector;
10369 struct drm_connector *crt = NULL;
10370 struct intel_load_detect_pipe load_detect_temp;
10371
10372 /* We can't just switch on the pipe A, we need to set things up with a
10373 * proper mode and output configuration. As a gross hack, enable pipe A
10374 * by enabling the load detect pipe once. */
10375 list_for_each_entry(connector,
10376 &dev->mode_config.connector_list,
10377 base.head) {
10378 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10379 crt = &connector->base;
10380 break;
10381 }
10382 }
10383
10384 if (!crt)
10385 return;
10386
10387 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10388 intel_release_load_detect_pipe(crt, &load_detect_temp);
10389
652c393a 10390
7fad798e
DV		 10391}
10392
fa555837
DV		 10393static bool
10394intel_check_plane_mapping(struct intel_crtc *crtc)
10395{
7eb552ae
BW		 10396 struct drm_device *dev = crtc->base.dev;
10397 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10398 u32 reg, val;
10399
7eb552ae 10400 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10401 return true;
10402
10403 reg = DSPCNTR(!crtc->plane);
10404 val = I915_READ(reg);
10405
10406 if ((val & DISPLAY_PLANE_ENABLE) &&
10407 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10408 return false;
10409
10410 return true;
10411}
10412
24929352
DV		 10413static void intel_sanitize_crtc(struct intel_crtc *crtc)
10414{
10415 struct drm_device *dev = crtc->base.dev;
10416 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10417 u32 reg;
24929352 10418
24929352 10419 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10420 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10421 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10422
10423 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10424 * disable the crtc (and hence change the state) if it is wrong. Note
10425 * that gen4+ has a fixed plane -> pipe mapping. */
10426 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10427 struct intel_connector *connector;
10428 bool plane;
10429
24929352
DV		 10430 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10431 crtc->base.base.id);
10432
10433 /* Pipe has the wrong plane attached and the plane is active.
10434 * Temporarily change the plane mapping and disable everything
10435 * ... */
10436 plane = crtc->plane;
10437 crtc->plane = !plane;
10438 dev_priv->display.crtc_disable(&crtc->base);
10439 crtc->plane = plane;
10440
10441 /* ... and break all links. */
10442 list_for_each_entry(connector, &dev->mode_config.connector_list,
10443 base.head) {
10444 if (connector->encoder->base.crtc != &crtc->base)
10445 continue;
10446
10447 intel_connector_break_all_links(connector);
10448 }
10449
10450 WARN_ON(crtc->active);
10451 crtc->base.enabled = false;
10452 }
24929352 10453
7fad798e
DV		 10454 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10455 crtc->pipe == PIPE_A && !crtc->active) {
10456 /* BIOS forgot to enable pipe A, this mostly happens after
10457 * resume. Force-enable the pipe to fix this, the update_dpms
10458 * call below we restore the pipe to the right state, but leave
10459 * the required bits on. */
10460 intel_enable_pipe_a(dev);
10461 }
10462
24929352
DV		 10463 /* Adjust the state of the output pipe according to whether we
10464 * have active connectors/encoders. */
10465 intel_crtc_update_dpms(&crtc->base);
10466
10467 if (crtc->active != crtc->base.enabled) {
10468 struct intel_encoder *encoder;
10469
10470 /* This can happen either due to bugs in the get_hw_state
10471 * functions or because the pipe is force-enabled due to the
10472 * pipe A quirk. */
10473 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10474 crtc->base.base.id,
10475 crtc->base.enabled ? "enabled" : "disabled",
10476 crtc->active ? "enabled" : "disabled");
10477
10478 crtc->base.enabled = crtc->active;
10479
10480 /* Because we only establish the connector -> encoder ->
10481 * crtc links if something is active, this means the
10482 * crtc is now deactivated. Break the links. connector
10483 * -> encoder links are only establish when things are
10484 * actually up, hence no need to break them. */
10485 WARN_ON(crtc->active);
10486
10487 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10488 WARN_ON(encoder->connectors_active);
10489 encoder->base.crtc = NULL;
10490 }
10491 }
10492}
10493
10494static void intel_sanitize_encoder(struct intel_encoder *encoder)
10495{
10496 struct intel_connector *connector;
10497 struct drm_device *dev = encoder->base.dev;
10498
10499 /* We need to check both for a crtc link (meaning that the
10500 * encoder is active and trying to read from a pipe) and the
10501 * pipe itself being active. */
10502 bool has_active_crtc = encoder->base.crtc &&
10503 to_intel_crtc(encoder->base.crtc)->active;
10504
10505 if (encoder->connectors_active && !has_active_crtc) {
10506 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10507 encoder->base.base.id,
10508 drm_get_encoder_name(&encoder->base));
10509
10510 /* Connector is active, but has no active pipe. This is
10511 * fallout from our resume register restoring. Disable
10512 * the encoder manually again. */
10513 if (encoder->base.crtc) {
10514 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10515 encoder->base.base.id,
10516 drm_get_encoder_name(&encoder->base));
10517 encoder->disable(encoder);
10518 }
10519
10520 /* Inconsistent output/port/pipe state happens presumably due to
10521 * a bug in one of the get_hw_state functions. Or someplace else
10522 * in our code, like the register restore mess on resume. Clamp
10523 * things to off as a safer default. */
10524 list_for_each_entry(connector,
10525 &dev->mode_config.connector_list,
10526 base.head) {
10527 if (connector->encoder != encoder)
10528 continue;
10529
10530 intel_connector_break_all_links(connector);
10531 }
10532 }
10533 /* Enabled encoders without active connectors will be fixed in
10534 * the crtc fixup. */
10535}
10536
44cec740 10537void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10538{
10539 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10540 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10541
8dc8a27c
PZ		 10542 /* This function can be called both from intel_modeset_setup_hw_state or
10543 * at a very early point in our resume sequence, where the power well
10544 * structures are not yet restored. Since this function is at a very
10545 * paranoid "someone might have enabled VGA while we were not looking"
10546 * level, just check if the power well is enabled instead of trying to
10547 * follow the "don't touch the power well if we don't need it" policy
10548 * the rest of the driver uses. */
10549 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10550 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10551 return;
10552
0fde901f
KM		 10553 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10554 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10555 i915_disable_vga(dev);
6e1b4fda 10556 i915_disable_vga_mem(dev);
0fde901f
KM		 10557 }
10558}
10559
30e984df 10560static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10561{
10562 struct drm_i915_private *dev_priv = dev->dev_private;
10563 enum pipe pipe;
24929352
DV		 10564 struct intel_crtc *crtc;
10565 struct intel_encoder *encoder;
10566 struct intel_connector *connector;
5358901f 10567 int i;
24929352 10568
0e8ffe1b
DV		 10569 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10570 base.head) {
88adfff1 10571 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10572
0e8ffe1b
DV		 10573 crtc->active = dev_priv->display.get_pipe_config(crtc,
10574 &crtc->config);
24929352
DV		 10575
10576 crtc->base.enabled = crtc->active;
10577
10578 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10579 crtc->base.base.id,
10580 crtc->active ? "enabled" : "disabled");
10581 }
10582
5358901f 10583 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10584 if (HAS_DDI(dev))
6441ab5f
PZ		 10585 intel_ddi_setup_hw_pll_state(dev);
10586
5358901f
DV		 10587 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10588 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10589
10590 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10591 pll->active = 0;
10592 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10593 base.head) {
10594 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10595 pll->active++;
10596 }
10597 pll->refcount = pll->active;
10598
35c95375
DV		 10599 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10600 pll->name, pll->refcount, pll->on);
5358901f
DV		 10601 }
10602
24929352
DV		 10603 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10604 base.head) {
10605 pipe = 0;
10606
10607 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10608 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10609 encoder->base.crtc = &crtc->base;
510d5f2f 10610 if (encoder->get_config)
045ac3b5 10611 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10612 } else {
10613 encoder->base.crtc = NULL;
10614 }
10615
10616 encoder->connectors_active = false;
10617 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10618 encoder->base.base.id,
10619 drm_get_encoder_name(&encoder->base),
10620 encoder->base.crtc ? "enabled" : "disabled",
10621 pipe);
10622 }
10623
10624 list_for_each_entry(connector, &dev->mode_config.connector_list,
10625 base.head) {
10626 if (connector->get_hw_state(connector)) {
10627 connector->base.dpms = DRM_MODE_DPMS_ON;
10628 connector->encoder->connectors_active = true;
10629 connector->base.encoder = &connector->encoder->base;
10630 } else {
10631 connector->base.dpms = DRM_MODE_DPMS_OFF;
10632 connector->base.encoder = NULL;
10633 }
10634 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10635 connector->base.base.id,
10636 drm_get_connector_name(&connector->base),
10637 connector->base.encoder ? "enabled" : "disabled");
10638 }
30e984df
DV		 10639}
10640
10641/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10642 * and i915 state tracking structures. */
10643void intel_modeset_setup_hw_state(struct drm_device *dev,
10644 bool force_restore)
10645{
10646 struct drm_i915_private *dev_priv = dev->dev_private;
10647 enum pipe pipe;
30e984df
DV		 10648 struct intel_crtc *crtc;
10649 struct intel_encoder *encoder;
35c95375 10650 int i;
30e984df
DV		 10651
10652 intel_modeset_readout_hw_state(dev);
24929352 10653
babea61d
JB		 10654 /*
10655 * Now that we have the config, copy it to each CRTC struct
10656 * Note that this could go away if we move to using crtc_config
10657 * checking everywhere.
10658 */
10659 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10660 base.head) {
10661 if (crtc->active && i915_fastboot) {
10662 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10663
10664 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10665 crtc->base.base.id);
10666 drm_mode_debug_printmodeline(&crtc->base.mode);
10667 }
10668 }
10669
24929352
DV		 10670 /* HW state is read out, now we need to sanitize this mess. */
10671 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10672 base.head) {
10673 intel_sanitize_encoder(encoder);
10674 }
10675
10676 for_each_pipe(pipe) {
10677 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10678 intel_sanitize_crtc(crtc);
c0b03411 10679 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10680 }
9a935856 10681
35c95375
DV		 10682 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10683 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10684
10685 if (!pll->on || pll->active)
10686 continue;
10687
10688 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10689
10690 pll->disable(dev_priv, pll);
10691 pll->on = false;
10692 }
10693
45e2b5f6 10694 if (force_restore) {
7d0bc1ea
VS		 10695 i915_redisable_vga(dev);
10696
f30da187
DV		 10697 /*
10698 * We need to use raw interfaces for restoring state to avoid
10699 * checking (bogus) intermediate states.
10700 */
45e2b5f6 10701 for_each_pipe(pipe) {
b5644d05
JB		 10702 struct drm_crtc *crtc =
10703 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10704
10705 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10706 crtc->fb);
45e2b5f6
DV		 10707 }
10708 } else {
10709 intel_modeset_update_staged_output_state(dev);
10710 }
8af6cf88
DV		 10711
10712 intel_modeset_check_state(dev);
2e938892
DV		 10713
10714 drm_mode_config_reset(dev);
2c7111db
CW		 10715}
10716
10717void intel_modeset_gem_init(struct drm_device *dev)
10718{
1833b134 10719 intel_modeset_init_hw(dev);
02e792fb
DV		 10720
10721 intel_setup_overlay(dev);
24929352 10722
45e2b5f6 10723 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10724}
10725
10726void intel_modeset_cleanup(struct drm_device *dev)
10727{
652c393a
JB		 10728 struct drm_i915_private *dev_priv = dev->dev_private;
10729 struct drm_crtc *crtc;
d9255d57 10730 struct drm_connector *connector;
652c393a 10731
fd0c0642
DV		 10732 /*
10733 * Interrupts and polling as the first thing to avoid creating havoc.
10734 * Too much stuff here (turning of rps, connectors, ...) would
10735 * experience fancy races otherwise.
10736 */
10737 drm_irq_uninstall(dev);
10738 cancel_work_sync(&dev_priv->hotplug_work);
10739 /*
10740 * Due to the hpd irq storm handling the hotplug work can re-arm the
10741 * poll handlers. Hence disable polling after hpd handling is shut down.
10742 */
f87ea761 10743 drm_kms_helper_poll_fini(dev);
fd0c0642 10744
652c393a
JB		 10745 mutex_lock(&dev->struct_mutex);
10746
723bfd70
JB		 10747 intel_unregister_dsm_handler();
10748
652c393a
JB		 10749 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10750 /* Skip inactive CRTCs */
10751 if (!crtc->fb)
10752 continue;
10753
3dec0095 10754 intel_increase_pllclock(crtc);
652c393a
JB		 10755 }
10756
973d04f9 10757 intel_disable_fbc(dev);
e70236a8 10758
6e1b4fda 10759 i915_enable_vga_mem(dev);
81b5c7bc 10760
8090c6b9 10761 intel_disable_gt_powersave(dev);
0cdab21f 10762
930ebb46
DV		 10763 ironlake_teardown_rc6(dev);
10764
69341a5e
KH		 10765 mutex_unlock(&dev->struct_mutex);
10766
1630fe75
CW		 10767 /* flush any delayed tasks or pending work */
10768 flush_scheduled_work();
10769
dc652f90
JN		 10770 /* destroy backlight, if any, before the connectors */
10771 intel_panel_destroy_backlight(dev);
10772
d9255d57
PZ		 10773 /* destroy the sysfs files before encoders/connectors */
10774 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10775 drm_sysfs_connector_remove(connector);
10776
79e53945 10777 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10778
10779 intel_cleanup_overlay(dev);
79e53945
JB		 10780}
10781
f1c79df3
ZW		 10782/*
10783 * Return which encoder is currently attached for connector.
10784 */
df0e9248 10785struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10786{
df0e9248
CW		 10787 return &intel_attached_encoder(connector)->base;
10788}
f1c79df3 10789
df0e9248
CW		 10790void intel_connector_attach_encoder(struct intel_connector *connector,
10791 struct intel_encoder *encoder)
10792{
10793 connector->encoder = encoder;
10794 drm_mode_connector_attach_encoder(&connector->base,
10795 &encoder->base);
79e53945 10796}
28d52043
DA		 10797
10798/*
10799 * set vga decode state - true == enable VGA decode
10800 */
10801int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10802{
10803 struct drm_i915_private *dev_priv = dev->dev_private;
10804 u16 gmch_ctrl;
10805
10806 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10807 if (state)
10808 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10809 else
10810 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10811 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10812 return 0;
10813}
c4a1d9e4 10814
c4a1d9e4 10815struct intel_display_error_state {
ff57f1b0
PZ		 10816
10817 u32 power_well_driver;
10818
63b66e5b
CW		 10819 int num_transcoders;
10820
c4a1d9e4
CW		 10821 struct intel_cursor_error_state {
10822 u32 control;
10823 u32 position;
10824 u32 base;
10825 u32 size;
52331309 10826 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10827
10828 struct intel_pipe_error_state {
c4a1d9e4 10829 u32 source;
52331309 10830 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10831
10832 struct intel_plane_error_state {
10833 u32 control;
10834 u32 stride;
10835 u32 size;
10836 u32 pos;
10837 u32 addr;
10838 u32 surface;
10839 u32 tile_offset;
52331309 10840 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10841
10842 struct intel_transcoder_error_state {
10843 enum transcoder cpu_transcoder;
10844
10845 u32 conf;
10846
10847 u32 htotal;
10848 u32 hblank;
10849 u32 hsync;
10850 u32 vtotal;
10851 u32 vblank;
10852 u32 vsync;
10853 } transcoder[4];
c4a1d9e4
CW		 10854};
10855
10856struct intel_display_error_state *
10857intel_display_capture_error_state(struct drm_device *dev)
10858{
0206e353 10859 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10860 struct intel_display_error_state *error;
63b66e5b
CW		 10861 int transcoders[] = {
10862 TRANSCODER_A,
10863 TRANSCODER_B,
10864 TRANSCODER_C,
10865 TRANSCODER_EDP,
10866 };
c4a1d9e4
CW		 10867 int i;
10868
63b66e5b
CW		 10869 if (INTEL_INFO(dev)->num_pipes == 0)
10870 return NULL;
10871
c4a1d9e4
CW		 10872 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10873 if (error == NULL)
10874 return NULL;
10875
ff57f1b0
PZ		 10876 if (HAS_POWER_WELL(dev))
10877 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10878
52331309 10879 for_each_pipe(i) {
a18c4c3d
PZ		 10880 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10881 error->cursor[i].control = I915_READ(CURCNTR(i));
10882 error->cursor[i].position = I915_READ(CURPOS(i));
10883 error->cursor[i].base = I915_READ(CURBASE(i));
10884 } else {
10885 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10886 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10887 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10888 }
c4a1d9e4
CW		 10889
10890 error->plane[i].control = I915_READ(DSPCNTR(i));
10891 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10892 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10893 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10894 error->plane[i].pos = I915_READ(DSPPOS(i));
10895 }
ca291363
PZ		 10896 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10897 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10898 if (INTEL_INFO(dev)->gen >= 4) {
10899 error->plane[i].surface = I915_READ(DSPSURF(i));
10900 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10901 }
10902
c4a1d9e4 10903 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10904 }
10905
10906 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10907 if (HAS_DDI(dev_priv->dev))
10908 error->num_transcoders++; /* Account for eDP. */
10909
10910 for (i = 0; i < error->num_transcoders; i++) {
10911 enum transcoder cpu_transcoder = transcoders[i];
10912
10913 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10914
10915 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10916 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10917 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10918 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10919 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10920 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10921 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10922 }
10923
12d217c7
PZ		 10924 /* In the code above we read the registers without checking if the power
10925 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10926 * prevent the next I915_WRITE from detecting it and printing an error
10927 * message. */
907b28c5 10928 intel_uncore_clear_errors(dev);
12d217c7 10929
c4a1d9e4
CW		 10930 return error;
10931}
10932
edc3d884
MK		 10933#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10934
c4a1d9e4 10935void
edc3d884 10936intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10937 struct drm_device *dev,
10938 struct intel_display_error_state *error)
10939{
10940 int i;
10941
63b66e5b
CW		 10942 if (!error)
10943 return;
10944
edc3d884 10945 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10946 if (HAS_POWER_WELL(dev))
edc3d884 10947 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10948 error->power_well_driver);
52331309 10949 for_each_pipe(i) {
edc3d884 10950 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10951 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10952
10953 err_printf(m, "Plane [%d]:\n", i);
10954 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10955 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10956 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10957 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10958 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10959 }
4b71a570 10960 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10961 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10962 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10963 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10964 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10965 }
10966
edc3d884
MK		 10967 err_printf(m, "Cursor [%d]:\n", i);
10968 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10969 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10970 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10971 }
63b66e5b
CW		 10972
10973 for (i = 0; i < error->num_transcoders; i++) {
10974 err_printf(m, " CPU transcoder: %c\n",
10975 transcoder_name(error->transcoder[i].cpu_transcoder));
10976 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10977 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10978 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10979 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10980 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10981 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10982 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10983 }
c4a1d9e4 10984}
Linux kernel - Deliverables
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