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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
79e53945 | 47 | |
465c120c MR |
48 | /* Primary plane formats supported by all gen */ |
49 | #define COMMON_PRIMARY_FORMATS \ | |
50 | DRM_FORMAT_C8, \ | |
51 | DRM_FORMAT_RGB565, \ | |
52 | DRM_FORMAT_XRGB8888, \ | |
53 | DRM_FORMAT_ARGB8888 | |
54 | ||
55 | /* Primary plane formats for gen <= 3 */ | |
56 | static const uint32_t intel_primary_formats_gen2[] = { | |
57 | COMMON_PRIMARY_FORMATS, | |
58 | DRM_FORMAT_XRGB1555, | |
59 | DRM_FORMAT_ARGB1555, | |
60 | }; | |
61 | ||
62 | /* Primary plane formats for gen >= 4 */ | |
63 | static const uint32_t intel_primary_formats_gen4[] = { | |
64 | COMMON_PRIMARY_FORMATS, \ | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_ABGR8888, | |
67 | DRM_FORMAT_XRGB2101010, | |
68 | DRM_FORMAT_ARGB2101010, | |
69 | DRM_FORMAT_XBGR2101010, | |
70 | DRM_FORMAT_ABGR2101010, | |
71 | }; | |
72 | ||
3d7d6510 MR |
73 | /* Cursor formats */ |
74 | static const uint32_t intel_cursor_formats[] = { | |
75 | DRM_FORMAT_ARGB8888, | |
76 | }; | |
77 | ||
6b383a7f | 78 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 79 | |
f1f644dc | 80 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 81 | struct intel_crtc_state *pipe_config); |
18442d08 | 82 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 83 | struct intel_crtc_state *pipe_config); |
f1f644dc | 84 | |
e7457a9a | 85 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
83a57153 ACO |
86 | int x, int y, struct drm_framebuffer *old_fb, |
87 | struct drm_atomic_state *state); | |
eb1bfe80 JB |
88 | static int intel_framebuffer_init(struct drm_device *dev, |
89 | struct intel_framebuffer *ifb, | |
90 | struct drm_mode_fb_cmd2 *mode_cmd, | |
91 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
92 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
93 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 94 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
95 | struct intel_link_m_n *m_n, |
96 | struct intel_link_m_n *m2_n2); | |
29407aab | 97 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
98 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
99 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 100 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 101 | const struct intel_crtc_state *pipe_config); |
d288f65f | 102 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 103 | const struct intel_crtc_state *pipe_config); |
ea2c67bb MR |
104 | static void intel_begin_crtc_commit(struct drm_crtc *crtc); |
105 | static void intel_finish_crtc_commit(struct drm_crtc *crtc); | |
549e2bfb CK |
106 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
107 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
108 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
109 | int num_connectors); | |
ce22dba9 ML |
110 | static void intel_crtc_enable_planes(struct drm_crtc *crtc); |
111 | static void intel_crtc_disable_planes(struct drm_crtc *crtc); | |
e7457a9a | 112 | |
0e32b39c DA |
113 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
114 | { | |
115 | if (!connector->mst_port) | |
116 | return connector->encoder; | |
117 | else | |
118 | return &connector->mst_port->mst_encoders[pipe]->base; | |
119 | } | |
120 | ||
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
d2acd215 DV |
136 | int |
137 | intel_pch_rawclk(struct drm_device *dev) | |
138 | { | |
139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
140 | ||
141 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
142 | ||
143 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
144 | } | |
145 | ||
021357ac CW |
146 | static inline u32 /* units of 100MHz */ |
147 | intel_fdi_link_freq(struct drm_device *dev) | |
148 | { | |
8b99e68c CW |
149 | if (IS_GEN5(dev)) { |
150 | struct drm_i915_private *dev_priv = dev->dev_private; | |
151 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
152 | } else | |
153 | return 27; | |
021357ac CW |
154 | } |
155 | ||
5d536e28 | 156 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 157 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 158 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 159 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
160 | .m = { .min = 96, .max = 140 }, |
161 | .m1 = { .min = 18, .max = 26 }, | |
162 | .m2 = { .min = 6, .max = 16 }, | |
163 | .p = { .min = 4, .max = 128 }, | |
164 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
165 | .p2 = { .dot_limit = 165000, |
166 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
167 | }; |
168 | ||
5d536e28 DV |
169 | static const intel_limit_t intel_limits_i8xx_dvo = { |
170 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 171 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 172 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
173 | .m = { .min = 96, .max = 140 }, |
174 | .m1 = { .min = 18, .max = 26 }, | |
175 | .m2 = { .min = 6, .max = 16 }, | |
176 | .p = { .min = 4, .max = 128 }, | |
177 | .p1 = { .min = 2, .max = 33 }, | |
178 | .p2 = { .dot_limit = 165000, | |
179 | .p2_slow = 4, .p2_fast = 4 }, | |
180 | }; | |
181 | ||
e4b36699 | 182 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 183 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 184 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 185 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
186 | .m = { .min = 96, .max = 140 }, |
187 | .m1 = { .min = 18, .max = 26 }, | |
188 | .m2 = { .min = 6, .max = 16 }, | |
189 | .p = { .min = 4, .max = 128 }, | |
190 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
191 | .p2 = { .dot_limit = 165000, |
192 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 193 | }; |
273e27ca | 194 | |
e4b36699 | 195 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
196 | .dot = { .min = 20000, .max = 400000 }, |
197 | .vco = { .min = 1400000, .max = 2800000 }, | |
198 | .n = { .min = 1, .max = 6 }, | |
199 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
200 | .m1 = { .min = 8, .max = 18 }, |
201 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
202 | .p = { .min = 5, .max = 80 }, |
203 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
204 | .p2 = { .dot_limit = 200000, |
205 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
206 | }; |
207 | ||
208 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
209 | .dot = { .min = 20000, .max = 400000 }, |
210 | .vco = { .min = 1400000, .max = 2800000 }, | |
211 | .n = { .min = 1, .max = 6 }, | |
212 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
213 | .m1 = { .min = 8, .max = 18 }, |
214 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
215 | .p = { .min = 7, .max = 98 }, |
216 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
217 | .p2 = { .dot_limit = 112000, |
218 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
219 | }; |
220 | ||
273e27ca | 221 | |
e4b36699 | 222 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
223 | .dot = { .min = 25000, .max = 270000 }, |
224 | .vco = { .min = 1750000, .max = 3500000}, | |
225 | .n = { .min = 1, .max = 4 }, | |
226 | .m = { .min = 104, .max = 138 }, | |
227 | .m1 = { .min = 17, .max = 23 }, | |
228 | .m2 = { .min = 5, .max = 11 }, | |
229 | .p = { .min = 10, .max = 30 }, | |
230 | .p1 = { .min = 1, .max = 3}, | |
231 | .p2 = { .dot_limit = 270000, | |
232 | .p2_slow = 10, | |
233 | .p2_fast = 10 | |
044c7c41 | 234 | }, |
e4b36699 KP |
235 | }; |
236 | ||
237 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
238 | .dot = { .min = 22000, .max = 400000 }, |
239 | .vco = { .min = 1750000, .max = 3500000}, | |
240 | .n = { .min = 1, .max = 4 }, | |
241 | .m = { .min = 104, .max = 138 }, | |
242 | .m1 = { .min = 16, .max = 23 }, | |
243 | .m2 = { .min = 5, .max = 11 }, | |
244 | .p = { .min = 5, .max = 80 }, | |
245 | .p1 = { .min = 1, .max = 8}, | |
246 | .p2 = { .dot_limit = 165000, | |
247 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
248 | }; |
249 | ||
250 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
251 | .dot = { .min = 20000, .max = 115000 }, |
252 | .vco = { .min = 1750000, .max = 3500000 }, | |
253 | .n = { .min = 1, .max = 3 }, | |
254 | .m = { .min = 104, .max = 138 }, | |
255 | .m1 = { .min = 17, .max = 23 }, | |
256 | .m2 = { .min = 5, .max = 11 }, | |
257 | .p = { .min = 28, .max = 112 }, | |
258 | .p1 = { .min = 2, .max = 8 }, | |
259 | .p2 = { .dot_limit = 0, | |
260 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 261 | }, |
e4b36699 KP |
262 | }; |
263 | ||
264 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
265 | .dot = { .min = 80000, .max = 224000 }, |
266 | .vco = { .min = 1750000, .max = 3500000 }, | |
267 | .n = { .min = 1, .max = 3 }, | |
268 | .m = { .min = 104, .max = 138 }, | |
269 | .m1 = { .min = 17, .max = 23 }, | |
270 | .m2 = { .min = 5, .max = 11 }, | |
271 | .p = { .min = 14, .max = 42 }, | |
272 | .p1 = { .min = 2, .max = 6 }, | |
273 | .p2 = { .dot_limit = 0, | |
274 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 275 | }, |
e4b36699 KP |
276 | }; |
277 | ||
f2b115e6 | 278 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
279 | .dot = { .min = 20000, .max = 400000}, |
280 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 281 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
282 | .n = { .min = 3, .max = 6 }, |
283 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 284 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
285 | .m1 = { .min = 0, .max = 0 }, |
286 | .m2 = { .min = 0, .max = 254 }, | |
287 | .p = { .min = 5, .max = 80 }, | |
288 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
289 | .p2 = { .dot_limit = 200000, |
290 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
291 | }; |
292 | ||
f2b115e6 | 293 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
294 | .dot = { .min = 20000, .max = 400000 }, |
295 | .vco = { .min = 1700000, .max = 3500000 }, | |
296 | .n = { .min = 3, .max = 6 }, | |
297 | .m = { .min = 2, .max = 256 }, | |
298 | .m1 = { .min = 0, .max = 0 }, | |
299 | .m2 = { .min = 0, .max = 254 }, | |
300 | .p = { .min = 7, .max = 112 }, | |
301 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
302 | .p2 = { .dot_limit = 112000, |
303 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
304 | }; |
305 | ||
273e27ca EA |
306 | /* Ironlake / Sandybridge |
307 | * | |
308 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
309 | * the range value for them is (actual_value - 2). | |
310 | */ | |
b91ad0ec | 311 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
312 | .dot = { .min = 25000, .max = 350000 }, |
313 | .vco = { .min = 1760000, .max = 3510000 }, | |
314 | .n = { .min = 1, .max = 5 }, | |
315 | .m = { .min = 79, .max = 127 }, | |
316 | .m1 = { .min = 12, .max = 22 }, | |
317 | .m2 = { .min = 5, .max = 9 }, | |
318 | .p = { .min = 5, .max = 80 }, | |
319 | .p1 = { .min = 1, .max = 8 }, | |
320 | .p2 = { .dot_limit = 225000, | |
321 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
322 | }; |
323 | ||
b91ad0ec | 324 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
325 | .dot = { .min = 25000, .max = 350000 }, |
326 | .vco = { .min = 1760000, .max = 3510000 }, | |
327 | .n = { .min = 1, .max = 3 }, | |
328 | .m = { .min = 79, .max = 118 }, | |
329 | .m1 = { .min = 12, .max = 22 }, | |
330 | .m2 = { .min = 5, .max = 9 }, | |
331 | .p = { .min = 28, .max = 112 }, | |
332 | .p1 = { .min = 2, .max = 8 }, | |
333 | .p2 = { .dot_limit = 225000, | |
334 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
335 | }; |
336 | ||
337 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
338 | .dot = { .min = 25000, .max = 350000 }, |
339 | .vco = { .min = 1760000, .max = 3510000 }, | |
340 | .n = { .min = 1, .max = 3 }, | |
341 | .m = { .min = 79, .max = 127 }, | |
342 | .m1 = { .min = 12, .max = 22 }, | |
343 | .m2 = { .min = 5, .max = 9 }, | |
344 | .p = { .min = 14, .max = 56 }, | |
345 | .p1 = { .min = 2, .max = 8 }, | |
346 | .p2 = { .dot_limit = 225000, | |
347 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
348 | }; |
349 | ||
273e27ca | 350 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 351 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
352 | .dot = { .min = 25000, .max = 350000 }, |
353 | .vco = { .min = 1760000, .max = 3510000 }, | |
354 | .n = { .min = 1, .max = 2 }, | |
355 | .m = { .min = 79, .max = 126 }, | |
356 | .m1 = { .min = 12, .max = 22 }, | |
357 | .m2 = { .min = 5, .max = 9 }, | |
358 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 359 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
360 | .p2 = { .dot_limit = 225000, |
361 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
362 | }; |
363 | ||
364 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
365 | .dot = { .min = 25000, .max = 350000 }, |
366 | .vco = { .min = 1760000, .max = 3510000 }, | |
367 | .n = { .min = 1, .max = 3 }, | |
368 | .m = { .min = 79, .max = 126 }, | |
369 | .m1 = { .min = 12, .max = 22 }, | |
370 | .m2 = { .min = 5, .max = 9 }, | |
371 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 372 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
373 | .p2 = { .dot_limit = 225000, |
374 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
375 | }; |
376 | ||
dc730512 | 377 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
378 | /* |
379 | * These are the data rate limits (measured in fast clocks) | |
380 | * since those are the strictest limits we have. The fast | |
381 | * clock and actual rate limits are more relaxed, so checking | |
382 | * them would make no difference. | |
383 | */ | |
384 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 385 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 386 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
387 | .m1 = { .min = 2, .max = 3 }, |
388 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 389 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 390 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
391 | }; |
392 | ||
ef9348c8 CML |
393 | static const intel_limit_t intel_limits_chv = { |
394 | /* | |
395 | * These are the data rate limits (measured in fast clocks) | |
396 | * since those are the strictest limits we have. The fast | |
397 | * clock and actual rate limits are more relaxed, so checking | |
398 | * them would make no difference. | |
399 | */ | |
400 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 401 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
402 | .n = { .min = 1, .max = 1 }, |
403 | .m1 = { .min = 2, .max = 2 }, | |
404 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
405 | .p1 = { .min = 2, .max = 4 }, | |
406 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
407 | }; | |
408 | ||
5ab7b0b7 ID |
409 | static const intel_limit_t intel_limits_bxt = { |
410 | /* FIXME: find real dot limits */ | |
411 | .dot = { .min = 0, .max = INT_MAX }, | |
412 | .vco = { .min = 4800000, .max = 6480000 }, | |
413 | .n = { .min = 1, .max = 1 }, | |
414 | .m1 = { .min = 2, .max = 2 }, | |
415 | /* FIXME: find real m2 limits */ | |
416 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
417 | .p1 = { .min = 2, .max = 4 }, | |
418 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
419 | }; | |
420 | ||
6b4bf1c4 VS |
421 | static void vlv_clock(int refclk, intel_clock_t *clock) |
422 | { | |
423 | clock->m = clock->m1 * clock->m2; | |
424 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
425 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
426 | return; | |
fb03ac01 VS |
427 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
428 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
429 | } |
430 | ||
e0638cdf PZ |
431 | /** |
432 | * Returns whether any output on the specified pipe is of the specified type | |
433 | */ | |
4093561b | 434 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 435 | { |
409ee761 | 436 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
437 | struct intel_encoder *encoder; |
438 | ||
409ee761 | 439 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
440 | if (encoder->type == type) |
441 | return true; | |
442 | ||
443 | return false; | |
444 | } | |
445 | ||
d0737e1d ACO |
446 | /** |
447 | * Returns whether any output on the specified pipe will have the specified | |
448 | * type after a staged modeset is complete, i.e., the same as | |
449 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
450 | * encoder->crtc. | |
451 | */ | |
a93e255f ACO |
452 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
453 | int type) | |
d0737e1d | 454 | { |
a93e255f | 455 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 456 | struct drm_connector *connector; |
a93e255f | 457 | struct drm_connector_state *connector_state; |
d0737e1d | 458 | struct intel_encoder *encoder; |
a93e255f ACO |
459 | int i, num_connectors = 0; |
460 | ||
da3ced29 | 461 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
462 | if (connector_state->crtc != crtc_state->base.crtc) |
463 | continue; | |
464 | ||
465 | num_connectors++; | |
d0737e1d | 466 | |
a93e255f ACO |
467 | encoder = to_intel_encoder(connector_state->best_encoder); |
468 | if (encoder->type == type) | |
d0737e1d | 469 | return true; |
a93e255f ACO |
470 | } |
471 | ||
472 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
473 | |
474 | return false; | |
475 | } | |
476 | ||
a93e255f ACO |
477 | static const intel_limit_t * |
478 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 479 | { |
a93e255f | 480 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 481 | const intel_limit_t *limit; |
b91ad0ec | 482 | |
a93e255f | 483 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 484 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 485 | if (refclk == 100000) |
b91ad0ec ZW |
486 | limit = &intel_limits_ironlake_dual_lvds_100m; |
487 | else | |
488 | limit = &intel_limits_ironlake_dual_lvds; | |
489 | } else { | |
1b894b59 | 490 | if (refclk == 100000) |
b91ad0ec ZW |
491 | limit = &intel_limits_ironlake_single_lvds_100m; |
492 | else | |
493 | limit = &intel_limits_ironlake_single_lvds; | |
494 | } | |
c6bb3538 | 495 | } else |
b91ad0ec | 496 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
497 | |
498 | return limit; | |
499 | } | |
500 | ||
a93e255f ACO |
501 | static const intel_limit_t * |
502 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 503 | { |
a93e255f | 504 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
505 | const intel_limit_t *limit; |
506 | ||
a93e255f | 507 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 508 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 509 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 510 | else |
e4b36699 | 511 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
512 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
513 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 514 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 515 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 516 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 517 | } else /* The option is for other outputs */ |
e4b36699 | 518 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
519 | |
520 | return limit; | |
521 | } | |
522 | ||
a93e255f ACO |
523 | static const intel_limit_t * |
524 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 525 | { |
a93e255f | 526 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
527 | const intel_limit_t *limit; |
528 | ||
5ab7b0b7 ID |
529 | if (IS_BROXTON(dev)) |
530 | limit = &intel_limits_bxt; | |
531 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 532 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 533 | else if (IS_G4X(dev)) { |
a93e255f | 534 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 535 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 536 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 537 | limit = &intel_limits_pineview_lvds; |
2177832f | 538 | else |
f2b115e6 | 539 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
540 | } else if (IS_CHERRYVIEW(dev)) { |
541 | limit = &intel_limits_chv; | |
a0c4da24 | 542 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 543 | limit = &intel_limits_vlv; |
a6c45cf0 | 544 | } else if (!IS_GEN2(dev)) { |
a93e255f | 545 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
546 | limit = &intel_limits_i9xx_lvds; |
547 | else | |
548 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 549 | } else { |
a93e255f | 550 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 551 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 552 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 553 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
554 | else |
555 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
556 | } |
557 | return limit; | |
558 | } | |
559 | ||
f2b115e6 AJ |
560 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
561 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 562 | { |
2177832f SL |
563 | clock->m = clock->m2 + 2; |
564 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
565 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
566 | return; | |
fb03ac01 VS |
567 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
568 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
569 | } |
570 | ||
7429e9d4 DV |
571 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
572 | { | |
573 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
574 | } | |
575 | ||
ac58c3f0 | 576 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 577 | { |
7429e9d4 | 578 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 579 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
580 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
581 | return; | |
fb03ac01 VS |
582 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
583 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
584 | } |
585 | ||
ef9348c8 CML |
586 | static void chv_clock(int refclk, intel_clock_t *clock) |
587 | { | |
588 | clock->m = clock->m1 * clock->m2; | |
589 | clock->p = clock->p1 * clock->p2; | |
590 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
591 | return; | |
592 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
593 | clock->n << 22); | |
594 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
595 | } | |
596 | ||
7c04d1d9 | 597 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
598 | /** |
599 | * Returns whether the given set of divisors are valid for a given refclk with | |
600 | * the given connectors. | |
601 | */ | |
602 | ||
1b894b59 CW |
603 | static bool intel_PLL_is_valid(struct drm_device *dev, |
604 | const intel_limit_t *limit, | |
605 | const intel_clock_t *clock) | |
79e53945 | 606 | { |
f01b7962 VS |
607 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
608 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 609 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 610 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 611 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 612 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 613 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 614 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 615 | |
5ab7b0b7 | 616 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
f01b7962 VS |
617 | if (clock->m1 <= clock->m2) |
618 | INTELPllInvalid("m1 <= m2\n"); | |
619 | ||
5ab7b0b7 | 620 | if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
621 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
622 | INTELPllInvalid("p out of range\n"); | |
623 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
624 | INTELPllInvalid("m out of range\n"); | |
625 | } | |
626 | ||
79e53945 | 627 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 628 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
629 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
630 | * connector, etc., rather than just a single range. | |
631 | */ | |
632 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 633 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
634 | |
635 | return true; | |
636 | } | |
637 | ||
d4906093 | 638 | static bool |
a93e255f ACO |
639 | i9xx_find_best_dpll(const intel_limit_t *limit, |
640 | struct intel_crtc_state *crtc_state, | |
cec2f356 SP |
641 | int target, int refclk, intel_clock_t *match_clock, |
642 | intel_clock_t *best_clock) | |
79e53945 | 643 | { |
a93e255f | 644 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 645 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 646 | intel_clock_t clock; |
79e53945 JB |
647 | int err = target; |
648 | ||
a93e255f | 649 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 650 | /* |
a210b028 DV |
651 | * For LVDS just rely on its current settings for dual-channel. |
652 | * We haven't figured out how to reliably set up different | |
653 | * single/dual channel state, if we even can. | |
79e53945 | 654 | */ |
1974cad0 | 655 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
656 | clock.p2 = limit->p2.p2_fast; |
657 | else | |
658 | clock.p2 = limit->p2.p2_slow; | |
659 | } else { | |
660 | if (target < limit->p2.dot_limit) | |
661 | clock.p2 = limit->p2.p2_slow; | |
662 | else | |
663 | clock.p2 = limit->p2.p2_fast; | |
664 | } | |
665 | ||
0206e353 | 666 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 667 | |
42158660 ZY |
668 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
669 | clock.m1++) { | |
670 | for (clock.m2 = limit->m2.min; | |
671 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 672 | if (clock.m2 >= clock.m1) |
42158660 ZY |
673 | break; |
674 | for (clock.n = limit->n.min; | |
675 | clock.n <= limit->n.max; clock.n++) { | |
676 | for (clock.p1 = limit->p1.min; | |
677 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
678 | int this_err; |
679 | ||
ac58c3f0 DV |
680 | i9xx_clock(refclk, &clock); |
681 | if (!intel_PLL_is_valid(dev, limit, | |
682 | &clock)) | |
683 | continue; | |
684 | if (match_clock && | |
685 | clock.p != match_clock->p) | |
686 | continue; | |
687 | ||
688 | this_err = abs(clock.dot - target); | |
689 | if (this_err < err) { | |
690 | *best_clock = clock; | |
691 | err = this_err; | |
692 | } | |
693 | } | |
694 | } | |
695 | } | |
696 | } | |
697 | ||
698 | return (err != target); | |
699 | } | |
700 | ||
701 | static bool | |
a93e255f ACO |
702 | pnv_find_best_dpll(const intel_limit_t *limit, |
703 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
704 | int target, int refclk, intel_clock_t *match_clock, |
705 | intel_clock_t *best_clock) | |
79e53945 | 706 | { |
a93e255f | 707 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 708 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 709 | intel_clock_t clock; |
79e53945 JB |
710 | int err = target; |
711 | ||
a93e255f | 712 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 713 | /* |
a210b028 DV |
714 | * For LVDS just rely on its current settings for dual-channel. |
715 | * We haven't figured out how to reliably set up different | |
716 | * single/dual channel state, if we even can. | |
79e53945 | 717 | */ |
1974cad0 | 718 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
719 | clock.p2 = limit->p2.p2_fast; |
720 | else | |
721 | clock.p2 = limit->p2.p2_slow; | |
722 | } else { | |
723 | if (target < limit->p2.dot_limit) | |
724 | clock.p2 = limit->p2.p2_slow; | |
725 | else | |
726 | clock.p2 = limit->p2.p2_fast; | |
727 | } | |
728 | ||
0206e353 | 729 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 730 | |
42158660 ZY |
731 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
732 | clock.m1++) { | |
733 | for (clock.m2 = limit->m2.min; | |
734 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
735 | for (clock.n = limit->n.min; |
736 | clock.n <= limit->n.max; clock.n++) { | |
737 | for (clock.p1 = limit->p1.min; | |
738 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
739 | int this_err; |
740 | ||
ac58c3f0 | 741 | pineview_clock(refclk, &clock); |
1b894b59 CW |
742 | if (!intel_PLL_is_valid(dev, limit, |
743 | &clock)) | |
79e53945 | 744 | continue; |
cec2f356 SP |
745 | if (match_clock && |
746 | clock.p != match_clock->p) | |
747 | continue; | |
79e53945 JB |
748 | |
749 | this_err = abs(clock.dot - target); | |
750 | if (this_err < err) { | |
751 | *best_clock = clock; | |
752 | err = this_err; | |
753 | } | |
754 | } | |
755 | } | |
756 | } | |
757 | } | |
758 | ||
759 | return (err != target); | |
760 | } | |
761 | ||
d4906093 | 762 | static bool |
a93e255f ACO |
763 | g4x_find_best_dpll(const intel_limit_t *limit, |
764 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
765 | int target, int refclk, intel_clock_t *match_clock, |
766 | intel_clock_t *best_clock) | |
d4906093 | 767 | { |
a93e255f | 768 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 769 | struct drm_device *dev = crtc->base.dev; |
d4906093 ML |
770 | intel_clock_t clock; |
771 | int max_n; | |
772 | bool found; | |
6ba770dc AJ |
773 | /* approximately equals target * 0.00585 */ |
774 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
775 | found = false; |
776 | ||
a93e255f | 777 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 778 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
779 | clock.p2 = limit->p2.p2_fast; |
780 | else | |
781 | clock.p2 = limit->p2.p2_slow; | |
782 | } else { | |
783 | if (target < limit->p2.dot_limit) | |
784 | clock.p2 = limit->p2.p2_slow; | |
785 | else | |
786 | clock.p2 = limit->p2.p2_fast; | |
787 | } | |
788 | ||
789 | memset(best_clock, 0, sizeof(*best_clock)); | |
790 | max_n = limit->n.max; | |
f77f13e2 | 791 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 792 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 793 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
794 | for (clock.m1 = limit->m1.max; |
795 | clock.m1 >= limit->m1.min; clock.m1--) { | |
796 | for (clock.m2 = limit->m2.max; | |
797 | clock.m2 >= limit->m2.min; clock.m2--) { | |
798 | for (clock.p1 = limit->p1.max; | |
799 | clock.p1 >= limit->p1.min; clock.p1--) { | |
800 | int this_err; | |
801 | ||
ac58c3f0 | 802 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
803 | if (!intel_PLL_is_valid(dev, limit, |
804 | &clock)) | |
d4906093 | 805 | continue; |
1b894b59 CW |
806 | |
807 | this_err = abs(clock.dot - target); | |
d4906093 ML |
808 | if (this_err < err_most) { |
809 | *best_clock = clock; | |
810 | err_most = this_err; | |
811 | max_n = clock.n; | |
812 | found = true; | |
813 | } | |
814 | } | |
815 | } | |
816 | } | |
817 | } | |
2c07245f ZW |
818 | return found; |
819 | } | |
820 | ||
d5dd62bd ID |
821 | /* |
822 | * Check if the calculated PLL configuration is more optimal compared to the | |
823 | * best configuration and error found so far. Return the calculated error. | |
824 | */ | |
825 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
826 | const intel_clock_t *calculated_clock, | |
827 | const intel_clock_t *best_clock, | |
828 | unsigned int best_error_ppm, | |
829 | unsigned int *error_ppm) | |
830 | { | |
9ca3ba01 ID |
831 | /* |
832 | * For CHV ignore the error and consider only the P value. | |
833 | * Prefer a bigger P value based on HW requirements. | |
834 | */ | |
835 | if (IS_CHERRYVIEW(dev)) { | |
836 | *error_ppm = 0; | |
837 | ||
838 | return calculated_clock->p > best_clock->p; | |
839 | } | |
840 | ||
24be4e46 ID |
841 | if (WARN_ON_ONCE(!target_freq)) |
842 | return false; | |
843 | ||
d5dd62bd ID |
844 | *error_ppm = div_u64(1000000ULL * |
845 | abs(target_freq - calculated_clock->dot), | |
846 | target_freq); | |
847 | /* | |
848 | * Prefer a better P value over a better (smaller) error if the error | |
849 | * is small. Ensure this preference for future configurations too by | |
850 | * setting the error to 0. | |
851 | */ | |
852 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
853 | *error_ppm = 0; | |
854 | ||
855 | return true; | |
856 | } | |
857 | ||
858 | return *error_ppm + 10 < best_error_ppm; | |
859 | } | |
860 | ||
a0c4da24 | 861 | static bool |
a93e255f ACO |
862 | vlv_find_best_dpll(const intel_limit_t *limit, |
863 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
864 | int target, int refclk, intel_clock_t *match_clock, |
865 | intel_clock_t *best_clock) | |
a0c4da24 | 866 | { |
a93e255f | 867 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 868 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 869 | intel_clock_t clock; |
69e4f900 | 870 | unsigned int bestppm = 1000000; |
27e639bf VS |
871 | /* min update 19.2 MHz */ |
872 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 873 | bool found = false; |
a0c4da24 | 874 | |
6b4bf1c4 VS |
875 | target *= 5; /* fast clock */ |
876 | ||
877 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
878 | |
879 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 880 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 881 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 882 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 883 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 884 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 885 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 886 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 887 | unsigned int ppm; |
69e4f900 | 888 | |
6b4bf1c4 VS |
889 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
890 | refclk * clock.m1); | |
891 | ||
892 | vlv_clock(refclk, &clock); | |
43b0ac53 | 893 | |
f01b7962 VS |
894 | if (!intel_PLL_is_valid(dev, limit, |
895 | &clock)) | |
43b0ac53 VS |
896 | continue; |
897 | ||
d5dd62bd ID |
898 | if (!vlv_PLL_is_optimal(dev, target, |
899 | &clock, | |
900 | best_clock, | |
901 | bestppm, &ppm)) | |
902 | continue; | |
6b4bf1c4 | 903 | |
d5dd62bd ID |
904 | *best_clock = clock; |
905 | bestppm = ppm; | |
906 | found = true; | |
a0c4da24 JB |
907 | } |
908 | } | |
909 | } | |
910 | } | |
a0c4da24 | 911 | |
49e497ef | 912 | return found; |
a0c4da24 | 913 | } |
a4fc5ed6 | 914 | |
ef9348c8 | 915 | static bool |
a93e255f ACO |
916 | chv_find_best_dpll(const intel_limit_t *limit, |
917 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
918 | int target, int refclk, intel_clock_t *match_clock, |
919 | intel_clock_t *best_clock) | |
920 | { | |
a93e255f | 921 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 922 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 923 | unsigned int best_error_ppm; |
ef9348c8 CML |
924 | intel_clock_t clock; |
925 | uint64_t m2; | |
926 | int found = false; | |
927 | ||
928 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 929 | best_error_ppm = 1000000; |
ef9348c8 CML |
930 | |
931 | /* | |
932 | * Based on hardware doc, the n always set to 1, and m1 always | |
933 | * set to 2. If requires to support 200Mhz refclk, we need to | |
934 | * revisit this because n may not 1 anymore. | |
935 | */ | |
936 | clock.n = 1, clock.m1 = 2; | |
937 | target *= 5; /* fast clock */ | |
938 | ||
939 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
940 | for (clock.p2 = limit->p2.p2_fast; | |
941 | clock.p2 >= limit->p2.p2_slow; | |
942 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 943 | unsigned int error_ppm; |
ef9348c8 CML |
944 | |
945 | clock.p = clock.p1 * clock.p2; | |
946 | ||
947 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
948 | clock.n) << 22, refclk * clock.m1); | |
949 | ||
950 | if (m2 > INT_MAX/clock.m1) | |
951 | continue; | |
952 | ||
953 | clock.m2 = m2; | |
954 | ||
955 | chv_clock(refclk, &clock); | |
956 | ||
957 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
958 | continue; | |
959 | ||
9ca3ba01 ID |
960 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
961 | best_error_ppm, &error_ppm)) | |
962 | continue; | |
963 | ||
964 | *best_clock = clock; | |
965 | best_error_ppm = error_ppm; | |
966 | found = true; | |
ef9348c8 CML |
967 | } |
968 | } | |
969 | ||
970 | return found; | |
971 | } | |
972 | ||
5ab7b0b7 ID |
973 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
974 | intel_clock_t *best_clock) | |
975 | { | |
976 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
977 | ||
978 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
979 | target_clock, refclk, NULL, best_clock); | |
980 | } | |
981 | ||
20ddf665 VS |
982 | bool intel_crtc_active(struct drm_crtc *crtc) |
983 | { | |
984 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
985 | ||
986 | /* Be paranoid as we can arrive here with only partial | |
987 | * state retrieved from the hardware during setup. | |
988 | * | |
241bfc38 | 989 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
990 | * as Haswell has gained clock readout/fastboot support. |
991 | * | |
66e514c1 | 992 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 993 | * properly reconstruct framebuffers. |
c3d1f436 MR |
994 | * |
995 | * FIXME: The intel_crtc->active here should be switched to | |
996 | * crtc->state->active once we have proper CRTC states wired up | |
997 | * for atomic. | |
20ddf665 | 998 | */ |
c3d1f436 | 999 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1000 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1001 | } |
1002 | ||
a5c961d1 PZ |
1003 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1004 | enum pipe pipe) | |
1005 | { | |
1006 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1007 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1008 | ||
6e3c9717 | 1009 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1010 | } |
1011 | ||
fbf49ea2 VS |
1012 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1013 | { | |
1014 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1015 | u32 reg = PIPEDSL(pipe); | |
1016 | u32 line1, line2; | |
1017 | u32 line_mask; | |
1018 | ||
1019 | if (IS_GEN2(dev)) | |
1020 | line_mask = DSL_LINEMASK_GEN2; | |
1021 | else | |
1022 | line_mask = DSL_LINEMASK_GEN3; | |
1023 | ||
1024 | line1 = I915_READ(reg) & line_mask; | |
1025 | mdelay(5); | |
1026 | line2 = I915_READ(reg) & line_mask; | |
1027 | ||
1028 | return line1 == line2; | |
1029 | } | |
1030 | ||
ab7ad7f6 KP |
1031 | /* |
1032 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1033 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1034 | * |
1035 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1036 | * spinning on the vblank interrupt status bit, since we won't actually | |
1037 | * see an interrupt when the pipe is disabled. | |
1038 | * | |
ab7ad7f6 KP |
1039 | * On Gen4 and above: |
1040 | * wait for the pipe register state bit to turn off | |
1041 | * | |
1042 | * Otherwise: | |
1043 | * wait for the display line value to settle (it usually | |
1044 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1045 | * |
9d0498a2 | 1046 | */ |
575f7ab7 | 1047 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1048 | { |
575f7ab7 | 1049 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1050 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1051 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1052 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1053 | |
1054 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 1055 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1056 | |
1057 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1058 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1059 | 100)) | |
284637d9 | 1060 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1061 | } else { |
ab7ad7f6 | 1062 | /* Wait for the display line to settle */ |
fbf49ea2 | 1063 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1064 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1065 | } |
79e53945 JB |
1066 | } |
1067 | ||
b0ea7d37 DL |
1068 | /* |
1069 | * ibx_digital_port_connected - is the specified port connected? | |
1070 | * @dev_priv: i915 private structure | |
1071 | * @port: the port to test | |
1072 | * | |
1073 | * Returns true if @port is connected, false otherwise. | |
1074 | */ | |
1075 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1076 | struct intel_digital_port *port) | |
1077 | { | |
1078 | u32 bit; | |
1079 | ||
c36346e3 | 1080 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1081 | switch (port->port) { |
c36346e3 DL |
1082 | case PORT_B: |
1083 | bit = SDE_PORTB_HOTPLUG; | |
1084 | break; | |
1085 | case PORT_C: | |
1086 | bit = SDE_PORTC_HOTPLUG; | |
1087 | break; | |
1088 | case PORT_D: | |
1089 | bit = SDE_PORTD_HOTPLUG; | |
1090 | break; | |
1091 | default: | |
1092 | return true; | |
1093 | } | |
1094 | } else { | |
eba905b2 | 1095 | switch (port->port) { |
c36346e3 DL |
1096 | case PORT_B: |
1097 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1098 | break; | |
1099 | case PORT_C: | |
1100 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1101 | break; | |
1102 | case PORT_D: | |
1103 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1104 | break; | |
1105 | default: | |
1106 | return true; | |
1107 | } | |
b0ea7d37 DL |
1108 | } |
1109 | ||
1110 | return I915_READ(SDEISR) & bit; | |
1111 | } | |
1112 | ||
b24e7179 JB |
1113 | static const char *state_string(bool enabled) |
1114 | { | |
1115 | return enabled ? "on" : "off"; | |
1116 | } | |
1117 | ||
1118 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1119 | void assert_pll(struct drm_i915_private *dev_priv, |
1120 | enum pipe pipe, bool state) | |
b24e7179 JB |
1121 | { |
1122 | int reg; | |
1123 | u32 val; | |
1124 | bool cur_state; | |
1125 | ||
1126 | reg = DPLL(pipe); | |
1127 | val = I915_READ(reg); | |
1128 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
e2c719b7 | 1129 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1130 | "PLL state assertion failure (expected %s, current %s)\n", |
1131 | state_string(state), state_string(cur_state)); | |
1132 | } | |
b24e7179 | 1133 | |
23538ef1 JN |
1134 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1135 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1136 | { | |
1137 | u32 val; | |
1138 | bool cur_state; | |
1139 | ||
1140 | mutex_lock(&dev_priv->dpio_lock); | |
1141 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1142 | mutex_unlock(&dev_priv->dpio_lock); | |
1143 | ||
1144 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1145 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1146 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1147 | state_string(state), state_string(cur_state)); | |
1148 | } | |
1149 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1150 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1151 | ||
55607e8a | 1152 | struct intel_shared_dpll * |
e2b78267 DV |
1153 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1154 | { | |
1155 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1156 | ||
6e3c9717 | 1157 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1158 | return NULL; |
1159 | ||
6e3c9717 | 1160 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1161 | } |
1162 | ||
040484af | 1163 | /* For ILK+ */ |
55607e8a DV |
1164 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1165 | struct intel_shared_dpll *pll, | |
1166 | bool state) | |
040484af | 1167 | { |
040484af | 1168 | bool cur_state; |
5358901f | 1169 | struct intel_dpll_hw_state hw_state; |
040484af | 1170 | |
92b27b08 | 1171 | if (WARN (!pll, |
46edb027 | 1172 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1173 | return; |
ee7b9f93 | 1174 | |
5358901f | 1175 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1176 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1177 | "%s assertion failure (expected %s, current %s)\n", |
1178 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1179 | } |
040484af JB |
1180 | |
1181 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1182 | enum pipe pipe, bool state) | |
1183 | { | |
1184 | int reg; | |
1185 | u32 val; | |
1186 | bool cur_state; | |
ad80a810 PZ |
1187 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1188 | pipe); | |
040484af | 1189 | |
affa9354 PZ |
1190 | if (HAS_DDI(dev_priv->dev)) { |
1191 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1192 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1193 | val = I915_READ(reg); |
ad80a810 | 1194 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1195 | } else { |
1196 | reg = FDI_TX_CTL(pipe); | |
1197 | val = I915_READ(reg); | |
1198 | cur_state = !!(val & FDI_TX_ENABLE); | |
1199 | } | |
e2c719b7 | 1200 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1201 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1202 | state_string(state), state_string(cur_state)); | |
1203 | } | |
1204 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1205 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1206 | ||
1207 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1208 | enum pipe pipe, bool state) | |
1209 | { | |
1210 | int reg; | |
1211 | u32 val; | |
1212 | bool cur_state; | |
1213 | ||
d63fa0dc PZ |
1214 | reg = FDI_RX_CTL(pipe); |
1215 | val = I915_READ(reg); | |
1216 | cur_state = !!(val & FDI_RX_ENABLE); | |
e2c719b7 | 1217 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1218 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1219 | state_string(state), state_string(cur_state)); | |
1220 | } | |
1221 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1222 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1223 | ||
1224 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1225 | enum pipe pipe) | |
1226 | { | |
1227 | int reg; | |
1228 | u32 val; | |
1229 | ||
1230 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1231 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1232 | return; |
1233 | ||
bf507ef7 | 1234 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1235 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1236 | return; |
1237 | ||
040484af JB |
1238 | reg = FDI_TX_CTL(pipe); |
1239 | val = I915_READ(reg); | |
e2c719b7 | 1240 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1241 | } |
1242 | ||
55607e8a DV |
1243 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1244 | enum pipe pipe, bool state) | |
040484af JB |
1245 | { |
1246 | int reg; | |
1247 | u32 val; | |
55607e8a | 1248 | bool cur_state; |
040484af JB |
1249 | |
1250 | reg = FDI_RX_CTL(pipe); | |
1251 | val = I915_READ(reg); | |
55607e8a | 1252 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1253 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1254 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1255 | state_string(state), state_string(cur_state)); | |
040484af JB |
1256 | } |
1257 | ||
b680c37a DV |
1258 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1259 | enum pipe pipe) | |
ea0760cf | 1260 | { |
bedd4dba JN |
1261 | struct drm_device *dev = dev_priv->dev; |
1262 | int pp_reg; | |
ea0760cf JB |
1263 | u32 val; |
1264 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1265 | bool locked = true; |
ea0760cf | 1266 | |
bedd4dba JN |
1267 | if (WARN_ON(HAS_DDI(dev))) |
1268 | return; | |
1269 | ||
1270 | if (HAS_PCH_SPLIT(dev)) { | |
1271 | u32 port_sel; | |
1272 | ||
ea0760cf | 1273 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1274 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1275 | ||
1276 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1277 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1278 | panel_pipe = PIPE_B; | |
1279 | /* XXX: else fix for eDP */ | |
1280 | } else if (IS_VALLEYVIEW(dev)) { | |
1281 | /* presumably write lock depends on pipe, not port select */ | |
1282 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1283 | panel_pipe = pipe; | |
ea0760cf JB |
1284 | } else { |
1285 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1286 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1287 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1288 | } |
1289 | ||
1290 | val = I915_READ(pp_reg); | |
1291 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1292 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1293 | locked = false; |
1294 | ||
e2c719b7 | 1295 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1296 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1297 | pipe_name(pipe)); |
ea0760cf JB |
1298 | } |
1299 | ||
93ce0ba6 JN |
1300 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1301 | enum pipe pipe, bool state) | |
1302 | { | |
1303 | struct drm_device *dev = dev_priv->dev; | |
1304 | bool cur_state; | |
1305 | ||
d9d82081 | 1306 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1307 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1308 | else |
5efb3e28 | 1309 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1310 | |
e2c719b7 | 1311 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1312 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1313 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1314 | } | |
1315 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1316 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1317 | ||
b840d907 JB |
1318 | void assert_pipe(struct drm_i915_private *dev_priv, |
1319 | enum pipe pipe, bool state) | |
b24e7179 JB |
1320 | { |
1321 | int reg; | |
1322 | u32 val; | |
63d7bbe9 | 1323 | bool cur_state; |
702e7a56 PZ |
1324 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1325 | pipe); | |
b24e7179 | 1326 | |
b6b5d049 VS |
1327 | /* if we need the pipe quirk it must be always on */ |
1328 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1329 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1330 | state = true; |
1331 | ||
f458ebbc | 1332 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1333 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1334 | cur_state = false; |
1335 | } else { | |
1336 | reg = PIPECONF(cpu_transcoder); | |
1337 | val = I915_READ(reg); | |
1338 | cur_state = !!(val & PIPECONF_ENABLE); | |
1339 | } | |
1340 | ||
e2c719b7 | 1341 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1342 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1343 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1344 | } |
1345 | ||
931872fc CW |
1346 | static void assert_plane(struct drm_i915_private *dev_priv, |
1347 | enum plane plane, bool state) | |
b24e7179 JB |
1348 | { |
1349 | int reg; | |
1350 | u32 val; | |
931872fc | 1351 | bool cur_state; |
b24e7179 JB |
1352 | |
1353 | reg = DSPCNTR(plane); | |
1354 | val = I915_READ(reg); | |
931872fc | 1355 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1356 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1357 | "plane %c assertion failure (expected %s, current %s)\n", |
1358 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1359 | } |
1360 | ||
931872fc CW |
1361 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1362 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1363 | ||
b24e7179 JB |
1364 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1365 | enum pipe pipe) | |
1366 | { | |
653e1026 | 1367 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1368 | int reg, i; |
1369 | u32 val; | |
1370 | int cur_pipe; | |
1371 | ||
653e1026 VS |
1372 | /* Primary planes are fixed to pipes on gen4+ */ |
1373 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1374 | reg = DSPCNTR(pipe); |
1375 | val = I915_READ(reg); | |
e2c719b7 | 1376 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1377 | "plane %c assertion failure, should be disabled but not\n", |
1378 | plane_name(pipe)); | |
19ec1358 | 1379 | return; |
28c05794 | 1380 | } |
19ec1358 | 1381 | |
b24e7179 | 1382 | /* Need to check both planes against the pipe */ |
055e393f | 1383 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1384 | reg = DSPCNTR(i); |
1385 | val = I915_READ(reg); | |
1386 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1387 | DISPPLANE_SEL_PIPE_SHIFT; | |
e2c719b7 | 1388 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1389 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1390 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1391 | } |
1392 | } | |
1393 | ||
19332d7a JB |
1394 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1395 | enum pipe pipe) | |
1396 | { | |
20674eef | 1397 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1398 | int reg, sprite; |
19332d7a JB |
1399 | u32 val; |
1400 | ||
7feb8b88 | 1401 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1402 | for_each_sprite(dev_priv, pipe, sprite) { |
7feb8b88 | 1403 | val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1404 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1405 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1406 | sprite, pipe_name(pipe)); | |
1407 | } | |
1408 | } else if (IS_VALLEYVIEW(dev)) { | |
3bdcfc0c | 1409 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 1410 | reg = SPCNTR(pipe, sprite); |
20674eef | 1411 | val = I915_READ(reg); |
e2c719b7 | 1412 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1413 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1414 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1415 | } |
1416 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1417 | reg = SPRCTL(pipe); | |
19332d7a | 1418 | val = I915_READ(reg); |
e2c719b7 | 1419 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1420 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1421 | plane_name(pipe), pipe_name(pipe)); |
1422 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1423 | reg = DVSCNTR(pipe); | |
19332d7a | 1424 | val = I915_READ(reg); |
e2c719b7 | 1425 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1426 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1427 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1428 | } |
1429 | } | |
1430 | ||
08c71e5e VS |
1431 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1432 | { | |
e2c719b7 | 1433 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1434 | drm_crtc_vblank_put(crtc); |
1435 | } | |
1436 | ||
89eff4be | 1437 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1438 | { |
1439 | u32 val; | |
1440 | bool enabled; | |
1441 | ||
e2c719b7 | 1442 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1443 | |
92f2584a JB |
1444 | val = I915_READ(PCH_DREF_CONTROL); |
1445 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1446 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1447 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1448 | } |
1449 | ||
ab9412ba DV |
1450 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1451 | enum pipe pipe) | |
92f2584a JB |
1452 | { |
1453 | int reg; | |
1454 | u32 val; | |
1455 | bool enabled; | |
1456 | ||
ab9412ba | 1457 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1458 | val = I915_READ(reg); |
1459 | enabled = !!(val & TRANS_ENABLE); | |
e2c719b7 | 1460 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1461 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1462 | pipe_name(pipe)); | |
92f2584a JB |
1463 | } |
1464 | ||
4e634389 KP |
1465 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1466 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1467 | { |
1468 | if ((val & DP_PORT_EN) == 0) | |
1469 | return false; | |
1470 | ||
1471 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1472 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1473 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1474 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1475 | return false; | |
44f37d1f CML |
1476 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1477 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1478 | return false; | |
f0575e92 KP |
1479 | } else { |
1480 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1481 | return false; | |
1482 | } | |
1483 | return true; | |
1484 | } | |
1485 | ||
1519b995 KP |
1486 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1487 | enum pipe pipe, u32 val) | |
1488 | { | |
dc0fa718 | 1489 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1490 | return false; |
1491 | ||
1492 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1493 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1494 | return false; |
44f37d1f CML |
1495 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1496 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1497 | return false; | |
1519b995 | 1498 | } else { |
dc0fa718 | 1499 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1500 | return false; |
1501 | } | |
1502 | return true; | |
1503 | } | |
1504 | ||
1505 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1506 | enum pipe pipe, u32 val) | |
1507 | { | |
1508 | if ((val & LVDS_PORT_EN) == 0) | |
1509 | return false; | |
1510 | ||
1511 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1512 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1513 | return false; | |
1514 | } else { | |
1515 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1516 | return false; | |
1517 | } | |
1518 | return true; | |
1519 | } | |
1520 | ||
1521 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1522 | enum pipe pipe, u32 val) | |
1523 | { | |
1524 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1525 | return false; | |
1526 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1527 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1528 | return false; | |
1529 | } else { | |
1530 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1531 | return false; | |
1532 | } | |
1533 | return true; | |
1534 | } | |
1535 | ||
291906f1 | 1536 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1537 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1538 | { |
47a05eca | 1539 | u32 val = I915_READ(reg); |
e2c719b7 | 1540 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1541 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1542 | reg, pipe_name(pipe)); |
de9a35ab | 1543 | |
e2c719b7 | 1544 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1545 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1546 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1547 | } |
1548 | ||
1549 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1550 | enum pipe pipe, int reg) | |
1551 | { | |
47a05eca | 1552 | u32 val = I915_READ(reg); |
e2c719b7 | 1553 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1554 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1555 | reg, pipe_name(pipe)); |
de9a35ab | 1556 | |
e2c719b7 | 1557 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1558 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1559 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1560 | } |
1561 | ||
1562 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1563 | enum pipe pipe) | |
1564 | { | |
1565 | int reg; | |
1566 | u32 val; | |
291906f1 | 1567 | |
f0575e92 KP |
1568 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1569 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1570 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1571 | |
1572 | reg = PCH_ADPA; | |
1573 | val = I915_READ(reg); | |
e2c719b7 | 1574 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1575 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1576 | pipe_name(pipe)); |
291906f1 JB |
1577 | |
1578 | reg = PCH_LVDS; | |
1579 | val = I915_READ(reg); | |
e2c719b7 | 1580 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1581 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1582 | pipe_name(pipe)); |
291906f1 | 1583 | |
e2debe91 PZ |
1584 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1585 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1586 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1587 | } |
1588 | ||
40e9cf64 JB |
1589 | static void intel_init_dpio(struct drm_device *dev) |
1590 | { | |
1591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1592 | ||
1593 | if (!IS_VALLEYVIEW(dev)) | |
1594 | return; | |
1595 | ||
a09caddd CML |
1596 | /* |
1597 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1598 | * CHV x1 PHY (DP/HDMI D) | |
1599 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1600 | */ | |
1601 | if (IS_CHERRYVIEW(dev)) { | |
1602 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1603 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1604 | } else { | |
1605 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1606 | } | |
5382f5f3 JB |
1607 | } |
1608 | ||
d288f65f | 1609 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1610 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1611 | { |
426115cf DV |
1612 | struct drm_device *dev = crtc->base.dev; |
1613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1614 | int reg = DPLL(crtc->pipe); | |
d288f65f | 1615 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1616 | |
426115cf | 1617 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1618 | |
1619 | /* No really, not for ILK+ */ | |
1620 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1621 | ||
1622 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1623 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1624 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1625 | |
426115cf DV |
1626 | I915_WRITE(reg, dpll); |
1627 | POSTING_READ(reg); | |
1628 | udelay(150); | |
1629 | ||
1630 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1631 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1632 | ||
d288f65f | 1633 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1634 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1635 | |
1636 | /* We do this three times for luck */ | |
426115cf | 1637 | I915_WRITE(reg, dpll); |
87442f73 DV |
1638 | POSTING_READ(reg); |
1639 | udelay(150); /* wait for warmup */ | |
426115cf | 1640 | I915_WRITE(reg, dpll); |
87442f73 DV |
1641 | POSTING_READ(reg); |
1642 | udelay(150); /* wait for warmup */ | |
426115cf | 1643 | I915_WRITE(reg, dpll); |
87442f73 DV |
1644 | POSTING_READ(reg); |
1645 | udelay(150); /* wait for warmup */ | |
1646 | } | |
1647 | ||
d288f65f | 1648 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1649 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1650 | { |
1651 | struct drm_device *dev = crtc->base.dev; | |
1652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1653 | int pipe = crtc->pipe; | |
1654 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1655 | u32 tmp; |
1656 | ||
1657 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1658 | ||
1659 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1660 | ||
1661 | mutex_lock(&dev_priv->dpio_lock); | |
1662 | ||
1663 | /* Enable back the 10bit clock to display controller */ | |
1664 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1665 | tmp |= DPIO_DCLKP_EN; | |
1666 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1667 | ||
1668 | /* | |
1669 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1670 | */ | |
1671 | udelay(1); | |
1672 | ||
1673 | /* Enable PLL */ | |
d288f65f | 1674 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1675 | |
1676 | /* Check PLL is locked */ | |
a11b0703 | 1677 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1678 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1679 | ||
a11b0703 | 1680 | /* not sure when this should be written */ |
d288f65f | 1681 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 VS |
1682 | POSTING_READ(DPLL_MD(pipe)); |
1683 | ||
9d556c99 CML |
1684 | mutex_unlock(&dev_priv->dpio_lock); |
1685 | } | |
1686 | ||
1c4e0274 VS |
1687 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1688 | { | |
1689 | struct intel_crtc *crtc; | |
1690 | int count = 0; | |
1691 | ||
1692 | for_each_intel_crtc(dev, crtc) | |
1693 | count += crtc->active && | |
409ee761 | 1694 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1695 | |
1696 | return count; | |
1697 | } | |
1698 | ||
66e3d5c0 | 1699 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1700 | { |
66e3d5c0 DV |
1701 | struct drm_device *dev = crtc->base.dev; |
1702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1703 | int reg = DPLL(crtc->pipe); | |
6e3c9717 | 1704 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1705 | |
66e3d5c0 | 1706 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1707 | |
63d7bbe9 | 1708 | /* No really, not for ILK+ */ |
3d13ef2e | 1709 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1710 | |
1711 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1712 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1713 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1714 | |
1c4e0274 VS |
1715 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1716 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1717 | /* | |
1718 | * It appears to be important that we don't enable this | |
1719 | * for the current pipe before otherwise configuring the | |
1720 | * PLL. No idea how this should be handled if multiple | |
1721 | * DVO outputs are enabled simultaneosly. | |
1722 | */ | |
1723 | dpll |= DPLL_DVO_2X_MODE; | |
1724 | I915_WRITE(DPLL(!crtc->pipe), | |
1725 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1726 | } | |
66e3d5c0 DV |
1727 | |
1728 | /* Wait for the clocks to stabilize. */ | |
1729 | POSTING_READ(reg); | |
1730 | udelay(150); | |
1731 | ||
1732 | if (INTEL_INFO(dev)->gen >= 4) { | |
1733 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1734 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1735 | } else { |
1736 | /* The pixel multiplier can only be updated once the | |
1737 | * DPLL is enabled and the clocks are stable. | |
1738 | * | |
1739 | * So write it again. | |
1740 | */ | |
1741 | I915_WRITE(reg, dpll); | |
1742 | } | |
63d7bbe9 JB |
1743 | |
1744 | /* We do this three times for luck */ | |
66e3d5c0 | 1745 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1746 | POSTING_READ(reg); |
1747 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1748 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1749 | POSTING_READ(reg); |
1750 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1751 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1752 | POSTING_READ(reg); |
1753 | udelay(150); /* wait for warmup */ | |
1754 | } | |
1755 | ||
1756 | /** | |
50b44a44 | 1757 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1758 | * @dev_priv: i915 private structure |
1759 | * @pipe: pipe PLL to disable | |
1760 | * | |
1761 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1762 | * | |
1763 | * Note! This is for pre-ILK only. | |
1764 | */ | |
1c4e0274 | 1765 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1766 | { |
1c4e0274 VS |
1767 | struct drm_device *dev = crtc->base.dev; |
1768 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1769 | enum pipe pipe = crtc->pipe; | |
1770 | ||
1771 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1772 | if (IS_I830(dev) && | |
409ee761 | 1773 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
1c4e0274 VS |
1774 | intel_num_dvo_pipes(dev) == 1) { |
1775 | I915_WRITE(DPLL(PIPE_B), | |
1776 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1777 | I915_WRITE(DPLL(PIPE_A), | |
1778 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1779 | } | |
1780 | ||
b6b5d049 VS |
1781 | /* Don't disable pipe or pipe PLLs if needed */ |
1782 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1783 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1784 | return; |
1785 | ||
1786 | /* Make sure the pipe isn't still relying on us */ | |
1787 | assert_pipe_disabled(dev_priv, pipe); | |
1788 | ||
50b44a44 DV |
1789 | I915_WRITE(DPLL(pipe), 0); |
1790 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1791 | } |
1792 | ||
f6071166 JB |
1793 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1794 | { | |
1795 | u32 val = 0; | |
1796 | ||
1797 | /* Make sure the pipe isn't still relying on us */ | |
1798 | assert_pipe_disabled(dev_priv, pipe); | |
1799 | ||
e5cbfbfb ID |
1800 | /* |
1801 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1802 | * The latter is needed for VGA hotplug / manual detection. | |
1803 | */ | |
f6071166 | 1804 | if (pipe == PIPE_B) |
e5cbfbfb | 1805 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1806 | I915_WRITE(DPLL(pipe), val); |
1807 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1808 | |
1809 | } | |
1810 | ||
1811 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1812 | { | |
d752048d | 1813 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1814 | u32 val; |
1815 | ||
a11b0703 VS |
1816 | /* Make sure the pipe isn't still relying on us */ |
1817 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1818 | |
a11b0703 | 1819 | /* Set PLL en = 0 */ |
d17ec4ce | 1820 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1821 | if (pipe != PIPE_A) |
1822 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1823 | I915_WRITE(DPLL(pipe), val); | |
1824 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1825 | |
1826 | mutex_lock(&dev_priv->dpio_lock); | |
1827 | ||
1828 | /* Disable 10bit clock to display controller */ | |
1829 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1830 | val &= ~DPIO_DCLKP_EN; | |
1831 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1832 | ||
61407f6d VS |
1833 | /* disable left/right clock distribution */ |
1834 | if (pipe != PIPE_B) { | |
1835 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1836 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1837 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1838 | } else { | |
1839 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1840 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1841 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1842 | } | |
1843 | ||
d752048d | 1844 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1845 | } |
1846 | ||
e4607fcf CML |
1847 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1848 | struct intel_digital_port *dport) | |
89b667f8 JB |
1849 | { |
1850 | u32 port_mask; | |
00fc31b7 | 1851 | int dpll_reg; |
89b667f8 | 1852 | |
e4607fcf CML |
1853 | switch (dport->port) { |
1854 | case PORT_B: | |
89b667f8 | 1855 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1856 | dpll_reg = DPLL(0); |
e4607fcf CML |
1857 | break; |
1858 | case PORT_C: | |
89b667f8 | 1859 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1860 | dpll_reg = DPLL(0); |
1861 | break; | |
1862 | case PORT_D: | |
1863 | port_mask = DPLL_PORTD_READY_MASK; | |
1864 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1865 | break; |
1866 | default: | |
1867 | BUG(); | |
1868 | } | |
89b667f8 | 1869 | |
00fc31b7 | 1870 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1871 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1872 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1873 | } |
1874 | ||
b14b1055 DV |
1875 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1876 | { | |
1877 | struct drm_device *dev = crtc->base.dev; | |
1878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1879 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1880 | ||
be19f0ff CW |
1881 | if (WARN_ON(pll == NULL)) |
1882 | return; | |
1883 | ||
3e369b76 | 1884 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1885 | if (pll->active == 0) { |
1886 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1887 | WARN_ON(pll->on); | |
1888 | assert_shared_dpll_disabled(dev_priv, pll); | |
1889 | ||
1890 | pll->mode_set(dev_priv, pll); | |
1891 | } | |
1892 | } | |
1893 | ||
92f2584a | 1894 | /** |
85b3894f | 1895 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1896 | * @dev_priv: i915 private structure |
1897 | * @pipe: pipe PLL to enable | |
1898 | * | |
1899 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1900 | * drives the transcoder clock. | |
1901 | */ | |
85b3894f | 1902 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1903 | { |
3d13ef2e DL |
1904 | struct drm_device *dev = crtc->base.dev; |
1905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1906 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1907 | |
87a875bb | 1908 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1909 | return; |
1910 | ||
3e369b76 | 1911 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1912 | return; |
ee7b9f93 | 1913 | |
74dd6928 | 1914 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1915 | pll->name, pll->active, pll->on, |
e2b78267 | 1916 | crtc->base.base.id); |
92f2584a | 1917 | |
cdbd2316 DV |
1918 | if (pll->active++) { |
1919 | WARN_ON(!pll->on); | |
e9d6944e | 1920 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1921 | return; |
1922 | } | |
f4a091c7 | 1923 | WARN_ON(pll->on); |
ee7b9f93 | 1924 | |
bd2bb1b9 PZ |
1925 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1926 | ||
46edb027 | 1927 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1928 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1929 | pll->on = true; |
92f2584a JB |
1930 | } |
1931 | ||
f6daaec2 | 1932 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1933 | { |
3d13ef2e DL |
1934 | struct drm_device *dev = crtc->base.dev; |
1935 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1936 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1937 | |
92f2584a | 1938 | /* PCH only available on ILK+ */ |
3d13ef2e | 1939 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1940 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1941 | return; |
92f2584a | 1942 | |
3e369b76 | 1943 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1944 | return; |
7a419866 | 1945 | |
46edb027 DV |
1946 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1947 | pll->name, pll->active, pll->on, | |
e2b78267 | 1948 | crtc->base.base.id); |
7a419866 | 1949 | |
48da64a8 | 1950 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1951 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1952 | return; |
1953 | } | |
1954 | ||
e9d6944e | 1955 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1956 | WARN_ON(!pll->on); |
cdbd2316 | 1957 | if (--pll->active) |
7a419866 | 1958 | return; |
ee7b9f93 | 1959 | |
46edb027 | 1960 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1961 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1962 | pll->on = false; |
bd2bb1b9 PZ |
1963 | |
1964 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1965 | } |
1966 | ||
b8a4f404 PZ |
1967 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1968 | enum pipe pipe) | |
040484af | 1969 | { |
23670b32 | 1970 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1971 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1972 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1973 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1974 | |
1975 | /* PCH only available on ILK+ */ | |
55522f37 | 1976 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1977 | |
1978 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1979 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1980 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1981 | |
1982 | /* FDI must be feeding us bits for PCH ports */ | |
1983 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1984 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1985 | ||
23670b32 DV |
1986 | if (HAS_PCH_CPT(dev)) { |
1987 | /* Workaround: Set the timing override bit before enabling the | |
1988 | * pch transcoder. */ | |
1989 | reg = TRANS_CHICKEN2(pipe); | |
1990 | val = I915_READ(reg); | |
1991 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1992 | I915_WRITE(reg, val); | |
59c859d6 | 1993 | } |
23670b32 | 1994 | |
ab9412ba | 1995 | reg = PCH_TRANSCONF(pipe); |
040484af | 1996 | val = I915_READ(reg); |
5f7f726d | 1997 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1998 | |
1999 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
2000 | /* | |
2001 | * make the BPC in transcoder be consistent with | |
2002 | * that in pipeconf reg. | |
2003 | */ | |
dfd07d72 DV |
2004 | val &= ~PIPECONF_BPC_MASK; |
2005 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2006 | } |
5f7f726d PZ |
2007 | |
2008 | val &= ~TRANS_INTERLACE_MASK; | |
2009 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2010 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2011 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2012 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2013 | else | |
2014 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2015 | else |
2016 | val |= TRANS_PROGRESSIVE; | |
2017 | ||
040484af JB |
2018 | I915_WRITE(reg, val | TRANS_ENABLE); |
2019 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2020 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2021 | } |
2022 | ||
8fb033d7 | 2023 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2024 | enum transcoder cpu_transcoder) |
040484af | 2025 | { |
8fb033d7 | 2026 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2027 | |
2028 | /* PCH only available on ILK+ */ | |
55522f37 | 2029 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2030 | |
8fb033d7 | 2031 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2032 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2033 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2034 | |
223a6fdf PZ |
2035 | /* Workaround: set timing override bit. */ |
2036 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2037 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
2038 | I915_WRITE(_TRANSA_CHICKEN2, val); |
2039 | ||
25f3ef11 | 2040 | val = TRANS_ENABLE; |
937bb610 | 2041 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2042 | |
9a76b1c6 PZ |
2043 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2044 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2045 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2046 | else |
2047 | val |= TRANS_PROGRESSIVE; | |
2048 | ||
ab9412ba DV |
2049 | I915_WRITE(LPT_TRANSCONF, val); |
2050 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2051 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2052 | } |
2053 | ||
b8a4f404 PZ |
2054 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2055 | enum pipe pipe) | |
040484af | 2056 | { |
23670b32 DV |
2057 | struct drm_device *dev = dev_priv->dev; |
2058 | uint32_t reg, val; | |
040484af JB |
2059 | |
2060 | /* FDI relies on the transcoder */ | |
2061 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2062 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2063 | ||
291906f1 JB |
2064 | /* Ports must be off as well */ |
2065 | assert_pch_ports_disabled(dev_priv, pipe); | |
2066 | ||
ab9412ba | 2067 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2068 | val = I915_READ(reg); |
2069 | val &= ~TRANS_ENABLE; | |
2070 | I915_WRITE(reg, val); | |
2071 | /* wait for PCH transcoder off, transcoder state */ | |
2072 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2073 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2074 | |
2075 | if (!HAS_PCH_IBX(dev)) { | |
2076 | /* Workaround: Clear the timing override chicken bit again. */ | |
2077 | reg = TRANS_CHICKEN2(pipe); | |
2078 | val = I915_READ(reg); | |
2079 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2080 | I915_WRITE(reg, val); | |
2081 | } | |
040484af JB |
2082 | } |
2083 | ||
ab4d966c | 2084 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2085 | { |
8fb033d7 PZ |
2086 | u32 val; |
2087 | ||
ab9412ba | 2088 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2089 | val &= ~TRANS_ENABLE; |
ab9412ba | 2090 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2091 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2092 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2093 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2094 | |
2095 | /* Workaround: clear timing override bit. */ | |
2096 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2097 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2098 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2099 | } |
2100 | ||
b24e7179 | 2101 | /** |
309cfea8 | 2102 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2103 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2104 | * |
0372264a | 2105 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2106 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2107 | */ |
e1fdc473 | 2108 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2109 | { |
0372264a PZ |
2110 | struct drm_device *dev = crtc->base.dev; |
2111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2112 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2113 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2114 | pipe); | |
1a240d4d | 2115 | enum pipe pch_transcoder; |
b24e7179 JB |
2116 | int reg; |
2117 | u32 val; | |
2118 | ||
58c6eaa2 | 2119 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2120 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2121 | assert_sprites_disabled(dev_priv, pipe); |
2122 | ||
681e5811 | 2123 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2124 | pch_transcoder = TRANSCODER_A; |
2125 | else | |
2126 | pch_transcoder = pipe; | |
2127 | ||
b24e7179 JB |
2128 | /* |
2129 | * A pipe without a PLL won't actually be able to drive bits from | |
2130 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2131 | * need the check. | |
2132 | */ | |
50360403 | 2133 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
409ee761 | 2134 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2135 | assert_dsi_pll_enabled(dev_priv); |
2136 | else | |
2137 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2138 | else { |
6e3c9717 | 2139 | if (crtc->config->has_pch_encoder) { |
040484af | 2140 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2141 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2142 | assert_fdi_tx_pll_enabled(dev_priv, |
2143 | (enum pipe) cpu_transcoder); | |
040484af JB |
2144 | } |
2145 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2146 | } | |
b24e7179 | 2147 | |
702e7a56 | 2148 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2149 | val = I915_READ(reg); |
7ad25d48 | 2150 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2151 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2152 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2153 | return; |
7ad25d48 | 2154 | } |
00d70b15 CW |
2155 | |
2156 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2157 | POSTING_READ(reg); |
b24e7179 JB |
2158 | } |
2159 | ||
2160 | /** | |
309cfea8 | 2161 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2162 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2163 | * |
575f7ab7 VS |
2164 | * Disable the pipe of @crtc, making sure that various hardware |
2165 | * specific requirements are met, if applicable, e.g. plane | |
2166 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2167 | * |
2168 | * Will wait until the pipe has shut down before returning. | |
2169 | */ | |
575f7ab7 | 2170 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2171 | { |
575f7ab7 | 2172 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2173 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2174 | enum pipe pipe = crtc->pipe; |
b24e7179 JB |
2175 | int reg; |
2176 | u32 val; | |
2177 | ||
2178 | /* | |
2179 | * Make sure planes won't keep trying to pump pixels to us, | |
2180 | * or we might hang the display. | |
2181 | */ | |
2182 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2183 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2184 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2185 | |
702e7a56 | 2186 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2187 | val = I915_READ(reg); |
00d70b15 CW |
2188 | if ((val & PIPECONF_ENABLE) == 0) |
2189 | return; | |
2190 | ||
67adc644 VS |
2191 | /* |
2192 | * Double wide has implications for planes | |
2193 | * so best keep it disabled when not needed. | |
2194 | */ | |
6e3c9717 | 2195 | if (crtc->config->double_wide) |
67adc644 VS |
2196 | val &= ~PIPECONF_DOUBLE_WIDE; |
2197 | ||
2198 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2199 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2200 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2201 | val &= ~PIPECONF_ENABLE; |
2202 | ||
2203 | I915_WRITE(reg, val); | |
2204 | if ((val & PIPECONF_ENABLE) == 0) | |
2205 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2206 | } |
2207 | ||
d74362c9 KP |
2208 | /* |
2209 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2210 | * trigger in order to latch. The display address reg provides this. | |
2211 | */ | |
1dba99f4 VS |
2212 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2213 | enum plane plane) | |
d74362c9 | 2214 | { |
3d13ef2e DL |
2215 | struct drm_device *dev = dev_priv->dev; |
2216 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2217 | |
2218 | I915_WRITE(reg, I915_READ(reg)); | |
2219 | POSTING_READ(reg); | |
d74362c9 KP |
2220 | } |
2221 | ||
b24e7179 | 2222 | /** |
262ca2b0 | 2223 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2224 | * @plane: plane to be enabled |
2225 | * @crtc: crtc for the plane | |
b24e7179 | 2226 | * |
fdd508a6 | 2227 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2228 | */ |
fdd508a6 VS |
2229 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2230 | struct drm_crtc *crtc) | |
b24e7179 | 2231 | { |
fdd508a6 VS |
2232 | struct drm_device *dev = plane->dev; |
2233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2234 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2235 | |
2236 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2237 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b70709a6 | 2238 | to_intel_plane_state(plane->state)->visible = true; |
939c2fe8 | 2239 | |
fdd508a6 VS |
2240 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2241 | crtc->x, crtc->y); | |
b24e7179 JB |
2242 | } |
2243 | ||
693db184 CW |
2244 | static bool need_vtd_wa(struct drm_device *dev) |
2245 | { | |
2246 | #ifdef CONFIG_INTEL_IOMMU | |
2247 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2248 | return true; | |
2249 | #endif | |
2250 | return false; | |
2251 | } | |
2252 | ||
50470bb0 | 2253 | unsigned int |
6761dd31 TU |
2254 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
2255 | uint64_t fb_format_modifier) | |
a57ce0b2 | 2256 | { |
6761dd31 TU |
2257 | unsigned int tile_height; |
2258 | uint32_t pixel_bytes; | |
a57ce0b2 | 2259 | |
b5d0e9bf DL |
2260 | switch (fb_format_modifier) { |
2261 | case DRM_FORMAT_MOD_NONE: | |
2262 | tile_height = 1; | |
2263 | break; | |
2264 | case I915_FORMAT_MOD_X_TILED: | |
2265 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2266 | break; | |
2267 | case I915_FORMAT_MOD_Y_TILED: | |
2268 | tile_height = 32; | |
2269 | break; | |
2270 | case I915_FORMAT_MOD_Yf_TILED: | |
6761dd31 TU |
2271 | pixel_bytes = drm_format_plane_cpp(pixel_format, 0); |
2272 | switch (pixel_bytes) { | |
b5d0e9bf | 2273 | default: |
6761dd31 | 2274 | case 1: |
b5d0e9bf DL |
2275 | tile_height = 64; |
2276 | break; | |
6761dd31 TU |
2277 | case 2: |
2278 | case 4: | |
b5d0e9bf DL |
2279 | tile_height = 32; |
2280 | break; | |
6761dd31 | 2281 | case 8: |
b5d0e9bf DL |
2282 | tile_height = 16; |
2283 | break; | |
6761dd31 | 2284 | case 16: |
b5d0e9bf DL |
2285 | WARN_ONCE(1, |
2286 | "128-bit pixels are not supported for display!"); | |
2287 | tile_height = 16; | |
2288 | break; | |
2289 | } | |
2290 | break; | |
2291 | default: | |
2292 | MISSING_CASE(fb_format_modifier); | |
2293 | tile_height = 1; | |
2294 | break; | |
2295 | } | |
091df6cb | 2296 | |
6761dd31 TU |
2297 | return tile_height; |
2298 | } | |
2299 | ||
2300 | unsigned int | |
2301 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2302 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2303 | { | |
2304 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
2305 | fb_format_modifier)); | |
a57ce0b2 JB |
2306 | } |
2307 | ||
f64b98cd TU |
2308 | static int |
2309 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, | |
2310 | const struct drm_plane_state *plane_state) | |
2311 | { | |
50470bb0 | 2312 | struct intel_rotation_info *info = &view->rotation_info; |
50470bb0 | 2313 | |
f64b98cd TU |
2314 | *view = i915_ggtt_view_normal; |
2315 | ||
50470bb0 TU |
2316 | if (!plane_state) |
2317 | return 0; | |
2318 | ||
121920fa | 2319 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
50470bb0 TU |
2320 | return 0; |
2321 | ||
9abc4648 | 2322 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2323 | |
2324 | info->height = fb->height; | |
2325 | info->pixel_format = fb->pixel_format; | |
2326 | info->pitch = fb->pitches[0]; | |
2327 | info->fb_modifier = fb->modifier[0]; | |
2328 | ||
f64b98cd TU |
2329 | return 0; |
2330 | } | |
2331 | ||
127bd2ac | 2332 | int |
850c4cdc TU |
2333 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2334 | struct drm_framebuffer *fb, | |
82bc3b2d | 2335 | const struct drm_plane_state *plane_state, |
a4872ba6 | 2336 | struct intel_engine_cs *pipelined) |
6b95a207 | 2337 | { |
850c4cdc | 2338 | struct drm_device *dev = fb->dev; |
ce453d81 | 2339 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2340 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2341 | struct i915_ggtt_view view; |
6b95a207 KH |
2342 | u32 alignment; |
2343 | int ret; | |
2344 | ||
ebcdd39e MR |
2345 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2346 | ||
7b911adc TU |
2347 | switch (fb->modifier[0]) { |
2348 | case DRM_FORMAT_MOD_NONE: | |
1fada4cc DL |
2349 | if (INTEL_INFO(dev)->gen >= 9) |
2350 | alignment = 256 * 1024; | |
2351 | else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) | |
534843da | 2352 | alignment = 128 * 1024; |
a6c45cf0 | 2353 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2354 | alignment = 4 * 1024; |
2355 | else | |
2356 | alignment = 64 * 1024; | |
6b95a207 | 2357 | break; |
7b911adc | 2358 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2359 | if (INTEL_INFO(dev)->gen >= 9) |
2360 | alignment = 256 * 1024; | |
2361 | else { | |
2362 | /* pin() will align the object as required by fence */ | |
2363 | alignment = 0; | |
2364 | } | |
6b95a207 | 2365 | break; |
7b911adc | 2366 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2367 | case I915_FORMAT_MOD_Yf_TILED: |
2368 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2369 | "Y tiling bo slipped through, driver bug!\n")) | |
2370 | return -EINVAL; | |
2371 | alignment = 1 * 1024 * 1024; | |
2372 | break; | |
6b95a207 | 2373 | default: |
7b911adc TU |
2374 | MISSING_CASE(fb->modifier[0]); |
2375 | return -EINVAL; | |
6b95a207 KH |
2376 | } |
2377 | ||
f64b98cd TU |
2378 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2379 | if (ret) | |
2380 | return ret; | |
2381 | ||
693db184 CW |
2382 | /* Note that the w/a also requires 64 PTE of padding following the |
2383 | * bo. We currently fill all unused PTE with the shadow page and so | |
2384 | * we should always have valid PTE following the scanout preventing | |
2385 | * the VT-d warning. | |
2386 | */ | |
2387 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2388 | alignment = 256 * 1024; | |
2389 | ||
d6dd6843 PZ |
2390 | /* |
2391 | * Global gtt pte registers are special registers which actually forward | |
2392 | * writes to a chunk of system memory. Which means that there is no risk | |
2393 | * that the register values disappear as soon as we call | |
2394 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2395 | * pin/unpin/fence and not more. | |
2396 | */ | |
2397 | intel_runtime_pm_get(dev_priv); | |
2398 | ||
ce453d81 | 2399 | dev_priv->mm.interruptible = false; |
e6617330 | 2400 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined, |
f64b98cd | 2401 | &view); |
48b956c5 | 2402 | if (ret) |
ce453d81 | 2403 | goto err_interruptible; |
6b95a207 KH |
2404 | |
2405 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2406 | * fence, whereas 965+ only requires a fence if using | |
2407 | * framebuffer compression. For simplicity, we always install | |
2408 | * a fence as the cost is not that onerous. | |
2409 | */ | |
06d98131 | 2410 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2411 | if (ret) |
2412 | goto err_unpin; | |
1690e1eb | 2413 | |
9a5a53b3 | 2414 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2415 | |
ce453d81 | 2416 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2417 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2418 | return 0; |
48b956c5 CW |
2419 | |
2420 | err_unpin: | |
f64b98cd | 2421 | i915_gem_object_unpin_from_display_plane(obj, &view); |
ce453d81 CW |
2422 | err_interruptible: |
2423 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2424 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2425 | return ret; |
6b95a207 KH |
2426 | } |
2427 | ||
82bc3b2d TU |
2428 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2429 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2430 | { |
82bc3b2d | 2431 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd TU |
2432 | struct i915_ggtt_view view; |
2433 | int ret; | |
82bc3b2d | 2434 | |
ebcdd39e MR |
2435 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2436 | ||
f64b98cd TU |
2437 | ret = intel_fill_fb_ggtt_view(&view, fb, plane_state); |
2438 | WARN_ONCE(ret, "Couldn't get view from plane state!"); | |
2439 | ||
1690e1eb | 2440 | i915_gem_object_unpin_fence(obj); |
f64b98cd | 2441 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2442 | } |
2443 | ||
c2c75131 DV |
2444 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2445 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2446 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2447 | unsigned int tiling_mode, | |
2448 | unsigned int cpp, | |
2449 | unsigned int pitch) | |
c2c75131 | 2450 | { |
bc752862 CW |
2451 | if (tiling_mode != I915_TILING_NONE) { |
2452 | unsigned int tile_rows, tiles; | |
c2c75131 | 2453 | |
bc752862 CW |
2454 | tile_rows = *y / 8; |
2455 | *y %= 8; | |
c2c75131 | 2456 | |
bc752862 CW |
2457 | tiles = *x / (512/cpp); |
2458 | *x %= 512/cpp; | |
2459 | ||
2460 | return tile_rows * pitch * 8 + tiles * 4096; | |
2461 | } else { | |
2462 | unsigned int offset; | |
2463 | ||
2464 | offset = *y * pitch + *x * cpp; | |
2465 | *y = 0; | |
2466 | *x = (offset & 4095) / cpp; | |
2467 | return offset & -4096; | |
2468 | } | |
c2c75131 DV |
2469 | } |
2470 | ||
b35d63fa | 2471 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2472 | { |
2473 | switch (format) { | |
2474 | case DISPPLANE_8BPP: | |
2475 | return DRM_FORMAT_C8; | |
2476 | case DISPPLANE_BGRX555: | |
2477 | return DRM_FORMAT_XRGB1555; | |
2478 | case DISPPLANE_BGRX565: | |
2479 | return DRM_FORMAT_RGB565; | |
2480 | default: | |
2481 | case DISPPLANE_BGRX888: | |
2482 | return DRM_FORMAT_XRGB8888; | |
2483 | case DISPPLANE_RGBX888: | |
2484 | return DRM_FORMAT_XBGR8888; | |
2485 | case DISPPLANE_BGRX101010: | |
2486 | return DRM_FORMAT_XRGB2101010; | |
2487 | case DISPPLANE_RGBX101010: | |
2488 | return DRM_FORMAT_XBGR2101010; | |
2489 | } | |
2490 | } | |
2491 | ||
bc8d7dff DL |
2492 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2493 | { | |
2494 | switch (format) { | |
2495 | case PLANE_CTL_FORMAT_RGB_565: | |
2496 | return DRM_FORMAT_RGB565; | |
2497 | default: | |
2498 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2499 | if (rgb_order) { | |
2500 | if (alpha) | |
2501 | return DRM_FORMAT_ABGR8888; | |
2502 | else | |
2503 | return DRM_FORMAT_XBGR8888; | |
2504 | } else { | |
2505 | if (alpha) | |
2506 | return DRM_FORMAT_ARGB8888; | |
2507 | else | |
2508 | return DRM_FORMAT_XRGB8888; | |
2509 | } | |
2510 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2511 | if (rgb_order) | |
2512 | return DRM_FORMAT_XBGR2101010; | |
2513 | else | |
2514 | return DRM_FORMAT_XRGB2101010; | |
2515 | } | |
2516 | } | |
2517 | ||
5724dbd1 | 2518 | static bool |
f6936e29 DV |
2519 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2520 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2521 | { |
2522 | struct drm_device *dev = crtc->base.dev; | |
2523 | struct drm_i915_gem_object *obj = NULL; | |
2524 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2525 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2526 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2527 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2528 | PAGE_SIZE); | |
2529 | ||
2530 | size_aligned -= base_aligned; | |
46f297fb | 2531 | |
ff2652ea CW |
2532 | if (plane_config->size == 0) |
2533 | return false; | |
2534 | ||
f37b5c2b DV |
2535 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2536 | base_aligned, | |
2537 | base_aligned, | |
2538 | size_aligned); | |
46f297fb | 2539 | if (!obj) |
484b41dd | 2540 | return false; |
46f297fb | 2541 | |
49af449b DL |
2542 | obj->tiling_mode = plane_config->tiling; |
2543 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2544 | obj->stride = fb->pitches[0]; |
46f297fb | 2545 | |
6bf129df DL |
2546 | mode_cmd.pixel_format = fb->pixel_format; |
2547 | mode_cmd.width = fb->width; | |
2548 | mode_cmd.height = fb->height; | |
2549 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2550 | mode_cmd.modifier[0] = fb->modifier[0]; |
2551 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2552 | |
2553 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2554 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2555 | &mode_cmd, obj)) { |
46f297fb JB |
2556 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2557 | goto out_unref_obj; | |
2558 | } | |
46f297fb | 2559 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2560 | |
f6936e29 | 2561 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2562 | return true; |
46f297fb JB |
2563 | |
2564 | out_unref_obj: | |
2565 | drm_gem_object_unreference(&obj->base); | |
2566 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2567 | return false; |
2568 | } | |
2569 | ||
afd65eb4 MR |
2570 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2571 | static void | |
2572 | update_state_fb(struct drm_plane *plane) | |
2573 | { | |
2574 | if (plane->fb == plane->state->fb) | |
2575 | return; | |
2576 | ||
2577 | if (plane->state->fb) | |
2578 | drm_framebuffer_unreference(plane->state->fb); | |
2579 | plane->state->fb = plane->fb; | |
2580 | if (plane->state->fb) | |
2581 | drm_framebuffer_reference(plane->state->fb); | |
2582 | } | |
2583 | ||
5724dbd1 | 2584 | static void |
f6936e29 DV |
2585 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2586 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2587 | { |
2588 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2589 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2590 | struct drm_crtc *c; |
2591 | struct intel_crtc *i; | |
2ff8fde1 | 2592 | struct drm_i915_gem_object *obj; |
88595ac9 DV |
2593 | struct drm_plane *primary = intel_crtc->base.primary; |
2594 | struct drm_framebuffer *fb; | |
484b41dd | 2595 | |
2d14030b | 2596 | if (!plane_config->fb) |
484b41dd JB |
2597 | return; |
2598 | ||
f6936e29 | 2599 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2600 | fb = &plane_config->fb->base; |
2601 | goto valid_fb; | |
f55548b5 | 2602 | } |
484b41dd | 2603 | |
2d14030b | 2604 | kfree(plane_config->fb); |
484b41dd JB |
2605 | |
2606 | /* | |
2607 | * Failed to alloc the obj, check to see if we should share | |
2608 | * an fb with another CRTC instead | |
2609 | */ | |
70e1e0ec | 2610 | for_each_crtc(dev, c) { |
484b41dd JB |
2611 | i = to_intel_crtc(c); |
2612 | ||
2613 | if (c == &intel_crtc->base) | |
2614 | continue; | |
2615 | ||
2ff8fde1 MR |
2616 | if (!i->active) |
2617 | continue; | |
2618 | ||
88595ac9 DV |
2619 | fb = c->primary->fb; |
2620 | if (!fb) | |
484b41dd JB |
2621 | continue; |
2622 | ||
88595ac9 | 2623 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2624 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2625 | drm_framebuffer_reference(fb); |
2626 | goto valid_fb; | |
484b41dd JB |
2627 | } |
2628 | } | |
88595ac9 DV |
2629 | |
2630 | return; | |
2631 | ||
2632 | valid_fb: | |
2633 | obj = intel_fb_obj(fb); | |
2634 | if (obj->tiling_mode != I915_TILING_NONE) | |
2635 | dev_priv->preserve_bios_swizzle = true; | |
2636 | ||
2637 | primary->fb = fb; | |
2638 | primary->state->crtc = &intel_crtc->base; | |
2639 | primary->crtc = &intel_crtc->base; | |
2640 | update_state_fb(primary); | |
2641 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
46f297fb JB |
2642 | } |
2643 | ||
29b9bde6 DV |
2644 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2645 | struct drm_framebuffer *fb, | |
2646 | int x, int y) | |
81255565 JB |
2647 | { |
2648 | struct drm_device *dev = crtc->dev; | |
2649 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2650 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2651 | struct drm_plane *primary = crtc->primary; |
2652 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2653 | struct drm_i915_gem_object *obj; |
81255565 | 2654 | int plane = intel_crtc->plane; |
e506a0c6 | 2655 | unsigned long linear_offset; |
81255565 | 2656 | u32 dspcntr; |
f45651ba | 2657 | u32 reg = DSPCNTR(plane); |
48404c1e | 2658 | int pixel_size; |
f45651ba | 2659 | |
b70709a6 | 2660 | if (!visible || !fb) { |
fdd508a6 VS |
2661 | I915_WRITE(reg, 0); |
2662 | if (INTEL_INFO(dev)->gen >= 4) | |
2663 | I915_WRITE(DSPSURF(plane), 0); | |
2664 | else | |
2665 | I915_WRITE(DSPADDR(plane), 0); | |
2666 | POSTING_READ(reg); | |
2667 | return; | |
2668 | } | |
2669 | ||
c9ba6fad VS |
2670 | obj = intel_fb_obj(fb); |
2671 | if (WARN_ON(obj == NULL)) | |
2672 | return; | |
2673 | ||
2674 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2675 | ||
f45651ba VS |
2676 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2677 | ||
fdd508a6 | 2678 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2679 | |
2680 | if (INTEL_INFO(dev)->gen < 4) { | |
2681 | if (intel_crtc->pipe == PIPE_B) | |
2682 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2683 | ||
2684 | /* pipesrc and dspsize control the size that is scaled from, | |
2685 | * which should always be the user's requested size. | |
2686 | */ | |
2687 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2688 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2689 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2690 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2691 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2692 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2693 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2694 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2695 | I915_WRITE(PRIMPOS(plane), 0); |
2696 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2697 | } |
81255565 | 2698 | |
57779d06 VS |
2699 | switch (fb->pixel_format) { |
2700 | case DRM_FORMAT_C8: | |
81255565 JB |
2701 | dspcntr |= DISPPLANE_8BPP; |
2702 | break; | |
57779d06 VS |
2703 | case DRM_FORMAT_XRGB1555: |
2704 | case DRM_FORMAT_ARGB1555: | |
2705 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2706 | break; |
57779d06 VS |
2707 | case DRM_FORMAT_RGB565: |
2708 | dspcntr |= DISPPLANE_BGRX565; | |
2709 | break; | |
2710 | case DRM_FORMAT_XRGB8888: | |
2711 | case DRM_FORMAT_ARGB8888: | |
2712 | dspcntr |= DISPPLANE_BGRX888; | |
2713 | break; | |
2714 | case DRM_FORMAT_XBGR8888: | |
2715 | case DRM_FORMAT_ABGR8888: | |
2716 | dspcntr |= DISPPLANE_RGBX888; | |
2717 | break; | |
2718 | case DRM_FORMAT_XRGB2101010: | |
2719 | case DRM_FORMAT_ARGB2101010: | |
2720 | dspcntr |= DISPPLANE_BGRX101010; | |
2721 | break; | |
2722 | case DRM_FORMAT_XBGR2101010: | |
2723 | case DRM_FORMAT_ABGR2101010: | |
2724 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2725 | break; |
2726 | default: | |
baba133a | 2727 | BUG(); |
81255565 | 2728 | } |
57779d06 | 2729 | |
f45651ba VS |
2730 | if (INTEL_INFO(dev)->gen >= 4 && |
2731 | obj->tiling_mode != I915_TILING_NONE) | |
2732 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2733 | |
de1aa629 VS |
2734 | if (IS_G4X(dev)) |
2735 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2736 | ||
b9897127 | 2737 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2738 | |
c2c75131 DV |
2739 | if (INTEL_INFO(dev)->gen >= 4) { |
2740 | intel_crtc->dspaddr_offset = | |
bc752862 | 2741 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2742 | pixel_size, |
bc752862 | 2743 | fb->pitches[0]); |
c2c75131 DV |
2744 | linear_offset -= intel_crtc->dspaddr_offset; |
2745 | } else { | |
e506a0c6 | 2746 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2747 | } |
e506a0c6 | 2748 | |
8e7d688b | 2749 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2750 | dspcntr |= DISPPLANE_ROTATE_180; |
2751 | ||
6e3c9717 ACO |
2752 | x += (intel_crtc->config->pipe_src_w - 1); |
2753 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2754 | |
2755 | /* Finding the last pixel of the last line of the display | |
2756 | data and adding to linear_offset*/ | |
2757 | linear_offset += | |
6e3c9717 ACO |
2758 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2759 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2760 | } |
2761 | ||
2762 | I915_WRITE(reg, dspcntr); | |
2763 | ||
01f2c773 | 2764 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2765 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2766 | I915_WRITE(DSPSURF(plane), |
2767 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2768 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2769 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2770 | } else |
f343c5f6 | 2771 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2772 | POSTING_READ(reg); |
17638cd6 JB |
2773 | } |
2774 | ||
29b9bde6 DV |
2775 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2776 | struct drm_framebuffer *fb, | |
2777 | int x, int y) | |
17638cd6 JB |
2778 | { |
2779 | struct drm_device *dev = crtc->dev; | |
2780 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2781 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2782 | struct drm_plane *primary = crtc->primary; |
2783 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2784 | struct drm_i915_gem_object *obj; |
17638cd6 | 2785 | int plane = intel_crtc->plane; |
e506a0c6 | 2786 | unsigned long linear_offset; |
17638cd6 | 2787 | u32 dspcntr; |
f45651ba | 2788 | u32 reg = DSPCNTR(plane); |
48404c1e | 2789 | int pixel_size; |
f45651ba | 2790 | |
b70709a6 | 2791 | if (!visible || !fb) { |
fdd508a6 VS |
2792 | I915_WRITE(reg, 0); |
2793 | I915_WRITE(DSPSURF(plane), 0); | |
2794 | POSTING_READ(reg); | |
2795 | return; | |
2796 | } | |
2797 | ||
c9ba6fad VS |
2798 | obj = intel_fb_obj(fb); |
2799 | if (WARN_ON(obj == NULL)) | |
2800 | return; | |
2801 | ||
2802 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2803 | ||
f45651ba VS |
2804 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2805 | ||
fdd508a6 | 2806 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2807 | |
2808 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2809 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2810 | |
57779d06 VS |
2811 | switch (fb->pixel_format) { |
2812 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2813 | dspcntr |= DISPPLANE_8BPP; |
2814 | break; | |
57779d06 VS |
2815 | case DRM_FORMAT_RGB565: |
2816 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2817 | break; |
57779d06 VS |
2818 | case DRM_FORMAT_XRGB8888: |
2819 | case DRM_FORMAT_ARGB8888: | |
2820 | dspcntr |= DISPPLANE_BGRX888; | |
2821 | break; | |
2822 | case DRM_FORMAT_XBGR8888: | |
2823 | case DRM_FORMAT_ABGR8888: | |
2824 | dspcntr |= DISPPLANE_RGBX888; | |
2825 | break; | |
2826 | case DRM_FORMAT_XRGB2101010: | |
2827 | case DRM_FORMAT_ARGB2101010: | |
2828 | dspcntr |= DISPPLANE_BGRX101010; | |
2829 | break; | |
2830 | case DRM_FORMAT_XBGR2101010: | |
2831 | case DRM_FORMAT_ABGR2101010: | |
2832 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2833 | break; |
2834 | default: | |
baba133a | 2835 | BUG(); |
17638cd6 JB |
2836 | } |
2837 | ||
2838 | if (obj->tiling_mode != I915_TILING_NONE) | |
2839 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2840 | |
f45651ba | 2841 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2842 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2843 | |
b9897127 | 2844 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2845 | intel_crtc->dspaddr_offset = |
bc752862 | 2846 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2847 | pixel_size, |
bc752862 | 2848 | fb->pitches[0]); |
c2c75131 | 2849 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2850 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2851 | dspcntr |= DISPPLANE_ROTATE_180; |
2852 | ||
2853 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2854 | x += (intel_crtc->config->pipe_src_w - 1); |
2855 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2856 | |
2857 | /* Finding the last pixel of the last line of the display | |
2858 | data and adding to linear_offset*/ | |
2859 | linear_offset += | |
6e3c9717 ACO |
2860 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2861 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2862 | } |
2863 | } | |
2864 | ||
2865 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2866 | |
01f2c773 | 2867 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2868 | I915_WRITE(DSPSURF(plane), |
2869 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2870 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2871 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2872 | } else { | |
2873 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2874 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2875 | } | |
17638cd6 | 2876 | POSTING_READ(reg); |
17638cd6 JB |
2877 | } |
2878 | ||
b321803d DL |
2879 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2880 | uint32_t pixel_format) | |
2881 | { | |
2882 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2883 | ||
2884 | /* | |
2885 | * The stride is either expressed as a multiple of 64 bytes | |
2886 | * chunks for linear buffers or in number of tiles for tiled | |
2887 | * buffers. | |
2888 | */ | |
2889 | switch (fb_modifier) { | |
2890 | case DRM_FORMAT_MOD_NONE: | |
2891 | return 64; | |
2892 | case I915_FORMAT_MOD_X_TILED: | |
2893 | if (INTEL_INFO(dev)->gen == 2) | |
2894 | return 128; | |
2895 | return 512; | |
2896 | case I915_FORMAT_MOD_Y_TILED: | |
2897 | /* No need to check for old gens and Y tiling since this is | |
2898 | * about the display engine and those will be blocked before | |
2899 | * we get here. | |
2900 | */ | |
2901 | return 128; | |
2902 | case I915_FORMAT_MOD_Yf_TILED: | |
2903 | if (bits_per_pixel == 8) | |
2904 | return 64; | |
2905 | else | |
2906 | return 128; | |
2907 | default: | |
2908 | MISSING_CASE(fb_modifier); | |
2909 | return 64; | |
2910 | } | |
2911 | } | |
2912 | ||
121920fa TU |
2913 | unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane, |
2914 | struct drm_i915_gem_object *obj) | |
2915 | { | |
9abc4648 | 2916 | const struct i915_ggtt_view *view = &i915_ggtt_view_normal; |
121920fa TU |
2917 | |
2918 | if (intel_rotation_90_or_270(intel_plane->base.state->rotation)) | |
9abc4648 | 2919 | view = &i915_ggtt_view_rotated; |
121920fa TU |
2920 | |
2921 | return i915_gem_obj_ggtt_offset_view(obj, view); | |
2922 | } | |
2923 | ||
a1b2278e CK |
2924 | /* |
2925 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2926 | */ | |
2927 | void skl_detach_scalers(struct intel_crtc *intel_crtc) | |
2928 | { | |
2929 | struct drm_device *dev; | |
2930 | struct drm_i915_private *dev_priv; | |
2931 | struct intel_crtc_scaler_state *scaler_state; | |
2932 | int i; | |
2933 | ||
2934 | if (!intel_crtc || !intel_crtc->config) | |
2935 | return; | |
2936 | ||
2937 | dev = intel_crtc->base.dev; | |
2938 | dev_priv = dev->dev_private; | |
2939 | scaler_state = &intel_crtc->config->scaler_state; | |
2940 | ||
2941 | /* loop through and disable scalers that aren't in use */ | |
2942 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
2943 | if (!scaler_state->scalers[i].in_use) { | |
2944 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0); | |
2945 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0); | |
2946 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0); | |
2947 | DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n", | |
2948 | intel_crtc->base.base.id, intel_crtc->pipe, i); | |
2949 | } | |
2950 | } | |
2951 | } | |
2952 | ||
6156a456 | 2953 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2954 | { |
6156a456 CK |
2955 | u32 plane_ctl_format = 0; |
2956 | switch (pixel_format) { | |
70d21f0e | 2957 | case DRM_FORMAT_RGB565: |
6156a456 | 2958 | plane_ctl_format = PLANE_CTL_FORMAT_RGB_565; |
f75fb42a | 2959 | break; |
70d21f0e | 2960 | case DRM_FORMAT_XBGR8888: |
6156a456 CK |
2961 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
2962 | break; | |
2963 | case DRM_FORMAT_XRGB8888: | |
2964 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888; | |
70d21f0e | 2965 | break; |
6156a456 CK |
2966 | /* |
2967 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2968 | * to be already pre-multiplied. We need to add a knob (or a different | |
2969 | * DRM_FORMAT) for user-space to configure that. | |
2970 | */ | |
f75fb42a | 2971 | case DRM_FORMAT_ABGR8888: |
6156a456 CK |
2972 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
2973 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
2974 | break; | |
2975 | case DRM_FORMAT_ARGB8888: | |
2976 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | | |
2977 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; | |
f75fb42a | 2978 | break; |
70d21f0e | 2979 | case DRM_FORMAT_XRGB2101010: |
6156a456 | 2980 | plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e DL |
2981 | break; |
2982 | case DRM_FORMAT_XBGR2101010: | |
6156a456 CK |
2983 | plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
2984 | break; | |
2985 | case DRM_FORMAT_YUYV: | |
2986 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; | |
2987 | break; | |
2988 | case DRM_FORMAT_YVYU: | |
2989 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; | |
2990 | break; | |
2991 | case DRM_FORMAT_UYVY: | |
2992 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; | |
2993 | break; | |
2994 | case DRM_FORMAT_VYUY: | |
2995 | plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; | |
70d21f0e DL |
2996 | break; |
2997 | default: | |
2998 | BUG(); | |
2999 | } | |
6156a456 CK |
3000 | return plane_ctl_format; |
3001 | } | |
70d21f0e | 3002 | |
6156a456 CK |
3003 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3004 | { | |
3005 | u32 plane_ctl_tiling = 0; | |
3006 | switch (fb_modifier) { | |
30af77c4 | 3007 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3008 | break; |
30af77c4 | 3009 | case I915_FORMAT_MOD_X_TILED: |
6156a456 | 3010 | plane_ctl_tiling = PLANE_CTL_TILED_X; |
b321803d DL |
3011 | break; |
3012 | case I915_FORMAT_MOD_Y_TILED: | |
6156a456 | 3013 | plane_ctl_tiling = PLANE_CTL_TILED_Y; |
b321803d DL |
3014 | break; |
3015 | case I915_FORMAT_MOD_Yf_TILED: | |
6156a456 | 3016 | plane_ctl_tiling = PLANE_CTL_TILED_YF; |
70d21f0e DL |
3017 | break; |
3018 | default: | |
6156a456 | 3019 | MISSING_CASE(fb_modifier); |
70d21f0e | 3020 | } |
6156a456 CK |
3021 | return plane_ctl_tiling; |
3022 | } | |
70d21f0e | 3023 | |
6156a456 CK |
3024 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3025 | { | |
3026 | u32 plane_ctl_rotation = 0; | |
3b7a5119 | 3027 | switch (rotation) { |
6156a456 CK |
3028 | case BIT(DRM_ROTATE_0): |
3029 | break; | |
3b7a5119 | 3030 | case BIT(DRM_ROTATE_90): |
6156a456 | 3031 | plane_ctl_rotation = PLANE_CTL_ROTATE_90; |
3b7a5119 | 3032 | break; |
3b7a5119 | 3033 | case BIT(DRM_ROTATE_180): |
6156a456 | 3034 | plane_ctl_rotation = PLANE_CTL_ROTATE_180; |
3b7a5119 | 3035 | break; |
3b7a5119 | 3036 | case BIT(DRM_ROTATE_270): |
6156a456 | 3037 | plane_ctl_rotation = PLANE_CTL_ROTATE_270; |
3b7a5119 | 3038 | break; |
6156a456 CK |
3039 | default: |
3040 | MISSING_CASE(rotation); | |
3041 | } | |
3042 | ||
3043 | return plane_ctl_rotation; | |
3044 | } | |
3045 | ||
3046 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3047 | struct drm_framebuffer *fb, | |
3048 | int x, int y) | |
3049 | { | |
3050 | struct drm_device *dev = crtc->dev; | |
3051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3052 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3053 | struct drm_plane *plane = crtc->primary; |
3054 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3055 | struct drm_i915_gem_object *obj; |
3056 | int pipe = intel_crtc->pipe; | |
3057 | u32 plane_ctl, stride_div, stride; | |
3058 | u32 tile_height, plane_offset, plane_size; | |
3059 | unsigned int rotation; | |
3060 | int x_offset, y_offset; | |
3061 | unsigned long surf_addr; | |
6156a456 CK |
3062 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3063 | struct intel_plane_state *plane_state; | |
3064 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3065 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3066 | int scaler_id = -1; | |
3067 | ||
6156a456 CK |
3068 | plane_state = to_intel_plane_state(plane->state); |
3069 | ||
b70709a6 | 3070 | if (!visible || !fb) { |
6156a456 CK |
3071 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3072 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3073 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3074 | return; | |
3b7a5119 | 3075 | } |
70d21f0e | 3076 | |
6156a456 CK |
3077 | plane_ctl = PLANE_CTL_ENABLE | |
3078 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3079 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3080 | ||
3081 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3082 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3083 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3084 | ||
3085 | rotation = plane->state->rotation; | |
3086 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3087 | ||
b321803d DL |
3088 | obj = intel_fb_obj(fb); |
3089 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3090 | fb->pixel_format); | |
3b7a5119 SJ |
3091 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj); |
3092 | ||
6156a456 CK |
3093 | /* |
3094 | * FIXME: intel_plane_state->src, dst aren't set when transitional | |
3095 | * update_plane helpers are called from legacy paths. | |
3096 | * Once full atomic crtc is available, below check can be avoided. | |
3097 | */ | |
3098 | if (drm_rect_width(&plane_state->src)) { | |
3099 | scaler_id = plane_state->scaler_id; | |
3100 | src_x = plane_state->src.x1 >> 16; | |
3101 | src_y = plane_state->src.y1 >> 16; | |
3102 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3103 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3104 | dst_x = plane_state->dst.x1; | |
3105 | dst_y = plane_state->dst.y1; | |
3106 | dst_w = drm_rect_width(&plane_state->dst); | |
3107 | dst_h = drm_rect_height(&plane_state->dst); | |
3108 | ||
3109 | WARN_ON(x != src_x || y != src_y); | |
3110 | } else { | |
3111 | src_w = intel_crtc->config->pipe_src_w; | |
3112 | src_h = intel_crtc->config->pipe_src_h; | |
3113 | } | |
3114 | ||
3b7a5119 SJ |
3115 | if (intel_rotation_90_or_270(rotation)) { |
3116 | /* stride = Surface height in tiles */ | |
3117 | tile_height = intel_tile_height(dev, fb->bits_per_pixel, | |
3118 | fb->modifier[0]); | |
3119 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
6156a456 | 3120 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3121 | y_offset = x; |
6156a456 | 3122 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3123 | } else { |
3124 | stride = fb->pitches[0] / stride_div; | |
3125 | x_offset = x; | |
3126 | y_offset = y; | |
6156a456 | 3127 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3128 | } |
3129 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3130 | |
70d21f0e | 3131 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3132 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3133 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3134 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3135 | |
3136 | if (scaler_id >= 0) { | |
3137 | uint32_t ps_ctrl = 0; | |
3138 | ||
3139 | WARN_ON(!dst_w || !dst_h); | |
3140 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3141 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3142 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3143 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3144 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3145 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3146 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3147 | } else { | |
3148 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3149 | } | |
3150 | ||
121920fa | 3151 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3152 | |
3153 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3154 | } | |
3155 | ||
17638cd6 JB |
3156 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3157 | static int | |
3158 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3159 | int x, int y, enum mode_set_atomic state) | |
3160 | { | |
3161 | struct drm_device *dev = crtc->dev; | |
3162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3163 | |
6b8e6ed0 CW |
3164 | if (dev_priv->display.disable_fbc) |
3165 | dev_priv->display.disable_fbc(dev); | |
81255565 | 3166 | |
29b9bde6 DV |
3167 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3168 | ||
3169 | return 0; | |
81255565 JB |
3170 | } |
3171 | ||
7514747d | 3172 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3173 | { |
96a02917 VS |
3174 | struct drm_crtc *crtc; |
3175 | ||
70e1e0ec | 3176 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3177 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3178 | enum plane plane = intel_crtc->plane; | |
3179 | ||
3180 | intel_prepare_page_flip(dev, plane); | |
3181 | intel_finish_page_flip_plane(dev, plane); | |
3182 | } | |
7514747d VS |
3183 | } |
3184 | ||
3185 | static void intel_update_primary_planes(struct drm_device *dev) | |
3186 | { | |
3187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3188 | struct drm_crtc *crtc; | |
96a02917 | 3189 | |
70e1e0ec | 3190 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3191 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3192 | ||
51fd371b | 3193 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
3194 | /* |
3195 | * FIXME: Once we have proper support for primary planes (and | |
3196 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 3197 | * a NULL crtc->primary->fb. |
947fdaad | 3198 | */ |
f4510a27 | 3199 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 3200 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 3201 | crtc->primary->fb, |
262ca2b0 MR |
3202 | crtc->x, |
3203 | crtc->y); | |
51fd371b | 3204 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
3205 | } |
3206 | } | |
3207 | ||
ce22dba9 ML |
3208 | void intel_crtc_reset(struct intel_crtc *crtc) |
3209 | { | |
3210 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
3211 | ||
3212 | if (!crtc->active) | |
3213 | return; | |
3214 | ||
3215 | intel_crtc_disable_planes(&crtc->base); | |
3216 | dev_priv->display.crtc_disable(&crtc->base); | |
3217 | dev_priv->display.crtc_enable(&crtc->base); | |
3218 | intel_crtc_enable_planes(&crtc->base); | |
3219 | } | |
3220 | ||
7514747d VS |
3221 | void intel_prepare_reset(struct drm_device *dev) |
3222 | { | |
f98ce92f VS |
3223 | struct drm_i915_private *dev_priv = to_i915(dev); |
3224 | struct intel_crtc *crtc; | |
3225 | ||
7514747d VS |
3226 | /* no reset support for gen2 */ |
3227 | if (IS_GEN2(dev)) | |
3228 | return; | |
3229 | ||
3230 | /* reset doesn't touch the display */ | |
3231 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3232 | return; | |
3233 | ||
3234 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3235 | |
3236 | /* | |
3237 | * Disabling the crtcs gracefully seems nicer. Also the | |
3238 | * g33 docs say we should at least disable all the planes. | |
3239 | */ | |
3240 | for_each_intel_crtc(dev, crtc) { | |
ce22dba9 ML |
3241 | if (!crtc->active) |
3242 | continue; | |
3243 | ||
3244 | intel_crtc_disable_planes(&crtc->base); | |
3245 | dev_priv->display.crtc_disable(&crtc->base); | |
f98ce92f | 3246 | } |
7514747d VS |
3247 | } |
3248 | ||
3249 | void intel_finish_reset(struct drm_device *dev) | |
3250 | { | |
3251 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3252 | ||
3253 | /* | |
3254 | * Flips in the rings will be nuked by the reset, | |
3255 | * so complete all pending flips so that user space | |
3256 | * will get its events and not get stuck. | |
3257 | */ | |
3258 | intel_complete_page_flips(dev); | |
3259 | ||
3260 | /* no reset support for gen2 */ | |
3261 | if (IS_GEN2(dev)) | |
3262 | return; | |
3263 | ||
3264 | /* reset doesn't touch the display */ | |
3265 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3266 | /* | |
3267 | * Flips in the rings have been nuked by the reset, | |
3268 | * so update the base address of all primary | |
3269 | * planes to the the last fb to make sure we're | |
3270 | * showing the correct fb after a reset. | |
3271 | */ | |
3272 | intel_update_primary_planes(dev); | |
3273 | return; | |
3274 | } | |
3275 | ||
3276 | /* | |
3277 | * The display has been reset as well, | |
3278 | * so need a full re-initialization. | |
3279 | */ | |
3280 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3281 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3282 | ||
3283 | intel_modeset_init_hw(dev); | |
3284 | ||
3285 | spin_lock_irq(&dev_priv->irq_lock); | |
3286 | if (dev_priv->display.hpd_irq_setup) | |
3287 | dev_priv->display.hpd_irq_setup(dev); | |
3288 | spin_unlock_irq(&dev_priv->irq_lock); | |
3289 | ||
3290 | intel_modeset_setup_hw_state(dev, true); | |
3291 | ||
3292 | intel_hpd_init(dev_priv); | |
3293 | ||
3294 | drm_modeset_unlock_all(dev); | |
3295 | } | |
3296 | ||
14667a4b CW |
3297 | static int |
3298 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
3299 | { | |
2ff8fde1 | 3300 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
3301 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3302 | bool was_interruptible = dev_priv->mm.interruptible; | |
3303 | int ret; | |
3304 | ||
14667a4b CW |
3305 | /* Big Hammer, we also need to ensure that any pending |
3306 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
3307 | * current scanout is retired before unpinning the old | |
3308 | * framebuffer. | |
3309 | * | |
3310 | * This should only fail upon a hung GPU, in which case we | |
3311 | * can safely continue. | |
3312 | */ | |
3313 | dev_priv->mm.interruptible = false; | |
3314 | ret = i915_gem_object_finish_gpu(obj); | |
3315 | dev_priv->mm.interruptible = was_interruptible; | |
3316 | ||
3317 | return ret; | |
3318 | } | |
3319 | ||
7d5e3799 CW |
3320 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3321 | { | |
3322 | struct drm_device *dev = crtc->dev; | |
3323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3324 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3325 | bool pending; |
3326 | ||
3327 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3328 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3329 | return false; | |
3330 | ||
5e2d7afc | 3331 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3332 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3333 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3334 | |
3335 | return pending; | |
3336 | } | |
3337 | ||
e30e8f75 GP |
3338 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
3339 | { | |
3340 | struct drm_device *dev = crtc->base.dev; | |
3341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3342 | const struct drm_display_mode *adjusted_mode; | |
3343 | ||
3344 | if (!i915.fastboot) | |
3345 | return; | |
3346 | ||
3347 | /* | |
3348 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3349 | * that in compute_mode_changes we check the native mode (not the pfit | |
3350 | * mode) to see if we can flip rather than do a full mode set. In the | |
3351 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3352 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3353 | * sized surface. | |
3354 | * | |
3355 | * To fix this properly, we need to hoist the checks up into | |
3356 | * compute_mode_changes (or above), check the actual pfit state and | |
3357 | * whether the platform allows pfit disable with pipe active, and only | |
3358 | * then update the pipesrc and pfit state, even on the flip path. | |
3359 | */ | |
3360 | ||
6e3c9717 | 3361 | adjusted_mode = &crtc->config->base.adjusted_mode; |
e30e8f75 GP |
3362 | |
3363 | I915_WRITE(PIPESRC(crtc->pipe), | |
3364 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
3365 | (adjusted_mode->crtc_vdisplay - 1)); | |
6e3c9717 | 3366 | if (!crtc->config->pch_pfit.enabled && |
409ee761 ACO |
3367 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || |
3368 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
e30e8f75 GP |
3369 | I915_WRITE(PF_CTL(crtc->pipe), 0); |
3370 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
3371 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
3372 | } | |
6e3c9717 ACO |
3373 | crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay; |
3374 | crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay; | |
e30e8f75 GP |
3375 | } |
3376 | ||
5e84e1a4 ZW |
3377 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3378 | { | |
3379 | struct drm_device *dev = crtc->dev; | |
3380 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3381 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3382 | int pipe = intel_crtc->pipe; | |
3383 | u32 reg, temp; | |
3384 | ||
3385 | /* enable normal train */ | |
3386 | reg = FDI_TX_CTL(pipe); | |
3387 | temp = I915_READ(reg); | |
61e499bf | 3388 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3389 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3390 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3391 | } else { |
3392 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3393 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3394 | } |
5e84e1a4 ZW |
3395 | I915_WRITE(reg, temp); |
3396 | ||
3397 | reg = FDI_RX_CTL(pipe); | |
3398 | temp = I915_READ(reg); | |
3399 | if (HAS_PCH_CPT(dev)) { | |
3400 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3401 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3402 | } else { | |
3403 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3404 | temp |= FDI_LINK_TRAIN_NONE; | |
3405 | } | |
3406 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3407 | ||
3408 | /* wait one idle pattern time */ | |
3409 | POSTING_READ(reg); | |
3410 | udelay(1000); | |
357555c0 JB |
3411 | |
3412 | /* IVB wants error correction enabled */ | |
3413 | if (IS_IVYBRIDGE(dev)) | |
3414 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3415 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3416 | } |
3417 | ||
8db9d77b ZW |
3418 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3419 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3420 | { | |
3421 | struct drm_device *dev = crtc->dev; | |
3422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3423 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3424 | int pipe = intel_crtc->pipe; | |
5eddb70b | 3425 | u32 reg, temp, tries; |
8db9d77b | 3426 | |
1c8562f6 | 3427 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3428 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3429 | |
e1a44743 AJ |
3430 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3431 | for train result */ | |
5eddb70b CW |
3432 | reg = FDI_RX_IMR(pipe); |
3433 | temp = I915_READ(reg); | |
e1a44743 AJ |
3434 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3435 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3436 | I915_WRITE(reg, temp); |
3437 | I915_READ(reg); | |
e1a44743 AJ |
3438 | udelay(150); |
3439 | ||
8db9d77b | 3440 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3441 | reg = FDI_TX_CTL(pipe); |
3442 | temp = I915_READ(reg); | |
627eb5a3 | 3443 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3444 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3445 | temp &= ~FDI_LINK_TRAIN_NONE; |
3446 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3447 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3448 | |
5eddb70b CW |
3449 | reg = FDI_RX_CTL(pipe); |
3450 | temp = I915_READ(reg); | |
8db9d77b ZW |
3451 | temp &= ~FDI_LINK_TRAIN_NONE; |
3452 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3453 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3454 | ||
3455 | POSTING_READ(reg); | |
8db9d77b ZW |
3456 | udelay(150); |
3457 | ||
5b2adf89 | 3458 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3459 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3460 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3461 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3462 | |
5eddb70b | 3463 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3464 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3465 | temp = I915_READ(reg); |
8db9d77b ZW |
3466 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3467 | ||
3468 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3469 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3470 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3471 | break; |
3472 | } | |
8db9d77b | 3473 | } |
e1a44743 | 3474 | if (tries == 5) |
5eddb70b | 3475 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3476 | |
3477 | /* Train 2 */ | |
5eddb70b CW |
3478 | reg = FDI_TX_CTL(pipe); |
3479 | temp = I915_READ(reg); | |
8db9d77b ZW |
3480 | temp &= ~FDI_LINK_TRAIN_NONE; |
3481 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3482 | I915_WRITE(reg, temp); |
8db9d77b | 3483 | |
5eddb70b CW |
3484 | reg = FDI_RX_CTL(pipe); |
3485 | temp = I915_READ(reg); | |
8db9d77b ZW |
3486 | temp &= ~FDI_LINK_TRAIN_NONE; |
3487 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3488 | I915_WRITE(reg, temp); |
8db9d77b | 3489 | |
5eddb70b CW |
3490 | POSTING_READ(reg); |
3491 | udelay(150); | |
8db9d77b | 3492 | |
5eddb70b | 3493 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3494 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3495 | temp = I915_READ(reg); |
8db9d77b ZW |
3496 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3497 | ||
3498 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3499 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3500 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3501 | break; | |
3502 | } | |
8db9d77b | 3503 | } |
e1a44743 | 3504 | if (tries == 5) |
5eddb70b | 3505 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3506 | |
3507 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3508 | |
8db9d77b ZW |
3509 | } |
3510 | ||
0206e353 | 3511 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3512 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3513 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3514 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3515 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3516 | }; | |
3517 | ||
3518 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3519 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3520 | { | |
3521 | struct drm_device *dev = crtc->dev; | |
3522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3523 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3524 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3525 | u32 reg, temp, i, retry; |
8db9d77b | 3526 | |
e1a44743 AJ |
3527 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3528 | for train result */ | |
5eddb70b CW |
3529 | reg = FDI_RX_IMR(pipe); |
3530 | temp = I915_READ(reg); | |
e1a44743 AJ |
3531 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3532 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3533 | I915_WRITE(reg, temp); |
3534 | ||
3535 | POSTING_READ(reg); | |
e1a44743 AJ |
3536 | udelay(150); |
3537 | ||
8db9d77b | 3538 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3539 | reg = FDI_TX_CTL(pipe); |
3540 | temp = I915_READ(reg); | |
627eb5a3 | 3541 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3542 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3543 | temp &= ~FDI_LINK_TRAIN_NONE; |
3544 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3545 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3546 | /* SNB-B */ | |
3547 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3548 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3549 | |
d74cf324 DV |
3550 | I915_WRITE(FDI_RX_MISC(pipe), |
3551 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3552 | ||
5eddb70b CW |
3553 | reg = FDI_RX_CTL(pipe); |
3554 | temp = I915_READ(reg); | |
8db9d77b ZW |
3555 | if (HAS_PCH_CPT(dev)) { |
3556 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3557 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3558 | } else { | |
3559 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3560 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3561 | } | |
5eddb70b CW |
3562 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3563 | ||
3564 | POSTING_READ(reg); | |
8db9d77b ZW |
3565 | udelay(150); |
3566 | ||
0206e353 | 3567 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3568 | reg = FDI_TX_CTL(pipe); |
3569 | temp = I915_READ(reg); | |
8db9d77b ZW |
3570 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3571 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3572 | I915_WRITE(reg, temp); |
3573 | ||
3574 | POSTING_READ(reg); | |
8db9d77b ZW |
3575 | udelay(500); |
3576 | ||
fa37d39e SP |
3577 | for (retry = 0; retry < 5; retry++) { |
3578 | reg = FDI_RX_IIR(pipe); | |
3579 | temp = I915_READ(reg); | |
3580 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3581 | if (temp & FDI_RX_BIT_LOCK) { | |
3582 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3583 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3584 | break; | |
3585 | } | |
3586 | udelay(50); | |
8db9d77b | 3587 | } |
fa37d39e SP |
3588 | if (retry < 5) |
3589 | break; | |
8db9d77b ZW |
3590 | } |
3591 | if (i == 4) | |
5eddb70b | 3592 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3593 | |
3594 | /* Train 2 */ | |
5eddb70b CW |
3595 | reg = FDI_TX_CTL(pipe); |
3596 | temp = I915_READ(reg); | |
8db9d77b ZW |
3597 | temp &= ~FDI_LINK_TRAIN_NONE; |
3598 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3599 | if (IS_GEN6(dev)) { | |
3600 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3601 | /* SNB-B */ | |
3602 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3603 | } | |
5eddb70b | 3604 | I915_WRITE(reg, temp); |
8db9d77b | 3605 | |
5eddb70b CW |
3606 | reg = FDI_RX_CTL(pipe); |
3607 | temp = I915_READ(reg); | |
8db9d77b ZW |
3608 | if (HAS_PCH_CPT(dev)) { |
3609 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3610 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3611 | } else { | |
3612 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3613 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3614 | } | |
5eddb70b CW |
3615 | I915_WRITE(reg, temp); |
3616 | ||
3617 | POSTING_READ(reg); | |
8db9d77b ZW |
3618 | udelay(150); |
3619 | ||
0206e353 | 3620 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3621 | reg = FDI_TX_CTL(pipe); |
3622 | temp = I915_READ(reg); | |
8db9d77b ZW |
3623 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3624 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3625 | I915_WRITE(reg, temp); |
3626 | ||
3627 | POSTING_READ(reg); | |
8db9d77b ZW |
3628 | udelay(500); |
3629 | ||
fa37d39e SP |
3630 | for (retry = 0; retry < 5; retry++) { |
3631 | reg = FDI_RX_IIR(pipe); | |
3632 | temp = I915_READ(reg); | |
3633 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3634 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3635 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3636 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3637 | break; | |
3638 | } | |
3639 | udelay(50); | |
8db9d77b | 3640 | } |
fa37d39e SP |
3641 | if (retry < 5) |
3642 | break; | |
8db9d77b ZW |
3643 | } |
3644 | if (i == 4) | |
5eddb70b | 3645 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3646 | |
3647 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3648 | } | |
3649 | ||
357555c0 JB |
3650 | /* Manual link training for Ivy Bridge A0 parts */ |
3651 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3652 | { | |
3653 | struct drm_device *dev = crtc->dev; | |
3654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3655 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3656 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3657 | u32 reg, temp, i, j; |
357555c0 JB |
3658 | |
3659 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3660 | for train result */ | |
3661 | reg = FDI_RX_IMR(pipe); | |
3662 | temp = I915_READ(reg); | |
3663 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3664 | temp &= ~FDI_RX_BIT_LOCK; | |
3665 | I915_WRITE(reg, temp); | |
3666 | ||
3667 | POSTING_READ(reg); | |
3668 | udelay(150); | |
3669 | ||
01a415fd DV |
3670 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3671 | I915_READ(FDI_RX_IIR(pipe))); | |
3672 | ||
139ccd3f JB |
3673 | /* Try each vswing and preemphasis setting twice before moving on */ |
3674 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3675 | /* disable first in case we need to retry */ | |
3676 | reg = FDI_TX_CTL(pipe); | |
3677 | temp = I915_READ(reg); | |
3678 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3679 | temp &= ~FDI_TX_ENABLE; | |
3680 | I915_WRITE(reg, temp); | |
357555c0 | 3681 | |
139ccd3f JB |
3682 | reg = FDI_RX_CTL(pipe); |
3683 | temp = I915_READ(reg); | |
3684 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3685 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3686 | temp &= ~FDI_RX_ENABLE; | |
3687 | I915_WRITE(reg, temp); | |
357555c0 | 3688 | |
139ccd3f | 3689 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3690 | reg = FDI_TX_CTL(pipe); |
3691 | temp = I915_READ(reg); | |
139ccd3f | 3692 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3693 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3694 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3695 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3696 | temp |= snb_b_fdi_train_param[j/2]; |
3697 | temp |= FDI_COMPOSITE_SYNC; | |
3698 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3699 | |
139ccd3f JB |
3700 | I915_WRITE(FDI_RX_MISC(pipe), |
3701 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3702 | |
139ccd3f | 3703 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3704 | temp = I915_READ(reg); |
139ccd3f JB |
3705 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3706 | temp |= FDI_COMPOSITE_SYNC; | |
3707 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3708 | |
139ccd3f JB |
3709 | POSTING_READ(reg); |
3710 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3711 | |
139ccd3f JB |
3712 | for (i = 0; i < 4; i++) { |
3713 | reg = FDI_RX_IIR(pipe); | |
3714 | temp = I915_READ(reg); | |
3715 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3716 | |
139ccd3f JB |
3717 | if (temp & FDI_RX_BIT_LOCK || |
3718 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3719 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3720 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3721 | i); | |
3722 | break; | |
3723 | } | |
3724 | udelay(1); /* should be 0.5us */ | |
3725 | } | |
3726 | if (i == 4) { | |
3727 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3728 | continue; | |
3729 | } | |
357555c0 | 3730 | |
139ccd3f | 3731 | /* Train 2 */ |
357555c0 JB |
3732 | reg = FDI_TX_CTL(pipe); |
3733 | temp = I915_READ(reg); | |
139ccd3f JB |
3734 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3735 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3736 | I915_WRITE(reg, temp); | |
3737 | ||
3738 | reg = FDI_RX_CTL(pipe); | |
3739 | temp = I915_READ(reg); | |
3740 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3741 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3742 | I915_WRITE(reg, temp); |
3743 | ||
3744 | POSTING_READ(reg); | |
139ccd3f | 3745 | udelay(2); /* should be 1.5us */ |
357555c0 | 3746 | |
139ccd3f JB |
3747 | for (i = 0; i < 4; i++) { |
3748 | reg = FDI_RX_IIR(pipe); | |
3749 | temp = I915_READ(reg); | |
3750 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3751 | |
139ccd3f JB |
3752 | if (temp & FDI_RX_SYMBOL_LOCK || |
3753 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3754 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3755 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3756 | i); | |
3757 | goto train_done; | |
3758 | } | |
3759 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3760 | } |
139ccd3f JB |
3761 | if (i == 4) |
3762 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3763 | } |
357555c0 | 3764 | |
139ccd3f | 3765 | train_done: |
357555c0 JB |
3766 | DRM_DEBUG_KMS("FDI train done.\n"); |
3767 | } | |
3768 | ||
88cefb6c | 3769 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3770 | { |
88cefb6c | 3771 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3772 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3773 | int pipe = intel_crtc->pipe; |
5eddb70b | 3774 | u32 reg, temp; |
79e53945 | 3775 | |
c64e311e | 3776 | |
c98e9dcf | 3777 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3778 | reg = FDI_RX_CTL(pipe); |
3779 | temp = I915_READ(reg); | |
627eb5a3 | 3780 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3781 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3782 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3783 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3784 | ||
3785 | POSTING_READ(reg); | |
c98e9dcf JB |
3786 | udelay(200); |
3787 | ||
3788 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3789 | temp = I915_READ(reg); |
3790 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3791 | ||
3792 | POSTING_READ(reg); | |
c98e9dcf JB |
3793 | udelay(200); |
3794 | ||
20749730 PZ |
3795 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3796 | reg = FDI_TX_CTL(pipe); | |
3797 | temp = I915_READ(reg); | |
3798 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3799 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3800 | |
20749730 PZ |
3801 | POSTING_READ(reg); |
3802 | udelay(100); | |
6be4a607 | 3803 | } |
0e23b99d JB |
3804 | } |
3805 | ||
88cefb6c DV |
3806 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3807 | { | |
3808 | struct drm_device *dev = intel_crtc->base.dev; | |
3809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3810 | int pipe = intel_crtc->pipe; | |
3811 | u32 reg, temp; | |
3812 | ||
3813 | /* Switch from PCDclk to Rawclk */ | |
3814 | reg = FDI_RX_CTL(pipe); | |
3815 | temp = I915_READ(reg); | |
3816 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3817 | ||
3818 | /* Disable CPU FDI TX PLL */ | |
3819 | reg = FDI_TX_CTL(pipe); | |
3820 | temp = I915_READ(reg); | |
3821 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3822 | ||
3823 | POSTING_READ(reg); | |
3824 | udelay(100); | |
3825 | ||
3826 | reg = FDI_RX_CTL(pipe); | |
3827 | temp = I915_READ(reg); | |
3828 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3829 | ||
3830 | /* Wait for the clocks to turn off. */ | |
3831 | POSTING_READ(reg); | |
3832 | udelay(100); | |
3833 | } | |
3834 | ||
0fc932b8 JB |
3835 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3836 | { | |
3837 | struct drm_device *dev = crtc->dev; | |
3838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3839 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3840 | int pipe = intel_crtc->pipe; | |
3841 | u32 reg, temp; | |
3842 | ||
3843 | /* disable CPU FDI tx and PCH FDI rx */ | |
3844 | reg = FDI_TX_CTL(pipe); | |
3845 | temp = I915_READ(reg); | |
3846 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3847 | POSTING_READ(reg); | |
3848 | ||
3849 | reg = FDI_RX_CTL(pipe); | |
3850 | temp = I915_READ(reg); | |
3851 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3852 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3853 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3854 | ||
3855 | POSTING_READ(reg); | |
3856 | udelay(100); | |
3857 | ||
3858 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3859 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3860 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3861 | |
3862 | /* still set train pattern 1 */ | |
3863 | reg = FDI_TX_CTL(pipe); | |
3864 | temp = I915_READ(reg); | |
3865 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3866 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3867 | I915_WRITE(reg, temp); | |
3868 | ||
3869 | reg = FDI_RX_CTL(pipe); | |
3870 | temp = I915_READ(reg); | |
3871 | if (HAS_PCH_CPT(dev)) { | |
3872 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3873 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3874 | } else { | |
3875 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3876 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3877 | } | |
3878 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3879 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3880 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3881 | I915_WRITE(reg, temp); |
3882 | ||
3883 | POSTING_READ(reg); | |
3884 | udelay(100); | |
3885 | } | |
3886 | ||
5dce5b93 CW |
3887 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3888 | { | |
3889 | struct intel_crtc *crtc; | |
3890 | ||
3891 | /* Note that we don't need to be called with mode_config.lock here | |
3892 | * as our list of CRTC objects is static for the lifetime of the | |
3893 | * device and so cannot disappear as we iterate. Similarly, we can | |
3894 | * happily treat the predicates as racy, atomic checks as userspace | |
3895 | * cannot claim and pin a new fb without at least acquring the | |
3896 | * struct_mutex and so serialising with us. | |
3897 | */ | |
d3fcc808 | 3898 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3899 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3900 | continue; | |
3901 | ||
3902 | if (crtc->unpin_work) | |
3903 | intel_wait_for_vblank(dev, crtc->pipe); | |
3904 | ||
3905 | return true; | |
3906 | } | |
3907 | ||
3908 | return false; | |
3909 | } | |
3910 | ||
d6bbafa1 CW |
3911 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3912 | { | |
3913 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3914 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3915 | ||
3916 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3917 | smp_rmb(); | |
3918 | intel_crtc->unpin_work = NULL; | |
3919 | ||
3920 | if (work->event) | |
3921 | drm_send_vblank_event(intel_crtc->base.dev, | |
3922 | intel_crtc->pipe, | |
3923 | work->event); | |
3924 | ||
3925 | drm_crtc_vblank_put(&intel_crtc->base); | |
3926 | ||
3927 | wake_up_all(&dev_priv->pending_flip_queue); | |
3928 | queue_work(dev_priv->wq, &work->work); | |
3929 | ||
3930 | trace_i915_flip_complete(intel_crtc->plane, | |
3931 | work->pending_flip_obj); | |
3932 | } | |
3933 | ||
46a55d30 | 3934 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3935 | { |
0f91128d | 3936 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3937 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3938 | |
2c10d571 | 3939 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3940 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3941 | !intel_crtc_has_pending_flip(crtc), | |
3942 | 60*HZ) == 0)) { | |
3943 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2c10d571 | 3944 | |
5e2d7afc | 3945 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3946 | if (intel_crtc->unpin_work) { |
3947 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3948 | page_flip_completed(intel_crtc); | |
3949 | } | |
5e2d7afc | 3950 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3951 | } |
5bb61643 | 3952 | |
975d568a CW |
3953 | if (crtc->primary->fb) { |
3954 | mutex_lock(&dev->struct_mutex); | |
3955 | intel_finish_fb(crtc->primary->fb); | |
3956 | mutex_unlock(&dev->struct_mutex); | |
3957 | } | |
e6c3a2a6 CW |
3958 | } |
3959 | ||
e615efe4 ED |
3960 | /* Program iCLKIP clock to the desired frequency */ |
3961 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3962 | { | |
3963 | struct drm_device *dev = crtc->dev; | |
3964 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3965 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3966 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3967 | u32 temp; | |
3968 | ||
09153000 DV |
3969 | mutex_lock(&dev_priv->dpio_lock); |
3970 | ||
e615efe4 ED |
3971 | /* It is necessary to ungate the pixclk gate prior to programming |
3972 | * the divisors, and gate it back when it is done. | |
3973 | */ | |
3974 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3975 | ||
3976 | /* Disable SSCCTL */ | |
3977 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3978 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3979 | SBI_SSCCTL_DISABLE, | |
3980 | SBI_ICLK); | |
e615efe4 ED |
3981 | |
3982 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3983 | if (clock == 20000) { |
e615efe4 ED |
3984 | auxdiv = 1; |
3985 | divsel = 0x41; | |
3986 | phaseinc = 0x20; | |
3987 | } else { | |
3988 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3989 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3990 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3991 | * convert the virtual clock precision to KHz here for higher |
3992 | * precision. | |
3993 | */ | |
3994 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3995 | u32 iclk_pi_range = 64; | |
3996 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3997 | ||
12d7ceed | 3998 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3999 | msb_divisor_value = desired_divisor / iclk_pi_range; |
4000 | pi_value = desired_divisor % iclk_pi_range; | |
4001 | ||
4002 | auxdiv = 0; | |
4003 | divsel = msb_divisor_value - 2; | |
4004 | phaseinc = pi_value; | |
4005 | } | |
4006 | ||
4007 | /* This should not happen with any sane values */ | |
4008 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4009 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4010 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4011 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4012 | ||
4013 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4014 | clock, |
e615efe4 ED |
4015 | auxdiv, |
4016 | divsel, | |
4017 | phasedir, | |
4018 | phaseinc); | |
4019 | ||
4020 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 4021 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4022 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4023 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4024 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4025 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4026 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4027 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4028 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4029 | |
4030 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4031 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4032 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4033 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4034 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4035 | |
4036 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4037 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4038 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4039 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
4040 | |
4041 | /* Wait for initialization time */ | |
4042 | udelay(24); | |
4043 | ||
4044 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
4045 | |
4046 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
4047 | } |
4048 | ||
275f01b2 DV |
4049 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4050 | enum pipe pch_transcoder) | |
4051 | { | |
4052 | struct drm_device *dev = crtc->base.dev; | |
4053 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4054 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4055 | |
4056 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4057 | I915_READ(HTOTAL(cpu_transcoder))); | |
4058 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4059 | I915_READ(HBLANK(cpu_transcoder))); | |
4060 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4061 | I915_READ(HSYNC(cpu_transcoder))); | |
4062 | ||
4063 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4064 | I915_READ(VTOTAL(cpu_transcoder))); | |
4065 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4066 | I915_READ(VBLANK(cpu_transcoder))); | |
4067 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4068 | I915_READ(VSYNC(cpu_transcoder))); | |
4069 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4070 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4071 | } | |
4072 | ||
003632d9 | 4073 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4074 | { |
4075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4076 | uint32_t temp; | |
4077 | ||
4078 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4079 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4080 | return; |
4081 | ||
4082 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4083 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4084 | ||
003632d9 ACO |
4085 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4086 | if (enable) | |
4087 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4088 | ||
4089 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4090 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4091 | POSTING_READ(SOUTH_CHICKEN1); | |
4092 | } | |
4093 | ||
4094 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4095 | { | |
4096 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4097 | |
4098 | switch (intel_crtc->pipe) { | |
4099 | case PIPE_A: | |
4100 | break; | |
4101 | case PIPE_B: | |
6e3c9717 | 4102 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4103 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4104 | else |
003632d9 | 4105 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4106 | |
4107 | break; | |
4108 | case PIPE_C: | |
003632d9 | 4109 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4110 | |
4111 | break; | |
4112 | default: | |
4113 | BUG(); | |
4114 | } | |
4115 | } | |
4116 | ||
f67a559d JB |
4117 | /* |
4118 | * Enable PCH resources required for PCH ports: | |
4119 | * - PCH PLLs | |
4120 | * - FDI training & RX/TX | |
4121 | * - update transcoder timings | |
4122 | * - DP transcoding bits | |
4123 | * - transcoder | |
4124 | */ | |
4125 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4126 | { |
4127 | struct drm_device *dev = crtc->dev; | |
4128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4129 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4130 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 4131 | u32 reg, temp; |
2c07245f | 4132 | |
ab9412ba | 4133 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4134 | |
1fbc0d78 DV |
4135 | if (IS_IVYBRIDGE(dev)) |
4136 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4137 | ||
cd986abb DV |
4138 | /* Write the TU size bits before fdi link training, so that error |
4139 | * detection works. */ | |
4140 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4141 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4142 | ||
c98e9dcf | 4143 | /* For PCH output, training FDI link */ |
674cf967 | 4144 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4145 | |
3ad8a208 DV |
4146 | /* We need to program the right clock selection before writing the pixel |
4147 | * mutliplier into the DPLL. */ | |
303b81e0 | 4148 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4149 | u32 sel; |
4b645f14 | 4150 | |
c98e9dcf | 4151 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4152 | temp |= TRANS_DPLL_ENABLE(pipe); |
4153 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4154 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4155 | temp |= sel; |
4156 | else | |
4157 | temp &= ~sel; | |
c98e9dcf | 4158 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4159 | } |
5eddb70b | 4160 | |
3ad8a208 DV |
4161 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4162 | * transcoder, and we actually should do this to not upset any PCH | |
4163 | * transcoder that already use the clock when we share it. | |
4164 | * | |
4165 | * Note that enable_shared_dpll tries to do the right thing, but | |
4166 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4167 | * the right LVDS enable sequence. */ | |
85b3894f | 4168 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4169 | |
d9b6cb56 JB |
4170 | /* set transcoder timing, panel must allow it */ |
4171 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4172 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4173 | |
303b81e0 | 4174 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4175 | |
c98e9dcf | 4176 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4177 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
dfd07d72 | 4178 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
4179 | reg = TRANS_DP_CTL(pipe); |
4180 | temp = I915_READ(reg); | |
4181 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4182 | TRANS_DP_SYNC_MASK | |
4183 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
4184 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
4185 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 4186 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
4187 | |
4188 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 4189 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 4190 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4191 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4192 | |
4193 | switch (intel_trans_dp_port_sel(crtc)) { | |
4194 | case PCH_DP_B: | |
5eddb70b | 4195 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
4196 | break; |
4197 | case PCH_DP_C: | |
5eddb70b | 4198 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
4199 | break; |
4200 | case PCH_DP_D: | |
5eddb70b | 4201 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4202 | break; |
4203 | default: | |
e95d41e1 | 4204 | BUG(); |
32f9d658 | 4205 | } |
2c07245f | 4206 | |
5eddb70b | 4207 | I915_WRITE(reg, temp); |
6be4a607 | 4208 | } |
b52eb4dc | 4209 | |
b8a4f404 | 4210 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4211 | } |
4212 | ||
1507e5bd PZ |
4213 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4214 | { | |
4215 | struct drm_device *dev = crtc->dev; | |
4216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4217 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4218 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4219 | |
ab9412ba | 4220 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4221 | |
8c52b5e8 | 4222 | lpt_program_iclkip(crtc); |
1507e5bd | 4223 | |
0540e488 | 4224 | /* Set transcoder timing. */ |
275f01b2 | 4225 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4226 | |
937bb610 | 4227 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4228 | } |
4229 | ||
716c2e55 | 4230 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 4231 | { |
e2b78267 | 4232 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
4233 | |
4234 | if (pll == NULL) | |
4235 | return; | |
4236 | ||
3e369b76 | 4237 | if (!(pll->config.crtc_mask & (1 << crtc->pipe))) { |
1e6f2ddc | 4238 | WARN(1, "bad %s crtc mask\n", pll->name); |
ee7b9f93 JB |
4239 | return; |
4240 | } | |
4241 | ||
3e369b76 ACO |
4242 | pll->config.crtc_mask &= ~(1 << crtc->pipe); |
4243 | if (pll->config.crtc_mask == 0) { | |
f4a091c7 DV |
4244 | WARN_ON(pll->on); |
4245 | WARN_ON(pll->active); | |
4246 | } | |
4247 | ||
6e3c9717 | 4248 | crtc->config->shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
4249 | } |
4250 | ||
190f68c5 ACO |
4251 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4252 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4253 | { |
e2b78267 | 4254 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4255 | struct intel_shared_dpll *pll; |
e2b78267 | 4256 | enum intel_dpll_id i; |
ee7b9f93 | 4257 | |
98b6bd99 DV |
4258 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4259 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4260 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4261 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4262 | |
46edb027 DV |
4263 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4264 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4265 | |
8bd31e67 | 4266 | WARN_ON(pll->new_config->crtc_mask); |
f2a69f44 | 4267 | |
98b6bd99 DV |
4268 | goto found; |
4269 | } | |
4270 | ||
bcddf610 S |
4271 | if (IS_BROXTON(dev_priv->dev)) { |
4272 | /* PLL is attached to port in bxt */ | |
4273 | struct intel_encoder *encoder; | |
4274 | struct intel_digital_port *intel_dig_port; | |
4275 | ||
4276 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4277 | if (WARN_ON(!encoder)) | |
4278 | return NULL; | |
4279 | ||
4280 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4281 | /* 1:1 mapping between ports and PLLs */ | |
4282 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4283 | pll = &dev_priv->shared_dplls[i]; | |
4284 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4285 | crtc->base.base.id, pll->name); | |
4286 | WARN_ON(pll->new_config->crtc_mask); | |
4287 | ||
4288 | goto found; | |
4289 | } | |
4290 | ||
e72f9fbf DV |
4291 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4292 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
4293 | |
4294 | /* Only want to check enabled timings first */ | |
8bd31e67 | 4295 | if (pll->new_config->crtc_mask == 0) |
ee7b9f93 JB |
4296 | continue; |
4297 | ||
190f68c5 | 4298 | if (memcmp(&crtc_state->dpll_hw_state, |
8bd31e67 ACO |
4299 | &pll->new_config->hw_state, |
4300 | sizeof(pll->new_config->hw_state)) == 0) { | |
4301 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", | |
1e6f2ddc | 4302 | crtc->base.base.id, pll->name, |
8bd31e67 ACO |
4303 | pll->new_config->crtc_mask, |
4304 | pll->active); | |
ee7b9f93 JB |
4305 | goto found; |
4306 | } | |
4307 | } | |
4308 | ||
4309 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4310 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4311 | pll = &dev_priv->shared_dplls[i]; | |
8bd31e67 | 4312 | if (pll->new_config->crtc_mask == 0) { |
46edb027 DV |
4313 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4314 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4315 | goto found; |
4316 | } | |
4317 | } | |
4318 | ||
4319 | return NULL; | |
4320 | ||
4321 | found: | |
8bd31e67 | 4322 | if (pll->new_config->crtc_mask == 0) |
190f68c5 | 4323 | pll->new_config->hw_state = crtc_state->dpll_hw_state; |
f2a69f44 | 4324 | |
190f68c5 | 4325 | crtc_state->shared_dpll = i; |
46edb027 DV |
4326 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4327 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4328 | |
8bd31e67 | 4329 | pll->new_config->crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4330 | |
ee7b9f93 JB |
4331 | return pll; |
4332 | } | |
4333 | ||
8bd31e67 ACO |
4334 | /** |
4335 | * intel_shared_dpll_start_config - start a new PLL staged config | |
4336 | * @dev_priv: DRM device | |
4337 | * @clear_pipes: mask of pipes that will have their PLLs freed | |
4338 | * | |
4339 | * Starts a new PLL staged config, copying the current config but | |
4340 | * releasing the references of pipes specified in clear_pipes. | |
4341 | */ | |
4342 | static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv, | |
4343 | unsigned clear_pipes) | |
4344 | { | |
4345 | struct intel_shared_dpll *pll; | |
4346 | enum intel_dpll_id i; | |
4347 | ||
4348 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4349 | pll = &dev_priv->shared_dplls[i]; | |
4350 | ||
4351 | pll->new_config = kmemdup(&pll->config, sizeof pll->config, | |
4352 | GFP_KERNEL); | |
4353 | if (!pll->new_config) | |
4354 | goto cleanup; | |
4355 | ||
4356 | pll->new_config->crtc_mask &= ~clear_pipes; | |
4357 | } | |
4358 | ||
4359 | return 0; | |
4360 | ||
4361 | cleanup: | |
4362 | while (--i >= 0) { | |
4363 | pll = &dev_priv->shared_dplls[i]; | |
f354d733 | 4364 | kfree(pll->new_config); |
8bd31e67 ACO |
4365 | pll->new_config = NULL; |
4366 | } | |
4367 | ||
4368 | return -ENOMEM; | |
4369 | } | |
4370 | ||
4371 | static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv) | |
4372 | { | |
4373 | struct intel_shared_dpll *pll; | |
4374 | enum intel_dpll_id i; | |
4375 | ||
4376 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4377 | pll = &dev_priv->shared_dplls[i]; | |
4378 | ||
4379 | WARN_ON(pll->new_config == &pll->config); | |
4380 | ||
4381 | pll->config = *pll->new_config; | |
4382 | kfree(pll->new_config); | |
4383 | pll->new_config = NULL; | |
4384 | } | |
4385 | } | |
4386 | ||
4387 | static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv) | |
4388 | { | |
4389 | struct intel_shared_dpll *pll; | |
4390 | enum intel_dpll_id i; | |
4391 | ||
4392 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
4393 | pll = &dev_priv->shared_dplls[i]; | |
4394 | ||
4395 | WARN_ON(pll->new_config == &pll->config); | |
4396 | ||
4397 | kfree(pll->new_config); | |
4398 | pll->new_config = NULL; | |
4399 | } | |
4400 | } | |
4401 | ||
a1520318 | 4402 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4403 | { |
4404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 4405 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4406 | u32 temp; |
4407 | ||
4408 | temp = I915_READ(dslreg); | |
4409 | udelay(500); | |
4410 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4411 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4412 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4413 | } |
4414 | } | |
4415 | ||
a1b2278e CK |
4416 | /** |
4417 | * skl_update_scaler_users - Stages update to crtc's scaler state | |
4418 | * @intel_crtc: crtc | |
4419 | * @crtc_state: crtc_state | |
4420 | * @plane: plane (NULL indicates crtc is requesting update) | |
4421 | * @plane_state: plane's state | |
4422 | * @force_detach: request unconditional detachment of scaler | |
4423 | * | |
4424 | * This function updates scaler state for requested plane or crtc. | |
4425 | * To request scaler usage update for a plane, caller shall pass plane pointer. | |
4426 | * To request scaler usage update for crtc, caller shall pass plane pointer | |
4427 | * as NULL. | |
4428 | * | |
4429 | * Return | |
4430 | * 0 - scaler_usage updated successfully | |
4431 | * error - requested scaling cannot be supported or other error condition | |
4432 | */ | |
4433 | int | |
4434 | skl_update_scaler_users( | |
4435 | struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state, | |
4436 | struct intel_plane *intel_plane, struct intel_plane_state *plane_state, | |
4437 | int force_detach) | |
4438 | { | |
4439 | int need_scaling; | |
4440 | int idx; | |
4441 | int src_w, src_h, dst_w, dst_h; | |
4442 | int *scaler_id; | |
4443 | struct drm_framebuffer *fb; | |
4444 | struct intel_crtc_scaler_state *scaler_state; | |
6156a456 | 4445 | unsigned int rotation; |
a1b2278e CK |
4446 | |
4447 | if (!intel_crtc || !crtc_state) | |
4448 | return 0; | |
4449 | ||
4450 | scaler_state = &crtc_state->scaler_state; | |
4451 | ||
4452 | idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX; | |
4453 | fb = intel_plane ? plane_state->base.fb : NULL; | |
4454 | ||
4455 | if (intel_plane) { | |
4456 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
4457 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
4458 | dst_w = drm_rect_width(&plane_state->dst); | |
4459 | dst_h = drm_rect_height(&plane_state->dst); | |
4460 | scaler_id = &plane_state->scaler_id; | |
6156a456 | 4461 | rotation = plane_state->base.rotation; |
a1b2278e CK |
4462 | } else { |
4463 | struct drm_display_mode *adjusted_mode = | |
4464 | &crtc_state->base.adjusted_mode; | |
4465 | src_w = crtc_state->pipe_src_w; | |
4466 | src_h = crtc_state->pipe_src_h; | |
4467 | dst_w = adjusted_mode->hdisplay; | |
4468 | dst_h = adjusted_mode->vdisplay; | |
4469 | scaler_id = &scaler_state->scaler_id; | |
6156a456 | 4470 | rotation = DRM_ROTATE_0; |
a1b2278e | 4471 | } |
6156a456 CK |
4472 | |
4473 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4474 | (src_h != dst_w || src_w != dst_h): | |
4475 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4476 | |
4477 | /* | |
4478 | * if plane is being disabled or scaler is no more required or force detach | |
4479 | * - free scaler binded to this plane/crtc | |
4480 | * - in order to do this, update crtc->scaler_usage | |
4481 | * | |
4482 | * Here scaler state in crtc_state is set free so that | |
4483 | * scaler can be assigned to other user. Actual register | |
4484 | * update to free the scaler is done in plane/panel-fit programming. | |
4485 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4486 | */ | |
4487 | if (force_detach || !need_scaling || (intel_plane && | |
4488 | (!fb || !plane_state->visible))) { | |
4489 | if (*scaler_id >= 0) { | |
4490 | scaler_state->scaler_users &= ~(1 << idx); | |
4491 | scaler_state->scalers[*scaler_id].in_use = 0; | |
4492 | ||
4493 | DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d " | |
4494 | "crtc_state = %p scaler_users = 0x%x\n", | |
4495 | intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC", | |
4496 | intel_plane ? intel_plane->base.base.id : | |
4497 | intel_crtc->base.base.id, crtc_state, | |
4498 | scaler_state->scaler_users); | |
4499 | *scaler_id = -1; | |
4500 | } | |
4501 | return 0; | |
4502 | } | |
4503 | ||
4504 | /* range checks */ | |
4505 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4506 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4507 | ||
4508 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4509 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
4510 | DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u " | |
4511 | "size is out of scaler range\n", | |
4512 | intel_plane ? "PLANE" : "CRTC", | |
4513 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4514 | intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h); | |
4515 | return -EINVAL; | |
4516 | } | |
4517 | ||
4518 | /* check colorkey */ | |
4519 | if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) { | |
4520 | DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed", | |
4521 | intel_plane->base.base.id); | |
4522 | return -EINVAL; | |
4523 | } | |
4524 | ||
4525 | /* Check src format */ | |
4526 | if (intel_plane) { | |
4527 | switch (fb->pixel_format) { | |
4528 | case DRM_FORMAT_RGB565: | |
4529 | case DRM_FORMAT_XBGR8888: | |
4530 | case DRM_FORMAT_XRGB8888: | |
4531 | case DRM_FORMAT_ABGR8888: | |
4532 | case DRM_FORMAT_ARGB8888: | |
4533 | case DRM_FORMAT_XRGB2101010: | |
4534 | case DRM_FORMAT_ARGB2101010: | |
4535 | case DRM_FORMAT_XBGR2101010: | |
4536 | case DRM_FORMAT_ABGR2101010: | |
4537 | case DRM_FORMAT_YUYV: | |
4538 | case DRM_FORMAT_YVYU: | |
4539 | case DRM_FORMAT_UYVY: | |
4540 | case DRM_FORMAT_VYUY: | |
4541 | break; | |
4542 | default: | |
4543 | DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n", | |
4544 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4545 | return -EINVAL; | |
4546 | } | |
4547 | } | |
4548 | ||
4549 | /* mark this plane as a scaler user in crtc_state */ | |
4550 | scaler_state->scaler_users |= (1 << idx); | |
4551 | DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u " | |
4552 | "crtc_state = %p scaler_users = 0x%x\n", | |
4553 | intel_plane ? "PLANE" : "CRTC", | |
4554 | intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id, | |
4555 | src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users); | |
4556 | return 0; | |
4557 | } | |
4558 | ||
4559 | static void skylake_pfit_update(struct intel_crtc *crtc, int enable) | |
bd2e244f JB |
4560 | { |
4561 | struct drm_device *dev = crtc->base.dev; | |
4562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4563 | int pipe = crtc->pipe; | |
a1b2278e CK |
4564 | struct intel_crtc_scaler_state *scaler_state = |
4565 | &crtc->config->scaler_state; | |
4566 | ||
4567 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4568 | ||
4569 | /* To update pfit, first update scaler state */ | |
4570 | skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable); | |
4571 | intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config); | |
4572 | skl_detach_scalers(crtc); | |
4573 | if (!enable) | |
4574 | return; | |
bd2e244f | 4575 | |
6e3c9717 | 4576 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4577 | int id; |
4578 | ||
4579 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4580 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4581 | return; | |
4582 | } | |
4583 | ||
4584 | id = scaler_state->scaler_id; | |
4585 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4586 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4587 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4588 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4589 | ||
4590 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4591 | } |
4592 | } | |
4593 | ||
b074cec8 JB |
4594 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4595 | { | |
4596 | struct drm_device *dev = crtc->base.dev; | |
4597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4598 | int pipe = crtc->pipe; | |
4599 | ||
6e3c9717 | 4600 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4601 | /* Force use of hard-coded filter coefficients |
4602 | * as some pre-programmed values are broken, | |
4603 | * e.g. x201. | |
4604 | */ | |
4605 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4606 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4607 | PF_PIPE_SEL_IVB(pipe)); | |
4608 | else | |
4609 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4610 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4611 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4612 | } |
4613 | } | |
4614 | ||
4a3b8769 | 4615 | static void intel_enable_sprite_planes(struct drm_crtc *crtc) |
bb53d4ae VS |
4616 | { |
4617 | struct drm_device *dev = crtc->dev; | |
4618 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 4619 | struct drm_plane *plane; |
bb53d4ae VS |
4620 | struct intel_plane *intel_plane; |
4621 | ||
af2b653b MR |
4622 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
4623 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
4624 | if (intel_plane->pipe == pipe) |
4625 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 4626 | } |
bb53d4ae VS |
4627 | } |
4628 | ||
20bc8673 | 4629 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4630 | { |
cea165c3 VS |
4631 | struct drm_device *dev = crtc->base.dev; |
4632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4633 | |
6e3c9717 | 4634 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4635 | return; |
4636 | ||
cea165c3 VS |
4637 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4638 | intel_wait_for_vblank(dev, crtc->pipe); | |
4639 | ||
d77e4531 | 4640 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4641 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4642 | mutex_lock(&dev_priv->rps.hw_lock); |
4643 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4644 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4645 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4646 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4647 | * mailbox." Moreover, the mailbox may return a bogus state, |
4648 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4649 | */ |
4650 | } else { | |
4651 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4652 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4653 | * is essentially intel_wait_for_vblank. If we don't have this | |
4654 | * and don't wait for vblanks until the end of crtc_enable, then | |
4655 | * the HW state readout code will complain that the expected | |
4656 | * IPS_CTL value is not the one we read. */ | |
4657 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4658 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4659 | } | |
d77e4531 PZ |
4660 | } |
4661 | ||
20bc8673 | 4662 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4663 | { |
4664 | struct drm_device *dev = crtc->base.dev; | |
4665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4666 | ||
6e3c9717 | 4667 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4668 | return; |
4669 | ||
4670 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4671 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4672 | mutex_lock(&dev_priv->rps.hw_lock); |
4673 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4674 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4675 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4676 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4677 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4678 | } else { |
2a114cc1 | 4679 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4680 | POSTING_READ(IPS_CTL); |
4681 | } | |
d77e4531 PZ |
4682 | |
4683 | /* We need to wait for a vblank before we can disable the plane. */ | |
4684 | intel_wait_for_vblank(dev, crtc->pipe); | |
4685 | } | |
4686 | ||
4687 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4688 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4689 | { | |
4690 | struct drm_device *dev = crtc->dev; | |
4691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4692 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4693 | enum pipe pipe = intel_crtc->pipe; | |
4694 | int palreg = PALETTE(pipe); | |
4695 | int i; | |
4696 | bool reenable_ips = false; | |
4697 | ||
4698 | /* The clocks have to be on to load the palette. */ | |
83d65738 | 4699 | if (!crtc->state->enable || !intel_crtc->active) |
d77e4531 PZ |
4700 | return; |
4701 | ||
50360403 | 4702 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
409ee761 | 4703 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) |
d77e4531 PZ |
4704 | assert_dsi_pll_enabled(dev_priv); |
4705 | else | |
4706 | assert_pll_enabled(dev_priv, pipe); | |
4707 | } | |
4708 | ||
4709 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4710 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4711 | palreg = LGC_PALETTE(pipe); |
4712 | ||
4713 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4714 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4715 | */ | |
6e3c9717 | 4716 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4717 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4718 | GAMMA_MODE_MODE_SPLIT)) { | |
4719 | hsw_disable_ips(intel_crtc); | |
4720 | reenable_ips = true; | |
4721 | } | |
4722 | ||
4723 | for (i = 0; i < 256; i++) { | |
4724 | I915_WRITE(palreg + 4 * i, | |
4725 | (intel_crtc->lut_r[i] << 16) | | |
4726 | (intel_crtc->lut_g[i] << 8) | | |
4727 | intel_crtc->lut_b[i]); | |
4728 | } | |
4729 | ||
4730 | if (reenable_ips) | |
4731 | hsw_enable_ips(intel_crtc); | |
4732 | } | |
4733 | ||
7cac945f | 4734 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4735 | { |
7cac945f | 4736 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4737 | struct drm_device *dev = intel_crtc->base.dev; |
4738 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4739 | ||
4740 | mutex_lock(&dev->struct_mutex); | |
4741 | dev_priv->mm.interruptible = false; | |
4742 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4743 | dev_priv->mm.interruptible = true; | |
4744 | mutex_unlock(&dev->struct_mutex); | |
4745 | } | |
4746 | ||
4747 | /* Let userspace switch the overlay on again. In most cases userspace | |
4748 | * has to recompute where to put it anyway. | |
4749 | */ | |
4750 | } | |
4751 | ||
87d4300a ML |
4752 | /** |
4753 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4754 | * @crtc: the CRTC whose primary plane was just enabled | |
4755 | * | |
4756 | * Performs potentially sleeping operations that must be done after the primary | |
4757 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4758 | * called due to an explicit primary plane update, or due to an implicit | |
4759 | * re-enable that is caused when a sprite plane is updated to no longer | |
4760 | * completely hide the primary plane. | |
4761 | */ | |
4762 | static void | |
4763 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4764 | { |
4765 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4766 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4768 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4769 | |
87d4300a ML |
4770 | /* |
4771 | * BDW signals flip done immediately if the plane | |
4772 | * is disabled, even if the plane enable is already | |
4773 | * armed to occur at the next vblank :( | |
4774 | */ | |
4775 | if (IS_BROADWELL(dev)) | |
4776 | intel_wait_for_vblank(dev, pipe); | |
a5c4d7bc | 4777 | |
87d4300a ML |
4778 | /* |
4779 | * FIXME IPS should be fine as long as one plane is | |
4780 | * enabled, but in practice it seems to have problems | |
4781 | * when going from primary only to sprite only and vice | |
4782 | * versa. | |
4783 | */ | |
a5c4d7bc VS |
4784 | hsw_enable_ips(intel_crtc); |
4785 | ||
4786 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 4787 | intel_fbc_update(dev); |
a5c4d7bc | 4788 | mutex_unlock(&dev->struct_mutex); |
f99d7069 DV |
4789 | |
4790 | /* | |
87d4300a ML |
4791 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4792 | * So don't enable underrun reporting before at least some planes | |
4793 | * are enabled. | |
4794 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4795 | * but leave the pipe running. | |
f99d7069 | 4796 | */ |
87d4300a ML |
4797 | if (IS_GEN2(dev)) |
4798 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4799 | ||
4800 | /* Underruns don't raise interrupts, so check manually. */ | |
4801 | if (HAS_GMCH_DISPLAY(dev)) | |
4802 | i9xx_check_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4803 | } |
4804 | ||
87d4300a ML |
4805 | /** |
4806 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4807 | * @crtc: the CRTC whose primary plane is to be disabled | |
4808 | * | |
4809 | * Performs potentially sleeping operations that must be done before the | |
4810 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4811 | * be called due to an explicit primary plane update, or due to an implicit | |
4812 | * disable that is caused when a sprite plane completely hides the primary | |
4813 | * plane. | |
4814 | */ | |
4815 | static void | |
4816 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4817 | { |
4818 | struct drm_device *dev = crtc->dev; | |
4819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4820 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4821 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4822 | |
87d4300a ML |
4823 | /* |
4824 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4825 | * So diasble underrun reporting before all the planes get disabled. | |
4826 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4827 | * but leave the pipe running. | |
4828 | */ | |
4829 | if (IS_GEN2(dev)) | |
4830 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4831 | |
87d4300a ML |
4832 | /* |
4833 | * Vblank time updates from the shadow to live plane control register | |
4834 | * are blocked if the memory self-refresh mode is active at that | |
4835 | * moment. So to make sure the plane gets truly disabled, disable | |
4836 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4837 | * will be checked/applied by the HW only at the next frame start | |
4838 | * event which is after the vblank start event, so we need to have a | |
4839 | * wait-for-vblank between disabling the plane and the pipe. | |
4840 | */ | |
4841 | if (HAS_GMCH_DISPLAY(dev)) | |
4842 | intel_set_memory_cxsr(dev_priv, false); | |
4843 | ||
4844 | mutex_lock(&dev->struct_mutex); | |
e35fef21 | 4845 | if (dev_priv->fbc.crtc == intel_crtc) |
7ff0ebcc | 4846 | intel_fbc_disable(dev); |
87d4300a | 4847 | mutex_unlock(&dev->struct_mutex); |
a5c4d7bc | 4848 | |
87d4300a ML |
4849 | /* |
4850 | * FIXME IPS should be fine as long as one plane is | |
4851 | * enabled, but in practice it seems to have problems | |
4852 | * when going from primary only to sprite only and vice | |
4853 | * versa. | |
4854 | */ | |
a5c4d7bc | 4855 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4856 | } |
4857 | ||
4858 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) | |
4859 | { | |
87d4300a ML |
4860 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
4861 | intel_enable_sprite_planes(crtc); | |
4862 | intel_crtc_update_cursor(crtc, true); | |
87d4300a ML |
4863 | |
4864 | intel_post_enable_primary(crtc); | |
4865 | } | |
4866 | ||
4867 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) | |
4868 | { | |
4869 | struct drm_device *dev = crtc->dev; | |
4870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4871 | struct intel_plane *intel_plane; | |
4872 | int pipe = intel_crtc->pipe; | |
4873 | ||
4874 | intel_crtc_wait_for_pending_flips(crtc); | |
4875 | ||
4876 | intel_pre_disable_primary(crtc); | |
a5c4d7bc | 4877 | |
7cac945f | 4878 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 ML |
4879 | for_each_intel_plane(dev, intel_plane) { |
4880 | if (intel_plane->pipe == pipe) { | |
4881 | struct drm_crtc *from = intel_plane->base.crtc; | |
4882 | ||
4883 | intel_plane->disable_plane(&intel_plane->base, | |
4884 | from ?: crtc, true); | |
4885 | } | |
4886 | } | |
f98551ae | 4887 | |
f99d7069 DV |
4888 | /* |
4889 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4890 | * to compute the mask of flip planes precisely. For the time being | |
4891 | * consider this a flip to a NULL plane. | |
4892 | */ | |
4893 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4894 | } |
4895 | ||
f67a559d JB |
4896 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4897 | { | |
4898 | struct drm_device *dev = crtc->dev; | |
4899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4900 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4901 | struct intel_encoder *encoder; |
f67a559d | 4902 | int pipe = intel_crtc->pipe; |
f67a559d | 4903 | |
83d65738 | 4904 | WARN_ON(!crtc->state->enable); |
08a48469 | 4905 | |
f67a559d JB |
4906 | if (intel_crtc->active) |
4907 | return; | |
4908 | ||
6e3c9717 | 4909 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4910 | intel_prepare_shared_dpll(intel_crtc); |
4911 | ||
6e3c9717 | 4912 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4913 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4914 | |
4915 | intel_set_pipe_timings(intel_crtc); | |
4916 | ||
6e3c9717 | 4917 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4918 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4919 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4920 | } |
4921 | ||
4922 | ironlake_set_pipeconf(crtc); | |
4923 | ||
f67a559d | 4924 | intel_crtc->active = true; |
8664281b | 4925 | |
a72e4c9f DV |
4926 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4927 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
8664281b | 4928 | |
f6736a1a | 4929 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4930 | if (encoder->pre_enable) |
4931 | encoder->pre_enable(encoder); | |
f67a559d | 4932 | |
6e3c9717 | 4933 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4934 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4935 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4936 | * enabling. */ | |
88cefb6c | 4937 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4938 | } else { |
4939 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4940 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4941 | } | |
f67a559d | 4942 | |
b074cec8 | 4943 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4944 | |
9c54c0dd JB |
4945 | /* |
4946 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4947 | * clocks enabled | |
4948 | */ | |
4949 | intel_crtc_load_lut(crtc); | |
4950 | ||
f37fcc2a | 4951 | intel_update_watermarks(crtc); |
e1fdc473 | 4952 | intel_enable_pipe(intel_crtc); |
f67a559d | 4953 | |
6e3c9717 | 4954 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4955 | ironlake_pch_enable(crtc); |
c98e9dcf | 4956 | |
f9b61ff6 DV |
4957 | assert_vblank_disabled(crtc); |
4958 | drm_crtc_vblank_on(crtc); | |
4959 | ||
fa5c73b1 DV |
4960 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4961 | encoder->enable(encoder); | |
61b77ddd DV |
4962 | |
4963 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4964 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6be4a607 JB |
4965 | } |
4966 | ||
42db64ef PZ |
4967 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4968 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4969 | { | |
f5adf94e | 4970 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4971 | } |
4972 | ||
e4916946 PZ |
4973 | /* |
4974 | * This implements the workaround described in the "notes" section of the mode | |
4975 | * set sequence documentation. When going from no pipes or single pipe to | |
4976 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4977 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4978 | */ | |
4979 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4980 | { | |
4981 | struct drm_device *dev = crtc->base.dev; | |
4982 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4983 | ||
4984 | /* We want to get the other_active_crtc only if there's only 1 other | |
4985 | * active crtc. */ | |
d3fcc808 | 4986 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4987 | if (!crtc_it->active || crtc_it == crtc) |
4988 | continue; | |
4989 | ||
4990 | if (other_active_crtc) | |
4991 | return; | |
4992 | ||
4993 | other_active_crtc = crtc_it; | |
4994 | } | |
4995 | if (!other_active_crtc) | |
4996 | return; | |
4997 | ||
4998 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4999 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
5000 | } | |
5001 | ||
4f771f10 PZ |
5002 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
5003 | { | |
5004 | struct drm_device *dev = crtc->dev; | |
5005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5006 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5007 | struct intel_encoder *encoder; | |
5008 | int pipe = intel_crtc->pipe; | |
4f771f10 | 5009 | |
83d65738 | 5010 | WARN_ON(!crtc->state->enable); |
4f771f10 PZ |
5011 | |
5012 | if (intel_crtc->active) | |
5013 | return; | |
5014 | ||
df8ad70c DV |
5015 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
5016 | intel_enable_shared_dpll(intel_crtc); | |
5017 | ||
6e3c9717 | 5018 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5019 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
5020 | |
5021 | intel_set_pipe_timings(intel_crtc); | |
5022 | ||
6e3c9717 ACO |
5023 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
5024 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
5025 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
5026 | } |
5027 | ||
6e3c9717 | 5028 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5029 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5030 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5031 | } |
5032 | ||
5033 | haswell_set_pipeconf(crtc); | |
5034 | ||
5035 | intel_set_pipe_csc(crtc); | |
5036 | ||
4f771f10 | 5037 | intel_crtc->active = true; |
8664281b | 5038 | |
a72e4c9f | 5039 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4f771f10 PZ |
5040 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5041 | if (encoder->pre_enable) | |
5042 | encoder->pre_enable(encoder); | |
5043 | ||
6e3c9717 | 5044 | if (intel_crtc->config->has_pch_encoder) { |
a72e4c9f DV |
5045 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5046 | true); | |
4fe9467d ID |
5047 | dev_priv->display.fdi_link_train(crtc); |
5048 | } | |
5049 | ||
1f544388 | 5050 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5051 | |
ff6d9f55 | 5052 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5053 | skylake_pfit_update(intel_crtc, 1); |
ff6d9f55 | 5054 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5055 | ironlake_pfit_enable(intel_crtc); |
ff6d9f55 JB |
5056 | else |
5057 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 PZ |
5058 | |
5059 | /* | |
5060 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5061 | * clocks enabled | |
5062 | */ | |
5063 | intel_crtc_load_lut(crtc); | |
5064 | ||
1f544388 | 5065 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 5066 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5067 | |
f37fcc2a | 5068 | intel_update_watermarks(crtc); |
e1fdc473 | 5069 | intel_enable_pipe(intel_crtc); |
42db64ef | 5070 | |
6e3c9717 | 5071 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5072 | lpt_pch_enable(crtc); |
4f771f10 | 5073 | |
6e3c9717 | 5074 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5075 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5076 | ||
f9b61ff6 DV |
5077 | assert_vblank_disabled(crtc); |
5078 | drm_crtc_vblank_on(crtc); | |
5079 | ||
8807e55b | 5080 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5081 | encoder->enable(encoder); |
8807e55b JN |
5082 | intel_opregion_notify_encoder(encoder, true); |
5083 | } | |
4f771f10 | 5084 | |
e4916946 PZ |
5085 | /* If we change the relative order between pipe/planes enabling, we need |
5086 | * to change the workaround. */ | |
5087 | haswell_mode_set_planes_workaround(intel_crtc); | |
4f771f10 PZ |
5088 | } |
5089 | ||
3f8dce3a DV |
5090 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
5091 | { | |
5092 | struct drm_device *dev = crtc->base.dev; | |
5093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5094 | int pipe = crtc->pipe; | |
5095 | ||
5096 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5097 | * it's in use. The hw state code will make sure we get this right. */ | |
6e3c9717 | 5098 | if (crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5099 | I915_WRITE(PF_CTL(pipe), 0); |
5100 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5101 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5102 | } | |
5103 | } | |
5104 | ||
6be4a607 JB |
5105 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5106 | { | |
5107 | struct drm_device *dev = crtc->dev; | |
5108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5109 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5110 | struct intel_encoder *encoder; |
6be4a607 | 5111 | int pipe = intel_crtc->pipe; |
5eddb70b | 5112 | u32 reg, temp; |
b52eb4dc | 5113 | |
f7abfe8b CW |
5114 | if (!intel_crtc->active) |
5115 | return; | |
5116 | ||
ea9d758d DV |
5117 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5118 | encoder->disable(encoder); | |
5119 | ||
f9b61ff6 DV |
5120 | drm_crtc_vblank_off(crtc); |
5121 | assert_vblank_disabled(crtc); | |
5122 | ||
6e3c9717 | 5123 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f | 5124 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
d925c59a | 5125 | |
575f7ab7 | 5126 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5127 | |
3f8dce3a | 5128 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 5129 | |
bf49ec8c DV |
5130 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5131 | if (encoder->post_disable) | |
5132 | encoder->post_disable(encoder); | |
2c07245f | 5133 | |
6e3c9717 | 5134 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5135 | ironlake_fdi_disable(crtc); |
913d8d11 | 5136 | |
d925c59a | 5137 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5138 | |
d925c59a DV |
5139 | if (HAS_PCH_CPT(dev)) { |
5140 | /* disable TRANS_DP_CTL */ | |
5141 | reg = TRANS_DP_CTL(pipe); | |
5142 | temp = I915_READ(reg); | |
5143 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5144 | TRANS_DP_PORT_SEL_MASK); | |
5145 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5146 | I915_WRITE(reg, temp); | |
5147 | ||
5148 | /* disable DPLL_SEL */ | |
5149 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5150 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5151 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5152 | } |
e3421a18 | 5153 | |
d925c59a | 5154 | /* disable PCH DPLL */ |
e72f9fbf | 5155 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 5156 | |
d925c59a DV |
5157 | ironlake_fdi_pll_disable(intel_crtc); |
5158 | } | |
6b383a7f | 5159 | |
f7abfe8b | 5160 | intel_crtc->active = false; |
46ba614c | 5161 | intel_update_watermarks(crtc); |
d1ebd816 BW |
5162 | |
5163 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5164 | intel_fbc_update(dev); |
d1ebd816 | 5165 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 5166 | } |
1b3c7a47 | 5167 | |
4f771f10 | 5168 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5169 | { |
4f771f10 PZ |
5170 | struct drm_device *dev = crtc->dev; |
5171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5172 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5173 | struct intel_encoder *encoder; |
6e3c9717 | 5174 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5175 | |
4f771f10 PZ |
5176 | if (!intel_crtc->active) |
5177 | return; | |
5178 | ||
8807e55b JN |
5179 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5180 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5181 | encoder->disable(encoder); |
8807e55b | 5182 | } |
4f771f10 | 5183 | |
f9b61ff6 DV |
5184 | drm_crtc_vblank_off(crtc); |
5185 | assert_vblank_disabled(crtc); | |
5186 | ||
6e3c9717 | 5187 | if (intel_crtc->config->has_pch_encoder) |
a72e4c9f DV |
5188 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5189 | false); | |
575f7ab7 | 5190 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5191 | |
6e3c9717 | 5192 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5193 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5194 | ||
ad80a810 | 5195 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5196 | |
ff6d9f55 | 5197 | if (INTEL_INFO(dev)->gen == 9) |
a1b2278e | 5198 | skylake_pfit_update(intel_crtc, 0); |
ff6d9f55 | 5199 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 5200 | ironlake_pfit_disable(intel_crtc); |
ff6d9f55 JB |
5201 | else |
5202 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
4f771f10 | 5203 | |
1f544388 | 5204 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5205 | |
6e3c9717 | 5206 | if (intel_crtc->config->has_pch_encoder) { |
ab4d966c | 5207 | lpt_disable_pch_transcoder(dev_priv); |
1ad960f2 | 5208 | intel_ddi_fdi_disable(crtc); |
83616634 | 5209 | } |
4f771f10 | 5210 | |
97b040aa ID |
5211 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5212 | if (encoder->post_disable) | |
5213 | encoder->post_disable(encoder); | |
5214 | ||
4f771f10 | 5215 | intel_crtc->active = false; |
46ba614c | 5216 | intel_update_watermarks(crtc); |
4f771f10 PZ |
5217 | |
5218 | mutex_lock(&dev->struct_mutex); | |
7ff0ebcc | 5219 | intel_fbc_update(dev); |
4f771f10 | 5220 | mutex_unlock(&dev->struct_mutex); |
df8ad70c DV |
5221 | |
5222 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
5223 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
5224 | } |
5225 | ||
ee7b9f93 JB |
5226 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
5227 | { | |
5228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 5229 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
5230 | } |
5231 | ||
6441ab5f | 5232 | |
2dd24552 JB |
5233 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5234 | { | |
5235 | struct drm_device *dev = crtc->base.dev; | |
5236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5237 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5238 | |
681a8504 | 5239 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5240 | return; |
5241 | ||
2dd24552 | 5242 | /* |
c0b03411 DV |
5243 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5244 | * according to register description and PRM. | |
2dd24552 | 5245 | */ |
c0b03411 DV |
5246 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5247 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5248 | |
b074cec8 JB |
5249 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5250 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5251 | |
5252 | /* Border color in case we don't scale up to the full screen. Black by | |
5253 | * default, change to something else for debugging. */ | |
5254 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5255 | } |
5256 | ||
d05410f9 DA |
5257 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5258 | { | |
5259 | switch (port) { | |
5260 | case PORT_A: | |
5261 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
5262 | case PORT_B: | |
5263 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
5264 | case PORT_C: | |
5265 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
5266 | case PORT_D: | |
5267 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
5268 | default: | |
5269 | WARN_ON_ONCE(1); | |
5270 | return POWER_DOMAIN_PORT_OTHER; | |
5271 | } | |
5272 | } | |
5273 | ||
77d22dca ID |
5274 | #define for_each_power_domain(domain, mask) \ |
5275 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
5276 | if ((1 << (domain)) & (mask)) | |
5277 | ||
319be8ae ID |
5278 | enum intel_display_power_domain |
5279 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5280 | { | |
5281 | struct drm_device *dev = intel_encoder->base.dev; | |
5282 | struct intel_digital_port *intel_dig_port; | |
5283 | ||
5284 | switch (intel_encoder->type) { | |
5285 | case INTEL_OUTPUT_UNKNOWN: | |
5286 | /* Only DDI platforms should ever use this output type */ | |
5287 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5288 | case INTEL_OUTPUT_DISPLAYPORT: | |
5289 | case INTEL_OUTPUT_HDMI: | |
5290 | case INTEL_OUTPUT_EDP: | |
5291 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5292 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5293 | case INTEL_OUTPUT_DP_MST: |
5294 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5295 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5296 | case INTEL_OUTPUT_ANALOG: |
5297 | return POWER_DOMAIN_PORT_CRT; | |
5298 | case INTEL_OUTPUT_DSI: | |
5299 | return POWER_DOMAIN_PORT_DSI; | |
5300 | default: | |
5301 | return POWER_DOMAIN_PORT_OTHER; | |
5302 | } | |
5303 | } | |
5304 | ||
5305 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 5306 | { |
319be8ae ID |
5307 | struct drm_device *dev = crtc->dev; |
5308 | struct intel_encoder *intel_encoder; | |
5309 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5310 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
5311 | unsigned long mask; |
5312 | enum transcoder transcoder; | |
5313 | ||
5314 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
5315 | ||
5316 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
5317 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5318 | if (intel_crtc->config->pch_pfit.enabled || |
5319 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5320 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5321 | ||
319be8ae ID |
5322 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5323 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5324 | ||
77d22dca ID |
5325 | return mask; |
5326 | } | |
5327 | ||
679dacd4 | 5328 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
77d22dca | 5329 | { |
679dacd4 | 5330 | struct drm_device *dev = state->dev; |
77d22dca ID |
5331 | struct drm_i915_private *dev_priv = dev->dev_private; |
5332 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
5333 | struct intel_crtc *crtc; | |
5334 | ||
5335 | /* | |
5336 | * First get all needed power domains, then put all unneeded, to avoid | |
5337 | * any unnecessary toggling of the power wells. | |
5338 | */ | |
d3fcc808 | 5339 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5340 | enum intel_display_power_domain domain; |
5341 | ||
83d65738 | 5342 | if (!crtc->base.state->enable) |
77d22dca ID |
5343 | continue; |
5344 | ||
319be8ae | 5345 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
5346 | |
5347 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
5348 | intel_display_power_get(dev_priv, domain); | |
5349 | } | |
5350 | ||
50f6e502 | 5351 | if (dev_priv->display.modeset_global_resources) |
679dacd4 | 5352 | dev_priv->display.modeset_global_resources(state); |
50f6e502 | 5353 | |
d3fcc808 | 5354 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
5355 | enum intel_display_power_domain domain; |
5356 | ||
5357 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
5358 | intel_display_power_put(dev_priv, domain); | |
5359 | ||
5360 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
5361 | } | |
5362 | ||
5363 | intel_display_set_init_power(dev_priv, false); | |
5364 | } | |
5365 | ||
f8437dd1 VK |
5366 | void broxton_set_cdclk(struct drm_device *dev, int frequency) |
5367 | { | |
5368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5369 | uint32_t divider; | |
5370 | uint32_t ratio; | |
5371 | uint32_t current_freq; | |
5372 | int ret; | |
5373 | ||
5374 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5375 | switch (frequency) { | |
5376 | case 144000: | |
5377 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5378 | ratio = BXT_DE_PLL_RATIO(60); | |
5379 | break; | |
5380 | case 288000: | |
5381 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5382 | ratio = BXT_DE_PLL_RATIO(60); | |
5383 | break; | |
5384 | case 384000: | |
5385 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5386 | ratio = BXT_DE_PLL_RATIO(60); | |
5387 | break; | |
5388 | case 576000: | |
5389 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5390 | ratio = BXT_DE_PLL_RATIO(60); | |
5391 | break; | |
5392 | case 624000: | |
5393 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5394 | ratio = BXT_DE_PLL_RATIO(65); | |
5395 | break; | |
5396 | case 19200: | |
5397 | /* | |
5398 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5399 | * to suppress GCC warning. | |
5400 | */ | |
5401 | ratio = 0; | |
5402 | divider = 0; | |
5403 | break; | |
5404 | default: | |
5405 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5406 | ||
5407 | return; | |
5408 | } | |
5409 | ||
5410 | mutex_lock(&dev_priv->rps.hw_lock); | |
5411 | /* Inform power controller of upcoming frequency change */ | |
5412 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5413 | 0x80000000); | |
5414 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5415 | ||
5416 | if (ret) { | |
5417 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5418 | ret, frequency); | |
5419 | return; | |
5420 | } | |
5421 | ||
5422 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5423 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5424 | current_freq = current_freq * 500 + 1000; | |
5425 | ||
5426 | /* | |
5427 | * DE PLL has to be disabled when | |
5428 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5429 | * - before setting to 624MHz (PLL needs toggling) | |
5430 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5431 | */ | |
5432 | if (frequency == 19200 || frequency == 624000 || | |
5433 | current_freq == 624000) { | |
5434 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5435 | /* Timeout 200us */ | |
5436 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5437 | 1)) | |
5438 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5439 | } | |
5440 | ||
5441 | if (frequency != 19200) { | |
5442 | uint32_t val; | |
5443 | ||
5444 | val = I915_READ(BXT_DE_PLL_CTL); | |
5445 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5446 | val |= ratio; | |
5447 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5448 | ||
5449 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5450 | /* Timeout 200us */ | |
5451 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5452 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5453 | ||
5454 | val = I915_READ(CDCLK_CTL); | |
5455 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5456 | val |= divider; | |
5457 | /* | |
5458 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5459 | * enable otherwise. | |
5460 | */ | |
5461 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5462 | if (frequency >= 500000) | |
5463 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5464 | ||
5465 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5466 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5467 | val |= (frequency - 1000) / 500; | |
5468 | I915_WRITE(CDCLK_CTL, val); | |
5469 | } | |
5470 | ||
5471 | mutex_lock(&dev_priv->rps.hw_lock); | |
5472 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5473 | DIV_ROUND_UP(frequency, 25000)); | |
5474 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5475 | ||
5476 | if (ret) { | |
5477 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5478 | ret, frequency); | |
5479 | return; | |
5480 | } | |
5481 | ||
5482 | dev_priv->cdclk_freq = frequency; | |
5483 | } | |
5484 | ||
5485 | void broxton_init_cdclk(struct drm_device *dev) | |
5486 | { | |
5487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5488 | uint32_t val; | |
5489 | ||
5490 | /* | |
5491 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5492 | * or else the reset will hang because there is no PCH to respond. | |
5493 | * Move the handshake programming to initialization sequence. | |
5494 | * Previously was left up to BIOS. | |
5495 | */ | |
5496 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5497 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5498 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5499 | ||
5500 | /* Enable PG1 for cdclk */ | |
5501 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5502 | ||
5503 | /* check if cd clock is enabled */ | |
5504 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5505 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5506 | return; | |
5507 | } | |
5508 | ||
5509 | /* | |
5510 | * FIXME: | |
5511 | * - The initial CDCLK needs to be read from VBT. | |
5512 | * Need to make this change after VBT has changes for BXT. | |
5513 | * - check if setting the max (or any) cdclk freq is really necessary | |
5514 | * here, it belongs to modeset time | |
5515 | */ | |
5516 | broxton_set_cdclk(dev, 624000); | |
5517 | ||
5518 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5519 | POSTING_READ(DBUF_CTL); |
5520 | ||
f8437dd1 VK |
5521 | udelay(10); |
5522 | ||
5523 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5524 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5525 | } | |
5526 | ||
5527 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5528 | { | |
5529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5530 | ||
5531 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5532 | POSTING_READ(DBUF_CTL); |
5533 | ||
f8437dd1 VK |
5534 | udelay(10); |
5535 | ||
5536 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5537 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5538 | ||
5539 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5540 | broxton_set_cdclk(dev, 19200); | |
5541 | ||
5542 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5543 | } | |
5544 | ||
dfcab17e | 5545 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 5546 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 5547 | { |
586f49dc | 5548 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 5549 | |
586f49dc JB |
5550 | /* Obtain SKU information */ |
5551 | mutex_lock(&dev_priv->dpio_lock); | |
5552 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
5553 | CCK_FUSE_HPLL_FREQ_MASK; | |
5554 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 5555 | |
dfcab17e | 5556 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
5557 | } |
5558 | ||
f8bf63fd VS |
5559 | static void vlv_update_cdclk(struct drm_device *dev) |
5560 | { | |
5561 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5562 | ||
164dfd28 | 5563 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); |
43dc52c3 | 5564 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", |
164dfd28 | 5565 | dev_priv->cdclk_freq); |
f8bf63fd VS |
5566 | |
5567 | /* | |
5568 | * Program the gmbus_freq based on the cdclk frequency. | |
5569 | * BSpec erroneously claims we should aim for 4MHz, but | |
5570 | * in fact 1MHz is the correct frequency. | |
5571 | */ | |
164dfd28 | 5572 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
f8bf63fd VS |
5573 | } |
5574 | ||
30a970c6 JB |
5575 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5576 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5577 | { | |
5578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5579 | u32 val, cmd; | |
5580 | ||
164dfd28 VK |
5581 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5582 | != dev_priv->cdclk_freq); | |
d60c4473 | 5583 | |
dfcab17e | 5584 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5585 | cmd = 2; |
dfcab17e | 5586 | else if (cdclk == 266667) |
30a970c6 JB |
5587 | cmd = 1; |
5588 | else | |
5589 | cmd = 0; | |
5590 | ||
5591 | mutex_lock(&dev_priv->rps.hw_lock); | |
5592 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5593 | val &= ~DSPFREQGUAR_MASK; | |
5594 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5595 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5596 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5597 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5598 | 50)) { | |
5599 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5600 | } | |
5601 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5602 | ||
dfcab17e | 5603 | if (cdclk == 400000) { |
6bcda4f0 | 5604 | u32 divider; |
30a970c6 | 5605 | |
6bcda4f0 | 5606 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 JB |
5607 | |
5608 | mutex_lock(&dev_priv->dpio_lock); | |
5609 | /* adjust cdclk divider */ | |
5610 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 5611 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
5612 | val |= divider; |
5613 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5614 | |
5615 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
5616 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5617 | 50)) | |
5618 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5619 | mutex_unlock(&dev_priv->dpio_lock); |
5620 | } | |
5621 | ||
5622 | mutex_lock(&dev_priv->dpio_lock); | |
5623 | /* adjust self-refresh exit latency value */ | |
5624 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5625 | val &= ~0x7f; | |
5626 | ||
5627 | /* | |
5628 | * For high bandwidth configs, we set a higher latency in the bunit | |
5629 | * so that the core display fetch happens in time to avoid underruns. | |
5630 | */ | |
dfcab17e | 5631 | if (cdclk == 400000) |
30a970c6 JB |
5632 | val |= 4500 / 250; /* 4.5 usec */ |
5633 | else | |
5634 | val |= 3000 / 250; /* 3.0 usec */ | |
5635 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
5636 | mutex_unlock(&dev_priv->dpio_lock); | |
5637 | ||
f8bf63fd | 5638 | vlv_update_cdclk(dev); |
30a970c6 JB |
5639 | } |
5640 | ||
383c5a6a VS |
5641 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5642 | { | |
5643 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5644 | u32 val, cmd; | |
5645 | ||
164dfd28 VK |
5646 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5647 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5648 | |
5649 | switch (cdclk) { | |
383c5a6a VS |
5650 | case 333333: |
5651 | case 320000: | |
383c5a6a | 5652 | case 266667: |
383c5a6a | 5653 | case 200000: |
383c5a6a VS |
5654 | break; |
5655 | default: | |
5f77eeb0 | 5656 | MISSING_CASE(cdclk); |
383c5a6a VS |
5657 | return; |
5658 | } | |
5659 | ||
9d0d3fda VS |
5660 | /* |
5661 | * Specs are full of misinformation, but testing on actual | |
5662 | * hardware has shown that we just need to write the desired | |
5663 | * CCK divider into the Punit register. | |
5664 | */ | |
5665 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5666 | ||
383c5a6a VS |
5667 | mutex_lock(&dev_priv->rps.hw_lock); |
5668 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5669 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5670 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5671 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5672 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5673 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5674 | 50)) { | |
5675 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5676 | } | |
5677 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5678 | ||
5679 | vlv_update_cdclk(dev); | |
5680 | } | |
5681 | ||
30a970c6 JB |
5682 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5683 | int max_pixclk) | |
5684 | { | |
6bcda4f0 | 5685 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5686 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5687 | |
30a970c6 JB |
5688 | /* |
5689 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5690 | * 200MHz | |
5691 | * 267MHz | |
29dc7ef3 | 5692 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5693 | * 400MHz (VLV only) |
5694 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5695 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5696 | * |
5697 | * We seem to get an unstable or solid color picture at 200MHz. | |
5698 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5699 | * are off. | |
30a970c6 | 5700 | */ |
6cca3195 VS |
5701 | if (!IS_CHERRYVIEW(dev_priv) && |
5702 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5703 | return 400000; |
6cca3195 | 5704 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5705 | return freq_320; |
e37c67a1 | 5706 | else if (max_pixclk > 0) |
dfcab17e | 5707 | return 266667; |
e37c67a1 VS |
5708 | else |
5709 | return 200000; | |
30a970c6 JB |
5710 | } |
5711 | ||
f8437dd1 VK |
5712 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
5713 | int max_pixclk) | |
5714 | { | |
5715 | /* | |
5716 | * FIXME: | |
5717 | * - remove the guardband, it's not needed on BXT | |
5718 | * - set 19.2MHz bypass frequency if there are no active pipes | |
5719 | */ | |
5720 | if (max_pixclk > 576000*9/10) | |
5721 | return 624000; | |
5722 | else if (max_pixclk > 384000*9/10) | |
5723 | return 576000; | |
5724 | else if (max_pixclk > 288000*9/10) | |
5725 | return 384000; | |
5726 | else if (max_pixclk > 144000*9/10) | |
5727 | return 288000; | |
5728 | else | |
5729 | return 144000; | |
5730 | } | |
5731 | ||
2f2d7aa1 | 5732 | /* compute the max pixel clock for new configuration */ |
304603f4 | 5733 | static int intel_mode_max_pixclk(struct drm_atomic_state *state) |
30a970c6 | 5734 | { |
304603f4 | 5735 | struct drm_device *dev = state->dev; |
30a970c6 | 5736 | struct intel_crtc *intel_crtc; |
304603f4 | 5737 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
5738 | int max_pixclk = 0; |
5739 | ||
d3fcc808 | 5740 | for_each_intel_crtc(dev, intel_crtc) { |
304603f4 ACO |
5741 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
5742 | if (IS_ERR(crtc_state)) | |
5743 | return PTR_ERR(crtc_state); | |
5744 | ||
5745 | if (!crtc_state->base.enable) | |
5746 | continue; | |
5747 | ||
5748 | max_pixclk = max(max_pixclk, | |
5749 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
5750 | } |
5751 | ||
5752 | return max_pixclk; | |
5753 | } | |
5754 | ||
304603f4 | 5755 | static int valleyview_modeset_global_pipes(struct drm_atomic_state *state, |
2f2d7aa1 | 5756 | unsigned *prepare_pipes) |
30a970c6 | 5757 | { |
304603f4 | 5758 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
30a970c6 | 5759 | struct intel_crtc *intel_crtc; |
304603f4 | 5760 | int max_pixclk = intel_mode_max_pixclk(state); |
f8437dd1 | 5761 | int cdclk; |
30a970c6 | 5762 | |
304603f4 ACO |
5763 | if (max_pixclk < 0) |
5764 | return max_pixclk; | |
30a970c6 | 5765 | |
f8437dd1 VK |
5766 | if (IS_VALLEYVIEW(dev_priv)) |
5767 | cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); | |
5768 | else | |
5769 | cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
5770 | ||
5771 | if (cdclk == dev_priv->cdclk_freq) | |
304603f4 | 5772 | return 0; |
30a970c6 | 5773 | |
2f2d7aa1 | 5774 | /* disable/enable all currently active pipes while we change cdclk */ |
304603f4 | 5775 | for_each_intel_crtc(state->dev, intel_crtc) |
83d65738 | 5776 | if (intel_crtc->base.state->enable) |
30a970c6 | 5777 | *prepare_pipes |= (1 << intel_crtc->pipe); |
304603f4 ACO |
5778 | |
5779 | return 0; | |
30a970c6 JB |
5780 | } |
5781 | ||
1e69cd74 VS |
5782 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5783 | { | |
5784 | unsigned int credits, default_credits; | |
5785 | ||
5786 | if (IS_CHERRYVIEW(dev_priv)) | |
5787 | default_credits = PFI_CREDIT(12); | |
5788 | else | |
5789 | default_credits = PFI_CREDIT(8); | |
5790 | ||
164dfd28 | 5791 | if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) { |
1e69cd74 VS |
5792 | /* CHV suggested value is 31 or 63 */ |
5793 | if (IS_CHERRYVIEW(dev_priv)) | |
5794 | credits = PFI_CREDIT_31; | |
5795 | else | |
5796 | credits = PFI_CREDIT(15); | |
5797 | } else { | |
5798 | credits = default_credits; | |
5799 | } | |
5800 | ||
5801 | /* | |
5802 | * WA - write default credits before re-programming | |
5803 | * FIXME: should we also set the resend bit here? | |
5804 | */ | |
5805 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5806 | default_credits); | |
5807 | ||
5808 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5809 | credits | PFI_CREDIT_RESEND); | |
5810 | ||
5811 | /* | |
5812 | * FIXME is this guaranteed to clear | |
5813 | * immediately or should we poll for it? | |
5814 | */ | |
5815 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
5816 | } | |
5817 | ||
679dacd4 | 5818 | static void valleyview_modeset_global_resources(struct drm_atomic_state *state) |
30a970c6 | 5819 | { |
679dacd4 | 5820 | struct drm_device *dev = state->dev; |
30a970c6 | 5821 | struct drm_i915_private *dev_priv = dev->dev_private; |
304603f4 ACO |
5822 | int max_pixclk = intel_mode_max_pixclk(state); |
5823 | int req_cdclk; | |
5824 | ||
5825 | /* The only reason this can fail is if we fail to add the crtc_state | |
5826 | * to the atomic state. But that can't happen since the call to | |
5827 | * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which | |
5828 | * can't have failed otherwise the mode set would be aborted) added all | |
5829 | * the states already. */ | |
5830 | if (WARN_ON(max_pixclk < 0)) | |
5831 | return; | |
30a970c6 | 5832 | |
304603f4 | 5833 | req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
30a970c6 | 5834 | |
164dfd28 | 5835 | if (req_cdclk != dev_priv->cdclk_freq) { |
738c05c0 ID |
5836 | /* |
5837 | * FIXME: We can end up here with all power domains off, yet | |
5838 | * with a CDCLK frequency other than the minimum. To account | |
5839 | * for this take the PIPE-A power domain, which covers the HW | |
5840 | * blocks needed for the following programming. This can be | |
5841 | * removed once it's guaranteed that we get here either with | |
5842 | * the minimum CDCLK set, or the required power domains | |
5843 | * enabled. | |
5844 | */ | |
5845 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
5846 | ||
383c5a6a VS |
5847 | if (IS_CHERRYVIEW(dev)) |
5848 | cherryview_set_cdclk(dev, req_cdclk); | |
5849 | else | |
5850 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 5851 | |
1e69cd74 VS |
5852 | vlv_program_pfi_credits(dev_priv); |
5853 | ||
738c05c0 | 5854 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
383c5a6a | 5855 | } |
30a970c6 JB |
5856 | } |
5857 | ||
89b667f8 JB |
5858 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
5859 | { | |
5860 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5861 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
5862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5863 | struct intel_encoder *encoder; | |
5864 | int pipe = intel_crtc->pipe; | |
23538ef1 | 5865 | bool is_dsi; |
89b667f8 | 5866 | |
83d65738 | 5867 | WARN_ON(!crtc->state->enable); |
89b667f8 JB |
5868 | |
5869 | if (intel_crtc->active) | |
5870 | return; | |
5871 | ||
409ee761 | 5872 | is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); |
8525a235 | 5873 | |
1ae0d137 VS |
5874 | if (!is_dsi) { |
5875 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5876 | chv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5877 | else |
6e3c9717 | 5878 | vlv_prepare_pll(intel_crtc, intel_crtc->config); |
1ae0d137 | 5879 | } |
5b18e57c | 5880 | |
6e3c9717 | 5881 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5882 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5883 | |
5884 | intel_set_pipe_timings(intel_crtc); | |
5885 | ||
c14b0485 VS |
5886 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
5887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5888 | ||
5889 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
5890 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
5891 | } | |
5892 | ||
5b18e57c DV |
5893 | i9xx_set_pipeconf(intel_crtc); |
5894 | ||
89b667f8 | 5895 | intel_crtc->active = true; |
89b667f8 | 5896 | |
a72e4c9f | 5897 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5898 | |
89b667f8 JB |
5899 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5900 | if (encoder->pre_pll_enable) | |
5901 | encoder->pre_pll_enable(encoder); | |
5902 | ||
9d556c99 CML |
5903 | if (!is_dsi) { |
5904 | if (IS_CHERRYVIEW(dev)) | |
6e3c9717 | 5905 | chv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5906 | else |
6e3c9717 | 5907 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
9d556c99 | 5908 | } |
89b667f8 JB |
5909 | |
5910 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
5911 | if (encoder->pre_enable) | |
5912 | encoder->pre_enable(encoder); | |
5913 | ||
2dd24552 JB |
5914 | i9xx_pfit_enable(intel_crtc); |
5915 | ||
63cbb074 VS |
5916 | intel_crtc_load_lut(crtc); |
5917 | ||
f37fcc2a | 5918 | intel_update_watermarks(crtc); |
e1fdc473 | 5919 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5920 | |
4b3a9526 VS |
5921 | assert_vblank_disabled(crtc); |
5922 | drm_crtc_vblank_on(crtc); | |
5923 | ||
f9b61ff6 DV |
5924 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5925 | encoder->enable(encoder); | |
89b667f8 JB |
5926 | } |
5927 | ||
f13c2ef3 DV |
5928 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
5929 | { | |
5930 | struct drm_device *dev = crtc->base.dev; | |
5931 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5932 | ||
6e3c9717 ACO |
5933 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5934 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
5935 | } |
5936 | ||
0b8765c6 | 5937 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
5938 | { |
5939 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 5940 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 5941 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 5942 | struct intel_encoder *encoder; |
79e53945 | 5943 | int pipe = intel_crtc->pipe; |
79e53945 | 5944 | |
83d65738 | 5945 | WARN_ON(!crtc->state->enable); |
08a48469 | 5946 | |
f7abfe8b CW |
5947 | if (intel_crtc->active) |
5948 | return; | |
5949 | ||
f13c2ef3 DV |
5950 | i9xx_set_pll_dividers(intel_crtc); |
5951 | ||
6e3c9717 | 5952 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5953 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
5954 | |
5955 | intel_set_pipe_timings(intel_crtc); | |
5956 | ||
5b18e57c DV |
5957 | i9xx_set_pipeconf(intel_crtc); |
5958 | ||
f7abfe8b | 5959 | intel_crtc->active = true; |
6b383a7f | 5960 | |
4a3436e8 | 5961 | if (!IS_GEN2(dev)) |
a72e4c9f | 5962 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 5963 | |
9d6d9f19 MK |
5964 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5965 | if (encoder->pre_enable) | |
5966 | encoder->pre_enable(encoder); | |
5967 | ||
f6736a1a DV |
5968 | i9xx_enable_pll(intel_crtc); |
5969 | ||
2dd24552 JB |
5970 | i9xx_pfit_enable(intel_crtc); |
5971 | ||
63cbb074 VS |
5972 | intel_crtc_load_lut(crtc); |
5973 | ||
f37fcc2a | 5974 | intel_update_watermarks(crtc); |
e1fdc473 | 5975 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 5976 | |
4b3a9526 VS |
5977 | assert_vblank_disabled(crtc); |
5978 | drm_crtc_vblank_on(crtc); | |
5979 | ||
f9b61ff6 DV |
5980 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5981 | encoder->enable(encoder); | |
0b8765c6 | 5982 | } |
79e53945 | 5983 | |
87476d63 DV |
5984 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5985 | { | |
5986 | struct drm_device *dev = crtc->base.dev; | |
5987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 5988 | |
6e3c9717 | 5989 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 5990 | return; |
87476d63 | 5991 | |
328d8e82 | 5992 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 5993 | |
328d8e82 DV |
5994 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
5995 | I915_READ(PFIT_CONTROL)); | |
5996 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
5997 | } |
5998 | ||
0b8765c6 JB |
5999 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6000 | { | |
6001 | struct drm_device *dev = crtc->dev; | |
6002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6003 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6004 | struct intel_encoder *encoder; |
0b8765c6 | 6005 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6006 | |
f7abfe8b CW |
6007 | if (!intel_crtc->active) |
6008 | return; | |
6009 | ||
6304cd91 VS |
6010 | /* |
6011 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6012 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6013 | * We also need to wait on all gmch platforms because of the |
6014 | * self-refresh mode constraint explained above. | |
6304cd91 | 6015 | */ |
564ed191 | 6016 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6017 | |
4b3a9526 VS |
6018 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6019 | encoder->disable(encoder); | |
6020 | ||
f9b61ff6 DV |
6021 | drm_crtc_vblank_off(crtc); |
6022 | assert_vblank_disabled(crtc); | |
6023 | ||
575f7ab7 | 6024 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6025 | |
87476d63 | 6026 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6027 | |
89b667f8 JB |
6028 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6029 | if (encoder->post_disable) | |
6030 | encoder->post_disable(encoder); | |
6031 | ||
409ee761 | 6032 | if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { |
076ed3b2 CML |
6033 | if (IS_CHERRYVIEW(dev)) |
6034 | chv_disable_pll(dev_priv, pipe); | |
6035 | else if (IS_VALLEYVIEW(dev)) | |
6036 | vlv_disable_pll(dev_priv, pipe); | |
6037 | else | |
1c4e0274 | 6038 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6039 | } |
0b8765c6 | 6040 | |
4a3436e8 | 6041 | if (!IS_GEN2(dev)) |
a72e4c9f | 6042 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
4a3436e8 | 6043 | |
f7abfe8b | 6044 | intel_crtc->active = false; |
46ba614c | 6045 | intel_update_watermarks(crtc); |
f37fcc2a | 6046 | |
efa9624e | 6047 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 6048 | intel_fbc_update(dev); |
efa9624e | 6049 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
6050 | } |
6051 | ||
ee7b9f93 JB |
6052 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
6053 | { | |
6054 | } | |
6055 | ||
b04c5bd6 BF |
6056 | /* Master function to enable/disable CRTC and corresponding power wells */ |
6057 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
6058 | { |
6059 | struct drm_device *dev = crtc->dev; | |
6060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 6061 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
6062 | enum intel_display_power_domain domain; |
6063 | unsigned long domains; | |
976f8a20 | 6064 | |
0e572fe7 DV |
6065 | if (enable) { |
6066 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
6067 | domains = get_crtc_power_domains(crtc); |
6068 | for_each_power_domain(domain, domains) | |
6069 | intel_display_power_get(dev_priv, domain); | |
6070 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
6071 | |
6072 | dev_priv->display.crtc_enable(crtc); | |
ce22dba9 | 6073 | intel_crtc_enable_planes(crtc); |
0e572fe7 DV |
6074 | } |
6075 | } else { | |
6076 | if (intel_crtc->active) { | |
ce22dba9 | 6077 | intel_crtc_disable_planes(crtc); |
0e572fe7 DV |
6078 | dev_priv->display.crtc_disable(crtc); |
6079 | ||
e1e9fb84 DV |
6080 | domains = intel_crtc->enabled_power_domains; |
6081 | for_each_power_domain(domain, domains) | |
6082 | intel_display_power_put(dev_priv, domain); | |
6083 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
6084 | } |
6085 | } | |
b04c5bd6 BF |
6086 | } |
6087 | ||
6088 | /** | |
6089 | * Sets the power management mode of the pipe and plane. | |
6090 | */ | |
6091 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
6092 | { | |
6093 | struct drm_device *dev = crtc->dev; | |
6094 | struct intel_encoder *intel_encoder; | |
6095 | bool enable = false; | |
6096 | ||
6097 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
6098 | enable |= intel_encoder->connectors_active; | |
6099 | ||
6100 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
6101 | } |
6102 | ||
cdd59983 CW |
6103 | static void intel_crtc_disable(struct drm_crtc *crtc) |
6104 | { | |
cdd59983 | 6105 | struct drm_device *dev = crtc->dev; |
976f8a20 | 6106 | struct drm_connector *connector; |
ee7b9f93 | 6107 | struct drm_i915_private *dev_priv = dev->dev_private; |
cdd59983 | 6108 | |
976f8a20 | 6109 | /* crtc should still be enabled when we disable it. */ |
83d65738 | 6110 | WARN_ON(!crtc->state->enable); |
976f8a20 | 6111 | |
ce22dba9 | 6112 | intel_crtc_disable_planes(crtc); |
976f8a20 | 6113 | dev_priv->display.crtc_disable(crtc); |
ee7b9f93 JB |
6114 | dev_priv->display.off(crtc); |
6115 | ||
70a101f8 | 6116 | drm_plane_helper_disable(crtc->primary); |
976f8a20 DV |
6117 | |
6118 | /* Update computed state. */ | |
6119 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
6120 | if (!connector->encoder || !connector->encoder->crtc) | |
6121 | continue; | |
6122 | ||
6123 | if (connector->encoder->crtc != crtc) | |
6124 | continue; | |
6125 | ||
6126 | connector->dpms = DRM_MODE_DPMS_OFF; | |
6127 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
6128 | } |
6129 | } | |
6130 | ||
ea5b213a | 6131 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6132 | { |
4ef69c7a | 6133 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6134 | |
ea5b213a CW |
6135 | drm_encoder_cleanup(encoder); |
6136 | kfree(intel_encoder); | |
7e7d76c3 JB |
6137 | } |
6138 | ||
9237329d | 6139 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
6140 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
6141 | * state of the entire output pipe. */ | |
9237329d | 6142 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 6143 | { |
5ab432ef DV |
6144 | if (mode == DRM_MODE_DPMS_ON) { |
6145 | encoder->connectors_active = true; | |
6146 | ||
b2cabb0e | 6147 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
6148 | } else { |
6149 | encoder->connectors_active = false; | |
6150 | ||
b2cabb0e | 6151 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 6152 | } |
79e53945 JB |
6153 | } |
6154 | ||
0a91ca29 DV |
6155 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6156 | * internal consistency). */ | |
b980514c | 6157 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6158 | { |
0a91ca29 DV |
6159 | if (connector->get_hw_state(connector)) { |
6160 | struct intel_encoder *encoder = connector->encoder; | |
6161 | struct drm_crtc *crtc; | |
6162 | bool encoder_enabled; | |
6163 | enum pipe pipe; | |
6164 | ||
6165 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6166 | connector->base.base.id, | |
c23cc417 | 6167 | connector->base.name); |
0a91ca29 | 6168 | |
0e32b39c DA |
6169 | /* there is no real hw state for MST connectors */ |
6170 | if (connector->mst_port) | |
6171 | return; | |
6172 | ||
e2c719b7 | 6173 | I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
0a91ca29 | 6174 | "wrong connector dpms state\n"); |
e2c719b7 | 6175 | I915_STATE_WARN(connector->base.encoder != &encoder->base, |
0a91ca29 | 6176 | "active connector not linked to encoder\n"); |
0a91ca29 | 6177 | |
36cd7444 | 6178 | if (encoder) { |
e2c719b7 | 6179 | I915_STATE_WARN(!encoder->connectors_active, |
36cd7444 DA |
6180 | "encoder->connectors_active not set\n"); |
6181 | ||
6182 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 RC |
6183 | I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n"); |
6184 | if (I915_STATE_WARN_ON(!encoder->base.crtc)) | |
36cd7444 | 6185 | return; |
0a91ca29 | 6186 | |
36cd7444 | 6187 | crtc = encoder->base.crtc; |
0a91ca29 | 6188 | |
83d65738 MR |
6189 | I915_STATE_WARN(!crtc->state->enable, |
6190 | "crtc not enabled\n"); | |
e2c719b7 RC |
6191 | I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); |
6192 | I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe, | |
36cd7444 DA |
6193 | "encoder active on the wrong pipe\n"); |
6194 | } | |
0a91ca29 | 6195 | } |
79e53945 JB |
6196 | } |
6197 | ||
08d9bc92 ACO |
6198 | int intel_connector_init(struct intel_connector *connector) |
6199 | { | |
6200 | struct drm_connector_state *connector_state; | |
6201 | ||
6202 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6203 | if (!connector_state) | |
6204 | return -ENOMEM; | |
6205 | ||
6206 | connector->base.state = connector_state; | |
6207 | return 0; | |
6208 | } | |
6209 | ||
6210 | struct intel_connector *intel_connector_alloc(void) | |
6211 | { | |
6212 | struct intel_connector *connector; | |
6213 | ||
6214 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6215 | if (!connector) | |
6216 | return NULL; | |
6217 | ||
6218 | if (intel_connector_init(connector) < 0) { | |
6219 | kfree(connector); | |
6220 | return NULL; | |
6221 | } | |
6222 | ||
6223 | return connector; | |
6224 | } | |
6225 | ||
5ab432ef DV |
6226 | /* Even simpler default implementation, if there's really no special case to |
6227 | * consider. */ | |
6228 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 6229 | { |
5ab432ef DV |
6230 | /* All the simple cases only support two dpms states. */ |
6231 | if (mode != DRM_MODE_DPMS_ON) | |
6232 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 6233 | |
5ab432ef DV |
6234 | if (mode == connector->dpms) |
6235 | return; | |
6236 | ||
6237 | connector->dpms = mode; | |
6238 | ||
6239 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
6240 | if (connector->encoder) |
6241 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 6242 | |
b980514c | 6243 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
6244 | } |
6245 | ||
f0947c37 DV |
6246 | /* Simple connector->get_hw_state implementation for encoders that support only |
6247 | * one connector and no cloning and hence the encoder state determines the state | |
6248 | * of the connector. */ | |
6249 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6250 | { |
24929352 | 6251 | enum pipe pipe = 0; |
f0947c37 | 6252 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6253 | |
f0947c37 | 6254 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6255 | } |
6256 | ||
6d293983 | 6257 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6258 | { |
6d293983 ACO |
6259 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6260 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6261 | |
6262 | return 0; | |
6263 | } | |
6264 | ||
6d293983 | 6265 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6266 | struct intel_crtc_state *pipe_config) |
1857e1da | 6267 | { |
6d293983 ACO |
6268 | struct drm_atomic_state *state = pipe_config->base.state; |
6269 | struct intel_crtc *other_crtc; | |
6270 | struct intel_crtc_state *other_crtc_state; | |
6271 | ||
1857e1da DV |
6272 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6273 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6274 | if (pipe_config->fdi_lanes > 4) { | |
6275 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6276 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6277 | return -EINVAL; |
1857e1da DV |
6278 | } |
6279 | ||
bafb6553 | 6280 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6281 | if (pipe_config->fdi_lanes > 2) { |
6282 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6283 | pipe_config->fdi_lanes); | |
6d293983 | 6284 | return -EINVAL; |
1857e1da | 6285 | } else { |
6d293983 | 6286 | return 0; |
1857e1da DV |
6287 | } |
6288 | } | |
6289 | ||
6290 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6291 | return 0; |
1857e1da DV |
6292 | |
6293 | /* Ivybridge 3 pipe is really complicated */ | |
6294 | switch (pipe) { | |
6295 | case PIPE_A: | |
6d293983 | 6296 | return 0; |
1857e1da | 6297 | case PIPE_B: |
6d293983 ACO |
6298 | if (pipe_config->fdi_lanes <= 2) |
6299 | return 0; | |
6300 | ||
6301 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6302 | other_crtc_state = | |
6303 | intel_atomic_get_crtc_state(state, other_crtc); | |
6304 | if (IS_ERR(other_crtc_state)) | |
6305 | return PTR_ERR(other_crtc_state); | |
6306 | ||
6307 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6308 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6309 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6310 | return -EINVAL; |
1857e1da | 6311 | } |
6d293983 | 6312 | return 0; |
1857e1da | 6313 | case PIPE_C: |
251cc67c VS |
6314 | if (pipe_config->fdi_lanes > 2) { |
6315 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6316 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6317 | return -EINVAL; |
251cc67c | 6318 | } |
6d293983 ACO |
6319 | |
6320 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6321 | other_crtc_state = | |
6322 | intel_atomic_get_crtc_state(state, other_crtc); | |
6323 | if (IS_ERR(other_crtc_state)) | |
6324 | return PTR_ERR(other_crtc_state); | |
6325 | ||
6326 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6327 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6328 | return -EINVAL; |
1857e1da | 6329 | } |
6d293983 | 6330 | return 0; |
1857e1da DV |
6331 | default: |
6332 | BUG(); | |
6333 | } | |
6334 | } | |
6335 | ||
e29c22c0 DV |
6336 | #define RETRY 1 |
6337 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6338 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6339 | { |
1857e1da | 6340 | struct drm_device *dev = intel_crtc->base.dev; |
2d112de7 | 6341 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6342 | int lane, link_bw, fdi_dotclock, ret; |
6343 | bool needs_recompute = false; | |
877d48d5 | 6344 | |
e29c22c0 | 6345 | retry: |
877d48d5 DV |
6346 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6347 | * each output octet as 10 bits. The actual frequency | |
6348 | * is stored as a divider into a 100MHz clock, and the | |
6349 | * mode pixel clock is stored in units of 1KHz. | |
6350 | * Hence the bw of each lane in terms of the mode signal | |
6351 | * is: | |
6352 | */ | |
6353 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6354 | ||
241bfc38 | 6355 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6356 | |
2bd89a07 | 6357 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6358 | pipe_config->pipe_bpp); |
6359 | ||
6360 | pipe_config->fdi_lanes = lane; | |
6361 | ||
2bd89a07 | 6362 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6363 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6364 | |
6d293983 ACO |
6365 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6366 | intel_crtc->pipe, pipe_config); | |
6367 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6368 | pipe_config->pipe_bpp -= 2*3; |
6369 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6370 | pipe_config->pipe_bpp); | |
6371 | needs_recompute = true; | |
6372 | pipe_config->bw_constrained = true; | |
6373 | ||
6374 | goto retry; | |
6375 | } | |
6376 | ||
6377 | if (needs_recompute) | |
6378 | return RETRY; | |
6379 | ||
6d293983 | 6380 | return ret; |
877d48d5 DV |
6381 | } |
6382 | ||
42db64ef | 6383 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6384 | struct intel_crtc_state *pipe_config) |
42db64ef | 6385 | { |
d330a953 | 6386 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 6387 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 6388 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
6389 | } |
6390 | ||
a43f6e0f | 6391 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6392 | struct intel_crtc_state *pipe_config) |
79e53945 | 6393 | { |
a43f6e0f | 6394 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6395 | struct drm_i915_private *dev_priv = dev->dev_private; |
2d112de7 | 6396 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d03c93d4 | 6397 | int ret; |
89749350 | 6398 | |
ad3a4479 | 6399 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6400 | if (INTEL_INFO(dev)->gen < 4) { |
cf532bb2 VS |
6401 | int clock_limit = |
6402 | dev_priv->display.get_display_clock_speed(dev); | |
6403 | ||
6404 | /* | |
6405 | * Enable pixel doubling when the dot clock | |
6406 | * is > 90% of the (display) core speed. | |
6407 | * | |
b397c96b VS |
6408 | * GDG double wide on either pipe, |
6409 | * otherwise pipe A only. | |
cf532bb2 | 6410 | */ |
b397c96b | 6411 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 6412 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 6413 | clock_limit *= 2; |
cf532bb2 | 6414 | pipe_config->double_wide = true; |
ad3a4479 VS |
6415 | } |
6416 | ||
241bfc38 | 6417 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 6418 | return -EINVAL; |
2c07245f | 6419 | } |
89749350 | 6420 | |
1d1d0e27 VS |
6421 | /* |
6422 | * Pipe horizontal size must be even in: | |
6423 | * - DVO ganged mode | |
6424 | * - LVDS dual channel mode | |
6425 | * - Double wide pipe | |
6426 | */ | |
a93e255f | 6427 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6428 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6429 | pipe_config->pipe_src_w &= ~1; | |
6430 | ||
8693a824 DL |
6431 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6432 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6433 | */ |
6434 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
6435 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 6436 | return -EINVAL; |
44f46b42 | 6437 | |
f5adf94e | 6438 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6439 | hsw_compute_ips_config(crtc, pipe_config); |
6440 | ||
877d48d5 | 6441 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6442 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6443 | |
d03c93d4 CK |
6444 | /* FIXME: remove below call once atomic mode set is place and all crtc |
6445 | * related checks called from atomic_crtc_check function */ | |
6446 | ret = 0; | |
6447 | DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n", | |
6448 | crtc, pipe_config->base.state); | |
6449 | ret = intel_atomic_setup_scalers(dev, crtc, pipe_config); | |
6450 | ||
6451 | return ret; | |
79e53945 JB |
6452 | } |
6453 | ||
1652d19e VS |
6454 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6455 | { | |
6456 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6457 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6458 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6459 | uint32_t linkrate; | |
6460 | ||
6461 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) { | |
6462 | WARN(1, "LCPLL1 not enabled\n"); | |
6463 | return 24000; /* 24MHz is the cd freq with NSSC ref */ | |
6464 | } | |
6465 | ||
6466 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6467 | return 540000; | |
6468 | ||
6469 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6470 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6471 | |
71cd8423 DL |
6472 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6473 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6474 | /* vco 8640 */ |
6475 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6476 | case CDCLK_FREQ_450_432: | |
6477 | return 432000; | |
6478 | case CDCLK_FREQ_337_308: | |
6479 | return 308570; | |
6480 | case CDCLK_FREQ_675_617: | |
6481 | return 617140; | |
6482 | default: | |
6483 | WARN(1, "Unknown cd freq selection\n"); | |
6484 | } | |
6485 | } else { | |
6486 | /* vco 8100 */ | |
6487 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6488 | case CDCLK_FREQ_450_432: | |
6489 | return 450000; | |
6490 | case CDCLK_FREQ_337_308: | |
6491 | return 337500; | |
6492 | case CDCLK_FREQ_675_617: | |
6493 | return 675000; | |
6494 | default: | |
6495 | WARN(1, "Unknown cd freq selection\n"); | |
6496 | } | |
6497 | } | |
6498 | ||
6499 | /* error case, do as if DPLL0 isn't enabled */ | |
6500 | return 24000; | |
6501 | } | |
6502 | ||
6503 | static int broadwell_get_display_clock_speed(struct drm_device *dev) | |
6504 | { | |
6505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6506 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6507 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6508 | ||
6509 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6510 | return 800000; | |
6511 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6512 | return 450000; | |
6513 | else if (freq == LCPLL_CLK_FREQ_450) | |
6514 | return 450000; | |
6515 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6516 | return 540000; | |
6517 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6518 | return 337500; | |
6519 | else | |
6520 | return 675000; | |
6521 | } | |
6522 | ||
6523 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6524 | { | |
6525 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6526 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6527 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6528 | ||
6529 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6530 | return 800000; | |
6531 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6532 | return 450000; | |
6533 | else if (freq == LCPLL_CLK_FREQ_450) | |
6534 | return 450000; | |
6535 | else if (IS_HSW_ULT(dev)) | |
6536 | return 337500; | |
6537 | else | |
6538 | return 540000; | |
79e53945 JB |
6539 | } |
6540 | ||
25eb05fc JB |
6541 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6542 | { | |
d197b7d3 | 6543 | struct drm_i915_private *dev_priv = dev->dev_private; |
d197b7d3 VS |
6544 | u32 val; |
6545 | int divider; | |
6546 | ||
6bcda4f0 VS |
6547 | if (dev_priv->hpll_freq == 0) |
6548 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
6549 | ||
d197b7d3 VS |
6550 | mutex_lock(&dev_priv->dpio_lock); |
6551 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
6552 | mutex_unlock(&dev_priv->dpio_lock); | |
6553 | ||
6554 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
6555 | ||
7d007f40 VS |
6556 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
6557 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
6558 | "cdclk change in progress\n"); | |
6559 | ||
6bcda4f0 | 6560 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); |
25eb05fc JB |
6561 | } |
6562 | ||
b37a6434 VS |
6563 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6564 | { | |
6565 | return 450000; | |
6566 | } | |
6567 | ||
e70236a8 JB |
6568 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6569 | { | |
6570 | return 400000; | |
6571 | } | |
79e53945 | 6572 | |
e70236a8 | 6573 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6574 | { |
e907f170 | 6575 | return 333333; |
e70236a8 | 6576 | } |
79e53945 | 6577 | |
e70236a8 JB |
6578 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6579 | { | |
6580 | return 200000; | |
6581 | } | |
79e53945 | 6582 | |
257a7ffc DV |
6583 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6584 | { | |
6585 | u16 gcfgc = 0; | |
6586 | ||
6587 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6588 | ||
6589 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6590 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6591 | return 266667; |
257a7ffc | 6592 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6593 | return 333333; |
257a7ffc | 6594 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6595 | return 444444; |
257a7ffc DV |
6596 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6597 | return 200000; | |
6598 | default: | |
6599 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6600 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6601 | return 133333; |
257a7ffc | 6602 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6603 | return 166667; |
257a7ffc DV |
6604 | } |
6605 | } | |
6606 | ||
e70236a8 JB |
6607 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6608 | { | |
6609 | u16 gcfgc = 0; | |
79e53945 | 6610 | |
e70236a8 JB |
6611 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6612 | ||
6613 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6614 | return 133333; |
e70236a8 JB |
6615 | else { |
6616 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6617 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6618 | return 333333; |
e70236a8 JB |
6619 | default: |
6620 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6621 | return 190000; | |
79e53945 | 6622 | } |
e70236a8 JB |
6623 | } |
6624 | } | |
6625 | ||
6626 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6627 | { | |
e907f170 | 6628 | return 266667; |
e70236a8 JB |
6629 | } |
6630 | ||
6631 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
6632 | { | |
6633 | u16 hpllcc = 0; | |
6634 | /* Assume that the hardware is in the high speed state. This | |
6635 | * should be the default. | |
6636 | */ | |
6637 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6638 | case GC_CLOCK_133_200: | |
6639 | case GC_CLOCK_100_200: | |
6640 | return 200000; | |
6641 | case GC_CLOCK_166_250: | |
6642 | return 250000; | |
6643 | case GC_CLOCK_100_133: | |
e907f170 | 6644 | return 133333; |
e70236a8 | 6645 | } |
79e53945 | 6646 | |
e70236a8 JB |
6647 | /* Shouldn't happen */ |
6648 | return 0; | |
6649 | } | |
79e53945 | 6650 | |
e70236a8 JB |
6651 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6652 | { | |
e907f170 | 6653 | return 133333; |
79e53945 JB |
6654 | } |
6655 | ||
2c07245f | 6656 | static void |
a65851af | 6657 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6658 | { |
a65851af VS |
6659 | while (*num > DATA_LINK_M_N_MASK || |
6660 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6661 | *num >>= 1; |
6662 | *den >>= 1; | |
6663 | } | |
6664 | } | |
6665 | ||
a65851af VS |
6666 | static void compute_m_n(unsigned int m, unsigned int n, |
6667 | uint32_t *ret_m, uint32_t *ret_n) | |
6668 | { | |
6669 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6670 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6671 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6672 | } | |
6673 | ||
e69d0bc1 DV |
6674 | void |
6675 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6676 | int pixel_clock, int link_clock, | |
6677 | struct intel_link_m_n *m_n) | |
2c07245f | 6678 | { |
e69d0bc1 | 6679 | m_n->tu = 64; |
a65851af VS |
6680 | |
6681 | compute_m_n(bits_per_pixel * pixel_clock, | |
6682 | link_clock * nlanes * 8, | |
6683 | &m_n->gmch_m, &m_n->gmch_n); | |
6684 | ||
6685 | compute_m_n(pixel_clock, link_clock, | |
6686 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6687 | } |
6688 | ||
a7615030 CW |
6689 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6690 | { | |
d330a953 JN |
6691 | if (i915.panel_use_ssc >= 0) |
6692 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6693 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6694 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6695 | } |
6696 | ||
a93e255f ACO |
6697 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
6698 | int num_connectors) | |
c65d77d8 | 6699 | { |
a93e255f | 6700 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
6701 | struct drm_i915_private *dev_priv = dev->dev_private; |
6702 | int refclk; | |
6703 | ||
a93e255f ACO |
6704 | WARN_ON(!crtc_state->base.state); |
6705 | ||
5ab7b0b7 | 6706 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 6707 | refclk = 100000; |
a93e255f | 6708 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 6709 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
6710 | refclk = dev_priv->vbt.lvds_ssc_freq; |
6711 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
6712 | } else if (!IS_GEN2(dev)) { |
6713 | refclk = 96000; | |
6714 | } else { | |
6715 | refclk = 48000; | |
6716 | } | |
6717 | ||
6718 | return refclk; | |
6719 | } | |
6720 | ||
7429e9d4 | 6721 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6722 | { |
7df00d7a | 6723 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6724 | } |
f47709a9 | 6725 | |
7429e9d4 DV |
6726 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6727 | { | |
6728 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6729 | } |
6730 | ||
f47709a9 | 6731 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6732 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
6733 | intel_clock_t *reduced_clock) |
6734 | { | |
f47709a9 | 6735 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
6736 | u32 fp, fp2 = 0; |
6737 | ||
6738 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 6739 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6740 | if (reduced_clock) |
7429e9d4 | 6741 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6742 | } else { |
190f68c5 | 6743 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6744 | if (reduced_clock) |
7429e9d4 | 6745 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6746 | } |
6747 | ||
190f68c5 | 6748 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6749 | |
f47709a9 | 6750 | crtc->lowfreq_avail = false; |
a93e255f | 6751 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6752 | reduced_clock) { |
190f68c5 | 6753 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6754 | crtc->lowfreq_avail = true; |
a7516a05 | 6755 | } else { |
190f68c5 | 6756 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6757 | } |
6758 | } | |
6759 | ||
5e69f97f CML |
6760 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6761 | pipe) | |
89b667f8 JB |
6762 | { |
6763 | u32 reg_val; | |
6764 | ||
6765 | /* | |
6766 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6767 | * and set it to a reasonable value instead. | |
6768 | */ | |
ab3c759a | 6769 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6770 | reg_val &= 0xffffff00; |
6771 | reg_val |= 0x00000030; | |
ab3c759a | 6772 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6773 | |
ab3c759a | 6774 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6775 | reg_val &= 0x8cffffff; |
6776 | reg_val = 0x8c000000; | |
ab3c759a | 6777 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6778 | |
ab3c759a | 6779 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6780 | reg_val &= 0xffffff00; |
ab3c759a | 6781 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6782 | |
ab3c759a | 6783 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6784 | reg_val &= 0x00ffffff; |
6785 | reg_val |= 0xb0000000; | |
ab3c759a | 6786 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6787 | } |
6788 | ||
b551842d DV |
6789 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6790 | struct intel_link_m_n *m_n) | |
6791 | { | |
6792 | struct drm_device *dev = crtc->base.dev; | |
6793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6794 | int pipe = crtc->pipe; | |
6795 | ||
e3b95f1e DV |
6796 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6797 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6798 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6799 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6800 | } |
6801 | ||
6802 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6803 | struct intel_link_m_n *m_n, |
6804 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
6805 | { |
6806 | struct drm_device *dev = crtc->base.dev; | |
6807 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6808 | int pipe = crtc->pipe; | |
6e3c9717 | 6809 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
6810 | |
6811 | if (INTEL_INFO(dev)->gen >= 5) { | |
6812 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
6813 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6814 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6815 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6816 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6817 | * for gen < 8) and if DRRS is supported (to make sure the | |
6818 | * registers are not unnecessarily accessed). | |
6819 | */ | |
44395bfe | 6820 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 6821 | crtc->config->has_drrs) { |
f769cd24 VK |
6822 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6823 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6824 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6825 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6826 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6827 | } | |
b551842d | 6828 | } else { |
e3b95f1e DV |
6829 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6830 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6831 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6832 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6833 | } |
6834 | } | |
6835 | ||
fe3cd48d | 6836 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6837 | { |
fe3cd48d R |
6838 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6839 | ||
6840 | if (m_n == M1_N1) { | |
6841 | dp_m_n = &crtc->config->dp_m_n; | |
6842 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6843 | } else if (m_n == M2_N2) { | |
6844 | ||
6845 | /* | |
6846 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6847 | * needs to be programmed into M1_N1. | |
6848 | */ | |
6849 | dp_m_n = &crtc->config->dp_m2_n2; | |
6850 | } else { | |
6851 | DRM_ERROR("Unsupported divider value\n"); | |
6852 | return; | |
6853 | } | |
6854 | ||
6e3c9717 ACO |
6855 | if (crtc->config->has_pch_encoder) |
6856 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6857 | else |
fe3cd48d | 6858 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6859 | } |
6860 | ||
d288f65f | 6861 | static void vlv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6862 | struct intel_crtc_state *pipe_config) |
bdd4b6a6 DV |
6863 | { |
6864 | u32 dpll, dpll_md; | |
6865 | ||
6866 | /* | |
6867 | * Enable DPIO clock input. We should never disable the reference | |
6868 | * clock for pipe B, since VGA hotplug / manual detection depends | |
6869 | * on it. | |
6870 | */ | |
6871 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
6872 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
6873 | /* We should never disable this, set it here for state tracking */ | |
6874 | if (crtc->pipe == PIPE_B) | |
6875 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6876 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 6877 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 6878 | |
d288f65f | 6879 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 6880 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 6881 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
6882 | } |
6883 | ||
d288f65f | 6884 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6885 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6886 | { |
f47709a9 | 6887 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 6888 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 6889 | int pipe = crtc->pipe; |
bdd4b6a6 | 6890 | u32 mdiv; |
a0c4da24 | 6891 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6892 | u32 coreclk, reg_val; |
a0c4da24 | 6893 | |
09153000 DV |
6894 | mutex_lock(&dev_priv->dpio_lock); |
6895 | ||
d288f65f VS |
6896 | bestn = pipe_config->dpll.n; |
6897 | bestm1 = pipe_config->dpll.m1; | |
6898 | bestm2 = pipe_config->dpll.m2; | |
6899 | bestp1 = pipe_config->dpll.p1; | |
6900 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6901 | |
89b667f8 JB |
6902 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6903 | ||
6904 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6905 | if (pipe == PIPE_B) |
5e69f97f | 6906 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6907 | |
6908 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6909 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6910 | |
6911 | /* Disable target IRef on PLL */ | |
ab3c759a | 6912 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6913 | reg_val &= 0x00ffffff; |
ab3c759a | 6914 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6915 | |
6916 | /* Disable fast lock */ | |
ab3c759a | 6917 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6918 | |
6919 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6920 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6921 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6922 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6923 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6924 | |
6925 | /* | |
6926 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6927 | * but we don't support that). | |
6928 | * Note: don't use the DAC post divider as it seems unstable. | |
6929 | */ | |
6930 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6931 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6932 | |
a0c4da24 | 6933 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6934 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6935 | |
89b667f8 | 6936 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6937 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
6938 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
6939 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6940 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6941 | 0x009f0003); |
89b667f8 | 6942 | else |
ab3c759a | 6943 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6944 | 0x00d0000f); |
6945 | ||
681a8504 | 6946 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 6947 | /* Use SSC source */ |
bdd4b6a6 | 6948 | if (pipe == PIPE_A) |
ab3c759a | 6949 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6950 | 0x0df40000); |
6951 | else | |
ab3c759a | 6952 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6953 | 0x0df70000); |
6954 | } else { /* HDMI or VGA */ | |
6955 | /* Use bend source */ | |
bdd4b6a6 | 6956 | if (pipe == PIPE_A) |
ab3c759a | 6957 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6958 | 0x0df70000); |
6959 | else | |
ab3c759a | 6960 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6961 | 0x0df40000); |
6962 | } | |
a0c4da24 | 6963 | |
ab3c759a | 6964 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6965 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
6966 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
6967 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 6968 | coreclk |= 0x01000000; |
ab3c759a | 6969 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6970 | |
ab3c759a | 6971 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 6972 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
6973 | } |
6974 | ||
d288f65f | 6975 | static void chv_update_pll(struct intel_crtc *crtc, |
5cec258b | 6976 | struct intel_crtc_state *pipe_config) |
1ae0d137 | 6977 | { |
d288f65f | 6978 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | |
1ae0d137 VS |
6979 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | |
6980 | DPLL_VCO_ENABLE; | |
6981 | if (crtc->pipe != PIPE_A) | |
d288f65f | 6982 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 6983 | |
d288f65f VS |
6984 | pipe_config->dpll_hw_state.dpll_md = |
6985 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
6986 | } |
6987 | ||
d288f65f | 6988 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6989 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6990 | { |
6991 | struct drm_device *dev = crtc->base.dev; | |
6992 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6993 | int pipe = crtc->pipe; | |
6994 | int dpll_reg = DPLL(crtc->pipe); | |
6995 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9cbe40c1 | 6996 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6997 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6998 | u32 dpio_val; |
9cbe40c1 | 6999 | int vco; |
9d556c99 | 7000 | |
d288f65f VS |
7001 | bestn = pipe_config->dpll.n; |
7002 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7003 | bestm1 = pipe_config->dpll.m1; | |
7004 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7005 | bestp1 = pipe_config->dpll.p1; | |
7006 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7007 | vco = pipe_config->dpll.vco; |
a945ce7e | 7008 | dpio_val = 0; |
9cbe40c1 | 7009 | loopfilter = 0; |
9d556c99 CML |
7010 | |
7011 | /* | |
7012 | * Enable Refclk and SSC | |
7013 | */ | |
a11b0703 | 7014 | I915_WRITE(dpll_reg, |
d288f65f | 7015 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 VS |
7016 | |
7017 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 7018 | |
9d556c99 CML |
7019 | /* p1 and p2 divider */ |
7020 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7021 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7022 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7023 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7024 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7025 | ||
7026 | /* Feedback post-divider - m2 */ | |
7027 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7028 | ||
7029 | /* Feedback refclk divider - n and m1 */ | |
7030 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7031 | DPIO_CHV_M1_DIV_BY_2 | | |
7032 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7033 | ||
7034 | /* M2 fraction division */ | |
a945ce7e VP |
7035 | if (bestm2_frac) |
7036 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
9d556c99 CML |
7037 | |
7038 | /* M2 fraction division enable */ | |
a945ce7e VP |
7039 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7040 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7041 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7042 | if (bestm2_frac) | |
7043 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7044 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7045 | |
de3a0fde VP |
7046 | /* Program digital lock detect threshold */ |
7047 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7048 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7049 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7050 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7051 | if (!bestm2_frac) | |
7052 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7053 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7054 | ||
9d556c99 | 7055 | /* Loop filter */ |
9cbe40c1 VP |
7056 | if (vco == 5400000) { |
7057 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7058 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7059 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7060 | tribuf_calcntr = 0x9; | |
7061 | } else if (vco <= 6200000) { | |
7062 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7063 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7064 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7065 | tribuf_calcntr = 0x9; | |
7066 | } else if (vco <= 6480000) { | |
7067 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7068 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7069 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7070 | tribuf_calcntr = 0x8; | |
7071 | } else { | |
7072 | /* Not supported. Apply the same limits as in the max case */ | |
7073 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7074 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7075 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7076 | tribuf_calcntr = 0; | |
7077 | } | |
9d556c99 CML |
7078 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7079 | ||
968040b2 | 7080 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7081 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7082 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7083 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7084 | ||
9d556c99 CML |
7085 | /* AFC Recal */ |
7086 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7087 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7088 | DPIO_AFC_RECAL); | |
7089 | ||
7090 | mutex_unlock(&dev_priv->dpio_lock); | |
7091 | } | |
7092 | ||
d288f65f VS |
7093 | /** |
7094 | * vlv_force_pll_on - forcibly enable just the PLL | |
7095 | * @dev_priv: i915 private structure | |
7096 | * @pipe: pipe PLL to enable | |
7097 | * @dpll: PLL configuration | |
7098 | * | |
7099 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7100 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7101 | * be enabled. | |
7102 | */ | |
7103 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7104 | const struct dpll *dpll) | |
7105 | { | |
7106 | struct intel_crtc *crtc = | |
7107 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7108 | struct intel_crtc_state pipe_config = { |
a93e255f | 7109 | .base.crtc = &crtc->base, |
d288f65f VS |
7110 | .pixel_multiplier = 1, |
7111 | .dpll = *dpll, | |
7112 | }; | |
7113 | ||
7114 | if (IS_CHERRYVIEW(dev)) { | |
7115 | chv_update_pll(crtc, &pipe_config); | |
7116 | chv_prepare_pll(crtc, &pipe_config); | |
7117 | chv_enable_pll(crtc, &pipe_config); | |
7118 | } else { | |
7119 | vlv_update_pll(crtc, &pipe_config); | |
7120 | vlv_prepare_pll(crtc, &pipe_config); | |
7121 | vlv_enable_pll(crtc, &pipe_config); | |
7122 | } | |
7123 | } | |
7124 | ||
7125 | /** | |
7126 | * vlv_force_pll_off - forcibly disable just the PLL | |
7127 | * @dev_priv: i915 private structure | |
7128 | * @pipe: pipe PLL to disable | |
7129 | * | |
7130 | * Disable the PLL for @pipe. To be used in cases where we need | |
7131 | * the PLL enabled even when @pipe is not going to be enabled. | |
7132 | */ | |
7133 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7134 | { | |
7135 | if (IS_CHERRYVIEW(dev)) | |
7136 | chv_disable_pll(to_i915(dev), pipe); | |
7137 | else | |
7138 | vlv_disable_pll(to_i915(dev), pipe); | |
7139 | } | |
7140 | ||
f47709a9 | 7141 | static void i9xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7142 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7143 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7144 | int num_connectors) |
7145 | { | |
f47709a9 | 7146 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7147 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7148 | u32 dpll; |
7149 | bool is_sdvo; | |
190f68c5 | 7150 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7151 | |
190f68c5 | 7152 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7153 | |
a93e255f ACO |
7154 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7155 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7156 | |
7157 | dpll = DPLL_VGA_MODE_DIS; | |
7158 | ||
a93e255f | 7159 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7160 | dpll |= DPLLB_MODE_LVDS; |
7161 | else | |
7162 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7163 | |
ef1b460d | 7164 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7165 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7166 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7167 | } |
198a037f DV |
7168 | |
7169 | if (is_sdvo) | |
4a33e48d | 7170 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7171 | |
190f68c5 | 7172 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7173 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7174 | |
7175 | /* compute bitmask from p1 value */ | |
7176 | if (IS_PINEVIEW(dev)) | |
7177 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7178 | else { | |
7179 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7180 | if (IS_G4X(dev) && reduced_clock) | |
7181 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7182 | } | |
7183 | switch (clock->p2) { | |
7184 | case 5: | |
7185 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7186 | break; | |
7187 | case 7: | |
7188 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7189 | break; | |
7190 | case 10: | |
7191 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7192 | break; | |
7193 | case 14: | |
7194 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7195 | break; | |
7196 | } | |
7197 | if (INTEL_INFO(dev)->gen >= 4) | |
7198 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7199 | ||
190f68c5 | 7200 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7201 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7202 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7203 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7204 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7205 | else | |
7206 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7207 | ||
7208 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7209 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7210 | |
eb1cbe48 | 7211 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7212 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7213 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7214 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7215 | } |
7216 | } | |
7217 | ||
f47709a9 | 7218 | static void i8xx_update_pll(struct intel_crtc *crtc, |
190f68c5 | 7219 | struct intel_crtc_state *crtc_state, |
f47709a9 | 7220 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
7221 | int num_connectors) |
7222 | { | |
f47709a9 | 7223 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7224 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7225 | u32 dpll; |
190f68c5 | 7226 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7227 | |
190f68c5 | 7228 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7229 | |
eb1cbe48 DV |
7230 | dpll = DPLL_VGA_MODE_DIS; |
7231 | ||
a93e255f | 7232 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7233 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7234 | } else { | |
7235 | if (clock->p1 == 2) | |
7236 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7237 | else | |
7238 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7239 | if (clock->p2 == 4) | |
7240 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7241 | } | |
7242 | ||
a93e255f | 7243 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7244 | dpll |= DPLL_DVO_2X_MODE; |
7245 | ||
a93e255f | 7246 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7247 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7248 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7249 | else | |
7250 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7251 | ||
7252 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7253 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7254 | } |
7255 | ||
8a654f3b | 7256 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7257 | { |
7258 | struct drm_device *dev = intel_crtc->base.dev; | |
7259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7260 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7261 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
8a654f3b | 7262 | struct drm_display_mode *adjusted_mode = |
6e3c9717 | 7263 | &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7264 | uint32_t crtc_vtotal, crtc_vblank_end; |
7265 | int vsyncshift = 0; | |
4d8a62ea DV |
7266 | |
7267 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7268 | * the hw state checker will get angry at the mismatch. */ | |
7269 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7270 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7271 | |
609aeaca | 7272 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7273 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7274 | crtc_vtotal -= 1; |
7275 | crtc_vblank_end -= 1; | |
609aeaca | 7276 | |
409ee761 | 7277 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7278 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7279 | else | |
7280 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7281 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7282 | if (vsyncshift < 0) |
7283 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7284 | } |
7285 | ||
7286 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7287 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7288 | |
fe2b8f9d | 7289 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7290 | (adjusted_mode->crtc_hdisplay - 1) | |
7291 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7292 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7293 | (adjusted_mode->crtc_hblank_start - 1) | |
7294 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7295 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7296 | (adjusted_mode->crtc_hsync_start - 1) | |
7297 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7298 | ||
fe2b8f9d | 7299 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7300 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7301 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7302 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7303 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7304 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7305 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7306 | (adjusted_mode->crtc_vsync_start - 1) | |
7307 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7308 | ||
b5e508d4 PZ |
7309 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7310 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7311 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7312 | * bits. */ | |
7313 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7314 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7315 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7316 | ||
b0e77b9c PZ |
7317 | /* pipesrc controls the size that is scaled from, which should |
7318 | * always be the user's requested size. | |
7319 | */ | |
7320 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7321 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7322 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7323 | } |
7324 | ||
1bd1bd80 | 7325 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7326 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7327 | { |
7328 | struct drm_device *dev = crtc->base.dev; | |
7329 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7330 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7331 | uint32_t tmp; | |
7332 | ||
7333 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7334 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7335 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7336 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7337 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7338 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7339 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7340 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7341 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7342 | |
7343 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7344 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7345 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7346 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7347 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7348 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7349 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7350 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7351 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7352 | |
7353 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7354 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7355 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7356 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7357 | } |
7358 | ||
7359 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7360 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7361 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7362 | ||
2d112de7 ACO |
7363 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7364 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7365 | } |
7366 | ||
f6a83288 | 7367 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7368 | struct intel_crtc_state *pipe_config) |
babea61d | 7369 | { |
2d112de7 ACO |
7370 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7371 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7372 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7373 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7374 | |
2d112de7 ACO |
7375 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7376 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7377 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7378 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7379 | |
2d112de7 | 7380 | mode->flags = pipe_config->base.adjusted_mode.flags; |
babea61d | 7381 | |
2d112de7 ACO |
7382 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7383 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
babea61d JB |
7384 | } |
7385 | ||
84b046f3 DV |
7386 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7387 | { | |
7388 | struct drm_device *dev = intel_crtc->base.dev; | |
7389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7390 | uint32_t pipeconf; | |
7391 | ||
9f11a9e4 | 7392 | pipeconf = 0; |
84b046f3 | 7393 | |
b6b5d049 VS |
7394 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7395 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7396 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7397 | |
6e3c9717 | 7398 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7399 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7400 | |
ff9ce46e DV |
7401 | /* only g4x and later have fancy bpc/dither controls */ |
7402 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e | 7403 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7404 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7405 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7406 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7407 | |
6e3c9717 | 7408 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7409 | case 18: |
7410 | pipeconf |= PIPECONF_6BPC; | |
7411 | break; | |
7412 | case 24: | |
7413 | pipeconf |= PIPECONF_8BPC; | |
7414 | break; | |
7415 | case 30: | |
7416 | pipeconf |= PIPECONF_10BPC; | |
7417 | break; | |
7418 | default: | |
7419 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7420 | BUG(); | |
84b046f3 DV |
7421 | } |
7422 | } | |
7423 | ||
7424 | if (HAS_PIPE_CXSR(dev)) { | |
7425 | if (intel_crtc->lowfreq_avail) { | |
7426 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7427 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7428 | } else { | |
7429 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7430 | } |
7431 | } | |
7432 | ||
6e3c9717 | 7433 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7434 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7435 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7436 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7437 | else | |
7438 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7439 | } else | |
84b046f3 DV |
7440 | pipeconf |= PIPECONF_PROGRESSIVE; |
7441 | ||
6e3c9717 | 7442 | if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) |
9f11a9e4 | 7443 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7444 | |
84b046f3 DV |
7445 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7446 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7447 | } | |
7448 | ||
190f68c5 ACO |
7449 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7450 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7451 | { |
c7653199 | 7452 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7453 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7454 | int refclk, num_connectors = 0; |
652c393a | 7455 | intel_clock_t clock, reduced_clock; |
a16af721 | 7456 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 7457 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 7458 | struct intel_encoder *encoder; |
d4906093 | 7459 | const intel_limit_t *limit; |
55bb9992 | 7460 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7461 | struct drm_connector *connector; |
55bb9992 ACO |
7462 | struct drm_connector_state *connector_state; |
7463 | int i; | |
79e53945 | 7464 | |
da3ced29 | 7465 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
7466 | if (connector_state->crtc != &crtc->base) |
7467 | continue; | |
7468 | ||
7469 | encoder = to_intel_encoder(connector_state->best_encoder); | |
7470 | ||
5eddb70b | 7471 | switch (encoder->type) { |
79e53945 JB |
7472 | case INTEL_OUTPUT_LVDS: |
7473 | is_lvds = true; | |
7474 | break; | |
e9fd1c02 JN |
7475 | case INTEL_OUTPUT_DSI: |
7476 | is_dsi = true; | |
7477 | break; | |
6847d71b PZ |
7478 | default: |
7479 | break; | |
79e53945 | 7480 | } |
43565a06 | 7481 | |
c751ce4f | 7482 | num_connectors++; |
79e53945 JB |
7483 | } |
7484 | ||
f2335330 | 7485 | if (is_dsi) |
5b18e57c | 7486 | return 0; |
f2335330 | 7487 | |
190f68c5 | 7488 | if (!crtc_state->clock_set) { |
a93e255f | 7489 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7490 | |
e9fd1c02 JN |
7491 | /* |
7492 | * Returns a set of divisors for the desired target clock with | |
7493 | * the given refclk, or FALSE. The returned values represent | |
7494 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7495 | * 2) / p1 / p2. | |
7496 | */ | |
a93e255f ACO |
7497 | limit = intel_limit(crtc_state, refclk); |
7498 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7499 | crtc_state->port_clock, |
e9fd1c02 | 7500 | refclk, NULL, &clock); |
f2335330 | 7501 | if (!ok) { |
e9fd1c02 JN |
7502 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7503 | return -EINVAL; | |
7504 | } | |
79e53945 | 7505 | |
f2335330 JN |
7506 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
7507 | /* | |
7508 | * Ensure we match the reduced clock's P to the target | |
7509 | * clock. If the clocks don't match, we can't switch | |
7510 | * the display clock by using the FP0/FP1. In such case | |
7511 | * we will disable the LVDS downclock feature. | |
7512 | */ | |
7513 | has_reduced_clock = | |
a93e255f | 7514 | dev_priv->display.find_dpll(limit, crtc_state, |
f2335330 JN |
7515 | dev_priv->lvds_downclock, |
7516 | refclk, &clock, | |
7517 | &reduced_clock); | |
7518 | } | |
7519 | /* Compat-code for transition, will disappear. */ | |
190f68c5 ACO |
7520 | crtc_state->dpll.n = clock.n; |
7521 | crtc_state->dpll.m1 = clock.m1; | |
7522 | crtc_state->dpll.m2 = clock.m2; | |
7523 | crtc_state->dpll.p1 = clock.p1; | |
7524 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7525 | } |
7026d4ac | 7526 | |
e9fd1c02 | 7527 | if (IS_GEN2(dev)) { |
190f68c5 | 7528 | i8xx_update_pll(crtc, crtc_state, |
2a8f64ca VP |
7529 | has_reduced_clock ? &reduced_clock : NULL, |
7530 | num_connectors); | |
9d556c99 | 7531 | } else if (IS_CHERRYVIEW(dev)) { |
190f68c5 | 7532 | chv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7533 | } else if (IS_VALLEYVIEW(dev)) { |
190f68c5 | 7534 | vlv_update_pll(crtc, crtc_state); |
e9fd1c02 | 7535 | } else { |
190f68c5 | 7536 | i9xx_update_pll(crtc, crtc_state, |
eb1cbe48 | 7537 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 7538 | num_connectors); |
e9fd1c02 | 7539 | } |
79e53945 | 7540 | |
c8f7a0db | 7541 | return 0; |
f564048e EA |
7542 | } |
7543 | ||
2fa2fe9a | 7544 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7545 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7546 | { |
7547 | struct drm_device *dev = crtc->base.dev; | |
7548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7549 | uint32_t tmp; | |
7550 | ||
dc9e7dec VS |
7551 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7552 | return; | |
7553 | ||
2fa2fe9a | 7554 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7555 | if (!(tmp & PFIT_ENABLE)) |
7556 | return; | |
2fa2fe9a | 7557 | |
06922821 | 7558 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7559 | if (INTEL_INFO(dev)->gen < 4) { |
7560 | if (crtc->pipe != PIPE_B) | |
7561 | return; | |
2fa2fe9a DV |
7562 | } else { |
7563 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7564 | return; | |
7565 | } | |
7566 | ||
06922821 | 7567 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
7568 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
7569 | if (INTEL_INFO(dev)->gen < 5) | |
7570 | pipe_config->gmch_pfit.lvds_border_bits = | |
7571 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
7572 | } | |
7573 | ||
acbec814 | 7574 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7575 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7576 | { |
7577 | struct drm_device *dev = crtc->base.dev; | |
7578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7579 | int pipe = pipe_config->cpu_transcoder; | |
7580 | intel_clock_t clock; | |
7581 | u32 mdiv; | |
662c6ecb | 7582 | int refclk = 100000; |
acbec814 | 7583 | |
f573de5a SK |
7584 | /* In case of MIPI DPLL will not even be used */ |
7585 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
7586 | return; | |
7587 | ||
acbec814 | 7588 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 7589 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
7590 | mutex_unlock(&dev_priv->dpio_lock); |
7591 | ||
7592 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7593 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7594 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7595 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7596 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7597 | ||
f646628b | 7598 | vlv_clock(refclk, &clock); |
acbec814 | 7599 | |
f646628b VS |
7600 | /* clock.dot is the fast clock */ |
7601 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
7602 | } |
7603 | ||
5724dbd1 DL |
7604 | static void |
7605 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7606 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7607 | { |
7608 | struct drm_device *dev = crtc->base.dev; | |
7609 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7610 | u32 val, base, offset; | |
7611 | int pipe = crtc->pipe, plane = crtc->plane; | |
7612 | int fourcc, pixel_format; | |
6761dd31 | 7613 | unsigned int aligned_height; |
b113d5ee | 7614 | struct drm_framebuffer *fb; |
1b842c89 | 7615 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7616 | |
42a7b088 DL |
7617 | val = I915_READ(DSPCNTR(plane)); |
7618 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7619 | return; | |
7620 | ||
d9806c9f | 7621 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7622 | if (!intel_fb) { |
1ad292b5 JB |
7623 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7624 | return; | |
7625 | } | |
7626 | ||
1b842c89 DL |
7627 | fb = &intel_fb->base; |
7628 | ||
18c5247e DV |
7629 | if (INTEL_INFO(dev)->gen >= 4) { |
7630 | if (val & DISPPLANE_TILED) { | |
49af449b | 7631 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
7632 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
7633 | } | |
7634 | } | |
1ad292b5 JB |
7635 | |
7636 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7637 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
7638 | fb->pixel_format = fourcc; |
7639 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
7640 | |
7641 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 7642 | if (plane_config->tiling) |
1ad292b5 JB |
7643 | offset = I915_READ(DSPTILEOFF(plane)); |
7644 | else | |
7645 | offset = I915_READ(DSPLINOFF(plane)); | |
7646 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7647 | } else { | |
7648 | base = I915_READ(DSPADDR(plane)); | |
7649 | } | |
7650 | plane_config->base = base; | |
7651 | ||
7652 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7653 | fb->width = ((val >> 16) & 0xfff) + 1; |
7654 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7655 | |
7656 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7657 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7658 | |
b113d5ee | 7659 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
7660 | fb->pixel_format, |
7661 | fb->modifier[0]); | |
1ad292b5 | 7662 | |
f37b5c2b | 7663 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7664 | |
2844a921 DL |
7665 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7666 | pipe_name(pipe), plane, fb->width, fb->height, | |
7667 | fb->bits_per_pixel, base, fb->pitches[0], | |
7668 | plane_config->size); | |
1ad292b5 | 7669 | |
2d14030b | 7670 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7671 | } |
7672 | ||
70b23a98 | 7673 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7674 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7675 | { |
7676 | struct drm_device *dev = crtc->base.dev; | |
7677 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7678 | int pipe = pipe_config->cpu_transcoder; | |
7679 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
7680 | intel_clock_t clock; | |
7681 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
7682 | int refclk = 100000; | |
7683 | ||
7684 | mutex_lock(&dev_priv->dpio_lock); | |
7685 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
7686 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7687 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7688 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
7689 | mutex_unlock(&dev_priv->dpio_lock); | |
7690 | ||
7691 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
7692 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
7693 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
7694 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7695 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7696 | ||
7697 | chv_clock(refclk, &clock); | |
7698 | ||
7699 | /* clock.dot is the fast clock */ | |
7700 | pipe_config->port_clock = clock.dot / 5; | |
7701 | } | |
7702 | ||
0e8ffe1b | 7703 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7704 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
7705 | { |
7706 | struct drm_device *dev = crtc->base.dev; | |
7707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7708 | uint32_t tmp; | |
7709 | ||
f458ebbc DV |
7710 | if (!intel_display_power_is_enabled(dev_priv, |
7711 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
7712 | return false; |
7713 | ||
e143a21c | 7714 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7715 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7716 | |
0e8ffe1b DV |
7717 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7718 | if (!(tmp & PIPECONF_ENABLE)) | |
7719 | return false; | |
7720 | ||
42571aef VS |
7721 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
7722 | switch (tmp & PIPECONF_BPC_MASK) { | |
7723 | case PIPECONF_6BPC: | |
7724 | pipe_config->pipe_bpp = 18; | |
7725 | break; | |
7726 | case PIPECONF_8BPC: | |
7727 | pipe_config->pipe_bpp = 24; | |
7728 | break; | |
7729 | case PIPECONF_10BPC: | |
7730 | pipe_config->pipe_bpp = 30; | |
7731 | break; | |
7732 | default: | |
7733 | break; | |
7734 | } | |
7735 | } | |
7736 | ||
b5a9fa09 DV |
7737 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
7738 | pipe_config->limited_color_range = true; | |
7739 | ||
282740f7 VS |
7740 | if (INTEL_INFO(dev)->gen < 4) |
7741 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
7742 | ||
1bd1bd80 DV |
7743 | intel_get_pipe_timings(crtc, pipe_config); |
7744 | ||
2fa2fe9a DV |
7745 | i9xx_get_pfit_config(crtc, pipe_config); |
7746 | ||
6c49f241 DV |
7747 | if (INTEL_INFO(dev)->gen >= 4) { |
7748 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
7749 | pipe_config->pixel_multiplier = | |
7750 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7751 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7752 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
7753 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
7754 | tmp = I915_READ(DPLL(crtc->pipe)); | |
7755 | pipe_config->pixel_multiplier = | |
7756 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7757 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7758 | } else { | |
7759 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7760 | * port and will be fixed up in the encoder->get_config | |
7761 | * function. */ | |
7762 | pipe_config->pixel_multiplier = 1; | |
7763 | } | |
8bcc2795 DV |
7764 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
7765 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
7766 | /* |
7767 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7768 | * on 830. Filter it out here so that we don't | |
7769 | * report errors due to that. | |
7770 | */ | |
7771 | if (IS_I830(dev)) | |
7772 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
7773 | ||
8bcc2795 DV |
7774 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7775 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7776 | } else { |
7777 | /* Mask out read-only status bits. */ | |
7778 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7779 | DPLL_PORTC_READY_MASK | | |
7780 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7781 | } |
6c49f241 | 7782 | |
70b23a98 VS |
7783 | if (IS_CHERRYVIEW(dev)) |
7784 | chv_crtc_clock_get(crtc, pipe_config); | |
7785 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
7786 | vlv_crtc_clock_get(crtc, pipe_config); |
7787 | else | |
7788 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7789 | |
0e8ffe1b DV |
7790 | return true; |
7791 | } | |
7792 | ||
dde86e2d | 7793 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
7794 | { |
7795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 7796 | struct intel_encoder *encoder; |
74cfd7ac | 7797 | u32 val, final; |
13d83a67 | 7798 | bool has_lvds = false; |
199e5d79 | 7799 | bool has_cpu_edp = false; |
199e5d79 | 7800 | bool has_panel = false; |
99eb6a01 KP |
7801 | bool has_ck505 = false; |
7802 | bool can_ssc = false; | |
13d83a67 JB |
7803 | |
7804 | /* We need to take the global config into account */ | |
b2784e15 | 7805 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
7806 | switch (encoder->type) { |
7807 | case INTEL_OUTPUT_LVDS: | |
7808 | has_panel = true; | |
7809 | has_lvds = true; | |
7810 | break; | |
7811 | case INTEL_OUTPUT_EDP: | |
7812 | has_panel = true; | |
2de6905f | 7813 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7814 | has_cpu_edp = true; |
7815 | break; | |
6847d71b PZ |
7816 | default: |
7817 | break; | |
13d83a67 JB |
7818 | } |
7819 | } | |
7820 | ||
99eb6a01 | 7821 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 7822 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7823 | can_ssc = has_ck505; |
7824 | } else { | |
7825 | has_ck505 = false; | |
7826 | can_ssc = true; | |
7827 | } | |
7828 | ||
2de6905f ID |
7829 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
7830 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
7831 | |
7832 | /* Ironlake: try to setup display ref clock before DPLL | |
7833 | * enabling. This is only under driver's control after | |
7834 | * PCH B stepping, previous chipset stepping should be | |
7835 | * ignoring this setting. | |
7836 | */ | |
74cfd7ac CW |
7837 | val = I915_READ(PCH_DREF_CONTROL); |
7838 | ||
7839 | /* As we must carefully and slowly disable/enable each source in turn, | |
7840 | * compute the final state we want first and check if we need to | |
7841 | * make any changes at all. | |
7842 | */ | |
7843 | final = val; | |
7844 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7845 | if (has_ck505) | |
7846 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7847 | else | |
7848 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7849 | ||
7850 | final &= ~DREF_SSC_SOURCE_MASK; | |
7851 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
7852 | final &= ~DREF_SSC1_ENABLE; | |
7853 | ||
7854 | if (has_panel) { | |
7855 | final |= DREF_SSC_SOURCE_ENABLE; | |
7856 | ||
7857 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7858 | final |= DREF_SSC1_ENABLE; | |
7859 | ||
7860 | if (has_cpu_edp) { | |
7861 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7862 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7863 | else | |
7864 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7865 | } else | |
7866 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7867 | } else { | |
7868 | final |= DREF_SSC_SOURCE_DISABLE; | |
7869 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
7870 | } | |
7871 | ||
7872 | if (final == val) | |
7873 | return; | |
7874 | ||
13d83a67 | 7875 | /* Always enable nonspread source */ |
74cfd7ac | 7876 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7877 | |
99eb6a01 | 7878 | if (has_ck505) |
74cfd7ac | 7879 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7880 | else |
74cfd7ac | 7881 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7882 | |
199e5d79 | 7883 | if (has_panel) { |
74cfd7ac CW |
7884 | val &= ~DREF_SSC_SOURCE_MASK; |
7885 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7886 | |
199e5d79 | 7887 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7888 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7889 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7890 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7891 | } else |
74cfd7ac | 7892 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7893 | |
7894 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7895 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7896 | POSTING_READ(PCH_DREF_CONTROL); |
7897 | udelay(200); | |
7898 | ||
74cfd7ac | 7899 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7900 | |
7901 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7902 | if (has_cpu_edp) { |
99eb6a01 | 7903 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7904 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7905 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7906 | } else |
74cfd7ac | 7907 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7908 | } else |
74cfd7ac | 7909 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7910 | |
74cfd7ac | 7911 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7912 | POSTING_READ(PCH_DREF_CONTROL); |
7913 | udelay(200); | |
7914 | } else { | |
7915 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
7916 | ||
74cfd7ac | 7917 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7918 | |
7919 | /* Turn off CPU output */ | |
74cfd7ac | 7920 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7921 | |
74cfd7ac | 7922 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7923 | POSTING_READ(PCH_DREF_CONTROL); |
7924 | udelay(200); | |
7925 | ||
7926 | /* Turn off the SSC source */ | |
74cfd7ac CW |
7927 | val &= ~DREF_SSC_SOURCE_MASK; |
7928 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
7929 | |
7930 | /* Turn off SSC1 */ | |
74cfd7ac | 7931 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 7932 | |
74cfd7ac | 7933 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
7934 | POSTING_READ(PCH_DREF_CONTROL); |
7935 | udelay(200); | |
7936 | } | |
74cfd7ac CW |
7937 | |
7938 | BUG_ON(val != final); | |
13d83a67 JB |
7939 | } |
7940 | ||
f31f2d55 | 7941 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7942 | { |
f31f2d55 | 7943 | uint32_t tmp; |
dde86e2d | 7944 | |
0ff066a9 PZ |
7945 | tmp = I915_READ(SOUTH_CHICKEN2); |
7946 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7947 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7948 | |
0ff066a9 PZ |
7949 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
7950 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
7951 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 7952 | |
0ff066a9 PZ |
7953 | tmp = I915_READ(SOUTH_CHICKEN2); |
7954 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7955 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7956 | |
0ff066a9 PZ |
7957 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
7958 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
7959 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
7960 | } |
7961 | ||
7962 | /* WaMPhyProgramming:hsw */ | |
7963 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7964 | { | |
7965 | uint32_t tmp; | |
dde86e2d PZ |
7966 | |
7967 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7968 | tmp &= ~(0xFF << 24); | |
7969 | tmp |= (0x12 << 24); | |
7970 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7971 | ||
dde86e2d PZ |
7972 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7973 | tmp |= (1 << 11); | |
7974 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7975 | ||
7976 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7977 | tmp |= (1 << 11); | |
7978 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7979 | ||
dde86e2d PZ |
7980 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7981 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7982 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7983 | ||
7984 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7985 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7986 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7987 | ||
0ff066a9 PZ |
7988 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7989 | tmp &= ~(7 << 13); | |
7990 | tmp |= (5 << 13); | |
7991 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7992 | |
0ff066a9 PZ |
7993 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7994 | tmp &= ~(7 << 13); | |
7995 | tmp |= (5 << 13); | |
7996 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7997 | |
7998 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7999 | tmp &= ~0xFF; | |
8000 | tmp |= 0x1C; | |
8001 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8002 | ||
8003 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8004 | tmp &= ~0xFF; | |
8005 | tmp |= 0x1C; | |
8006 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8007 | ||
8008 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8009 | tmp &= ~(0xFF << 16); | |
8010 | tmp |= (0x1C << 16); | |
8011 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8012 | ||
8013 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8014 | tmp &= ~(0xFF << 16); | |
8015 | tmp |= (0x1C << 16); | |
8016 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8017 | ||
0ff066a9 PZ |
8018 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8019 | tmp |= (1 << 27); | |
8020 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8021 | |
0ff066a9 PZ |
8022 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8023 | tmp |= (1 << 27); | |
8024 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8025 | |
0ff066a9 PZ |
8026 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8027 | tmp &= ~(0xF << 28); | |
8028 | tmp |= (4 << 28); | |
8029 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8030 | |
0ff066a9 PZ |
8031 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8032 | tmp &= ~(0xF << 28); | |
8033 | tmp |= (4 << 28); | |
8034 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8035 | } |
8036 | ||
2fa86a1f PZ |
8037 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8038 | * Programming" based on the parameters passed: | |
8039 | * - Sequence to enable CLKOUT_DP | |
8040 | * - Sequence to enable CLKOUT_DP without spread | |
8041 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8042 | */ | |
8043 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8044 | bool with_fdi) | |
f31f2d55 PZ |
8045 | { |
8046 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8047 | uint32_t reg, tmp; |
8048 | ||
8049 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8050 | with_spread = true; | |
8051 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
8052 | with_fdi, "LP PCH doesn't have FDI\n")) | |
8053 | with_fdi = false; | |
f31f2d55 PZ |
8054 | |
8055 | mutex_lock(&dev_priv->dpio_lock); | |
8056 | ||
8057 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8058 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8059 | tmp |= SBI_SSCCTL_PATHALT; | |
8060 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8061 | ||
8062 | udelay(24); | |
8063 | ||
2fa86a1f PZ |
8064 | if (with_spread) { |
8065 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8066 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8067 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8068 | |
2fa86a1f PZ |
8069 | if (with_fdi) { |
8070 | lpt_reset_fdi_mphy(dev_priv); | |
8071 | lpt_program_fdi_mphy(dev_priv); | |
8072 | } | |
8073 | } | |
dde86e2d | 8074 | |
2fa86a1f PZ |
8075 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
8076 | SBI_GEN0 : SBI_DBUFF0; | |
8077 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8078 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8079 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
8080 | |
8081 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
8082 | } |
8083 | ||
47701c3b PZ |
8084 | /* Sequence to disable CLKOUT_DP */ |
8085 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8086 | { | |
8087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8088 | uint32_t reg, tmp; | |
8089 | ||
8090 | mutex_lock(&dev_priv->dpio_lock); | |
8091 | ||
8092 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
8093 | SBI_GEN0 : SBI_DBUFF0; | |
8094 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
8095 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8096 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8097 | ||
8098 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8099 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8100 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8101 | tmp |= SBI_SSCCTL_PATHALT; | |
8102 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8103 | udelay(32); | |
8104 | } | |
8105 | tmp |= SBI_SSCCTL_DISABLE; | |
8106 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8107 | } | |
8108 | ||
8109 | mutex_unlock(&dev_priv->dpio_lock); | |
8110 | } | |
8111 | ||
bf8fa3d3 PZ |
8112 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8113 | { | |
bf8fa3d3 PZ |
8114 | struct intel_encoder *encoder; |
8115 | bool has_vga = false; | |
8116 | ||
b2784e15 | 8117 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8118 | switch (encoder->type) { |
8119 | case INTEL_OUTPUT_ANALOG: | |
8120 | has_vga = true; | |
8121 | break; | |
6847d71b PZ |
8122 | default: |
8123 | break; | |
bf8fa3d3 PZ |
8124 | } |
8125 | } | |
8126 | ||
47701c3b PZ |
8127 | if (has_vga) |
8128 | lpt_enable_clkout_dp(dev, true, true); | |
8129 | else | |
8130 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
8131 | } |
8132 | ||
dde86e2d PZ |
8133 | /* |
8134 | * Initialize reference clocks when the driver loads | |
8135 | */ | |
8136 | void intel_init_pch_refclk(struct drm_device *dev) | |
8137 | { | |
8138 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8139 | ironlake_init_pch_refclk(dev); | |
8140 | else if (HAS_PCH_LPT(dev)) | |
8141 | lpt_init_pch_refclk(dev); | |
8142 | } | |
8143 | ||
55bb9992 | 8144 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8145 | { |
55bb9992 | 8146 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8147 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8148 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8149 | struct drm_connector *connector; |
55bb9992 | 8150 | struct drm_connector_state *connector_state; |
d9d444cb | 8151 | struct intel_encoder *encoder; |
55bb9992 | 8152 | int num_connectors = 0, i; |
d9d444cb JB |
8153 | bool is_lvds = false; |
8154 | ||
da3ced29 | 8155 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8156 | if (connector_state->crtc != crtc_state->base.crtc) |
8157 | continue; | |
8158 | ||
8159 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8160 | ||
d9d444cb JB |
8161 | switch (encoder->type) { |
8162 | case INTEL_OUTPUT_LVDS: | |
8163 | is_lvds = true; | |
8164 | break; | |
6847d71b PZ |
8165 | default: |
8166 | break; | |
d9d444cb JB |
8167 | } |
8168 | num_connectors++; | |
8169 | } | |
8170 | ||
8171 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8172 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8173 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8174 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8175 | } |
8176 | ||
8177 | return 120000; | |
8178 | } | |
8179 | ||
6ff93609 | 8180 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8181 | { |
c8203565 | 8182 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8183 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8184 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8185 | uint32_t val; |
8186 | ||
78114071 | 8187 | val = 0; |
c8203565 | 8188 | |
6e3c9717 | 8189 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8190 | case 18: |
dfd07d72 | 8191 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8192 | break; |
8193 | case 24: | |
dfd07d72 | 8194 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8195 | break; |
8196 | case 30: | |
dfd07d72 | 8197 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8198 | break; |
8199 | case 36: | |
dfd07d72 | 8200 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8201 | break; |
8202 | default: | |
cc769b62 PZ |
8203 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8204 | BUG(); | |
c8203565 PZ |
8205 | } |
8206 | ||
6e3c9717 | 8207 | if (intel_crtc->config->dither) |
c8203565 PZ |
8208 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8209 | ||
6e3c9717 | 8210 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8211 | val |= PIPECONF_INTERLACED_ILK; |
8212 | else | |
8213 | val |= PIPECONF_PROGRESSIVE; | |
8214 | ||
6e3c9717 | 8215 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8216 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8217 | |
c8203565 PZ |
8218 | I915_WRITE(PIPECONF(pipe), val); |
8219 | POSTING_READ(PIPECONF(pipe)); | |
8220 | } | |
8221 | ||
86d3efce VS |
8222 | /* |
8223 | * Set up the pipe CSC unit. | |
8224 | * | |
8225 | * Currently only full range RGB to limited range RGB conversion | |
8226 | * is supported, but eventually this should handle various | |
8227 | * RGB<->YCbCr scenarios as well. | |
8228 | */ | |
50f3b016 | 8229 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8230 | { |
8231 | struct drm_device *dev = crtc->dev; | |
8232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8234 | int pipe = intel_crtc->pipe; | |
8235 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8236 | ||
8237 | /* | |
8238 | * TODO: Check what kind of values actually come out of the pipe | |
8239 | * with these coeff/postoff values and adjust to get the best | |
8240 | * accuracy. Perhaps we even need to take the bpc value into | |
8241 | * consideration. | |
8242 | */ | |
8243 | ||
6e3c9717 | 8244 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8245 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8246 | ||
8247 | /* | |
8248 | * GY/GU and RY/RU should be the other way around according | |
8249 | * to BSpec, but reality doesn't agree. Just set them up in | |
8250 | * a way that results in the correct picture. | |
8251 | */ | |
8252 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8253 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8254 | ||
8255 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8256 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8257 | ||
8258 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8259 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8260 | ||
8261 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8262 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8263 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8264 | ||
8265 | if (INTEL_INFO(dev)->gen > 6) { | |
8266 | uint16_t postoff = 0; | |
8267 | ||
6e3c9717 | 8268 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8269 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8270 | |
8271 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8272 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8273 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8274 | ||
8275 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8276 | } else { | |
8277 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8278 | ||
6e3c9717 | 8279 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8280 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8281 | ||
8282 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8283 | } | |
8284 | } | |
8285 | ||
6ff93609 | 8286 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8287 | { |
756f85cf PZ |
8288 | struct drm_device *dev = crtc->dev; |
8289 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8291 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8292 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8293 | uint32_t val; |
8294 | ||
3eff4faa | 8295 | val = 0; |
ee2b0b38 | 8296 | |
6e3c9717 | 8297 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8298 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8299 | ||
6e3c9717 | 8300 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8301 | val |= PIPECONF_INTERLACED_ILK; |
8302 | else | |
8303 | val |= PIPECONF_PROGRESSIVE; | |
8304 | ||
702e7a56 PZ |
8305 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8306 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8307 | |
8308 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8309 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8310 | |
3cdf122c | 8311 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8312 | val = 0; |
8313 | ||
6e3c9717 | 8314 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8315 | case 18: |
8316 | val |= PIPEMISC_DITHER_6_BPC; | |
8317 | break; | |
8318 | case 24: | |
8319 | val |= PIPEMISC_DITHER_8_BPC; | |
8320 | break; | |
8321 | case 30: | |
8322 | val |= PIPEMISC_DITHER_10_BPC; | |
8323 | break; | |
8324 | case 36: | |
8325 | val |= PIPEMISC_DITHER_12_BPC; | |
8326 | break; | |
8327 | default: | |
8328 | /* Case prevented by pipe_config_set_bpp. */ | |
8329 | BUG(); | |
8330 | } | |
8331 | ||
6e3c9717 | 8332 | if (intel_crtc->config->dither) |
756f85cf PZ |
8333 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8334 | ||
8335 | I915_WRITE(PIPEMISC(pipe), val); | |
8336 | } | |
ee2b0b38 PZ |
8337 | } |
8338 | ||
6591c6e4 | 8339 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8340 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8341 | intel_clock_t *clock, |
8342 | bool *has_reduced_clock, | |
8343 | intel_clock_t *reduced_clock) | |
8344 | { | |
8345 | struct drm_device *dev = crtc->dev; | |
8346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8347 | int refclk; |
d4906093 | 8348 | const intel_limit_t *limit; |
a16af721 | 8349 | bool ret, is_lvds = false; |
79e53945 | 8350 | |
a93e255f | 8351 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 8352 | |
55bb9992 | 8353 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8354 | |
d4906093 ML |
8355 | /* |
8356 | * Returns a set of divisors for the desired target clock with the given | |
8357 | * refclk, or FALSE. The returned values represent the clock equation: | |
8358 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8359 | */ | |
a93e255f ACO |
8360 | limit = intel_limit(crtc_state, refclk); |
8361 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8362 | crtc_state->port_clock, |
ee9300bb | 8363 | refclk, NULL, clock); |
6591c6e4 PZ |
8364 | if (!ret) |
8365 | return false; | |
cda4b7d3 | 8366 | |
ddc9003c | 8367 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
8368 | /* |
8369 | * Ensure we match the reduced clock's P to the target clock. | |
8370 | * If the clocks don't match, we can't switch the display clock | |
8371 | * by using the FP0/FP1. In such case we will disable the LVDS | |
8372 | * downclock feature. | |
8373 | */ | |
ee9300bb | 8374 | *has_reduced_clock = |
a93e255f | 8375 | dev_priv->display.find_dpll(limit, crtc_state, |
ee9300bb DV |
8376 | dev_priv->lvds_downclock, |
8377 | refclk, clock, | |
8378 | reduced_clock); | |
652c393a | 8379 | } |
61e9653f | 8380 | |
6591c6e4 PZ |
8381 | return true; |
8382 | } | |
8383 | ||
d4b1931c PZ |
8384 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8385 | { | |
8386 | /* | |
8387 | * Account for spread spectrum to avoid | |
8388 | * oversubscribing the link. Max center spread | |
8389 | * is 2.5%; use 5% for safety's sake. | |
8390 | */ | |
8391 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8392 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8393 | } |
8394 | ||
7429e9d4 | 8395 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8396 | { |
7429e9d4 | 8397 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8398 | } |
8399 | ||
de13a2e3 | 8400 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8401 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8402 | u32 *fp, |
9a7c7890 | 8403 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8404 | { |
de13a2e3 | 8405 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8406 | struct drm_device *dev = crtc->dev; |
8407 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8408 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8409 | struct drm_connector *connector; |
55bb9992 ACO |
8410 | struct drm_connector_state *connector_state; |
8411 | struct intel_encoder *encoder; | |
de13a2e3 | 8412 | uint32_t dpll; |
55bb9992 | 8413 | int factor, num_connectors = 0, i; |
09ede541 | 8414 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8415 | |
da3ced29 | 8416 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8417 | if (connector_state->crtc != crtc_state->base.crtc) |
8418 | continue; | |
8419 | ||
8420 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8421 | ||
8422 | switch (encoder->type) { | |
79e53945 JB |
8423 | case INTEL_OUTPUT_LVDS: |
8424 | is_lvds = true; | |
8425 | break; | |
8426 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8427 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8428 | is_sdvo = true; |
79e53945 | 8429 | break; |
6847d71b PZ |
8430 | default: |
8431 | break; | |
79e53945 | 8432 | } |
43565a06 | 8433 | |
c751ce4f | 8434 | num_connectors++; |
79e53945 | 8435 | } |
79e53945 | 8436 | |
c1858123 | 8437 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8438 | factor = 21; |
8439 | if (is_lvds) { | |
8440 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8441 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8442 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8443 | factor = 25; |
190f68c5 | 8444 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8445 | factor = 20; |
c1858123 | 8446 | |
190f68c5 | 8447 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8448 | *fp |= FP_CB_TUNE; |
2c07245f | 8449 | |
9a7c7890 DV |
8450 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8451 | *fp2 |= FP_CB_TUNE; | |
8452 | ||
5eddb70b | 8453 | dpll = 0; |
2c07245f | 8454 | |
a07d6787 EA |
8455 | if (is_lvds) |
8456 | dpll |= DPLLB_MODE_LVDS; | |
8457 | else | |
8458 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8459 | |
190f68c5 | 8460 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8461 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8462 | |
8463 | if (is_sdvo) | |
4a33e48d | 8464 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8465 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8466 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8467 | |
a07d6787 | 8468 | /* compute bitmask from p1 value */ |
190f68c5 | 8469 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8470 | /* also FPA1 */ |
190f68c5 | 8471 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8472 | |
190f68c5 | 8473 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8474 | case 5: |
8475 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8476 | break; | |
8477 | case 7: | |
8478 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8479 | break; | |
8480 | case 10: | |
8481 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8482 | break; | |
8483 | case 14: | |
8484 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8485 | break; | |
79e53945 JB |
8486 | } |
8487 | ||
b4c09f3b | 8488 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8489 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8490 | else |
8491 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8492 | ||
959e16d6 | 8493 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8494 | } |
8495 | ||
190f68c5 ACO |
8496 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8497 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8498 | { |
c7653199 | 8499 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 8500 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 8501 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 8502 | bool ok, has_reduced_clock = false; |
8b47047b | 8503 | bool is_lvds = false; |
e2b78267 | 8504 | struct intel_shared_dpll *pll; |
de13a2e3 | 8505 | |
409ee761 | 8506 | is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS); |
79e53945 | 8507 | |
5dc5298b PZ |
8508 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
8509 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 8510 | |
190f68c5 | 8511 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 8512 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 8513 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
8514 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8515 | return -EINVAL; | |
79e53945 | 8516 | } |
f47709a9 | 8517 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8518 | if (!crtc_state->clock_set) { |
8519 | crtc_state->dpll.n = clock.n; | |
8520 | crtc_state->dpll.m1 = clock.m1; | |
8521 | crtc_state->dpll.m2 = clock.m2; | |
8522 | crtc_state->dpll.p1 = clock.p1; | |
8523 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8524 | } |
79e53945 | 8525 | |
5dc5298b | 8526 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
8527 | if (crtc_state->has_pch_encoder) { |
8528 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 8529 | if (has_reduced_clock) |
7429e9d4 | 8530 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 8531 | |
190f68c5 | 8532 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
8533 | &fp, &reduced_clock, |
8534 | has_reduced_clock ? &fp2 : NULL); | |
8535 | ||
190f68c5 ACO |
8536 | crtc_state->dpll_hw_state.dpll = dpll; |
8537 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 8538 | if (has_reduced_clock) |
190f68c5 | 8539 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 8540 | else |
190f68c5 | 8541 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 8542 | |
190f68c5 | 8543 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 8544 | if (pll == NULL) { |
84f44ce7 | 8545 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 8546 | pipe_name(crtc->pipe)); |
4b645f14 JB |
8547 | return -EINVAL; |
8548 | } | |
3fb37703 | 8549 | } |
79e53945 | 8550 | |
ab585dea | 8551 | if (is_lvds && has_reduced_clock) |
c7653199 | 8552 | crtc->lowfreq_avail = true; |
bcd644e0 | 8553 | else |
c7653199 | 8554 | crtc->lowfreq_avail = false; |
e2b78267 | 8555 | |
c8f7a0db | 8556 | return 0; |
79e53945 JB |
8557 | } |
8558 | ||
eb14cb74 VS |
8559 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8560 | struct intel_link_m_n *m_n) | |
8561 | { | |
8562 | struct drm_device *dev = crtc->base.dev; | |
8563 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8564 | enum pipe pipe = crtc->pipe; | |
8565 | ||
8566 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8567 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8568 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8569 | & ~TU_SIZE_MASK; | |
8570 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8571 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8572 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8573 | } | |
8574 | ||
8575 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8576 | enum transcoder transcoder, | |
b95af8be VK |
8577 | struct intel_link_m_n *m_n, |
8578 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8579 | { |
8580 | struct drm_device *dev = crtc->base.dev; | |
8581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8582 | enum pipe pipe = crtc->pipe; |
72419203 | 8583 | |
eb14cb74 VS |
8584 | if (INTEL_INFO(dev)->gen >= 5) { |
8585 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8586 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8587 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8588 | & ~TU_SIZE_MASK; | |
8589 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8590 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8591 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8592 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8593 | * gen < 8) and if DRRS is supported (to make sure the | |
8594 | * registers are not unnecessarily read). | |
8595 | */ | |
8596 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8597 | crtc->config->has_drrs) { |
b95af8be VK |
8598 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8599 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8600 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8601 | & ~TU_SIZE_MASK; | |
8602 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8603 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8604 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8605 | } | |
eb14cb74 VS |
8606 | } else { |
8607 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8608 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8609 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8610 | & ~TU_SIZE_MASK; | |
8611 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8612 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8613 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8614 | } | |
8615 | } | |
8616 | ||
8617 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8618 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8619 | { |
681a8504 | 8620 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8621 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8622 | else | |
8623 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8624 | &pipe_config->dp_m_n, |
8625 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8626 | } |
72419203 | 8627 | |
eb14cb74 | 8628 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8629 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8630 | { |
8631 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8632 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8633 | } |
8634 | ||
bd2e244f | 8635 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8636 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8637 | { |
8638 | struct drm_device *dev = crtc->base.dev; | |
8639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
8640 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8641 | uint32_t ps_ctrl = 0; | |
8642 | int id = -1; | |
8643 | int i; | |
bd2e244f | 8644 | |
a1b2278e CK |
8645 | /* find scaler attached to this pipe */ |
8646 | for (i = 0; i < crtc->num_scalers; i++) { | |
8647 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8648 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8649 | id = i; | |
8650 | pipe_config->pch_pfit.enabled = true; | |
8651 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8652 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8653 | break; | |
8654 | } | |
8655 | } | |
bd2e244f | 8656 | |
a1b2278e CK |
8657 | scaler_state->scaler_id = id; |
8658 | if (id >= 0) { | |
8659 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8660 | } else { | |
8661 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8662 | } |
8663 | } | |
8664 | ||
5724dbd1 DL |
8665 | static void |
8666 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8667 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8668 | { |
8669 | struct drm_device *dev = crtc->base.dev; | |
8670 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 8671 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8672 | int pipe = crtc->pipe; |
8673 | int fourcc, pixel_format; | |
6761dd31 | 8674 | unsigned int aligned_height; |
bc8d7dff | 8675 | struct drm_framebuffer *fb; |
1b842c89 | 8676 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8677 | |
d9806c9f | 8678 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8679 | if (!intel_fb) { |
bc8d7dff DL |
8680 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8681 | return; | |
8682 | } | |
8683 | ||
1b842c89 DL |
8684 | fb = &intel_fb->base; |
8685 | ||
bc8d7dff | 8686 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8687 | if (!(val & PLANE_CTL_ENABLE)) |
8688 | goto error; | |
8689 | ||
bc8d7dff DL |
8690 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8691 | fourcc = skl_format_to_fourcc(pixel_format, | |
8692 | val & PLANE_CTL_ORDER_RGBX, | |
8693 | val & PLANE_CTL_ALPHA_MASK); | |
8694 | fb->pixel_format = fourcc; | |
8695 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
8696 | ||
40f46283 DL |
8697 | tiling = val & PLANE_CTL_TILED_MASK; |
8698 | switch (tiling) { | |
8699 | case PLANE_CTL_TILED_LINEAR: | |
8700 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
8701 | break; | |
8702 | case PLANE_CTL_TILED_X: | |
8703 | plane_config->tiling = I915_TILING_X; | |
8704 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
8705 | break; | |
8706 | case PLANE_CTL_TILED_Y: | |
8707 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
8708 | break; | |
8709 | case PLANE_CTL_TILED_YF: | |
8710 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
8711 | break; | |
8712 | default: | |
8713 | MISSING_CASE(tiling); | |
8714 | goto error; | |
8715 | } | |
8716 | ||
bc8d7dff DL |
8717 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8718 | plane_config->base = base; | |
8719 | ||
8720 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8721 | ||
8722 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8723 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8724 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8725 | ||
8726 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
8727 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
8728 | fb->pixel_format); | |
bc8d7dff DL |
8729 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8730 | ||
8731 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
8732 | fb->pixel_format, |
8733 | fb->modifier[0]); | |
bc8d7dff | 8734 | |
f37b5c2b | 8735 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8736 | |
8737 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8738 | pipe_name(pipe), fb->width, fb->height, | |
8739 | fb->bits_per_pixel, base, fb->pitches[0], | |
8740 | plane_config->size); | |
8741 | ||
2d14030b | 8742 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8743 | return; |
8744 | ||
8745 | error: | |
8746 | kfree(fb); | |
8747 | } | |
8748 | ||
2fa2fe9a | 8749 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8750 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8751 | { |
8752 | struct drm_device *dev = crtc->base.dev; | |
8753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8754 | uint32_t tmp; | |
8755 | ||
8756 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8757 | ||
8758 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8759 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8760 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8761 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8762 | |
8763 | /* We currently do not free assignements of panel fitters on | |
8764 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8765 | * differentiates them) so just WARN about this case for now. */ | |
8766 | if (IS_GEN7(dev)) { | |
8767 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
8768 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8769 | } | |
2fa2fe9a | 8770 | } |
79e53945 JB |
8771 | } |
8772 | ||
5724dbd1 DL |
8773 | static void |
8774 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8775 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8776 | { |
8777 | struct drm_device *dev = crtc->base.dev; | |
8778 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8779 | u32 val, base, offset; | |
aeee5a49 | 8780 | int pipe = crtc->pipe; |
4c6baa59 | 8781 | int fourcc, pixel_format; |
6761dd31 | 8782 | unsigned int aligned_height; |
b113d5ee | 8783 | struct drm_framebuffer *fb; |
1b842c89 | 8784 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8785 | |
42a7b088 DL |
8786 | val = I915_READ(DSPCNTR(pipe)); |
8787 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8788 | return; | |
8789 | ||
d9806c9f | 8790 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8791 | if (!intel_fb) { |
4c6baa59 JB |
8792 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8793 | return; | |
8794 | } | |
8795 | ||
1b842c89 DL |
8796 | fb = &intel_fb->base; |
8797 | ||
18c5247e DV |
8798 | if (INTEL_INFO(dev)->gen >= 4) { |
8799 | if (val & DISPPLANE_TILED) { | |
49af449b | 8800 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8801 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8802 | } | |
8803 | } | |
4c6baa59 JB |
8804 | |
8805 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8806 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8807 | fb->pixel_format = fourcc; |
8808 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 8809 | |
aeee5a49 | 8810 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 8811 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 8812 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8813 | } else { |
49af449b | 8814 | if (plane_config->tiling) |
aeee5a49 | 8815 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8816 | else |
aeee5a49 | 8817 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8818 | } |
8819 | plane_config->base = base; | |
8820 | ||
8821 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8822 | fb->width = ((val >> 16) & 0xfff) + 1; |
8823 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8824 | |
8825 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8826 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8827 | |
b113d5ee | 8828 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8829 | fb->pixel_format, |
8830 | fb->modifier[0]); | |
4c6baa59 | 8831 | |
f37b5c2b | 8832 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8833 | |
2844a921 DL |
8834 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8835 | pipe_name(pipe), fb->width, fb->height, | |
8836 | fb->bits_per_pixel, base, fb->pitches[0], | |
8837 | plane_config->size); | |
b113d5ee | 8838 | |
2d14030b | 8839 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8840 | } |
8841 | ||
0e8ffe1b | 8842 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8843 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8844 | { |
8845 | struct drm_device *dev = crtc->base.dev; | |
8846 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8847 | uint32_t tmp; | |
8848 | ||
f458ebbc DV |
8849 | if (!intel_display_power_is_enabled(dev_priv, |
8850 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
8851 | return false; |
8852 | ||
e143a21c | 8853 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8854 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8855 | |
0e8ffe1b DV |
8856 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8857 | if (!(tmp & PIPECONF_ENABLE)) | |
8858 | return false; | |
8859 | ||
42571aef VS |
8860 | switch (tmp & PIPECONF_BPC_MASK) { |
8861 | case PIPECONF_6BPC: | |
8862 | pipe_config->pipe_bpp = 18; | |
8863 | break; | |
8864 | case PIPECONF_8BPC: | |
8865 | pipe_config->pipe_bpp = 24; | |
8866 | break; | |
8867 | case PIPECONF_10BPC: | |
8868 | pipe_config->pipe_bpp = 30; | |
8869 | break; | |
8870 | case PIPECONF_12BPC: | |
8871 | pipe_config->pipe_bpp = 36; | |
8872 | break; | |
8873 | default: | |
8874 | break; | |
8875 | } | |
8876 | ||
b5a9fa09 DV |
8877 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8878 | pipe_config->limited_color_range = true; | |
8879 | ||
ab9412ba | 8880 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
8881 | struct intel_shared_dpll *pll; |
8882 | ||
88adfff1 DV |
8883 | pipe_config->has_pch_encoder = true; |
8884 | ||
627eb5a3 DV |
8885 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8886 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8887 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8888 | |
8889 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8890 | |
c0d43d62 | 8891 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
8892 | pipe_config->shared_dpll = |
8893 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
8894 | } else { |
8895 | tmp = I915_READ(PCH_DPLL_SEL); | |
8896 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8897 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
8898 | else | |
8899 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
8900 | } | |
66e985c0 DV |
8901 | |
8902 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
8903 | ||
8904 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
8905 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8906 | |
8907 | tmp = pipe_config->dpll_hw_state.dpll; | |
8908 | pipe_config->pixel_multiplier = | |
8909 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8910 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8911 | |
8912 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8913 | } else { |
8914 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8915 | } |
8916 | ||
1bd1bd80 DV |
8917 | intel_get_pipe_timings(crtc, pipe_config); |
8918 | ||
2fa2fe9a DV |
8919 | ironlake_get_pfit_config(crtc, pipe_config); |
8920 | ||
0e8ffe1b DV |
8921 | return true; |
8922 | } | |
8923 | ||
be256dc7 PZ |
8924 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8925 | { | |
8926 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 8927 | struct intel_crtc *crtc; |
be256dc7 | 8928 | |
d3fcc808 | 8929 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8930 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8931 | pipe_name(crtc->pipe)); |
8932 | ||
e2c719b7 RC |
8933 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8934 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
8935 | I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
8936 | I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
8937 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); | |
8938 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 8939 | "CPU PWM1 enabled\n"); |
c5107b87 | 8940 | if (IS_HASWELL(dev)) |
e2c719b7 | 8941 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8942 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8943 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8944 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8945 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8946 | "Utility pin enabled\n"); |
e2c719b7 | 8947 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8948 | |
9926ada1 PZ |
8949 | /* |
8950 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8951 | * interrupts remain enabled. We used to check for that, but since it's | |
8952 | * gen-specific and since we only disable LCPLL after we fully disable | |
8953 | * the interrupts, the check below should be enough. | |
8954 | */ | |
e2c719b7 | 8955 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8956 | } |
8957 | ||
9ccd5aeb PZ |
8958 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8959 | { | |
8960 | struct drm_device *dev = dev_priv->dev; | |
8961 | ||
8962 | if (IS_HASWELL(dev)) | |
8963 | return I915_READ(D_COMP_HSW); | |
8964 | else | |
8965 | return I915_READ(D_COMP_BDW); | |
8966 | } | |
8967 | ||
3c4c9b81 PZ |
8968 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8969 | { | |
8970 | struct drm_device *dev = dev_priv->dev; | |
8971 | ||
8972 | if (IS_HASWELL(dev)) { | |
8973 | mutex_lock(&dev_priv->rps.hw_lock); | |
8974 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8975 | val)) | |
f475dadf | 8976 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8977 | mutex_unlock(&dev_priv->rps.hw_lock); |
8978 | } else { | |
9ccd5aeb PZ |
8979 | I915_WRITE(D_COMP_BDW, val); |
8980 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8981 | } |
be256dc7 PZ |
8982 | } |
8983 | ||
8984 | /* | |
8985 | * This function implements pieces of two sequences from BSpec: | |
8986 | * - Sequence for display software to disable LCPLL | |
8987 | * - Sequence for display software to allow package C8+ | |
8988 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8989 | * register. Callers should take care of disabling all the display engine | |
8990 | * functions, doing the mode unset, fixing interrupts, etc. | |
8991 | */ | |
6ff58d53 PZ |
8992 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8993 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8994 | { |
8995 | uint32_t val; | |
8996 | ||
8997 | assert_can_disable_lcpll(dev_priv); | |
8998 | ||
8999 | val = I915_READ(LCPLL_CTL); | |
9000 | ||
9001 | if (switch_to_fclk) { | |
9002 | val |= LCPLL_CD_SOURCE_FCLK; | |
9003 | I915_WRITE(LCPLL_CTL, val); | |
9004 | ||
9005 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9006 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9007 | DRM_ERROR("Switching to FCLK failed\n"); | |
9008 | ||
9009 | val = I915_READ(LCPLL_CTL); | |
9010 | } | |
9011 | ||
9012 | val |= LCPLL_PLL_DISABLE; | |
9013 | I915_WRITE(LCPLL_CTL, val); | |
9014 | POSTING_READ(LCPLL_CTL); | |
9015 | ||
9016 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9017 | DRM_ERROR("LCPLL still locked\n"); | |
9018 | ||
9ccd5aeb | 9019 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9020 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9021 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9022 | ndelay(100); |
9023 | ||
9ccd5aeb PZ |
9024 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9025 | 1)) | |
be256dc7 PZ |
9026 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9027 | ||
9028 | if (allow_power_down) { | |
9029 | val = I915_READ(LCPLL_CTL); | |
9030 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9031 | I915_WRITE(LCPLL_CTL, val); | |
9032 | POSTING_READ(LCPLL_CTL); | |
9033 | } | |
9034 | } | |
9035 | ||
9036 | /* | |
9037 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9038 | * source. | |
9039 | */ | |
6ff58d53 | 9040 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9041 | { |
9042 | uint32_t val; | |
9043 | ||
9044 | val = I915_READ(LCPLL_CTL); | |
9045 | ||
9046 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9047 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9048 | return; | |
9049 | ||
a8a8bd54 PZ |
9050 | /* |
9051 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9052 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9053 | */ |
59bad947 | 9054 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9055 | |
be256dc7 PZ |
9056 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9057 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9058 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9059 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9060 | } |
9061 | ||
9ccd5aeb | 9062 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9063 | val |= D_COMP_COMP_FORCE; |
9064 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9065 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9066 | |
9067 | val = I915_READ(LCPLL_CTL); | |
9068 | val &= ~LCPLL_PLL_DISABLE; | |
9069 | I915_WRITE(LCPLL_CTL, val); | |
9070 | ||
9071 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9072 | DRM_ERROR("LCPLL not locked yet\n"); | |
9073 | ||
9074 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9075 | val = I915_READ(LCPLL_CTL); | |
9076 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9077 | I915_WRITE(LCPLL_CTL, val); | |
9078 | ||
9079 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9080 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9081 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9082 | } | |
215733fa | 9083 | |
59bad947 | 9084 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
be256dc7 PZ |
9085 | } |
9086 | ||
765dab67 PZ |
9087 | /* |
9088 | * Package states C8 and deeper are really deep PC states that can only be | |
9089 | * reached when all the devices on the system allow it, so even if the graphics | |
9090 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9091 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9092 | * | |
9093 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9094 | * well is disabled and most interrupts are disabled, and these are also | |
9095 | * requirements for runtime PM. When these conditions are met, we manually do | |
9096 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9097 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9098 | * hang the machine. | |
9099 | * | |
9100 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9101 | * the state of some registers, so when we come back from PC8+ we need to | |
9102 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9103 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9104 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9105 | * because of the runtime PM support). | |
9106 | * | |
9107 | * For more, read "Display Sequences for Package C8" on the hardware | |
9108 | * documentation. | |
9109 | */ | |
a14cb6fc | 9110 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9111 | { |
c67a470b PZ |
9112 | struct drm_device *dev = dev_priv->dev; |
9113 | uint32_t val; | |
9114 | ||
c67a470b PZ |
9115 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9116 | ||
c67a470b PZ |
9117 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
9118 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9119 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9120 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9121 | } | |
9122 | ||
9123 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9124 | hsw_disable_lcpll(dev_priv, true, true); |
9125 | } | |
9126 | ||
a14cb6fc | 9127 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9128 | { |
9129 | struct drm_device *dev = dev_priv->dev; | |
9130 | uint32_t val; | |
9131 | ||
c67a470b PZ |
9132 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9133 | ||
9134 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9135 | lpt_init_pch_refclk(dev); |
9136 | ||
9137 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
9138 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
9139 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9140 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9141 | } | |
9142 | ||
9143 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9144 | } |
9145 | ||
f8437dd1 VK |
9146 | static void broxton_modeset_global_resources(struct drm_atomic_state *state) |
9147 | { | |
9148 | struct drm_device *dev = state->dev; | |
9149 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9150 | int max_pixclk = intel_mode_max_pixclk(state); | |
9151 | int req_cdclk; | |
9152 | ||
9153 | /* see the comment in valleyview_modeset_global_resources */ | |
9154 | if (WARN_ON(max_pixclk < 0)) | |
9155 | return; | |
9156 | ||
9157 | req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk); | |
9158 | ||
9159 | if (req_cdclk != dev_priv->cdclk_freq) | |
9160 | broxton_set_cdclk(dev, req_cdclk); | |
9161 | } | |
9162 | ||
190f68c5 ACO |
9163 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9164 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9165 | { |
190f68c5 | 9166 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9167 | return -EINVAL; |
716c2e55 | 9168 | |
c7653199 | 9169 | crtc->lowfreq_avail = false; |
644cef34 | 9170 | |
c8f7a0db | 9171 | return 0; |
79e53945 JB |
9172 | } |
9173 | ||
3760b59c S |
9174 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9175 | enum port port, | |
9176 | struct intel_crtc_state *pipe_config) | |
9177 | { | |
9178 | switch (port) { | |
9179 | case PORT_A: | |
9180 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9181 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9182 | break; | |
9183 | case PORT_B: | |
9184 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9185 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9186 | break; | |
9187 | case PORT_C: | |
9188 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9189 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9190 | break; | |
9191 | default: | |
9192 | DRM_ERROR("Incorrect port type\n"); | |
9193 | } | |
9194 | } | |
9195 | ||
96b7dfb7 S |
9196 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9197 | enum port port, | |
5cec258b | 9198 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9199 | { |
3148ade7 | 9200 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9201 | |
9202 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9203 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9204 | ||
9205 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9206 | case SKL_DPLL0: |
9207 | /* | |
9208 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9209 | * of the shared DPLL framework and thus needs to be read out | |
9210 | * separately | |
9211 | */ | |
9212 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9213 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9214 | break; | |
96b7dfb7 S |
9215 | case SKL_DPLL1: |
9216 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9217 | break; | |
9218 | case SKL_DPLL2: | |
9219 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9220 | break; | |
9221 | case SKL_DPLL3: | |
9222 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9223 | break; | |
96b7dfb7 S |
9224 | } |
9225 | } | |
9226 | ||
7d2c8175 DL |
9227 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9228 | enum port port, | |
5cec258b | 9229 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9230 | { |
9231 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9232 | ||
9233 | switch (pipe_config->ddi_pll_sel) { | |
9234 | case PORT_CLK_SEL_WRPLL1: | |
9235 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9236 | break; | |
9237 | case PORT_CLK_SEL_WRPLL2: | |
9238 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9239 | break; | |
9240 | } | |
9241 | } | |
9242 | ||
26804afd | 9243 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9244 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9245 | { |
9246 | struct drm_device *dev = crtc->base.dev; | |
9247 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9248 | struct intel_shared_dpll *pll; |
26804afd DV |
9249 | enum port port; |
9250 | uint32_t tmp; | |
9251 | ||
9252 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9253 | ||
9254 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9255 | ||
96b7dfb7 S |
9256 | if (IS_SKYLAKE(dev)) |
9257 | skylake_get_ddi_pll(dev_priv, port, pipe_config); | |
3760b59c S |
9258 | else if (IS_BROXTON(dev)) |
9259 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9260 | else |
9261 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9262 | |
d452c5b6 DV |
9263 | if (pipe_config->shared_dpll >= 0) { |
9264 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9265 | ||
9266 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9267 | &pipe_config->dpll_hw_state)); | |
9268 | } | |
9269 | ||
26804afd DV |
9270 | /* |
9271 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9272 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9273 | * the PCH transcoder is on. | |
9274 | */ | |
ca370455 DL |
9275 | if (INTEL_INFO(dev)->gen < 9 && |
9276 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9277 | pipe_config->has_pch_encoder = true; |
9278 | ||
9279 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9280 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9281 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9282 | ||
9283 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9284 | } | |
9285 | } | |
9286 | ||
0e8ffe1b | 9287 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9288 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9289 | { |
9290 | struct drm_device *dev = crtc->base.dev; | |
9291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9292 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9293 | uint32_t tmp; |
9294 | ||
f458ebbc | 9295 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9296 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9297 | return false; | |
9298 | ||
e143a21c | 9299 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9300 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9301 | ||
eccb140b DV |
9302 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9303 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9304 | enum pipe trans_edp_pipe; | |
9305 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9306 | default: | |
9307 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9308 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9309 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9310 | trans_edp_pipe = PIPE_A; | |
9311 | break; | |
9312 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9313 | trans_edp_pipe = PIPE_B; | |
9314 | break; | |
9315 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9316 | trans_edp_pipe = PIPE_C; | |
9317 | break; | |
9318 | } | |
9319 | ||
9320 | if (trans_edp_pipe == crtc->pipe) | |
9321 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9322 | } | |
9323 | ||
f458ebbc | 9324 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9325 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9326 | return false; |
9327 | ||
eccb140b | 9328 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9329 | if (!(tmp & PIPECONF_ENABLE)) |
9330 | return false; | |
9331 | ||
26804afd | 9332 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9333 | |
1bd1bd80 DV |
9334 | intel_get_pipe_timings(crtc, pipe_config); |
9335 | ||
a1b2278e CK |
9336 | if (INTEL_INFO(dev)->gen >= 9) { |
9337 | skl_init_scalers(dev, crtc, pipe_config); | |
9338 | } | |
9339 | ||
2fa2fe9a | 9340 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
bd2e244f | 9341 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
ff6d9f55 | 9342 | if (INTEL_INFO(dev)->gen == 9) |
bd2e244f | 9343 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9344 | else if (INTEL_INFO(dev)->gen < 9) |
bd2e244f | 9345 | ironlake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 JB |
9346 | else |
9347 | MISSING_CASE(INTEL_INFO(dev)->gen); | |
9348 | ||
a1b2278e CK |
9349 | } else { |
9350 | pipe_config->scaler_state.scaler_id = -1; | |
9351 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f | 9352 | } |
88adfff1 | 9353 | |
e59150dc JB |
9354 | if (IS_HASWELL(dev)) |
9355 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
9356 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9357 | |
ebb69c95 CT |
9358 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
9359 | pipe_config->pixel_multiplier = | |
9360 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9361 | } else { | |
9362 | pipe_config->pixel_multiplier = 1; | |
9363 | } | |
6c49f241 | 9364 | |
0e8ffe1b DV |
9365 | return true; |
9366 | } | |
9367 | ||
560b85bb CW |
9368 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
9369 | { | |
9370 | struct drm_device *dev = crtc->dev; | |
9371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9372 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 9373 | uint32_t cntl = 0, size = 0; |
560b85bb | 9374 | |
dc41c154 | 9375 | if (base) { |
3dd512fb MR |
9376 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
9377 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
9378 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9379 | ||
9380 | switch (stride) { | |
9381 | default: | |
9382 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9383 | width, stride); | |
9384 | stride = 256; | |
9385 | /* fallthrough */ | |
9386 | case 256: | |
9387 | case 512: | |
9388 | case 1024: | |
9389 | case 2048: | |
9390 | break; | |
4b0e333e CW |
9391 | } |
9392 | ||
dc41c154 VS |
9393 | cntl |= CURSOR_ENABLE | |
9394 | CURSOR_GAMMA_ENABLE | | |
9395 | CURSOR_FORMAT_ARGB | | |
9396 | CURSOR_STRIDE(stride); | |
9397 | ||
9398 | size = (height << 12) | width; | |
4b0e333e | 9399 | } |
560b85bb | 9400 | |
dc41c154 VS |
9401 | if (intel_crtc->cursor_cntl != 0 && |
9402 | (intel_crtc->cursor_base != base || | |
9403 | intel_crtc->cursor_size != size || | |
9404 | intel_crtc->cursor_cntl != cntl)) { | |
9405 | /* On these chipsets we can only modify the base/size/stride | |
9406 | * whilst the cursor is disabled. | |
9407 | */ | |
9408 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 9409 | POSTING_READ(_CURACNTR); |
dc41c154 | 9410 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9411 | } |
560b85bb | 9412 | |
99d1f387 | 9413 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 9414 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
9415 | intel_crtc->cursor_base = base; |
9416 | } | |
4726e0b0 | 9417 | |
dc41c154 VS |
9418 | if (intel_crtc->cursor_size != size) { |
9419 | I915_WRITE(CURSIZE, size); | |
9420 | intel_crtc->cursor_size = size; | |
4b0e333e | 9421 | } |
560b85bb | 9422 | |
4b0e333e | 9423 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
9424 | I915_WRITE(_CURACNTR, cntl); |
9425 | POSTING_READ(_CURACNTR); | |
4b0e333e | 9426 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9427 | } |
560b85bb CW |
9428 | } |
9429 | ||
560b85bb | 9430 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
9431 | { |
9432 | struct drm_device *dev = crtc->dev; | |
9433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9435 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
9436 | uint32_t cntl; |
9437 | ||
9438 | cntl = 0; | |
9439 | if (base) { | |
9440 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 9441 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
9442 | case 64: |
9443 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9444 | break; | |
9445 | case 128: | |
9446 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9447 | break; | |
9448 | case 256: | |
9449 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9450 | break; | |
9451 | default: | |
3dd512fb | 9452 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 9453 | return; |
65a21cd6 | 9454 | } |
4b0e333e | 9455 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 VS |
9456 | |
9457 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
9458 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
4b0e333e | 9459 | } |
65a21cd6 | 9460 | |
8e7d688b | 9461 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
9462 | cntl |= CURSOR_ROTATE_180; |
9463 | ||
4b0e333e CW |
9464 | if (intel_crtc->cursor_cntl != cntl) { |
9465 | I915_WRITE(CURCNTR(pipe), cntl); | |
9466 | POSTING_READ(CURCNTR(pipe)); | |
9467 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9468 | } |
4b0e333e | 9469 | |
65a21cd6 | 9470 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9471 | I915_WRITE(CURBASE(pipe), base); |
9472 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9473 | |
9474 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9475 | } |
9476 | ||
cda4b7d3 | 9477 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
9478 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
9479 | bool on) | |
cda4b7d3 CW |
9480 | { |
9481 | struct drm_device *dev = crtc->dev; | |
9482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9483 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9484 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
9485 | int x = crtc->cursor_x; |
9486 | int y = crtc->cursor_y; | |
d6e4db15 | 9487 | u32 base = 0, pos = 0; |
cda4b7d3 | 9488 | |
d6e4db15 | 9489 | if (on) |
cda4b7d3 | 9490 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 9491 | |
6e3c9717 | 9492 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
9493 | base = 0; |
9494 | ||
6e3c9717 | 9495 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
9496 | base = 0; |
9497 | ||
9498 | if (x < 0) { | |
3dd512fb | 9499 | if (x + intel_crtc->base.cursor->state->crtc_w <= 0) |
cda4b7d3 CW |
9500 | base = 0; |
9501 | ||
9502 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9503 | x = -x; | |
9504 | } | |
9505 | pos |= x << CURSOR_X_SHIFT; | |
9506 | ||
9507 | if (y < 0) { | |
3dd512fb | 9508 | if (y + intel_crtc->base.cursor->state->crtc_h <= 0) |
cda4b7d3 CW |
9509 | base = 0; |
9510 | ||
9511 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9512 | y = -y; | |
9513 | } | |
9514 | pos |= y << CURSOR_Y_SHIFT; | |
9515 | ||
4b0e333e | 9516 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
9517 | return; |
9518 | ||
5efb3e28 VS |
9519 | I915_WRITE(CURPOS(pipe), pos); |
9520 | ||
4398ad45 VS |
9521 | /* ILK+ do this automagically */ |
9522 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 9523 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
3dd512fb MR |
9524 | base += (intel_crtc->base.cursor->state->crtc_h * |
9525 | intel_crtc->base.cursor->state->crtc_w - 1) * 4; | |
4398ad45 VS |
9526 | } |
9527 | ||
8ac54669 | 9528 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
9529 | i845_update_cursor(crtc, base); |
9530 | else | |
9531 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
9532 | } |
9533 | ||
dc41c154 VS |
9534 | static bool cursor_size_ok(struct drm_device *dev, |
9535 | uint32_t width, uint32_t height) | |
9536 | { | |
9537 | if (width == 0 || height == 0) | |
9538 | return false; | |
9539 | ||
9540 | /* | |
9541 | * 845g/865g are special in that they are only limited by | |
9542 | * the width of their cursors, the height is arbitrary up to | |
9543 | * the precision of the register. Everything else requires | |
9544 | * square cursors, limited to a few power-of-two sizes. | |
9545 | */ | |
9546 | if (IS_845G(dev) || IS_I865G(dev)) { | |
9547 | if ((width & 63) != 0) | |
9548 | return false; | |
9549 | ||
9550 | if (width > (IS_845G(dev) ? 64 : 512)) | |
9551 | return false; | |
9552 | ||
9553 | if (height > 1023) | |
9554 | return false; | |
9555 | } else { | |
9556 | switch (width | height) { | |
9557 | case 256: | |
9558 | case 128: | |
9559 | if (IS_GEN2(dev)) | |
9560 | return false; | |
9561 | case 64: | |
9562 | break; | |
9563 | default: | |
9564 | return false; | |
9565 | } | |
9566 | } | |
9567 | ||
9568 | return true; | |
9569 | } | |
9570 | ||
79e53945 | 9571 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 9572 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 9573 | { |
7203425a | 9574 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 9575 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 9576 | |
7203425a | 9577 | for (i = start; i < end; i++) { |
79e53945 JB |
9578 | intel_crtc->lut_r[i] = red[i] >> 8; |
9579 | intel_crtc->lut_g[i] = green[i] >> 8; | |
9580 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
9581 | } | |
9582 | ||
9583 | intel_crtc_load_lut(crtc); | |
9584 | } | |
9585 | ||
79e53945 JB |
9586 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9587 | static struct drm_display_mode load_detect_mode = { | |
9588 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9589 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9590 | }; | |
9591 | ||
a8bb6818 DV |
9592 | struct drm_framebuffer * |
9593 | __intel_framebuffer_create(struct drm_device *dev, | |
9594 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9595 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
9596 | { |
9597 | struct intel_framebuffer *intel_fb; | |
9598 | int ret; | |
9599 | ||
9600 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
9601 | if (!intel_fb) { | |
6ccb81f2 | 9602 | drm_gem_object_unreference(&obj->base); |
d2dff872 CW |
9603 | return ERR_PTR(-ENOMEM); |
9604 | } | |
9605 | ||
9606 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
9607 | if (ret) |
9608 | goto err; | |
d2dff872 CW |
9609 | |
9610 | return &intel_fb->base; | |
dd4916c5 | 9611 | err: |
6ccb81f2 | 9612 | drm_gem_object_unreference(&obj->base); |
dd4916c5 DV |
9613 | kfree(intel_fb); |
9614 | ||
9615 | return ERR_PTR(ret); | |
d2dff872 CW |
9616 | } |
9617 | ||
b5ea642a | 9618 | static struct drm_framebuffer * |
a8bb6818 DV |
9619 | intel_framebuffer_create(struct drm_device *dev, |
9620 | struct drm_mode_fb_cmd2 *mode_cmd, | |
9621 | struct drm_i915_gem_object *obj) | |
9622 | { | |
9623 | struct drm_framebuffer *fb; | |
9624 | int ret; | |
9625 | ||
9626 | ret = i915_mutex_lock_interruptible(dev); | |
9627 | if (ret) | |
9628 | return ERR_PTR(ret); | |
9629 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
9630 | mutex_unlock(&dev->struct_mutex); | |
9631 | ||
9632 | return fb; | |
9633 | } | |
9634 | ||
d2dff872 CW |
9635 | static u32 |
9636 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9637 | { | |
9638 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9639 | return ALIGN(pitch, 64); | |
9640 | } | |
9641 | ||
9642 | static u32 | |
9643 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9644 | { | |
9645 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9646 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9647 | } |
9648 | ||
9649 | static struct drm_framebuffer * | |
9650 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9651 | struct drm_display_mode *mode, | |
9652 | int depth, int bpp) | |
9653 | { | |
9654 | struct drm_i915_gem_object *obj; | |
0fed39bd | 9655 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
9656 | |
9657 | obj = i915_gem_alloc_object(dev, | |
9658 | intel_framebuffer_size_for_mode(mode, bpp)); | |
9659 | if (obj == NULL) | |
9660 | return ERR_PTR(-ENOMEM); | |
9661 | ||
9662 | mode_cmd.width = mode->hdisplay; | |
9663 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9664 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9665 | bpp); | |
5ca0c34a | 9666 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
9667 | |
9668 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
9669 | } | |
9670 | ||
9671 | static struct drm_framebuffer * | |
9672 | mode_fits_in_fbdev(struct drm_device *dev, | |
9673 | struct drm_display_mode *mode) | |
9674 | { | |
4520f53a | 9675 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
9676 | struct drm_i915_private *dev_priv = dev->dev_private; |
9677 | struct drm_i915_gem_object *obj; | |
9678 | struct drm_framebuffer *fb; | |
9679 | ||
4c0e5528 | 9680 | if (!dev_priv->fbdev) |
d2dff872 CW |
9681 | return NULL; |
9682 | ||
4c0e5528 | 9683 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9684 | return NULL; |
9685 | ||
4c0e5528 DV |
9686 | obj = dev_priv->fbdev->fb->obj; |
9687 | BUG_ON(!obj); | |
9688 | ||
8bcd4553 | 9689 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
9690 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
9691 | fb->bits_per_pixel)) | |
d2dff872 CW |
9692 | return NULL; |
9693 | ||
01f2c773 | 9694 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9695 | return NULL; |
9696 | ||
9697 | return fb; | |
4520f53a DV |
9698 | #else |
9699 | return NULL; | |
9700 | #endif | |
d2dff872 CW |
9701 | } |
9702 | ||
d2434ab7 | 9703 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9704 | struct drm_display_mode *mode, |
51fd371b RC |
9705 | struct intel_load_detect_pipe *old, |
9706 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9707 | { |
9708 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9709 | struct intel_encoder *intel_encoder = |
9710 | intel_attached_encoder(connector); | |
79e53945 | 9711 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9712 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9713 | struct drm_crtc *crtc = NULL; |
9714 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 9715 | struct drm_framebuffer *fb; |
51fd371b | 9716 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 9717 | struct drm_atomic_state *state = NULL; |
944b0c76 | 9718 | struct drm_connector_state *connector_state; |
4be07317 | 9719 | struct intel_crtc_state *crtc_state; |
51fd371b | 9720 | int ret, i = -1; |
79e53945 | 9721 | |
d2dff872 | 9722 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9723 | connector->base.id, connector->name, |
8e329a03 | 9724 | encoder->base.id, encoder->name); |
d2dff872 | 9725 | |
51fd371b RC |
9726 | retry: |
9727 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9728 | if (ret) | |
9729 | goto fail_unlock; | |
6e9f798d | 9730 | |
79e53945 JB |
9731 | /* |
9732 | * Algorithm gets a little messy: | |
7a5e4805 | 9733 | * |
79e53945 JB |
9734 | * - if the connector already has an assigned crtc, use it (but make |
9735 | * sure it's on first) | |
7a5e4805 | 9736 | * |
79e53945 JB |
9737 | * - try to find the first unused crtc that can drive this connector, |
9738 | * and use that if we find one | |
79e53945 JB |
9739 | */ |
9740 | ||
9741 | /* See if we already have a CRTC for this connector */ | |
9742 | if (encoder->crtc) { | |
9743 | crtc = encoder->crtc; | |
8261b191 | 9744 | |
51fd371b | 9745 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de DV |
9746 | if (ret) |
9747 | goto fail_unlock; | |
9748 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
51fd371b RC |
9749 | if (ret) |
9750 | goto fail_unlock; | |
7b24056b | 9751 | |
24218aac | 9752 | old->dpms_mode = connector->dpms; |
8261b191 CW |
9753 | old->load_detect_temp = false; |
9754 | ||
9755 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
9756 | if (connector->dpms != DRM_MODE_DPMS_ON) |
9757 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 9758 | |
7173188d | 9759 | return true; |
79e53945 JB |
9760 | } |
9761 | ||
9762 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9763 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9764 | i++; |
9765 | if (!(encoder->possible_crtcs & (1 << i))) | |
9766 | continue; | |
83d65738 | 9767 | if (possible_crtc->state->enable) |
a459249c VS |
9768 | continue; |
9769 | /* This can occur when applying the pipe A quirk on resume. */ | |
9770 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
9771 | continue; | |
9772 | ||
9773 | crtc = possible_crtc; | |
9774 | break; | |
79e53945 JB |
9775 | } |
9776 | ||
9777 | /* | |
9778 | * If we didn't find an unused CRTC, don't use any. | |
9779 | */ | |
9780 | if (!crtc) { | |
7173188d | 9781 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 9782 | goto fail_unlock; |
79e53945 JB |
9783 | } |
9784 | ||
51fd371b RC |
9785 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
9786 | if (ret) | |
4d02e2de DV |
9787 | goto fail_unlock; |
9788 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); | |
9789 | if (ret) | |
51fd371b | 9790 | goto fail_unlock; |
fc303101 DV |
9791 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
9792 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
9793 | |
9794 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 | 9795 | intel_crtc->new_enabled = true; |
24218aac | 9796 | old->dpms_mode = connector->dpms; |
8261b191 | 9797 | old->load_detect_temp = true; |
d2dff872 | 9798 | old->release_fb = NULL; |
79e53945 | 9799 | |
83a57153 ACO |
9800 | state = drm_atomic_state_alloc(dev); |
9801 | if (!state) | |
9802 | return false; | |
9803 | ||
9804 | state->acquire_ctx = ctx; | |
9805 | ||
944b0c76 ACO |
9806 | connector_state = drm_atomic_get_connector_state(state, connector); |
9807 | if (IS_ERR(connector_state)) { | |
9808 | ret = PTR_ERR(connector_state); | |
9809 | goto fail; | |
9810 | } | |
9811 | ||
9812 | connector_state->crtc = crtc; | |
9813 | connector_state->best_encoder = &intel_encoder->base; | |
9814 | ||
4be07317 ACO |
9815 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9816 | if (IS_ERR(crtc_state)) { | |
9817 | ret = PTR_ERR(crtc_state); | |
9818 | goto fail; | |
9819 | } | |
9820 | ||
9821 | crtc_state->base.enable = true; | |
9822 | ||
6492711d CW |
9823 | if (!mode) |
9824 | mode = &load_detect_mode; | |
79e53945 | 9825 | |
d2dff872 CW |
9826 | /* We need a framebuffer large enough to accommodate all accesses |
9827 | * that the plane may generate whilst we perform load detection. | |
9828 | * We can not rely on the fbcon either being present (we get called | |
9829 | * during its initialisation to detect all boot displays, or it may | |
9830 | * not even exist) or that it is large enough to satisfy the | |
9831 | * requested mode. | |
9832 | */ | |
94352cf9 DV |
9833 | fb = mode_fits_in_fbdev(dev, mode); |
9834 | if (fb == NULL) { | |
d2dff872 | 9835 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
9836 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
9837 | old->release_fb = fb; | |
d2dff872 CW |
9838 | } else |
9839 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9840 | if (IS_ERR(fb)) { |
d2dff872 | 9841 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9842 | goto fail; |
79e53945 | 9843 | } |
79e53945 | 9844 | |
83a57153 | 9845 | if (intel_set_mode(crtc, mode, 0, 0, fb, state)) { |
6492711d | 9846 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
9847 | if (old->release_fb) |
9848 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 9849 | goto fail; |
79e53945 | 9850 | } |
9128b040 | 9851 | crtc->primary->crtc = crtc; |
7173188d | 9852 | |
79e53945 | 9853 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 9854 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 9855 | return true; |
412b61d8 VS |
9856 | |
9857 | fail: | |
83d65738 | 9858 | intel_crtc->new_enabled = crtc->state->enable; |
51fd371b | 9859 | fail_unlock: |
e5d958ef ACO |
9860 | drm_atomic_state_free(state); |
9861 | state = NULL; | |
83a57153 | 9862 | |
51fd371b RC |
9863 | if (ret == -EDEADLK) { |
9864 | drm_modeset_backoff(ctx); | |
9865 | goto retry; | |
9866 | } | |
9867 | ||
412b61d8 | 9868 | return false; |
79e53945 JB |
9869 | } |
9870 | ||
d2434ab7 | 9871 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9872 | struct intel_load_detect_pipe *old, |
9873 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9874 | { |
83a57153 | 9875 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
9876 | struct intel_encoder *intel_encoder = |
9877 | intel_attached_encoder(connector); | |
4ef69c7a | 9878 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 9879 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 9880 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 9881 | struct drm_atomic_state *state; |
944b0c76 | 9882 | struct drm_connector_state *connector_state; |
4be07317 | 9883 | struct intel_crtc_state *crtc_state; |
79e53945 | 9884 | |
d2dff872 | 9885 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9886 | connector->base.id, connector->name, |
8e329a03 | 9887 | encoder->base.id, encoder->name); |
d2dff872 | 9888 | |
8261b191 | 9889 | if (old->load_detect_temp) { |
83a57153 | 9890 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
9891 | if (!state) |
9892 | goto fail; | |
83a57153 ACO |
9893 | |
9894 | state->acquire_ctx = ctx; | |
9895 | ||
944b0c76 ACO |
9896 | connector_state = drm_atomic_get_connector_state(state, connector); |
9897 | if (IS_ERR(connector_state)) | |
9898 | goto fail; | |
9899 | ||
4be07317 ACO |
9900 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9901 | if (IS_ERR(crtc_state)) | |
9902 | goto fail; | |
9903 | ||
fc303101 DV |
9904 | to_intel_connector(connector)->new_encoder = NULL; |
9905 | intel_encoder->new_crtc = NULL; | |
412b61d8 | 9906 | intel_crtc->new_enabled = false; |
944b0c76 ACO |
9907 | |
9908 | connector_state->best_encoder = NULL; | |
9909 | connector_state->crtc = NULL; | |
9910 | ||
4be07317 ACO |
9911 | crtc_state->base.enable = false; |
9912 | ||
83a57153 ACO |
9913 | intel_set_mode(crtc, NULL, 0, 0, NULL, state); |
9914 | ||
9915 | drm_atomic_state_free(state); | |
d2dff872 | 9916 | |
36206361 DV |
9917 | if (old->release_fb) { |
9918 | drm_framebuffer_unregister_private(old->release_fb); | |
9919 | drm_framebuffer_unreference(old->release_fb); | |
9920 | } | |
d2dff872 | 9921 | |
0622a53c | 9922 | return; |
79e53945 JB |
9923 | } |
9924 | ||
c751ce4f | 9925 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
9926 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
9927 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
9928 | |
9929 | return; | |
9930 | fail: | |
9931 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
9932 | drm_atomic_state_free(state); | |
79e53945 JB |
9933 | } |
9934 | ||
da4a1efa | 9935 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9936 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
9937 | { |
9938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9939 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
9940 | ||
9941 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9942 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
9943 | else if (HAS_PCH_SPLIT(dev)) |
9944 | return 120000; | |
9945 | else if (!IS_GEN2(dev)) | |
9946 | return 96000; | |
9947 | else | |
9948 | return 48000; | |
9949 | } | |
9950 | ||
79e53945 | 9951 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9952 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9953 | struct intel_crtc_state *pipe_config) |
79e53945 | 9954 | { |
f1f644dc | 9955 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 9956 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 9957 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9958 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
9959 | u32 fp; |
9960 | intel_clock_t clock; | |
da4a1efa | 9961 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9962 | |
9963 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9964 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9965 | else |
293623f7 | 9966 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9967 | |
9968 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
9969 | if (IS_PINEVIEW(dev)) { |
9970 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
9971 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9972 | } else { |
9973 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9974 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9975 | } | |
9976 | ||
a6c45cf0 | 9977 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
9978 | if (IS_PINEVIEW(dev)) |
9979 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
9980 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9981 | else |
9982 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9983 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9984 | ||
9985 | switch (dpll & DPLL_MODE_MASK) { | |
9986 | case DPLLB_MODE_DAC_SERIAL: | |
9987 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9988 | 5 : 10; | |
9989 | break; | |
9990 | case DPLLB_MODE_LVDS: | |
9991 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9992 | 7 : 14; | |
9993 | break; | |
9994 | default: | |
28c97730 | 9995 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9996 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9997 | return; |
79e53945 JB |
9998 | } |
9999 | ||
ac58c3f0 | 10000 | if (IS_PINEVIEW(dev)) |
da4a1efa | 10001 | pineview_clock(refclk, &clock); |
ac58c3f0 | 10002 | else |
da4a1efa | 10003 | i9xx_clock(refclk, &clock); |
79e53945 | 10004 | } else { |
0fb58223 | 10005 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10006 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10007 | |
10008 | if (is_lvds) { | |
10009 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10010 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10011 | |
10012 | if (lvds & LVDS_CLKB_POWER_UP) | |
10013 | clock.p2 = 7; | |
10014 | else | |
10015 | clock.p2 = 14; | |
79e53945 JB |
10016 | } else { |
10017 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10018 | clock.p1 = 2; | |
10019 | else { | |
10020 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10021 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10022 | } | |
10023 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10024 | clock.p2 = 4; | |
10025 | else | |
10026 | clock.p2 = 2; | |
79e53945 | 10027 | } |
da4a1efa VS |
10028 | |
10029 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
10030 | } |
10031 | ||
18442d08 VS |
10032 | /* |
10033 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10034 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10035 | * encoder's get_config() function. |
10036 | */ | |
10037 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
10038 | } |
10039 | ||
6878da05 VS |
10040 | int intel_dotclock_calculate(int link_freq, |
10041 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10042 | { |
f1f644dc JB |
10043 | /* |
10044 | * The calculation for the data clock is: | |
1041a02f | 10045 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10046 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10047 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10048 | * |
10049 | * and the link clock is simpler: | |
1041a02f | 10050 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10051 | */ |
10052 | ||
6878da05 VS |
10053 | if (!m_n->link_n) |
10054 | return 0; | |
f1f644dc | 10055 | |
6878da05 VS |
10056 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10057 | } | |
f1f644dc | 10058 | |
18442d08 | 10059 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10060 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10061 | { |
10062 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10063 | |
18442d08 VS |
10064 | /* read out port_clock from the DPLL */ |
10065 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10066 | |
f1f644dc | 10067 | /* |
18442d08 | 10068 | * This value does not include pixel_multiplier. |
241bfc38 | 10069 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10070 | * agree once we know their relationship in the encoder's |
10071 | * get_config() function. | |
79e53945 | 10072 | */ |
2d112de7 | 10073 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10074 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10075 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10076 | } |
10077 | ||
10078 | /** Returns the currently programmed mode of the given pipe. */ | |
10079 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10080 | struct drm_crtc *crtc) | |
10081 | { | |
548f245b | 10082 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10083 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10084 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10085 | struct drm_display_mode *mode; |
5cec258b | 10086 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10087 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10088 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10089 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10090 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10091 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10092 | |
10093 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10094 | if (!mode) | |
10095 | return NULL; | |
10096 | ||
f1f644dc JB |
10097 | /* |
10098 | * Construct a pipe_config sufficient for getting the clock info | |
10099 | * back out of crtc_clock_get. | |
10100 | * | |
10101 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10102 | * to use a real value here instead. | |
10103 | */ | |
293623f7 | 10104 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10105 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10106 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10107 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10108 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10109 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10110 | ||
773ae034 | 10111 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10112 | mode->hdisplay = (htot & 0xffff) + 1; |
10113 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10114 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10115 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10116 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10117 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10118 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10119 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10120 | ||
10121 | drm_mode_set_name(mode); | |
79e53945 JB |
10122 | |
10123 | return mode; | |
10124 | } | |
10125 | ||
652c393a JB |
10126 | static void intel_decrease_pllclock(struct drm_crtc *crtc) |
10127 | { | |
10128 | struct drm_device *dev = crtc->dev; | |
fbee40df | 10129 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 10131 | |
baff296c | 10132 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
10133 | return; |
10134 | ||
10135 | if (!dev_priv->lvds_downclock_avail) | |
10136 | return; | |
10137 | ||
10138 | /* | |
10139 | * Since this is called by a timer, we should never get here in | |
10140 | * the manual case. | |
10141 | */ | |
10142 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
10143 | int pipe = intel_crtc->pipe; |
10144 | int dpll_reg = DPLL(pipe); | |
10145 | int dpll; | |
f6e5b160 | 10146 | |
44d98a61 | 10147 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 10148 | |
8ac5a6d5 | 10149 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 10150 | |
dc257cf1 | 10151 | dpll = I915_READ(dpll_reg); |
652c393a JB |
10152 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
10153 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 10154 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
10155 | dpll = I915_READ(dpll_reg); |
10156 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 10157 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
10158 | } |
10159 | ||
10160 | } | |
10161 | ||
f047e395 CW |
10162 | void intel_mark_busy(struct drm_device *dev) |
10163 | { | |
c67a470b PZ |
10164 | struct drm_i915_private *dev_priv = dev->dev_private; |
10165 | ||
f62a0076 CW |
10166 | if (dev_priv->mm.busy) |
10167 | return; | |
10168 | ||
43694d69 | 10169 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10170 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10171 | if (INTEL_INFO(dev)->gen >= 6) |
10172 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10173 | dev_priv->mm.busy = true; |
f047e395 CW |
10174 | } |
10175 | ||
10176 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10177 | { |
c67a470b | 10178 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10179 | struct drm_crtc *crtc; |
652c393a | 10180 | |
f62a0076 CW |
10181 | if (!dev_priv->mm.busy) |
10182 | return; | |
10183 | ||
10184 | dev_priv->mm.busy = false; | |
10185 | ||
70e1e0ec | 10186 | for_each_crtc(dev, crtc) { |
f4510a27 | 10187 | if (!crtc->primary->fb) |
652c393a JB |
10188 | continue; |
10189 | ||
725a5b54 | 10190 | intel_decrease_pllclock(crtc); |
652c393a | 10191 | } |
b29c19b6 | 10192 | |
3d13ef2e | 10193 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10194 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10195 | |
43694d69 | 10196 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10197 | } |
10198 | ||
f5de6e07 ACO |
10199 | static void intel_crtc_set_state(struct intel_crtc *crtc, |
10200 | struct intel_crtc_state *crtc_state) | |
10201 | { | |
10202 | kfree(crtc->config); | |
10203 | crtc->config = crtc_state; | |
16f3f658 | 10204 | crtc->base.state = &crtc_state->base; |
f5de6e07 ACO |
10205 | } |
10206 | ||
79e53945 JB |
10207 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10208 | { | |
10209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10210 | struct drm_device *dev = crtc->dev; |
10211 | struct intel_unpin_work *work; | |
67e77c5a | 10212 | |
5e2d7afc | 10213 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10214 | work = intel_crtc->unpin_work; |
10215 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10216 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10217 | |
10218 | if (work) { | |
10219 | cancel_work_sync(&work->work); | |
10220 | kfree(work); | |
10221 | } | |
79e53945 | 10222 | |
f5de6e07 | 10223 | intel_crtc_set_state(intel_crtc, NULL); |
79e53945 | 10224 | drm_crtc_cleanup(crtc); |
67e77c5a | 10225 | |
79e53945 JB |
10226 | kfree(intel_crtc); |
10227 | } | |
10228 | ||
6b95a207 KH |
10229 | static void intel_unpin_work_fn(struct work_struct *__work) |
10230 | { | |
10231 | struct intel_unpin_work *work = | |
10232 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 10233 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 10234 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 10235 | |
b4a98e57 | 10236 | mutex_lock(&dev->struct_mutex); |
82bc3b2d | 10237 | intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state); |
05394f39 | 10238 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10239 | |
7ff0ebcc | 10240 | intel_fbc_update(dev); |
f06cc1b9 JH |
10241 | |
10242 | if (work->flip_queued_req) | |
146d84f0 | 10243 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10244 | mutex_unlock(&dev->struct_mutex); |
10245 | ||
f99d7069 | 10246 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
89ed88ba | 10247 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10248 | |
b4a98e57 CW |
10249 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
10250 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
10251 | ||
6b95a207 KH |
10252 | kfree(work); |
10253 | } | |
10254 | ||
1afe3e9d | 10255 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10256 | struct drm_crtc *crtc) |
6b95a207 | 10257 | { |
6b95a207 KH |
10258 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10259 | struct intel_unpin_work *work; | |
6b95a207 KH |
10260 | unsigned long flags; |
10261 | ||
10262 | /* Ignore early vblank irqs */ | |
10263 | if (intel_crtc == NULL) | |
10264 | return; | |
10265 | ||
f326038a DV |
10266 | /* |
10267 | * This is called both by irq handlers and the reset code (to complete | |
10268 | * lost pageflips) so needs the full irqsave spinlocks. | |
10269 | */ | |
6b95a207 KH |
10270 | spin_lock_irqsave(&dev->event_lock, flags); |
10271 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10272 | |
10273 | /* Ensure we don't miss a work->pending update ... */ | |
10274 | smp_rmb(); | |
10275 | ||
10276 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10277 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10278 | return; | |
10279 | } | |
10280 | ||
d6bbafa1 | 10281 | page_flip_completed(intel_crtc); |
0af7e4df | 10282 | |
6b95a207 | 10283 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10284 | } |
10285 | ||
1afe3e9d JB |
10286 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10287 | { | |
fbee40df | 10288 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10289 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10290 | ||
49b14a5c | 10291 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10292 | } |
10293 | ||
10294 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10295 | { | |
fbee40df | 10296 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10297 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10298 | ||
49b14a5c | 10299 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10300 | } |
10301 | ||
75f7f3ec VS |
10302 | /* Is 'a' after or equal to 'b'? */ |
10303 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10304 | { | |
10305 | return !((a - b) & 0x80000000); | |
10306 | } | |
10307 | ||
10308 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10309 | { | |
10310 | struct drm_device *dev = crtc->base.dev; | |
10311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10312 | ||
bdfa7542 VS |
10313 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10314 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10315 | return true; | |
10316 | ||
75f7f3ec VS |
10317 | /* |
10318 | * The relevant registers doen't exist on pre-ctg. | |
10319 | * As the flip done interrupt doesn't trigger for mmio | |
10320 | * flips on gmch platforms, a flip count check isn't | |
10321 | * really needed there. But since ctg has the registers, | |
10322 | * include it in the check anyway. | |
10323 | */ | |
10324 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10325 | return true; | |
10326 | ||
10327 | /* | |
10328 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10329 | * used the same base address. In that case the mmio flip might | |
10330 | * have completed, but the CS hasn't even executed the flip yet. | |
10331 | * | |
10332 | * A flip count check isn't enough as the CS might have updated | |
10333 | * the base address just after start of vblank, but before we | |
10334 | * managed to process the interrupt. This means we'd complete the | |
10335 | * CS flip too soon. | |
10336 | * | |
10337 | * Combining both checks should get us a good enough result. It may | |
10338 | * still happen that the CS flip has been executed, but has not | |
10339 | * yet actually completed. But in case the base address is the same | |
10340 | * anyway, we don't really care. | |
10341 | */ | |
10342 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10343 | crtc->unpin_work->gtt_offset && | |
10344 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
10345 | crtc->unpin_work->flip_count); | |
10346 | } | |
10347 | ||
6b95a207 KH |
10348 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10349 | { | |
fbee40df | 10350 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10351 | struct intel_crtc *intel_crtc = |
10352 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10353 | unsigned long flags; | |
10354 | ||
f326038a DV |
10355 | |
10356 | /* | |
10357 | * This is called both by irq handlers and the reset code (to complete | |
10358 | * lost pageflips) so needs the full irqsave spinlocks. | |
10359 | * | |
10360 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10361 | * generate a page-flip completion irq, i.e. every modeset |
10362 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10363 | */ | |
6b95a207 | 10364 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10365 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10366 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10367 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10368 | } | |
10369 | ||
eba905b2 | 10370 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
10371 | { |
10372 | /* Ensure that the work item is consistent when activating it ... */ | |
10373 | smp_wmb(); | |
10374 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
10375 | /* and that it is marked active as soon as the irq could fire. */ | |
10376 | smp_wmb(); | |
10377 | } | |
10378 | ||
8c9f3aaf JB |
10379 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10380 | struct drm_crtc *crtc, | |
10381 | struct drm_framebuffer *fb, | |
ed8d1975 | 10382 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10383 | struct intel_engine_cs *ring, |
ed8d1975 | 10384 | uint32_t flags) |
8c9f3aaf | 10385 | { |
8c9f3aaf | 10386 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10387 | u32 flip_mask; |
10388 | int ret; | |
10389 | ||
6d90c952 | 10390 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10391 | if (ret) |
4fa62c89 | 10392 | return ret; |
8c9f3aaf JB |
10393 | |
10394 | /* Can't queue multiple flips, so wait for the previous | |
10395 | * one to finish before executing the next. | |
10396 | */ | |
10397 | if (intel_crtc->plane) | |
10398 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10399 | else | |
10400 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10401 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10402 | intel_ring_emit(ring, MI_NOOP); | |
10403 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
10404 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10405 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10406 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 10407 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
10408 | |
10409 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10410 | __intel_ring_advance(ring); |
83d4092b | 10411 | return 0; |
8c9f3aaf JB |
10412 | } |
10413 | ||
10414 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10415 | struct drm_crtc *crtc, | |
10416 | struct drm_framebuffer *fb, | |
ed8d1975 | 10417 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10418 | struct intel_engine_cs *ring, |
ed8d1975 | 10419 | uint32_t flags) |
8c9f3aaf | 10420 | { |
8c9f3aaf | 10421 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10422 | u32 flip_mask; |
10423 | int ret; | |
10424 | ||
6d90c952 | 10425 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 10426 | if (ret) |
4fa62c89 | 10427 | return ret; |
8c9f3aaf JB |
10428 | |
10429 | if (intel_crtc->plane) | |
10430 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10431 | else | |
10432 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
10433 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
10434 | intel_ring_emit(ring, MI_NOOP); | |
10435 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
10436 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10437 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10438 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
10439 | intel_ring_emit(ring, MI_NOOP); |
10440 | ||
e7d841ca | 10441 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 10442 | __intel_ring_advance(ring); |
83d4092b | 10443 | return 0; |
8c9f3aaf JB |
10444 | } |
10445 | ||
10446 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
10447 | struct drm_crtc *crtc, | |
10448 | struct drm_framebuffer *fb, | |
ed8d1975 | 10449 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10450 | struct intel_engine_cs *ring, |
ed8d1975 | 10451 | uint32_t flags) |
8c9f3aaf JB |
10452 | { |
10453 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10454 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10455 | uint32_t pf, pipesrc; | |
10456 | int ret; | |
10457 | ||
6d90c952 | 10458 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10459 | if (ret) |
4fa62c89 | 10460 | return ret; |
8c9f3aaf JB |
10461 | |
10462 | /* i965+ uses the linear or tiled offsets from the | |
10463 | * Display Registers (which do not change across a page-flip) | |
10464 | * so we need only reprogram the base address. | |
10465 | */ | |
6d90c952 DV |
10466 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10467 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10468 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 10469 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 10470 | obj->tiling_mode); |
8c9f3aaf JB |
10471 | |
10472 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10473 | * untested on non-native modes, so ignore it for now. | |
10474 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10475 | */ | |
10476 | pf = 0; | |
10477 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 10478 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10479 | |
10480 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10481 | __intel_ring_advance(ring); |
83d4092b | 10482 | return 0; |
8c9f3aaf JB |
10483 | } |
10484 | ||
10485 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
10486 | struct drm_crtc *crtc, | |
10487 | struct drm_framebuffer *fb, | |
ed8d1975 | 10488 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10489 | struct intel_engine_cs *ring, |
ed8d1975 | 10490 | uint32_t flags) |
8c9f3aaf JB |
10491 | { |
10492 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10493 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10494 | uint32_t pf, pipesrc; | |
10495 | int ret; | |
10496 | ||
6d90c952 | 10497 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 10498 | if (ret) |
4fa62c89 | 10499 | return ret; |
8c9f3aaf | 10500 | |
6d90c952 DV |
10501 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
10502 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
10503 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 10504 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 10505 | |
dc257cf1 DV |
10506 | /* Contrary to the suggestions in the documentation, |
10507 | * "Enable Panel Fitter" does not seem to be required when page | |
10508 | * flipping with a non-native mode, and worse causes a normal | |
10509 | * modeset to fail. | |
10510 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10511 | */ | |
10512 | pf = 0; | |
8c9f3aaf | 10513 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 10514 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
10515 | |
10516 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10517 | __intel_ring_advance(ring); |
83d4092b | 10518 | return 0; |
8c9f3aaf JB |
10519 | } |
10520 | ||
7c9017e5 JB |
10521 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10522 | struct drm_crtc *crtc, | |
10523 | struct drm_framebuffer *fb, | |
ed8d1975 | 10524 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10525 | struct intel_engine_cs *ring, |
ed8d1975 | 10526 | uint32_t flags) |
7c9017e5 | 10527 | { |
7c9017e5 | 10528 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 10529 | uint32_t plane_bit = 0; |
ffe74d75 CW |
10530 | int len, ret; |
10531 | ||
eba905b2 | 10532 | switch (intel_crtc->plane) { |
cb05d8de DV |
10533 | case PLANE_A: |
10534 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10535 | break; | |
10536 | case PLANE_B: | |
10537 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10538 | break; | |
10539 | case PLANE_C: | |
10540 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10541 | break; | |
10542 | default: | |
10543 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 10544 | return -ENODEV; |
cb05d8de DV |
10545 | } |
10546 | ||
ffe74d75 | 10547 | len = 4; |
f476828a | 10548 | if (ring->id == RCS) { |
ffe74d75 | 10549 | len += 6; |
f476828a DL |
10550 | /* |
10551 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10552 | * 48bits addresses, and we need a NOOP for the batch size to | |
10553 | * stay even. | |
10554 | */ | |
10555 | if (IS_GEN8(dev)) | |
10556 | len += 2; | |
10557 | } | |
ffe74d75 | 10558 | |
f66fab8e VS |
10559 | /* |
10560 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10561 | * "The full packet must be contained within the same cache line." | |
10562 | * | |
10563 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10564 | * cacheline, if we ever start emitting more commands before | |
10565 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10566 | * then do the cacheline alignment, and finally emit the | |
10567 | * MI_DISPLAY_FLIP. | |
10568 | */ | |
10569 | ret = intel_ring_cacheline_align(ring); | |
10570 | if (ret) | |
4fa62c89 | 10571 | return ret; |
f66fab8e | 10572 | |
ffe74d75 | 10573 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 10574 | if (ret) |
4fa62c89 | 10575 | return ret; |
7c9017e5 | 10576 | |
ffe74d75 CW |
10577 | /* Unmask the flip-done completion message. Note that the bspec says that |
10578 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10579 | * more than one flip event at any time (or ensure that one flip message | |
10580 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10581 | * Experimentation says that BCS works despite DERRMR masking all | |
10582 | * flip-done completion events and that unmasking all planes at once | |
10583 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10584 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10585 | */ | |
10586 | if (ring->id == RCS) { | |
10587 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
10588 | intel_ring_emit(ring, DERRMR); | |
10589 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10590 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10591 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
10592 | if (IS_GEN8(dev)) |
10593 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
10594 | MI_SRM_LRM_GLOBAL_GTT); | |
10595 | else | |
10596 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
10597 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
10598 | intel_ring_emit(ring, DERRMR); |
10599 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
10600 | if (IS_GEN8(dev)) { |
10601 | intel_ring_emit(ring, 0); | |
10602 | intel_ring_emit(ring, MI_NOOP); | |
10603 | } | |
ffe74d75 CW |
10604 | } |
10605 | ||
cb05d8de | 10606 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 10607 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 10608 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 10609 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
10610 | |
10611 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 10612 | __intel_ring_advance(ring); |
83d4092b | 10613 | return 0; |
7c9017e5 JB |
10614 | } |
10615 | ||
84c33a64 SG |
10616 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
10617 | struct drm_i915_gem_object *obj) | |
10618 | { | |
10619 | /* | |
10620 | * This is not being used for older platforms, because | |
10621 | * non-availability of flip done interrupt forces us to use | |
10622 | * CS flips. Older platforms derive flip done using some clever | |
10623 | * tricks involving the flip_pending status bits and vblank irqs. | |
10624 | * So using MMIO flips there would disrupt this mechanism. | |
10625 | */ | |
10626 | ||
8e09bf83 CW |
10627 | if (ring == NULL) |
10628 | return true; | |
10629 | ||
84c33a64 SG |
10630 | if (INTEL_INFO(ring->dev)->gen < 5) |
10631 | return false; | |
10632 | ||
10633 | if (i915.use_mmio_flip < 0) | |
10634 | return false; | |
10635 | else if (i915.use_mmio_flip > 0) | |
10636 | return true; | |
14bf993e OM |
10637 | else if (i915.enable_execlists) |
10638 | return true; | |
84c33a64 | 10639 | else |
41c52415 | 10640 | return ring != i915_gem_request_get_ring(obj->last_read_req); |
84c33a64 SG |
10641 | } |
10642 | ||
ff944564 DL |
10643 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc) |
10644 | { | |
10645 | struct drm_device *dev = intel_crtc->base.dev; | |
10646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10647 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 DL |
10648 | const enum pipe pipe = intel_crtc->pipe; |
10649 | u32 ctl, stride; | |
10650 | ||
10651 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10652 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
10653 | switch (fb->modifier[0]) { |
10654 | case DRM_FORMAT_MOD_NONE: | |
10655 | break; | |
10656 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 10657 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
10658 | break; |
10659 | case I915_FORMAT_MOD_Y_TILED: | |
10660 | ctl |= PLANE_CTL_TILED_Y; | |
10661 | break; | |
10662 | case I915_FORMAT_MOD_Yf_TILED: | |
10663 | ctl |= PLANE_CTL_TILED_YF; | |
10664 | break; | |
10665 | default: | |
10666 | MISSING_CASE(fb->modifier[0]); | |
10667 | } | |
ff944564 DL |
10668 | |
10669 | /* | |
10670 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
10671 | * linear buffers or in number of tiles for tiled buffers. | |
10672 | */ | |
2ebef630 TU |
10673 | stride = fb->pitches[0] / |
10674 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
10675 | fb->pixel_format); | |
ff944564 DL |
10676 | |
10677 | /* | |
10678 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10679 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10680 | */ | |
10681 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10682 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10683 | ||
10684 | I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset); | |
10685 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10686 | } | |
10687 | ||
10688 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc) | |
84c33a64 SG |
10689 | { |
10690 | struct drm_device *dev = intel_crtc->base.dev; | |
10691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10692 | struct intel_framebuffer *intel_fb = | |
10693 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
10694 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10695 | u32 dspcntr; | |
10696 | u32 reg; | |
10697 | ||
84c33a64 SG |
10698 | reg = DSPCNTR(intel_crtc->plane); |
10699 | dspcntr = I915_READ(reg); | |
10700 | ||
c5d97472 DL |
10701 | if (obj->tiling_mode != I915_TILING_NONE) |
10702 | dspcntr |= DISPPLANE_TILED; | |
10703 | else | |
10704 | dspcntr &= ~DISPPLANE_TILED; | |
10705 | ||
84c33a64 SG |
10706 | I915_WRITE(reg, dspcntr); |
10707 | ||
10708 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
10709 | intel_crtc->unpin_work->gtt_offset); | |
10710 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
84c33a64 | 10711 | |
ff944564 DL |
10712 | } |
10713 | ||
10714 | /* | |
10715 | * XXX: This is the temporary way to update the plane registers until we get | |
10716 | * around to using the usual plane update functions for MMIO flips | |
10717 | */ | |
10718 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
10719 | { | |
10720 | struct drm_device *dev = intel_crtc->base.dev; | |
10721 | bool atomic_update; | |
10722 | u32 start_vbl_count; | |
10723 | ||
10724 | intel_mark_page_flip_active(intel_crtc); | |
10725 | ||
10726 | atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count); | |
10727 | ||
10728 | if (INTEL_INFO(dev)->gen >= 9) | |
10729 | skl_do_mmio_flip(intel_crtc); | |
10730 | else | |
10731 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10732 | ilk_do_mmio_flip(intel_crtc); | |
10733 | ||
9362c7c5 ACO |
10734 | if (atomic_update) |
10735 | intel_pipe_update_end(intel_crtc, start_vbl_count); | |
84c33a64 SG |
10736 | } |
10737 | ||
9362c7c5 | 10738 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 10739 | { |
cc8c4cc2 | 10740 | struct intel_crtc *crtc = |
9362c7c5 | 10741 | container_of(work, struct intel_crtc, mmio_flip.work); |
cc8c4cc2 | 10742 | struct intel_mmio_flip *mmio_flip; |
84c33a64 | 10743 | |
cc8c4cc2 JH |
10744 | mmio_flip = &crtc->mmio_flip; |
10745 | if (mmio_flip->req) | |
9c654818 JH |
10746 | WARN_ON(__i915_wait_request(mmio_flip->req, |
10747 | crtc->reset_counter, | |
10748 | false, NULL, NULL) != 0); | |
84c33a64 | 10749 | |
cc8c4cc2 JH |
10750 | intel_do_mmio_flip(crtc); |
10751 | if (mmio_flip->req) { | |
10752 | mutex_lock(&crtc->base.dev->struct_mutex); | |
146d84f0 | 10753 | i915_gem_request_assign(&mmio_flip->req, NULL); |
cc8c4cc2 JH |
10754 | mutex_unlock(&crtc->base.dev->struct_mutex); |
10755 | } | |
84c33a64 SG |
10756 | } |
10757 | ||
10758 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
10759 | struct drm_crtc *crtc, | |
10760 | struct drm_framebuffer *fb, | |
10761 | struct drm_i915_gem_object *obj, | |
10762 | struct intel_engine_cs *ring, | |
10763 | uint32_t flags) | |
10764 | { | |
84c33a64 | 10765 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
84c33a64 | 10766 | |
cc8c4cc2 JH |
10767 | i915_gem_request_assign(&intel_crtc->mmio_flip.req, |
10768 | obj->last_write_req); | |
536f5b5e ACO |
10769 | |
10770 | schedule_work(&intel_crtc->mmio_flip.work); | |
84c33a64 | 10771 | |
84c33a64 SG |
10772 | return 0; |
10773 | } | |
10774 | ||
8c9f3aaf JB |
10775 | static int intel_default_queue_flip(struct drm_device *dev, |
10776 | struct drm_crtc *crtc, | |
10777 | struct drm_framebuffer *fb, | |
ed8d1975 | 10778 | struct drm_i915_gem_object *obj, |
a4872ba6 | 10779 | struct intel_engine_cs *ring, |
ed8d1975 | 10780 | uint32_t flags) |
8c9f3aaf JB |
10781 | { |
10782 | return -ENODEV; | |
10783 | } | |
10784 | ||
d6bbafa1 CW |
10785 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
10786 | struct drm_crtc *crtc) | |
10787 | { | |
10788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10789 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10790 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
10791 | u32 addr; | |
10792 | ||
10793 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
10794 | return true; | |
10795 | ||
10796 | if (!work->enable_stall_check) | |
10797 | return false; | |
10798 | ||
10799 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
10800 | if (work->flip_queued_req && |
10801 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
10802 | return false; |
10803 | ||
1e3feefd | 10804 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
10805 | } |
10806 | ||
1e3feefd | 10807 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
10808 | return false; |
10809 | ||
10810 | /* Potential stall - if we see that the flip has happened, | |
10811 | * assume a missed interrupt. */ | |
10812 | if (INTEL_INFO(dev)->gen >= 4) | |
10813 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10814 | else | |
10815 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10816 | ||
10817 | /* There is a potential issue here with a false positive after a flip | |
10818 | * to the same address. We could address this by checking for a | |
10819 | * non-incrementing frame counter. | |
10820 | */ | |
10821 | return addr == work->gtt_offset; | |
10822 | } | |
10823 | ||
10824 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
10825 | { | |
10826 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10827 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
10828 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 10829 | struct intel_unpin_work *work; |
f326038a | 10830 | |
6c51d46f | 10831 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
10832 | |
10833 | if (crtc == NULL) | |
10834 | return; | |
10835 | ||
f326038a | 10836 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
10837 | work = intel_crtc->unpin_work; |
10838 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 10839 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 10840 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 10841 | page_flip_completed(intel_crtc); |
6ad790c0 | 10842 | work = NULL; |
d6bbafa1 | 10843 | } |
6ad790c0 CW |
10844 | if (work != NULL && |
10845 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
10846 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 10847 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
10848 | } |
10849 | ||
6b95a207 KH |
10850 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10851 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
10852 | struct drm_pending_vblank_event *event, |
10853 | uint32_t page_flip_flags) | |
6b95a207 KH |
10854 | { |
10855 | struct drm_device *dev = crtc->dev; | |
10856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 10857 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 10858 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 10859 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 10860 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 10861 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 10862 | struct intel_unpin_work *work; |
a4872ba6 | 10863 | struct intel_engine_cs *ring; |
cf5d8a46 | 10864 | bool mmio_flip; |
52e68630 | 10865 | int ret; |
6b95a207 | 10866 | |
2ff8fde1 MR |
10867 | /* |
10868 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10869 | * check to be safe. In the future we may enable pageflipping from | |
10870 | * a disabled primary plane. | |
10871 | */ | |
10872 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10873 | return -EBUSY; | |
10874 | ||
e6a595d2 | 10875 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 10876 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
10877 | return -EINVAL; |
10878 | ||
10879 | /* | |
10880 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10881 | * Note that pitch changes could also affect these register. | |
10882 | */ | |
10883 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
10884 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10885 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
10886 | return -EINVAL; |
10887 | ||
f900db47 CW |
10888 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
10889 | goto out_hang; | |
10890 | ||
b14c5679 | 10891 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
10892 | if (work == NULL) |
10893 | return -ENOMEM; | |
10894 | ||
6b95a207 | 10895 | work->event = event; |
b4a98e57 | 10896 | work->crtc = crtc; |
ab8d6675 | 10897 | work->old_fb = old_fb; |
6b95a207 KH |
10898 | INIT_WORK(&work->work, intel_unpin_work_fn); |
10899 | ||
87b6b101 | 10900 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
10901 | if (ret) |
10902 | goto free_work; | |
10903 | ||
6b95a207 | 10904 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 10905 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 10906 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
10907 | /* Before declaring the flip queue wedged, check if |
10908 | * the hardware completed the operation behind our backs. | |
10909 | */ | |
10910 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
10911 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10912 | page_flip_completed(intel_crtc); | |
10913 | } else { | |
10914 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 10915 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 10916 | |
d6bbafa1 CW |
10917 | drm_crtc_vblank_put(crtc); |
10918 | kfree(work); | |
10919 | return -EBUSY; | |
10920 | } | |
6b95a207 KH |
10921 | } |
10922 | intel_crtc->unpin_work = work; | |
5e2d7afc | 10923 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 10924 | |
b4a98e57 CW |
10925 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
10926 | flush_workqueue(dev_priv->wq); | |
10927 | ||
75dfca80 | 10928 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 10929 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 10930 | drm_gem_object_reference(&obj->base); |
6b95a207 | 10931 | |
f4510a27 | 10932 | crtc->primary->fb = fb; |
afd65eb4 | 10933 | update_state_fb(crtc->primary); |
1ed1f968 | 10934 | |
e1f99ce6 | 10935 | work->pending_flip_obj = obj; |
e1f99ce6 | 10936 | |
89ed88ba CW |
10937 | ret = i915_mutex_lock_interruptible(dev); |
10938 | if (ret) | |
10939 | goto cleanup; | |
10940 | ||
b4a98e57 | 10941 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 10942 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 10943 | |
75f7f3ec | 10944 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 10945 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 10946 | |
4fa62c89 VS |
10947 | if (IS_VALLEYVIEW(dev)) { |
10948 | ring = &dev_priv->ring[BCS]; | |
ab8d6675 | 10949 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
10950 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10951 | ring = NULL; | |
48bf5b2d | 10952 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 10953 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 10954 | } else if (INTEL_INFO(dev)->gen >= 7) { |
41c52415 | 10955 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4fa62c89 VS |
10956 | if (ring == NULL || ring->id != RCS) |
10957 | ring = &dev_priv->ring[BCS]; | |
10958 | } else { | |
10959 | ring = &dev_priv->ring[RCS]; | |
10960 | } | |
10961 | ||
cf5d8a46 CW |
10962 | mmio_flip = use_mmio_flip(ring, obj); |
10963 | ||
10964 | /* When using CS flips, we want to emit semaphores between rings. | |
10965 | * However, when using mmio flips we will create a task to do the | |
10966 | * synchronisation, so all we want here is to pin the framebuffer | |
10967 | * into the display plane and skip any waits. | |
10968 | */ | |
82bc3b2d | 10969 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
cf5d8a46 CW |
10970 | crtc->primary->state, |
10971 | mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring); | |
8c9f3aaf JB |
10972 | if (ret) |
10973 | goto cleanup_pending; | |
6b95a207 | 10974 | |
121920fa TU |
10975 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj) |
10976 | + intel_crtc->dspaddr_offset; | |
4fa62c89 | 10977 | |
cf5d8a46 | 10978 | if (mmio_flip) { |
84c33a64 SG |
10979 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
10980 | page_flip_flags); | |
d6bbafa1 CW |
10981 | if (ret) |
10982 | goto cleanup_unpin; | |
10983 | ||
f06cc1b9 JH |
10984 | i915_gem_request_assign(&work->flip_queued_req, |
10985 | obj->last_write_req); | |
d6bbafa1 | 10986 | } else { |
84c33a64 | 10987 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
10988 | page_flip_flags); |
10989 | if (ret) | |
10990 | goto cleanup_unpin; | |
10991 | ||
f06cc1b9 JH |
10992 | i915_gem_request_assign(&work->flip_queued_req, |
10993 | intel_ring_get_request(ring)); | |
d6bbafa1 CW |
10994 | } |
10995 | ||
1e3feefd | 10996 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 10997 | work->enable_stall_check = true; |
4fa62c89 | 10998 | |
ab8d6675 | 10999 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a071fa00 DV |
11000 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
11001 | ||
7ff0ebcc | 11002 | intel_fbc_disable(dev); |
f99d7069 | 11003 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
11004 | mutex_unlock(&dev->struct_mutex); |
11005 | ||
e5510fac JB |
11006 | trace_i915_flip_request(intel_crtc->plane, obj); |
11007 | ||
6b95a207 | 11008 | return 0; |
96b099fd | 11009 | |
4fa62c89 | 11010 | cleanup_unpin: |
82bc3b2d | 11011 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11012 | cleanup_pending: |
b4a98e57 | 11013 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11014 | mutex_unlock(&dev->struct_mutex); |
11015 | cleanup: | |
f4510a27 | 11016 | crtc->primary->fb = old_fb; |
afd65eb4 | 11017 | update_state_fb(crtc->primary); |
89ed88ba CW |
11018 | |
11019 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11020 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11021 | |
5e2d7afc | 11022 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11023 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11024 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11025 | |
87b6b101 | 11026 | drm_crtc_vblank_put(crtc); |
7317c75e | 11027 | free_work: |
96b099fd CW |
11028 | kfree(work); |
11029 | ||
f900db47 CW |
11030 | if (ret == -EIO) { |
11031 | out_hang: | |
53a366b9 | 11032 | ret = intel_plane_restore(primary); |
f0d3dad3 | 11033 | if (ret == 0 && event) { |
5e2d7afc | 11034 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11035 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11036 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11037 | } |
f900db47 | 11038 | } |
96b099fd | 11039 | return ret; |
6b95a207 KH |
11040 | } |
11041 | ||
65b38e0d | 11042 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
11043 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
11044 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
11045 | .atomic_begin = intel_begin_crtc_commit, |
11046 | .atomic_flush = intel_finish_crtc_commit, | |
f6e5b160 CW |
11047 | }; |
11048 | ||
9a935856 DV |
11049 | /** |
11050 | * intel_modeset_update_staged_output_state | |
11051 | * | |
11052 | * Updates the staged output configuration state, e.g. after we've read out the | |
11053 | * current hw state. | |
11054 | */ | |
11055 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 11056 | { |
7668851f | 11057 | struct intel_crtc *crtc; |
9a935856 DV |
11058 | struct intel_encoder *encoder; |
11059 | struct intel_connector *connector; | |
f6e5b160 | 11060 | |
3a3371ff | 11061 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11062 | connector->new_encoder = |
11063 | to_intel_encoder(connector->base.encoder); | |
11064 | } | |
f6e5b160 | 11065 | |
b2784e15 | 11066 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11067 | encoder->new_crtc = |
11068 | to_intel_crtc(encoder->base.crtc); | |
11069 | } | |
7668851f | 11070 | |
d3fcc808 | 11071 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11072 | crtc->new_enabled = crtc->base.state->enable; |
7668851f | 11073 | } |
f6e5b160 CW |
11074 | } |
11075 | ||
d29b2f9d ACO |
11076 | /* Transitional helper to copy current connector/encoder state to |
11077 | * connector->state. This is needed so that code that is partially | |
11078 | * converted to atomic does the right thing. | |
11079 | */ | |
11080 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) | |
11081 | { | |
11082 | struct intel_connector *connector; | |
11083 | ||
11084 | for_each_intel_connector(dev, connector) { | |
11085 | if (connector->base.encoder) { | |
11086 | connector->base.state->best_encoder = | |
11087 | connector->base.encoder; | |
11088 | connector->base.state->crtc = | |
11089 | connector->base.encoder->crtc; | |
11090 | } else { | |
11091 | connector->base.state->best_encoder = NULL; | |
11092 | connector->base.state->crtc = NULL; | |
11093 | } | |
11094 | } | |
11095 | } | |
11096 | ||
9a935856 DV |
11097 | /** |
11098 | * intel_modeset_commit_output_state | |
11099 | * | |
11100 | * This function copies the stage display pipe configuration to the real one. | |
11101 | */ | |
11102 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
11103 | { | |
7668851f | 11104 | struct intel_crtc *crtc; |
9a935856 DV |
11105 | struct intel_encoder *encoder; |
11106 | struct intel_connector *connector; | |
f6e5b160 | 11107 | |
3a3371ff | 11108 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
11109 | connector->base.encoder = &connector->new_encoder->base; |
11110 | } | |
f6e5b160 | 11111 | |
b2784e15 | 11112 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11113 | encoder->base.crtc = &encoder->new_crtc->base; |
11114 | } | |
7668851f | 11115 | |
d3fcc808 | 11116 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 11117 | crtc->base.state->enable = crtc->new_enabled; |
7668851f VS |
11118 | crtc->base.enabled = crtc->new_enabled; |
11119 | } | |
d29b2f9d ACO |
11120 | |
11121 | intel_modeset_update_connector_atomic_state(dev); | |
9a935856 DV |
11122 | } |
11123 | ||
050f7aeb | 11124 | static void |
eba905b2 | 11125 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11126 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11127 | { |
11128 | int bpp = pipe_config->pipe_bpp; | |
11129 | ||
11130 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11131 | connector->base.base.id, | |
c23cc417 | 11132 | connector->base.name); |
050f7aeb DV |
11133 | |
11134 | /* Don't use an invalid EDID bpc value */ | |
11135 | if (connector->base.display_info.bpc && | |
11136 | connector->base.display_info.bpc * 3 < bpp) { | |
11137 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
11138 | bpp, connector->base.display_info.bpc*3); | |
11139 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
11140 | } | |
11141 | ||
11142 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
11143 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
11144 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
11145 | bpp); | |
11146 | pipe_config->pipe_bpp = 24; | |
11147 | } | |
11148 | } | |
11149 | ||
4e53c2e0 | 11150 | static int |
050f7aeb | 11151 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11152 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11153 | { |
050f7aeb | 11154 | struct drm_device *dev = crtc->base.dev; |
1486017f | 11155 | struct drm_atomic_state *state; |
da3ced29 ACO |
11156 | struct drm_connector *connector; |
11157 | struct drm_connector_state *connector_state; | |
1486017f | 11158 | int bpp, i; |
4e53c2e0 | 11159 | |
d328c9d7 | 11160 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev))) |
4e53c2e0 | 11161 | bpp = 10*3; |
d328c9d7 DV |
11162 | else if (INTEL_INFO(dev)->gen >= 5) |
11163 | bpp = 12*3; | |
11164 | else | |
11165 | bpp = 8*3; | |
11166 | ||
4e53c2e0 | 11167 | |
4e53c2e0 DV |
11168 | pipe_config->pipe_bpp = bpp; |
11169 | ||
1486017f ACO |
11170 | state = pipe_config->base.state; |
11171 | ||
4e53c2e0 | 11172 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11173 | for_each_connector_in_state(state, connector, connector_state, i) { |
11174 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11175 | continue; |
11176 | ||
da3ced29 ACO |
11177 | connected_sink_compute_bpp(to_intel_connector(connector), |
11178 | pipe_config); | |
4e53c2e0 DV |
11179 | } |
11180 | ||
11181 | return bpp; | |
11182 | } | |
11183 | ||
644db711 DV |
11184 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11185 | { | |
11186 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11187 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11188 | mode->crtc_clock, |
644db711 DV |
11189 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11190 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11191 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11192 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11193 | } | |
11194 | ||
c0b03411 | 11195 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11196 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11197 | const char *context) |
11198 | { | |
6a60cd87 CK |
11199 | struct drm_device *dev = crtc->base.dev; |
11200 | struct drm_plane *plane; | |
11201 | struct intel_plane *intel_plane; | |
11202 | struct intel_plane_state *state; | |
11203 | struct drm_framebuffer *fb; | |
11204 | ||
11205 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
11206 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
11207 | |
11208 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
11209 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
11210 | pipe_config->pipe_bpp, pipe_config->dither); | |
11211 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
11212 | pipe_config->has_pch_encoder, | |
11213 | pipe_config->fdi_lanes, | |
11214 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
11215 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
11216 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
11217 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11218 | pipe_config->has_dp_encoder, | |
11219 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
11220 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
11221 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
11222 | |
11223 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
11224 | pipe_config->has_dp_encoder, | |
11225 | pipe_config->dp_m2_n2.gmch_m, | |
11226 | pipe_config->dp_m2_n2.gmch_n, | |
11227 | pipe_config->dp_m2_n2.link_m, | |
11228 | pipe_config->dp_m2_n2.link_n, | |
11229 | pipe_config->dp_m2_n2.tu); | |
11230 | ||
55072d19 DV |
11231 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
11232 | pipe_config->has_audio, | |
11233 | pipe_config->has_infoframe); | |
11234 | ||
c0b03411 | 11235 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11236 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11237 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11238 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11239 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 11240 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
11241 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
11242 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
6a60cd87 CK |
11243 | DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers); |
11244 | DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users); | |
11245 | DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
11246 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
11247 | pipe_config->gmch_pfit.control, | |
11248 | pipe_config->gmch_pfit.pgm_ratios, | |
11249 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 11250 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 11251 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
11252 | pipe_config->pch_pfit.size, |
11253 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 11254 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 11255 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 CK |
11256 | |
11257 | DRM_DEBUG_KMS("planes on this crtc\n"); | |
11258 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
11259 | intel_plane = to_intel_plane(plane); | |
11260 | if (intel_plane->pipe != crtc->pipe) | |
11261 | continue; | |
11262 | ||
11263 | state = to_intel_plane_state(plane->state); | |
11264 | fb = state->base.fb; | |
11265 | if (!fb) { | |
11266 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
11267 | "disabled, scaler_id = %d\n", | |
11268 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11269 | plane->base.id, intel_plane->pipe, | |
11270 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
11271 | drm_plane_index(plane), state->scaler_id); | |
11272 | continue; | |
11273 | } | |
11274 | ||
11275 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
11276 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
11277 | plane->base.id, intel_plane->pipe, | |
11278 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
11279 | drm_plane_index(plane)); | |
11280 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
11281 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
11282 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
11283 | state->scaler_id, | |
11284 | state->src.x1 >> 16, state->src.y1 >> 16, | |
11285 | drm_rect_width(&state->src) >> 16, | |
11286 | drm_rect_height(&state->src) >> 16, | |
11287 | state->dst.x1, state->dst.y1, | |
11288 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
11289 | } | |
c0b03411 DV |
11290 | } |
11291 | ||
bc079e8b VS |
11292 | static bool encoders_cloneable(const struct intel_encoder *a, |
11293 | const struct intel_encoder *b) | |
accfc0c5 | 11294 | { |
bc079e8b VS |
11295 | /* masks could be asymmetric, so check both ways */ |
11296 | return a == b || (a->cloneable & (1 << b->type) && | |
11297 | b->cloneable & (1 << a->type)); | |
11298 | } | |
11299 | ||
98a221da ACO |
11300 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, |
11301 | struct intel_crtc *crtc, | |
bc079e8b VS |
11302 | struct intel_encoder *encoder) |
11303 | { | |
bc079e8b | 11304 | struct intel_encoder *source_encoder; |
da3ced29 | 11305 | struct drm_connector *connector; |
98a221da ACO |
11306 | struct drm_connector_state *connector_state; |
11307 | int i; | |
bc079e8b | 11308 | |
da3ced29 | 11309 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da | 11310 | if (connector_state->crtc != &crtc->base) |
bc079e8b VS |
11311 | continue; |
11312 | ||
98a221da ACO |
11313 | source_encoder = |
11314 | to_intel_encoder(connector_state->best_encoder); | |
bc079e8b VS |
11315 | if (!encoders_cloneable(encoder, source_encoder)) |
11316 | return false; | |
11317 | } | |
11318 | ||
11319 | return true; | |
11320 | } | |
11321 | ||
98a221da ACO |
11322 | static bool check_encoder_cloning(struct drm_atomic_state *state, |
11323 | struct intel_crtc *crtc) | |
bc079e8b | 11324 | { |
accfc0c5 | 11325 | struct intel_encoder *encoder; |
da3ced29 | 11326 | struct drm_connector *connector; |
98a221da ACO |
11327 | struct drm_connector_state *connector_state; |
11328 | int i; | |
accfc0c5 | 11329 | |
da3ced29 | 11330 | for_each_connector_in_state(state, connector, connector_state, i) { |
98a221da ACO |
11331 | if (connector_state->crtc != &crtc->base) |
11332 | continue; | |
11333 | ||
11334 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11335 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
bc079e8b | 11336 | return false; |
accfc0c5 DV |
11337 | } |
11338 | ||
bc079e8b | 11339 | return true; |
accfc0c5 DV |
11340 | } |
11341 | ||
5448a00d | 11342 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11343 | { |
5448a00d ACO |
11344 | struct drm_device *dev = state->dev; |
11345 | struct intel_encoder *encoder; | |
da3ced29 | 11346 | struct drm_connector *connector; |
5448a00d | 11347 | struct drm_connector_state *connector_state; |
00f0b378 | 11348 | unsigned int used_ports = 0; |
5448a00d | 11349 | int i; |
00f0b378 VS |
11350 | |
11351 | /* | |
11352 | * Walk the connector list instead of the encoder | |
11353 | * list to detect the problem on ddi platforms | |
11354 | * where there's just one encoder per digital port. | |
11355 | */ | |
da3ced29 | 11356 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 11357 | if (!connector_state->best_encoder) |
00f0b378 VS |
11358 | continue; |
11359 | ||
5448a00d ACO |
11360 | encoder = to_intel_encoder(connector_state->best_encoder); |
11361 | ||
11362 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11363 | |
11364 | switch (encoder->type) { | |
11365 | unsigned int port_mask; | |
11366 | case INTEL_OUTPUT_UNKNOWN: | |
11367 | if (WARN_ON(!HAS_DDI(dev))) | |
11368 | break; | |
11369 | case INTEL_OUTPUT_DISPLAYPORT: | |
11370 | case INTEL_OUTPUT_HDMI: | |
11371 | case INTEL_OUTPUT_EDP: | |
11372 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11373 | ||
11374 | /* the same port mustn't appear more than once */ | |
11375 | if (used_ports & port_mask) | |
11376 | return false; | |
11377 | ||
11378 | used_ports |= port_mask; | |
11379 | default: | |
11380 | break; | |
11381 | } | |
11382 | } | |
11383 | ||
11384 | return true; | |
11385 | } | |
11386 | ||
83a57153 ACO |
11387 | static void |
11388 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11389 | { | |
11390 | struct drm_crtc_state tmp_state; | |
663a3640 | 11391 | struct intel_crtc_scaler_state scaler_state; |
83a57153 | 11392 | |
663a3640 | 11393 | /* Clear only the intel specific part of the crtc state excluding scalers */ |
83a57153 | 11394 | tmp_state = crtc_state->base; |
663a3640 | 11395 | scaler_state = crtc_state->scaler_state; |
83a57153 ACO |
11396 | memset(crtc_state, 0, sizeof *crtc_state); |
11397 | crtc_state->base = tmp_state; | |
663a3640 | 11398 | crtc_state->scaler_state = scaler_state; |
83a57153 ACO |
11399 | } |
11400 | ||
548ee15b | 11401 | static int |
b8cecdf5 | 11402 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
83a57153 | 11403 | struct drm_display_mode *mode, |
548ee15b ACO |
11404 | struct drm_atomic_state *state, |
11405 | struct intel_crtc_state *pipe_config) | |
ee7b9f93 | 11406 | { |
7758a113 | 11407 | struct intel_encoder *encoder; |
da3ced29 | 11408 | struct drm_connector *connector; |
0b901879 | 11409 | struct drm_connector_state *connector_state; |
d328c9d7 | 11410 | int base_bpp, ret = -EINVAL; |
0b901879 | 11411 | int i; |
e29c22c0 | 11412 | bool retry = true; |
ee7b9f93 | 11413 | |
98a221da | 11414 | if (!check_encoder_cloning(state, to_intel_crtc(crtc))) { |
accfc0c5 | 11415 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
548ee15b | 11416 | return -EINVAL; |
accfc0c5 DV |
11417 | } |
11418 | ||
5448a00d | 11419 | if (!check_digital_port_conflicts(state)) { |
00f0b378 | 11420 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); |
548ee15b | 11421 | return -EINVAL; |
00f0b378 VS |
11422 | } |
11423 | ||
83a57153 | 11424 | clear_intel_crtc_state(pipe_config); |
7758a113 | 11425 | |
07878248 | 11426 | pipe_config->base.crtc = crtc; |
2d112de7 ACO |
11427 | drm_mode_copy(&pipe_config->base.adjusted_mode, mode); |
11428 | drm_mode_copy(&pipe_config->base.mode, mode); | |
37327abd | 11429 | |
e143a21c DV |
11430 | pipe_config->cpu_transcoder = |
11431 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 11432 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 11433 | |
2960bc9c ID |
11434 | /* |
11435 | * Sanitize sync polarity flags based on requested ones. If neither | |
11436 | * positive or negative polarity is requested, treat this as meaning | |
11437 | * negative polarity. | |
11438 | */ | |
2d112de7 | 11439 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11440 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11441 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11442 | |
2d112de7 | 11443 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11444 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11445 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11446 | |
050f7aeb DV |
11447 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
11448 | * plane pixel format and any sink constraints into account. Returns the | |
11449 | * source plane bpp so that dithering can be selected on mismatches | |
11450 | * after encoders and crtc also have had their say. */ | |
d328c9d7 DV |
11451 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11452 | pipe_config); | |
11453 | if (base_bpp < 0) | |
4e53c2e0 DV |
11454 | goto fail; |
11455 | ||
e41a56be VS |
11456 | /* |
11457 | * Determine the real pipe dimensions. Note that stereo modes can | |
11458 | * increase the actual pipe size due to the frame doubling and | |
11459 | * insertion of additional space for blanks between the frame. This | |
11460 | * is stored in the crtc timings. We use the requested mode to do this | |
11461 | * computation to clearly distinguish it from the adjusted mode, which | |
11462 | * can be changed by the connectors in the below retry loop. | |
11463 | */ | |
2d112de7 | 11464 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11465 | &pipe_config->pipe_src_w, |
11466 | &pipe_config->pipe_src_h); | |
e41a56be | 11467 | |
e29c22c0 | 11468 | encoder_retry: |
ef1b460d | 11469 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11470 | pipe_config->port_clock = 0; |
ef1b460d | 11471 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11472 | |
135c81b8 | 11473 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11474 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11475 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11476 | |
7758a113 DV |
11477 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11478 | * adjust it according to limitations or connector properties, and also | |
11479 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11480 | */ |
da3ced29 | 11481 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 11482 | if (connector_state->crtc != crtc) |
7758a113 | 11483 | continue; |
7ae89233 | 11484 | |
0b901879 ACO |
11485 | encoder = to_intel_encoder(connector_state->best_encoder); |
11486 | ||
efea6e8e DV |
11487 | if (!(encoder->compute_config(encoder, pipe_config))) { |
11488 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
11489 | goto fail; |
11490 | } | |
ee7b9f93 | 11491 | } |
47f1c6c9 | 11492 | |
ff9a6750 DV |
11493 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11494 | * done afterwards in case the encoder adjusts the mode. */ | |
11495 | if (!pipe_config->port_clock) | |
2d112de7 | 11496 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11497 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11498 | |
a43f6e0f | 11499 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11500 | if (ret < 0) { |
7758a113 DV |
11501 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11502 | goto fail; | |
ee7b9f93 | 11503 | } |
e29c22c0 DV |
11504 | |
11505 | if (ret == RETRY) { | |
11506 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11507 | ret = -EINVAL; | |
11508 | goto fail; | |
11509 | } | |
11510 | ||
11511 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11512 | retry = false; | |
11513 | goto encoder_retry; | |
11514 | } | |
11515 | ||
d328c9d7 | 11516 | pipe_config->dither = pipe_config->pipe_bpp != base_bpp; |
4e53c2e0 | 11517 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11518 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11519 | |
548ee15b | 11520 | return 0; |
7758a113 | 11521 | fail: |
548ee15b | 11522 | return ret; |
ee7b9f93 | 11523 | } |
47f1c6c9 | 11524 | |
e2e1ed41 DV |
11525 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
11526 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
11527 | static void | |
11528 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
11529 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
11530 | { |
11531 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
11532 | struct drm_device *dev = crtc->dev; |
11533 | struct intel_encoder *encoder; | |
11534 | struct intel_connector *connector; | |
11535 | struct drm_crtc *tmp_crtc; | |
79e53945 | 11536 | |
e2e1ed41 | 11537 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 11538 | |
e2e1ed41 DV |
11539 | /* Check which crtcs have changed outputs connected to them, these need |
11540 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
11541 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
11542 | * bit set at most. */ | |
3a3371ff | 11543 | for_each_intel_connector(dev, connector) { |
e2e1ed41 DV |
11544 | if (connector->base.encoder == &connector->new_encoder->base) |
11545 | continue; | |
79e53945 | 11546 | |
e2e1ed41 DV |
11547 | if (connector->base.encoder) { |
11548 | tmp_crtc = connector->base.encoder->crtc; | |
11549 | ||
11550 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
11551 | } | |
11552 | ||
11553 | if (connector->new_encoder) | |
11554 | *prepare_pipes |= | |
11555 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
11556 | } |
11557 | ||
b2784e15 | 11558 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
11559 | if (encoder->base.crtc == &encoder->new_crtc->base) |
11560 | continue; | |
11561 | ||
11562 | if (encoder->base.crtc) { | |
11563 | tmp_crtc = encoder->base.crtc; | |
11564 | ||
11565 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
11566 | } | |
11567 | ||
11568 | if (encoder->new_crtc) | |
11569 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
11570 | } |
11571 | ||
7668851f | 11572 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 11573 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 11574 | if (intel_crtc->base.state->enable == intel_crtc->new_enabled) |
e2e1ed41 | 11575 | continue; |
7e7d76c3 | 11576 | |
7668851f | 11577 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 11578 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
11579 | else |
11580 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
11581 | } |
11582 | ||
e2e1ed41 DV |
11583 | |
11584 | /* set_mode is also used to update properties on life display pipes. */ | |
11585 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 11586 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
11587 | *prepare_pipes |= 1 << intel_crtc->pipe; |
11588 | ||
b6c5164d DV |
11589 | /* |
11590 | * For simplicity do a full modeset on any pipe where the output routing | |
11591 | * changed. We could be more clever, but that would require us to be | |
11592 | * more careful with calling the relevant encoder->mode_set functions. | |
11593 | */ | |
e2e1ed41 DV |
11594 | if (*prepare_pipes) |
11595 | *modeset_pipes = *prepare_pipes; | |
11596 | ||
11597 | /* ... and mask these out. */ | |
11598 | *modeset_pipes &= ~(*disable_pipes); | |
11599 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
11600 | |
11601 | /* | |
11602 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
11603 | * obies this rule, but the modeset restore mode of | |
11604 | * intel_modeset_setup_hw_state does not. | |
11605 | */ | |
11606 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
11607 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
11608 | |
11609 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
11610 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 11611 | } |
79e53945 | 11612 | |
ea9d758d | 11613 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 11614 | { |
ea9d758d | 11615 | struct drm_encoder *encoder; |
f6e5b160 | 11616 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 11617 | |
ea9d758d DV |
11618 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
11619 | if (encoder->crtc == crtc) | |
11620 | return true; | |
11621 | ||
11622 | return false; | |
11623 | } | |
11624 | ||
11625 | static void | |
11626 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
11627 | { | |
ba41c0de | 11628 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea9d758d DV |
11629 | struct intel_encoder *intel_encoder; |
11630 | struct intel_crtc *intel_crtc; | |
11631 | struct drm_connector *connector; | |
11632 | ||
ba41c0de DV |
11633 | intel_shared_dpll_commit(dev_priv); |
11634 | ||
b2784e15 | 11635 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
11636 | if (!intel_encoder->base.crtc) |
11637 | continue; | |
11638 | ||
11639 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
11640 | ||
11641 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
11642 | intel_encoder->connectors_active = false; | |
11643 | } | |
11644 | ||
11645 | intel_modeset_commit_output_state(dev); | |
11646 | ||
7668851f | 11647 | /* Double check state. */ |
d3fcc808 | 11648 | for_each_intel_crtc(dev, intel_crtc) { |
83d65738 | 11649 | WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base)); |
ea9d758d DV |
11650 | } |
11651 | ||
11652 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
11653 | if (!connector->encoder || !connector->encoder->crtc) | |
11654 | continue; | |
11655 | ||
11656 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
11657 | ||
11658 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
11659 | struct drm_property *dpms_property = |
11660 | dev->mode_config.dpms_property; | |
11661 | ||
ea9d758d | 11662 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 11663 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
11664 | dpms_property, |
11665 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
11666 | |
11667 | intel_encoder = to_intel_encoder(connector->encoder); | |
11668 | intel_encoder->connectors_active = true; | |
11669 | } | |
11670 | } | |
11671 | ||
11672 | } | |
11673 | ||
3bd26263 | 11674 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11675 | { |
3bd26263 | 11676 | int diff; |
f1f644dc JB |
11677 | |
11678 | if (clock1 == clock2) | |
11679 | return true; | |
11680 | ||
11681 | if (!clock1 || !clock2) | |
11682 | return false; | |
11683 | ||
11684 | diff = abs(clock1 - clock2); | |
11685 | ||
11686 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11687 | return true; | |
11688 | ||
11689 | return false; | |
11690 | } | |
11691 | ||
25c5b266 DV |
11692 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
11693 | list_for_each_entry((intel_crtc), \ | |
11694 | &(dev)->mode_config.crtc_list, \ | |
11695 | base.head) \ | |
0973f18f | 11696 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 11697 | |
0e8ffe1b | 11698 | static bool |
2fa2fe9a | 11699 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b ACO |
11700 | struct intel_crtc_state *current_config, |
11701 | struct intel_crtc_state *pipe_config) | |
0e8ffe1b | 11702 | { |
66e985c0 DV |
11703 | #define PIPE_CONF_CHECK_X(name) \ |
11704 | if (current_config->name != pipe_config->name) { \ | |
11705 | DRM_ERROR("mismatch in " #name " " \ | |
11706 | "(expected 0x%08x, found 0x%08x)\n", \ | |
11707 | current_config->name, \ | |
11708 | pipe_config->name); \ | |
11709 | return false; \ | |
11710 | } | |
11711 | ||
08a24034 DV |
11712 | #define PIPE_CONF_CHECK_I(name) \ |
11713 | if (current_config->name != pipe_config->name) { \ | |
11714 | DRM_ERROR("mismatch in " #name " " \ | |
11715 | "(expected %i, found %i)\n", \ | |
11716 | current_config->name, \ | |
11717 | pipe_config->name); \ | |
11718 | return false; \ | |
88adfff1 DV |
11719 | } |
11720 | ||
b95af8be VK |
11721 | /* This is required for BDW+ where there is only one set of registers for |
11722 | * switching between high and low RR. | |
11723 | * This macro can be used whenever a comparison has to be made between one | |
11724 | * hw state and multiple sw state variables. | |
11725 | */ | |
11726 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
11727 | if ((current_config->name != pipe_config->name) && \ | |
11728 | (current_config->alt_name != pipe_config->name)) { \ | |
11729 | DRM_ERROR("mismatch in " #name " " \ | |
11730 | "(expected %i or %i, found %i)\n", \ | |
11731 | current_config->name, \ | |
11732 | current_config->alt_name, \ | |
11733 | pipe_config->name); \ | |
11734 | return false; \ | |
11735 | } | |
11736 | ||
1bd1bd80 DV |
11737 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11738 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 11739 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
11740 | "(expected %i, found %i)\n", \ |
11741 | current_config->name & (mask), \ | |
11742 | pipe_config->name & (mask)); \ | |
11743 | return false; \ | |
11744 | } | |
11745 | ||
5e550656 VS |
11746 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11747 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
11748 | DRM_ERROR("mismatch in " #name " " \ | |
11749 | "(expected %i, found %i)\n", \ | |
11750 | current_config->name, \ | |
11751 | pipe_config->name); \ | |
11752 | return false; \ | |
11753 | } | |
11754 | ||
bb760063 DV |
11755 | #define PIPE_CONF_QUIRK(quirk) \ |
11756 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11757 | ||
eccb140b DV |
11758 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11759 | ||
08a24034 DV |
11760 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11761 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
11762 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
11763 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
11764 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
11765 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
11766 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 11767 | |
eb14cb74 | 11768 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
11769 | |
11770 | if (INTEL_INFO(dev)->gen < 8) { | |
11771 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
11772 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
11773 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
11774 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
11775 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
11776 | ||
11777 | if (current_config->has_drrs) { | |
11778 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
11779 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
11780 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
11781 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
11782 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
11783 | } | |
11784 | } else { | |
11785 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
11786 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
11787 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
11788 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
11789 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
11790 | } | |
eb14cb74 | 11791 | |
2d112de7 ACO |
11792 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11793 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11794 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11795 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11796 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11797 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11798 | |
2d112de7 ACO |
11799 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11800 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11801 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11802 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11803 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11804 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11805 | |
c93f54cf | 11806 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11807 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
11808 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
11809 | IS_VALLEYVIEW(dev)) | |
11810 | PIPE_CONF_CHECK_I(limited_color_range); | |
e43823ec | 11811 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11812 | |
9ed109a7 DV |
11813 | PIPE_CONF_CHECK_I(has_audio); |
11814 | ||
2d112de7 | 11815 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11816 | DRM_MODE_FLAG_INTERLACE); |
11817 | ||
bb760063 | 11818 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11819 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11820 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11821 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11822 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11823 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11824 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11825 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11826 | DRM_MODE_FLAG_NVSYNC); |
11827 | } | |
045ac3b5 | 11828 | |
37327abd VS |
11829 | PIPE_CONF_CHECK_I(pipe_src_w); |
11830 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 11831 | |
9953599b DV |
11832 | /* |
11833 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
11834 | * screen. Since we don't yet re-compute the pipe config when moving | |
11835 | * just the lvds port away to another pipe the sw tracking won't match. | |
11836 | * | |
11837 | * Proper atomic modesets with recomputed global state will fix this. | |
11838 | * Until then just don't check gmch state for inherited modes. | |
11839 | */ | |
11840 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
11841 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
11842 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
11843 | if (INTEL_INFO(dev)->gen < 4) | |
11844 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
11845 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
11846 | } | |
11847 | ||
fd4daa9c CW |
11848 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
11849 | if (current_config->pch_pfit.enabled) { | |
11850 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
11851 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
11852 | } | |
2fa2fe9a | 11853 | |
a1b2278e CK |
11854 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
11855 | ||
e59150dc JB |
11856 | /* BDW+ don't expose a synchronous way to read the state */ |
11857 | if (IS_HASWELL(dev)) | |
11858 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 11859 | |
282740f7 VS |
11860 | PIPE_CONF_CHECK_I(double_wide); |
11861 | ||
26804afd DV |
11862 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
11863 | ||
c0d43d62 | 11864 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 11865 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11866 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11867 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11868 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11869 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
3f4cd19f DL |
11870 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11871 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11872 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11873 | |
42571aef VS |
11874 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
11875 | PIPE_CONF_CHECK_I(pipe_bpp); | |
11876 | ||
2d112de7 | 11877 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11878 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11879 | |
66e985c0 | 11880 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11881 | #undef PIPE_CONF_CHECK_I |
b95af8be | 11882 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 11883 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11884 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11885 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11886 | |
0e8ffe1b DV |
11887 | return true; |
11888 | } | |
11889 | ||
08db6652 DL |
11890 | static void check_wm_state(struct drm_device *dev) |
11891 | { | |
11892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11893 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
11894 | struct intel_crtc *intel_crtc; | |
11895 | int plane; | |
11896 | ||
11897 | if (INTEL_INFO(dev)->gen < 9) | |
11898 | return; | |
11899 | ||
11900 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
11901 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11902 | ||
11903 | for_each_intel_crtc(dev, intel_crtc) { | |
11904 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
11905 | const enum pipe pipe = intel_crtc->pipe; | |
11906 | ||
11907 | if (!intel_crtc->active) | |
11908 | continue; | |
11909 | ||
11910 | /* planes */ | |
dd740780 | 11911 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
11912 | hw_entry = &hw_ddb.plane[pipe][plane]; |
11913 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
11914 | ||
11915 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11916 | continue; | |
11917 | ||
11918 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
11919 | "(expected (%u,%u), found (%u,%u))\n", | |
11920 | pipe_name(pipe), plane + 1, | |
11921 | sw_entry->start, sw_entry->end, | |
11922 | hw_entry->start, hw_entry->end); | |
11923 | } | |
11924 | ||
11925 | /* cursor */ | |
11926 | hw_entry = &hw_ddb.cursor[pipe]; | |
11927 | sw_entry = &sw_ddb->cursor[pipe]; | |
11928 | ||
11929 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
11930 | continue; | |
11931 | ||
11932 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
11933 | "(expected (%u,%u), found (%u,%u))\n", | |
11934 | pipe_name(pipe), | |
11935 | sw_entry->start, sw_entry->end, | |
11936 | hw_entry->start, hw_entry->end); | |
11937 | } | |
11938 | } | |
11939 | ||
91d1b4bd DV |
11940 | static void |
11941 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 11942 | { |
8af6cf88 DV |
11943 | struct intel_connector *connector; |
11944 | ||
3a3371ff | 11945 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11946 | /* This also checks the encoder/connector hw state with the |
11947 | * ->get_hw_state callbacks. */ | |
11948 | intel_connector_check_state(connector); | |
11949 | ||
e2c719b7 | 11950 | I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder, |
8af6cf88 DV |
11951 | "connector's staged encoder doesn't match current encoder\n"); |
11952 | } | |
91d1b4bd DV |
11953 | } |
11954 | ||
11955 | static void | |
11956 | check_encoder_state(struct drm_device *dev) | |
11957 | { | |
11958 | struct intel_encoder *encoder; | |
11959 | struct intel_connector *connector; | |
8af6cf88 | 11960 | |
b2784e15 | 11961 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
11962 | bool enabled = false; |
11963 | bool active = false; | |
11964 | enum pipe pipe, tracked_pipe; | |
11965 | ||
11966 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11967 | encoder->base.base.id, | |
8e329a03 | 11968 | encoder->base.name); |
8af6cf88 | 11969 | |
e2c719b7 | 11970 | I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc, |
8af6cf88 | 11971 | "encoder's stage crtc doesn't match current crtc\n"); |
e2c719b7 | 11972 | I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc, |
8af6cf88 DV |
11973 | "encoder's active_connectors set, but no crtc\n"); |
11974 | ||
3a3371ff | 11975 | for_each_intel_connector(dev, connector) { |
8af6cf88 DV |
11976 | if (connector->base.encoder != &encoder->base) |
11977 | continue; | |
11978 | enabled = true; | |
11979 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
11980 | active = true; | |
11981 | } | |
0e32b39c DA |
11982 | /* |
11983 | * for MST connectors if we unplug the connector is gone | |
11984 | * away but the encoder is still connected to a crtc | |
11985 | * until a modeset happens in response to the hotplug. | |
11986 | */ | |
11987 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
11988 | continue; | |
11989 | ||
e2c719b7 | 11990 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11991 | "encoder's enabled state mismatch " |
11992 | "(expected %i, found %i)\n", | |
11993 | !!encoder->base.crtc, enabled); | |
e2c719b7 | 11994 | I915_STATE_WARN(active && !encoder->base.crtc, |
8af6cf88 DV |
11995 | "active encoder with no crtc\n"); |
11996 | ||
e2c719b7 | 11997 | I915_STATE_WARN(encoder->connectors_active != active, |
8af6cf88 DV |
11998 | "encoder's computed active state doesn't match tracked active state " |
11999 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
12000 | ||
12001 | active = encoder->get_hw_state(encoder, &pipe); | |
e2c719b7 | 12002 | I915_STATE_WARN(active != encoder->connectors_active, |
8af6cf88 DV |
12003 | "encoder's hw state doesn't match sw tracking " |
12004 | "(expected %i, found %i)\n", | |
12005 | encoder->connectors_active, active); | |
12006 | ||
12007 | if (!encoder->base.crtc) | |
12008 | continue; | |
12009 | ||
12010 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
e2c719b7 | 12011 | I915_STATE_WARN(active && pipe != tracked_pipe, |
8af6cf88 DV |
12012 | "active encoder's pipe doesn't match" |
12013 | "(expected %i, found %i)\n", | |
12014 | tracked_pipe, pipe); | |
12015 | ||
12016 | } | |
91d1b4bd DV |
12017 | } |
12018 | ||
12019 | static void | |
12020 | check_crtc_state(struct drm_device *dev) | |
12021 | { | |
fbee40df | 12022 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12023 | struct intel_crtc *crtc; |
12024 | struct intel_encoder *encoder; | |
5cec258b | 12025 | struct intel_crtc_state pipe_config; |
8af6cf88 | 12026 | |
d3fcc808 | 12027 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
12028 | bool enabled = false; |
12029 | bool active = false; | |
12030 | ||
045ac3b5 JB |
12031 | memset(&pipe_config, 0, sizeof(pipe_config)); |
12032 | ||
8af6cf88 DV |
12033 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12034 | crtc->base.base.id); | |
12035 | ||
83d65738 | 12036 | I915_STATE_WARN(crtc->active && !crtc->base.state->enable, |
8af6cf88 DV |
12037 | "active crtc, but not enabled in sw tracking\n"); |
12038 | ||
b2784e15 | 12039 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
12040 | if (encoder->base.crtc != &crtc->base) |
12041 | continue; | |
12042 | enabled = true; | |
12043 | if (encoder->connectors_active) | |
12044 | active = true; | |
12045 | } | |
6c49f241 | 12046 | |
e2c719b7 | 12047 | I915_STATE_WARN(active != crtc->active, |
8af6cf88 DV |
12048 | "crtc's computed active state doesn't match tracked active state " |
12049 | "(expected %i, found %i)\n", active, crtc->active); | |
83d65738 | 12050 | I915_STATE_WARN(enabled != crtc->base.state->enable, |
8af6cf88 | 12051 | "crtc's computed enabled state doesn't match tracked enabled state " |
83d65738 MR |
12052 | "(expected %i, found %i)\n", enabled, |
12053 | crtc->base.state->enable); | |
8af6cf88 | 12054 | |
0e8ffe1b DV |
12055 | active = dev_priv->display.get_pipe_config(crtc, |
12056 | &pipe_config); | |
d62cf62a | 12057 | |
b6b5d049 VS |
12058 | /* hw state is inconsistent with the pipe quirk */ |
12059 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12060 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
12061 | active = crtc->active; |
12062 | ||
b2784e15 | 12063 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 12064 | enum pipe pipe; |
6c49f241 DV |
12065 | if (encoder->base.crtc != &crtc->base) |
12066 | continue; | |
1d37b689 | 12067 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
12068 | encoder->get_config(encoder, &pipe_config); |
12069 | } | |
12070 | ||
e2c719b7 | 12071 | I915_STATE_WARN(crtc->active != active, |
0e8ffe1b DV |
12072 | "crtc active state doesn't match with hw state " |
12073 | "(expected %i, found %i)\n", crtc->active, active); | |
12074 | ||
c0b03411 | 12075 | if (active && |
6e3c9717 | 12076 | !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) { |
e2c719b7 | 12077 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
c0b03411 DV |
12078 | intel_dump_pipe_config(crtc, &pipe_config, |
12079 | "[hw state]"); | |
6e3c9717 | 12080 | intel_dump_pipe_config(crtc, crtc->config, |
c0b03411 DV |
12081 | "[sw state]"); |
12082 | } | |
8af6cf88 DV |
12083 | } |
12084 | } | |
12085 | ||
91d1b4bd DV |
12086 | static void |
12087 | check_shared_dpll_state(struct drm_device *dev) | |
12088 | { | |
fbee40df | 12089 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12090 | struct intel_crtc *crtc; |
12091 | struct intel_dpll_hw_state dpll_hw_state; | |
12092 | int i; | |
5358901f DV |
12093 | |
12094 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12095 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12096 | int enabled_crtcs = 0, active_crtcs = 0; | |
12097 | bool active; | |
12098 | ||
12099 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12100 | ||
12101 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12102 | ||
12103 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12104 | ||
e2c719b7 | 12105 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12106 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12107 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12108 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12109 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12110 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12111 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12112 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12113 | "pll on state mismatch (expected %i, found %i)\n", |
12114 | pll->on, active); | |
12115 | ||
d3fcc808 | 12116 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12117 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12118 | enabled_crtcs++; |
12119 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12120 | active_crtcs++; | |
12121 | } | |
e2c719b7 | 12122 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12123 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12124 | pll->active, active_crtcs); | |
e2c719b7 | 12125 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12126 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12127 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12128 | |
e2c719b7 | 12129 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
12130 | sizeof(dpll_hw_state)), |
12131 | "pll hw state mismatch\n"); | |
5358901f | 12132 | } |
8af6cf88 DV |
12133 | } |
12134 | ||
91d1b4bd DV |
12135 | void |
12136 | intel_modeset_check_state(struct drm_device *dev) | |
12137 | { | |
08db6652 | 12138 | check_wm_state(dev); |
91d1b4bd DV |
12139 | check_connector_state(dev); |
12140 | check_encoder_state(dev); | |
12141 | check_crtc_state(dev); | |
12142 | check_shared_dpll_state(dev); | |
12143 | } | |
12144 | ||
5cec258b | 12145 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
12146 | int dotclock) |
12147 | { | |
12148 | /* | |
12149 | * FDI already provided one idea for the dotclock. | |
12150 | * Yell if the encoder disagrees. | |
12151 | */ | |
2d112de7 | 12152 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 12153 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 12154 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
12155 | } |
12156 | ||
80715b2f VS |
12157 | static void update_scanline_offset(struct intel_crtc *crtc) |
12158 | { | |
12159 | struct drm_device *dev = crtc->base.dev; | |
12160 | ||
12161 | /* | |
12162 | * The scanline counter increments at the leading edge of hsync. | |
12163 | * | |
12164 | * On most platforms it starts counting from vtotal-1 on the | |
12165 | * first active line. That means the scanline counter value is | |
12166 | * always one less than what we would expect. Ie. just after | |
12167 | * start of vblank, which also occurs at start of hsync (on the | |
12168 | * last active line), the scanline counter will read vblank_start-1. | |
12169 | * | |
12170 | * On gen2 the scanline counter starts counting from 1 instead | |
12171 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12172 | * to keep the value positive), instead of adding one. | |
12173 | * | |
12174 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12175 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12176 | * there's an extra 1 line difference. So we need to add two instead of | |
12177 | * one to the value. | |
12178 | */ | |
12179 | if (IS_GEN2(dev)) { | |
6e3c9717 | 12180 | const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12181 | int vtotal; |
12182 | ||
12183 | vtotal = mode->crtc_vtotal; | |
12184 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
12185 | vtotal /= 2; | |
12186 | ||
12187 | crtc->scanline_offset = vtotal - 1; | |
12188 | } else if (HAS_DDI(dev) && | |
409ee761 | 12189 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12190 | crtc->scanline_offset = 2; |
12191 | } else | |
12192 | crtc->scanline_offset = 1; | |
12193 | } | |
12194 | ||
5cec258b | 12195 | static struct intel_crtc_state * |
7f27126e JB |
12196 | intel_modeset_compute_config(struct drm_crtc *crtc, |
12197 | struct drm_display_mode *mode, | |
83a57153 | 12198 | struct drm_atomic_state *state, |
7f27126e JB |
12199 | unsigned *modeset_pipes, |
12200 | unsigned *prepare_pipes, | |
12201 | unsigned *disable_pipes) | |
12202 | { | |
548ee15b | 12203 | struct intel_crtc_state *pipe_config; |
0b901879 ACO |
12204 | int ret = 0; |
12205 | ||
12206 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12207 | if (ret) | |
12208 | return ERR_PTR(ret); | |
7f27126e JB |
12209 | |
12210 | intel_modeset_affected_pipes(crtc, modeset_pipes, | |
12211 | prepare_pipes, disable_pipes); | |
12212 | ||
7f27126e JB |
12213 | /* |
12214 | * Note this needs changes when we start tracking multiple modes | |
12215 | * and crtcs. At that point we'll need to compute the whole config | |
12216 | * (i.e. one pipe_config for each crtc) rather than just the one | |
12217 | * for this crtc. | |
12218 | */ | |
548ee15b ACO |
12219 | pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc)); |
12220 | if (IS_ERR(pipe_config)) | |
12221 | return pipe_config; | |
83a57153 | 12222 | |
4fed33f6 | 12223 | if (!pipe_config->base.enable) |
548ee15b | 12224 | return pipe_config; |
7f27126e | 12225 | |
548ee15b ACO |
12226 | ret = intel_modeset_pipe_config(crtc, mode, state, pipe_config); |
12227 | if (ret) | |
12228 | return ERR_PTR(ret); | |
12229 | ||
12230 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]"); | |
db7542dd | 12231 | |
548ee15b | 12232 | return pipe_config; |
7f27126e JB |
12233 | } |
12234 | ||
225da59b | 12235 | static int __intel_set_mode_setup_plls(struct drm_atomic_state *state, |
ed6739ef ACO |
12236 | unsigned modeset_pipes, |
12237 | unsigned disable_pipes) | |
12238 | { | |
225da59b | 12239 | struct drm_device *dev = state->dev; |
ed6739ef ACO |
12240 | struct drm_i915_private *dev_priv = to_i915(dev); |
12241 | unsigned clear_pipes = modeset_pipes | disable_pipes; | |
12242 | struct intel_crtc *intel_crtc; | |
12243 | int ret = 0; | |
12244 | ||
12245 | if (!dev_priv->display.crtc_compute_clock) | |
12246 | return 0; | |
12247 | ||
12248 | ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); | |
12249 | if (ret) | |
12250 | goto done; | |
12251 | ||
12252 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { | |
225da59b ACO |
12253 | struct intel_crtc_state *crtc_state = |
12254 | intel_atomic_get_crtc_state(state, intel_crtc); | |
12255 | ||
12256 | /* Modeset pipes should have a new state by now */ | |
12257 | if (WARN_ON(IS_ERR(crtc_state))) | |
12258 | continue; | |
12259 | ||
ed6739ef | 12260 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
225da59b | 12261 | crtc_state); |
ed6739ef ACO |
12262 | if (ret) { |
12263 | intel_shared_dpll_abort_config(dev_priv); | |
12264 | goto done; | |
12265 | } | |
12266 | } | |
12267 | ||
12268 | done: | |
12269 | return ret; | |
12270 | } | |
12271 | ||
f30da187 DV |
12272 | static int __intel_set_mode(struct drm_crtc *crtc, |
12273 | struct drm_display_mode *mode, | |
7f27126e | 12274 | int x, int y, struct drm_framebuffer *fb, |
5cec258b | 12275 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
12276 | unsigned modeset_pipes, |
12277 | unsigned prepare_pipes, | |
12278 | unsigned disable_pipes) | |
a6778b3c DV |
12279 | { |
12280 | struct drm_device *dev = crtc->dev; | |
fbee40df | 12281 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 12282 | struct drm_display_mode *saved_mode; |
304603f4 | 12283 | struct drm_atomic_state *state = pipe_config->base.state; |
83a57153 | 12284 | struct intel_crtc_state *crtc_state_copy = NULL; |
25c5b266 | 12285 | struct intel_crtc *intel_crtc; |
c0c36b94 | 12286 | int ret = 0; |
a6778b3c | 12287 | |
4b4b9238 | 12288 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
12289 | if (!saved_mode) |
12290 | return -ENOMEM; | |
a6778b3c | 12291 | |
83a57153 ACO |
12292 | crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL); |
12293 | if (!crtc_state_copy) { | |
12294 | ret = -ENOMEM; | |
12295 | goto done; | |
12296 | } | |
12297 | ||
3ac18232 | 12298 | *saved_mode = crtc->mode; |
a6778b3c | 12299 | |
30a970c6 JB |
12300 | /* |
12301 | * See if the config requires any additional preparation, e.g. | |
12302 | * to adjust global state with pipes off. We need to do this | |
12303 | * here so we can get the modeset_pipe updated config for the new | |
12304 | * mode set on this crtc. For other crtcs we need to use the | |
12305 | * adjusted_mode bits in the crtc directly. | |
12306 | */ | |
f8437dd1 | 12307 | if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) { |
304603f4 ACO |
12308 | ret = valleyview_modeset_global_pipes(state, &prepare_pipes); |
12309 | if (ret) | |
12310 | goto done; | |
30a970c6 | 12311 | |
c164f833 VS |
12312 | /* may have added more to prepare_pipes than we should */ |
12313 | prepare_pipes &= ~disable_pipes; | |
12314 | } | |
12315 | ||
225da59b | 12316 | ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes); |
ed6739ef ACO |
12317 | if (ret) |
12318 | goto done; | |
8bd31e67 | 12319 | |
460da916 DV |
12320 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
12321 | intel_crtc_disable(&intel_crtc->base); | |
12322 | ||
ea9d758d | 12323 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
ce22dba9 ML |
12324 | if (intel_crtc->base.state->enable) { |
12325 | intel_crtc_disable_planes(&intel_crtc->base); | |
ea9d758d | 12326 | dev_priv->display.crtc_disable(&intel_crtc->base); |
ce22dba9 | 12327 | } |
ea9d758d | 12328 | } |
a6778b3c | 12329 | |
6c4c86f5 DV |
12330 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
12331 | * to set it here already despite that we pass it down the callchain. | |
7f27126e JB |
12332 | * |
12333 | * Note we'll need to fix this up when we start tracking multiple | |
12334 | * pipes; here we assume a single modeset_pipe and only track the | |
12335 | * single crtc and mode. | |
f6e5b160 | 12336 | */ |
b8cecdf5 | 12337 | if (modeset_pipes) { |
25c5b266 | 12338 | crtc->mode = *mode; |
b8cecdf5 DV |
12339 | /* mode_set/enable/disable functions rely on a correct pipe |
12340 | * config. */ | |
f5de6e07 | 12341 | intel_crtc_set_state(to_intel_crtc(crtc), pipe_config); |
c326c0a9 VS |
12342 | |
12343 | /* | |
12344 | * Calculate and store various constants which | |
12345 | * are later needed by vblank and swap-completion | |
12346 | * timestamping. They are derived from true hwmode. | |
12347 | */ | |
12348 | drm_calc_timestamping_constants(crtc, | |
2d112de7 | 12349 | &pipe_config->base.adjusted_mode); |
b8cecdf5 | 12350 | } |
7758a113 | 12351 | |
ea9d758d DV |
12352 | /* Only after disabling all output pipelines that will be changed can we |
12353 | * update the the output configuration. */ | |
12354 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 12355 | |
304603f4 | 12356 | modeset_update_crtc_power_domains(state); |
47fab737 | 12357 | |
25c5b266 | 12358 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
455a6808 GP |
12359 | struct drm_plane *primary = intel_crtc->base.primary; |
12360 | int vdisplay, hdisplay; | |
4c10794f | 12361 | |
455a6808 | 12362 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); |
70a101f8 MR |
12363 | ret = drm_plane_helper_update(primary, &intel_crtc->base, |
12364 | fb, 0, 0, | |
12365 | hdisplay, vdisplay, | |
12366 | x << 16, y << 16, | |
12367 | hdisplay << 16, vdisplay << 16); | |
a6778b3c DV |
12368 | } |
12369 | ||
12370 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
12371 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
12372 | update_scanline_offset(intel_crtc); | |
12373 | ||
25c5b266 | 12374 | dev_priv->display.crtc_enable(&intel_crtc->base); |
ce22dba9 | 12375 | intel_crtc_enable_planes(&intel_crtc->base); |
80715b2f | 12376 | } |
a6778b3c | 12377 | |
a6778b3c DV |
12378 | /* FIXME: add subpixel order */ |
12379 | done: | |
83d65738 | 12380 | if (ret && crtc->state->enable) |
3ac18232 | 12381 | crtc->mode = *saved_mode; |
a6778b3c | 12382 | |
83a57153 ACO |
12383 | if (ret == 0 && pipe_config) { |
12384 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12385 | ||
12386 | /* The pipe_config will be freed with the atomic state, so | |
12387 | * make a copy. */ | |
12388 | memcpy(crtc_state_copy, intel_crtc->config, | |
12389 | sizeof *crtc_state_copy); | |
12390 | intel_crtc->config = crtc_state_copy; | |
12391 | intel_crtc->base.state = &crtc_state_copy->base; | |
83a57153 ACO |
12392 | } else { |
12393 | kfree(crtc_state_copy); | |
12394 | } | |
12395 | ||
3ac18232 | 12396 | kfree(saved_mode); |
a6778b3c | 12397 | return ret; |
f6e5b160 CW |
12398 | } |
12399 | ||
7f27126e JB |
12400 | static int intel_set_mode_pipes(struct drm_crtc *crtc, |
12401 | struct drm_display_mode *mode, | |
12402 | int x, int y, struct drm_framebuffer *fb, | |
5cec258b | 12403 | struct intel_crtc_state *pipe_config, |
7f27126e JB |
12404 | unsigned modeset_pipes, |
12405 | unsigned prepare_pipes, | |
12406 | unsigned disable_pipes) | |
f30da187 DV |
12407 | { |
12408 | int ret; | |
12409 | ||
7f27126e JB |
12410 | ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes, |
12411 | prepare_pipes, disable_pipes); | |
f30da187 DV |
12412 | |
12413 | if (ret == 0) | |
12414 | intel_modeset_check_state(crtc->dev); | |
12415 | ||
12416 | return ret; | |
12417 | } | |
12418 | ||
7f27126e JB |
12419 | static int intel_set_mode(struct drm_crtc *crtc, |
12420 | struct drm_display_mode *mode, | |
83a57153 ACO |
12421 | int x, int y, struct drm_framebuffer *fb, |
12422 | struct drm_atomic_state *state) | |
7f27126e | 12423 | { |
5cec258b | 12424 | struct intel_crtc_state *pipe_config; |
7f27126e | 12425 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
83a57153 | 12426 | int ret = 0; |
7f27126e | 12427 | |
8805aa71 | 12428 | pipe_config = intel_modeset_compute_config(crtc, mode, state, |
7f27126e JB |
12429 | &modeset_pipes, |
12430 | &prepare_pipes, | |
12431 | &disable_pipes); | |
12432 | ||
83a57153 ACO |
12433 | if (IS_ERR(pipe_config)) { |
12434 | ret = PTR_ERR(pipe_config); | |
12435 | goto out; | |
12436 | } | |
12437 | ||
12438 | ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config, | |
12439 | modeset_pipes, prepare_pipes, | |
12440 | disable_pipes); | |
12441 | if (ret) | |
12442 | goto out; | |
7f27126e | 12443 | |
83a57153 ACO |
12444 | out: |
12445 | return ret; | |
7f27126e JB |
12446 | } |
12447 | ||
c0c36b94 CW |
12448 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
12449 | { | |
83a57153 ACO |
12450 | struct drm_device *dev = crtc->dev; |
12451 | struct drm_atomic_state *state; | |
4be07317 | 12452 | struct intel_crtc *intel_crtc; |
83a57153 ACO |
12453 | struct intel_encoder *encoder; |
12454 | struct intel_connector *connector; | |
12455 | struct drm_connector_state *connector_state; | |
4be07317 | 12456 | struct intel_crtc_state *crtc_state; |
83a57153 ACO |
12457 | |
12458 | state = drm_atomic_state_alloc(dev); | |
12459 | if (!state) { | |
12460 | DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory", | |
12461 | crtc->base.id); | |
12462 | return; | |
12463 | } | |
12464 | ||
12465 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12466 | ||
12467 | /* The force restore path in the HW readout code relies on the staged | |
12468 | * config still keeping the user requested config while the actual | |
12469 | * state has been overwritten by the configuration read from HW. We | |
12470 | * need to copy the staged config to the atomic state, otherwise the | |
12471 | * mode set will just reapply the state the HW is already in. */ | |
12472 | for_each_intel_encoder(dev, encoder) { | |
12473 | if (&encoder->new_crtc->base != crtc) | |
12474 | continue; | |
12475 | ||
12476 | for_each_intel_connector(dev, connector) { | |
12477 | if (connector->new_encoder != encoder) | |
12478 | continue; | |
12479 | ||
12480 | connector_state = drm_atomic_get_connector_state(state, &connector->base); | |
12481 | if (IS_ERR(connector_state)) { | |
12482 | DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n", | |
12483 | connector->base.base.id, | |
12484 | connector->base.name, | |
12485 | PTR_ERR(connector_state)); | |
12486 | continue; | |
12487 | } | |
12488 | ||
12489 | connector_state->crtc = crtc; | |
12490 | connector_state->best_encoder = &encoder->base; | |
12491 | } | |
12492 | } | |
12493 | ||
4be07317 ACO |
12494 | for_each_intel_crtc(dev, intel_crtc) { |
12495 | if (intel_crtc->new_enabled == intel_crtc->base.enabled) | |
12496 | continue; | |
12497 | ||
12498 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
12499 | if (IS_ERR(crtc_state)) { | |
12500 | DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n", | |
12501 | intel_crtc->base.base.id, | |
12502 | PTR_ERR(crtc_state)); | |
12503 | continue; | |
12504 | } | |
12505 | ||
12506 | crtc_state->base.enable = intel_crtc->new_enabled; | |
12507 | } | |
12508 | ||
83a57153 ACO |
12509 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb, |
12510 | state); | |
12511 | ||
12512 | drm_atomic_state_free(state); | |
c0c36b94 CW |
12513 | } |
12514 | ||
25c5b266 DV |
12515 | #undef for_each_intel_crtc_masked |
12516 | ||
d9e55608 DV |
12517 | static void intel_set_config_free(struct intel_set_config *config) |
12518 | { | |
12519 | if (!config) | |
12520 | return; | |
12521 | ||
1aa4b628 DV |
12522 | kfree(config->save_connector_encoders); |
12523 | kfree(config->save_encoder_crtcs); | |
7668851f | 12524 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
12525 | kfree(config); |
12526 | } | |
12527 | ||
85f9eb71 DV |
12528 | static int intel_set_config_save_state(struct drm_device *dev, |
12529 | struct intel_set_config *config) | |
12530 | { | |
7668851f | 12531 | struct drm_crtc *crtc; |
85f9eb71 DV |
12532 | struct drm_encoder *encoder; |
12533 | struct drm_connector *connector; | |
12534 | int count; | |
12535 | ||
7668851f VS |
12536 | config->save_crtc_enabled = |
12537 | kcalloc(dev->mode_config.num_crtc, | |
12538 | sizeof(bool), GFP_KERNEL); | |
12539 | if (!config->save_crtc_enabled) | |
12540 | return -ENOMEM; | |
12541 | ||
1aa4b628 DV |
12542 | config->save_encoder_crtcs = |
12543 | kcalloc(dev->mode_config.num_encoder, | |
12544 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
12545 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
12546 | return -ENOMEM; |
12547 | ||
1aa4b628 DV |
12548 | config->save_connector_encoders = |
12549 | kcalloc(dev->mode_config.num_connector, | |
12550 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
12551 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
12552 | return -ENOMEM; |
12553 | ||
12554 | /* Copy data. Note that driver private data is not affected. | |
12555 | * Should anything bad happen only the expected state is | |
12556 | * restored, not the drivers personal bookkeeping. | |
12557 | */ | |
7668851f | 12558 | count = 0; |
70e1e0ec | 12559 | for_each_crtc(dev, crtc) { |
83d65738 | 12560 | config->save_crtc_enabled[count++] = crtc->state->enable; |
7668851f VS |
12561 | } |
12562 | ||
85f9eb71 DV |
12563 | count = 0; |
12564 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 12565 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
12566 | } |
12567 | ||
12568 | count = 0; | |
12569 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 12570 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
12571 | } |
12572 | ||
12573 | return 0; | |
12574 | } | |
12575 | ||
12576 | static void intel_set_config_restore_state(struct drm_device *dev, | |
12577 | struct intel_set_config *config) | |
12578 | { | |
7668851f | 12579 | struct intel_crtc *crtc; |
9a935856 DV |
12580 | struct intel_encoder *encoder; |
12581 | struct intel_connector *connector; | |
85f9eb71 DV |
12582 | int count; |
12583 | ||
7668851f | 12584 | count = 0; |
d3fcc808 | 12585 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
12586 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
12587 | } | |
12588 | ||
85f9eb71 | 12589 | count = 0; |
b2784e15 | 12590 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
12591 | encoder->new_crtc = |
12592 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
12593 | } |
12594 | ||
12595 | count = 0; | |
3a3371ff | 12596 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12597 | connector->new_encoder = |
12598 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
12599 | } |
12600 | } | |
12601 | ||
e3de42b6 | 12602 | static bool |
2e57f47d | 12603 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
12604 | { |
12605 | int i; | |
12606 | ||
2e57f47d CW |
12607 | if (set->num_connectors == 0) |
12608 | return false; | |
12609 | ||
12610 | if (WARN_ON(set->connectors == NULL)) | |
12611 | return false; | |
12612 | ||
12613 | for (i = 0; i < set->num_connectors; i++) | |
12614 | if (set->connectors[i]->encoder && | |
12615 | set->connectors[i]->encoder->crtc == set->crtc && | |
12616 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
12617 | return true; |
12618 | ||
12619 | return false; | |
12620 | } | |
12621 | ||
5e2b584e DV |
12622 | static void |
12623 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
12624 | struct intel_set_config *config) | |
12625 | { | |
462a425a ACO |
12626 | struct drm_device *dev = set->crtc->dev; |
12627 | struct intel_connector *connector; | |
12628 | struct intel_encoder *encoder; | |
12629 | struct intel_crtc *crtc; | |
5e2b584e DV |
12630 | |
12631 | /* We should be able to check here if the fb has the same properties | |
12632 | * and then just flip_or_move it */ | |
2e57f47d CW |
12633 | if (is_crtc_connector_off(set)) { |
12634 | config->mode_changed = true; | |
f4510a27 | 12635 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
12636 | /* |
12637 | * If we have no fb, we can only flip as long as the crtc is | |
12638 | * active, otherwise we need a full mode set. The crtc may | |
12639 | * be active if we've only disabled the primary plane, or | |
12640 | * in fastboot situations. | |
12641 | */ | |
f4510a27 | 12642 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
12643 | struct intel_crtc *intel_crtc = |
12644 | to_intel_crtc(set->crtc); | |
12645 | ||
3b150f08 | 12646 | if (intel_crtc->active) { |
319d9827 JB |
12647 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
12648 | config->fb_changed = true; | |
12649 | } else { | |
12650 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
12651 | config->mode_changed = true; | |
12652 | } | |
5e2b584e DV |
12653 | } else if (set->fb == NULL) { |
12654 | config->mode_changed = true; | |
72f4901e | 12655 | } else if (set->fb->pixel_format != |
f4510a27 | 12656 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 12657 | config->mode_changed = true; |
e3de42b6 | 12658 | } else { |
5e2b584e | 12659 | config->fb_changed = true; |
e3de42b6 | 12660 | } |
5e2b584e DV |
12661 | } |
12662 | ||
835c5873 | 12663 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
12664 | config->fb_changed = true; |
12665 | ||
12666 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
12667 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
12668 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
12669 | drm_mode_debug_printmodeline(set->mode); | |
12670 | config->mode_changed = true; | |
12671 | } | |
a1d95703 | 12672 | |
462a425a ACO |
12673 | for_each_intel_connector(dev, connector) { |
12674 | if (&connector->new_encoder->base == connector->base.encoder) | |
12675 | continue; | |
12676 | ||
12677 | config->mode_changed = true; | |
12678 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n", | |
12679 | connector->base.base.id, | |
12680 | connector->base.name); | |
12681 | } | |
12682 | ||
12683 | for_each_intel_encoder(dev, encoder) { | |
12684 | if (&encoder->new_crtc->base == encoder->base.crtc) | |
12685 | continue; | |
12686 | ||
12687 | DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n", | |
12688 | encoder->base.base.id, | |
12689 | encoder->base.name); | |
12690 | config->mode_changed = true; | |
12691 | } | |
12692 | ||
12693 | for_each_intel_crtc(dev, crtc) { | |
12694 | if (crtc->new_enabled == crtc->base.state->enable) | |
12695 | continue; | |
12696 | ||
12697 | DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n", | |
12698 | crtc->base.base.id, | |
12699 | crtc->new_enabled ? "en" : "dis"); | |
12700 | config->mode_changed = true; | |
12701 | } | |
12702 | ||
a1d95703 CW |
12703 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", |
12704 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
12705 | } |
12706 | ||
2e431051 | 12707 | static int |
9a935856 DV |
12708 | intel_modeset_stage_output_state(struct drm_device *dev, |
12709 | struct drm_mode_set *set, | |
944b0c76 | 12710 | struct drm_atomic_state *state) |
50f56119 | 12711 | { |
9a935856 | 12712 | struct intel_connector *connector; |
944b0c76 | 12713 | struct drm_connector_state *connector_state; |
9a935856 | 12714 | struct intel_encoder *encoder; |
7668851f | 12715 | struct intel_crtc *crtc; |
4be07317 | 12716 | struct intel_crtc_state *crtc_state; |
f3f08572 | 12717 | int ro; |
50f56119 | 12718 | |
9abdda74 | 12719 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
12720 | * of connectors. For paranoia, double-check this. */ |
12721 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
12722 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
12723 | ||
3a3371ff | 12724 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12725 | /* Otherwise traverse passed in connector list and get encoders |
12726 | * for them. */ | |
50f56119 | 12727 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 12728 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 12729 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
12730 | break; |
12731 | } | |
12732 | } | |
12733 | ||
9a935856 DV |
12734 | /* If we disable the crtc, disable all its connectors. Also, if |
12735 | * the connector is on the changing crtc but not on the new | |
12736 | * connector list, disable it. */ | |
12737 | if ((!set->fb || ro == set->num_connectors) && | |
12738 | connector->base.encoder && | |
12739 | connector->base.encoder->crtc == set->crtc) { | |
12740 | connector->new_encoder = NULL; | |
12741 | ||
12742 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
12743 | connector->base.base.id, | |
c23cc417 | 12744 | connector->base.name); |
9a935856 | 12745 | } |
50f56119 | 12746 | } |
9a935856 | 12747 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 12748 | |
9a935856 | 12749 | /* Update crtc of enabled connectors. */ |
3a3371ff | 12750 | for_each_intel_connector(dev, connector) { |
7668851f VS |
12751 | struct drm_crtc *new_crtc; |
12752 | ||
9a935856 | 12753 | if (!connector->new_encoder) |
50f56119 DV |
12754 | continue; |
12755 | ||
9a935856 | 12756 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
12757 | |
12758 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 12759 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
12760 | new_crtc = set->crtc; |
12761 | } | |
12762 | ||
12763 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
12764 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
12765 | new_crtc)) { | |
5e2b584e | 12766 | return -EINVAL; |
50f56119 | 12767 | } |
0e32b39c | 12768 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 | 12769 | |
944b0c76 ACO |
12770 | connector_state = |
12771 | drm_atomic_get_connector_state(state, &connector->base); | |
12772 | if (IS_ERR(connector_state)) | |
12773 | return PTR_ERR(connector_state); | |
12774 | ||
12775 | connector_state->crtc = new_crtc; | |
12776 | connector_state->best_encoder = &connector->new_encoder->base; | |
12777 | ||
9a935856 DV |
12778 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", |
12779 | connector->base.base.id, | |
c23cc417 | 12780 | connector->base.name, |
9a935856 DV |
12781 | new_crtc->base.id); |
12782 | } | |
12783 | ||
12784 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 12785 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 12786 | int num_connectors = 0; |
3a3371ff | 12787 | for_each_intel_connector(dev, connector) { |
9a935856 DV |
12788 | if (connector->new_encoder == encoder) { |
12789 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 12790 | num_connectors++; |
9a935856 DV |
12791 | } |
12792 | } | |
5a65f358 PZ |
12793 | |
12794 | if (num_connectors == 0) | |
12795 | encoder->new_crtc = NULL; | |
12796 | else if (num_connectors > 1) | |
12797 | return -EINVAL; | |
50f56119 | 12798 | } |
9a935856 | 12799 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
3a3371ff | 12800 | for_each_intel_connector(dev, connector) { |
944b0c76 ACO |
12801 | connector_state = |
12802 | drm_atomic_get_connector_state(state, &connector->base); | |
9d918c15 ACO |
12803 | if (IS_ERR(connector_state)) |
12804 | return PTR_ERR(connector_state); | |
944b0c76 ACO |
12805 | |
12806 | if (connector->new_encoder) { | |
0e32b39c DA |
12807 | if (connector->new_encoder != connector->encoder) |
12808 | connector->encoder = connector->new_encoder; | |
944b0c76 ACO |
12809 | } else { |
12810 | connector_state->crtc = NULL; | |
f61cccf3 | 12811 | connector_state->best_encoder = NULL; |
944b0c76 | 12812 | } |
0e32b39c | 12813 | } |
d3fcc808 | 12814 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
12815 | crtc->new_enabled = false; |
12816 | ||
b2784e15 | 12817 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
12818 | if (encoder->new_crtc == crtc) { |
12819 | crtc->new_enabled = true; | |
12820 | break; | |
12821 | } | |
12822 | } | |
4be07317 ACO |
12823 | |
12824 | if (crtc->new_enabled != crtc->base.state->enable) { | |
12825 | crtc_state = intel_atomic_get_crtc_state(state, crtc); | |
12826 | if (IS_ERR(crtc_state)) | |
12827 | return PTR_ERR(crtc_state); | |
12828 | ||
12829 | crtc_state->base.enable = crtc->new_enabled; | |
12830 | } | |
7668851f VS |
12831 | } |
12832 | ||
2e431051 DV |
12833 | return 0; |
12834 | } | |
12835 | ||
7d00a1f5 VS |
12836 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
12837 | { | |
12838 | struct drm_device *dev = crtc->base.dev; | |
12839 | struct intel_encoder *encoder; | |
12840 | struct intel_connector *connector; | |
12841 | ||
12842 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
12843 | pipe_name(crtc->pipe)); | |
12844 | ||
3a3371ff | 12845 | for_each_intel_connector(dev, connector) { |
7d00a1f5 VS |
12846 | if (connector->new_encoder && |
12847 | connector->new_encoder->new_crtc == crtc) | |
12848 | connector->new_encoder = NULL; | |
12849 | } | |
12850 | ||
b2784e15 | 12851 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
12852 | if (encoder->new_crtc == crtc) |
12853 | encoder->new_crtc = NULL; | |
12854 | } | |
12855 | ||
12856 | crtc->new_enabled = false; | |
12857 | } | |
12858 | ||
2e431051 DV |
12859 | static int intel_crtc_set_config(struct drm_mode_set *set) |
12860 | { | |
12861 | struct drm_device *dev; | |
2e431051 | 12862 | struct drm_mode_set save_set; |
83a57153 | 12863 | struct drm_atomic_state *state = NULL; |
2e431051 | 12864 | struct intel_set_config *config; |
5cec258b | 12865 | struct intel_crtc_state *pipe_config; |
50f52756 | 12866 | unsigned modeset_pipes, prepare_pipes, disable_pipes; |
2e431051 | 12867 | int ret; |
2e431051 | 12868 | |
8d3e375e DV |
12869 | BUG_ON(!set); |
12870 | BUG_ON(!set->crtc); | |
12871 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 12872 | |
7e53f3a4 DV |
12873 | /* Enforce sane interface api - has been abused by the fb helper. */ |
12874 | BUG_ON(!set->mode && set->fb); | |
12875 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 12876 | |
2e431051 DV |
12877 | if (set->fb) { |
12878 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
12879 | set->crtc->base.id, set->fb->base.id, | |
12880 | (int)set->num_connectors, set->x, set->y); | |
12881 | } else { | |
12882 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
12883 | } |
12884 | ||
12885 | dev = set->crtc->dev; | |
12886 | ||
12887 | ret = -ENOMEM; | |
12888 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
12889 | if (!config) | |
12890 | goto out_config; | |
12891 | ||
12892 | ret = intel_set_config_save_state(dev, config); | |
12893 | if (ret) | |
12894 | goto out_config; | |
12895 | ||
12896 | save_set.crtc = set->crtc; | |
12897 | save_set.mode = &set->crtc->mode; | |
12898 | save_set.x = set->crtc->x; | |
12899 | save_set.y = set->crtc->y; | |
f4510a27 | 12900 | save_set.fb = set->crtc->primary->fb; |
2e431051 | 12901 | |
83a57153 ACO |
12902 | state = drm_atomic_state_alloc(dev); |
12903 | if (!state) { | |
12904 | ret = -ENOMEM; | |
12905 | goto out_config; | |
12906 | } | |
12907 | ||
12908 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
12909 | ||
462a425a | 12910 | ret = intel_modeset_stage_output_state(dev, set, state); |
2e431051 DV |
12911 | if (ret) |
12912 | goto fail; | |
12913 | ||
462a425a ACO |
12914 | /* Compute whether we need a full modeset, only an fb base update or no |
12915 | * change at all. In the future we might also check whether only the | |
12916 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
12917 | * such cases. */ | |
12918 | intel_set_config_compute_mode_changes(set, config); | |
12919 | ||
50f52756 | 12920 | pipe_config = intel_modeset_compute_config(set->crtc, set->mode, |
8805aa71 | 12921 | state, |
50f52756 JB |
12922 | &modeset_pipes, |
12923 | &prepare_pipes, | |
12924 | &disable_pipes); | |
20664591 | 12925 | if (IS_ERR(pipe_config)) { |
6ac0483b | 12926 | ret = PTR_ERR(pipe_config); |
50f52756 | 12927 | goto fail; |
20664591 | 12928 | } else if (pipe_config) { |
b9950a13 | 12929 | if (pipe_config->has_audio != |
6e3c9717 | 12930 | to_intel_crtc(set->crtc)->config->has_audio) |
20664591 JB |
12931 | config->mode_changed = true; |
12932 | ||
af15d2ce JB |
12933 | /* |
12934 | * Note we have an issue here with infoframes: current code | |
12935 | * only updates them on the full mode set path per hw | |
12936 | * requirements. So here we should be checking for any | |
12937 | * required changes and forcing a mode set. | |
12938 | */ | |
20664591 | 12939 | } |
50f52756 | 12940 | |
1f9954d0 JB |
12941 | intel_update_pipe_size(to_intel_crtc(set->crtc)); |
12942 | ||
5e2b584e | 12943 | if (config->mode_changed) { |
50f52756 JB |
12944 | ret = intel_set_mode_pipes(set->crtc, set->mode, |
12945 | set->x, set->y, set->fb, pipe_config, | |
12946 | modeset_pipes, prepare_pipes, | |
12947 | disable_pipes); | |
5e2b584e | 12948 | } else if (config->fb_changed) { |
3b150f08 | 12949 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
455a6808 | 12950 | struct drm_plane *primary = set->crtc->primary; |
b70709a6 ML |
12951 | struct intel_plane_state *plane_state = |
12952 | to_intel_plane_state(primary->state); | |
12953 | bool was_visible = plane_state->visible; | |
455a6808 | 12954 | int vdisplay, hdisplay; |
3b150f08 | 12955 | |
455a6808 | 12956 | drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay); |
70a101f8 MR |
12957 | ret = drm_plane_helper_update(primary, set->crtc, set->fb, |
12958 | 0, 0, hdisplay, vdisplay, | |
12959 | set->x << 16, set->y << 16, | |
12960 | hdisplay << 16, vdisplay << 16); | |
3b150f08 MR |
12961 | |
12962 | /* | |
12963 | * We need to make sure the primary plane is re-enabled if it | |
12964 | * has previously been turned off. | |
12965 | */ | |
b70709a6 ML |
12966 | plane_state = to_intel_plane_state(primary->state); |
12967 | if (ret == 0 && !was_visible && plane_state->visible) { | |
3b150f08 | 12968 | WARN_ON(!intel_crtc->active); |
87d4300a | 12969 | intel_post_enable_primary(set->crtc); |
3b150f08 MR |
12970 | } |
12971 | ||
7ca51a3a JB |
12972 | /* |
12973 | * In the fastboot case this may be our only check of the | |
12974 | * state after boot. It would be better to only do it on | |
12975 | * the first update, but we don't have a nice way of doing that | |
12976 | * (and really, set_config isn't used much for high freq page | |
12977 | * flipping, so increasing its cost here shouldn't be a big | |
12978 | * deal). | |
12979 | */ | |
d330a953 | 12980 | if (i915.fastboot && ret == 0) |
7ca51a3a | 12981 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
12982 | } |
12983 | ||
2d05eae1 | 12984 | if (ret) { |
bf67dfeb DV |
12985 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
12986 | set->crtc->base.id, ret); | |
50f56119 | 12987 | fail: |
2d05eae1 | 12988 | intel_set_config_restore_state(dev, config); |
50f56119 | 12989 | |
83a57153 ACO |
12990 | drm_atomic_state_clear(state); |
12991 | ||
7d00a1f5 VS |
12992 | /* |
12993 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
12994 | * force the pipe off to avoid oopsing in the modeset code | |
12995 | * due to fb==NULL. This should only happen during boot since | |
12996 | * we don't yet reconstruct the FB from the hardware state. | |
12997 | */ | |
12998 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
12999 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
13000 | ||
2d05eae1 CW |
13001 | /* Try to restore the config */ |
13002 | if (config->mode_changed && | |
13003 | intel_set_mode(save_set.crtc, save_set.mode, | |
83a57153 ACO |
13004 | save_set.x, save_set.y, save_set.fb, |
13005 | state)) | |
2d05eae1 CW |
13006 | DRM_ERROR("failed to restore config after modeset failure\n"); |
13007 | } | |
50f56119 | 13008 | |
d9e55608 | 13009 | out_config: |
e5d958ef | 13010 | drm_atomic_state_free(state); |
83a57153 | 13011 | |
d9e55608 | 13012 | intel_set_config_free(config); |
50f56119 DV |
13013 | return ret; |
13014 | } | |
f6e5b160 CW |
13015 | |
13016 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 13017 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 13018 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
13019 | .destroy = intel_crtc_destroy, |
13020 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13021 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13022 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13023 | }; |
13024 | ||
5358901f DV |
13025 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13026 | struct intel_shared_dpll *pll, | |
13027 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13028 | { |
5358901f | 13029 | uint32_t val; |
ee7b9f93 | 13030 | |
f458ebbc | 13031 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13032 | return false; |
13033 | ||
5358901f | 13034 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13035 | hw_state->dpll = val; |
13036 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13037 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13038 | |
13039 | return val & DPLL_VCO_ENABLE; | |
13040 | } | |
13041 | ||
15bdd4cf DV |
13042 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13043 | struct intel_shared_dpll *pll) | |
13044 | { | |
3e369b76 ACO |
13045 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13046 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13047 | } |
13048 | ||
e7b903d2 DV |
13049 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13050 | struct intel_shared_dpll *pll) | |
13051 | { | |
e7b903d2 | 13052 | /* PCH refclock must be enabled first */ |
89eff4be | 13053 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13054 | |
3e369b76 | 13055 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13056 | |
13057 | /* Wait for the clocks to stabilize. */ | |
13058 | POSTING_READ(PCH_DPLL(pll->id)); | |
13059 | udelay(150); | |
13060 | ||
13061 | /* The pixel multiplier can only be updated once the | |
13062 | * DPLL is enabled and the clocks are stable. | |
13063 | * | |
13064 | * So write it again. | |
13065 | */ | |
3e369b76 | 13066 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13067 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13068 | udelay(200); |
13069 | } | |
13070 | ||
13071 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13072 | struct intel_shared_dpll *pll) | |
13073 | { | |
13074 | struct drm_device *dev = dev_priv->dev; | |
13075 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13076 | |
13077 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13078 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13079 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13080 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13081 | } |
13082 | ||
15bdd4cf DV |
13083 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13084 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13085 | udelay(200); |
13086 | } | |
13087 | ||
46edb027 DV |
13088 | static char *ibx_pch_dpll_names[] = { |
13089 | "PCH DPLL A", | |
13090 | "PCH DPLL B", | |
13091 | }; | |
13092 | ||
7c74ade1 | 13093 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13094 | { |
e7b903d2 | 13095 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13096 | int i; |
13097 | ||
7c74ade1 | 13098 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13099 | |
e72f9fbf | 13100 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13101 | dev_priv->shared_dplls[i].id = i; |
13102 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13103 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13104 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13105 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13106 | dev_priv->shared_dplls[i].get_hw_state = |
13107 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13108 | } |
13109 | } | |
13110 | ||
7c74ade1 DV |
13111 | static void intel_shared_dpll_init(struct drm_device *dev) |
13112 | { | |
e7b903d2 | 13113 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13114 | |
9cd86933 DV |
13115 | if (HAS_DDI(dev)) |
13116 | intel_ddi_pll_init(dev); | |
13117 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13118 | ibx_pch_dpll_init(dev); |
13119 | else | |
13120 | dev_priv->num_shared_dpll = 0; | |
13121 | ||
13122 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13123 | } |
13124 | ||
1fc0a8f7 TU |
13125 | /** |
13126 | * intel_wm_need_update - Check whether watermarks need updating | |
13127 | * @plane: drm plane | |
13128 | * @state: new plane state | |
13129 | * | |
13130 | * Check current plane state versus the new one to determine whether | |
13131 | * watermarks need to be recalculated. | |
13132 | * | |
13133 | * Returns true or false. | |
13134 | */ | |
13135 | bool intel_wm_need_update(struct drm_plane *plane, | |
13136 | struct drm_plane_state *state) | |
13137 | { | |
13138 | /* Update watermarks on tiling changes. */ | |
13139 | if (!plane->state->fb || !state->fb || | |
13140 | plane->state->fb->modifier[0] != state->fb->modifier[0] || | |
13141 | plane->state->rotation != state->rotation) | |
13142 | return true; | |
13143 | ||
13144 | return false; | |
13145 | } | |
13146 | ||
6beb8c23 MR |
13147 | /** |
13148 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13149 | * @plane: drm plane to prepare for | |
13150 | * @fb: framebuffer to prepare for presentation | |
13151 | * | |
13152 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13153 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13154 | * bits. Some older platforms need special physical address handling for | |
13155 | * cursor planes. | |
13156 | * | |
13157 | * Returns 0 on success, negative error code on failure. | |
13158 | */ | |
13159 | int | |
13160 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13161 | struct drm_framebuffer *fb, |
13162 | const struct drm_plane_state *new_state) | |
465c120c MR |
13163 | { |
13164 | struct drm_device *dev = plane->dev; | |
6beb8c23 MR |
13165 | struct intel_plane *intel_plane = to_intel_plane(plane); |
13166 | enum pipe pipe = intel_plane->pipe; | |
13167 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13168 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
13169 | unsigned frontbuffer_bits = 0; | |
13170 | int ret = 0; | |
465c120c | 13171 | |
ea2c67bb | 13172 | if (!obj) |
465c120c MR |
13173 | return 0; |
13174 | ||
6beb8c23 MR |
13175 | switch (plane->type) { |
13176 | case DRM_PLANE_TYPE_PRIMARY: | |
13177 | frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe); | |
13178 | break; | |
13179 | case DRM_PLANE_TYPE_CURSOR: | |
13180 | frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe); | |
13181 | break; | |
13182 | case DRM_PLANE_TYPE_OVERLAY: | |
13183 | frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe); | |
13184 | break; | |
13185 | } | |
465c120c | 13186 | |
6beb8c23 | 13187 | mutex_lock(&dev->struct_mutex); |
465c120c | 13188 | |
6beb8c23 MR |
13189 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
13190 | INTEL_INFO(dev)->cursor_needs_physical) { | |
13191 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13192 | ret = i915_gem_object_attach_phys(obj, align); | |
13193 | if (ret) | |
13194 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13195 | } else { | |
82bc3b2d | 13196 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL); |
6beb8c23 | 13197 | } |
465c120c | 13198 | |
6beb8c23 MR |
13199 | if (ret == 0) |
13200 | i915_gem_track_fb(old_obj, obj, frontbuffer_bits); | |
fdd508a6 | 13201 | |
4c34574f | 13202 | mutex_unlock(&dev->struct_mutex); |
465c120c | 13203 | |
6beb8c23 MR |
13204 | return ret; |
13205 | } | |
13206 | ||
38f3ce3a MR |
13207 | /** |
13208 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13209 | * @plane: drm plane to clean up for | |
13210 | * @fb: old framebuffer that was on plane | |
13211 | * | |
13212 | * Cleans up a framebuffer that has just been removed from a plane. | |
13213 | */ | |
13214 | void | |
13215 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee TU |
13216 | struct drm_framebuffer *fb, |
13217 | const struct drm_plane_state *old_state) | |
38f3ce3a MR |
13218 | { |
13219 | struct drm_device *dev = plane->dev; | |
13220 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
13221 | ||
13222 | if (WARN_ON(!obj)) | |
13223 | return; | |
13224 | ||
13225 | if (plane->type != DRM_PLANE_TYPE_CURSOR || | |
13226 | !INTEL_INFO(dev)->cursor_needs_physical) { | |
13227 | mutex_lock(&dev->struct_mutex); | |
82bc3b2d | 13228 | intel_unpin_fb_obj(fb, old_state); |
38f3ce3a MR |
13229 | mutex_unlock(&dev->struct_mutex); |
13230 | } | |
465c120c MR |
13231 | } |
13232 | ||
6156a456 CK |
13233 | int |
13234 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13235 | { | |
13236 | int max_scale; | |
13237 | struct drm_device *dev; | |
13238 | struct drm_i915_private *dev_priv; | |
13239 | int crtc_clock, cdclk; | |
13240 | ||
13241 | if (!intel_crtc || !crtc_state) | |
13242 | return DRM_PLANE_HELPER_NO_SCALING; | |
13243 | ||
13244 | dev = intel_crtc->base.dev; | |
13245 | dev_priv = dev->dev_private; | |
13246 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
13247 | cdclk = dev_priv->display.get_display_clock_speed(dev); | |
13248 | ||
13249 | if (!crtc_clock || !cdclk) | |
13250 | return DRM_PLANE_HELPER_NO_SCALING; | |
13251 | ||
13252 | /* | |
13253 | * skl max scale is lower of: | |
13254 | * close to 3 but not 3, -1 is for that purpose | |
13255 | * or | |
13256 | * cdclk/crtc_clock | |
13257 | */ | |
13258 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13259 | ||
13260 | return max_scale; | |
13261 | } | |
13262 | ||
465c120c | 13263 | static int |
3c692a41 GP |
13264 | intel_check_primary_plane(struct drm_plane *plane, |
13265 | struct intel_plane_state *state) | |
13266 | { | |
32b7eeec MR |
13267 | struct drm_device *dev = plane->dev; |
13268 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2b875c22 | 13269 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13270 | struct intel_crtc *intel_crtc; |
6156a456 | 13271 | struct intel_crtc_state *crtc_state; |
2b875c22 | 13272 | struct drm_framebuffer *fb = state->base.fb; |
3c692a41 GP |
13273 | struct drm_rect *dest = &state->dst; |
13274 | struct drm_rect *src = &state->src; | |
13275 | const struct drm_rect *clip = &state->clip; | |
d8106366 | 13276 | bool can_position = false; |
6156a456 CK |
13277 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13278 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; | |
465c120c MR |
13279 | int ret; |
13280 | ||
ea2c67bb MR |
13281 | crtc = crtc ? crtc : plane->crtc; |
13282 | intel_crtc = to_intel_crtc(crtc); | |
6156a456 CK |
13283 | crtc_state = state->base.state ? |
13284 | intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL; | |
ea2c67bb | 13285 | |
6156a456 CK |
13286 | if (INTEL_INFO(dev)->gen >= 9) { |
13287 | min_scale = 1; | |
13288 | max_scale = skl_max_scale(intel_crtc, crtc_state); | |
d8106366 | 13289 | can_position = true; |
6156a456 | 13290 | } |
d8106366 | 13291 | |
c59cb179 MR |
13292 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
13293 | src, dest, clip, | |
6156a456 CK |
13294 | min_scale, |
13295 | max_scale, | |
d8106366 SJ |
13296 | can_position, true, |
13297 | &state->visible); | |
c59cb179 MR |
13298 | if (ret) |
13299 | return ret; | |
465c120c | 13300 | |
32b7eeec | 13301 | if (intel_crtc->active) { |
b70709a6 ML |
13302 | struct intel_plane_state *old_state = |
13303 | to_intel_plane_state(plane->state); | |
13304 | ||
32b7eeec MR |
13305 | intel_crtc->atomic.wait_for_flips = true; |
13306 | ||
13307 | /* | |
13308 | * FBC does not work on some platforms for rotated | |
13309 | * planes, so disable it when rotation is not 0 and | |
13310 | * update it when rotation is set back to 0. | |
13311 | * | |
13312 | * FIXME: This is redundant with the fbc update done in | |
13313 | * the primary plane enable function except that that | |
13314 | * one is done too late. We eventually need to unify | |
13315 | * this. | |
13316 | */ | |
b70709a6 | 13317 | if (state->visible && |
32b7eeec | 13318 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
e35fef21 | 13319 | dev_priv->fbc.crtc == intel_crtc && |
8e7d688b | 13320 | state->base.rotation != BIT(DRM_ROTATE_0)) { |
32b7eeec MR |
13321 | intel_crtc->atomic.disable_fbc = true; |
13322 | } | |
13323 | ||
b70709a6 | 13324 | if (state->visible && !old_state->visible) { |
32b7eeec MR |
13325 | /* |
13326 | * BDW signals flip done immediately if the plane | |
13327 | * is disabled, even if the plane enable is already | |
13328 | * armed to occur at the next vblank :( | |
13329 | */ | |
b70709a6 | 13330 | if (IS_BROADWELL(dev)) |
32b7eeec MR |
13331 | intel_crtc->atomic.wait_vblank = true; |
13332 | } | |
13333 | ||
13334 | intel_crtc->atomic.fb_bits |= | |
13335 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); | |
13336 | ||
13337 | intel_crtc->atomic.update_fbc = true; | |
0fda6568 | 13338 | |
1fc0a8f7 | 13339 | if (intel_wm_need_update(plane, &state->base)) |
0fda6568 | 13340 | intel_crtc->atomic.update_wm = true; |
ccc759dc GP |
13341 | } |
13342 | ||
6156a456 CK |
13343 | if (INTEL_INFO(dev)->gen >= 9) { |
13344 | ret = skl_update_scaler_users(intel_crtc, crtc_state, | |
13345 | to_intel_plane(plane), state, 0); | |
13346 | if (ret) | |
13347 | return ret; | |
13348 | } | |
13349 | ||
14af293f GP |
13350 | return 0; |
13351 | } | |
13352 | ||
13353 | static void | |
13354 | intel_commit_primary_plane(struct drm_plane *plane, | |
13355 | struct intel_plane_state *state) | |
13356 | { | |
2b875c22 MR |
13357 | struct drm_crtc *crtc = state->base.crtc; |
13358 | struct drm_framebuffer *fb = state->base.fb; | |
13359 | struct drm_device *dev = plane->dev; | |
14af293f | 13360 | struct drm_i915_private *dev_priv = dev->dev_private; |
ea2c67bb | 13361 | struct intel_crtc *intel_crtc; |
14af293f GP |
13362 | struct drm_rect *src = &state->src; |
13363 | ||
ea2c67bb MR |
13364 | crtc = crtc ? crtc : plane->crtc; |
13365 | intel_crtc = to_intel_crtc(crtc); | |
cf4c7c12 MR |
13366 | |
13367 | plane->fb = fb; | |
9dc806fc MR |
13368 | crtc->x = src->x1 >> 16; |
13369 | crtc->y = src->y1 >> 16; | |
ccc759dc | 13370 | |
ccc759dc | 13371 | if (intel_crtc->active) { |
27321ae8 | 13372 | if (state->visible) |
ccc759dc GP |
13373 | /* FIXME: kill this fastboot hack */ |
13374 | intel_update_pipe_size(intel_crtc); | |
465c120c | 13375 | |
27321ae8 ML |
13376 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
13377 | crtc->x, crtc->y); | |
ccc759dc | 13378 | } |
465c120c MR |
13379 | } |
13380 | ||
a8ad0d8e ML |
13381 | static void |
13382 | intel_disable_primary_plane(struct drm_plane *plane, | |
13383 | struct drm_crtc *crtc, | |
13384 | bool force) | |
13385 | { | |
13386 | struct drm_device *dev = plane->dev; | |
13387 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13388 | ||
a8ad0d8e ML |
13389 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13390 | } | |
13391 | ||
32b7eeec | 13392 | static void intel_begin_crtc_commit(struct drm_crtc *crtc) |
3c692a41 | 13393 | { |
32b7eeec | 13394 | struct drm_device *dev = crtc->dev; |
140fd38d | 13395 | struct drm_i915_private *dev_priv = dev->dev_private; |
3c692a41 | 13396 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ea2c67bb MR |
13397 | struct intel_plane *intel_plane; |
13398 | struct drm_plane *p; | |
13399 | unsigned fb_bits = 0; | |
13400 | ||
13401 | /* Track fb's for any planes being disabled */ | |
13402 | list_for_each_entry(p, &dev->mode_config.plane_list, head) { | |
13403 | intel_plane = to_intel_plane(p); | |
13404 | ||
13405 | if (intel_crtc->atomic.disabled_planes & | |
13406 | (1 << drm_plane_index(p))) { | |
13407 | switch (p->type) { | |
13408 | case DRM_PLANE_TYPE_PRIMARY: | |
13409 | fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe); | |
13410 | break; | |
13411 | case DRM_PLANE_TYPE_CURSOR: | |
13412 | fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe); | |
13413 | break; | |
13414 | case DRM_PLANE_TYPE_OVERLAY: | |
13415 | fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe); | |
13416 | break; | |
13417 | } | |
3c692a41 | 13418 | |
ea2c67bb MR |
13419 | mutex_lock(&dev->struct_mutex); |
13420 | i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits); | |
13421 | mutex_unlock(&dev->struct_mutex); | |
13422 | } | |
13423 | } | |
3c692a41 | 13424 | |
32b7eeec MR |
13425 | if (intel_crtc->atomic.wait_for_flips) |
13426 | intel_crtc_wait_for_pending_flips(crtc); | |
3c692a41 | 13427 | |
32b7eeec MR |
13428 | if (intel_crtc->atomic.disable_fbc) |
13429 | intel_fbc_disable(dev); | |
3c692a41 | 13430 | |
32b7eeec MR |
13431 | if (intel_crtc->atomic.pre_disable_primary) |
13432 | intel_pre_disable_primary(crtc); | |
3c692a41 | 13433 | |
32b7eeec MR |
13434 | if (intel_crtc->atomic.update_wm) |
13435 | intel_update_watermarks(crtc); | |
3c692a41 | 13436 | |
32b7eeec | 13437 | intel_runtime_pm_get(dev_priv); |
3c692a41 | 13438 | |
c34c9ee4 MR |
13439 | /* Perform vblank evasion around commit operation */ |
13440 | if (intel_crtc->active) | |
13441 | intel_crtc->atomic.evade = | |
13442 | intel_pipe_update_start(intel_crtc, | |
13443 | &intel_crtc->atomic.start_vbl_count); | |
32b7eeec MR |
13444 | } |
13445 | ||
13446 | static void intel_finish_crtc_commit(struct drm_crtc *crtc) | |
13447 | { | |
13448 | struct drm_device *dev = crtc->dev; | |
13449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13450 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13451 | struct drm_plane *p; | |
13452 | ||
c34c9ee4 MR |
13453 | if (intel_crtc->atomic.evade) |
13454 | intel_pipe_update_end(intel_crtc, | |
13455 | intel_crtc->atomic.start_vbl_count); | |
3c692a41 | 13456 | |
140fd38d | 13457 | intel_runtime_pm_put(dev_priv); |
3c692a41 | 13458 | |
32b7eeec MR |
13459 | if (intel_crtc->atomic.wait_vblank) |
13460 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
13461 | ||
13462 | intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits); | |
13463 | ||
13464 | if (intel_crtc->atomic.update_fbc) { | |
ccc759dc | 13465 | mutex_lock(&dev->struct_mutex); |
7ff0ebcc | 13466 | intel_fbc_update(dev); |
ccc759dc | 13467 | mutex_unlock(&dev->struct_mutex); |
38f3ce3a | 13468 | } |
3c692a41 | 13469 | |
32b7eeec MR |
13470 | if (intel_crtc->atomic.post_enable_primary) |
13471 | intel_post_enable_primary(crtc); | |
3c692a41 | 13472 | |
32b7eeec MR |
13473 | drm_for_each_legacy_plane(p, &dev->mode_config.plane_list) |
13474 | if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p)) | |
13475 | intel_update_sprite_watermarks(p, crtc, 0, 0, 0, | |
13476 | false, false); | |
13477 | ||
13478 | memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic)); | |
3c692a41 GP |
13479 | } |
13480 | ||
cf4c7c12 | 13481 | /** |
4a3b8769 MR |
13482 | * intel_plane_destroy - destroy a plane |
13483 | * @plane: plane to destroy | |
cf4c7c12 | 13484 | * |
4a3b8769 MR |
13485 | * Common destruction function for all types of planes (primary, cursor, |
13486 | * sprite). | |
cf4c7c12 | 13487 | */ |
4a3b8769 | 13488 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13489 | { |
13490 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13491 | drm_plane_cleanup(plane); | |
13492 | kfree(intel_plane); | |
13493 | } | |
13494 | ||
65a3fea0 | 13495 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13496 | .update_plane = drm_atomic_helper_update_plane, |
13497 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13498 | .destroy = intel_plane_destroy, |
c196e1d6 | 13499 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13500 | .atomic_get_property = intel_plane_atomic_get_property, |
13501 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13502 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13503 | .atomic_destroy_state = intel_plane_destroy_state, | |
13504 | ||
465c120c MR |
13505 | }; |
13506 | ||
13507 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13508 | int pipe) | |
13509 | { | |
13510 | struct intel_plane *primary; | |
8e7d688b | 13511 | struct intel_plane_state *state; |
465c120c MR |
13512 | const uint32_t *intel_primary_formats; |
13513 | int num_formats; | |
13514 | ||
13515 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13516 | if (primary == NULL) | |
13517 | return NULL; | |
13518 | ||
8e7d688b MR |
13519 | state = intel_create_plane_state(&primary->base); |
13520 | if (!state) { | |
ea2c67bb MR |
13521 | kfree(primary); |
13522 | return NULL; | |
13523 | } | |
8e7d688b | 13524 | primary->base.state = &state->base; |
ea2c67bb | 13525 | |
465c120c MR |
13526 | primary->can_scale = false; |
13527 | primary->max_downscale = 1; | |
6156a456 CK |
13528 | if (INTEL_INFO(dev)->gen >= 9) { |
13529 | primary->can_scale = true; | |
13530 | } | |
549e2bfb | 13531 | state->scaler_id = -1; |
465c120c MR |
13532 | primary->pipe = pipe; |
13533 | primary->plane = pipe; | |
c59cb179 MR |
13534 | primary->check_plane = intel_check_primary_plane; |
13535 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13536 | primary->disable_plane = intel_disable_primary_plane; |
08e221fb | 13537 | primary->ckey.flags = I915_SET_COLORKEY_NONE; |
465c120c MR |
13538 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13539 | primary->plane = !pipe; | |
13540 | ||
13541 | if (INTEL_INFO(dev)->gen <= 3) { | |
13542 | intel_primary_formats = intel_primary_formats_gen2; | |
13543 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
13544 | } else { | |
13545 | intel_primary_formats = intel_primary_formats_gen4; | |
13546 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
13547 | } | |
13548 | ||
13549 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 13550 | &intel_plane_funcs, |
465c120c MR |
13551 | intel_primary_formats, num_formats, |
13552 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 13553 | |
3b7a5119 SJ |
13554 | if (INTEL_INFO(dev)->gen >= 4) |
13555 | intel_create_rotation_property(dev, primary); | |
48404c1e | 13556 | |
ea2c67bb MR |
13557 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13558 | ||
465c120c MR |
13559 | return &primary->base; |
13560 | } | |
13561 | ||
3b7a5119 SJ |
13562 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
13563 | { | |
13564 | if (!dev->mode_config.rotation_property) { | |
13565 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
13566 | BIT(DRM_ROTATE_180); | |
13567 | ||
13568 | if (INTEL_INFO(dev)->gen >= 9) | |
13569 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
13570 | ||
13571 | dev->mode_config.rotation_property = | |
13572 | drm_mode_create_rotation_property(dev, flags); | |
13573 | } | |
13574 | if (dev->mode_config.rotation_property) | |
13575 | drm_object_attach_property(&plane->base.base, | |
13576 | dev->mode_config.rotation_property, | |
13577 | plane->base.state->rotation); | |
13578 | } | |
13579 | ||
3d7d6510 | 13580 | static int |
852e787c GP |
13581 | intel_check_cursor_plane(struct drm_plane *plane, |
13582 | struct intel_plane_state *state) | |
3d7d6510 | 13583 | { |
2b875c22 | 13584 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb | 13585 | struct drm_device *dev = plane->dev; |
2b875c22 | 13586 | struct drm_framebuffer *fb = state->base.fb; |
852e787c GP |
13587 | struct drm_rect *dest = &state->dst; |
13588 | struct drm_rect *src = &state->src; | |
13589 | const struct drm_rect *clip = &state->clip; | |
757f9a3e | 13590 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
ea2c67bb | 13591 | struct intel_crtc *intel_crtc; |
757f9a3e GP |
13592 | unsigned stride; |
13593 | int ret; | |
3d7d6510 | 13594 | |
ea2c67bb MR |
13595 | crtc = crtc ? crtc : plane->crtc; |
13596 | intel_crtc = to_intel_crtc(crtc); | |
13597 | ||
757f9a3e | 13598 | ret = drm_plane_helper_check_update(plane, crtc, fb, |
852e787c | 13599 | src, dest, clip, |
3d7d6510 MR |
13600 | DRM_PLANE_HELPER_NO_SCALING, |
13601 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 13602 | true, true, &state->visible); |
757f9a3e GP |
13603 | if (ret) |
13604 | return ret; | |
13605 | ||
13606 | ||
13607 | /* if we want to turn off the cursor ignore width and height */ | |
13608 | if (!obj) | |
32b7eeec | 13609 | goto finish; |
757f9a3e | 13610 | |
757f9a3e | 13611 | /* Check for which cursor types we support */ |
ea2c67bb MR |
13612 | if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) { |
13613 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
13614 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13615 | return -EINVAL; |
13616 | } | |
13617 | ||
ea2c67bb MR |
13618 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13619 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13620 | DRM_DEBUG_KMS("buffer is too small\n"); |
13621 | return -ENOMEM; | |
13622 | } | |
13623 | ||
3a656b54 | 13624 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e GP |
13625 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
13626 | ret = -EINVAL; | |
13627 | } | |
757f9a3e | 13628 | |
32b7eeec MR |
13629 | finish: |
13630 | if (intel_crtc->active) { | |
3749f463 | 13631 | if (plane->state->crtc_w != state->base.crtc_w) |
32b7eeec MR |
13632 | intel_crtc->atomic.update_wm = true; |
13633 | ||
13634 | intel_crtc->atomic.fb_bits |= | |
13635 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe); | |
13636 | } | |
13637 | ||
757f9a3e | 13638 | return ret; |
852e787c | 13639 | } |
3d7d6510 | 13640 | |
a8ad0d8e ML |
13641 | static void |
13642 | intel_disable_cursor_plane(struct drm_plane *plane, | |
13643 | struct drm_crtc *crtc, | |
13644 | bool force) | |
13645 | { | |
13646 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13647 | ||
13648 | if (!force) { | |
13649 | plane->fb = NULL; | |
13650 | intel_crtc->cursor_bo = NULL; | |
13651 | intel_crtc->cursor_addr = 0; | |
13652 | } | |
13653 | ||
13654 | intel_crtc_update_cursor(crtc, false); | |
13655 | } | |
13656 | ||
f4a2cf29 | 13657 | static void |
852e787c GP |
13658 | intel_commit_cursor_plane(struct drm_plane *plane, |
13659 | struct intel_plane_state *state) | |
13660 | { | |
2b875c22 | 13661 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
13662 | struct drm_device *dev = plane->dev; |
13663 | struct intel_crtc *intel_crtc; | |
2b875c22 | 13664 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13665 | uint32_t addr; |
852e787c | 13666 | |
ea2c67bb MR |
13667 | crtc = crtc ? crtc : plane->crtc; |
13668 | intel_crtc = to_intel_crtc(crtc); | |
13669 | ||
2b875c22 | 13670 | plane->fb = state->base.fb; |
ea2c67bb MR |
13671 | crtc->cursor_x = state->base.crtc_x; |
13672 | crtc->cursor_y = state->base.crtc_y; | |
13673 | ||
a912f12f GP |
13674 | if (intel_crtc->cursor_bo == obj) |
13675 | goto update; | |
4ed91096 | 13676 | |
f4a2cf29 | 13677 | if (!obj) |
a912f12f | 13678 | addr = 0; |
f4a2cf29 | 13679 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 13680 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 13681 | else |
a912f12f | 13682 | addr = obj->phys_handle->busaddr; |
852e787c | 13683 | |
a912f12f GP |
13684 | intel_crtc->cursor_addr = addr; |
13685 | intel_crtc->cursor_bo = obj; | |
13686 | update: | |
852e787c | 13687 | |
32b7eeec | 13688 | if (intel_crtc->active) |
a912f12f | 13689 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
13690 | } |
13691 | ||
3d7d6510 MR |
13692 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
13693 | int pipe) | |
13694 | { | |
13695 | struct intel_plane *cursor; | |
8e7d688b | 13696 | struct intel_plane_state *state; |
3d7d6510 MR |
13697 | |
13698 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
13699 | if (cursor == NULL) | |
13700 | return NULL; | |
13701 | ||
8e7d688b MR |
13702 | state = intel_create_plane_state(&cursor->base); |
13703 | if (!state) { | |
ea2c67bb MR |
13704 | kfree(cursor); |
13705 | return NULL; | |
13706 | } | |
8e7d688b | 13707 | cursor->base.state = &state->base; |
ea2c67bb | 13708 | |
3d7d6510 MR |
13709 | cursor->can_scale = false; |
13710 | cursor->max_downscale = 1; | |
13711 | cursor->pipe = pipe; | |
13712 | cursor->plane = pipe; | |
549e2bfb | 13713 | state->scaler_id = -1; |
c59cb179 MR |
13714 | cursor->check_plane = intel_check_cursor_plane; |
13715 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 13716 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
13717 | |
13718 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 13719 | &intel_plane_funcs, |
3d7d6510 MR |
13720 | intel_cursor_formats, |
13721 | ARRAY_SIZE(intel_cursor_formats), | |
13722 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
13723 | |
13724 | if (INTEL_INFO(dev)->gen >= 4) { | |
13725 | if (!dev->mode_config.rotation_property) | |
13726 | dev->mode_config.rotation_property = | |
13727 | drm_mode_create_rotation_property(dev, | |
13728 | BIT(DRM_ROTATE_0) | | |
13729 | BIT(DRM_ROTATE_180)); | |
13730 | if (dev->mode_config.rotation_property) | |
13731 | drm_object_attach_property(&cursor->base.base, | |
13732 | dev->mode_config.rotation_property, | |
8e7d688b | 13733 | state->base.rotation); |
4398ad45 VS |
13734 | } |
13735 | ||
ea2c67bb MR |
13736 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13737 | ||
3d7d6510 MR |
13738 | return &cursor->base; |
13739 | } | |
13740 | ||
549e2bfb CK |
13741 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
13742 | struct intel_crtc_state *crtc_state) | |
13743 | { | |
13744 | int i; | |
13745 | struct intel_scaler *intel_scaler; | |
13746 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
13747 | ||
13748 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
13749 | intel_scaler = &scaler_state->scalers[i]; | |
13750 | intel_scaler->in_use = 0; | |
13751 | intel_scaler->id = i; | |
13752 | ||
13753 | intel_scaler->mode = PS_SCALER_MODE_DYN; | |
13754 | } | |
13755 | ||
13756 | scaler_state->scaler_id = -1; | |
13757 | } | |
13758 | ||
b358d0a6 | 13759 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 13760 | { |
fbee40df | 13761 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 13762 | struct intel_crtc *intel_crtc; |
f5de6e07 | 13763 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
13764 | struct drm_plane *primary = NULL; |
13765 | struct drm_plane *cursor = NULL; | |
465c120c | 13766 | int i, ret; |
79e53945 | 13767 | |
955382f3 | 13768 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
13769 | if (intel_crtc == NULL) |
13770 | return; | |
13771 | ||
f5de6e07 ACO |
13772 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
13773 | if (!crtc_state) | |
13774 | goto fail; | |
13775 | intel_crtc_set_state(intel_crtc, crtc_state); | |
07878248 | 13776 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13777 | |
549e2bfb CK |
13778 | /* initialize shared scalers */ |
13779 | if (INTEL_INFO(dev)->gen >= 9) { | |
13780 | if (pipe == PIPE_C) | |
13781 | intel_crtc->num_scalers = 1; | |
13782 | else | |
13783 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
13784 | ||
13785 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
13786 | } | |
13787 | ||
465c120c | 13788 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
13789 | if (!primary) |
13790 | goto fail; | |
13791 | ||
13792 | cursor = intel_cursor_plane_create(dev, pipe); | |
13793 | if (!cursor) | |
13794 | goto fail; | |
13795 | ||
465c120c | 13796 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
13797 | cursor, &intel_crtc_funcs); |
13798 | if (ret) | |
13799 | goto fail; | |
79e53945 JB |
13800 | |
13801 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
13802 | for (i = 0; i < 256; i++) { |
13803 | intel_crtc->lut_r[i] = i; | |
13804 | intel_crtc->lut_g[i] = i; | |
13805 | intel_crtc->lut_b[i] = i; | |
13806 | } | |
13807 | ||
1f1c2e24 VS |
13808 | /* |
13809 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 13810 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 13811 | */ |
80824003 JB |
13812 | intel_crtc->pipe = pipe; |
13813 | intel_crtc->plane = pipe; | |
3a77c4c4 | 13814 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 13815 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 13816 | intel_crtc->plane = !pipe; |
80824003 JB |
13817 | } |
13818 | ||
4b0e333e CW |
13819 | intel_crtc->cursor_base = ~0; |
13820 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13821 | intel_crtc->cursor_size = ~0; |
8d7849db | 13822 | |
22fd0fab JB |
13823 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13824 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
13825 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
13826 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
13827 | ||
9362c7c5 ACO |
13828 | INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func); |
13829 | ||
79e53945 | 13830 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
13831 | |
13832 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
13833 | return; |
13834 | ||
13835 | fail: | |
13836 | if (primary) | |
13837 | drm_plane_cleanup(primary); | |
13838 | if (cursor) | |
13839 | drm_plane_cleanup(cursor); | |
f5de6e07 | 13840 | kfree(crtc_state); |
3d7d6510 | 13841 | kfree(intel_crtc); |
79e53945 JB |
13842 | } |
13843 | ||
752aa88a JB |
13844 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13845 | { | |
13846 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13847 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13848 | |
51fd371b | 13849 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13850 | |
d3babd3f | 13851 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13852 | return INVALID_PIPE; |
13853 | ||
13854 | return to_intel_crtc(encoder->crtc)->pipe; | |
13855 | } | |
13856 | ||
08d7b3d1 | 13857 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13858 | struct drm_file *file) |
08d7b3d1 | 13859 | { |
08d7b3d1 | 13860 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13861 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13862 | struct intel_crtc *crtc; |
08d7b3d1 | 13863 | |
7707e653 | 13864 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 13865 | |
7707e653 | 13866 | if (!drmmode_crtc) { |
08d7b3d1 | 13867 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 13868 | return -ENOENT; |
08d7b3d1 CW |
13869 | } |
13870 | ||
7707e653 | 13871 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13872 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13873 | |
c05422d5 | 13874 | return 0; |
08d7b3d1 CW |
13875 | } |
13876 | ||
66a9278e | 13877 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13878 | { |
66a9278e DV |
13879 | struct drm_device *dev = encoder->base.dev; |
13880 | struct intel_encoder *source_encoder; | |
79e53945 | 13881 | int index_mask = 0; |
79e53945 JB |
13882 | int entry = 0; |
13883 | ||
b2784e15 | 13884 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13885 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13886 | index_mask |= (1 << entry); |
13887 | ||
79e53945 JB |
13888 | entry++; |
13889 | } | |
4ef69c7a | 13890 | |
79e53945 JB |
13891 | return index_mask; |
13892 | } | |
13893 | ||
4d302442 CW |
13894 | static bool has_edp_a(struct drm_device *dev) |
13895 | { | |
13896 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13897 | ||
13898 | if (!IS_MOBILE(dev)) | |
13899 | return false; | |
13900 | ||
13901 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13902 | return false; | |
13903 | ||
e3589908 | 13904 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13905 | return false; |
13906 | ||
13907 | return true; | |
13908 | } | |
13909 | ||
84b4e042 JB |
13910 | static bool intel_crt_present(struct drm_device *dev) |
13911 | { | |
13912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13913 | ||
884497ed DL |
13914 | if (INTEL_INFO(dev)->gen >= 9) |
13915 | return false; | |
13916 | ||
cf404ce4 | 13917 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
13918 | return false; |
13919 | ||
13920 | if (IS_CHERRYVIEW(dev)) | |
13921 | return false; | |
13922 | ||
13923 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
13924 | return false; | |
13925 | ||
13926 | return true; | |
13927 | } | |
13928 | ||
79e53945 JB |
13929 | static void intel_setup_outputs(struct drm_device *dev) |
13930 | { | |
725e30ad | 13931 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 13932 | struct intel_encoder *encoder; |
cb0953d7 | 13933 | bool dpd_is_edp = false; |
79e53945 | 13934 | |
c9093354 | 13935 | intel_lvds_init(dev); |
79e53945 | 13936 | |
84b4e042 | 13937 | if (intel_crt_present(dev)) |
79935fca | 13938 | intel_crt_init(dev); |
cb0953d7 | 13939 | |
c776eb2e VK |
13940 | if (IS_BROXTON(dev)) { |
13941 | /* | |
13942 | * FIXME: Broxton doesn't support port detection via the | |
13943 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13944 | * detect the ports. | |
13945 | */ | |
13946 | intel_ddi_init(dev, PORT_A); | |
13947 | intel_ddi_init(dev, PORT_B); | |
13948 | intel_ddi_init(dev, PORT_C); | |
13949 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
13950 | int found; |
13951 | ||
de31facd JB |
13952 | /* |
13953 | * Haswell uses DDI functions to detect digital outputs. | |
13954 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13955 | * it's there. | |
13956 | */ | |
0e72a5b5 | 13957 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; |
de31facd JB |
13958 | /* WaIgnoreDDIAStrap: skl */ |
13959 | if (found || | |
13960 | (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0)) | |
0e72a5b5 ED |
13961 | intel_ddi_init(dev, PORT_A); |
13962 | ||
13963 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13964 | * register */ | |
13965 | found = I915_READ(SFUSE_STRAP); | |
13966 | ||
13967 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
13968 | intel_ddi_init(dev, PORT_B); | |
13969 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
13970 | intel_ddi_init(dev, PORT_C); | |
13971 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
13972 | intel_ddi_init(dev, PORT_D); | |
13973 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 13974 | int found; |
5d8a7752 | 13975 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
13976 | |
13977 | if (has_edp_a(dev)) | |
13978 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 13979 | |
dc0fa718 | 13980 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13981 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 13982 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 13983 | if (!found) |
e2debe91 | 13984 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 13985 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 13986 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13987 | } |
13988 | ||
dc0fa718 | 13989 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 13990 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 13991 | |
dc0fa718 | 13992 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 13993 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 13994 | |
5eb08b69 | 13995 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 13996 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 13997 | |
270b3042 | 13998 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 13999 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 14000 | } else if (IS_VALLEYVIEW(dev)) { |
e17ac6db VS |
14001 | /* |
14002 | * The DP_DETECTED bit is the latched state of the DDC | |
14003 | * SDA pin at boot. However since eDP doesn't require DDC | |
14004 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14005 | * eDP ports may have been muxed to an alternate function. | |
14006 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14007 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14008 | * detect eDP ports. | |
14009 | */ | |
d2182a66 VS |
14010 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED && |
14011 | !intel_dp_is_edp(dev, PORT_B)) | |
585a94b8 AB |
14012 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, |
14013 | PORT_B); | |
e17ac6db VS |
14014 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED || |
14015 | intel_dp_is_edp(dev, PORT_B)) | |
14016 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
585a94b8 | 14017 | |
d2182a66 VS |
14018 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED && |
14019 | !intel_dp_is_edp(dev, PORT_C)) | |
6f6005a5 JB |
14020 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, |
14021 | PORT_C); | |
e17ac6db VS |
14022 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED || |
14023 | intel_dp_is_edp(dev, PORT_C)) | |
14024 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); | |
19c03924 | 14025 | |
9418c1f1 | 14026 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14027 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) |
9418c1f1 VS |
14028 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, |
14029 | PORT_D); | |
e17ac6db VS |
14030 | /* eDP not supported on port D, so don't check VBT */ |
14031 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
14032 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
9418c1f1 VS |
14033 | } |
14034 | ||
3cfca973 | 14035 | intel_dsi_init(dev); |
103a196f | 14036 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 14037 | bool found = false; |
7d57382e | 14038 | |
e2debe91 | 14039 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14040 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 14041 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
14042 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
14043 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 14044 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14045 | } |
27185ae1 | 14046 | |
e7281eab | 14047 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 14048 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14049 | } |
13520b05 KH |
14050 | |
14051 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14052 | |
e2debe91 | 14053 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14054 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 14055 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 14056 | } |
27185ae1 | 14057 | |
e2debe91 | 14058 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14059 | |
b01f2c3a JB |
14060 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
14061 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 14062 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14063 | } |
e7281eab | 14064 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 14065 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14066 | } |
27185ae1 | 14067 | |
b01f2c3a | 14068 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 14069 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14070 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14071 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14072 | intel_dvo_init(dev); |
14073 | ||
103a196f | 14074 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14075 | intel_tv_init(dev); |
14076 | ||
0bc12bcb | 14077 | intel_psr_init(dev); |
7c8f8a70 | 14078 | |
b2784e15 | 14079 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14080 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14081 | encoder->base.possible_clones = | |
66a9278e | 14082 | intel_encoder_clones(encoder); |
79e53945 | 14083 | } |
47356eb6 | 14084 | |
dde86e2d | 14085 | intel_init_pch_refclk(dev); |
270b3042 DV |
14086 | |
14087 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14088 | } |
14089 | ||
14090 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14091 | { | |
60a5ca01 | 14092 | struct drm_device *dev = fb->dev; |
79e53945 | 14093 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14094 | |
ef2d633e | 14095 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14096 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14097 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14098 | drm_gem_object_unreference(&intel_fb->obj->base); |
14099 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14100 | kfree(intel_fb); |
14101 | } | |
14102 | ||
14103 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14104 | struct drm_file *file, |
79e53945 JB |
14105 | unsigned int *handle) |
14106 | { | |
14107 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14108 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14109 | |
05394f39 | 14110 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14111 | } |
14112 | ||
14113 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
14114 | .destroy = intel_user_framebuffer_destroy, | |
14115 | .create_handle = intel_user_framebuffer_create_handle, | |
14116 | }; | |
14117 | ||
b321803d DL |
14118 | static |
14119 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14120 | uint32_t pixel_format) | |
14121 | { | |
14122 | u32 gen = INTEL_INFO(dev)->gen; | |
14123 | ||
14124 | if (gen >= 9) { | |
14125 | /* "The stride in bytes must not exceed the of the size of 8K | |
14126 | * pixels and 32K bytes." | |
14127 | */ | |
14128 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
14129 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) { | |
14130 | return 32*1024; | |
14131 | } else if (gen >= 4) { | |
14132 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14133 | return 16*1024; | |
14134 | else | |
14135 | return 32*1024; | |
14136 | } else if (gen >= 3) { | |
14137 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14138 | return 8*1024; | |
14139 | else | |
14140 | return 16*1024; | |
14141 | } else { | |
14142 | /* XXX DSPC is limited to 4k tiled */ | |
14143 | return 8*1024; | |
14144 | } | |
14145 | } | |
14146 | ||
b5ea642a DV |
14147 | static int intel_framebuffer_init(struct drm_device *dev, |
14148 | struct intel_framebuffer *intel_fb, | |
14149 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14150 | struct drm_i915_gem_object *obj) | |
79e53945 | 14151 | { |
6761dd31 | 14152 | unsigned int aligned_height; |
79e53945 | 14153 | int ret; |
b321803d | 14154 | u32 pitch_limit, stride_alignment; |
79e53945 | 14155 | |
dd4916c5 DV |
14156 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14157 | ||
2a80eada DV |
14158 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14159 | /* Enforce that fb modifier and tiling mode match, but only for | |
14160 | * X-tiled. This is needed for FBC. */ | |
14161 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14162 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14163 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14164 | return -EINVAL; | |
14165 | } | |
14166 | } else { | |
14167 | if (obj->tiling_mode == I915_TILING_X) | |
14168 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14169 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14170 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14171 | return -EINVAL; | |
14172 | } | |
14173 | } | |
14174 | ||
9a8f0a12 TU |
14175 | /* Passed in modifier sanity checking. */ |
14176 | switch (mode_cmd->modifier[0]) { | |
14177 | case I915_FORMAT_MOD_Y_TILED: | |
14178 | case I915_FORMAT_MOD_Yf_TILED: | |
14179 | if (INTEL_INFO(dev)->gen < 9) { | |
14180 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14181 | mode_cmd->modifier[0]); | |
14182 | return -EINVAL; | |
14183 | } | |
14184 | case DRM_FORMAT_MOD_NONE: | |
14185 | case I915_FORMAT_MOD_X_TILED: | |
14186 | break; | |
14187 | default: | |
c0f40428 JB |
14188 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14189 | mode_cmd->modifier[0]); | |
57cd6508 | 14190 | return -EINVAL; |
c16ed4be | 14191 | } |
57cd6508 | 14192 | |
b321803d DL |
14193 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14194 | mode_cmd->pixel_format); | |
14195 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14196 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14197 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14198 | return -EINVAL; |
c16ed4be | 14199 | } |
57cd6508 | 14200 | |
b321803d DL |
14201 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14202 | mode_cmd->pixel_format); | |
a35cdaa0 | 14203 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14204 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14205 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14206 | "tiled" : "linear", |
a35cdaa0 | 14207 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14208 | return -EINVAL; |
c16ed4be | 14209 | } |
5d7bd705 | 14210 | |
2a80eada | 14211 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14212 | mode_cmd->pitches[0] != obj->stride) { |
14213 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14214 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14215 | return -EINVAL; |
c16ed4be | 14216 | } |
5d7bd705 | 14217 | |
57779d06 | 14218 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14219 | switch (mode_cmd->pixel_format) { |
57779d06 | 14220 | case DRM_FORMAT_C8: |
04b3924d VS |
14221 | case DRM_FORMAT_RGB565: |
14222 | case DRM_FORMAT_XRGB8888: | |
14223 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14224 | break; |
14225 | case DRM_FORMAT_XRGB1555: | |
14226 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 14227 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14228 | DRM_DEBUG("unsupported pixel format: %s\n", |
14229 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14230 | return -EINVAL; |
c16ed4be | 14231 | } |
57779d06 VS |
14232 | break; |
14233 | case DRM_FORMAT_XBGR8888: | |
14234 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
14235 | case DRM_FORMAT_XRGB2101010: |
14236 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
14237 | case DRM_FORMAT_XBGR2101010: |
14238 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 14239 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14240 | DRM_DEBUG("unsupported pixel format: %s\n", |
14241 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14242 | return -EINVAL; |
c16ed4be | 14243 | } |
b5626747 | 14244 | break; |
04b3924d VS |
14245 | case DRM_FORMAT_YUYV: |
14246 | case DRM_FORMAT_UYVY: | |
14247 | case DRM_FORMAT_YVYU: | |
14248 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14249 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14250 | DRM_DEBUG("unsupported pixel format: %s\n", |
14251 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14252 | return -EINVAL; |
c16ed4be | 14253 | } |
57cd6508 CW |
14254 | break; |
14255 | default: | |
4ee62c76 VS |
14256 | DRM_DEBUG("unsupported pixel format: %s\n", |
14257 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14258 | return -EINVAL; |
14259 | } | |
14260 | ||
90f9a336 VS |
14261 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14262 | if (mode_cmd->offsets[0] != 0) | |
14263 | return -EINVAL; | |
14264 | ||
ec2c981e | 14265 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14266 | mode_cmd->pixel_format, |
14267 | mode_cmd->modifier[0]); | |
53155c0a DV |
14268 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14269 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14270 | return -EINVAL; | |
14271 | ||
c7d73f6a DV |
14272 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14273 | intel_fb->obj = obj; | |
80075d49 | 14274 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14275 | |
79e53945 JB |
14276 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14277 | if (ret) { | |
14278 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14279 | return ret; | |
14280 | } | |
14281 | ||
79e53945 JB |
14282 | return 0; |
14283 | } | |
14284 | ||
79e53945 JB |
14285 | static struct drm_framebuffer * |
14286 | intel_user_framebuffer_create(struct drm_device *dev, | |
14287 | struct drm_file *filp, | |
308e5bcb | 14288 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 14289 | { |
05394f39 | 14290 | struct drm_i915_gem_object *obj; |
79e53945 | 14291 | |
308e5bcb JB |
14292 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
14293 | mode_cmd->handles[0])); | |
c8725226 | 14294 | if (&obj->base == NULL) |
cce13ff7 | 14295 | return ERR_PTR(-ENOENT); |
79e53945 | 14296 | |
d2dff872 | 14297 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
14298 | } |
14299 | ||
4520f53a | 14300 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 14301 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14302 | { |
14303 | } | |
14304 | #endif | |
14305 | ||
79e53945 | 14306 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14307 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14308 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14309 | .atomic_check = intel_atomic_check, |
14310 | .atomic_commit = intel_atomic_commit, | |
79e53945 JB |
14311 | }; |
14312 | ||
e70236a8 JB |
14313 | /* Set up chip specific display functions */ |
14314 | static void intel_init_display(struct drm_device *dev) | |
14315 | { | |
14316 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14317 | ||
ee9300bb DV |
14318 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14319 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14320 | else if (IS_CHERRYVIEW(dev)) |
14321 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14322 | else if (IS_VALLEYVIEW(dev)) |
14323 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14324 | else if (IS_PINEVIEW(dev)) | |
14325 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14326 | else | |
14327 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14328 | ||
bc8d7dff DL |
14329 | if (INTEL_INFO(dev)->gen >= 9) { |
14330 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14331 | dev_priv->display.get_initial_plane_config = |
14332 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14333 | dev_priv->display.crtc_compute_clock = |
14334 | haswell_crtc_compute_clock; | |
14335 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14336 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
14337 | dev_priv->display.off = ironlake_crtc_off; | |
14338 | dev_priv->display.update_primary_plane = | |
14339 | skylake_update_primary_plane; | |
14340 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14341 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14342 | dev_priv->display.get_initial_plane_config = |
14343 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14344 | dev_priv->display.crtc_compute_clock = |
14345 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14346 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14347 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 14348 | dev_priv->display.off = ironlake_crtc_off; |
bc8d7dff DL |
14349 | dev_priv->display.update_primary_plane = |
14350 | ironlake_update_primary_plane; | |
09b4ddf9 | 14351 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14352 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14353 | dev_priv->display.get_initial_plane_config = |
14354 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14355 | dev_priv->display.crtc_compute_clock = |
14356 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14357 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14358 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 14359 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
14360 | dev_priv->display.update_primary_plane = |
14361 | ironlake_update_primary_plane; | |
89b667f8 JB |
14362 | } else if (IS_VALLEYVIEW(dev)) { |
14363 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
5724dbd1 DL |
14364 | dev_priv->display.get_initial_plane_config = |
14365 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14366 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14367 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14368 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14369 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
14370 | dev_priv->display.update_primary_plane = |
14371 | i9xx_update_primary_plane; | |
f564048e | 14372 | } else { |
0e8ffe1b | 14373 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14374 | dev_priv->display.get_initial_plane_config = |
14375 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14376 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14377 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14378 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 14379 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
14380 | dev_priv->display.update_primary_plane = |
14381 | i9xx_update_primary_plane; | |
f564048e | 14382 | } |
e70236a8 | 14383 | |
e70236a8 | 14384 | /* Returns the core display clock speed */ |
1652d19e VS |
14385 | if (IS_SKYLAKE(dev)) |
14386 | dev_priv->display.get_display_clock_speed = | |
14387 | skylake_get_display_clock_speed; | |
14388 | else if (IS_BROADWELL(dev)) | |
14389 | dev_priv->display.get_display_clock_speed = | |
14390 | broadwell_get_display_clock_speed; | |
14391 | else if (IS_HASWELL(dev)) | |
14392 | dev_priv->display.get_display_clock_speed = | |
14393 | haswell_get_display_clock_speed; | |
14394 | else if (IS_VALLEYVIEW(dev)) | |
25eb05fc JB |
14395 | dev_priv->display.get_display_clock_speed = |
14396 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14397 | else if (IS_GEN5(dev)) |
14398 | dev_priv->display.get_display_clock_speed = | |
14399 | ilk_get_display_clock_speed; | |
a7c66cd8 VS |
14400 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
14401 | IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
14402 | dev_priv->display.get_display_clock_speed = |
14403 | i945_get_display_clock_speed; | |
14404 | else if (IS_I915G(dev)) | |
14405 | dev_priv->display.get_display_clock_speed = | |
14406 | i915_get_display_clock_speed; | |
257a7ffc | 14407 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14408 | dev_priv->display.get_display_clock_speed = |
14409 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
14410 | else if (IS_PINEVIEW(dev)) |
14411 | dev_priv->display.get_display_clock_speed = | |
14412 | pnv_get_display_clock_speed; | |
e70236a8 JB |
14413 | else if (IS_I915GM(dev)) |
14414 | dev_priv->display.get_display_clock_speed = | |
14415 | i915gm_get_display_clock_speed; | |
14416 | else if (IS_I865G(dev)) | |
14417 | dev_priv->display.get_display_clock_speed = | |
14418 | i865_get_display_clock_speed; | |
f0f8a9ce | 14419 | else if (IS_I85X(dev)) |
e70236a8 JB |
14420 | dev_priv->display.get_display_clock_speed = |
14421 | i855_get_display_clock_speed; | |
14422 | else /* 852, 830 */ | |
14423 | dev_priv->display.get_display_clock_speed = | |
14424 | i830_get_display_clock_speed; | |
14425 | ||
7c10a2b5 | 14426 | if (IS_GEN5(dev)) { |
3bb11b53 | 14427 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14428 | } else if (IS_GEN6(dev)) { |
14429 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14430 | } else if (IS_IVYBRIDGE(dev)) { |
14431 | /* FIXME: detect B0+ stepping and use auto training */ | |
14432 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14433 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14434 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
30a970c6 JB |
14435 | } else if (IS_VALLEYVIEW(dev)) { |
14436 | dev_priv->display.modeset_global_resources = | |
14437 | valleyview_modeset_global_resources; | |
f8437dd1 VK |
14438 | } else if (IS_BROXTON(dev)) { |
14439 | dev_priv->display.modeset_global_resources = | |
14440 | broxton_modeset_global_resources; | |
e70236a8 | 14441 | } |
8c9f3aaf | 14442 | |
8c9f3aaf JB |
14443 | switch (INTEL_INFO(dev)->gen) { |
14444 | case 2: | |
14445 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14446 | break; | |
14447 | ||
14448 | case 3: | |
14449 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14450 | break; | |
14451 | ||
14452 | case 4: | |
14453 | case 5: | |
14454 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14455 | break; | |
14456 | ||
14457 | case 6: | |
14458 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14459 | break; | |
7c9017e5 | 14460 | case 7: |
4e0bbc31 | 14461 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14462 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14463 | break; | |
830c81db | 14464 | case 9: |
ba343e02 TU |
14465 | /* Drop through - unsupported since execlist only. */ |
14466 | default: | |
14467 | /* Default just returns -ENODEV to indicate unsupported */ | |
14468 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14469 | } |
7bd688cd JN |
14470 | |
14471 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
14472 | |
14473 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
14474 | } |
14475 | ||
b690e96c JB |
14476 | /* |
14477 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14478 | * resume, or other times. This quirk makes sure that's the case for | |
14479 | * affected systems. | |
14480 | */ | |
0206e353 | 14481 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14482 | { |
14483 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14484 | ||
14485 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14486 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14487 | } |
14488 | ||
b6b5d049 VS |
14489 | static void quirk_pipeb_force(struct drm_device *dev) |
14490 | { | |
14491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14492 | ||
14493 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14494 | DRM_INFO("applying pipe b force quirk\n"); | |
14495 | } | |
14496 | ||
435793df KP |
14497 | /* |
14498 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14499 | */ | |
14500 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14501 | { | |
14502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14503 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 14504 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14505 | } |
14506 | ||
4dca20ef | 14507 | /* |
5a15ab5b CE |
14508 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14509 | * brightness value | |
4dca20ef CE |
14510 | */ |
14511 | static void quirk_invert_brightness(struct drm_device *dev) | |
14512 | { | |
14513 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14514 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 14515 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14516 | } |
14517 | ||
9c72cc6f SD |
14518 | /* Some VBT's incorrectly indicate no backlight is present */ |
14519 | static void quirk_backlight_present(struct drm_device *dev) | |
14520 | { | |
14521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14522 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
14523 | DRM_INFO("applying backlight present quirk\n"); | |
14524 | } | |
14525 | ||
b690e96c JB |
14526 | struct intel_quirk { |
14527 | int device; | |
14528 | int subsystem_vendor; | |
14529 | int subsystem_device; | |
14530 | void (*hook)(struct drm_device *dev); | |
14531 | }; | |
14532 | ||
5f85f176 EE |
14533 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14534 | struct intel_dmi_quirk { | |
14535 | void (*hook)(struct drm_device *dev); | |
14536 | const struct dmi_system_id (*dmi_id_list)[]; | |
14537 | }; | |
14538 | ||
14539 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14540 | { | |
14541 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14542 | return 1; | |
14543 | } | |
14544 | ||
14545 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14546 | { | |
14547 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14548 | { | |
14549 | .callback = intel_dmi_reverse_brightness, | |
14550 | .ident = "NCR Corporation", | |
14551 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14552 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14553 | }, | |
14554 | }, | |
14555 | { } /* terminating entry */ | |
14556 | }, | |
14557 | .hook = quirk_invert_brightness, | |
14558 | }, | |
14559 | }; | |
14560 | ||
c43b5634 | 14561 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 14562 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 14563 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 14564 | |
b690e96c JB |
14565 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14566 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14567 | ||
b690e96c JB |
14568 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14569 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14570 | ||
5f080c0f VS |
14571 | /* 830 needs to leave pipe A & dpll A up */ |
14572 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14573 | ||
b6b5d049 VS |
14574 | /* 830 needs to leave pipe B & dpll B up */ |
14575 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14576 | ||
435793df KP |
14577 | /* Lenovo U160 cannot use SSC on LVDS */ |
14578 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14579 | |
14580 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14581 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14582 | |
be505f64 AH |
14583 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14584 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14585 | ||
14586 | /* Acer/eMachines G725 */ | |
14587 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14588 | ||
14589 | /* Acer/eMachines e725 */ | |
14590 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14591 | ||
14592 | /* Acer/Packard Bell NCL20 */ | |
14593 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14594 | ||
14595 | /* Acer Aspire 4736Z */ | |
14596 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14597 | |
14598 | /* Acer Aspire 5336 */ | |
14599 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14600 | |
14601 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14602 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14603 | |
dfb3d47b SD |
14604 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14605 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14606 | ||
b2a9601c | 14607 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14608 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14609 | ||
d4967d8c SD |
14610 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14611 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14612 | |
14613 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14614 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14615 | |
14616 | /* Dell Chromebook 11 */ | |
14617 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14618 | }; |
14619 | ||
14620 | static void intel_init_quirks(struct drm_device *dev) | |
14621 | { | |
14622 | struct pci_dev *d = dev->pdev; | |
14623 | int i; | |
14624 | ||
14625 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14626 | struct intel_quirk *q = &intel_quirks[i]; | |
14627 | ||
14628 | if (d->device == q->device && | |
14629 | (d->subsystem_vendor == q->subsystem_vendor || | |
14630 | q->subsystem_vendor == PCI_ANY_ID) && | |
14631 | (d->subsystem_device == q->subsystem_device || | |
14632 | q->subsystem_device == PCI_ANY_ID)) | |
14633 | q->hook(dev); | |
14634 | } | |
5f85f176 EE |
14635 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14636 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14637 | intel_dmi_quirks[i].hook(dev); | |
14638 | } | |
b690e96c JB |
14639 | } |
14640 | ||
9cce37f4 JB |
14641 | /* Disable the VGA plane that we never use */ |
14642 | static void i915_disable_vga(struct drm_device *dev) | |
14643 | { | |
14644 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14645 | u8 sr1; | |
766aa1c4 | 14646 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 14647 | |
2b37c616 | 14648 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 14649 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14650 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14651 | sr1 = inb(VGA_SR_DATA); |
14652 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
14653 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
14654 | udelay(300); | |
14655 | ||
01f5a626 | 14656 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14657 | POSTING_READ(vga_reg); |
14658 | } | |
14659 | ||
f817586c DV |
14660 | void intel_modeset_init_hw(struct drm_device *dev) |
14661 | { | |
a8f78b58 ED |
14662 | intel_prepare_ddi(dev); |
14663 | ||
f8bf63fd VS |
14664 | if (IS_VALLEYVIEW(dev)) |
14665 | vlv_update_cdclk(dev); | |
14666 | ||
f817586c DV |
14667 | intel_init_clock_gating(dev); |
14668 | ||
8090c6b9 | 14669 | intel_enable_gt_powersave(dev); |
f817586c DV |
14670 | } |
14671 | ||
79e53945 JB |
14672 | void intel_modeset_init(struct drm_device *dev) |
14673 | { | |
652c393a | 14674 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 14675 | int sprite, ret; |
8cc87b75 | 14676 | enum pipe pipe; |
46f297fb | 14677 | struct intel_crtc *crtc; |
79e53945 JB |
14678 | |
14679 | drm_mode_config_init(dev); | |
14680 | ||
14681 | dev->mode_config.min_width = 0; | |
14682 | dev->mode_config.min_height = 0; | |
14683 | ||
019d96cb DA |
14684 | dev->mode_config.preferred_depth = 24; |
14685 | dev->mode_config.prefer_shadow = 1; | |
14686 | ||
25bab385 TU |
14687 | dev->mode_config.allow_fb_modifiers = true; |
14688 | ||
e6ecefaa | 14689 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14690 | |
b690e96c JB |
14691 | intel_init_quirks(dev); |
14692 | ||
1fa61106 ED |
14693 | intel_init_pm(dev); |
14694 | ||
e3c74757 BW |
14695 | if (INTEL_INFO(dev)->num_pipes == 0) |
14696 | return; | |
14697 | ||
e70236a8 | 14698 | intel_init_display(dev); |
7c10a2b5 | 14699 | intel_init_audio(dev); |
e70236a8 | 14700 | |
a6c45cf0 CW |
14701 | if (IS_GEN2(dev)) { |
14702 | dev->mode_config.max_width = 2048; | |
14703 | dev->mode_config.max_height = 2048; | |
14704 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
14705 | dev->mode_config.max_width = 4096; |
14706 | dev->mode_config.max_height = 4096; | |
79e53945 | 14707 | } else { |
a6c45cf0 CW |
14708 | dev->mode_config.max_width = 8192; |
14709 | dev->mode_config.max_height = 8192; | |
79e53945 | 14710 | } |
068be561 | 14711 | |
dc41c154 VS |
14712 | if (IS_845G(dev) || IS_I865G(dev)) { |
14713 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
14714 | dev->mode_config.cursor_height = 1023; | |
14715 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
14716 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14717 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14718 | } else { | |
14719 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14720 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14721 | } | |
14722 | ||
5d4545ae | 14723 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 14724 | |
28c97730 | 14725 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
14726 | INTEL_INFO(dev)->num_pipes, |
14727 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14728 | |
055e393f | 14729 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 14730 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 14731 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 14732 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 14733 | if (ret) |
06da8da2 | 14734 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 14735 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 14736 | } |
79e53945 JB |
14737 | } |
14738 | ||
f42bb70d JB |
14739 | intel_init_dpio(dev); |
14740 | ||
e72f9fbf | 14741 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14742 | |
9cce37f4 JB |
14743 | /* Just disable it once at startup */ |
14744 | i915_disable_vga(dev); | |
79e53945 | 14745 | intel_setup_outputs(dev); |
11be49eb CW |
14746 | |
14747 | /* Just in case the BIOS is doing something questionable. */ | |
7ff0ebcc | 14748 | intel_fbc_disable(dev); |
fa9fa083 | 14749 | |
6e9f798d | 14750 | drm_modeset_lock_all(dev); |
fa9fa083 | 14751 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 14752 | drm_modeset_unlock_all(dev); |
46f297fb | 14753 | |
d3fcc808 | 14754 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
14755 | if (!crtc->active) |
14756 | continue; | |
14757 | ||
46f297fb | 14758 | /* |
46f297fb JB |
14759 | * Note that reserving the BIOS fb up front prevents us |
14760 | * from stuffing other stolen allocations like the ring | |
14761 | * on top. This prevents some ugliness at boot time, and | |
14762 | * can even allow for smooth boot transitions if the BIOS | |
14763 | * fb is large enough for the active pipe configuration. | |
14764 | */ | |
5724dbd1 DL |
14765 | if (dev_priv->display.get_initial_plane_config) { |
14766 | dev_priv->display.get_initial_plane_config(crtc, | |
46f297fb JB |
14767 | &crtc->plane_config); |
14768 | /* | |
14769 | * If the fb is shared between multiple heads, we'll | |
14770 | * just get the first one. | |
14771 | */ | |
f6936e29 | 14772 | intel_find_initial_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 14773 | } |
46f297fb | 14774 | } |
2c7111db CW |
14775 | } |
14776 | ||
7fad798e DV |
14777 | static void intel_enable_pipe_a(struct drm_device *dev) |
14778 | { | |
14779 | struct intel_connector *connector; | |
14780 | struct drm_connector *crt = NULL; | |
14781 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 14782 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
14783 | |
14784 | /* We can't just switch on the pipe A, we need to set things up with a | |
14785 | * proper mode and output configuration. As a gross hack, enable pipe A | |
14786 | * by enabling the load detect pipe once. */ | |
3a3371ff | 14787 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
14788 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
14789 | crt = &connector->base; | |
14790 | break; | |
14791 | } | |
14792 | } | |
14793 | ||
14794 | if (!crt) | |
14795 | return; | |
14796 | ||
208bf9fd | 14797 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 14798 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
14799 | } |
14800 | ||
fa555837 DV |
14801 | static bool |
14802 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14803 | { | |
7eb552ae BW |
14804 | struct drm_device *dev = crtc->base.dev; |
14805 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
14806 | u32 reg, val; |
14807 | ||
7eb552ae | 14808 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
14809 | return true; |
14810 | ||
14811 | reg = DSPCNTR(!crtc->plane); | |
14812 | val = I915_READ(reg); | |
14813 | ||
14814 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14815 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14816 | return false; | |
14817 | ||
14818 | return true; | |
14819 | } | |
14820 | ||
24929352 DV |
14821 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
14822 | { | |
14823 | struct drm_device *dev = crtc->base.dev; | |
14824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 14825 | u32 reg; |
24929352 | 14826 | |
24929352 | 14827 | /* Clear any frame start delays used for debugging left by the BIOS */ |
6e3c9717 | 14828 | reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 DV |
14829 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
14830 | ||
d3eaf884 | 14831 | /* restore vblank interrupts to correct state */ |
9625604c | 14832 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 VS |
14833 | if (crtc->active) { |
14834 | update_scanline_offset(crtc); | |
9625604c DV |
14835 | drm_crtc_vblank_on(&crtc->base); |
14836 | } | |
d3eaf884 | 14837 | |
24929352 | 14838 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14839 | * disable the crtc (and hence change the state) if it is wrong. Note |
14840 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
14841 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
14842 | struct intel_connector *connector; |
14843 | bool plane; | |
14844 | ||
24929352 DV |
14845 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
14846 | crtc->base.base.id); | |
14847 | ||
14848 | /* Pipe has the wrong plane attached and the plane is active. | |
14849 | * Temporarily change the plane mapping and disable everything | |
14850 | * ... */ | |
14851 | plane = crtc->plane; | |
b70709a6 | 14852 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 14853 | crtc->plane = !plane; |
ce22dba9 | 14854 | intel_crtc_disable_planes(&crtc->base); |
24929352 DV |
14855 | dev_priv->display.crtc_disable(&crtc->base); |
14856 | crtc->plane = plane; | |
14857 | ||
14858 | /* ... and break all links. */ | |
3a3371ff | 14859 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14860 | if (connector->encoder->base.crtc != &crtc->base) |
14861 | continue; | |
14862 | ||
7f1950fb EE |
14863 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14864 | connector->base.encoder = NULL; | |
24929352 | 14865 | } |
7f1950fb EE |
14866 | /* multiple connectors may have the same encoder: |
14867 | * handle them and break crtc link separately */ | |
3a3371ff | 14868 | for_each_intel_connector(dev, connector) |
7f1950fb EE |
14869 | if (connector->encoder->base.crtc == &crtc->base) { |
14870 | connector->encoder->base.crtc = NULL; | |
14871 | connector->encoder->connectors_active = false; | |
14872 | } | |
24929352 DV |
14873 | |
14874 | WARN_ON(crtc->active); | |
83d65738 | 14875 | crtc->base.state->enable = false; |
24929352 DV |
14876 | crtc->base.enabled = false; |
14877 | } | |
24929352 | 14878 | |
7fad798e DV |
14879 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
14880 | crtc->pipe == PIPE_A && !crtc->active) { | |
14881 | /* BIOS forgot to enable pipe A, this mostly happens after | |
14882 | * resume. Force-enable the pipe to fix this, the update_dpms | |
14883 | * call below we restore the pipe to the right state, but leave | |
14884 | * the required bits on. */ | |
14885 | intel_enable_pipe_a(dev); | |
14886 | } | |
14887 | ||
24929352 DV |
14888 | /* Adjust the state of the output pipe according to whether we |
14889 | * have active connectors/encoders. */ | |
14890 | intel_crtc_update_dpms(&crtc->base); | |
14891 | ||
83d65738 | 14892 | if (crtc->active != crtc->base.state->enable) { |
24929352 DV |
14893 | struct intel_encoder *encoder; |
14894 | ||
14895 | /* This can happen either due to bugs in the get_hw_state | |
14896 | * functions or because the pipe is force-enabled due to the | |
14897 | * pipe A quirk. */ | |
14898 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
14899 | crtc->base.base.id, | |
83d65738 | 14900 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
14901 | crtc->active ? "enabled" : "disabled"); |
14902 | ||
83d65738 | 14903 | crtc->base.state->enable = crtc->active; |
24929352 DV |
14904 | crtc->base.enabled = crtc->active; |
14905 | ||
14906 | /* Because we only establish the connector -> encoder -> | |
14907 | * crtc links if something is active, this means the | |
14908 | * crtc is now deactivated. Break the links. connector | |
14909 | * -> encoder links are only establish when things are | |
14910 | * actually up, hence no need to break them. */ | |
14911 | WARN_ON(crtc->active); | |
14912 | ||
14913 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
14914 | WARN_ON(encoder->connectors_active); | |
14915 | encoder->base.crtc = NULL; | |
14916 | } | |
14917 | } | |
c5ab3bc0 | 14918 | |
a3ed6aad | 14919 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
14920 | /* |
14921 | * We start out with underrun reporting disabled to avoid races. | |
14922 | * For correct bookkeeping mark this on active crtcs. | |
14923 | * | |
c5ab3bc0 DV |
14924 | * Also on gmch platforms we dont have any hardware bits to |
14925 | * disable the underrun reporting. Which means we need to start | |
14926 | * out with underrun reporting disabled also on inactive pipes, | |
14927 | * since otherwise we'll complain about the garbage we read when | |
14928 | * e.g. coming up after runtime pm. | |
14929 | * | |
4cc31489 DV |
14930 | * No protection against concurrent access is required - at |
14931 | * worst a fifo underrun happens which also sets this to false. | |
14932 | */ | |
14933 | crtc->cpu_fifo_underrun_disabled = true; | |
14934 | crtc->pch_fifo_underrun_disabled = true; | |
14935 | } | |
24929352 DV |
14936 | } |
14937 | ||
14938 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14939 | { | |
14940 | struct intel_connector *connector; | |
14941 | struct drm_device *dev = encoder->base.dev; | |
14942 | ||
14943 | /* We need to check both for a crtc link (meaning that the | |
14944 | * encoder is active and trying to read from a pipe) and the | |
14945 | * pipe itself being active. */ | |
14946 | bool has_active_crtc = encoder->base.crtc && | |
14947 | to_intel_crtc(encoder->base.crtc)->active; | |
14948 | ||
14949 | if (encoder->connectors_active && !has_active_crtc) { | |
14950 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
14951 | encoder->base.base.id, | |
8e329a03 | 14952 | encoder->base.name); |
24929352 DV |
14953 | |
14954 | /* Connector is active, but has no active pipe. This is | |
14955 | * fallout from our resume register restoring. Disable | |
14956 | * the encoder manually again. */ | |
14957 | if (encoder->base.crtc) { | |
14958 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
14959 | encoder->base.base.id, | |
8e329a03 | 14960 | encoder->base.name); |
24929352 | 14961 | encoder->disable(encoder); |
a62d1497 VS |
14962 | if (encoder->post_disable) |
14963 | encoder->post_disable(encoder); | |
24929352 | 14964 | } |
7f1950fb EE |
14965 | encoder->base.crtc = NULL; |
14966 | encoder->connectors_active = false; | |
24929352 DV |
14967 | |
14968 | /* Inconsistent output/port/pipe state happens presumably due to | |
14969 | * a bug in one of the get_hw_state functions. Or someplace else | |
14970 | * in our code, like the register restore mess on resume. Clamp | |
14971 | * things to off as a safer default. */ | |
3a3371ff | 14972 | for_each_intel_connector(dev, connector) { |
24929352 DV |
14973 | if (connector->encoder != encoder) |
14974 | continue; | |
7f1950fb EE |
14975 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
14976 | connector->base.encoder = NULL; | |
24929352 DV |
14977 | } |
14978 | } | |
14979 | /* Enabled encoders without active connectors will be fixed in | |
14980 | * the crtc fixup. */ | |
14981 | } | |
14982 | ||
04098753 | 14983 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
14984 | { |
14985 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 14986 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 14987 | |
04098753 ID |
14988 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14989 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
14990 | i915_disable_vga(dev); | |
14991 | } | |
14992 | } | |
14993 | ||
14994 | void i915_redisable_vga(struct drm_device *dev) | |
14995 | { | |
14996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14997 | ||
8dc8a27c PZ |
14998 | /* This function can be called both from intel_modeset_setup_hw_state or |
14999 | * at a very early point in our resume sequence, where the power well | |
15000 | * structures are not yet restored. Since this function is at a very | |
15001 | * paranoid "someone might have enabled VGA while we were not looking" | |
15002 | * level, just check if the power well is enabled instead of trying to | |
15003 | * follow the "don't touch the power well if we don't need it" policy | |
15004 | * the rest of the driver uses. */ | |
f458ebbc | 15005 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15006 | return; |
15007 | ||
04098753 | 15008 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15009 | } |
15010 | ||
98ec7739 VS |
15011 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
15012 | { | |
15013 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
15014 | ||
15015 | if (!crtc->active) | |
15016 | return false; | |
15017 | ||
15018 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
15019 | } | |
15020 | ||
30e984df | 15021 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15022 | { |
15023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15024 | enum pipe pipe; | |
24929352 DV |
15025 | struct intel_crtc *crtc; |
15026 | struct intel_encoder *encoder; | |
15027 | struct intel_connector *connector; | |
5358901f | 15028 | int i; |
24929352 | 15029 | |
d3fcc808 | 15030 | for_each_intel_crtc(dev, crtc) { |
b70709a6 ML |
15031 | struct drm_plane *primary = crtc->base.primary; |
15032 | struct intel_plane_state *plane_state; | |
15033 | ||
6e3c9717 | 15034 | memset(crtc->config, 0, sizeof(*crtc->config)); |
3b117c8f | 15035 | |
6e3c9717 | 15036 | crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
9953599b | 15037 | |
0e8ffe1b | 15038 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 15039 | crtc->config); |
24929352 | 15040 | |
83d65738 | 15041 | crtc->base.state->enable = crtc->active; |
24929352 | 15042 | crtc->base.enabled = crtc->active; |
b70709a6 ML |
15043 | |
15044 | plane_state = to_intel_plane_state(primary->state); | |
15045 | plane_state->visible = primary_get_hw_state(crtc); | |
24929352 DV |
15046 | |
15047 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15048 | crtc->base.base.id, | |
15049 | crtc->active ? "enabled" : "disabled"); | |
15050 | } | |
15051 | ||
5358901f DV |
15052 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15053 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15054 | ||
3e369b76 ACO |
15055 | pll->on = pll->get_hw_state(dev_priv, pll, |
15056 | &pll->config.hw_state); | |
5358901f | 15057 | pll->active = 0; |
3e369b76 | 15058 | pll->config.crtc_mask = 0; |
d3fcc808 | 15059 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15060 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15061 | pll->active++; |
3e369b76 | 15062 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15063 | } |
5358901f | 15064 | } |
5358901f | 15065 | |
1e6f2ddc | 15066 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15067 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15068 | |
3e369b76 | 15069 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15070 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15071 | } |
15072 | ||
b2784e15 | 15073 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15074 | pipe = 0; |
15075 | ||
15076 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15077 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15078 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15079 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15080 | } else { |
15081 | encoder->base.crtc = NULL; | |
15082 | } | |
15083 | ||
15084 | encoder->connectors_active = false; | |
6f2bcceb | 15085 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15086 | encoder->base.base.id, |
8e329a03 | 15087 | encoder->base.name, |
24929352 | 15088 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15089 | pipe_name(pipe)); |
24929352 DV |
15090 | } |
15091 | ||
3a3371ff | 15092 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15093 | if (connector->get_hw_state(connector)) { |
15094 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
15095 | connector->encoder->connectors_active = true; | |
15096 | connector->base.encoder = &connector->encoder->base; | |
15097 | } else { | |
15098 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15099 | connector->base.encoder = NULL; | |
15100 | } | |
15101 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15102 | connector->base.base.id, | |
c23cc417 | 15103 | connector->base.name, |
24929352 DV |
15104 | connector->base.encoder ? "enabled" : "disabled"); |
15105 | } | |
30e984df DV |
15106 | } |
15107 | ||
15108 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
15109 | * and i915 state tracking structures. */ | |
15110 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
15111 | bool force_restore) | |
15112 | { | |
15113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15114 | enum pipe pipe; | |
30e984df DV |
15115 | struct intel_crtc *crtc; |
15116 | struct intel_encoder *encoder; | |
35c95375 | 15117 | int i; |
30e984df DV |
15118 | |
15119 | intel_modeset_readout_hw_state(dev); | |
24929352 | 15120 | |
babea61d JB |
15121 | /* |
15122 | * Now that we have the config, copy it to each CRTC struct | |
15123 | * Note that this could go away if we move to using crtc_config | |
15124 | * checking everywhere. | |
15125 | */ | |
d3fcc808 | 15126 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 15127 | if (crtc->active && i915.fastboot) { |
6e3c9717 ACO |
15128 | intel_mode_from_pipe_config(&crtc->base.mode, |
15129 | crtc->config); | |
babea61d JB |
15130 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
15131 | crtc->base.base.id); | |
15132 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
15133 | } | |
15134 | } | |
15135 | ||
24929352 | 15136 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 15137 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15138 | intel_sanitize_encoder(encoder); |
15139 | } | |
15140 | ||
055e393f | 15141 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15142 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15143 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15144 | intel_dump_pipe_config(crtc, crtc->config, |
15145 | "[setup_hw_state]"); | |
24929352 | 15146 | } |
9a935856 | 15147 | |
d29b2f9d ACO |
15148 | intel_modeset_update_connector_atomic_state(dev); |
15149 | ||
35c95375 DV |
15150 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15151 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15152 | ||
15153 | if (!pll->on || pll->active) | |
15154 | continue; | |
15155 | ||
15156 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15157 | ||
15158 | pll->disable(dev_priv, pll); | |
15159 | pll->on = false; | |
15160 | } | |
15161 | ||
3078999f PB |
15162 | if (IS_GEN9(dev)) |
15163 | skl_wm_get_hw_state(dev); | |
15164 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 VS |
15165 | ilk_wm_get_hw_state(dev); |
15166 | ||
45e2b5f6 | 15167 | if (force_restore) { |
7d0bc1ea VS |
15168 | i915_redisable_vga(dev); |
15169 | ||
f30da187 DV |
15170 | /* |
15171 | * We need to use raw interfaces for restoring state to avoid | |
15172 | * checking (bogus) intermediate states. | |
15173 | */ | |
055e393f | 15174 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
15175 | struct drm_crtc *crtc = |
15176 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 | 15177 | |
83a57153 | 15178 | intel_crtc_restore_mode(crtc); |
45e2b5f6 DV |
15179 | } |
15180 | } else { | |
15181 | intel_modeset_update_staged_output_state(dev); | |
15182 | } | |
8af6cf88 DV |
15183 | |
15184 | intel_modeset_check_state(dev); | |
2c7111db CW |
15185 | } |
15186 | ||
15187 | void intel_modeset_gem_init(struct drm_device *dev) | |
15188 | { | |
92122789 | 15189 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd | 15190 | struct drm_crtc *c; |
2ff8fde1 | 15191 | struct drm_i915_gem_object *obj; |
e0d6149b | 15192 | int ret; |
484b41dd | 15193 | |
ae48434c ID |
15194 | mutex_lock(&dev->struct_mutex); |
15195 | intel_init_gt_powersave(dev); | |
15196 | mutex_unlock(&dev->struct_mutex); | |
15197 | ||
92122789 JB |
15198 | /* |
15199 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15200 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15201 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15202 | * indicates as much. | |
15203 | */ | |
15204 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
15205 | dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15206 | DREF_SSC1_ENABLE); | |
15207 | ||
1833b134 | 15208 | intel_modeset_init_hw(dev); |
02e792fb DV |
15209 | |
15210 | intel_setup_overlay(dev); | |
484b41dd JB |
15211 | |
15212 | /* | |
15213 | * Make sure any fbs we allocated at startup are properly | |
15214 | * pinned & fenced. When we do the allocation it's too early | |
15215 | * for this. | |
15216 | */ | |
70e1e0ec | 15217 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15218 | obj = intel_fb_obj(c->primary->fb); |
15219 | if (obj == NULL) | |
484b41dd JB |
15220 | continue; |
15221 | ||
e0d6149b TU |
15222 | mutex_lock(&dev->struct_mutex); |
15223 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15224 | c->primary->fb, | |
15225 | c->primary->state, | |
15226 | NULL); | |
15227 | mutex_unlock(&dev->struct_mutex); | |
15228 | if (ret) { | |
484b41dd JB |
15229 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15230 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15231 | drm_framebuffer_unreference(c->primary->fb); |
15232 | c->primary->fb = NULL; | |
afd65eb4 | 15233 | update_state_fb(c->primary); |
484b41dd JB |
15234 | } |
15235 | } | |
0962c3c9 VS |
15236 | |
15237 | intel_backlight_register(dev); | |
79e53945 JB |
15238 | } |
15239 | ||
4932e2c3 ID |
15240 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15241 | { | |
15242 | struct drm_connector *connector = &intel_connector->base; | |
15243 | ||
15244 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15245 | drm_connector_unregister(connector); |
4932e2c3 ID |
15246 | } |
15247 | ||
79e53945 JB |
15248 | void intel_modeset_cleanup(struct drm_device *dev) |
15249 | { | |
652c393a | 15250 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15251 | struct drm_connector *connector; |
652c393a | 15252 | |
2eb5252e ID |
15253 | intel_disable_gt_powersave(dev); |
15254 | ||
0962c3c9 VS |
15255 | intel_backlight_unregister(dev); |
15256 | ||
fd0c0642 DV |
15257 | /* |
15258 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15259 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15260 | * experience fancy races otherwise. |
15261 | */ | |
2aeb7d3a | 15262 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15263 | |
fd0c0642 DV |
15264 | /* |
15265 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15266 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15267 | */ | |
f87ea761 | 15268 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15269 | |
652c393a JB |
15270 | mutex_lock(&dev->struct_mutex); |
15271 | ||
723bfd70 JB |
15272 | intel_unregister_dsm_handler(); |
15273 | ||
7ff0ebcc | 15274 | intel_fbc_disable(dev); |
e70236a8 | 15275 | |
69341a5e KH |
15276 | mutex_unlock(&dev->struct_mutex); |
15277 | ||
1630fe75 CW |
15278 | /* flush any delayed tasks or pending work */ |
15279 | flush_scheduled_work(); | |
15280 | ||
db31af1d JN |
15281 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15282 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15283 | struct intel_connector *intel_connector; |
15284 | ||
15285 | intel_connector = to_intel_connector(connector); | |
15286 | intel_connector->unregister(intel_connector); | |
db31af1d | 15287 | } |
d9255d57 | 15288 | |
79e53945 | 15289 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15290 | |
15291 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15292 | |
15293 | mutex_lock(&dev->struct_mutex); | |
15294 | intel_cleanup_gt_powersave(dev); | |
15295 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15296 | } |
15297 | ||
f1c79df3 ZW |
15298 | /* |
15299 | * Return which encoder is currently attached for connector. | |
15300 | */ | |
df0e9248 | 15301 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15302 | { |
df0e9248 CW |
15303 | return &intel_attached_encoder(connector)->base; |
15304 | } | |
f1c79df3 | 15305 | |
df0e9248 CW |
15306 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15307 | struct intel_encoder *encoder) | |
15308 | { | |
15309 | connector->encoder = encoder; | |
15310 | drm_mode_connector_attach_encoder(&connector->base, | |
15311 | &encoder->base); | |
79e53945 | 15312 | } |
28d52043 DA |
15313 | |
15314 | /* | |
15315 | * set vga decode state - true == enable VGA decode | |
15316 | */ | |
15317 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15318 | { | |
15319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15320 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15321 | u16 gmch_ctrl; |
15322 | ||
75fa041d CW |
15323 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15324 | DRM_ERROR("failed to read control word\n"); | |
15325 | return -EIO; | |
15326 | } | |
15327 | ||
c0cc8a55 CW |
15328 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15329 | return 0; | |
15330 | ||
28d52043 DA |
15331 | if (state) |
15332 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15333 | else | |
15334 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15335 | |
15336 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15337 | DRM_ERROR("failed to write control word\n"); | |
15338 | return -EIO; | |
15339 | } | |
15340 | ||
28d52043 DA |
15341 | return 0; |
15342 | } | |
c4a1d9e4 | 15343 | |
c4a1d9e4 | 15344 | struct intel_display_error_state { |
ff57f1b0 PZ |
15345 | |
15346 | u32 power_well_driver; | |
15347 | ||
63b66e5b CW |
15348 | int num_transcoders; |
15349 | ||
c4a1d9e4 CW |
15350 | struct intel_cursor_error_state { |
15351 | u32 control; | |
15352 | u32 position; | |
15353 | u32 base; | |
15354 | u32 size; | |
52331309 | 15355 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15356 | |
15357 | struct intel_pipe_error_state { | |
ddf9c536 | 15358 | bool power_domain_on; |
c4a1d9e4 | 15359 | u32 source; |
f301b1e1 | 15360 | u32 stat; |
52331309 | 15361 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15362 | |
15363 | struct intel_plane_error_state { | |
15364 | u32 control; | |
15365 | u32 stride; | |
15366 | u32 size; | |
15367 | u32 pos; | |
15368 | u32 addr; | |
15369 | u32 surface; | |
15370 | u32 tile_offset; | |
52331309 | 15371 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15372 | |
15373 | struct intel_transcoder_error_state { | |
ddf9c536 | 15374 | bool power_domain_on; |
63b66e5b CW |
15375 | enum transcoder cpu_transcoder; |
15376 | ||
15377 | u32 conf; | |
15378 | ||
15379 | u32 htotal; | |
15380 | u32 hblank; | |
15381 | u32 hsync; | |
15382 | u32 vtotal; | |
15383 | u32 vblank; | |
15384 | u32 vsync; | |
15385 | } transcoder[4]; | |
c4a1d9e4 CW |
15386 | }; |
15387 | ||
15388 | struct intel_display_error_state * | |
15389 | intel_display_capture_error_state(struct drm_device *dev) | |
15390 | { | |
fbee40df | 15391 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15392 | struct intel_display_error_state *error; |
63b66e5b CW |
15393 | int transcoders[] = { |
15394 | TRANSCODER_A, | |
15395 | TRANSCODER_B, | |
15396 | TRANSCODER_C, | |
15397 | TRANSCODER_EDP, | |
15398 | }; | |
c4a1d9e4 CW |
15399 | int i; |
15400 | ||
63b66e5b CW |
15401 | if (INTEL_INFO(dev)->num_pipes == 0) |
15402 | return NULL; | |
15403 | ||
9d1cb914 | 15404 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15405 | if (error == NULL) |
15406 | return NULL; | |
15407 | ||
190be112 | 15408 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15409 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15410 | ||
055e393f | 15411 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15412 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15413 | __intel_display_power_is_enabled(dev_priv, |
15414 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15415 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15416 | continue; |
15417 | ||
5efb3e28 VS |
15418 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15419 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15420 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15421 | |
15422 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15423 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 15424 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 15425 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15426 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15427 | } | |
ca291363 PZ |
15428 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
15429 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
15430 | if (INTEL_INFO(dev)->gen >= 4) { |
15431 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
15432 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15433 | } | |
15434 | ||
c4a1d9e4 | 15435 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15436 | |
3abfce77 | 15437 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 15438 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15439 | } |
15440 | ||
15441 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
15442 | if (HAS_DDI(dev_priv->dev)) | |
15443 | error->num_transcoders++; /* Account for eDP. */ | |
15444 | ||
15445 | for (i = 0; i < error->num_transcoders; i++) { | |
15446 | enum transcoder cpu_transcoder = transcoders[i]; | |
15447 | ||
ddf9c536 | 15448 | error->transcoder[i].power_domain_on = |
f458ebbc | 15449 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15450 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15451 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15452 | continue; |
15453 | ||
63b66e5b CW |
15454 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15455 | ||
15456 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15457 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15458 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15459 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15460 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15461 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15462 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15463 | } |
15464 | ||
15465 | return error; | |
15466 | } | |
15467 | ||
edc3d884 MK |
15468 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15469 | ||
c4a1d9e4 | 15470 | void |
edc3d884 | 15471 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15472 | struct drm_device *dev, |
15473 | struct intel_display_error_state *error) | |
15474 | { | |
055e393f | 15475 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
15476 | int i; |
15477 | ||
63b66e5b CW |
15478 | if (!error) |
15479 | return; | |
15480 | ||
edc3d884 | 15481 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 15482 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 15483 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15484 | error->power_well_driver); |
055e393f | 15485 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15486 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
15487 | err_printf(m, " Power: %s\n", |
15488 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 15489 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15490 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15491 | |
15492 | err_printf(m, "Plane [%d]:\n", i); | |
15493 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15494 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 15495 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
15496 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15497 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15498 | } |
4b71a570 | 15499 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 15500 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 15501 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
15502 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15503 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15504 | } |
15505 | ||
edc3d884 MK |
15506 | err_printf(m, "Cursor [%d]:\n", i); |
15507 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15508 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15509 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15510 | } |
63b66e5b CW |
15511 | |
15512 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 15513 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 15514 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
15515 | err_printf(m, " Power: %s\n", |
15516 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
15517 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15518 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15519 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15520 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15521 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15522 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15523 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15524 | } | |
c4a1d9e4 | 15525 | } |
e2fcdaa9 VS |
15526 | |
15527 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
15528 | { | |
15529 | struct intel_crtc *crtc; | |
15530 | ||
15531 | for_each_intel_crtc(dev, crtc) { | |
15532 | struct intel_unpin_work *work; | |
e2fcdaa9 | 15533 | |
5e2d7afc | 15534 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15535 | |
15536 | work = crtc->unpin_work; | |
15537 | ||
15538 | if (work && work->event && | |
15539 | work->event->base.file_priv == file) { | |
15540 | kfree(work->event); | |
15541 | work->event = NULL; | |
15542 | } | |
15543 | ||
5e2d7afc | 15544 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
15545 | } |
15546 | } |