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drm/i915: No LVDS hardware on Intel D410PT and D425KT
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
2377b741
JB		 72/* FDI */
73#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
74
d2acd215
DV		 75int
76intel_pch_rawclk(struct drm_device *dev)
77{
78 struct drm_i915_private *dev_priv = dev->dev_private;
79
80 WARN_ON(!HAS_PCH_SPLIT(dev));
81
82 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
83}
84
021357ac
CW		 85static inline u32 /* units of 100MHz */
86intel_fdi_link_freq(struct drm_device *dev)
87{
8b99e68c
CW		 88 if (IS_GEN5(dev)) {
89 struct drm_i915_private *dev_priv = dev->dev_private;
90 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
91 } else
92 return 27;
021357ac
CW		 93}
94
5d536e28 95static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 96 .dot = { .min = 25000, .max = 350000 },
97 .vco = { .min = 930000, .max = 1400000 },
98 .n = { .min = 3, .max = 16 },
99 .m = { .min = 96, .max = 140 },
100 .m1 = { .min = 18, .max = 26 },
101 .m2 = { .min = 6, .max = 16 },
102 .p = { .min = 4, .max = 128 },
103 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 104 .p2 = { .dot_limit = 165000,
105 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 106};
107
5d536e28
DV		 108static const intel_limit_t intel_limits_i8xx_dvo = {
109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 4 },
119};
120
e4b36699 121static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
e4b36699 132};
273e27ca 133
e4b36699 134static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 135 .dot = { .min = 20000, .max = 400000 },
136 .vco = { .min = 1400000, .max = 2800000 },
137 .n = { .min = 1, .max = 6 },
138 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 139 .m1 = { .min = 8, .max = 18 },
140 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 141 .p = { .min = 5, .max = 80 },
142 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 143 .p2 = { .dot_limit = 200000,
144 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 145};
146
147static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 7, .max = 98 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 112000,
157 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 158};
159
273e27ca 160
e4b36699 161static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 162 .dot = { .min = 25000, .max = 270000 },
163 .vco = { .min = 1750000, .max = 3500000},
164 .n = { .min = 1, .max = 4 },
165 .m = { .min = 104, .max = 138 },
166 .m1 = { .min = 17, .max = 23 },
167 .m2 = { .min = 5, .max = 11 },
168 .p = { .min = 10, .max = 30 },
169 .p1 = { .min = 1, .max = 3},
170 .p2 = { .dot_limit = 270000,
171 .p2_slow = 10,
172 .p2_fast = 10
044c7c41 173 },
e4b36699
KP		 174};
175
176static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 177 .dot = { .min = 22000, .max = 400000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 16, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 5, .max = 80 },
184 .p1 = { .min = 1, .max = 8},
185 .p2 = { .dot_limit = 165000,
186 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 190 .dot = { .min = 20000, .max = 115000 },
191 .vco = { .min = 1750000, .max = 3500000 },
192 .n = { .min = 1, .max = 3 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 17, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 28, .max = 112 },
197 .p1 = { .min = 2, .max = 8 },
198 .p2 = { .dot_limit = 0,
199 .p2_slow = 14, .p2_fast = 14
044c7c41 200 },
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 80000, .max = 224000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 14, .max = 42 },
211 .p1 = { .min = 2, .max = 6 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 7, .p2_fast = 7
044c7c41 214 },
e4b36699
KP		 215};
216
f2b115e6 217static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 218 .dot = { .min = 20000, .max = 400000},
219 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 220 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 221 .n = { .min = 3, .max = 6 },
222 .m = { .min = 2, .max = 256 },
273e27ca 223 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 224 .m1 = { .min = 0, .max = 0 },
225 .m2 = { .min = 0, .max = 254 },
226 .p = { .min = 5, .max = 80 },
227 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 228 .p2 = { .dot_limit = 200000,
229 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 230};
231
f2b115e6 232static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 233 .dot = { .min = 20000, .max = 400000 },
234 .vco = { .min = 1700000, .max = 3500000 },
235 .n = { .min = 3, .max = 6 },
236 .m = { .min = 2, .max = 256 },
237 .m1 = { .min = 0, .max = 0 },
238 .m2 = { .min = 0, .max = 254 },
239 .p = { .min = 7, .max = 112 },
240 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 241 .p2 = { .dot_limit = 112000,
242 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 243};
244
273e27ca
EA		 245/* Ironlake / Sandybridge
246 *
247 * We calculate clock using (register_value + 2) for N/M1/M2, so here
248 * the range value for them is (actual_value - 2).
249 */
b91ad0ec 250static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 251 .dot = { .min = 25000, .max = 350000 },
252 .vco = { .min = 1760000, .max = 3510000 },
253 .n = { .min = 1, .max = 5 },
254 .m = { .min = 79, .max = 127 },
255 .m1 = { .min = 12, .max = 22 },
256 .m2 = { .min = 5, .max = 9 },
257 .p = { .min = 5, .max = 80 },
258 .p1 = { .min = 1, .max = 8 },
259 .p2 = { .dot_limit = 225000,
260 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 261};
262
b91ad0ec 263static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 1760000, .max = 3510000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 79, .max = 118 },
268 .m1 = { .min = 12, .max = 22 },
269 .m2 = { .min = 5, .max = 9 },
270 .p = { .min = 28, .max = 112 },
271 .p1 = { .min = 2, .max = 8 },
272 .p2 = { .dot_limit = 225000,
273 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 274};
275
276static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 1760000, .max = 3510000 },
279 .n = { .min = 1, .max = 3 },
280 .m = { .min = 79, .max = 127 },
281 .m1 = { .min = 12, .max = 22 },
282 .m2 = { .min = 5, .max = 9 },
283 .p = { .min = 14, .max = 56 },
284 .p1 = { .min = 2, .max = 8 },
285 .p2 = { .dot_limit = 225000,
286 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 287};
288
273e27ca 289/* LVDS 100mhz refclk limits. */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 2 },
294 .m = { .min = 79, .max = 126 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 28, .max = 112 },
0206e353 298 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 301};
302
303static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 3 },
307 .m = { .min = 79, .max = 126 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 14, .max = 42 },
0206e353 311 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 314};
315
a0c4da24
JB		 316static const intel_limit_t intel_limits_vlv_dac = {
317 .dot = { .min = 25000, .max = 270000 },
318 .vco = { .min = 4000000, .max = 6000000 },
319 .n = { .min = 1, .max = 7 },
320 .m = { .min = 22, .max = 450 }, /* guess */
321 .m1 = { .min = 2, .max = 3 },
322 .m2 = { .min = 11, .max = 156 },
323 .p = { .min = 10, .max = 30 },
75e53986 324 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 325 .p2 = { .dot_limit = 270000,
326 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 327};
328
329static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 332 .n = { .min = 1, .max = 7 },
333 .m = { .min = 60, .max = 300 }, /* guess */
334 .m1 = { .min = 2, .max = 3 },
335 .m2 = { .min = 11, .max = 156 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 2, .max = 3 },
338 .p2 = { .dot_limit = 270000,
339 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 340};
341
342static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 345 .n = { .min = 1, .max = 7 },
74a4dd2e 346 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 353};
354
1b894b59
CW		 355static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
356 int refclk)
2c07245f 357{
b91ad0ec 358 struct drm_device *dev = crtc->dev;
2c07245f 359 const intel_limit_t *limit;
b91ad0ec
ZW		 360
361 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 362 if (intel_is_dual_link_lvds(dev)) {
1b894b59 363 if (refclk == 100000)
b91ad0ec
ZW		 364 limit = &intel_limits_ironlake_dual_lvds_100m;
365 else
366 limit = &intel_limits_ironlake_dual_lvds;
367 } else {
1b894b59 368 if (refclk == 100000)
b91ad0ec
ZW		 369 limit = &intel_limits_ironlake_single_lvds_100m;
370 else
371 limit = &intel_limits_ironlake_single_lvds;
372 }
c6bb3538 373 } else
b91ad0ec 374 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 375
376 return limit;
377}
378
044c7c41
ML		 379static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
380{
381 struct drm_device *dev = crtc->dev;
044c7c41
ML		 382 const intel_limit_t *limit;
383
384 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 385 if (intel_is_dual_link_lvds(dev))
e4b36699 386 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 387 else
e4b36699 388 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
390 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 391 limit = &intel_limits_g4x_hdmi;
044c7c41 392 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 393 limit = &intel_limits_g4x_sdvo;
044c7c41 394 } else /* The option is for other outputs */
e4b36699 395 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 396
397 return limit;
398}
399
1b894b59 400static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 401{
402 struct drm_device *dev = crtc->dev;
403 const intel_limit_t *limit;
404
bad720ff 405 if (HAS_PCH_SPLIT(dev))
1b894b59 406 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 407 else if (IS_G4X(dev)) {
044c7c41 408 limit = intel_g4x_limit(crtc);
f2b115e6 409 } else if (IS_PINEVIEW(dev)) {
2177832f 410 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 411 limit = &intel_limits_pineview_lvds;
2177832f 412 else
f2b115e6 413 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 414 } else if (IS_VALLEYVIEW(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
416 limit = &intel_limits_vlv_dac;
417 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
418 limit = &intel_limits_vlv_hdmi;
419 else
420 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 421 } else if (!IS_GEN2(dev)) {
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
423 limit = &intel_limits_i9xx_lvds;
424 else
425 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 426 } else {
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 428 limit = &intel_limits_i8xx_lvds;
5d536e28 429 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 430 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 431 else
432 limit = &intel_limits_i8xx_dac;
79e53945
JB		 433 }
434 return limit;
435}
436
f2b115e6
AJ		 437/* m1 is reserved as 0 in Pineview, n is a ring counter */
438static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 439{
2177832f
SL		 440 clock->m = clock->m2 + 2;
441 clock->p = clock->p1 * clock->p2;
442 clock->vco = refclk * clock->m / clock->n;
443 clock->dot = clock->vco / clock->p;
444}
445
7429e9d4
DV		 446static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
447{
448 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
449}
450
ac58c3f0 451static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 452{
7429e9d4 453 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 454 clock->p = clock->p1 * clock->p2;
455 clock->vco = refclk * clock->m / (clock->n + 2);
456 clock->dot = clock->vco / clock->p;
457}
458
79e53945
JB		 459/**
460 * Returns whether any output on the specified pipe is of the specified type
461 */
4ef69c7a 462bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 463{
4ef69c7a 464 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 465 struct intel_encoder *encoder;
466
6c2b7c12
DV		 467 for_each_encoder_on_crtc(dev, crtc, encoder)
468 if (encoder->type == type)
4ef69c7a
CW		 469 return true;
470
471 return false;
79e53945
JB		 472}
473
7c04d1d9 474#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 475/**
476 * Returns whether the given set of divisors are valid for a given refclk with
477 * the given connectors.
478 */
479
1b894b59
CW		 480static bool intel_PLL_is_valid(struct drm_device *dev,
481 const intel_limit_t *limit,
482 const intel_clock_t *clock)
79e53945 483{
79e53945 484 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 485 INTELPllInvalid("p1 out of range\n");
79e53945 486 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 487 INTELPllInvalid("p out of range\n");
79e53945 488 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 489 INTELPllInvalid("m2 out of range\n");
79e53945 490 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 491 INTELPllInvalid("m1 out of range\n");
f2b115e6 492 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 493 INTELPllInvalid("m1 <= m2\n");
79e53945 494 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 495 INTELPllInvalid("m out of range\n");
79e53945 496 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 497 INTELPllInvalid("n out of range\n");
79e53945 498 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 499 INTELPllInvalid("vco out of range\n");
79e53945
JB		 500 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
501 * connector, etc., rather than just a single range.
502 */
503 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 504 INTELPllInvalid("dot out of range\n");
79e53945
JB		 505
506 return true;
507}
508
d4906093 509static bool
ee9300bb 510i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 511 int target, int refclk, intel_clock_t *match_clock,
512 intel_clock_t *best_clock)
79e53945
JB		 513{
514 struct drm_device *dev = crtc->dev;
79e53945 515 intel_clock_t clock;
79e53945
JB		 516 int err = target;
517
a210b028 518 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 519 /*
a210b028
DV		 520 * For LVDS just rely on its current settings for dual-channel.
521 * We haven't figured out how to reliably set up different
522 * single/dual channel state, if we even can.
79e53945 523 */
1974cad0 524 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 525 clock.p2 = limit->p2.p2_fast;
526 else
527 clock.p2 = limit->p2.p2_slow;
528 } else {
529 if (target < limit->p2.dot_limit)
530 clock.p2 = limit->p2.p2_slow;
531 else
532 clock.p2 = limit->p2.p2_fast;
533 }
534
0206e353 535 memset(best_clock, 0, sizeof(*best_clock));
79e53945 536
42158660
ZY		 537 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
538 clock.m1++) {
539 for (clock.m2 = limit->m2.min;
540 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 541 if (clock.m2 >= clock.m1)
42158660
ZY		 542 break;
543 for (clock.n = limit->n.min;
544 clock.n <= limit->n.max; clock.n++) {
545 for (clock.p1 = limit->p1.min;
546 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 547 int this_err;
548
ac58c3f0
DV		 549 i9xx_clock(refclk, &clock);
550 if (!intel_PLL_is_valid(dev, limit,
551 &clock))
552 continue;
553 if (match_clock &&
554 clock.p != match_clock->p)
555 continue;
556
557 this_err = abs(clock.dot - target);
558 if (this_err < err) {
559 *best_clock = clock;
560 err = this_err;
561 }
562 }
563 }
564 }
565 }
566
567 return (err != target);
568}
569
570static bool
ee9300bb
DV		 571pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
572 int target, int refclk, intel_clock_t *match_clock,
573 intel_clock_t *best_clock)
79e53945
JB		 574{
575 struct drm_device *dev = crtc->dev;
79e53945 576 intel_clock_t clock;
79e53945
JB		 577 int err = target;
578
a210b028 579 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 580 /*
a210b028
DV		 581 * For LVDS just rely on its current settings for dual-channel.
582 * We haven't figured out how to reliably set up different
583 * single/dual channel state, if we even can.
79e53945 584 */
1974cad0 585 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 586 clock.p2 = limit->p2.p2_fast;
587 else
588 clock.p2 = limit->p2.p2_slow;
589 } else {
590 if (target < limit->p2.dot_limit)
591 clock.p2 = limit->p2.p2_slow;
592 else
593 clock.p2 = limit->p2.p2_fast;
594 }
595
0206e353 596 memset(best_clock, 0, sizeof(*best_clock));
79e53945 597
42158660
ZY		 598 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
599 clock.m1++) {
600 for (clock.m2 = limit->m2.min;
601 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 602 for (clock.n = limit->n.min;
603 clock.n <= limit->n.max; clock.n++) {
604 for (clock.p1 = limit->p1.min;
605 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 606 int this_err;
607
ac58c3f0 608 pineview_clock(refclk, &clock);
1b894b59
CW		 609 if (!intel_PLL_is_valid(dev, limit,
610 &clock))
79e53945 611 continue;
cec2f356
SP		 612 if (match_clock &&
613 clock.p != match_clock->p)
614 continue;
79e53945
JB		 615
616 this_err = abs(clock.dot - target);
617 if (this_err < err) {
618 *best_clock = clock;
619 err = this_err;
620 }
621 }
622 }
623 }
624 }
625
626 return (err != target);
627}
628
d4906093 629static bool
ee9300bb
DV		 630g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
631 int target, int refclk, intel_clock_t *match_clock,
632 intel_clock_t *best_clock)
d4906093
ML		 633{
634 struct drm_device *dev = crtc->dev;
d4906093
ML		 635 intel_clock_t clock;
636 int max_n;
637 bool found;
6ba770dc
AJ		 638 /* approximately equals target * 0.00585 */
639 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 640 found = false;
641
642 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 643 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 644 clock.p2 = limit->p2.p2_fast;
645 else
646 clock.p2 = limit->p2.p2_slow;
647 } else {
648 if (target < limit->p2.dot_limit)
649 clock.p2 = limit->p2.p2_slow;
650 else
651 clock.p2 = limit->p2.p2_fast;
652 }
653
654 memset(best_clock, 0, sizeof(*best_clock));
655 max_n = limit->n.max;
f77f13e2 656 /* based on hardware requirement, prefer smaller n to precision */
d4906093 657 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 658 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 659 for (clock.m1 = limit->m1.max;
660 clock.m1 >= limit->m1.min; clock.m1--) {
661 for (clock.m2 = limit->m2.max;
662 clock.m2 >= limit->m2.min; clock.m2--) {
663 for (clock.p1 = limit->p1.max;
664 clock.p1 >= limit->p1.min; clock.p1--) {
665 int this_err;
666
ac58c3f0 667 i9xx_clock(refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
d4906093 670 continue;
1b894b59
CW		 671
672 this_err = abs(clock.dot - target);
d4906093
ML		 673 if (this_err < err_most) {
674 *best_clock = clock;
675 err_most = this_err;
676 max_n = clock.n;
677 found = true;
678 }
679 }
680 }
681 }
682 }
2c07245f
ZW		 683 return found;
684}
685
a0c4da24 686static bool
ee9300bb
DV		 687vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
688 int target, int refclk, intel_clock_t *match_clock,
689 intel_clock_t *best_clock)
a0c4da24
JB		 690{
691 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
692 u32 m, n, fastclk;
f3f08572 693 u32 updrate, minupdate, p;
a0c4da24
JB		 694 unsigned long bestppm, ppm, absppm;
695 int dotclk, flag;
696
af447bd3 697 flag = 0;
a0c4da24
JB		 698 dotclk = target * 1000;
699 bestppm = 1000000;
700 ppm = absppm = 0;
701 fastclk = dotclk / (2*100);
702 updrate = 0;
703 minupdate = 19200;
a0c4da24
JB		 704 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
705 bestm1 = bestm2 = bestp1 = bestp2 = 0;
706
707 /* based on hardware requirement, prefer smaller n to precision */
708 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
709 updrate = refclk / n;
710 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
711 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
712 if (p2 > 10)
713 p2 = p2 - 1;
714 p = p1 * p2;
715 /* based on hardware requirement, prefer bigger m1,m2 values */
716 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
717 m2 = (((2*(fastclk * p * n / m1 )) +
718 refclk) / (2*refclk));
719 m = m1 * m2;
720 vco = updrate * m;
721 if (vco >= limit->vco.min && vco < limit->vco.max) {
722 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
723 absppm = (ppm > 0) ? ppm : (-ppm);
724 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
725 bestppm = 0;
726 flag = 1;
727 }
728 if (absppm < bestppm - 10) {
729 bestppm = absppm;
730 flag = 1;
731 }
732 if (flag) {
733 bestn = n;
734 bestm1 = m1;
735 bestm2 = m2;
736 bestp1 = p1;
737 bestp2 = p2;
738 flag = 0;
739 }
740 }
741 }
742 }
743 }
744 }
745 best_clock->n = bestn;
746 best_clock->m1 = bestm1;
747 best_clock->m2 = bestm2;
748 best_clock->p1 = bestp1;
749 best_clock->p2 = bestp2;
750
751 return true;
752}
a4fc5ed6 753
a5c961d1
PZ		 754enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
755 enum pipe pipe)
756{
757 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
759
3b117c8f 760 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 761}
762
a928d536
PZ		 763static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
764{
765 struct drm_i915_private *dev_priv = dev->dev_private;
766 u32 frame, frame_reg = PIPEFRAME(pipe);
767
768 frame = I915_READ(frame_reg);
769
770 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
771 DRM_DEBUG_KMS("vblank wait timed out\n");
772}
773
9d0498a2
JB		 774/**
775 * intel_wait_for_vblank - wait for vblank on a given pipe
776 * @dev: drm device
777 * @pipe: pipe to wait for
778 *
779 * Wait for vblank to occur on a given pipe. Needed for various bits of
780 * mode setting code.
781 */
782void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 783{
9d0498a2 784 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 785 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 786
a928d536
PZ		 787 if (INTEL_INFO(dev)->gen >= 5) {
788 ironlake_wait_for_vblank(dev, pipe);
789 return;
790 }
791
300387c0
CW		 792 /* Clear existing vblank status. Note this will clear any other
793 * sticky status fields as well.
794 *
795 * This races with i915_driver_irq_handler() with the result
796 * that either function could miss a vblank event. Here it is not
797 * fatal, as we will either wait upon the next vblank interrupt or
798 * timeout. Generally speaking intel_wait_for_vblank() is only
799 * called during modeset at which time the GPU should be idle and
800 * should *not* be performing page flips and thus not waiting on
801 * vblanks...
802 * Currently, the result of us stealing a vblank from the irq
803 * handler is that a single frame will be skipped during swapbuffers.
804 */
805 I915_WRITE(pipestat_reg,
806 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
807
9d0498a2 808 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 809 if (wait_for(I915_READ(pipestat_reg) &
810 PIPE_VBLANK_INTERRUPT_STATUS,
811 50))
9d0498a2
JB		 812 DRM_DEBUG_KMS("vblank wait timed out\n");
813}
814
ab7ad7f6
KP		 815/*
816 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 817 * @dev: drm device
818 * @pipe: pipe to wait for
819 *
820 * After disabling a pipe, we can't wait for vblank in the usual way,
821 * spinning on the vblank interrupt status bit, since we won't actually
822 * see an interrupt when the pipe is disabled.
823 *
ab7ad7f6
KP		 824 * On Gen4 and above:
825 * wait for the pipe register state bit to turn off
826 *
827 * Otherwise:
828 * wait for the display line value to settle (it usually
829 * ends up stopping at the start of the next frame).
58e10eb9 830 *
9d0498a2 831 */
58e10eb9 832void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 833{
834 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 835 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
836 pipe);
ab7ad7f6
KP		 837
838 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 839 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 840
841 /* Wait for the Pipe State to go off */
58e10eb9
CW		 842 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
843 100))
284637d9 844 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 845 } else {
837ba00f 846 u32 last_line, line_mask;
58e10eb9 847 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 848 unsigned long timeout = jiffies + msecs_to_jiffies(100);
849
837ba00f
PZ		 850 if (IS_GEN2(dev))
851 line_mask = DSL_LINEMASK_GEN2;
852 else
853 line_mask = DSL_LINEMASK_GEN3;
854
ab7ad7f6
KP		 855 /* Wait for the display line to settle */
856 do {
837ba00f 857 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 858 mdelay(5);
837ba00f 859 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 860 time_after(timeout, jiffies));
861 if (time_after(jiffies, timeout))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 }
79e53945
JB		 864}
865
b0ea7d37
DL		 866/*
867 * ibx_digital_port_connected - is the specified port connected?
868 * @dev_priv: i915 private structure
869 * @port: the port to test
870 *
871 * Returns true if @port is connected, false otherwise.
872 */
873bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
874 struct intel_digital_port *port)
875{
876 u32 bit;
877
c36346e3
DL		 878 if (HAS_PCH_IBX(dev_priv->dev)) {
879 switch(port->port) {
880 case PORT_B:
881 bit = SDE_PORTB_HOTPLUG;
882 break;
883 case PORT_C:
884 bit = SDE_PORTC_HOTPLUG;
885 break;
886 case PORT_D:
887 bit = SDE_PORTD_HOTPLUG;
888 break;
889 default:
890 return true;
891 }
892 } else {
893 switch(port->port) {
894 case PORT_B:
895 bit = SDE_PORTB_HOTPLUG_CPT;
896 break;
897 case PORT_C:
898 bit = SDE_PORTC_HOTPLUG_CPT;
899 break;
900 case PORT_D:
901 bit = SDE_PORTD_HOTPLUG_CPT;
902 break;
903 default:
904 return true;
905 }
b0ea7d37
DL		 906 }
907
908 return I915_READ(SDEISR) & bit;
909}
910
b24e7179
JB		 911static const char *state_string(bool enabled)
912{
913 return enabled ? "on" : "off";
914}
915
916/* Only for pre-ILK configs */
55607e8a
DV		 917void assert_pll(struct drm_i915_private *dev_priv,
918 enum pipe pipe, bool state)
b24e7179
JB		 919{
920 int reg;
921 u32 val;
922 bool cur_state;
923
924 reg = DPLL(pipe);
925 val = I915_READ(reg);
926 cur_state = !!(val & DPLL_VCO_ENABLE);
927 WARN(cur_state != state,
928 "PLL state assertion failure (expected %s, current %s)\n",
929 state_string(state), state_string(cur_state));
930}
b24e7179 931
55607e8a 932struct intel_shared_dpll *
e2b78267
DV		 933intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
934{
935 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
936
a43f6e0f 937 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 938 return NULL;
939
a43f6e0f 940 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 941}
942
040484af 943/* For ILK+ */
55607e8a
DV		 944void assert_shared_dpll(struct drm_i915_private *dev_priv,
945 struct intel_shared_dpll *pll,
946 bool state)
040484af 947{
040484af 948 bool cur_state;
5358901f 949 struct intel_dpll_hw_state hw_state;
040484af 950
9d82aa17
ED		 951 if (HAS_PCH_LPT(dev_priv->dev)) {
952 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
953 return;
954 }
955
92b27b08 956 if (WARN (!pll,
46edb027 957 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 958 return;
ee7b9f93 959
5358901f 960 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 961 WARN(cur_state != state,
5358901f
DV		 962 "%s assertion failure (expected %s, current %s)\n",
963 pll->name, state_string(state), state_string(cur_state));
040484af 964}
040484af
JB		 965
966static void assert_fdi_tx(struct drm_i915_private *dev_priv,
967 enum pipe pipe, bool state)
968{
969 int reg;
970 u32 val;
971 bool cur_state;
ad80a810
PZ		 972 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
973 pipe);
040484af 974
affa9354
PZ		 975 if (HAS_DDI(dev_priv->dev)) {
976 /* DDI does not have a specific FDI_TX register */
ad80a810 977 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 978 val = I915_READ(reg);
ad80a810 979 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 980 } else {
981 reg = FDI_TX_CTL(pipe);
982 val = I915_READ(reg);
983 cur_state = !!(val & FDI_TX_ENABLE);
984 }
040484af
JB		 985 WARN(cur_state != state,
986 "FDI TX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
990#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
991
992static void assert_fdi_rx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994{
995 int reg;
996 u32 val;
997 bool cur_state;
998
d63fa0dc
PZ		 999 reg = FDI_RX_CTL(pipe);
1000 val = I915_READ(reg);
1001 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI RX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1007#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1008
1009static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014
1015 /* ILK FDI PLL is always enabled */
1016 if (dev_priv->info->gen == 5)
1017 return;
1018
bf507ef7 1019 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1020 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1021 return;
1022
040484af
JB		 1023 reg = FDI_TX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1026}
1027
55607e8a
DV		 1028void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1029 enum pipe pipe, bool state)
040484af
JB		 1030{
1031 int reg;
1032 u32 val;
55607e8a 1033 bool cur_state;
040484af
JB		 1034
1035 reg = FDI_RX_CTL(pipe);
1036 val = I915_READ(reg);
55607e8a
DV		 1037 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1038 WARN(cur_state != state,
1039 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
040484af
JB		 1041}
1042
ea0760cf
JB		 1043static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1044 enum pipe pipe)
1045{
1046 int pp_reg, lvds_reg;
1047 u32 val;
1048 enum pipe panel_pipe = PIPE_A;
0de3b485 1049 bool locked = true;
ea0760cf
JB		 1050
1051 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1052 pp_reg = PCH_PP_CONTROL;
1053 lvds_reg = PCH_LVDS;
1054 } else {
1055 pp_reg = PP_CONTROL;
1056 lvds_reg = LVDS;
1057 }
1058
1059 val = I915_READ(pp_reg);
1060 if (!(val & PANEL_POWER_ON) ||
1061 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1062 locked = false;
1063
1064 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1065 panel_pipe = PIPE_B;
1066
1067 WARN(panel_pipe == pipe && locked,
1068 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1069 pipe_name(pipe));
ea0760cf
JB		 1070}
1071
b840d907
JB		 1072void assert_pipe(struct drm_i915_private *dev_priv,
1073 enum pipe pipe, bool state)
b24e7179
JB		 1074{
1075 int reg;
1076 u32 val;
63d7bbe9 1077 bool cur_state;
702e7a56
PZ		 1078 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1079 pipe);
b24e7179 1080
8e636784
DV		 1081 /* if we need the pipe A quirk it must be always on */
1082 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1083 state = true;
1084
b97186f0
PZ		 1085 if (!intel_display_power_enabled(dev_priv->dev,
1086 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1087 cur_state = false;
1088 } else {
1089 reg = PIPECONF(cpu_transcoder);
1090 val = I915_READ(reg);
1091 cur_state = !!(val & PIPECONF_ENABLE);
1092 }
1093
63d7bbe9
JB		 1094 WARN(cur_state != state,
1095 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1096 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1097}
1098
931872fc
CW		 1099static void assert_plane(struct drm_i915_private *dev_priv,
1100 enum plane plane, bool state)
b24e7179
JB		 1101{
1102 int reg;
1103 u32 val;
931872fc 1104 bool cur_state;
b24e7179
JB		 1105
1106 reg = DSPCNTR(plane);
1107 val = I915_READ(reg);
931872fc
CW		 1108 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1109 WARN(cur_state != state,
1110 "plane %c assertion failure (expected %s, current %s)\n",
1111 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1112}
1113
931872fc
CW		 1114#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1115#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1116
b24e7179
JB		 1117static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1118 enum pipe pipe)
1119{
653e1026 1120 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1121 int reg, i;
1122 u32 val;
1123 int cur_pipe;
1124
653e1026
VS		 1125 /* Primary planes are fixed to pipes on gen4+ */
1126 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1127 reg = DSPCNTR(pipe);
1128 val = I915_READ(reg);
1129 WARN((val & DISPLAY_PLANE_ENABLE),
1130 "plane %c assertion failure, should be disabled but not\n",
1131 plane_name(pipe));
19ec1358 1132 return;
28c05794 1133 }
19ec1358 1134
b24e7179 1135 /* Need to check both planes against the pipe */
08e2a7de 1136 for_each_pipe(i) {
b24e7179
JB		 1137 reg = DSPCNTR(i);
1138 val = I915_READ(reg);
1139 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1140 DISPPLANE_SEL_PIPE_SHIFT;
1141 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1142 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1143 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1144 }
1145}
1146
19332d7a
JB		 1147static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1148 enum pipe pipe)
1149{
20674eef 1150 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1151 int reg, i;
1152 u32 val;
1153
20674eef
VS		 1154 if (IS_VALLEYVIEW(dev)) {
1155 for (i = 0; i < dev_priv->num_plane; i++) {
1156 reg = SPCNTR(pipe, i);
1157 val = I915_READ(reg);
1158 WARN((val & SP_ENABLE),
1159 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1160 sprite_name(pipe, i), pipe_name(pipe));
1161 }
1162 } else if (INTEL_INFO(dev)->gen >= 7) {
1163 reg = SPRCTL(pipe);
19332d7a 1164 val = I915_READ(reg);
20674eef 1165 WARN((val & SPRITE_ENABLE),
06da8da2 1166 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1167 plane_name(pipe), pipe_name(pipe));
1168 } else if (INTEL_INFO(dev)->gen >= 5) {
1169 reg = DVSCNTR(pipe);
19332d7a 1170 val = I915_READ(reg);
20674eef 1171 WARN((val & DVS_ENABLE),
06da8da2 1172 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1173 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1174 }
1175}
1176
92f2584a
JB		 1177static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1178{
1179 u32 val;
1180 bool enabled;
1181
9d82aa17
ED		 1182 if (HAS_PCH_LPT(dev_priv->dev)) {
1183 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1184 return;
1185 }
1186
92f2584a
JB		 1187 val = I915_READ(PCH_DREF_CONTROL);
1188 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1189 DREF_SUPERSPREAD_SOURCE_MASK));
1190 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1191}
1192
ab9412ba
DV		 1193static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1194 enum pipe pipe)
92f2584a
JB		 1195{
1196 int reg;
1197 u32 val;
1198 bool enabled;
1199
ab9412ba 1200 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1201 val = I915_READ(reg);
1202 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1203 WARN(enabled,
1204 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1205 pipe_name(pipe));
92f2584a
JB		 1206}
1207
4e634389
KP		 1208static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1210{
1211 if ((val & DP_PORT_EN) == 0)
1212 return false;
1213
1214 if (HAS_PCH_CPT(dev_priv->dev)) {
1215 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1216 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1217 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1218 return false;
1219 } else {
1220 if ((val & DP_PIPE_MASK) != (pipe << 30))
1221 return false;
1222 }
1223 return true;
1224}
1225
1519b995
KP		 1226static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1227 enum pipe pipe, u32 val)
1228{
dc0fa718 1229 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1230 return false;
1231
1232 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1233 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1234 return false;
1235 } else {
dc0fa718 1236 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1237 return false;
1238 }
1239 return true;
1240}
1241
1242static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244{
1245 if ((val & LVDS_PORT_EN) == 0)
1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
1249 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1250 return false;
1251 } else {
1252 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1253 return false;
1254 }
1255 return true;
1256}
1257
1258static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260{
1261 if ((val & ADPA_DAC_ENABLE) == 0)
1262 return false;
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
1264 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1265 return false;
1266 } else {
1267 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1268 return false;
1269 }
1270 return true;
1271}
1272
291906f1 1273static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1274 enum pipe pipe, int reg, u32 port_sel)
291906f1 1275{
47a05eca 1276 u32 val = I915_READ(reg);
4e634389 1277 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1278 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1279 reg, pipe_name(pipe));
de9a35ab 1280
75c5da27
DV		 1281 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1282 && (val & DP_PIPEB_SELECT),
de9a35ab 1283 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1284}
1285
1286static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1287 enum pipe pipe, int reg)
1288{
47a05eca 1289 u32 val = I915_READ(reg);
b70ad586 1290 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1291 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1292 reg, pipe_name(pipe));
de9a35ab 1293
dc0fa718 1294 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1295 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1296 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1297}
1298
1299static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1300 enum pipe pipe)
1301{
1302 int reg;
1303 u32 val;
291906f1 1304
f0575e92
KP		 1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1306 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1307 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1308
1309 reg = PCH_ADPA;
1310 val = I915_READ(reg);
b70ad586 1311 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1312 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1313 pipe_name(pipe));
291906f1
JB		 1314
1315 reg = PCH_LVDS;
1316 val = I915_READ(reg);
b70ad586 1317 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1318 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1319 pipe_name(pipe));
291906f1 1320
e2debe91
PZ		 1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1322 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1323 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1324}
1325
426115cf 1326static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1327{
426115cf
DV		 1328 struct drm_device *dev = crtc->base.dev;
1329 struct drm_i915_private *dev_priv = dev->dev_private;
1330 int reg = DPLL(crtc->pipe);
1331 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1332
426115cf 1333 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1334
1335 /* No really, not for ILK+ */
1336 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1337
1338 /* PLL is protected by panel, make sure we can write it */
1339 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1340 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1341
426115cf
DV		 1342 I915_WRITE(reg, dpll);
1343 POSTING_READ(reg);
1344 udelay(150);
1345
1346 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1347 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1348
1349 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1350 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1351
1352 /* We do this three times for luck */
426115cf 1353 I915_WRITE(reg, dpll);
87442f73
DV		 1354 POSTING_READ(reg);
1355 udelay(150); /* wait for warmup */
426115cf 1356 I915_WRITE(reg, dpll);
87442f73
DV		 1357 POSTING_READ(reg);
1358 udelay(150); /* wait for warmup */
426115cf 1359 I915_WRITE(reg, dpll);
87442f73
DV		 1360 POSTING_READ(reg);
1361 udelay(150); /* wait for warmup */
1362}
1363
66e3d5c0 1364static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1365{
66e3d5c0
DV		 1366 struct drm_device *dev = crtc->base.dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 int reg = DPLL(crtc->pipe);
1369 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1370
66e3d5c0 1371 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1372
63d7bbe9 1373 /* No really, not for ILK+ */
87442f73 1374 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1375
1376 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1377 if (IS_MOBILE(dev) && !IS_I830(dev))
1378 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1379
66e3d5c0
DV		 1380 I915_WRITE(reg, dpll);
1381
1382 /* Wait for the clocks to stabilize. */
1383 POSTING_READ(reg);
1384 udelay(150);
1385
1386 if (INTEL_INFO(dev)->gen >= 4) {
1387 I915_WRITE(DPLL_MD(crtc->pipe),
1388 crtc->config.dpll_hw_state.dpll_md);
1389 } else {
1390 /* The pixel multiplier can only be updated once the
1391 * DPLL is enabled and the clocks are stable.
1392 *
1393 * So write it again.
1394 */
1395 I915_WRITE(reg, dpll);
1396 }
63d7bbe9
JB		 1397
1398 /* We do this three times for luck */
66e3d5c0 1399 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1400 POSTING_READ(reg);
1401 udelay(150); /* wait for warmup */
66e3d5c0 1402 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1403 POSTING_READ(reg);
1404 udelay(150); /* wait for warmup */
66e3d5c0 1405 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1406 POSTING_READ(reg);
1407 udelay(150); /* wait for warmup */
1408}
1409
1410/**
50b44a44 1411 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1412 * @dev_priv: i915 private structure
1413 * @pipe: pipe PLL to disable
1414 *
1415 * Disable the PLL for @pipe, making sure the pipe is off first.
1416 *
1417 * Note! This is for pre-ILK only.
1418 */
50b44a44 1419static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1420{
63d7bbe9
JB		 1421 /* Don't disable pipe A or pipe A PLLs if needed */
1422 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1423 return;
1424
1425 /* Make sure the pipe isn't still relying on us */
1426 assert_pipe_disabled(dev_priv, pipe);
1427
50b44a44
DV		 1428 I915_WRITE(DPLL(pipe), 0);
1429 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1430}
1431
89b667f8
JB		 1432void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1433{
1434 u32 port_mask;
1435
1436 if (!port)
1437 port_mask = DPLL_PORTB_READY_MASK;
1438 else
1439 port_mask = DPLL_PORTC_READY_MASK;
1440
1441 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1442 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1443 'B' + port, I915_READ(DPLL(0)));
1444}
1445
92f2584a 1446/**
e72f9fbf 1447 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1448 * @dev_priv: i915 private structure
1449 * @pipe: pipe PLL to enable
1450 *
1451 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1452 * drives the transcoder clock.
1453 */
e2b78267 1454static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1455{
e2b78267
DV		 1456 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1457 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1458
48da64a8 1459 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1460 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1461 if (WARN_ON(pll == NULL))
48da64a8
CW		 1462 return;
1463
1464 if (WARN_ON(pll->refcount == 0))
1465 return;
ee7b9f93 1466
46edb027
DV		 1467 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1468 pll->name, pll->active, pll->on,
e2b78267 1469 crtc->base.base.id);
92f2584a 1470
cdbd2316
DV		 1471 if (pll->active++) {
1472 WARN_ON(!pll->on);
e9d6944e 1473 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1474 return;
1475 }
f4a091c7 1476 WARN_ON(pll->on);
ee7b9f93 1477
46edb027 1478 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1479 pll->enable(dev_priv, pll);
ee7b9f93 1480 pll->on = true;
92f2584a
JB		 1481}
1482
e2b78267 1483static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1484{
e2b78267
DV		 1485 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1486 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1487
92f2584a
JB		 1488 /* PCH only available on ILK+ */
1489 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1490 if (WARN_ON(pll == NULL))
ee7b9f93 1491 return;
92f2584a 1492
48da64a8
CW		 1493 if (WARN_ON(pll->refcount == 0))
1494 return;
7a419866 1495
46edb027
DV		 1496 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1497 pll->name, pll->active, pll->on,
e2b78267 1498 crtc->base.base.id);
7a419866 1499
48da64a8 1500 if (WARN_ON(pll->active == 0)) {
e9d6944e 1501 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1502 return;
1503 }
1504
e9d6944e 1505 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1506 WARN_ON(!pll->on);
cdbd2316 1507 if (--pll->active)
7a419866 1508 return;
ee7b9f93 1509
46edb027 1510 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1511 pll->disable(dev_priv, pll);
ee7b9f93 1512 pll->on = false;
92f2584a
JB		 1513}
1514
b8a4f404
PZ		 1515static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1516 enum pipe pipe)
040484af 1517{
23670b32 1518 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1519 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1521 uint32_t reg, val, pipeconf_val;
040484af
JB		 1522
1523 /* PCH only available on ILK+ */
1524 BUG_ON(dev_priv->info->gen < 5);
1525
1526 /* Make sure PCH DPLL is enabled */
e72f9fbf 1527 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1528 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1529
1530 /* FDI must be feeding us bits for PCH ports */
1531 assert_fdi_tx_enabled(dev_priv, pipe);
1532 assert_fdi_rx_enabled(dev_priv, pipe);
1533
23670b32
DV		 1534 if (HAS_PCH_CPT(dev)) {
1535 /* Workaround: Set the timing override bit before enabling the
1536 * pch transcoder. */
1537 reg = TRANS_CHICKEN2(pipe);
1538 val = I915_READ(reg);
1539 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1540 I915_WRITE(reg, val);
59c859d6 1541 }
23670b32 1542
ab9412ba 1543 reg = PCH_TRANSCONF(pipe);
040484af 1544 val = I915_READ(reg);
5f7f726d 1545 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1546
1547 if (HAS_PCH_IBX(dev_priv->dev)) {
1548 /*
1549 * make the BPC in transcoder be consistent with
1550 * that in pipeconf reg.
1551 */
dfd07d72
DV		 1552 val &= ~PIPECONF_BPC_MASK;
1553 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1554 }
5f7f726d
PZ		 1555
1556 val &= ~TRANS_INTERLACE_MASK;
1557 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1558 if (HAS_PCH_IBX(dev_priv->dev) &&
1559 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1560 val |= TRANS_LEGACY_INTERLACED_ILK;
1561 else
1562 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1563 else
1564 val |= TRANS_PROGRESSIVE;
1565
040484af
JB		 1566 I915_WRITE(reg, val | TRANS_ENABLE);
1567 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1568 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1569}
1570
8fb033d7 1571static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1572 enum transcoder cpu_transcoder)
040484af 1573{
8fb033d7 1574 u32 val, pipeconf_val;
8fb033d7
PZ		 1575
1576 /* PCH only available on ILK+ */
1577 BUG_ON(dev_priv->info->gen < 5);
1578
8fb033d7 1579 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1580 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1581 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1582
223a6fdf
PZ		 1583 /* Workaround: set timing override bit. */
1584 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1585 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1586 I915_WRITE(_TRANSA_CHICKEN2, val);
1587
25f3ef11 1588 val = TRANS_ENABLE;
937bb610 1589 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1590
9a76b1c6
PZ		 1591 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1592 PIPECONF_INTERLACED_ILK)
a35f2679 1593 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1594 else
1595 val |= TRANS_PROGRESSIVE;
1596
ab9412ba
DV		 1597 I915_WRITE(LPT_TRANSCONF, val);
1598 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1599 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1600}
1601
b8a4f404
PZ		 1602static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1603 enum pipe pipe)
040484af 1604{
23670b32
DV		 1605 struct drm_device *dev = dev_priv->dev;
1606 uint32_t reg, val;
040484af
JB		 1607
1608 /* FDI relies on the transcoder */
1609 assert_fdi_tx_disabled(dev_priv, pipe);
1610 assert_fdi_rx_disabled(dev_priv, pipe);
1611
291906f1
JB		 1612 /* Ports must be off as well */
1613 assert_pch_ports_disabled(dev_priv, pipe);
1614
ab9412ba 1615 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1616 val = I915_READ(reg);
1617 val &= ~TRANS_ENABLE;
1618 I915_WRITE(reg, val);
1619 /* wait for PCH transcoder off, transcoder state */
1620 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1621 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1622
1623 if (!HAS_PCH_IBX(dev)) {
1624 /* Workaround: Clear the timing override chicken bit again. */
1625 reg = TRANS_CHICKEN2(pipe);
1626 val = I915_READ(reg);
1627 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1628 I915_WRITE(reg, val);
1629 }
040484af
JB		 1630}
1631
ab4d966c 1632static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1633{
8fb033d7
PZ		 1634 u32 val;
1635
ab9412ba 1636 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1637 val &= ~TRANS_ENABLE;
ab9412ba 1638 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1639 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1640 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1641 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1642
1643 /* Workaround: clear timing override bit. */
1644 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1645 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1646 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1647}
1648
b24e7179 1649/**
309cfea8 1650 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1651 * @dev_priv: i915 private structure
1652 * @pipe: pipe to enable
040484af 1653 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1654 *
1655 * Enable @pipe, making sure that various hardware specific requirements
1656 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1657 *
1658 * @pipe should be %PIPE_A or %PIPE_B.
1659 *
1660 * Will wait until the pipe is actually running (i.e. first vblank) before
1661 * returning.
1662 */
040484af
JB		 1663static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1664 bool pch_port)
b24e7179 1665{
702e7a56
PZ		 1666 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1667 pipe);
1a240d4d 1668 enum pipe pch_transcoder;
b24e7179
JB		 1669 int reg;
1670 u32 val;
1671
58c6eaa2
DV		 1672 assert_planes_disabled(dev_priv, pipe);
1673 assert_sprites_disabled(dev_priv, pipe);
1674
681e5811 1675 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1676 pch_transcoder = TRANSCODER_A;
1677 else
1678 pch_transcoder = pipe;
1679
b24e7179
JB		 1680 /*
1681 * A pipe without a PLL won't actually be able to drive bits from
1682 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1683 * need the check.
1684 */
1685 if (!HAS_PCH_SPLIT(dev_priv->dev))
1686 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1687 else {
1688 if (pch_port) {
1689 /* if driving the PCH, we need FDI enabled */
cc391bbb 1690 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1691 assert_fdi_tx_pll_enabled(dev_priv,
1692 (enum pipe) cpu_transcoder);
040484af
JB		 1693 }
1694 /* FIXME: assert CPU port conditions for SNB+ */
1695 }
b24e7179 1696
702e7a56 1697 reg = PIPECONF(cpu_transcoder);
b24e7179 1698 val = I915_READ(reg);
00d70b15
CW		 1699 if (val & PIPECONF_ENABLE)
1700 return;
1701
1702 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1703 intel_wait_for_vblank(dev_priv->dev, pipe);
1704}
1705
1706/**
309cfea8 1707 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1708 * @dev_priv: i915 private structure
1709 * @pipe: pipe to disable
1710 *
1711 * Disable @pipe, making sure that various hardware specific requirements
1712 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1713 *
1714 * @pipe should be %PIPE_A or %PIPE_B.
1715 *
1716 * Will wait until the pipe has shut down before returning.
1717 */
1718static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1719 enum pipe pipe)
1720{
702e7a56
PZ		 1721 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1722 pipe);
b24e7179
JB		 1723 int reg;
1724 u32 val;
1725
1726 /*
1727 * Make sure planes won't keep trying to pump pixels to us,
1728 * or we might hang the display.
1729 */
1730 assert_planes_disabled(dev_priv, pipe);
19332d7a 1731 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1732
1733 /* Don't disable pipe A or pipe A PLLs if needed */
1734 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1735 return;
1736
702e7a56 1737 reg = PIPECONF(cpu_transcoder);
b24e7179 1738 val = I915_READ(reg);
00d70b15
CW		 1739 if ((val & PIPECONF_ENABLE) == 0)
1740 return;
1741
1742 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1743 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1744}
1745
d74362c9
KP		 1746/*
1747 * Plane regs are double buffered, going from enabled->disabled needs a
1748 * trigger in order to latch. The display address reg provides this.
1749 */
6f1d69b0 1750void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1751 enum plane plane)
1752{
14f86147
DL		 1753 if (dev_priv->info->gen >= 4)
1754 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1755 else
1756 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1757}
1758
b24e7179
JB		 1759/**
1760 * intel_enable_plane - enable a display plane on a given pipe
1761 * @dev_priv: i915 private structure
1762 * @plane: plane to enable
1763 * @pipe: pipe being fed
1764 *
1765 * Enable @plane on @pipe, making sure that @pipe is running first.
1766 */
1767static void intel_enable_plane(struct drm_i915_private *dev_priv,
1768 enum plane plane, enum pipe pipe)
1769{
1770 int reg;
1771 u32 val;
1772
1773 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1774 assert_pipe_enabled(dev_priv, pipe);
1775
1776 reg = DSPCNTR(plane);
1777 val = I915_READ(reg);
00d70b15
CW		 1778 if (val & DISPLAY_PLANE_ENABLE)
1779 return;
1780
1781 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1782 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1783 intel_wait_for_vblank(dev_priv->dev, pipe);
1784}
1785
b24e7179
JB		 1786/**
1787 * intel_disable_plane - disable a display plane
1788 * @dev_priv: i915 private structure
1789 * @plane: plane to disable
1790 * @pipe: pipe consuming the data
1791 *
1792 * Disable @plane; should be an independent operation.
1793 */
1794static void intel_disable_plane(struct drm_i915_private *dev_priv,
1795 enum plane plane, enum pipe pipe)
1796{
1797 int reg;
1798 u32 val;
1799
1800 reg = DSPCNTR(plane);
1801 val = I915_READ(reg);
00d70b15
CW		 1802 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1803 return;
1804
1805 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1806 intel_flush_display_plane(dev_priv, plane);
1807 intel_wait_for_vblank(dev_priv->dev, pipe);
1808}
1809
693db184
CW		 1810static bool need_vtd_wa(struct drm_device *dev)
1811{
1812#ifdef CONFIG_INTEL_IOMMU
1813 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1814 return true;
1815#endif
1816 return false;
1817}
1818
127bd2ac 1819int
48b956c5 1820intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1821 struct drm_i915_gem_object *obj,
919926ae 1822 struct intel_ring_buffer *pipelined)
6b95a207 1823{
ce453d81 1824 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1825 u32 alignment;
1826 int ret;
1827
05394f39 1828 switch (obj->tiling_mode) {
6b95a207 1829 case I915_TILING_NONE:
534843da
CW		 1830 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1831 alignment = 128 * 1024;
a6c45cf0 1832 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1833 alignment = 4 * 1024;
1834 else
1835 alignment = 64 * 1024;
6b95a207
KH		 1836 break;
1837 case I915_TILING_X:
1838 /* pin() will align the object as required by fence */
1839 alignment = 0;
1840 break;
1841 case I915_TILING_Y:
8bb6e959
DV		 1842 /* Despite that we check this in framebuffer_init userspace can
1843 * screw us over and change the tiling after the fact. Only
1844 * pinned buffers can't change their tiling. */
1845 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1846 return -EINVAL;
1847 default:
1848 BUG();
1849 }
1850
693db184
CW		 1851 /* Note that the w/a also requires 64 PTE of padding following the
1852 * bo. We currently fill all unused PTE with the shadow page and so
1853 * we should always have valid PTE following the scanout preventing
1854 * the VT-d warning.
1855 */
1856 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1857 alignment = 256 * 1024;
1858
ce453d81 1859 dev_priv->mm.interruptible = false;
2da3b9b9 1860 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1861 if (ret)
ce453d81 1862 goto err_interruptible;
6b95a207
KH		 1863
1864 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1865 * fence, whereas 965+ only requires a fence if using
1866 * framebuffer compression. For simplicity, we always install
1867 * a fence as the cost is not that onerous.
1868 */
06d98131 1869 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1870 if (ret)
1871 goto err_unpin;
1690e1eb 1872
9a5a53b3 1873 i915_gem_object_pin_fence(obj);
6b95a207 1874
ce453d81 1875 dev_priv->mm.interruptible = true;
6b95a207 1876 return 0;
48b956c5
CW		 1877
1878err_unpin:
cc98b413 1879 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1880err_interruptible:
1881 dev_priv->mm.interruptible = true;
48b956c5 1882 return ret;
6b95a207
KH		 1883}
1884
1690e1eb
CW		 1885void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1886{
1887 i915_gem_object_unpin_fence(obj);
cc98b413 1888 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1889}
1890
c2c75131
DV		 1891/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1892 * is assumed to be a power-of-two. */
bc752862
CW		 1893unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1894 unsigned int tiling_mode,
1895 unsigned int cpp,
1896 unsigned int pitch)
c2c75131 1897{
bc752862
CW		 1898 if (tiling_mode != I915_TILING_NONE) {
1899 unsigned int tile_rows, tiles;
c2c75131 1900
bc752862
CW		 1901 tile_rows = *y / 8;
1902 *y %= 8;
c2c75131 1903
bc752862
CW		 1904 tiles = *x / (512/cpp);
1905 *x %= 512/cpp;
1906
1907 return tile_rows * pitch * 8 + tiles * 4096;
1908 } else {
1909 unsigned int offset;
1910
1911 offset = *y * pitch + *x * cpp;
1912 *y = 0;
1913 *x = (offset & 4095) / cpp;
1914 return offset & -4096;
1915 }
c2c75131
DV		 1916}
1917
17638cd6
JB		 1918static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1919 int x, int y)
81255565
JB		 1920{
1921 struct drm_device *dev = crtc->dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1924 struct intel_framebuffer *intel_fb;
05394f39 1925 struct drm_i915_gem_object *obj;
81255565 1926 int plane = intel_crtc->plane;
e506a0c6 1927 unsigned long linear_offset;
81255565 1928 u32 dspcntr;
5eddb70b 1929 u32 reg;
81255565
JB		 1930
1931 switch (plane) {
1932 case 0:
1933 case 1:
1934 break;
1935 default:
84f44ce7 1936 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1937 return -EINVAL;
1938 }
1939
1940 intel_fb = to_intel_framebuffer(fb);
1941 obj = intel_fb->obj;
81255565 1942
5eddb70b
CW		 1943 reg = DSPCNTR(plane);
1944 dspcntr = I915_READ(reg);
81255565
JB		 1945 /* Mask out pixel format bits in case we change it */
1946 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1947 switch (fb->pixel_format) {
1948 case DRM_FORMAT_C8:
81255565
JB		 1949 dspcntr |= DISPPLANE_8BPP;
1950 break;
57779d06
VS		 1951 case DRM_FORMAT_XRGB1555:
1952 case DRM_FORMAT_ARGB1555:
1953 dspcntr |= DISPPLANE_BGRX555;
81255565 1954 break;
57779d06
VS		 1955 case DRM_FORMAT_RGB565:
1956 dspcntr |= DISPPLANE_BGRX565;
1957 break;
1958 case DRM_FORMAT_XRGB8888:
1959 case DRM_FORMAT_ARGB8888:
1960 dspcntr |= DISPPLANE_BGRX888;
1961 break;
1962 case DRM_FORMAT_XBGR8888:
1963 case DRM_FORMAT_ABGR8888:
1964 dspcntr |= DISPPLANE_RGBX888;
1965 break;
1966 case DRM_FORMAT_XRGB2101010:
1967 case DRM_FORMAT_ARGB2101010:
1968 dspcntr |= DISPPLANE_BGRX101010;
1969 break;
1970 case DRM_FORMAT_XBGR2101010:
1971 case DRM_FORMAT_ABGR2101010:
1972 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1973 break;
1974 default:
baba133a 1975 BUG();
81255565 1976 }
57779d06 1977
a6c45cf0 1978 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1979 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1980 dspcntr |= DISPPLANE_TILED;
1981 else
1982 dspcntr &= ~DISPPLANE_TILED;
1983 }
1984
de1aa629
VS		 1985 if (IS_G4X(dev))
1986 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1987
5eddb70b 1988 I915_WRITE(reg, dspcntr);
81255565 1989
e506a0c6 1990 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1991
c2c75131
DV		 1992 if (INTEL_INFO(dev)->gen >= 4) {
1993 intel_crtc->dspaddr_offset =
bc752862
CW		 1994 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1995 fb->bits_per_pixel / 8,
1996 fb->pitches[0]);
c2c75131
DV		 1997 linear_offset -= intel_crtc->dspaddr_offset;
1998 } else {
e506a0c6 1999 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2000 }
e506a0c6 2001
f343c5f6
BW		 2002 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2003 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2004 fb->pitches[0]);
01f2c773 2005 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2006 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2007 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2008 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2009 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2010 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2011 } else
f343c5f6 2012 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2013 POSTING_READ(reg);
81255565 2014
17638cd6
JB		 2015 return 0;
2016}
2017
2018static int ironlake_update_plane(struct drm_crtc *crtc,
2019 struct drm_framebuffer *fb, int x, int y)
2020{
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
2025 struct drm_i915_gem_object *obj;
2026 int plane = intel_crtc->plane;
e506a0c6 2027 unsigned long linear_offset;
17638cd6
JB		 2028 u32 dspcntr;
2029 u32 reg;
2030
2031 switch (plane) {
2032 case 0:
2033 case 1:
27f8227b 2034 case 2:
17638cd6
JB		 2035 break;
2036 default:
84f44ce7 2037 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2038 return -EINVAL;
2039 }
2040
2041 intel_fb = to_intel_framebuffer(fb);
2042 obj = intel_fb->obj;
2043
2044 reg = DSPCNTR(plane);
2045 dspcntr = I915_READ(reg);
2046 /* Mask out pixel format bits in case we change it */
2047 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2048 switch (fb->pixel_format) {
2049 case DRM_FORMAT_C8:
17638cd6
JB		 2050 dspcntr |= DISPPLANE_8BPP;
2051 break;
57779d06
VS		 2052 case DRM_FORMAT_RGB565:
2053 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2054 break;
57779d06
VS		 2055 case DRM_FORMAT_XRGB8888:
2056 case DRM_FORMAT_ARGB8888:
2057 dspcntr |= DISPPLANE_BGRX888;
2058 break;
2059 case DRM_FORMAT_XBGR8888:
2060 case DRM_FORMAT_ABGR8888:
2061 dspcntr |= DISPPLANE_RGBX888;
2062 break;
2063 case DRM_FORMAT_XRGB2101010:
2064 case DRM_FORMAT_ARGB2101010:
2065 dspcntr |= DISPPLANE_BGRX101010;
2066 break;
2067 case DRM_FORMAT_XBGR2101010:
2068 case DRM_FORMAT_ABGR2101010:
2069 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2070 break;
2071 default:
baba133a 2072 BUG();
17638cd6
JB		 2073 }
2074
2075 if (obj->tiling_mode != I915_TILING_NONE)
2076 dspcntr |= DISPPLANE_TILED;
2077 else
2078 dspcntr &= ~DISPPLANE_TILED;
2079
1f5d76db
PZ		 2080 if (IS_HASWELL(dev))
2081 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2082 else
2083 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2084
2085 I915_WRITE(reg, dspcntr);
2086
e506a0c6 2087 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2088 intel_crtc->dspaddr_offset =
bc752862
CW		 2089 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2090 fb->bits_per_pixel / 8,
2091 fb->pitches[0]);
c2c75131 2092 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2093
f343c5f6
BW		 2094 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2095 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2096 fb->pitches[0]);
01f2c773 2097 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2098 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2099 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2100 if (IS_HASWELL(dev)) {
2101 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2102 } else {
2103 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2104 I915_WRITE(DSPLINOFF(plane), linear_offset);
2105 }
17638cd6
JB		 2106 POSTING_READ(reg);
2107
2108 return 0;
2109}
2110
2111/* Assume fb object is pinned & idle & fenced and just update base pointers */
2112static int
2113intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2114 int x, int y, enum mode_set_atomic state)
2115{
2116 struct drm_device *dev = crtc->dev;
2117 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2118
6b8e6ed0
CW		 2119 if (dev_priv->display.disable_fbc)
2120 dev_priv->display.disable_fbc(dev);
3dec0095 2121 intel_increase_pllclock(crtc);
81255565 2122
6b8e6ed0 2123 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2124}
2125
96a02917
VS		 2126void intel_display_handle_reset(struct drm_device *dev)
2127{
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 struct drm_crtc *crtc;
2130
2131 /*
2132 * Flips in the rings have been nuked by the reset,
2133 * so complete all pending flips so that user space
2134 * will get its events and not get stuck.
2135 *
2136 * Also update the base address of all primary
2137 * planes to the the last fb to make sure we're
2138 * showing the correct fb after a reset.
2139 *
2140 * Need to make two loops over the crtcs so that we
2141 * don't try to grab a crtc mutex before the
2142 * pending_flip_queue really got woken up.
2143 */
2144
2145 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2147 enum plane plane = intel_crtc->plane;
2148
2149 intel_prepare_page_flip(dev, plane);
2150 intel_finish_page_flip_plane(dev, plane);
2151 }
2152
2153 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2155
2156 mutex_lock(&crtc->mutex);
2157 if (intel_crtc->active)
2158 dev_priv->display.update_plane(crtc, crtc->fb,
2159 crtc->x, crtc->y);
2160 mutex_unlock(&crtc->mutex);
2161 }
2162}
2163
14667a4b
CW		 2164static int
2165intel_finish_fb(struct drm_framebuffer *old_fb)
2166{
2167 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2168 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2169 bool was_interruptible = dev_priv->mm.interruptible;
2170 int ret;
2171
14667a4b
CW		 2172 /* Big Hammer, we also need to ensure that any pending
2173 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2174 * current scanout is retired before unpinning the old
2175 * framebuffer.
2176 *
2177 * This should only fail upon a hung GPU, in which case we
2178 * can safely continue.
2179 */
2180 dev_priv->mm.interruptible = false;
2181 ret = i915_gem_object_finish_gpu(obj);
2182 dev_priv->mm.interruptible = was_interruptible;
2183
2184 return ret;
2185}
2186
198598d0
VS		 2187static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2188{
2189 struct drm_device *dev = crtc->dev;
2190 struct drm_i915_master_private *master_priv;
2191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2192
2193 if (!dev->primary->master)
2194 return;
2195
2196 master_priv = dev->primary->master->driver_priv;
2197 if (!master_priv->sarea_priv)
2198 return;
2199
2200 switch (intel_crtc->pipe) {
2201 case 0:
2202 master_priv->sarea_priv->pipeA_x = x;
2203 master_priv->sarea_priv->pipeA_y = y;
2204 break;
2205 case 1:
2206 master_priv->sarea_priv->pipeB_x = x;
2207 master_priv->sarea_priv->pipeB_y = y;
2208 break;
2209 default:
2210 break;
2211 }
2212}
2213
5c3b82e2 2214static int
3c4fdcfb 2215intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2216 struct drm_framebuffer *fb)
79e53945
JB		 2217{
2218 struct drm_device *dev = crtc->dev;
6b8e6ed0 2219 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2221 struct drm_framebuffer *old_fb;
5c3b82e2 2222 int ret;
79e53945
JB		 2223
2224 /* no fb bound */
94352cf9 2225 if (!fb) {
a5071c2f 2226 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2227 return 0;
2228 }
2229
7eb552ae 2230 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2231 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2232 plane_name(intel_crtc->plane),
2233 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2234 return -EINVAL;
79e53945
JB		 2235 }
2236
5c3b82e2 2237 mutex_lock(&dev->struct_mutex);
265db958 2238 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2239 to_intel_framebuffer(fb)->obj,
919926ae 2240 NULL);
5c3b82e2
CW		 2241 if (ret != 0) {
2242 mutex_unlock(&dev->struct_mutex);
a5071c2f 2243 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2244 return ret;
2245 }
79e53945 2246
4d6a3e63
JB		 2247 /* Update pipe size and adjust fitter if needed */
2248 if (i915_fastboot) {
2249 I915_WRITE(PIPESRC(intel_crtc->pipe),
2250 ((crtc->mode.hdisplay - 1) << 16) |
2251 (crtc->mode.vdisplay - 1));
fd4daa9c 2252 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2253 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2254 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2255 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2256 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2257 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2258 }
2259 }
2260
94352cf9 2261 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2262 if (ret) {
94352cf9 2263 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2264 mutex_unlock(&dev->struct_mutex);
a5071c2f 2265 DRM_ERROR("failed to update base address\n");
4e6cfefc 2266 return ret;
79e53945 2267 }
3c4fdcfb 2268
94352cf9
DV		 2269 old_fb = crtc->fb;
2270 crtc->fb = fb;
6c4c86f5
DV		 2271 crtc->x = x;
2272 crtc->y = y;
94352cf9 2273
b7f1de28 2274 if (old_fb) {
d7697eea
DV		 2275 if (intel_crtc->active && old_fb != fb)
2276 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2277 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2278 }
652c393a 2279
6b8e6ed0 2280 intel_update_fbc(dev);
4906557e 2281 intel_edp_psr_update(dev);
5c3b82e2 2282 mutex_unlock(&dev->struct_mutex);
79e53945 2283
198598d0 2284 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2285
2286 return 0;
79e53945
JB		 2287}
2288
5e84e1a4
ZW		 2289static void intel_fdi_normal_train(struct drm_crtc *crtc)
2290{
2291 struct drm_device *dev = crtc->dev;
2292 struct drm_i915_private *dev_priv = dev->dev_private;
2293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2294 int pipe = intel_crtc->pipe;
2295 u32 reg, temp;
2296
2297 /* enable normal train */
2298 reg = FDI_TX_CTL(pipe);
2299 temp = I915_READ(reg);
61e499bf 2300 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2301 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2302 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2303 } else {
2304 temp &= ~FDI_LINK_TRAIN_NONE;
2305 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2306 }
5e84e1a4
ZW		 2307 I915_WRITE(reg, temp);
2308
2309 reg = FDI_RX_CTL(pipe);
2310 temp = I915_READ(reg);
2311 if (HAS_PCH_CPT(dev)) {
2312 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2313 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2314 } else {
2315 temp &= ~FDI_LINK_TRAIN_NONE;
2316 temp |= FDI_LINK_TRAIN_NONE;
2317 }
2318 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2319
2320 /* wait one idle pattern time */
2321 POSTING_READ(reg);
2322 udelay(1000);
357555c0
JB		 2323
2324 /* IVB wants error correction enabled */
2325 if (IS_IVYBRIDGE(dev))
2326 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2327 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2328}
2329
1e833f40
DV		 2330static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2331{
2332 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2333}
2334
01a415fd
DV		 2335static void ivb_modeset_global_resources(struct drm_device *dev)
2336{
2337 struct drm_i915_private *dev_priv = dev->dev_private;
2338 struct intel_crtc *pipe_B_crtc =
2339 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2340 struct intel_crtc *pipe_C_crtc =
2341 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2342 uint32_t temp;
2343
1e833f40
DV		 2344 /*
2345 * When everything is off disable fdi C so that we could enable fdi B
2346 * with all lanes. Note that we don't care about enabled pipes without
2347 * an enabled pch encoder.
2348 */
2349 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2350 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2351 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2352 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2353
2354 temp = I915_READ(SOUTH_CHICKEN1);
2355 temp &= ~FDI_BC_BIFURCATION_SELECT;
2356 DRM_DEBUG_KMS("disabling fdi C rx\n");
2357 I915_WRITE(SOUTH_CHICKEN1, temp);
2358 }
2359}
2360
8db9d77b
ZW		 2361/* The FDI link training functions for ILK/Ibexpeak. */
2362static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2363{
2364 struct drm_device *dev = crtc->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2367 int pipe = intel_crtc->pipe;
0fc932b8 2368 int plane = intel_crtc->plane;
5eddb70b 2369 u32 reg, temp, tries;
8db9d77b 2370
0fc932b8
JB		 2371 /* FDI needs bits from pipe & plane first */
2372 assert_pipe_enabled(dev_priv, pipe);
2373 assert_plane_enabled(dev_priv, plane);
2374
e1a44743
AJ		 2375 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2376 for train result */
5eddb70b
CW		 2377 reg = FDI_RX_IMR(pipe);
2378 temp = I915_READ(reg);
e1a44743
AJ		 2379 temp &= ~FDI_RX_SYMBOL_LOCK;
2380 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2381 I915_WRITE(reg, temp);
2382 I915_READ(reg);
e1a44743
AJ		 2383 udelay(150);
2384
8db9d77b 2385 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2386 reg = FDI_TX_CTL(pipe);
2387 temp = I915_READ(reg);
627eb5a3
DV		 2388 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2389 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2390 temp &= ~FDI_LINK_TRAIN_NONE;
2391 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2392 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2393
5eddb70b
CW		 2394 reg = FDI_RX_CTL(pipe);
2395 temp = I915_READ(reg);
8db9d77b
ZW		 2396 temp &= ~FDI_LINK_TRAIN_NONE;
2397 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2398 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2399
2400 POSTING_READ(reg);
8db9d77b
ZW		 2401 udelay(150);
2402
5b2adf89 2403 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2404 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2405 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2406 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2407
5eddb70b 2408 reg = FDI_RX_IIR(pipe);
e1a44743 2409 for (tries = 0; tries < 5; tries++) {
5eddb70b 2410 temp = I915_READ(reg);
8db9d77b
ZW		 2411 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2412
2413 if ((temp & FDI_RX_BIT_LOCK)) {
2414 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2415 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2416 break;
2417 }
8db9d77b 2418 }
e1a44743 2419 if (tries == 5)
5eddb70b 2420 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2421
2422 /* Train 2 */
5eddb70b
CW		 2423 reg = FDI_TX_CTL(pipe);
2424 temp = I915_READ(reg);
8db9d77b
ZW		 2425 temp &= ~FDI_LINK_TRAIN_NONE;
2426 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2427 I915_WRITE(reg, temp);
8db9d77b 2428
5eddb70b
CW		 2429 reg = FDI_RX_CTL(pipe);
2430 temp = I915_READ(reg);
8db9d77b
ZW		 2431 temp &= ~FDI_LINK_TRAIN_NONE;
2432 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2433 I915_WRITE(reg, temp);
8db9d77b 2434
5eddb70b
CW		 2435 POSTING_READ(reg);
2436 udelay(150);
8db9d77b 2437
5eddb70b 2438 reg = FDI_RX_IIR(pipe);
e1a44743 2439 for (tries = 0; tries < 5; tries++) {
5eddb70b 2440 temp = I915_READ(reg);
8db9d77b
ZW		 2441 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2442
2443 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2444 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2445 DRM_DEBUG_KMS("FDI train 2 done.\n");
2446 break;
2447 }
8db9d77b 2448 }
e1a44743 2449 if (tries == 5)
5eddb70b 2450 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2451
2452 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2453
8db9d77b
ZW		 2454}
2455
0206e353 2456static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2457 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2458 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2459 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2460 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2461};
2462
2463/* The FDI link training functions for SNB/Cougarpoint. */
2464static void gen6_fdi_link_train(struct drm_crtc *crtc)
2465{
2466 struct drm_device *dev = crtc->dev;
2467 struct drm_i915_private *dev_priv = dev->dev_private;
2468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2469 int pipe = intel_crtc->pipe;
fa37d39e 2470 u32 reg, temp, i, retry;
8db9d77b 2471
e1a44743
AJ		 2472 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2473 for train result */
5eddb70b
CW		 2474 reg = FDI_RX_IMR(pipe);
2475 temp = I915_READ(reg);
e1a44743
AJ		 2476 temp &= ~FDI_RX_SYMBOL_LOCK;
2477 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2478 I915_WRITE(reg, temp);
2479
2480 POSTING_READ(reg);
e1a44743
AJ		 2481 udelay(150);
2482
8db9d77b 2483 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2484 reg = FDI_TX_CTL(pipe);
2485 temp = I915_READ(reg);
627eb5a3
DV		 2486 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2487 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_1;
2490 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2491 /* SNB-B */
2492 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2493 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2494
d74cf324
DV		 2495 I915_WRITE(FDI_RX_MISC(pipe),
2496 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2497
5eddb70b
CW		 2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
8db9d77b
ZW		 2500 if (HAS_PCH_CPT(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503 } else {
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 }
5eddb70b
CW		 2507 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509 POSTING_READ(reg);
8db9d77b
ZW		 2510 udelay(150);
2511
0206e353 2512 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2513 reg = FDI_TX_CTL(pipe);
2514 temp = I915_READ(reg);
8db9d77b
ZW		 2515 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2516 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2517 I915_WRITE(reg, temp);
2518
2519 POSTING_READ(reg);
8db9d77b
ZW		 2520 udelay(500);
2521
fa37d39e
SP		 2522 for (retry = 0; retry < 5; retry++) {
2523 reg = FDI_RX_IIR(pipe);
2524 temp = I915_READ(reg);
2525 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2526 if (temp & FDI_RX_BIT_LOCK) {
2527 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2528 DRM_DEBUG_KMS("FDI train 1 done.\n");
2529 break;
2530 }
2531 udelay(50);
8db9d77b 2532 }
fa37d39e
SP		 2533 if (retry < 5)
2534 break;
8db9d77b
ZW		 2535 }
2536 if (i == 4)
5eddb70b 2537 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2538
2539 /* Train 2 */
5eddb70b
CW		 2540 reg = FDI_TX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 temp &= ~FDI_LINK_TRAIN_NONE;
2543 temp |= FDI_LINK_TRAIN_PATTERN_2;
2544 if (IS_GEN6(dev)) {
2545 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2546 /* SNB-B */
2547 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2548 }
5eddb70b 2549 I915_WRITE(reg, temp);
8db9d77b 2550
5eddb70b
CW		 2551 reg = FDI_RX_CTL(pipe);
2552 temp = I915_READ(reg);
8db9d77b
ZW		 2553 if (HAS_PCH_CPT(dev)) {
2554 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2555 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2556 } else {
2557 temp &= ~FDI_LINK_TRAIN_NONE;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2;
2559 }
5eddb70b
CW		 2560 I915_WRITE(reg, temp);
2561
2562 POSTING_READ(reg);
8db9d77b
ZW		 2563 udelay(150);
2564
0206e353 2565 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2566 reg = FDI_TX_CTL(pipe);
2567 temp = I915_READ(reg);
8db9d77b
ZW		 2568 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2569 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2570 I915_WRITE(reg, temp);
2571
2572 POSTING_READ(reg);
8db9d77b
ZW		 2573 udelay(500);
2574
fa37d39e
SP		 2575 for (retry = 0; retry < 5; retry++) {
2576 reg = FDI_RX_IIR(pipe);
2577 temp = I915_READ(reg);
2578 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2579 if (temp & FDI_RX_SYMBOL_LOCK) {
2580 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2581 DRM_DEBUG_KMS("FDI train 2 done.\n");
2582 break;
2583 }
2584 udelay(50);
8db9d77b 2585 }
fa37d39e
SP		 2586 if (retry < 5)
2587 break;
8db9d77b
ZW		 2588 }
2589 if (i == 4)
5eddb70b 2590 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2591
2592 DRM_DEBUG_KMS("FDI train done.\n");
2593}
2594
357555c0
JB		 2595/* Manual link training for Ivy Bridge A0 parts */
2596static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2597{
2598 struct drm_device *dev = crtc->dev;
2599 struct drm_i915_private *dev_priv = dev->dev_private;
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 int pipe = intel_crtc->pipe;
139ccd3f 2602 u32 reg, temp, i, j;
357555c0
JB		 2603
2604 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2605 for train result */
2606 reg = FDI_RX_IMR(pipe);
2607 temp = I915_READ(reg);
2608 temp &= ~FDI_RX_SYMBOL_LOCK;
2609 temp &= ~FDI_RX_BIT_LOCK;
2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
2613 udelay(150);
2614
01a415fd
DV		 2615 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2616 I915_READ(FDI_RX_IIR(pipe)));
2617
139ccd3f
JB		 2618 /* Try each vswing and preemphasis setting twice before moving on */
2619 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2620 /* disable first in case we need to retry */
2621 reg = FDI_TX_CTL(pipe);
2622 temp = I915_READ(reg);
2623 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624 temp &= ~FDI_TX_ENABLE;
2625 I915_WRITE(reg, temp);
357555c0 2626
139ccd3f
JB		 2627 reg = FDI_RX_CTL(pipe);
2628 temp = I915_READ(reg);
2629 temp &= ~FDI_LINK_TRAIN_AUTO;
2630 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2631 temp &= ~FDI_RX_ENABLE;
2632 I915_WRITE(reg, temp);
357555c0 2633
139ccd3f 2634 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2635 reg = FDI_TX_CTL(pipe);
2636 temp = I915_READ(reg);
139ccd3f
JB		 2637 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2638 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2639 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2640 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2641 temp |= snb_b_fdi_train_param[j/2];
2642 temp |= FDI_COMPOSITE_SYNC;
2643 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2644
139ccd3f
JB		 2645 I915_WRITE(FDI_RX_MISC(pipe),
2646 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2647
139ccd3f 2648 reg = FDI_RX_CTL(pipe);
357555c0 2649 temp = I915_READ(reg);
139ccd3f
JB		 2650 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2651 temp |= FDI_COMPOSITE_SYNC;
2652 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2653
139ccd3f
JB		 2654 POSTING_READ(reg);
2655 udelay(1); /* should be 0.5us */
357555c0 2656
139ccd3f
JB		 2657 for (i = 0; i < 4; i++) {
2658 reg = FDI_RX_IIR(pipe);
2659 temp = I915_READ(reg);
2660 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2661
139ccd3f
JB		 2662 if (temp & FDI_RX_BIT_LOCK ||
2663 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2664 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2665 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2666 i);
2667 break;
2668 }
2669 udelay(1); /* should be 0.5us */
2670 }
2671 if (i == 4) {
2672 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2673 continue;
2674 }
357555c0 2675
139ccd3f 2676 /* Train 2 */
357555c0
JB		 2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
139ccd3f
JB		 2679 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2681 I915_WRITE(reg, temp);
2682
2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2686 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2687 I915_WRITE(reg, temp);
2688
2689 POSTING_READ(reg);
139ccd3f 2690 udelay(2); /* should be 1.5us */
357555c0 2691
139ccd3f
JB		 2692 for (i = 0; i < 4; i++) {
2693 reg = FDI_RX_IIR(pipe);
2694 temp = I915_READ(reg);
2695 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2696
139ccd3f
JB		 2697 if (temp & FDI_RX_SYMBOL_LOCK ||
2698 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2699 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2700 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2701 i);
2702 goto train_done;
2703 }
2704 udelay(2); /* should be 1.5us */
357555c0 2705 }
139ccd3f
JB		 2706 if (i == 4)
2707 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2708 }
357555c0 2709
139ccd3f 2710train_done:
357555c0
JB		 2711 DRM_DEBUG_KMS("FDI train done.\n");
2712}
2713
88cefb6c 2714static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2715{
88cefb6c 2716 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2717 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2718 int pipe = intel_crtc->pipe;
5eddb70b 2719 u32 reg, temp;
79e53945 2720
c64e311e 2721
c98e9dcf 2722 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2723 reg = FDI_RX_CTL(pipe);
2724 temp = I915_READ(reg);
627eb5a3
DV		 2725 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2726 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2727 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2728 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2729
2730 POSTING_READ(reg);
c98e9dcf
JB		 2731 udelay(200);
2732
2733 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2734 temp = I915_READ(reg);
2735 I915_WRITE(reg, temp | FDI_PCDCLK);
2736
2737 POSTING_READ(reg);
c98e9dcf
JB		 2738 udelay(200);
2739
20749730
PZ		 2740 /* Enable CPU FDI TX PLL, always on for Ironlake */
2741 reg = FDI_TX_CTL(pipe);
2742 temp = I915_READ(reg);
2743 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2744 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2745
20749730
PZ		 2746 POSTING_READ(reg);
2747 udelay(100);
6be4a607 2748 }
0e23b99d
JB		 2749}
2750
88cefb6c
DV		 2751static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2752{
2753 struct drm_device *dev = intel_crtc->base.dev;
2754 struct drm_i915_private *dev_priv = dev->dev_private;
2755 int pipe = intel_crtc->pipe;
2756 u32 reg, temp;
2757
2758 /* Switch from PCDclk to Rawclk */
2759 reg = FDI_RX_CTL(pipe);
2760 temp = I915_READ(reg);
2761 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2762
2763 /* Disable CPU FDI TX PLL */
2764 reg = FDI_TX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2767
2768 POSTING_READ(reg);
2769 udelay(100);
2770
2771 reg = FDI_RX_CTL(pipe);
2772 temp = I915_READ(reg);
2773 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2774
2775 /* Wait for the clocks to turn off. */
2776 POSTING_READ(reg);
2777 udelay(100);
2778}
2779
0fc932b8
JB		 2780static void ironlake_fdi_disable(struct drm_crtc *crtc)
2781{
2782 struct drm_device *dev = crtc->dev;
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2785 int pipe = intel_crtc->pipe;
2786 u32 reg, temp;
2787
2788 /* disable CPU FDI tx and PCH FDI rx */
2789 reg = FDI_TX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2792 POSTING_READ(reg);
2793
2794 reg = FDI_RX_CTL(pipe);
2795 temp = I915_READ(reg);
2796 temp &= ~(0x7 << 16);
dfd07d72 2797 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2798 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2799
2800 POSTING_READ(reg);
2801 udelay(100);
2802
2803 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2804 if (HAS_PCH_IBX(dev)) {
2805 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2806 }
0fc932b8
JB		 2807
2808 /* still set train pattern 1 */
2809 reg = FDI_TX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 temp &= ~FDI_LINK_TRAIN_NONE;
2812 temp |= FDI_LINK_TRAIN_PATTERN_1;
2813 I915_WRITE(reg, temp);
2814
2815 reg = FDI_RX_CTL(pipe);
2816 temp = I915_READ(reg);
2817 if (HAS_PCH_CPT(dev)) {
2818 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2820 } else {
2821 temp &= ~FDI_LINK_TRAIN_NONE;
2822 temp |= FDI_LINK_TRAIN_PATTERN_1;
2823 }
2824 /* BPC in FDI rx is consistent with that in PIPECONF */
2825 temp &= ~(0x07 << 16);
dfd07d72 2826 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2827 I915_WRITE(reg, temp);
2828
2829 POSTING_READ(reg);
2830 udelay(100);
2831}
2832
5bb61643
CW		 2833static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2834{
2835 struct drm_device *dev = crtc->dev;
2836 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2837 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2838 unsigned long flags;
2839 bool pending;
2840
10d83730
VS		 2841 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2842 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2843 return false;
2844
2845 spin_lock_irqsave(&dev->event_lock, flags);
2846 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2847 spin_unlock_irqrestore(&dev->event_lock, flags);
2848
2849 return pending;
2850}
2851
e6c3a2a6
CW		 2852static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2853{
0f91128d 2854 struct drm_device *dev = crtc->dev;
5bb61643 2855 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2856
2857 if (crtc->fb == NULL)
2858 return;
2859
2c10d571
DV		 2860 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2861
5bb61643
CW		 2862 wait_event(dev_priv->pending_flip_queue,
2863 !intel_crtc_has_pending_flip(crtc));
2864
0f91128d
CW		 2865 mutex_lock(&dev->struct_mutex);
2866 intel_finish_fb(crtc->fb);
2867 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2868}
2869
e615efe4
ED		 2870/* Program iCLKIP clock to the desired frequency */
2871static void lpt_program_iclkip(struct drm_crtc *crtc)
2872{
2873 struct drm_device *dev = crtc->dev;
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2876 u32 temp;
2877
09153000
DV		 2878 mutex_lock(&dev_priv->dpio_lock);
2879
e615efe4
ED		 2880 /* It is necessary to ungate the pixclk gate prior to programming
2881 * the divisors, and gate it back when it is done.
2882 */
2883 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2884
2885 /* Disable SSCCTL */
2886 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2887 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2888 SBI_SSCCTL_DISABLE,
2889 SBI_ICLK);
e615efe4
ED		 2890
2891 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2892 if (crtc->mode.clock == 20000) {
2893 auxdiv = 1;
2894 divsel = 0x41;
2895 phaseinc = 0x20;
2896 } else {
2897 /* The iCLK virtual clock root frequency is in MHz,
2898 * but the crtc->mode.clock in in KHz. To get the divisors,
2899 * it is necessary to divide one by another, so we
2900 * convert the virtual clock precision to KHz here for higher
2901 * precision.
2902 */
2903 u32 iclk_virtual_root_freq = 172800 * 1000;
2904 u32 iclk_pi_range = 64;
2905 u32 desired_divisor, msb_divisor_value, pi_value;
2906
2907 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2908 msb_divisor_value = desired_divisor / iclk_pi_range;
2909 pi_value = desired_divisor % iclk_pi_range;
2910
2911 auxdiv = 0;
2912 divsel = msb_divisor_value - 2;
2913 phaseinc = pi_value;
2914 }
2915
2916 /* This should not happen with any sane values */
2917 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2918 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2919 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2920 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2921
2922 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2923 crtc->mode.clock,
2924 auxdiv,
2925 divsel,
2926 phasedir,
2927 phaseinc);
2928
2929 /* Program SSCDIVINTPHASE6 */
988d6ee8 2930 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2931 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2932 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2933 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2934 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2935 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2936 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2937 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2938
2939 /* Program SSCAUXDIV */
988d6ee8 2940 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2941 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2942 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2943 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2944
2945 /* Enable modulator and associated divider */
988d6ee8 2946 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2947 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2948 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2949
2950 /* Wait for initialization time */
2951 udelay(24);
2952
2953 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2954
2955 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2956}
2957
275f01b2
DV		 2958static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2959 enum pipe pch_transcoder)
2960{
2961 struct drm_device *dev = crtc->base.dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2964
2965 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2966 I915_READ(HTOTAL(cpu_transcoder)));
2967 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2968 I915_READ(HBLANK(cpu_transcoder)));
2969 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2970 I915_READ(HSYNC(cpu_transcoder)));
2971
2972 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2973 I915_READ(VTOTAL(cpu_transcoder)));
2974 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2975 I915_READ(VBLANK(cpu_transcoder)));
2976 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2977 I915_READ(VSYNC(cpu_transcoder)));
2978 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2979 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2980}
2981
f67a559d
JB		 2982/*
2983 * Enable PCH resources required for PCH ports:
2984 * - PCH PLLs
2985 * - FDI training & RX/TX
2986 * - update transcoder timings
2987 * - DP transcoding bits
2988 * - transcoder
2989 */
2990static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2991{
2992 struct drm_device *dev = crtc->dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2995 int pipe = intel_crtc->pipe;
ee7b9f93 2996 u32 reg, temp;
2c07245f 2997
ab9412ba 2998 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2999
cd986abb
DV		 3000 /* Write the TU size bits before fdi link training, so that error
3001 * detection works. */
3002 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3003 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3004
c98e9dcf 3005 /* For PCH output, training FDI link */
674cf967 3006 dev_priv->display.fdi_link_train(crtc);
2c07245f 3007
3ad8a208
DV		 3008 /* We need to program the right clock selection before writing the pixel
3009 * mutliplier into the DPLL. */
303b81e0 3010 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3011 u32 sel;
4b645f14 3012
c98e9dcf 3013 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3014 temp |= TRANS_DPLL_ENABLE(pipe);
3015 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3016 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3017 temp |= sel;
3018 else
3019 temp &= ~sel;
c98e9dcf 3020 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3021 }
5eddb70b 3022
3ad8a208
DV		 3023 /* XXX: pch pll's can be enabled any time before we enable the PCH
3024 * transcoder, and we actually should do this to not upset any PCH
3025 * transcoder that already use the clock when we share it.
3026 *
3027 * Note that enable_shared_dpll tries to do the right thing, but
3028 * get_shared_dpll unconditionally resets the pll - we need that to have
3029 * the right LVDS enable sequence. */
3030 ironlake_enable_shared_dpll(intel_crtc);
3031
d9b6cb56
JB		 3032 /* set transcoder timing, panel must allow it */
3033 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3034 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3035
303b81e0 3036 intel_fdi_normal_train(crtc);
5e84e1a4 3037
c98e9dcf
JB		 3038 /* For PCH DP, enable TRANS_DP_CTL */
3039 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3040 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3041 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3042 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3043 reg = TRANS_DP_CTL(pipe);
3044 temp = I915_READ(reg);
3045 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3046 TRANS_DP_SYNC_MASK |
3047 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3048 temp |= (TRANS_DP_OUTPUT_ENABLE |
3049 TRANS_DP_ENH_FRAMING);
9325c9f0 3050 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3051
3052 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3053 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3054 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3055 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3056
3057 switch (intel_trans_dp_port_sel(crtc)) {
3058 case PCH_DP_B:
5eddb70b 3059 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3060 break;
3061 case PCH_DP_C:
5eddb70b 3062 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3063 break;
3064 case PCH_DP_D:
5eddb70b 3065 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3066 break;
3067 default:
e95d41e1 3068 BUG();
32f9d658 3069 }
2c07245f 3070
5eddb70b 3071 I915_WRITE(reg, temp);
6be4a607 3072 }
b52eb4dc 3073
b8a4f404 3074 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3075}
3076
1507e5bd
PZ		 3077static void lpt_pch_enable(struct drm_crtc *crtc)
3078{
3079 struct drm_device *dev = crtc->dev;
3080 struct drm_i915_private *dev_priv = dev->dev_private;
3081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3082 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3083
ab9412ba 3084 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3085
8c52b5e8 3086 lpt_program_iclkip(crtc);
1507e5bd 3087
0540e488 3088 /* Set transcoder timing. */
275f01b2 3089 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3090
937bb610 3091 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3092}
3093
e2b78267 3094static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3095{
e2b78267 3096 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3097
3098 if (pll == NULL)
3099 return;
3100
3101 if (pll->refcount == 0) {
46edb027 3102 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3103 return;
3104 }
3105
f4a091c7
DV		 3106 if (--pll->refcount == 0) {
3107 WARN_ON(pll->on);
3108 WARN_ON(pll->active);
3109 }
3110
a43f6e0f 3111 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3112}
3113
b89a1d39 3114static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3115{
e2b78267
DV		 3116 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3117 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3118 enum intel_dpll_id i;
ee7b9f93 3119
ee7b9f93 3120 if (pll) {
46edb027
DV		 3121 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3122 crtc->base.base.id, pll->name);
e2b78267 3123 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3124 }
3125
98b6bd99
DV		 3126 if (HAS_PCH_IBX(dev_priv->dev)) {
3127 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3128 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3129 pll = &dev_priv->shared_dplls[i];
98b6bd99 3130
46edb027
DV		 3131 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3132 crtc->base.base.id, pll->name);
98b6bd99
DV		 3133
3134 goto found;
3135 }
3136
e72f9fbf
DV		 3137 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3138 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3139
3140 /* Only want to check enabled timings first */
3141 if (pll->refcount == 0)
3142 continue;
3143
b89a1d39
DV		 3144 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3145 sizeof(pll->hw_state)) == 0) {
46edb027 3146 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3147 crtc->base.base.id,
46edb027 3148 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3149
3150 goto found;
3151 }
3152 }
3153
3154 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3155 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3156 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3157 if (pll->refcount == 0) {
46edb027
DV		 3158 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3159 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3160 goto found;
3161 }
3162 }
3163
3164 return NULL;
3165
3166found:
a43f6e0f 3167 crtc->config.shared_dpll = i;
46edb027
DV		 3168 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3169 pipe_name(crtc->pipe));
ee7b9f93 3170
cdbd2316 3171 if (pll->active == 0) {
66e985c0
DV		 3172 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3173 sizeof(pll->hw_state));
3174
46edb027 3175 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3176 WARN_ON(pll->on);
e9d6944e 3177 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3178
15bdd4cf 3179 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3180 }
3181 pll->refcount++;
e04c7350 3182
ee7b9f93
JB		 3183 return pll;
3184}
3185
a1520318 3186static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3187{
3188 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3189 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3190 u32 temp;
3191
3192 temp = I915_READ(dslreg);
3193 udelay(500);
3194 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3195 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3196 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3197 }
3198}
3199
b074cec8
JB		 3200static void ironlake_pfit_enable(struct intel_crtc *crtc)
3201{
3202 struct drm_device *dev = crtc->base.dev;
3203 struct drm_i915_private *dev_priv = dev->dev_private;
3204 int pipe = crtc->pipe;
3205
fd4daa9c 3206 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3207 /* Force use of hard-coded filter coefficients
3208 * as some pre-programmed values are broken,
3209 * e.g. x201.
3210 */
3211 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3212 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3213 PF_PIPE_SEL_IVB(pipe));
3214 else
3215 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3216 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3217 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3218 }
3219}
3220
bb53d4ae
VS		 3221static void intel_enable_planes(struct drm_crtc *crtc)
3222{
3223 struct drm_device *dev = crtc->dev;
3224 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3225 struct intel_plane *intel_plane;
3226
3227 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3228 if (intel_plane->pipe == pipe)
3229 intel_plane_restore(&intel_plane->base);
3230}
3231
3232static void intel_disable_planes(struct drm_crtc *crtc)
3233{
3234 struct drm_device *dev = crtc->dev;
3235 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3236 struct intel_plane *intel_plane;
3237
3238 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3239 if (intel_plane->pipe == pipe)
3240 intel_plane_disable(&intel_plane->base);
3241}
3242
f67a559d
JB		 3243static void ironlake_crtc_enable(struct drm_crtc *crtc)
3244{
3245 struct drm_device *dev = crtc->dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3248 struct intel_encoder *encoder;
f67a559d
JB		 3249 int pipe = intel_crtc->pipe;
3250 int plane = intel_crtc->plane;
f67a559d 3251
08a48469
DV		 3252 WARN_ON(!crtc->enabled);
3253
f67a559d
JB		 3254 if (intel_crtc->active)
3255 return;
3256
3257 intel_crtc->active = true;
8664281b
PZ		 3258
3259 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3260 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3261
f67a559d
JB		 3262 intel_update_watermarks(dev);
3263
f6736a1a 3264 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3265 if (encoder->pre_enable)
3266 encoder->pre_enable(encoder);
f67a559d 3267
5bfe2ac0 3268 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3269 /* Note: FDI PLL enabling _must_ be done before we enable the
3270 * cpu pipes, hence this is separate from all the other fdi/pch
3271 * enabling. */
88cefb6c 3272 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3273 } else {
3274 assert_fdi_tx_disabled(dev_priv, pipe);
3275 assert_fdi_rx_disabled(dev_priv, pipe);
3276 }
f67a559d 3277
b074cec8 3278 ironlake_pfit_enable(intel_crtc);
f67a559d 3279
9c54c0dd
JB		 3280 /*
3281 * On ILK+ LUT must be loaded before the pipe is running but with
3282 * clocks enabled
3283 */
3284 intel_crtc_load_lut(crtc);
3285
5bfe2ac0
DV		 3286 intel_enable_pipe(dev_priv, pipe,
3287 intel_crtc->config.has_pch_encoder);
f67a559d 3288 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3289 intel_enable_planes(crtc);
5c38d48c 3290 intel_crtc_update_cursor(crtc, true);
f67a559d 3291
5bfe2ac0 3292 if (intel_crtc->config.has_pch_encoder)
f67a559d 3293 ironlake_pch_enable(crtc);
c98e9dcf 3294
d1ebd816 3295 mutex_lock(&dev->struct_mutex);
bed4a673 3296 intel_update_fbc(dev);
d1ebd816
BW		 3297 mutex_unlock(&dev->struct_mutex);
3298
fa5c73b1
DV		 3299 for_each_encoder_on_crtc(dev, crtc, encoder)
3300 encoder->enable(encoder);
61b77ddd
DV		 3301
3302 if (HAS_PCH_CPT(dev))
a1520318 3303 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3304
3305 /*
3306 * There seems to be a race in PCH platform hw (at least on some
3307 * outputs) where an enabled pipe still completes any pageflip right
3308 * away (as if the pipe is off) instead of waiting for vblank. As soon
3309 * as the first vblank happend, everything works as expected. Hence just
3310 * wait for one vblank before returning to avoid strange things
3311 * happening.
3312 */
3313 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3314}
3315
42db64ef
PZ		 3316/* IPS only exists on ULT machines and is tied to pipe A. */
3317static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3318{
f5adf94e 3319 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3320}
3321
3322static void hsw_enable_ips(struct intel_crtc *crtc)
3323{
3324 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3325
3326 if (!crtc->config.ips_enabled)
3327 return;
3328
3329 /* We can only enable IPS after we enable a plane and wait for a vblank.
3330 * We guarantee that the plane is enabled by calling intel_enable_ips
3331 * only after intel_enable_plane. And intel_enable_plane already waits
3332 * for a vblank, so all we need to do here is to enable the IPS bit. */
3333 assert_plane_enabled(dev_priv, crtc->plane);
3334 I915_WRITE(IPS_CTL, IPS_ENABLE);
3335}
3336
3337static void hsw_disable_ips(struct intel_crtc *crtc)
3338{
3339 struct drm_device *dev = crtc->base.dev;
3340 struct drm_i915_private *dev_priv = dev->dev_private;
3341
3342 if (!crtc->config.ips_enabled)
3343 return;
3344
3345 assert_plane_enabled(dev_priv, crtc->plane);
3346 I915_WRITE(IPS_CTL, 0);
3347
3348 /* We need to wait for a vblank before we can disable the plane. */
3349 intel_wait_for_vblank(dev, crtc->pipe);
3350}
3351
4f771f10
PZ		 3352static void haswell_crtc_enable(struct drm_crtc *crtc)
3353{
3354 struct drm_device *dev = crtc->dev;
3355 struct drm_i915_private *dev_priv = dev->dev_private;
3356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3357 struct intel_encoder *encoder;
3358 int pipe = intel_crtc->pipe;
3359 int plane = intel_crtc->plane;
4f771f10
PZ		 3360
3361 WARN_ON(!crtc->enabled);
3362
3363 if (intel_crtc->active)
3364 return;
3365
3366 intel_crtc->active = true;
8664281b
PZ		 3367
3368 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3369 if (intel_crtc->config.has_pch_encoder)
3370 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3371
4f771f10
PZ		 3372 intel_update_watermarks(dev);
3373
5bfe2ac0 3374 if (intel_crtc->config.has_pch_encoder)
04945641 3375 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3376
3377 for_each_encoder_on_crtc(dev, crtc, encoder)
3378 if (encoder->pre_enable)
3379 encoder->pre_enable(encoder);
3380
1f544388 3381 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3382
b074cec8 3383 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3384
3385 /*
3386 * On ILK+ LUT must be loaded before the pipe is running but with
3387 * clocks enabled
3388 */
3389 intel_crtc_load_lut(crtc);
3390
1f544388 3391 intel_ddi_set_pipe_settings(crtc);
8228c251 3392 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3393
5bfe2ac0
DV		 3394 intel_enable_pipe(dev_priv, pipe,
3395 intel_crtc->config.has_pch_encoder);
4f771f10 3396 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3397 intel_enable_planes(crtc);
5c38d48c 3398 intel_crtc_update_cursor(crtc, true);
4f771f10 3399
42db64ef
PZ		 3400 hsw_enable_ips(intel_crtc);
3401
5bfe2ac0 3402 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3403 lpt_pch_enable(crtc);
4f771f10
PZ		 3404
3405 mutex_lock(&dev->struct_mutex);
3406 intel_update_fbc(dev);
3407 mutex_unlock(&dev->struct_mutex);
3408
4f771f10
PZ		 3409 for_each_encoder_on_crtc(dev, crtc, encoder)
3410 encoder->enable(encoder);
3411
4f771f10
PZ		 3412 /*
3413 * There seems to be a race in PCH platform hw (at least on some
3414 * outputs) where an enabled pipe still completes any pageflip right
3415 * away (as if the pipe is off) instead of waiting for vblank. As soon
3416 * as the first vblank happend, everything works as expected. Hence just
3417 * wait for one vblank before returning to avoid strange things
3418 * happening.
3419 */
3420 intel_wait_for_vblank(dev, intel_crtc->pipe);
3421}
3422
3f8dce3a
DV		 3423static void ironlake_pfit_disable(struct intel_crtc *crtc)
3424{
3425 struct drm_device *dev = crtc->base.dev;
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427 int pipe = crtc->pipe;
3428
3429 /* To avoid upsetting the power well on haswell only disable the pfit if
3430 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3431 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3432 I915_WRITE(PF_CTL(pipe), 0);
3433 I915_WRITE(PF_WIN_POS(pipe), 0);
3434 I915_WRITE(PF_WIN_SZ(pipe), 0);
3435 }
3436}
3437
6be4a607
JB		 3438static void ironlake_crtc_disable(struct drm_crtc *crtc)
3439{
3440 struct drm_device *dev = crtc->dev;
3441 struct drm_i915_private *dev_priv = dev->dev_private;
3442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3443 struct intel_encoder *encoder;
6be4a607
JB		 3444 int pipe = intel_crtc->pipe;
3445 int plane = intel_crtc->plane;
5eddb70b 3446 u32 reg, temp;
b52eb4dc 3447
ef9c3aee 3448
f7abfe8b
CW		 3449 if (!intel_crtc->active)
3450 return;
3451
ea9d758d
DV		 3452 for_each_encoder_on_crtc(dev, crtc, encoder)
3453 encoder->disable(encoder);
3454
e6c3a2a6 3455 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3456 drm_vblank_off(dev, pipe);
913d8d11 3457
5c3fe8b0 3458 if (dev_priv->fbc.plane == plane)
973d04f9 3459 intel_disable_fbc(dev);
2c07245f 3460
0d5b8c61 3461 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3462 intel_disable_planes(crtc);
0d5b8c61
VS		 3463 intel_disable_plane(dev_priv, plane, pipe);
3464
d925c59a
DV		 3465 if (intel_crtc->config.has_pch_encoder)
3466 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3467
b24e7179 3468 intel_disable_pipe(dev_priv, pipe);
32f9d658 3469
3f8dce3a 3470 ironlake_pfit_disable(intel_crtc);
2c07245f 3471
bf49ec8c
DV		 3472 for_each_encoder_on_crtc(dev, crtc, encoder)
3473 if (encoder->post_disable)
3474 encoder->post_disable(encoder);
2c07245f 3475
d925c59a
DV		 3476 if (intel_crtc->config.has_pch_encoder) {
3477 ironlake_fdi_disable(crtc);
913d8d11 3478
d925c59a
DV		 3479 ironlake_disable_pch_transcoder(dev_priv, pipe);
3480 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3481
d925c59a
DV		 3482 if (HAS_PCH_CPT(dev)) {
3483 /* disable TRANS_DP_CTL */
3484 reg = TRANS_DP_CTL(pipe);
3485 temp = I915_READ(reg);
3486 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3487 TRANS_DP_PORT_SEL_MASK);
3488 temp |= TRANS_DP_PORT_SEL_NONE;
3489 I915_WRITE(reg, temp);
3490
3491 /* disable DPLL_SEL */
3492 temp = I915_READ(PCH_DPLL_SEL);
11887397 3493 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3494 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3495 }
e3421a18 3496
d925c59a 3497 /* disable PCH DPLL */
e72f9fbf 3498 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3499
d925c59a
DV		 3500 ironlake_fdi_pll_disable(intel_crtc);
3501 }
6b383a7f 3502
f7abfe8b 3503 intel_crtc->active = false;
6b383a7f 3504 intel_update_watermarks(dev);
d1ebd816
BW		 3505
3506 mutex_lock(&dev->struct_mutex);
6b383a7f 3507 intel_update_fbc(dev);
d1ebd816 3508 mutex_unlock(&dev->struct_mutex);
6be4a607 3509}
1b3c7a47 3510
4f771f10 3511static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3512{
4f771f10
PZ		 3513 struct drm_device *dev = crtc->dev;
3514 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3516 struct intel_encoder *encoder;
3517 int pipe = intel_crtc->pipe;
3518 int plane = intel_crtc->plane;
3b117c8f 3519 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3520
4f771f10
PZ		 3521 if (!intel_crtc->active)
3522 return;
3523
3524 for_each_encoder_on_crtc(dev, crtc, encoder)
3525 encoder->disable(encoder);
3526
3527 intel_crtc_wait_for_pending_flips(crtc);
3528 drm_vblank_off(dev, pipe);
4f771f10 3529
891348b2 3530 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3531 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3532 intel_disable_fbc(dev);
3533
42db64ef
PZ		 3534 hsw_disable_ips(intel_crtc);
3535
0d5b8c61 3536 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3537 intel_disable_planes(crtc);
891348b2
RV		 3538 intel_disable_plane(dev_priv, plane, pipe);
3539
8664281b
PZ		 3540 if (intel_crtc->config.has_pch_encoder)
3541 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3542 intel_disable_pipe(dev_priv, pipe);
3543
ad80a810 3544 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3545
3f8dce3a 3546 ironlake_pfit_disable(intel_crtc);
4f771f10 3547
1f544388 3548 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3549
3550 for_each_encoder_on_crtc(dev, crtc, encoder)
3551 if (encoder->post_disable)
3552 encoder->post_disable(encoder);
3553
88adfff1 3554 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3555 lpt_disable_pch_transcoder(dev_priv);
8664281b 3556 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3557 intel_ddi_fdi_disable(crtc);
83616634 3558 }
4f771f10
PZ		 3559
3560 intel_crtc->active = false;
3561 intel_update_watermarks(dev);
3562
3563 mutex_lock(&dev->struct_mutex);
3564 intel_update_fbc(dev);
3565 mutex_unlock(&dev->struct_mutex);
3566}
3567
ee7b9f93
JB		 3568static void ironlake_crtc_off(struct drm_crtc *crtc)
3569{
3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3571 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3572}
3573
6441ab5f
PZ		 3574static void haswell_crtc_off(struct drm_crtc *crtc)
3575{
3576 intel_ddi_put_crtc_pll(crtc);
3577}
3578
02e792fb
DV		 3579static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3580{
02e792fb 3581 if (!enable && intel_crtc->overlay) {
23f09ce3 3582 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3583 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3584
23f09ce3 3585 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3586 dev_priv->mm.interruptible = false;
3587 (void) intel_overlay_switch_off(intel_crtc->overlay);
3588 dev_priv->mm.interruptible = true;
23f09ce3 3589 mutex_unlock(&dev->struct_mutex);
02e792fb 3590 }
02e792fb 3591
5dcdbcb0
CW		 3592 /* Let userspace switch the overlay on again. In most cases userspace
3593 * has to recompute where to put it anyway.
3594 */
02e792fb
DV		 3595}
3596
61bc95c1
EE		 3597/**
3598 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3599 * cursor plane briefly if not already running after enabling the display
3600 * plane.
3601 * This workaround avoids occasional blank screens when self refresh is
3602 * enabled.
3603 */
3604static void
3605g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3606{
3607 u32 cntl = I915_READ(CURCNTR(pipe));
3608
3609 if ((cntl & CURSOR_MODE) == 0) {
3610 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3611
3612 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3613 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3614 intel_wait_for_vblank(dev_priv->dev, pipe);
3615 I915_WRITE(CURCNTR(pipe), cntl);
3616 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3617 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3618 }
3619}
3620
2dd24552
JB		 3621static void i9xx_pfit_enable(struct intel_crtc *crtc)
3622{
3623 struct drm_device *dev = crtc->base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct intel_crtc_config *pipe_config = &crtc->config;
3626
328d8e82 3627 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3628 return;
3629
2dd24552 3630 /*
c0b03411
DV		 3631 * The panel fitter should only be adjusted whilst the pipe is disabled,
3632 * according to register description and PRM.
2dd24552 3633 */
c0b03411
DV		 3634 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3635 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3636
b074cec8
JB		 3637 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3638 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3639
3640 /* Border color in case we don't scale up to the full screen. Black by
3641 * default, change to something else for debugging. */
3642 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3643}
3644
89b667f8
JB		 3645static void valleyview_crtc_enable(struct drm_crtc *crtc)
3646{
3647 struct drm_device *dev = crtc->dev;
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3650 struct intel_encoder *encoder;
3651 int pipe = intel_crtc->pipe;
3652 int plane = intel_crtc->plane;
3653
3654 WARN_ON(!crtc->enabled);
3655
3656 if (intel_crtc->active)
3657 return;
3658
3659 intel_crtc->active = true;
3660 intel_update_watermarks(dev);
3661
89b667f8
JB		 3662 for_each_encoder_on_crtc(dev, crtc, encoder)
3663 if (encoder->pre_pll_enable)
3664 encoder->pre_pll_enable(encoder);
3665
426115cf 3666 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3667
3668 for_each_encoder_on_crtc(dev, crtc, encoder)
3669 if (encoder->pre_enable)
3670 encoder->pre_enable(encoder);
3671
2dd24552
JB		 3672 i9xx_pfit_enable(intel_crtc);
3673
63cbb074
VS		 3674 intel_crtc_load_lut(crtc);
3675
89b667f8
JB		 3676 intel_enable_pipe(dev_priv, pipe, false);
3677 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3678 intel_enable_planes(crtc);
5c38d48c 3679 intel_crtc_update_cursor(crtc, true);
89b667f8 3680
89b667f8 3681 intel_update_fbc(dev);
5004945f
JN		 3682
3683 for_each_encoder_on_crtc(dev, crtc, encoder)
3684 encoder->enable(encoder);
89b667f8
JB		 3685}
3686
0b8765c6 3687static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3688{
3689 struct drm_device *dev = crtc->dev;
79e53945
JB		 3690 struct drm_i915_private *dev_priv = dev->dev_private;
3691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3692 struct intel_encoder *encoder;
79e53945 3693 int pipe = intel_crtc->pipe;
80824003 3694 int plane = intel_crtc->plane;
79e53945 3695
08a48469
DV		 3696 WARN_ON(!crtc->enabled);
3697
f7abfe8b
CW		 3698 if (intel_crtc->active)
3699 return;
3700
3701 intel_crtc->active = true;
6b383a7f
CW		 3702 intel_update_watermarks(dev);
3703
9d6d9f19
MK		 3704 for_each_encoder_on_crtc(dev, crtc, encoder)
3705 if (encoder->pre_enable)
3706 encoder->pre_enable(encoder);
3707
f6736a1a
DV		 3708 i9xx_enable_pll(intel_crtc);
3709
2dd24552
JB		 3710 i9xx_pfit_enable(intel_crtc);
3711
63cbb074
VS		 3712 intel_crtc_load_lut(crtc);
3713
040484af 3714 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3715 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3716 intel_enable_planes(crtc);
22e407d7 3717 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3718 if (IS_G4X(dev))
3719 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3720 intel_crtc_update_cursor(crtc, true);
79e53945 3721
0b8765c6
JB		 3722 /* Give the overlay scaler a chance to enable if it's on this pipe */
3723 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3724
f440eb13 3725 intel_update_fbc(dev);
ef9c3aee 3726
fa5c73b1
DV		 3727 for_each_encoder_on_crtc(dev, crtc, encoder)
3728 encoder->enable(encoder);
0b8765c6 3729}
79e53945 3730
87476d63
DV		 3731static void i9xx_pfit_disable(struct intel_crtc *crtc)
3732{
3733 struct drm_device *dev = crtc->base.dev;
3734 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3735
328d8e82
DV		 3736 if (!crtc->config.gmch_pfit.control)
3737 return;
87476d63 3738
328d8e82 3739 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3740
328d8e82
DV		 3741 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3742 I915_READ(PFIT_CONTROL));
3743 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3744}
3745
0b8765c6
JB		 3746static void i9xx_crtc_disable(struct drm_crtc *crtc)
3747{
3748 struct drm_device *dev = crtc->dev;
3749 struct drm_i915_private *dev_priv = dev->dev_private;
3750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3751 struct intel_encoder *encoder;
0b8765c6
JB		 3752 int pipe = intel_crtc->pipe;
3753 int plane = intel_crtc->plane;
ef9c3aee 3754
f7abfe8b
CW		 3755 if (!intel_crtc->active)
3756 return;
3757
ea9d758d
DV		 3758 for_each_encoder_on_crtc(dev, crtc, encoder)
3759 encoder->disable(encoder);
3760
0b8765c6 3761 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3762 intel_crtc_wait_for_pending_flips(crtc);
3763 drm_vblank_off(dev, pipe);
0b8765c6 3764
5c3fe8b0 3765 if (dev_priv->fbc.plane == plane)
973d04f9 3766 intel_disable_fbc(dev);
79e53945 3767
0d5b8c61
VS		 3768 intel_crtc_dpms_overlay(intel_crtc, false);
3769 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3770 intel_disable_planes(crtc);
b24e7179 3771 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3772
b24e7179 3773 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3774
87476d63 3775 i9xx_pfit_disable(intel_crtc);
24a1f16d 3776
89b667f8
JB		 3777 for_each_encoder_on_crtc(dev, crtc, encoder)
3778 if (encoder->post_disable)
3779 encoder->post_disable(encoder);
3780
50b44a44 3781 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3782
f7abfe8b 3783 intel_crtc->active = false;
6b383a7f
CW		 3784 intel_update_fbc(dev);
3785 intel_update_watermarks(dev);
0b8765c6
JB		 3786}
3787
ee7b9f93
JB		 3788static void i9xx_crtc_off(struct drm_crtc *crtc)
3789{
3790}
3791
976f8a20
DV		 3792static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3793 bool enabled)
2c07245f
ZW		 3794{
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_master_private *master_priv;
3797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3798 int pipe = intel_crtc->pipe;
79e53945
JB		 3799
3800 if (!dev->primary->master)
3801 return;
3802
3803 master_priv = dev->primary->master->driver_priv;
3804 if (!master_priv->sarea_priv)
3805 return;
3806
79e53945
JB		 3807 switch (pipe) {
3808 case 0:
3809 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3810 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3811 break;
3812 case 1:
3813 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3814 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3815 break;
3816 default:
9db4a9c7 3817 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3818 break;
3819 }
79e53945
JB		 3820}
3821
976f8a20
DV		 3822/**
3823 * Sets the power management mode of the pipe and plane.
3824 */
3825void intel_crtc_update_dpms(struct drm_crtc *crtc)
3826{
3827 struct drm_device *dev = crtc->dev;
3828 struct drm_i915_private *dev_priv = dev->dev_private;
3829 struct intel_encoder *intel_encoder;
3830 bool enable = false;
3831
3832 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3833 enable |= intel_encoder->connectors_active;
3834
3835 if (enable)
3836 dev_priv->display.crtc_enable(crtc);
3837 else
3838 dev_priv->display.crtc_disable(crtc);
3839
3840 intel_crtc_update_sarea(crtc, enable);
3841}
3842
cdd59983
CW		 3843static void intel_crtc_disable(struct drm_crtc *crtc)
3844{
cdd59983 3845 struct drm_device *dev = crtc->dev;
976f8a20 3846 struct drm_connector *connector;
ee7b9f93 3847 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3849
976f8a20
DV		 3850 /* crtc should still be enabled when we disable it. */
3851 WARN_ON(!crtc->enabled);
3852
3853 dev_priv->display.crtc_disable(crtc);
c77bf565 3854 intel_crtc->eld_vld = false;
976f8a20 3855 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3856 dev_priv->display.off(crtc);
3857
931872fc
CW		 3858 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3859 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3860
3861 if (crtc->fb) {
3862 mutex_lock(&dev->struct_mutex);
1690e1eb 3863 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3864 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3865 crtc->fb = NULL;
3866 }
3867
3868 /* Update computed state. */
3869 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3870 if (!connector->encoder || !connector->encoder->crtc)
3871 continue;
3872
3873 if (connector->encoder->crtc != crtc)
3874 continue;
3875
3876 connector->dpms = DRM_MODE_DPMS_OFF;
3877 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3878 }
3879}
3880
ea5b213a 3881void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3882{
4ef69c7a 3883 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3884
ea5b213a
CW		 3885 drm_encoder_cleanup(encoder);
3886 kfree(intel_encoder);
7e7d76c3
JB		 3887}
3888
9237329d 3889/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3890 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3891 * state of the entire output pipe. */
9237329d 3892static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3893{
5ab432ef
DV		 3894 if (mode == DRM_MODE_DPMS_ON) {
3895 encoder->connectors_active = true;
3896
b2cabb0e 3897 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3898 } else {
3899 encoder->connectors_active = false;
3900
b2cabb0e 3901 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3902 }
79e53945
JB		 3903}
3904
0a91ca29
DV		 3905/* Cross check the actual hw state with our own modeset state tracking (and it's
3906 * internal consistency). */
b980514c 3907static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3908{
0a91ca29
DV		 3909 if (connector->get_hw_state(connector)) {
3910 struct intel_encoder *encoder = connector->encoder;
3911 struct drm_crtc *crtc;
3912 bool encoder_enabled;
3913 enum pipe pipe;
3914
3915 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3916 connector->base.base.id,
3917 drm_get_connector_name(&connector->base));
3918
3919 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3920 "wrong connector dpms state\n");
3921 WARN(connector->base.encoder != &encoder->base,
3922 "active connector not linked to encoder\n");
3923 WARN(!encoder->connectors_active,
3924 "encoder->connectors_active not set\n");
3925
3926 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3927 WARN(!encoder_enabled, "encoder not enabled\n");
3928 if (WARN_ON(!encoder->base.crtc))
3929 return;
3930
3931 crtc = encoder->base.crtc;
3932
3933 WARN(!crtc->enabled, "crtc not enabled\n");
3934 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3935 WARN(pipe != to_intel_crtc(crtc)->pipe,
3936 "encoder active on the wrong pipe\n");
3937 }
79e53945
JB		 3938}
3939
5ab432ef
DV		 3940/* Even simpler default implementation, if there's really no special case to
3941 * consider. */
3942void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3943{
5ab432ef
DV		 3944 /* All the simple cases only support two dpms states. */
3945 if (mode != DRM_MODE_DPMS_ON)
3946 mode = DRM_MODE_DPMS_OFF;
d4270e57 3947
5ab432ef
DV		 3948 if (mode == connector->dpms)
3949 return;
3950
3951 connector->dpms = mode;
3952
3953 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 3954 if (connector->encoder)
3955 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 3956
b980514c 3957 intel_modeset_check_state(connector->dev);
79e53945
JB		 3958}
3959
f0947c37
DV		 3960/* Simple connector->get_hw_state implementation for encoders that support only
3961 * one connector and no cloning and hence the encoder state determines the state
3962 * of the connector. */
3963bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3964{
24929352 3965 enum pipe pipe = 0;
f0947c37 3966 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3967
f0947c37 3968 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3969}
3970
1857e1da
DV		 3971static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3972 struct intel_crtc_config *pipe_config)
3973{
3974 struct drm_i915_private *dev_priv = dev->dev_private;
3975 struct intel_crtc *pipe_B_crtc =
3976 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3977
3978 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3979 pipe_name(pipe), pipe_config->fdi_lanes);
3980 if (pipe_config->fdi_lanes > 4) {
3981 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3982 pipe_name(pipe), pipe_config->fdi_lanes);
3983 return false;
3984 }
3985
3986 if (IS_HASWELL(dev)) {
3987 if (pipe_config->fdi_lanes > 2) {
3988 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3989 pipe_config->fdi_lanes);
3990 return false;
3991 } else {
3992 return true;
3993 }
3994 }
3995
3996 if (INTEL_INFO(dev)->num_pipes == 2)
3997 return true;
3998
3999 /* Ivybridge 3 pipe is really complicated */
4000 switch (pipe) {
4001 case PIPE_A:
4002 return true;
4003 case PIPE_B:
4004 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4005 pipe_config->fdi_lanes > 2) {
4006 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4007 pipe_name(pipe), pipe_config->fdi_lanes);
4008 return false;
4009 }
4010 return true;
4011 case PIPE_C:
1e833f40 4012 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4013 pipe_B_crtc->config.fdi_lanes <= 2) {
4014 if (pipe_config->fdi_lanes > 2) {
4015 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4016 pipe_name(pipe), pipe_config->fdi_lanes);
4017 return false;
4018 }
4019 } else {
4020 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4021 return false;
4022 }
4023 return true;
4024 default:
4025 BUG();
4026 }
4027}
4028
e29c22c0
DV		 4029#define RETRY 1
4030static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4031 struct intel_crtc_config *pipe_config)
877d48d5 4032{
1857e1da 4033 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4034 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4035 int lane, link_bw, fdi_dotclock;
e29c22c0 4036 bool setup_ok, needs_recompute = false;
877d48d5 4037
e29c22c0 4038retry:
877d48d5
DV		 4039 /* FDI is a binary signal running at ~2.7GHz, encoding
4040 * each output octet as 10 bits. The actual frequency
4041 * is stored as a divider into a 100MHz clock, and the
4042 * mode pixel clock is stored in units of 1KHz.
4043 * Hence the bw of each lane in terms of the mode signal
4044 * is:
4045 */
4046 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4047
ff9a6750 4048 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4049 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4050
2bd89a07 4051 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4052 pipe_config->pipe_bpp);
4053
4054 pipe_config->fdi_lanes = lane;
4055
2bd89a07 4056 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4057 link_bw, &pipe_config->fdi_m_n);
1857e1da 4058
e29c22c0
DV		 4059 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4060 intel_crtc->pipe, pipe_config);
4061 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4062 pipe_config->pipe_bpp -= 2*3;
4063 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4064 pipe_config->pipe_bpp);
4065 needs_recompute = true;
4066 pipe_config->bw_constrained = true;
4067
4068 goto retry;
4069 }
4070
4071 if (needs_recompute)
4072 return RETRY;
4073
4074 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4075}
4076
42db64ef
PZ		 4077static void hsw_compute_ips_config(struct intel_crtc *crtc,
4078 struct intel_crtc_config *pipe_config)
4079{
3c4ca58c
PZ		 4080 pipe_config->ips_enabled = i915_enable_ips &&
4081 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4082 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4083}
4084
a43f6e0f 4085static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4086 struct intel_crtc_config *pipe_config)
79e53945 4087{
a43f6e0f 4088 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4089 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4090
bad720ff 4091 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4092 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4093 if (pipe_config->requested_mode.clock * 3
4094 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4095 return -EINVAL;
2c07245f 4096 }
89749350 4097
8693a824
DL		 4098 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4099 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4100 */
4101 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4102 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4103 return -EINVAL;
44f46b42 4104
bd080ee5 4105 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4106 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4107 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4108 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4109 * for lvds. */
4110 pipe_config->pipe_bpp = 8*3;
4111 }
4112
f5adf94e 4113 if (HAS_IPS(dev))
a43f6e0f
DV		 4114 hsw_compute_ips_config(crtc, pipe_config);
4115
4116 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4117 * clock survives for now. */
4118 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4119 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4120
877d48d5 4121 if (pipe_config->has_pch_encoder)
a43f6e0f 4122 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4123
e29c22c0 4124 return 0;
79e53945
JB		 4125}
4126
25eb05fc
JB		 4127static int valleyview_get_display_clock_speed(struct drm_device *dev)
4128{
4129 return 400000; /* FIXME */
4130}
4131
e70236a8
JB		 4132static int i945_get_display_clock_speed(struct drm_device *dev)
4133{
4134 return 400000;
4135}
79e53945 4136
e70236a8 4137static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4138{
e70236a8
JB		 4139 return 333000;
4140}
79e53945 4141
e70236a8
JB		 4142static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4143{
4144 return 200000;
4145}
79e53945 4146
257a7ffc
DV		 4147static int pnv_get_display_clock_speed(struct drm_device *dev)
4148{
4149 u16 gcfgc = 0;
4150
4151 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4152
4153 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4154 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4155 return 267000;
4156 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4157 return 333000;
4158 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4159 return 444000;
4160 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4161 return 200000;
4162 default:
4163 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4164 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4165 return 133000;
4166 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4167 return 167000;
4168 }
4169}
4170
e70236a8
JB		 4171static int i915gm_get_display_clock_speed(struct drm_device *dev)
4172{
4173 u16 gcfgc = 0;
79e53945 4174
e70236a8
JB		 4175 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4176
4177 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4178 return 133000;
4179 else {
4180 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4181 case GC_DISPLAY_CLOCK_333_MHZ:
4182 return 333000;
4183 default:
4184 case GC_DISPLAY_CLOCK_190_200_MHZ:
4185 return 190000;
79e53945 4186 }
e70236a8
JB		 4187 }
4188}
4189
4190static int i865_get_display_clock_speed(struct drm_device *dev)
4191{
4192 return 266000;
4193}
4194
4195static int i855_get_display_clock_speed(struct drm_device *dev)
4196{
4197 u16 hpllcc = 0;
4198 /* Assume that the hardware is in the high speed state. This
4199 * should be the default.
4200 */
4201 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4202 case GC_CLOCK_133_200:
4203 case GC_CLOCK_100_200:
4204 return 200000;
4205 case GC_CLOCK_166_250:
4206 return 250000;
4207 case GC_CLOCK_100_133:
79e53945 4208 return 133000;
e70236a8 4209 }
79e53945 4210
e70236a8
JB		 4211 /* Shouldn't happen */
4212 return 0;
4213}
79e53945 4214
e70236a8
JB		 4215static int i830_get_display_clock_speed(struct drm_device *dev)
4216{
4217 return 133000;
79e53945
JB		 4218}
4219
2c07245f 4220static void
a65851af 4221intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4222{
a65851af
VS		 4223 while (*num > DATA_LINK_M_N_MASK ||
4224 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4225 *num >>= 1;
4226 *den >>= 1;
4227 }
4228}
4229
a65851af
VS		 4230static void compute_m_n(unsigned int m, unsigned int n,
4231 uint32_t *ret_m, uint32_t *ret_n)
4232{
4233 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4234 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4235 intel_reduce_m_n_ratio(ret_m, ret_n);
4236}
4237
e69d0bc1
DV		 4238void
4239intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4240 int pixel_clock, int link_clock,
4241 struct intel_link_m_n *m_n)
2c07245f 4242{
e69d0bc1 4243 m_n->tu = 64;
a65851af
VS		 4244
4245 compute_m_n(bits_per_pixel * pixel_clock,
4246 link_clock * nlanes * 8,
4247 &m_n->gmch_m, &m_n->gmch_n);
4248
4249 compute_m_n(pixel_clock, link_clock,
4250 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4251}
4252
a7615030
CW		 4253static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4254{
72bbe58c
KP		 4255 if (i915_panel_use_ssc >= 0)
4256 return i915_panel_use_ssc != 0;
41aa3448 4257 return dev_priv->vbt.lvds_use_ssc
435793df 4258 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4259}
4260
a0c4da24
JB		 4261static int vlv_get_refclk(struct drm_crtc *crtc)
4262{
4263 struct drm_device *dev = crtc->dev;
4264 struct drm_i915_private *dev_priv = dev->dev_private;
4265 int refclk = 27000; /* for DP & HDMI */
4266
4267 return 100000; /* only one validated so far */
4268
4269 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4270 refclk = 96000;
4271 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4272 if (intel_panel_use_ssc(dev_priv))
4273 refclk = 100000;
4274 else
4275 refclk = 96000;
4276 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4277 refclk = 100000;
4278 }
4279
4280 return refclk;
4281}
4282
c65d77d8
JB		 4283static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4284{
4285 struct drm_device *dev = crtc->dev;
4286 struct drm_i915_private *dev_priv = dev->dev_private;
4287 int refclk;
4288
a0c4da24
JB		 4289 if (IS_VALLEYVIEW(dev)) {
4290 refclk = vlv_get_refclk(crtc);
4291 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4292 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4293 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4294 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4295 refclk / 1000);
4296 } else if (!IS_GEN2(dev)) {
4297 refclk = 96000;
4298 } else {
4299 refclk = 48000;
4300 }
4301
4302 return refclk;
4303}
4304
7429e9d4 4305static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4306{
7df00d7a 4307 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4308}
f47709a9 4309
7429e9d4
DV		 4310static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4311{
4312 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4313}
4314
f47709a9 4315static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4316 intel_clock_t *reduced_clock)
4317{
f47709a9 4318 struct drm_device *dev = crtc->base.dev;
a7516a05 4319 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4320 int pipe = crtc->pipe;
a7516a05
JB		 4321 u32 fp, fp2 = 0;
4322
4323 if (IS_PINEVIEW(dev)) {
7429e9d4 4324 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4325 if (reduced_clock)
7429e9d4 4326 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4327 } else {
7429e9d4 4328 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4329 if (reduced_clock)
7429e9d4 4330 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4331 }
4332
4333 I915_WRITE(FP0(pipe), fp);
8bcc2795 4334 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4335
f47709a9
DV		 4336 crtc->lowfreq_avail = false;
4337 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4338 reduced_clock && i915_powersave) {
4339 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4340 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4341 crtc->lowfreq_avail = true;
a7516a05
JB		 4342 } else {
4343 I915_WRITE(FP1(pipe), fp);
8bcc2795 4344 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4345 }
4346}
4347
89b667f8
JB		 4348static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4349{
4350 u32 reg_val;
4351
4352 /*
4353 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4354 * and set it to a reasonable value instead.
4355 */
ae99258f 4356 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4357 reg_val &= 0xffffff00;
4358 reg_val |= 0x00000030;
ae99258f 4359 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4360
ae99258f 4361 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4362 reg_val &= 0x8cffffff;
4363 reg_val = 0x8c000000;
ae99258f 4364 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4365
ae99258f 4366 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4367 reg_val &= 0xffffff00;
ae99258f 4368 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4369
ae99258f 4370 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4371 reg_val &= 0x00ffffff;
4372 reg_val |= 0xb0000000;
ae99258f 4373 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4374}
4375
b551842d
DV		 4376static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4377 struct intel_link_m_n *m_n)
4378{
4379 struct drm_device *dev = crtc->base.dev;
4380 struct drm_i915_private *dev_priv = dev->dev_private;
4381 int pipe = crtc->pipe;
4382
e3b95f1e
DV		 4383 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4384 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4385 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4386 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4387}
4388
4389static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4390 struct intel_link_m_n *m_n)
4391{
4392 struct drm_device *dev = crtc->base.dev;
4393 struct drm_i915_private *dev_priv = dev->dev_private;
4394 int pipe = crtc->pipe;
4395 enum transcoder transcoder = crtc->config.cpu_transcoder;
4396
4397 if (INTEL_INFO(dev)->gen >= 5) {
4398 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4399 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4400 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4401 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4402 } else {
e3b95f1e
DV		 4403 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4404 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4405 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4406 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4407 }
4408}
4409
03afc4a2
DV		 4410static void intel_dp_set_m_n(struct intel_crtc *crtc)
4411{
4412 if (crtc->config.has_pch_encoder)
4413 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4414 else
4415 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4416}
4417
f47709a9 4418static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4419{
f47709a9 4420 struct drm_device *dev = crtc->base.dev;
a0c4da24 4421 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4422 int pipe = crtc->pipe;
89b667f8 4423 u32 dpll, mdiv;
a0c4da24 4424 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4425 u32 coreclk, reg_val, dpll_md;
a0c4da24 4426
09153000
DV		 4427 mutex_lock(&dev_priv->dpio_lock);
4428
f47709a9
DV		 4429 bestn = crtc->config.dpll.n;
4430 bestm1 = crtc->config.dpll.m1;
4431 bestm2 = crtc->config.dpll.m2;
4432 bestp1 = crtc->config.dpll.p1;
4433 bestp2 = crtc->config.dpll.p2;
a0c4da24 4434
89b667f8
JB		 4435 /* See eDP HDMI DPIO driver vbios notes doc */
4436
4437 /* PLL B needs special handling */
4438 if (pipe)
4439 vlv_pllb_recal_opamp(dev_priv);
4440
4441 /* Set up Tx target for periodic Rcomp update */
ae99258f 4442 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4443
4444 /* Disable target IRef on PLL */
ae99258f 4445 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4446 reg_val &= 0x00ffffff;
ae99258f 4447 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4448
4449 /* Disable fast lock */
ae99258f 4450 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4451
4452 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4453 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4454 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4455 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4456 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4457
4458 /*
4459 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4460 * but we don't support that).
4461 * Note: don't use the DAC post divider as it seems unstable.
4462 */
4463 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4464 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4465
a0c4da24 4466 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4467 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4468
89b667f8 4469 /* Set HBR and RBR LPF coefficients */
ff9a6750 4470 if (crtc->config.port_clock == 162000 ||
99750bd4 4471 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4472 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4473 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
885b0120 4474 0x009f0003);
89b667f8 4475 else
4abb2c39 4476 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4477 0x00d0000f);
4478
4479 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4480 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4481 /* Use SSC source */
4482 if (!pipe)
ae99258f 4483 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4484 0x0df40000);
4485 else
ae99258f 4486 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4487 0x0df70000);
4488 } else { /* HDMI or VGA */
4489 /* Use bend source */
4490 if (!pipe)
ae99258f 4491 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4492 0x0df70000);
4493 else
ae99258f 4494 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4495 0x0df40000);
4496 }
a0c4da24 4497
ae99258f 4498 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4499 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4500 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4501 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4502 coreclk |= 0x01000000;
ae99258f 4503 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4504
ae99258f 4505 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4506
89b667f8
JB		 4507 /* Enable DPIO clock input */
4508 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4509 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4510 if (pipe)
4511 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4512
4513 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4514 crtc->config.dpll_hw_state.dpll = dpll;
4515
ef1b460d
DV		 4516 dpll_md = (crtc->config.pixel_multiplier - 1)
4517 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4518 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4519
89b667f8
JB		 4520 if (crtc->config.has_dp_encoder)
4521 intel_dp_set_m_n(crtc);
09153000
DV		 4522
4523 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4524}
4525
f47709a9
DV		 4526static void i9xx_update_pll(struct intel_crtc *crtc,
4527 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4528 int num_connectors)
4529{
f47709a9 4530 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4531 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4532 u32 dpll;
4533 bool is_sdvo;
f47709a9 4534 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4535
f47709a9 4536 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4537
f47709a9
DV		 4538 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4539 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4540
4541 dpll = DPLL_VGA_MODE_DIS;
4542
f47709a9 4543 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4544 dpll |= DPLLB_MODE_LVDS;
4545 else
4546 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4547
ef1b460d 4548 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4549 dpll |= (crtc->config.pixel_multiplier - 1)
4550 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4551 }
198a037f
DV		 4552
4553 if (is_sdvo)
4a33e48d 4554 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4555
f47709a9 4556 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4557 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4558
4559 /* compute bitmask from p1 value */
4560 if (IS_PINEVIEW(dev))
4561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4562 else {
4563 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4564 if (IS_G4X(dev) && reduced_clock)
4565 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4566 }
4567 switch (clock->p2) {
4568 case 5:
4569 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4570 break;
4571 case 7:
4572 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4573 break;
4574 case 10:
4575 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4576 break;
4577 case 14:
4578 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4579 break;
4580 }
4581 if (INTEL_INFO(dev)->gen >= 4)
4582 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4583
09ede541 4584 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4585 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4586 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4587 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4588 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4589 else
4590 dpll |= PLL_REF_INPUT_DREFCLK;
4591
4592 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4593 crtc->config.dpll_hw_state.dpll = dpll;
4594
eb1cbe48 4595 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4596 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4597 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4598 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4599 }
66e3d5c0
DV		 4600
4601 if (crtc->config.has_dp_encoder)
4602 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4603}
4604
f47709a9 4605static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4606 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4607 int num_connectors)
4608{
f47709a9 4609 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4610 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4611 u32 dpll;
f47709a9 4612 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4613
f47709a9 4614 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4615
eb1cbe48
DV		 4616 dpll = DPLL_VGA_MODE_DIS;
4617
f47709a9 4618 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4619 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4620 } else {
4621 if (clock->p1 == 2)
4622 dpll |= PLL_P1_DIVIDE_BY_TWO;
4623 else
4624 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4625 if (clock->p2 == 4)
4626 dpll |= PLL_P2_DIVIDE_BY_4;
4627 }
4628
4a33e48d
DV		 4629 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4630 dpll |= DPLL_DVO_2X_MODE;
4631
f47709a9 4632 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4633 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4634 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4635 else
4636 dpll |= PLL_REF_INPUT_DREFCLK;
4637
4638 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4639 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4640}
4641
8a654f3b 4642static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4643{
4644 struct drm_device *dev = intel_crtc->base.dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4647 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4648 struct drm_display_mode *adjusted_mode =
4649 &intel_crtc->config.adjusted_mode;
4650 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4651 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4652
4653 /* We need to be careful not to changed the adjusted mode, for otherwise
4654 * the hw state checker will get angry at the mismatch. */
4655 crtc_vtotal = adjusted_mode->crtc_vtotal;
4656 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4657
4658 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4659 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4660 crtc_vtotal -= 1;
4661 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4662 vsyncshift = adjusted_mode->crtc_hsync_start
4663 - adjusted_mode->crtc_htotal / 2;
4664 } else {
4665 vsyncshift = 0;
4666 }
4667
4668 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4669 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4670
fe2b8f9d 4671 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4672 (adjusted_mode->crtc_hdisplay - 1) |
4673 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4674 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4675 (adjusted_mode->crtc_hblank_start - 1) |
4676 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4677 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4678 (adjusted_mode->crtc_hsync_start - 1) |
4679 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4680
fe2b8f9d 4681 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4682 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4683 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4684 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4685 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4686 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4687 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4688 (adjusted_mode->crtc_vsync_start - 1) |
4689 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4690
b5e508d4
PZ		 4691 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4692 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4693 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4694 * bits. */
4695 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4696 (pipe == PIPE_B || pipe == PIPE_C))
4697 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4698
b0e77b9c
PZ		 4699 /* pipesrc controls the size that is scaled from, which should
4700 * always be the user's requested size.
4701 */
4702 I915_WRITE(PIPESRC(pipe),
4703 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4704}
4705
1bd1bd80
DV		 4706static void intel_get_pipe_timings(struct intel_crtc *crtc,
4707 struct intel_crtc_config *pipe_config)
4708{
4709 struct drm_device *dev = crtc->base.dev;
4710 struct drm_i915_private *dev_priv = dev->dev_private;
4711 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4712 uint32_t tmp;
4713
4714 tmp = I915_READ(HTOTAL(cpu_transcoder));
4715 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4716 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4717 tmp = I915_READ(HBLANK(cpu_transcoder));
4718 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4719 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4720 tmp = I915_READ(HSYNC(cpu_transcoder));
4721 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4722 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4723
4724 tmp = I915_READ(VTOTAL(cpu_transcoder));
4725 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4726 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4727 tmp = I915_READ(VBLANK(cpu_transcoder));
4728 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4729 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4730 tmp = I915_READ(VSYNC(cpu_transcoder));
4731 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4732 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4733
4734 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4735 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4736 pipe_config->adjusted_mode.crtc_vtotal += 1;
4737 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4738 }
4739
4740 tmp = I915_READ(PIPESRC(crtc->pipe));
4741 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4742 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4743}
4744
babea61d
JB		 4745static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4746 struct intel_crtc_config *pipe_config)
4747{
4748 struct drm_crtc *crtc = &intel_crtc->base;
4749
4750 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4751 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4752 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4753 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4754
4755 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4756 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4757 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4758 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4759
4760 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4761
4762 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4763 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4764}
4765
84b046f3
DV		 4766static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4767{
4768 struct drm_device *dev = intel_crtc->base.dev;
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4770 uint32_t pipeconf;
4771
9f11a9e4 4772 pipeconf = 0;
84b046f3 4773
67c72a12
DV		 4774 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4775 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4776 pipeconf |= PIPECONF_ENABLE;
4777
84b046f3
DV		 4778 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4779 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4780 * core speed.
4781 *
4782 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4783 * pipe == 0 check?
4784 */
4785 if (intel_crtc->config.requested_mode.clock >
4786 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4787 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4788 }
4789
ff9ce46e
DV		 4790 /* only g4x and later have fancy bpc/dither controls */
4791 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4792 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4793 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4794 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4795 PIPECONF_DITHER_TYPE_SP;
84b046f3 4796
ff9ce46e
DV		 4797 switch (intel_crtc->config.pipe_bpp) {
4798 case 18:
4799 pipeconf |= PIPECONF_6BPC;
4800 break;
4801 case 24:
4802 pipeconf |= PIPECONF_8BPC;
4803 break;
4804 case 30:
4805 pipeconf |= PIPECONF_10BPC;
4806 break;
4807 default:
4808 /* Case prevented by intel_choose_pipe_bpp_dither. */
4809 BUG();
84b046f3
DV		 4810 }
4811 }
4812
4813 if (HAS_PIPE_CXSR(dev)) {
4814 if (intel_crtc->lowfreq_avail) {
4815 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4816 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4817 } else {
4818 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4819 }
4820 }
4821
84b046f3
DV		 4822 if (!IS_GEN2(dev) &&
4823 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4824 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4825 else
4826 pipeconf |= PIPECONF_PROGRESSIVE;
4827
9f11a9e4
DV		 4828 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4829 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4830
84b046f3
DV		 4831 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4832 POSTING_READ(PIPECONF(intel_crtc->pipe));
4833}
4834
f564048e 4835static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4836 int x, int y,
94352cf9 4837 struct drm_framebuffer *fb)
79e53945
JB		 4838{
4839 struct drm_device *dev = crtc->dev;
4840 struct drm_i915_private *dev_priv = dev->dev_private;
4841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4842 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4843 int pipe = intel_crtc->pipe;
80824003 4844 int plane = intel_crtc->plane;
c751ce4f 4845 int refclk, num_connectors = 0;
652c393a 4846 intel_clock_t clock, reduced_clock;
84b046f3 4847 u32 dspcntr;
a16af721
DV		 4848 bool ok, has_reduced_clock = false;
4849 bool is_lvds = false;
5eddb70b 4850 struct intel_encoder *encoder;
d4906093 4851 const intel_limit_t *limit;
5c3b82e2 4852 int ret;
79e53945 4853
6c2b7c12 4854 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4855 switch (encoder->type) {
79e53945
JB		 4856 case INTEL_OUTPUT_LVDS:
4857 is_lvds = true;
4858 break;
79e53945 4859 }
43565a06 4860
c751ce4f 4861 num_connectors++;
79e53945
JB		 4862 }
4863
c65d77d8 4864 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4865
d4906093
ML		 4866 /*
4867 * Returns a set of divisors for the desired target clock with the given
4868 * refclk, or FALSE. The returned values represent the clock equation:
4869 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4870 */
1b894b59 4871 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4872 ok = dev_priv->display.find_dpll(limit, crtc,
4873 intel_crtc->config.port_clock,
ee9300bb
DV		 4874 refclk, NULL, &clock);
4875 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4876 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4877 return -EINVAL;
79e53945
JB		 4878 }
4879
ddc9003c 4880 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4881 /*
4882 * Ensure we match the reduced clock's P to the target clock.
4883 * If the clocks don't match, we can't switch the display clock
4884 * by using the FP0/FP1. In such case we will disable the LVDS
4885 * downclock feature.
4886 */
ee9300bb
DV		 4887 has_reduced_clock =
4888 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4889 dev_priv->lvds_downclock,
ee9300bb 4890 refclk, &clock,
5eddb70b 4891 &reduced_clock);
7026d4ac 4892 }
f47709a9
DV		 4893 /* Compat-code for transition, will disappear. */
4894 if (!intel_crtc->config.clock_set) {
4895 intel_crtc->config.dpll.n = clock.n;
4896 intel_crtc->config.dpll.m1 = clock.m1;
4897 intel_crtc->config.dpll.m2 = clock.m2;
4898 intel_crtc->config.dpll.p1 = clock.p1;
4899 intel_crtc->config.dpll.p2 = clock.p2;
4900 }
7026d4ac 4901
eb1cbe48 4902 if (IS_GEN2(dev))
8a654f3b 4903 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4904 has_reduced_clock ? &reduced_clock : NULL,
4905 num_connectors);
a0c4da24 4906 else if (IS_VALLEYVIEW(dev))
f47709a9 4907 vlv_update_pll(intel_crtc);
79e53945 4908 else
f47709a9 4909 i9xx_update_pll(intel_crtc,
eb1cbe48 4910 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4911 num_connectors);
79e53945 4912
79e53945
JB		 4913 /* Set up the display plane register */
4914 dspcntr = DISPPLANE_GAMMA_ENABLE;
4915
da6ecc5d
JB		 4916 if (!IS_VALLEYVIEW(dev)) {
4917 if (pipe == 0)
4918 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4919 else
4920 dspcntr |= DISPPLANE_SEL_PIPE_B;
4921 }
79e53945 4922
8a654f3b 4923 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4924
4925 /* pipesrc and dspsize control the size that is scaled from,
4926 * which should always be the user's requested size.
79e53945 4927 */
929c77fb
EA		 4928 I915_WRITE(DSPSIZE(plane),
4929 ((mode->vdisplay - 1) << 16) |
4930 (mode->hdisplay - 1));
4931 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4932
84b046f3
DV		 4933 i9xx_set_pipeconf(intel_crtc);
4934
f564048e
EA		 4935 I915_WRITE(DSPCNTR(plane), dspcntr);
4936 POSTING_READ(DSPCNTR(plane));
4937
94352cf9 4938 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4939
4940 intel_update_watermarks(dev);
4941
f564048e
EA		 4942 return ret;
4943}
4944
2fa2fe9a
DV		 4945static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4946 struct intel_crtc_config *pipe_config)
4947{
4948 struct drm_device *dev = crtc->base.dev;
4949 struct drm_i915_private *dev_priv = dev->dev_private;
4950 uint32_t tmp;
4951
4952 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 4953 if (!(tmp & PFIT_ENABLE))
4954 return;
2fa2fe9a 4955
06922821 4956 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 4957 if (INTEL_INFO(dev)->gen < 4) {
4958 if (crtc->pipe != PIPE_B)
4959 return;
2fa2fe9a
DV		 4960 } else {
4961 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4962 return;
4963 }
4964
06922821 4965 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 4966 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4967 if (INTEL_INFO(dev)->gen < 5)
4968 pipe_config->gmch_pfit.lvds_border_bits =
4969 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4970}
4971
0e8ffe1b
DV		 4972static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4973 struct intel_crtc_config *pipe_config)
4974{
4975 struct drm_device *dev = crtc->base.dev;
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 uint32_t tmp;
4978
e143a21c 4979 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 4980 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4981
0e8ffe1b
DV		 4982 tmp = I915_READ(PIPECONF(crtc->pipe));
4983 if (!(tmp & PIPECONF_ENABLE))
4984 return false;
4985
4f56d12e
VS		 4986 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4987 switch (tmp & PIPECONF_BPC_MASK) {
4988 case PIPECONF_6BPC:
4989 pipe_config->pipe_bpp = 18;
4990 break;
4991 case PIPECONF_8BPC:
4992 pipe_config->pipe_bpp = 24;
4993 break;
4994 case PIPECONF_10BPC:
4995 pipe_config->pipe_bpp = 30;
4996 break;
4997 default:
4998 break;
4999 }
5000 }
5001
1bd1bd80
DV		 5002 intel_get_pipe_timings(crtc, pipe_config);
5003
2fa2fe9a
DV		 5004 i9xx_get_pfit_config(crtc, pipe_config);
5005
6c49f241
DV		 5006 if (INTEL_INFO(dev)->gen >= 4) {
5007 tmp = I915_READ(DPLL_MD(crtc->pipe));
5008 pipe_config->pixel_multiplier =
5009 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5010 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5011 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5012 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5013 tmp = I915_READ(DPLL(crtc->pipe));
5014 pipe_config->pixel_multiplier =
5015 ((tmp & SDVO_MULTIPLIER_MASK)
5016 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5017 } else {
5018 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5019 * port and will be fixed up in the encoder->get_config
5020 * function. */
5021 pipe_config->pixel_multiplier = 1;
5022 }
8bcc2795
DV		 5023 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5024 if (!IS_VALLEYVIEW(dev)) {
5025 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5026 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5027 } else {
5028 /* Mask out read-only status bits. */
5029 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5030 DPLL_PORTC_READY_MASK |
5031 DPLL_PORTB_READY_MASK);
8bcc2795 5032 }
6c49f241 5033
0e8ffe1b
DV		 5034 return true;
5035}
5036
dde86e2d 5037static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5038{
5039 struct drm_i915_private *dev_priv = dev->dev_private;
5040 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5041 struct intel_encoder *encoder;
74cfd7ac 5042 u32 val, final;
13d83a67 5043 bool has_lvds = false;
199e5d79 5044 bool has_cpu_edp = false;
199e5d79 5045 bool has_panel = false;
99eb6a01
KP		 5046 bool has_ck505 = false;
5047 bool can_ssc = false;
13d83a67
JB		 5048
5049 /* We need to take the global config into account */
199e5d79
KP		 5050 list_for_each_entry(encoder, &mode_config->encoder_list,
5051 base.head) {
5052 switch (encoder->type) {
5053 case INTEL_OUTPUT_LVDS:
5054 has_panel = true;
5055 has_lvds = true;
5056 break;
5057 case INTEL_OUTPUT_EDP:
5058 has_panel = true;
2de6905f 5059 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5060 has_cpu_edp = true;
5061 break;
13d83a67
JB		 5062 }
5063 }
5064
99eb6a01 5065 if (HAS_PCH_IBX(dev)) {
41aa3448 5066 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5067 can_ssc = has_ck505;
5068 } else {
5069 has_ck505 = false;
5070 can_ssc = true;
5071 }
5072
2de6905f
ID		 5073 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5074 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5075
5076 /* Ironlake: try to setup display ref clock before DPLL
5077 * enabling. This is only under driver's control after
5078 * PCH B stepping, previous chipset stepping should be
5079 * ignoring this setting.
5080 */
74cfd7ac
CW		 5081 val = I915_READ(PCH_DREF_CONTROL);
5082
5083 /* As we must carefully and slowly disable/enable each source in turn,
5084 * compute the final state we want first and check if we need to
5085 * make any changes at all.
5086 */
5087 final = val;
5088 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5089 if (has_ck505)
5090 final |= DREF_NONSPREAD_CK505_ENABLE;
5091 else
5092 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5093
5094 final &= ~DREF_SSC_SOURCE_MASK;
5095 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5096 final &= ~DREF_SSC1_ENABLE;
5097
5098 if (has_panel) {
5099 final |= DREF_SSC_SOURCE_ENABLE;
5100
5101 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5102 final |= DREF_SSC1_ENABLE;
5103
5104 if (has_cpu_edp) {
5105 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5106 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5107 else
5108 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5109 } else
5110 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5111 } else {
5112 final |= DREF_SSC_SOURCE_DISABLE;
5113 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5114 }
5115
5116 if (final == val)
5117 return;
5118
13d83a67 5119 /* Always enable nonspread source */
74cfd7ac 5120 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5121
99eb6a01 5122 if (has_ck505)
74cfd7ac 5123 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5124 else
74cfd7ac 5125 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5126
199e5d79 5127 if (has_panel) {
74cfd7ac
CW		 5128 val &= ~DREF_SSC_SOURCE_MASK;
5129 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5130
199e5d79 5131 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5132 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5133 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5134 val |= DREF_SSC1_ENABLE;
e77166b5 5135 } else
74cfd7ac 5136 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5137
5138 /* Get SSC going before enabling the outputs */
74cfd7ac 5139 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5140 POSTING_READ(PCH_DREF_CONTROL);
5141 udelay(200);
5142
74cfd7ac 5143 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5144
5145 /* Enable CPU source on CPU attached eDP */
199e5d79 5146 if (has_cpu_edp) {
99eb6a01 5147 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5148 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5149 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5150 }
13d83a67 5151 else
74cfd7ac 5152 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5153 } else
74cfd7ac 5154 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5155
74cfd7ac 5156 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5157 POSTING_READ(PCH_DREF_CONTROL);
5158 udelay(200);
5159 } else {
5160 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5161
74cfd7ac 5162 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5163
5164 /* Turn off CPU output */
74cfd7ac 5165 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5166
74cfd7ac 5167 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5168 POSTING_READ(PCH_DREF_CONTROL);
5169 udelay(200);
5170
5171 /* Turn off the SSC source */
74cfd7ac
CW		 5172 val &= ~DREF_SSC_SOURCE_MASK;
5173 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5174
5175 /* Turn off SSC1 */
74cfd7ac 5176 val &= ~DREF_SSC1_ENABLE;
199e5d79 5177
74cfd7ac 5178 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5179 POSTING_READ(PCH_DREF_CONTROL);
5180 udelay(200);
5181 }
74cfd7ac
CW		 5182
5183 BUG_ON(val != final);
13d83a67
JB		 5184}
5185
f31f2d55 5186static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5187{
f31f2d55 5188 uint32_t tmp;
dde86e2d 5189
0ff066a9
PZ		 5190 tmp = I915_READ(SOUTH_CHICKEN2);
5191 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5192 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5193
0ff066a9
PZ		 5194 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5195 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5196 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5197
0ff066a9
PZ		 5198 tmp = I915_READ(SOUTH_CHICKEN2);
5199 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5200 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5201
0ff066a9
PZ		 5202 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5203 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5204 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5205}
5206
5207/* WaMPhyProgramming:hsw */
5208static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5209{
5210 uint32_t tmp;
dde86e2d
PZ		 5211
5212 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5213 tmp &= ~(0xFF << 24);
5214 tmp |= (0x12 << 24);
5215 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5216
dde86e2d
PZ		 5217 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5218 tmp |= (1 << 11);
5219 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5220
5221 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5222 tmp |= (1 << 11);
5223 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5224
dde86e2d
PZ		 5225 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5226 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5227 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5228
5229 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5230 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5231 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5232
0ff066a9
PZ		 5233 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5234 tmp &= ~(7 << 13);
5235 tmp |= (5 << 13);
5236 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5237
0ff066a9
PZ		 5238 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5239 tmp &= ~(7 << 13);
5240 tmp |= (5 << 13);
5241 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5242
5243 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5244 tmp &= ~0xFF;
5245 tmp |= 0x1C;
5246 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5247
5248 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5249 tmp &= ~0xFF;
5250 tmp |= 0x1C;
5251 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5252
5253 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5254 tmp &= ~(0xFF << 16);
5255 tmp |= (0x1C << 16);
5256 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5259 tmp &= ~(0xFF << 16);
5260 tmp |= (0x1C << 16);
5261 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5262
0ff066a9
PZ		 5263 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5264 tmp |= (1 << 27);
5265 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5266
0ff066a9
PZ		 5267 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5268 tmp |= (1 << 27);
5269 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5270
0ff066a9
PZ		 5271 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5272 tmp &= ~(0xF << 28);
5273 tmp |= (4 << 28);
5274 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5275
0ff066a9
PZ		 5276 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5277 tmp &= ~(0xF << 28);
5278 tmp |= (4 << 28);
5279 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5280}
5281
2fa86a1f
PZ		 5282/* Implements 3 different sequences from BSpec chapter "Display iCLK
5283 * Programming" based on the parameters passed:
5284 * - Sequence to enable CLKOUT_DP
5285 * - Sequence to enable CLKOUT_DP without spread
5286 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5287 */
5288static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5289 bool with_fdi)
f31f2d55
PZ		 5290{
5291 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5292 uint32_t reg, tmp;
5293
5294 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5295 with_spread = true;
5296 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5297 with_fdi, "LP PCH doesn't have FDI\n"))
5298 with_fdi = false;
f31f2d55
PZ		 5299
5300 mutex_lock(&dev_priv->dpio_lock);
5301
5302 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5303 tmp &= ~SBI_SSCCTL_DISABLE;
5304 tmp |= SBI_SSCCTL_PATHALT;
5305 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5306
5307 udelay(24);
5308
2fa86a1f
PZ		 5309 if (with_spread) {
5310 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5311 tmp &= ~SBI_SSCCTL_PATHALT;
5312 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5313
2fa86a1f
PZ		 5314 if (with_fdi) {
5315 lpt_reset_fdi_mphy(dev_priv);
5316 lpt_program_fdi_mphy(dev_priv);
5317 }
5318 }
dde86e2d 5319
2fa86a1f
PZ		 5320 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5321 SBI_GEN0 : SBI_DBUFF0;
5322 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5323 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5324 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5325
5326 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5327}
5328
47701c3b
PZ		 5329/* Sequence to disable CLKOUT_DP */
5330static void lpt_disable_clkout_dp(struct drm_device *dev)
5331{
5332 struct drm_i915_private *dev_priv = dev->dev_private;
5333 uint32_t reg, tmp;
5334
5335 mutex_lock(&dev_priv->dpio_lock);
5336
5337 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5338 SBI_GEN0 : SBI_DBUFF0;
5339 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5340 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5341 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5342
5343 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5344 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5345 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5346 tmp |= SBI_SSCCTL_PATHALT;
5347 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5348 udelay(32);
5349 }
5350 tmp |= SBI_SSCCTL_DISABLE;
5351 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5352 }
5353
5354 mutex_unlock(&dev_priv->dpio_lock);
5355}
5356
bf8fa3d3
PZ		 5357static void lpt_init_pch_refclk(struct drm_device *dev)
5358{
5359 struct drm_mode_config *mode_config = &dev->mode_config;
5360 struct intel_encoder *encoder;
5361 bool has_vga = false;
5362
5363 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5364 switch (encoder->type) {
5365 case INTEL_OUTPUT_ANALOG:
5366 has_vga = true;
5367 break;
5368 }
5369 }
5370
47701c3b
PZ		 5371 if (has_vga)
5372 lpt_enable_clkout_dp(dev, true, true);
5373 else
5374 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5375}
5376
dde86e2d
PZ		 5377/*
5378 * Initialize reference clocks when the driver loads
5379 */
5380void intel_init_pch_refclk(struct drm_device *dev)
5381{
5382 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5383 ironlake_init_pch_refclk(dev);
5384 else if (HAS_PCH_LPT(dev))
5385 lpt_init_pch_refclk(dev);
5386}
5387
d9d444cb
JB		 5388static int ironlake_get_refclk(struct drm_crtc *crtc)
5389{
5390 struct drm_device *dev = crtc->dev;
5391 struct drm_i915_private *dev_priv = dev->dev_private;
5392 struct intel_encoder *encoder;
d9d444cb
JB		 5393 int num_connectors = 0;
5394 bool is_lvds = false;
5395
6c2b7c12 5396 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5397 switch (encoder->type) {
5398 case INTEL_OUTPUT_LVDS:
5399 is_lvds = true;
5400 break;
d9d444cb
JB		 5401 }
5402 num_connectors++;
5403 }
5404
5405 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5406 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5407 dev_priv->vbt.lvds_ssc_freq);
5408 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5409 }
5410
5411 return 120000;
5412}
5413
6ff93609 5414static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5415{
c8203565 5416 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5418 int pipe = intel_crtc->pipe;
c8203565
PZ		 5419 uint32_t val;
5420
78114071 5421 val = 0;
c8203565 5422
965e0c48 5423 switch (intel_crtc->config.pipe_bpp) {
c8203565 5424 case 18:
dfd07d72 5425 val |= PIPECONF_6BPC;
c8203565
PZ		 5426 break;
5427 case 24:
dfd07d72 5428 val |= PIPECONF_8BPC;
c8203565
PZ		 5429 break;
5430 case 30:
dfd07d72 5431 val |= PIPECONF_10BPC;
c8203565
PZ		 5432 break;
5433 case 36:
dfd07d72 5434 val |= PIPECONF_12BPC;
c8203565
PZ		 5435 break;
5436 default:
cc769b62
PZ		 5437 /* Case prevented by intel_choose_pipe_bpp_dither. */
5438 BUG();
c8203565
PZ		 5439 }
5440
d8b32247 5441 if (intel_crtc->config.dither)
c8203565
PZ		 5442 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5443
6ff93609 5444 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5445 val |= PIPECONF_INTERLACED_ILK;
5446 else
5447 val |= PIPECONF_PROGRESSIVE;
5448
50f3b016 5449 if (intel_crtc->config.limited_color_range)
3685a8f3 5450 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5451
c8203565
PZ		 5452 I915_WRITE(PIPECONF(pipe), val);
5453 POSTING_READ(PIPECONF(pipe));
5454}
5455
86d3efce
VS		 5456/*
5457 * Set up the pipe CSC unit.
5458 *
5459 * Currently only full range RGB to limited range RGB conversion
5460 * is supported, but eventually this should handle various
5461 * RGB<->YCbCr scenarios as well.
5462 */
50f3b016 5463static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5464{
5465 struct drm_device *dev = crtc->dev;
5466 struct drm_i915_private *dev_priv = dev->dev_private;
5467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5468 int pipe = intel_crtc->pipe;
5469 uint16_t coeff = 0x7800; /* 1.0 */
5470
5471 /*
5472 * TODO: Check what kind of values actually come out of the pipe
5473 * with these coeff/postoff values and adjust to get the best
5474 * accuracy. Perhaps we even need to take the bpc value into
5475 * consideration.
5476 */
5477
50f3b016 5478 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5479 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5480
5481 /*
5482 * GY/GU and RY/RU should be the other way around according
5483 * to BSpec, but reality doesn't agree. Just set them up in
5484 * a way that results in the correct picture.
5485 */
5486 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5487 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5488
5489 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5490 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5491
5492 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5493 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5494
5495 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5496 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5497 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5498
5499 if (INTEL_INFO(dev)->gen > 6) {
5500 uint16_t postoff = 0;
5501
50f3b016 5502 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5503 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5504
5505 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5506 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5507 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5508
5509 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5510 } else {
5511 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5512
50f3b016 5513 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5514 mode |= CSC_BLACK_SCREEN_OFFSET;
5515
5516 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5517 }
5518}
5519
6ff93609 5520static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5521{
5522 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5524 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5525 uint32_t val;
5526
3eff4faa 5527 val = 0;
ee2b0b38 5528
d8b32247 5529 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5530 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5531
6ff93609 5532 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5533 val |= PIPECONF_INTERLACED_ILK;
5534 else
5535 val |= PIPECONF_PROGRESSIVE;
5536
702e7a56
PZ		 5537 I915_WRITE(PIPECONF(cpu_transcoder), val);
5538 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5539
5540 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5541 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5542}
5543
6591c6e4 5544static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5545 intel_clock_t *clock,
5546 bool *has_reduced_clock,
5547 intel_clock_t *reduced_clock)
5548{
5549 struct drm_device *dev = crtc->dev;
5550 struct drm_i915_private *dev_priv = dev->dev_private;
5551 struct intel_encoder *intel_encoder;
5552 int refclk;
d4906093 5553 const intel_limit_t *limit;
a16af721 5554 bool ret, is_lvds = false;
79e53945 5555
6591c6e4
PZ		 5556 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5557 switch (intel_encoder->type) {
79e53945
JB		 5558 case INTEL_OUTPUT_LVDS:
5559 is_lvds = true;
5560 break;
79e53945
JB		 5561 }
5562 }
5563
d9d444cb 5564 refclk = ironlake_get_refclk(crtc);
79e53945 5565
d4906093
ML		 5566 /*
5567 * Returns a set of divisors for the desired target clock with the given
5568 * refclk, or FALSE. The returned values represent the clock equation:
5569 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5570 */
1b894b59 5571 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5572 ret = dev_priv->display.find_dpll(limit, crtc,
5573 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5574 refclk, NULL, clock);
6591c6e4
PZ		 5575 if (!ret)
5576 return false;
cda4b7d3 5577
ddc9003c 5578 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5579 /*
5580 * Ensure we match the reduced clock's P to the target clock.
5581 * If the clocks don't match, we can't switch the display clock
5582 * by using the FP0/FP1. In such case we will disable the LVDS
5583 * downclock feature.
5584 */
ee9300bb
DV		 5585 *has_reduced_clock =
5586 dev_priv->display.find_dpll(limit, crtc,
5587 dev_priv->lvds_downclock,
5588 refclk, clock,
5589 reduced_clock);
652c393a 5590 }
61e9653f 5591
6591c6e4
PZ		 5592 return true;
5593}
5594
01a415fd
DV		 5595static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5596{
5597 struct drm_i915_private *dev_priv = dev->dev_private;
5598 uint32_t temp;
5599
5600 temp = I915_READ(SOUTH_CHICKEN1);
5601 if (temp & FDI_BC_BIFURCATION_SELECT)
5602 return;
5603
5604 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5605 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5606
5607 temp |= FDI_BC_BIFURCATION_SELECT;
5608 DRM_DEBUG_KMS("enabling fdi C rx\n");
5609 I915_WRITE(SOUTH_CHICKEN1, temp);
5610 POSTING_READ(SOUTH_CHICKEN1);
5611}
5612
ebfd86fd 5613static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5614{
5615 struct drm_device *dev = intel_crtc->base.dev;
5616 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5617
5618 switch (intel_crtc->pipe) {
5619 case PIPE_A:
ebfd86fd 5620 break;
01a415fd 5621 case PIPE_B:
ebfd86fd 5622 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5623 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5624 else
5625 cpt_enable_fdi_bc_bifurcation(dev);
5626
ebfd86fd 5627 break;
01a415fd 5628 case PIPE_C:
01a415fd
DV		 5629 cpt_enable_fdi_bc_bifurcation(dev);
5630
ebfd86fd 5631 break;
01a415fd
DV		 5632 default:
5633 BUG();
5634 }
5635}
5636
d4b1931c
PZ		 5637int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5638{
5639 /*
5640 * Account for spread spectrum to avoid
5641 * oversubscribing the link. Max center spread
5642 * is 2.5%; use 5% for safety's sake.
5643 */
5644 u32 bps = target_clock * bpp * 21 / 20;
5645 return bps / (link_bw * 8) + 1;
5646}
5647
7429e9d4 5648static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5649{
7429e9d4 5650 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5651}
5652
de13a2e3 5653static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5654 u32 *fp,
9a7c7890 5655 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5656{
de13a2e3 5657 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5658 struct drm_device *dev = crtc->dev;
5659 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5660 struct intel_encoder *intel_encoder;
5661 uint32_t dpll;
6cc5f341 5662 int factor, num_connectors = 0;
09ede541 5663 bool is_lvds = false, is_sdvo = false;
79e53945 5664
de13a2e3
PZ		 5665 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5666 switch (intel_encoder->type) {
79e53945
JB		 5667 case INTEL_OUTPUT_LVDS:
5668 is_lvds = true;
5669 break;
5670 case INTEL_OUTPUT_SDVO:
7d57382e 5671 case INTEL_OUTPUT_HDMI:
79e53945 5672 is_sdvo = true;
79e53945 5673 break;
79e53945 5674 }
43565a06 5675
c751ce4f 5676 num_connectors++;
79e53945 5677 }
79e53945 5678
c1858123 5679 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5680 factor = 21;
5681 if (is_lvds) {
5682 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5683 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5684 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5685 factor = 25;
09ede541 5686 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5687 factor = 20;
c1858123 5688
7429e9d4 5689 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5690 *fp |= FP_CB_TUNE;
2c07245f 5691
9a7c7890
DV		 5692 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5693 *fp2 |= FP_CB_TUNE;
5694
5eddb70b 5695 dpll = 0;
2c07245f 5696
a07d6787
EA		 5697 if (is_lvds)
5698 dpll |= DPLLB_MODE_LVDS;
5699 else
5700 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5701
ef1b460d
DV		 5702 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5703 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5704
5705 if (is_sdvo)
4a33e48d 5706 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5707 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5708 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5709
a07d6787 5710 /* compute bitmask from p1 value */
7429e9d4 5711 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5712 /* also FPA1 */
7429e9d4 5713 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5714
7429e9d4 5715 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5716 case 5:
5717 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5718 break;
5719 case 7:
5720 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5721 break;
5722 case 10:
5723 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5724 break;
5725 case 14:
5726 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5727 break;
79e53945
JB		 5728 }
5729
b4c09f3b 5730 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5731 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5732 else
5733 dpll |= PLL_REF_INPUT_DREFCLK;
5734
959e16d6 5735 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5736}
5737
5738static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5739 int x, int y,
5740 struct drm_framebuffer *fb)
5741{
5742 struct drm_device *dev = crtc->dev;
5743 struct drm_i915_private *dev_priv = dev->dev_private;
5744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5745 int pipe = intel_crtc->pipe;
5746 int plane = intel_crtc->plane;
5747 int num_connectors = 0;
5748 intel_clock_t clock, reduced_clock;
cbbab5bd 5749 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5750 bool ok, has_reduced_clock = false;
8b47047b 5751 bool is_lvds = false;
de13a2e3 5752 struct intel_encoder *encoder;
e2b78267 5753 struct intel_shared_dpll *pll;
de13a2e3 5754 int ret;
de13a2e3
PZ		 5755
5756 for_each_encoder_on_crtc(dev, crtc, encoder) {
5757 switch (encoder->type) {
5758 case INTEL_OUTPUT_LVDS:
5759 is_lvds = true;
5760 break;
de13a2e3
PZ		 5761 }
5762
5763 num_connectors++;
a07d6787 5764 }
79e53945 5765
5dc5298b
PZ		 5766 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5767 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5768
ff9a6750 5769 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5770 &has_reduced_clock, &reduced_clock);
ee9300bb 5771 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5772 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5773 return -EINVAL;
79e53945 5774 }
f47709a9
DV		 5775 /* Compat-code for transition, will disappear. */
5776 if (!intel_crtc->config.clock_set) {
5777 intel_crtc->config.dpll.n = clock.n;
5778 intel_crtc->config.dpll.m1 = clock.m1;
5779 intel_crtc->config.dpll.m2 = clock.m2;
5780 intel_crtc->config.dpll.p1 = clock.p1;
5781 intel_crtc->config.dpll.p2 = clock.p2;
5782 }
79e53945 5783
5dc5298b 5784 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5785 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5786 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5787 if (has_reduced_clock)
7429e9d4 5788 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5789
7429e9d4 5790 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5791 &fp, &reduced_clock,
5792 has_reduced_clock ? &fp2 : NULL);
5793
959e16d6 5794 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5795 intel_crtc->config.dpll_hw_state.fp0 = fp;
5796 if (has_reduced_clock)
5797 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5798 else
5799 intel_crtc->config.dpll_hw_state.fp1 = fp;
5800
b89a1d39 5801 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5802 if (pll == NULL) {
84f44ce7
VS		 5803 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5804 pipe_name(pipe));
4b645f14
JB		 5805 return -EINVAL;
5806 }
ee7b9f93 5807 } else
e72f9fbf 5808 intel_put_shared_dpll(intel_crtc);
79e53945 5809
03afc4a2
DV		 5810 if (intel_crtc->config.has_dp_encoder)
5811 intel_dp_set_m_n(intel_crtc);
79e53945 5812
bcd644e0
DV		 5813 if (is_lvds && has_reduced_clock && i915_powersave)
5814 intel_crtc->lowfreq_avail = true;
5815 else
5816 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5817
5818 if (intel_crtc->config.has_pch_encoder) {
5819 pll = intel_crtc_to_shared_dpll(intel_crtc);
5820
652c393a
JB		 5821 }
5822
8a654f3b 5823 intel_set_pipe_timings(intel_crtc);
5eddb70b 5824
ca3a0ff8 5825 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5826 intel_cpu_transcoder_set_m_n(intel_crtc,
5827 &intel_crtc->config.fdi_m_n);
5828 }
2c07245f 5829
ebfd86fd
DV		 5830 if (IS_IVYBRIDGE(dev))
5831 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5832
6ff93609 5833 ironlake_set_pipeconf(crtc);
79e53945 5834
a1f9e77e
PZ		 5835 /* Set up the display plane register */
5836 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5837 POSTING_READ(DSPCNTR(plane));
79e53945 5838
94352cf9 5839 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5840
5841 intel_update_watermarks(dev);
5842
1857e1da 5843 return ret;
79e53945
JB		 5844}
5845
72419203
DV		 5846static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5847 struct intel_crtc_config *pipe_config)
5848{
5849 struct drm_device *dev = crtc->base.dev;
5850 struct drm_i915_private *dev_priv = dev->dev_private;
5851 enum transcoder transcoder = pipe_config->cpu_transcoder;
5852
5853 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5854 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5855 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5856 & ~TU_SIZE_MASK;
5857 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5858 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5859 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5860}
5861
2fa2fe9a
DV		 5862static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5863 struct intel_crtc_config *pipe_config)
5864{
5865 struct drm_device *dev = crtc->base.dev;
5866 struct drm_i915_private *dev_priv = dev->dev_private;
5867 uint32_t tmp;
5868
5869 tmp = I915_READ(PF_CTL(crtc->pipe));
5870
5871 if (tmp & PF_ENABLE) {
fd4daa9c 5872 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 5873 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5874 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5875
5876 /* We currently do not free assignements of panel fitters on
5877 * ivb/hsw (since we don't use the higher upscaling modes which
5878 * differentiates them) so just WARN about this case for now. */
5879 if (IS_GEN7(dev)) {
5880 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5881 PF_PIPE_SEL_IVB(crtc->pipe));
5882 }
2fa2fe9a 5883 }
79e53945
JB		 5884}
5885
0e8ffe1b
DV		 5886static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5887 struct intel_crtc_config *pipe_config)
5888{
5889 struct drm_device *dev = crtc->base.dev;
5890 struct drm_i915_private *dev_priv = dev->dev_private;
5891 uint32_t tmp;
5892
e143a21c 5893 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5894 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5895
0e8ffe1b
DV		 5896 tmp = I915_READ(PIPECONF(crtc->pipe));
5897 if (!(tmp & PIPECONF_ENABLE))
5898 return false;
5899
4f56d12e
VS		 5900 switch (tmp & PIPECONF_BPC_MASK) {
5901 case PIPECONF_6BPC:
5902 pipe_config->pipe_bpp = 18;
5903 break;
5904 case PIPECONF_8BPC:
5905 pipe_config->pipe_bpp = 24;
5906 break;
5907 case PIPECONF_10BPC:
5908 pipe_config->pipe_bpp = 30;
5909 break;
5910 case PIPECONF_12BPC:
5911 pipe_config->pipe_bpp = 36;
5912 break;
5913 default:
5914 break;
5915 }
5916
ab9412ba 5917 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5918 struct intel_shared_dpll *pll;
5919
88adfff1
DV		 5920 pipe_config->has_pch_encoder = true;
5921
627eb5a3
DV		 5922 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5923 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5924 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5925
5926 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5927
c0d43d62 5928 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 5929 pipe_config->shared_dpll =
5930 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 5931 } else {
5932 tmp = I915_READ(PCH_DPLL_SEL);
5933 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5934 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5935 else
5936 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5937 }
66e985c0
DV		 5938
5939 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5940
5941 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5942 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5943
5944 tmp = pipe_config->dpll_hw_state.dpll;
5945 pipe_config->pixel_multiplier =
5946 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5947 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5948 } else {
5949 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5950 }
5951
1bd1bd80
DV		 5952 intel_get_pipe_timings(crtc, pipe_config);
5953
2fa2fe9a
DV		 5954 ironlake_get_pfit_config(crtc, pipe_config);
5955
0e8ffe1b
DV		 5956 return true;
5957}
5958
be256dc7
PZ		 5959static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
5960{
5961 struct drm_device *dev = dev_priv->dev;
5962 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
5963 struct intel_crtc *crtc;
5964 unsigned long irqflags;
bd633a7c 5965 uint32_t val;
be256dc7
PZ		 5966
5967 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
5968 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
5969 pipe_name(crtc->pipe));
5970
5971 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
5972 WARN(plls->spll_refcount, "SPLL enabled\n");
5973 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
5974 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
5975 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
5976 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
5977 "CPU PWM1 enabled\n");
5978 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
5979 "CPU PWM2 enabled\n");
5980 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
5981 "PCH PWM1 enabled\n");
5982 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
5983 "Utility pin enabled\n");
5984 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
5985
5986 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5987 val = I915_READ(DEIMR);
5988 WARN((val & ~DE_PCH_EVENT_IVB) != val,
5989 "Unexpected DEIMR bits enabled: 0x%x\n", val);
5990 val = I915_READ(SDEIMR);
bd633a7c 5991 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 5992 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
5993 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5994}
5995
5996/*
5997 * This function implements pieces of two sequences from BSpec:
5998 * - Sequence for display software to disable LCPLL
5999 * - Sequence for display software to allow package C8+
6000 * The steps implemented here are just the steps that actually touch the LCPLL
6001 * register. Callers should take care of disabling all the display engine
6002 * functions, doing the mode unset, fixing interrupts, etc.
6003 */
6004void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6005 bool switch_to_fclk, bool allow_power_down)
6006{
6007 uint32_t val;
6008
6009 assert_can_disable_lcpll(dev_priv);
6010
6011 val = I915_READ(LCPLL_CTL);
6012
6013 if (switch_to_fclk) {
6014 val |= LCPLL_CD_SOURCE_FCLK;
6015 I915_WRITE(LCPLL_CTL, val);
6016
6017 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6018 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6019 DRM_ERROR("Switching to FCLK failed\n");
6020
6021 val = I915_READ(LCPLL_CTL);
6022 }
6023
6024 val |= LCPLL_PLL_DISABLE;
6025 I915_WRITE(LCPLL_CTL, val);
6026 POSTING_READ(LCPLL_CTL);
6027
6028 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6029 DRM_ERROR("LCPLL still locked\n");
6030
6031 val = I915_READ(D_COMP);
6032 val |= D_COMP_COMP_DISABLE;
6033 I915_WRITE(D_COMP, val);
6034 POSTING_READ(D_COMP);
6035 ndelay(100);
6036
6037 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6038 DRM_ERROR("D_COMP RCOMP still in progress\n");
6039
6040 if (allow_power_down) {
6041 val = I915_READ(LCPLL_CTL);
6042 val |= LCPLL_POWER_DOWN_ALLOW;
6043 I915_WRITE(LCPLL_CTL, val);
6044 POSTING_READ(LCPLL_CTL);
6045 }
6046}
6047
6048/*
6049 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6050 * source.
6051 */
6052void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6053{
6054 uint32_t val;
6055
6056 val = I915_READ(LCPLL_CTL);
6057
6058 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6059 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6060 return;
6061
215733fa
PZ		 6062 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6063 * we'll hang the machine! */
6064 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6065
be256dc7
PZ		 6066 if (val & LCPLL_POWER_DOWN_ALLOW) {
6067 val &= ~LCPLL_POWER_DOWN_ALLOW;
6068 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6069 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6070 }
6071
6072 val = I915_READ(D_COMP);
6073 val |= D_COMP_COMP_FORCE;
6074 val &= ~D_COMP_COMP_DISABLE;
6075 I915_WRITE(D_COMP, val);
35d8f2eb 6076 POSTING_READ(D_COMP);
be256dc7
PZ		 6077
6078 val = I915_READ(LCPLL_CTL);
6079 val &= ~LCPLL_PLL_DISABLE;
6080 I915_WRITE(LCPLL_CTL, val);
6081
6082 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6083 DRM_ERROR("LCPLL not locked yet\n");
6084
6085 if (val & LCPLL_CD_SOURCE_FCLK) {
6086 val = I915_READ(LCPLL_CTL);
6087 val &= ~LCPLL_CD_SOURCE_FCLK;
6088 I915_WRITE(LCPLL_CTL, val);
6089
6090 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6091 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6092 DRM_ERROR("Switching back to LCPLL failed\n");
6093 }
215733fa
PZ		 6094
6095 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6096}
6097
c67a470b
PZ		 6098void hsw_enable_pc8_work(struct work_struct *__work)
6099{
6100 struct drm_i915_private *dev_priv =
6101 container_of(to_delayed_work(__work), struct drm_i915_private,
6102 pc8.enable_work);
6103 struct drm_device *dev = dev_priv->dev;
6104 uint32_t val;
6105
6106 if (dev_priv->pc8.enabled)
6107 return;
6108
6109 DRM_DEBUG_KMS("Enabling package C8+\n");
6110
6111 dev_priv->pc8.enabled = true;
6112
6113 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6114 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6115 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6116 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6117 }
6118
6119 lpt_disable_clkout_dp(dev);
6120 hsw_pc8_disable_interrupts(dev);
6121 hsw_disable_lcpll(dev_priv, true, true);
6122}
6123
6124static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6125{
6126 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6127 WARN(dev_priv->pc8.disable_count < 1,
6128 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6129
6130 dev_priv->pc8.disable_count--;
6131 if (dev_priv->pc8.disable_count != 0)
6132 return;
6133
6134 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6135 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6136}
6137
6138static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6139{
6140 struct drm_device *dev = dev_priv->dev;
6141 uint32_t val;
6142
6143 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6144 WARN(dev_priv->pc8.disable_count < 0,
6145 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6146
6147 dev_priv->pc8.disable_count++;
6148 if (dev_priv->pc8.disable_count != 1)
6149 return;
6150
6151 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6152 if (!dev_priv->pc8.enabled)
6153 return;
6154
6155 DRM_DEBUG_KMS("Disabling package C8+\n");
6156
6157 hsw_restore_lcpll(dev_priv);
6158 hsw_pc8_restore_interrupts(dev);
6159 lpt_init_pch_refclk(dev);
6160
6161 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6162 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6163 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6164 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6165 }
6166
6167 intel_prepare_ddi(dev);
6168 i915_gem_init_swizzling(dev);
6169 mutex_lock(&dev_priv->rps.hw_lock);
6170 gen6_update_ring_freq(dev);
6171 mutex_unlock(&dev_priv->rps.hw_lock);
6172 dev_priv->pc8.enabled = false;
6173}
6174
6175void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6176{
6177 mutex_lock(&dev_priv->pc8.lock);
6178 __hsw_enable_package_c8(dev_priv);
6179 mutex_unlock(&dev_priv->pc8.lock);
6180}
6181
6182void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6183{
6184 mutex_lock(&dev_priv->pc8.lock);
6185 __hsw_disable_package_c8(dev_priv);
6186 mutex_unlock(&dev_priv->pc8.lock);
6187}
6188
6189static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6190{
6191 struct drm_device *dev = dev_priv->dev;
6192 struct intel_crtc *crtc;
6193 uint32_t val;
6194
6195 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6196 if (crtc->base.enabled)
6197 return false;
6198
6199 /* This case is still possible since we have the i915.disable_power_well
6200 * parameter and also the KVMr or something else might be requesting the
6201 * power well. */
6202 val = I915_READ(HSW_PWR_WELL_DRIVER);
6203 if (val != 0) {
6204 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6205 return false;
6206 }
6207
6208 return true;
6209}
6210
6211/* Since we're called from modeset_global_resources there's no way to
6212 * symmetrically increase and decrease the refcount, so we use
6213 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6214 * or not.
6215 */
6216static void hsw_update_package_c8(struct drm_device *dev)
6217{
6218 struct drm_i915_private *dev_priv = dev->dev_private;
6219 bool allow;
6220
6221 if (!i915_enable_pc8)
6222 return;
6223
6224 mutex_lock(&dev_priv->pc8.lock);
6225
6226 allow = hsw_can_enable_package_c8(dev_priv);
6227
6228 if (allow == dev_priv->pc8.requirements_met)
6229 goto done;
6230
6231 dev_priv->pc8.requirements_met = allow;
6232
6233 if (allow)
6234 __hsw_enable_package_c8(dev_priv);
6235 else
6236 __hsw_disable_package_c8(dev_priv);
6237
6238done:
6239 mutex_unlock(&dev_priv->pc8.lock);
6240}
6241
6242static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6243{
6244 if (!dev_priv->pc8.gpu_idle) {
6245 dev_priv->pc8.gpu_idle = true;
6246 hsw_enable_package_c8(dev_priv);
6247 }
6248}
6249
6250static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6251{
6252 if (dev_priv->pc8.gpu_idle) {
6253 dev_priv->pc8.gpu_idle = false;
6254 hsw_disable_package_c8(dev_priv);
6255 }
be256dc7
PZ		 6256}
6257
d6dd9eb1
DV		 6258static void haswell_modeset_global_resources(struct drm_device *dev)
6259{
d6dd9eb1
DV		 6260 bool enable = false;
6261 struct intel_crtc *crtc;
d6dd9eb1
DV		 6262
6263 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6264 if (!crtc->base.enabled)
6265 continue;
d6dd9eb1 6266
fd4daa9c 6267 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6268 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6269 enable = true;
6270 }
6271
d6dd9eb1 6272 intel_set_power_well(dev, enable);
c67a470b
PZ		 6273
6274 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6275}
6276
09b4ddf9 6277static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6278 int x, int y,
6279 struct drm_framebuffer *fb)
6280{
6281 struct drm_device *dev = crtc->dev;
6282 struct drm_i915_private *dev_priv = dev->dev_private;
6283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6284 int plane = intel_crtc->plane;
09b4ddf9 6285 int ret;
09b4ddf9 6286
ff9a6750 6287 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6288 return -EINVAL;
6289
03afc4a2
DV		 6290 if (intel_crtc->config.has_dp_encoder)
6291 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6292
6293 intel_crtc->lowfreq_avail = false;
09b4ddf9 6294
8a654f3b 6295 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6296
ca3a0ff8 6297 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6298 intel_cpu_transcoder_set_m_n(intel_crtc,
6299 &intel_crtc->config.fdi_m_n);
6300 }
09b4ddf9 6301
6ff93609 6302 haswell_set_pipeconf(crtc);
09b4ddf9 6303
50f3b016 6304 intel_set_pipe_csc(crtc);
86d3efce 6305
09b4ddf9 6306 /* Set up the display plane register */
86d3efce 6307 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6308 POSTING_READ(DSPCNTR(plane));
6309
6310 ret = intel_pipe_set_base(crtc, x, y, fb);
6311
6312 intel_update_watermarks(dev);
6313
1f803ee5 6314 return ret;
79e53945
JB		 6315}
6316
0e8ffe1b
DV		 6317static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6318 struct intel_crtc_config *pipe_config)
6319{
6320 struct drm_device *dev = crtc->base.dev;
6321 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6322 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6323 uint32_t tmp;
6324
e143a21c 6325 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6326 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6327
eccb140b
DV		 6328 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6329 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6330 enum pipe trans_edp_pipe;
6331 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6332 default:
6333 WARN(1, "unknown pipe linked to edp transcoder\n");
6334 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6335 case TRANS_DDI_EDP_INPUT_A_ON:
6336 trans_edp_pipe = PIPE_A;
6337 break;
6338 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6339 trans_edp_pipe = PIPE_B;
6340 break;
6341 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6342 trans_edp_pipe = PIPE_C;
6343 break;
6344 }
6345
6346 if (trans_edp_pipe == crtc->pipe)
6347 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6348 }
6349
b97186f0 6350 if (!intel_display_power_enabled(dev,
eccb140b 6351 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6352 return false;
6353
eccb140b 6354 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6355 if (!(tmp & PIPECONF_ENABLE))
6356 return false;
6357
88adfff1 6358 /*
f196e6be 6359 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6360 * DDI E. So just check whether this pipe is wired to DDI E and whether
6361 * the PCH transcoder is on.
6362 */
eccb140b 6363 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6364 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6365 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6366 pipe_config->has_pch_encoder = true;
6367
627eb5a3
DV		 6368 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6369 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6370 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6371
6372 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6373 }
6374
1bd1bd80
DV		 6375 intel_get_pipe_timings(crtc, pipe_config);
6376
2fa2fe9a
DV		 6377 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6378 if (intel_display_power_enabled(dev, pfit_domain))
6379 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6380
42db64ef
PZ		 6381 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6382 (I915_READ(IPS_CTL) & IPS_ENABLE);
6383
6c49f241
DV		 6384 pipe_config->pixel_multiplier = 1;
6385
0e8ffe1b
DV		 6386 return true;
6387}
6388
f564048e 6389static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6390 int x, int y,
94352cf9 6391 struct drm_framebuffer *fb)
f564048e
EA		 6392{
6393 struct drm_device *dev = crtc->dev;
6394 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6395 struct intel_encoder *encoder;
0b701d27 6396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6397 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6398 int pipe = intel_crtc->pipe;
f564048e
EA		 6399 int ret;
6400
0b701d27 6401 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6402
b8cecdf5
DV		 6403 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6404
79e53945 6405 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6406
9256aa19
DV		 6407 if (ret != 0)
6408 return ret;
6409
6410 for_each_encoder_on_crtc(dev, crtc, encoder) {
6411 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6412 encoder->base.base.id,
6413 drm_get_encoder_name(&encoder->base),
6414 mode->base.id, mode->name);
36f2d1f1 6415 encoder->mode_set(encoder);
9256aa19
DV		 6416 }
6417
6418 return 0;
79e53945
JB		 6419}
6420
3a9627f4
WF		 6421static bool intel_eld_uptodate(struct drm_connector *connector,
6422 int reg_eldv, uint32_t bits_eldv,
6423 int reg_elda, uint32_t bits_elda,
6424 int reg_edid)
6425{
6426 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6427 uint8_t *eld = connector->eld;
6428 uint32_t i;
6429
6430 i = I915_READ(reg_eldv);
6431 i &= bits_eldv;
6432
6433 if (!eld[0])
6434 return !i;
6435
6436 if (!i)
6437 return false;
6438
6439 i = I915_READ(reg_elda);
6440 i &= ~bits_elda;
6441 I915_WRITE(reg_elda, i);
6442
6443 for (i = 0; i < eld[2]; i++)
6444 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6445 return false;
6446
6447 return true;
6448}
6449
e0dac65e
WF		 6450static void g4x_write_eld(struct drm_connector *connector,
6451 struct drm_crtc *crtc)
6452{
6453 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6454 uint8_t *eld = connector->eld;
6455 uint32_t eldv;
6456 uint32_t len;
6457 uint32_t i;
6458
6459 i = I915_READ(G4X_AUD_VID_DID);
6460
6461 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6462 eldv = G4X_ELDV_DEVCL_DEVBLC;
6463 else
6464 eldv = G4X_ELDV_DEVCTG;
6465
3a9627f4
WF		 6466 if (intel_eld_uptodate(connector,
6467 G4X_AUD_CNTL_ST, eldv,
6468 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6469 G4X_HDMIW_HDMIEDID))
6470 return;
6471
e0dac65e
WF		 6472 i = I915_READ(G4X_AUD_CNTL_ST);
6473 i &= ~(eldv | G4X_ELD_ADDR);
6474 len = (i >> 9) & 0x1f; /* ELD buffer size */
6475 I915_WRITE(G4X_AUD_CNTL_ST, i);
6476
6477 if (!eld[0])
6478 return;
6479
6480 len = min_t(uint8_t, eld[2], len);
6481 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6482 for (i = 0; i < len; i++)
6483 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6484
6485 i = I915_READ(G4X_AUD_CNTL_ST);
6486 i |= eldv;
6487 I915_WRITE(G4X_AUD_CNTL_ST, i);
6488}
6489
83358c85
WX		 6490static void haswell_write_eld(struct drm_connector *connector,
6491 struct drm_crtc *crtc)
6492{
6493 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6494 uint8_t *eld = connector->eld;
6495 struct drm_device *dev = crtc->dev;
7b9f35a6 6496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6497 uint32_t eldv;
6498 uint32_t i;
6499 int len;
6500 int pipe = to_intel_crtc(crtc)->pipe;
6501 int tmp;
6502
6503 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6504 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6505 int aud_config = HSW_AUD_CFG(pipe);
6506 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6507
6508
6509 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6510
6511 /* Audio output enable */
6512 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6513 tmp = I915_READ(aud_cntrl_st2);
6514 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6515 I915_WRITE(aud_cntrl_st2, tmp);
6516
6517 /* Wait for 1 vertical blank */
6518 intel_wait_for_vblank(dev, pipe);
6519
6520 /* Set ELD valid state */
6521 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6522 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6523 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6524 I915_WRITE(aud_cntrl_st2, tmp);
6525 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6526 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6527
6528 /* Enable HDMI mode */
6529 tmp = I915_READ(aud_config);
7e7cb34f 6530 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6531 /* clear N_programing_enable and N_value_index */
6532 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6533 I915_WRITE(aud_config, tmp);
6534
6535 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6536
6537 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6538 intel_crtc->eld_vld = true;
83358c85
WX		 6539
6540 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6541 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6542 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6543 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6544 } else
6545 I915_WRITE(aud_config, 0);
6546
6547 if (intel_eld_uptodate(connector,
6548 aud_cntrl_st2, eldv,
6549 aud_cntl_st, IBX_ELD_ADDRESS,
6550 hdmiw_hdmiedid))
6551 return;
6552
6553 i = I915_READ(aud_cntrl_st2);
6554 i &= ~eldv;
6555 I915_WRITE(aud_cntrl_st2, i);
6556
6557 if (!eld[0])
6558 return;
6559
6560 i = I915_READ(aud_cntl_st);
6561 i &= ~IBX_ELD_ADDRESS;
6562 I915_WRITE(aud_cntl_st, i);
6563 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6564 DRM_DEBUG_DRIVER("port num:%d\n", i);
6565
6566 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6567 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6568 for (i = 0; i < len; i++)
6569 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6570
6571 i = I915_READ(aud_cntrl_st2);
6572 i |= eldv;
6573 I915_WRITE(aud_cntrl_st2, i);
6574
6575}
6576
e0dac65e
WF		 6577static void ironlake_write_eld(struct drm_connector *connector,
6578 struct drm_crtc *crtc)
6579{
6580 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6581 uint8_t *eld = connector->eld;
6582 uint32_t eldv;
6583 uint32_t i;
6584 int len;
6585 int hdmiw_hdmiedid;
b6daa025 6586 int aud_config;
e0dac65e
WF		 6587 int aud_cntl_st;
6588 int aud_cntrl_st2;
9b138a83 6589 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6590
b3f33cbf 6591 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6592 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6593 aud_config = IBX_AUD_CFG(pipe);
6594 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6595 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6596 } else {
9b138a83
WX		 6597 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6598 aud_config = CPT_AUD_CFG(pipe);
6599 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6600 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6601 }
6602
9b138a83 6603 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6604
6605 i = I915_READ(aud_cntl_st);
9b138a83 6606 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6607 if (!i) {
6608 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6609 /* operate blindly on all ports */
1202b4c6
WF		 6610 eldv = IBX_ELD_VALIDB;
6611 eldv |= IBX_ELD_VALIDB << 4;
6612 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6613 } else {
2582a850 6614 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6615 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6616 }
6617
3a9627f4
WF		 6618 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6619 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6620 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6621 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6622 } else
6623 I915_WRITE(aud_config, 0);
e0dac65e 6624
3a9627f4
WF		 6625 if (intel_eld_uptodate(connector,
6626 aud_cntrl_st2, eldv,
6627 aud_cntl_st, IBX_ELD_ADDRESS,
6628 hdmiw_hdmiedid))
6629 return;
6630
e0dac65e
WF		 6631 i = I915_READ(aud_cntrl_st2);
6632 i &= ~eldv;
6633 I915_WRITE(aud_cntrl_st2, i);
6634
6635 if (!eld[0])
6636 return;
6637
e0dac65e 6638 i = I915_READ(aud_cntl_st);
1202b4c6 6639 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6640 I915_WRITE(aud_cntl_st, i);
6641
6642 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6643 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6644 for (i = 0; i < len; i++)
6645 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6646
6647 i = I915_READ(aud_cntrl_st2);
6648 i |= eldv;
6649 I915_WRITE(aud_cntrl_st2, i);
6650}
6651
6652void intel_write_eld(struct drm_encoder *encoder,
6653 struct drm_display_mode *mode)
6654{
6655 struct drm_crtc *crtc = encoder->crtc;
6656 struct drm_connector *connector;
6657 struct drm_device *dev = encoder->dev;
6658 struct drm_i915_private *dev_priv = dev->dev_private;
6659
6660 connector = drm_select_eld(encoder, mode);
6661 if (!connector)
6662 return;
6663
6664 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6665 connector->base.id,
6666 drm_get_connector_name(connector),
6667 connector->encoder->base.id,
6668 drm_get_encoder_name(connector->encoder));
6669
6670 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6671
6672 if (dev_priv->display.write_eld)
6673 dev_priv->display.write_eld(connector, crtc);
6674}
6675
79e53945
JB		 6676/** Loads the palette/gamma unit for the CRTC with the prepared values */
6677void intel_crtc_load_lut(struct drm_crtc *crtc)
6678{
6679 struct drm_device *dev = crtc->dev;
6680 struct drm_i915_private *dev_priv = dev->dev_private;
6681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6682 enum pipe pipe = intel_crtc->pipe;
6683 int palreg = PALETTE(pipe);
79e53945 6684 int i;
42db64ef 6685 bool reenable_ips = false;
79e53945
JB		 6686
6687 /* The clocks have to be on to load the palette. */
aed3f09d 6688 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6689 return;
6690
14420bd0
VS		 6691 if (!HAS_PCH_SPLIT(dev_priv->dev))
6692 assert_pll_enabled(dev_priv, pipe);
6693
f2b115e6 6694 /* use legacy palette for Ironlake */
bad720ff 6695 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6696 palreg = LGC_PALETTE(pipe);
6697
6698 /* Workaround : Do not read or write the pipe palette/gamma data while
6699 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6700 */
6701 if (intel_crtc->config.ips_enabled &&
6702 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6703 GAMMA_MODE_MODE_SPLIT)) {
6704 hsw_disable_ips(intel_crtc);
6705 reenable_ips = true;
6706 }
2c07245f 6707
79e53945
JB		 6708 for (i = 0; i < 256; i++) {
6709 I915_WRITE(palreg + 4 * i,
6710 (intel_crtc->lut_r[i] << 16) |
6711 (intel_crtc->lut_g[i] << 8) |
6712 intel_crtc->lut_b[i]);
6713 }
42db64ef
PZ		 6714
6715 if (reenable_ips)
6716 hsw_enable_ips(intel_crtc);
79e53945
JB		 6717}
6718
560b85bb
CW		 6719static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6720{
6721 struct drm_device *dev = crtc->dev;
6722 struct drm_i915_private *dev_priv = dev->dev_private;
6723 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6724 bool visible = base != 0;
6725 u32 cntl;
6726
6727 if (intel_crtc->cursor_visible == visible)
6728 return;
6729
9db4a9c7 6730 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6731 if (visible) {
6732 /* On these chipsets we can only modify the base whilst
6733 * the cursor is disabled.
6734 */
9db4a9c7 6735 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6736
6737 cntl &= ~(CURSOR_FORMAT_MASK);
6738 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6739 cntl |= CURSOR_ENABLE |
6740 CURSOR_GAMMA_ENABLE |
6741 CURSOR_FORMAT_ARGB;
6742 } else
6743 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6744 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6745
6746 intel_crtc->cursor_visible = visible;
6747}
6748
6749static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6750{
6751 struct drm_device *dev = crtc->dev;
6752 struct drm_i915_private *dev_priv = dev->dev_private;
6753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6754 int pipe = intel_crtc->pipe;
6755 bool visible = base != 0;
6756
6757 if (intel_crtc->cursor_visible != visible) {
548f245b 6758 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6759 if (base) {
6760 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6761 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6762 cntl |= pipe << 28; /* Connect to correct pipe */
6763 } else {
6764 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6765 cntl |= CURSOR_MODE_DISABLE;
6766 }
9db4a9c7 6767 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6768
6769 intel_crtc->cursor_visible = visible;
6770 }
6771 /* and commit changes on next vblank */
9db4a9c7 6772 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6773}
6774
65a21cd6
JB		 6775static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6776{
6777 struct drm_device *dev = crtc->dev;
6778 struct drm_i915_private *dev_priv = dev->dev_private;
6779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6780 int pipe = intel_crtc->pipe;
6781 bool visible = base != 0;
6782
6783 if (intel_crtc->cursor_visible != visible) {
6784 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6785 if (base) {
6786 cntl &= ~CURSOR_MODE;
6787 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6788 } else {
6789 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6790 cntl |= CURSOR_MODE_DISABLE;
6791 }
1f5d76db 6792 if (IS_HASWELL(dev)) {
86d3efce 6793 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6794 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6795 }
65a21cd6
JB		 6796 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6797
6798 intel_crtc->cursor_visible = visible;
6799 }
6800 /* and commit changes on next vblank */
6801 I915_WRITE(CURBASE_IVB(pipe), base);
6802}
6803
cda4b7d3 6804/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6805static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6806 bool on)
cda4b7d3
CW		 6807{
6808 struct drm_device *dev = crtc->dev;
6809 struct drm_i915_private *dev_priv = dev->dev_private;
6810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6811 int pipe = intel_crtc->pipe;
6812 int x = intel_crtc->cursor_x;
6813 int y = intel_crtc->cursor_y;
560b85bb 6814 u32 base, pos;
cda4b7d3
CW		 6815 bool visible;
6816
6817 pos = 0;
6818
6b383a7f 6819 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6820 base = intel_crtc->cursor_addr;
6821 if (x > (int) crtc->fb->width)
6822 base = 0;
6823
6824 if (y > (int) crtc->fb->height)
6825 base = 0;
6826 } else
6827 base = 0;
6828
6829 if (x < 0) {
6830 if (x + intel_crtc->cursor_width < 0)
6831 base = 0;
6832
6833 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6834 x = -x;
6835 }
6836 pos |= x << CURSOR_X_SHIFT;
6837
6838 if (y < 0) {
6839 if (y + intel_crtc->cursor_height < 0)
6840 base = 0;
6841
6842 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6843 y = -y;
6844 }
6845 pos |= y << CURSOR_Y_SHIFT;
6846
6847 visible = base != 0;
560b85bb 6848 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6849 return;
6850
0cd83aa9 6851 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6852 I915_WRITE(CURPOS_IVB(pipe), pos);
6853 ivb_update_cursor(crtc, base);
6854 } else {
6855 I915_WRITE(CURPOS(pipe), pos);
6856 if (IS_845G(dev) || IS_I865G(dev))
6857 i845_update_cursor(crtc, base);
6858 else
6859 i9xx_update_cursor(crtc, base);
6860 }
cda4b7d3
CW		 6861}
6862
79e53945 6863static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6864 struct drm_file *file,
79e53945
JB		 6865 uint32_t handle,
6866 uint32_t width, uint32_t height)
6867{
6868 struct drm_device *dev = crtc->dev;
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6871 struct drm_i915_gem_object *obj;
cda4b7d3 6872 uint32_t addr;
3f8bc370 6873 int ret;
79e53945 6874
79e53945
JB		 6875 /* if we want to turn off the cursor ignore width and height */
6876 if (!handle) {
28c97730 6877 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6878 addr = 0;
05394f39 6879 obj = NULL;
5004417d 6880 mutex_lock(&dev->struct_mutex);
3f8bc370 6881 goto finish;
79e53945
JB		 6882 }
6883
6884 /* Currently we only support 64x64 cursors */
6885 if (width != 64 || height != 64) {
6886 DRM_ERROR("we currently only support 64x64 cursors\n");
6887 return -EINVAL;
6888 }
6889
05394f39 6890 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6891 if (&obj->base == NULL)
79e53945
JB		 6892 return -ENOENT;
6893
05394f39 6894 if (obj->base.size < width * height * 4) {
79e53945 6895 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6896 ret = -ENOMEM;
6897 goto fail;
79e53945
JB		 6898 }
6899
71acb5eb 6900 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6901 mutex_lock(&dev->struct_mutex);
b295d1b6 6902 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6903 unsigned alignment;
6904
d9e86c0e
CW		 6905 if (obj->tiling_mode) {
6906 DRM_ERROR("cursor cannot be tiled\n");
6907 ret = -EINVAL;
6908 goto fail_locked;
6909 }
6910
693db184
CW		 6911 /* Note that the w/a also requires 2 PTE of padding following
6912 * the bo. We currently fill all unused PTE with the shadow
6913 * page and so we should always have valid PTE following the
6914 * cursor preventing the VT-d warning.
6915 */
6916 alignment = 0;
6917 if (need_vtd_wa(dev))
6918 alignment = 64*1024;
6919
6920 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6921 if (ret) {
6922 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6923 goto fail_locked;
e7b526bb
CW		 6924 }
6925
d9e86c0e
CW		 6926 ret = i915_gem_object_put_fence(obj);
6927 if (ret) {
2da3b9b9 6928 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6929 goto fail_unpin;
6930 }
6931
f343c5f6 6932 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 6933 } else {
6eeefaf3 6934 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6935 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6936 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6937 align);
71acb5eb
DA		 6938 if (ret) {
6939 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6940 goto fail_locked;
71acb5eb 6941 }
05394f39 6942 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6943 }
6944
a6c45cf0 6945 if (IS_GEN2(dev))
14b60391
JB		 6946 I915_WRITE(CURSIZE, (height << 12) | width);
6947
3f8bc370 6948 finish:
3f8bc370 6949 if (intel_crtc->cursor_bo) {
b295d1b6 6950 if (dev_priv->info->cursor_needs_physical) {
05394f39 6951 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6952 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6953 } else
cc98b413 6954 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 6955 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6956 }
80824003 6957
7f9872e0 6958 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6959
6960 intel_crtc->cursor_addr = addr;
05394f39 6961 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6962 intel_crtc->cursor_width = width;
6963 intel_crtc->cursor_height = height;
6964
f2f5f771
VS		 6965 if (intel_crtc->active)
6966 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6967
79e53945 6968 return 0;
e7b526bb 6969fail_unpin:
cc98b413 6970 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 6971fail_locked:
34b8686e 6972 mutex_unlock(&dev->struct_mutex);
bc9025bd 6973fail:
05394f39 6974 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6975 return ret;
79e53945
JB		 6976}
6977
6978static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6979{
79e53945 6980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6981
cda4b7d3
CW		 6982 intel_crtc->cursor_x = x;
6983 intel_crtc->cursor_y = y;
652c393a 6984
f2f5f771
VS		 6985 if (intel_crtc->active)
6986 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6987
6988 return 0;
6989}
6990
6991/** Sets the color ramps on behalf of RandR */
6992void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6993 u16 blue, int regno)
6994{
6995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6996
6997 intel_crtc->lut_r[regno] = red >> 8;
6998 intel_crtc->lut_g[regno] = green >> 8;
6999 intel_crtc->lut_b[regno] = blue >> 8;
7000}
7001
b8c00ac5
DA		 7002void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7003 u16 *blue, int regno)
7004{
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7006
7007 *red = intel_crtc->lut_r[regno] << 8;
7008 *green = intel_crtc->lut_g[regno] << 8;
7009 *blue = intel_crtc->lut_b[regno] << 8;
7010}
7011
79e53945 7012static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7013 u16 *blue, uint32_t start, uint32_t size)
79e53945 7014{
7203425a 7015 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7017
7203425a 7018 for (i = start; i < end; i++) {
79e53945
JB		 7019 intel_crtc->lut_r[i] = red[i] >> 8;
7020 intel_crtc->lut_g[i] = green[i] >> 8;
7021 intel_crtc->lut_b[i] = blue[i] >> 8;
7022 }
7023
7024 intel_crtc_load_lut(crtc);
7025}
7026
79e53945
JB		 7027/* VESA 640x480x72Hz mode to set on the pipe */
7028static struct drm_display_mode load_detect_mode = {
7029 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7030 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7031};
7032
d2dff872
CW		 7033static struct drm_framebuffer *
7034intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7035 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7036 struct drm_i915_gem_object *obj)
7037{
7038 struct intel_framebuffer *intel_fb;
7039 int ret;
7040
7041 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7042 if (!intel_fb) {
7043 drm_gem_object_unreference_unlocked(&obj->base);
7044 return ERR_PTR(-ENOMEM);
7045 }
7046
7047 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7048 if (ret) {
7049 drm_gem_object_unreference_unlocked(&obj->base);
7050 kfree(intel_fb);
7051 return ERR_PTR(ret);
7052 }
7053
7054 return &intel_fb->base;
7055}
7056
7057static u32
7058intel_framebuffer_pitch_for_width(int width, int bpp)
7059{
7060 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7061 return ALIGN(pitch, 64);
7062}
7063
7064static u32
7065intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7066{
7067 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7068 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7069}
7070
7071static struct drm_framebuffer *
7072intel_framebuffer_create_for_mode(struct drm_device *dev,
7073 struct drm_display_mode *mode,
7074 int depth, int bpp)
7075{
7076 struct drm_i915_gem_object *obj;
0fed39bd 7077 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7078
7079 obj = i915_gem_alloc_object(dev,
7080 intel_framebuffer_size_for_mode(mode, bpp));
7081 if (obj == NULL)
7082 return ERR_PTR(-ENOMEM);
7083
7084 mode_cmd.width = mode->hdisplay;
7085 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7086 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7087 bpp);
5ca0c34a 7088 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7089
7090 return intel_framebuffer_create(dev, &mode_cmd, obj);
7091}
7092
7093static struct drm_framebuffer *
7094mode_fits_in_fbdev(struct drm_device *dev,
7095 struct drm_display_mode *mode)
7096{
7097 struct drm_i915_private *dev_priv = dev->dev_private;
7098 struct drm_i915_gem_object *obj;
7099 struct drm_framebuffer *fb;
7100
7101 if (dev_priv->fbdev == NULL)
7102 return NULL;
7103
7104 obj = dev_priv->fbdev->ifb.obj;
7105 if (obj == NULL)
7106 return NULL;
7107
7108 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7109 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7110 fb->bits_per_pixel))
d2dff872
CW		 7111 return NULL;
7112
01f2c773 7113 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7114 return NULL;
7115
7116 return fb;
7117}
7118
d2434ab7 7119bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7120 struct drm_display_mode *mode,
8261b191 7121 struct intel_load_detect_pipe *old)
79e53945
JB		 7122{
7123 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7124 struct intel_encoder *intel_encoder =
7125 intel_attached_encoder(connector);
79e53945 7126 struct drm_crtc *possible_crtc;
4ef69c7a 7127 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7128 struct drm_crtc *crtc = NULL;
7129 struct drm_device *dev = encoder->dev;
94352cf9 7130 struct drm_framebuffer *fb;
79e53945
JB		 7131 int i = -1;
7132
d2dff872
CW		 7133 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7134 connector->base.id, drm_get_connector_name(connector),
7135 encoder->base.id, drm_get_encoder_name(encoder));
7136
79e53945
JB		 7137 /*
7138 * Algorithm gets a little messy:
7a5e4805 7139 *
79e53945
JB		 7140 * - if the connector already has an assigned crtc, use it (but make
7141 * sure it's on first)
7a5e4805 7142 *
79e53945
JB		 7143 * - try to find the first unused crtc that can drive this connector,
7144 * and use that if we find one
79e53945
JB		 7145 */
7146
7147 /* See if we already have a CRTC for this connector */
7148 if (encoder->crtc) {
7149 crtc = encoder->crtc;
8261b191 7150
7b24056b
DV		 7151 mutex_lock(&crtc->mutex);
7152
24218aac 7153 old->dpms_mode = connector->dpms;
8261b191
CW		 7154 old->load_detect_temp = false;
7155
7156 /* Make sure the crtc and connector are running */
24218aac
DV		 7157 if (connector->dpms != DRM_MODE_DPMS_ON)
7158 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7159
7173188d 7160 return true;
79e53945
JB		 7161 }
7162
7163 /* Find an unused one (if possible) */
7164 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7165 i++;
7166 if (!(encoder->possible_crtcs & (1 << i)))
7167 continue;
7168 if (!possible_crtc->enabled) {
7169 crtc = possible_crtc;
7170 break;
7171 }
79e53945
JB		 7172 }
7173
7174 /*
7175 * If we didn't find an unused CRTC, don't use any.
7176 */
7177 if (!crtc) {
7173188d
CW		 7178 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7179 return false;
79e53945
JB		 7180 }
7181
7b24056b 7182 mutex_lock(&crtc->mutex);
fc303101
DV		 7183 intel_encoder->new_crtc = to_intel_crtc(crtc);
7184 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7185
7186 intel_crtc = to_intel_crtc(crtc);
24218aac 7187 old->dpms_mode = connector->dpms;
8261b191 7188 old->load_detect_temp = true;
d2dff872 7189 old->release_fb = NULL;
79e53945 7190
6492711d
CW		 7191 if (!mode)
7192 mode = &load_detect_mode;
79e53945 7193
d2dff872
CW		 7194 /* We need a framebuffer large enough to accommodate all accesses
7195 * that the plane may generate whilst we perform load detection.
7196 * We can not rely on the fbcon either being present (we get called
7197 * during its initialisation to detect all boot displays, or it may
7198 * not even exist) or that it is large enough to satisfy the
7199 * requested mode.
7200 */
94352cf9
DV		 7201 fb = mode_fits_in_fbdev(dev, mode);
7202 if (fb == NULL) {
d2dff872 7203 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7204 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7205 old->release_fb = fb;
d2dff872
CW		 7206 } else
7207 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7208 if (IS_ERR(fb)) {
d2dff872 7209 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7210 mutex_unlock(&crtc->mutex);
0e8b3d3e 7211 return false;
79e53945 7212 }
79e53945 7213
c0c36b94 7214 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7215 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7216 if (old->release_fb)
7217 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7218 mutex_unlock(&crtc->mutex);
0e8b3d3e 7219 return false;
79e53945 7220 }
7173188d 7221
79e53945 7222 /* let the connector get through one full cycle before testing */
9d0498a2 7223 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7224 return true;
79e53945
JB		 7225}
7226
d2434ab7 7227void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7228 struct intel_load_detect_pipe *old)
79e53945 7229{
d2434ab7
DV		 7230 struct intel_encoder *intel_encoder =
7231 intel_attached_encoder(connector);
4ef69c7a 7232 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7233 struct drm_crtc *crtc = encoder->crtc;
79e53945 7234
d2dff872
CW		 7235 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7236 connector->base.id, drm_get_connector_name(connector),
7237 encoder->base.id, drm_get_encoder_name(encoder));
7238
8261b191 7239 if (old->load_detect_temp) {
fc303101
DV		 7240 to_intel_connector(connector)->new_encoder = NULL;
7241 intel_encoder->new_crtc = NULL;
7242 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7243
36206361
DV		 7244 if (old->release_fb) {
7245 drm_framebuffer_unregister_private(old->release_fb);
7246 drm_framebuffer_unreference(old->release_fb);
7247 }
d2dff872 7248
67c96400 7249 mutex_unlock(&crtc->mutex);
0622a53c 7250 return;
79e53945
JB		 7251 }
7252
c751ce4f 7253 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7254 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7255 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7256
7257 mutex_unlock(&crtc->mutex);
79e53945
JB		 7258}
7259
7260/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7261static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7262 struct intel_crtc_config *pipe_config)
79e53945 7263{
f1f644dc 7264 struct drm_device *dev = crtc->base.dev;
79e53945 7265 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7266 int pipe = pipe_config->cpu_transcoder;
548f245b 7267 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 7268 u32 fp;
7269 intel_clock_t clock;
7270
7271 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 7272 fp = I915_READ(FP0(pipe));
79e53945 7273 else
39adb7a5 7274 fp = I915_READ(FP1(pipe));
79e53945
JB		 7275
7276 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7277 if (IS_PINEVIEW(dev)) {
7278 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7279 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7280 } else {
7281 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7282 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7283 }
7284
a6c45cf0 7285 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7286 if (IS_PINEVIEW(dev))
7287 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7288 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7289 else
7290 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7291 DPLL_FPA01_P1_POST_DIV_SHIFT);
7292
7293 switch (dpll & DPLL_MODE_MASK) {
7294 case DPLLB_MODE_DAC_SERIAL:
7295 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7296 5 : 10;
7297 break;
7298 case DPLLB_MODE_LVDS:
7299 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7300 7 : 14;
7301 break;
7302 default:
28c97730 7303 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7304 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 7305 pipe_config->adjusted_mode.clock = 0;
7306 return;
79e53945
JB		 7307 }
7308
ac58c3f0
DV		 7309 if (IS_PINEVIEW(dev))
7310 pineview_clock(96000, &clock);
7311 else
7312 i9xx_clock(96000, &clock);
79e53945
JB		 7313 } else {
7314 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7315
7316 if (is_lvds) {
7317 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7318 DPLL_FPA01_P1_POST_DIV_SHIFT);
7319 clock.p2 = 14;
7320
7321 if ((dpll & PLL_REF_INPUT_MASK) ==
7322 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7323 /* XXX: might not be 66MHz */
ac58c3f0 7324 i9xx_clock(66000, &clock);
79e53945 7325 } else
ac58c3f0 7326 i9xx_clock(48000, &clock);
79e53945
JB		 7327 } else {
7328 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7329 clock.p1 = 2;
7330 else {
7331 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7332 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7333 }
7334 if (dpll & PLL_P2_DIVIDE_BY_4)
7335 clock.p2 = 4;
7336 else
7337 clock.p2 = 2;
7338
ac58c3f0 7339 i9xx_clock(48000, &clock);
79e53945
JB		 7340 }
7341 }
7342
a2dc53e7 7343 pipe_config->adjusted_mode.clock = clock.dot;
f1f644dc
JB		 7344}
7345
7346static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7347 struct intel_crtc_config *pipe_config)
7348{
7349 struct drm_device *dev = crtc->base.dev;
7350 struct drm_i915_private *dev_priv = dev->dev_private;
7351 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7352 int link_freq, repeat;
7353 u64 clock;
7354 u32 link_m, link_n;
7355
7356 repeat = pipe_config->pixel_multiplier;
7357
7358 /*
7359 * The calculation for the data clock is:
7360 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7361 * But we want to avoid losing precison if possible, so:
7362 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7363 *
7364 * and the link clock is simpler:
7365 * link_clock = (m * link_clock * repeat) / n
7366 */
7367
7368 /*
7369 * We need to get the FDI or DP link clock here to derive
7370 * the M/N dividers.
7371 *
7372 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7373 * For DP, it's either 1.62GHz or 2.7GHz.
7374 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7375 */
f1f644dc
JB		 7376 if (pipe_config->has_pch_encoder)
7377 link_freq = intel_fdi_link_freq(dev) * 10000;
7378 else
7379 link_freq = pipe_config->port_clock;
7380
7381 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7382 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7383
7384 if (!link_m || !link_n)
7385 return;
79e53945 7386
f1f644dc
JB		 7387 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7388 do_div(clock, link_n);
7389
7390 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 7391}
7392
7393/** Returns the currently programmed mode of the given pipe. */
7394struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7395 struct drm_crtc *crtc)
7396{
548f245b 7397 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7399 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7400 struct drm_display_mode *mode;
f1f644dc 7401 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7402 int htot = I915_READ(HTOTAL(cpu_transcoder));
7403 int hsync = I915_READ(HSYNC(cpu_transcoder));
7404 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7405 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7406
7407 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7408 if (!mode)
7409 return NULL;
7410
f1f644dc
JB		 7411 /*
7412 * Construct a pipe_config sufficient for getting the clock info
7413 * back out of crtc_clock_get.
7414 *
7415 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7416 * to use a real value here instead.
7417 */
e143a21c 7418 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB		 7419 pipe_config.pixel_multiplier = 1;
7420 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7421
7422 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7423 mode->hdisplay = (htot & 0xffff) + 1;
7424 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7425 mode->hsync_start = (hsync & 0xffff) + 1;
7426 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7427 mode->vdisplay = (vtot & 0xffff) + 1;
7428 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7429 mode->vsync_start = (vsync & 0xffff) + 1;
7430 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7431
7432 drm_mode_set_name(mode);
79e53945
JB		 7433
7434 return mode;
7435}
7436
3dec0095 7437static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7438{
7439 struct drm_device *dev = crtc->dev;
7440 drm_i915_private_t *dev_priv = dev->dev_private;
7441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7442 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7443 int dpll_reg = DPLL(pipe);
7444 int dpll;
652c393a 7445
bad720ff 7446 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7447 return;
7448
7449 if (!dev_priv->lvds_downclock_avail)
7450 return;
7451
dbdc6479 7452 dpll = I915_READ(dpll_reg);
652c393a 7453 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7454 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7455
8ac5a6d5 7456 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7457
7458 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7459 I915_WRITE(dpll_reg, dpll);
9d0498a2 7460 intel_wait_for_vblank(dev, pipe);
dbdc6479 7461
652c393a
JB		 7462 dpll = I915_READ(dpll_reg);
7463 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7464 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7465 }
652c393a
JB		 7466}
7467
7468static void intel_decrease_pllclock(struct drm_crtc *crtc)
7469{
7470 struct drm_device *dev = crtc->dev;
7471 drm_i915_private_t *dev_priv = dev->dev_private;
7472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7473
bad720ff 7474 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7475 return;
7476
7477 if (!dev_priv->lvds_downclock_avail)
7478 return;
7479
7480 /*
7481 * Since this is called by a timer, we should never get here in
7482 * the manual case.
7483 */
7484 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7485 int pipe = intel_crtc->pipe;
7486 int dpll_reg = DPLL(pipe);
7487 int dpll;
f6e5b160 7488
44d98a61 7489 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7490
8ac5a6d5 7491 assert_panel_unlocked(dev_priv, pipe);
652c393a 7492
dc257cf1 7493 dpll = I915_READ(dpll_reg);
652c393a
JB		 7494 dpll |= DISPLAY_RATE_SELECT_FPA1;
7495 I915_WRITE(dpll_reg, dpll);
9d0498a2 7496 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7497 dpll = I915_READ(dpll_reg);
7498 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7499 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7500 }
7501
7502}
7503
f047e395
CW		 7504void intel_mark_busy(struct drm_device *dev)
7505{
c67a470b
PZ		 7506 struct drm_i915_private *dev_priv = dev->dev_private;
7507
7508 hsw_package_c8_gpu_busy(dev_priv);
7509 i915_update_gfx_val(dev_priv);
f047e395
CW		 7510}
7511
7512void intel_mark_idle(struct drm_device *dev)
652c393a 7513{
c67a470b 7514 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7515 struct drm_crtc *crtc;
652c393a 7516
c67a470b
PZ		 7517 hsw_package_c8_gpu_idle(dev_priv);
7518
652c393a
JB		 7519 if (!i915_powersave)
7520 return;
7521
652c393a 7522 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7523 if (!crtc->fb)
7524 continue;
7525
725a5b54 7526 intel_decrease_pllclock(crtc);
652c393a 7527 }
652c393a
JB		 7528}
7529
c65355bb
CW		 7530void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7531 struct intel_ring_buffer *ring)
652c393a 7532{
f047e395
CW		 7533 struct drm_device *dev = obj->base.dev;
7534 struct drm_crtc *crtc;
652c393a 7535
f047e395 7536 if (!i915_powersave)
acb87dfb
CW		 7537 return;
7538
652c393a
JB		 7539 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7540 if (!crtc->fb)
7541 continue;
7542
c65355bb
CW		 7543 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7544 continue;
7545
7546 intel_increase_pllclock(crtc);
7547 if (ring && intel_fbc_enabled(dev))
7548 ring->fbc_dirty = true;
652c393a
JB		 7549 }
7550}
7551
79e53945
JB		 7552static void intel_crtc_destroy(struct drm_crtc *crtc)
7553{
7554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7555 struct drm_device *dev = crtc->dev;
7556 struct intel_unpin_work *work;
7557 unsigned long flags;
7558
7559 spin_lock_irqsave(&dev->event_lock, flags);
7560 work = intel_crtc->unpin_work;
7561 intel_crtc->unpin_work = NULL;
7562 spin_unlock_irqrestore(&dev->event_lock, flags);
7563
7564 if (work) {
7565 cancel_work_sync(&work->work);
7566 kfree(work);
7567 }
79e53945 7568
40ccc72b
MK		 7569 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7570
79e53945 7571 drm_crtc_cleanup(crtc);
67e77c5a 7572
79e53945
JB		 7573 kfree(intel_crtc);
7574}
7575
6b95a207
KH		 7576static void intel_unpin_work_fn(struct work_struct *__work)
7577{
7578 struct intel_unpin_work *work =
7579 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7580 struct drm_device *dev = work->crtc->dev;
6b95a207 7581
b4a98e57 7582 mutex_lock(&dev->struct_mutex);
1690e1eb 7583 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7584 drm_gem_object_unreference(&work->pending_flip_obj->base);
7585 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7586
b4a98e57
CW		 7587 intel_update_fbc(dev);
7588 mutex_unlock(&dev->struct_mutex);
7589
7590 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7591 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7592
6b95a207
KH		 7593 kfree(work);
7594}
7595
1afe3e9d 7596static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7597 struct drm_crtc *crtc)
6b95a207
KH		 7598{
7599 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7601 struct intel_unpin_work *work;
6b95a207
KH		 7602 unsigned long flags;
7603
7604 /* Ignore early vblank irqs */
7605 if (intel_crtc == NULL)
7606 return;
7607
7608 spin_lock_irqsave(&dev->event_lock, flags);
7609 work = intel_crtc->unpin_work;
e7d841ca
CW		 7610
7611 /* Ensure we don't miss a work->pending update ... */
7612 smp_rmb();
7613
7614 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7615 spin_unlock_irqrestore(&dev->event_lock, flags);
7616 return;
7617 }
7618
e7d841ca
CW		 7619 /* and that the unpin work is consistent wrt ->pending. */
7620 smp_rmb();
7621
6b95a207 7622 intel_crtc->unpin_work = NULL;
6b95a207 7623
45a066eb
RC		 7624 if (work->event)
7625 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7626
0af7e4df
MK		 7627 drm_vblank_put(dev, intel_crtc->pipe);
7628
6b95a207
KH		 7629 spin_unlock_irqrestore(&dev->event_lock, flags);
7630
2c10d571 7631 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7632
7633 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7634
7635 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7636}
7637
1afe3e9d
JB		 7638void intel_finish_page_flip(struct drm_device *dev, int pipe)
7639{
7640 drm_i915_private_t *dev_priv = dev->dev_private;
7641 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7642
49b14a5c 7643 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7644}
7645
7646void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7647{
7648 drm_i915_private_t *dev_priv = dev->dev_private;
7649 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7650
49b14a5c 7651 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7652}
7653
6b95a207
KH		 7654void intel_prepare_page_flip(struct drm_device *dev, int plane)
7655{
7656 drm_i915_private_t *dev_priv = dev->dev_private;
7657 struct intel_crtc *intel_crtc =
7658 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7659 unsigned long flags;
7660
e7d841ca
CW		 7661 /* NB: An MMIO update of the plane base pointer will also
7662 * generate a page-flip completion irq, i.e. every modeset
7663 * is also accompanied by a spurious intel_prepare_page_flip().
7664 */
6b95a207 7665 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7666 if (intel_crtc->unpin_work)
7667 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7668 spin_unlock_irqrestore(&dev->event_lock, flags);
7669}
7670
e7d841ca
CW		 7671inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7672{
7673 /* Ensure that the work item is consistent when activating it ... */
7674 smp_wmb();
7675 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7676 /* and that it is marked active as soon as the irq could fire. */
7677 smp_wmb();
7678}
7679
8c9f3aaf
JB		 7680static int intel_gen2_queue_flip(struct drm_device *dev,
7681 struct drm_crtc *crtc,
7682 struct drm_framebuffer *fb,
ed8d1975
KP		 7683 struct drm_i915_gem_object *obj,
7684 uint32_t flags)
8c9f3aaf
JB		 7685{
7686 struct drm_i915_private *dev_priv = dev->dev_private;
7687 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7688 u32 flip_mask;
6d90c952 7689 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7690 int ret;
7691
6d90c952 7692 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7693 if (ret)
83d4092b 7694 goto err;
8c9f3aaf 7695
6d90c952 7696 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7697 if (ret)
83d4092b 7698 goto err_unpin;
8c9f3aaf
JB		 7699
7700 /* Can't queue multiple flips, so wait for the previous
7701 * one to finish before executing the next.
7702 */
7703 if (intel_crtc->plane)
7704 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7705 else
7706 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7707 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7708 intel_ring_emit(ring, MI_NOOP);
7709 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7710 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7711 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7712 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7713 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7714
7715 intel_mark_page_flip_active(intel_crtc);
6d90c952 7716 intel_ring_advance(ring);
83d4092b
CW		 7717 return 0;
7718
7719err_unpin:
7720 intel_unpin_fb_obj(obj);
7721err:
8c9f3aaf
JB		 7722 return ret;
7723}
7724
7725static int intel_gen3_queue_flip(struct drm_device *dev,
7726 struct drm_crtc *crtc,
7727 struct drm_framebuffer *fb,
ed8d1975
KP		 7728 struct drm_i915_gem_object *obj,
7729 uint32_t flags)
8c9f3aaf
JB		 7730{
7731 struct drm_i915_private *dev_priv = dev->dev_private;
7732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7733 u32 flip_mask;
6d90c952 7734 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7735 int ret;
7736
6d90c952 7737 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7738 if (ret)
83d4092b 7739 goto err;
8c9f3aaf 7740
6d90c952 7741 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7742 if (ret)
83d4092b 7743 goto err_unpin;
8c9f3aaf
JB		 7744
7745 if (intel_crtc->plane)
7746 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7747 else
7748 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7749 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7750 intel_ring_emit(ring, MI_NOOP);
7751 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7752 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7753 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7754 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7755 intel_ring_emit(ring, MI_NOOP);
7756
e7d841ca 7757 intel_mark_page_flip_active(intel_crtc);
6d90c952 7758 intel_ring_advance(ring);
83d4092b
CW		 7759 return 0;
7760
7761err_unpin:
7762 intel_unpin_fb_obj(obj);
7763err:
8c9f3aaf
JB		 7764 return ret;
7765}
7766
7767static int intel_gen4_queue_flip(struct drm_device *dev,
7768 struct drm_crtc *crtc,
7769 struct drm_framebuffer *fb,
ed8d1975
KP		 7770 struct drm_i915_gem_object *obj,
7771 uint32_t flags)
8c9f3aaf
JB		 7772{
7773 struct drm_i915_private *dev_priv = dev->dev_private;
7774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7775 uint32_t pf, pipesrc;
6d90c952 7776 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7777 int ret;
7778
6d90c952 7779 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7780 if (ret)
83d4092b 7781 goto err;
8c9f3aaf 7782
6d90c952 7783 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7784 if (ret)
83d4092b 7785 goto err_unpin;
8c9f3aaf
JB		 7786
7787 /* i965+ uses the linear or tiled offsets from the
7788 * Display Registers (which do not change across a page-flip)
7789 * so we need only reprogram the base address.
7790 */
6d90c952
DV		 7791 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7792 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7793 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7794 intel_ring_emit(ring,
f343c5f6 7795 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7796 obj->tiling_mode);
8c9f3aaf
JB		 7797
7798 /* XXX Enabling the panel-fitter across page-flip is so far
7799 * untested on non-native modes, so ignore it for now.
7800 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7801 */
7802 pf = 0;
7803 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7804 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7805
7806 intel_mark_page_flip_active(intel_crtc);
6d90c952 7807 intel_ring_advance(ring);
83d4092b
CW		 7808 return 0;
7809
7810err_unpin:
7811 intel_unpin_fb_obj(obj);
7812err:
8c9f3aaf
JB		 7813 return ret;
7814}
7815
7816static int intel_gen6_queue_flip(struct drm_device *dev,
7817 struct drm_crtc *crtc,
7818 struct drm_framebuffer *fb,
ed8d1975
KP		 7819 struct drm_i915_gem_object *obj,
7820 uint32_t flags)
8c9f3aaf
JB		 7821{
7822 struct drm_i915_private *dev_priv = dev->dev_private;
7823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7824 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7825 uint32_t pf, pipesrc;
7826 int ret;
7827
6d90c952 7828 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7829 if (ret)
83d4092b 7830 goto err;
8c9f3aaf 7831
6d90c952 7832 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7833 if (ret)
83d4092b 7834 goto err_unpin;
8c9f3aaf 7835
6d90c952
DV		 7836 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7837 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7838 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7839 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7840
dc257cf1
DV		 7841 /* Contrary to the suggestions in the documentation,
7842 * "Enable Panel Fitter" does not seem to be required when page
7843 * flipping with a non-native mode, and worse causes a normal
7844 * modeset to fail.
7845 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7846 */
7847 pf = 0;
8c9f3aaf 7848 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7849 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7850
7851 intel_mark_page_flip_active(intel_crtc);
6d90c952 7852 intel_ring_advance(ring);
83d4092b
CW		 7853 return 0;
7854
7855err_unpin:
7856 intel_unpin_fb_obj(obj);
7857err:
8c9f3aaf
JB		 7858 return ret;
7859}
7860
7c9017e5
JB		 7861static int intel_gen7_queue_flip(struct drm_device *dev,
7862 struct drm_crtc *crtc,
7863 struct drm_framebuffer *fb,
ed8d1975
KP		 7864 struct drm_i915_gem_object *obj,
7865 uint32_t flags)
7c9017e5
JB		 7866{
7867 struct drm_i915_private *dev_priv = dev->dev_private;
7868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7869 struct intel_ring_buffer *ring;
cb05d8de 7870 uint32_t plane_bit = 0;
ffe74d75
CW		 7871 int len, ret;
7872
7873 ring = obj->ring;
1c5fd085 7874 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 7875 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7876
7877 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7878 if (ret)
83d4092b 7879 goto err;
7c9017e5 7880
cb05d8de
DV		 7881 switch(intel_crtc->plane) {
7882 case PLANE_A:
7883 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7884 break;
7885 case PLANE_B:
7886 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7887 break;
7888 case PLANE_C:
7889 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7890 break;
7891 default:
7892 WARN_ONCE(1, "unknown plane in flip command\n");
7893 ret = -ENODEV;
ab3951eb 7894 goto err_unpin;
cb05d8de
DV		 7895 }
7896
ffe74d75
CW		 7897 len = 4;
7898 if (ring->id == RCS)
7899 len += 6;
7900
7901 ret = intel_ring_begin(ring, len);
7c9017e5 7902 if (ret)
83d4092b 7903 goto err_unpin;
7c9017e5 7904
ffe74d75
CW		 7905 /* Unmask the flip-done completion message. Note that the bspec says that
7906 * we should do this for both the BCS and RCS, and that we must not unmask
7907 * more than one flip event at any time (or ensure that one flip message
7908 * can be sent by waiting for flip-done prior to queueing new flips).
7909 * Experimentation says that BCS works despite DERRMR masking all
7910 * flip-done completion events and that unmasking all planes at once
7911 * for the RCS also doesn't appear to drop events. Setting the DERRMR
7912 * to zero does lead to lockups within MI_DISPLAY_FLIP.
7913 */
7914 if (ring->id == RCS) {
7915 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
7916 intel_ring_emit(ring, DERRMR);
7917 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
7918 DERRMR_PIPEB_PRI_FLIP_DONE |
7919 DERRMR_PIPEC_PRI_FLIP_DONE));
7920 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
7921 intel_ring_emit(ring, DERRMR);
7922 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
7923 }
7924
cb05d8de 7925 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7926 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 7927 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 7928 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7929
7930 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7931 intel_ring_advance(ring);
83d4092b
CW		 7932 return 0;
7933
7934err_unpin:
7935 intel_unpin_fb_obj(obj);
7936err:
7c9017e5
JB		 7937 return ret;
7938}
7939
8c9f3aaf
JB		 7940static int intel_default_queue_flip(struct drm_device *dev,
7941 struct drm_crtc *crtc,
7942 struct drm_framebuffer *fb,
ed8d1975
KP		 7943 struct drm_i915_gem_object *obj,
7944 uint32_t flags)
8c9f3aaf
JB		 7945{
7946 return -ENODEV;
7947}
7948
6b95a207
KH		 7949static int intel_crtc_page_flip(struct drm_crtc *crtc,
7950 struct drm_framebuffer *fb,
ed8d1975
KP		 7951 struct drm_pending_vblank_event *event,
7952 uint32_t page_flip_flags)
6b95a207
KH		 7953{
7954 struct drm_device *dev = crtc->dev;
7955 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7956 struct drm_framebuffer *old_fb = crtc->fb;
7957 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7959 struct intel_unpin_work *work;
8c9f3aaf 7960 unsigned long flags;
52e68630 7961 int ret;
6b95a207 7962
e6a595d2
VS		 7963 /* Can't change pixel format via MI display flips. */
7964 if (fb->pixel_format != crtc->fb->pixel_format)
7965 return -EINVAL;
7966
7967 /*
7968 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7969 * Note that pitch changes could also affect these register.
7970 */
7971 if (INTEL_INFO(dev)->gen > 3 &&
7972 (fb->offsets[0] != crtc->fb->offsets[0] ||
7973 fb->pitches[0] != crtc->fb->pitches[0]))
7974 return -EINVAL;
7975
6b95a207
KH		 7976 work = kzalloc(sizeof *work, GFP_KERNEL);
7977 if (work == NULL)
7978 return -ENOMEM;
7979
6b95a207 7980 work->event = event;
b4a98e57 7981 work->crtc = crtc;
4a35f83b 7982 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7983 INIT_WORK(&work->work, intel_unpin_work_fn);
7984
7317c75e
JB		 7985 ret = drm_vblank_get(dev, intel_crtc->pipe);
7986 if (ret)
7987 goto free_work;
7988
6b95a207
KH		 7989 /* We borrow the event spin lock for protecting unpin_work */
7990 spin_lock_irqsave(&dev->event_lock, flags);
7991 if (intel_crtc->unpin_work) {
7992 spin_unlock_irqrestore(&dev->event_lock, flags);
7993 kfree(work);
7317c75e 7994 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7995
7996 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7997 return -EBUSY;
7998 }
7999 intel_crtc->unpin_work = work;
8000 spin_unlock_irqrestore(&dev->event_lock, flags);
8001
b4a98e57
CW		 8002 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8003 flush_workqueue(dev_priv->wq);
8004
79158103
CW		 8005 ret = i915_mutex_lock_interruptible(dev);
8006 if (ret)
8007 goto cleanup;
6b95a207 8008
75dfca80 8009 /* Reference the objects for the scheduled work. */
05394f39
CW		 8010 drm_gem_object_reference(&work->old_fb_obj->base);
8011 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8012
8013 crtc->fb = fb;
96b099fd 8014
e1f99ce6 8015 work->pending_flip_obj = obj;
e1f99ce6 8016
4e5359cd
SF		 8017 work->enable_stall_check = true;
8018
b4a98e57 8019 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8020 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8021
ed8d1975 8022 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8023 if (ret)
8024 goto cleanup_pending;
6b95a207 8025
7782de3b 8026 intel_disable_fbc(dev);
c65355bb 8027 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8028 mutex_unlock(&dev->struct_mutex);
8029
e5510fac
JB		 8030 trace_i915_flip_request(intel_crtc->plane, obj);
8031
6b95a207 8032 return 0;
96b099fd 8033
8c9f3aaf 8034cleanup_pending:
b4a98e57 8035 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8036 crtc->fb = old_fb;
05394f39
CW		 8037 drm_gem_object_unreference(&work->old_fb_obj->base);
8038 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8039 mutex_unlock(&dev->struct_mutex);
8040
79158103 8041cleanup:
96b099fd
CW		 8042 spin_lock_irqsave(&dev->event_lock, flags);
8043 intel_crtc->unpin_work = NULL;
8044 spin_unlock_irqrestore(&dev->event_lock, flags);
8045
7317c75e
JB		 8046 drm_vblank_put(dev, intel_crtc->pipe);
8047free_work:
96b099fd
CW		 8048 kfree(work);
8049
8050 return ret;
6b95a207
KH		 8051}
8052
f6e5b160 8053static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8054 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8055 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8056};
8057
50f56119
DV		 8058static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8059 struct drm_crtc *crtc)
8060{
8061 struct drm_device *dev;
8062 struct drm_crtc *tmp;
8063 int crtc_mask = 1;
47f1c6c9 8064
50f56119 8065 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8066
50f56119 8067 dev = crtc->dev;
47f1c6c9 8068
50f56119
DV		 8069 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8070 if (tmp == crtc)
8071 break;
8072 crtc_mask <<= 1;
8073 }
47f1c6c9 8074
50f56119
DV		 8075 if (encoder->possible_crtcs & crtc_mask)
8076 return true;
8077 return false;
47f1c6c9 8078}
79e53945 8079
9a935856
DV		 8080/**
8081 * intel_modeset_update_staged_output_state
8082 *
8083 * Updates the staged output configuration state, e.g. after we've read out the
8084 * current hw state.
8085 */
8086static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8087{
9a935856
DV		 8088 struct intel_encoder *encoder;
8089 struct intel_connector *connector;
f6e5b160 8090
9a935856
DV		 8091 list_for_each_entry(connector, &dev->mode_config.connector_list,
8092 base.head) {
8093 connector->new_encoder =
8094 to_intel_encoder(connector->base.encoder);
8095 }
f6e5b160 8096
9a935856
DV		 8097 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8098 base.head) {
8099 encoder->new_crtc =
8100 to_intel_crtc(encoder->base.crtc);
8101 }
f6e5b160
CW		 8102}
8103
9a935856
DV		 8104/**
8105 * intel_modeset_commit_output_state
8106 *
8107 * This function copies the stage display pipe configuration to the real one.
8108 */
8109static void intel_modeset_commit_output_state(struct drm_device *dev)
8110{
8111 struct intel_encoder *encoder;
8112 struct intel_connector *connector;
f6e5b160 8113
9a935856
DV		 8114 list_for_each_entry(connector, &dev->mode_config.connector_list,
8115 base.head) {
8116 connector->base.encoder = &connector->new_encoder->base;
8117 }
f6e5b160 8118
9a935856
DV		 8119 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8120 base.head) {
8121 encoder->base.crtc = &encoder->new_crtc->base;
8122 }
8123}
8124
050f7aeb
DV		 8125static void
8126connected_sink_compute_bpp(struct intel_connector * connector,
8127 struct intel_crtc_config *pipe_config)
8128{
8129 int bpp = pipe_config->pipe_bpp;
8130
8131 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8132 connector->base.base.id,
8133 drm_get_connector_name(&connector->base));
8134
8135 /* Don't use an invalid EDID bpc value */
8136 if (connector->base.display_info.bpc &&
8137 connector->base.display_info.bpc * 3 < bpp) {
8138 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8139 bpp, connector->base.display_info.bpc*3);
8140 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8141 }
8142
8143 /* Clamp bpp to 8 on screens without EDID 1.4 */
8144 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8145 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8146 bpp);
8147 pipe_config->pipe_bpp = 24;
8148 }
8149}
8150
4e53c2e0 8151static int
050f7aeb
DV		 8152compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8153 struct drm_framebuffer *fb,
8154 struct intel_crtc_config *pipe_config)
4e53c2e0 8155{
050f7aeb
DV		 8156 struct drm_device *dev = crtc->base.dev;
8157 struct intel_connector *connector;
4e53c2e0
DV		 8158 int bpp;
8159
d42264b1
DV		 8160 switch (fb->pixel_format) {
8161 case DRM_FORMAT_C8:
4e53c2e0
DV		 8162 bpp = 8*3; /* since we go through a colormap */
8163 break;
d42264b1
DV		 8164 case DRM_FORMAT_XRGB1555:
8165 case DRM_FORMAT_ARGB1555:
8166 /* checked in intel_framebuffer_init already */
8167 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8168 return -EINVAL;
8169 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8170 bpp = 6*3; /* min is 18bpp */
8171 break;
d42264b1
DV		 8172 case DRM_FORMAT_XBGR8888:
8173 case DRM_FORMAT_ABGR8888:
8174 /* checked in intel_framebuffer_init already */
8175 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8176 return -EINVAL;
8177 case DRM_FORMAT_XRGB8888:
8178 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8179 bpp = 8*3;
8180 break;
d42264b1
DV		 8181 case DRM_FORMAT_XRGB2101010:
8182 case DRM_FORMAT_ARGB2101010:
8183 case DRM_FORMAT_XBGR2101010:
8184 case DRM_FORMAT_ABGR2101010:
8185 /* checked in intel_framebuffer_init already */
8186 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8187 return -EINVAL;
4e53c2e0
DV		 8188 bpp = 10*3;
8189 break;
baba133a 8190 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8191 default:
8192 DRM_DEBUG_KMS("unsupported depth\n");
8193 return -EINVAL;
8194 }
8195
4e53c2e0
DV		 8196 pipe_config->pipe_bpp = bpp;
8197
8198 /* Clamp display bpp to EDID value */
8199 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8200 base.head) {
1b829e05
DV		 8201 if (!connector->new_encoder ||
8202 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8203 continue;
8204
050f7aeb 8205 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8206 }
8207
8208 return bpp;
8209}
8210
c0b03411
DV		 8211static void intel_dump_pipe_config(struct intel_crtc *crtc,
8212 struct intel_crtc_config *pipe_config,
8213 const char *context)
8214{
8215 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8216 context, pipe_name(crtc->pipe));
8217
8218 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8219 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8220 pipe_config->pipe_bpp, pipe_config->dither);
8221 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8222 pipe_config->has_pch_encoder,
8223 pipe_config->fdi_lanes,
8224 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8225 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8226 pipe_config->fdi_m_n.tu);
8227 DRM_DEBUG_KMS("requested mode:\n");
8228 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8229 DRM_DEBUG_KMS("adjusted mode:\n");
8230 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8231 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8232 pipe_config->gmch_pfit.control,
8233 pipe_config->gmch_pfit.pgm_ratios,
8234 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8235 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8236 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8237 pipe_config->pch_pfit.size,
8238 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8239 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 8240}
8241
accfc0c5
DV		 8242static bool check_encoder_cloning(struct drm_crtc *crtc)
8243{
8244 int num_encoders = 0;
8245 bool uncloneable_encoders = false;
8246 struct intel_encoder *encoder;
8247
8248 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8249 base.head) {
8250 if (&encoder->new_crtc->base != crtc)
8251 continue;
8252
8253 num_encoders++;
8254 if (!encoder->cloneable)
8255 uncloneable_encoders = true;
8256 }
8257
8258 return !(num_encoders > 1 && uncloneable_encoders);
8259}
8260
b8cecdf5
DV		 8261static struct intel_crtc_config *
8262intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8263 struct drm_framebuffer *fb,
b8cecdf5 8264 struct drm_display_mode *mode)
ee7b9f93 8265{
7758a113 8266 struct drm_device *dev = crtc->dev;
7758a113 8267 struct intel_encoder *encoder;
b8cecdf5 8268 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8269 int plane_bpp, ret = -EINVAL;
8270 bool retry = true;
ee7b9f93 8271
accfc0c5
DV		 8272 if (!check_encoder_cloning(crtc)) {
8273 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8274 return ERR_PTR(-EINVAL);
8275 }
8276
b8cecdf5
DV		 8277 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8278 if (!pipe_config)
7758a113
DV		 8279 return ERR_PTR(-ENOMEM);
8280
b8cecdf5
DV		 8281 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8282 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 8283 pipe_config->cpu_transcoder =
8284 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8285 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8286
2960bc9c
ID		 8287 /*
8288 * Sanitize sync polarity flags based on requested ones. If neither
8289 * positive or negative polarity is requested, treat this as meaning
8290 * negative polarity.
8291 */
8292 if (!(pipe_config->adjusted_mode.flags &
8293 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8294 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8295
8296 if (!(pipe_config->adjusted_mode.flags &
8297 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8298 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8299
050f7aeb
DV		 8300 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8301 * plane pixel format and any sink constraints into account. Returns the
8302 * source plane bpp so that dithering can be selected on mismatches
8303 * after encoders and crtc also have had their say. */
8304 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8305 fb, pipe_config);
4e53c2e0
DV		 8306 if (plane_bpp < 0)
8307 goto fail;
8308
e29c22c0 8309encoder_retry:
ef1b460d 8310 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8311 pipe_config->port_clock = 0;
ef1b460d 8312 pipe_config->pixel_multiplier = 1;
ff9a6750 8313
135c81b8
DV		 8314 /* Fill in default crtc timings, allow encoders to overwrite them. */
8315 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8316
7758a113
DV		 8317 /* Pass our mode to the connectors and the CRTC to give them a chance to
8318 * adjust it according to limitations or connector properties, and also
8319 * a chance to reject the mode entirely.
47f1c6c9 8320 */
7758a113
DV		 8321 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8322 base.head) {
47f1c6c9 8323
7758a113
DV		 8324 if (&encoder->new_crtc->base != crtc)
8325 continue;
7ae89233 8326
efea6e8e
DV		 8327 if (!(encoder->compute_config(encoder, pipe_config))) {
8328 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8329 goto fail;
8330 }
ee7b9f93 8331 }
47f1c6c9 8332
ff9a6750
DV		 8333 /* Set default port clock if not overwritten by the encoder. Needs to be
8334 * done afterwards in case the encoder adjusts the mode. */
8335 if (!pipe_config->port_clock)
8336 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
8337
a43f6e0f 8338 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8339 if (ret < 0) {
7758a113
DV		 8340 DRM_DEBUG_KMS("CRTC fixup failed\n");
8341 goto fail;
ee7b9f93 8342 }
e29c22c0
DV		 8343
8344 if (ret == RETRY) {
8345 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8346 ret = -EINVAL;
8347 goto fail;
8348 }
8349
8350 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8351 retry = false;
8352 goto encoder_retry;
8353 }
8354
4e53c2e0
DV		 8355 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8356 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8357 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8358
b8cecdf5 8359 return pipe_config;
7758a113 8360fail:
b8cecdf5 8361 kfree(pipe_config);
e29c22c0 8362 return ERR_PTR(ret);
ee7b9f93 8363}
47f1c6c9 8364
e2e1ed41
DV		 8365/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8366 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8367static void
8368intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8369 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8370{
8371 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8372 struct drm_device *dev = crtc->dev;
8373 struct intel_encoder *encoder;
8374 struct intel_connector *connector;
8375 struct drm_crtc *tmp_crtc;
79e53945 8376
e2e1ed41 8377 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8378
e2e1ed41
DV		 8379 /* Check which crtcs have changed outputs connected to them, these need
8380 * to be part of the prepare_pipes mask. We don't (yet) support global
8381 * modeset across multiple crtcs, so modeset_pipes will only have one
8382 * bit set at most. */
8383 list_for_each_entry(connector, &dev->mode_config.connector_list,
8384 base.head) {
8385 if (connector->base.encoder == &connector->new_encoder->base)
8386 continue;
79e53945 8387
e2e1ed41
DV		 8388 if (connector->base.encoder) {
8389 tmp_crtc = connector->base.encoder->crtc;
8390
8391 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8392 }
8393
8394 if (connector->new_encoder)
8395 *prepare_pipes |=
8396 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8397 }
8398
e2e1ed41
DV		 8399 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8400 base.head) {
8401 if (encoder->base.crtc == &encoder->new_crtc->base)
8402 continue;
8403
8404 if (encoder->base.crtc) {
8405 tmp_crtc = encoder->base.crtc;
8406
8407 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8408 }
8409
8410 if (encoder->new_crtc)
8411 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8412 }
8413
e2e1ed41
DV		 8414 /* Check for any pipes that will be fully disabled ... */
8415 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8416 base.head) {
8417 bool used = false;
22fd0fab 8418
e2e1ed41
DV		 8419 /* Don't try to disable disabled crtcs. */
8420 if (!intel_crtc->base.enabled)
8421 continue;
7e7d76c3 8422
e2e1ed41
DV		 8423 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8424 base.head) {
8425 if (encoder->new_crtc == intel_crtc)
8426 used = true;
8427 }
8428
8429 if (!used)
8430 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8431 }
8432
e2e1ed41
DV		 8433
8434 /* set_mode is also used to update properties on life display pipes. */
8435 intel_crtc = to_intel_crtc(crtc);
8436 if (crtc->enabled)
8437 *prepare_pipes |= 1 << intel_crtc->pipe;
8438
b6c5164d
DV		 8439 /*
8440 * For simplicity do a full modeset on any pipe where the output routing
8441 * changed. We could be more clever, but that would require us to be
8442 * more careful with calling the relevant encoder->mode_set functions.
8443 */
e2e1ed41
DV		 8444 if (*prepare_pipes)
8445 *modeset_pipes = *prepare_pipes;
8446
8447 /* ... and mask these out. */
8448 *modeset_pipes &= ~(*disable_pipes);
8449 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8450
8451 /*
8452 * HACK: We don't (yet) fully support global modesets. intel_set_config
8453 * obies this rule, but the modeset restore mode of
8454 * intel_modeset_setup_hw_state does not.
8455 */
8456 *modeset_pipes &= 1 << intel_crtc->pipe;
8457 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8458
8459 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8460 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8461}
79e53945 8462
ea9d758d 8463static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8464{
ea9d758d 8465 struct drm_encoder *encoder;
f6e5b160 8466 struct drm_device *dev = crtc->dev;
f6e5b160 8467
ea9d758d
DV		 8468 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8469 if (encoder->crtc == crtc)
8470 return true;
8471
8472 return false;
8473}
8474
8475static void
8476intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8477{
8478 struct intel_encoder *intel_encoder;
8479 struct intel_crtc *intel_crtc;
8480 struct drm_connector *connector;
8481
8482 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8483 base.head) {
8484 if (!intel_encoder->base.crtc)
8485 continue;
8486
8487 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8488
8489 if (prepare_pipes & (1 << intel_crtc->pipe))
8490 intel_encoder->connectors_active = false;
8491 }
8492
8493 intel_modeset_commit_output_state(dev);
8494
8495 /* Update computed state. */
8496 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8497 base.head) {
8498 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8499 }
8500
8501 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8502 if (!connector->encoder || !connector->encoder->crtc)
8503 continue;
8504
8505 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8506
8507 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8508 struct drm_property *dpms_property =
8509 dev->mode_config.dpms_property;
8510
ea9d758d 8511 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8512 drm_object_property_set_value(&connector->base,
68d34720
DV		 8513 dpms_property,
8514 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8515
8516 intel_encoder = to_intel_encoder(connector->encoder);
8517 intel_encoder->connectors_active = true;
8518 }
8519 }
8520
8521}
8522
f1f644dc
JB		 8523static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8524 struct intel_crtc_config *new)
8525{
8526 int clock1, clock2, diff;
8527
8528 clock1 = cur->adjusted_mode.clock;
8529 clock2 = new->adjusted_mode.clock;
8530
8531 if (clock1 == clock2)
8532 return true;
8533
8534 if (!clock1 || !clock2)
8535 return false;
8536
8537 diff = abs(clock1 - clock2);
8538
8539 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8540 return true;
8541
8542 return false;
8543}
8544
25c5b266
DV		 8545#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8546 list_for_each_entry((intel_crtc), \
8547 &(dev)->mode_config.crtc_list, \
8548 base.head) \
0973f18f 8549 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8550
0e8ffe1b 8551static bool
2fa2fe9a
DV		 8552intel_pipe_config_compare(struct drm_device *dev,
8553 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8554 struct intel_crtc_config *pipe_config)
8555{
66e985c0
DV		 8556#define PIPE_CONF_CHECK_X(name) \
8557 if (current_config->name != pipe_config->name) { \
8558 DRM_ERROR("mismatch in " #name " " \
8559 "(expected 0x%08x, found 0x%08x)\n", \
8560 current_config->name, \
8561 pipe_config->name); \
8562 return false; \
8563 }
8564
08a24034
DV		 8565#define PIPE_CONF_CHECK_I(name) \
8566 if (current_config->name != pipe_config->name) { \
8567 DRM_ERROR("mismatch in " #name " " \
8568 "(expected %i, found %i)\n", \
8569 current_config->name, \
8570 pipe_config->name); \
8571 return false; \
88adfff1
DV		 8572 }
8573
1bd1bd80
DV		 8574#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8575 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8576 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8577 "(expected %i, found %i)\n", \
8578 current_config->name & (mask), \
8579 pipe_config->name & (mask)); \
8580 return false; \
8581 }
8582
bb760063
DV		 8583#define PIPE_CONF_QUIRK(quirk) \
8584 ((current_config->quirks | pipe_config->quirks) & (quirk))
8585
eccb140b
DV		 8586 PIPE_CONF_CHECK_I(cpu_transcoder);
8587
08a24034
DV		 8588 PIPE_CONF_CHECK_I(has_pch_encoder);
8589 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8590 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8591 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8592 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8593 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8594 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8595
1bd1bd80
DV		 8596 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8597 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8598 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8599 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8600 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8601 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8602
8603 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8604 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8605 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8606 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8607 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8608 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8609
c93f54cf 8610 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8611
1bd1bd80
DV		 8612 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8613 DRM_MODE_FLAG_INTERLACE);
8614
bb760063
DV		 8615 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8616 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8617 DRM_MODE_FLAG_PHSYNC);
8618 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8619 DRM_MODE_FLAG_NHSYNC);
8620 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8621 DRM_MODE_FLAG_PVSYNC);
8622 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8623 DRM_MODE_FLAG_NVSYNC);
8624 }
045ac3b5 8625
1bd1bd80
DV		 8626 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8627 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8628
2fa2fe9a
DV		 8629 PIPE_CONF_CHECK_I(gmch_pfit.control);
8630 /* pfit ratios are autocomputed by the hw on gen4+ */
8631 if (INTEL_INFO(dev)->gen < 4)
8632 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8633 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8634 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8635 if (current_config->pch_pfit.enabled) {
8636 PIPE_CONF_CHECK_I(pch_pfit.pos);
8637 PIPE_CONF_CHECK_I(pch_pfit.size);
8638 }
2fa2fe9a 8639
42db64ef
PZ		 8640 PIPE_CONF_CHECK_I(ips_enabled);
8641
c0d43d62 8642 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8643 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8644 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8645 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8646 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8647
4f56d12e
VS		 8648 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8649 PIPE_CONF_CHECK_I(pipe_bpp);
8650
66e985c0 8651#undef PIPE_CONF_CHECK_X
08a24034 8652#undef PIPE_CONF_CHECK_I
1bd1bd80 8653#undef PIPE_CONF_CHECK_FLAGS
bb760063 8654#undef PIPE_CONF_QUIRK
88adfff1 8655
f1f644dc
JB		 8656 if (!IS_HASWELL(dev)) {
8657 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8658 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8659 current_config->adjusted_mode.clock,
8660 pipe_config->adjusted_mode.clock);
8661 return false;
8662 }
8663 }
8664
0e8ffe1b
DV		 8665 return true;
8666}
8667
91d1b4bd
DV		 8668static void
8669check_connector_state(struct drm_device *dev)
8af6cf88 8670{
8af6cf88
DV		 8671 struct intel_connector *connector;
8672
8673 list_for_each_entry(connector, &dev->mode_config.connector_list,
8674 base.head) {
8675 /* This also checks the encoder/connector hw state with the
8676 * ->get_hw_state callbacks. */
8677 intel_connector_check_state(connector);
8678
8679 WARN(&connector->new_encoder->base != connector->base.encoder,
8680 "connector's staged encoder doesn't match current encoder\n");
8681 }
91d1b4bd
DV		 8682}
8683
8684static void
8685check_encoder_state(struct drm_device *dev)
8686{
8687 struct intel_encoder *encoder;
8688 struct intel_connector *connector;
8af6cf88
DV		 8689
8690 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8691 base.head) {
8692 bool enabled = false;
8693 bool active = false;
8694 enum pipe pipe, tracked_pipe;
8695
8696 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8697 encoder->base.base.id,
8698 drm_get_encoder_name(&encoder->base));
8699
8700 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8701 "encoder's stage crtc doesn't match current crtc\n");
8702 WARN(encoder->connectors_active && !encoder->base.crtc,
8703 "encoder's active_connectors set, but no crtc\n");
8704
8705 list_for_each_entry(connector, &dev->mode_config.connector_list,
8706 base.head) {
8707 if (connector->base.encoder != &encoder->base)
8708 continue;
8709 enabled = true;
8710 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8711 active = true;
8712 }
8713 WARN(!!encoder->base.crtc != enabled,
8714 "encoder's enabled state mismatch "
8715 "(expected %i, found %i)\n",
8716 !!encoder->base.crtc, enabled);
8717 WARN(active && !encoder->base.crtc,
8718 "active encoder with no crtc\n");
8719
8720 WARN(encoder->connectors_active != active,
8721 "encoder's computed active state doesn't match tracked active state "
8722 "(expected %i, found %i)\n", active, encoder->connectors_active);
8723
8724 active = encoder->get_hw_state(encoder, &pipe);
8725 WARN(active != encoder->connectors_active,
8726 "encoder's hw state doesn't match sw tracking "
8727 "(expected %i, found %i)\n",
8728 encoder->connectors_active, active);
8729
8730 if (!encoder->base.crtc)
8731 continue;
8732
8733 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8734 WARN(active && pipe != tracked_pipe,
8735 "active encoder's pipe doesn't match"
8736 "(expected %i, found %i)\n",
8737 tracked_pipe, pipe);
8738
8739 }
91d1b4bd
DV		 8740}
8741
8742static void
8743check_crtc_state(struct drm_device *dev)
8744{
8745 drm_i915_private_t *dev_priv = dev->dev_private;
8746 struct intel_crtc *crtc;
8747 struct intel_encoder *encoder;
8748 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8749
8750 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8751 base.head) {
8752 bool enabled = false;
8753 bool active = false;
8754
045ac3b5
JB		 8755 memset(&pipe_config, 0, sizeof(pipe_config));
8756
8af6cf88
DV		 8757 DRM_DEBUG_KMS("[CRTC:%d]\n",
8758 crtc->base.base.id);
8759
8760 WARN(crtc->active && !crtc->base.enabled,
8761 "active crtc, but not enabled in sw tracking\n");
8762
8763 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8764 base.head) {
8765 if (encoder->base.crtc != &crtc->base)
8766 continue;
8767 enabled = true;
8768 if (encoder->connectors_active)
8769 active = true;
8770 }
6c49f241 8771
8af6cf88
DV		 8772 WARN(active != crtc->active,
8773 "crtc's computed active state doesn't match tracked active state "
8774 "(expected %i, found %i)\n", active, crtc->active);
8775 WARN(enabled != crtc->base.enabled,
8776 "crtc's computed enabled state doesn't match tracked enabled state "
8777 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8778
0e8ffe1b
DV		 8779 active = dev_priv->display.get_pipe_config(crtc,
8780 &pipe_config);
d62cf62a
DV		 8781
8782 /* hw state is inconsistent with the pipe A quirk */
8783 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8784 active = crtc->active;
8785
6c49f241
DV		 8786 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8787 base.head) {
3eaba51c 8788 enum pipe pipe;
6c49f241
DV		 8789 if (encoder->base.crtc != &crtc->base)
8790 continue;
3eaba51c
VS		 8791 if (encoder->get_config &&
8792 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8793 encoder->get_config(encoder, &pipe_config);
8794 }
8795
510d5f2f
JB		 8796 if (dev_priv->display.get_clock)
8797 dev_priv->display.get_clock(crtc, &pipe_config);
8798
0e8ffe1b
DV		 8799 WARN(crtc->active != active,
8800 "crtc active state doesn't match with hw state "
8801 "(expected %i, found %i)\n", crtc->active, active);
8802
c0b03411
DV		 8803 if (active &&
8804 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8805 WARN(1, "pipe state doesn't match!\n");
8806 intel_dump_pipe_config(crtc, &pipe_config,
8807 "[hw state]");
8808 intel_dump_pipe_config(crtc, &crtc->config,
8809 "[sw state]");
8810 }
8af6cf88
DV		 8811 }
8812}
8813
91d1b4bd
DV		 8814static void
8815check_shared_dpll_state(struct drm_device *dev)
8816{
8817 drm_i915_private_t *dev_priv = dev->dev_private;
8818 struct intel_crtc *crtc;
8819 struct intel_dpll_hw_state dpll_hw_state;
8820 int i;
5358901f
DV		 8821
8822 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8823 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8824 int enabled_crtcs = 0, active_crtcs = 0;
8825 bool active;
8826
8827 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8828
8829 DRM_DEBUG_KMS("%s\n", pll->name);
8830
8831 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8832
8833 WARN(pll->active > pll->refcount,
8834 "more active pll users than references: %i vs %i\n",
8835 pll->active, pll->refcount);
8836 WARN(pll->active && !pll->on,
8837 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8838 WARN(pll->on && !pll->active,
8839 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8840 WARN(pll->on != active,
8841 "pll on state mismatch (expected %i, found %i)\n",
8842 pll->on, active);
8843
8844 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8845 base.head) {
8846 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8847 enabled_crtcs++;
8848 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8849 active_crtcs++;
8850 }
8851 WARN(pll->active != active_crtcs,
8852 "pll active crtcs mismatch (expected %i, found %i)\n",
8853 pll->active, active_crtcs);
8854 WARN(pll->refcount != enabled_crtcs,
8855 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8856 pll->refcount, enabled_crtcs);
66e985c0
DV		 8857
8858 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8859 sizeof(dpll_hw_state)),
8860 "pll hw state mismatch\n");
5358901f 8861 }
8af6cf88
DV		 8862}
8863
91d1b4bd
DV		 8864void
8865intel_modeset_check_state(struct drm_device *dev)
8866{
8867 check_connector_state(dev);
8868 check_encoder_state(dev);
8869 check_crtc_state(dev);
8870 check_shared_dpll_state(dev);
8871}
8872
f30da187
DV		 8873static int __intel_set_mode(struct drm_crtc *crtc,
8874 struct drm_display_mode *mode,
8875 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8876{
8877 struct drm_device *dev = crtc->dev;
dbf2b54e 8878 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8879 struct drm_display_mode *saved_mode, *saved_hwmode;
8880 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8881 struct intel_crtc *intel_crtc;
8882 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8883 int ret = 0;
a6778b3c 8884
3ac18232 8885 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8886 if (!saved_mode)
8887 return -ENOMEM;
3ac18232 8888 saved_hwmode = saved_mode + 1;
a6778b3c 8889
e2e1ed41 8890 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8891 &prepare_pipes, &disable_pipes);
8892
3ac18232
TG		 8893 *saved_hwmode = crtc->hwmode;
8894 *saved_mode = crtc->mode;
a6778b3c 8895
25c5b266
DV		 8896 /* Hack: Because we don't (yet) support global modeset on multiple
8897 * crtcs, we don't keep track of the new mode for more than one crtc.
8898 * Hence simply check whether any bit is set in modeset_pipes in all the
8899 * pieces of code that are not yet converted to deal with mutliple crtcs
8900 * changing their mode at the same time. */
25c5b266 8901 if (modeset_pipes) {
4e53c2e0 8902 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8903 if (IS_ERR(pipe_config)) {
8904 ret = PTR_ERR(pipe_config);
8905 pipe_config = NULL;
8906
3ac18232 8907 goto out;
25c5b266 8908 }
c0b03411
DV		 8909 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8910 "[modeset]");
25c5b266 8911 }
a6778b3c 8912
460da916
DV		 8913 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8914 intel_crtc_disable(&intel_crtc->base);
8915
ea9d758d
DV		 8916 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8917 if (intel_crtc->base.enabled)
8918 dev_priv->display.crtc_disable(&intel_crtc->base);
8919 }
a6778b3c 8920
6c4c86f5
DV		 8921 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8922 * to set it here already despite that we pass it down the callchain.
f6e5b160 8923 */
b8cecdf5 8924 if (modeset_pipes) {
25c5b266 8925 crtc->mode = *mode;
b8cecdf5
DV		 8926 /* mode_set/enable/disable functions rely on a correct pipe
8927 * config. */
8928 to_intel_crtc(crtc)->config = *pipe_config;
8929 }
7758a113 8930
ea9d758d
DV		 8931 /* Only after disabling all output pipelines that will be changed can we
8932 * update the the output configuration. */
8933 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8934
47fab737
DV		 8935 if (dev_priv->display.modeset_global_resources)
8936 dev_priv->display.modeset_global_resources(dev);
8937
a6778b3c
DV		 8938 /* Set up the DPLL and any encoders state that needs to adjust or depend
8939 * on the DPLL.
f6e5b160 8940 */
25c5b266 8941 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8942 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8943 x, y, fb);
8944 if (ret)
8945 goto done;
a6778b3c
DV		 8946 }
8947
8948 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8949 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8950 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8951
25c5b266
DV		 8952 if (modeset_pipes) {
8953 /* Store real post-adjustment hardware mode. */
b8cecdf5 8954 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8955
25c5b266
DV		 8956 /* Calculate and store various constants which
8957 * are later needed by vblank and swap-completion
8958 * timestamping. They are derived from true hwmode.
8959 */
8960 drm_calc_timestamping_constants(crtc);
8961 }
a6778b3c
DV		 8962
8963 /* FIXME: add subpixel order */
8964done:
c0c36b94 8965 if (ret && crtc->enabled) {
3ac18232
TG		 8966 crtc->hwmode = *saved_hwmode;
8967 crtc->mode = *saved_mode;
a6778b3c
DV		 8968 }
8969
3ac18232 8970out:
b8cecdf5 8971 kfree(pipe_config);
3ac18232 8972 kfree(saved_mode);
a6778b3c 8973 return ret;
f6e5b160
CW		 8974}
8975
e7457a9a
DL		 8976static int intel_set_mode(struct drm_crtc *crtc,
8977 struct drm_display_mode *mode,
8978 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 8979{
8980 int ret;
8981
8982 ret = __intel_set_mode(crtc, mode, x, y, fb);
8983
8984 if (ret == 0)
8985 intel_modeset_check_state(crtc->dev);
8986
8987 return ret;
8988}
8989
c0c36b94
CW		 8990void intel_crtc_restore_mode(struct drm_crtc *crtc)
8991{
8992 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8993}
8994
25c5b266
DV		 8995#undef for_each_intel_crtc_masked
8996
d9e55608
DV		 8997static void intel_set_config_free(struct intel_set_config *config)
8998{
8999 if (!config)
9000 return;
9001
1aa4b628
DV		 9002 kfree(config->save_connector_encoders);
9003 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9004 kfree(config);
9005}
9006
85f9eb71
DV		 9007static int intel_set_config_save_state(struct drm_device *dev,
9008 struct intel_set_config *config)
9009{
85f9eb71
DV		 9010 struct drm_encoder *encoder;
9011 struct drm_connector *connector;
9012 int count;
9013
1aa4b628
DV		 9014 config->save_encoder_crtcs =
9015 kcalloc(dev->mode_config.num_encoder,
9016 sizeof(struct drm_crtc *), GFP_KERNEL);
9017 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9018 return -ENOMEM;
9019
1aa4b628
DV		 9020 config->save_connector_encoders =
9021 kcalloc(dev->mode_config.num_connector,
9022 sizeof(struct drm_encoder *), GFP_KERNEL);
9023 if (!config->save_connector_encoders)
85f9eb71
DV		 9024 return -ENOMEM;
9025
9026 /* Copy data. Note that driver private data is not affected.
9027 * Should anything bad happen only the expected state is
9028 * restored, not the drivers personal bookkeeping.
9029 */
85f9eb71
DV		 9030 count = 0;
9031 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9032 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9033 }
9034
9035 count = 0;
9036 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9037 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9038 }
9039
9040 return 0;
9041}
9042
9043static void intel_set_config_restore_state(struct drm_device *dev,
9044 struct intel_set_config *config)
9045{
9a935856
DV		 9046 struct intel_encoder *encoder;
9047 struct intel_connector *connector;
85f9eb71
DV		 9048 int count;
9049
85f9eb71 9050 count = 0;
9a935856
DV		 9051 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9052 encoder->new_crtc =
9053 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9054 }
9055
9056 count = 0;
9a935856
DV		 9057 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9058 connector->new_encoder =
9059 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9060 }
9061}
9062
e3de42b6 9063static bool
2e57f47d 9064is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9065{
9066 int i;
9067
2e57f47d
CW		 9068 if (set->num_connectors == 0)
9069 return false;
9070
9071 if (WARN_ON(set->connectors == NULL))
9072 return false;
9073
9074 for (i = 0; i < set->num_connectors; i++)
9075 if (set->connectors[i]->encoder &&
9076 set->connectors[i]->encoder->crtc == set->crtc &&
9077 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9078 return true;
9079
9080 return false;
9081}
9082
5e2b584e
DV		 9083static void
9084intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9085 struct intel_set_config *config)
9086{
9087
9088 /* We should be able to check here if the fb has the same properties
9089 * and then just flip_or_move it */
2e57f47d
CW		 9090 if (is_crtc_connector_off(set)) {
9091 config->mode_changed = true;
e3de42b6 9092 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9093 /* If we have no fb then treat it as a full mode set */
9094 if (set->crtc->fb == NULL) {
319d9827
JB		 9095 struct intel_crtc *intel_crtc =
9096 to_intel_crtc(set->crtc);
9097
9098 if (intel_crtc->active && i915_fastboot) {
9099 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9100 config->fb_changed = true;
9101 } else {
9102 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9103 config->mode_changed = true;
9104 }
5e2b584e
DV		 9105 } else if (set->fb == NULL) {
9106 config->mode_changed = true;
72f4901e
DV		 9107 } else if (set->fb->pixel_format !=
9108 set->crtc->fb->pixel_format) {
5e2b584e 9109 config->mode_changed = true;
e3de42b6 9110 } else {
5e2b584e 9111 config->fb_changed = true;
e3de42b6 9112 }
5e2b584e
DV		 9113 }
9114
835c5873 9115 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9116 config->fb_changed = true;
9117
9118 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9119 DRM_DEBUG_KMS("modes are different, full mode set\n");
9120 drm_mode_debug_printmodeline(&set->crtc->mode);
9121 drm_mode_debug_printmodeline(set->mode);
9122 config->mode_changed = true;
9123 }
a1d95703
CW		 9124
9125 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9126 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9127}
9128
2e431051 9129static int
9a935856
DV		 9130intel_modeset_stage_output_state(struct drm_device *dev,
9131 struct drm_mode_set *set,
9132 struct intel_set_config *config)
50f56119 9133{
85f9eb71 9134 struct drm_crtc *new_crtc;
9a935856
DV		 9135 struct intel_connector *connector;
9136 struct intel_encoder *encoder;
f3f08572 9137 int ro;
50f56119 9138
9abdda74 9139 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9140 * of connectors. For paranoia, double-check this. */
9141 WARN_ON(!set->fb && (set->num_connectors != 0));
9142 WARN_ON(set->fb && (set->num_connectors == 0));
9143
9a935856
DV		 9144 list_for_each_entry(connector, &dev->mode_config.connector_list,
9145 base.head) {
9146 /* Otherwise traverse passed in connector list and get encoders
9147 * for them. */
50f56119 9148 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9149 if (set->connectors[ro] == &connector->base) {
9150 connector->new_encoder = connector->encoder;
50f56119
DV		 9151 break;
9152 }
9153 }
9154
9a935856
DV		 9155 /* If we disable the crtc, disable all its connectors. Also, if
9156 * the connector is on the changing crtc but not on the new
9157 * connector list, disable it. */
9158 if ((!set->fb || ro == set->num_connectors) &&
9159 connector->base.encoder &&
9160 connector->base.encoder->crtc == set->crtc) {
9161 connector->new_encoder = NULL;
9162
9163 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9164 connector->base.base.id,
9165 drm_get_connector_name(&connector->base));
9166 }
9167
9168
9169 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9170 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9171 config->mode_changed = true;
50f56119
DV		 9172 }
9173 }
9a935856 9174 /* connector->new_encoder is now updated for all connectors. */
50f56119 9175
9a935856 9176 /* Update crtc of enabled connectors. */
9a935856
DV		 9177 list_for_each_entry(connector, &dev->mode_config.connector_list,
9178 base.head) {
9179 if (!connector->new_encoder)
50f56119
DV		 9180 continue;
9181
9a935856 9182 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9183
9184 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9185 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9186 new_crtc = set->crtc;
9187 }
9188
9189 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9190 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9191 new_crtc)) {
5e2b584e 9192 return -EINVAL;
50f56119 9193 }
9a935856
DV		 9194 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9195
9196 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9197 connector->base.base.id,
9198 drm_get_connector_name(&connector->base),
9199 new_crtc->base.id);
9200 }
9201
9202 /* Check for any encoders that needs to be disabled. */
9203 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9204 base.head) {
9205 list_for_each_entry(connector,
9206 &dev->mode_config.connector_list,
9207 base.head) {
9208 if (connector->new_encoder == encoder) {
9209 WARN_ON(!connector->new_encoder->new_crtc);
9210
9211 goto next_encoder;
9212 }
9213 }
9214 encoder->new_crtc = NULL;
9215next_encoder:
9216 /* Only now check for crtc changes so we don't miss encoders
9217 * that will be disabled. */
9218 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9219 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9220 config->mode_changed = true;
50f56119
DV		 9221 }
9222 }
9a935856 9223 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9224
2e431051
DV		 9225 return 0;
9226}
9227
9228static int intel_crtc_set_config(struct drm_mode_set *set)
9229{
9230 struct drm_device *dev;
2e431051
DV		 9231 struct drm_mode_set save_set;
9232 struct intel_set_config *config;
9233 int ret;
2e431051 9234
8d3e375e
DV		 9235 BUG_ON(!set);
9236 BUG_ON(!set->crtc);
9237 BUG_ON(!set->crtc->helper_private);
2e431051 9238
7e53f3a4
DV		 9239 /* Enforce sane interface api - has been abused by the fb helper. */
9240 BUG_ON(!set->mode && set->fb);
9241 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9242
2e431051
DV		 9243 if (set->fb) {
9244 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9245 set->crtc->base.id, set->fb->base.id,
9246 (int)set->num_connectors, set->x, set->y);
9247 } else {
9248 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9249 }
9250
9251 dev = set->crtc->dev;
9252
9253 ret = -ENOMEM;
9254 config = kzalloc(sizeof(*config), GFP_KERNEL);
9255 if (!config)
9256 goto out_config;
9257
9258 ret = intel_set_config_save_state(dev, config);
9259 if (ret)
9260 goto out_config;
9261
9262 save_set.crtc = set->crtc;
9263 save_set.mode = &set->crtc->mode;
9264 save_set.x = set->crtc->x;
9265 save_set.y = set->crtc->y;
9266 save_set.fb = set->crtc->fb;
9267
9268 /* Compute whether we need a full modeset, only an fb base update or no
9269 * change at all. In the future we might also check whether only the
9270 * mode changed, e.g. for LVDS where we only change the panel fitter in
9271 * such cases. */
9272 intel_set_config_compute_mode_changes(set, config);
9273
9a935856 9274 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9275 if (ret)
9276 goto fail;
9277
5e2b584e 9278 if (config->mode_changed) {
c0c36b94
CW		 9279 ret = intel_set_mode(set->crtc, set->mode,
9280 set->x, set->y, set->fb);
5e2b584e 9281 } else if (config->fb_changed) {
4878cae2
VS		 9282 intel_crtc_wait_for_pending_flips(set->crtc);
9283
4f660f49 9284 ret = intel_pipe_set_base(set->crtc,
94352cf9 9285 set->x, set->y, set->fb);
50f56119
DV		 9286 }
9287
2d05eae1 9288 if (ret) {
bf67dfeb
DV		 9289 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9290 set->crtc->base.id, ret);
50f56119 9291fail:
2d05eae1 9292 intel_set_config_restore_state(dev, config);
50f56119 9293
2d05eae1
CW		 9294 /* Try to restore the config */
9295 if (config->mode_changed &&
9296 intel_set_mode(save_set.crtc, save_set.mode,
9297 save_set.x, save_set.y, save_set.fb))
9298 DRM_ERROR("failed to restore config after modeset failure\n");
9299 }
50f56119 9300
d9e55608
DV		 9301out_config:
9302 intel_set_config_free(config);
50f56119
DV		 9303 return ret;
9304}
f6e5b160
CW		 9305
9306static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9307 .cursor_set = intel_crtc_cursor_set,
9308 .cursor_move = intel_crtc_cursor_move,
9309 .gamma_set = intel_crtc_gamma_set,
50f56119 9310 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9311 .destroy = intel_crtc_destroy,
9312 .page_flip = intel_crtc_page_flip,
9313};
9314
79f689aa
PZ		 9315static void intel_cpu_pll_init(struct drm_device *dev)
9316{
affa9354 9317 if (HAS_DDI(dev))
79f689aa
PZ		 9318 intel_ddi_pll_init(dev);
9319}
9320
5358901f
DV		 9321static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9322 struct intel_shared_dpll *pll,
9323 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9324{
5358901f 9325 uint32_t val;
ee7b9f93 9326
5358901f 9327 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9328 hw_state->dpll = val;
9329 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9330 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9331
9332 return val & DPLL_VCO_ENABLE;
9333}
9334
15bdd4cf
DV		 9335static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9336 struct intel_shared_dpll *pll)
9337{
9338 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9339 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9340}
9341
e7b903d2
DV		 9342static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9343 struct intel_shared_dpll *pll)
9344{
e7b903d2
DV		 9345 /* PCH refclock must be enabled first */
9346 assert_pch_refclk_enabled(dev_priv);
9347
15bdd4cf
DV		 9348 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9349
9350 /* Wait for the clocks to stabilize. */
9351 POSTING_READ(PCH_DPLL(pll->id));
9352 udelay(150);
9353
9354 /* The pixel multiplier can only be updated once the
9355 * DPLL is enabled and the clocks are stable.
9356 *
9357 * So write it again.
9358 */
9359 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9360 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9361 udelay(200);
9362}
9363
9364static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9365 struct intel_shared_dpll *pll)
9366{
9367 struct drm_device *dev = dev_priv->dev;
9368 struct intel_crtc *crtc;
e7b903d2
DV		 9369
9370 /* Make sure no transcoder isn't still depending on us. */
9371 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9372 if (intel_crtc_to_shared_dpll(crtc) == pll)
9373 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9374 }
9375
15bdd4cf
DV		 9376 I915_WRITE(PCH_DPLL(pll->id), 0);
9377 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9378 udelay(200);
9379}
9380
46edb027
DV		 9381static char *ibx_pch_dpll_names[] = {
9382 "PCH DPLL A",
9383 "PCH DPLL B",
9384};
9385
7c74ade1 9386static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9387{
e7b903d2 9388 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9389 int i;
9390
7c74ade1 9391 dev_priv->num_shared_dpll = 2;
ee7b9f93 9392
e72f9fbf 9393 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9394 dev_priv->shared_dplls[i].id = i;
9395 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9396 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9397 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9398 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9399 dev_priv->shared_dplls[i].get_hw_state =
9400 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9401 }
9402}
9403
7c74ade1
DV		 9404static void intel_shared_dpll_init(struct drm_device *dev)
9405{
e7b903d2 9406 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9407
9408 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9409 ibx_pch_dpll_init(dev);
9410 else
9411 dev_priv->num_shared_dpll = 0;
9412
9413 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9414 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9415 dev_priv->num_shared_dpll);
9416}
9417
b358d0a6 9418static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9419{
22fd0fab 9420 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9421 struct intel_crtc *intel_crtc;
9422 int i;
9423
9424 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9425 if (intel_crtc == NULL)
9426 return;
9427
9428 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9429
9430 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9431 for (i = 0; i < 256; i++) {
9432 intel_crtc->lut_r[i] = i;
9433 intel_crtc->lut_g[i] = i;
9434 intel_crtc->lut_b[i] = i;
9435 }
9436
80824003
JB		 9437 /* Swap pipes & planes for FBC on pre-965 */
9438 intel_crtc->pipe = pipe;
9439 intel_crtc->plane = pipe;
e2e767ab 9440 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9441 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9442 intel_crtc->plane = !pipe;
80824003
JB		 9443 }
9444
22fd0fab
JB		 9445 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9446 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9447 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9448 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9449
79e53945 9450 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9451}
9452
08d7b3d1 9453int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9454 struct drm_file *file)
08d7b3d1 9455{
08d7b3d1 9456 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9457 struct drm_mode_object *drmmode_obj;
9458 struct intel_crtc *crtc;
08d7b3d1 9459
1cff8f6b
DV		 9460 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9461 return -ENODEV;
08d7b3d1 9462
c05422d5
DV		 9463 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9464 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9465
c05422d5 9466 if (!drmmode_obj) {
08d7b3d1
CW		 9467 DRM_ERROR("no such CRTC id\n");
9468 return -EINVAL;
9469 }
9470
c05422d5
DV		 9471 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9472 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9473
c05422d5 9474 return 0;
08d7b3d1
CW		 9475}
9476
66a9278e 9477static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9478{
66a9278e
DV		 9479 struct drm_device *dev = encoder->base.dev;
9480 struct intel_encoder *source_encoder;
79e53945 9481 int index_mask = 0;
79e53945
JB		 9482 int entry = 0;
9483
66a9278e
DV		 9484 list_for_each_entry(source_encoder,
9485 &dev->mode_config.encoder_list, base.head) {
9486
9487 if (encoder == source_encoder)
79e53945 9488 index_mask |= (1 << entry);
66a9278e
DV		 9489
9490 /* Intel hw has only one MUX where enocoders could be cloned. */
9491 if (encoder->cloneable && source_encoder->cloneable)
9492 index_mask |= (1 << entry);
9493
79e53945
JB		 9494 entry++;
9495 }
4ef69c7a 9496
79e53945
JB		 9497 return index_mask;
9498}
9499
4d302442
CW		 9500static bool has_edp_a(struct drm_device *dev)
9501{
9502 struct drm_i915_private *dev_priv = dev->dev_private;
9503
9504 if (!IS_MOBILE(dev))
9505 return false;
9506
9507 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9508 return false;
9509
9510 if (IS_GEN5(dev) &&
9511 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9512 return false;
9513
9514 return true;
9515}
9516
79e53945
JB		 9517static void intel_setup_outputs(struct drm_device *dev)
9518{
725e30ad 9519 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9520 struct intel_encoder *encoder;
cb0953d7 9521 bool dpd_is_edp = false;
79e53945 9522
c9093354 9523 intel_lvds_init(dev);
79e53945 9524
c40c0f5b 9525 if (!IS_ULT(dev))
79935fca 9526 intel_crt_init(dev);
cb0953d7 9527
affa9354 9528 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9529 int found;
9530
9531 /* Haswell uses DDI functions to detect digital outputs */
9532 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9533 /* DDI A only supports eDP */
9534 if (found)
9535 intel_ddi_init(dev, PORT_A);
9536
9537 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9538 * register */
9539 found = I915_READ(SFUSE_STRAP);
9540
9541 if (found & SFUSE_STRAP_DDIB_DETECTED)
9542 intel_ddi_init(dev, PORT_B);
9543 if (found & SFUSE_STRAP_DDIC_DETECTED)
9544 intel_ddi_init(dev, PORT_C);
9545 if (found & SFUSE_STRAP_DDID_DETECTED)
9546 intel_ddi_init(dev, PORT_D);
9547 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9548 int found;
270b3042
DV		 9549 dpd_is_edp = intel_dpd_is_edp(dev);
9550
9551 if (has_edp_a(dev))
9552 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9553
dc0fa718 9554 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9555 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9556 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9557 if (!found)
e2debe91 9558 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9559 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9560 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9561 }
9562
dc0fa718 9563 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9564 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9565
dc0fa718 9566 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9567 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9568
5eb08b69 9569 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9570 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9571
270b3042 9572 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9573 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9574 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9575 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9576 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9577 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9578 PORT_C);
9579 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9580 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9581 PORT_C);
9582 }
19c03924 9583
dc0fa718 9584 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9585 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9586 PORT_B);
67cfc203
VS		 9587 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9588 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9589 }
103a196f 9590 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9591 bool found = false;
7d57382e 9592
e2debe91 9593 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9594 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9595 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9596 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9597 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9598 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9599 }
27185ae1 9600
e7281eab 9601 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9602 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9603 }
13520b05
KH		 9604
9605 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9606
e2debe91 9607 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9608 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9609 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9610 }
27185ae1 9611
e2debe91 9612 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9613
b01f2c3a
JB		 9614 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9615 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9616 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9617 }
e7281eab 9618 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9619 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9620 }
27185ae1 9621
b01f2c3a 9622 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9623 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9624 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9625 } else if (IS_GEN2(dev))
79e53945
JB		 9626 intel_dvo_init(dev);
9627
103a196f 9628 if (SUPPORTS_TV(dev))
79e53945
JB		 9629 intel_tv_init(dev);
9630
4ef69c7a
CW		 9631 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9632 encoder->base.possible_crtcs = encoder->crtc_mask;
9633 encoder->base.possible_clones =
66a9278e 9634 intel_encoder_clones(encoder);
79e53945 9635 }
47356eb6 9636
dde86e2d 9637 intel_init_pch_refclk(dev);
270b3042
DV		 9638
9639 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9640}
9641
ddfe1567
CW		 9642void intel_framebuffer_fini(struct intel_framebuffer *fb)
9643{
9644 drm_framebuffer_cleanup(&fb->base);
9645 drm_gem_object_unreference_unlocked(&fb->obj->base);
9646}
9647
79e53945
JB		 9648static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9649{
9650 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9651
ddfe1567 9652 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9653 kfree(intel_fb);
9654}
9655
9656static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9657 struct drm_file *file,
79e53945
JB		 9658 unsigned int *handle)
9659{
9660 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9661 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9662
05394f39 9663 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9664}
9665
9666static const struct drm_framebuffer_funcs intel_fb_funcs = {
9667 .destroy = intel_user_framebuffer_destroy,
9668 .create_handle = intel_user_framebuffer_create_handle,
9669};
9670
38651674
DA		 9671int intel_framebuffer_init(struct drm_device *dev,
9672 struct intel_framebuffer *intel_fb,
308e5bcb 9673 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9674 struct drm_i915_gem_object *obj)
79e53945 9675{
a35cdaa0 9676 int pitch_limit;
79e53945
JB		 9677 int ret;
9678
c16ed4be
CW		 9679 if (obj->tiling_mode == I915_TILING_Y) {
9680 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9681 return -EINVAL;
c16ed4be 9682 }
57cd6508 9683
c16ed4be
CW		 9684 if (mode_cmd->pitches[0] & 63) {
9685 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9686 mode_cmd->pitches[0]);
57cd6508 9687 return -EINVAL;
c16ed4be 9688 }
57cd6508 9689
a35cdaa0
CW		 9690 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9691 pitch_limit = 32*1024;
9692 } else if (INTEL_INFO(dev)->gen >= 4) {
9693 if (obj->tiling_mode)
9694 pitch_limit = 16*1024;
9695 else
9696 pitch_limit = 32*1024;
9697 } else if (INTEL_INFO(dev)->gen >= 3) {
9698 if (obj->tiling_mode)
9699 pitch_limit = 8*1024;
9700 else
9701 pitch_limit = 16*1024;
9702 } else
9703 /* XXX DSPC is limited to 4k tiled */
9704 pitch_limit = 8*1024;
9705
9706 if (mode_cmd->pitches[0] > pitch_limit) {
9707 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9708 obj->tiling_mode ? "tiled" : "linear",
9709 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9710 return -EINVAL;
c16ed4be 9711 }
5d7bd705
VS		 9712
9713 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9714 mode_cmd->pitches[0] != obj->stride) {
9715 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9716 mode_cmd->pitches[0], obj->stride);
5d7bd705 9717 return -EINVAL;
c16ed4be 9718 }
5d7bd705 9719
57779d06 9720 /* Reject formats not supported by any plane early. */
308e5bcb 9721 switch (mode_cmd->pixel_format) {
57779d06 9722 case DRM_FORMAT_C8:
04b3924d
VS		 9723 case DRM_FORMAT_RGB565:
9724 case DRM_FORMAT_XRGB8888:
9725 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9726 break;
9727 case DRM_FORMAT_XRGB1555:
9728 case DRM_FORMAT_ARGB1555:
c16ed4be 9729 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9730 DRM_DEBUG("unsupported pixel format: %s\n",
9731 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9732 return -EINVAL;
c16ed4be 9733 }
57779d06
VS		 9734 break;
9735 case DRM_FORMAT_XBGR8888:
9736 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9737 case DRM_FORMAT_XRGB2101010:
9738 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9739 case DRM_FORMAT_XBGR2101010:
9740 case DRM_FORMAT_ABGR2101010:
c16ed4be 9741 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9742 DRM_DEBUG("unsupported pixel format: %s\n",
9743 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9744 return -EINVAL;
c16ed4be 9745 }
b5626747 9746 break;
04b3924d
VS		 9747 case DRM_FORMAT_YUYV:
9748 case DRM_FORMAT_UYVY:
9749 case DRM_FORMAT_YVYU:
9750 case DRM_FORMAT_VYUY:
c16ed4be 9751 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9752 DRM_DEBUG("unsupported pixel format: %s\n",
9753 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9754 return -EINVAL;
c16ed4be 9755 }
57cd6508
CW		 9756 break;
9757 default:
4ee62c76
VS		 9758 DRM_DEBUG("unsupported pixel format: %s\n",
9759 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9760 return -EINVAL;
9761 }
9762
90f9a336
VS		 9763 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9764 if (mode_cmd->offsets[0] != 0)
9765 return -EINVAL;
9766
c7d73f6a
DV		 9767 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9768 intel_fb->obj = obj;
9769
79e53945
JB		 9770 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9771 if (ret) {
9772 DRM_ERROR("framebuffer init failed %d\n", ret);
9773 return ret;
9774 }
9775
79e53945
JB		 9776 return 0;
9777}
9778
79e53945
JB		 9779static struct drm_framebuffer *
9780intel_user_framebuffer_create(struct drm_device *dev,
9781 struct drm_file *filp,
308e5bcb 9782 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9783{
05394f39 9784 struct drm_i915_gem_object *obj;
79e53945 9785
308e5bcb
JB		 9786 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9787 mode_cmd->handles[0]));
c8725226 9788 if (&obj->base == NULL)
cce13ff7 9789 return ERR_PTR(-ENOENT);
79e53945 9790
d2dff872 9791 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9792}
9793
79e53945 9794static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9795 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9796 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9797};
9798
e70236a8
JB		 9799/* Set up chip specific display functions */
9800static void intel_init_display(struct drm_device *dev)
9801{
9802 struct drm_i915_private *dev_priv = dev->dev_private;
9803
ee9300bb
DV		 9804 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9805 dev_priv->display.find_dpll = g4x_find_best_dpll;
9806 else if (IS_VALLEYVIEW(dev))
9807 dev_priv->display.find_dpll = vlv_find_best_dpll;
9808 else if (IS_PINEVIEW(dev))
9809 dev_priv->display.find_dpll = pnv_find_best_dpll;
9810 else
9811 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9812
affa9354 9813 if (HAS_DDI(dev)) {
0e8ffe1b 9814 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9815 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9816 dev_priv->display.crtc_enable = haswell_crtc_enable;
9817 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9818 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9819 dev_priv->display.update_plane = ironlake_update_plane;
9820 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9821 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9822 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9823 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9824 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9825 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9826 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9827 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9828 } else if (IS_VALLEYVIEW(dev)) {
9829 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9830 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9831 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9832 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9833 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9834 dev_priv->display.off = i9xx_crtc_off;
9835 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9836 } else {
0e8ffe1b 9837 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9838 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9839 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9840 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9841 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9842 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9843 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9844 }
e70236a8 9845
e70236a8 9846 /* Returns the core display clock speed */
25eb05fc
JB		 9847 if (IS_VALLEYVIEW(dev))
9848 dev_priv->display.get_display_clock_speed =
9849 valleyview_get_display_clock_speed;
9850 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9851 dev_priv->display.get_display_clock_speed =
9852 i945_get_display_clock_speed;
9853 else if (IS_I915G(dev))
9854 dev_priv->display.get_display_clock_speed =
9855 i915_get_display_clock_speed;
257a7ffc 9856 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9857 dev_priv->display.get_display_clock_speed =
9858 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9859 else if (IS_PINEVIEW(dev))
9860 dev_priv->display.get_display_clock_speed =
9861 pnv_get_display_clock_speed;
e70236a8
JB		 9862 else if (IS_I915GM(dev))
9863 dev_priv->display.get_display_clock_speed =
9864 i915gm_get_display_clock_speed;
9865 else if (IS_I865G(dev))
9866 dev_priv->display.get_display_clock_speed =
9867 i865_get_display_clock_speed;
f0f8a9ce 9868 else if (IS_I85X(dev))
e70236a8
JB		 9869 dev_priv->display.get_display_clock_speed =
9870 i855_get_display_clock_speed;
9871 else /* 852, 830 */
9872 dev_priv->display.get_display_clock_speed =
9873 i830_get_display_clock_speed;
9874
7f8a8569 9875 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9876 if (IS_GEN5(dev)) {
674cf967 9877 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9878 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9879 } else if (IS_GEN6(dev)) {
674cf967 9880 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9881 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9882 } else if (IS_IVYBRIDGE(dev)) {
9883 /* FIXME: detect B0+ stepping and use auto training */
9884 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9885 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9886 dev_priv->display.modeset_global_resources =
9887 ivb_modeset_global_resources;
c82e4d26
ED		 9888 } else if (IS_HASWELL(dev)) {
9889 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9890 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9891 dev_priv->display.modeset_global_resources =
9892 haswell_modeset_global_resources;
a0e63c22 9893 }
6067aaea 9894 } else if (IS_G4X(dev)) {
e0dac65e 9895 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9896 }
8c9f3aaf
JB		 9897
9898 /* Default just returns -ENODEV to indicate unsupported */
9899 dev_priv->display.queue_flip = intel_default_queue_flip;
9900
9901 switch (INTEL_INFO(dev)->gen) {
9902 case 2:
9903 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9904 break;
9905
9906 case 3:
9907 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9908 break;
9909
9910 case 4:
9911 case 5:
9912 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9913 break;
9914
9915 case 6:
9916 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9917 break;
7c9017e5
JB		 9918 case 7:
9919 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9920 break;
8c9f3aaf 9921 }
e70236a8
JB		 9922}
9923
b690e96c
JB		 9924/*
9925 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9926 * resume, or other times. This quirk makes sure that's the case for
9927 * affected systems.
9928 */
0206e353 9929static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9930{
9931 struct drm_i915_private *dev_priv = dev->dev_private;
9932
9933 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9934 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9935}
9936
435793df
KP		 9937/*
9938 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9939 */
9940static void quirk_ssc_force_disable(struct drm_device *dev)
9941{
9942 struct drm_i915_private *dev_priv = dev->dev_private;
9943 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9944 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9945}
9946
4dca20ef 9947/*
5a15ab5b
CE		 9948 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9949 * brightness value
4dca20ef
CE		 9950 */
9951static void quirk_invert_brightness(struct drm_device *dev)
9952{
9953 struct drm_i915_private *dev_priv = dev->dev_private;
9954 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9955 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9956}
9957
e85843be
KM		 9958/*
9959 * Some machines (Dell XPS13) suffer broken backlight controls if
9960 * BLM_PCH_PWM_ENABLE is set.
9961 */
9962static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9963{
9964 struct drm_i915_private *dev_priv = dev->dev_private;
9965 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9966 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9967}
9968
b690e96c
JB		 9969struct intel_quirk {
9970 int device;
9971 int subsystem_vendor;
9972 int subsystem_device;
9973 void (*hook)(struct drm_device *dev);
9974};
9975
5f85f176
EE		 9976/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9977struct intel_dmi_quirk {
9978 void (*hook)(struct drm_device *dev);
9979 const struct dmi_system_id (*dmi_id_list)[];
9980};
9981
9982static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9983{
9984 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9985 return 1;
9986}
9987
9988static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9989 {
9990 .dmi_id_list = &(const struct dmi_system_id[]) {
9991 {
9992 .callback = intel_dmi_reverse_brightness,
9993 .ident = "NCR Corporation",
9994 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9995 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9996 },
9997 },
9998 { } /* terminating entry */
9999 },
10000 .hook = quirk_invert_brightness,
10001 },
10002};
10003
c43b5634 10004static struct intel_quirk intel_quirks[] = {
b690e96c 10005 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10006 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10007
b690e96c
JB		 10008 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10009 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10010
b690e96c
JB		 10011 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10012 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10013
ccd0d36e 10014 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10015 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10016 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10017
10018 /* Lenovo U160 cannot use SSC on LVDS */
10019 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10020
10021 /* Sony Vaio Y cannot use SSC on LVDS */
10022 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10023
10024 /* Acer Aspire 5734Z must invert backlight brightness */
10025 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10026
10027 /* Acer/eMachines G725 */
10028 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10029
10030 /* Acer/eMachines e725 */
10031 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10032
10033 /* Acer/Packard Bell NCL20 */
10034 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10035
10036 /* Acer Aspire 4736Z */
10037 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10038
10039 /* Dell XPS13 HD Sandy Bridge */
10040 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10041 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10042 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10043};
10044
10045static void intel_init_quirks(struct drm_device *dev)
10046{
10047 struct pci_dev *d = dev->pdev;
10048 int i;
10049
10050 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10051 struct intel_quirk *q = &intel_quirks[i];
10052
10053 if (d->device == q->device &&
10054 (d->subsystem_vendor == q->subsystem_vendor ||
10055 q->subsystem_vendor == PCI_ANY_ID) &&
10056 (d->subsystem_device == q->subsystem_device ||
10057 q->subsystem_device == PCI_ANY_ID))
10058 q->hook(dev);
10059 }
5f85f176
EE		 10060 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10061 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10062 intel_dmi_quirks[i].hook(dev);
10063 }
b690e96c
JB		 10064}
10065
9cce37f4
JB		 10066/* Disable the VGA plane that we never use */
10067static void i915_disable_vga(struct drm_device *dev)
10068{
10069 struct drm_i915_private *dev_priv = dev->dev_private;
10070 u8 sr1;
766aa1c4 10071 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10072
10073 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10074 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10075 sr1 = inb(VGA_SR_DATA);
10076 outb(sr1 | 1<<5, VGA_SR_DATA);
10077 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10078 udelay(300);
10079
10080 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10081 POSTING_READ(vga_reg);
10082}
10083
f817586c
DV		 10084void intel_modeset_init_hw(struct drm_device *dev)
10085{
fa42e23c 10086 intel_init_power_well(dev);
0232e927 10087
a8f78b58
ED		 10088 intel_prepare_ddi(dev);
10089
f817586c
DV		 10090 intel_init_clock_gating(dev);
10091
79f5b2c7 10092 mutex_lock(&dev->struct_mutex);
8090c6b9 10093 intel_enable_gt_powersave(dev);
79f5b2c7 10094 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10095}
10096
7d708ee4
ID		 10097void intel_modeset_suspend_hw(struct drm_device *dev)
10098{
10099 intel_suspend_hw(dev);
10100}
10101
79e53945
JB		 10102void intel_modeset_init(struct drm_device *dev)
10103{
652c393a 10104 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10105 int i, j, ret;
79e53945
JB		 10106
10107 drm_mode_config_init(dev);
10108
10109 dev->mode_config.min_width = 0;
10110 dev->mode_config.min_height = 0;
10111
019d96cb
DA		 10112 dev->mode_config.preferred_depth = 24;
10113 dev->mode_config.prefer_shadow = 1;
10114
e6ecefaa 10115 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10116
b690e96c
JB		 10117 intel_init_quirks(dev);
10118
1fa61106
ED		 10119 intel_init_pm(dev);
10120
e3c74757
BW		 10121 if (INTEL_INFO(dev)->num_pipes == 0)
10122 return;
10123
e70236a8
JB		 10124 intel_init_display(dev);
10125
a6c45cf0
CW		 10126 if (IS_GEN2(dev)) {
10127 dev->mode_config.max_width = 2048;
10128 dev->mode_config.max_height = 2048;
10129 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10130 dev->mode_config.max_width = 4096;
10131 dev->mode_config.max_height = 4096;
79e53945 10132 } else {
a6c45cf0
CW		 10133 dev->mode_config.max_width = 8192;
10134 dev->mode_config.max_height = 8192;
79e53945 10135 }
5d4545ae 10136 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10137
28c97730 10138 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10139 INTEL_INFO(dev)->num_pipes,
10140 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10141
08e2a7de 10142 for_each_pipe(i) {
79e53945 10143 intel_crtc_init(dev, i);
7f1f3851
JB		 10144 for (j = 0; j < dev_priv->num_plane; j++) {
10145 ret = intel_plane_init(dev, i, j);
10146 if (ret)
06da8da2
VS		 10147 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10148 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10149 }
79e53945
JB		 10150 }
10151
79f689aa 10152 intel_cpu_pll_init(dev);
e72f9fbf 10153 intel_shared_dpll_init(dev);
ee7b9f93 10154
9cce37f4
JB		 10155 /* Just disable it once at startup */
10156 i915_disable_vga(dev);
79e53945 10157 intel_setup_outputs(dev);
11be49eb
CW		 10158
10159 /* Just in case the BIOS is doing something questionable. */
10160 intel_disable_fbc(dev);
2c7111db
CW		 10161}
10162
24929352
DV		 10163static void
10164intel_connector_break_all_links(struct intel_connector *connector)
10165{
10166 connector->base.dpms = DRM_MODE_DPMS_OFF;
10167 connector->base.encoder = NULL;
10168 connector->encoder->connectors_active = false;
10169 connector->encoder->base.crtc = NULL;
10170}
10171
7fad798e
DV		 10172static void intel_enable_pipe_a(struct drm_device *dev)
10173{
10174 struct intel_connector *connector;
10175 struct drm_connector *crt = NULL;
10176 struct intel_load_detect_pipe load_detect_temp;
10177
10178 /* We can't just switch on the pipe A, we need to set things up with a
10179 * proper mode and output configuration. As a gross hack, enable pipe A
10180 * by enabling the load detect pipe once. */
10181 list_for_each_entry(connector,
10182 &dev->mode_config.connector_list,
10183 base.head) {
10184 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10185 crt = &connector->base;
10186 break;
10187 }
10188 }
10189
10190 if (!crt)
10191 return;
10192
10193 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10194 intel_release_load_detect_pipe(crt, &load_detect_temp);
10195
652c393a 10196
7fad798e
DV		 10197}
10198
fa555837
DV		 10199static bool
10200intel_check_plane_mapping(struct intel_crtc *crtc)
10201{
7eb552ae
BW		 10202 struct drm_device *dev = crtc->base.dev;
10203 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10204 u32 reg, val;
10205
7eb552ae 10206 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10207 return true;
10208
10209 reg = DSPCNTR(!crtc->plane);
10210 val = I915_READ(reg);
10211
10212 if ((val & DISPLAY_PLANE_ENABLE) &&
10213 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10214 return false;
10215
10216 return true;
10217}
10218
24929352
DV		 10219static void intel_sanitize_crtc(struct intel_crtc *crtc)
10220{
10221 struct drm_device *dev = crtc->base.dev;
10222 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10223 u32 reg;
24929352 10224
24929352 10225 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10226 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10227 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10228
10229 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10230 * disable the crtc (and hence change the state) if it is wrong. Note
10231 * that gen4+ has a fixed plane -> pipe mapping. */
10232 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10233 struct intel_connector *connector;
10234 bool plane;
10235
24929352
DV		 10236 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10237 crtc->base.base.id);
10238
10239 /* Pipe has the wrong plane attached and the plane is active.
10240 * Temporarily change the plane mapping and disable everything
10241 * ... */
10242 plane = crtc->plane;
10243 crtc->plane = !plane;
10244 dev_priv->display.crtc_disable(&crtc->base);
10245 crtc->plane = plane;
10246
10247 /* ... and break all links. */
10248 list_for_each_entry(connector, &dev->mode_config.connector_list,
10249 base.head) {
10250 if (connector->encoder->base.crtc != &crtc->base)
10251 continue;
10252
10253 intel_connector_break_all_links(connector);
10254 }
10255
10256 WARN_ON(crtc->active);
10257 crtc->base.enabled = false;
10258 }
24929352 10259
7fad798e
DV		 10260 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10261 crtc->pipe == PIPE_A && !crtc->active) {
10262 /* BIOS forgot to enable pipe A, this mostly happens after
10263 * resume. Force-enable the pipe to fix this, the update_dpms
10264 * call below we restore the pipe to the right state, but leave
10265 * the required bits on. */
10266 intel_enable_pipe_a(dev);
10267 }
10268
24929352
DV		 10269 /* Adjust the state of the output pipe according to whether we
10270 * have active connectors/encoders. */
10271 intel_crtc_update_dpms(&crtc->base);
10272
10273 if (crtc->active != crtc->base.enabled) {
10274 struct intel_encoder *encoder;
10275
10276 /* This can happen either due to bugs in the get_hw_state
10277 * functions or because the pipe is force-enabled due to the
10278 * pipe A quirk. */
10279 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10280 crtc->base.base.id,
10281 crtc->base.enabled ? "enabled" : "disabled",
10282 crtc->active ? "enabled" : "disabled");
10283
10284 crtc->base.enabled = crtc->active;
10285
10286 /* Because we only establish the connector -> encoder ->
10287 * crtc links if something is active, this means the
10288 * crtc is now deactivated. Break the links. connector
10289 * -> encoder links are only establish when things are
10290 * actually up, hence no need to break them. */
10291 WARN_ON(crtc->active);
10292
10293 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10294 WARN_ON(encoder->connectors_active);
10295 encoder->base.crtc = NULL;
10296 }
10297 }
10298}
10299
10300static void intel_sanitize_encoder(struct intel_encoder *encoder)
10301{
10302 struct intel_connector *connector;
10303 struct drm_device *dev = encoder->base.dev;
10304
10305 /* We need to check both for a crtc link (meaning that the
10306 * encoder is active and trying to read from a pipe) and the
10307 * pipe itself being active. */
10308 bool has_active_crtc = encoder->base.crtc &&
10309 to_intel_crtc(encoder->base.crtc)->active;
10310
10311 if (encoder->connectors_active && !has_active_crtc) {
10312 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10313 encoder->base.base.id,
10314 drm_get_encoder_name(&encoder->base));
10315
10316 /* Connector is active, but has no active pipe. This is
10317 * fallout from our resume register restoring. Disable
10318 * the encoder manually again. */
10319 if (encoder->base.crtc) {
10320 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10321 encoder->base.base.id,
10322 drm_get_encoder_name(&encoder->base));
10323 encoder->disable(encoder);
10324 }
10325
10326 /* Inconsistent output/port/pipe state happens presumably due to
10327 * a bug in one of the get_hw_state functions. Or someplace else
10328 * in our code, like the register restore mess on resume. Clamp
10329 * things to off as a safer default. */
10330 list_for_each_entry(connector,
10331 &dev->mode_config.connector_list,
10332 base.head) {
10333 if (connector->encoder != encoder)
10334 continue;
10335
10336 intel_connector_break_all_links(connector);
10337 }
10338 }
10339 /* Enabled encoders without active connectors will be fixed in
10340 * the crtc fixup. */
10341}
10342
44cec740 10343void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10344{
10345 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10346 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10347
8dc8a27c
PZ		 10348 /* This function can be called both from intel_modeset_setup_hw_state or
10349 * at a very early point in our resume sequence, where the power well
10350 * structures are not yet restored. Since this function is at a very
10351 * paranoid "someone might have enabled VGA while we were not looking"
10352 * level, just check if the power well is enabled instead of trying to
10353 * follow the "don't touch the power well if we don't need it" policy
10354 * the rest of the driver uses. */
10355 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10356 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10357 return;
10358
0fde901f
KM		 10359 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10360 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10361 i915_disable_vga(dev);
0fde901f
KM		 10362 }
10363}
10364
30e984df 10365static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10366{
10367 struct drm_i915_private *dev_priv = dev->dev_private;
10368 enum pipe pipe;
24929352
DV		 10369 struct intel_crtc *crtc;
10370 struct intel_encoder *encoder;
10371 struct intel_connector *connector;
5358901f 10372 int i;
24929352 10373
0e8ffe1b
DV		 10374 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10375 base.head) {
88adfff1 10376 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10377
0e8ffe1b
DV		 10378 crtc->active = dev_priv->display.get_pipe_config(crtc,
10379 &crtc->config);
24929352
DV		 10380
10381 crtc->base.enabled = crtc->active;
10382
10383 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10384 crtc->base.base.id,
10385 crtc->active ? "enabled" : "disabled");
10386 }
10387
5358901f 10388 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10389 if (HAS_DDI(dev))
6441ab5f
PZ		 10390 intel_ddi_setup_hw_pll_state(dev);
10391
5358901f
DV		 10392 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10393 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10394
10395 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10396 pll->active = 0;
10397 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10398 base.head) {
10399 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10400 pll->active++;
10401 }
10402 pll->refcount = pll->active;
10403
35c95375
DV		 10404 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10405 pll->name, pll->refcount, pll->on);
5358901f
DV		 10406 }
10407
24929352
DV		 10408 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10409 base.head) {
10410 pipe = 0;
10411
10412 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10413 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10414 encoder->base.crtc = &crtc->base;
510d5f2f 10415 if (encoder->get_config)
045ac3b5 10416 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10417 } else {
10418 encoder->base.crtc = NULL;
10419 }
10420
10421 encoder->connectors_active = false;
10422 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10423 encoder->base.base.id,
10424 drm_get_encoder_name(&encoder->base),
10425 encoder->base.crtc ? "enabled" : "disabled",
10426 pipe);
10427 }
10428
510d5f2f
JB		 10429 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10430 base.head) {
10431 if (!crtc->active)
10432 continue;
10433 if (dev_priv->display.get_clock)
10434 dev_priv->display.get_clock(crtc,
10435 &crtc->config);
10436 }
10437
24929352
DV		 10438 list_for_each_entry(connector, &dev->mode_config.connector_list,
10439 base.head) {
10440 if (connector->get_hw_state(connector)) {
10441 connector->base.dpms = DRM_MODE_DPMS_ON;
10442 connector->encoder->connectors_active = true;
10443 connector->base.encoder = &connector->encoder->base;
10444 } else {
10445 connector->base.dpms = DRM_MODE_DPMS_OFF;
10446 connector->base.encoder = NULL;
10447 }
10448 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10449 connector->base.base.id,
10450 drm_get_connector_name(&connector->base),
10451 connector->base.encoder ? "enabled" : "disabled");
10452 }
30e984df
DV		 10453}
10454
10455/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10456 * and i915 state tracking structures. */
10457void intel_modeset_setup_hw_state(struct drm_device *dev,
10458 bool force_restore)
10459{
10460 struct drm_i915_private *dev_priv = dev->dev_private;
10461 enum pipe pipe;
10462 struct drm_plane *plane;
10463 struct intel_crtc *crtc;
10464 struct intel_encoder *encoder;
35c95375 10465 int i;
30e984df
DV		 10466
10467 intel_modeset_readout_hw_state(dev);
24929352 10468
babea61d
JB		 10469 /*
10470 * Now that we have the config, copy it to each CRTC struct
10471 * Note that this could go away if we move to using crtc_config
10472 * checking everywhere.
10473 */
10474 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10475 base.head) {
10476 if (crtc->active && i915_fastboot) {
10477 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10478
10479 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10480 crtc->base.base.id);
10481 drm_mode_debug_printmodeline(&crtc->base.mode);
10482 }
10483 }
10484
24929352
DV		 10485 /* HW state is read out, now we need to sanitize this mess. */
10486 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10487 base.head) {
10488 intel_sanitize_encoder(encoder);
10489 }
10490
10491 for_each_pipe(pipe) {
10492 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10493 intel_sanitize_crtc(crtc);
c0b03411 10494 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10495 }
9a935856 10496
35c95375
DV		 10497 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10498 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10499
10500 if (!pll->on || pll->active)
10501 continue;
10502
10503 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10504
10505 pll->disable(dev_priv, pll);
10506 pll->on = false;
10507 }
10508
45e2b5f6 10509 if (force_restore) {
f30da187
DV		 10510 /*
10511 * We need to use raw interfaces for restoring state to avoid
10512 * checking (bogus) intermediate states.
10513 */
45e2b5f6 10514 for_each_pipe(pipe) {
b5644d05
JB		 10515 struct drm_crtc *crtc =
10516 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10517
10518 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10519 crtc->fb);
45e2b5f6 10520 }
b5644d05
JB		 10521 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10522 intel_plane_restore(plane);
0fde901f
KM		 10523
10524 i915_redisable_vga(dev);
45e2b5f6
DV		 10525 } else {
10526 intel_modeset_update_staged_output_state(dev);
10527 }
8af6cf88
DV		 10528
10529 intel_modeset_check_state(dev);
2e938892
DV		 10530
10531 drm_mode_config_reset(dev);
2c7111db
CW		 10532}
10533
10534void intel_modeset_gem_init(struct drm_device *dev)
10535{
1833b134 10536 intel_modeset_init_hw(dev);
02e792fb
DV		 10537
10538 intel_setup_overlay(dev);
24929352 10539
45e2b5f6 10540 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10541}
10542
10543void intel_modeset_cleanup(struct drm_device *dev)
10544{
652c393a
JB		 10545 struct drm_i915_private *dev_priv = dev->dev_private;
10546 struct drm_crtc *crtc;
652c393a 10547
fd0c0642
DV		 10548 /*
10549 * Interrupts and polling as the first thing to avoid creating havoc.
10550 * Too much stuff here (turning of rps, connectors, ...) would
10551 * experience fancy races otherwise.
10552 */
10553 drm_irq_uninstall(dev);
10554 cancel_work_sync(&dev_priv->hotplug_work);
10555 /*
10556 * Due to the hpd irq storm handling the hotplug work can re-arm the
10557 * poll handlers. Hence disable polling after hpd handling is shut down.
10558 */
f87ea761 10559 drm_kms_helper_poll_fini(dev);
fd0c0642 10560
652c393a
JB		 10561 mutex_lock(&dev->struct_mutex);
10562
723bfd70
JB		 10563 intel_unregister_dsm_handler();
10564
652c393a
JB		 10565 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10566 /* Skip inactive CRTCs */
10567 if (!crtc->fb)
10568 continue;
10569
3dec0095 10570 intel_increase_pllclock(crtc);
652c393a
JB		 10571 }
10572
973d04f9 10573 intel_disable_fbc(dev);
e70236a8 10574
8090c6b9 10575 intel_disable_gt_powersave(dev);
0cdab21f 10576
930ebb46
DV		 10577 ironlake_teardown_rc6(dev);
10578
69341a5e
KH		 10579 mutex_unlock(&dev->struct_mutex);
10580
1630fe75
CW		 10581 /* flush any delayed tasks or pending work */
10582 flush_scheduled_work();
10583
dc652f90
JN		 10584 /* destroy backlight, if any, before the connectors */
10585 intel_panel_destroy_backlight(dev);
10586
79e53945 10587 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10588
10589 intel_cleanup_overlay(dev);
79e53945
JB		 10590}
10591
f1c79df3
ZW		 10592/*
10593 * Return which encoder is currently attached for connector.
10594 */
df0e9248 10595struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10596{
df0e9248
CW		 10597 return &intel_attached_encoder(connector)->base;
10598}
f1c79df3 10599
df0e9248
CW		 10600void intel_connector_attach_encoder(struct intel_connector *connector,
10601 struct intel_encoder *encoder)
10602{
10603 connector->encoder = encoder;
10604 drm_mode_connector_attach_encoder(&connector->base,
10605 &encoder->base);
79e53945 10606}
28d52043
DA		 10607
10608/*
10609 * set vga decode state - true == enable VGA decode
10610 */
10611int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10612{
10613 struct drm_i915_private *dev_priv = dev->dev_private;
10614 u16 gmch_ctrl;
10615
10616 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10617 if (state)
10618 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10619 else
10620 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10621 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10622 return 0;
10623}
c4a1d9e4 10624
c4a1d9e4 10625struct intel_display_error_state {
ff57f1b0
PZ		 10626
10627 u32 power_well_driver;
10628
63b66e5b
CW		 10629 int num_transcoders;
10630
c4a1d9e4
CW		 10631 struct intel_cursor_error_state {
10632 u32 control;
10633 u32 position;
10634 u32 base;
10635 u32 size;
52331309 10636 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10637
10638 struct intel_pipe_error_state {
c4a1d9e4 10639 u32 source;
52331309 10640 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10641
10642 struct intel_plane_error_state {
10643 u32 control;
10644 u32 stride;
10645 u32 size;
10646 u32 pos;
10647 u32 addr;
10648 u32 surface;
10649 u32 tile_offset;
52331309 10650 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10651
10652 struct intel_transcoder_error_state {
10653 enum transcoder cpu_transcoder;
10654
10655 u32 conf;
10656
10657 u32 htotal;
10658 u32 hblank;
10659 u32 hsync;
10660 u32 vtotal;
10661 u32 vblank;
10662 u32 vsync;
10663 } transcoder[4];
c4a1d9e4
CW		 10664};
10665
10666struct intel_display_error_state *
10667intel_display_capture_error_state(struct drm_device *dev)
10668{
0206e353 10669 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10670 struct intel_display_error_state *error;
63b66e5b
CW		 10671 int transcoders[] = {
10672 TRANSCODER_A,
10673 TRANSCODER_B,
10674 TRANSCODER_C,
10675 TRANSCODER_EDP,
10676 };
c4a1d9e4
CW		 10677 int i;
10678
63b66e5b
CW		 10679 if (INTEL_INFO(dev)->num_pipes == 0)
10680 return NULL;
10681
c4a1d9e4
CW		 10682 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10683 if (error == NULL)
10684 return NULL;
10685
ff57f1b0
PZ		 10686 if (HAS_POWER_WELL(dev))
10687 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10688
52331309 10689 for_each_pipe(i) {
a18c4c3d
PZ		 10690 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10691 error->cursor[i].control = I915_READ(CURCNTR(i));
10692 error->cursor[i].position = I915_READ(CURPOS(i));
10693 error->cursor[i].base = I915_READ(CURBASE(i));
10694 } else {
10695 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10696 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10697 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10698 }
c4a1d9e4
CW		 10699
10700 error->plane[i].control = I915_READ(DSPCNTR(i));
10701 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10702 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10703 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10704 error->plane[i].pos = I915_READ(DSPPOS(i));
10705 }
ca291363
PZ		 10706 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10707 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10708 if (INTEL_INFO(dev)->gen >= 4) {
10709 error->plane[i].surface = I915_READ(DSPSURF(i));
10710 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10711 }
10712
c4a1d9e4 10713 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10714 }
10715
10716 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10717 if (HAS_DDI(dev_priv->dev))
10718 error->num_transcoders++; /* Account for eDP. */
10719
10720 for (i = 0; i < error->num_transcoders; i++) {
10721 enum transcoder cpu_transcoder = transcoders[i];
10722
10723 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10724
10725 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10726 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10727 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10728 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10729 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10730 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10731 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10732 }
10733
12d217c7
PZ		 10734 /* In the code above we read the registers without checking if the power
10735 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10736 * prevent the next I915_WRITE from detecting it and printing an error
10737 * message. */
907b28c5 10738 intel_uncore_clear_errors(dev);
12d217c7 10739
c4a1d9e4
CW		 10740 return error;
10741}
10742
edc3d884
MK		 10743#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10744
c4a1d9e4 10745void
edc3d884 10746intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10747 struct drm_device *dev,
10748 struct intel_display_error_state *error)
10749{
10750 int i;
10751
63b66e5b
CW		 10752 if (!error)
10753 return;
10754
edc3d884 10755 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10756 if (HAS_POWER_WELL(dev))
edc3d884 10757 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10758 error->power_well_driver);
52331309 10759 for_each_pipe(i) {
edc3d884 10760 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10761 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10762
10763 err_printf(m, "Plane [%d]:\n", i);
10764 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10765 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10766 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10767 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10768 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10769 }
4b71a570 10770 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10771 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10772 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10773 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10774 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10775 }
10776
edc3d884
MK		 10777 err_printf(m, "Cursor [%d]:\n", i);
10778 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10779 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10780 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10781 }
63b66e5b
CW		 10782
10783 for (i = 0; i < error->num_transcoders; i++) {
10784 err_printf(m, " CPU transcoder: %c\n",
10785 transcoder_name(error->transcoder[i].cpu_transcoder));
10786 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10787 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10788 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10789 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10790 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10791 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10792 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10793 }
c4a1d9e4 10794}
Linux kernel - Deliverables
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