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drm/i915: get rid of intel_crtc_disable and related code, v3
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB		 91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV		 95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML		 113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA		 116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB		 126} intel_range_t;
127
128typedef struct {
0206e353
AJ		 129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB		 131} intel_p2_t;
132
d4906093
ML		 133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ		 135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV		 139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW		 149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW		 152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW		 157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ		 163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 170};
171
5d536e28
DV		 172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV		 176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP		 265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP		 279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 307};
308
273e27ca
EA		 309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 394};
395
ef9348c8
CML		 396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID		 412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS		 424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS		 430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 432}
433
e0638cdf
PZ		 434/**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
4093561b 437bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 438{
409ee761 439 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 440 struct intel_encoder *encoder;
441
409ee761 442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 443 if (encoder->type == type)
444 return true;
445
446 return false;
447}
448
d0737e1d
ACO		 449/**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
a93e255f
ACO		 455static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
d0737e1d 457{
a93e255f 458 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 459 struct drm_connector *connector;
a93e255f 460 struct drm_connector_state *connector_state;
d0737e1d 461 struct intel_encoder *encoder;
a93e255f
ACO		 462 int i, num_connectors = 0;
463
da3ced29 464 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
d0737e1d 469
a93e255f
ACO		 470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
d0737e1d 472 return true;
a93e255f
ACO		 473 }
474
475 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 476
477 return false;
478}
479
a93e255f
ACO		 480static const intel_limit_t *
481intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 482{
a93e255f 483 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 484 const intel_limit_t *limit;
b91ad0ec 485
a93e255f 486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 487 if (intel_is_dual_link_lvds(dev)) {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW		 489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
c6bb3538 498 } else
b91ad0ec 499 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 500
501 return limit;
502}
503
a93e255f
ACO		 504static const intel_limit_t *
505intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 506{
a93e255f 507 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 508 const intel_limit_t *limit;
509
a93e255f 510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 511 if (intel_is_dual_link_lvds(dev))
e4b36699 512 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 513 else
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
a93e255f 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
044c7c41 520 } else /* The option is for other outputs */
e4b36699 521 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 530 const intel_limit_t *limit;
531
5ab7b0b7
ID		 532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
a93e255f 535 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 536 else if (IS_G4X(dev)) {
a93e255f 537 limit = intel_g4x_limit(crtc_state);
f2b115e6 538 } else if (IS_PINEVIEW(dev)) {
a93e255f 539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 540 limit = &intel_limits_pineview_lvds;
2177832f 541 else
f2b115e6 542 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
a0c4da24 545 } else if (IS_VALLEYVIEW(dev)) {
dc730512 546 limit = &intel_limits_vlv;
a6c45cf0 547 } else if (!IS_GEN2(dev)) {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
79e53945 552 } else {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 554 limit = &intel_limits_i8xx_lvds;
a93e255f 555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 556 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 557 else
558 limit = &intel_limits_i8xx_dac;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
fb03ac01
VS		 570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 572}
573
7429e9d4
DV		 574static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575{
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577}
578
ac58c3f0 579static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 580{
7429e9d4 581 clock->m = i9xx_dpll_compute_m(clock);
79e53945 582 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
fb03ac01
VS		 585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 587}
588
ef9348c8
CML		 589static void chv_clock(int refclk, intel_clock_t *clock)
590{
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598}
599
7c04d1d9 600#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 601/**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
1b894b59
CW		 606static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
79e53945 609{
f01b7962
VS		 610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
79e53945 612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 613 INTELPllInvalid("p1 out of range\n");
79e53945 614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 615 INTELPllInvalid("m2 out of range\n");
79e53945 616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 617 INTELPllInvalid("m1 out of range\n");
f01b7962 618
5ab7b0b7 619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
5ab7b0b7 623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
79e53945 630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 631 INTELPllInvalid("vco out of range\n");
79e53945
JB		 632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 636 INTELPllInvalid("dot out of range\n");
79e53945
JB		 637
638 return true;
639}
640
d4906093 641static bool
a93e255f
ACO		 642i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
cec2f356
SP		 644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
79e53945 646{
a93e255f 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 648 struct drm_device *dev = crtc->base.dev;
79e53945 649 intel_clock_t clock;
79e53945
JB		 650 int err = target;
651
a93e255f 652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 653 /*
a210b028
DV		 654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
79e53945 657 */
1974cad0 658 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
0206e353 669 memset(best_clock, 0, sizeof(*best_clock));
79e53945 670
42158660
ZY		 671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 675 if (clock.m2 >= clock.m1)
42158660
ZY		 676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 681 int this_err;
682
ac58c3f0
DV		 683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702}
703
704static bool
a93e255f
ACO		 705pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
79e53945 709{
a93e255f 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 711 struct drm_device *dev = crtc->base.dev;
79e53945 712 intel_clock_t clock;
79e53945
JB		 713 int err = target;
714
a93e255f 715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 716 /*
a210b028
DV		 717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
79e53945 720 */
1974cad0 721 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
0206e353 732 memset(best_clock, 0, sizeof(*best_clock));
79e53945 733
42158660
ZY		 734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 742 int this_err;
743
ac58c3f0 744 pineview_clock(refclk, &clock);
1b894b59
CW		 745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
79e53945 747 continue;
cec2f356
SP		 748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
79e53945
JB		 751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763}
764
d4906093 765static bool
a93e255f
ACO		 766g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
d4906093 770{
a93e255f 771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 772 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 773 intel_clock_t clock;
774 int max_n;
775 bool found;
6ba770dc
AJ		 776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 778 found = false;
779
a93e255f 780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 781 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
f77f13e2 794 /* based on hardware requirement, prefer smaller n to precision */
d4906093 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 796 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
ac58c3f0 805 i9xx_clock(refclk, &clock);
1b894b59
CW		 806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
d4906093 808 continue;
1b894b59
CW		 809
810 this_err = abs(clock.dot - target);
d4906093
ML		 811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
2c07245f
ZW		 821 return found;
822}
823
d5dd62bd
ID		 824/*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833{
9ca3ba01
ID		 834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
24be4e46
ID		 844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
d5dd62bd
ID		 847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862}
863
a0c4da24 864static bool
a93e255f
ACO		 865vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
a0c4da24 869{
a93e255f 870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 871 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 872 intel_clock_t clock;
69e4f900 873 unsigned int bestppm = 1000000;
27e639bf
VS		 874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 876 bool found = false;
a0c4da24 877
6b4bf1c4
VS		 878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 881
882 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 887 clock.p = clock.p1 * clock.p2;
a0c4da24 888 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 890 unsigned int ppm;
69e4f900 891
6b4bf1c4
VS		 892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
43b0ac53 896
f01b7962
VS		 897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
43b0ac53
VS		 899 continue;
900
d5dd62bd
ID		 901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
6b4bf1c4 906
d5dd62bd
ID		 907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
a0c4da24
JB		 910 }
911 }
912 }
913 }
a0c4da24 914
49e497ef 915 return found;
a0c4da24 916}
a4fc5ed6 917
ef9348c8 918static bool
a93e255f
ACO		 919chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923{
a93e255f 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 925 struct drm_device *dev = crtc->base.dev;
9ca3ba01 926 unsigned int best_error_ppm;
ef9348c8
CML		 927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 932 best_error_ppm = 1000000;
ef9348c8
CML		 933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 946 unsigned int error_ppm;
ef9348c8
CML		 947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
9ca3ba01
ID		 963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
ef9348c8
CML		 970 }
971 }
972
973 return found;
974}
975
5ab7b0b7
ID		 976bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978{
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983}
984
20ddf665
VS		 985bool intel_crtc_active(struct drm_crtc *crtc)
986{
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
241bfc38 992 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 993 * as Haswell has gained clock readout/fastboot support.
994 *
66e514c1 995 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 996 * properly reconstruct framebuffers.
c3d1f436
MR		 997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
20ddf665 1001 */
c3d1f436 1002 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1004}
1005
a5c961d1
PZ		 1006enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008{
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
6e3c9717 1012 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1013}
1014
fbf49ea2
VS		 1015static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032}
1033
ab7ad7f6
KP		 1034/*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1036 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
ab7ad7f6
KP		 1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
58e10eb9 1048 *
9d0498a2 1049 */
575f7ab7 1050static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1051{
575f7ab7 1052 struct drm_device *dev = crtc->base.dev;
9d0498a2 1053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1055 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1058 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1059
1060 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 } else {
ab7ad7f6 1065 /* Wait for the display line to settle */
fbf49ea2 1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1067 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1068 }
79e53945
JB		 1069}
1070
b0ea7d37
DL		 1071/*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080{
1081 u32 bit;
1082
c36346e3 1083 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1084 switch (port->port) {
c36346e3
DL		 1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
eba905b2 1098 switch (port->port) {
c36346e3
DL		 1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
b0ea7d37
DL		 1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114}
1115
b24e7179
JB		 1116static const char *state_string(bool enabled)
1117{
1118 return enabled ? "on" : "off";
1119}
1120
1121/* Only for pre-ILK configs */
55607e8a
DV		 1122void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
b24e7179
JB		 1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1132 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
b24e7179 1136
23538ef1
JN		 1137/* XXX: the dsi pll is shared between MIPI DSI ports */
1138static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139{
1140 u32 val;
1141 bool cur_state;
1142
a580516d 1143 mutex_lock(&dev_priv->sb_lock);
23538ef1 1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1145 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1146
1147 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1148 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151}
1152#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
55607e8a 1155struct intel_shared_dpll *
e2b78267
DV		 1156intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157{
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
6e3c9717 1160 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1161 return NULL;
1162
6e3c9717 1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1164}
1165
040484af 1166/* For ILK+ */
55607e8a
DV		 1167void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
040484af 1170{
040484af 1171 bool cur_state;
5358901f 1172 struct intel_dpll_hw_state hw_state;
040484af 1173
92b27b08 1174 if (WARN (!pll,
46edb027 1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1176 return;
ee7b9f93 1177
5358901f 1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1179 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
040484af 1182}
040484af
JB		 1183
1184static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186{
1187 int reg;
1188 u32 val;
1189 bool cur_state;
ad80a810
PZ		 1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
040484af 1192
affa9354
PZ		 1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
ad80a810 1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1196 val = I915_READ(reg);
ad80a810 1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
e2c719b7 1203 I915_STATE_WARN(cur_state != state,
040484af
JB		 1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206}
1207#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212{
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
d63fa0dc
PZ		 1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1220 I915_STATE_WARN(cur_state != state,
040484af
JB		 1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223}
1224#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229{
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
3d13ef2e 1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1235 return;
1236
bf507ef7 1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1238 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1239 return;
1240
040484af
JB		 1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
e2c719b7 1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1244}
1245
55607e8a
DV		 1246void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
040484af
JB		 1248{
1249 int reg;
1250 u32 val;
55607e8a 1251 bool cur_state;
040484af
JB		 1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
55607e8a 1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
040484af
JB		 1259}
1260
b680c37a
DV		 1261void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
ea0760cf 1263{
bedd4dba
JN		 1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
ea0760cf
JB		 1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
0de3b485 1268 bool locked = true;
ea0760cf 1269
bedd4dba
JN		 1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
ea0760cf 1276 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
ea0760cf
JB		 1287 } else {
1288 pp_reg = PP_CONTROL;
bedd4dba
JN		 1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
ea0760cf
JB		 1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1296 locked = false;
1297
e2c719b7 1298 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1299 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1300 pipe_name(pipe));
ea0760cf
JB		 1301}
1302
93ce0ba6
JN		 1303static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305{
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
d9d82081 1309 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1311 else
5efb3e28 1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1313
e2c719b7 1314 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317}
1318#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
b840d907
JB		 1321void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
b24e7179
JB		 1323{
1324 int reg;
1325 u32 val;
63d7bbe9 1326 bool cur_state;
702e7a56
PZ		 1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
b24e7179 1329
b6b5d049
VS		 1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1333 state = true;
1334
f458ebbc 1335 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
63d7bbe9 1345 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1346 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
b24e7179
JB		 1351{
1352 int reg;
1353 u32 val;
931872fc 1354 bool cur_state;
b24e7179
JB		 1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
931872fc 1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1359 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1362}
1363
931872fc
CW		 1364#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
b24e7179
JB		 1367static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369{
653e1026 1370 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
653e1026
VS		 1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
e2c719b7 1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
19ec1358 1382 return;
28c05794 1383 }
19ec1358 1384
b24e7179 1385 /* Need to check both planes against the pipe */
055e393f 1386 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1394 }
1395}
1396
19332d7a
JB		 1397static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
20674eef 1400 struct drm_device *dev = dev_priv->dev;
1fe47785 1401 int reg, sprite;
19332d7a
JB		 1402 u32 val;
1403
7feb8b88 1404 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1406 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1412 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1413 reg = SPCNTR(pipe, sprite);
20674eef 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1417 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
19332d7a 1421 val = I915_READ(reg);
e2c719b7 1422 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1430 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1431 }
1432}
1433
08c71e5e
VS		 1434static void assert_vblank_disabled(struct drm_crtc *crtc)
1435{
e2c719b7 1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1437 drm_crtc_vblank_put(crtc);
1438}
1439
89eff4be 1440static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1441{
1442 u32 val;
1443 bool enabled;
1444
e2c719b7 1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1446
92f2584a
JB		 1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1451}
1452
ab9412ba
DV		 1453static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
92f2584a
JB		 1455{
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
ab9412ba 1460 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1463 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
92f2584a
JB		 1466}
1467
4e634389
KP		 1468static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1470{
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
44f37d1f
CML		 1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
f0575e92
KP		 1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487}
1488
1519b995
KP		 1489static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
dc0fa718 1492 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1497 return false;
44f37d1f
CML		 1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1519b995 1501 } else {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1503 return false;
1504 }
1505 return true;
1506}
1507
1508static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510{
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
1524static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537}
1538
291906f1 1539static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1540 enum pipe pipe, int reg, u32 port_sel)
291906f1 1541{
47a05eca 1542 u32 val = I915_READ(reg);
e2c719b7 1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1545 reg, pipe_name(pipe));
de9a35ab 1546
e2c719b7 1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1548 && (val & DP_PIPEB_SELECT),
de9a35ab 1549 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1550}
1551
1552static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554{
47a05eca 1555 u32 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 reg, pipe_name(pipe));
de9a35ab 1559
e2c719b7 1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1561 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1562 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1563}
1564
1565static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567{
1568 int reg;
1569 u32 val;
291906f1 1570
f0575e92
KP		 1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
e2c719b7 1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1579 pipe_name(pipe));
291906f1
JB		 1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
e2debe91
PZ		 1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1590}
1591
40e9cf64
JB		 1592static void intel_init_dpio(struct drm_device *dev)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
a09caddd
CML		 1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
5382f5f3
JB		 1610}
1611
d288f65f 1612static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
87442f73 1614{
426115cf
DV		 1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
d288f65f 1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1619
426115cf 1620 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1626 if (IS_MOBILE(dev_priv->dev))
426115cf 1627 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1628
426115cf
DV		 1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
d288f65f 1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1637 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1638
1639 /* We do this three times for luck */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
DV		 1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
DV		 1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649}
1650
d288f65f 1651static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1652 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1653{
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
a580516d 1664 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
54433e91
VS		 1671 mutex_unlock(&dev_priv->sb_lock);
1672
9d556c99
CML		 1673 /*
1674 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1675 */
1676 udelay(1);
1677
1678 /* Enable PLL */
d288f65f 1679 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1680
1681 /* Check PLL is locked */
a11b0703 1682 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1683 DRM_ERROR("PLL %d failed to lock\n", pipe);
1684
a11b0703 1685 /* not sure when this should be written */
d288f65f 1686 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1687 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1688}
1689
1c4e0274
VS		 1690static int intel_num_dvo_pipes(struct drm_device *dev)
1691{
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
409ee761 1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1698
1699 return count;
1700}
1701
66e3d5c0 1702static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1703{
66e3d5c0
DV		 1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
6e3c9717 1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1708
66e3d5c0 1709 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1710
63d7bbe9 1711 /* No really, not for ILK+ */
3d13ef2e 1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1713
1714 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1717
1c4e0274
VS		 1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
66e3d5c0
DV		 1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1737 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
63d7bbe9
JB		 1746
1747 /* We do this three times for luck */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757}
1758
1759/**
50b44a44 1760 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1c4e0274 1768static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1769{
1c4e0274
VS		 1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
409ee761 1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
b6b5d049
VS		 1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
50b44a44
DV		 1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1794}
1795
f6071166
JB		 1796static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797{
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
e5cbfbfb
ID		 1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
f6071166 1807 if (pipe == PIPE_B)
e5cbfbfb 1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1811
1812}
1813
1814static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815{
d752048d 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1817 u32 val;
1818
a11b0703
VS		 1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1821
a11b0703 1822 /* Set PLL en = 0 */
d17ec4ce 1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
d752048d 1828
a580516d 1829 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
61407f6d
VS		 1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
a580516d 1847 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1848}
1849
e4607fcf 1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
89b667f8
JB		 1853{
1854 u32 port_mask;
00fc31b7 1855 int dpll_reg;
89b667f8 1856
e4607fcf
CML		 1857 switch (dport->port) {
1858 case PORT_B:
89b667f8 1859 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
e4607fcf
CML		 1861 break;
1862 case PORT_C:
89b667f8 1863 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1864 dpll_reg = DPLL(0);
9b6de0a1 1865 expected_mask <<= 4;
00fc31b7
CML		 1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1870 break;
1871 default:
1872 BUG();
1873 }
89b667f8 1874
9b6de0a1
VS		 1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1878}
1879
b14b1055
DV		 1880static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881{
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
be19f0ff
CW		 1886 if (WARN_ON(pll == NULL))
1887 return;
1888
3e369b76 1889 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897}
1898
92f2584a 1899/**
85b3894f 1900 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
85b3894f 1907static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1908{
3d13ef2e
DL		 1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1912
87a875bb 1913 if (WARN_ON(pll == NULL))
48da64a8
CW		 1914 return;
1915
3e369b76 1916 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1917 return;
ee7b9f93 1918
74dd6928 1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1920 pll->name, pll->active, pll->on,
e2b78267 1921 crtc->base.base.id);
92f2584a 1922
cdbd2316
DV		 1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
e9d6944e 1925 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1926 return;
1927 }
f4a091c7 1928 WARN_ON(pll->on);
ee7b9f93 1929
bd2bb1b9
PZ		 1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
46edb027 1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1933 pll->enable(dev_priv, pll);
ee7b9f93 1934 pll->on = true;
92f2584a
JB		 1935}
1936
f6daaec2 1937static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1938{
3d13ef2e
DL		 1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1942
92f2584a 1943 /* PCH only available on ILK+ */
3d13ef2e 1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1945 if (WARN_ON(pll == NULL))
ee7b9f93 1946 return;
92f2584a 1947
3e369b76 1948 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1949 return;
7a419866 1950
46edb027
DV		 1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
e2b78267 1953 crtc->base.base.id);
7a419866 1954
48da64a8 1955 if (WARN_ON(pll->active == 0)) {
e9d6944e 1956 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1957 return;
1958 }
1959
e9d6944e 1960 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1961 WARN_ON(!pll->on);
cdbd2316 1962 if (--pll->active)
7a419866 1963 return;
ee7b9f93 1964
46edb027 1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1966 pll->disable(dev_priv, pll);
ee7b9f93 1967 pll->on = false;
bd2bb1b9
PZ		 1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1970}
1971
b8a4f404
PZ		 1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
040484af 1974{
23670b32 1975 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1978 uint32_t reg, val, pipeconf_val;
040484af
JB		 1979
1980 /* PCH only available on ILK+ */
55522f37 1981 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1982
1983 /* Make sure PCH DPLL is enabled */
e72f9fbf 1984 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1985 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
23670b32
DV		 1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
59c859d6 1998 }
23670b32 1999
ab9412ba 2000 reg = PCH_TRANSCONF(pipe);
040484af 2001 val = I915_READ(reg);
5f7f726d 2002 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
dfd07d72
DV		 2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2011 }
5f7f726d
PZ		 2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2015 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
040484af
JB		 2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2026}
2027
8fb033d7 2028static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2029 enum transcoder cpu_transcoder)
040484af 2030{
8fb033d7 2031 u32 val, pipeconf_val;
8fb033d7
PZ		 2032
2033 /* PCH only available on ILK+ */
55522f37 2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2035
8fb033d7 2036 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2039
223a6fdf
PZ		 2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
25f3ef11 2045 val = TRANS_ENABLE;
937bb610 2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2047
9a76b1c6
PZ		 2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
a35f2679 2050 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
ab9412ba
DV		 2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2056 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2057}
2058
b8a4f404
PZ		 2059static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
040484af 2061{
23670b32
DV		 2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
040484af
JB		 2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
291906f1
JB		 2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
ab9412ba 2072 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
040484af
JB		 2087}
2088
ab4d966c 2089static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2090{
8fb033d7
PZ		 2091 u32 val;
2092
ab9412ba 2093 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2094 val &= ~TRANS_ENABLE;
ab9412ba 2095 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2096 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2098 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2103 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2104}
2105
b24e7179 2106/**
309cfea8 2107 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2108 * @crtc: crtc responsible for the pipe
b24e7179 2109 *
0372264a 2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2112 */
e1fdc473 2113static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2114{
0372264a
PZ		 2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
1a240d4d 2120 enum pipe pch_transcoder;
b24e7179
JB		 2121 int reg;
2122 u32 val;
2123
58c6eaa2 2124 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2125 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2126 assert_sprites_disabled(dev_priv, pipe);
2127
681e5811 2128 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
b24e7179
JB		 2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
50360403 2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
040484af 2143 else {
6e3c9717 2144 if (crtc->config->has_pch_encoder) {
040484af 2145 /* if driving the PCH, we need FDI enabled */
cc391bbb 2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
040484af
JB		 2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
b24e7179 2152
702e7a56 2153 reg = PIPECONF(cpu_transcoder);
b24e7179 2154 val = I915_READ(reg);
7ad25d48 2155 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2158 return;
7ad25d48 2159 }
00d70b15
CW		 2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2162 POSTING_READ(reg);
b24e7179
JB		 2163}
2164
2165/**
309cfea8 2166 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2167 * @crtc: crtc whose pipes is to be disabled
b24e7179 2168 *
575f7ab7
VS		 2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
b24e7179
JB		 2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
575f7ab7 2175static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2176{
575f7ab7 2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2179 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2188 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2189 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2190
702e7a56 2191 reg = PIPECONF(cpu_transcoder);
b24e7179 2192 val = I915_READ(reg);
00d70b15
CW		 2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
67adc644
VS		 2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
6e3c9717 2200 if (crtc->config->double_wide)
67adc644
VS		 2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2211}
2212
2213/**
262ca2b0 2214 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2215 * @plane: plane to be enabled
2216 * @crtc: crtc for the plane
b24e7179 2217 *
fdd508a6 2218 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2219 */
fdd508a6
VS		 2220static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2221 struct drm_crtc *crtc)
b24e7179 2222{
fdd508a6
VS		 2223 struct drm_device *dev = plane->dev;
2224 struct drm_i915_private *dev_priv = dev->dev_private;
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2226
2227 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2228 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2229 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2230
fdd508a6
VS		 2231 dev_priv->display.update_primary_plane(crtc, plane->fb,
2232 crtc->x, crtc->y);
b24e7179
JB		 2233}
2234
693db184
CW		 2235static bool need_vtd_wa(struct drm_device *dev)
2236{
2237#ifdef CONFIG_INTEL_IOMMU
2238 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2239 return true;
2240#endif
2241 return false;
2242}
2243
50470bb0 2244unsigned int
6761dd31
TU		 2245intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2246 uint64_t fb_format_modifier)
a57ce0b2 2247{
6761dd31
TU		 2248 unsigned int tile_height;
2249 uint32_t pixel_bytes;
a57ce0b2 2250
b5d0e9bf
DL		 2251 switch (fb_format_modifier) {
2252 case DRM_FORMAT_MOD_NONE:
2253 tile_height = 1;
2254 break;
2255 case I915_FORMAT_MOD_X_TILED:
2256 tile_height = IS_GEN2(dev) ? 16 : 8;
2257 break;
2258 case I915_FORMAT_MOD_Y_TILED:
2259 tile_height = 32;
2260 break;
2261 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2262 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2263 switch (pixel_bytes) {
b5d0e9bf 2264 default:
6761dd31 2265 case 1:
b5d0e9bf
DL		 2266 tile_height = 64;
2267 break;
6761dd31
TU		 2268 case 2:
2269 case 4:
b5d0e9bf
DL		 2270 tile_height = 32;
2271 break;
6761dd31 2272 case 8:
b5d0e9bf
DL		 2273 tile_height = 16;
2274 break;
6761dd31 2275 case 16:
b5d0e9bf
DL		 2276 WARN_ONCE(1,
2277 "128-bit pixels are not supported for display!");
2278 tile_height = 16;
2279 break;
2280 }
2281 break;
2282 default:
2283 MISSING_CASE(fb_format_modifier);
2284 tile_height = 1;
2285 break;
2286 }
091df6cb 2287
6761dd31
TU		 2288 return tile_height;
2289}
2290
2291unsigned int
2292intel_fb_align_height(struct drm_device *dev, unsigned int height,
2293 uint32_t pixel_format, uint64_t fb_format_modifier)
2294{
2295 return ALIGN(height, intel_tile_height(dev, pixel_format,
2296 fb_format_modifier));
a57ce0b2
JB		 2297}
2298
f64b98cd
TU		 2299static int
2300intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2301 const struct drm_plane_state *plane_state)
2302{
50470bb0 2303 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2304
f64b98cd
TU		 2305 *view = i915_ggtt_view_normal;
2306
50470bb0
TU		 2307 if (!plane_state)
2308 return 0;
2309
121920fa 2310 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2311 return 0;
2312
9abc4648 2313 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2314
2315 info->height = fb->height;
2316 info->pixel_format = fb->pixel_format;
2317 info->pitch = fb->pitches[0];
2318 info->fb_modifier = fb->modifier[0];
2319
f64b98cd
TU		 2320 return 0;
2321}
2322
127bd2ac 2323int
850c4cdc
TU		 2324intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2325 struct drm_framebuffer *fb,
82bc3b2d 2326 const struct drm_plane_state *plane_state,
a4872ba6 2327 struct intel_engine_cs *pipelined)
6b95a207 2328{
850c4cdc 2329 struct drm_device *dev = fb->dev;
ce453d81 2330 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2331 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2332 struct i915_ggtt_view view;
6b95a207
KH		 2333 u32 alignment;
2334 int ret;
2335
ebcdd39e
MR		 2336 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2337
7b911adc
TU		 2338 switch (fb->modifier[0]) {
2339 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2340 if (INTEL_INFO(dev)->gen >= 9)
2341 alignment = 256 * 1024;
2342 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2343 alignment = 128 * 1024;
a6c45cf0 2344 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2345 alignment = 4 * 1024;
2346 else
2347 alignment = 64 * 1024;
6b95a207 2348 break;
7b911adc 2349 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else {
2353 /* pin() will align the object as required by fence */
2354 alignment = 0;
2355 }
6b95a207 2356 break;
7b911adc 2357 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2358 case I915_FORMAT_MOD_Yf_TILED:
2359 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2361 return -EINVAL;
2362 alignment = 1 * 1024 * 1024;
2363 break;
6b95a207 2364 default:
7b911adc
TU		 2365 MISSING_CASE(fb->modifier[0]);
2366 return -EINVAL;
6b95a207
KH		 2367 }
2368
f64b98cd
TU		 2369 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2370 if (ret)
2371 return ret;
2372
693db184
CW		 2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2376 * the VT-d warning.
2377 */
2378 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2379 alignment = 256 * 1024;
2380
d6dd6843
PZ		 2381 /*
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2387 */
2388 intel_runtime_pm_get(dev_priv);
2389
ce453d81 2390 dev_priv->mm.interruptible = false;
e6617330 2391 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2392 &view);
48b956c5 2393 if (ret)
ce453d81 2394 goto err_interruptible;
6b95a207
KH		 2395
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2400 */
06d98131 2401 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2402 if (ret)
2403 goto err_unpin;
1690e1eb 2404
9a5a53b3 2405 i915_gem_object_pin_fence(obj);
6b95a207 2406
ce453d81 2407 dev_priv->mm.interruptible = true;
d6dd6843 2408 intel_runtime_pm_put(dev_priv);
6b95a207 2409 return 0;
48b956c5
CW		 2410
2411err_unpin:
f64b98cd 2412 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2413err_interruptible:
2414 dev_priv->mm.interruptible = true;
d6dd6843 2415 intel_runtime_pm_put(dev_priv);
48b956c5 2416 return ret;
6b95a207
KH		 2417}
2418
82bc3b2d
TU		 2419static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2420 const struct drm_plane_state *plane_state)
1690e1eb 2421{
82bc3b2d 2422 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2423 struct i915_ggtt_view view;
2424 int ret;
82bc3b2d 2425
ebcdd39e
MR		 2426 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2427
f64b98cd
TU		 2428 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2429 WARN_ONCE(ret, "Couldn't get view from plane state!");
2430
1690e1eb 2431 i915_gem_object_unpin_fence(obj);
f64b98cd 2432 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2433}
2434
c2c75131
DV		 2435/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2436 * is assumed to be a power-of-two. */
bc752862
CW		 2437unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2438 unsigned int tiling_mode,
2439 unsigned int cpp,
2440 unsigned int pitch)
c2c75131 2441{
bc752862
CW		 2442 if (tiling_mode != I915_TILING_NONE) {
2443 unsigned int tile_rows, tiles;
c2c75131 2444
bc752862
CW		 2445 tile_rows = *y / 8;
2446 *y %= 8;
c2c75131 2447
bc752862
CW		 2448 tiles = *x / (512/cpp);
2449 *x %= 512/cpp;
2450
2451 return tile_rows * pitch * 8 + tiles * 4096;
2452 } else {
2453 unsigned int offset;
2454
2455 offset = *y * pitch + *x * cpp;
2456 *y = 0;
2457 *x = (offset & 4095) / cpp;
2458 return offset & -4096;
2459 }
c2c75131
DV		 2460}
2461
b35d63fa 2462static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2463{
2464 switch (format) {
2465 case DISPPLANE_8BPP:
2466 return DRM_FORMAT_C8;
2467 case DISPPLANE_BGRX555:
2468 return DRM_FORMAT_XRGB1555;
2469 case DISPPLANE_BGRX565:
2470 return DRM_FORMAT_RGB565;
2471 default:
2472 case DISPPLANE_BGRX888:
2473 return DRM_FORMAT_XRGB8888;
2474 case DISPPLANE_RGBX888:
2475 return DRM_FORMAT_XBGR8888;
2476 case DISPPLANE_BGRX101010:
2477 return DRM_FORMAT_XRGB2101010;
2478 case DISPPLANE_RGBX101010:
2479 return DRM_FORMAT_XBGR2101010;
2480 }
2481}
2482
bc8d7dff
DL		 2483static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2484{
2485 switch (format) {
2486 case PLANE_CTL_FORMAT_RGB_565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case PLANE_CTL_FORMAT_XRGB_8888:
2490 if (rgb_order) {
2491 if (alpha)
2492 return DRM_FORMAT_ABGR8888;
2493 else
2494 return DRM_FORMAT_XBGR8888;
2495 } else {
2496 if (alpha)
2497 return DRM_FORMAT_ARGB8888;
2498 else
2499 return DRM_FORMAT_XRGB8888;
2500 }
2501 case PLANE_CTL_FORMAT_XRGB_2101010:
2502 if (rgb_order)
2503 return DRM_FORMAT_XBGR2101010;
2504 else
2505 return DRM_FORMAT_XRGB2101010;
2506 }
2507}
2508
5724dbd1 2509static bool
f6936e29
DV		 2510intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2511 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2512{
2513 struct drm_device *dev = crtc->base.dev;
2514 struct drm_i915_gem_object *obj = NULL;
2515 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2516 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2517 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2518 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2519 PAGE_SIZE);
2520
2521 size_aligned -= base_aligned;
46f297fb 2522
ff2652ea
CW		 2523 if (plane_config->size == 0)
2524 return false;
2525
f37b5c2b
DV		 2526 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2527 base_aligned,
2528 base_aligned,
2529 size_aligned);
46f297fb 2530 if (!obj)
484b41dd 2531 return false;
46f297fb 2532
49af449b
DL		 2533 obj->tiling_mode = plane_config->tiling;
2534 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2535 obj->stride = fb->pitches[0];
46f297fb 2536
6bf129df
DL		 2537 mode_cmd.pixel_format = fb->pixel_format;
2538 mode_cmd.width = fb->width;
2539 mode_cmd.height = fb->height;
2540 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2541 mode_cmd.modifier[0] = fb->modifier[0];
2542 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2543
2544 mutex_lock(&dev->struct_mutex);
6bf129df 2545 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2546 &mode_cmd, obj)) {
46f297fb
JB		 2547 DRM_DEBUG_KMS("intel fb init failed\n");
2548 goto out_unref_obj;
2549 }
46f297fb 2550 mutex_unlock(&dev->struct_mutex);
484b41dd 2551
f6936e29 2552 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2553 return true;
46f297fb
JB		 2554
2555out_unref_obj:
2556 drm_gem_object_unreference(&obj->base);
2557 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2558 return false;
2559}
2560
afd65eb4
MR		 2561/* Update plane->state->fb to match plane->fb after driver-internal updates */
2562static void
2563update_state_fb(struct drm_plane *plane)
2564{
2565 if (plane->fb == plane->state->fb)
2566 return;
2567
2568 if (plane->state->fb)
2569 drm_framebuffer_unreference(plane->state->fb);
2570 plane->state->fb = plane->fb;
2571 if (plane->state->fb)
2572 drm_framebuffer_reference(plane->state->fb);
2573}
2574
5724dbd1 2575static void
f6936e29
DV		 2576intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2577 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2578{
2579 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2580 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2581 struct drm_crtc *c;
2582 struct intel_crtc *i;
2ff8fde1 2583 struct drm_i915_gem_object *obj;
88595ac9
DV		 2584 struct drm_plane *primary = intel_crtc->base.primary;
2585 struct drm_framebuffer *fb;
484b41dd 2586
2d14030b 2587 if (!plane_config->fb)
484b41dd
JB		 2588 return;
2589
f6936e29 2590 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2591 fb = &plane_config->fb->base;
2592 goto valid_fb;
f55548b5 2593 }
484b41dd 2594
2d14030b 2595 kfree(plane_config->fb);
484b41dd
JB		 2596
2597 /*
2598 * Failed to alloc the obj, check to see if we should share
2599 * an fb with another CRTC instead
2600 */
70e1e0ec 2601 for_each_crtc(dev, c) {
484b41dd
JB		 2602 i = to_intel_crtc(c);
2603
2604 if (c == &intel_crtc->base)
2605 continue;
2606
2ff8fde1
MR		 2607 if (!i->active)
2608 continue;
2609
88595ac9
DV		 2610 fb = c->primary->fb;
2611 if (!fb)
484b41dd
JB		 2612 continue;
2613
88595ac9 2614 obj = intel_fb_obj(fb);
2ff8fde1 2615 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2616 drm_framebuffer_reference(fb);
2617 goto valid_fb;
484b41dd
JB		 2618 }
2619 }
88595ac9
DV		 2620
2621 return;
2622
2623valid_fb:
2624 obj = intel_fb_obj(fb);
2625 if (obj->tiling_mode != I915_TILING_NONE)
2626 dev_priv->preserve_bios_swizzle = true;
2627
2628 primary->fb = fb;
2629 primary->state->crtc = &intel_crtc->base;
2630 primary->crtc = &intel_crtc->base;
2631 update_state_fb(primary);
2632 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2633}
2634
29b9bde6
DV		 2635static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2636 struct drm_framebuffer *fb,
2637 int x, int y)
81255565
JB		 2638{
2639 struct drm_device *dev = crtc->dev;
2640 struct drm_i915_private *dev_priv = dev->dev_private;
2641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2642 struct drm_plane *primary = crtc->primary;
2643 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2644 struct drm_i915_gem_object *obj;
81255565 2645 int plane = intel_crtc->plane;
e506a0c6 2646 unsigned long linear_offset;
81255565 2647 u32 dspcntr;
f45651ba 2648 u32 reg = DSPCNTR(plane);
48404c1e 2649 int pixel_size;
f45651ba 2650
b70709a6 2651 if (!visible || !fb) {
fdd508a6
VS		 2652 I915_WRITE(reg, 0);
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2655 else
2656 I915_WRITE(DSPADDR(plane), 0);
2657 POSTING_READ(reg);
2658 return;
2659 }
2660
c9ba6fad
VS		 2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2663 return;
2664
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
f45651ba
VS		 2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
fdd508a6 2669 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2670
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2677 */
2678 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2681 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2688 }
81255565 2689
57779d06
VS		 2690 switch (fb->pixel_format) {
2691 case DRM_FORMAT_C8:
81255565
JB		 2692 dspcntr |= DISPPLANE_8BPP;
2693 break;
57779d06 2694 case DRM_FORMAT_XRGB1555:
57779d06 2695 dspcntr |= DISPPLANE_BGRX555;
81255565 2696 break;
57779d06
VS		 2697 case DRM_FORMAT_RGB565:
2698 dspcntr |= DISPPLANE_BGRX565;
2699 break;
2700 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2701 dspcntr |= DISPPLANE_BGRX888;
2702 break;
2703 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2704 dspcntr |= DISPPLANE_RGBX888;
2705 break;
2706 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2707 dspcntr |= DISPPLANE_BGRX101010;
2708 break;
2709 case DRM_FORMAT_XBGR2101010:
57779d06 2710 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2711 break;
2712 default:
baba133a 2713 BUG();
81255565 2714 }
57779d06 2715
f45651ba
VS		 2716 if (INTEL_INFO(dev)->gen >= 4 &&
2717 obj->tiling_mode != I915_TILING_NONE)
2718 dspcntr |= DISPPLANE_TILED;
81255565 2719
de1aa629
VS		 2720 if (IS_G4X(dev))
2721 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2722
b9897127 2723 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2724
c2c75131
DV		 2725 if (INTEL_INFO(dev)->gen >= 4) {
2726 intel_crtc->dspaddr_offset =
bc752862 2727 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2728 pixel_size,
bc752862 2729 fb->pitches[0]);
c2c75131
DV		 2730 linear_offset -= intel_crtc->dspaddr_offset;
2731 } else {
e506a0c6 2732 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2733 }
e506a0c6 2734
8e7d688b 2735 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2736 dspcntr |= DISPPLANE_ROTATE_180;
2737
6e3c9717
ACO		 2738 x += (intel_crtc->config->pipe_src_w - 1);
2739 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2740
2741 /* Finding the last pixel of the last line of the display
2742 data and adding to linear_offset*/
2743 linear_offset +=
6e3c9717
ACO		 2744 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2745 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2746 }
2747
2748 I915_WRITE(reg, dspcntr);
2749
01f2c773 2750 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2751 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2752 I915_WRITE(DSPSURF(plane),
2753 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2754 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2755 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2756 } else
f343c5f6 2757 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2758 POSTING_READ(reg);
17638cd6
JB		 2759}
2760
29b9bde6
DV		 2761static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2762 struct drm_framebuffer *fb,
2763 int x, int y)
17638cd6
JB		 2764{
2765 struct drm_device *dev = crtc->dev;
2766 struct drm_i915_private *dev_priv = dev->dev_private;
2767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2768 struct drm_plane *primary = crtc->primary;
2769 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2770 struct drm_i915_gem_object *obj;
17638cd6 2771 int plane = intel_crtc->plane;
e506a0c6 2772 unsigned long linear_offset;
17638cd6 2773 u32 dspcntr;
f45651ba 2774 u32 reg = DSPCNTR(plane);
48404c1e 2775 int pixel_size;
f45651ba 2776
b70709a6 2777 if (!visible || !fb) {
fdd508a6
VS		 2778 I915_WRITE(reg, 0);
2779 I915_WRITE(DSPSURF(plane), 0);
2780 POSTING_READ(reg);
2781 return;
2782 }
2783
c9ba6fad
VS		 2784 obj = intel_fb_obj(fb);
2785 if (WARN_ON(obj == NULL))
2786 return;
2787
2788 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2789
f45651ba
VS		 2790 dspcntr = DISPPLANE_GAMMA_ENABLE;
2791
fdd508a6 2792 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2793
2794 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2795 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2796
57779d06
VS		 2797 switch (fb->pixel_format) {
2798 case DRM_FORMAT_C8:
17638cd6
JB		 2799 dspcntr |= DISPPLANE_8BPP;
2800 break;
57779d06
VS		 2801 case DRM_FORMAT_RGB565:
2802 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2803 break;
57779d06 2804 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2805 dspcntr |= DISPPLANE_BGRX888;
2806 break;
2807 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2808 dspcntr |= DISPPLANE_RGBX888;
2809 break;
2810 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2811 dspcntr |= DISPPLANE_BGRX101010;
2812 break;
2813 case DRM_FORMAT_XBGR2101010:
57779d06 2814 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2815 break;
2816 default:
baba133a 2817 BUG();
17638cd6
JB		 2818 }
2819
2820 if (obj->tiling_mode != I915_TILING_NONE)
2821 dspcntr |= DISPPLANE_TILED;
17638cd6 2822
f45651ba 2823 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2824 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2825
b9897127 2826 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2827 intel_crtc->dspaddr_offset =
bc752862 2828 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2829 pixel_size,
bc752862 2830 fb->pitches[0]);
c2c75131 2831 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2832 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2833 dspcntr |= DISPPLANE_ROTATE_180;
2834
2835 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2836 x += (intel_crtc->config->pipe_src_w - 1);
2837 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2838
2839 /* Finding the last pixel of the last line of the display
2840 data and adding to linear_offset*/
2841 linear_offset +=
6e3c9717
ACO		 2842 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2843 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2844 }
2845 }
2846
2847 I915_WRITE(reg, dspcntr);
17638cd6 2848
01f2c773 2849 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2850 I915_WRITE(DSPSURF(plane),
2851 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2852 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2853 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2854 } else {
2855 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2856 I915_WRITE(DSPLINOFF(plane), linear_offset);
2857 }
17638cd6 2858 POSTING_READ(reg);
17638cd6
JB		 2859}
2860
b321803d
DL		 2861u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2862 uint32_t pixel_format)
2863{
2864 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2865
2866 /*
2867 * The stride is either expressed as a multiple of 64 bytes
2868 * chunks for linear buffers or in number of tiles for tiled
2869 * buffers.
2870 */
2871 switch (fb_modifier) {
2872 case DRM_FORMAT_MOD_NONE:
2873 return 64;
2874 case I915_FORMAT_MOD_X_TILED:
2875 if (INTEL_INFO(dev)->gen == 2)
2876 return 128;
2877 return 512;
2878 case I915_FORMAT_MOD_Y_TILED:
2879 /* No need to check for old gens and Y tiling since this is
2880 * about the display engine and those will be blocked before
2881 * we get here.
2882 */
2883 return 128;
2884 case I915_FORMAT_MOD_Yf_TILED:
2885 if (bits_per_pixel == 8)
2886 return 64;
2887 else
2888 return 128;
2889 default:
2890 MISSING_CASE(fb_modifier);
2891 return 64;
2892 }
2893}
2894
121920fa
TU		 2895unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2896 struct drm_i915_gem_object *obj)
2897{
9abc4648 2898 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2899
2900 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2901 view = &i915_ggtt_view_rotated;
121920fa
TU		 2902
2903 return i915_gem_obj_ggtt_offset_view(obj, view);
2904}
2905
a1b2278e
CK		 2906/*
2907 * This function detaches (aka. unbinds) unused scalers in hardware
2908 */
2909void skl_detach_scalers(struct intel_crtc *intel_crtc)
2910{
2911 struct drm_device *dev;
2912 struct drm_i915_private *dev_priv;
2913 struct intel_crtc_scaler_state *scaler_state;
2914 int i;
2915
2916 if (!intel_crtc || !intel_crtc->config)
2917 return;
2918
2919 dev = intel_crtc->base.dev;
2920 dev_priv = dev->dev_private;
2921 scaler_state = &intel_crtc->config->scaler_state;
2922
2923 /* loop through and disable scalers that aren't in use */
2924 for (i = 0; i < intel_crtc->num_scalers; i++) {
2925 if (!scaler_state->scalers[i].in_use) {
2926 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2927 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2928 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2929 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2930 intel_crtc->base.base.id, intel_crtc->pipe, i);
2931 }
2932 }
2933}
2934
6156a456 2935u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2936{
6156a456 2937 switch (pixel_format) {
d161cf7a 2938 case DRM_FORMAT_C8:
c34ce3d1 2939 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2940 case DRM_FORMAT_RGB565:
c34ce3d1 2941 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2942 case DRM_FORMAT_XBGR8888:
c34ce3d1 2943 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2944 case DRM_FORMAT_XRGB8888:
c34ce3d1 2945 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2946 /*
2947 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2948 * to be already pre-multiplied. We need to add a knob (or a different
2949 * DRM_FORMAT) for user-space to configure that.
2950 */
f75fb42a 2951 case DRM_FORMAT_ABGR8888:
c34ce3d1 2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2953 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2954 case DRM_FORMAT_ARGB8888:
c34ce3d1 2955 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2956 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2957 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2958 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2959 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2960 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2961 case DRM_FORMAT_YUYV:
c34ce3d1 2962 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2963 case DRM_FORMAT_YVYU:
c34ce3d1 2964 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2965 case DRM_FORMAT_UYVY:
c34ce3d1 2966 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2967 case DRM_FORMAT_VYUY:
c34ce3d1 2968 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2969 default:
4249eeef 2970 MISSING_CASE(pixel_format);
70d21f0e 2971 }
8cfcba41 2972
c34ce3d1 2973 return 0;
6156a456 2974}
70d21f0e 2975
6156a456
CK		 2976u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2977{
6156a456 2978 switch (fb_modifier) {
30af77c4 2979 case DRM_FORMAT_MOD_NONE:
70d21f0e 2980 break;
30af77c4 2981 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2982 return PLANE_CTL_TILED_X;
b321803d 2983 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2984 return PLANE_CTL_TILED_Y;
b321803d 2985 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2986 return PLANE_CTL_TILED_YF;
70d21f0e 2987 default:
6156a456 2988 MISSING_CASE(fb_modifier);
70d21f0e 2989 }
8cfcba41 2990
c34ce3d1 2991 return 0;
6156a456 2992}
70d21f0e 2993
6156a456
CK		 2994u32 skl_plane_ctl_rotation(unsigned int rotation)
2995{
3b7a5119 2996 switch (rotation) {
6156a456
CK		 2997 case BIT(DRM_ROTATE_0):
2998 break;
1e8df167
SJ		 2999 /*
3000 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3001 * while i915 HW rotation is clockwise, thats why this swapping.
3002 */
3b7a5119 3003 case BIT(DRM_ROTATE_90):
1e8df167 3004 return PLANE_CTL_ROTATE_270;
3b7a5119 3005 case BIT(DRM_ROTATE_180):
c34ce3d1 3006 return PLANE_CTL_ROTATE_180;
3b7a5119 3007 case BIT(DRM_ROTATE_270):
1e8df167 3008 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3009 default:
3010 MISSING_CASE(rotation);
3011 }
3012
c34ce3d1 3013 return 0;
6156a456
CK		 3014}
3015
3016static void skylake_update_primary_plane(struct drm_crtc *crtc,
3017 struct drm_framebuffer *fb,
3018 int x, int y)
3019{
3020 struct drm_device *dev = crtc->dev;
3021 struct drm_i915_private *dev_priv = dev->dev_private;
3022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3023 struct drm_plane *plane = crtc->primary;
3024 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3025 struct drm_i915_gem_object *obj;
3026 int pipe = intel_crtc->pipe;
3027 u32 plane_ctl, stride_div, stride;
3028 u32 tile_height, plane_offset, plane_size;
3029 unsigned int rotation;
3030 int x_offset, y_offset;
3031 unsigned long surf_addr;
6156a456
CK		 3032 struct intel_crtc_state *crtc_state = intel_crtc->config;
3033 struct intel_plane_state *plane_state;
3034 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3035 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3036 int scaler_id = -1;
3037
6156a456
CK		 3038 plane_state = to_intel_plane_state(plane->state);
3039
b70709a6 3040 if (!visible || !fb) {
6156a456
CK		 3041 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3042 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3043 POSTING_READ(PLANE_CTL(pipe, 0));
3044 return;
3b7a5119 3045 }
70d21f0e 3046
6156a456
CK		 3047 plane_ctl = PLANE_CTL_ENABLE |
3048 PLANE_CTL_PIPE_GAMMA_ENABLE |
3049 PLANE_CTL_PIPE_CSC_ENABLE;
3050
3051 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3052 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3053 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3054
3055 rotation = plane->state->rotation;
3056 plane_ctl |= skl_plane_ctl_rotation(rotation);
3057
b321803d
DL		 3058 obj = intel_fb_obj(fb);
3059 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3060 fb->pixel_format);
3b7a5119
SJ		 3061 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3062
6156a456
CK		 3063 /*
3064 * FIXME: intel_plane_state->src, dst aren't set when transitional
3065 * update_plane helpers are called from legacy paths.
3066 * Once full atomic crtc is available, below check can be avoided.
3067 */
3068 if (drm_rect_width(&plane_state->src)) {
3069 scaler_id = plane_state->scaler_id;
3070 src_x = plane_state->src.x1 >> 16;
3071 src_y = plane_state->src.y1 >> 16;
3072 src_w = drm_rect_width(&plane_state->src) >> 16;
3073 src_h = drm_rect_height(&plane_state->src) >> 16;
3074 dst_x = plane_state->dst.x1;
3075 dst_y = plane_state->dst.y1;
3076 dst_w = drm_rect_width(&plane_state->dst);
3077 dst_h = drm_rect_height(&plane_state->dst);
3078
3079 WARN_ON(x != src_x || y != src_y);
3080 } else {
3081 src_w = intel_crtc->config->pipe_src_w;
3082 src_h = intel_crtc->config->pipe_src_h;
3083 }
3084
3b7a5119
SJ		 3085 if (intel_rotation_90_or_270(rotation)) {
3086 /* stride = Surface height in tiles */
2614f17d 3087 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3088 fb->modifier[0]);
3089 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3090 x_offset = stride * tile_height - y - src_h;
3b7a5119 3091 y_offset = x;
6156a456 3092 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3093 } else {
3094 stride = fb->pitches[0] / stride_div;
3095 x_offset = x;
3096 y_offset = y;
6156a456 3097 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3098 }
3099 plane_offset = y_offset << 16 | x_offset;
b321803d 3100
70d21f0e 3101 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3102 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3103 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3104 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3105
3106 if (scaler_id >= 0) {
3107 uint32_t ps_ctrl = 0;
3108
3109 WARN_ON(!dst_w || !dst_h);
3110 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3111 crtc_state->scaler_state.scalers[scaler_id].mode;
3112 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3113 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3114 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3115 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3116 I915_WRITE(PLANE_POS(pipe, 0), 0);
3117 } else {
3118 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3119 }
3120
121920fa 3121 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3122
3123 POSTING_READ(PLANE_SURF(pipe, 0));
3124}
3125
17638cd6
JB		 3126/* Assume fb object is pinned & idle & fenced and just update base pointers */
3127static int
3128intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3129 int x, int y, enum mode_set_atomic state)
3130{
3131 struct drm_device *dev = crtc->dev;
3132 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3133
6b8e6ed0
CW		 3134 if (dev_priv->display.disable_fbc)
3135 dev_priv->display.disable_fbc(dev);
81255565 3136
29b9bde6
DV		 3137 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3138
3139 return 0;
81255565
JB		 3140}
3141
7514747d 3142static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3143{
96a02917
VS		 3144 struct drm_crtc *crtc;
3145
70e1e0ec 3146 for_each_crtc(dev, crtc) {
96a02917
VS		 3147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3148 enum plane plane = intel_crtc->plane;
3149
3150 intel_prepare_page_flip(dev, plane);
3151 intel_finish_page_flip_plane(dev, plane);
3152 }
7514747d
VS		 3153}
3154
3155static void intel_update_primary_planes(struct drm_device *dev)
3156{
3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 struct drm_crtc *crtc;
96a02917 3159
70e1e0ec 3160 for_each_crtc(dev, crtc) {
96a02917
VS		 3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162
51fd371b 3163 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3164 /*
3165 * FIXME: Once we have proper support for primary planes (and
3166 * disabling them without disabling the entire crtc) allow again
66e514c1 3167 * a NULL crtc->primary->fb.
947fdaad 3168 */
f4510a27 3169 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3170 dev_priv->display.update_primary_plane(crtc,
66e514c1 3171 crtc->primary->fb,
262ca2b0
MR		 3172 crtc->x,
3173 crtc->y);
51fd371b 3174 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3175 }
3176}
3177
ce22dba9
ML		 3178void intel_crtc_reset(struct intel_crtc *crtc)
3179{
3180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3181
3182 if (!crtc->active)
3183 return;
3184
3185 intel_crtc_disable_planes(&crtc->base);
3186 dev_priv->display.crtc_disable(&crtc->base);
3187 dev_priv->display.crtc_enable(&crtc->base);
3188 intel_crtc_enable_planes(&crtc->base);
3189}
3190
7514747d
VS		 3191void intel_prepare_reset(struct drm_device *dev)
3192{
f98ce92f
VS		 3193 struct drm_i915_private *dev_priv = to_i915(dev);
3194 struct intel_crtc *crtc;
3195
7514747d
VS		 3196 /* no reset support for gen2 */
3197 if (IS_GEN2(dev))
3198 return;
3199
3200 /* reset doesn't touch the display */
3201 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3202 return;
3203
3204 drm_modeset_lock_all(dev);
f98ce92f
VS		 3205
3206 /*
3207 * Disabling the crtcs gracefully seems nicer. Also the
3208 * g33 docs say we should at least disable all the planes.
3209 */
3210 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3211 if (!crtc->active)
3212 continue;
3213
3214 intel_crtc_disable_planes(&crtc->base);
3215 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3216 }
7514747d
VS		 3217}
3218
3219void intel_finish_reset(struct drm_device *dev)
3220{
3221 struct drm_i915_private *dev_priv = to_i915(dev);
3222
3223 /*
3224 * Flips in the rings will be nuked by the reset,
3225 * so complete all pending flips so that user space
3226 * will get its events and not get stuck.
3227 */
3228 intel_complete_page_flips(dev);
3229
3230 /* no reset support for gen2 */
3231 if (IS_GEN2(dev))
3232 return;
3233
3234 /* reset doesn't touch the display */
3235 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3236 /*
3237 * Flips in the rings have been nuked by the reset,
3238 * so update the base address of all primary
3239 * planes to the the last fb to make sure we're
3240 * showing the correct fb after a reset.
3241 */
3242 intel_update_primary_planes(dev);
3243 return;
3244 }
3245
3246 /*
3247 * The display has been reset as well,
3248 * so need a full re-initialization.
3249 */
3250 intel_runtime_pm_disable_interrupts(dev_priv);
3251 intel_runtime_pm_enable_interrupts(dev_priv);
3252
3253 intel_modeset_init_hw(dev);
3254
3255 spin_lock_irq(&dev_priv->irq_lock);
3256 if (dev_priv->display.hpd_irq_setup)
3257 dev_priv->display.hpd_irq_setup(dev);
3258 spin_unlock_irq(&dev_priv->irq_lock);
3259
3260 intel_modeset_setup_hw_state(dev, true);
3261
3262 intel_hpd_init(dev_priv);
3263
3264 drm_modeset_unlock_all(dev);
3265}
3266
2e2f351d 3267static void
14667a4b
CW		 3268intel_finish_fb(struct drm_framebuffer *old_fb)
3269{
2ff8fde1 3270 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3271 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3272 bool was_interruptible = dev_priv->mm.interruptible;
3273 int ret;
3274
14667a4b
CW		 3275 /* Big Hammer, we also need to ensure that any pending
3276 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3277 * current scanout is retired before unpinning the old
2e2f351d
CW		 3278 * framebuffer. Note that we rely on userspace rendering
3279 * into the buffer attached to the pipe they are waiting
3280 * on. If not, userspace generates a GPU hang with IPEHR
3281 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3282 *
3283 * This should only fail upon a hung GPU, in which case we
3284 * can safely continue.
3285 */
3286 dev_priv->mm.interruptible = false;
2e2f351d 3287 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3288 dev_priv->mm.interruptible = was_interruptible;
3289
2e2f351d 3290 WARN_ON(ret);
14667a4b
CW		 3291}
3292
7d5e3799
CW		 3293static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3294{
3295 struct drm_device *dev = crtc->dev;
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3298 bool pending;
3299
3300 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3301 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3302 return false;
3303
5e2d7afc 3304 spin_lock_irq(&dev->event_lock);
7d5e3799 3305 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3306 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3307
3308 return pending;
3309}
3310
e30e8f75
GP		 3311static void intel_update_pipe_size(struct intel_crtc *crtc)
3312{
3313 struct drm_device *dev = crtc->base.dev;
3314 struct drm_i915_private *dev_priv = dev->dev_private;
3315 const struct drm_display_mode *adjusted_mode;
3316
3317 if (!i915.fastboot)
3318 return;
3319
3320 /*
3321 * Update pipe size and adjust fitter if needed: the reason for this is
3322 * that in compute_mode_changes we check the native mode (not the pfit
3323 * mode) to see if we can flip rather than do a full mode set. In the
3324 * fastboot case, we'll flip, but if we don't update the pipesrc and
3325 * pfit state, we'll end up with a big fb scanned out into the wrong
3326 * sized surface.
3327 *
3328 * To fix this properly, we need to hoist the checks up into
3329 * compute_mode_changes (or above), check the actual pfit state and
3330 * whether the platform allows pfit disable with pipe active, and only
3331 * then update the pipesrc and pfit state, even on the flip path.
3332 */
3333
6e3c9717 3334 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3335
3336 I915_WRITE(PIPESRC(crtc->pipe),
3337 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3338 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3339 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3340 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3341 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3342 I915_WRITE(PF_CTL(crtc->pipe), 0);
3343 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3344 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3345 }
6e3c9717
ACO		 3346 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3347 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3348}
3349
5e84e1a4
ZW		 3350static void intel_fdi_normal_train(struct drm_crtc *crtc)
3351{
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355 int pipe = intel_crtc->pipe;
3356 u32 reg, temp;
3357
3358 /* enable normal train */
3359 reg = FDI_TX_CTL(pipe);
3360 temp = I915_READ(reg);
61e499bf 3361 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3362 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3363 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3364 } else {
3365 temp &= ~FDI_LINK_TRAIN_NONE;
3366 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3367 }
5e84e1a4
ZW		 3368 I915_WRITE(reg, temp);
3369
3370 reg = FDI_RX_CTL(pipe);
3371 temp = I915_READ(reg);
3372 if (HAS_PCH_CPT(dev)) {
3373 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3374 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3375 } else {
3376 temp &= ~FDI_LINK_TRAIN_NONE;
3377 temp |= FDI_LINK_TRAIN_NONE;
3378 }
3379 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3380
3381 /* wait one idle pattern time */
3382 POSTING_READ(reg);
3383 udelay(1000);
357555c0
JB		 3384
3385 /* IVB wants error correction enabled */
3386 if (IS_IVYBRIDGE(dev))
3387 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3388 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3389}
3390
8db9d77b
ZW		 3391/* The FDI link training functions for ILK/Ibexpeak. */
3392static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3393{
3394 struct drm_device *dev = crtc->dev;
3395 struct drm_i915_private *dev_priv = dev->dev_private;
3396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3397 int pipe = intel_crtc->pipe;
5eddb70b 3398 u32 reg, temp, tries;
8db9d77b 3399
1c8562f6 3400 /* FDI needs bits from pipe first */
0fc932b8 3401 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3402
e1a44743
AJ		 3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404 for train result */
5eddb70b
CW		 3405 reg = FDI_RX_IMR(pipe);
3406 temp = I915_READ(reg);
e1a44743
AJ		 3407 temp &= ~FDI_RX_SYMBOL_LOCK;
3408 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3409 I915_WRITE(reg, temp);
3410 I915_READ(reg);
e1a44743
AJ		 3411 udelay(150);
3412
8db9d77b 3413 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3414 reg = FDI_TX_CTL(pipe);
3415 temp = I915_READ(reg);
627eb5a3 3416 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3417 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3420 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3421
5eddb70b
CW		 3422 reg = FDI_RX_CTL(pipe);
3423 temp = I915_READ(reg);
8db9d77b
ZW		 3424 temp &= ~FDI_LINK_TRAIN_NONE;
3425 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3426 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428 POSTING_READ(reg);
8db9d77b
ZW		 3429 udelay(150);
3430
5b2adf89 3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3435
5eddb70b 3436 reg = FDI_RX_IIR(pipe);
e1a44743 3437 for (tries = 0; tries < 5; tries++) {
5eddb70b 3438 temp = I915_READ(reg);
8db9d77b
ZW		 3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441 if ((temp & FDI_RX_BIT_LOCK)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3443 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3444 break;
3445 }
8db9d77b 3446 }
e1a44743 3447 if (tries == 5)
5eddb70b 3448 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3449
3450 /* Train 2 */
5eddb70b
CW		 3451 reg = FDI_TX_CTL(pipe);
3452 temp = I915_READ(reg);
8db9d77b
ZW		 3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3455 I915_WRITE(reg, temp);
8db9d77b 3456
5eddb70b
CW		 3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
8db9d77b
ZW		 3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3461 I915_WRITE(reg, temp);
8db9d77b 3462
5eddb70b
CW		 3463 POSTING_READ(reg);
3464 udelay(150);
8db9d77b 3465
5eddb70b 3466 reg = FDI_RX_IIR(pipe);
e1a44743 3467 for (tries = 0; tries < 5; tries++) {
5eddb70b 3468 temp = I915_READ(reg);
8db9d77b
ZW		 3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3472 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3474 break;
3475 }
8db9d77b 3476 }
e1a44743 3477 if (tries == 5)
5eddb70b 3478 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3479
3480 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3481
8db9d77b
ZW		 3482}
3483
0206e353 3484static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489};
3490
3491/* The FDI link training functions for SNB/Cougarpoint. */
3492static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493{
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
fa37d39e 3498 u32 reg, temp, i, retry;
8db9d77b 3499
e1a44743
AJ		 3500 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3501 for train result */
5eddb70b
CW		 3502 reg = FDI_RX_IMR(pipe);
3503 temp = I915_READ(reg);
e1a44743
AJ		 3504 temp &= ~FDI_RX_SYMBOL_LOCK;
3505 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3506 I915_WRITE(reg, temp);
3507
3508 POSTING_READ(reg);
e1a44743
AJ		 3509 udelay(150);
3510
8db9d77b 3511 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3512 reg = FDI_TX_CTL(pipe);
3513 temp = I915_READ(reg);
627eb5a3 3514 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3515 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3516 temp &= ~FDI_LINK_TRAIN_NONE;
3517 temp |= FDI_LINK_TRAIN_PATTERN_1;
3518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3519 /* SNB-B */
3520 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3521 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3522
d74cf324
DV		 3523 I915_WRITE(FDI_RX_MISC(pipe),
3524 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3525
5eddb70b
CW		 3526 reg = FDI_RX_CTL(pipe);
3527 temp = I915_READ(reg);
8db9d77b
ZW		 3528 if (HAS_PCH_CPT(dev)) {
3529 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3530 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3531 } else {
3532 temp &= ~FDI_LINK_TRAIN_NONE;
3533 temp |= FDI_LINK_TRAIN_PATTERN_1;
3534 }
5eddb70b
CW		 3535 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3536
3537 POSTING_READ(reg);
8db9d77b
ZW		 3538 udelay(150);
3539
0206e353 3540 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3541 reg = FDI_TX_CTL(pipe);
3542 temp = I915_READ(reg);
8db9d77b
ZW		 3543 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3544 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3545 I915_WRITE(reg, temp);
3546
3547 POSTING_READ(reg);
8db9d77b
ZW		 3548 udelay(500);
3549
fa37d39e
SP		 3550 for (retry = 0; retry < 5; retry++) {
3551 reg = FDI_RX_IIR(pipe);
3552 temp = I915_READ(reg);
3553 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3554 if (temp & FDI_RX_BIT_LOCK) {
3555 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3556 DRM_DEBUG_KMS("FDI train 1 done.\n");
3557 break;
3558 }
3559 udelay(50);
8db9d77b 3560 }
fa37d39e
SP		 3561 if (retry < 5)
3562 break;
8db9d77b
ZW		 3563 }
3564 if (i == 4)
5eddb70b 3565 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3566
3567 /* Train 2 */
5eddb70b
CW		 3568 reg = FDI_TX_CTL(pipe);
3569 temp = I915_READ(reg);
8db9d77b
ZW		 3570 temp &= ~FDI_LINK_TRAIN_NONE;
3571 temp |= FDI_LINK_TRAIN_PATTERN_2;
3572 if (IS_GEN6(dev)) {
3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 /* SNB-B */
3575 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3576 }
5eddb70b 3577 I915_WRITE(reg, temp);
8db9d77b 3578
5eddb70b
CW		 3579 reg = FDI_RX_CTL(pipe);
3580 temp = I915_READ(reg);
8db9d77b
ZW		 3581 if (HAS_PCH_CPT(dev)) {
3582 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3583 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3584 } else {
3585 temp &= ~FDI_LINK_TRAIN_NONE;
3586 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587 }
5eddb70b
CW		 3588 I915_WRITE(reg, temp);
3589
3590 POSTING_READ(reg);
8db9d77b
ZW		 3591 udelay(150);
3592
0206e353 3593 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3594 reg = FDI_TX_CTL(pipe);
3595 temp = I915_READ(reg);
8db9d77b
ZW		 3596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3597 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3598 I915_WRITE(reg, temp);
3599
3600 POSTING_READ(reg);
8db9d77b
ZW		 3601 udelay(500);
3602
fa37d39e
SP		 3603 for (retry = 0; retry < 5; retry++) {
3604 reg = FDI_RX_IIR(pipe);
3605 temp = I915_READ(reg);
3606 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3607 if (temp & FDI_RX_SYMBOL_LOCK) {
3608 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3609 DRM_DEBUG_KMS("FDI train 2 done.\n");
3610 break;
3611 }
3612 udelay(50);
8db9d77b 3613 }
fa37d39e
SP		 3614 if (retry < 5)
3615 break;
8db9d77b
ZW		 3616 }
3617 if (i == 4)
5eddb70b 3618 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3619
3620 DRM_DEBUG_KMS("FDI train done.\n");
3621}
3622
357555c0
JB		 3623/* Manual link training for Ivy Bridge A0 parts */
3624static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3625{
3626 struct drm_device *dev = crtc->dev;
3627 struct drm_i915_private *dev_priv = dev->dev_private;
3628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3629 int pipe = intel_crtc->pipe;
139ccd3f 3630 u32 reg, temp, i, j;
357555c0
JB		 3631
3632 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3633 for train result */
3634 reg = FDI_RX_IMR(pipe);
3635 temp = I915_READ(reg);
3636 temp &= ~FDI_RX_SYMBOL_LOCK;
3637 temp &= ~FDI_RX_BIT_LOCK;
3638 I915_WRITE(reg, temp);
3639
3640 POSTING_READ(reg);
3641 udelay(150);
3642
01a415fd
DV		 3643 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3644 I915_READ(FDI_RX_IIR(pipe)));
3645
139ccd3f
JB		 3646 /* Try each vswing and preemphasis setting twice before moving on */
3647 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3648 /* disable first in case we need to retry */
3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3652 temp &= ~FDI_TX_ENABLE;
3653 I915_WRITE(reg, temp);
357555c0 3654
139ccd3f
JB		 3655 reg = FDI_RX_CTL(pipe);
3656 temp = I915_READ(reg);
3657 temp &= ~FDI_LINK_TRAIN_AUTO;
3658 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3659 temp &= ~FDI_RX_ENABLE;
3660 I915_WRITE(reg, temp);
357555c0 3661
139ccd3f 3662 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
139ccd3f 3665 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3667 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3669 temp |= snb_b_fdi_train_param[j/2];
3670 temp |= FDI_COMPOSITE_SYNC;
3671 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3672
139ccd3f
JB		 3673 I915_WRITE(FDI_RX_MISC(pipe),
3674 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3675
139ccd3f 3676 reg = FDI_RX_CTL(pipe);
357555c0 3677 temp = I915_READ(reg);
139ccd3f
JB		 3678 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3679 temp |= FDI_COMPOSITE_SYNC;
3680 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3681
139ccd3f
JB		 3682 POSTING_READ(reg);
3683 udelay(1); /* should be 0.5us */
357555c0 3684
139ccd3f
JB		 3685 for (i = 0; i < 4; i++) {
3686 reg = FDI_RX_IIR(pipe);
3687 temp = I915_READ(reg);
3688 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3689
139ccd3f
JB		 3690 if (temp & FDI_RX_BIT_LOCK ||
3691 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3692 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3693 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3694 i);
3695 break;
3696 }
3697 udelay(1); /* should be 0.5us */
3698 }
3699 if (i == 4) {
3700 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3701 continue;
3702 }
357555c0 3703
139ccd3f 3704 /* Train 2 */
357555c0
JB		 3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
139ccd3f
JB		 3707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3709 I915_WRITE(reg, temp);
3710
3711 reg = FDI_RX_CTL(pipe);
3712 temp = I915_READ(reg);
3713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3715 I915_WRITE(reg, temp);
3716
3717 POSTING_READ(reg);
139ccd3f 3718 udelay(2); /* should be 1.5us */
357555c0 3719
139ccd3f
JB		 3720 for (i = 0; i < 4; i++) {
3721 reg = FDI_RX_IIR(pipe);
3722 temp = I915_READ(reg);
3723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3724
139ccd3f
JB		 3725 if (temp & FDI_RX_SYMBOL_LOCK ||
3726 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3727 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3728 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3729 i);
3730 goto train_done;
3731 }
3732 udelay(2); /* should be 1.5us */
357555c0 3733 }
139ccd3f
JB		 3734 if (i == 4)
3735 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3736 }
357555c0 3737
139ccd3f 3738train_done:
357555c0
JB		 3739 DRM_DEBUG_KMS("FDI train done.\n");
3740}
3741
88cefb6c 3742static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3743{
88cefb6c 3744 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3745 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3746 int pipe = intel_crtc->pipe;
5eddb70b 3747 u32 reg, temp;
79e53945 3748
c64e311e 3749
c98e9dcf 3750 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3751 reg = FDI_RX_CTL(pipe);
3752 temp = I915_READ(reg);
627eb5a3 3753 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3754 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3755 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3756 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3757
3758 POSTING_READ(reg);
c98e9dcf
JB		 3759 udelay(200);
3760
3761 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3762 temp = I915_READ(reg);
3763 I915_WRITE(reg, temp | FDI_PCDCLK);
3764
3765 POSTING_READ(reg);
c98e9dcf
JB		 3766 udelay(200);
3767
20749730
PZ		 3768 /* Enable CPU FDI TX PLL, always on for Ironlake */
3769 reg = FDI_TX_CTL(pipe);
3770 temp = I915_READ(reg);
3771 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3772 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3773
20749730
PZ		 3774 POSTING_READ(reg);
3775 udelay(100);
6be4a607 3776 }
0e23b99d
JB		 3777}
3778
88cefb6c
DV		 3779static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3780{
3781 struct drm_device *dev = intel_crtc->base.dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 int pipe = intel_crtc->pipe;
3784 u32 reg, temp;
3785
3786 /* Switch from PCDclk to Rawclk */
3787 reg = FDI_RX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3790
3791 /* Disable CPU FDI TX PLL */
3792 reg = FDI_TX_CTL(pipe);
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3795
3796 POSTING_READ(reg);
3797 udelay(100);
3798
3799 reg = FDI_RX_CTL(pipe);
3800 temp = I915_READ(reg);
3801 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3802
3803 /* Wait for the clocks to turn off. */
3804 POSTING_READ(reg);
3805 udelay(100);
3806}
3807
0fc932b8
JB		 3808static void ironlake_fdi_disable(struct drm_crtc *crtc)
3809{
3810 struct drm_device *dev = crtc->dev;
3811 struct drm_i915_private *dev_priv = dev->dev_private;
3812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3813 int pipe = intel_crtc->pipe;
3814 u32 reg, temp;
3815
3816 /* disable CPU FDI tx and PCH FDI rx */
3817 reg = FDI_TX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3820 POSTING_READ(reg);
3821
3822 reg = FDI_RX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~(0x7 << 16);
dfd07d72 3825 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3826 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3827
3828 POSTING_READ(reg);
3829 udelay(100);
3830
3831 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3832 if (HAS_PCH_IBX(dev))
6f06ce18 3833 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3834
3835 /* still set train pattern 1 */
3836 reg = FDI_TX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~FDI_LINK_TRAIN_NONE;
3839 temp |= FDI_LINK_TRAIN_PATTERN_1;
3840 I915_WRITE(reg, temp);
3841
3842 reg = FDI_RX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 if (HAS_PCH_CPT(dev)) {
3845 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3846 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3847 } else {
3848 temp &= ~FDI_LINK_TRAIN_NONE;
3849 temp |= FDI_LINK_TRAIN_PATTERN_1;
3850 }
3851 /* BPC in FDI rx is consistent with that in PIPECONF */
3852 temp &= ~(0x07 << 16);
dfd07d72 3853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3854 I915_WRITE(reg, temp);
3855
3856 POSTING_READ(reg);
3857 udelay(100);
3858}
3859
5dce5b93
CW		 3860bool intel_has_pending_fb_unpin(struct drm_device *dev)
3861{
3862 struct intel_crtc *crtc;
3863
3864 /* Note that we don't need to be called with mode_config.lock here
3865 * as our list of CRTC objects is static for the lifetime of the
3866 * device and so cannot disappear as we iterate. Similarly, we can
3867 * happily treat the predicates as racy, atomic checks as userspace
3868 * cannot claim and pin a new fb without at least acquring the
3869 * struct_mutex and so serialising with us.
3870 */
d3fcc808 3871 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3872 if (atomic_read(&crtc->unpin_work_count) == 0)
3873 continue;
3874
3875 if (crtc->unpin_work)
3876 intel_wait_for_vblank(dev, crtc->pipe);
3877
3878 return true;
3879 }
3880
3881 return false;
3882}
3883
d6bbafa1
CW		 3884static void page_flip_completed(struct intel_crtc *intel_crtc)
3885{
3886 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3887 struct intel_unpin_work *work = intel_crtc->unpin_work;
3888
3889 /* ensure that the unpin work is consistent wrt ->pending. */
3890 smp_rmb();
3891 intel_crtc->unpin_work = NULL;
3892
3893 if (work->event)
3894 drm_send_vblank_event(intel_crtc->base.dev,
3895 intel_crtc->pipe,
3896 work->event);
3897
3898 drm_crtc_vblank_put(&intel_crtc->base);
3899
3900 wake_up_all(&dev_priv->pending_flip_queue);
3901 queue_work(dev_priv->wq, &work->work);
3902
3903 trace_i915_flip_complete(intel_crtc->plane,
3904 work->pending_flip_obj);
3905}
3906
46a55d30 3907void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3908{
0f91128d 3909 struct drm_device *dev = crtc->dev;
5bb61643 3910 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3911
2c10d571 3912 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3913 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3914 !intel_crtc_has_pending_flip(crtc),
3915 60*HZ) == 0)) {
3916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3917
5e2d7afc 3918 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3919 if (intel_crtc->unpin_work) {
3920 WARN_ONCE(1, "Removing stuck page flip\n");
3921 page_flip_completed(intel_crtc);
3922 }
5e2d7afc 3923 spin_unlock_irq(&dev->event_lock);
9c787942 3924 }
5bb61643 3925
975d568a
CW		 3926 if (crtc->primary->fb) {
3927 mutex_lock(&dev->struct_mutex);
3928 intel_finish_fb(crtc->primary->fb);
3929 mutex_unlock(&dev->struct_mutex);
3930 }
e6c3a2a6
CW		 3931}
3932
e615efe4
ED		 3933/* Program iCLKIP clock to the desired frequency */
3934static void lpt_program_iclkip(struct drm_crtc *crtc)
3935{
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3938 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3939 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3940 u32 temp;
3941
a580516d 3942 mutex_lock(&dev_priv->sb_lock);
09153000 3943
e615efe4
ED		 3944 /* It is necessary to ungate the pixclk gate prior to programming
3945 * the divisors, and gate it back when it is done.
3946 */
3947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3948
3949 /* Disable SSCCTL */
3950 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3951 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3952 SBI_SSCCTL_DISABLE,
3953 SBI_ICLK);
e615efe4
ED		 3954
3955 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3956 if (clock == 20000) {
e615efe4
ED		 3957 auxdiv = 1;
3958 divsel = 0x41;
3959 phaseinc = 0x20;
3960 } else {
3961 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3962 * but the adjusted_mode->crtc_clock in in KHz. To get the
3963 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3964 * convert the virtual clock precision to KHz here for higher
3965 * precision.
3966 */
3967 u32 iclk_virtual_root_freq = 172800 * 1000;
3968 u32 iclk_pi_range = 64;
3969 u32 desired_divisor, msb_divisor_value, pi_value;
3970
12d7ceed 3971 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3972 msb_divisor_value = desired_divisor / iclk_pi_range;
3973 pi_value = desired_divisor % iclk_pi_range;
3974
3975 auxdiv = 0;
3976 divsel = msb_divisor_value - 2;
3977 phaseinc = pi_value;
3978 }
3979
3980 /* This should not happen with any sane values */
3981 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3982 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3983 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3984 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3985
3986 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3987 clock,
e615efe4
ED		 3988 auxdiv,
3989 divsel,
3990 phasedir,
3991 phaseinc);
3992
3993 /* Program SSCDIVINTPHASE6 */
988d6ee8 3994 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3995 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3996 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3997 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3998 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3999 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4000 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4001 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4002
4003 /* Program SSCAUXDIV */
988d6ee8 4004 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4005 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4006 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4007 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4008
4009 /* Enable modulator and associated divider */
988d6ee8 4010 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4011 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4012 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4013
4014 /* Wait for initialization time */
4015 udelay(24);
4016
4017 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4018
a580516d 4019 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4020}
4021
275f01b2
DV		 4022static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4023 enum pipe pch_transcoder)
4024{
4025 struct drm_device *dev = crtc->base.dev;
4026 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4027 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4028
4029 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4030 I915_READ(HTOTAL(cpu_transcoder)));
4031 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4032 I915_READ(HBLANK(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4034 I915_READ(HSYNC(cpu_transcoder)));
4035
4036 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4037 I915_READ(VTOTAL(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4039 I915_READ(VBLANK(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4041 I915_READ(VSYNC(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4043 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4044}
4045
003632d9 4046static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4047{
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 uint32_t temp;
4050
4051 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4052 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4053 return;
4054
4055 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4056 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4057
003632d9
ACO		 4058 temp &= ~FDI_BC_BIFURCATION_SELECT;
4059 if (enable)
4060 temp |= FDI_BC_BIFURCATION_SELECT;
4061
4062 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4063 I915_WRITE(SOUTH_CHICKEN1, temp);
4064 POSTING_READ(SOUTH_CHICKEN1);
4065}
4066
4067static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4068{
4069 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4070
4071 switch (intel_crtc->pipe) {
4072 case PIPE_A:
4073 break;
4074 case PIPE_B:
6e3c9717 4075 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4076 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4077 else
003632d9 4078 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4079
4080 break;
4081 case PIPE_C:
003632d9 4082 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4083
4084 break;
4085 default:
4086 BUG();
4087 }
4088}
4089
f67a559d
JB		 4090/*
4091 * Enable PCH resources required for PCH ports:
4092 * - PCH PLLs
4093 * - FDI training & RX/TX
4094 * - update transcoder timings
4095 * - DP transcoding bits
4096 * - transcoder
4097 */
4098static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4099{
4100 struct drm_device *dev = crtc->dev;
4101 struct drm_i915_private *dev_priv = dev->dev_private;
4102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4103 int pipe = intel_crtc->pipe;
ee7b9f93 4104 u32 reg, temp;
2c07245f 4105
ab9412ba 4106 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4107
1fbc0d78
DV		 4108 if (IS_IVYBRIDGE(dev))
4109 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4110
cd986abb
DV		 4111 /* Write the TU size bits before fdi link training, so that error
4112 * detection works. */
4113 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4114 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4115
c98e9dcf 4116 /* For PCH output, training FDI link */
674cf967 4117 dev_priv->display.fdi_link_train(crtc);
2c07245f 4118
3ad8a208
DV		 4119 /* We need to program the right clock selection before writing the pixel
4120 * mutliplier into the DPLL. */
303b81e0 4121 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4122 u32 sel;
4b645f14 4123
c98e9dcf 4124 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4125 temp |= TRANS_DPLL_ENABLE(pipe);
4126 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4127 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4128 temp |= sel;
4129 else
4130 temp &= ~sel;
c98e9dcf 4131 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4132 }
5eddb70b 4133
3ad8a208
DV		 4134 /* XXX: pch pll's can be enabled any time before we enable the PCH
4135 * transcoder, and we actually should do this to not upset any PCH
4136 * transcoder that already use the clock when we share it.
4137 *
4138 * Note that enable_shared_dpll tries to do the right thing, but
4139 * get_shared_dpll unconditionally resets the pll - we need that to have
4140 * the right LVDS enable sequence. */
85b3894f 4141 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4142
d9b6cb56
JB		 4143 /* set transcoder timing, panel must allow it */
4144 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4145 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4146
303b81e0 4147 intel_fdi_normal_train(crtc);
5e84e1a4 4148
c98e9dcf 4149 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4150 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4151 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4152 reg = TRANS_DP_CTL(pipe);
4153 temp = I915_READ(reg);
4154 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4155 TRANS_DP_SYNC_MASK |
4156 TRANS_DP_BPC_MASK);
e3ef4479 4157 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4158 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4159
4160 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4161 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4162 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4163 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4164
4165 switch (intel_trans_dp_port_sel(crtc)) {
4166 case PCH_DP_B:
5eddb70b 4167 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4168 break;
4169 case PCH_DP_C:
5eddb70b 4170 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4171 break;
4172 case PCH_DP_D:
5eddb70b 4173 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4174 break;
4175 default:
e95d41e1 4176 BUG();
32f9d658 4177 }
2c07245f 4178
5eddb70b 4179 I915_WRITE(reg, temp);
6be4a607 4180 }
b52eb4dc 4181
b8a4f404 4182 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4183}
4184
1507e5bd
PZ		 4185static void lpt_pch_enable(struct drm_crtc *crtc)
4186{
4187 struct drm_device *dev = crtc->dev;
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4190 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4191
ab9412ba 4192 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4193
8c52b5e8 4194 lpt_program_iclkip(crtc);
1507e5bd 4195
0540e488 4196 /* Set transcoder timing. */
275f01b2 4197 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4198
937bb610 4199 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4200}
4201
190f68c5
ACO		 4202struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4203 struct intel_crtc_state *crtc_state)
ee7b9f93 4204{
e2b78267 4205 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4206 struct intel_shared_dpll *pll;
e2b78267 4207 enum intel_dpll_id i;
ee7b9f93 4208
98b6bd99
DV		 4209 if (HAS_PCH_IBX(dev_priv->dev)) {
4210 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4211 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4212 pll = &dev_priv->shared_dplls[i];
98b6bd99 4213
46edb027
DV		 4214 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4215 crtc->base.base.id, pll->name);
98b6bd99 4216
8bd31e67 4217 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4218
98b6bd99
DV		 4219 goto found;
4220 }
4221
bcddf610
S		 4222 if (IS_BROXTON(dev_priv->dev)) {
4223 /* PLL is attached to port in bxt */
4224 struct intel_encoder *encoder;
4225 struct intel_digital_port *intel_dig_port;
4226
4227 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4228 if (WARN_ON(!encoder))
4229 return NULL;
4230
4231 intel_dig_port = enc_to_dig_port(&encoder->base);
4232 /* 1:1 mapping between ports and PLLs */
4233 i = (enum intel_dpll_id)intel_dig_port->port;
4234 pll = &dev_priv->shared_dplls[i];
4235 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4236 crtc->base.base.id, pll->name);
4237 WARN_ON(pll->new_config->crtc_mask);
4238
4239 goto found;
4240 }
4241
e72f9fbf
DV		 4242 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4243 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4244
4245 /* Only want to check enabled timings first */
8bd31e67 4246 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4247 continue;
4248
190f68c5 4249 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4250 &pll->new_config->hw_state,
4251 sizeof(pll->new_config->hw_state)) == 0) {
4252 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4253 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4254 pll->new_config->crtc_mask,
4255 pll->active);
ee7b9f93
JB		 4256 goto found;
4257 }
4258 }
4259
4260 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4261 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4262 pll = &dev_priv->shared_dplls[i];
8bd31e67 4263 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4264 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4265 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4266 goto found;
4267 }
4268 }
4269
4270 return NULL;
4271
4272found:
8bd31e67 4273 if (pll->new_config->crtc_mask == 0)
190f68c5 4274 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4275
190f68c5 4276 crtc_state->shared_dpll = i;
46edb027
DV		 4277 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4278 pipe_name(crtc->pipe));
ee7b9f93 4279
8bd31e67 4280 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4281
ee7b9f93
JB		 4282 return pll;
4283}
4284
8bd31e67
ACO		 4285/**
4286 * intel_shared_dpll_start_config - start a new PLL staged config
4287 * @dev_priv: DRM device
4288 * @clear_pipes: mask of pipes that will have their PLLs freed
4289 *
4290 * Starts a new PLL staged config, copying the current config but
4291 * releasing the references of pipes specified in clear_pipes.
4292 */
4293static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4294 unsigned clear_pipes)
4295{
4296 struct intel_shared_dpll *pll;
4297 enum intel_dpll_id i;
4298
4299 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4300 pll = &dev_priv->shared_dplls[i];
4301
4302 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4303 GFP_KERNEL);
4304 if (!pll->new_config)
4305 goto cleanup;
4306
4307 pll->new_config->crtc_mask &= ~clear_pipes;
4308 }
4309
4310 return 0;
4311
4312cleanup:
4313 while (--i >= 0) {
4314 pll = &dev_priv->shared_dplls[i];
f354d733 4315 kfree(pll->new_config);
8bd31e67
ACO		 4316 pll->new_config = NULL;
4317 }
4318
4319 return -ENOMEM;
4320}
4321
4322static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4323{
4324 struct intel_shared_dpll *pll;
4325 enum intel_dpll_id i;
4326
4327 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4328 pll = &dev_priv->shared_dplls[i];
4329
4330 WARN_ON(pll->new_config == &pll->config);
4331
4332 pll->config = *pll->new_config;
4333 kfree(pll->new_config);
4334 pll->new_config = NULL;
4335 }
4336}
4337
4338static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4339{
4340 struct intel_shared_dpll *pll;
4341 enum intel_dpll_id i;
4342
4343 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4344 pll = &dev_priv->shared_dplls[i];
4345
4346 WARN_ON(pll->new_config == &pll->config);
4347
4348 kfree(pll->new_config);
4349 pll->new_config = NULL;
4350 }
4351}
4352
a1520318 4353static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4354{
4355 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4356 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4357 u32 temp;
4358
4359 temp = I915_READ(dslreg);
4360 udelay(500);
4361 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4362 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4363 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4364 }
4365}
4366
a1b2278e
CK		 4367/**
4368 * skl_update_scaler_users - Stages update to crtc's scaler state
4369 * @intel_crtc: crtc
4370 * @crtc_state: crtc_state
4371 * @plane: plane (NULL indicates crtc is requesting update)
4372 * @plane_state: plane's state
4373 * @force_detach: request unconditional detachment of scaler
4374 *
4375 * This function updates scaler state for requested plane or crtc.
4376 * To request scaler usage update for a plane, caller shall pass plane pointer.
4377 * To request scaler usage update for crtc, caller shall pass plane pointer
4378 * as NULL.
4379 *
4380 * Return
4381 * 0 - scaler_usage updated successfully
4382 * error - requested scaling cannot be supported or other error condition
4383 */
4384int
4385skl_update_scaler_users(
4386 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4387 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4388 int force_detach)
4389{
4390 int need_scaling;
4391 int idx;
4392 int src_w, src_h, dst_w, dst_h;
4393 int *scaler_id;
4394 struct drm_framebuffer *fb;
4395 struct intel_crtc_scaler_state *scaler_state;
6156a456 4396 unsigned int rotation;
a1b2278e
CK		 4397
4398 if (!intel_crtc || !crtc_state)
4399 return 0;
4400
4401 scaler_state = &crtc_state->scaler_state;
4402
4403 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4404 fb = intel_plane ? plane_state->base.fb : NULL;
4405
4406 if (intel_plane) {
4407 src_w = drm_rect_width(&plane_state->src) >> 16;
4408 src_h = drm_rect_height(&plane_state->src) >> 16;
4409 dst_w = drm_rect_width(&plane_state->dst);
4410 dst_h = drm_rect_height(&plane_state->dst);
4411 scaler_id = &plane_state->scaler_id;
6156a456 4412 rotation = plane_state->base.rotation;
a1b2278e
CK		 4413 } else {
4414 struct drm_display_mode *adjusted_mode =
4415 &crtc_state->base.adjusted_mode;
4416 src_w = crtc_state->pipe_src_w;
4417 src_h = crtc_state->pipe_src_h;
4418 dst_w = adjusted_mode->hdisplay;
4419 dst_h = adjusted_mode->vdisplay;
4420 scaler_id = &scaler_state->scaler_id;
6156a456 4421 rotation = DRM_ROTATE_0;
a1b2278e 4422 }
6156a456
CK		 4423
4424 need_scaling = intel_rotation_90_or_270(rotation) ?
4425 (src_h != dst_w || src_w != dst_h):
4426 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4427
4428 /*
4429 * if plane is being disabled or scaler is no more required or force detach
4430 * - free scaler binded to this plane/crtc
4431 * - in order to do this, update crtc->scaler_usage
4432 *
4433 * Here scaler state in crtc_state is set free so that
4434 * scaler can be assigned to other user. Actual register
4435 * update to free the scaler is done in plane/panel-fit programming.
4436 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4437 */
4438 if (force_detach || !need_scaling || (intel_plane &&
4439 (!fb || !plane_state->visible))) {
4440 if (*scaler_id >= 0) {
4441 scaler_state->scaler_users &= ~(1 << idx);
4442 scaler_state->scalers[*scaler_id].in_use = 0;
4443
4444 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4445 "crtc_state = %p scaler_users = 0x%x\n",
4446 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4447 intel_plane ? intel_plane->base.base.id :
4448 intel_crtc->base.base.id, crtc_state,
4449 scaler_state->scaler_users);
4450 *scaler_id = -1;
4451 }
4452 return 0;
4453 }
4454
4455 /* range checks */
4456 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4457 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4458
4459 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4460 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4461 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4462 "size is out of scaler range\n",
4463 intel_plane ? "PLANE" : "CRTC",
4464 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4465 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4466 return -EINVAL;
4467 }
4468
4469 /* check colorkey */
225c228a
CK		 4470 if (WARN_ON(intel_plane &&
4471 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4472 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4473 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4474 return -EINVAL;
4475 }
4476
4477 /* Check src format */
4478 if (intel_plane) {
4479 switch (fb->pixel_format) {
4480 case DRM_FORMAT_RGB565:
4481 case DRM_FORMAT_XBGR8888:
4482 case DRM_FORMAT_XRGB8888:
4483 case DRM_FORMAT_ABGR8888:
4484 case DRM_FORMAT_ARGB8888:
4485 case DRM_FORMAT_XRGB2101010:
a1b2278e 4486 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4487 case DRM_FORMAT_YUYV:
4488 case DRM_FORMAT_YVYU:
4489 case DRM_FORMAT_UYVY:
4490 case DRM_FORMAT_VYUY:
4491 break;
4492 default:
4493 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4494 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4495 return -EINVAL;
4496 }
4497 }
4498
4499 /* mark this plane as a scaler user in crtc_state */
4500 scaler_state->scaler_users |= (1 << idx);
4501 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4502 "crtc_state = %p scaler_users = 0x%x\n",
4503 intel_plane ? "PLANE" : "CRTC",
4504 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4505 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4506 return 0;
4507}
4508
4509static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4510{
4511 struct drm_device *dev = crtc->base.dev;
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513 int pipe = crtc->pipe;
a1b2278e
CK		 4514 struct intel_crtc_scaler_state *scaler_state =
4515 &crtc->config->scaler_state;
4516
4517 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4518
4519 /* To update pfit, first update scaler state */
4520 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4521 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4522 skl_detach_scalers(crtc);
4523 if (!enable)
4524 return;
bd2e244f 4525
6e3c9717 4526 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4527 int id;
4528
4529 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4530 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4531 return;
4532 }
4533
4534 id = scaler_state->scaler_id;
4535 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4536 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4537 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4538 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4539
4540 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4541 }
4542}
4543
b074cec8
JB		 4544static void ironlake_pfit_enable(struct intel_crtc *crtc)
4545{
4546 struct drm_device *dev = crtc->base.dev;
4547 struct drm_i915_private *dev_priv = dev->dev_private;
4548 int pipe = crtc->pipe;
4549
6e3c9717 4550 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4551 /* Force use of hard-coded filter coefficients
4552 * as some pre-programmed values are broken,
4553 * e.g. x201.
4554 */
4555 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4556 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4557 PF_PIPE_SEL_IVB(pipe));
4558 else
4559 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4560 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4561 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4562 }
4563}
4564
4a3b8769 4565static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4566{
4567 struct drm_device *dev = crtc->dev;
4568 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4569 struct drm_plane *plane;
bb53d4ae
VS		 4570 struct intel_plane *intel_plane;
4571
af2b653b
MR		 4572 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4573 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4574 if (intel_plane->pipe == pipe)
4575 intel_plane_restore(&intel_plane->base);
af2b653b 4576 }
bb53d4ae
VS		 4577}
4578
20bc8673 4579void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4580{
cea165c3
VS		 4581 struct drm_device *dev = crtc->base.dev;
4582 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4583
6e3c9717 4584 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4585 return;
4586
cea165c3
VS		 4587 /* We can only enable IPS after we enable a plane and wait for a vblank */
4588 intel_wait_for_vblank(dev, crtc->pipe);
4589
d77e4531 4590 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4591 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4592 mutex_lock(&dev_priv->rps.hw_lock);
4593 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4594 mutex_unlock(&dev_priv->rps.hw_lock);
4595 /* Quoting Art Runyan: "its not safe to expect any particular
4596 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4597 * mailbox." Moreover, the mailbox may return a bogus state,
4598 * so we need to just enable it and continue on.
2a114cc1
BW		 4599 */
4600 } else {
4601 I915_WRITE(IPS_CTL, IPS_ENABLE);
4602 /* The bit only becomes 1 in the next vblank, so this wait here
4603 * is essentially intel_wait_for_vblank. If we don't have this
4604 * and don't wait for vblanks until the end of crtc_enable, then
4605 * the HW state readout code will complain that the expected
4606 * IPS_CTL value is not the one we read. */
4607 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4608 DRM_ERROR("Timed out waiting for IPS enable\n");
4609 }
d77e4531
PZ		 4610}
4611
20bc8673 4612void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4613{
4614 struct drm_device *dev = crtc->base.dev;
4615 struct drm_i915_private *dev_priv = dev->dev_private;
4616
6e3c9717 4617 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4618 return;
4619
4620 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4621 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4622 mutex_lock(&dev_priv->rps.hw_lock);
4623 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4624 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4625 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4626 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4627 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4628 } else {
2a114cc1 4629 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4630 POSTING_READ(IPS_CTL);
4631 }
d77e4531
PZ		 4632
4633 /* We need to wait for a vblank before we can disable the plane. */
4634 intel_wait_for_vblank(dev, crtc->pipe);
4635}
4636
4637/** Loads the palette/gamma unit for the CRTC with the prepared values */
4638static void intel_crtc_load_lut(struct drm_crtc *crtc)
4639{
4640 struct drm_device *dev = crtc->dev;
4641 struct drm_i915_private *dev_priv = dev->dev_private;
4642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4643 enum pipe pipe = intel_crtc->pipe;
4644 int palreg = PALETTE(pipe);
4645 int i;
4646 bool reenable_ips = false;
4647
4648 /* The clocks have to be on to load the palette. */
83d65738 4649 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4650 return;
4651
50360403 4652 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4653 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4654 assert_dsi_pll_enabled(dev_priv);
4655 else
4656 assert_pll_enabled(dev_priv, pipe);
4657 }
4658
4659 /* use legacy palette for Ironlake */
7a1db49a 4660 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4661 palreg = LGC_PALETTE(pipe);
4662
4663 /* Workaround : Do not read or write the pipe palette/gamma data while
4664 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4665 */
6e3c9717 4666 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4667 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4668 GAMMA_MODE_MODE_SPLIT)) {
4669 hsw_disable_ips(intel_crtc);
4670 reenable_ips = true;
4671 }
4672
4673 for (i = 0; i < 256; i++) {
4674 I915_WRITE(palreg + 4 * i,
4675 (intel_crtc->lut_r[i] << 16) |
4676 (intel_crtc->lut_g[i] << 8) |
4677 intel_crtc->lut_b[i]);
4678 }
4679
4680 if (reenable_ips)
4681 hsw_enable_ips(intel_crtc);
4682}
4683
7cac945f 4684static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4685{
7cac945f 4686 if (intel_crtc->overlay) {
d3eedb1a
VS		 4687 struct drm_device *dev = intel_crtc->base.dev;
4688 struct drm_i915_private *dev_priv = dev->dev_private;
4689
4690 mutex_lock(&dev->struct_mutex);
4691 dev_priv->mm.interruptible = false;
4692 (void) intel_overlay_switch_off(intel_crtc->overlay);
4693 dev_priv->mm.interruptible = true;
4694 mutex_unlock(&dev->struct_mutex);
4695 }
4696
4697 /* Let userspace switch the overlay on again. In most cases userspace
4698 * has to recompute where to put it anyway.
4699 */
4700}
4701
87d4300a
ML		 4702/**
4703 * intel_post_enable_primary - Perform operations after enabling primary plane
4704 * @crtc: the CRTC whose primary plane was just enabled
4705 *
4706 * Performs potentially sleeping operations that must be done after the primary
4707 * plane is enabled, such as updating FBC and IPS. Note that this may be
4708 * called due to an explicit primary plane update, or due to an implicit
4709 * re-enable that is caused when a sprite plane is updated to no longer
4710 * completely hide the primary plane.
4711 */
4712static void
4713intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4714{
4715 struct drm_device *dev = crtc->dev;
87d4300a 4716 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4718 int pipe = intel_crtc->pipe;
a5c4d7bc 4719
87d4300a
ML		 4720 /*
4721 * BDW signals flip done immediately if the plane
4722 * is disabled, even if the plane enable is already
4723 * armed to occur at the next vblank :(
4724 */
4725 if (IS_BROADWELL(dev))
4726 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4727
87d4300a
ML		 4728 /*
4729 * FIXME IPS should be fine as long as one plane is
4730 * enabled, but in practice it seems to have problems
4731 * when going from primary only to sprite only and vice
4732 * versa.
4733 */
a5c4d7bc
VS		 4734 hsw_enable_ips(intel_crtc);
4735
4736 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4737 intel_fbc_update(dev);
a5c4d7bc 4738 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4739
4740 /*
87d4300a
ML		 4741 * Gen2 reports pipe underruns whenever all planes are disabled.
4742 * So don't enable underrun reporting before at least some planes
4743 * are enabled.
4744 * FIXME: Need to fix the logic to work when we turn off all planes
4745 * but leave the pipe running.
f99d7069 4746 */
87d4300a
ML		 4747 if (IS_GEN2(dev))
4748 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4749
4750 /* Underruns don't raise interrupts, so check manually. */
4751 if (HAS_GMCH_DISPLAY(dev))
4752 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4753}
4754
87d4300a
ML		 4755/**
4756 * intel_pre_disable_primary - Perform operations before disabling primary plane
4757 * @crtc: the CRTC whose primary plane is to be disabled
4758 *
4759 * Performs potentially sleeping operations that must be done before the
4760 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4761 * be called due to an explicit primary plane update, or due to an implicit
4762 * disable that is caused when a sprite plane completely hides the primary
4763 * plane.
4764 */
4765static void
4766intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4767{
4768 struct drm_device *dev = crtc->dev;
4769 struct drm_i915_private *dev_priv = dev->dev_private;
4770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4771 int pipe = intel_crtc->pipe;
a5c4d7bc 4772
87d4300a
ML		 4773 /*
4774 * Gen2 reports pipe underruns whenever all planes are disabled.
4775 * So diasble underrun reporting before all the planes get disabled.
4776 * FIXME: Need to fix the logic to work when we turn off all planes
4777 * but leave the pipe running.
4778 */
4779 if (IS_GEN2(dev))
4780 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4781
87d4300a
ML		 4782 /*
4783 * Vblank time updates from the shadow to live plane control register
4784 * are blocked if the memory self-refresh mode is active at that
4785 * moment. So to make sure the plane gets truly disabled, disable
4786 * first the self-refresh mode. The self-refresh enable bit in turn
4787 * will be checked/applied by the HW only at the next frame start
4788 * event which is after the vblank start event, so we need to have a
4789 * wait-for-vblank between disabling the plane and the pipe.
4790 */
4791 if (HAS_GMCH_DISPLAY(dev))
4792 intel_set_memory_cxsr(dev_priv, false);
4793
4794 mutex_lock(&dev->struct_mutex);
e35fef21 4795 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4796 intel_fbc_disable(dev);
87d4300a 4797 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4798
87d4300a
ML		 4799 /*
4800 * FIXME IPS should be fine as long as one plane is
4801 * enabled, but in practice it seems to have problems
4802 * when going from primary only to sprite only and vice
4803 * versa.
4804 */
a5c4d7bc 4805 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4806}
4807
4808static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4809{
2d847d45
RV		 4810 struct drm_device *dev = crtc->dev;
4811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4812 int pipe = intel_crtc->pipe;
4813
87d4300a
ML		 4814 intel_enable_primary_hw_plane(crtc->primary, crtc);
4815 intel_enable_sprite_planes(crtc);
4816 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4817
4818 intel_post_enable_primary(crtc);
2d847d45
RV		 4819
4820 /*
4821 * FIXME: Once we grow proper nuclear flip support out of this we need
4822 * to compute the mask of flip planes precisely. For the time being
4823 * consider this a flip to a NULL plane.
4824 */
4825 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
87d4300a
ML		 4826}
4827
4828static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4829{
4830 struct drm_device *dev = crtc->dev;
4831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4832 struct intel_plane *intel_plane;
4833 int pipe = intel_crtc->pipe;
4834
4835 intel_crtc_wait_for_pending_flips(crtc);
4836
4837 intel_pre_disable_primary(crtc);
a5c4d7bc 4838
7cac945f 4839 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4840 for_each_intel_plane(dev, intel_plane) {
4841 if (intel_plane->pipe == pipe) {
4842 struct drm_crtc *from = intel_plane->base.crtc;
4843
4844 intel_plane->disable_plane(&intel_plane->base,
4845 from ?: crtc, true);
4846 }
4847 }
f98551ae 4848
f99d7069
DV		 4849 /*
4850 * FIXME: Once we grow proper nuclear flip support out of this we need
4851 * to compute the mask of flip planes precisely. For the time being
4852 * consider this a flip to a NULL plane.
4853 */
4854 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4855}
4856
f67a559d
JB		 4857static void ironlake_crtc_enable(struct drm_crtc *crtc)
4858{
4859 struct drm_device *dev = crtc->dev;
4860 struct drm_i915_private *dev_priv = dev->dev_private;
4861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4862 struct intel_encoder *encoder;
f67a559d 4863 int pipe = intel_crtc->pipe;
f67a559d 4864
83d65738 4865 WARN_ON(!crtc->state->enable);
08a48469 4866
f67a559d
JB		 4867 if (intel_crtc->active)
4868 return;
4869
6e3c9717 4870 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4871 intel_prepare_shared_dpll(intel_crtc);
4872
6e3c9717 4873 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4874 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4875
4876 intel_set_pipe_timings(intel_crtc);
4877
6e3c9717 4878 if (intel_crtc->config->has_pch_encoder) {
29407aab 4879 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4880 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4881 }
4882
4883 ironlake_set_pipeconf(crtc);
4884
f67a559d 4885 intel_crtc->active = true;
8664281b 4886
a72e4c9f
DV		 4887 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4888 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4889
f6736a1a 4890 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4891 if (encoder->pre_enable)
4892 encoder->pre_enable(encoder);
f67a559d 4893
6e3c9717 4894 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4895 /* Note: FDI PLL enabling _must_ be done before we enable the
4896 * cpu pipes, hence this is separate from all the other fdi/pch
4897 * enabling. */
88cefb6c 4898 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4899 } else {
4900 assert_fdi_tx_disabled(dev_priv, pipe);
4901 assert_fdi_rx_disabled(dev_priv, pipe);
4902 }
f67a559d 4903
b074cec8 4904 ironlake_pfit_enable(intel_crtc);
f67a559d 4905
9c54c0dd
JB		 4906 /*
4907 * On ILK+ LUT must be loaded before the pipe is running but with
4908 * clocks enabled
4909 */
4910 intel_crtc_load_lut(crtc);
4911
f37fcc2a 4912 intel_update_watermarks(crtc);
e1fdc473 4913 intel_enable_pipe(intel_crtc);
f67a559d 4914
6e3c9717 4915 if (intel_crtc->config->has_pch_encoder)
f67a559d 4916 ironlake_pch_enable(crtc);
c98e9dcf 4917
f9b61ff6
DV		 4918 assert_vblank_disabled(crtc);
4919 drm_crtc_vblank_on(crtc);
4920
fa5c73b1
DV		 4921 for_each_encoder_on_crtc(dev, crtc, encoder)
4922 encoder->enable(encoder);
61b77ddd
DV		 4923
4924 if (HAS_PCH_CPT(dev))
a1520318 4925 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4926}
4927
42db64ef
PZ		 4928/* IPS only exists on ULT machines and is tied to pipe A. */
4929static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4930{
f5adf94e 4931 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4932}
4933
e4916946
PZ		 4934/*
4935 * This implements the workaround described in the "notes" section of the mode
4936 * set sequence documentation. When going from no pipes or single pipe to
4937 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4938 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4939 */
4940static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4941{
4942 struct drm_device *dev = crtc->base.dev;
4943 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4944
4945 /* We want to get the other_active_crtc only if there's only 1 other
4946 * active crtc. */
d3fcc808 4947 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4948 if (!crtc_it->active || crtc_it == crtc)
4949 continue;
4950
4951 if (other_active_crtc)
4952 return;
4953
4954 other_active_crtc = crtc_it;
4955 }
4956 if (!other_active_crtc)
4957 return;
4958
4959 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4960 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4961}
4962
4f771f10
PZ		 4963static void haswell_crtc_enable(struct drm_crtc *crtc)
4964{
4965 struct drm_device *dev = crtc->dev;
4966 struct drm_i915_private *dev_priv = dev->dev_private;
4967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4968 struct intel_encoder *encoder;
4969 int pipe = intel_crtc->pipe;
4f771f10 4970
83d65738 4971 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4972
4973 if (intel_crtc->active)
4974 return;
4975
df8ad70c
DV		 4976 if (intel_crtc_to_shared_dpll(intel_crtc))
4977 intel_enable_shared_dpll(intel_crtc);
4978
6e3c9717 4979 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4980 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4981
4982 intel_set_pipe_timings(intel_crtc);
4983
6e3c9717
ACO		 4984 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4985 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4986 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4987 }
4988
6e3c9717 4989 if (intel_crtc->config->has_pch_encoder) {
229fca97 4990 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4991 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4992 }
4993
4994 haswell_set_pipeconf(crtc);
4995
4996 intel_set_pipe_csc(crtc);
4997
4f771f10 4998 intel_crtc->active = true;
8664281b 4999
a72e4c9f 5000 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5001 for_each_encoder_on_crtc(dev, crtc, encoder)
5002 if (encoder->pre_enable)
5003 encoder->pre_enable(encoder);
5004
6e3c9717 5005 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5006 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5007 true);
4fe9467d
ID		 5008 dev_priv->display.fdi_link_train(crtc);
5009 }
5010
1f544388 5011 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5012
ff6d9f55 5013 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5014 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5015 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5016 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5017 else
5018 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5019
5020 /*
5021 * On ILK+ LUT must be loaded before the pipe is running but with
5022 * clocks enabled
5023 */
5024 intel_crtc_load_lut(crtc);
5025
1f544388 5026 intel_ddi_set_pipe_settings(crtc);
8228c251 5027 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5028
f37fcc2a 5029 intel_update_watermarks(crtc);
e1fdc473 5030 intel_enable_pipe(intel_crtc);
42db64ef 5031
6e3c9717 5032 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5033 lpt_pch_enable(crtc);
4f771f10 5034
6e3c9717 5035 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5036 intel_ddi_set_vc_payload_alloc(crtc, true);
5037
f9b61ff6
DV		 5038 assert_vblank_disabled(crtc);
5039 drm_crtc_vblank_on(crtc);
5040
8807e55b 5041 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5042 encoder->enable(encoder);
8807e55b
JN		 5043 intel_opregion_notify_encoder(encoder, true);
5044 }
4f771f10 5045
e4916946
PZ		 5046 /* If we change the relative order between pipe/planes enabling, we need
5047 * to change the workaround. */
5048 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5049}
5050
3f8dce3a
DV		 5051static void ironlake_pfit_disable(struct intel_crtc *crtc)
5052{
5053 struct drm_device *dev = crtc->base.dev;
5054 struct drm_i915_private *dev_priv = dev->dev_private;
5055 int pipe = crtc->pipe;
5056
5057 /* To avoid upsetting the power well on haswell only disable the pfit if
5058 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5059 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5060 I915_WRITE(PF_CTL(pipe), 0);
5061 I915_WRITE(PF_WIN_POS(pipe), 0);
5062 I915_WRITE(PF_WIN_SZ(pipe), 0);
5063 }
5064}
5065
6be4a607
JB		 5066static void ironlake_crtc_disable(struct drm_crtc *crtc)
5067{
5068 struct drm_device *dev = crtc->dev;
5069 struct drm_i915_private *dev_priv = dev->dev_private;
5070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5071 struct intel_encoder *encoder;
6be4a607 5072 int pipe = intel_crtc->pipe;
5eddb70b 5073 u32 reg, temp;
b52eb4dc 5074
f7abfe8b
CW		 5075 if (!intel_crtc->active)
5076 return;
5077
ea9d758d
DV		 5078 for_each_encoder_on_crtc(dev, crtc, encoder)
5079 encoder->disable(encoder);
5080
f9b61ff6
DV		 5081 drm_crtc_vblank_off(crtc);
5082 assert_vblank_disabled(crtc);
5083
6e3c9717 5084 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5085 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5086
575f7ab7 5087 intel_disable_pipe(intel_crtc);
32f9d658 5088
3f8dce3a 5089 ironlake_pfit_disable(intel_crtc);
2c07245f 5090
5a74f70a
VS		 5091 if (intel_crtc->config->has_pch_encoder)
5092 ironlake_fdi_disable(crtc);
5093
bf49ec8c
DV		 5094 for_each_encoder_on_crtc(dev, crtc, encoder)
5095 if (encoder->post_disable)
5096 encoder->post_disable(encoder);
2c07245f 5097
6e3c9717 5098 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5099 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5100
d925c59a
DV		 5101 if (HAS_PCH_CPT(dev)) {
5102 /* disable TRANS_DP_CTL */
5103 reg = TRANS_DP_CTL(pipe);
5104 temp = I915_READ(reg);
5105 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5106 TRANS_DP_PORT_SEL_MASK);
5107 temp |= TRANS_DP_PORT_SEL_NONE;
5108 I915_WRITE(reg, temp);
5109
5110 /* disable DPLL_SEL */
5111 temp = I915_READ(PCH_DPLL_SEL);
11887397 5112 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5113 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5114 }
e3421a18 5115
d925c59a 5116 /* disable PCH DPLL */
e72f9fbf 5117 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5118
d925c59a
DV		 5119 ironlake_fdi_pll_disable(intel_crtc);
5120 }
6b383a7f 5121
f7abfe8b 5122 intel_crtc->active = false;
46ba614c 5123 intel_update_watermarks(crtc);
d1ebd816
BW		 5124
5125 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5126 intel_fbc_update(dev);
d1ebd816 5127 mutex_unlock(&dev->struct_mutex);
6be4a607 5128}
1b3c7a47 5129
4f771f10 5130static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5131{
4f771f10
PZ		 5132 struct drm_device *dev = crtc->dev;
5133 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5135 struct intel_encoder *encoder;
6e3c9717 5136 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5137
4f771f10
PZ		 5138 if (!intel_crtc->active)
5139 return;
5140
8807e55b
JN		 5141 for_each_encoder_on_crtc(dev, crtc, encoder) {
5142 intel_opregion_notify_encoder(encoder, false);
4f771f10 5143 encoder->disable(encoder);
8807e55b 5144 }
4f771f10 5145
f9b61ff6
DV		 5146 drm_crtc_vblank_off(crtc);
5147 assert_vblank_disabled(crtc);
5148
6e3c9717 5149 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5150 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5151 false);
575f7ab7 5152 intel_disable_pipe(intel_crtc);
4f771f10 5153
6e3c9717 5154 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5155 intel_ddi_set_vc_payload_alloc(crtc, false);
5156
ad80a810 5157 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5158
ff6d9f55 5159 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5160 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5161 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5162 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5163 else
5164 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5165
1f544388 5166 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5167
6e3c9717 5168 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5169 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5170 intel_ddi_fdi_disable(crtc);
83616634 5171 }
4f771f10 5172
97b040aa
ID		 5173 for_each_encoder_on_crtc(dev, crtc, encoder)
5174 if (encoder->post_disable)
5175 encoder->post_disable(encoder);
5176
4f771f10 5177 intel_crtc->active = false;
46ba614c 5178 intel_update_watermarks(crtc);
4f771f10
PZ		 5179
5180 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5181 intel_fbc_update(dev);
4f771f10 5182 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5183
5184 if (intel_crtc_to_shared_dpll(intel_crtc))
5185 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5186}
5187
2dd24552
JB		 5188static void i9xx_pfit_enable(struct intel_crtc *crtc)
5189{
5190 struct drm_device *dev = crtc->base.dev;
5191 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5192 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5193
681a8504 5194 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5195 return;
5196
2dd24552 5197 /*
c0b03411
DV		 5198 * The panel fitter should only be adjusted whilst the pipe is disabled,
5199 * according to register description and PRM.
2dd24552 5200 */
c0b03411
DV		 5201 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5202 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5203
b074cec8
JB		 5204 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5205 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5206
5207 /* Border color in case we don't scale up to the full screen. Black by
5208 * default, change to something else for debugging. */
5209 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5210}
5211
d05410f9
DA		 5212static enum intel_display_power_domain port_to_power_domain(enum port port)
5213{
5214 switch (port) {
5215 case PORT_A:
5216 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5217 case PORT_B:
5218 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5219 case PORT_C:
5220 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5221 case PORT_D:
5222 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5223 default:
5224 WARN_ON_ONCE(1);
5225 return POWER_DOMAIN_PORT_OTHER;
5226 }
5227}
5228
77d22dca
ID		 5229#define for_each_power_domain(domain, mask) \
5230 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5231 if ((1 << (domain)) & (mask))
5232
319be8ae
ID		 5233enum intel_display_power_domain
5234intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5235{
5236 struct drm_device *dev = intel_encoder->base.dev;
5237 struct intel_digital_port *intel_dig_port;
5238
5239 switch (intel_encoder->type) {
5240 case INTEL_OUTPUT_UNKNOWN:
5241 /* Only DDI platforms should ever use this output type */
5242 WARN_ON_ONCE(!HAS_DDI(dev));
5243 case INTEL_OUTPUT_DISPLAYPORT:
5244 case INTEL_OUTPUT_HDMI:
5245 case INTEL_OUTPUT_EDP:
5246 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5247 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5248 case INTEL_OUTPUT_DP_MST:
5249 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5250 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5251 case INTEL_OUTPUT_ANALOG:
5252 return POWER_DOMAIN_PORT_CRT;
5253 case INTEL_OUTPUT_DSI:
5254 return POWER_DOMAIN_PORT_DSI;
5255 default:
5256 return POWER_DOMAIN_PORT_OTHER;
5257 }
5258}
5259
5260static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5261{
319be8ae
ID		 5262 struct drm_device *dev = crtc->dev;
5263 struct intel_encoder *intel_encoder;
5264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5265 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5266 unsigned long mask;
5267 enum transcoder transcoder;
5268
5269 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5270
5271 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5272 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5273 if (intel_crtc->config->pch_pfit.enabled ||
5274 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5275 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5276
319be8ae
ID		 5277 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5278 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5279
77d22dca
ID		 5280 return mask;
5281}
5282
679dacd4 5283static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5284{
679dacd4 5285 struct drm_device *dev = state->dev;
77d22dca
ID		 5286 struct drm_i915_private *dev_priv = dev->dev_private;
5287 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5288 struct intel_crtc *crtc;
5289
5290 /*
5291 * First get all needed power domains, then put all unneeded, to avoid
5292 * any unnecessary toggling of the power wells.
5293 */
d3fcc808 5294 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5295 enum intel_display_power_domain domain;
5296
83d65738 5297 if (!crtc->base.state->enable)
77d22dca
ID		 5298 continue;
5299
319be8ae 5300 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5301
5302 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5303 intel_display_power_get(dev_priv, domain);
5304 }
5305
50f6e502 5306 if (dev_priv->display.modeset_global_resources)
679dacd4 5307 dev_priv->display.modeset_global_resources(state);
50f6e502 5308
d3fcc808 5309 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5310 enum intel_display_power_domain domain;
5311
5312 for_each_power_domain(domain, crtc->enabled_power_domains)
5313 intel_display_power_put(dev_priv, domain);
5314
5315 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5316 }
5317
5318 intel_display_set_init_power(dev_priv, false);
5319}
5320
560a7ae4
DL		 5321static void intel_update_max_cdclk(struct drm_device *dev)
5322{
5323 struct drm_i915_private *dev_priv = dev->dev_private;
5324
5325 if (IS_SKYLAKE(dev)) {
5326 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5327
5328 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5329 dev_priv->max_cdclk_freq = 675000;
5330 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5331 dev_priv->max_cdclk_freq = 540000;
5332 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5333 dev_priv->max_cdclk_freq = 450000;
5334 else
5335 dev_priv->max_cdclk_freq = 337500;
5336 } else if (IS_BROADWELL(dev)) {
5337 /*
5338 * FIXME with extra cooling we can allow
5339 * 540 MHz for ULX and 675 Mhz for ULT.
5340 * How can we know if extra cooling is
5341 * available? PCI ID, VTB, something else?
5342 */
5343 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5344 dev_priv->max_cdclk_freq = 450000;
5345 else if (IS_BDW_ULX(dev))
5346 dev_priv->max_cdclk_freq = 450000;
5347 else if (IS_BDW_ULT(dev))
5348 dev_priv->max_cdclk_freq = 540000;
5349 else
5350 dev_priv->max_cdclk_freq = 675000;
5351 } else if (IS_VALLEYVIEW(dev)) {
5352 dev_priv->max_cdclk_freq = 400000;
5353 } else {
5354 /* otherwise assume cdclk is fixed */
5355 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5356 }
5357
5358 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5359 dev_priv->max_cdclk_freq);
5360}
5361
5362static void intel_update_cdclk(struct drm_device *dev)
5363{
5364 struct drm_i915_private *dev_priv = dev->dev_private;
5365
5366 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5367 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5368 dev_priv->cdclk_freq);
5369
5370 /*
5371 * Program the gmbus_freq based on the cdclk frequency.
5372 * BSpec erroneously claims we should aim for 4MHz, but
5373 * in fact 1MHz is the correct frequency.
5374 */
5375 if (IS_VALLEYVIEW(dev)) {
5376 /*
5377 * Program the gmbus_freq based on the cdclk frequency.
5378 * BSpec erroneously claims we should aim for 4MHz, but
5379 * in fact 1MHz is the correct frequency.
5380 */
5381 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5382 }
5383
5384 if (dev_priv->max_cdclk_freq == 0)
5385 intel_update_max_cdclk(dev);
5386}
5387
70d0c574 5388static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5389{
5390 struct drm_i915_private *dev_priv = dev->dev_private;
5391 uint32_t divider;
5392 uint32_t ratio;
5393 uint32_t current_freq;
5394 int ret;
5395
5396 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5397 switch (frequency) {
5398 case 144000:
5399 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5400 ratio = BXT_DE_PLL_RATIO(60);
5401 break;
5402 case 288000:
5403 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5404 ratio = BXT_DE_PLL_RATIO(60);
5405 break;
5406 case 384000:
5407 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5408 ratio = BXT_DE_PLL_RATIO(60);
5409 break;
5410 case 576000:
5411 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5412 ratio = BXT_DE_PLL_RATIO(60);
5413 break;
5414 case 624000:
5415 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5416 ratio = BXT_DE_PLL_RATIO(65);
5417 break;
5418 case 19200:
5419 /*
5420 * Bypass frequency with DE PLL disabled. Init ratio, divider
5421 * to suppress GCC warning.
5422 */
5423 ratio = 0;
5424 divider = 0;
5425 break;
5426 default:
5427 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5428
5429 return;
5430 }
5431
5432 mutex_lock(&dev_priv->rps.hw_lock);
5433 /* Inform power controller of upcoming frequency change */
5434 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5435 0x80000000);
5436 mutex_unlock(&dev_priv->rps.hw_lock);
5437
5438 if (ret) {
5439 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5440 ret, frequency);
5441 return;
5442 }
5443
5444 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5445 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5446 current_freq = current_freq * 500 + 1000;
5447
5448 /*
5449 * DE PLL has to be disabled when
5450 * - setting to 19.2MHz (bypass, PLL isn't used)
5451 * - before setting to 624MHz (PLL needs toggling)
5452 * - before setting to any frequency from 624MHz (PLL needs toggling)
5453 */
5454 if (frequency == 19200 || frequency == 624000 ||
5455 current_freq == 624000) {
5456 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5457 /* Timeout 200us */
5458 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5459 1))
5460 DRM_ERROR("timout waiting for DE PLL unlock\n");
5461 }
5462
5463 if (frequency != 19200) {
5464 uint32_t val;
5465
5466 val = I915_READ(BXT_DE_PLL_CTL);
5467 val &= ~BXT_DE_PLL_RATIO_MASK;
5468 val |= ratio;
5469 I915_WRITE(BXT_DE_PLL_CTL, val);
5470
5471 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5472 /* Timeout 200us */
5473 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5474 DRM_ERROR("timeout waiting for DE PLL lock\n");
5475
5476 val = I915_READ(CDCLK_CTL);
5477 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5478 val |= divider;
5479 /*
5480 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5481 * enable otherwise.
5482 */
5483 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5484 if (frequency >= 500000)
5485 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5486
5487 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5488 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5489 val |= (frequency - 1000) / 500;
5490 I915_WRITE(CDCLK_CTL, val);
5491 }
5492
5493 mutex_lock(&dev_priv->rps.hw_lock);
5494 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5495 DIV_ROUND_UP(frequency, 25000));
5496 mutex_unlock(&dev_priv->rps.hw_lock);
5497
5498 if (ret) {
5499 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5500 ret, frequency);
5501 return;
5502 }
5503
a47871bd 5504 intel_update_cdclk(dev);
f8437dd1
VK		 5505}
5506
5507void broxton_init_cdclk(struct drm_device *dev)
5508{
5509 struct drm_i915_private *dev_priv = dev->dev_private;
5510 uint32_t val;
5511
5512 /*
5513 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5514 * or else the reset will hang because there is no PCH to respond.
5515 * Move the handshake programming to initialization sequence.
5516 * Previously was left up to BIOS.
5517 */
5518 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5519 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5520 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5521
5522 /* Enable PG1 for cdclk */
5523 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5524
5525 /* check if cd clock is enabled */
5526 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5527 DRM_DEBUG_KMS("Display already initialized\n");
5528 return;
5529 }
5530
5531 /*
5532 * FIXME:
5533 * - The initial CDCLK needs to be read from VBT.
5534 * Need to make this change after VBT has changes for BXT.
5535 * - check if setting the max (or any) cdclk freq is really necessary
5536 * here, it belongs to modeset time
5537 */
5538 broxton_set_cdclk(dev, 624000);
5539
5540 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5541 POSTING_READ(DBUF_CTL);
5542
f8437dd1
VK		 5543 udelay(10);
5544
5545 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5546 DRM_ERROR("DBuf power enable timeout!\n");
5547}
5548
5549void broxton_uninit_cdclk(struct drm_device *dev)
5550{
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5552
5553 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5554 POSTING_READ(DBUF_CTL);
5555
f8437dd1
VK		 5556 udelay(10);
5557
5558 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5559 DRM_ERROR("DBuf power disable timeout!\n");
5560
5561 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5562 broxton_set_cdclk(dev, 19200);
5563
5564 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5565}
5566
5d96d8af
DL		 5567static const struct skl_cdclk_entry {
5568 unsigned int freq;
5569 unsigned int vco;
5570} skl_cdclk_frequencies[] = {
5571 { .freq = 308570, .vco = 8640 },
5572 { .freq = 337500, .vco = 8100 },
5573 { .freq = 432000, .vco = 8640 },
5574 { .freq = 450000, .vco = 8100 },
5575 { .freq = 540000, .vco = 8100 },
5576 { .freq = 617140, .vco = 8640 },
5577 { .freq = 675000, .vco = 8100 },
5578};
5579
5580static unsigned int skl_cdclk_decimal(unsigned int freq)
5581{
5582 return (freq - 1000) / 500;
5583}
5584
5585static unsigned int skl_cdclk_get_vco(unsigned int freq)
5586{
5587 unsigned int i;
5588
5589 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5590 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5591
5592 if (e->freq == freq)
5593 return e->vco;
5594 }
5595
5596 return 8100;
5597}
5598
5599static void
5600skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5601{
5602 unsigned int min_freq;
5603 u32 val;
5604
5605 /* select the minimum CDCLK before enabling DPLL 0 */
5606 val = I915_READ(CDCLK_CTL);
5607 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5608 val |= CDCLK_FREQ_337_308;
5609
5610 if (required_vco == 8640)
5611 min_freq = 308570;
5612 else
5613 min_freq = 337500;
5614
5615 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5616
5617 I915_WRITE(CDCLK_CTL, val);
5618 POSTING_READ(CDCLK_CTL);
5619
5620 /*
5621 * We always enable DPLL0 with the lowest link rate possible, but still
5622 * taking into account the VCO required to operate the eDP panel at the
5623 * desired frequency. The usual DP link rates operate with a VCO of
5624 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5625 * The modeset code is responsible for the selection of the exact link
5626 * rate later on, with the constraint of choosing a frequency that
5627 * works with required_vco.
5628 */
5629 val = I915_READ(DPLL_CTRL1);
5630
5631 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5632 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5633 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5634 if (required_vco == 8640)
5635 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5636 SKL_DPLL0);
5637 else
5638 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5639 SKL_DPLL0);
5640
5641 I915_WRITE(DPLL_CTRL1, val);
5642 POSTING_READ(DPLL_CTRL1);
5643
5644 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5645
5646 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5647 DRM_ERROR("DPLL0 not locked\n");
5648}
5649
5650static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5651{
5652 int ret;
5653 u32 val;
5654
5655 /* inform PCU we want to change CDCLK */
5656 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5657 mutex_lock(&dev_priv->rps.hw_lock);
5658 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5659 mutex_unlock(&dev_priv->rps.hw_lock);
5660
5661 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5662}
5663
5664static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5665{
5666 unsigned int i;
5667
5668 for (i = 0; i < 15; i++) {
5669 if (skl_cdclk_pcu_ready(dev_priv))
5670 return true;
5671 udelay(10);
5672 }
5673
5674 return false;
5675}
5676
5677static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5678{
560a7ae4 5679 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5680 u32 freq_select, pcu_ack;
5681
5682 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5683
5684 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5685 DRM_ERROR("failed to inform PCU about cdclk change\n");
5686 return;
5687 }
5688
5689 /* set CDCLK_CTL */
5690 switch(freq) {
5691 case 450000:
5692 case 432000:
5693 freq_select = CDCLK_FREQ_450_432;
5694 pcu_ack = 1;
5695 break;
5696 case 540000:
5697 freq_select = CDCLK_FREQ_540;
5698 pcu_ack = 2;
5699 break;
5700 case 308570:
5701 case 337500:
5702 default:
5703 freq_select = CDCLK_FREQ_337_308;
5704 pcu_ack = 0;
5705 break;
5706 case 617140:
5707 case 675000:
5708 freq_select = CDCLK_FREQ_675_617;
5709 pcu_ack = 3;
5710 break;
5711 }
5712
5713 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5714 POSTING_READ(CDCLK_CTL);
5715
5716 /* inform PCU of the change */
5717 mutex_lock(&dev_priv->rps.hw_lock);
5718 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5719 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5720
5721 intel_update_cdclk(dev);
5d96d8af
DL		 5722}
5723
5724void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5725{
5726 /* disable DBUF power */
5727 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5728 POSTING_READ(DBUF_CTL);
5729
5730 udelay(10);
5731
5732 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5733 DRM_ERROR("DBuf power disable timeout\n");
5734
5735 /* disable DPLL0 */
5736 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5737 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5738 DRM_ERROR("Couldn't disable DPLL0\n");
5739
5740 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5741}
5742
5743void skl_init_cdclk(struct drm_i915_private *dev_priv)
5744{
5745 u32 val;
5746 unsigned int required_vco;
5747
5748 /* enable PCH reset handshake */
5749 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5750 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5751
5752 /* enable PG1 and Misc I/O */
5753 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5754
5755 /* DPLL0 already enabed !? */
5756 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5757 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5758 return;
5759 }
5760
5761 /* enable DPLL0 */
5762 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5763 skl_dpll0_enable(dev_priv, required_vco);
5764
5765 /* set CDCLK to the frequency the BIOS chose */
5766 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5767
5768 /* enable DBUF power */
5769 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5770 POSTING_READ(DBUF_CTL);
5771
5772 udelay(10);
5773
5774 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5775 DRM_ERROR("DBuf power enable timeout\n");
5776}
5777
dfcab17e 5778/* returns HPLL frequency in kHz */
f8bf63fd 5779static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5780{
586f49dc 5781 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5782
586f49dc 5783 /* Obtain SKU information */
a580516d 5784 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5785 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5786 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5787 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5788
dfcab17e 5789 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5790}
5791
5792/* Adjust CDclk dividers to allow high res or save power if possible */
5793static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5794{
5795 struct drm_i915_private *dev_priv = dev->dev_private;
5796 u32 val, cmd;
5797
164dfd28
VK		 5798 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5799 != dev_priv->cdclk_freq);
d60c4473 5800
dfcab17e 5801 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5802 cmd = 2;
dfcab17e 5803 else if (cdclk == 266667)
30a970c6
JB		 5804 cmd = 1;
5805 else
5806 cmd = 0;
5807
5808 mutex_lock(&dev_priv->rps.hw_lock);
5809 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5810 val &= ~DSPFREQGUAR_MASK;
5811 val |= (cmd << DSPFREQGUAR_SHIFT);
5812 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5813 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5814 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5815 50)) {
5816 DRM_ERROR("timed out waiting for CDclk change\n");
5817 }
5818 mutex_unlock(&dev_priv->rps.hw_lock);
5819
54433e91
VS		 5820 mutex_lock(&dev_priv->sb_lock);
5821
dfcab17e 5822 if (cdclk == 400000) {
6bcda4f0 5823 u32 divider;
30a970c6 5824
6bcda4f0 5825 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5826
30a970c6
JB		 5827 /* adjust cdclk divider */
5828 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5829 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5830 val |= divider;
5831 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5832
5833 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5834 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5835 50))
5836 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5837 }
5838
30a970c6
JB		 5839 /* adjust self-refresh exit latency value */
5840 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5841 val &= ~0x7f;
5842
5843 /*
5844 * For high bandwidth configs, we set a higher latency in the bunit
5845 * so that the core display fetch happens in time to avoid underruns.
5846 */
dfcab17e 5847 if (cdclk == 400000)
30a970c6
JB		 5848 val |= 4500 / 250; /* 4.5 usec */
5849 else
5850 val |= 3000 / 250; /* 3.0 usec */
5851 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5852
a580516d 5853 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5854
b6283055 5855 intel_update_cdclk(dev);
30a970c6
JB		 5856}
5857
383c5a6a
VS		 5858static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5859{
5860 struct drm_i915_private *dev_priv = dev->dev_private;
5861 u32 val, cmd;
5862
164dfd28
VK		 5863 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5864 != dev_priv->cdclk_freq);
383c5a6a
VS		 5865
5866 switch (cdclk) {
383c5a6a
VS		 5867 case 333333:
5868 case 320000:
383c5a6a 5869 case 266667:
383c5a6a 5870 case 200000:
383c5a6a
VS		 5871 break;
5872 default:
5f77eeb0 5873 MISSING_CASE(cdclk);
383c5a6a
VS		 5874 return;
5875 }
5876
9d0d3fda
VS		 5877 /*
5878 * Specs are full of misinformation, but testing on actual
5879 * hardware has shown that we just need to write the desired
5880 * CCK divider into the Punit register.
5881 */
5882 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5883
383c5a6a
VS		 5884 mutex_lock(&dev_priv->rps.hw_lock);
5885 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5886 val &= ~DSPFREQGUAR_MASK_CHV;
5887 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5888 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5889 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5890 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5891 50)) {
5892 DRM_ERROR("timed out waiting for CDclk change\n");
5893 }
5894 mutex_unlock(&dev_priv->rps.hw_lock);
5895
b6283055 5896 intel_update_cdclk(dev);
383c5a6a
VS		 5897}
5898
30a970c6
JB		 5899static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5900 int max_pixclk)
5901{
6bcda4f0 5902 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5903 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5904
30a970c6
JB		 5905 /*
5906 * Really only a few cases to deal with, as only 4 CDclks are supported:
5907 * 200MHz
5908 * 267MHz
29dc7ef3 5909 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5910 * 400MHz (VLV only)
5911 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5912 * of the lower bin and adjust if needed.
e37c67a1
VS		 5913 *
5914 * We seem to get an unstable or solid color picture at 200MHz.
5915 * Not sure what's wrong. For now use 200MHz only when all pipes
5916 * are off.
30a970c6 5917 */
6cca3195
VS		 5918 if (!IS_CHERRYVIEW(dev_priv) &&
5919 max_pixclk > freq_320*limit/100)
dfcab17e 5920 return 400000;
6cca3195 5921 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5922 return freq_320;
e37c67a1 5923 else if (max_pixclk > 0)
dfcab17e 5924 return 266667;
e37c67a1
VS		 5925 else
5926 return 200000;
30a970c6
JB		 5927}
5928
f8437dd1
VK		 5929static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5930 int max_pixclk)
5931{
5932 /*
5933 * FIXME:
5934 * - remove the guardband, it's not needed on BXT
5935 * - set 19.2MHz bypass frequency if there are no active pipes
5936 */
5937 if (max_pixclk > 576000*9/10)
5938 return 624000;
5939 else if (max_pixclk > 384000*9/10)
5940 return 576000;
5941 else if (max_pixclk > 288000*9/10)
5942 return 384000;
5943 else if (max_pixclk > 144000*9/10)
5944 return 288000;
5945 else
5946 return 144000;
5947}
5948
a821fc46
ACO		 5949/* Compute the max pixel clock for new configuration. Uses atomic state if
5950 * that's non-NULL, look at current state otherwise. */
5951static int intel_mode_max_pixclk(struct drm_device *dev,
5952 struct drm_atomic_state *state)
30a970c6 5953{
30a970c6 5954 struct intel_crtc *intel_crtc;
304603f4 5955 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5956 int max_pixclk = 0;
5957
d3fcc808 5958 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5959 if (state)
5960 crtc_state =
5961 intel_atomic_get_crtc_state(state, intel_crtc);
5962 else
5963 crtc_state = intel_crtc->config;
304603f4
ACO		 5964 if (IS_ERR(crtc_state))
5965 return PTR_ERR(crtc_state);
5966
5967 if (!crtc_state->base.enable)
5968 continue;
5969
5970 max_pixclk = max(max_pixclk,
5971 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5972 }
5973
5974 return max_pixclk;
5975}
5976
0a9ab303 5977static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5978{
304603f4 5979 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5980 struct drm_crtc *crtc;
5981 struct drm_crtc_state *crtc_state;
a821fc46 5982 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5983 int cdclk, i;
30a970c6 5984
304603f4
ACO		 5985 if (max_pixclk < 0)
5986 return max_pixclk;
30a970c6 5987
f8437dd1
VK		 5988 if (IS_VALLEYVIEW(dev_priv))
5989 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5990 else
5991 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5992
5993 if (cdclk == dev_priv->cdclk_freq)
304603f4 5994 return 0;
30a970c6 5995
0a9ab303
ACO		 5996 /* add all active pipes to the state */
5997 for_each_crtc(state->dev, crtc) {
5998 if (!crtc->state->enable)
5999 continue;
6000
6001 crtc_state = drm_atomic_get_crtc_state(state, crtc);
6002 if (IS_ERR(crtc_state))
6003 return PTR_ERR(crtc_state);
6004 }
6005
2f2d7aa1 6006 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 6007 for_each_crtc_in_state(state, crtc, crtc_state, i)
6008 if (crtc_state->enable)
6009 crtc_state->mode_changed = true;
304603f4
ACO		 6010
6011 return 0;
30a970c6
JB		 6012}
6013
1e69cd74
VS		 6014static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6015{
6016 unsigned int credits, default_credits;
6017
6018 if (IS_CHERRYVIEW(dev_priv))
6019 default_credits = PFI_CREDIT(12);
6020 else
6021 default_credits = PFI_CREDIT(8);
6022
164dfd28 6023 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 6024 /* CHV suggested value is 31 or 63 */
6025 if (IS_CHERRYVIEW(dev_priv))
6026 credits = PFI_CREDIT_31;
6027 else
6028 credits = PFI_CREDIT(15);
6029 } else {
6030 credits = default_credits;
6031 }
6032
6033 /*
6034 * WA - write default credits before re-programming
6035 * FIXME: should we also set the resend bit here?
6036 */
6037 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6038 default_credits);
6039
6040 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6041 credits | PFI_CREDIT_RESEND);
6042
6043 /*
6044 * FIXME is this guaranteed to clear
6045 * immediately or should we poll for it?
6046 */
6047 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6048}
6049
a821fc46 6050static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 6051{
a821fc46 6052 struct drm_device *dev = old_state->dev;
30a970c6 6053 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 6054 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 6055 int req_cdclk;
6056
a821fc46
ACO		 6057 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6058 * never fail. */
304603f4
ACO		 6059 if (WARN_ON(max_pixclk < 0))
6060 return;
30a970c6 6061
304603f4 6062 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6063
164dfd28 6064 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 6065 /*
6066 * FIXME: We can end up here with all power domains off, yet
6067 * with a CDCLK frequency other than the minimum. To account
6068 * for this take the PIPE-A power domain, which covers the HW
6069 * blocks needed for the following programming. This can be
6070 * removed once it's guaranteed that we get here either with
6071 * the minimum CDCLK set, or the required power domains
6072 * enabled.
6073 */
6074 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6075
383c5a6a
VS		 6076 if (IS_CHERRYVIEW(dev))
6077 cherryview_set_cdclk(dev, req_cdclk);
6078 else
6079 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6080
1e69cd74
VS		 6081 vlv_program_pfi_credits(dev_priv);
6082
738c05c0 6083 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6084 }
30a970c6
JB		 6085}
6086
89b667f8
JB		 6087static void valleyview_crtc_enable(struct drm_crtc *crtc)
6088{
6089 struct drm_device *dev = crtc->dev;
a72e4c9f 6090 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6092 struct intel_encoder *encoder;
6093 int pipe = intel_crtc->pipe;
23538ef1 6094 bool is_dsi;
89b667f8 6095
83d65738 6096 WARN_ON(!crtc->state->enable);
89b667f8
JB		 6097
6098 if (intel_crtc->active)
6099 return;
6100
409ee761 6101 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6102
1ae0d137
VS		 6103 if (!is_dsi) {
6104 if (IS_CHERRYVIEW(dev))
6e3c9717 6105 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6106 else
6e3c9717 6107 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6108 }
5b18e57c 6109
6e3c9717 6110 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6111 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6112
6113 intel_set_pipe_timings(intel_crtc);
6114
c14b0485
VS		 6115 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6116 struct drm_i915_private *dev_priv = dev->dev_private;
6117
6118 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6119 I915_WRITE(CHV_CANVAS(pipe), 0);
6120 }
6121
5b18e57c
DV		 6122 i9xx_set_pipeconf(intel_crtc);
6123
89b667f8 6124 intel_crtc->active = true;
89b667f8 6125
a72e4c9f 6126 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6127
89b667f8
JB		 6128 for_each_encoder_on_crtc(dev, crtc, encoder)
6129 if (encoder->pre_pll_enable)
6130 encoder->pre_pll_enable(encoder);
6131
9d556c99
CML		 6132 if (!is_dsi) {
6133 if (IS_CHERRYVIEW(dev))
6e3c9717 6134 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6135 else
6e3c9717 6136 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6137 }
89b667f8
JB		 6138
6139 for_each_encoder_on_crtc(dev, crtc, encoder)
6140 if (encoder->pre_enable)
6141 encoder->pre_enable(encoder);
6142
2dd24552
JB		 6143 i9xx_pfit_enable(intel_crtc);
6144
63cbb074
VS		 6145 intel_crtc_load_lut(crtc);
6146
f37fcc2a 6147 intel_update_watermarks(crtc);
e1fdc473 6148 intel_enable_pipe(intel_crtc);
be6a6f8e 6149
4b3a9526
VS		 6150 assert_vblank_disabled(crtc);
6151 drm_crtc_vblank_on(crtc);
6152
f9b61ff6
DV		 6153 for_each_encoder_on_crtc(dev, crtc, encoder)
6154 encoder->enable(encoder);
89b667f8
JB		 6155}
6156
f13c2ef3
DV		 6157static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6158{
6159 struct drm_device *dev = crtc->base.dev;
6160 struct drm_i915_private *dev_priv = dev->dev_private;
6161
6e3c9717
ACO		 6162 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6163 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6164}
6165
0b8765c6 6166static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6167{
6168 struct drm_device *dev = crtc->dev;
a72e4c9f 6169 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6171 struct intel_encoder *encoder;
79e53945 6172 int pipe = intel_crtc->pipe;
79e53945 6173
83d65738 6174 WARN_ON(!crtc->state->enable);
08a48469 6175
f7abfe8b
CW		 6176 if (intel_crtc->active)
6177 return;
6178
f13c2ef3
DV		 6179 i9xx_set_pll_dividers(intel_crtc);
6180
6e3c9717 6181 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6182 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6183
6184 intel_set_pipe_timings(intel_crtc);
6185
5b18e57c
DV		 6186 i9xx_set_pipeconf(intel_crtc);
6187
f7abfe8b 6188 intel_crtc->active = true;
6b383a7f 6189
4a3436e8 6190 if (!IS_GEN2(dev))
a72e4c9f 6191 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6192
9d6d9f19
MK		 6193 for_each_encoder_on_crtc(dev, crtc, encoder)
6194 if (encoder->pre_enable)
6195 encoder->pre_enable(encoder);
6196
f6736a1a
DV		 6197 i9xx_enable_pll(intel_crtc);
6198
2dd24552
JB		 6199 i9xx_pfit_enable(intel_crtc);
6200
63cbb074
VS		 6201 intel_crtc_load_lut(crtc);
6202
f37fcc2a 6203 intel_update_watermarks(crtc);
e1fdc473 6204 intel_enable_pipe(intel_crtc);
be6a6f8e 6205
4b3a9526
VS		 6206 assert_vblank_disabled(crtc);
6207 drm_crtc_vblank_on(crtc);
6208
f9b61ff6
DV		 6209 for_each_encoder_on_crtc(dev, crtc, encoder)
6210 encoder->enable(encoder);
0b8765c6 6211}
79e53945 6212
87476d63
DV		 6213static void i9xx_pfit_disable(struct intel_crtc *crtc)
6214{
6215 struct drm_device *dev = crtc->base.dev;
6216 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6217
6e3c9717 6218 if (!crtc->config->gmch_pfit.control)
328d8e82 6219 return;
87476d63 6220
328d8e82 6221 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6222
328d8e82
DV		 6223 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6224 I915_READ(PFIT_CONTROL));
6225 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6226}
6227
0b8765c6
JB		 6228static void i9xx_crtc_disable(struct drm_crtc *crtc)
6229{
6230 struct drm_device *dev = crtc->dev;
6231 struct drm_i915_private *dev_priv = dev->dev_private;
6232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6233 struct intel_encoder *encoder;
0b8765c6 6234 int pipe = intel_crtc->pipe;
ef9c3aee 6235
f7abfe8b
CW		 6236 if (!intel_crtc->active)
6237 return;
6238
6304cd91
VS		 6239 /*
6240 * On gen2 planes are double buffered but the pipe isn't, so we must
6241 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6242 * We also need to wait on all gmch platforms because of the
6243 * self-refresh mode constraint explained above.
6304cd91 6244 */
564ed191 6245 intel_wait_for_vblank(dev, pipe);
6304cd91 6246
4b3a9526
VS		 6247 for_each_encoder_on_crtc(dev, crtc, encoder)
6248 encoder->disable(encoder);
6249
f9b61ff6
DV		 6250 drm_crtc_vblank_off(crtc);
6251 assert_vblank_disabled(crtc);
6252
575f7ab7 6253 intel_disable_pipe(intel_crtc);
24a1f16d 6254
87476d63 6255 i9xx_pfit_disable(intel_crtc);
24a1f16d 6256
89b667f8
JB		 6257 for_each_encoder_on_crtc(dev, crtc, encoder)
6258 if (encoder->post_disable)
6259 encoder->post_disable(encoder);
6260
409ee761 6261 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6262 if (IS_CHERRYVIEW(dev))
6263 chv_disable_pll(dev_priv, pipe);
6264 else if (IS_VALLEYVIEW(dev))
6265 vlv_disable_pll(dev_priv, pipe);
6266 else
1c4e0274 6267 i9xx_disable_pll(intel_crtc);
076ed3b2 6268 }
0b8765c6 6269
4a3436e8 6270 if (!IS_GEN2(dev))
a72e4c9f 6271 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6272
f7abfe8b 6273 intel_crtc->active = false;
46ba614c 6274 intel_update_watermarks(crtc);
f37fcc2a 6275
efa9624e 6276 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6277 intel_fbc_update(dev);
efa9624e 6278 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6279}
6280
b04c5bd6
BF		 6281/* Master function to enable/disable CRTC and corresponding power wells */
6282void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6283{
6284 struct drm_device *dev = crtc->dev;
6285 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6287 enum intel_display_power_domain domain;
6288 unsigned long domains;
976f8a20 6289
0e572fe7
DV		 6290 if (enable) {
6291 if (!intel_crtc->active) {
e1e9fb84
DV		 6292 domains = get_crtc_power_domains(crtc);
6293 for_each_power_domain(domain, domains)
6294 intel_display_power_get(dev_priv, domain);
6295 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6296
6297 dev_priv->display.crtc_enable(crtc);
ce22dba9 6298 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6299 }
6300 } else {
6301 if (intel_crtc->active) {
ce22dba9 6302 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6303 dev_priv->display.crtc_disable(crtc);
6304
e1e9fb84
DV		 6305 domains = intel_crtc->enabled_power_domains;
6306 for_each_power_domain(domain, domains)
6307 intel_display_power_put(dev_priv, domain);
6308 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6309 }
6310 }
b04c5bd6
BF		 6311}
6312
6313/**
6314 * Sets the power management mode of the pipe and plane.
6315 */
6316void intel_crtc_update_dpms(struct drm_crtc *crtc)
6317{
6318 struct drm_device *dev = crtc->dev;
6319 struct intel_encoder *intel_encoder;
6320 bool enable = false;
6321
6322 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6323 enable |= intel_encoder->connectors_active;
6324
6325 intel_crtc_control(crtc, enable);
0f63cca2
ACO		 6326
6327 crtc->state->active = enable;
976f8a20
DV		 6328}
6329
ea5b213a 6330void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6331{
4ef69c7a 6332 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6333
ea5b213a
CW		 6334 drm_encoder_cleanup(encoder);
6335 kfree(intel_encoder);
7e7d76c3
JB		 6336}
6337
9237329d 6338/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6339 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6340 * state of the entire output pipe. */
9237329d 6341static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6342{
5ab432ef
DV		 6343 if (mode == DRM_MODE_DPMS_ON) {
6344 encoder->connectors_active = true;
6345
b2cabb0e 6346 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6347 } else {
6348 encoder->connectors_active = false;
6349
b2cabb0e 6350 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6351 }
79e53945
JB		 6352}
6353
0a91ca29
DV		 6354/* Cross check the actual hw state with our own modeset state tracking (and it's
6355 * internal consistency). */
b980514c 6356static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6357{
0a91ca29
DV		 6358 if (connector->get_hw_state(connector)) {
6359 struct intel_encoder *encoder = connector->encoder;
6360 struct drm_crtc *crtc;
6361 bool encoder_enabled;
6362 enum pipe pipe;
6363
6364 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6365 connector->base.base.id,
c23cc417 6366 connector->base.name);
0a91ca29 6367
0e32b39c
DA		 6368 /* there is no real hw state for MST connectors */
6369 if (connector->mst_port)
6370 return;
6371
e2c719b7 6372 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6373 "wrong connector dpms state\n");
e2c719b7 6374 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6375 "active connector not linked to encoder\n");
0a91ca29 6376
36cd7444 6377 if (encoder) {
e2c719b7 6378 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6379 "encoder->connectors_active not set\n");
6380
6381 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6382 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6383 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6384 return;
0a91ca29 6385
36cd7444 6386 crtc = encoder->base.crtc;
0a91ca29 6387
83d65738
MR		 6388 I915_STATE_WARN(!crtc->state->enable,
6389 "crtc not enabled\n");
e2c719b7
RC		 6390 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6391 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6392 "encoder active on the wrong pipe\n");
6393 }
0a91ca29 6394 }
79e53945
JB		 6395}
6396
08d9bc92
ACO		 6397int intel_connector_init(struct intel_connector *connector)
6398{
6399 struct drm_connector_state *connector_state;
6400
6401 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6402 if (!connector_state)
6403 return -ENOMEM;
6404
6405 connector->base.state = connector_state;
6406 return 0;
6407}
6408
6409struct intel_connector *intel_connector_alloc(void)
6410{
6411 struct intel_connector *connector;
6412
6413 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6414 if (!connector)
6415 return NULL;
6416
6417 if (intel_connector_init(connector) < 0) {
6418 kfree(connector);
6419 return NULL;
6420 }
6421
6422 return connector;
6423}
6424
5ab432ef
DV		 6425/* Even simpler default implementation, if there's really no special case to
6426 * consider. */
6427void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6428{
5ab432ef
DV		 6429 /* All the simple cases only support two dpms states. */
6430 if (mode != DRM_MODE_DPMS_ON)
6431 mode = DRM_MODE_DPMS_OFF;
d4270e57 6432
5ab432ef
DV		 6433 if (mode == connector->dpms)
6434 return;
6435
6436 connector->dpms = mode;
6437
6438 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6439 if (connector->encoder)
6440 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6441
b980514c 6442 intel_modeset_check_state(connector->dev);
79e53945
JB		 6443}
6444
f0947c37
DV		 6445/* Simple connector->get_hw_state implementation for encoders that support only
6446 * one connector and no cloning and hence the encoder state determines the state
6447 * of the connector. */
6448bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6449{
24929352 6450 enum pipe pipe = 0;
f0947c37 6451 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6452
f0947c37 6453 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6454}
6455
6d293983 6456static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6457{
6d293983
ACO		 6458 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6459 return crtc_state->fdi_lanes;
d272ddfa
VS		 6460
6461 return 0;
6462}
6463
6d293983 6464static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6465 struct intel_crtc_state *pipe_config)
1857e1da 6466{
6d293983
ACO		 6467 struct drm_atomic_state *state = pipe_config->base.state;
6468 struct intel_crtc *other_crtc;
6469 struct intel_crtc_state *other_crtc_state;
6470
1857e1da
DV		 6471 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6472 pipe_name(pipe), pipe_config->fdi_lanes);
6473 if (pipe_config->fdi_lanes > 4) {
6474 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6475 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6476 return -EINVAL;
1857e1da
DV		 6477 }
6478
bafb6553 6479 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6480 if (pipe_config->fdi_lanes > 2) {
6481 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6482 pipe_config->fdi_lanes);
6d293983 6483 return -EINVAL;
1857e1da 6484 } else {
6d293983 6485 return 0;
1857e1da
DV		 6486 }
6487 }
6488
6489 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6490 return 0;
1857e1da
DV		 6491
6492 /* Ivybridge 3 pipe is really complicated */
6493 switch (pipe) {
6494 case PIPE_A:
6d293983 6495 return 0;
1857e1da 6496 case PIPE_B:
6d293983
ACO		 6497 if (pipe_config->fdi_lanes <= 2)
6498 return 0;
6499
6500 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6501 other_crtc_state =
6502 intel_atomic_get_crtc_state(state, other_crtc);
6503 if (IS_ERR(other_crtc_state))
6504 return PTR_ERR(other_crtc_state);
6505
6506 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6507 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6508 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6509 return -EINVAL;
1857e1da 6510 }
6d293983 6511 return 0;
1857e1da 6512 case PIPE_C:
251cc67c
VS		 6513 if (pipe_config->fdi_lanes > 2) {
6514 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6515 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6516 return -EINVAL;
251cc67c 6517 }
6d293983
ACO		 6518
6519 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6520 other_crtc_state =
6521 intel_atomic_get_crtc_state(state, other_crtc);
6522 if (IS_ERR(other_crtc_state))
6523 return PTR_ERR(other_crtc_state);
6524
6525 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6526 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6527 return -EINVAL;
1857e1da 6528 }
6d293983 6529 return 0;
1857e1da
DV		 6530 default:
6531 BUG();
6532 }
6533}
6534
e29c22c0
DV		 6535#define RETRY 1
6536static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6537 struct intel_crtc_state *pipe_config)
877d48d5 6538{
1857e1da 6539 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6540 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6541 int lane, link_bw, fdi_dotclock, ret;
6542 bool needs_recompute = false;
877d48d5 6543
e29c22c0 6544retry:
877d48d5
DV		 6545 /* FDI is a binary signal running at ~2.7GHz, encoding
6546 * each output octet as 10 bits. The actual frequency
6547 * is stored as a divider into a 100MHz clock, and the
6548 * mode pixel clock is stored in units of 1KHz.
6549 * Hence the bw of each lane in terms of the mode signal
6550 * is:
6551 */
6552 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6553
241bfc38 6554 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6555
2bd89a07 6556 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6557 pipe_config->pipe_bpp);
6558
6559 pipe_config->fdi_lanes = lane;
6560
2bd89a07 6561 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6562 link_bw, &pipe_config->fdi_m_n);
1857e1da 6563
6d293983
ACO		 6564 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6565 intel_crtc->pipe, pipe_config);
6566 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6567 pipe_config->pipe_bpp -= 2*3;
6568 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6569 pipe_config->pipe_bpp);
6570 needs_recompute = true;
6571 pipe_config->bw_constrained = true;
6572
6573 goto retry;
6574 }
6575
6576 if (needs_recompute)
6577 return RETRY;
6578
6d293983 6579 return ret;
877d48d5
DV		 6580}
6581
8cfb3407
VS		 6582static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6583 struct intel_crtc_state *pipe_config)
6584{
6585 if (pipe_config->pipe_bpp > 24)
6586 return false;
6587
6588 /* HSW can handle pixel rate up to cdclk? */
6589 if (IS_HASWELL(dev_priv->dev))
6590 return true;
6591
6592 /*
b432e5cf
VS		 6593 * We compare against max which means we must take
6594 * the increased cdclk requirement into account when
6595 * calculating the new cdclk.
6596 *
6597 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6598 */
6599 return ilk_pipe_pixel_rate(pipe_config) <=
6600 dev_priv->max_cdclk_freq * 95 / 100;
6601}
6602
42db64ef 6603static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6604 struct intel_crtc_state *pipe_config)
42db64ef 6605{
8cfb3407
VS		 6606 struct drm_device *dev = crtc->base.dev;
6607 struct drm_i915_private *dev_priv = dev->dev_private;
6608
d330a953 6609 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6610 hsw_crtc_supports_ips(crtc) &&
6611 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6612}
6613
a43f6e0f 6614static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6615 struct intel_crtc_state *pipe_config)
79e53945 6616{
a43f6e0f 6617 struct drm_device *dev = crtc->base.dev;
8bd31e67 6618 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6619 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6620 int ret;
89749350 6621
ad3a4479 6622 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6623 if (INTEL_INFO(dev)->gen < 4) {
44913155 6624 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6625
6626 /*
6627 * Enable pixel doubling when the dot clock
6628 * is > 90% of the (display) core speed.
6629 *
b397c96b
VS		 6630 * GDG double wide on either pipe,
6631 * otherwise pipe A only.
cf532bb2 6632 */
b397c96b 6633 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6634 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6635 clock_limit *= 2;
cf532bb2 6636 pipe_config->double_wide = true;
ad3a4479
VS		 6637 }
6638
241bfc38 6639 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6640 return -EINVAL;
2c07245f 6641 }
89749350 6642
1d1d0e27
VS		 6643 /*
6644 * Pipe horizontal size must be even in:
6645 * - DVO ganged mode
6646 * - LVDS dual channel mode
6647 * - Double wide pipe
6648 */
a93e255f 6649 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6650 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6651 pipe_config->pipe_src_w &= ~1;
6652
8693a824
DL		 6653 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6654 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6655 */
6656 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6657 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6658 return -EINVAL;
44f46b42 6659
f5adf94e 6660 if (HAS_IPS(dev))
a43f6e0f
DV		 6661 hsw_compute_ips_config(crtc, pipe_config);
6662
877d48d5 6663 if (pipe_config->has_pch_encoder)
a43f6e0f 6664 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6665
d03c93d4
CK		 6666 /* FIXME: remove below call once atomic mode set is place and all crtc
6667 * related checks called from atomic_crtc_check function */
6668 ret = 0;
6669 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6670 crtc, pipe_config->base.state);
6671 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6672
6673 return ret;
79e53945
JB		 6674}
6675
1652d19e
VS		 6676static int skylake_get_display_clock_speed(struct drm_device *dev)
6677{
6678 struct drm_i915_private *dev_priv = to_i915(dev);
6679 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6680 uint32_t cdctl = I915_READ(CDCLK_CTL);
6681 uint32_t linkrate;
6682
414355a7 6683 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6684 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6685
6686 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6687 return 540000;
6688
6689 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6690 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6691
71cd8423
DL		 6692 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6693 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6694 /* vco 8640 */
6695 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6696 case CDCLK_FREQ_450_432:
6697 return 432000;
6698 case CDCLK_FREQ_337_308:
6699 return 308570;
6700 case CDCLK_FREQ_675_617:
6701 return 617140;
6702 default:
6703 WARN(1, "Unknown cd freq selection\n");
6704 }
6705 } else {
6706 /* vco 8100 */
6707 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6708 case CDCLK_FREQ_450_432:
6709 return 450000;
6710 case CDCLK_FREQ_337_308:
6711 return 337500;
6712 case CDCLK_FREQ_675_617:
6713 return 675000;
6714 default:
6715 WARN(1, "Unknown cd freq selection\n");
6716 }
6717 }
6718
6719 /* error case, do as if DPLL0 isn't enabled */
6720 return 24000;
6721}
6722
6723static int broadwell_get_display_clock_speed(struct drm_device *dev)
6724{
6725 struct drm_i915_private *dev_priv = dev->dev_private;
6726 uint32_t lcpll = I915_READ(LCPLL_CTL);
6727 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6728
6729 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6730 return 800000;
6731 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6732 return 450000;
6733 else if (freq == LCPLL_CLK_FREQ_450)
6734 return 450000;
6735 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6736 return 540000;
6737 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6738 return 337500;
6739 else
6740 return 675000;
6741}
6742
6743static int haswell_get_display_clock_speed(struct drm_device *dev)
6744{
6745 struct drm_i915_private *dev_priv = dev->dev_private;
6746 uint32_t lcpll = I915_READ(LCPLL_CTL);
6747 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6748
6749 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6750 return 800000;
6751 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6752 return 450000;
6753 else if (freq == LCPLL_CLK_FREQ_450)
6754 return 450000;
6755 else if (IS_HSW_ULT(dev))
6756 return 337500;
6757 else
6758 return 540000;
79e53945
JB		 6759}
6760
25eb05fc
JB		 6761static int valleyview_get_display_clock_speed(struct drm_device *dev)
6762{
d197b7d3 6763 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6764 u32 val;
6765 int divider;
6766
6bcda4f0
VS		 6767 if (dev_priv->hpll_freq == 0)
6768 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6769
a580516d 6770 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6771 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6772 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6773
6774 divider = val & DISPLAY_FREQUENCY_VALUES;
6775
7d007f40
VS		 6776 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6777 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6778 "cdclk change in progress\n");
6779
6bcda4f0 6780 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6781}
6782
b37a6434
VS		 6783static int ilk_get_display_clock_speed(struct drm_device *dev)
6784{
6785 return 450000;
6786}
6787
e70236a8
JB		 6788static int i945_get_display_clock_speed(struct drm_device *dev)
6789{
6790 return 400000;
6791}
79e53945 6792
e70236a8 6793static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6794{
e907f170 6795 return 333333;
e70236a8 6796}
79e53945 6797
e70236a8
JB		 6798static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6799{
6800 return 200000;
6801}
79e53945 6802
257a7ffc
DV		 6803static int pnv_get_display_clock_speed(struct drm_device *dev)
6804{
6805 u16 gcfgc = 0;
6806
6807 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6808
6809 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6810 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6811 return 266667;
257a7ffc 6812 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6813 return 333333;
257a7ffc 6814 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6815 return 444444;
257a7ffc
DV		 6816 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6817 return 200000;
6818 default:
6819 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6820 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6821 return 133333;
257a7ffc 6822 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6823 return 166667;
257a7ffc
DV		 6824 }
6825}
6826
e70236a8
JB		 6827static int i915gm_get_display_clock_speed(struct drm_device *dev)
6828{
6829 u16 gcfgc = 0;
79e53945 6830
e70236a8
JB		 6831 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6832
6833 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6834 return 133333;
e70236a8
JB		 6835 else {
6836 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6837 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6838 return 333333;
e70236a8
JB		 6839 default:
6840 case GC_DISPLAY_CLOCK_190_200_MHZ:
6841 return 190000;
79e53945 6842 }
e70236a8
JB		 6843 }
6844}
6845
6846static int i865_get_display_clock_speed(struct drm_device *dev)
6847{
e907f170 6848 return 266667;
e70236a8
JB		 6849}
6850
1b1d2716 6851static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6852{
6853 u16 hpllcc = 0;
1b1d2716 6854
65cd2b3f
VS		 6855 /*
6856 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6857 * encoding is different :(
6858 * FIXME is this the right way to detect 852GM/852GMV?
6859 */
6860 if (dev->pdev->revision == 0x1)
6861 return 133333;
6862
1b1d2716
VS		 6863 pci_bus_read_config_word(dev->pdev->bus,
6864 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6865
e70236a8
JB		 6866 /* Assume that the hardware is in the high speed state. This
6867 * should be the default.
6868 */
6869 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6870 case GC_CLOCK_133_200:
1b1d2716 6871 case GC_CLOCK_133_200_2:
e70236a8
JB		 6872 case GC_CLOCK_100_200:
6873 return 200000;
6874 case GC_CLOCK_166_250:
6875 return 250000;
6876 case GC_CLOCK_100_133:
e907f170 6877 return 133333;
1b1d2716
VS		 6878 case GC_CLOCK_133_266:
6879 case GC_CLOCK_133_266_2:
6880 case GC_CLOCK_166_266:
6881 return 266667;
e70236a8 6882 }
79e53945 6883
e70236a8
JB		 6884 /* Shouldn't happen */
6885 return 0;
6886}
79e53945 6887
e70236a8
JB		 6888static int i830_get_display_clock_speed(struct drm_device *dev)
6889{
e907f170 6890 return 133333;
79e53945
JB		 6891}
6892
34edce2f
VS		 6893static unsigned int intel_hpll_vco(struct drm_device *dev)
6894{
6895 struct drm_i915_private *dev_priv = dev->dev_private;
6896 static const unsigned int blb_vco[8] = {
6897 [0] = 3200000,
6898 [1] = 4000000,
6899 [2] = 5333333,
6900 [3] = 4800000,
6901 [4] = 6400000,
6902 };
6903 static const unsigned int pnv_vco[8] = {
6904 [0] = 3200000,
6905 [1] = 4000000,
6906 [2] = 5333333,
6907 [3] = 4800000,
6908 [4] = 2666667,
6909 };
6910 static const unsigned int cl_vco[8] = {
6911 [0] = 3200000,
6912 [1] = 4000000,
6913 [2] = 5333333,
6914 [3] = 6400000,
6915 [4] = 3333333,
6916 [5] = 3566667,
6917 [6] = 4266667,
6918 };
6919 static const unsigned int elk_vco[8] = {
6920 [0] = 3200000,
6921 [1] = 4000000,
6922 [2] = 5333333,
6923 [3] = 4800000,
6924 };
6925 static const unsigned int ctg_vco[8] = {
6926 [0] = 3200000,
6927 [1] = 4000000,
6928 [2] = 5333333,
6929 [3] = 6400000,
6930 [4] = 2666667,
6931 [5] = 4266667,
6932 };
6933 const unsigned int *vco_table;
6934 unsigned int vco;
6935 uint8_t tmp = 0;
6936
6937 /* FIXME other chipsets? */
6938 if (IS_GM45(dev))
6939 vco_table = ctg_vco;
6940 else if (IS_G4X(dev))
6941 vco_table = elk_vco;
6942 else if (IS_CRESTLINE(dev))
6943 vco_table = cl_vco;
6944 else if (IS_PINEVIEW(dev))
6945 vco_table = pnv_vco;
6946 else if (IS_G33(dev))
6947 vco_table = blb_vco;
6948 else
6949 return 0;
6950
6951 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6952
6953 vco = vco_table[tmp & 0x7];
6954 if (vco == 0)
6955 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6956 else
6957 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6958
6959 return vco;
6960}
6961
6962static int gm45_get_display_clock_speed(struct drm_device *dev)
6963{
6964 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6965 uint16_t tmp = 0;
6966
6967 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6968
6969 cdclk_sel = (tmp >> 12) & 0x1;
6970
6971 switch (vco) {
6972 case 2666667:
6973 case 4000000:
6974 case 5333333:
6975 return cdclk_sel ? 333333 : 222222;
6976 case 3200000:
6977 return cdclk_sel ? 320000 : 228571;
6978 default:
6979 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6980 return 222222;
6981 }
6982}
6983
6984static int i965gm_get_display_clock_speed(struct drm_device *dev)
6985{
6986 static const uint8_t div_3200[] = { 16, 10, 8 };
6987 static const uint8_t div_4000[] = { 20, 12, 10 };
6988 static const uint8_t div_5333[] = { 24, 16, 14 };
6989 const uint8_t *div_table;
6990 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6991 uint16_t tmp = 0;
6992
6993 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6994
6995 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6996
6997 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6998 goto fail;
6999
7000 switch (vco) {
7001 case 3200000:
7002 div_table = div_3200;
7003 break;
7004 case 4000000:
7005 div_table = div_4000;
7006 break;
7007 case 5333333:
7008 div_table = div_5333;
7009 break;
7010 default:
7011 goto fail;
7012 }
7013
7014 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7015
7016 fail:
7017 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7018 return 200000;
7019}
7020
7021static int g33_get_display_clock_speed(struct drm_device *dev)
7022{
7023 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7024 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7025 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7026 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7027 const uint8_t *div_table;
7028 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7029 uint16_t tmp = 0;
7030
7031 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7032
7033 cdclk_sel = (tmp >> 4) & 0x7;
7034
7035 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7036 goto fail;
7037
7038 switch (vco) {
7039 case 3200000:
7040 div_table = div_3200;
7041 break;
7042 case 4000000:
7043 div_table = div_4000;
7044 break;
7045 case 4800000:
7046 div_table = div_4800;
7047 break;
7048 case 5333333:
7049 div_table = div_5333;
7050 break;
7051 default:
7052 goto fail;
7053 }
7054
7055 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7056
7057 fail:
7058 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7059 return 190476;
7060}
7061
2c07245f 7062static void
a65851af 7063intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7064{
a65851af
VS		 7065 while (*num > DATA_LINK_M_N_MASK ||
7066 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7067 *num >>= 1;
7068 *den >>= 1;
7069 }
7070}
7071
a65851af
VS		 7072static void compute_m_n(unsigned int m, unsigned int n,
7073 uint32_t *ret_m, uint32_t *ret_n)
7074{
7075 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7076 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7077 intel_reduce_m_n_ratio(ret_m, ret_n);
7078}
7079
e69d0bc1
DV		 7080void
7081intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7082 int pixel_clock, int link_clock,
7083 struct intel_link_m_n *m_n)
2c07245f 7084{
e69d0bc1 7085 m_n->tu = 64;
a65851af
VS		 7086
7087 compute_m_n(bits_per_pixel * pixel_clock,
7088 link_clock * nlanes * 8,
7089 &m_n->gmch_m, &m_n->gmch_n);
7090
7091 compute_m_n(pixel_clock, link_clock,
7092 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7093}
7094
a7615030
CW		 7095static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7096{
d330a953
JN		 7097 if (i915.panel_use_ssc >= 0)
7098 return i915.panel_use_ssc != 0;
41aa3448 7099 return dev_priv->vbt.lvds_use_ssc
435793df 7100 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7101}
7102
a93e255f
ACO		 7103static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7104 int num_connectors)
c65d77d8 7105{
a93e255f 7106 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7107 struct drm_i915_private *dev_priv = dev->dev_private;
7108 int refclk;
7109
a93e255f
ACO		 7110 WARN_ON(!crtc_state->base.state);
7111
5ab7b0b7 7112 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7113 refclk = 100000;
a93e255f 7114 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7115 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7116 refclk = dev_priv->vbt.lvds_ssc_freq;
7117 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7118 } else if (!IS_GEN2(dev)) {
7119 refclk = 96000;
7120 } else {
7121 refclk = 48000;
7122 }
7123
7124 return refclk;
7125}
7126
7429e9d4 7127static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7128{
7df00d7a 7129 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7130}
f47709a9 7131
7429e9d4
DV		 7132static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7133{
7134 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7135}
7136
f47709a9 7137static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7138 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7139 intel_clock_t *reduced_clock)
7140{
f47709a9 7141 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7142 u32 fp, fp2 = 0;
7143
7144 if (IS_PINEVIEW(dev)) {
190f68c5 7145 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7146 if (reduced_clock)
7429e9d4 7147 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7148 } else {
190f68c5 7149 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7150 if (reduced_clock)
7429e9d4 7151 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7152 }
7153
190f68c5 7154 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7155
f47709a9 7156 crtc->lowfreq_avail = false;
a93e255f 7157 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7158 reduced_clock) {
190f68c5 7159 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7160 crtc->lowfreq_avail = true;
a7516a05 7161 } else {
190f68c5 7162 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7163 }
7164}
7165
5e69f97f
CML		 7166static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7167 pipe)
89b667f8
JB		 7168{
7169 u32 reg_val;
7170
7171 /*
7172 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7173 * and set it to a reasonable value instead.
7174 */
ab3c759a 7175 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7176 reg_val &= 0xffffff00;
7177 reg_val |= 0x00000030;
ab3c759a 7178 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7179
ab3c759a 7180 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7181 reg_val &= 0x8cffffff;
7182 reg_val = 0x8c000000;
ab3c759a 7183 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7184
ab3c759a 7185 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7186 reg_val &= 0xffffff00;
ab3c759a 7187 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7188
ab3c759a 7189 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7190 reg_val &= 0x00ffffff;
7191 reg_val |= 0xb0000000;
ab3c759a 7192 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7193}
7194
b551842d
DV		 7195static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7196 struct intel_link_m_n *m_n)
7197{
7198 struct drm_device *dev = crtc->base.dev;
7199 struct drm_i915_private *dev_priv = dev->dev_private;
7200 int pipe = crtc->pipe;
7201
e3b95f1e
DV		 7202 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7203 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7204 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7205 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7206}
7207
7208static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7209 struct intel_link_m_n *m_n,
7210 struct intel_link_m_n *m2_n2)
b551842d
DV		 7211{
7212 struct drm_device *dev = crtc->base.dev;
7213 struct drm_i915_private *dev_priv = dev->dev_private;
7214 int pipe = crtc->pipe;
6e3c9717 7215 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7216
7217 if (INTEL_INFO(dev)->gen >= 5) {
7218 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7219 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7220 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7221 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7222 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7223 * for gen < 8) and if DRRS is supported (to make sure the
7224 * registers are not unnecessarily accessed).
7225 */
44395bfe 7226 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7227 crtc->config->has_drrs) {
f769cd24
VK		 7228 I915_WRITE(PIPE_DATA_M2(transcoder),
7229 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7230 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7231 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7232 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7233 }
b551842d 7234 } else {
e3b95f1e
DV		 7235 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7236 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7237 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7238 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7239 }
7240}
7241
fe3cd48d 7242void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7243{
fe3cd48d
R		 7244 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7245
7246 if (m_n == M1_N1) {
7247 dp_m_n = &crtc->config->dp_m_n;
7248 dp_m2_n2 = &crtc->config->dp_m2_n2;
7249 } else if (m_n == M2_N2) {
7250
7251 /*
7252 * M2_N2 registers are not supported. Hence m2_n2 divider value
7253 * needs to be programmed into M1_N1.
7254 */
7255 dp_m_n = &crtc->config->dp_m2_n2;
7256 } else {
7257 DRM_ERROR("Unsupported divider value\n");
7258 return;
7259 }
7260
6e3c9717
ACO		 7261 if (crtc->config->has_pch_encoder)
7262 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7263 else
fe3cd48d 7264 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7265}
7266
d288f65f 7267static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7268 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7269{
7270 u32 dpll, dpll_md;
7271
7272 /*
7273 * Enable DPIO clock input. We should never disable the reference
7274 * clock for pipe B, since VGA hotplug / manual detection depends
7275 * on it.
7276 */
7277 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7278 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7279 /* We should never disable this, set it here for state tracking */
7280 if (crtc->pipe == PIPE_B)
7281 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7282 dpll |= DPLL_VCO_ENABLE;
d288f65f 7283 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7284
d288f65f 7285 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7286 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7287 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7288}
7289
d288f65f 7290static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7291 const struct intel_crtc_state *pipe_config)
a0c4da24 7292{
f47709a9 7293 struct drm_device *dev = crtc->base.dev;
a0c4da24 7294 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7295 int pipe = crtc->pipe;
bdd4b6a6 7296 u32 mdiv;
a0c4da24 7297 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7298 u32 coreclk, reg_val;
a0c4da24 7299
a580516d 7300 mutex_lock(&dev_priv->sb_lock);
09153000 7301
d288f65f
VS		 7302 bestn = pipe_config->dpll.n;
7303 bestm1 = pipe_config->dpll.m1;
7304 bestm2 = pipe_config->dpll.m2;
7305 bestp1 = pipe_config->dpll.p1;
7306 bestp2 = pipe_config->dpll.p2;
a0c4da24 7307
89b667f8
JB		 7308 /* See eDP HDMI DPIO driver vbios notes doc */
7309
7310 /* PLL B needs special handling */
bdd4b6a6 7311 if (pipe == PIPE_B)
5e69f97f 7312 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7313
7314 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7315 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7316
7317 /* Disable target IRef on PLL */
ab3c759a 7318 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7319 reg_val &= 0x00ffffff;
ab3c759a 7320 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7321
7322 /* Disable fast lock */
ab3c759a 7323 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7324
7325 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7326 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7327 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7328 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7329 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7330
7331 /*
7332 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7333 * but we don't support that).
7334 * Note: don't use the DAC post divider as it seems unstable.
7335 */
7336 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7337 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7338
a0c4da24 7339 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7340 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7341
89b667f8 7342 /* Set HBR and RBR LPF coefficients */
d288f65f 7343 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7344 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7345 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7346 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7347 0x009f0003);
89b667f8 7348 else
ab3c759a 7349 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7350 0x00d0000f);
7351
681a8504 7352 if (pipe_config->has_dp_encoder) {
89b667f8 7353 /* Use SSC source */
bdd4b6a6 7354 if (pipe == PIPE_A)
ab3c759a 7355 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7356 0x0df40000);
7357 else
ab3c759a 7358 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7359 0x0df70000);
7360 } else { /* HDMI or VGA */
7361 /* Use bend source */
bdd4b6a6 7362 if (pipe == PIPE_A)
ab3c759a 7363 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7364 0x0df70000);
7365 else
ab3c759a 7366 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7367 0x0df40000);
7368 }
a0c4da24 7369
ab3c759a 7370 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7371 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7372 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7373 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7374 coreclk |= 0x01000000;
ab3c759a 7375 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7376
ab3c759a 7377 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7378 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7379}
7380
d288f65f 7381static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7382 struct intel_crtc_state *pipe_config)
1ae0d137 7383{
d288f65f 7384 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7385 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7386 DPLL_VCO_ENABLE;
7387 if (crtc->pipe != PIPE_A)
d288f65f 7388 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7389
d288f65f
VS		 7390 pipe_config->dpll_hw_state.dpll_md =
7391 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7392}
7393
d288f65f 7394static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7395 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7396{
7397 struct drm_device *dev = crtc->base.dev;
7398 struct drm_i915_private *dev_priv = dev->dev_private;
7399 int pipe = crtc->pipe;
7400 int dpll_reg = DPLL(crtc->pipe);
7401 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7402 u32 loopfilter, tribuf_calcntr;
9d556c99 7403 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7404 u32 dpio_val;
9cbe40c1 7405 int vco;
9d556c99 7406
d288f65f
VS		 7407 bestn = pipe_config->dpll.n;
7408 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7409 bestm1 = pipe_config->dpll.m1;
7410 bestm2 = pipe_config->dpll.m2 >> 22;
7411 bestp1 = pipe_config->dpll.p1;
7412 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7413 vco = pipe_config->dpll.vco;
a945ce7e 7414 dpio_val = 0;
9cbe40c1 7415 loopfilter = 0;
9d556c99
CML		 7416
7417 /*
7418 * Enable Refclk and SSC
7419 */
a11b0703 7420 I915_WRITE(dpll_reg,
d288f65f 7421 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7422
a580516d 7423 mutex_lock(&dev_priv->sb_lock);
9d556c99 7424
9d556c99
CML		 7425 /* p1 and p2 divider */
7426 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7427 5 << DPIO_CHV_S1_DIV_SHIFT |
7428 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7429 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7430 1 << DPIO_CHV_K_DIV_SHIFT);
7431
7432 /* Feedback post-divider - m2 */
7433 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7434
7435 /* Feedback refclk divider - n and m1 */
7436 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7437 DPIO_CHV_M1_DIV_BY_2 |
7438 1 << DPIO_CHV_N_DIV_SHIFT);
7439
7440 /* M2 fraction division */
a945ce7e
VP		 7441 if (bestm2_frac)
7442 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7443
7444 /* M2 fraction division enable */
a945ce7e
VP		 7445 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7446 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7447 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7448 if (bestm2_frac)
7449 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7450 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7451
de3a0fde
VP		 7452 /* Program digital lock detect threshold */
7453 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7454 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7455 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7456 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7457 if (!bestm2_frac)
7458 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7459 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7460
9d556c99 7461 /* Loop filter */
9cbe40c1
VP		 7462 if (vco == 5400000) {
7463 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7464 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7465 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7466 tribuf_calcntr = 0x9;
7467 } else if (vco <= 6200000) {
7468 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7469 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7470 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7471 tribuf_calcntr = 0x9;
7472 } else if (vco <= 6480000) {
7473 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7474 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7475 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7476 tribuf_calcntr = 0x8;
7477 } else {
7478 /* Not supported. Apply the same limits as in the max case */
7479 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7480 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7481 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7482 tribuf_calcntr = 0;
7483 }
9d556c99
CML		 7484 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7485
968040b2 7486 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7487 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7488 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7489 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7490
9d556c99
CML		 7491 /* AFC Recal */
7492 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7493 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7494 DPIO_AFC_RECAL);
7495
a580516d 7496 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7497}
7498
d288f65f
VS		 7499/**
7500 * vlv_force_pll_on - forcibly enable just the PLL
7501 * @dev_priv: i915 private structure
7502 * @pipe: pipe PLL to enable
7503 * @dpll: PLL configuration
7504 *
7505 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7506 * in cases where we need the PLL enabled even when @pipe is not going to
7507 * be enabled.
7508 */
7509void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7510 const struct dpll *dpll)
7511{
7512 struct intel_crtc *crtc =
7513 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7514 struct intel_crtc_state pipe_config = {
a93e255f 7515 .base.crtc = &crtc->base,
d288f65f
VS		 7516 .pixel_multiplier = 1,
7517 .dpll = *dpll,
7518 };
7519
7520 if (IS_CHERRYVIEW(dev)) {
7521 chv_update_pll(crtc, &pipe_config);
7522 chv_prepare_pll(crtc, &pipe_config);
7523 chv_enable_pll(crtc, &pipe_config);
7524 } else {
7525 vlv_update_pll(crtc, &pipe_config);
7526 vlv_prepare_pll(crtc, &pipe_config);
7527 vlv_enable_pll(crtc, &pipe_config);
7528 }
7529}
7530
7531/**
7532 * vlv_force_pll_off - forcibly disable just the PLL
7533 * @dev_priv: i915 private structure
7534 * @pipe: pipe PLL to disable
7535 *
7536 * Disable the PLL for @pipe. To be used in cases where we need
7537 * the PLL enabled even when @pipe is not going to be enabled.
7538 */
7539void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7540{
7541 if (IS_CHERRYVIEW(dev))
7542 chv_disable_pll(to_i915(dev), pipe);
7543 else
7544 vlv_disable_pll(to_i915(dev), pipe);
7545}
7546
f47709a9 7547static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7548 struct intel_crtc_state *crtc_state,
f47709a9 7549 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7550 int num_connectors)
7551{
f47709a9 7552 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7553 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7554 u32 dpll;
7555 bool is_sdvo;
190f68c5 7556 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7557
190f68c5 7558 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7559
a93e255f
ACO		 7560 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7561 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7562
7563 dpll = DPLL_VGA_MODE_DIS;
7564
a93e255f 7565 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7566 dpll |= DPLLB_MODE_LVDS;
7567 else
7568 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7569
ef1b460d 7570 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7571 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7572 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7573 }
198a037f
DV		 7574
7575 if (is_sdvo)
4a33e48d 7576 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7577
190f68c5 7578 if (crtc_state->has_dp_encoder)
4a33e48d 7579 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7580
7581 /* compute bitmask from p1 value */
7582 if (IS_PINEVIEW(dev))
7583 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7584 else {
7585 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7586 if (IS_G4X(dev) && reduced_clock)
7587 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7588 }
7589 switch (clock->p2) {
7590 case 5:
7591 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7592 break;
7593 case 7:
7594 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7595 break;
7596 case 10:
7597 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7598 break;
7599 case 14:
7600 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7601 break;
7602 }
7603 if (INTEL_INFO(dev)->gen >= 4)
7604 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7605
190f68c5 7606 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7607 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7608 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7609 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7610 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7611 else
7612 dpll |= PLL_REF_INPUT_DREFCLK;
7613
7614 dpll |= DPLL_VCO_ENABLE;
190f68c5 7615 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7616
eb1cbe48 7617 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7618 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7619 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7620 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7621 }
7622}
7623
f47709a9 7624static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7625 struct intel_crtc_state *crtc_state,
f47709a9 7626 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7627 int num_connectors)
7628{
f47709a9 7629 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7630 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7631 u32 dpll;
190f68c5 7632 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7633
190f68c5 7634 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7635
eb1cbe48
DV		 7636 dpll = DPLL_VGA_MODE_DIS;
7637
a93e255f 7638 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7639 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7640 } else {
7641 if (clock->p1 == 2)
7642 dpll |= PLL_P1_DIVIDE_BY_TWO;
7643 else
7644 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7645 if (clock->p2 == 4)
7646 dpll |= PLL_P2_DIVIDE_BY_4;
7647 }
7648
a93e255f 7649 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7650 dpll |= DPLL_DVO_2X_MODE;
7651
a93e255f 7652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7653 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7654 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7655 else
7656 dpll |= PLL_REF_INPUT_DREFCLK;
7657
7658 dpll |= DPLL_VCO_ENABLE;
190f68c5 7659 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7660}
7661
8a654f3b 7662static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7663{
7664 struct drm_device *dev = intel_crtc->base.dev;
7665 struct drm_i915_private *dev_priv = dev->dev_private;
7666 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7667 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7668 struct drm_display_mode *adjusted_mode =
6e3c9717 7669 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7670 uint32_t crtc_vtotal, crtc_vblank_end;
7671 int vsyncshift = 0;
4d8a62ea
DV		 7672
7673 /* We need to be careful not to changed the adjusted mode, for otherwise
7674 * the hw state checker will get angry at the mismatch. */
7675 crtc_vtotal = adjusted_mode->crtc_vtotal;
7676 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7677
609aeaca 7678 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7679 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7680 crtc_vtotal -= 1;
7681 crtc_vblank_end -= 1;
609aeaca 7682
409ee761 7683 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7684 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7685 else
7686 vsyncshift = adjusted_mode->crtc_hsync_start -
7687 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7688 if (vsyncshift < 0)
7689 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7690 }
7691
7692 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7693 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7694
fe2b8f9d 7695 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7696 (adjusted_mode->crtc_hdisplay - 1) |
7697 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7698 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7699 (adjusted_mode->crtc_hblank_start - 1) |
7700 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7701 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7702 (adjusted_mode->crtc_hsync_start - 1) |
7703 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7704
fe2b8f9d 7705 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7706 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7707 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7708 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7709 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7710 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7711 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7712 (adjusted_mode->crtc_vsync_start - 1) |
7713 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7714
b5e508d4
PZ		 7715 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7716 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7717 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7718 * bits. */
7719 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7720 (pipe == PIPE_B || pipe == PIPE_C))
7721 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7722
b0e77b9c
PZ		 7723 /* pipesrc controls the size that is scaled from, which should
7724 * always be the user's requested size.
7725 */
7726 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7727 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7728 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7729}
7730
1bd1bd80 7731static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7732 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7733{
7734 struct drm_device *dev = crtc->base.dev;
7735 struct drm_i915_private *dev_priv = dev->dev_private;
7736 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7737 uint32_t tmp;
7738
7739 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7740 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7741 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7742 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7743 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7744 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7745 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7746 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7747 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7748
7749 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7750 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7751 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7752 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7753 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7754 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7755 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7756 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7757 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7758
7759 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7760 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7761 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7762 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7763 }
7764
7765 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7766 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7767 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7768
2d112de7
ACO		 7769 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7770 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7771}
7772
f6a83288 7773void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7774 struct intel_crtc_state *pipe_config)
babea61d 7775{
2d112de7
ACO		 7776 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7777 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7778 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7779 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7780
2d112de7
ACO		 7781 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7782 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7783 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7784 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7785
2d112de7 7786 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7787
2d112de7
ACO		 7788 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7789 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7790}
7791
84b046f3
DV		 7792static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7793{
7794 struct drm_device *dev = intel_crtc->base.dev;
7795 struct drm_i915_private *dev_priv = dev->dev_private;
7796 uint32_t pipeconf;
7797
9f11a9e4 7798 pipeconf = 0;
84b046f3 7799
b6b5d049
VS		 7800 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7801 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7802 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7803
6e3c9717 7804 if (intel_crtc->config->double_wide)
cf532bb2 7805 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7806
ff9ce46e
DV		 7807 /* only g4x and later have fancy bpc/dither controls */
7808 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7809 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7810 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7811 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7812 PIPECONF_DITHER_TYPE_SP;
84b046f3 7813
6e3c9717 7814 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7815 case 18:
7816 pipeconf |= PIPECONF_6BPC;
7817 break;
7818 case 24:
7819 pipeconf |= PIPECONF_8BPC;
7820 break;
7821 case 30:
7822 pipeconf |= PIPECONF_10BPC;
7823 break;
7824 default:
7825 /* Case prevented by intel_choose_pipe_bpp_dither. */
7826 BUG();
84b046f3
DV		 7827 }
7828 }
7829
7830 if (HAS_PIPE_CXSR(dev)) {
7831 if (intel_crtc->lowfreq_avail) {
7832 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7833 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7834 } else {
7835 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7836 }
7837 }
7838
6e3c9717 7839 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7840 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7841 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7842 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7843 else
7844 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7845 } else
84b046f3
DV		 7846 pipeconf |= PIPECONF_PROGRESSIVE;
7847
6e3c9717 7848 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7849 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7850
84b046f3
DV		 7851 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7852 POSTING_READ(PIPECONF(intel_crtc->pipe));
7853}
7854
190f68c5
ACO		 7855static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7856 struct intel_crtc_state *crtc_state)
79e53945 7857{
c7653199 7858 struct drm_device *dev = crtc->base.dev;
79e53945 7859 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7860 int refclk, num_connectors = 0;
652c393a 7861 intel_clock_t clock, reduced_clock;
a16af721 7862 bool ok, has_reduced_clock = false;
e9fd1c02 7863 bool is_lvds = false, is_dsi = false;
5eddb70b 7864 struct intel_encoder *encoder;
d4906093 7865 const intel_limit_t *limit;
55bb9992 7866 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7867 struct drm_connector *connector;
55bb9992
ACO		 7868 struct drm_connector_state *connector_state;
7869 int i;
79e53945 7870
dd3cd74a
ACO		 7871 memset(&crtc_state->dpll_hw_state, 0,
7872 sizeof(crtc_state->dpll_hw_state));
7873
da3ced29 7874 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7875 if (connector_state->crtc != &crtc->base)
7876 continue;
7877
7878 encoder = to_intel_encoder(connector_state->best_encoder);
7879
5eddb70b 7880 switch (encoder->type) {
79e53945
JB		 7881 case INTEL_OUTPUT_LVDS:
7882 is_lvds = true;
7883 break;
e9fd1c02
JN		 7884 case INTEL_OUTPUT_DSI:
7885 is_dsi = true;
7886 break;
6847d71b
PZ		 7887 default:
7888 break;
79e53945 7889 }
43565a06 7890
c751ce4f 7891 num_connectors++;
79e53945
JB		 7892 }
7893
f2335330 7894 if (is_dsi)
5b18e57c 7895 return 0;
f2335330 7896
190f68c5 7897 if (!crtc_state->clock_set) {
a93e255f 7898 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7899
e9fd1c02
JN		 7900 /*
7901 * Returns a set of divisors for the desired target clock with
7902 * the given refclk, or FALSE. The returned values represent
7903 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7904 * 2) / p1 / p2.
7905 */
a93e255f
ACO		 7906 limit = intel_limit(crtc_state, refclk);
7907 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7908 crtc_state->port_clock,
e9fd1c02 7909 refclk, NULL, &clock);
f2335330 7910 if (!ok) {
e9fd1c02
JN		 7911 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7912 return -EINVAL;
7913 }
79e53945 7914
f2335330
JN		 7915 if (is_lvds && dev_priv->lvds_downclock_avail) {
7916 /*
7917 * Ensure we match the reduced clock's P to the target
7918 * clock. If the clocks don't match, we can't switch
7919 * the display clock by using the FP0/FP1. In such case
7920 * we will disable the LVDS downclock feature.
7921 */
7922 has_reduced_clock =
a93e255f 7923 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7924 dev_priv->lvds_downclock,
7925 refclk, &clock,
7926 &reduced_clock);
7927 }
7928 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7929 crtc_state->dpll.n = clock.n;
7930 crtc_state->dpll.m1 = clock.m1;
7931 crtc_state->dpll.m2 = clock.m2;
7932 crtc_state->dpll.p1 = clock.p1;
7933 crtc_state->dpll.p2 = clock.p2;
f47709a9 7934 }
7026d4ac 7935
e9fd1c02 7936 if (IS_GEN2(dev)) {
190f68c5 7937 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7938 has_reduced_clock ? &reduced_clock : NULL,
7939 num_connectors);
9d556c99 7940 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7941 chv_update_pll(crtc, crtc_state);
e9fd1c02 7942 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7943 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7944 } else {
190f68c5 7945 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7946 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7947 num_connectors);
e9fd1c02 7948 }
79e53945 7949
c8f7a0db 7950 return 0;
f564048e
EA		 7951}
7952
2fa2fe9a 7953static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7954 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7955{
7956 struct drm_device *dev = crtc->base.dev;
7957 struct drm_i915_private *dev_priv = dev->dev_private;
7958 uint32_t tmp;
7959
dc9e7dec
VS		 7960 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7961 return;
7962
2fa2fe9a 7963 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7964 if (!(tmp & PFIT_ENABLE))
7965 return;
2fa2fe9a 7966
06922821 7967 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7968 if (INTEL_INFO(dev)->gen < 4) {
7969 if (crtc->pipe != PIPE_B)
7970 return;
2fa2fe9a
DV		 7971 } else {
7972 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7973 return;
7974 }
7975
06922821 7976 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7977 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7978 if (INTEL_INFO(dev)->gen < 5)
7979 pipe_config->gmch_pfit.lvds_border_bits =
7980 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7981}
7982
acbec814 7983static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7984 struct intel_crtc_state *pipe_config)
acbec814
JB		 7985{
7986 struct drm_device *dev = crtc->base.dev;
7987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 int pipe = pipe_config->cpu_transcoder;
7989 intel_clock_t clock;
7990 u32 mdiv;
662c6ecb 7991 int refclk = 100000;
acbec814 7992
f573de5a
SK		 7993 /* In case of MIPI DPLL will not even be used */
7994 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7995 return;
7996
a580516d 7997 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7998 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7999 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 8000
8001 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8002 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8003 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8004 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8005 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8006
f646628b 8007 vlv_clock(refclk, &clock);
acbec814 8008
f646628b
VS		 8009 /* clock.dot is the fast clock */
8010 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 8011}
8012
5724dbd1
DL		 8013static void
8014i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8015 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 8016{
8017 struct drm_device *dev = crtc->base.dev;
8018 struct drm_i915_private *dev_priv = dev->dev_private;
8019 u32 val, base, offset;
8020 int pipe = crtc->pipe, plane = crtc->plane;
8021 int fourcc, pixel_format;
6761dd31 8022 unsigned int aligned_height;
b113d5ee 8023 struct drm_framebuffer *fb;
1b842c89 8024 struct intel_framebuffer *intel_fb;
1ad292b5 8025
42a7b088
DL		 8026 val = I915_READ(DSPCNTR(plane));
8027 if (!(val & DISPLAY_PLANE_ENABLE))
8028 return;
8029
d9806c9f 8030 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8031 if (!intel_fb) {
1ad292b5
JB		 8032 DRM_DEBUG_KMS("failed to alloc fb\n");
8033 return;
8034 }
8035
1b842c89
DL		 8036 fb = &intel_fb->base;
8037
18c5247e
DV		 8038 if (INTEL_INFO(dev)->gen >= 4) {
8039 if (val & DISPPLANE_TILED) {
49af449b 8040 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8041 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8042 }
8043 }
1ad292b5
JB		 8044
8045 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8046 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8047 fb->pixel_format = fourcc;
8048 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8049
8050 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8051 if (plane_config->tiling)
1ad292b5
JB		 8052 offset = I915_READ(DSPTILEOFF(plane));
8053 else
8054 offset = I915_READ(DSPLINOFF(plane));
8055 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8056 } else {
8057 base = I915_READ(DSPADDR(plane));
8058 }
8059 plane_config->base = base;
8060
8061 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8062 fb->width = ((val >> 16) & 0xfff) + 1;
8063 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8064
8065 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8066 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8067
b113d5ee 8068 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8069 fb->pixel_format,
8070 fb->modifier[0]);
1ad292b5 8071
f37b5c2b 8072 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8073
2844a921
DL		 8074 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8075 pipe_name(pipe), plane, fb->width, fb->height,
8076 fb->bits_per_pixel, base, fb->pitches[0],
8077 plane_config->size);
1ad292b5 8078
2d14030b 8079 plane_config->fb = intel_fb;
1ad292b5
JB		 8080}
8081
70b23a98 8082static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8083 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8084{
8085 struct drm_device *dev = crtc->base.dev;
8086 struct drm_i915_private *dev_priv = dev->dev_private;
8087 int pipe = pipe_config->cpu_transcoder;
8088 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8089 intel_clock_t clock;
8090 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8091 int refclk = 100000;
8092
a580516d 8093 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8094 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8095 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8096 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8097 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8098 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8099
8100 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8101 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8102 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8103 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8104 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8105
8106 chv_clock(refclk, &clock);
8107
8108 /* clock.dot is the fast clock */
8109 pipe_config->port_clock = clock.dot / 5;
8110}
8111
0e8ffe1b 8112static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8113 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8114{
8115 struct drm_device *dev = crtc->base.dev;
8116 struct drm_i915_private *dev_priv = dev->dev_private;
8117 uint32_t tmp;
8118
f458ebbc
DV		 8119 if (!intel_display_power_is_enabled(dev_priv,
8120 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8121 return false;
8122
e143a21c 8123 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8124 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8125
0e8ffe1b
DV		 8126 tmp = I915_READ(PIPECONF(crtc->pipe));
8127 if (!(tmp & PIPECONF_ENABLE))
8128 return false;
8129
42571aef
VS		 8130 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8131 switch (tmp & PIPECONF_BPC_MASK) {
8132 case PIPECONF_6BPC:
8133 pipe_config->pipe_bpp = 18;
8134 break;
8135 case PIPECONF_8BPC:
8136 pipe_config->pipe_bpp = 24;
8137 break;
8138 case PIPECONF_10BPC:
8139 pipe_config->pipe_bpp = 30;
8140 break;
8141 default:
8142 break;
8143 }
8144 }
8145
b5a9fa09
DV		 8146 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8147 pipe_config->limited_color_range = true;
8148
282740f7
VS		 8149 if (INTEL_INFO(dev)->gen < 4)
8150 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8151
1bd1bd80
DV		 8152 intel_get_pipe_timings(crtc, pipe_config);
8153
2fa2fe9a
DV		 8154 i9xx_get_pfit_config(crtc, pipe_config);
8155
6c49f241
DV		 8156 if (INTEL_INFO(dev)->gen >= 4) {
8157 tmp = I915_READ(DPLL_MD(crtc->pipe));
8158 pipe_config->pixel_multiplier =
8159 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8160 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8161 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8162 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8163 tmp = I915_READ(DPLL(crtc->pipe));
8164 pipe_config->pixel_multiplier =
8165 ((tmp & SDVO_MULTIPLIER_MASK)
8166 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8167 } else {
8168 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8169 * port and will be fixed up in the encoder->get_config
8170 * function. */
8171 pipe_config->pixel_multiplier = 1;
8172 }
8bcc2795
DV		 8173 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8174 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8175 /*
8176 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8177 * on 830. Filter it out here so that we don't
8178 * report errors due to that.
8179 */
8180 if (IS_I830(dev))
8181 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8182
8bcc2795
DV		 8183 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8184 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8185 } else {
8186 /* Mask out read-only status bits. */
8187 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8188 DPLL_PORTC_READY_MASK |
8189 DPLL_PORTB_READY_MASK);
8bcc2795 8190 }
6c49f241 8191
70b23a98
VS		 8192 if (IS_CHERRYVIEW(dev))
8193 chv_crtc_clock_get(crtc, pipe_config);
8194 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8195 vlv_crtc_clock_get(crtc, pipe_config);
8196 else
8197 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8198
0e8ffe1b
DV		 8199 return true;
8200}
8201
dde86e2d 8202static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8203{
8204 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8205 struct intel_encoder *encoder;
74cfd7ac 8206 u32 val, final;
13d83a67 8207 bool has_lvds = false;
199e5d79 8208 bool has_cpu_edp = false;
199e5d79 8209 bool has_panel = false;
99eb6a01
KP		 8210 bool has_ck505 = false;
8211 bool can_ssc = false;
13d83a67
JB		 8212
8213 /* We need to take the global config into account */
b2784e15 8214 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8215 switch (encoder->type) {
8216 case INTEL_OUTPUT_LVDS:
8217 has_panel = true;
8218 has_lvds = true;
8219 break;
8220 case INTEL_OUTPUT_EDP:
8221 has_panel = true;
2de6905f 8222 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8223 has_cpu_edp = true;
8224 break;
6847d71b
PZ		 8225 default:
8226 break;
13d83a67
JB		 8227 }
8228 }
8229
99eb6a01 8230 if (HAS_PCH_IBX(dev)) {
41aa3448 8231 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8232 can_ssc = has_ck505;
8233 } else {
8234 has_ck505 = false;
8235 can_ssc = true;
8236 }
8237
2de6905f
ID		 8238 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8239 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8240
8241 /* Ironlake: try to setup display ref clock before DPLL
8242 * enabling. This is only under driver's control after
8243 * PCH B stepping, previous chipset stepping should be
8244 * ignoring this setting.
8245 */
74cfd7ac
CW		 8246 val = I915_READ(PCH_DREF_CONTROL);
8247
8248 /* As we must carefully and slowly disable/enable each source in turn,
8249 * compute the final state we want first and check if we need to
8250 * make any changes at all.
8251 */
8252 final = val;
8253 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8254 if (has_ck505)
8255 final |= DREF_NONSPREAD_CK505_ENABLE;
8256 else
8257 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8258
8259 final &= ~DREF_SSC_SOURCE_MASK;
8260 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8261 final &= ~DREF_SSC1_ENABLE;
8262
8263 if (has_panel) {
8264 final |= DREF_SSC_SOURCE_ENABLE;
8265
8266 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8267 final |= DREF_SSC1_ENABLE;
8268
8269 if (has_cpu_edp) {
8270 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8271 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8272 else
8273 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8274 } else
8275 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8276 } else {
8277 final |= DREF_SSC_SOURCE_DISABLE;
8278 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8279 }
8280
8281 if (final == val)
8282 return;
8283
13d83a67 8284 /* Always enable nonspread source */
74cfd7ac 8285 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8286
99eb6a01 8287 if (has_ck505)
74cfd7ac 8288 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8289 else
74cfd7ac 8290 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8291
199e5d79 8292 if (has_panel) {
74cfd7ac
CW		 8293 val &= ~DREF_SSC_SOURCE_MASK;
8294 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8295
199e5d79 8296 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8297 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8298 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8299 val |= DREF_SSC1_ENABLE;
e77166b5 8300 } else
74cfd7ac 8301 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8302
8303 /* Get SSC going before enabling the outputs */
74cfd7ac 8304 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8305 POSTING_READ(PCH_DREF_CONTROL);
8306 udelay(200);
8307
74cfd7ac 8308 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8309
8310 /* Enable CPU source on CPU attached eDP */
199e5d79 8311 if (has_cpu_edp) {
99eb6a01 8312 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8313 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8314 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8315 } else
74cfd7ac 8316 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8317 } else
74cfd7ac 8318 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8319
74cfd7ac 8320 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8321 POSTING_READ(PCH_DREF_CONTROL);
8322 udelay(200);
8323 } else {
8324 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8325
74cfd7ac 8326 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8327
8328 /* Turn off CPU output */
74cfd7ac 8329 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8330
74cfd7ac 8331 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8332 POSTING_READ(PCH_DREF_CONTROL);
8333 udelay(200);
8334
8335 /* Turn off the SSC source */
74cfd7ac
CW		 8336 val &= ~DREF_SSC_SOURCE_MASK;
8337 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8338
8339 /* Turn off SSC1 */
74cfd7ac 8340 val &= ~DREF_SSC1_ENABLE;
199e5d79 8341
74cfd7ac 8342 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8343 POSTING_READ(PCH_DREF_CONTROL);
8344 udelay(200);
8345 }
74cfd7ac
CW		 8346
8347 BUG_ON(val != final);
13d83a67
JB		 8348}
8349
f31f2d55 8350static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8351{
f31f2d55 8352 uint32_t tmp;
dde86e2d 8353
0ff066a9
PZ		 8354 tmp = I915_READ(SOUTH_CHICKEN2);
8355 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8356 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8357
0ff066a9
PZ		 8358 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8359 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8360 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8361
0ff066a9
PZ		 8362 tmp = I915_READ(SOUTH_CHICKEN2);
8363 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8364 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8365
0ff066a9
PZ		 8366 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8367 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8368 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8369}
8370
8371/* WaMPhyProgramming:hsw */
8372static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8373{
8374 uint32_t tmp;
dde86e2d
PZ		 8375
8376 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8377 tmp &= ~(0xFF << 24);
8378 tmp |= (0x12 << 24);
8379 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8380
dde86e2d
PZ		 8381 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8382 tmp |= (1 << 11);
8383 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8384
8385 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8386 tmp |= (1 << 11);
8387 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8388
dde86e2d
PZ		 8389 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8390 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8391 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8392
8393 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8394 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8395 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8396
0ff066a9
PZ		 8397 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8398 tmp &= ~(7 << 13);
8399 tmp |= (5 << 13);
8400 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8401
0ff066a9
PZ		 8402 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8403 tmp &= ~(7 << 13);
8404 tmp |= (5 << 13);
8405 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8406
8407 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8408 tmp &= ~0xFF;
8409 tmp |= 0x1C;
8410 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8411
8412 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8413 tmp &= ~0xFF;
8414 tmp |= 0x1C;
8415 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8416
8417 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8418 tmp &= ~(0xFF << 16);
8419 tmp |= (0x1C << 16);
8420 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8421
8422 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8423 tmp &= ~(0xFF << 16);
8424 tmp |= (0x1C << 16);
8425 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8426
0ff066a9
PZ		 8427 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8428 tmp |= (1 << 27);
8429 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8430
0ff066a9
PZ		 8431 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8432 tmp |= (1 << 27);
8433 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8434
0ff066a9
PZ		 8435 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8436 tmp &= ~(0xF << 28);
8437 tmp |= (4 << 28);
8438 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8439
0ff066a9
PZ		 8440 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8441 tmp &= ~(0xF << 28);
8442 tmp |= (4 << 28);
8443 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8444}
8445
2fa86a1f
PZ		 8446/* Implements 3 different sequences from BSpec chapter "Display iCLK
8447 * Programming" based on the parameters passed:
8448 * - Sequence to enable CLKOUT_DP
8449 * - Sequence to enable CLKOUT_DP without spread
8450 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8451 */
8452static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8453 bool with_fdi)
f31f2d55
PZ		 8454{
8455 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8456 uint32_t reg, tmp;
8457
8458 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8459 with_spread = true;
8460 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8461 with_fdi, "LP PCH doesn't have FDI\n"))
8462 with_fdi = false;
f31f2d55 8463
a580516d 8464 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8465
8466 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8467 tmp &= ~SBI_SSCCTL_DISABLE;
8468 tmp |= SBI_SSCCTL_PATHALT;
8469 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8470
8471 udelay(24);
8472
2fa86a1f
PZ		 8473 if (with_spread) {
8474 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8475 tmp &= ~SBI_SSCCTL_PATHALT;
8476 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8477
2fa86a1f
PZ		 8478 if (with_fdi) {
8479 lpt_reset_fdi_mphy(dev_priv);
8480 lpt_program_fdi_mphy(dev_priv);
8481 }
8482 }
dde86e2d 8483
2fa86a1f
PZ		 8484 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8485 SBI_GEN0 : SBI_DBUFF0;
8486 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8487 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8488 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8489
a580516d 8490 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8491}
8492
47701c3b
PZ		 8493/* Sequence to disable CLKOUT_DP */
8494static void lpt_disable_clkout_dp(struct drm_device *dev)
8495{
8496 struct drm_i915_private *dev_priv = dev->dev_private;
8497 uint32_t reg, tmp;
8498
a580516d 8499 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8500
8501 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8502 SBI_GEN0 : SBI_DBUFF0;
8503 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8504 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8505 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8506
8507 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8508 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8509 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8510 tmp |= SBI_SSCCTL_PATHALT;
8511 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8512 udelay(32);
8513 }
8514 tmp |= SBI_SSCCTL_DISABLE;
8515 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8516 }
8517
a580516d 8518 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8519}
8520
bf8fa3d3
PZ		 8521static void lpt_init_pch_refclk(struct drm_device *dev)
8522{
bf8fa3d3
PZ		 8523 struct intel_encoder *encoder;
8524 bool has_vga = false;
8525
b2784e15 8526 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8527 switch (encoder->type) {
8528 case INTEL_OUTPUT_ANALOG:
8529 has_vga = true;
8530 break;
6847d71b
PZ		 8531 default:
8532 break;
bf8fa3d3
PZ		 8533 }
8534 }
8535
47701c3b
PZ		 8536 if (has_vga)
8537 lpt_enable_clkout_dp(dev, true, true);
8538 else
8539 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8540}
8541
dde86e2d
PZ		 8542/*
8543 * Initialize reference clocks when the driver loads
8544 */
8545void intel_init_pch_refclk(struct drm_device *dev)
8546{
8547 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8548 ironlake_init_pch_refclk(dev);
8549 else if (HAS_PCH_LPT(dev))
8550 lpt_init_pch_refclk(dev);
8551}
8552
55bb9992 8553static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8554{
55bb9992 8555 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8556 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8557 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8558 struct drm_connector *connector;
55bb9992 8559 struct drm_connector_state *connector_state;
d9d444cb 8560 struct intel_encoder *encoder;
55bb9992 8561 int num_connectors = 0, i;
d9d444cb
JB		 8562 bool is_lvds = false;
8563
da3ced29 8564 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8565 if (connector_state->crtc != crtc_state->base.crtc)
8566 continue;
8567
8568 encoder = to_intel_encoder(connector_state->best_encoder);
8569
d9d444cb
JB		 8570 switch (encoder->type) {
8571 case INTEL_OUTPUT_LVDS:
8572 is_lvds = true;
8573 break;
6847d71b
PZ		 8574 default:
8575 break;
d9d444cb
JB		 8576 }
8577 num_connectors++;
8578 }
8579
8580 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8581 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8582 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8583 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8584 }
8585
8586 return 120000;
8587}
8588
6ff93609 8589static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8590{
c8203565 8591 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8593 int pipe = intel_crtc->pipe;
c8203565
PZ		 8594 uint32_t val;
8595
78114071 8596 val = 0;
c8203565 8597
6e3c9717 8598 switch (intel_crtc->config->pipe_bpp) {
c8203565 8599 case 18:
dfd07d72 8600 val |= PIPECONF_6BPC;
c8203565
PZ		 8601 break;
8602 case 24:
dfd07d72 8603 val |= PIPECONF_8BPC;
c8203565
PZ		 8604 break;
8605 case 30:
dfd07d72 8606 val |= PIPECONF_10BPC;
c8203565
PZ		 8607 break;
8608 case 36:
dfd07d72 8609 val |= PIPECONF_12BPC;
c8203565
PZ		 8610 break;
8611 default:
cc769b62
PZ		 8612 /* Case prevented by intel_choose_pipe_bpp_dither. */
8613 BUG();
c8203565
PZ		 8614 }
8615
6e3c9717 8616 if (intel_crtc->config->dither)
c8203565
PZ		 8617 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8618
6e3c9717 8619 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8620 val |= PIPECONF_INTERLACED_ILK;
8621 else
8622 val |= PIPECONF_PROGRESSIVE;
8623
6e3c9717 8624 if (intel_crtc->config->limited_color_range)
3685a8f3 8625 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8626
c8203565
PZ		 8627 I915_WRITE(PIPECONF(pipe), val);
8628 POSTING_READ(PIPECONF(pipe));
8629}
8630
86d3efce
VS		 8631/*
8632 * Set up the pipe CSC unit.
8633 *
8634 * Currently only full range RGB to limited range RGB conversion
8635 * is supported, but eventually this should handle various
8636 * RGB<->YCbCr scenarios as well.
8637 */
50f3b016 8638static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8639{
8640 struct drm_device *dev = crtc->dev;
8641 struct drm_i915_private *dev_priv = dev->dev_private;
8642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8643 int pipe = intel_crtc->pipe;
8644 uint16_t coeff = 0x7800; /* 1.0 */
8645
8646 /*
8647 * TODO: Check what kind of values actually come out of the pipe
8648 * with these coeff/postoff values and adjust to get the best
8649 * accuracy. Perhaps we even need to take the bpc value into
8650 * consideration.
8651 */
8652
6e3c9717 8653 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8654 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8655
8656 /*
8657 * GY/GU and RY/RU should be the other way around according
8658 * to BSpec, but reality doesn't agree. Just set them up in
8659 * a way that results in the correct picture.
8660 */
8661 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8662 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8663
8664 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8665 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8666
8667 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8668 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8669
8670 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8671 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8672 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8673
8674 if (INTEL_INFO(dev)->gen > 6) {
8675 uint16_t postoff = 0;
8676
6e3c9717 8677 if (intel_crtc->config->limited_color_range)
32cf0cb0 8678 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8679
8680 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8681 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8682 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8683
8684 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8685 } else {
8686 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8687
6e3c9717 8688 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8689 mode |= CSC_BLACK_SCREEN_OFFSET;
8690
8691 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8692 }
8693}
8694
6ff93609 8695static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8696{
756f85cf
PZ		 8697 struct drm_device *dev = crtc->dev;
8698 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8700 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8701 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8702 uint32_t val;
8703
3eff4faa 8704 val = 0;
ee2b0b38 8705
6e3c9717 8706 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8707 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8708
6e3c9717 8709 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8710 val |= PIPECONF_INTERLACED_ILK;
8711 else
8712 val |= PIPECONF_PROGRESSIVE;
8713
702e7a56
PZ		 8714 I915_WRITE(PIPECONF(cpu_transcoder), val);
8715 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8716
8717 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8718 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8719
3cdf122c 8720 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8721 val = 0;
8722
6e3c9717 8723 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8724 case 18:
8725 val |= PIPEMISC_DITHER_6_BPC;
8726 break;
8727 case 24:
8728 val |= PIPEMISC_DITHER_8_BPC;
8729 break;
8730 case 30:
8731 val |= PIPEMISC_DITHER_10_BPC;
8732 break;
8733 case 36:
8734 val |= PIPEMISC_DITHER_12_BPC;
8735 break;
8736 default:
8737 /* Case prevented by pipe_config_set_bpp. */
8738 BUG();
8739 }
8740
6e3c9717 8741 if (intel_crtc->config->dither)
756f85cf
PZ		 8742 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8743
8744 I915_WRITE(PIPEMISC(pipe), val);
8745 }
ee2b0b38
PZ		 8746}
8747
6591c6e4 8748static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8749 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8750 intel_clock_t *clock,
8751 bool *has_reduced_clock,
8752 intel_clock_t *reduced_clock)
8753{
8754 struct drm_device *dev = crtc->dev;
8755 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8756 int refclk;
d4906093 8757 const intel_limit_t *limit;
a16af721 8758 bool ret, is_lvds = false;
79e53945 8759
a93e255f 8760 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8761
55bb9992 8762 refclk = ironlake_get_refclk(crtc_state);
79e53945 8763
d4906093
ML		 8764 /*
8765 * Returns a set of divisors for the desired target clock with the given
8766 * refclk, or FALSE. The returned values represent the clock equation:
8767 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8768 */
a93e255f
ACO		 8769 limit = intel_limit(crtc_state, refclk);
8770 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8771 crtc_state->port_clock,
ee9300bb 8772 refclk, NULL, clock);
6591c6e4
PZ		 8773 if (!ret)
8774 return false;
cda4b7d3 8775
ddc9003c 8776 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8777 /*
8778 * Ensure we match the reduced clock's P to the target clock.
8779 * If the clocks don't match, we can't switch the display clock
8780 * by using the FP0/FP1. In such case we will disable the LVDS
8781 * downclock feature.
8782 */
ee9300bb 8783 *has_reduced_clock =
a93e255f 8784 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8785 dev_priv->lvds_downclock,
8786 refclk, clock,
8787 reduced_clock);
652c393a 8788 }
61e9653f 8789
6591c6e4
PZ		 8790 return true;
8791}
8792
d4b1931c
PZ		 8793int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8794{
8795 /*
8796 * Account for spread spectrum to avoid
8797 * oversubscribing the link. Max center spread
8798 * is 2.5%; use 5% for safety's sake.
8799 */
8800 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8801 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8802}
8803
7429e9d4 8804static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8805{
7429e9d4 8806 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8807}
8808
de13a2e3 8809static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8810 struct intel_crtc_state *crtc_state,
7429e9d4 8811 u32 *fp,
9a7c7890 8812 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8813{
de13a2e3 8814 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8815 struct drm_device *dev = crtc->dev;
8816 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8817 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8818 struct drm_connector *connector;
55bb9992
ACO		 8819 struct drm_connector_state *connector_state;
8820 struct intel_encoder *encoder;
de13a2e3 8821 uint32_t dpll;
55bb9992 8822 int factor, num_connectors = 0, i;
09ede541 8823 bool is_lvds = false, is_sdvo = false;
79e53945 8824
da3ced29 8825 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8826 if (connector_state->crtc != crtc_state->base.crtc)
8827 continue;
8828
8829 encoder = to_intel_encoder(connector_state->best_encoder);
8830
8831 switch (encoder->type) {
79e53945
JB		 8832 case INTEL_OUTPUT_LVDS:
8833 is_lvds = true;
8834 break;
8835 case INTEL_OUTPUT_SDVO:
7d57382e 8836 case INTEL_OUTPUT_HDMI:
79e53945 8837 is_sdvo = true;
79e53945 8838 break;
6847d71b
PZ		 8839 default:
8840 break;
79e53945 8841 }
43565a06 8842
c751ce4f 8843 num_connectors++;
79e53945 8844 }
79e53945 8845
c1858123 8846 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8847 factor = 21;
8848 if (is_lvds) {
8849 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8850 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8851 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8852 factor = 25;
190f68c5 8853 } else if (crtc_state->sdvo_tv_clock)
8febb297 8854 factor = 20;
c1858123 8855
190f68c5 8856 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8857 *fp |= FP_CB_TUNE;
2c07245f 8858
9a7c7890
DV		 8859 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8860 *fp2 |= FP_CB_TUNE;
8861
5eddb70b 8862 dpll = 0;
2c07245f 8863
a07d6787
EA		 8864 if (is_lvds)
8865 dpll |= DPLLB_MODE_LVDS;
8866 else
8867 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8868
190f68c5 8869 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8870 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8871
8872 if (is_sdvo)
4a33e48d 8873 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8874 if (crtc_state->has_dp_encoder)
4a33e48d 8875 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8876
a07d6787 8877 /* compute bitmask from p1 value */
190f68c5 8878 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8879 /* also FPA1 */
190f68c5 8880 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8881
190f68c5 8882 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8883 case 5:
8884 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8885 break;
8886 case 7:
8887 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8888 break;
8889 case 10:
8890 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8891 break;
8892 case 14:
8893 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8894 break;
79e53945
JB		 8895 }
8896
b4c09f3b 8897 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8898 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8899 else
8900 dpll |= PLL_REF_INPUT_DREFCLK;
8901
959e16d6 8902 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8903}
8904
190f68c5
ACO		 8905static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8906 struct intel_crtc_state *crtc_state)
de13a2e3 8907{
c7653199 8908 struct drm_device *dev = crtc->base.dev;
de13a2e3 8909 intel_clock_t clock, reduced_clock;
cbbab5bd 8910 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8911 bool ok, has_reduced_clock = false;
8b47047b 8912 bool is_lvds = false;
e2b78267 8913 struct intel_shared_dpll *pll;
de13a2e3 8914
dd3cd74a
ACO		 8915 memset(&crtc_state->dpll_hw_state, 0,
8916 sizeof(crtc_state->dpll_hw_state));
8917
409ee761 8918 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8919
5dc5298b
PZ		 8920 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8921 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8922
190f68c5 8923 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8924 &has_reduced_clock, &reduced_clock);
190f68c5 8925 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8926 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8927 return -EINVAL;
79e53945 8928 }
f47709a9 8929 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8930 if (!crtc_state->clock_set) {
8931 crtc_state->dpll.n = clock.n;
8932 crtc_state->dpll.m1 = clock.m1;
8933 crtc_state->dpll.m2 = clock.m2;
8934 crtc_state->dpll.p1 = clock.p1;
8935 crtc_state->dpll.p2 = clock.p2;
f47709a9 8936 }
79e53945 8937
5dc5298b 8938 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8939 if (crtc_state->has_pch_encoder) {
8940 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8941 if (has_reduced_clock)
7429e9d4 8942 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8943
190f68c5 8944 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8945 &fp, &reduced_clock,
8946 has_reduced_clock ? &fp2 : NULL);
8947
190f68c5
ACO		 8948 crtc_state->dpll_hw_state.dpll = dpll;
8949 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8950 if (has_reduced_clock)
190f68c5 8951 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8952 else
190f68c5 8953 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8954
190f68c5 8955 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8956 if (pll == NULL) {
84f44ce7 8957 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8958 pipe_name(crtc->pipe));
4b645f14
JB		 8959 return -EINVAL;
8960 }
3fb37703 8961 }
79e53945 8962
ab585dea 8963 if (is_lvds && has_reduced_clock)
c7653199 8964 crtc->lowfreq_avail = true;
bcd644e0 8965 else
c7653199 8966 crtc->lowfreq_avail = false;
e2b78267 8967
c8f7a0db 8968 return 0;
79e53945
JB		 8969}
8970
eb14cb74
VS		 8971static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8972 struct intel_link_m_n *m_n)
8973{
8974 struct drm_device *dev = crtc->base.dev;
8975 struct drm_i915_private *dev_priv = dev->dev_private;
8976 enum pipe pipe = crtc->pipe;
8977
8978 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8979 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8980 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8981 & ~TU_SIZE_MASK;
8982 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8983 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8984 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8985}
8986
8987static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8988 enum transcoder transcoder,
b95af8be
VK		 8989 struct intel_link_m_n *m_n,
8990 struct intel_link_m_n *m2_n2)
72419203
DV		 8991{
8992 struct drm_device *dev = crtc->base.dev;
8993 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8994 enum pipe pipe = crtc->pipe;
72419203 8995
eb14cb74
VS		 8996 if (INTEL_INFO(dev)->gen >= 5) {
8997 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8998 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8999 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9000 & ~TU_SIZE_MASK;
9001 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9002 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9003 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 9004 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9005 * gen < 8) and if DRRS is supported (to make sure the
9006 * registers are not unnecessarily read).
9007 */
9008 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 9009 crtc->config->has_drrs) {
b95af8be
VK		 9010 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9011 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9012 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9013 & ~TU_SIZE_MASK;
9014 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9015 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9016 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9017 }
eb14cb74
VS		 9018 } else {
9019 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9020 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9021 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9022 & ~TU_SIZE_MASK;
9023 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9024 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9025 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9026 }
9027}
9028
9029void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9030 struct intel_crtc_state *pipe_config)
eb14cb74 9031{
681a8504 9032 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9033 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9034 else
9035 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9036 &pipe_config->dp_m_n,
9037 &pipe_config->dp_m2_n2);
eb14cb74 9038}
72419203 9039
eb14cb74 9040static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9041 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9042{
9043 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9044 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9045}
9046
bd2e244f 9047static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9048 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9049{
9050 struct drm_device *dev = crtc->base.dev;
9051 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9052 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9053 uint32_t ps_ctrl = 0;
9054 int id = -1;
9055 int i;
bd2e244f 9056
a1b2278e
CK		 9057 /* find scaler attached to this pipe */
9058 for (i = 0; i < crtc->num_scalers; i++) {
9059 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9060 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9061 id = i;
9062 pipe_config->pch_pfit.enabled = true;
9063 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9064 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9065 break;
9066 }
9067 }
bd2e244f 9068
a1b2278e
CK		 9069 scaler_state->scaler_id = id;
9070 if (id >= 0) {
9071 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9072 } else {
9073 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9074 }
9075}
9076
5724dbd1
DL		 9077static void
9078skylake_get_initial_plane_config(struct intel_crtc *crtc,
9079 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9080{
9081 struct drm_device *dev = crtc->base.dev;
9082 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9083 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9084 int pipe = crtc->pipe;
9085 int fourcc, pixel_format;
6761dd31 9086 unsigned int aligned_height;
bc8d7dff 9087 struct drm_framebuffer *fb;
1b842c89 9088 struct intel_framebuffer *intel_fb;
bc8d7dff 9089
d9806c9f 9090 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9091 if (!intel_fb) {
bc8d7dff
DL		 9092 DRM_DEBUG_KMS("failed to alloc fb\n");
9093 return;
9094 }
9095
1b842c89
DL		 9096 fb = &intel_fb->base;
9097
bc8d7dff 9098 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9099 if (!(val & PLANE_CTL_ENABLE))
9100 goto error;
9101
bc8d7dff
DL		 9102 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9103 fourcc = skl_format_to_fourcc(pixel_format,
9104 val & PLANE_CTL_ORDER_RGBX,
9105 val & PLANE_CTL_ALPHA_MASK);
9106 fb->pixel_format = fourcc;
9107 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9108
40f46283
DL		 9109 tiling = val & PLANE_CTL_TILED_MASK;
9110 switch (tiling) {
9111 case PLANE_CTL_TILED_LINEAR:
9112 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9113 break;
9114 case PLANE_CTL_TILED_X:
9115 plane_config->tiling = I915_TILING_X;
9116 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9117 break;
9118 case PLANE_CTL_TILED_Y:
9119 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9120 break;
9121 case PLANE_CTL_TILED_YF:
9122 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9123 break;
9124 default:
9125 MISSING_CASE(tiling);
9126 goto error;
9127 }
9128
bc8d7dff
DL		 9129 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9130 plane_config->base = base;
9131
9132 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9133
9134 val = I915_READ(PLANE_SIZE(pipe, 0));
9135 fb->height = ((val >> 16) & 0xfff) + 1;
9136 fb->width = ((val >> 0) & 0x1fff) + 1;
9137
9138 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9139 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9140 fb->pixel_format);
bc8d7dff
DL		 9141 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9142
9143 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9144 fb->pixel_format,
9145 fb->modifier[0]);
bc8d7dff 9146
f37b5c2b 9147 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9148
9149 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9150 pipe_name(pipe), fb->width, fb->height,
9151 fb->bits_per_pixel, base, fb->pitches[0],
9152 plane_config->size);
9153
2d14030b 9154 plane_config->fb = intel_fb;
bc8d7dff
DL		 9155 return;
9156
9157error:
9158 kfree(fb);
9159}
9160
2fa2fe9a 9161static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9162 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9163{
9164 struct drm_device *dev = crtc->base.dev;
9165 struct drm_i915_private *dev_priv = dev->dev_private;
9166 uint32_t tmp;
9167
9168 tmp = I915_READ(PF_CTL(crtc->pipe));
9169
9170 if (tmp & PF_ENABLE) {
fd4daa9c 9171 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9172 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9173 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9174
9175 /* We currently do not free assignements of panel fitters on
9176 * ivb/hsw (since we don't use the higher upscaling modes which
9177 * differentiates them) so just WARN about this case for now. */
9178 if (IS_GEN7(dev)) {
9179 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9180 PF_PIPE_SEL_IVB(crtc->pipe));
9181 }
2fa2fe9a 9182 }
79e53945
JB		 9183}
9184
5724dbd1
DL		 9185static void
9186ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9187 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9188{
9189 struct drm_device *dev = crtc->base.dev;
9190 struct drm_i915_private *dev_priv = dev->dev_private;
9191 u32 val, base, offset;
aeee5a49 9192 int pipe = crtc->pipe;
4c6baa59 9193 int fourcc, pixel_format;
6761dd31 9194 unsigned int aligned_height;
b113d5ee 9195 struct drm_framebuffer *fb;
1b842c89 9196 struct intel_framebuffer *intel_fb;
4c6baa59 9197
42a7b088
DL		 9198 val = I915_READ(DSPCNTR(pipe));
9199 if (!(val & DISPLAY_PLANE_ENABLE))
9200 return;
9201
d9806c9f 9202 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9203 if (!intel_fb) {
4c6baa59
JB		 9204 DRM_DEBUG_KMS("failed to alloc fb\n");
9205 return;
9206 }
9207
1b842c89
DL		 9208 fb = &intel_fb->base;
9209
18c5247e
DV		 9210 if (INTEL_INFO(dev)->gen >= 4) {
9211 if (val & DISPPLANE_TILED) {
49af449b 9212 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9213 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9214 }
9215 }
4c6baa59
JB		 9216
9217 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9218 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9219 fb->pixel_format = fourcc;
9220 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9221
aeee5a49 9222 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9223 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9224 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9225 } else {
49af449b 9226 if (plane_config->tiling)
aeee5a49 9227 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9228 else
aeee5a49 9229 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9230 }
9231 plane_config->base = base;
9232
9233 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9234 fb->width = ((val >> 16) & 0xfff) + 1;
9235 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9236
9237 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9238 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9239
b113d5ee 9240 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9241 fb->pixel_format,
9242 fb->modifier[0]);
4c6baa59 9243
f37b5c2b 9244 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9245
2844a921
DL		 9246 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9247 pipe_name(pipe), fb->width, fb->height,
9248 fb->bits_per_pixel, base, fb->pitches[0],
9249 plane_config->size);
b113d5ee 9250
2d14030b 9251 plane_config->fb = intel_fb;
4c6baa59
JB		 9252}
9253
0e8ffe1b 9254static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9255 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9256{
9257 struct drm_device *dev = crtc->base.dev;
9258 struct drm_i915_private *dev_priv = dev->dev_private;
9259 uint32_t tmp;
9260
f458ebbc
DV		 9261 if (!intel_display_power_is_enabled(dev_priv,
9262 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9263 return false;
9264
e143a21c 9265 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9266 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9267
0e8ffe1b
DV		 9268 tmp = I915_READ(PIPECONF(crtc->pipe));
9269 if (!(tmp & PIPECONF_ENABLE))
9270 return false;
9271
42571aef
VS		 9272 switch (tmp & PIPECONF_BPC_MASK) {
9273 case PIPECONF_6BPC:
9274 pipe_config->pipe_bpp = 18;
9275 break;
9276 case PIPECONF_8BPC:
9277 pipe_config->pipe_bpp = 24;
9278 break;
9279 case PIPECONF_10BPC:
9280 pipe_config->pipe_bpp = 30;
9281 break;
9282 case PIPECONF_12BPC:
9283 pipe_config->pipe_bpp = 36;
9284 break;
9285 default:
9286 break;
9287 }
9288
b5a9fa09
DV		 9289 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9290 pipe_config->limited_color_range = true;
9291
ab9412ba 9292 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9293 struct intel_shared_dpll *pll;
9294
88adfff1
DV		 9295 pipe_config->has_pch_encoder = true;
9296
627eb5a3
DV		 9297 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9298 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9299 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9300
9301 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9302
c0d43d62 9303 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9304 pipe_config->shared_dpll =
9305 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9306 } else {
9307 tmp = I915_READ(PCH_DPLL_SEL);
9308 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9309 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9310 else
9311 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9312 }
66e985c0
DV		 9313
9314 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9315
9316 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9317 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9318
9319 tmp = pipe_config->dpll_hw_state.dpll;
9320 pipe_config->pixel_multiplier =
9321 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9322 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9323
9324 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9325 } else {
9326 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9327 }
9328
1bd1bd80
DV		 9329 intel_get_pipe_timings(crtc, pipe_config);
9330
2fa2fe9a
DV		 9331 ironlake_get_pfit_config(crtc, pipe_config);
9332
0e8ffe1b
DV		 9333 return true;
9334}
9335
be256dc7
PZ		 9336static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9337{
9338 struct drm_device *dev = dev_priv->dev;
be256dc7 9339 struct intel_crtc *crtc;
be256dc7 9340
d3fcc808 9341 for_each_intel_crtc(dev, crtc)
e2c719b7 9342 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9343 pipe_name(crtc->pipe));
9344
e2c719b7
RC		 9345 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9346 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9347 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9348 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9349 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9350 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9351 "CPU PWM1 enabled\n");
c5107b87 9352 if (IS_HASWELL(dev))
e2c719b7 9353 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9354 "CPU PWM2 enabled\n");
e2c719b7 9355 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9356 "PCH PWM1 enabled\n");
e2c719b7 9357 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9358 "Utility pin enabled\n");
e2c719b7 9359 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9360
9926ada1
PZ		 9361 /*
9362 * In theory we can still leave IRQs enabled, as long as only the HPD
9363 * interrupts remain enabled. We used to check for that, but since it's
9364 * gen-specific and since we only disable LCPLL after we fully disable
9365 * the interrupts, the check below should be enough.
9366 */
e2c719b7 9367 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9368}
9369
9ccd5aeb
PZ		 9370static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9371{
9372 struct drm_device *dev = dev_priv->dev;
9373
9374 if (IS_HASWELL(dev))
9375 return I915_READ(D_COMP_HSW);
9376 else
9377 return I915_READ(D_COMP_BDW);
9378}
9379
3c4c9b81
PZ		 9380static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9381{
9382 struct drm_device *dev = dev_priv->dev;
9383
9384 if (IS_HASWELL(dev)) {
9385 mutex_lock(&dev_priv->rps.hw_lock);
9386 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9387 val))
f475dadf 9388 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9389 mutex_unlock(&dev_priv->rps.hw_lock);
9390 } else {
9ccd5aeb
PZ		 9391 I915_WRITE(D_COMP_BDW, val);
9392 POSTING_READ(D_COMP_BDW);
3c4c9b81 9393 }
be256dc7
PZ		 9394}
9395
9396/*
9397 * This function implements pieces of two sequences from BSpec:
9398 * - Sequence for display software to disable LCPLL
9399 * - Sequence for display software to allow package C8+
9400 * The steps implemented here are just the steps that actually touch the LCPLL
9401 * register. Callers should take care of disabling all the display engine
9402 * functions, doing the mode unset, fixing interrupts, etc.
9403 */
6ff58d53
PZ		 9404static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9405 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9406{
9407 uint32_t val;
9408
9409 assert_can_disable_lcpll(dev_priv);
9410
9411 val = I915_READ(LCPLL_CTL);
9412
9413 if (switch_to_fclk) {
9414 val |= LCPLL_CD_SOURCE_FCLK;
9415 I915_WRITE(LCPLL_CTL, val);
9416
9417 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9418 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9419 DRM_ERROR("Switching to FCLK failed\n");
9420
9421 val = I915_READ(LCPLL_CTL);
9422 }
9423
9424 val |= LCPLL_PLL_DISABLE;
9425 I915_WRITE(LCPLL_CTL, val);
9426 POSTING_READ(LCPLL_CTL);
9427
9428 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9429 DRM_ERROR("LCPLL still locked\n");
9430
9ccd5aeb 9431 val = hsw_read_dcomp(dev_priv);
be256dc7 9432 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9433 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9434 ndelay(100);
9435
9ccd5aeb
PZ		 9436 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9437 1))
be256dc7
PZ		 9438 DRM_ERROR("D_COMP RCOMP still in progress\n");
9439
9440 if (allow_power_down) {
9441 val = I915_READ(LCPLL_CTL);
9442 val |= LCPLL_POWER_DOWN_ALLOW;
9443 I915_WRITE(LCPLL_CTL, val);
9444 POSTING_READ(LCPLL_CTL);
9445 }
9446}
9447
9448/*
9449 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9450 * source.
9451 */
6ff58d53 9452static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9453{
9454 uint32_t val;
9455
9456 val = I915_READ(LCPLL_CTL);
9457
9458 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9459 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9460 return;
9461
a8a8bd54
PZ		 9462 /*
9463 * Make sure we're not on PC8 state before disabling PC8, otherwise
9464 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9465 */
59bad947 9466 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9467
be256dc7
PZ		 9468 if (val & LCPLL_POWER_DOWN_ALLOW) {
9469 val &= ~LCPLL_POWER_DOWN_ALLOW;
9470 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9471 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9472 }
9473
9ccd5aeb 9474 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9475 val |= D_COMP_COMP_FORCE;
9476 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9477 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9478
9479 val = I915_READ(LCPLL_CTL);
9480 val &= ~LCPLL_PLL_DISABLE;
9481 I915_WRITE(LCPLL_CTL, val);
9482
9483 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9484 DRM_ERROR("LCPLL not locked yet\n");
9485
9486 if (val & LCPLL_CD_SOURCE_FCLK) {
9487 val = I915_READ(LCPLL_CTL);
9488 val &= ~LCPLL_CD_SOURCE_FCLK;
9489 I915_WRITE(LCPLL_CTL, val);
9490
9491 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9492 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9493 DRM_ERROR("Switching back to LCPLL failed\n");
9494 }
215733fa 9495
59bad947 9496 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9497 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9498}
9499
765dab67
PZ		 9500/*
9501 * Package states C8 and deeper are really deep PC states that can only be
9502 * reached when all the devices on the system allow it, so even if the graphics
9503 * device allows PC8+, it doesn't mean the system will actually get to these
9504 * states. Our driver only allows PC8+ when going into runtime PM.
9505 *
9506 * The requirements for PC8+ are that all the outputs are disabled, the power
9507 * well is disabled and most interrupts are disabled, and these are also
9508 * requirements for runtime PM. When these conditions are met, we manually do
9509 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9510 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9511 * hang the machine.
9512 *
9513 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9514 * the state of some registers, so when we come back from PC8+ we need to
9515 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9516 * need to take care of the registers kept by RC6. Notice that this happens even
9517 * if we don't put the device in PCI D3 state (which is what currently happens
9518 * because of the runtime PM support).
9519 *
9520 * For more, read "Display Sequences for Package C8" on the hardware
9521 * documentation.
9522 */
a14cb6fc 9523void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9524{
c67a470b
PZ		 9525 struct drm_device *dev = dev_priv->dev;
9526 uint32_t val;
9527
c67a470b
PZ		 9528 DRM_DEBUG_KMS("Enabling package C8+\n");
9529
c67a470b
PZ		 9530 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9531 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9532 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9533 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9534 }
9535
9536 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9537 hsw_disable_lcpll(dev_priv, true, true);
9538}
9539
a14cb6fc 9540void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9541{
9542 struct drm_device *dev = dev_priv->dev;
9543 uint32_t val;
9544
c67a470b
PZ		 9545 DRM_DEBUG_KMS("Disabling package C8+\n");
9546
9547 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9548 lpt_init_pch_refclk(dev);
9549
9550 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9551 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9552 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9553 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9554 }
9555
9556 intel_prepare_ddi(dev);
c67a470b
PZ		 9557}
9558
a821fc46 9559static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9560{
a821fc46 9561 struct drm_device *dev = old_state->dev;
f8437dd1 9562 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9563 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9564 int req_cdclk;
9565
9566 /* see the comment in valleyview_modeset_global_resources */
9567 if (WARN_ON(max_pixclk < 0))
9568 return;
9569
9570 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9571
9572 if (req_cdclk != dev_priv->cdclk_freq)
9573 broxton_set_cdclk(dev, req_cdclk);
9574}
9575
b432e5cf
VS		 9576/* compute the max rate for new configuration */
9577static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9578{
9579 struct drm_device *dev = dev_priv->dev;
9580 struct intel_crtc *intel_crtc;
9581 struct drm_crtc *crtc;
9582 int max_pixel_rate = 0;
9583 int pixel_rate;
9584
9585 for_each_crtc(dev, crtc) {
9586 if (!crtc->state->enable)
9587 continue;
9588
9589 intel_crtc = to_intel_crtc(crtc);
9590 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9591
9592 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9593 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9594 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9595
9596 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9597 }
9598
9599 return max_pixel_rate;
9600}
9601
9602static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9603{
9604 struct drm_i915_private *dev_priv = dev->dev_private;
9605 uint32_t val, data;
9606 int ret;
9607
9608 if (WARN((I915_READ(LCPLL_CTL) &
9609 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9610 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9611 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9612 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9613 "trying to change cdclk frequency with cdclk not enabled\n"))
9614 return;
9615
9616 mutex_lock(&dev_priv->rps.hw_lock);
9617 ret = sandybridge_pcode_write(dev_priv,
9618 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9619 mutex_unlock(&dev_priv->rps.hw_lock);
9620 if (ret) {
9621 DRM_ERROR("failed to inform pcode about cdclk change\n");
9622 return;
9623 }
9624
9625 val = I915_READ(LCPLL_CTL);
9626 val |= LCPLL_CD_SOURCE_FCLK;
9627 I915_WRITE(LCPLL_CTL, val);
9628
9629 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9630 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9631 DRM_ERROR("Switching to FCLK failed\n");
9632
9633 val = I915_READ(LCPLL_CTL);
9634 val &= ~LCPLL_CLK_FREQ_MASK;
9635
9636 switch (cdclk) {
9637 case 450000:
9638 val |= LCPLL_CLK_FREQ_450;
9639 data = 0;
9640 break;
9641 case 540000:
9642 val |= LCPLL_CLK_FREQ_54O_BDW;
9643 data = 1;
9644 break;
9645 case 337500:
9646 val |= LCPLL_CLK_FREQ_337_5_BDW;
9647 data = 2;
9648 break;
9649 case 675000:
9650 val |= LCPLL_CLK_FREQ_675_BDW;
9651 data = 3;
9652 break;
9653 default:
9654 WARN(1, "invalid cdclk frequency\n");
9655 return;
9656 }
9657
9658 I915_WRITE(LCPLL_CTL, val);
9659
9660 val = I915_READ(LCPLL_CTL);
9661 val &= ~LCPLL_CD_SOURCE_FCLK;
9662 I915_WRITE(LCPLL_CTL, val);
9663
9664 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9665 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9666 DRM_ERROR("Switching back to LCPLL failed\n");
9667
9668 mutex_lock(&dev_priv->rps.hw_lock);
9669 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9670 mutex_unlock(&dev_priv->rps.hw_lock);
9671
9672 intel_update_cdclk(dev);
9673
9674 WARN(cdclk != dev_priv->cdclk_freq,
9675 "cdclk requested %d kHz but got %d kHz\n",
9676 cdclk, dev_priv->cdclk_freq);
9677}
9678
9679static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9680 int max_pixel_rate)
9681{
9682 int cdclk;
9683
9684 /*
9685 * FIXME should also account for plane ratio
9686 * once 64bpp pixel formats are supported.
9687 */
9688 if (max_pixel_rate > 540000)
9689 cdclk = 675000;
9690 else if (max_pixel_rate > 450000)
9691 cdclk = 540000;
9692 else if (max_pixel_rate > 337500)
9693 cdclk = 450000;
9694 else
9695 cdclk = 337500;
9696
9697 /*
9698 * FIXME move the cdclk caclulation to
9699 * compute_config() so we can fail gracegully.
9700 */
9701 if (cdclk > dev_priv->max_cdclk_freq) {
9702 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9703 cdclk, dev_priv->max_cdclk_freq);
9704 cdclk = dev_priv->max_cdclk_freq;
9705 }
9706
9707 return cdclk;
9708}
9709
9710static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9711{
9712 struct drm_i915_private *dev_priv = to_i915(state->dev);
9713 struct drm_crtc *crtc;
9714 struct drm_crtc_state *crtc_state;
9715 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9716 int cdclk, i;
9717
9718 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9719
9720 if (cdclk == dev_priv->cdclk_freq)
9721 return 0;
9722
9723 /* add all active pipes to the state */
9724 for_each_crtc(state->dev, crtc) {
9725 if (!crtc->state->enable)
9726 continue;
9727
9728 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9729 if (IS_ERR(crtc_state))
9730 return PTR_ERR(crtc_state);
9731 }
9732
9733 /* disable/enable all currently active pipes while we change cdclk */
9734 for_each_crtc_in_state(state, crtc, crtc_state, i)
9735 if (crtc_state->enable)
9736 crtc_state->mode_changed = true;
9737
9738 return 0;
9739}
9740
9741static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9742{
9743 struct drm_device *dev = state->dev;
9744 struct drm_i915_private *dev_priv = dev->dev_private;
9745 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9746 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9747
9748 if (req_cdclk != dev_priv->cdclk_freq)
9749 broadwell_set_cdclk(dev, req_cdclk);
9750}
9751
190f68c5
ACO		 9752static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9753 struct intel_crtc_state *crtc_state)
09b4ddf9 9754{
190f68c5 9755 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9756 return -EINVAL;
716c2e55 9757
c7653199 9758 crtc->lowfreq_avail = false;
644cef34 9759
c8f7a0db 9760 return 0;
79e53945
JB		 9761}
9762
3760b59c
S		 9763static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9764 enum port port,
9765 struct intel_crtc_state *pipe_config)
9766{
9767 switch (port) {
9768 case PORT_A:
9769 pipe_config->ddi_pll_sel = SKL_DPLL0;
9770 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9771 break;
9772 case PORT_B:
9773 pipe_config->ddi_pll_sel = SKL_DPLL1;
9774 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9775 break;
9776 case PORT_C:
9777 pipe_config->ddi_pll_sel = SKL_DPLL2;
9778 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9779 break;
9780 default:
9781 DRM_ERROR("Incorrect port type\n");
9782 }
9783}
9784
96b7dfb7
S		 9785static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9786 enum port port,
5cec258b 9787 struct intel_crtc_state *pipe_config)
96b7dfb7 9788{
3148ade7 9789 u32 temp, dpll_ctl1;
96b7dfb7
S		 9790
9791 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9792 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9793
9794 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9795 case SKL_DPLL0:
9796 /*
9797 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9798 * of the shared DPLL framework and thus needs to be read out
9799 * separately
9800 */
9801 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9802 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9803 break;
96b7dfb7
S		 9804 case SKL_DPLL1:
9805 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9806 break;
9807 case SKL_DPLL2:
9808 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9809 break;
9810 case SKL_DPLL3:
9811 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9812 break;
96b7dfb7
S		 9813 }
9814}
9815
7d2c8175
DL		 9816static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9817 enum port port,
5cec258b 9818 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9819{
9820 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9821
9822 switch (pipe_config->ddi_pll_sel) {
9823 case PORT_CLK_SEL_WRPLL1:
9824 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9825 break;
9826 case PORT_CLK_SEL_WRPLL2:
9827 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9828 break;
9829 }
9830}
9831
26804afd 9832static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9833 struct intel_crtc_state *pipe_config)
26804afd
DV		 9834{
9835 struct drm_device *dev = crtc->base.dev;
9836 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9837 struct intel_shared_dpll *pll;
26804afd
DV		 9838 enum port port;
9839 uint32_t tmp;
9840
9841 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9842
9843 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9844
96b7dfb7
S		 9845 if (IS_SKYLAKE(dev))
9846 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9847 else if (IS_BROXTON(dev))
9848 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9849 else
9850 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9851
d452c5b6
DV		 9852 if (pipe_config->shared_dpll >= 0) {
9853 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9854
9855 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9856 &pipe_config->dpll_hw_state));
9857 }
9858
26804afd
DV		 9859 /*
9860 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9861 * DDI E. So just check whether this pipe is wired to DDI E and whether
9862 * the PCH transcoder is on.
9863 */
ca370455
DL		 9864 if (INTEL_INFO(dev)->gen < 9 &&
9865 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9866 pipe_config->has_pch_encoder = true;
9867
9868 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9869 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9870 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9871
9872 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9873 }
9874}
9875
0e8ffe1b 9876static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9877 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9878{
9879 struct drm_device *dev = crtc->base.dev;
9880 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9881 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9882 uint32_t tmp;
9883
f458ebbc 9884 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9885 POWER_DOMAIN_PIPE(crtc->pipe)))
9886 return false;
9887
e143a21c 9888 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9889 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9890
eccb140b
DV		 9891 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9892 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9893 enum pipe trans_edp_pipe;
9894 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9895 default:
9896 WARN(1, "unknown pipe linked to edp transcoder\n");
9897 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9898 case TRANS_DDI_EDP_INPUT_A_ON:
9899 trans_edp_pipe = PIPE_A;
9900 break;
9901 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9902 trans_edp_pipe = PIPE_B;
9903 break;
9904 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9905 trans_edp_pipe = PIPE_C;
9906 break;
9907 }
9908
9909 if (trans_edp_pipe == crtc->pipe)
9910 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9911 }
9912
f458ebbc 9913 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9914 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9915 return false;
9916
eccb140b 9917 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9918 if (!(tmp & PIPECONF_ENABLE))
9919 return false;
9920
26804afd 9921 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9922
1bd1bd80
DV		 9923 intel_get_pipe_timings(crtc, pipe_config);
9924
a1b2278e
CK		 9925 if (INTEL_INFO(dev)->gen >= 9) {
9926 skl_init_scalers(dev, crtc, pipe_config);
9927 }
9928
2fa2fe9a 9929 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9930
9931 if (INTEL_INFO(dev)->gen >= 9) {
9932 pipe_config->scaler_state.scaler_id = -1;
9933 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9934 }
9935
bd2e244f 9936 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9937 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9938 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9939 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9940 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9941 else
9942 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9943 }
88adfff1 9944
e59150dc
JB		 9945 if (IS_HASWELL(dev))
9946 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9947 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9948
ebb69c95
CT		 9949 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9950 pipe_config->pixel_multiplier =
9951 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9952 } else {
9953 pipe_config->pixel_multiplier = 1;
9954 }
6c49f241 9955
0e8ffe1b
DV		 9956 return true;
9957}
9958
560b85bb
CW		 9959static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9960{
9961 struct drm_device *dev = crtc->dev;
9962 struct drm_i915_private *dev_priv = dev->dev_private;
9963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9964 uint32_t cntl = 0, size = 0;
560b85bb 9965
dc41c154 9966 if (base) {
3dd512fb
MR		 9967 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9968 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9969 unsigned int stride = roundup_pow_of_two(width) * 4;
9970
9971 switch (stride) {
9972 default:
9973 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9974 width, stride);
9975 stride = 256;
9976 /* fallthrough */
9977 case 256:
9978 case 512:
9979 case 1024:
9980 case 2048:
9981 break;
4b0e333e
CW		 9982 }
9983
dc41c154
VS		 9984 cntl |= CURSOR_ENABLE |
9985 CURSOR_GAMMA_ENABLE |
9986 CURSOR_FORMAT_ARGB |
9987 CURSOR_STRIDE(stride);
9988
9989 size = (height << 12) | width;
4b0e333e 9990 }
560b85bb 9991
dc41c154
VS		 9992 if (intel_crtc->cursor_cntl != 0 &&
9993 (intel_crtc->cursor_base != base ||
9994 intel_crtc->cursor_size != size ||
9995 intel_crtc->cursor_cntl != cntl)) {
9996 /* On these chipsets we can only modify the base/size/stride
9997 * whilst the cursor is disabled.
9998 */
9999 I915_WRITE(_CURACNTR, 0);
4b0e333e 10000 POSTING_READ(_CURACNTR);
dc41c154 10001 intel_crtc->cursor_cntl = 0;
4b0e333e 10002 }
560b85bb 10003
99d1f387 10004 if (intel_crtc->cursor_base != base) {
9db4a9c7 10005 I915_WRITE(_CURABASE, base);
99d1f387
VS		 10006 intel_crtc->cursor_base = base;
10007 }
4726e0b0 10008
dc41c154
VS		 10009 if (intel_crtc->cursor_size != size) {
10010 I915_WRITE(CURSIZE, size);
10011 intel_crtc->cursor_size = size;
4b0e333e 10012 }
560b85bb 10013
4b0e333e 10014 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 10015 I915_WRITE(_CURACNTR, cntl);
10016 POSTING_READ(_CURACNTR);
4b0e333e 10017 intel_crtc->cursor_cntl = cntl;
560b85bb 10018 }
560b85bb
CW		 10019}
10020
560b85bb 10021static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 10022{
10023 struct drm_device *dev = crtc->dev;
10024 struct drm_i915_private *dev_priv = dev->dev_private;
10025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10026 int pipe = intel_crtc->pipe;
4b0e333e
CW		 10027 uint32_t cntl;
10028
10029 cntl = 0;
10030 if (base) {
10031 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 10032 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 10033 case 64:
10034 cntl |= CURSOR_MODE_64_ARGB_AX;
10035 break;
10036 case 128:
10037 cntl |= CURSOR_MODE_128_ARGB_AX;
10038 break;
10039 case 256:
10040 cntl |= CURSOR_MODE_256_ARGB_AX;
10041 break;
10042 default:
3dd512fb 10043 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 10044 return;
65a21cd6 10045 }
4b0e333e 10046 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 10047
10048 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10049 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 10050 }
65a21cd6 10051
8e7d688b 10052 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 10053 cntl |= CURSOR_ROTATE_180;
10054
4b0e333e
CW		 10055 if (intel_crtc->cursor_cntl != cntl) {
10056 I915_WRITE(CURCNTR(pipe), cntl);
10057 POSTING_READ(CURCNTR(pipe));
10058 intel_crtc->cursor_cntl = cntl;
65a21cd6 10059 }
4b0e333e 10060
65a21cd6 10061 /* and commit changes on next vblank */
5efb3e28
VS		 10062 I915_WRITE(CURBASE(pipe), base);
10063 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 10064
10065 intel_crtc->cursor_base = base;
65a21cd6
JB		 10066}
10067
cda4b7d3 10068/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 10069static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10070 bool on)
cda4b7d3
CW		 10071{
10072 struct drm_device *dev = crtc->dev;
10073 struct drm_i915_private *dev_priv = dev->dev_private;
10074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10075 int pipe = intel_crtc->pipe;
3d7d6510
MR		 10076 int x = crtc->cursor_x;
10077 int y = crtc->cursor_y;
d6e4db15 10078 u32 base = 0, pos = 0;
cda4b7d3 10079
d6e4db15 10080 if (on)
cda4b7d3 10081 base = intel_crtc->cursor_addr;
cda4b7d3 10082
6e3c9717 10083 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 10084 base = 0;
10085
6e3c9717 10086 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 10087 base = 0;
10088
10089 if (x < 0) {
3dd512fb 10090 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 10091 base = 0;
10092
10093 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10094 x = -x;
10095 }
10096 pos |= x << CURSOR_X_SHIFT;
10097
10098 if (y < 0) {
3dd512fb 10099 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 10100 base = 0;
10101
10102 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10103 y = -y;
10104 }
10105 pos |= y << CURSOR_Y_SHIFT;
10106
4b0e333e 10107 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10108 return;
10109
5efb3e28
VS		 10110 I915_WRITE(CURPOS(pipe), pos);
10111
4398ad45
VS		 10112 /* ILK+ do this automagically */
10113 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10114 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 10115 base += (intel_crtc->base.cursor->state->crtc_h *
10116 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 10117 }
10118
8ac54669 10119 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10120 i845_update_cursor(crtc, base);
10121 else
10122 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10123}
10124
dc41c154
VS		 10125static bool cursor_size_ok(struct drm_device *dev,
10126 uint32_t width, uint32_t height)
10127{
10128 if (width == 0 || height == 0)
10129 return false;
10130
10131 /*
10132 * 845g/865g are special in that they are only limited by
10133 * the width of their cursors, the height is arbitrary up to
10134 * the precision of the register. Everything else requires
10135 * square cursors, limited to a few power-of-two sizes.
10136 */
10137 if (IS_845G(dev) || IS_I865G(dev)) {
10138 if ((width & 63) != 0)
10139 return false;
10140
10141 if (width > (IS_845G(dev) ? 64 : 512))
10142 return false;
10143
10144 if (height > 1023)
10145 return false;
10146 } else {
10147 switch (width | height) {
10148 case 256:
10149 case 128:
10150 if (IS_GEN2(dev))
10151 return false;
10152 case 64:
10153 break;
10154 default:
10155 return false;
10156 }
10157 }
10158
10159 return true;
10160}
10161
79e53945 10162static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10163 u16 *blue, uint32_t start, uint32_t size)
79e53945 10164{
7203425a 10165 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10167
7203425a 10168 for (i = start; i < end; i++) {
79e53945
JB		 10169 intel_crtc->lut_r[i] = red[i] >> 8;
10170 intel_crtc->lut_g[i] = green[i] >> 8;
10171 intel_crtc->lut_b[i] = blue[i] >> 8;
10172 }
10173
10174 intel_crtc_load_lut(crtc);
10175}
10176
79e53945
JB		 10177/* VESA 640x480x72Hz mode to set on the pipe */
10178static struct drm_display_mode load_detect_mode = {
10179 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10180 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10181};
10182
a8bb6818
DV		 10183struct drm_framebuffer *
10184__intel_framebuffer_create(struct drm_device *dev,
10185 struct drm_mode_fb_cmd2 *mode_cmd,
10186 struct drm_i915_gem_object *obj)
d2dff872
CW		 10187{
10188 struct intel_framebuffer *intel_fb;
10189 int ret;
10190
10191 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10192 if (!intel_fb) {
6ccb81f2 10193 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10194 return ERR_PTR(-ENOMEM);
10195 }
10196
10197 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10198 if (ret)
10199 goto err;
d2dff872
CW		 10200
10201 return &intel_fb->base;
dd4916c5 10202err:
6ccb81f2 10203 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10204 kfree(intel_fb);
10205
10206 return ERR_PTR(ret);
d2dff872
CW		 10207}
10208
b5ea642a 10209static struct drm_framebuffer *
a8bb6818
DV		 10210intel_framebuffer_create(struct drm_device *dev,
10211 struct drm_mode_fb_cmd2 *mode_cmd,
10212 struct drm_i915_gem_object *obj)
10213{
10214 struct drm_framebuffer *fb;
10215 int ret;
10216
10217 ret = i915_mutex_lock_interruptible(dev);
10218 if (ret)
10219 return ERR_PTR(ret);
10220 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10221 mutex_unlock(&dev->struct_mutex);
10222
10223 return fb;
10224}
10225
d2dff872
CW		 10226static u32
10227intel_framebuffer_pitch_for_width(int width, int bpp)
10228{
10229 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10230 return ALIGN(pitch, 64);
10231}
10232
10233static u32
10234intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10235{
10236 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10237 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10238}
10239
10240static struct drm_framebuffer *
10241intel_framebuffer_create_for_mode(struct drm_device *dev,
10242 struct drm_display_mode *mode,
10243 int depth, int bpp)
10244{
10245 struct drm_i915_gem_object *obj;
0fed39bd 10246 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10247
10248 obj = i915_gem_alloc_object(dev,
10249 intel_framebuffer_size_for_mode(mode, bpp));
10250 if (obj == NULL)
10251 return ERR_PTR(-ENOMEM);
10252
10253 mode_cmd.width = mode->hdisplay;
10254 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10255 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10256 bpp);
5ca0c34a 10257 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10258
10259 return intel_framebuffer_create(dev, &mode_cmd, obj);
10260}
10261
10262static struct drm_framebuffer *
10263mode_fits_in_fbdev(struct drm_device *dev,
10264 struct drm_display_mode *mode)
10265{
4520f53a 10266#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10267 struct drm_i915_private *dev_priv = dev->dev_private;
10268 struct drm_i915_gem_object *obj;
10269 struct drm_framebuffer *fb;
10270
4c0e5528 10271 if (!dev_priv->fbdev)
d2dff872
CW		 10272 return NULL;
10273
4c0e5528 10274 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10275 return NULL;
10276
4c0e5528
DV		 10277 obj = dev_priv->fbdev->fb->obj;
10278 BUG_ON(!obj);
10279
8bcd4553 10280 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10281 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10282 fb->bits_per_pixel))
d2dff872
CW		 10283 return NULL;
10284
01f2c773 10285 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10286 return NULL;
10287
10288 return fb;
4520f53a
DV		 10289#else
10290 return NULL;
10291#endif
d2dff872
CW		 10292}
10293
d3a40d1b
ACO		 10294static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10295 struct drm_crtc *crtc,
10296 struct drm_display_mode *mode,
10297 struct drm_framebuffer *fb,
10298 int x, int y)
10299{
10300 struct drm_plane_state *plane_state;
10301 int hdisplay, vdisplay;
10302 int ret;
10303
10304 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10305 if (IS_ERR(plane_state))
10306 return PTR_ERR(plane_state);
10307
10308 if (mode)
10309 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10310 else
10311 hdisplay = vdisplay = 0;
10312
10313 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10314 if (ret)
10315 return ret;
10316 drm_atomic_set_fb_for_plane(plane_state, fb);
10317 plane_state->crtc_x = 0;
10318 plane_state->crtc_y = 0;
10319 plane_state->crtc_w = hdisplay;
10320 plane_state->crtc_h = vdisplay;
10321 plane_state->src_x = x << 16;
10322 plane_state->src_y = y << 16;
10323 plane_state->src_w = hdisplay << 16;
10324 plane_state->src_h = vdisplay << 16;
10325
10326 return 0;
10327}
10328
d2434ab7 10329bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10330 struct drm_display_mode *mode,
51fd371b
RC		 10331 struct intel_load_detect_pipe *old,
10332 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10333{
10334 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10335 struct intel_encoder *intel_encoder =
10336 intel_attached_encoder(connector);
79e53945 10337 struct drm_crtc *possible_crtc;
4ef69c7a 10338 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10339 struct drm_crtc *crtc = NULL;
10340 struct drm_device *dev = encoder->dev;
94352cf9 10341 struct drm_framebuffer *fb;
51fd371b 10342 struct drm_mode_config *config = &dev->mode_config;
83a57153 10343 struct drm_atomic_state *state = NULL;
944b0c76 10344 struct drm_connector_state *connector_state;
4be07317 10345 struct intel_crtc_state *crtc_state;
51fd371b 10346 int ret, i = -1;
79e53945 10347
d2dff872 10348 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10349 connector->base.id, connector->name,
8e329a03 10350 encoder->base.id, encoder->name);
d2dff872 10351
51fd371b
RC		 10352retry:
10353 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10354 if (ret)
10355 goto fail_unlock;
6e9f798d 10356
79e53945
JB		 10357 /*
10358 * Algorithm gets a little messy:
7a5e4805 10359 *
79e53945
JB		 10360 * - if the connector already has an assigned crtc, use it (but make
10361 * sure it's on first)
7a5e4805 10362 *
79e53945
JB		 10363 * - try to find the first unused crtc that can drive this connector,
10364 * and use that if we find one
79e53945
JB		 10365 */
10366
10367 /* See if we already have a CRTC for this connector */
10368 if (encoder->crtc) {
10369 crtc = encoder->crtc;
8261b191 10370
51fd371b 10371 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10372 if (ret)
10373 goto fail_unlock;
10374 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10375 if (ret)
10376 goto fail_unlock;
7b24056b 10377
24218aac 10378 old->dpms_mode = connector->dpms;
8261b191
CW		 10379 old->load_detect_temp = false;
10380
10381 /* Make sure the crtc and connector are running */
24218aac
DV		 10382 if (connector->dpms != DRM_MODE_DPMS_ON)
10383 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10384
7173188d 10385 return true;
79e53945
JB		 10386 }
10387
10388 /* Find an unused one (if possible) */
70e1e0ec 10389 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10390 i++;
10391 if (!(encoder->possible_crtcs & (1 << i)))
10392 continue;
83d65738 10393 if (possible_crtc->state->enable)
a459249c
VS		 10394 continue;
10395 /* This can occur when applying the pipe A quirk on resume. */
10396 if (to_intel_crtc(possible_crtc)->new_enabled)
10397 continue;
10398
10399 crtc = possible_crtc;
10400 break;
79e53945
JB		 10401 }
10402
10403 /*
10404 * If we didn't find an unused CRTC, don't use any.
10405 */
10406 if (!crtc) {
7173188d 10407 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10408 goto fail_unlock;
79e53945
JB		 10409 }
10410
51fd371b
RC		 10411 ret = drm_modeset_lock(&crtc->mutex, ctx);
10412 if (ret)
4d02e2de
DV		 10413 goto fail_unlock;
10414 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10415 if (ret)
51fd371b 10416 goto fail_unlock;
fc303101
DV		 10417 intel_encoder->new_crtc = to_intel_crtc(crtc);
10418 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10419
10420 intel_crtc = to_intel_crtc(crtc);
412b61d8 10421 intel_crtc->new_enabled = true;
24218aac 10422 old->dpms_mode = connector->dpms;
8261b191 10423 old->load_detect_temp = true;
d2dff872 10424 old->release_fb = NULL;
79e53945 10425
83a57153
ACO		 10426 state = drm_atomic_state_alloc(dev);
10427 if (!state)
10428 return false;
10429
10430 state->acquire_ctx = ctx;
10431
944b0c76
ACO		 10432 connector_state = drm_atomic_get_connector_state(state, connector);
10433 if (IS_ERR(connector_state)) {
10434 ret = PTR_ERR(connector_state);
10435 goto fail;
10436 }
10437
10438 connector_state->crtc = crtc;
10439 connector_state->best_encoder = &intel_encoder->base;
10440
4be07317
ACO		 10441 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10442 if (IS_ERR(crtc_state)) {
10443 ret = PTR_ERR(crtc_state);
10444 goto fail;
10445 }
10446
49d6fa21 10447 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10448
6492711d
CW		 10449 if (!mode)
10450 mode = &load_detect_mode;
79e53945 10451
d2dff872
CW		 10452 /* We need a framebuffer large enough to accommodate all accesses
10453 * that the plane may generate whilst we perform load detection.
10454 * We can not rely on the fbcon either being present (we get called
10455 * during its initialisation to detect all boot displays, or it may
10456 * not even exist) or that it is large enough to satisfy the
10457 * requested mode.
10458 */
94352cf9
DV		 10459 fb = mode_fits_in_fbdev(dev, mode);
10460 if (fb == NULL) {
d2dff872 10461 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10462 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10463 old->release_fb = fb;
d2dff872
CW		 10464 } else
10465 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10466 if (IS_ERR(fb)) {
d2dff872 10467 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10468 goto fail;
79e53945 10469 }
79e53945 10470
d3a40d1b
ACO		 10471 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10472 if (ret)
10473 goto fail;
10474
8c7b5ccb
ACO		 10475 drm_mode_copy(&crtc_state->base.mode, mode);
10476
10477 if (intel_set_mode(crtc, state)) {
6492711d 10478 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10479 if (old->release_fb)
10480 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10481 goto fail;
79e53945 10482 }
9128b040 10483 crtc->primary->crtc = crtc;
7173188d 10484
79e53945 10485 /* let the connector get through one full cycle before testing */
9d0498a2 10486 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10487 return true;
412b61d8
VS		 10488
10489 fail:
83d65738 10490 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10491fail_unlock:
e5d958ef
ACO		 10492 drm_atomic_state_free(state);
10493 state = NULL;
83a57153 10494
51fd371b
RC		 10495 if (ret == -EDEADLK) {
10496 drm_modeset_backoff(ctx);
10497 goto retry;
10498 }
10499
412b61d8 10500 return false;
79e53945
JB		 10501}
10502
d2434ab7 10503void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10504 struct intel_load_detect_pipe *old,
10505 struct drm_modeset_acquire_ctx *ctx)
79e53945 10506{
83a57153 10507 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10508 struct intel_encoder *intel_encoder =
10509 intel_attached_encoder(connector);
4ef69c7a 10510 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10511 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10513 struct drm_atomic_state *state;
944b0c76 10514 struct drm_connector_state *connector_state;
4be07317 10515 struct intel_crtc_state *crtc_state;
d3a40d1b 10516 int ret;
79e53945 10517
d2dff872 10518 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10519 connector->base.id, connector->name,
8e329a03 10520 encoder->base.id, encoder->name);
d2dff872 10521
8261b191 10522 if (old->load_detect_temp) {
83a57153 10523 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10524 if (!state)
10525 goto fail;
83a57153
ACO		 10526
10527 state->acquire_ctx = ctx;
10528
944b0c76
ACO		 10529 connector_state = drm_atomic_get_connector_state(state, connector);
10530 if (IS_ERR(connector_state))
10531 goto fail;
10532
4be07317
ACO		 10533 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10534 if (IS_ERR(crtc_state))
10535 goto fail;
10536
fc303101
DV		 10537 to_intel_connector(connector)->new_encoder = NULL;
10538 intel_encoder->new_crtc = NULL;
412b61d8 10539 intel_crtc->new_enabled = false;
944b0c76
ACO		 10540
10541 connector_state->best_encoder = NULL;
10542 connector_state->crtc = NULL;
10543
49d6fa21 10544 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10545
d3a40d1b
ACO		 10546 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10547 0, 0);
10548 if (ret)
10549 goto fail;
10550
2bfb4627
ACO		 10551 ret = intel_set_mode(crtc, state);
10552 if (ret)
10553 goto fail;
d2dff872 10554
36206361
DV		 10555 if (old->release_fb) {
10556 drm_framebuffer_unregister_private(old->release_fb);
10557 drm_framebuffer_unreference(old->release_fb);
10558 }
d2dff872 10559
0622a53c 10560 return;
79e53945
JB		 10561 }
10562
c751ce4f 10563 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10564 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10565 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10566
10567 return;
10568fail:
10569 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10570 drm_atomic_state_free(state);
79e53945
JB		 10571}
10572
da4a1efa 10573static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10574 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10575{
10576 struct drm_i915_private *dev_priv = dev->dev_private;
10577 u32 dpll = pipe_config->dpll_hw_state.dpll;
10578
10579 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10580 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10581 else if (HAS_PCH_SPLIT(dev))
10582 return 120000;
10583 else if (!IS_GEN2(dev))
10584 return 96000;
10585 else
10586 return 48000;
10587}
10588
79e53945 10589/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10590static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10591 struct intel_crtc_state *pipe_config)
79e53945 10592{
f1f644dc 10593 struct drm_device *dev = crtc->base.dev;
79e53945 10594 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10595 int pipe = pipe_config->cpu_transcoder;
293623f7 10596 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10597 u32 fp;
10598 intel_clock_t clock;
da4a1efa 10599 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10600
10601 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10602 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10603 else
293623f7 10604 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10605
10606 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10607 if (IS_PINEVIEW(dev)) {
10608 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10609 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10610 } else {
10611 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10612 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10613 }
10614
a6c45cf0 10615 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10616 if (IS_PINEVIEW(dev))
10617 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10618 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10619 else
10620 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10621 DPLL_FPA01_P1_POST_DIV_SHIFT);
10622
10623 switch (dpll & DPLL_MODE_MASK) {
10624 case DPLLB_MODE_DAC_SERIAL:
10625 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10626 5 : 10;
10627 break;
10628 case DPLLB_MODE_LVDS:
10629 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10630 7 : 14;
10631 break;
10632 default:
28c97730 10633 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10634 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10635 return;
79e53945
JB		 10636 }
10637
ac58c3f0 10638 if (IS_PINEVIEW(dev))
da4a1efa 10639 pineview_clock(refclk, &clock);
ac58c3f0 10640 else
da4a1efa 10641 i9xx_clock(refclk, &clock);
79e53945 10642 } else {
0fb58223 10643 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10644 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10645
10646 if (is_lvds) {
10647 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10648 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10649
10650 if (lvds & LVDS_CLKB_POWER_UP)
10651 clock.p2 = 7;
10652 else
10653 clock.p2 = 14;
79e53945
JB		 10654 } else {
10655 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10656 clock.p1 = 2;
10657 else {
10658 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10659 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10660 }
10661 if (dpll & PLL_P2_DIVIDE_BY_4)
10662 clock.p2 = 4;
10663 else
10664 clock.p2 = 2;
79e53945 10665 }
da4a1efa
VS		 10666
10667 i9xx_clock(refclk, &clock);
79e53945
JB		 10668 }
10669
18442d08
VS		 10670 /*
10671 * This value includes pixel_multiplier. We will use
241bfc38 10672 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10673 * encoder's get_config() function.
10674 */
10675 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10676}
10677
6878da05
VS		 10678int intel_dotclock_calculate(int link_freq,
10679 const struct intel_link_m_n *m_n)
f1f644dc 10680{
f1f644dc
JB		 10681 /*
10682 * The calculation for the data clock is:
1041a02f 10683 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10684 * But we want to avoid losing precison if possible, so:
1041a02f 10685 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10686 *
10687 * and the link clock is simpler:
1041a02f 10688 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10689 */
10690
6878da05
VS		 10691 if (!m_n->link_n)
10692 return 0;
f1f644dc 10693
6878da05
VS		 10694 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10695}
f1f644dc 10696
18442d08 10697static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10698 struct intel_crtc_state *pipe_config)
6878da05
VS		 10699{
10700 struct drm_device *dev = crtc->base.dev;
79e53945 10701
18442d08
VS		 10702 /* read out port_clock from the DPLL */
10703 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10704
f1f644dc 10705 /*
18442d08 10706 * This value does not include pixel_multiplier.
241bfc38 10707 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10708 * agree once we know their relationship in the encoder's
10709 * get_config() function.
79e53945 10710 */
2d112de7 10711 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10712 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10713 &pipe_config->fdi_m_n);
79e53945
JB		 10714}
10715
10716/** Returns the currently programmed mode of the given pipe. */
10717struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10718 struct drm_crtc *crtc)
10719{
548f245b 10720 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10722 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10723 struct drm_display_mode *mode;
5cec258b 10724 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10725 int htot = I915_READ(HTOTAL(cpu_transcoder));
10726 int hsync = I915_READ(HSYNC(cpu_transcoder));
10727 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10728 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10729 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10730
10731 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10732 if (!mode)
10733 return NULL;
10734
f1f644dc
JB		 10735 /*
10736 * Construct a pipe_config sufficient for getting the clock info
10737 * back out of crtc_clock_get.
10738 *
10739 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10740 * to use a real value here instead.
10741 */
293623f7 10742 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10743 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10744 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10745 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10746 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10747 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10748
773ae034 10749 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10750 mode->hdisplay = (htot & 0xffff) + 1;
10751 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10752 mode->hsync_start = (hsync & 0xffff) + 1;
10753 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10754 mode->vdisplay = (vtot & 0xffff) + 1;
10755 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10756 mode->vsync_start = (vsync & 0xffff) + 1;
10757 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10758
10759 drm_mode_set_name(mode);
79e53945
JB		 10760
10761 return mode;
10762}
10763
652c393a
JB		 10764static void intel_decrease_pllclock(struct drm_crtc *crtc)
10765{
10766 struct drm_device *dev = crtc->dev;
fbee40df 10767 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10769
baff296c 10770 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10771 return;
10772
10773 if (!dev_priv->lvds_downclock_avail)
10774 return;
10775
10776 /*
10777 * Since this is called by a timer, we should never get here in
10778 * the manual case.
10779 */
10780 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10781 int pipe = intel_crtc->pipe;
10782 int dpll_reg = DPLL(pipe);
10783 int dpll;
f6e5b160 10784
44d98a61 10785 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10786
8ac5a6d5 10787 assert_panel_unlocked(dev_priv, pipe);
652c393a 10788
dc257cf1 10789 dpll = I915_READ(dpll_reg);
652c393a
JB		 10790 dpll |= DISPLAY_RATE_SELECT_FPA1;
10791 I915_WRITE(dpll_reg, dpll);
9d0498a2 10792 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10793 dpll = I915_READ(dpll_reg);
10794 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10795 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10796 }
10797
10798}
10799
f047e395
CW		 10800void intel_mark_busy(struct drm_device *dev)
10801{
c67a470b
PZ		 10802 struct drm_i915_private *dev_priv = dev->dev_private;
10803
f62a0076
CW		 10804 if (dev_priv->mm.busy)
10805 return;
10806
43694d69 10807 intel_runtime_pm_get(dev_priv);
c67a470b 10808 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10809 if (INTEL_INFO(dev)->gen >= 6)
10810 gen6_rps_busy(dev_priv);
f62a0076 10811 dev_priv->mm.busy = true;
f047e395
CW		 10812}
10813
10814void intel_mark_idle(struct drm_device *dev)
652c393a 10815{
c67a470b 10816 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10817 struct drm_crtc *crtc;
652c393a 10818
f62a0076
CW		 10819 if (!dev_priv->mm.busy)
10820 return;
10821
10822 dev_priv->mm.busy = false;
10823
70e1e0ec 10824 for_each_crtc(dev, crtc) {
f4510a27 10825 if (!crtc->primary->fb)
652c393a
JB		 10826 continue;
10827
725a5b54 10828 intel_decrease_pllclock(crtc);
652c393a 10829 }
b29c19b6 10830
3d13ef2e 10831 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10832 gen6_rps_idle(dev->dev_private);
bb4cdd53 10833
43694d69 10834 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10835}
10836
79e53945
JB		 10837static void intel_crtc_destroy(struct drm_crtc *crtc)
10838{
10839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10840 struct drm_device *dev = crtc->dev;
10841 struct intel_unpin_work *work;
67e77c5a 10842
5e2d7afc 10843 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10844 work = intel_crtc->unpin_work;
10845 intel_crtc->unpin_work = NULL;
5e2d7afc 10846 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10847
10848 if (work) {
10849 cancel_work_sync(&work->work);
10850 kfree(work);
10851 }
79e53945
JB		 10852
10853 drm_crtc_cleanup(crtc);
67e77c5a 10854
79e53945
JB		 10855 kfree(intel_crtc);
10856}
10857
6b95a207
KH		 10858static void intel_unpin_work_fn(struct work_struct *__work)
10859{
10860 struct intel_unpin_work *work =
10861 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10862 struct drm_device *dev = work->crtc->dev;
f99d7069 10863 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10864
b4a98e57 10865 mutex_lock(&dev->struct_mutex);
82bc3b2d 10866 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10867 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10868
7ff0ebcc 10869 intel_fbc_update(dev);
f06cc1b9
JH		 10870
10871 if (work->flip_queued_req)
146d84f0 10872 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10873 mutex_unlock(&dev->struct_mutex);
10874
f99d7069 10875 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10876 drm_framebuffer_unreference(work->old_fb);
f99d7069 10877
b4a98e57
CW		 10878 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10879 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10880
6b95a207
KH		 10881 kfree(work);
10882}
10883
1afe3e9d 10884static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10885 struct drm_crtc *crtc)
6b95a207 10886{
6b95a207
KH		 10887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10888 struct intel_unpin_work *work;
6b95a207
KH		 10889 unsigned long flags;
10890
10891 /* Ignore early vblank irqs */
10892 if (intel_crtc == NULL)
10893 return;
10894
f326038a
DV		 10895 /*
10896 * This is called both by irq handlers and the reset code (to complete
10897 * lost pageflips) so needs the full irqsave spinlocks.
10898 */
6b95a207
KH		 10899 spin_lock_irqsave(&dev->event_lock, flags);
10900 work = intel_crtc->unpin_work;
e7d841ca
CW		 10901
10902 /* Ensure we don't miss a work->pending update ... */
10903 smp_rmb();
10904
10905 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10906 spin_unlock_irqrestore(&dev->event_lock, flags);
10907 return;
10908 }
10909
d6bbafa1 10910 page_flip_completed(intel_crtc);
0af7e4df 10911
6b95a207 10912 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10913}
10914
1afe3e9d
JB		 10915void intel_finish_page_flip(struct drm_device *dev, int pipe)
10916{
fbee40df 10917 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10918 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10919
49b14a5c 10920 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10921}
10922
10923void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10924{
fbee40df 10925 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10926 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10927
49b14a5c 10928 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10929}
10930
75f7f3ec
VS		 10931/* Is 'a' after or equal to 'b'? */
10932static bool g4x_flip_count_after_eq(u32 a, u32 b)
10933{
10934 return !((a - b) & 0x80000000);
10935}
10936
10937static bool page_flip_finished(struct intel_crtc *crtc)
10938{
10939 struct drm_device *dev = crtc->base.dev;
10940 struct drm_i915_private *dev_priv = dev->dev_private;
10941
bdfa7542
VS		 10942 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10943 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10944 return true;
10945
75f7f3ec
VS		 10946 /*
10947 * The relevant registers doen't exist on pre-ctg.
10948 * As the flip done interrupt doesn't trigger for mmio
10949 * flips on gmch platforms, a flip count check isn't
10950 * really needed there. But since ctg has the registers,
10951 * include it in the check anyway.
10952 */
10953 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10954 return true;
10955
10956 /*
10957 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10958 * used the same base address. In that case the mmio flip might
10959 * have completed, but the CS hasn't even executed the flip yet.
10960 *
10961 * A flip count check isn't enough as the CS might have updated
10962 * the base address just after start of vblank, but before we
10963 * managed to process the interrupt. This means we'd complete the
10964 * CS flip too soon.
10965 *
10966 * Combining both checks should get us a good enough result. It may
10967 * still happen that the CS flip has been executed, but has not
10968 * yet actually completed. But in case the base address is the same
10969 * anyway, we don't really care.
10970 */
10971 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10972 crtc->unpin_work->gtt_offset &&
10973 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10974 crtc->unpin_work->flip_count);
10975}
10976
6b95a207
KH		 10977void intel_prepare_page_flip(struct drm_device *dev, int plane)
10978{
fbee40df 10979 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10980 struct intel_crtc *intel_crtc =
10981 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10982 unsigned long flags;
10983
f326038a
DV		 10984
10985 /*
10986 * This is called both by irq handlers and the reset code (to complete
10987 * lost pageflips) so needs the full irqsave spinlocks.
10988 *
10989 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10990 * generate a page-flip completion irq, i.e. every modeset
10991 * is also accompanied by a spurious intel_prepare_page_flip().
10992 */
6b95a207 10993 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10994 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10995 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10996 spin_unlock_irqrestore(&dev->event_lock, flags);
10997}
10998
eba905b2 10999static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 11000{
11001 /* Ensure that the work item is consistent when activating it ... */
11002 smp_wmb();
11003 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
11004 /* and that it is marked active as soon as the irq could fire. */
11005 smp_wmb();
11006}
11007
8c9f3aaf
JB		 11008static int intel_gen2_queue_flip(struct drm_device *dev,
11009 struct drm_crtc *crtc,
11010 struct drm_framebuffer *fb,
ed8d1975 11011 struct drm_i915_gem_object *obj,
a4872ba6 11012 struct intel_engine_cs *ring,
ed8d1975 11013 uint32_t flags)
8c9f3aaf 11014{
8c9f3aaf 11015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11016 u32 flip_mask;
11017 int ret;
11018
6d90c952 11019 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11020 if (ret)
4fa62c89 11021 return ret;
8c9f3aaf
JB		 11022
11023 /* Can't queue multiple flips, so wait for the previous
11024 * one to finish before executing the next.
11025 */
11026 if (intel_crtc->plane)
11027 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11028 else
11029 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11030 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11031 intel_ring_emit(ring, MI_NOOP);
11032 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11033 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11034 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11035 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 11036 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 11037
11038 intel_mark_page_flip_active(intel_crtc);
09246732 11039 __intel_ring_advance(ring);
83d4092b 11040 return 0;
8c9f3aaf
JB		 11041}
11042
11043static int intel_gen3_queue_flip(struct drm_device *dev,
11044 struct drm_crtc *crtc,
11045 struct drm_framebuffer *fb,
ed8d1975 11046 struct drm_i915_gem_object *obj,
a4872ba6 11047 struct intel_engine_cs *ring,
ed8d1975 11048 uint32_t flags)
8c9f3aaf 11049{
8c9f3aaf 11050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11051 u32 flip_mask;
11052 int ret;
11053
6d90c952 11054 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11055 if (ret)
4fa62c89 11056 return ret;
8c9f3aaf
JB		 11057
11058 if (intel_crtc->plane)
11059 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11060 else
11061 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11062 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11063 intel_ring_emit(ring, MI_NOOP);
11064 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11065 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11066 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11067 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 11068 intel_ring_emit(ring, MI_NOOP);
11069
e7d841ca 11070 intel_mark_page_flip_active(intel_crtc);
09246732 11071 __intel_ring_advance(ring);
83d4092b 11072 return 0;
8c9f3aaf
JB		 11073}
11074
11075static int intel_gen4_queue_flip(struct drm_device *dev,
11076 struct drm_crtc *crtc,
11077 struct drm_framebuffer *fb,
ed8d1975 11078 struct drm_i915_gem_object *obj,
a4872ba6 11079 struct intel_engine_cs *ring,
ed8d1975 11080 uint32_t flags)
8c9f3aaf
JB		 11081{
11082 struct drm_i915_private *dev_priv = dev->dev_private;
11083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11084 uint32_t pf, pipesrc;
11085 int ret;
11086
6d90c952 11087 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11088 if (ret)
4fa62c89 11089 return ret;
8c9f3aaf
JB		 11090
11091 /* i965+ uses the linear or tiled offsets from the
11092 * Display Registers (which do not change across a page-flip)
11093 * so we need only reprogram the base address.
11094 */
6d90c952
DV		 11095 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11096 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11097 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11098 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 11099 obj->tiling_mode);
8c9f3aaf
JB		 11100
11101 /* XXX Enabling the panel-fitter across page-flip is so far
11102 * untested on non-native modes, so ignore it for now.
11103 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11104 */
11105 pf = 0;
11106 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11107 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11108
11109 intel_mark_page_flip_active(intel_crtc);
09246732 11110 __intel_ring_advance(ring);
83d4092b 11111 return 0;
8c9f3aaf
JB		 11112}
11113
11114static int intel_gen6_queue_flip(struct drm_device *dev,
11115 struct drm_crtc *crtc,
11116 struct drm_framebuffer *fb,
ed8d1975 11117 struct drm_i915_gem_object *obj,
a4872ba6 11118 struct intel_engine_cs *ring,
ed8d1975 11119 uint32_t flags)
8c9f3aaf
JB		 11120{
11121 struct drm_i915_private *dev_priv = dev->dev_private;
11122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11123 uint32_t pf, pipesrc;
11124 int ret;
11125
6d90c952 11126 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11127 if (ret)
4fa62c89 11128 return ret;
8c9f3aaf 11129
6d90c952
DV		 11130 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11131 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11132 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 11133 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 11134
dc257cf1
DV		 11135 /* Contrary to the suggestions in the documentation,
11136 * "Enable Panel Fitter" does not seem to be required when page
11137 * flipping with a non-native mode, and worse causes a normal
11138 * modeset to fail.
11139 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11140 */
11141 pf = 0;
8c9f3aaf 11142 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11143 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11144
11145 intel_mark_page_flip_active(intel_crtc);
09246732 11146 __intel_ring_advance(ring);
83d4092b 11147 return 0;
8c9f3aaf
JB		 11148}
11149
7c9017e5
JB		 11150static int intel_gen7_queue_flip(struct drm_device *dev,
11151 struct drm_crtc *crtc,
11152 struct drm_framebuffer *fb,
ed8d1975 11153 struct drm_i915_gem_object *obj,
a4872ba6 11154 struct intel_engine_cs *ring,
ed8d1975 11155 uint32_t flags)
7c9017e5 11156{
7c9017e5 11157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11158 uint32_t plane_bit = 0;
ffe74d75
CW		 11159 int len, ret;
11160
eba905b2 11161 switch (intel_crtc->plane) {
cb05d8de
DV		 11162 case PLANE_A:
11163 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11164 break;
11165 case PLANE_B:
11166 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11167 break;
11168 case PLANE_C:
11169 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11170 break;
11171 default:
11172 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11173 return -ENODEV;
cb05d8de
DV		 11174 }
11175
ffe74d75 11176 len = 4;
f476828a 11177 if (ring->id == RCS) {
ffe74d75 11178 len += 6;
f476828a
DL		 11179 /*
11180 * On Gen 8, SRM is now taking an extra dword to accommodate
11181 * 48bits addresses, and we need a NOOP for the batch size to
11182 * stay even.
11183 */
11184 if (IS_GEN8(dev))
11185 len += 2;
11186 }
ffe74d75 11187
f66fab8e
VS		 11188 /*
11189 * BSpec MI_DISPLAY_FLIP for IVB:
11190 * "The full packet must be contained within the same cache line."
11191 *
11192 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11193 * cacheline, if we ever start emitting more commands before
11194 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11195 * then do the cacheline alignment, and finally emit the
11196 * MI_DISPLAY_FLIP.
11197 */
11198 ret = intel_ring_cacheline_align(ring);
11199 if (ret)
4fa62c89 11200 return ret;
f66fab8e 11201
ffe74d75 11202 ret = intel_ring_begin(ring, len);
7c9017e5 11203 if (ret)
4fa62c89 11204 return ret;
7c9017e5 11205
ffe74d75
CW		 11206 /* Unmask the flip-done completion message. Note that the bspec says that
11207 * we should do this for both the BCS and RCS, and that we must not unmask
11208 * more than one flip event at any time (or ensure that one flip message
11209 * can be sent by waiting for flip-done prior to queueing new flips).
11210 * Experimentation says that BCS works despite DERRMR masking all
11211 * flip-done completion events and that unmasking all planes at once
11212 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11213 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11214 */
11215 if (ring->id == RCS) {
11216 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11217 intel_ring_emit(ring, DERRMR);
11218 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11219 DERRMR_PIPEB_PRI_FLIP_DONE |
11220 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11221 if (IS_GEN8(dev))
11222 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11223 MI_SRM_LRM_GLOBAL_GTT);
11224 else
11225 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11226 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11227 intel_ring_emit(ring, DERRMR);
11228 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11229 if (IS_GEN8(dev)) {
11230 intel_ring_emit(ring, 0);
11231 intel_ring_emit(ring, MI_NOOP);
11232 }
ffe74d75
CW		 11233 }
11234
cb05d8de 11235 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11236 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11237 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11238 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11239
11240 intel_mark_page_flip_active(intel_crtc);
09246732 11241 __intel_ring_advance(ring);
83d4092b 11242 return 0;
7c9017e5
JB		 11243}
11244
84c33a64
SG		 11245static bool use_mmio_flip(struct intel_engine_cs *ring,
11246 struct drm_i915_gem_object *obj)
11247{
11248 /*
11249 * This is not being used for older platforms, because
11250 * non-availability of flip done interrupt forces us to use
11251 * CS flips. Older platforms derive flip done using some clever
11252 * tricks involving the flip_pending status bits and vblank irqs.
11253 * So using MMIO flips there would disrupt this mechanism.
11254 */
11255
8e09bf83
CW		 11256 if (ring == NULL)
11257 return true;
11258
84c33a64
SG		 11259 if (INTEL_INFO(ring->dev)->gen < 5)
11260 return false;
11261
11262 if (i915.use_mmio_flip < 0)
11263 return false;
11264 else if (i915.use_mmio_flip > 0)
11265 return true;
14bf993e
OM		 11266 else if (i915.enable_execlists)
11267 return true;
84c33a64 11268 else
b4716185 11269 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11270}
11271
ff944564
DL		 11272static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11273{
11274 struct drm_device *dev = intel_crtc->base.dev;
11275 struct drm_i915_private *dev_priv = dev->dev_private;
11276 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11277 const enum pipe pipe = intel_crtc->pipe;
11278 u32 ctl, stride;
11279
11280 ctl = I915_READ(PLANE_CTL(pipe, 0));
11281 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11282 switch (fb->modifier[0]) {
11283 case DRM_FORMAT_MOD_NONE:
11284 break;
11285 case I915_FORMAT_MOD_X_TILED:
ff944564 11286 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11287 break;
11288 case I915_FORMAT_MOD_Y_TILED:
11289 ctl |= PLANE_CTL_TILED_Y;
11290 break;
11291 case I915_FORMAT_MOD_Yf_TILED:
11292 ctl |= PLANE_CTL_TILED_YF;
11293 break;
11294 default:
11295 MISSING_CASE(fb->modifier[0]);
11296 }
ff944564
DL		 11297
11298 /*
11299 * The stride is either expressed as a multiple of 64 bytes chunks for
11300 * linear buffers or in number of tiles for tiled buffers.
11301 */
2ebef630
TU		 11302 stride = fb->pitches[0] /
11303 intel_fb_stride_alignment(dev, fb->modifier[0],
11304 fb->pixel_format);
ff944564
DL		 11305
11306 /*
11307 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11308 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11309 */
11310 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11311 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11312
11313 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11314 POSTING_READ(PLANE_SURF(pipe, 0));
11315}
11316
11317static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11318{
11319 struct drm_device *dev = intel_crtc->base.dev;
11320 struct drm_i915_private *dev_priv = dev->dev_private;
11321 struct intel_framebuffer *intel_fb =
11322 to_intel_framebuffer(intel_crtc->base.primary->fb);
11323 struct drm_i915_gem_object *obj = intel_fb->obj;
11324 u32 dspcntr;
11325 u32 reg;
11326
84c33a64
SG		 11327 reg = DSPCNTR(intel_crtc->plane);
11328 dspcntr = I915_READ(reg);
11329
c5d97472
DL		 11330 if (obj->tiling_mode != I915_TILING_NONE)
11331 dspcntr |= DISPPLANE_TILED;
11332 else
11333 dspcntr &= ~DISPPLANE_TILED;
11334
84c33a64
SG		 11335 I915_WRITE(reg, dspcntr);
11336
11337 I915_WRITE(DSPSURF(intel_crtc->plane),
11338 intel_crtc->unpin_work->gtt_offset);
11339 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11340
ff944564
DL		 11341}
11342
11343/*
11344 * XXX: This is the temporary way to update the plane registers until we get
11345 * around to using the usual plane update functions for MMIO flips
11346 */
11347static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11348{
11349 struct drm_device *dev = intel_crtc->base.dev;
11350 bool atomic_update;
11351 u32 start_vbl_count;
11352
11353 intel_mark_page_flip_active(intel_crtc);
11354
11355 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11356
11357 if (INTEL_INFO(dev)->gen >= 9)
11358 skl_do_mmio_flip(intel_crtc);
11359 else
11360 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11361 ilk_do_mmio_flip(intel_crtc);
11362
9362c7c5
ACO		 11363 if (atomic_update)
11364 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11365}
11366
9362c7c5 11367static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11368{
b2cfe0ab
CW		 11369 struct intel_mmio_flip *mmio_flip =
11370 container_of(work, struct intel_mmio_flip, work);
84c33a64 11371
eed29a5b
DV		 11372 if (mmio_flip->req)
11373 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11374 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11375 false, NULL,
11376 &mmio_flip->i915->rps.mmioflips));
84c33a64 11377
b2cfe0ab
CW		 11378 intel_do_mmio_flip(mmio_flip->crtc);
11379
eed29a5b 11380 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11381 kfree(mmio_flip);
84c33a64
SG		 11382}
11383
11384static int intel_queue_mmio_flip(struct drm_device *dev,
11385 struct drm_crtc *crtc,
11386 struct drm_framebuffer *fb,
11387 struct drm_i915_gem_object *obj,
11388 struct intel_engine_cs *ring,
11389 uint32_t flags)
11390{
b2cfe0ab
CW		 11391 struct intel_mmio_flip *mmio_flip;
11392
11393 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11394 if (mmio_flip == NULL)
11395 return -ENOMEM;
84c33a64 11396
bcafc4e3 11397 mmio_flip->i915 = to_i915(dev);
eed29a5b 11398 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11399 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11400
b2cfe0ab
CW		 11401 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11402 schedule_work(&mmio_flip->work);
84c33a64 11403
84c33a64
SG		 11404 return 0;
11405}
11406
8c9f3aaf
JB		 11407static int intel_default_queue_flip(struct drm_device *dev,
11408 struct drm_crtc *crtc,
11409 struct drm_framebuffer *fb,
ed8d1975 11410 struct drm_i915_gem_object *obj,
a4872ba6 11411 struct intel_engine_cs *ring,
ed8d1975 11412 uint32_t flags)
8c9f3aaf
JB		 11413{
11414 return -ENODEV;
11415}
11416
d6bbafa1
CW		 11417static bool __intel_pageflip_stall_check(struct drm_device *dev,
11418 struct drm_crtc *crtc)
11419{
11420 struct drm_i915_private *dev_priv = dev->dev_private;
11421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11422 struct intel_unpin_work *work = intel_crtc->unpin_work;
11423 u32 addr;
11424
11425 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11426 return true;
11427
11428 if (!work->enable_stall_check)
11429 return false;
11430
11431 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11432 if (work->flip_queued_req &&
11433 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11434 return false;
11435
1e3feefd 11436 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11437 }
11438
1e3feefd 11439 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11440 return false;
11441
11442 /* Potential stall - if we see that the flip has happened,
11443 * assume a missed interrupt. */
11444 if (INTEL_INFO(dev)->gen >= 4)
11445 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11446 else
11447 addr = I915_READ(DSPADDR(intel_crtc->plane));
11448
11449 /* There is a potential issue here with a false positive after a flip
11450 * to the same address. We could address this by checking for a
11451 * non-incrementing frame counter.
11452 */
11453 return addr == work->gtt_offset;
11454}
11455
11456void intel_check_page_flip(struct drm_device *dev, int pipe)
11457{
11458 struct drm_i915_private *dev_priv = dev->dev_private;
11459 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11461 struct intel_unpin_work *work;
f326038a 11462
6c51d46f 11463 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11464
11465 if (crtc == NULL)
11466 return;
11467
f326038a 11468 spin_lock(&dev->event_lock);
6ad790c0
CW		 11469 work = intel_crtc->unpin_work;
11470 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11471 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11472 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11473 page_flip_completed(intel_crtc);
6ad790c0 11474 work = NULL;
d6bbafa1 11475 }
6ad790c0
CW		 11476 if (work != NULL &&
11477 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11478 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11479 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11480}
11481
6b95a207
KH		 11482static int intel_crtc_page_flip(struct drm_crtc *crtc,
11483 struct drm_framebuffer *fb,
ed8d1975
KP		 11484 struct drm_pending_vblank_event *event,
11485 uint32_t page_flip_flags)
6b95a207
KH		 11486{
11487 struct drm_device *dev = crtc->dev;
11488 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11489 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11490 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11492 struct drm_plane *primary = crtc->primary;
a071fa00 11493 enum pipe pipe = intel_crtc->pipe;
6b95a207 11494 struct intel_unpin_work *work;
a4872ba6 11495 struct intel_engine_cs *ring;
cf5d8a46 11496 bool mmio_flip;
52e68630 11497 int ret;
6b95a207 11498
2ff8fde1
MR		 11499 /*
11500 * drm_mode_page_flip_ioctl() should already catch this, but double
11501 * check to be safe. In the future we may enable pageflipping from
11502 * a disabled primary plane.
11503 */
11504 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11505 return -EBUSY;
11506
e6a595d2 11507 /* Can't change pixel format via MI display flips. */
f4510a27 11508 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11509 return -EINVAL;
11510
11511 /*
11512 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11513 * Note that pitch changes could also affect these register.
11514 */
11515 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11516 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11517 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11518 return -EINVAL;
11519
f900db47
CW		 11520 if (i915_terminally_wedged(&dev_priv->gpu_error))
11521 goto out_hang;
11522
b14c5679 11523 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11524 if (work == NULL)
11525 return -ENOMEM;
11526
6b95a207 11527 work->event = event;
b4a98e57 11528 work->crtc = crtc;
ab8d6675 11529 work->old_fb = old_fb;
6b95a207
KH		 11530 INIT_WORK(&work->work, intel_unpin_work_fn);
11531
87b6b101 11532 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11533 if (ret)
11534 goto free_work;
11535
6b95a207 11536 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11537 spin_lock_irq(&dev->event_lock);
6b95a207 11538 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11539 /* Before declaring the flip queue wedged, check if
11540 * the hardware completed the operation behind our backs.
11541 */
11542 if (__intel_pageflip_stall_check(dev, crtc)) {
11543 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11544 page_flip_completed(intel_crtc);
11545 } else {
11546 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11547 spin_unlock_irq(&dev->event_lock);
468f0b44 11548
d6bbafa1
CW		 11549 drm_crtc_vblank_put(crtc);
11550 kfree(work);
11551 return -EBUSY;
11552 }
6b95a207
KH		 11553 }
11554 intel_crtc->unpin_work = work;
5e2d7afc 11555 spin_unlock_irq(&dev->event_lock);
6b95a207 11556
b4a98e57
CW		 11557 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11558 flush_workqueue(dev_priv->wq);
11559
75dfca80 11560 /* Reference the objects for the scheduled work. */
ab8d6675 11561 drm_framebuffer_reference(work->old_fb);
05394f39 11562 drm_gem_object_reference(&obj->base);
6b95a207 11563
f4510a27 11564 crtc->primary->fb = fb;
afd65eb4 11565 update_state_fb(crtc->primary);
1ed1f968 11566
e1f99ce6 11567 work->pending_flip_obj = obj;
e1f99ce6 11568
89ed88ba
CW		 11569 ret = i915_mutex_lock_interruptible(dev);
11570 if (ret)
11571 goto cleanup;
11572
b4a98e57 11573 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11574 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11575
75f7f3ec 11576 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11577 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11578
4fa62c89
VS		 11579 if (IS_VALLEYVIEW(dev)) {
11580 ring = &dev_priv->ring[BCS];
ab8d6675 11581 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11582 /* vlv: DISPLAY_FLIP fails to change tiling */
11583 ring = NULL;
48bf5b2d 11584 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11585 ring = &dev_priv->ring[BCS];
4fa62c89 11586 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11587 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11588 if (ring == NULL || ring->id != RCS)
11589 ring = &dev_priv->ring[BCS];
11590 } else {
11591 ring = &dev_priv->ring[RCS];
11592 }
11593
cf5d8a46
CW		 11594 mmio_flip = use_mmio_flip(ring, obj);
11595
11596 /* When using CS flips, we want to emit semaphores between rings.
11597 * However, when using mmio flips we will create a task to do the
11598 * synchronisation, so all we want here is to pin the framebuffer
11599 * into the display plane and skip any waits.
11600 */
82bc3b2d 11601 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11602 crtc->primary->state,
b4716185 11603 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11604 if (ret)
11605 goto cleanup_pending;
6b95a207 11606
121920fa
TU		 11607 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11608 + intel_crtc->dspaddr_offset;
4fa62c89 11609
cf5d8a46 11610 if (mmio_flip) {
84c33a64
SG		 11611 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11612 page_flip_flags);
d6bbafa1
CW		 11613 if (ret)
11614 goto cleanup_unpin;
11615
f06cc1b9
JH		 11616 i915_gem_request_assign(&work->flip_queued_req,
11617 obj->last_write_req);
d6bbafa1 11618 } else {
d94b5030
CW		 11619 if (obj->last_write_req) {
11620 ret = i915_gem_check_olr(obj->last_write_req);
11621 if (ret)
11622 goto cleanup_unpin;
11623 }
11624
84c33a64 11625 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11626 page_flip_flags);
11627 if (ret)
11628 goto cleanup_unpin;
11629
f06cc1b9
JH		 11630 i915_gem_request_assign(&work->flip_queued_req,
11631 intel_ring_get_request(ring));
d6bbafa1
CW		 11632 }
11633
1e3feefd 11634 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11635 work->enable_stall_check = true;
4fa62c89 11636
ab8d6675 11637 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11638 INTEL_FRONTBUFFER_PRIMARY(pipe));
11639
7ff0ebcc 11640 intel_fbc_disable(dev);
f99d7069 11641 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11642 mutex_unlock(&dev->struct_mutex);
11643
e5510fac
JB		 11644 trace_i915_flip_request(intel_crtc->plane, obj);
11645
6b95a207 11646 return 0;
96b099fd 11647
4fa62c89 11648cleanup_unpin:
82bc3b2d 11649 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11650cleanup_pending:
b4a98e57 11651 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11652 mutex_unlock(&dev->struct_mutex);
11653cleanup:
f4510a27 11654 crtc->primary->fb = old_fb;
afd65eb4 11655 update_state_fb(crtc->primary);
89ed88ba
CW		 11656
11657 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11658 drm_framebuffer_unreference(work->old_fb);
96b099fd 11659
5e2d7afc 11660 spin_lock_irq(&dev->event_lock);
96b099fd 11661 intel_crtc->unpin_work = NULL;
5e2d7afc 11662 spin_unlock_irq(&dev->event_lock);
96b099fd 11663
87b6b101 11664 drm_crtc_vblank_put(crtc);
7317c75e 11665free_work:
96b099fd
CW		 11666 kfree(work);
11667
f900db47
CW		 11668 if (ret == -EIO) {
11669out_hang:
53a366b9 11670 ret = intel_plane_restore(primary);
f0d3dad3 11671 if (ret == 0 && event) {
5e2d7afc 11672 spin_lock_irq(&dev->event_lock);
a071fa00 11673 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11674 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11675 }
f900db47 11676 }
96b099fd 11677 return ret;
6b95a207
KH		 11678}
11679
65b38e0d 11680static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11681 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11682 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11683 .atomic_begin = intel_begin_crtc_commit,
11684 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11685};
11686
9a935856
DV		 11687/**
11688 * intel_modeset_update_staged_output_state
11689 *
11690 * Updates the staged output configuration state, e.g. after we've read out the
11691 * current hw state.
11692 */
11693static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11694{
7668851f 11695 struct intel_crtc *crtc;
9a935856
DV		 11696 struct intel_encoder *encoder;
11697 struct intel_connector *connector;
f6e5b160 11698
3a3371ff 11699 for_each_intel_connector(dev, connector) {
9a935856
DV		 11700 connector->new_encoder =
11701 to_intel_encoder(connector->base.encoder);
11702 }
f6e5b160 11703
b2784e15 11704 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11705 encoder->new_crtc =
11706 to_intel_crtc(encoder->base.crtc);
11707 }
7668851f 11708
d3fcc808 11709 for_each_intel_crtc(dev, crtc) {
83d65738 11710 crtc->new_enabled = crtc->base.state->enable;
7668851f 11711 }
f6e5b160
CW		 11712}
11713
d29b2f9d
ACO		 11714/* Transitional helper to copy current connector/encoder state to
11715 * connector->state. This is needed so that code that is partially
11716 * converted to atomic does the right thing.
11717 */
11718static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11719{
11720 struct intel_connector *connector;
11721
11722 for_each_intel_connector(dev, connector) {
11723 if (connector->base.encoder) {
11724 connector->base.state->best_encoder =
11725 connector->base.encoder;
11726 connector->base.state->crtc =
11727 connector->base.encoder->crtc;
11728 } else {
11729 connector->base.state->best_encoder = NULL;
11730 connector->base.state->crtc = NULL;
11731 }
11732 }
11733}
11734
a821fc46 11735/* Fixup legacy state after an atomic state swap.
9a935856 11736 */
a821fc46 11737static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11738{
a821fc46 11739 struct intel_crtc *crtc;
9a935856 11740 struct intel_encoder *encoder;
a821fc46 11741 struct intel_connector *connector;
d5432a9d 11742
a821fc46
ACO		 11743 for_each_intel_connector(state->dev, connector) {
11744 connector->base.encoder = connector->base.state->best_encoder;
11745 if (connector->base.encoder)
11746 connector->base.encoder->crtc =
11747 connector->base.state->crtc;
9a935856 11748 }
f6e5b160 11749
d5432a9d
ACO		 11750 /* Update crtc of disabled encoders */
11751 for_each_intel_encoder(state->dev, encoder) {
11752 int num_connectors = 0;
11753
a821fc46
ACO		 11754 for_each_intel_connector(state->dev, connector)
11755 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO		 11756 num_connectors++;
11757
11758 if (num_connectors == 0)
11759 encoder->base.crtc = NULL;
9a935856 11760 }
7668851f 11761
a821fc46
ACO		 11762 for_each_intel_crtc(state->dev, crtc) {
11763 crtc->base.enabled = crtc->base.state->enable;
11764 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11765 }
d29b2f9d 11766
d5432a9d
ACO		 11767 /* Copy the new configuration to the staged state, to keep the few
11768 * pieces of code that haven't been converted yet happy */
11769 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV		 11770}
11771
050f7aeb 11772static void
eba905b2 11773connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11774 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11775{
11776 int bpp = pipe_config->pipe_bpp;
11777
11778 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11779 connector->base.base.id,
c23cc417 11780 connector->base.name);
050f7aeb
DV		 11781
11782 /* Don't use an invalid EDID bpc value */
11783 if (connector->base.display_info.bpc &&
11784 connector->base.display_info.bpc * 3 < bpp) {
11785 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11786 bpp, connector->base.display_info.bpc*3);
11787 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11788 }
11789
11790 /* Clamp bpp to 8 on screens without EDID 1.4 */
11791 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11792 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11793 bpp);
11794 pipe_config->pipe_bpp = 24;
11795 }
11796}
11797
4e53c2e0 11798static int
050f7aeb 11799compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11800 struct intel_crtc_state *pipe_config)
4e53c2e0 11801{
050f7aeb 11802 struct drm_device *dev = crtc->base.dev;
1486017f 11803 struct drm_atomic_state *state;
da3ced29
ACO		 11804 struct drm_connector *connector;
11805 struct drm_connector_state *connector_state;
1486017f 11806 int bpp, i;
4e53c2e0 11807
d328c9d7 11808 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11809 bpp = 10*3;
d328c9d7
DV		 11810 else if (INTEL_INFO(dev)->gen >= 5)
11811 bpp = 12*3;
11812 else
11813 bpp = 8*3;
11814
4e53c2e0 11815
4e53c2e0
DV		 11816 pipe_config->pipe_bpp = bpp;
11817
1486017f
ACO		 11818 state = pipe_config->base.state;
11819
4e53c2e0 11820 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11821 for_each_connector_in_state(state, connector, connector_state, i) {
11822 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11823 continue;
11824
da3ced29
ACO		 11825 connected_sink_compute_bpp(to_intel_connector(connector),
11826 pipe_config);
4e53c2e0
DV		 11827 }
11828
11829 return bpp;
11830}
11831
644db711
DV		 11832static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11833{
11834 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11835 "type: 0x%x flags: 0x%x\n",
1342830c 11836 mode->crtc_clock,
644db711
DV		 11837 mode->crtc_hdisplay, mode->crtc_hsync_start,
11838 mode->crtc_hsync_end, mode->crtc_htotal,
11839 mode->crtc_vdisplay, mode->crtc_vsync_start,
11840 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11841}
11842
c0b03411 11843static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11844 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11845 const char *context)
11846{
6a60cd87
CK		 11847 struct drm_device *dev = crtc->base.dev;
11848 struct drm_plane *plane;
11849 struct intel_plane *intel_plane;
11850 struct intel_plane_state *state;
11851 struct drm_framebuffer *fb;
11852
11853 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11854 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11855
11856 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11857 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11858 pipe_config->pipe_bpp, pipe_config->dither);
11859 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11860 pipe_config->has_pch_encoder,
11861 pipe_config->fdi_lanes,
11862 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11863 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11864 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11865 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11866 pipe_config->has_dp_encoder,
11867 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11868 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11869 pipe_config->dp_m_n.tu);
b95af8be
VK		 11870
11871 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11872 pipe_config->has_dp_encoder,
11873 pipe_config->dp_m2_n2.gmch_m,
11874 pipe_config->dp_m2_n2.gmch_n,
11875 pipe_config->dp_m2_n2.link_m,
11876 pipe_config->dp_m2_n2.link_n,
11877 pipe_config->dp_m2_n2.tu);
11878
55072d19
DV		 11879 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11880 pipe_config->has_audio,
11881 pipe_config->has_infoframe);
11882
c0b03411 11883 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11884 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11885 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11886 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11887 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11888 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11889 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11890 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11891 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11892 crtc->num_scalers,
11893 pipe_config->scaler_state.scaler_users,
11894 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11895 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11896 pipe_config->gmch_pfit.control,
11897 pipe_config->gmch_pfit.pgm_ratios,
11898 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11899 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11900 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11901 pipe_config->pch_pfit.size,
11902 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11903 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11904 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11905
415ff0f6
TU		 11906 if (IS_BROXTON(dev)) {
11907 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11908 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11909 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11910 pipe_config->ddi_pll_sel,
11911 pipe_config->dpll_hw_state.ebb0,
11912 pipe_config->dpll_hw_state.pll0,
11913 pipe_config->dpll_hw_state.pll1,
11914 pipe_config->dpll_hw_state.pll2,
11915 pipe_config->dpll_hw_state.pll3,
11916 pipe_config->dpll_hw_state.pll6,
11917 pipe_config->dpll_hw_state.pll8,
11918 pipe_config->dpll_hw_state.pcsdw12);
11919 } else if (IS_SKYLAKE(dev)) {
11920 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11921 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11922 pipe_config->ddi_pll_sel,
11923 pipe_config->dpll_hw_state.ctrl1,
11924 pipe_config->dpll_hw_state.cfgcr1,
11925 pipe_config->dpll_hw_state.cfgcr2);
11926 } else if (HAS_DDI(dev)) {
11927 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11928 pipe_config->ddi_pll_sel,
11929 pipe_config->dpll_hw_state.wrpll);
11930 } else {
11931 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11932 "fp0: 0x%x, fp1: 0x%x\n",
11933 pipe_config->dpll_hw_state.dpll,
11934 pipe_config->dpll_hw_state.dpll_md,
11935 pipe_config->dpll_hw_state.fp0,
11936 pipe_config->dpll_hw_state.fp1);
11937 }
11938
6a60cd87
CK		 11939 DRM_DEBUG_KMS("planes on this crtc\n");
11940 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11941 intel_plane = to_intel_plane(plane);
11942 if (intel_plane->pipe != crtc->pipe)
11943 continue;
11944
11945 state = to_intel_plane_state(plane->state);
11946 fb = state->base.fb;
11947 if (!fb) {
11948 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11949 "disabled, scaler_id = %d\n",
11950 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11951 plane->base.id, intel_plane->pipe,
11952 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11953 drm_plane_index(plane), state->scaler_id);
11954 continue;
11955 }
11956
11957 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11958 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11959 plane->base.id, intel_plane->pipe,
11960 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11961 drm_plane_index(plane));
11962 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11963 fb->base.id, fb->width, fb->height, fb->pixel_format);
11964 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11965 state->scaler_id,
11966 state->src.x1 >> 16, state->src.y1 >> 16,
11967 drm_rect_width(&state->src) >> 16,
11968 drm_rect_height(&state->src) >> 16,
11969 state->dst.x1, state->dst.y1,
11970 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11971 }
c0b03411
DV		 11972}
11973
bc079e8b
VS		 11974static bool encoders_cloneable(const struct intel_encoder *a,
11975 const struct intel_encoder *b)
accfc0c5 11976{
bc079e8b
VS		 11977 /* masks could be asymmetric, so check both ways */
11978 return a == b || (a->cloneable & (1 << b->type) &&
11979 b->cloneable & (1 << a->type));
11980}
11981
98a221da
ACO		 11982static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11983 struct intel_crtc *crtc,
bc079e8b
VS		 11984 struct intel_encoder *encoder)
11985{
bc079e8b 11986 struct intel_encoder *source_encoder;
da3ced29 11987 struct drm_connector *connector;
98a221da
ACO		 11988 struct drm_connector_state *connector_state;
11989 int i;
bc079e8b 11990
da3ced29 11991 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11992 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11993 continue;
11994
98a221da
ACO		 11995 source_encoder =
11996 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11997 if (!encoders_cloneable(encoder, source_encoder))
11998 return false;
11999 }
12000
12001 return true;
12002}
12003
98a221da
ACO		 12004static bool check_encoder_cloning(struct drm_atomic_state *state,
12005 struct intel_crtc *crtc)
bc079e8b 12006{
accfc0c5 12007 struct intel_encoder *encoder;
da3ced29 12008 struct drm_connector *connector;
98a221da
ACO		 12009 struct drm_connector_state *connector_state;
12010 int i;
accfc0c5 12011
da3ced29 12012 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 12013 if (connector_state->crtc != &crtc->base)
12014 continue;
12015
12016 encoder = to_intel_encoder(connector_state->best_encoder);
12017 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 12018 return false;
accfc0c5
DV		 12019 }
12020
bc079e8b 12021 return true;
accfc0c5
DV		 12022}
12023
5448a00d 12024static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12025{
5448a00d
ACO		 12026 struct drm_device *dev = state->dev;
12027 struct intel_encoder *encoder;
da3ced29 12028 struct drm_connector *connector;
5448a00d 12029 struct drm_connector_state *connector_state;
00f0b378 12030 unsigned int used_ports = 0;
5448a00d 12031 int i;
00f0b378
VS		 12032
12033 /*
12034 * Walk the connector list instead of the encoder
12035 * list to detect the problem on ddi platforms
12036 * where there's just one encoder per digital port.
12037 */
da3ced29 12038 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12039 if (!connector_state->best_encoder)
00f0b378
VS		 12040 continue;
12041
5448a00d
ACO		 12042 encoder = to_intel_encoder(connector_state->best_encoder);
12043
12044 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12045
12046 switch (encoder->type) {
12047 unsigned int port_mask;
12048 case INTEL_OUTPUT_UNKNOWN:
12049 if (WARN_ON(!HAS_DDI(dev)))
12050 break;
12051 case INTEL_OUTPUT_DISPLAYPORT:
12052 case INTEL_OUTPUT_HDMI:
12053 case INTEL_OUTPUT_EDP:
12054 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12055
12056 /* the same port mustn't appear more than once */
12057 if (used_ports & port_mask)
12058 return false;
12059
12060 used_ports |= port_mask;
12061 default:
12062 break;
12063 }
12064 }
12065
12066 return true;
12067}
12068
83a57153
ACO		 12069static void
12070clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12071{
12072 struct drm_crtc_state tmp_state;
663a3640 12073 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12074 struct intel_dpll_hw_state dpll_hw_state;
12075 enum intel_dpll_id shared_dpll;
8504c74c 12076 uint32_t ddi_pll_sel;
83a57153 12077
7546a384
ACO		 12078 /* FIXME: before the switch to atomic started, a new pipe_config was
12079 * kzalloc'd. Code that depends on any field being zero should be
12080 * fixed, so that the crtc_state can be safely duplicated. For now,
12081 * only fields that are know to not cause problems are preserved. */
12082
83a57153 12083 tmp_state = crtc_state->base;
663a3640 12084 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12085 shared_dpll = crtc_state->shared_dpll;
12086 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12087 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12088
83a57153 12089 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12090
83a57153 12091 crtc_state->base = tmp_state;
663a3640 12092 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12093 crtc_state->shared_dpll = shared_dpll;
12094 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12095 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12096}
12097
548ee15b 12098static int
b8cecdf5 12099intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 12100 struct drm_atomic_state *state,
12101 struct intel_crtc_state *pipe_config)
ee7b9f93 12102{
7758a113 12103 struct intel_encoder *encoder;
da3ced29 12104 struct drm_connector *connector;
0b901879 12105 struct drm_connector_state *connector_state;
d328c9d7 12106 int base_bpp, ret = -EINVAL;
0b901879 12107 int i;
e29c22c0 12108 bool retry = true;
ee7b9f93 12109
98a221da 12110 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 12111 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 12112 return -EINVAL;
accfc0c5
DV		 12113 }
12114
5448a00d 12115 if (!check_digital_port_conflicts(state)) {
00f0b378 12116 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 12117 return -EINVAL;
00f0b378
VS		 12118 }
12119
83a57153 12120 clear_intel_crtc_state(pipe_config);
7758a113 12121
e143a21c
DV		 12122 pipe_config->cpu_transcoder =
12123 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12124
2960bc9c
ID		 12125 /*
12126 * Sanitize sync polarity flags based on requested ones. If neither
12127 * positive or negative polarity is requested, treat this as meaning
12128 * negative polarity.
12129 */
2d112de7 12130 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12131 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12132 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12133
2d112de7 12134 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12135 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12136 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12137
050f7aeb
DV		 12138 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12139 * plane pixel format and any sink constraints into account. Returns the
12140 * source plane bpp so that dithering can be selected on mismatches
12141 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12142 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12143 pipe_config);
12144 if (base_bpp < 0)
4e53c2e0
DV		 12145 goto fail;
12146
e41a56be
VS		 12147 /*
12148 * Determine the real pipe dimensions. Note that stereo modes can
12149 * increase the actual pipe size due to the frame doubling and
12150 * insertion of additional space for blanks between the frame. This
12151 * is stored in the crtc timings. We use the requested mode to do this
12152 * computation to clearly distinguish it from the adjusted mode, which
12153 * can be changed by the connectors in the below retry loop.
12154 */
2d112de7 12155 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12156 &pipe_config->pipe_src_w,
12157 &pipe_config->pipe_src_h);
e41a56be 12158
e29c22c0 12159encoder_retry:
ef1b460d 12160 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12161 pipe_config->port_clock = 0;
ef1b460d 12162 pipe_config->pixel_multiplier = 1;
ff9a6750 12163
135c81b8 12164 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12165 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12166 CRTC_STEREO_DOUBLE);
135c81b8 12167
7758a113
DV		 12168 /* Pass our mode to the connectors and the CRTC to give them a chance to
12169 * adjust it according to limitations or connector properties, and also
12170 * a chance to reject the mode entirely.
47f1c6c9 12171 */
da3ced29 12172 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12173 if (connector_state->crtc != crtc)
7758a113 12174 continue;
7ae89233 12175
0b901879
ACO		 12176 encoder = to_intel_encoder(connector_state->best_encoder);
12177
efea6e8e
DV		 12178 if (!(encoder->compute_config(encoder, pipe_config))) {
12179 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12180 goto fail;
12181 }
ee7b9f93 12182 }
47f1c6c9 12183
ff9a6750
DV		 12184 /* Set default port clock if not overwritten by the encoder. Needs to be
12185 * done afterwards in case the encoder adjusts the mode. */
12186 if (!pipe_config->port_clock)
2d112de7 12187 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12188 * pipe_config->pixel_multiplier;
ff9a6750 12189
a43f6e0f 12190 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12191 if (ret < 0) {
7758a113
DV		 12192 DRM_DEBUG_KMS("CRTC fixup failed\n");
12193 goto fail;
ee7b9f93 12194 }
e29c22c0
DV		 12195
12196 if (ret == RETRY) {
12197 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12198 ret = -EINVAL;
12199 goto fail;
12200 }
12201
12202 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12203 retry = false;
12204 goto encoder_retry;
12205 }
12206
d328c9d7 12207 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12208 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12209 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12210
548ee15b 12211 return 0;
7758a113 12212fail:
548ee15b 12213 return ret;
ee7b9f93 12214}
47f1c6c9 12215
ea9d758d 12216static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12217{
ea9d758d 12218 struct drm_encoder *encoder;
f6e5b160 12219 struct drm_device *dev = crtc->dev;
f6e5b160 12220
ea9d758d
DV		 12221 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12222 if (encoder->crtc == crtc)
12223 return true;
12224
12225 return false;
12226}
12227
0a9ab303
ACO		 12228static bool
12229needs_modeset(struct drm_crtc_state *state)
12230{
12231 return state->mode_changed || state->active_changed;
12232}
12233
ea9d758d 12234static void
0a9ab303 12235intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12236{
0a9ab303 12237 struct drm_device *dev = state->dev;
ba41c0de 12238 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 12239 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12240 struct drm_crtc *crtc;
12241 struct drm_crtc_state *crtc_state;
ea9d758d
DV		 12242 struct drm_connector *connector;
12243
ba41c0de 12244 intel_shared_dpll_commit(dev_priv);
69024de8 12245 drm_atomic_helper_swap_state(state->dev, state);
ba41c0de 12246
b2784e15 12247 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12248 if (!intel_encoder->base.crtc)
12249 continue;
12250
69024de8
ML		 12251 crtc = intel_encoder->base.crtc;
12252 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12253 if (!crtc_state || !needs_modeset(crtc->state))
12254 continue;
ea9d758d 12255
69024de8 12256 intel_encoder->connectors_active = false;
ea9d758d
DV		 12257 }
12258
a821fc46 12259 intel_modeset_fixup_state(state);
ea9d758d 12260
7668851f 12261 /* Double check state. */
0a9ab303
ACO		 12262 for_each_crtc(dev, crtc) {
12263 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV		 12264 }
12265
12266 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12267 if (!connector->encoder || !connector->encoder->crtc)
12268 continue;
12269
69024de8
ML		 12270 crtc = connector->encoder->crtc;
12271 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12272 if (!crtc_state || !needs_modeset(crtc->state))
12273 continue;
ea9d758d 12274
69024de8
ML		 12275 if (crtc->state->enable) {
12276 struct drm_property *dpms_property =
12277 dev->mode_config.dpms_property;
68d34720 12278
69024de8
ML		 12279 connector->dpms = DRM_MODE_DPMS_ON;
12280 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12281
69024de8
ML		 12282 intel_encoder = to_intel_encoder(connector->encoder);
12283 intel_encoder->connectors_active = true;
12284 } else
12285 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12286 }
ea9d758d
DV		 12287}
12288
3bd26263 12289static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12290{
3bd26263 12291 int diff;
f1f644dc
JB		 12292
12293 if (clock1 == clock2)
12294 return true;
12295
12296 if (!clock1 || !clock2)
12297 return false;
12298
12299 diff = abs(clock1 - clock2);
12300
12301 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12302 return true;
12303
12304 return false;
12305}
12306
25c5b266
DV		 12307#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12308 list_for_each_entry((intel_crtc), \
12309 &(dev)->mode_config.crtc_list, \
12310 base.head) \
0973f18f 12311 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12312
0e8ffe1b 12313static bool
2fa2fe9a 12314intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12315 struct intel_crtc_state *current_config,
12316 struct intel_crtc_state *pipe_config)
0e8ffe1b 12317{
66e985c0
DV		 12318#define PIPE_CONF_CHECK_X(name) \
12319 if (current_config->name != pipe_config->name) { \
12320 DRM_ERROR("mismatch in " #name " " \
12321 "(expected 0x%08x, found 0x%08x)\n", \
12322 current_config->name, \
12323 pipe_config->name); \
12324 return false; \
12325 }
12326
08a24034
DV		 12327#define PIPE_CONF_CHECK_I(name) \
12328 if (current_config->name != pipe_config->name) { \
12329 DRM_ERROR("mismatch in " #name " " \
12330 "(expected %i, found %i)\n", \
12331 current_config->name, \
12332 pipe_config->name); \
12333 return false; \
88adfff1
DV		 12334 }
12335
b95af8be
VK		 12336/* This is required for BDW+ where there is only one set of registers for
12337 * switching between high and low RR.
12338 * This macro can be used whenever a comparison has to be made between one
12339 * hw state and multiple sw state variables.
12340 */
12341#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12342 if ((current_config->name != pipe_config->name) && \
12343 (current_config->alt_name != pipe_config->name)) { \
12344 DRM_ERROR("mismatch in " #name " " \
12345 "(expected %i or %i, found %i)\n", \
12346 current_config->name, \
12347 current_config->alt_name, \
12348 pipe_config->name); \
12349 return false; \
12350 }
12351
1bd1bd80
DV		 12352#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12353 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12354 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12355 "(expected %i, found %i)\n", \
12356 current_config->name & (mask), \
12357 pipe_config->name & (mask)); \
12358 return false; \
12359 }
12360
5e550656
VS		 12361#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12362 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12363 DRM_ERROR("mismatch in " #name " " \
12364 "(expected %i, found %i)\n", \
12365 current_config->name, \
12366 pipe_config->name); \
12367 return false; \
12368 }
12369
bb760063
DV		 12370#define PIPE_CONF_QUIRK(quirk) \
12371 ((current_config->quirks | pipe_config->quirks) & (quirk))
12372
eccb140b
DV		 12373 PIPE_CONF_CHECK_I(cpu_transcoder);
12374
08a24034
DV		 12375 PIPE_CONF_CHECK_I(has_pch_encoder);
12376 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12377 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12378 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12379 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12380 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12381 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12382
eb14cb74 12383 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12384
12385 if (INTEL_INFO(dev)->gen < 8) {
12386 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12387 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12388 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12389 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12390 PIPE_CONF_CHECK_I(dp_m_n.tu);
12391
12392 if (current_config->has_drrs) {
12393 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12394 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12395 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12396 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12397 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12398 }
12399 } else {
12400 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12401 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12402 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12403 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12404 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12405 }
eb14cb74 12406
2d112de7
ACO		 12407 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12408 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12409 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12410 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12411 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12412 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12413
2d112de7
ACO		 12414 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12415 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12416 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12417 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12418 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12419 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12420
c93f54cf 12421 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12422 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12423 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12424 IS_VALLEYVIEW(dev))
12425 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12426 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12427
9ed109a7
DV		 12428 PIPE_CONF_CHECK_I(has_audio);
12429
2d112de7 12430 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12431 DRM_MODE_FLAG_INTERLACE);
12432
bb760063 12433 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12434 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12435 DRM_MODE_FLAG_PHSYNC);
2d112de7 12436 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12437 DRM_MODE_FLAG_NHSYNC);
2d112de7 12438 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12439 DRM_MODE_FLAG_PVSYNC);
2d112de7 12440 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12441 DRM_MODE_FLAG_NVSYNC);
12442 }
045ac3b5 12443
37327abd
VS		 12444 PIPE_CONF_CHECK_I(pipe_src_w);
12445 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12446
9953599b
DV		 12447 /*
12448 * FIXME: BIOS likes to set up a cloned config with lvds+external
12449 * screen. Since we don't yet re-compute the pipe config when moving
12450 * just the lvds port away to another pipe the sw tracking won't match.
12451 *
12452 * Proper atomic modesets with recomputed global state will fix this.
12453 * Until then just don't check gmch state for inherited modes.
12454 */
12455 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12456 PIPE_CONF_CHECK_I(gmch_pfit.control);
12457 /* pfit ratios are autocomputed by the hw on gen4+ */
12458 if (INTEL_INFO(dev)->gen < 4)
12459 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12460 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12461 }
12462
fd4daa9c
CW		 12463 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12464 if (current_config->pch_pfit.enabled) {
12465 PIPE_CONF_CHECK_I(pch_pfit.pos);
12466 PIPE_CONF_CHECK_I(pch_pfit.size);
12467 }
2fa2fe9a 12468
a1b2278e
CK		 12469 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12470
e59150dc
JB		 12471 /* BDW+ don't expose a synchronous way to read the state */
12472 if (IS_HASWELL(dev))
12473 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12474
282740f7
VS		 12475 PIPE_CONF_CHECK_I(double_wide);
12476
26804afd
DV		 12477 PIPE_CONF_CHECK_X(ddi_pll_sel);
12478
c0d43d62 12479 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12480 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12481 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12482 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12483 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12484 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12485 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12486 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12487 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12488
42571aef
VS		 12489 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12490 PIPE_CONF_CHECK_I(pipe_bpp);
12491
2d112de7 12492 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12493 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12494
66e985c0 12495#undef PIPE_CONF_CHECK_X
08a24034 12496#undef PIPE_CONF_CHECK_I
b95af8be 12497#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12498#undef PIPE_CONF_CHECK_FLAGS
5e550656 12499#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12500#undef PIPE_CONF_QUIRK
88adfff1 12501
0e8ffe1b
DV		 12502 return true;
12503}
12504
08db6652
DL		 12505static void check_wm_state(struct drm_device *dev)
12506{
12507 struct drm_i915_private *dev_priv = dev->dev_private;
12508 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12509 struct intel_crtc *intel_crtc;
12510 int plane;
12511
12512 if (INTEL_INFO(dev)->gen < 9)
12513 return;
12514
12515 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12516 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12517
12518 for_each_intel_crtc(dev, intel_crtc) {
12519 struct skl_ddb_entry *hw_entry, *sw_entry;
12520 const enum pipe pipe = intel_crtc->pipe;
12521
12522 if (!intel_crtc->active)
12523 continue;
12524
12525 /* planes */
dd740780 12526 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12527 hw_entry = &hw_ddb.plane[pipe][plane];
12528 sw_entry = &sw_ddb->plane[pipe][plane];
12529
12530 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12531 continue;
12532
12533 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12534 "(expected (%u,%u), found (%u,%u))\n",
12535 pipe_name(pipe), plane + 1,
12536 sw_entry->start, sw_entry->end,
12537 hw_entry->start, hw_entry->end);
12538 }
12539
12540 /* cursor */
12541 hw_entry = &hw_ddb.cursor[pipe];
12542 sw_entry = &sw_ddb->cursor[pipe];
12543
12544 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12545 continue;
12546
12547 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12548 "(expected (%u,%u), found (%u,%u))\n",
12549 pipe_name(pipe),
12550 sw_entry->start, sw_entry->end,
12551 hw_entry->start, hw_entry->end);
12552 }
12553}
12554
91d1b4bd
DV		 12555static void
12556check_connector_state(struct drm_device *dev)
8af6cf88 12557{
8af6cf88
DV		 12558 struct intel_connector *connector;
12559
3a3371ff 12560 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12561 /* This also checks the encoder/connector hw state with the
12562 * ->get_hw_state callbacks. */
12563 intel_connector_check_state(connector);
12564
e2c719b7 12565 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12566 "connector's staged encoder doesn't match current encoder\n");
12567 }
91d1b4bd
DV		 12568}
12569
12570static void
12571check_encoder_state(struct drm_device *dev)
12572{
12573 struct intel_encoder *encoder;
12574 struct intel_connector *connector;
8af6cf88 12575
b2784e15 12576 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12577 bool enabled = false;
12578 bool active = false;
12579 enum pipe pipe, tracked_pipe;
12580
12581 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12582 encoder->base.base.id,
8e329a03 12583 encoder->base.name);
8af6cf88 12584
e2c719b7 12585 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12586 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12587 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12588 "encoder's active_connectors set, but no crtc\n");
12589
3a3371ff 12590 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12591 if (connector->base.encoder != &encoder->base)
12592 continue;
12593 enabled = true;
12594 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12595 active = true;
12596 }
0e32b39c
DA		 12597 /*
12598 * for MST connectors if we unplug the connector is gone
12599 * away but the encoder is still connected to a crtc
12600 * until a modeset happens in response to the hotplug.
12601 */
12602 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12603 continue;
12604
e2c719b7 12605 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12606 "encoder's enabled state mismatch "
12607 "(expected %i, found %i)\n",
12608 !!encoder->base.crtc, enabled);
e2c719b7 12609 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12610 "active encoder with no crtc\n");
12611
e2c719b7 12612 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12613 "encoder's computed active state doesn't match tracked active state "
12614 "(expected %i, found %i)\n", active, encoder->connectors_active);
12615
12616 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12617 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12618 "encoder's hw state doesn't match sw tracking "
12619 "(expected %i, found %i)\n",
12620 encoder->connectors_active, active);
12621
12622 if (!encoder->base.crtc)
12623 continue;
12624
12625 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12626 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12627 "active encoder's pipe doesn't match"
12628 "(expected %i, found %i)\n",
12629 tracked_pipe, pipe);
12630
12631 }
91d1b4bd
DV		 12632}
12633
12634static void
12635check_crtc_state(struct drm_device *dev)
12636{
fbee40df 12637 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12638 struct intel_crtc *crtc;
12639 struct intel_encoder *encoder;
5cec258b 12640 struct intel_crtc_state pipe_config;
8af6cf88 12641
d3fcc808 12642 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12643 bool enabled = false;
12644 bool active = false;
12645
045ac3b5
JB		 12646 memset(&pipe_config, 0, sizeof(pipe_config));
12647
8af6cf88
DV		 12648 DRM_DEBUG_KMS("[CRTC:%d]\n",
12649 crtc->base.base.id);
12650
83d65738 12651 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12652 "active crtc, but not enabled in sw tracking\n");
12653
b2784e15 12654 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12655 if (encoder->base.crtc != &crtc->base)
12656 continue;
12657 enabled = true;
12658 if (encoder->connectors_active)
12659 active = true;
12660 }
6c49f241 12661
e2c719b7 12662 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12663 "crtc's computed active state doesn't match tracked active state "
12664 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12665 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12666 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12667 "(expected %i, found %i)\n", enabled,
12668 crtc->base.state->enable);
8af6cf88 12669
0e8ffe1b
DV		 12670 active = dev_priv->display.get_pipe_config(crtc,
12671 &pipe_config);
d62cf62a 12672
b6b5d049
VS		 12673 /* hw state is inconsistent with the pipe quirk */
12674 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12675 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12676 active = crtc->active;
12677
b2784e15 12678 for_each_intel_encoder(dev, encoder) {
3eaba51c 12679 enum pipe pipe;
6c49f241
DV		 12680 if (encoder->base.crtc != &crtc->base)
12681 continue;
1d37b689 12682 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12683 encoder->get_config(encoder, &pipe_config);
12684 }
12685
e2c719b7 12686 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12687 "crtc active state doesn't match with hw state "
12688 "(expected %i, found %i)\n", crtc->active, active);
12689
c0b03411 12690 if (active &&
6e3c9717 12691 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12692 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12693 intel_dump_pipe_config(crtc, &pipe_config,
12694 "[hw state]");
6e3c9717 12695 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12696 "[sw state]");
12697 }
8af6cf88
DV		 12698 }
12699}
12700
91d1b4bd
DV		 12701static void
12702check_shared_dpll_state(struct drm_device *dev)
12703{
fbee40df 12704 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12705 struct intel_crtc *crtc;
12706 struct intel_dpll_hw_state dpll_hw_state;
12707 int i;
5358901f
DV		 12708
12709 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12710 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12711 int enabled_crtcs = 0, active_crtcs = 0;
12712 bool active;
12713
12714 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12715
12716 DRM_DEBUG_KMS("%s\n", pll->name);
12717
12718 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12719
e2c719b7 12720 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12721 "more active pll users than references: %i vs %i\n",
3e369b76 12722 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12723 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12724 "pll in active use but not on in sw tracking\n");
e2c719b7 12725 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12726 "pll in on but not on in use in sw tracking\n");
e2c719b7 12727 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12728 "pll on state mismatch (expected %i, found %i)\n",
12729 pll->on, active);
12730
d3fcc808 12731 for_each_intel_crtc(dev, crtc) {
83d65738 12732 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12733 enabled_crtcs++;
12734 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12735 active_crtcs++;
12736 }
e2c719b7 12737 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12738 "pll active crtcs mismatch (expected %i, found %i)\n",
12739 pll->active, active_crtcs);
e2c719b7 12740 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12741 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12742 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12743
e2c719b7 12744 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12745 sizeof(dpll_hw_state)),
12746 "pll hw state mismatch\n");
5358901f 12747 }
8af6cf88
DV		 12748}
12749
91d1b4bd
DV		 12750void
12751intel_modeset_check_state(struct drm_device *dev)
12752{
08db6652 12753 check_wm_state(dev);
91d1b4bd
DV		 12754 check_connector_state(dev);
12755 check_encoder_state(dev);
12756 check_crtc_state(dev);
12757 check_shared_dpll_state(dev);
12758}
12759
5cec258b 12760void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12761 int dotclock)
12762{
12763 /*
12764 * FDI already provided one idea for the dotclock.
12765 * Yell if the encoder disagrees.
12766 */
2d112de7 12767 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12768 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12769 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12770}
12771
80715b2f
VS		 12772static void update_scanline_offset(struct intel_crtc *crtc)
12773{
12774 struct drm_device *dev = crtc->base.dev;
12775
12776 /*
12777 * The scanline counter increments at the leading edge of hsync.
12778 *
12779 * On most platforms it starts counting from vtotal-1 on the
12780 * first active line. That means the scanline counter value is
12781 * always one less than what we would expect. Ie. just after
12782 * start of vblank, which also occurs at start of hsync (on the
12783 * last active line), the scanline counter will read vblank_start-1.
12784 *
12785 * On gen2 the scanline counter starts counting from 1 instead
12786 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12787 * to keep the value positive), instead of adding one.
12788 *
12789 * On HSW+ the behaviour of the scanline counter depends on the output
12790 * type. For DP ports it behaves like most other platforms, but on HDMI
12791 * there's an extra 1 line difference. So we need to add two instead of
12792 * one to the value.
12793 */
12794 if (IS_GEN2(dev)) {
6e3c9717 12795 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12796 int vtotal;
12797
12798 vtotal = mode->crtc_vtotal;
12799 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12800 vtotal /= 2;
12801
12802 crtc->scanline_offset = vtotal - 1;
12803 } else if (HAS_DDI(dev) &&
409ee761 12804 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12805 crtc->scanline_offset = 2;
12806 } else
12807 crtc->scanline_offset = 1;
12808}
12809
5cec258b 12810static struct intel_crtc_state *
7f27126e 12811intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12812 struct drm_atomic_state *state)
7f27126e 12813{
548ee15b 12814 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12815 int ret = 0;
12816
12817 ret = drm_atomic_add_affected_connectors(state, crtc);
12818 if (ret)
12819 return ERR_PTR(ret);
7f27126e 12820
8c7b5ccb
ACO		 12821 ret = drm_atomic_helper_check_modeset(state->dev, state);
12822 if (ret)
12823 return ERR_PTR(ret);
7f27126e 12824
7f27126e
JB		 12825 /*
12826 * Note this needs changes when we start tracking multiple modes
12827 * and crtcs. At that point we'll need to compute the whole config
12828 * (i.e. one pipe_config for each crtc) rather than just the one
12829 * for this crtc.
12830 */
548ee15b
ACO		 12831 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12832 if (IS_ERR(pipe_config))
12833 return pipe_config;
83a57153 12834
4fed33f6 12835 if (!pipe_config->base.enable)
548ee15b 12836 return pipe_config;
7f27126e 12837
8c7b5ccb 12838 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12839 if (ret)
12840 return ERR_PTR(ret);
12841
8d8c9b51
ACO		 12842 /* Check things that can only be changed through modeset */
12843 if (pipe_config->has_audio !=
12844 to_intel_crtc(crtc)->config->has_audio)
12845 pipe_config->base.mode_changed = true;
12846
12847 /*
12848 * Note we have an issue here with infoframes: current code
12849 * only updates them on the full mode set path per hw
12850 * requirements. So here we should be checking for any
12851 * required changes and forcing a mode set.
12852 */
12853
548ee15b 12854 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12855
8c7b5ccb
ACO		 12856 ret = drm_atomic_helper_check_planes(state->dev, state);
12857 if (ret)
12858 return ERR_PTR(ret);
12859
548ee15b 12860 return pipe_config;
7f27126e
JB		 12861}
12862
0a9ab303 12863static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12864{
225da59b 12865 struct drm_device *dev = state->dev;
ed6739ef 12866 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12867 unsigned clear_pipes = 0;
ed6739ef 12868 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12869 struct intel_crtc_state *intel_crtc_state;
12870 struct drm_crtc *crtc;
12871 struct drm_crtc_state *crtc_state;
ed6739ef 12872 int ret = 0;
0a9ab303 12873 int i;
ed6739ef
ACO		 12874
12875 if (!dev_priv->display.crtc_compute_clock)
12876 return 0;
12877
0a9ab303
ACO		 12878 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12879 intel_crtc = to_intel_crtc(crtc);
4978cc93 12880 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12881
4978cc93 12882 if (needs_modeset(crtc_state)) {
0a9ab303 12883 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12884 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12885 }
0a9ab303
ACO		 12886 }
12887
ed6739ef
ACO		 12888 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12889 if (ret)
12890 goto done;
12891
0a9ab303
ACO		 12892 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12893 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12894 continue;
12895
0a9ab303
ACO		 12896 intel_crtc = to_intel_crtc(crtc);
12897 intel_crtc_state = to_intel_crtc_state(crtc_state);
12898
ed6739ef 12899 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12900 intel_crtc_state);
ed6739ef
ACO		 12901 if (ret) {
12902 intel_shared_dpll_abort_config(dev_priv);
12903 goto done;
12904 }
12905 }
12906
12907done:
12908 return ret;
12909}
12910
054518dd
ACO		 12911/* Code that should eventually be part of atomic_check() */
12912static int __intel_set_mode_checks(struct drm_atomic_state *state)
12913{
12914 struct drm_device *dev = state->dev;
12915 int ret;
12916
12917 /*
12918 * See if the config requires any additional preparation, e.g.
12919 * to adjust global state with pipes off. We need to do this
12920 * here so we can get the modeset_pipe updated config for the new
12921 * mode set on this crtc. For other crtcs we need to use the
12922 * adjusted_mode bits in the crtc directly.
12923 */
b432e5cf
VS		 12924 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12925 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12926 ret = valleyview_modeset_global_pipes(state);
12927 else
12928 ret = broadwell_modeset_global_pipes(state);
12929
054518dd
ACO		 12930 if (ret)
12931 return ret;
12932 }
12933
12934 ret = __intel_set_mode_setup_plls(state);
12935 if (ret)
12936 return ret;
12937
12938 return 0;
12939}
12940
0a9ab303 12941static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12942 struct intel_crtc_state *pipe_config)
a6778b3c 12943{
0a9ab303 12944 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12945 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12946 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 12947 struct drm_crtc *crtc;
12948 struct drm_crtc_state *crtc_state;
c0c36b94 12949 int ret = 0;
0a9ab303 12950 int i;
a6778b3c 12951
054518dd
ACO		 12952 ret = __intel_set_mode_checks(state);
12953 if (ret < 0)
12954 return ret;
12955
d4afb8cc
ACO		 12956 ret = drm_atomic_helper_prepare_planes(dev, state);
12957 if (ret)
12958 return ret;
12959
0a9ab303
ACO		 12960 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12961 if (!needs_modeset(crtc_state))
12962 continue;
460da916 12963
69024de8
ML		 12964 intel_crtc_disable_planes(crtc);
12965 dev_priv->display.crtc_disable(crtc);
12966 if (!crtc_state->enable)
12967 drm_plane_helper_disable(crtc->primary);
ea9d758d 12968 }
a6778b3c 12969
6c4c86f5
DV		 12970 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12971 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12972 *
12973 * Note we'll need to fix this up when we start tracking multiple
12974 * pipes; here we assume a single modeset_pipe and only track the
12975 * single crtc and mode.
f6e5b160 12976 */
0a9ab303 12977 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 12978 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS		 12979
12980 /*
12981 * Calculate and store various constants which
12982 * are later needed by vblank and swap-completion
12983 * timestamping. They are derived from true hwmode.
12984 */
0a9ab303 12985 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 12986 &pipe_config->base.adjusted_mode);
b8cecdf5 12987 }
7758a113 12988
ea9d758d
DV		 12989 /* Only after disabling all output pipelines that will be changed can we
12990 * update the the output configuration. */
0a9ab303 12991 intel_modeset_update_state(state);
f6e5b160 12992
a821fc46
ACO		 12993 /* The state has been swaped above, so state actually contains the
12994 * old state now. */
12995
304603f4 12996 modeset_update_crtc_power_domains(state);
47fab737 12997
d4afb8cc 12998 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12999
13000 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13001 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 13002 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 13003 continue;
13004
13005 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 13006
0a9ab303
ACO		 13007 dev_priv->display.crtc_enable(crtc);
13008 intel_crtc_enable_planes(crtc);
80715b2f 13009 }
a6778b3c 13010
a6778b3c 13011 /* FIXME: add subpixel order */
83a57153 13012
d4afb8cc
ACO		 13013 drm_atomic_helper_cleanup_planes(dev, state);
13014
2bfb4627
ACO		 13015 drm_atomic_state_free(state);
13016
9eb45f22 13017 return 0;
f6e5b160
CW		 13018}
13019
0a9ab303 13020static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 13021 struct intel_crtc_state *pipe_config)
f30da187
DV		 13022{
13023 int ret;
13024
8c7b5ccb 13025 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 13026
13027 if (ret == 0)
13028 intel_modeset_check_state(crtc->dev);
13029
13030 return ret;
13031}
13032
7f27126e 13033static int intel_set_mode(struct drm_crtc *crtc,
83a57153 13034 struct drm_atomic_state *state)
7f27126e 13035{
5cec258b 13036 struct intel_crtc_state *pipe_config;
83a57153 13037 int ret = 0;
7f27126e 13038
8c7b5ccb 13039 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 13040 if (IS_ERR(pipe_config)) {
13041 ret = PTR_ERR(pipe_config);
13042 goto out;
13043 }
13044
8c7b5ccb 13045 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 13046 if (ret)
13047 goto out;
7f27126e 13048
83a57153
ACO		 13049out:
13050 return ret;
7f27126e
JB		 13051}
13052
c0c36b94
CW		 13053void intel_crtc_restore_mode(struct drm_crtc *crtc)
13054{
83a57153
ACO		 13055 struct drm_device *dev = crtc->dev;
13056 struct drm_atomic_state *state;
4be07317 13057 struct intel_crtc *intel_crtc;
83a57153
ACO		 13058 struct intel_encoder *encoder;
13059 struct intel_connector *connector;
13060 struct drm_connector_state *connector_state;
4be07317 13061 struct intel_crtc_state *crtc_state;
2bfb4627 13062 int ret;
83a57153
ACO		 13063
13064 state = drm_atomic_state_alloc(dev);
13065 if (!state) {
13066 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13067 crtc->base.id);
13068 return;
13069 }
13070
13071 state->acquire_ctx = dev->mode_config.acquire_ctx;
13072
13073 /* The force restore path in the HW readout code relies on the staged
13074 * config still keeping the user requested config while the actual
13075 * state has been overwritten by the configuration read from HW. We
13076 * need to copy the staged config to the atomic state, otherwise the
13077 * mode set will just reapply the state the HW is already in. */
13078 for_each_intel_encoder(dev, encoder) {
13079 if (&encoder->new_crtc->base != crtc)
13080 continue;
13081
13082 for_each_intel_connector(dev, connector) {
13083 if (connector->new_encoder != encoder)
13084 continue;
13085
13086 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13087 if (IS_ERR(connector_state)) {
13088 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13089 connector->base.base.id,
13090 connector->base.name,
13091 PTR_ERR(connector_state));
13092 continue;
13093 }
13094
13095 connector_state->crtc = crtc;
13096 connector_state->best_encoder = &encoder->base;
13097 }
13098 }
13099
4be07317
ACO		 13100 for_each_intel_crtc(dev, intel_crtc) {
13101 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13102 continue;
13103
13104 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13105 if (IS_ERR(crtc_state)) {
13106 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13107 intel_crtc->base.base.id,
13108 PTR_ERR(crtc_state));
13109 continue;
13110 }
13111
49d6fa21
ML		 13112 crtc_state->base.active = crtc_state->base.enable =
13113 intel_crtc->new_enabled;
8c7b5ccb
ACO		 13114
13115 if (&intel_crtc->base == crtc)
13116 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 13117 }
13118
d3a40d1b
ACO		 13119 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13120 crtc->primary->fb, crtc->x, crtc->y);
13121
2bfb4627
ACO		 13122 ret = intel_set_mode(crtc, state);
13123 if (ret)
13124 drm_atomic_state_free(state);
c0c36b94
CW		 13125}
13126
25c5b266
DV		 13127#undef for_each_intel_crtc_masked
13128
b7885264
ACO		 13129static bool intel_connector_in_mode_set(struct intel_connector *connector,
13130 struct drm_mode_set *set)
13131{
13132 int ro;
13133
13134 for (ro = 0; ro < set->num_connectors; ro++)
13135 if (set->connectors[ro] == &connector->base)
13136 return true;
13137
13138 return false;
13139}
13140
2e431051 13141static int
9a935856
DV		 13142intel_modeset_stage_output_state(struct drm_device *dev,
13143 struct drm_mode_set *set,
944b0c76 13144 struct drm_atomic_state *state)
50f56119 13145{
9a935856 13146 struct intel_connector *connector;
d5432a9d 13147 struct drm_connector *drm_connector;
944b0c76 13148 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13149 struct drm_crtc *crtc;
13150 struct drm_crtc_state *crtc_state;
13151 int i, ret;
50f56119 13152
9abdda74 13153 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13154 * of connectors. For paranoia, double-check this. */
13155 WARN_ON(!set->fb && (set->num_connectors != 0));
13156 WARN_ON(set->fb && (set->num_connectors == 0));
13157
3a3371ff 13158 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13159 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13160
d5432a9d
ACO		 13161 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13162 continue;
13163
13164 connector_state =
13165 drm_atomic_get_connector_state(state, &connector->base);
13166 if (IS_ERR(connector_state))
13167 return PTR_ERR(connector_state);
13168
b7885264
ACO		 13169 if (in_mode_set) {
13170 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13171 connector_state->best_encoder =
13172 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13173 }
13174
d5432a9d 13175 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13176 continue;
13177
9a935856
DV		 13178 /* If we disable the crtc, disable all its connectors. Also, if
13179 * the connector is on the changing crtc but not on the new
13180 * connector list, disable it. */
b7885264 13181 if (!set->fb || !in_mode_set) {
d5432a9d 13182 connector_state->best_encoder = NULL;
9a935856
DV		 13183
13184 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13185 connector->base.base.id,
c23cc417 13186 connector->base.name);
9a935856 13187 }
50f56119 13188 }
9a935856 13189 /* connector->new_encoder is now updated for all connectors. */
50f56119 13190
d5432a9d
ACO		 13191 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13192 connector = to_intel_connector(drm_connector);
13193
13194 if (!connector_state->best_encoder) {
13195 ret = drm_atomic_set_crtc_for_connector(connector_state,
13196 NULL);
13197 if (ret)
13198 return ret;
7668851f 13199
50f56119 13200 continue;
d5432a9d 13201 }
50f56119 13202
d5432a9d
ACO		 13203 if (intel_connector_in_mode_set(connector, set)) {
13204 struct drm_crtc *crtc = connector->base.state->crtc;
13205
13206 /* If this connector was in a previous crtc, add it
13207 * to the state. We might need to disable it. */
13208 if (crtc) {
13209 crtc_state =
13210 drm_atomic_get_crtc_state(state, crtc);
13211 if (IS_ERR(crtc_state))
13212 return PTR_ERR(crtc_state);
13213 }
13214
13215 ret = drm_atomic_set_crtc_for_connector(connector_state,
13216 set->crtc);
13217 if (ret)
13218 return ret;
13219 }
50f56119
DV		 13220
13221 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13222 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13223 connector_state->crtc)) {
5e2b584e 13224 return -EINVAL;
50f56119 13225 }
944b0c76 13226
9a935856
DV		 13227 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13228 connector->base.base.id,
c23cc417 13229 connector->base.name,
d5432a9d 13230 connector_state->crtc->base.id);
944b0c76 13231
d5432a9d
ACO		 13232 if (connector_state->best_encoder != &connector->encoder->base)
13233 connector->encoder =
13234 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13235 }
7668851f 13236
d5432a9d 13237 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13238 bool has_connectors;
13239
d5432a9d
ACO		 13240 ret = drm_atomic_add_affected_connectors(state, crtc);
13241 if (ret)
13242 return ret;
4be07317 13243
49d6fa21
ML		 13244 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13245 if (has_connectors != crtc_state->enable)
13246 crtc_state->enable =
13247 crtc_state->active = has_connectors;
7668851f
VS		 13248 }
13249
8c7b5ccb
ACO		 13250 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13251 set->fb, set->x, set->y);
13252 if (ret)
13253 return ret;
13254
13255 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13256 if (IS_ERR(crtc_state))
13257 return PTR_ERR(crtc_state);
13258
13259 if (set->mode)
13260 drm_mode_copy(&crtc_state->mode, set->mode);
13261
13262 if (set->num_connectors)
13263 crtc_state->active = true;
13264
2e431051
DV		 13265 return 0;
13266}
13267
bb546623
ACO		 13268static bool primary_plane_visible(struct drm_crtc *crtc)
13269{
13270 struct intel_plane_state *plane_state =
13271 to_intel_plane_state(crtc->primary->state);
13272
13273 return plane_state->visible;
13274}
13275
2e431051
DV		 13276static int intel_crtc_set_config(struct drm_mode_set *set)
13277{
13278 struct drm_device *dev;
83a57153 13279 struct drm_atomic_state *state = NULL;
5cec258b 13280 struct intel_crtc_state *pipe_config;
bb546623 13281 bool primary_plane_was_visible;
2e431051 13282 int ret;
2e431051 13283
8d3e375e
DV		 13284 BUG_ON(!set);
13285 BUG_ON(!set->crtc);
13286 BUG_ON(!set->crtc->helper_private);
2e431051 13287
7e53f3a4
DV		 13288 /* Enforce sane interface api - has been abused by the fb helper. */
13289 BUG_ON(!set->mode && set->fb);
13290 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13291
2e431051
DV		 13292 if (set->fb) {
13293 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13294 set->crtc->base.id, set->fb->base.id,
13295 (int)set->num_connectors, set->x, set->y);
13296 } else {
13297 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13298 }
13299
13300 dev = set->crtc->dev;
13301
83a57153 13302 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13303 if (!state)
13304 return -ENOMEM;
83a57153
ACO		 13305
13306 state->acquire_ctx = dev->mode_config.acquire_ctx;
13307
462a425a 13308 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13309 if (ret)
7cbf41d6 13310 goto out;
2e431051 13311
8c7b5ccb 13312 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 13313 if (IS_ERR(pipe_config)) {
6ac0483b 13314 ret = PTR_ERR(pipe_config);
7cbf41d6 13315 goto out;
20664591 13316 }
50f52756 13317
1f9954d0
JB		 13318 intel_update_pipe_size(to_intel_crtc(set->crtc));
13319
bb546623
ACO		 13320 primary_plane_was_visible = primary_plane_visible(set->crtc);
13321
8c7b5ccb 13322 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 13323
13324 if (ret == 0 &&
13325 pipe_config->base.enable &&
13326 pipe_config->base.planes_changed &&
13327 !needs_modeset(&pipe_config->base)) {
3b150f08 13328 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 13329
13330 /*
13331 * We need to make sure the primary plane is re-enabled if it
13332 * has previously been turned off.
13333 */
bb546623
ACO		 13334 if (ret == 0 && !primary_plane_was_visible &&
13335 primary_plane_visible(set->crtc)) {
3b150f08 13336 WARN_ON(!intel_crtc->active);
87d4300a 13337 intel_post_enable_primary(set->crtc);
3b150f08
MR		 13338 }
13339
7ca51a3a
JB		 13340 /*
13341 * In the fastboot case this may be our only check of the
13342 * state after boot. It would be better to only do it on
13343 * the first update, but we don't have a nice way of doing that
13344 * (and really, set_config isn't used much for high freq page
13345 * flipping, so increasing its cost here shouldn't be a big
13346 * deal).
13347 */
d330a953 13348 if (i915.fastboot && ret == 0)
7ca51a3a 13349 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 13350 }
13351
2d05eae1 13352 if (ret) {
bf67dfeb
DV		 13353 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13354 set->crtc->base.id, ret);
2d05eae1 13355 }
50f56119 13356
7cbf41d6 13357out:
2bfb4627
ACO		 13358 if (ret)
13359 drm_atomic_state_free(state);
50f56119
DV		 13360 return ret;
13361}
f6e5b160
CW		 13362
13363static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13364 .gamma_set = intel_crtc_gamma_set,
50f56119 13365 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13366 .destroy = intel_crtc_destroy,
13367 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13368 .atomic_duplicate_state = intel_crtc_duplicate_state,
13369 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13370};
13371
5358901f
DV		 13372static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13373 struct intel_shared_dpll *pll,
13374 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13375{
5358901f 13376 uint32_t val;
ee7b9f93 13377
f458ebbc 13378 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13379 return false;
13380
5358901f 13381 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13382 hw_state->dpll = val;
13383 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13384 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13385
13386 return val & DPLL_VCO_ENABLE;
13387}
13388
15bdd4cf
DV		 13389static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13390 struct intel_shared_dpll *pll)
13391{
3e369b76
ACO		 13392 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13393 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13394}
13395
e7b903d2
DV		 13396static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13397 struct intel_shared_dpll *pll)
13398{
e7b903d2 13399 /* PCH refclock must be enabled first */
89eff4be 13400 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13401
3e369b76 13402 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13403
13404 /* Wait for the clocks to stabilize. */
13405 POSTING_READ(PCH_DPLL(pll->id));
13406 udelay(150);
13407
13408 /* The pixel multiplier can only be updated once the
13409 * DPLL is enabled and the clocks are stable.
13410 *
13411 * So write it again.
13412 */
3e369b76 13413 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13414 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13415 udelay(200);
13416}
13417
13418static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13419 struct intel_shared_dpll *pll)
13420{
13421 struct drm_device *dev = dev_priv->dev;
13422 struct intel_crtc *crtc;
e7b903d2
DV		 13423
13424 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13425 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13426 if (intel_crtc_to_shared_dpll(crtc) == pll)
13427 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13428 }
13429
15bdd4cf
DV		 13430 I915_WRITE(PCH_DPLL(pll->id), 0);
13431 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13432 udelay(200);
13433}
13434
46edb027
DV		 13435static char *ibx_pch_dpll_names[] = {
13436 "PCH DPLL A",
13437 "PCH DPLL B",
13438};
13439
7c74ade1 13440static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13441{
e7b903d2 13442 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13443 int i;
13444
7c74ade1 13445 dev_priv->num_shared_dpll = 2;
ee7b9f93 13446
e72f9fbf 13447 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13448 dev_priv->shared_dplls[i].id = i;
13449 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13450 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13451 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13452 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13453 dev_priv->shared_dplls[i].get_hw_state =
13454 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13455 }
13456}
13457
7c74ade1
DV		 13458static void intel_shared_dpll_init(struct drm_device *dev)
13459{
e7b903d2 13460 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13461
b6283055
VS		 13462 intel_update_cdclk(dev);
13463
9cd86933
DV		 13464 if (HAS_DDI(dev))
13465 intel_ddi_pll_init(dev);
13466 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13467 ibx_pch_dpll_init(dev);
13468 else
13469 dev_priv->num_shared_dpll = 0;
13470
13471 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13472}
13473
1fc0a8f7
TU		 13474/**
13475 * intel_wm_need_update - Check whether watermarks need updating
13476 * @plane: drm plane
13477 * @state: new plane state
13478 *
13479 * Check current plane state versus the new one to determine whether
13480 * watermarks need to be recalculated.
13481 *
13482 * Returns true or false.
13483 */
13484bool intel_wm_need_update(struct drm_plane *plane,
13485 struct drm_plane_state *state)
13486{
13487 /* Update watermarks on tiling changes. */
13488 if (!plane->state->fb || !state->fb ||
13489 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13490 plane->state->rotation != state->rotation)
13491 return true;
13492
13493 return false;
13494}
13495
6beb8c23
MR		 13496/**
13497 * intel_prepare_plane_fb - Prepare fb for usage on plane
13498 * @plane: drm plane to prepare for
13499 * @fb: framebuffer to prepare for presentation
13500 *
13501 * Prepares a framebuffer for usage on a display plane. Generally this
13502 * involves pinning the underlying object and updating the frontbuffer tracking
13503 * bits. Some older platforms need special physical address handling for
13504 * cursor planes.
13505 *
13506 * Returns 0 on success, negative error code on failure.
13507 */
13508int
13509intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13510 struct drm_framebuffer *fb,
13511 const struct drm_plane_state *new_state)
465c120c
MR		 13512{
13513 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13514 struct intel_plane *intel_plane = to_intel_plane(plane);
13515 enum pipe pipe = intel_plane->pipe;
13516 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13517 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13518 unsigned frontbuffer_bits = 0;
13519 int ret = 0;
465c120c 13520
ea2c67bb 13521 if (!obj)
465c120c
MR		 13522 return 0;
13523
6beb8c23
MR		 13524 switch (plane->type) {
13525 case DRM_PLANE_TYPE_PRIMARY:
13526 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13527 break;
13528 case DRM_PLANE_TYPE_CURSOR:
13529 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13530 break;
13531 case DRM_PLANE_TYPE_OVERLAY:
13532 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13533 break;
13534 }
465c120c 13535
6beb8c23 13536 mutex_lock(&dev->struct_mutex);
465c120c 13537
6beb8c23
MR		 13538 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13539 INTEL_INFO(dev)->cursor_needs_physical) {
13540 int align = IS_I830(dev) ? 16 * 1024 : 256;
13541 ret = i915_gem_object_attach_phys(obj, align);
13542 if (ret)
13543 DRM_DEBUG_KMS("failed to attach phys object\n");
13544 } else {
82bc3b2d 13545 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13546 }
465c120c 13547
6beb8c23
MR		 13548 if (ret == 0)
13549 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13550
4c34574f 13551 mutex_unlock(&dev->struct_mutex);
465c120c 13552
6beb8c23
MR		 13553 return ret;
13554}
13555
38f3ce3a
MR		 13556/**
13557 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13558 * @plane: drm plane to clean up for
13559 * @fb: old framebuffer that was on plane
13560 *
13561 * Cleans up a framebuffer that has just been removed from a plane.
13562 */
13563void
13564intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13565 struct drm_framebuffer *fb,
13566 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13567{
13568 struct drm_device *dev = plane->dev;
13569 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13570
13571 if (WARN_ON(!obj))
13572 return;
13573
13574 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13575 !INTEL_INFO(dev)->cursor_needs_physical) {
13576 mutex_lock(&dev->struct_mutex);
82bc3b2d 13577 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13578 mutex_unlock(&dev->struct_mutex);
13579 }
465c120c
MR		 13580}
13581
6156a456
CK		 13582int
13583skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13584{
13585 int max_scale;
13586 struct drm_device *dev;
13587 struct drm_i915_private *dev_priv;
13588 int crtc_clock, cdclk;
13589
13590 if (!intel_crtc || !crtc_state)
13591 return DRM_PLANE_HELPER_NO_SCALING;
13592
13593 dev = intel_crtc->base.dev;
13594 dev_priv = dev->dev_private;
13595 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13596 cdclk = dev_priv->display.get_display_clock_speed(dev);
13597
13598 if (!crtc_clock || !cdclk)
13599 return DRM_PLANE_HELPER_NO_SCALING;
13600
13601 /*
13602 * skl max scale is lower of:
13603 * close to 3 but not 3, -1 is for that purpose
13604 * or
13605 * cdclk/crtc_clock
13606 */
13607 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13608
13609 return max_scale;
13610}
13611
465c120c 13612static int
3c692a41
GP		 13613intel_check_primary_plane(struct drm_plane *plane,
13614 struct intel_plane_state *state)
13615{
32b7eeec
MR		 13616 struct drm_device *dev = plane->dev;
13617 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13618 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13619 struct intel_crtc *intel_crtc;
6156a456 13620 struct intel_crtc_state *crtc_state;
2b875c22 13621 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13622 struct drm_rect *dest = &state->dst;
13623 struct drm_rect *src = &state->src;
13624 const struct drm_rect *clip = &state->clip;
d8106366 13625 bool can_position = false;
6156a456
CK		 13626 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13627 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13628 int ret;
13629
ea2c67bb
MR		 13630 crtc = crtc ? crtc : plane->crtc;
13631 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13632 crtc_state = state->base.state ?
13633 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13634
6156a456 13635 if (INTEL_INFO(dev)->gen >= 9) {
225c228a
CK		 13636 /* use scaler when colorkey is not required */
13637 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13638 min_scale = 1;
13639 max_scale = skl_max_scale(intel_crtc, crtc_state);
13640 }
d8106366 13641 can_position = true;
6156a456 13642 }
d8106366 13643
c59cb179
MR		 13644 ret = drm_plane_helper_check_update(plane, crtc, fb,
13645 src, dest, clip,
6156a456
CK		 13646 min_scale,
13647 max_scale,
d8106366
SJ		 13648 can_position, true,
13649 &state->visible);
c59cb179
MR		 13650 if (ret)
13651 return ret;
465c120c 13652
32b7eeec 13653 if (intel_crtc->active) {
b70709a6
ML		 13654 struct intel_plane_state *old_state =
13655 to_intel_plane_state(plane->state);
13656
32b7eeec
MR		 13657 intel_crtc->atomic.wait_for_flips = true;
13658
13659 /*
13660 * FBC does not work on some platforms for rotated
13661 * planes, so disable it when rotation is not 0 and
13662 * update it when rotation is set back to 0.
13663 *
13664 * FIXME: This is redundant with the fbc update done in
13665 * the primary plane enable function except that that
13666 * one is done too late. We eventually need to unify
13667 * this.
13668 */
b70709a6 13669 if (state->visible &&
32b7eeec 13670 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13671 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13672 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13673 intel_crtc->atomic.disable_fbc = true;
13674 }
13675
b70709a6 13676 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13677 /*
13678 * BDW signals flip done immediately if the plane
13679 * is disabled, even if the plane enable is already
13680 * armed to occur at the next vblank :(
13681 */
b70709a6 13682 if (IS_BROADWELL(dev))
32b7eeec
MR		 13683 intel_crtc->atomic.wait_vblank = true;
13684 }
13685
13686 intel_crtc->atomic.fb_bits |=
13687 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13688
13689 intel_crtc->atomic.update_fbc = true;
0fda6568 13690
1fc0a8f7 13691 if (intel_wm_need_update(plane, &state->base))
0fda6568 13692 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13693 }
13694
6156a456
CK		 13695 if (INTEL_INFO(dev)->gen >= 9) {
13696 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13697 to_intel_plane(plane), state, 0);
13698 if (ret)
13699 return ret;
13700 }
13701
14af293f
GP		 13702 return 0;
13703}
13704
13705static void
13706intel_commit_primary_plane(struct drm_plane *plane,
13707 struct intel_plane_state *state)
13708{
2b875c22
MR		 13709 struct drm_crtc *crtc = state->base.crtc;
13710 struct drm_framebuffer *fb = state->base.fb;
13711 struct drm_device *dev = plane->dev;
14af293f 13712 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13713 struct intel_crtc *intel_crtc;
14af293f
GP		 13714 struct drm_rect *src = &state->src;
13715
ea2c67bb
MR		 13716 crtc = crtc ? crtc : plane->crtc;
13717 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13718
13719 plane->fb = fb;
9dc806fc
MR		 13720 crtc->x = src->x1 >> 16;
13721 crtc->y = src->y1 >> 16;
ccc759dc 13722
ccc759dc 13723 if (intel_crtc->active) {
27321ae8 13724 if (state->visible)
ccc759dc
GP		 13725 /* FIXME: kill this fastboot hack */
13726 intel_update_pipe_size(intel_crtc);
465c120c 13727
27321ae8
ML		 13728 dev_priv->display.update_primary_plane(crtc, plane->fb,
13729 crtc->x, crtc->y);
ccc759dc 13730 }
465c120c
MR		 13731}
13732
a8ad0d8e
ML		 13733static void
13734intel_disable_primary_plane(struct drm_plane *plane,
13735 struct drm_crtc *crtc,
13736 bool force)
13737{
13738 struct drm_device *dev = plane->dev;
13739 struct drm_i915_private *dev_priv = dev->dev_private;
13740
a8ad0d8e
ML		 13741 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13742}
13743
32b7eeec 13744static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13745{
32b7eeec 13746 struct drm_device *dev = crtc->dev;
140fd38d 13747 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13749 struct intel_plane *intel_plane;
13750 struct drm_plane *p;
13751 unsigned fb_bits = 0;
13752
13753 /* Track fb's for any planes being disabled */
13754 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13755 intel_plane = to_intel_plane(p);
13756
13757 if (intel_crtc->atomic.disabled_planes &
13758 (1 << drm_plane_index(p))) {
13759 switch (p->type) {
13760 case DRM_PLANE_TYPE_PRIMARY:
13761 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13762 break;
13763 case DRM_PLANE_TYPE_CURSOR:
13764 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13765 break;
13766 case DRM_PLANE_TYPE_OVERLAY:
13767 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13768 break;
13769 }
3c692a41 13770
ea2c67bb
MR		 13771 mutex_lock(&dev->struct_mutex);
13772 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13773 mutex_unlock(&dev->struct_mutex);
13774 }
13775 }
3c692a41 13776
32b7eeec
MR		 13777 if (intel_crtc->atomic.wait_for_flips)
13778 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13779
32b7eeec
MR		 13780 if (intel_crtc->atomic.disable_fbc)
13781 intel_fbc_disable(dev);
3c692a41 13782
32b7eeec
MR		 13783 if (intel_crtc->atomic.pre_disable_primary)
13784 intel_pre_disable_primary(crtc);
3c692a41 13785
32b7eeec
MR		 13786 if (intel_crtc->atomic.update_wm)
13787 intel_update_watermarks(crtc);
3c692a41 13788
32b7eeec 13789 intel_runtime_pm_get(dev_priv);
3c692a41 13790
c34c9ee4
MR		 13791 /* Perform vblank evasion around commit operation */
13792 if (intel_crtc->active)
13793 intel_crtc->atomic.evade =
13794 intel_pipe_update_start(intel_crtc,
13795 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13796}
13797
13798static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13799{
13800 struct drm_device *dev = crtc->dev;
13801 struct drm_i915_private *dev_priv = dev->dev_private;
13802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13803 struct drm_plane *p;
13804
c34c9ee4
MR		 13805 if (intel_crtc->atomic.evade)
13806 intel_pipe_update_end(intel_crtc,
13807 intel_crtc->atomic.start_vbl_count);
3c692a41 13808
140fd38d 13809 intel_runtime_pm_put(dev_priv);
3c692a41 13810
32b7eeec
MR		 13811 if (intel_crtc->atomic.wait_vblank)
13812 intel_wait_for_vblank(dev, intel_crtc->pipe);
13813
13814 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13815
13816 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13817 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13818 intel_fbc_update(dev);
ccc759dc 13819 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13820 }
3c692a41 13821
32b7eeec
MR		 13822 if (intel_crtc->atomic.post_enable_primary)
13823 intel_post_enable_primary(crtc);
3c692a41 13824
32b7eeec
MR		 13825 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13826 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13827 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13828 false, false);
13829
13830 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13831}
13832
cf4c7c12 13833/**
4a3b8769
MR		 13834 * intel_plane_destroy - destroy a plane
13835 * @plane: plane to destroy
cf4c7c12 13836 *
4a3b8769
MR		 13837 * Common destruction function for all types of planes (primary, cursor,
13838 * sprite).
cf4c7c12 13839 */
4a3b8769 13840void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13841{
13842 struct intel_plane *intel_plane = to_intel_plane(plane);
13843 drm_plane_cleanup(plane);
13844 kfree(intel_plane);
13845}
13846
65a3fea0 13847const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13848 .update_plane = drm_atomic_helper_update_plane,
13849 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13850 .destroy = intel_plane_destroy,
c196e1d6 13851 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13852 .atomic_get_property = intel_plane_atomic_get_property,
13853 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13854 .atomic_duplicate_state = intel_plane_duplicate_state,
13855 .atomic_destroy_state = intel_plane_destroy_state,
13856
465c120c
MR		 13857};
13858
13859static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13860 int pipe)
13861{
13862 struct intel_plane *primary;
8e7d688b 13863 struct intel_plane_state *state;
465c120c
MR		 13864 const uint32_t *intel_primary_formats;
13865 int num_formats;
13866
13867 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13868 if (primary == NULL)
13869 return NULL;
13870
8e7d688b
MR		 13871 state = intel_create_plane_state(&primary->base);
13872 if (!state) {
ea2c67bb
MR		 13873 kfree(primary);
13874 return NULL;
13875 }
8e7d688b 13876 primary->base.state = &state->base;
ea2c67bb 13877
465c120c
MR		 13878 primary->can_scale = false;
13879 primary->max_downscale = 1;
6156a456
CK		 13880 if (INTEL_INFO(dev)->gen >= 9) {
13881 primary->can_scale = true;
af99ceda 13882 state->scaler_id = -1;
6156a456 13883 }
465c120c
MR		 13884 primary->pipe = pipe;
13885 primary->plane = pipe;
c59cb179
MR		 13886 primary->check_plane = intel_check_primary_plane;
13887 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13888 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13889 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13890 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13891 primary->plane = !pipe;
13892
6c0fd451
DL		 13893 if (INTEL_INFO(dev)->gen >= 9) {
13894 intel_primary_formats = skl_primary_formats;
13895 num_formats = ARRAY_SIZE(skl_primary_formats);
13896 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13897 intel_primary_formats = i965_primary_formats;
13898 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13899 } else {
13900 intel_primary_formats = i8xx_primary_formats;
13901 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13902 }
13903
13904 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13905 &intel_plane_funcs,
465c120c
MR		 13906 intel_primary_formats, num_formats,
13907 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13908
3b7a5119
SJ		 13909 if (INTEL_INFO(dev)->gen >= 4)
13910 intel_create_rotation_property(dev, primary);
48404c1e 13911
ea2c67bb
MR		 13912 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13913
465c120c
MR		 13914 return &primary->base;
13915}
13916
3b7a5119
SJ		 13917void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13918{
13919 if (!dev->mode_config.rotation_property) {
13920 unsigned long flags = BIT(DRM_ROTATE_0) |
13921 BIT(DRM_ROTATE_180);
13922
13923 if (INTEL_INFO(dev)->gen >= 9)
13924 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13925
13926 dev->mode_config.rotation_property =
13927 drm_mode_create_rotation_property(dev, flags);
13928 }
13929 if (dev->mode_config.rotation_property)
13930 drm_object_attach_property(&plane->base.base,
13931 dev->mode_config.rotation_property,
13932 plane->base.state->rotation);
13933}
13934
3d7d6510 13935static int
852e787c
GP		 13936intel_check_cursor_plane(struct drm_plane *plane,
13937 struct intel_plane_state *state)
3d7d6510 13938{
2b875c22 13939 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13940 struct drm_device *dev = plane->dev;
2b875c22 13941 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13942 struct drm_rect *dest = &state->dst;
13943 struct drm_rect *src = &state->src;
13944 const struct drm_rect *clip = &state->clip;
757f9a3e 13945 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13946 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13947 unsigned stride;
13948 int ret;
3d7d6510 13949
ea2c67bb
MR		 13950 crtc = crtc ? crtc : plane->crtc;
13951 intel_crtc = to_intel_crtc(crtc);
13952
757f9a3e 13953 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13954 src, dest, clip,
3d7d6510
MR		 13955 DRM_PLANE_HELPER_NO_SCALING,
13956 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13957 true, true, &state->visible);
757f9a3e
GP		 13958 if (ret)
13959 return ret;
13960
13961
13962 /* if we want to turn off the cursor ignore width and height */
13963 if (!obj)
32b7eeec 13964 goto finish;
757f9a3e 13965
757f9a3e 13966 /* Check for which cursor types we support */
ea2c67bb
MR		 13967 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13968 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13969 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13970 return -EINVAL;
13971 }
13972
ea2c67bb
MR		 13973 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13974 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13975 DRM_DEBUG_KMS("buffer is too small\n");
13976 return -ENOMEM;
13977 }
13978
3a656b54 13979 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13980 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13981 ret = -EINVAL;
13982 }
757f9a3e 13983
32b7eeec
MR		 13984finish:
13985 if (intel_crtc->active) {
3749f463 13986 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13987 intel_crtc->atomic.update_wm = true;
13988
13989 intel_crtc->atomic.fb_bits |=
13990 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13991 }
13992
757f9a3e 13993 return ret;
852e787c 13994}
3d7d6510 13995
a8ad0d8e
ML		 13996static void
13997intel_disable_cursor_plane(struct drm_plane *plane,
13998 struct drm_crtc *crtc,
13999 bool force)
14000{
14001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14002
14003 if (!force) {
14004 plane->fb = NULL;
14005 intel_crtc->cursor_bo = NULL;
14006 intel_crtc->cursor_addr = 0;
14007 }
14008
14009 intel_crtc_update_cursor(crtc, false);
14010}
14011
f4a2cf29 14012static void
852e787c
GP		 14013intel_commit_cursor_plane(struct drm_plane *plane,
14014 struct intel_plane_state *state)
14015{
2b875c22 14016 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 14017 struct drm_device *dev = plane->dev;
14018 struct intel_crtc *intel_crtc;
2b875c22 14019 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 14020 uint32_t addr;
852e787c 14021
ea2c67bb
MR		 14022 crtc = crtc ? crtc : plane->crtc;
14023 intel_crtc = to_intel_crtc(crtc);
14024
2b875c22 14025 plane->fb = state->base.fb;
ea2c67bb
MR		 14026 crtc->cursor_x = state->base.crtc_x;
14027 crtc->cursor_y = state->base.crtc_y;
14028
a912f12f
GP		 14029 if (intel_crtc->cursor_bo == obj)
14030 goto update;
4ed91096 14031
f4a2cf29 14032 if (!obj)
a912f12f 14033 addr = 0;
f4a2cf29 14034 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 14035 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 14036 else
a912f12f 14037 addr = obj->phys_handle->busaddr;
852e787c 14038
a912f12f
GP		 14039 intel_crtc->cursor_addr = addr;
14040 intel_crtc->cursor_bo = obj;
14041update:
852e787c 14042
32b7eeec 14043 if (intel_crtc->active)
a912f12f 14044 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 14045}
14046
3d7d6510
MR		 14047static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14048 int pipe)
14049{
14050 struct intel_plane *cursor;
8e7d688b 14051 struct intel_plane_state *state;
3d7d6510
MR		 14052
14053 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14054 if (cursor == NULL)
14055 return NULL;
14056
8e7d688b
MR		 14057 state = intel_create_plane_state(&cursor->base);
14058 if (!state) {
ea2c67bb
MR		 14059 kfree(cursor);
14060 return NULL;
14061 }
8e7d688b 14062 cursor->base.state = &state->base;
ea2c67bb 14063
3d7d6510
MR		 14064 cursor->can_scale = false;
14065 cursor->max_downscale = 1;
14066 cursor->pipe = pipe;
14067 cursor->plane = pipe;
c59cb179
MR		 14068 cursor->check_plane = intel_check_cursor_plane;
14069 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 14070 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 14071
14072 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14073 &intel_plane_funcs,
3d7d6510
MR		 14074 intel_cursor_formats,
14075 ARRAY_SIZE(intel_cursor_formats),
14076 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14077
14078 if (INTEL_INFO(dev)->gen >= 4) {
14079 if (!dev->mode_config.rotation_property)
14080 dev->mode_config.rotation_property =
14081 drm_mode_create_rotation_property(dev,
14082 BIT(DRM_ROTATE_0) |
14083 BIT(DRM_ROTATE_180));
14084 if (dev->mode_config.rotation_property)
14085 drm_object_attach_property(&cursor->base.base,
14086 dev->mode_config.rotation_property,
8e7d688b 14087 state->base.rotation);
4398ad45
VS		 14088 }
14089
af99ceda
CK		 14090 if (INTEL_INFO(dev)->gen >=9)
14091 state->scaler_id = -1;
14092
ea2c67bb
MR		 14093 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14094
3d7d6510
MR		 14095 return &cursor->base;
14096}
14097
549e2bfb
CK		 14098static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14099 struct intel_crtc_state *crtc_state)
14100{
14101 int i;
14102 struct intel_scaler *intel_scaler;
14103 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14104
14105 for (i = 0; i < intel_crtc->num_scalers; i++) {
14106 intel_scaler = &scaler_state->scalers[i];
14107 intel_scaler->in_use = 0;
14108 intel_scaler->id = i;
14109
14110 intel_scaler->mode = PS_SCALER_MODE_DYN;
14111 }
14112
14113 scaler_state->scaler_id = -1;
14114}
14115
b358d0a6 14116static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14117{
fbee40df 14118 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14119 struct intel_crtc *intel_crtc;
f5de6e07 14120 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14121 struct drm_plane *primary = NULL;
14122 struct drm_plane *cursor = NULL;
465c120c 14123 int i, ret;
79e53945 14124
955382f3 14125 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14126 if (intel_crtc == NULL)
14127 return;
14128
f5de6e07
ACO		 14129 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14130 if (!crtc_state)
14131 goto fail;
550acefd
ACO		 14132 intel_crtc->config = crtc_state;
14133 intel_crtc->base.state = &crtc_state->base;
07878248 14134 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14135
549e2bfb
CK		 14136 /* initialize shared scalers */
14137 if (INTEL_INFO(dev)->gen >= 9) {
14138 if (pipe == PIPE_C)
14139 intel_crtc->num_scalers = 1;
14140 else
14141 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14142
14143 skl_init_scalers(dev, intel_crtc, crtc_state);
14144 }
14145
465c120c 14146 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14147 if (!primary)
14148 goto fail;
14149
14150 cursor = intel_cursor_plane_create(dev, pipe);
14151 if (!cursor)
14152 goto fail;
14153
465c120c 14154 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14155 cursor, &intel_crtc_funcs);
14156 if (ret)
14157 goto fail;
79e53945
JB		 14158
14159 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14160 for (i = 0; i < 256; i++) {
14161 intel_crtc->lut_r[i] = i;
14162 intel_crtc->lut_g[i] = i;
14163 intel_crtc->lut_b[i] = i;
14164 }
14165
1f1c2e24
VS		 14166 /*
14167 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14168 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14169 */
80824003
JB		 14170 intel_crtc->pipe = pipe;
14171 intel_crtc->plane = pipe;
3a77c4c4 14172 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14173 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14174 intel_crtc->plane = !pipe;
80824003
JB		 14175 }
14176
4b0e333e
CW		 14177 intel_crtc->cursor_base = ~0;
14178 intel_crtc->cursor_cntl = ~0;
dc41c154 14179 intel_crtc->cursor_size = ~0;
8d7849db 14180
22fd0fab
JB		 14181 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14182 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14183 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14184 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14185
79e53945 14186 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14187
14188 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14189 return;
14190
14191fail:
14192 if (primary)
14193 drm_plane_cleanup(primary);
14194 if (cursor)
14195 drm_plane_cleanup(cursor);
f5de6e07 14196 kfree(crtc_state);
3d7d6510 14197 kfree(intel_crtc);
79e53945
JB		 14198}
14199
752aa88a
JB		 14200enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14201{
14202 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14203 struct drm_device *dev = connector->base.dev;
752aa88a 14204
51fd371b 14205 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14206
d3babd3f 14207 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14208 return INVALID_PIPE;
14209
14210 return to_intel_crtc(encoder->crtc)->pipe;
14211}
14212
08d7b3d1 14213int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14214 struct drm_file *file)
08d7b3d1 14215{
08d7b3d1 14216 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14217 struct drm_crtc *drmmode_crtc;
c05422d5 14218 struct intel_crtc *crtc;
08d7b3d1 14219
7707e653 14220 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14221
7707e653 14222 if (!drmmode_crtc) {
08d7b3d1 14223 DRM_ERROR("no such CRTC id\n");
3f2c2057 14224 return -ENOENT;
08d7b3d1
CW		 14225 }
14226
7707e653 14227 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14228 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14229
c05422d5 14230 return 0;
08d7b3d1
CW		 14231}
14232
66a9278e 14233static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14234{
66a9278e
DV		 14235 struct drm_device *dev = encoder->base.dev;
14236 struct intel_encoder *source_encoder;
79e53945 14237 int index_mask = 0;
79e53945
JB		 14238 int entry = 0;
14239
b2784e15 14240 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14241 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14242 index_mask |= (1 << entry);
14243
79e53945
JB		 14244 entry++;
14245 }
4ef69c7a 14246
79e53945
JB		 14247 return index_mask;
14248}
14249
4d302442
CW		 14250static bool has_edp_a(struct drm_device *dev)
14251{
14252 struct drm_i915_private *dev_priv = dev->dev_private;
14253
14254 if (!IS_MOBILE(dev))
14255 return false;
14256
14257 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14258 return false;
14259
e3589908 14260 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14261 return false;
14262
14263 return true;
14264}
14265
84b4e042
JB		 14266static bool intel_crt_present(struct drm_device *dev)
14267{
14268 struct drm_i915_private *dev_priv = dev->dev_private;
14269
884497ed
DL		 14270 if (INTEL_INFO(dev)->gen >= 9)
14271 return false;
14272
cf404ce4 14273 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14274 return false;
14275
14276 if (IS_CHERRYVIEW(dev))
14277 return false;
14278
14279 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14280 return false;
14281
14282 return true;
14283}
14284
79e53945
JB		 14285static void intel_setup_outputs(struct drm_device *dev)
14286{
725e30ad 14287 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14288 struct intel_encoder *encoder;
cb0953d7 14289 bool dpd_is_edp = false;
79e53945 14290
c9093354 14291 intel_lvds_init(dev);
79e53945 14292
84b4e042 14293 if (intel_crt_present(dev))
79935fca 14294 intel_crt_init(dev);
cb0953d7 14295
c776eb2e
VK		 14296 if (IS_BROXTON(dev)) {
14297 /*
14298 * FIXME: Broxton doesn't support port detection via the
14299 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14300 * detect the ports.
14301 */
14302 intel_ddi_init(dev, PORT_A);
14303 intel_ddi_init(dev, PORT_B);
14304 intel_ddi_init(dev, PORT_C);
14305 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14306 int found;
14307
de31facd
JB		 14308 /*
14309 * Haswell uses DDI functions to detect digital outputs.
14310 * On SKL pre-D0 the strap isn't connected, so we assume
14311 * it's there.
14312 */
0e72a5b5 14313 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14314 /* WaIgnoreDDIAStrap: skl */
14315 if (found ||
14316 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14317 intel_ddi_init(dev, PORT_A);
14318
14319 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14320 * register */
14321 found = I915_READ(SFUSE_STRAP);
14322
14323 if (found & SFUSE_STRAP_DDIB_DETECTED)
14324 intel_ddi_init(dev, PORT_B);
14325 if (found & SFUSE_STRAP_DDIC_DETECTED)
14326 intel_ddi_init(dev, PORT_C);
14327 if (found & SFUSE_STRAP_DDID_DETECTED)
14328 intel_ddi_init(dev, PORT_D);
14329 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14330 int found;
5d8a7752 14331 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14332
14333 if (has_edp_a(dev))
14334 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14335
dc0fa718 14336 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14337 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14338 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14339 if (!found)
e2debe91 14340 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14341 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14342 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14343 }
14344
dc0fa718 14345 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14346 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14347
dc0fa718 14348 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14349 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14350
5eb08b69 14351 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14352 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14353
270b3042 14354 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14355 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14356 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14357 /*
14358 * The DP_DETECTED bit is the latched state of the DDC
14359 * SDA pin at boot. However since eDP doesn't require DDC
14360 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14361 * eDP ports may have been muxed to an alternate function.
14362 * Thus we can't rely on the DP_DETECTED bit alone to detect
14363 * eDP ports. Consult the VBT as well as DP_DETECTED to
14364 * detect eDP ports.
14365 */
d2182a66
VS		 14366 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14367 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14368 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14369 PORT_B);
e17ac6db
VS		 14370 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14371 intel_dp_is_edp(dev, PORT_B))
14372 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14373
d2182a66
VS		 14374 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14375 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14376 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14377 PORT_C);
e17ac6db
VS		 14378 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14379 intel_dp_is_edp(dev, PORT_C))
14380 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14381
9418c1f1 14382 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14383 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14384 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14385 PORT_D);
e17ac6db
VS		 14386 /* eDP not supported on port D, so don't check VBT */
14387 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14388 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14389 }
14390
3cfca973 14391 intel_dsi_init(dev);
103a196f 14392 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14393 bool found = false;
7d57382e 14394
e2debe91 14395 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14396 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14397 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14398 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14399 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14400 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14401 }
27185ae1 14402
e7281eab 14403 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14404 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14405 }
13520b05
KH		 14406
14407 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14408
e2debe91 14409 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14410 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14411 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14412 }
27185ae1 14413
e2debe91 14414 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14415
b01f2c3a
JB		 14416 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14417 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14418 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14419 }
e7281eab 14420 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14421 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14422 }
27185ae1 14423
b01f2c3a 14424 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14425 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14426 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14427 } else if (IS_GEN2(dev))
79e53945
JB		 14428 intel_dvo_init(dev);
14429
103a196f 14430 if (SUPPORTS_TV(dev))
79e53945
JB		 14431 intel_tv_init(dev);
14432
0bc12bcb 14433 intel_psr_init(dev);
7c8f8a70 14434
b2784e15 14435 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14436 encoder->base.possible_crtcs = encoder->crtc_mask;
14437 encoder->base.possible_clones =
66a9278e 14438 intel_encoder_clones(encoder);
79e53945 14439 }
47356eb6 14440
dde86e2d 14441 intel_init_pch_refclk(dev);
270b3042
DV		 14442
14443 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14444}
14445
14446static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14447{
60a5ca01 14448 struct drm_device *dev = fb->dev;
79e53945 14449 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14450
ef2d633e 14451 drm_framebuffer_cleanup(fb);
60a5ca01 14452 mutex_lock(&dev->struct_mutex);
ef2d633e 14453 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14454 drm_gem_object_unreference(&intel_fb->obj->base);
14455 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14456 kfree(intel_fb);
14457}
14458
14459static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14460 struct drm_file *file,
79e53945
JB		 14461 unsigned int *handle)
14462{
14463 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14464 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14465
05394f39 14466 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14467}
14468
14469static const struct drm_framebuffer_funcs intel_fb_funcs = {
14470 .destroy = intel_user_framebuffer_destroy,
14471 .create_handle = intel_user_framebuffer_create_handle,
14472};
14473
b321803d
DL		 14474static
14475u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14476 uint32_t pixel_format)
14477{
14478 u32 gen = INTEL_INFO(dev)->gen;
14479
14480 if (gen >= 9) {
14481 /* "The stride in bytes must not exceed the of the size of 8K
14482 * pixels and 32K bytes."
14483 */
14484 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14485 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14486 return 32*1024;
14487 } else if (gen >= 4) {
14488 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14489 return 16*1024;
14490 else
14491 return 32*1024;
14492 } else if (gen >= 3) {
14493 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14494 return 8*1024;
14495 else
14496 return 16*1024;
14497 } else {
14498 /* XXX DSPC is limited to 4k tiled */
14499 return 8*1024;
14500 }
14501}
14502
b5ea642a
DV		 14503static int intel_framebuffer_init(struct drm_device *dev,
14504 struct intel_framebuffer *intel_fb,
14505 struct drm_mode_fb_cmd2 *mode_cmd,
14506 struct drm_i915_gem_object *obj)
79e53945 14507{
6761dd31 14508 unsigned int aligned_height;
79e53945 14509 int ret;
b321803d 14510 u32 pitch_limit, stride_alignment;
79e53945 14511
dd4916c5
DV		 14512 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14513
2a80eada
DV		 14514 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14515 /* Enforce that fb modifier and tiling mode match, but only for
14516 * X-tiled. This is needed for FBC. */
14517 if (!!(obj->tiling_mode == I915_TILING_X) !=
14518 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14519 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14520 return -EINVAL;
14521 }
14522 } else {
14523 if (obj->tiling_mode == I915_TILING_X)
14524 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14525 else if (obj->tiling_mode == I915_TILING_Y) {
14526 DRM_DEBUG("No Y tiling for legacy addfb\n");
14527 return -EINVAL;
14528 }
14529 }
14530
9a8f0a12
TU		 14531 /* Passed in modifier sanity checking. */
14532 switch (mode_cmd->modifier[0]) {
14533 case I915_FORMAT_MOD_Y_TILED:
14534 case I915_FORMAT_MOD_Yf_TILED:
14535 if (INTEL_INFO(dev)->gen < 9) {
14536 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14537 mode_cmd->modifier[0]);
14538 return -EINVAL;
14539 }
14540 case DRM_FORMAT_MOD_NONE:
14541 case I915_FORMAT_MOD_X_TILED:
14542 break;
14543 default:
c0f40428
JB		 14544 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14545 mode_cmd->modifier[0]);
57cd6508 14546 return -EINVAL;
c16ed4be 14547 }
57cd6508 14548
b321803d
DL		 14549 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14550 mode_cmd->pixel_format);
14551 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14552 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14553 mode_cmd->pitches[0], stride_alignment);
57cd6508 14554 return -EINVAL;
c16ed4be 14555 }
57cd6508 14556
b321803d
DL		 14557 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14558 mode_cmd->pixel_format);
a35cdaa0 14559 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14560 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14561 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14562 "tiled" : "linear",
a35cdaa0 14563 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14564 return -EINVAL;
c16ed4be 14565 }
5d7bd705 14566
2a80eada 14567 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14568 mode_cmd->pitches[0] != obj->stride) {
14569 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14570 mode_cmd->pitches[0], obj->stride);
5d7bd705 14571 return -EINVAL;
c16ed4be 14572 }
5d7bd705 14573
57779d06 14574 /* Reject formats not supported by any plane early. */
308e5bcb 14575 switch (mode_cmd->pixel_format) {
57779d06 14576 case DRM_FORMAT_C8:
04b3924d
VS		 14577 case DRM_FORMAT_RGB565:
14578 case DRM_FORMAT_XRGB8888:
14579 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14580 break;
14581 case DRM_FORMAT_XRGB1555:
c16ed4be 14582 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14583 DRM_DEBUG("unsupported pixel format: %s\n",
14584 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14585 return -EINVAL;
c16ed4be 14586 }
57779d06 14587 break;
57779d06 14588 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14589 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14590 DRM_DEBUG("unsupported pixel format: %s\n",
14591 drm_get_format_name(mode_cmd->pixel_format));
14592 return -EINVAL;
14593 }
14594 break;
14595 case DRM_FORMAT_XBGR8888:
04b3924d 14596 case DRM_FORMAT_XRGB2101010:
57779d06 14597 case DRM_FORMAT_XBGR2101010:
c16ed4be 14598 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14599 DRM_DEBUG("unsupported pixel format: %s\n",
14600 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14601 return -EINVAL;
c16ed4be 14602 }
b5626747 14603 break;
7531208b
DL		 14604 case DRM_FORMAT_ABGR2101010:
14605 if (!IS_VALLEYVIEW(dev)) {
14606 DRM_DEBUG("unsupported pixel format: %s\n",
14607 drm_get_format_name(mode_cmd->pixel_format));
14608 return -EINVAL;
14609 }
14610 break;
04b3924d
VS		 14611 case DRM_FORMAT_YUYV:
14612 case DRM_FORMAT_UYVY:
14613 case DRM_FORMAT_YVYU:
14614 case DRM_FORMAT_VYUY:
c16ed4be 14615 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14616 DRM_DEBUG("unsupported pixel format: %s\n",
14617 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14618 return -EINVAL;
c16ed4be 14619 }
57cd6508
CW		 14620 break;
14621 default:
4ee62c76
VS		 14622 DRM_DEBUG("unsupported pixel format: %s\n",
14623 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14624 return -EINVAL;
14625 }
14626
90f9a336
VS		 14627 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14628 if (mode_cmd->offsets[0] != 0)
14629 return -EINVAL;
14630
ec2c981e 14631 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14632 mode_cmd->pixel_format,
14633 mode_cmd->modifier[0]);
53155c0a
DV		 14634 /* FIXME drm helper for size checks (especially planar formats)? */
14635 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14636 return -EINVAL;
14637
c7d73f6a
DV		 14638 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14639 intel_fb->obj = obj;
80075d49 14640 intel_fb->obj->framebuffer_references++;
c7d73f6a 14641
79e53945
JB		 14642 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14643 if (ret) {
14644 DRM_ERROR("framebuffer init failed %d\n", ret);
14645 return ret;
14646 }
14647
79e53945
JB		 14648 return 0;
14649}
14650
79e53945
JB		 14651static struct drm_framebuffer *
14652intel_user_framebuffer_create(struct drm_device *dev,
14653 struct drm_file *filp,
308e5bcb 14654 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14655{
05394f39 14656 struct drm_i915_gem_object *obj;
79e53945 14657
308e5bcb
JB		 14658 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14659 mode_cmd->handles[0]));
c8725226 14660 if (&obj->base == NULL)
cce13ff7 14661 return ERR_PTR(-ENOENT);
79e53945 14662
d2dff872 14663 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14664}
14665
4520f53a 14666#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14667static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14668{
14669}
14670#endif
14671
79e53945 14672static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14673 .fb_create = intel_user_framebuffer_create,
0632fef6 14674 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14675 .atomic_check = intel_atomic_check,
14676 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14677};
14678
e70236a8
JB		 14679/* Set up chip specific display functions */
14680static void intel_init_display(struct drm_device *dev)
14681{
14682 struct drm_i915_private *dev_priv = dev->dev_private;
14683
ee9300bb
DV		 14684 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14685 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14686 else if (IS_CHERRYVIEW(dev))
14687 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14688 else if (IS_VALLEYVIEW(dev))
14689 dev_priv->display.find_dpll = vlv_find_best_dpll;
14690 else if (IS_PINEVIEW(dev))
14691 dev_priv->display.find_dpll = pnv_find_best_dpll;
14692 else
14693 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14694
bc8d7dff
DL		 14695 if (INTEL_INFO(dev)->gen >= 9) {
14696 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14697 dev_priv->display.get_initial_plane_config =
14698 skylake_get_initial_plane_config;
bc8d7dff
DL		 14699 dev_priv->display.crtc_compute_clock =
14700 haswell_crtc_compute_clock;
14701 dev_priv->display.crtc_enable = haswell_crtc_enable;
14702 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14703 dev_priv->display.update_primary_plane =
14704 skylake_update_primary_plane;
14705 } else if (HAS_DDI(dev)) {
0e8ffe1b 14706 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14707 dev_priv->display.get_initial_plane_config =
14708 ironlake_get_initial_plane_config;
797d0259
ACO		 14709 dev_priv->display.crtc_compute_clock =
14710 haswell_crtc_compute_clock;
4f771f10
PZ		 14711 dev_priv->display.crtc_enable = haswell_crtc_enable;
14712 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14713 dev_priv->display.update_primary_plane =
14714 ironlake_update_primary_plane;
09b4ddf9 14715 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14716 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14717 dev_priv->display.get_initial_plane_config =
14718 ironlake_get_initial_plane_config;
3fb37703
ACO		 14719 dev_priv->display.crtc_compute_clock =
14720 ironlake_crtc_compute_clock;
76e5a89c
DV		 14721 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14722 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14723 dev_priv->display.update_primary_plane =
14724 ironlake_update_primary_plane;
89b667f8
JB		 14725 } else if (IS_VALLEYVIEW(dev)) {
14726 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14727 dev_priv->display.get_initial_plane_config =
14728 i9xx_get_initial_plane_config;
d6dfee7a 14729 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14730 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14731 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14732 dev_priv->display.update_primary_plane =
14733 i9xx_update_primary_plane;
f564048e 14734 } else {
0e8ffe1b 14735 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14736 dev_priv->display.get_initial_plane_config =
14737 i9xx_get_initial_plane_config;
d6dfee7a 14738 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14739 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14740 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14741 dev_priv->display.update_primary_plane =
14742 i9xx_update_primary_plane;
f564048e 14743 }
e70236a8 14744
e70236a8 14745 /* Returns the core display clock speed */
1652d19e
VS		 14746 if (IS_SKYLAKE(dev))
14747 dev_priv->display.get_display_clock_speed =
14748 skylake_get_display_clock_speed;
14749 else if (IS_BROADWELL(dev))
14750 dev_priv->display.get_display_clock_speed =
14751 broadwell_get_display_clock_speed;
14752 else if (IS_HASWELL(dev))
14753 dev_priv->display.get_display_clock_speed =
14754 haswell_get_display_clock_speed;
14755 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14756 dev_priv->display.get_display_clock_speed =
14757 valleyview_get_display_clock_speed;
b37a6434
VS		 14758 else if (IS_GEN5(dev))
14759 dev_priv->display.get_display_clock_speed =
14760 ilk_get_display_clock_speed;
a7c66cd8 14761 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14762 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14763 dev_priv->display.get_display_clock_speed =
14764 i945_get_display_clock_speed;
34edce2f
VS		 14765 else if (IS_GM45(dev))
14766 dev_priv->display.get_display_clock_speed =
14767 gm45_get_display_clock_speed;
14768 else if (IS_CRESTLINE(dev))
14769 dev_priv->display.get_display_clock_speed =
14770 i965gm_get_display_clock_speed;
14771 else if (IS_PINEVIEW(dev))
14772 dev_priv->display.get_display_clock_speed =
14773 pnv_get_display_clock_speed;
14774 else if (IS_G33(dev) || IS_G4X(dev))
14775 dev_priv->display.get_display_clock_speed =
14776 g33_get_display_clock_speed;
e70236a8
JB		 14777 else if (IS_I915G(dev))
14778 dev_priv->display.get_display_clock_speed =
14779 i915_get_display_clock_speed;
257a7ffc 14780 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14781 dev_priv->display.get_display_clock_speed =
14782 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14783 else if (IS_PINEVIEW(dev))
14784 dev_priv->display.get_display_clock_speed =
14785 pnv_get_display_clock_speed;
e70236a8
JB		 14786 else if (IS_I915GM(dev))
14787 dev_priv->display.get_display_clock_speed =
14788 i915gm_get_display_clock_speed;
14789 else if (IS_I865G(dev))
14790 dev_priv->display.get_display_clock_speed =
14791 i865_get_display_clock_speed;
f0f8a9ce 14792 else if (IS_I85X(dev))
e70236a8 14793 dev_priv->display.get_display_clock_speed =
1b1d2716 14794 i85x_get_display_clock_speed;
623e01e5
VS		 14795 else { /* 830 */
14796 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14797 dev_priv->display.get_display_clock_speed =
14798 i830_get_display_clock_speed;
623e01e5 14799 }
e70236a8 14800
7c10a2b5 14801 if (IS_GEN5(dev)) {
3bb11b53 14802 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14803 } else if (IS_GEN6(dev)) {
14804 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14805 } else if (IS_IVYBRIDGE(dev)) {
14806 /* FIXME: detect B0+ stepping and use auto training */
14807 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14808 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14809 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
b432e5cf
VS		 14810 if (IS_BROADWELL(dev))
14811 dev_priv->display.modeset_global_resources =
14812 broadwell_modeset_global_resources;
30a970c6
JB		 14813 } else if (IS_VALLEYVIEW(dev)) {
14814 dev_priv->display.modeset_global_resources =
14815 valleyview_modeset_global_resources;
f8437dd1
VK		 14816 } else if (IS_BROXTON(dev)) {
14817 dev_priv->display.modeset_global_resources =
14818 broxton_modeset_global_resources;
e70236a8 14819 }
8c9f3aaf 14820
8c9f3aaf
JB		 14821 switch (INTEL_INFO(dev)->gen) {
14822 case 2:
14823 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14824 break;
14825
14826 case 3:
14827 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14828 break;
14829
14830 case 4:
14831 case 5:
14832 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14833 break;
14834
14835 case 6:
14836 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14837 break;
7c9017e5 14838 case 7:
4e0bbc31 14839 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14840 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14841 break;
830c81db 14842 case 9:
ba343e02
TU		 14843 /* Drop through - unsupported since execlist only. */
14844 default:
14845 /* Default just returns -ENODEV to indicate unsupported */
14846 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14847 }
7bd688cd
JN		 14848
14849 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14850
14851 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14852}
14853
b690e96c
JB		 14854/*
14855 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14856 * resume, or other times. This quirk makes sure that's the case for
14857 * affected systems.
14858 */
0206e353 14859static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14860{
14861 struct drm_i915_private *dev_priv = dev->dev_private;
14862
14863 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14864 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14865}
14866
b6b5d049
VS		 14867static void quirk_pipeb_force(struct drm_device *dev)
14868{
14869 struct drm_i915_private *dev_priv = dev->dev_private;
14870
14871 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14872 DRM_INFO("applying pipe b force quirk\n");
14873}
14874
435793df
KP		 14875/*
14876 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14877 */
14878static void quirk_ssc_force_disable(struct drm_device *dev)
14879{
14880 struct drm_i915_private *dev_priv = dev->dev_private;
14881 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14882 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14883}
14884
4dca20ef 14885/*
5a15ab5b
CE		 14886 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14887 * brightness value
4dca20ef
CE		 14888 */
14889static void quirk_invert_brightness(struct drm_device *dev)
14890{
14891 struct drm_i915_private *dev_priv = dev->dev_private;
14892 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14893 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14894}
14895
9c72cc6f
SD		 14896/* Some VBT's incorrectly indicate no backlight is present */
14897static void quirk_backlight_present(struct drm_device *dev)
14898{
14899 struct drm_i915_private *dev_priv = dev->dev_private;
14900 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14901 DRM_INFO("applying backlight present quirk\n");
14902}
14903
b690e96c
JB		 14904struct intel_quirk {
14905 int device;
14906 int subsystem_vendor;
14907 int subsystem_device;
14908 void (*hook)(struct drm_device *dev);
14909};
14910
5f85f176
EE		 14911/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14912struct intel_dmi_quirk {
14913 void (*hook)(struct drm_device *dev);
14914 const struct dmi_system_id (*dmi_id_list)[];
14915};
14916
14917static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14918{
14919 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14920 return 1;
14921}
14922
14923static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14924 {
14925 .dmi_id_list = &(const struct dmi_system_id[]) {
14926 {
14927 .callback = intel_dmi_reverse_brightness,
14928 .ident = "NCR Corporation",
14929 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14930 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14931 },
14932 },
14933 { } /* terminating entry */
14934 },
14935 .hook = quirk_invert_brightness,
14936 },
14937};
14938
c43b5634 14939static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14940 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14941 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14942
b690e96c
JB		 14943 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14944 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14945
5f080c0f
VS		 14946 /* 830 needs to leave pipe A & dpll A up */
14947 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14948
b6b5d049
VS		 14949 /* 830 needs to leave pipe B & dpll B up */
14950 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14951
435793df
KP		 14952 /* Lenovo U160 cannot use SSC on LVDS */
14953 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14954
14955 /* Sony Vaio Y cannot use SSC on LVDS */
14956 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14957
be505f64
AH		 14958 /* Acer Aspire 5734Z must invert backlight brightness */
14959 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14960
14961 /* Acer/eMachines G725 */
14962 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14963
14964 /* Acer/eMachines e725 */
14965 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14966
14967 /* Acer/Packard Bell NCL20 */
14968 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14969
14970 /* Acer Aspire 4736Z */
14971 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14972
14973 /* Acer Aspire 5336 */
14974 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14975
14976 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14977 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14978
dfb3d47b
SD		 14979 /* Acer C720 Chromebook (Core i3 4005U) */
14980 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14981
b2a9601c 14982 /* Apple Macbook 2,1 (Core 2 T7400) */
14983 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14984
d4967d8c
SD		 14985 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14986 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14987
14988 /* HP Chromebook 14 (Celeron 2955U) */
14989 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14990
14991 /* Dell Chromebook 11 */
14992 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14993};
14994
14995static void intel_init_quirks(struct drm_device *dev)
14996{
14997 struct pci_dev *d = dev->pdev;
14998 int i;
14999
15000 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15001 struct intel_quirk *q = &intel_quirks[i];
15002
15003 if (d->device == q->device &&
15004 (d->subsystem_vendor == q->subsystem_vendor ||
15005 q->subsystem_vendor == PCI_ANY_ID) &&
15006 (d->subsystem_device == q->subsystem_device ||
15007 q->subsystem_device == PCI_ANY_ID))
15008 q->hook(dev);
15009 }
5f85f176
EE		 15010 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15011 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15012 intel_dmi_quirks[i].hook(dev);
15013 }
b690e96c
JB		 15014}
15015
9cce37f4
JB		 15016/* Disable the VGA plane that we never use */
15017static void i915_disable_vga(struct drm_device *dev)
15018{
15019 struct drm_i915_private *dev_priv = dev->dev_private;
15020 u8 sr1;
766aa1c4 15021 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 15022
2b37c616 15023 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 15024 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 15025 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 15026 sr1 = inb(VGA_SR_DATA);
15027 outb(sr1 | 1<<5, VGA_SR_DATA);
15028 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15029 udelay(300);
15030
01f5a626 15031 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 15032 POSTING_READ(vga_reg);
15033}
15034
f817586c
DV		 15035void intel_modeset_init_hw(struct drm_device *dev)
15036{
b6283055 15037 intel_update_cdclk(dev);
a8f78b58 15038 intel_prepare_ddi(dev);
f817586c 15039 intel_init_clock_gating(dev);
8090c6b9 15040 intel_enable_gt_powersave(dev);
f817586c
DV		 15041}
15042
79e53945
JB		 15043void intel_modeset_init(struct drm_device *dev)
15044{
652c393a 15045 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 15046 int sprite, ret;
8cc87b75 15047 enum pipe pipe;
46f297fb 15048 struct intel_crtc *crtc;
79e53945
JB		 15049
15050 drm_mode_config_init(dev);
15051
15052 dev->mode_config.min_width = 0;
15053 dev->mode_config.min_height = 0;
15054
019d96cb
DA		 15055 dev->mode_config.preferred_depth = 24;
15056 dev->mode_config.prefer_shadow = 1;
15057
25bab385
TU		 15058 dev->mode_config.allow_fb_modifiers = true;
15059
e6ecefaa 15060 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15061
b690e96c
JB		 15062 intel_init_quirks(dev);
15063
1fa61106
ED		 15064 intel_init_pm(dev);
15065
e3c74757
BW		 15066 if (INTEL_INFO(dev)->num_pipes == 0)
15067 return;
15068
e70236a8 15069 intel_init_display(dev);
7c10a2b5 15070 intel_init_audio(dev);
e70236a8 15071
a6c45cf0
CW		 15072 if (IS_GEN2(dev)) {
15073 dev->mode_config.max_width = 2048;
15074 dev->mode_config.max_height = 2048;
15075 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15076 dev->mode_config.max_width = 4096;
15077 dev->mode_config.max_height = 4096;
79e53945 15078 } else {
a6c45cf0
CW		 15079 dev->mode_config.max_width = 8192;
15080 dev->mode_config.max_height = 8192;
79e53945 15081 }
068be561 15082
dc41c154
VS		 15083 if (IS_845G(dev) || IS_I865G(dev)) {
15084 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15085 dev->mode_config.cursor_height = 1023;
15086 } else if (IS_GEN2(dev)) {
068be561
DL		 15087 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15088 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15089 } else {
15090 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15091 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15092 }
15093
5d4545ae 15094 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15095
28c97730 15096 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15097 INTEL_INFO(dev)->num_pipes,
15098 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15099
055e393f 15100 for_each_pipe(dev_priv, pipe) {
8cc87b75 15101 intel_crtc_init(dev, pipe);
3bdcfc0c 15102 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15103 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15104 if (ret)
06da8da2 15105 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15106 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15107 }
79e53945
JB		 15108 }
15109
f42bb70d
JB		 15110 intel_init_dpio(dev);
15111
e72f9fbf 15112 intel_shared_dpll_init(dev);
ee7b9f93 15113
9cce37f4
JB		 15114 /* Just disable it once at startup */
15115 i915_disable_vga(dev);
79e53945 15116 intel_setup_outputs(dev);
11be49eb
CW		 15117
15118 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15119 intel_fbc_disable(dev);
fa9fa083 15120
6e9f798d 15121 drm_modeset_lock_all(dev);
fa9fa083 15122 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15123 drm_modeset_unlock_all(dev);
46f297fb 15124
d3fcc808 15125 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15126 if (!crtc->active)
15127 continue;
15128
46f297fb 15129 /*
46f297fb
JB		 15130 * Note that reserving the BIOS fb up front prevents us
15131 * from stuffing other stolen allocations like the ring
15132 * on top. This prevents some ugliness at boot time, and
15133 * can even allow for smooth boot transitions if the BIOS
15134 * fb is large enough for the active pipe configuration.
15135 */
5724dbd1
DL		 15136 if (dev_priv->display.get_initial_plane_config) {
15137 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15138 &crtc->plane_config);
15139 /*
15140 * If the fb is shared between multiple heads, we'll
15141 * just get the first one.
15142 */
f6936e29 15143 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15144 }
46f297fb 15145 }
2c7111db
CW		 15146}
15147
7fad798e
DV		 15148static void intel_enable_pipe_a(struct drm_device *dev)
15149{
15150 struct intel_connector *connector;
15151 struct drm_connector *crt = NULL;
15152 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15153 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15154
15155 /* We can't just switch on the pipe A, we need to set things up with a
15156 * proper mode and output configuration. As a gross hack, enable pipe A
15157 * by enabling the load detect pipe once. */
3a3371ff 15158 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15159 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15160 crt = &connector->base;
15161 break;
15162 }
15163 }
15164
15165 if (!crt)
15166 return;
15167
208bf9fd 15168 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15169 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15170}
15171
fa555837
DV		 15172static bool
15173intel_check_plane_mapping(struct intel_crtc *crtc)
15174{
7eb552ae
BW		 15175 struct drm_device *dev = crtc->base.dev;
15176 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15177 u32 reg, val;
15178
7eb552ae 15179 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15180 return true;
15181
15182 reg = DSPCNTR(!crtc->plane);
15183 val = I915_READ(reg);
15184
15185 if ((val & DISPLAY_PLANE_ENABLE) &&
15186 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15187 return false;
15188
15189 return true;
15190}
15191
24929352
DV		 15192static void intel_sanitize_crtc(struct intel_crtc *crtc)
15193{
15194 struct drm_device *dev = crtc->base.dev;
15195 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 15196 u32 reg;
24929352 15197
24929352 15198 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15199 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15200 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15201
d3eaf884 15202 /* restore vblank interrupts to correct state */
9625604c 15203 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15204 if (crtc->active) {
15205 update_scanline_offset(crtc);
9625604c
DV		 15206 drm_crtc_vblank_on(&crtc->base);
15207 }
d3eaf884 15208
24929352 15209 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15210 * disable the crtc (and hence change the state) if it is wrong. Note
15211 * that gen4+ has a fixed plane -> pipe mapping. */
15212 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15213 struct intel_connector *connector;
15214 bool plane;
15215
24929352
DV		 15216 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15217 crtc->base.base.id);
15218
15219 /* Pipe has the wrong plane attached and the plane is active.
15220 * Temporarily change the plane mapping and disable everything
15221 * ... */
15222 plane = crtc->plane;
b70709a6 15223 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15224 crtc->plane = !plane;
ce22dba9 15225 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 15226 dev_priv->display.crtc_disable(&crtc->base);
15227 crtc->plane = plane;
15228
15229 /* ... and break all links. */
3a3371ff 15230 for_each_intel_connector(dev, connector) {
24929352
DV		 15231 if (connector->encoder->base.crtc != &crtc->base)
15232 continue;
15233
7f1950fb
EE		 15234 connector->base.dpms = DRM_MODE_DPMS_OFF;
15235 connector->base.encoder = NULL;
24929352 15236 }
7f1950fb
EE		 15237 /* multiple connectors may have the same encoder:
15238 * handle them and break crtc link separately */
3a3371ff 15239 for_each_intel_connector(dev, connector)
7f1950fb
EE		 15240 if (connector->encoder->base.crtc == &crtc->base) {
15241 connector->encoder->base.crtc = NULL;
15242 connector->encoder->connectors_active = false;
15243 }
24929352
DV		 15244
15245 WARN_ON(crtc->active);
83d65738 15246 crtc->base.state->enable = false;
49d6fa21 15247 crtc->base.state->active = false;
24929352
DV		 15248 crtc->base.enabled = false;
15249 }
24929352 15250
7fad798e
DV		 15251 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15252 crtc->pipe == PIPE_A && !crtc->active) {
15253 /* BIOS forgot to enable pipe A, this mostly happens after
15254 * resume. Force-enable the pipe to fix this, the update_dpms
15255 * call below we restore the pipe to the right state, but leave
15256 * the required bits on. */
15257 intel_enable_pipe_a(dev);
15258 }
15259
24929352
DV		 15260 /* Adjust the state of the output pipe according to whether we
15261 * have active connectors/encoders. */
15262 intel_crtc_update_dpms(&crtc->base);
15263
83d65738 15264 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 15265 struct intel_encoder *encoder;
15266
15267 /* This can happen either due to bugs in the get_hw_state
15268 * functions or because the pipe is force-enabled due to the
15269 * pipe A quirk. */
15270 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15271 crtc->base.base.id,
83d65738 15272 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15273 crtc->active ? "enabled" : "disabled");
15274
83d65738 15275 crtc->base.state->enable = crtc->active;
49d6fa21 15276 crtc->base.state->active = crtc->active;
24929352
DV		 15277 crtc->base.enabled = crtc->active;
15278
15279 /* Because we only establish the connector -> encoder ->
15280 * crtc links if something is active, this means the
15281 * crtc is now deactivated. Break the links. connector
15282 * -> encoder links are only establish when things are
15283 * actually up, hence no need to break them. */
15284 WARN_ON(crtc->active);
15285
15286 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15287 WARN_ON(encoder->connectors_active);
15288 encoder->base.crtc = NULL;
15289 }
15290 }
c5ab3bc0 15291
a3ed6aad 15292 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15293 /*
15294 * We start out with underrun reporting disabled to avoid races.
15295 * For correct bookkeeping mark this on active crtcs.
15296 *
c5ab3bc0
DV		 15297 * Also on gmch platforms we dont have any hardware bits to
15298 * disable the underrun reporting. Which means we need to start
15299 * out with underrun reporting disabled also on inactive pipes,
15300 * since otherwise we'll complain about the garbage we read when
15301 * e.g. coming up after runtime pm.
15302 *
4cc31489
DV		 15303 * No protection against concurrent access is required - at
15304 * worst a fifo underrun happens which also sets this to false.
15305 */
15306 crtc->cpu_fifo_underrun_disabled = true;
15307 crtc->pch_fifo_underrun_disabled = true;
15308 }
24929352
DV		 15309}
15310
15311static void intel_sanitize_encoder(struct intel_encoder *encoder)
15312{
15313 struct intel_connector *connector;
15314 struct drm_device *dev = encoder->base.dev;
15315
15316 /* We need to check both for a crtc link (meaning that the
15317 * encoder is active and trying to read from a pipe) and the
15318 * pipe itself being active. */
15319 bool has_active_crtc = encoder->base.crtc &&
15320 to_intel_crtc(encoder->base.crtc)->active;
15321
15322 if (encoder->connectors_active && !has_active_crtc) {
15323 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15324 encoder->base.base.id,
8e329a03 15325 encoder->base.name);
24929352
DV		 15326
15327 /* Connector is active, but has no active pipe. This is
15328 * fallout from our resume register restoring. Disable
15329 * the encoder manually again. */
15330 if (encoder->base.crtc) {
15331 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15332 encoder->base.base.id,
8e329a03 15333 encoder->base.name);
24929352 15334 encoder->disable(encoder);
a62d1497
VS		 15335 if (encoder->post_disable)
15336 encoder->post_disable(encoder);
24929352 15337 }
7f1950fb
EE		 15338 encoder->base.crtc = NULL;
15339 encoder->connectors_active = false;
24929352
DV		 15340
15341 /* Inconsistent output/port/pipe state happens presumably due to
15342 * a bug in one of the get_hw_state functions. Or someplace else
15343 * in our code, like the register restore mess on resume. Clamp
15344 * things to off as a safer default. */
3a3371ff 15345 for_each_intel_connector(dev, connector) {
24929352
DV		 15346 if (connector->encoder != encoder)
15347 continue;
7f1950fb
EE		 15348 connector->base.dpms = DRM_MODE_DPMS_OFF;
15349 connector->base.encoder = NULL;
24929352
DV		 15350 }
15351 }
15352 /* Enabled encoders without active connectors will be fixed in
15353 * the crtc fixup. */
15354}
15355
04098753 15356void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15357{
15358 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15359 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15360
04098753
ID		 15361 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15362 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15363 i915_disable_vga(dev);
15364 }
15365}
15366
15367void i915_redisable_vga(struct drm_device *dev)
15368{
15369 struct drm_i915_private *dev_priv = dev->dev_private;
15370
8dc8a27c
PZ		 15371 /* This function can be called both from intel_modeset_setup_hw_state or
15372 * at a very early point in our resume sequence, where the power well
15373 * structures are not yet restored. Since this function is at a very
15374 * paranoid "someone might have enabled VGA while we were not looking"
15375 * level, just check if the power well is enabled instead of trying to
15376 * follow the "don't touch the power well if we don't need it" policy
15377 * the rest of the driver uses. */
f458ebbc 15378 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15379 return;
15380
04098753 15381 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15382}
15383
98ec7739
VS		 15384static bool primary_get_hw_state(struct intel_crtc *crtc)
15385{
15386 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15387
15388 if (!crtc->active)
15389 return false;
15390
15391 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15392}
15393
30e984df 15394static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15395{
15396 struct drm_i915_private *dev_priv = dev->dev_private;
15397 enum pipe pipe;
24929352
DV		 15398 struct intel_crtc *crtc;
15399 struct intel_encoder *encoder;
15400 struct intel_connector *connector;
5358901f 15401 int i;
24929352 15402
d3fcc808 15403 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15404 struct drm_plane *primary = crtc->base.primary;
15405 struct intel_plane_state *plane_state;
15406
6e3c9717 15407 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15408
6e3c9717 15409 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15410
0e8ffe1b 15411 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15412 crtc->config);
24929352 15413
83d65738 15414 crtc->base.state->enable = crtc->active;
49d6fa21 15415 crtc->base.state->active = crtc->active;
24929352 15416 crtc->base.enabled = crtc->active;
b70709a6
ML		 15417
15418 plane_state = to_intel_plane_state(primary->state);
15419 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15420
15421 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15422 crtc->base.base.id,
15423 crtc->active ? "enabled" : "disabled");
15424 }
15425
5358901f
DV		 15426 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15427 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15428
3e369b76
ACO		 15429 pll->on = pll->get_hw_state(dev_priv, pll,
15430 &pll->config.hw_state);
5358901f 15431 pll->active = 0;
3e369b76 15432 pll->config.crtc_mask = 0;
d3fcc808 15433 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15434 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15435 pll->active++;
3e369b76 15436 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15437 }
5358901f 15438 }
5358901f 15439
1e6f2ddc 15440 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15441 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15442
3e369b76 15443 if (pll->config.crtc_mask)
bd2bb1b9 15444 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15445 }
15446
b2784e15 15447 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15448 pipe = 0;
15449
15450 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15451 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15452 encoder->base.crtc = &crtc->base;
6e3c9717 15453 encoder->get_config(encoder, crtc->config);
24929352
DV		 15454 } else {
15455 encoder->base.crtc = NULL;
15456 }
15457
15458 encoder->connectors_active = false;
6f2bcceb 15459 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15460 encoder->base.base.id,
8e329a03 15461 encoder->base.name,
24929352 15462 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15463 pipe_name(pipe));
24929352
DV		 15464 }
15465
3a3371ff 15466 for_each_intel_connector(dev, connector) {
24929352
DV		 15467 if (connector->get_hw_state(connector)) {
15468 connector->base.dpms = DRM_MODE_DPMS_ON;
15469 connector->encoder->connectors_active = true;
15470 connector->base.encoder = &connector->encoder->base;
15471 } else {
15472 connector->base.dpms = DRM_MODE_DPMS_OFF;
15473 connector->base.encoder = NULL;
15474 }
15475 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15476 connector->base.base.id,
c23cc417 15477 connector->base.name,
24929352
DV		 15478 connector->base.encoder ? "enabled" : "disabled");
15479 }
30e984df
DV		 15480}
15481
15482/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15483 * and i915 state tracking structures. */
15484void intel_modeset_setup_hw_state(struct drm_device *dev,
15485 bool force_restore)
15486{
15487 struct drm_i915_private *dev_priv = dev->dev_private;
15488 enum pipe pipe;
30e984df
DV		 15489 struct intel_crtc *crtc;
15490 struct intel_encoder *encoder;
35c95375 15491 int i;
30e984df
DV		 15492
15493 intel_modeset_readout_hw_state(dev);
24929352 15494
babea61d
JB		 15495 /*
15496 * Now that we have the config, copy it to each CRTC struct
15497 * Note that this could go away if we move to using crtc_config
15498 * checking everywhere.
15499 */
d3fcc808 15500 for_each_intel_crtc(dev, crtc) {
d330a953 15501 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15502 intel_mode_from_pipe_config(&crtc->base.mode,
15503 crtc->config);
babea61d
JB		 15504 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15505 crtc->base.base.id);
15506 drm_mode_debug_printmodeline(&crtc->base.mode);
15507 }
15508 }
15509
24929352 15510 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15511 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15512 intel_sanitize_encoder(encoder);
15513 }
15514
055e393f 15515 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15516 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15517 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15518 intel_dump_pipe_config(crtc, crtc->config,
15519 "[setup_hw_state]");
24929352 15520 }
9a935856 15521
d29b2f9d
ACO		 15522 intel_modeset_update_connector_atomic_state(dev);
15523
35c95375
DV		 15524 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15525 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15526
15527 if (!pll->on || pll->active)
15528 continue;
15529
15530 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15531
15532 pll->disable(dev_priv, pll);
15533 pll->on = false;
15534 }
15535
3078999f
PB		 15536 if (IS_GEN9(dev))
15537 skl_wm_get_hw_state(dev);
15538 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15539 ilk_wm_get_hw_state(dev);
15540
45e2b5f6 15541 if (force_restore) {
7d0bc1ea
VS		 15542 i915_redisable_vga(dev);
15543
f30da187
DV		 15544 /*
15545 * We need to use raw interfaces for restoring state to avoid
15546 * checking (bogus) intermediate states.
15547 */
055e393f 15548 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15549 struct drm_crtc *crtc =
15550 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15551
83a57153 15552 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15553 }
15554 } else {
15555 intel_modeset_update_staged_output_state(dev);
15556 }
8af6cf88
DV		 15557
15558 intel_modeset_check_state(dev);
2c7111db
CW		 15559}
15560
15561void intel_modeset_gem_init(struct drm_device *dev)
15562{
92122789 15563 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15564 struct drm_crtc *c;
2ff8fde1 15565 struct drm_i915_gem_object *obj;
e0d6149b 15566 int ret;
484b41dd 15567
ae48434c
ID		 15568 mutex_lock(&dev->struct_mutex);
15569 intel_init_gt_powersave(dev);
15570 mutex_unlock(&dev->struct_mutex);
15571
92122789
JB		 15572 /*
15573 * There may be no VBT; and if the BIOS enabled SSC we can
15574 * just keep using it to avoid unnecessary flicker. Whereas if the
15575 * BIOS isn't using it, don't assume it will work even if the VBT
15576 * indicates as much.
15577 */
15578 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15579 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15580 DREF_SSC1_ENABLE);
15581
1833b134 15582 intel_modeset_init_hw(dev);
02e792fb
DV		 15583
15584 intel_setup_overlay(dev);
484b41dd
JB		 15585
15586 /*
15587 * Make sure any fbs we allocated at startup are properly
15588 * pinned & fenced. When we do the allocation it's too early
15589 * for this.
15590 */
70e1e0ec 15591 for_each_crtc(dev, c) {
2ff8fde1
MR		 15592 obj = intel_fb_obj(c->primary->fb);
15593 if (obj == NULL)
484b41dd
JB		 15594 continue;
15595
e0d6149b
TU		 15596 mutex_lock(&dev->struct_mutex);
15597 ret = intel_pin_and_fence_fb_obj(c->primary,
15598 c->primary->fb,
15599 c->primary->state,
15600 NULL);
15601 mutex_unlock(&dev->struct_mutex);
15602 if (ret) {
484b41dd
JB		 15603 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15604 to_intel_crtc(c)->pipe);
66e514c1
DA		 15605 drm_framebuffer_unreference(c->primary->fb);
15606 c->primary->fb = NULL;
afd65eb4 15607 update_state_fb(c->primary);
484b41dd
JB		 15608 }
15609 }
0962c3c9
VS		 15610
15611 intel_backlight_register(dev);
79e53945
JB		 15612}
15613
4932e2c3
ID		 15614void intel_connector_unregister(struct intel_connector *intel_connector)
15615{
15616 struct drm_connector *connector = &intel_connector->base;
15617
15618 intel_panel_destroy_backlight(connector);
34ea3d38 15619 drm_connector_unregister(connector);
4932e2c3
ID		 15620}
15621
79e53945
JB		 15622void intel_modeset_cleanup(struct drm_device *dev)
15623{
652c393a 15624 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15625 struct drm_connector *connector;
652c393a 15626
2eb5252e
ID		 15627 intel_disable_gt_powersave(dev);
15628
0962c3c9
VS		 15629 intel_backlight_unregister(dev);
15630
fd0c0642
DV		 15631 /*
15632 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15633 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15634 * experience fancy races otherwise.
15635 */
2aeb7d3a 15636 intel_irq_uninstall(dev_priv);
eb21b92b 15637
fd0c0642
DV		 15638 /*
15639 * Due to the hpd irq storm handling the hotplug work can re-arm the
15640 * poll handlers. Hence disable polling after hpd handling is shut down.
15641 */
f87ea761 15642 drm_kms_helper_poll_fini(dev);
fd0c0642 15643
652c393a
JB		 15644 mutex_lock(&dev->struct_mutex);
15645
723bfd70
JB		 15646 intel_unregister_dsm_handler();
15647
7ff0ebcc 15648 intel_fbc_disable(dev);
e70236a8 15649
69341a5e
KH		 15650 mutex_unlock(&dev->struct_mutex);
15651
1630fe75
CW		 15652 /* flush any delayed tasks or pending work */
15653 flush_scheduled_work();
15654
db31af1d
JN		 15655 /* destroy the backlight and sysfs files before encoders/connectors */
15656 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15657 struct intel_connector *intel_connector;
15658
15659 intel_connector = to_intel_connector(connector);
15660 intel_connector->unregister(intel_connector);
db31af1d 15661 }
d9255d57 15662
79e53945 15663 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15664
15665 intel_cleanup_overlay(dev);
ae48434c
ID		 15666
15667 mutex_lock(&dev->struct_mutex);
15668 intel_cleanup_gt_powersave(dev);
15669 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15670}
15671
f1c79df3
ZW		 15672/*
15673 * Return which encoder is currently attached for connector.
15674 */
df0e9248 15675struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15676{
df0e9248
CW		 15677 return &intel_attached_encoder(connector)->base;
15678}
f1c79df3 15679
df0e9248
CW		 15680void intel_connector_attach_encoder(struct intel_connector *connector,
15681 struct intel_encoder *encoder)
15682{
15683 connector->encoder = encoder;
15684 drm_mode_connector_attach_encoder(&connector->base,
15685 &encoder->base);
79e53945 15686}
28d52043
DA		 15687
15688/*
15689 * set vga decode state - true == enable VGA decode
15690 */
15691int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15692{
15693 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15694 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15695 u16 gmch_ctrl;
15696
75fa041d
CW		 15697 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15698 DRM_ERROR("failed to read control word\n");
15699 return -EIO;
15700 }
15701
c0cc8a55
CW		 15702 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15703 return 0;
15704
28d52043
DA		 15705 if (state)
15706 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15707 else
15708 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15709
15710 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15711 DRM_ERROR("failed to write control word\n");
15712 return -EIO;
15713 }
15714
28d52043
DA		 15715 return 0;
15716}
c4a1d9e4 15717
c4a1d9e4 15718struct intel_display_error_state {
ff57f1b0
PZ		 15719
15720 u32 power_well_driver;
15721
63b66e5b
CW		 15722 int num_transcoders;
15723
c4a1d9e4
CW		 15724 struct intel_cursor_error_state {
15725 u32 control;
15726 u32 position;
15727 u32 base;
15728 u32 size;
52331309 15729 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15730
15731 struct intel_pipe_error_state {
ddf9c536 15732 bool power_domain_on;
c4a1d9e4 15733 u32 source;
f301b1e1 15734 u32 stat;
52331309 15735 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15736
15737 struct intel_plane_error_state {
15738 u32 control;
15739 u32 stride;
15740 u32 size;
15741 u32 pos;
15742 u32 addr;
15743 u32 surface;
15744 u32 tile_offset;
52331309 15745 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15746
15747 struct intel_transcoder_error_state {
ddf9c536 15748 bool power_domain_on;
63b66e5b
CW		 15749 enum transcoder cpu_transcoder;
15750
15751 u32 conf;
15752
15753 u32 htotal;
15754 u32 hblank;
15755 u32 hsync;
15756 u32 vtotal;
15757 u32 vblank;
15758 u32 vsync;
15759 } transcoder[4];
c4a1d9e4
CW		 15760};
15761
15762struct intel_display_error_state *
15763intel_display_capture_error_state(struct drm_device *dev)
15764{
fbee40df 15765 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15766 struct intel_display_error_state *error;
63b66e5b
CW		 15767 int transcoders[] = {
15768 TRANSCODER_A,
15769 TRANSCODER_B,
15770 TRANSCODER_C,
15771 TRANSCODER_EDP,
15772 };
c4a1d9e4
CW		 15773 int i;
15774
63b66e5b
CW		 15775 if (INTEL_INFO(dev)->num_pipes == 0)
15776 return NULL;
15777
9d1cb914 15778 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15779 if (error == NULL)
15780 return NULL;
15781
190be112 15782 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15783 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15784
055e393f 15785 for_each_pipe(dev_priv, i) {
ddf9c536 15786 error->pipe[i].power_domain_on =
f458ebbc
DV		 15787 __intel_display_power_is_enabled(dev_priv,
15788 POWER_DOMAIN_PIPE(i));
ddf9c536 15789 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15790 continue;
15791
5efb3e28
VS		 15792 error->cursor[i].control = I915_READ(CURCNTR(i));
15793 error->cursor[i].position = I915_READ(CURPOS(i));
15794 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15795
15796 error->plane[i].control = I915_READ(DSPCNTR(i));
15797 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15798 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15799 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15800 error->plane[i].pos = I915_READ(DSPPOS(i));
15801 }
ca291363
PZ		 15802 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15803 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15804 if (INTEL_INFO(dev)->gen >= 4) {
15805 error->plane[i].surface = I915_READ(DSPSURF(i));
15806 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15807 }
15808
c4a1d9e4 15809 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15810
3abfce77 15811 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15812 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15813 }
15814
15815 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15816 if (HAS_DDI(dev_priv->dev))
15817 error->num_transcoders++; /* Account for eDP. */
15818
15819 for (i = 0; i < error->num_transcoders; i++) {
15820 enum transcoder cpu_transcoder = transcoders[i];
15821
ddf9c536 15822 error->transcoder[i].power_domain_on =
f458ebbc 15823 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15824 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15825 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15826 continue;
15827
63b66e5b
CW		 15828 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15829
15830 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15831 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15832 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15833 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15834 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15835 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15836 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15837 }
15838
15839 return error;
15840}
15841
edc3d884
MK		 15842#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15843
c4a1d9e4 15844void
edc3d884 15845intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15846 struct drm_device *dev,
15847 struct intel_display_error_state *error)
15848{
055e393f 15849 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15850 int i;
15851
63b66e5b
CW		 15852 if (!error)
15853 return;
15854
edc3d884 15855 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15856 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15857 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15858 error->power_well_driver);
055e393f 15859 for_each_pipe(dev_priv, i) {
edc3d884 15860 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15861 err_printf(m, " Power: %s\n",
15862 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15863 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15864 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15865
15866 err_printf(m, "Plane [%d]:\n", i);
15867 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15868 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15869 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15870 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15871 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15872 }
4b71a570 15873 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15874 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15875 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15876 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15877 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15878 }
15879
edc3d884
MK		 15880 err_printf(m, "Cursor [%d]:\n", i);
15881 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15882 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15883 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15884 }
63b66e5b
CW		 15885
15886 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15887 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15888 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15889 err_printf(m, " Power: %s\n",
15890 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15891 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15892 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15893 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15894 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15895 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15896 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15897 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15898 }
c4a1d9e4 15899}
e2fcdaa9
VS		 15900
15901void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15902{
15903 struct intel_crtc *crtc;
15904
15905 for_each_intel_crtc(dev, crtc) {
15906 struct intel_unpin_work *work;
e2fcdaa9 15907
5e2d7afc 15908 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15909
15910 work = crtc->unpin_work;
15911
15912 if (work && work->event &&
15913 work->event->base.file_priv == file) {
15914 kfree(work->event);
15915 work->event = NULL;
15916 }
15917
5e2d7afc 15918 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15919 }
15920}
Linux kernel - Deliverables
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