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drm: Print pretty names for pixel formats
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
57f350b6
JB		 384u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385{
09153000 386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 387
57f350b6
JB		 388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
09153000 390 return 0;
57f350b6
JB		 391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
09153000 398 return 0;
57f350b6 399 }
57f350b6 400
09153000 401 return I915_READ(DPIO_DATA);
57f350b6
JB		 402}
403
e2fa6fba 404void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 405{
09153000 406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 407
a0c4da24
JB		 408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
09153000 410 return;
a0c4da24
JB		 411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 419}
420
1b894b59
CW		 421static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
2c07245f 423{
b91ad0ec 424 struct drm_device *dev = crtc->dev;
2c07245f 425 const intel_limit_t *limit;
b91ad0ec
ZW		 426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 428 if (intel_is_dual_link_lvds(dev)) {
1b894b59 429 if (refclk == 100000)
b91ad0ec
ZW		 430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
1b894b59 434 if (refclk == 100000)
b91ad0ec
ZW		 435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
c6bb3538 439 } else
b91ad0ec 440 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 441
442 return limit;
443}
444
044c7c41
ML		 445static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446{
447 struct drm_device *dev = crtc->dev;
044c7c41
ML		 448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 451 if (intel_is_dual_link_lvds(dev))
e4b36699 452 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 453 else
e4b36699 454 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 457 limit = &intel_limits_g4x_hdmi;
044c7c41 458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 459 limit = &intel_limits_g4x_sdvo;
044c7c41 460 } else /* The option is for other outputs */
e4b36699 461 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 462
463 return limit;
464}
465
1b894b59 466static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 467{
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
bad720ff 471 if (HAS_PCH_SPLIT(dev))
1b894b59 472 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 473 else if (IS_G4X(dev)) {
044c7c41 474 limit = intel_g4x_limit(crtc);
f2b115e6 475 } else if (IS_PINEVIEW(dev)) {
2177832f 476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 477 limit = &intel_limits_pineview_lvds;
2177832f 478 else
f2b115e6 479 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 494 limit = &intel_limits_i8xx_lvds;
79e53945 495 else
e4b36699 496 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 497 }
498 return limit;
499}
500
f2b115e6
AJ		 501/* m1 is reserved as 0 in Pineview, n is a ring counter */
502static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 503{
2177832f
SL		 504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508}
509
7429e9d4
DV		 510static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511{
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513}
514
2177832f
SL		 515static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516{
f2b115e6
AJ		 517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
2177832f
SL		 519 return;
520 }
7429e9d4 521 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525}
526
79e53945
JB		 527/**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
4ef69c7a 530bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 531{
4ef69c7a 532 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 533 struct intel_encoder *encoder;
534
6c2b7c12
DV		 535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
4ef69c7a
CW		 537 return true;
538
539 return false;
79e53945
JB		 540}
541
7c04d1d9 542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
1b894b59
CW		 548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
79e53945 551{
79e53945 552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 553 INTELPllInvalid("p1 out of range\n");
79e53945 554 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 555 INTELPllInvalid("p out of range\n");
79e53945 556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 557 INTELPllInvalid("m2 out of range\n");
79e53945 558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 559 INTELPllInvalid("m1 out of range\n");
f2b115e6 560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 561 INTELPllInvalid("m1 <= m2\n");
79e53945 562 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 563 INTELPllInvalid("m out of range\n");
79e53945 564 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 565 INTELPllInvalid("n out of range\n");
79e53945 566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 567 INTELPllInvalid("vco out of range\n");
79e53945
JB		 568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 572 INTELPllInvalid("dot out of range\n");
79e53945
JB		 573
574 return true;
575}
576
d4906093
ML		 577static bool
578intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
d4906093 581
79e53945
JB		 582{
583 struct drm_device *dev = crtc->dev;
79e53945 584 intel_clock_t clock;
79e53945
JB		 585 int err = target;
586
a210b028 587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 588 /*
a210b028
DV		 589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
79e53945 592 */
1974cad0 593 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
0206e353 604 memset(best_clock, 0, sizeof(*best_clock));
79e53945 605
42158660
ZY		 606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 617 int this_err;
618
2177832f 619 intel_clock(dev, refclk, &clock);
1b894b59
CW		 620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
79e53945 622 continue;
cec2f356
SP		 623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
79e53945
JB		 626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638}
639
d4906093
ML		 640static bool
641intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
d4906093
ML		 644{
645 struct drm_device *dev = crtc->dev;
d4906093
ML		 646 intel_clock_t clock;
647 int max_n;
648 bool found;
6ba770dc
AJ		 649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 654 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666 max_n = limit->n.max;
f77f13e2 667 /* based on hardware requirement, prefer smaller n to precision */
d4906093 668 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 669 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 670 for (clock.m1 = limit->m1.max;
671 clock.m1 >= limit->m1.min; clock.m1--) {
672 for (clock.m2 = limit->m2.max;
673 clock.m2 >= limit->m2.min; clock.m2--) {
674 for (clock.p1 = limit->p1.max;
675 clock.p1 >= limit->p1.min; clock.p1--) {
676 int this_err;
677
2177832f 678 intel_clock(dev, refclk, &clock);
1b894b59
CW		 679 if (!intel_PLL_is_valid(dev, limit,
680 &clock))
d4906093 681 continue;
1b894b59
CW		 682
683 this_err = abs(clock.dot - target);
d4906093
ML		 684 if (this_err < err_most) {
685 *best_clock = clock;
686 err_most = this_err;
687 max_n = clock.n;
688 found = true;
689 }
690 }
691 }
692 }
693 }
2c07245f
ZW		 694 return found;
695}
696
a0c4da24
JB		 697static bool
698intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
699 int target, int refclk, intel_clock_t *match_clock,
700 intel_clock_t *best_clock)
701{
702 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
703 u32 m, n, fastclk;
704 u32 updrate, minupdate, fracbits, p;
705 unsigned long bestppm, ppm, absppm;
706 int dotclk, flag;
707
af447bd3 708 flag = 0;
a0c4da24
JB		 709 dotclk = target * 1000;
710 bestppm = 1000000;
711 ppm = absppm = 0;
712 fastclk = dotclk / (2*100);
713 updrate = 0;
714 minupdate = 19200;
715 fracbits = 1;
716 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
717 bestm1 = bestm2 = bestp1 = bestp2 = 0;
718
719 /* based on hardware requirement, prefer smaller n to precision */
720 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
721 updrate = refclk / n;
722 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
723 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
724 if (p2 > 10)
725 p2 = p2 - 1;
726 p = p1 * p2;
727 /* based on hardware requirement, prefer bigger m1,m2 values */
728 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
729 m2 = (((2*(fastclk * p * n / m1 )) +
730 refclk) / (2*refclk));
731 m = m1 * m2;
732 vco = updrate * m;
733 if (vco >= limit->vco.min && vco < limit->vco.max) {
734 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
735 absppm = (ppm > 0) ? ppm : (-ppm);
736 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
737 bestppm = 0;
738 flag = 1;
739 }
740 if (absppm < bestppm - 10) {
741 bestppm = absppm;
742 flag = 1;
743 }
744 if (flag) {
745 bestn = n;
746 bestm1 = m1;
747 bestm2 = m2;
748 bestp1 = p1;
749 bestp2 = p2;
750 flag = 0;
751 }
752 }
753 }
754 }
755 }
756 }
757 best_clock->n = bestn;
758 best_clock->m1 = bestm1;
759 best_clock->m2 = bestm2;
760 best_clock->p1 = bestp1;
761 best_clock->p2 = bestp2;
762
763 return true;
764}
a4fc5ed6 765
a5c961d1
PZ		 766enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
767 enum pipe pipe)
768{
769 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
771
3b117c8f 772 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 773}
774
a928d536
PZ		 775static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
776{
777 struct drm_i915_private *dev_priv = dev->dev_private;
778 u32 frame, frame_reg = PIPEFRAME(pipe);
779
780 frame = I915_READ(frame_reg);
781
782 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
783 DRM_DEBUG_KMS("vblank wait timed out\n");
784}
785
9d0498a2
JB		 786/**
787 * intel_wait_for_vblank - wait for vblank on a given pipe
788 * @dev: drm device
789 * @pipe: pipe to wait for
790 *
791 * Wait for vblank to occur on a given pipe. Needed for various bits of
792 * mode setting code.
793 */
794void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 795{
9d0498a2 796 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 797 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 798
a928d536
PZ		 799 if (INTEL_INFO(dev)->gen >= 5) {
800 ironlake_wait_for_vblank(dev, pipe);
801 return;
802 }
803
300387c0
CW		 804 /* Clear existing vblank status. Note this will clear any other
805 * sticky status fields as well.
806 *
807 * This races with i915_driver_irq_handler() with the result
808 * that either function could miss a vblank event. Here it is not
809 * fatal, as we will either wait upon the next vblank interrupt or
810 * timeout. Generally speaking intel_wait_for_vblank() is only
811 * called during modeset at which time the GPU should be idle and
812 * should *not* be performing page flips and thus not waiting on
813 * vblanks...
814 * Currently, the result of us stealing a vblank from the irq
815 * handler is that a single frame will be skipped during swapbuffers.
816 */
817 I915_WRITE(pipestat_reg,
818 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
819
9d0498a2 820 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 821 if (wait_for(I915_READ(pipestat_reg) &
822 PIPE_VBLANK_INTERRUPT_STATUS,
823 50))
9d0498a2
JB		 824 DRM_DEBUG_KMS("vblank wait timed out\n");
825}
826
ab7ad7f6
KP		 827/*
828 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 829 * @dev: drm device
830 * @pipe: pipe to wait for
831 *
832 * After disabling a pipe, we can't wait for vblank in the usual way,
833 * spinning on the vblank interrupt status bit, since we won't actually
834 * see an interrupt when the pipe is disabled.
835 *
ab7ad7f6
KP		 836 * On Gen4 and above:
837 * wait for the pipe register state bit to turn off
838 *
839 * Otherwise:
840 * wait for the display line value to settle (it usually
841 * ends up stopping at the start of the next frame).
58e10eb9 842 *
9d0498a2 843 */
58e10eb9 844void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 845{
846 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 847 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
848 pipe);
ab7ad7f6
KP		 849
850 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 851 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 852
853 /* Wait for the Pipe State to go off */
58e10eb9
CW		 854 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
855 100))
284637d9 856 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 857 } else {
837ba00f 858 u32 last_line, line_mask;
58e10eb9 859 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 860 unsigned long timeout = jiffies + msecs_to_jiffies(100);
861
837ba00f
PZ		 862 if (IS_GEN2(dev))
863 line_mask = DSL_LINEMASK_GEN2;
864 else
865 line_mask = DSL_LINEMASK_GEN3;
866
ab7ad7f6
KP		 867 /* Wait for the display line to settle */
868 do {
837ba00f 869 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 870 mdelay(5);
837ba00f 871 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 872 time_after(timeout, jiffies));
873 if (time_after(jiffies, timeout))
284637d9 874 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 875 }
79e53945
JB		 876}
877
b0ea7d37
DL		 878/*
879 * ibx_digital_port_connected - is the specified port connected?
880 * @dev_priv: i915 private structure
881 * @port: the port to test
882 *
883 * Returns true if @port is connected, false otherwise.
884 */
885bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
886 struct intel_digital_port *port)
887{
888 u32 bit;
889
c36346e3
DL		 890 if (HAS_PCH_IBX(dev_priv->dev)) {
891 switch(port->port) {
892 case PORT_B:
893 bit = SDE_PORTB_HOTPLUG;
894 break;
895 case PORT_C:
896 bit = SDE_PORTC_HOTPLUG;
897 break;
898 case PORT_D:
899 bit = SDE_PORTD_HOTPLUG;
900 break;
901 default:
902 return true;
903 }
904 } else {
905 switch(port->port) {
906 case PORT_B:
907 bit = SDE_PORTB_HOTPLUG_CPT;
908 break;
909 case PORT_C:
910 bit = SDE_PORTC_HOTPLUG_CPT;
911 break;
912 case PORT_D:
913 bit = SDE_PORTD_HOTPLUG_CPT;
914 break;
915 default:
916 return true;
917 }
b0ea7d37
DL		 918 }
919
920 return I915_READ(SDEISR) & bit;
921}
922
b24e7179
JB		 923static const char *state_string(bool enabled)
924{
925 return enabled ? "on" : "off";
926}
927
928/* Only for pre-ILK configs */
929static void assert_pll(struct drm_i915_private *dev_priv,
930 enum pipe pipe, bool state)
931{
932 int reg;
933 u32 val;
934 bool cur_state;
935
936 reg = DPLL(pipe);
937 val = I915_READ(reg);
938 cur_state = !!(val & DPLL_VCO_ENABLE);
939 WARN(cur_state != state,
940 "PLL state assertion failure (expected %s, current %s)\n",
941 state_string(state), state_string(cur_state));
942}
943#define assert_pll_enabled(d, p) assert_pll(d, p, true)
944#define assert_pll_disabled(d, p) assert_pll(d, p, false)
945
040484af
JB		 946/* For ILK+ */
947static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 948 struct intel_pch_pll *pll,
949 struct intel_crtc *crtc,
950 bool state)
040484af 951{
040484af
JB		 952 u32 val;
953 bool cur_state;
954
9d82aa17
ED		 955 if (HAS_PCH_LPT(dev_priv->dev)) {
956 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
957 return;
958 }
959
92b27b08
CW		 960 if (WARN (!pll,
961 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 962 return;
ee7b9f93 963
92b27b08
CW		 964 val = I915_READ(pll->pll_reg);
965 cur_state = !!(val & DPLL_VCO_ENABLE);
966 WARN(cur_state != state,
967 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
968 pll->pll_reg, state_string(state), state_string(cur_state), val);
969
970 /* Make sure the selected PLL is correctly attached to the transcoder */
971 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 972 u32 pch_dpll;
973
974 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 975 cur_state = pll->pll_reg == _PCH_DPLL_B;
976 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 977 "PLL[%d] not attached to this transcoder %c: %08x\n",
978 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 979 cur_state = !!(val >> (4*crtc->pipe + 3));
980 WARN(cur_state != state,
4bb6f1f3 981 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 982 pll->pll_reg == _PCH_DPLL_B,
983 state_string(state),
4bb6f1f3 984 pipe_name(crtc->pipe),
92b27b08
CW		 985 val);
986 }
d3ccbe86 987 }
040484af 988}
92b27b08
CW		 989#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
990#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 991
992static void assert_fdi_tx(struct drm_i915_private *dev_priv,
993 enum pipe pipe, bool state)
994{
995 int reg;
996 u32 val;
997 bool cur_state;
ad80a810
PZ		 998 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
999 pipe);
040484af 1000
affa9354
PZ		 1001 if (HAS_DDI(dev_priv->dev)) {
1002 /* DDI does not have a specific FDI_TX register */
ad80a810 1003 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1004 val = I915_READ(reg);
ad80a810 1005 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1006 } else {
1007 reg = FDI_TX_CTL(pipe);
1008 val = I915_READ(reg);
1009 cur_state = !!(val & FDI_TX_ENABLE);
1010 }
040484af
JB		 1011 WARN(cur_state != state,
1012 "FDI TX state assertion failure (expected %s, current %s)\n",
1013 state_string(state), state_string(cur_state));
1014}
1015#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1016#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1017
1018static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1019 enum pipe pipe, bool state)
1020{
1021 int reg;
1022 u32 val;
1023 bool cur_state;
1024
d63fa0dc
PZ		 1025 reg = FDI_RX_CTL(pipe);
1026 val = I915_READ(reg);
1027 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1028 WARN(cur_state != state,
1029 "FDI RX state assertion failure (expected %s, current %s)\n",
1030 state_string(state), state_string(cur_state));
1031}
1032#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1033#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1034
1035static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1036 enum pipe pipe)
1037{
1038 int reg;
1039 u32 val;
1040
1041 /* ILK FDI PLL is always enabled */
1042 if (dev_priv->info->gen == 5)
1043 return;
1044
bf507ef7 1045 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1046 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1047 return;
1048
040484af
JB		 1049 reg = FDI_TX_CTL(pipe);
1050 val = I915_READ(reg);
1051 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1052}
1053
1054static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1055 enum pipe pipe)
1056{
1057 int reg;
1058 u32 val;
1059
1060 reg = FDI_RX_CTL(pipe);
1061 val = I915_READ(reg);
1062 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1063}
1064
ea0760cf
JB		 1065static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1066 enum pipe pipe)
1067{
1068 int pp_reg, lvds_reg;
1069 u32 val;
1070 enum pipe panel_pipe = PIPE_A;
0de3b485 1071 bool locked = true;
ea0760cf
JB		 1072
1073 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1074 pp_reg = PCH_PP_CONTROL;
1075 lvds_reg = PCH_LVDS;
1076 } else {
1077 pp_reg = PP_CONTROL;
1078 lvds_reg = LVDS;
1079 }
1080
1081 val = I915_READ(pp_reg);
1082 if (!(val & PANEL_POWER_ON) ||
1083 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1084 locked = false;
1085
1086 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1087 panel_pipe = PIPE_B;
1088
1089 WARN(panel_pipe == pipe && locked,
1090 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1091 pipe_name(pipe));
ea0760cf
JB		 1092}
1093
b840d907
JB		 1094void assert_pipe(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
b24e7179
JB		 1096{
1097 int reg;
1098 u32 val;
63d7bbe9 1099 bool cur_state;
702e7a56
PZ		 1100 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1101 pipe);
b24e7179 1102
8e636784
DV		 1103 /* if we need the pipe A quirk it must be always on */
1104 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1105 state = true;
1106
b97186f0
PZ		 1107 if (!intel_display_power_enabled(dev_priv->dev,
1108 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1109 cur_state = false;
1110 } else {
1111 reg = PIPECONF(cpu_transcoder);
1112 val = I915_READ(reg);
1113 cur_state = !!(val & PIPECONF_ENABLE);
1114 }
1115
63d7bbe9
JB		 1116 WARN(cur_state != state,
1117 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1118 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1119}
1120
931872fc
CW		 1121static void assert_plane(struct drm_i915_private *dev_priv,
1122 enum plane plane, bool state)
b24e7179
JB		 1123{
1124 int reg;
1125 u32 val;
931872fc 1126 bool cur_state;
b24e7179
JB		 1127
1128 reg = DSPCNTR(plane);
1129 val = I915_READ(reg);
931872fc
CW		 1130 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1131 WARN(cur_state != state,
1132 "plane %c assertion failure (expected %s, current %s)\n",
1133 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1137#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1138
b24e7179
JB		 1139static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1140 enum pipe pipe)
1141{
1142 int reg, i;
1143 u32 val;
1144 int cur_pipe;
1145
19ec1358 1146 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1147 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1148 reg = DSPCNTR(pipe);
1149 val = I915_READ(reg);
1150 WARN((val & DISPLAY_PLANE_ENABLE),
1151 "plane %c assertion failure, should be disabled but not\n",
1152 plane_name(pipe));
19ec1358 1153 return;
28c05794 1154 }
19ec1358 1155
b24e7179
JB		 1156 /* Need to check both planes against the pipe */
1157 for (i = 0; i < 2; i++) {
1158 reg = DSPCNTR(i);
1159 val = I915_READ(reg);
1160 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1161 DISPPLANE_SEL_PIPE_SHIFT;
1162 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1163 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1164 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1165 }
1166}
1167
19332d7a
JB		 1168static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1169 enum pipe pipe)
1170{
1171 int reg, i;
1172 u32 val;
1173
1174 if (!IS_VALLEYVIEW(dev_priv->dev))
1175 return;
1176
1177 /* Need to check both planes against the pipe */
1178 for (i = 0; i < dev_priv->num_plane; i++) {
1179 reg = SPCNTR(pipe, i);
1180 val = I915_READ(reg);
1181 WARN((val & SP_ENABLE),
06da8da2
VS		 1182 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1183 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1184 }
1185}
1186
92f2584a
JB		 1187static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1188{
1189 u32 val;
1190 bool enabled;
1191
9d82aa17
ED		 1192 if (HAS_PCH_LPT(dev_priv->dev)) {
1193 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1194 return;
1195 }
1196
92f2584a
JB		 1197 val = I915_READ(PCH_DREF_CONTROL);
1198 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1199 DREF_SUPERSPREAD_SOURCE_MASK));
1200 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1201}
1202
ab9412ba
DV		 1203static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
92f2584a
JB		 1205{
1206 int reg;
1207 u32 val;
1208 bool enabled;
1209
ab9412ba 1210 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1211 val = I915_READ(reg);
1212 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1213 WARN(enabled,
1214 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1215 pipe_name(pipe));
92f2584a
JB		 1216}
1217
4e634389
KP		 1218static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1220{
1221 if ((val & DP_PORT_EN) == 0)
1222 return false;
1223
1224 if (HAS_PCH_CPT(dev_priv->dev)) {
1225 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1226 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1227 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1228 return false;
1229 } else {
1230 if ((val & DP_PIPE_MASK) != (pipe << 30))
1231 return false;
1232 }
1233 return true;
1234}
1235
1519b995
KP		 1236static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238{
dc0fa718 1239 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1240 return false;
1241
1242 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1243 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1244 return false;
1245 } else {
dc0fa718 1246 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1247 return false;
1248 }
1249 return true;
1250}
1251
1252static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, u32 val)
1254{
1255 if ((val & LVDS_PORT_EN) == 0)
1256 return false;
1257
1258 if (HAS_PCH_CPT(dev_priv->dev)) {
1259 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1260 return false;
1261 } else {
1262 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1263 return false;
1264 }
1265 return true;
1266}
1267
1268static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1269 enum pipe pipe, u32 val)
1270{
1271 if ((val & ADPA_DAC_ENABLE) == 0)
1272 return false;
1273 if (HAS_PCH_CPT(dev_priv->dev)) {
1274 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1275 return false;
1276 } else {
1277 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1278 return false;
1279 }
1280 return true;
1281}
1282
291906f1 1283static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1284 enum pipe pipe, int reg, u32 port_sel)
291906f1 1285{
47a05eca 1286 u32 val = I915_READ(reg);
4e634389 1287 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1288 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1289 reg, pipe_name(pipe));
de9a35ab 1290
75c5da27
DV		 1291 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1292 && (val & DP_PIPEB_SELECT),
de9a35ab 1293 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1294}
1295
1296static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, int reg)
1298{
47a05eca 1299 u32 val = I915_READ(reg);
b70ad586 1300 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1301 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1302 reg, pipe_name(pipe));
de9a35ab 1303
dc0fa718 1304 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1305 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1306 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1307}
1308
1309static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe)
1311{
1312 int reg;
1313 u32 val;
291906f1 1314
f0575e92
KP		 1315 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1316 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1317 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1318
1319 reg = PCH_ADPA;
1320 val = I915_READ(reg);
b70ad586 1321 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1322 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1323 pipe_name(pipe));
291906f1
JB		 1324
1325 reg = PCH_LVDS;
1326 val = I915_READ(reg);
b70ad586 1327 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1328 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 pipe_name(pipe));
291906f1 1330
e2debe91
PZ		 1331 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1332 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1333 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1334}
1335
63d7bbe9
JB		 1336/**
1337 * intel_enable_pll - enable a PLL
1338 * @dev_priv: i915 private structure
1339 * @pipe: pipe PLL to enable
1340 *
1341 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1342 * make sure the PLL reg is writable first though, since the panel write
1343 * protect mechanism may be enabled.
1344 *
1345 * Note! This is for pre-ILK only.
7434a255
TR		 1346 *
1347 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1348 */
1349static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1350{
1351 int reg;
1352 u32 val;
1353
58c6eaa2
DV		 1354 assert_pipe_disabled(dev_priv, pipe);
1355
63d7bbe9 1356 /* No really, not for ILK+ */
a0c4da24 1357 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1358
1359 /* PLL is protected by panel, make sure we can write it */
1360 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1361 assert_panel_unlocked(dev_priv, pipe);
1362
1363 reg = DPLL(pipe);
1364 val = I915_READ(reg);
1365 val |= DPLL_VCO_ENABLE;
1366
1367 /* We do this three times for luck */
1368 I915_WRITE(reg, val);
1369 POSTING_READ(reg);
1370 udelay(150); /* wait for warmup */
1371 I915_WRITE(reg, val);
1372 POSTING_READ(reg);
1373 udelay(150); /* wait for warmup */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377}
1378
1379/**
1380 * intel_disable_pll - disable a PLL
1381 * @dev_priv: i915 private structure
1382 * @pipe: pipe PLL to disable
1383 *
1384 * Disable the PLL for @pipe, making sure the pipe is off first.
1385 *
1386 * Note! This is for pre-ILK only.
1387 */
1388static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1389{
1390 int reg;
1391 u32 val;
1392
1393 /* Don't disable pipe A or pipe A PLLs if needed */
1394 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1395 return;
1396
1397 /* Make sure the pipe isn't still relying on us */
1398 assert_pipe_disabled(dev_priv, pipe);
1399
1400 reg = DPLL(pipe);
1401 val = I915_READ(reg);
1402 val &= ~DPLL_VCO_ENABLE;
1403 I915_WRITE(reg, val);
1404 POSTING_READ(reg);
1405}
1406
a416edef
ED		 1407/* SBI access */
1408static void
988d6ee8
PZ		 1409intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1410 enum intel_sbi_destination destination)
a416edef 1411{
988d6ee8 1412 u32 tmp;
a416edef 1413
09153000 1414 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1415
39fb50f6 1416 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1417 100)) {
1418 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1419 return;
a416edef
ED		 1420 }
1421
988d6ee8
PZ		 1422 I915_WRITE(SBI_ADDR, (reg << 16));
1423 I915_WRITE(SBI_DATA, value);
1424
1425 if (destination == SBI_ICLK)
1426 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1427 else
1428 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1429 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1430
39fb50f6 1431 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1432 100)) {
1433 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1434 return;
a416edef 1435 }
a416edef
ED		 1436}
1437
1438static u32
988d6ee8
PZ		 1439intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1440 enum intel_sbi_destination destination)
a416edef 1441{
39fb50f6 1442 u32 value = 0;
09153000 1443 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1444
39fb50f6 1445 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1446 100)) {
1447 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1448 return 0;
a416edef
ED		 1449 }
1450
988d6ee8
PZ		 1451 I915_WRITE(SBI_ADDR, (reg << 16));
1452
1453 if (destination == SBI_ICLK)
1454 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1455 else
1456 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1457 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1458
39fb50f6 1459 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1460 100)) {
1461 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1462 return 0;
a416edef
ED		 1463 }
1464
09153000 1465 return I915_READ(SBI_DATA);
a416edef
ED		 1466}
1467
89b667f8
JB		 1468void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1469{
1470 u32 port_mask;
1471
1472 if (!port)
1473 port_mask = DPLL_PORTB_READY_MASK;
1474 else
1475 port_mask = DPLL_PORTC_READY_MASK;
1476
1477 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1478 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1479 'B' + port, I915_READ(DPLL(0)));
1480}
1481
92f2584a 1482/**
b6b4e185 1483 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1484 * @dev_priv: i915 private structure
1485 * @pipe: pipe PLL to enable
1486 *
1487 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1488 * drives the transcoder clock.
1489 */
b6b4e185 1490static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1491{
ee7b9f93 1492 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1493 struct intel_pch_pll *pll;
92f2584a
JB		 1494 int reg;
1495 u32 val;
1496
48da64a8 1497 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1498 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1499 pll = intel_crtc->pch_pll;
1500 if (pll == NULL)
1501 return;
1502
1503 if (WARN_ON(pll->refcount == 0))
1504 return;
ee7b9f93
JB		 1505
1506 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1507 pll->pll_reg, pll->active, pll->on,
1508 intel_crtc->base.base.id);
92f2584a
JB		 1509
1510 /* PCH refclock must be enabled first */
1511 assert_pch_refclk_enabled(dev_priv);
1512
ee7b9f93 1513 if (pll->active++ && pll->on) {
92b27b08 1514 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1515 return;
1516 }
1517
1518 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1519
1520 reg = pll->pll_reg;
92f2584a
JB		 1521 val = I915_READ(reg);
1522 val |= DPLL_VCO_ENABLE;
1523 I915_WRITE(reg, val);
1524 POSTING_READ(reg);
1525 udelay(200);
ee7b9f93
JB		 1526
1527 pll->on = true;
92f2584a
JB		 1528}
1529
ee7b9f93 1530static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1531{
ee7b9f93
JB		 1532 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1533 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1534 int reg;
ee7b9f93 1535 u32 val;
4c609cb8 1536
92f2584a
JB		 1537 /* PCH only available on ILK+ */
1538 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1539 if (pll == NULL)
1540 return;
92f2584a 1541
48da64a8
CW		 1542 if (WARN_ON(pll->refcount == 0))
1543 return;
7a419866 1544
ee7b9f93
JB		 1545 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1546 pll->pll_reg, pll->active, pll->on,
1547 intel_crtc->base.base.id);
7a419866 1548
48da64a8 1549 if (WARN_ON(pll->active == 0)) {
92b27b08 1550 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1551 return;
1552 }
1553
ee7b9f93 1554 if (--pll->active) {
92b27b08 1555 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1556 return;
ee7b9f93
JB		 1557 }
1558
1559 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1560
1561 /* Make sure transcoder isn't still depending on us */
ab9412ba 1562 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1563
ee7b9f93 1564 reg = pll->pll_reg;
92f2584a
JB		 1565 val = I915_READ(reg);
1566 val &= ~DPLL_VCO_ENABLE;
1567 I915_WRITE(reg, val);
1568 POSTING_READ(reg);
1569 udelay(200);
ee7b9f93
JB		 1570
1571 pll->on = false;
92f2584a
JB		 1572}
1573
b8a4f404
PZ		 1574static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1575 enum pipe pipe)
040484af 1576{
23670b32 1577 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1578 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1579 uint32_t reg, val, pipeconf_val;
040484af
JB		 1580
1581 /* PCH only available on ILK+ */
1582 BUG_ON(dev_priv->info->gen < 5);
1583
1584 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1585 assert_pch_pll_enabled(dev_priv,
1586 to_intel_crtc(crtc)->pch_pll,
1587 to_intel_crtc(crtc));
040484af
JB		 1588
1589 /* FDI must be feeding us bits for PCH ports */
1590 assert_fdi_tx_enabled(dev_priv, pipe);
1591 assert_fdi_rx_enabled(dev_priv, pipe);
1592
23670b32
DV		 1593 if (HAS_PCH_CPT(dev)) {
1594 /* Workaround: Set the timing override bit before enabling the
1595 * pch transcoder. */
1596 reg = TRANS_CHICKEN2(pipe);
1597 val = I915_READ(reg);
1598 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1599 I915_WRITE(reg, val);
59c859d6 1600 }
23670b32 1601
ab9412ba 1602 reg = PCH_TRANSCONF(pipe);
040484af 1603 val = I915_READ(reg);
5f7f726d 1604 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1605
1606 if (HAS_PCH_IBX(dev_priv->dev)) {
1607 /*
1608 * make the BPC in transcoder be consistent with
1609 * that in pipeconf reg.
1610 */
dfd07d72
DV		 1611 val &= ~PIPECONF_BPC_MASK;
1612 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1613 }
5f7f726d
PZ		 1614
1615 val &= ~TRANS_INTERLACE_MASK;
1616 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1617 if (HAS_PCH_IBX(dev_priv->dev) &&
1618 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1619 val |= TRANS_LEGACY_INTERLACED_ILK;
1620 else
1621 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1622 else
1623 val |= TRANS_PROGRESSIVE;
1624
040484af
JB		 1625 I915_WRITE(reg, val | TRANS_ENABLE);
1626 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1627 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1628}
1629
8fb033d7 1630static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1631 enum transcoder cpu_transcoder)
040484af 1632{
8fb033d7 1633 u32 val, pipeconf_val;
8fb033d7
PZ		 1634
1635 /* PCH only available on ILK+ */
1636 BUG_ON(dev_priv->info->gen < 5);
1637
8fb033d7 1638 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1639 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1640 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1641
223a6fdf
PZ		 1642 /* Workaround: set timing override bit. */
1643 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1644 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1645 I915_WRITE(_TRANSA_CHICKEN2, val);
1646
25f3ef11 1647 val = TRANS_ENABLE;
937bb610 1648 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1649
9a76b1c6
PZ		 1650 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1651 PIPECONF_INTERLACED_ILK)
a35f2679 1652 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1653 else
1654 val |= TRANS_PROGRESSIVE;
1655
ab9412ba
DV		 1656 I915_WRITE(LPT_TRANSCONF, val);
1657 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1658 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1659}
1660
b8a4f404
PZ		 1661static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1662 enum pipe pipe)
040484af 1663{
23670b32
DV		 1664 struct drm_device *dev = dev_priv->dev;
1665 uint32_t reg, val;
040484af
JB		 1666
1667 /* FDI relies on the transcoder */
1668 assert_fdi_tx_disabled(dev_priv, pipe);
1669 assert_fdi_rx_disabled(dev_priv, pipe);
1670
291906f1
JB		 1671 /* Ports must be off as well */
1672 assert_pch_ports_disabled(dev_priv, pipe);
1673
ab9412ba 1674 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1675 val = I915_READ(reg);
1676 val &= ~TRANS_ENABLE;
1677 I915_WRITE(reg, val);
1678 /* wait for PCH transcoder off, transcoder state */
1679 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1680 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1681
1682 if (!HAS_PCH_IBX(dev)) {
1683 /* Workaround: Clear the timing override chicken bit again. */
1684 reg = TRANS_CHICKEN2(pipe);
1685 val = I915_READ(reg);
1686 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1687 I915_WRITE(reg, val);
1688 }
040484af
JB		 1689}
1690
ab4d966c 1691static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1692{
8fb033d7
PZ		 1693 u32 val;
1694
ab9412ba 1695 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1696 val &= ~TRANS_ENABLE;
ab9412ba 1697 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1698 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1699 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1700 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1701
1702 /* Workaround: clear timing override bit. */
1703 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1704 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1705 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1706}
1707
b24e7179 1708/**
309cfea8 1709 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1710 * @dev_priv: i915 private structure
1711 * @pipe: pipe to enable
040484af 1712 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1713 *
1714 * Enable @pipe, making sure that various hardware specific requirements
1715 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1716 *
1717 * @pipe should be %PIPE_A or %PIPE_B.
1718 *
1719 * Will wait until the pipe is actually running (i.e. first vblank) before
1720 * returning.
1721 */
040484af
JB		 1722static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1723 bool pch_port)
b24e7179 1724{
702e7a56
PZ		 1725 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1726 pipe);
1a240d4d 1727 enum pipe pch_transcoder;
b24e7179
JB		 1728 int reg;
1729 u32 val;
1730
58c6eaa2
DV		 1731 assert_planes_disabled(dev_priv, pipe);
1732 assert_sprites_disabled(dev_priv, pipe);
1733
681e5811 1734 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1735 pch_transcoder = TRANSCODER_A;
1736 else
1737 pch_transcoder = pipe;
1738
b24e7179
JB		 1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
cc391bbb 1749 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1750 assert_fdi_tx_pll_enabled(dev_priv,
1751 (enum pipe) cpu_transcoder);
040484af
JB		 1752 }
1753 /* FIXME: assert CPU port conditions for SNB+ */
1754 }
b24e7179 1755
702e7a56 1756 reg = PIPECONF(cpu_transcoder);
b24e7179 1757 val = I915_READ(reg);
00d70b15
CW		 1758 if (val & PIPECONF_ENABLE)
1759 return;
1760
1761 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1762 intel_wait_for_vblank(dev_priv->dev, pipe);
1763}
1764
1765/**
309cfea8 1766 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1767 * @dev_priv: i915 private structure
1768 * @pipe: pipe to disable
1769 *
1770 * Disable @pipe, making sure that various hardware specific requirements
1771 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1772 *
1773 * @pipe should be %PIPE_A or %PIPE_B.
1774 *
1775 * Will wait until the pipe has shut down before returning.
1776 */
1777static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1778 enum pipe pipe)
1779{
702e7a56
PZ		 1780 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1781 pipe);
b24e7179
JB		 1782 int reg;
1783 u32 val;
1784
1785 /*
1786 * Make sure planes won't keep trying to pump pixels to us,
1787 * or we might hang the display.
1788 */
1789 assert_planes_disabled(dev_priv, pipe);
19332d7a 1790 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1791
1792 /* Don't disable pipe A or pipe A PLLs if needed */
1793 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1794 return;
1795
702e7a56 1796 reg = PIPECONF(cpu_transcoder);
b24e7179 1797 val = I915_READ(reg);
00d70b15
CW		 1798 if ((val & PIPECONF_ENABLE) == 0)
1799 return;
1800
1801 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1802 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1803}
1804
d74362c9
KP		 1805/*
1806 * Plane regs are double buffered, going from enabled->disabled needs a
1807 * trigger in order to latch. The display address reg provides this.
1808 */
6f1d69b0 1809void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1810 enum plane plane)
1811{
14f86147
DL		 1812 if (dev_priv->info->gen >= 4)
1813 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1814 else
1815 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1816}
1817
b24e7179
JB		 1818/**
1819 * intel_enable_plane - enable a display plane on a given pipe
1820 * @dev_priv: i915 private structure
1821 * @plane: plane to enable
1822 * @pipe: pipe being fed
1823 *
1824 * Enable @plane on @pipe, making sure that @pipe is running first.
1825 */
1826static void intel_enable_plane(struct drm_i915_private *dev_priv,
1827 enum plane plane, enum pipe pipe)
1828{
1829 int reg;
1830 u32 val;
1831
1832 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1833 assert_pipe_enabled(dev_priv, pipe);
1834
1835 reg = DSPCNTR(plane);
1836 val = I915_READ(reg);
00d70b15
CW		 1837 if (val & DISPLAY_PLANE_ENABLE)
1838 return;
1839
1840 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1841 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1842 intel_wait_for_vblank(dev_priv->dev, pipe);
1843}
1844
b24e7179
JB		 1845/**
1846 * intel_disable_plane - disable a display plane
1847 * @dev_priv: i915 private structure
1848 * @plane: plane to disable
1849 * @pipe: pipe consuming the data
1850 *
1851 * Disable @plane; should be an independent operation.
1852 */
1853static void intel_disable_plane(struct drm_i915_private *dev_priv,
1854 enum plane plane, enum pipe pipe)
1855{
1856 int reg;
1857 u32 val;
1858
1859 reg = DSPCNTR(plane);
1860 val = I915_READ(reg);
00d70b15
CW		 1861 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1862 return;
1863
1864 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1865 intel_flush_display_plane(dev_priv, plane);
1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867}
1868
693db184
CW		 1869static bool need_vtd_wa(struct drm_device *dev)
1870{
1871#ifdef CONFIG_INTEL_IOMMU
1872 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1873 return true;
1874#endif
1875 return false;
1876}
1877
127bd2ac 1878int
48b956c5 1879intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1880 struct drm_i915_gem_object *obj,
919926ae 1881 struct intel_ring_buffer *pipelined)
6b95a207 1882{
ce453d81 1883 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1884 u32 alignment;
1885 int ret;
1886
05394f39 1887 switch (obj->tiling_mode) {
6b95a207 1888 case I915_TILING_NONE:
534843da
CW		 1889 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1890 alignment = 128 * 1024;
a6c45cf0 1891 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1892 alignment = 4 * 1024;
1893 else
1894 alignment = 64 * 1024;
6b95a207
KH		 1895 break;
1896 case I915_TILING_X:
1897 /* pin() will align the object as required by fence */
1898 alignment = 0;
1899 break;
1900 case I915_TILING_Y:
8bb6e959
DV		 1901 /* Despite that we check this in framebuffer_init userspace can
1902 * screw us over and change the tiling after the fact. Only
1903 * pinned buffers can't change their tiling. */
1904 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1905 return -EINVAL;
1906 default:
1907 BUG();
1908 }
1909
693db184
CW		 1910 /* Note that the w/a also requires 64 PTE of padding following the
1911 * bo. We currently fill all unused PTE with the shadow page and so
1912 * we should always have valid PTE following the scanout preventing
1913 * the VT-d warning.
1914 */
1915 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1916 alignment = 256 * 1024;
1917
ce453d81 1918 dev_priv->mm.interruptible = false;
2da3b9b9 1919 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1920 if (ret)
ce453d81 1921 goto err_interruptible;
6b95a207
KH		 1922
1923 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1924 * fence, whereas 965+ only requires a fence if using
1925 * framebuffer compression. For simplicity, we always install
1926 * a fence as the cost is not that onerous.
1927 */
06d98131 1928 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1929 if (ret)
1930 goto err_unpin;
1690e1eb 1931
9a5a53b3 1932 i915_gem_object_pin_fence(obj);
6b95a207 1933
ce453d81 1934 dev_priv->mm.interruptible = true;
6b95a207 1935 return 0;
48b956c5
CW		 1936
1937err_unpin:
1938 i915_gem_object_unpin(obj);
ce453d81
CW		 1939err_interruptible:
1940 dev_priv->mm.interruptible = true;
48b956c5 1941 return ret;
6b95a207
KH		 1942}
1943
1690e1eb
CW		 1944void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1945{
1946 i915_gem_object_unpin_fence(obj);
1947 i915_gem_object_unpin(obj);
1948}
1949
c2c75131
DV		 1950/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1951 * is assumed to be a power-of-two. */
bc752862
CW		 1952unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1953 unsigned int tiling_mode,
1954 unsigned int cpp,
1955 unsigned int pitch)
c2c75131 1956{
bc752862
CW		 1957 if (tiling_mode != I915_TILING_NONE) {
1958 unsigned int tile_rows, tiles;
c2c75131 1959
bc752862
CW		 1960 tile_rows = *y / 8;
1961 *y %= 8;
c2c75131 1962
bc752862
CW		 1963 tiles = *x / (512/cpp);
1964 *x %= 512/cpp;
1965
1966 return tile_rows * pitch * 8 + tiles * 4096;
1967 } else {
1968 unsigned int offset;
1969
1970 offset = *y * pitch + *x * cpp;
1971 *y = 0;
1972 *x = (offset & 4095) / cpp;
1973 return offset & -4096;
1974 }
c2c75131
DV		 1975}
1976
17638cd6
JB		 1977static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1978 int x, int y)
81255565
JB		 1979{
1980 struct drm_device *dev = crtc->dev;
1981 struct drm_i915_private *dev_priv = dev->dev_private;
1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983 struct intel_framebuffer *intel_fb;
05394f39 1984 struct drm_i915_gem_object *obj;
81255565 1985 int plane = intel_crtc->plane;
e506a0c6 1986 unsigned long linear_offset;
81255565 1987 u32 dspcntr;
5eddb70b 1988 u32 reg;
81255565
JB		 1989
1990 switch (plane) {
1991 case 0:
1992 case 1:
1993 break;
1994 default:
84f44ce7 1995 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1996 return -EINVAL;
1997 }
1998
1999 intel_fb = to_intel_framebuffer(fb);
2000 obj = intel_fb->obj;
81255565 2001
5eddb70b
CW		 2002 reg = DSPCNTR(plane);
2003 dspcntr = I915_READ(reg);
81255565
JB		 2004 /* Mask out pixel format bits in case we change it */
2005 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2006 switch (fb->pixel_format) {
2007 case DRM_FORMAT_C8:
81255565
JB		 2008 dspcntr |= DISPPLANE_8BPP;
2009 break;
57779d06
VS		 2010 case DRM_FORMAT_XRGB1555:
2011 case DRM_FORMAT_ARGB1555:
2012 dspcntr |= DISPPLANE_BGRX555;
81255565 2013 break;
57779d06
VS		 2014 case DRM_FORMAT_RGB565:
2015 dspcntr |= DISPPLANE_BGRX565;
2016 break;
2017 case DRM_FORMAT_XRGB8888:
2018 case DRM_FORMAT_ARGB8888:
2019 dspcntr |= DISPPLANE_BGRX888;
2020 break;
2021 case DRM_FORMAT_XBGR8888:
2022 case DRM_FORMAT_ABGR8888:
2023 dspcntr |= DISPPLANE_RGBX888;
2024 break;
2025 case DRM_FORMAT_XRGB2101010:
2026 case DRM_FORMAT_ARGB2101010:
2027 dspcntr |= DISPPLANE_BGRX101010;
2028 break;
2029 case DRM_FORMAT_XBGR2101010:
2030 case DRM_FORMAT_ABGR2101010:
2031 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2032 break;
2033 default:
baba133a 2034 BUG();
81255565 2035 }
57779d06 2036
a6c45cf0 2037 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2038 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2039 dspcntr |= DISPPLANE_TILED;
2040 else
2041 dspcntr &= ~DISPPLANE_TILED;
2042 }
2043
5eddb70b 2044 I915_WRITE(reg, dspcntr);
81255565 2045
e506a0c6 2046 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2047
c2c75131
DV		 2048 if (INTEL_INFO(dev)->gen >= 4) {
2049 intel_crtc->dspaddr_offset =
bc752862
CW		 2050 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2051 fb->bits_per_pixel / 8,
2052 fb->pitches[0]);
c2c75131
DV		 2053 linear_offset -= intel_crtc->dspaddr_offset;
2054 } else {
e506a0c6 2055 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2056 }
e506a0c6
DV		 2057
2058 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2059 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2060 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2061 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2062 I915_MODIFY_DISPBASE(DSPSURF(plane),
2063 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2064 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2065 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2066 } else
e506a0c6 2067 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2068 POSTING_READ(reg);
81255565 2069
17638cd6
JB		 2070 return 0;
2071}
2072
2073static int ironlake_update_plane(struct drm_crtc *crtc,
2074 struct drm_framebuffer *fb, int x, int y)
2075{
2076 struct drm_device *dev = crtc->dev;
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2079 struct intel_framebuffer *intel_fb;
2080 struct drm_i915_gem_object *obj;
2081 int plane = intel_crtc->plane;
e506a0c6 2082 unsigned long linear_offset;
17638cd6
JB		 2083 u32 dspcntr;
2084 u32 reg;
2085
2086 switch (plane) {
2087 case 0:
2088 case 1:
27f8227b 2089 case 2:
17638cd6
JB		 2090 break;
2091 default:
84f44ce7 2092 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2093 return -EINVAL;
2094 }
2095
2096 intel_fb = to_intel_framebuffer(fb);
2097 obj = intel_fb->obj;
2098
2099 reg = DSPCNTR(plane);
2100 dspcntr = I915_READ(reg);
2101 /* Mask out pixel format bits in case we change it */
2102 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2103 switch (fb->pixel_format) {
2104 case DRM_FORMAT_C8:
17638cd6
JB		 2105 dspcntr |= DISPPLANE_8BPP;
2106 break;
57779d06
VS		 2107 case DRM_FORMAT_RGB565:
2108 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2109 break;
57779d06
VS		 2110 case DRM_FORMAT_XRGB8888:
2111 case DRM_FORMAT_ARGB8888:
2112 dspcntr |= DISPPLANE_BGRX888;
2113 break;
2114 case DRM_FORMAT_XBGR8888:
2115 case DRM_FORMAT_ABGR8888:
2116 dspcntr |= DISPPLANE_RGBX888;
2117 break;
2118 case DRM_FORMAT_XRGB2101010:
2119 case DRM_FORMAT_ARGB2101010:
2120 dspcntr |= DISPPLANE_BGRX101010;
2121 break;
2122 case DRM_FORMAT_XBGR2101010:
2123 case DRM_FORMAT_ABGR2101010:
2124 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2125 break;
2126 default:
baba133a 2127 BUG();
17638cd6
JB		 2128 }
2129
2130 if (obj->tiling_mode != I915_TILING_NONE)
2131 dspcntr |= DISPPLANE_TILED;
2132 else
2133 dspcntr &= ~DISPPLANE_TILED;
2134
2135 /* must disable */
2136 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2137
2138 I915_WRITE(reg, dspcntr);
2139
e506a0c6 2140 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2141 intel_crtc->dspaddr_offset =
bc752862
CW		 2142 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2143 fb->bits_per_pixel / 8,
2144 fb->pitches[0]);
c2c75131 2145 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2146
e506a0c6
DV		 2147 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2148 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2149 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2150 I915_MODIFY_DISPBASE(DSPSURF(plane),
2151 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2152 if (IS_HASWELL(dev)) {
2153 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2154 } else {
2155 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2156 I915_WRITE(DSPLINOFF(plane), linear_offset);
2157 }
17638cd6
JB		 2158 POSTING_READ(reg);
2159
2160 return 0;
2161}
2162
2163/* Assume fb object is pinned & idle & fenced and just update base pointers */
2164static int
2165intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2166 int x, int y, enum mode_set_atomic state)
2167{
2168 struct drm_device *dev = crtc->dev;
2169 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2170
6b8e6ed0
CW		 2171 if (dev_priv->display.disable_fbc)
2172 dev_priv->display.disable_fbc(dev);
3dec0095 2173 intel_increase_pllclock(crtc);
81255565 2174
6b8e6ed0 2175 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2176}
2177
96a02917
VS		 2178void intel_display_handle_reset(struct drm_device *dev)
2179{
2180 struct drm_i915_private *dev_priv = dev->dev_private;
2181 struct drm_crtc *crtc;
2182
2183 /*
2184 * Flips in the rings have been nuked by the reset,
2185 * so complete all pending flips so that user space
2186 * will get its events and not get stuck.
2187 *
2188 * Also update the base address of all primary
2189 * planes to the the last fb to make sure we're
2190 * showing the correct fb after a reset.
2191 *
2192 * Need to make two loops over the crtcs so that we
2193 * don't try to grab a crtc mutex before the
2194 * pending_flip_queue really got woken up.
2195 */
2196
2197 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2199 enum plane plane = intel_crtc->plane;
2200
2201 intel_prepare_page_flip(dev, plane);
2202 intel_finish_page_flip_plane(dev, plane);
2203 }
2204
2205 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2207
2208 mutex_lock(&crtc->mutex);
2209 if (intel_crtc->active)
2210 dev_priv->display.update_plane(crtc, crtc->fb,
2211 crtc->x, crtc->y);
2212 mutex_unlock(&crtc->mutex);
2213 }
2214}
2215
14667a4b
CW		 2216static int
2217intel_finish_fb(struct drm_framebuffer *old_fb)
2218{
2219 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2220 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2221 bool was_interruptible = dev_priv->mm.interruptible;
2222 int ret;
2223
14667a4b
CW		 2224 /* Big Hammer, we also need to ensure that any pending
2225 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2226 * current scanout is retired before unpinning the old
2227 * framebuffer.
2228 *
2229 * This should only fail upon a hung GPU, in which case we
2230 * can safely continue.
2231 */
2232 dev_priv->mm.interruptible = false;
2233 ret = i915_gem_object_finish_gpu(obj);
2234 dev_priv->mm.interruptible = was_interruptible;
2235
2236 return ret;
2237}
2238
198598d0
VS		 2239static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2240{
2241 struct drm_device *dev = crtc->dev;
2242 struct drm_i915_master_private *master_priv;
2243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2244
2245 if (!dev->primary->master)
2246 return;
2247
2248 master_priv = dev->primary->master->driver_priv;
2249 if (!master_priv->sarea_priv)
2250 return;
2251
2252 switch (intel_crtc->pipe) {
2253 case 0:
2254 master_priv->sarea_priv->pipeA_x = x;
2255 master_priv->sarea_priv->pipeA_y = y;
2256 break;
2257 case 1:
2258 master_priv->sarea_priv->pipeB_x = x;
2259 master_priv->sarea_priv->pipeB_y = y;
2260 break;
2261 default:
2262 break;
2263 }
2264}
2265
5c3b82e2 2266static int
3c4fdcfb 2267intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2268 struct drm_framebuffer *fb)
79e53945
JB		 2269{
2270 struct drm_device *dev = crtc->dev;
6b8e6ed0 2271 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2273 struct drm_framebuffer *old_fb;
5c3b82e2 2274 int ret;
79e53945
JB		 2275
2276 /* no fb bound */
94352cf9 2277 if (!fb) {
a5071c2f 2278 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2279 return 0;
2280 }
2281
7eb552ae 2282 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2283 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2284 plane_name(intel_crtc->plane),
2285 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2286 return -EINVAL;
79e53945
JB		 2287 }
2288
5c3b82e2 2289 mutex_lock(&dev->struct_mutex);
265db958 2290 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2291 to_intel_framebuffer(fb)->obj,
919926ae 2292 NULL);
5c3b82e2
CW		 2293 if (ret != 0) {
2294 mutex_unlock(&dev->struct_mutex);
a5071c2f 2295 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2296 return ret;
2297 }
79e53945 2298
94352cf9 2299 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2300 if (ret) {
94352cf9 2301 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2302 mutex_unlock(&dev->struct_mutex);
a5071c2f 2303 DRM_ERROR("failed to update base address\n");
4e6cfefc 2304 return ret;
79e53945 2305 }
3c4fdcfb 2306
94352cf9
DV		 2307 old_fb = crtc->fb;
2308 crtc->fb = fb;
6c4c86f5
DV		 2309 crtc->x = x;
2310 crtc->y = y;
94352cf9 2311
b7f1de28
CW		 2312 if (old_fb) {
2313 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2314 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2315 }
652c393a 2316
6b8e6ed0 2317 intel_update_fbc(dev);
5c3b82e2 2318 mutex_unlock(&dev->struct_mutex);
79e53945 2319
198598d0 2320 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2321
2322 return 0;
79e53945
JB		 2323}
2324
5e84e1a4
ZW		 2325static void intel_fdi_normal_train(struct drm_crtc *crtc)
2326{
2327 struct drm_device *dev = crtc->dev;
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2330 int pipe = intel_crtc->pipe;
2331 u32 reg, temp;
2332
2333 /* enable normal train */
2334 reg = FDI_TX_CTL(pipe);
2335 temp = I915_READ(reg);
61e499bf 2336 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2337 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2338 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2339 } else {
2340 temp &= ~FDI_LINK_TRAIN_NONE;
2341 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2342 }
5e84e1a4
ZW		 2343 I915_WRITE(reg, temp);
2344
2345 reg = FDI_RX_CTL(pipe);
2346 temp = I915_READ(reg);
2347 if (HAS_PCH_CPT(dev)) {
2348 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2349 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2350 } else {
2351 temp &= ~FDI_LINK_TRAIN_NONE;
2352 temp |= FDI_LINK_TRAIN_NONE;
2353 }
2354 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2355
2356 /* wait one idle pattern time */
2357 POSTING_READ(reg);
2358 udelay(1000);
357555c0
JB		 2359
2360 /* IVB wants error correction enabled */
2361 if (IS_IVYBRIDGE(dev))
2362 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2363 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2364}
2365
1e833f40
DV		 2366static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2367{
2368 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2369}
2370
01a415fd
DV		 2371static void ivb_modeset_global_resources(struct drm_device *dev)
2372{
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 struct intel_crtc *pipe_B_crtc =
2375 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2376 struct intel_crtc *pipe_C_crtc =
2377 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2378 uint32_t temp;
2379
1e833f40
DV		 2380 /*
2381 * When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. Note that we don't care about enabled pipes without
2383 * an enabled pch encoder.
2384 */
2385 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2386 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2387 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2388 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2389
2390 temp = I915_READ(SOUTH_CHICKEN1);
2391 temp &= ~FDI_BC_BIFURCATION_SELECT;
2392 DRM_DEBUG_KMS("disabling fdi C rx\n");
2393 I915_WRITE(SOUTH_CHICKEN1, temp);
2394 }
2395}
2396
8db9d77b
ZW		 2397/* The FDI link training functions for ILK/Ibexpeak. */
2398static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2399{
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
0fc932b8 2404 int plane = intel_crtc->plane;
5eddb70b 2405 u32 reg, temp, tries;
8db9d77b 2406
0fc932b8
JB		 2407 /* FDI needs bits from pipe & plane first */
2408 assert_pipe_enabled(dev_priv, pipe);
2409 assert_plane_enabled(dev_priv, plane);
2410
e1a44743
AJ		 2411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2412 for train result */
5eddb70b
CW		 2413 reg = FDI_RX_IMR(pipe);
2414 temp = I915_READ(reg);
e1a44743
AJ		 2415 temp &= ~FDI_RX_SYMBOL_LOCK;
2416 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2417 I915_WRITE(reg, temp);
2418 I915_READ(reg);
e1a44743
AJ		 2419 udelay(150);
2420
8db9d77b 2421 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2422 reg = FDI_TX_CTL(pipe);
2423 temp = I915_READ(reg);
627eb5a3
DV		 2424 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2425 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2428 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2429
5eddb70b
CW		 2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2434 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2435
2436 POSTING_READ(reg);
8db9d77b
ZW		 2437 udelay(150);
2438
5b2adf89 2439 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2440 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2441 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2442 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2443
5eddb70b 2444 reg = FDI_RX_IIR(pipe);
e1a44743 2445 for (tries = 0; tries < 5; tries++) {
5eddb70b 2446 temp = I915_READ(reg);
8db9d77b
ZW		 2447 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2448
2449 if ((temp & FDI_RX_BIT_LOCK)) {
2450 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2451 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2452 break;
2453 }
8db9d77b 2454 }
e1a44743 2455 if (tries == 5)
5eddb70b 2456 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2457
2458 /* Train 2 */
5eddb70b
CW		 2459 reg = FDI_TX_CTL(pipe);
2460 temp = I915_READ(reg);
8db9d77b
ZW		 2461 temp &= ~FDI_LINK_TRAIN_NONE;
2462 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2463 I915_WRITE(reg, temp);
8db9d77b 2464
5eddb70b
CW		 2465 reg = FDI_RX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 POSTING_READ(reg);
2472 udelay(150);
8db9d77b 2473
5eddb70b 2474 reg = FDI_RX_IIR(pipe);
e1a44743 2475 for (tries = 0; tries < 5; tries++) {
5eddb70b 2476 temp = I915_READ(reg);
8db9d77b
ZW		 2477 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2478
2479 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2480 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2481 DRM_DEBUG_KMS("FDI train 2 done.\n");
2482 break;
2483 }
8db9d77b 2484 }
e1a44743 2485 if (tries == 5)
5eddb70b 2486 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2487
2488 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2489
8db9d77b
ZW		 2490}
2491
0206e353 2492static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2493 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2494 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2495 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2496 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2497};
2498
2499/* The FDI link training functions for SNB/Cougarpoint. */
2500static void gen6_fdi_link_train(struct drm_crtc *crtc)
2501{
2502 struct drm_device *dev = crtc->dev;
2503 struct drm_i915_private *dev_priv = dev->dev_private;
2504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2505 int pipe = intel_crtc->pipe;
fa37d39e 2506 u32 reg, temp, i, retry;
8db9d77b 2507
e1a44743
AJ		 2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2509 for train result */
5eddb70b
CW		 2510 reg = FDI_RX_IMR(pipe);
2511 temp = I915_READ(reg);
e1a44743
AJ		 2512 temp &= ~FDI_RX_SYMBOL_LOCK;
2513 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
e1a44743
AJ		 2517 udelay(150);
2518
8db9d77b 2519 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
627eb5a3
DV		 2522 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2523 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2524 temp &= ~FDI_LINK_TRAIN_NONE;
2525 temp |= FDI_LINK_TRAIN_PATTERN_1;
2526 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2527 /* SNB-B */
2528 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2529 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2530
d74cf324
DV		 2531 I915_WRITE(FDI_RX_MISC(pipe),
2532 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2533
5eddb70b
CW		 2534 reg = FDI_RX_CTL(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 if (HAS_PCH_CPT(dev)) {
2537 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2538 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2539 } else {
2540 temp &= ~FDI_LINK_TRAIN_NONE;
2541 temp |= FDI_LINK_TRAIN_PATTERN_1;
2542 }
5eddb70b
CW		 2543 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2544
2545 POSTING_READ(reg);
8db9d77b
ZW		 2546 udelay(150);
2547
0206e353 2548 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2549 reg = FDI_TX_CTL(pipe);
2550 temp = I915_READ(reg);
8db9d77b
ZW		 2551 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2552 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2553 I915_WRITE(reg, temp);
2554
2555 POSTING_READ(reg);
8db9d77b
ZW		 2556 udelay(500);
2557
fa37d39e
SP		 2558 for (retry = 0; retry < 5; retry++) {
2559 reg = FDI_RX_IIR(pipe);
2560 temp = I915_READ(reg);
2561 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2562 if (temp & FDI_RX_BIT_LOCK) {
2563 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2564 DRM_DEBUG_KMS("FDI train 1 done.\n");
2565 break;
2566 }
2567 udelay(50);
8db9d77b 2568 }
fa37d39e
SP		 2569 if (retry < 5)
2570 break;
8db9d77b
ZW		 2571 }
2572 if (i == 4)
5eddb70b 2573 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2574
2575 /* Train 2 */
5eddb70b
CW		 2576 reg = FDI_TX_CTL(pipe);
2577 temp = I915_READ(reg);
8db9d77b
ZW		 2578 temp &= ~FDI_LINK_TRAIN_NONE;
2579 temp |= FDI_LINK_TRAIN_PATTERN_2;
2580 if (IS_GEN6(dev)) {
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 /* SNB-B */
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2584 }
5eddb70b 2585 I915_WRITE(reg, temp);
8db9d77b 2586
5eddb70b
CW		 2587 reg = FDI_RX_CTL(pipe);
2588 temp = I915_READ(reg);
8db9d77b
ZW		 2589 if (HAS_PCH_CPT(dev)) {
2590 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2591 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2592 } else {
2593 temp &= ~FDI_LINK_TRAIN_NONE;
2594 temp |= FDI_LINK_TRAIN_PATTERN_2;
2595 }
5eddb70b
CW		 2596 I915_WRITE(reg, temp);
2597
2598 POSTING_READ(reg);
8db9d77b
ZW		 2599 udelay(150);
2600
0206e353 2601 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2602 reg = FDI_TX_CTL(pipe);
2603 temp = I915_READ(reg);
8db9d77b
ZW		 2604 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2605 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2606 I915_WRITE(reg, temp);
2607
2608 POSTING_READ(reg);
8db9d77b
ZW		 2609 udelay(500);
2610
fa37d39e
SP		 2611 for (retry = 0; retry < 5; retry++) {
2612 reg = FDI_RX_IIR(pipe);
2613 temp = I915_READ(reg);
2614 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2615 if (temp & FDI_RX_SYMBOL_LOCK) {
2616 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2617 DRM_DEBUG_KMS("FDI train 2 done.\n");
2618 break;
2619 }
2620 udelay(50);
8db9d77b 2621 }
fa37d39e
SP		 2622 if (retry < 5)
2623 break;
8db9d77b
ZW		 2624 }
2625 if (i == 4)
5eddb70b 2626 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2627
2628 DRM_DEBUG_KMS("FDI train done.\n");
2629}
2630
357555c0
JB		 2631/* Manual link training for Ivy Bridge A0 parts */
2632static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2633{
2634 struct drm_device *dev = crtc->dev;
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2637 int pipe = intel_crtc->pipe;
2638 u32 reg, temp, i;
2639
2640 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2641 for train result */
2642 reg = FDI_RX_IMR(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~FDI_RX_SYMBOL_LOCK;
2645 temp &= ~FDI_RX_BIT_LOCK;
2646 I915_WRITE(reg, temp);
2647
2648 POSTING_READ(reg);
2649 udelay(150);
2650
01a415fd
DV		 2651 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2652 I915_READ(FDI_RX_IIR(pipe)));
2653
357555c0
JB		 2654 /* enable CPU FDI TX and PCH FDI RX */
2655 reg = FDI_TX_CTL(pipe);
2656 temp = I915_READ(reg);
627eb5a3
DV		 2657 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2658 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2659 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2660 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2661 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2662 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2663 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2664 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2665
d74cf324
DV		 2666 I915_WRITE(FDI_RX_MISC(pipe),
2667 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2668
357555c0
JB		 2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2674 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2675 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2676
2677 POSTING_READ(reg);
2678 udelay(150);
2679
0206e353 2680 for (i = 0; i < 4; i++) {
357555c0
JB		 2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2684 temp |= snb_b_fdi_train_param[i];
2685 I915_WRITE(reg, temp);
2686
2687 POSTING_READ(reg);
2688 udelay(500);
2689
2690 reg = FDI_RX_IIR(pipe);
2691 temp = I915_READ(reg);
2692 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2693
2694 if (temp & FDI_RX_BIT_LOCK ||
2695 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2696 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2697 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2698 break;
2699 }
2700 }
2701 if (i == 4)
2702 DRM_ERROR("FDI train 1 fail!\n");
2703
2704 /* Train 2 */
2705 reg = FDI_TX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2708 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2709 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2710 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2711 I915_WRITE(reg, temp);
2712
2713 reg = FDI_RX_CTL(pipe);
2714 temp = I915_READ(reg);
2715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2717 I915_WRITE(reg, temp);
2718
2719 POSTING_READ(reg);
2720 udelay(150);
2721
0206e353 2722 for (i = 0; i < 4; i++) {
357555c0
JB		 2723 reg = FDI_TX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= snb_b_fdi_train_param[i];
2727 I915_WRITE(reg, temp);
2728
2729 POSTING_READ(reg);
2730 udelay(500);
2731
2732 reg = FDI_RX_IIR(pipe);
2733 temp = I915_READ(reg);
2734 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2735
2736 if (temp & FDI_RX_SYMBOL_LOCK) {
2737 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2738 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2739 break;
2740 }
2741 }
2742 if (i == 4)
2743 DRM_ERROR("FDI train 2 fail!\n");
2744
2745 DRM_DEBUG_KMS("FDI train done.\n");
2746}
2747
88cefb6c 2748static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2749{
88cefb6c 2750 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2751 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2752 int pipe = intel_crtc->pipe;
5eddb70b 2753 u32 reg, temp;
79e53945 2754
c64e311e 2755
c98e9dcf 2756 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2757 reg = FDI_RX_CTL(pipe);
2758 temp = I915_READ(reg);
627eb5a3
DV		 2759 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2760 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2761 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2762 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2763
2764 POSTING_READ(reg);
c98e9dcf
JB		 2765 udelay(200);
2766
2767 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2768 temp = I915_READ(reg);
2769 I915_WRITE(reg, temp | FDI_PCDCLK);
2770
2771 POSTING_READ(reg);
c98e9dcf
JB		 2772 udelay(200);
2773
20749730
PZ		 2774 /* Enable CPU FDI TX PLL, always on for Ironlake */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2778 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2779
20749730
PZ		 2780 POSTING_READ(reg);
2781 udelay(100);
6be4a607 2782 }
0e23b99d
JB		 2783}
2784
88cefb6c
DV		 2785static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2786{
2787 struct drm_device *dev = intel_crtc->base.dev;
2788 struct drm_i915_private *dev_priv = dev->dev_private;
2789 int pipe = intel_crtc->pipe;
2790 u32 reg, temp;
2791
2792 /* Switch from PCDclk to Rawclk */
2793 reg = FDI_RX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2796
2797 /* Disable CPU FDI TX PLL */
2798 reg = FDI_TX_CTL(pipe);
2799 temp = I915_READ(reg);
2800 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2801
2802 POSTING_READ(reg);
2803 udelay(100);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2808
2809 /* Wait for the clocks to turn off. */
2810 POSTING_READ(reg);
2811 udelay(100);
2812}
2813
0fc932b8
JB		 2814static void ironlake_fdi_disable(struct drm_crtc *crtc)
2815{
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int pipe = intel_crtc->pipe;
2820 u32 reg, temp;
2821
2822 /* disable CPU FDI tx and PCH FDI rx */
2823 reg = FDI_TX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2826 POSTING_READ(reg);
2827
2828 reg = FDI_RX_CTL(pipe);
2829 temp = I915_READ(reg);
2830 temp &= ~(0x7 << 16);
dfd07d72 2831 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2832 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2833
2834 POSTING_READ(reg);
2835 udelay(100);
2836
2837 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2838 if (HAS_PCH_IBX(dev)) {
2839 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2840 }
0fc932b8
JB		 2841
2842 /* still set train pattern 1 */
2843 reg = FDI_TX_CTL(pipe);
2844 temp = I915_READ(reg);
2845 temp &= ~FDI_LINK_TRAIN_NONE;
2846 temp |= FDI_LINK_TRAIN_PATTERN_1;
2847 I915_WRITE(reg, temp);
2848
2849 reg = FDI_RX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 if (HAS_PCH_CPT(dev)) {
2852 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2853 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2854 } else {
2855 temp &= ~FDI_LINK_TRAIN_NONE;
2856 temp |= FDI_LINK_TRAIN_PATTERN_1;
2857 }
2858 /* BPC in FDI rx is consistent with that in PIPECONF */
2859 temp &= ~(0x07 << 16);
dfd07d72 2860 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2861 I915_WRITE(reg, temp);
2862
2863 POSTING_READ(reg);
2864 udelay(100);
2865}
2866
5bb61643
CW		 2867static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2868{
2869 struct drm_device *dev = crtc->dev;
2870 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2872 unsigned long flags;
2873 bool pending;
2874
10d83730
VS		 2875 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2876 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2877 return false;
2878
2879 spin_lock_irqsave(&dev->event_lock, flags);
2880 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2881 spin_unlock_irqrestore(&dev->event_lock, flags);
2882
2883 return pending;
2884}
2885
e6c3a2a6
CW		 2886static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2887{
0f91128d 2888 struct drm_device *dev = crtc->dev;
5bb61643 2889 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2890
2891 if (crtc->fb == NULL)
2892 return;
2893
2c10d571
DV		 2894 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2895
5bb61643
CW		 2896 wait_event(dev_priv->pending_flip_queue,
2897 !intel_crtc_has_pending_flip(crtc));
2898
0f91128d
CW		 2899 mutex_lock(&dev->struct_mutex);
2900 intel_finish_fb(crtc->fb);
2901 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2902}
2903
e615efe4
ED		 2904/* Program iCLKIP clock to the desired frequency */
2905static void lpt_program_iclkip(struct drm_crtc *crtc)
2906{
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 u32 temp;
2911
09153000
DV		 2912 mutex_lock(&dev_priv->dpio_lock);
2913
e615efe4
ED		 2914 /* It is necessary to ungate the pixclk gate prior to programming
2915 * the divisors, and gate it back when it is done.
2916 */
2917 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2918
2919 /* Disable SSCCTL */
2920 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2921 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2922 SBI_SSCCTL_DISABLE,
2923 SBI_ICLK);
e615efe4
ED		 2924
2925 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2926 if (crtc->mode.clock == 20000) {
2927 auxdiv = 1;
2928 divsel = 0x41;
2929 phaseinc = 0x20;
2930 } else {
2931 /* The iCLK virtual clock root frequency is in MHz,
2932 * but the crtc->mode.clock in in KHz. To get the divisors,
2933 * it is necessary to divide one by another, so we
2934 * convert the virtual clock precision to KHz here for higher
2935 * precision.
2936 */
2937 u32 iclk_virtual_root_freq = 172800 * 1000;
2938 u32 iclk_pi_range = 64;
2939 u32 desired_divisor, msb_divisor_value, pi_value;
2940
2941 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2942 msb_divisor_value = desired_divisor / iclk_pi_range;
2943 pi_value = desired_divisor % iclk_pi_range;
2944
2945 auxdiv = 0;
2946 divsel = msb_divisor_value - 2;
2947 phaseinc = pi_value;
2948 }
2949
2950 /* This should not happen with any sane values */
2951 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2952 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2953 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2954 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2955
2956 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2957 crtc->mode.clock,
2958 auxdiv,
2959 divsel,
2960 phasedir,
2961 phaseinc);
2962
2963 /* Program SSCDIVINTPHASE6 */
988d6ee8 2964 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2965 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2966 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2967 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2968 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2969 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2970 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2971 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2972
2973 /* Program SSCAUXDIV */
988d6ee8 2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2977 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2978
2979 /* Enable modulator and associated divider */
988d6ee8 2980 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2981 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2982 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2983
2984 /* Wait for initialization time */
2985 udelay(24);
2986
2987 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2988
2989 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2990}
2991
275f01b2
DV		 2992static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2993 enum pipe pch_transcoder)
2994{
2995 struct drm_device *dev = crtc->base.dev;
2996 struct drm_i915_private *dev_priv = dev->dev_private;
2997 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2998
2999 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3000 I915_READ(HTOTAL(cpu_transcoder)));
3001 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3002 I915_READ(HBLANK(cpu_transcoder)));
3003 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3004 I915_READ(HSYNC(cpu_transcoder)));
3005
3006 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3007 I915_READ(VTOTAL(cpu_transcoder)));
3008 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3009 I915_READ(VBLANK(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3011 I915_READ(VSYNC(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3013 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3014}
3015
f67a559d
JB		 3016/*
3017 * Enable PCH resources required for PCH ports:
3018 * - PCH PLLs
3019 * - FDI training & RX/TX
3020 * - update transcoder timings
3021 * - DP transcoding bits
3022 * - transcoder
3023 */
3024static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3025{
3026 struct drm_device *dev = crtc->dev;
3027 struct drm_i915_private *dev_priv = dev->dev_private;
3028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3029 int pipe = intel_crtc->pipe;
ee7b9f93 3030 u32 reg, temp;
2c07245f 3031
ab9412ba 3032 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3033
cd986abb
DV		 3034 /* Write the TU size bits before fdi link training, so that error
3035 * detection works. */
3036 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3037 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3038
c98e9dcf 3039 /* For PCH output, training FDI link */
674cf967 3040 dev_priv->display.fdi_link_train(crtc);
2c07245f 3041
572deb37
DV		 3042 /* XXX: pch pll's can be enabled any time before we enable the PCH
3043 * transcoder, and we actually should do this to not upset any PCH
3044 * transcoder that already use the clock when we share it.
3045 *
3046 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3047 * unconditionally resets the pll - we need that to have the right LVDS
3048 * enable sequence. */
b6b4e185 3049 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3050
303b81e0 3051 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3052 u32 sel;
4b645f14 3053
c98e9dcf 3054 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3055 switch (pipe) {
3056 default:
3057 case 0:
3058 temp |= TRANSA_DPLL_ENABLE;
3059 sel = TRANSA_DPLLB_SEL;
3060 break;
3061 case 1:
3062 temp |= TRANSB_DPLL_ENABLE;
3063 sel = TRANSB_DPLLB_SEL;
3064 break;
3065 case 2:
3066 temp |= TRANSC_DPLL_ENABLE;
3067 sel = TRANSC_DPLLB_SEL;
3068 break;
d64311ab 3069 }
ee7b9f93
JB		 3070 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3071 temp |= sel;
3072 else
3073 temp &= ~sel;
c98e9dcf 3074 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3075 }
5eddb70b 3076
d9b6cb56
JB		 3077 /* set transcoder timing, panel must allow it */
3078 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3079 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3080
303b81e0 3081 intel_fdi_normal_train(crtc);
5e84e1a4 3082
c98e9dcf
JB		 3083 /* For PCH DP, enable TRANS_DP_CTL */
3084 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3085 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3086 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3087 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3088 reg = TRANS_DP_CTL(pipe);
3089 temp = I915_READ(reg);
3090 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3091 TRANS_DP_SYNC_MASK |
3092 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3093 temp |= (TRANS_DP_OUTPUT_ENABLE |
3094 TRANS_DP_ENH_FRAMING);
9325c9f0 3095 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3096
3097 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3098 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3099 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3100 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3101
3102 switch (intel_trans_dp_port_sel(crtc)) {
3103 case PCH_DP_B:
5eddb70b 3104 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3105 break;
3106 case PCH_DP_C:
5eddb70b 3107 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3108 break;
3109 case PCH_DP_D:
5eddb70b 3110 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3111 break;
3112 default:
e95d41e1 3113 BUG();
32f9d658 3114 }
2c07245f 3115
5eddb70b 3116 I915_WRITE(reg, temp);
6be4a607 3117 }
b52eb4dc 3118
b8a4f404 3119 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3120}
3121
1507e5bd
PZ		 3122static void lpt_pch_enable(struct drm_crtc *crtc)
3123{
3124 struct drm_device *dev = crtc->dev;
3125 struct drm_i915_private *dev_priv = dev->dev_private;
3126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3127 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3128
ab9412ba 3129 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3130
8c52b5e8 3131 lpt_program_iclkip(crtc);
1507e5bd 3132
0540e488 3133 /* Set transcoder timing. */
275f01b2 3134 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3135
937bb610 3136 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3137}
3138
ee7b9f93
JB		 3139static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3140{
3141 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3142
3143 if (pll == NULL)
3144 return;
3145
3146 if (pll->refcount == 0) {
3147 WARN(1, "bad PCH PLL refcount\n");
3148 return;
3149 }
3150
3151 --pll->refcount;
3152 intel_crtc->pch_pll = NULL;
3153}
3154
3155static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3156{
3157 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3158 struct intel_pch_pll *pll;
3159 int i;
3160
3161 pll = intel_crtc->pch_pll;
3162 if (pll) {
3163 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto prepare;
3166 }
3167
98b6bd99
DV		 3168 if (HAS_PCH_IBX(dev_priv->dev)) {
3169 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3170 i = intel_crtc->pipe;
3171 pll = &dev_priv->pch_plls[i];
3172
3173 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3174 intel_crtc->base.base.id, pll->pll_reg);
3175
3176 goto found;
3177 }
3178
ee7b9f93
JB		 3179 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3180 pll = &dev_priv->pch_plls[i];
3181
3182 /* Only want to check enabled timings first */
3183 if (pll->refcount == 0)
3184 continue;
3185
3186 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3187 fp == I915_READ(pll->fp0_reg)) {
3188 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3189 intel_crtc->base.base.id,
3190 pll->pll_reg, pll->refcount, pll->active);
3191
3192 goto found;
3193 }
3194 }
3195
3196 /* Ok no matching timings, maybe there's a free one? */
3197 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3198 pll = &dev_priv->pch_plls[i];
3199 if (pll->refcount == 0) {
3200 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3201 intel_crtc->base.base.id, pll->pll_reg);
3202 goto found;
3203 }
3204 }
3205
3206 return NULL;
3207
3208found:
3209 intel_crtc->pch_pll = pll;
3210 pll->refcount++;
84f44ce7 3211 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3212prepare: /* separate function? */
3213 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3214
e04c7350
CW		 3215 /* Wait for the clocks to stabilize before rewriting the regs */
3216 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3217 POSTING_READ(pll->pll_reg);
3218 udelay(150);
e04c7350
CW		 3219
3220 I915_WRITE(pll->fp0_reg, fp);
3221 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3222 pll->on = false;
3223 return pll;
3224}
3225
a1520318 3226static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3227{
3228 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3229 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3230 u32 temp;
3231
3232 temp = I915_READ(dslreg);
3233 udelay(500);
3234 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3235 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3236 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3237 }
3238}
3239
b074cec8
JB		 3240static void ironlake_pfit_enable(struct intel_crtc *crtc)
3241{
3242 struct drm_device *dev = crtc->base.dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 int pipe = crtc->pipe;
3245
0ef37f3f 3246 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3247 /* Force use of hard-coded filter coefficients
3248 * as some pre-programmed values are broken,
3249 * e.g. x201.
3250 */
3251 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3252 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3253 PF_PIPE_SEL_IVB(pipe));
3254 else
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3256 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3257 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3258 }
3259}
3260
f67a559d
JB		 3261static void ironlake_crtc_enable(struct drm_crtc *crtc)
3262{
3263 struct drm_device *dev = crtc->dev;
3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3266 struct intel_encoder *encoder;
f67a559d
JB		 3267 int pipe = intel_crtc->pipe;
3268 int plane = intel_crtc->plane;
3269 u32 temp;
f67a559d 3270
08a48469
DV		 3271 WARN_ON(!crtc->enabled);
3272
f67a559d
JB		 3273 if (intel_crtc->active)
3274 return;
3275
3276 intel_crtc->active = true;
8664281b
PZ		 3277
3278 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3279 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3280
f67a559d
JB		 3281 intel_update_watermarks(dev);
3282
3283 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3284 temp = I915_READ(PCH_LVDS);
3285 if ((temp & LVDS_PORT_EN) == 0)
3286 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3287 }
3288
f67a559d 3289
5bfe2ac0 3290 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3291 /* Note: FDI PLL enabling _must_ be done before we enable the
3292 * cpu pipes, hence this is separate from all the other fdi/pch
3293 * enabling. */
88cefb6c 3294 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3295 } else {
3296 assert_fdi_tx_disabled(dev_priv, pipe);
3297 assert_fdi_rx_disabled(dev_priv, pipe);
3298 }
f67a559d 3299
bf49ec8c
DV		 3300 for_each_encoder_on_crtc(dev, crtc, encoder)
3301 if (encoder->pre_enable)
3302 encoder->pre_enable(encoder);
f67a559d
JB		 3303
3304 /* Enable panel fitting for LVDS */
b074cec8 3305 ironlake_pfit_enable(intel_crtc);
f67a559d 3306
9c54c0dd
JB		 3307 /*
3308 * On ILK+ LUT must be loaded before the pipe is running but with
3309 * clocks enabled
3310 */
3311 intel_crtc_load_lut(crtc);
3312
5bfe2ac0
DV		 3313 intel_enable_pipe(dev_priv, pipe,
3314 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3315 intel_enable_plane(dev_priv, plane, pipe);
3316
5bfe2ac0 3317 if (intel_crtc->config.has_pch_encoder)
f67a559d 3318 ironlake_pch_enable(crtc);
c98e9dcf 3319
d1ebd816 3320 mutex_lock(&dev->struct_mutex);
bed4a673 3321 intel_update_fbc(dev);
d1ebd816
BW		 3322 mutex_unlock(&dev->struct_mutex);
3323
6b383a7f 3324 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3325
fa5c73b1
DV		 3326 for_each_encoder_on_crtc(dev, crtc, encoder)
3327 encoder->enable(encoder);
61b77ddd
DV		 3328
3329 if (HAS_PCH_CPT(dev))
a1520318 3330 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3331
3332 /*
3333 * There seems to be a race in PCH platform hw (at least on some
3334 * outputs) where an enabled pipe still completes any pageflip right
3335 * away (as if the pipe is off) instead of waiting for vblank. As soon
3336 * as the first vblank happend, everything works as expected. Hence just
3337 * wait for one vblank before returning to avoid strange things
3338 * happening.
3339 */
3340 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3341}
3342
4f771f10
PZ		 3343static void haswell_crtc_enable(struct drm_crtc *crtc)
3344{
3345 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348 struct intel_encoder *encoder;
3349 int pipe = intel_crtc->pipe;
3350 int plane = intel_crtc->plane;
4f771f10
PZ		 3351
3352 WARN_ON(!crtc->enabled);
3353
3354 if (intel_crtc->active)
3355 return;
3356
3357 intel_crtc->active = true;
8664281b
PZ		 3358
3359 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3360 if (intel_crtc->config.has_pch_encoder)
3361 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3362
4f771f10
PZ		 3363 intel_update_watermarks(dev);
3364
5bfe2ac0 3365 if (intel_crtc->config.has_pch_encoder)
04945641 3366 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3367
3368 for_each_encoder_on_crtc(dev, crtc, encoder)
3369 if (encoder->pre_enable)
3370 encoder->pre_enable(encoder);
3371
1f544388 3372 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3373
1f544388 3374 /* Enable panel fitting for eDP */
b074cec8 3375 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3376
3377 /*
3378 * On ILK+ LUT must be loaded before the pipe is running but with
3379 * clocks enabled
3380 */
3381 intel_crtc_load_lut(crtc);
3382
1f544388 3383 intel_ddi_set_pipe_settings(crtc);
8228c251 3384 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3385
5bfe2ac0
DV		 3386 intel_enable_pipe(dev_priv, pipe,
3387 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3388 intel_enable_plane(dev_priv, plane, pipe);
3389
5bfe2ac0 3390 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3391 lpt_pch_enable(crtc);
4f771f10
PZ		 3392
3393 mutex_lock(&dev->struct_mutex);
3394 intel_update_fbc(dev);
3395 mutex_unlock(&dev->struct_mutex);
3396
3397 intel_crtc_update_cursor(crtc, true);
3398
3399 for_each_encoder_on_crtc(dev, crtc, encoder)
3400 encoder->enable(encoder);
3401
4f771f10
PZ		 3402 /*
3403 * There seems to be a race in PCH platform hw (at least on some
3404 * outputs) where an enabled pipe still completes any pageflip right
3405 * away (as if the pipe is off) instead of waiting for vblank. As soon
3406 * as the first vblank happend, everything works as expected. Hence just
3407 * wait for one vblank before returning to avoid strange things
3408 * happening.
3409 */
3410 intel_wait_for_vblank(dev, intel_crtc->pipe);
3411}
3412
3f8dce3a
DV		 3413static void ironlake_pfit_disable(struct intel_crtc *crtc)
3414{
3415 struct drm_device *dev = crtc->base.dev;
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3417 int pipe = crtc->pipe;
3418
3419 /* To avoid upsetting the power well on haswell only disable the pfit if
3420 * it's in use. The hw state code will make sure we get this right. */
3421 if (crtc->config.pch_pfit.size) {
3422 I915_WRITE(PF_CTL(pipe), 0);
3423 I915_WRITE(PF_WIN_POS(pipe), 0);
3424 I915_WRITE(PF_WIN_SZ(pipe), 0);
3425 }
3426}
3427
6be4a607
JB		 3428static void ironlake_crtc_disable(struct drm_crtc *crtc)
3429{
3430 struct drm_device *dev = crtc->dev;
3431 struct drm_i915_private *dev_priv = dev->dev_private;
3432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3433 struct intel_encoder *encoder;
6be4a607
JB		 3434 int pipe = intel_crtc->pipe;
3435 int plane = intel_crtc->plane;
5eddb70b 3436 u32 reg, temp;
b52eb4dc 3437
ef9c3aee 3438
f7abfe8b
CW		 3439 if (!intel_crtc->active)
3440 return;
3441
ea9d758d
DV		 3442 for_each_encoder_on_crtc(dev, crtc, encoder)
3443 encoder->disable(encoder);
3444
e6c3a2a6 3445 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3446 drm_vblank_off(dev, pipe);
6b383a7f 3447 intel_crtc_update_cursor(crtc, false);
5eddb70b 3448
b24e7179 3449 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3450
973d04f9
CW		 3451 if (dev_priv->cfb_plane == plane)
3452 intel_disable_fbc(dev);
2c07245f 3453
8664281b 3454 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3455 intel_disable_pipe(dev_priv, pipe);
32f9d658 3456
3f8dce3a 3457 ironlake_pfit_disable(intel_crtc);
2c07245f 3458
bf49ec8c
DV		 3459 for_each_encoder_on_crtc(dev, crtc, encoder)
3460 if (encoder->post_disable)
3461 encoder->post_disable(encoder);
2c07245f 3462
0fc932b8 3463 ironlake_fdi_disable(crtc);
249c0e64 3464
b8a4f404 3465 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3466 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3467
6be4a607
JB		 3468 if (HAS_PCH_CPT(dev)) {
3469 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3470 reg = TRANS_DP_CTL(pipe);
3471 temp = I915_READ(reg);
3472 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3473 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3474 I915_WRITE(reg, temp);
6be4a607
JB		 3475
3476 /* disable DPLL_SEL */
3477 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3478 switch (pipe) {
3479 case 0:
d64311ab 3480 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3481 break;
3482 case 1:
6be4a607 3483 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3484 break;
3485 case 2:
4b645f14 3486 /* C shares PLL A or B */
d64311ab 3487 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3488 break;
3489 default:
3490 BUG(); /* wtf */
3491 }
6be4a607 3492 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3493 }
e3421a18 3494
6be4a607 3495 /* disable PCH DPLL */
ee7b9f93 3496 intel_disable_pch_pll(intel_crtc);
8db9d77b 3497
88cefb6c 3498 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3499
f7abfe8b 3500 intel_crtc->active = false;
6b383a7f 3501 intel_update_watermarks(dev);
d1ebd816
BW		 3502
3503 mutex_lock(&dev->struct_mutex);
6b383a7f 3504 intel_update_fbc(dev);
d1ebd816 3505 mutex_unlock(&dev->struct_mutex);
6be4a607 3506}
1b3c7a47 3507
4f771f10 3508static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3509{
4f771f10
PZ		 3510 struct drm_device *dev = crtc->dev;
3511 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3513 struct intel_encoder *encoder;
3514 int pipe = intel_crtc->pipe;
3515 int plane = intel_crtc->plane;
3b117c8f 3516 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3517
4f771f10
PZ		 3518 if (!intel_crtc->active)
3519 return;
3520
3521 for_each_encoder_on_crtc(dev, crtc, encoder)
3522 encoder->disable(encoder);
3523
3524 intel_crtc_wait_for_pending_flips(crtc);
3525 drm_vblank_off(dev, pipe);
3526 intel_crtc_update_cursor(crtc, false);
3527
891348b2 3528 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3529 if (dev_priv->cfb_plane == plane)
3530 intel_disable_fbc(dev);
3531
891348b2
RV		 3532 intel_disable_plane(dev_priv, plane, pipe);
3533
8664281b
PZ		 3534 if (intel_crtc->config.has_pch_encoder)
3535 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3536 intel_disable_pipe(dev_priv, pipe);
3537
ad80a810 3538 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3539
3f8dce3a 3540 ironlake_pfit_disable(intel_crtc);
4f771f10 3541
1f544388 3542 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3543
3544 for_each_encoder_on_crtc(dev, crtc, encoder)
3545 if (encoder->post_disable)
3546 encoder->post_disable(encoder);
3547
88adfff1 3548 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3549 lpt_disable_pch_transcoder(dev_priv);
8664281b 3550 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3551 intel_ddi_fdi_disable(crtc);
83616634 3552 }
4f771f10
PZ		 3553
3554 intel_crtc->active = false;
3555 intel_update_watermarks(dev);
3556
3557 mutex_lock(&dev->struct_mutex);
3558 intel_update_fbc(dev);
3559 mutex_unlock(&dev->struct_mutex);
3560}
3561
ee7b9f93
JB		 3562static void ironlake_crtc_off(struct drm_crtc *crtc)
3563{
3564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3565 intel_put_pch_pll(intel_crtc);
3566}
3567
6441ab5f
PZ		 3568static void haswell_crtc_off(struct drm_crtc *crtc)
3569{
a5c961d1
PZ		 3570 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3571
3572 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3573 * start using it. */
3b117c8f 3574 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3575
6441ab5f
PZ		 3576 intel_ddi_put_crtc_pll(crtc);
3577}
3578
02e792fb
DV		 3579static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3580{
02e792fb 3581 if (!enable && intel_crtc->overlay) {
23f09ce3 3582 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3583 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3584
23f09ce3 3585 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3586 dev_priv->mm.interruptible = false;
3587 (void) intel_overlay_switch_off(intel_crtc->overlay);
3588 dev_priv->mm.interruptible = true;
23f09ce3 3589 mutex_unlock(&dev->struct_mutex);
02e792fb 3590 }
02e792fb 3591
5dcdbcb0
CW		 3592 /* Let userspace switch the overlay on again. In most cases userspace
3593 * has to recompute where to put it anyway.
3594 */
02e792fb
DV		 3595}
3596
61bc95c1
EE		 3597/**
3598 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3599 * cursor plane briefly if not already running after enabling the display
3600 * plane.
3601 * This workaround avoids occasional blank screens when self refresh is
3602 * enabled.
3603 */
3604static void
3605g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3606{
3607 u32 cntl = I915_READ(CURCNTR(pipe));
3608
3609 if ((cntl & CURSOR_MODE) == 0) {
3610 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3611
3612 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3613 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3614 intel_wait_for_vblank(dev_priv->dev, pipe);
3615 I915_WRITE(CURCNTR(pipe), cntl);
3616 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3617 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3618 }
3619}
3620
2dd24552
JB		 3621static void i9xx_pfit_enable(struct intel_crtc *crtc)
3622{
3623 struct drm_device *dev = crtc->base.dev;
3624 struct drm_i915_private *dev_priv = dev->dev_private;
3625 struct intel_crtc_config *pipe_config = &crtc->config;
3626
328d8e82 3627 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3628 return;
3629
3630 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3631 assert_pipe_disabled(dev_priv, crtc->pipe);
3632
3633 /*
3634 * Enable automatic panel scaling so that non-native modes
3635 * fill the screen. The panel fitter should only be
3636 * adjusted whilst the pipe is disabled, according to
3637 * register description and PRM.
3638 */
3639 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
b074cec8
JB		 3640 pipe_config->gmch_pfit.control,
3641 pipe_config->gmch_pfit.pgm_ratios);
2dd24552 3642
b074cec8
JB		 3643 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3644 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3645
3646 /* Border color in case we don't scale up to the full screen. Black by
3647 * default, change to something else for debugging. */
3648 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3649}
3650
89b667f8
JB		 3651static void valleyview_crtc_enable(struct drm_crtc *crtc)
3652{
3653 struct drm_device *dev = crtc->dev;
3654 struct drm_i915_private *dev_priv = dev->dev_private;
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 struct intel_encoder *encoder;
3657 int pipe = intel_crtc->pipe;
3658 int plane = intel_crtc->plane;
3659
3660 WARN_ON(!crtc->enabled);
3661
3662 if (intel_crtc->active)
3663 return;
3664
3665 intel_crtc->active = true;
3666 intel_update_watermarks(dev);
3667
3668 mutex_lock(&dev_priv->dpio_lock);
3669
3670 for_each_encoder_on_crtc(dev, crtc, encoder)
3671 if (encoder->pre_pll_enable)
3672 encoder->pre_pll_enable(encoder);
3673
3674 intel_enable_pll(dev_priv, pipe);
3675
3676 for_each_encoder_on_crtc(dev, crtc, encoder)
3677 if (encoder->pre_enable)
3678 encoder->pre_enable(encoder);
3679
3680 /* VLV wants encoder enabling _before_ the pipe is up. */
3681 for_each_encoder_on_crtc(dev, crtc, encoder)
3682 encoder->enable(encoder);
3683
2dd24552
JB		 3684 /* Enable panel fitting for eDP */
3685 i9xx_pfit_enable(intel_crtc);
3686
89b667f8
JB		 3687 intel_enable_pipe(dev_priv, pipe, false);
3688 intel_enable_plane(dev_priv, plane, pipe);
3689
3690 intel_crtc_load_lut(crtc);
3691 intel_update_fbc(dev);
3692
3693 /* Give the overlay scaler a chance to enable if it's on this pipe */
3694 intel_crtc_dpms_overlay(intel_crtc, true);
3695 intel_crtc_update_cursor(crtc, true);
3696
3697 mutex_unlock(&dev_priv->dpio_lock);
3698}
3699
0b8765c6 3700static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3701{
3702 struct drm_device *dev = crtc->dev;
79e53945
JB		 3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3705 struct intel_encoder *encoder;
79e53945 3706 int pipe = intel_crtc->pipe;
80824003 3707 int plane = intel_crtc->plane;
79e53945 3708
08a48469
DV		 3709 WARN_ON(!crtc->enabled);
3710
f7abfe8b
CW		 3711 if (intel_crtc->active)
3712 return;
3713
3714 intel_crtc->active = true;
6b383a7f
CW		 3715 intel_update_watermarks(dev);
3716
63d7bbe9 3717 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3718
3719 for_each_encoder_on_crtc(dev, crtc, encoder)
3720 if (encoder->pre_enable)
3721 encoder->pre_enable(encoder);
3722
2dd24552
JB		 3723 /* Enable panel fitting for LVDS */
3724 i9xx_pfit_enable(intel_crtc);
3725
040484af 3726 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3727 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3728 if (IS_G4X(dev))
3729 g4x_fixup_plane(dev_priv, pipe);
79e53945 3730
0b8765c6 3731 intel_crtc_load_lut(crtc);
bed4a673 3732 intel_update_fbc(dev);
79e53945 3733
0b8765c6
JB		 3734 /* Give the overlay scaler a chance to enable if it's on this pipe */
3735 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3736 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3737
fa5c73b1
DV		 3738 for_each_encoder_on_crtc(dev, crtc, encoder)
3739 encoder->enable(encoder);
0b8765c6 3740}
79e53945 3741
87476d63
DV		 3742static void i9xx_pfit_disable(struct intel_crtc *crtc)
3743{
3744 struct drm_device *dev = crtc->base.dev;
3745 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3746
328d8e82
DV		 3747 if (!crtc->config.gmch_pfit.control)
3748 return;
87476d63 3749
328d8e82 3750 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3751
328d8e82
DV		 3752 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3753 I915_READ(PFIT_CONTROL));
3754 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3755}
3756
0b8765c6
JB		 3757static void i9xx_crtc_disable(struct drm_crtc *crtc)
3758{
3759 struct drm_device *dev = crtc->dev;
3760 struct drm_i915_private *dev_priv = dev->dev_private;
3761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3762 struct intel_encoder *encoder;
0b8765c6
JB		 3763 int pipe = intel_crtc->pipe;
3764 int plane = intel_crtc->plane;
ef9c3aee 3765
f7abfe8b
CW		 3766 if (!intel_crtc->active)
3767 return;
3768
ea9d758d
DV		 3769 for_each_encoder_on_crtc(dev, crtc, encoder)
3770 encoder->disable(encoder);
3771
0b8765c6 3772 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3773 intel_crtc_wait_for_pending_flips(crtc);
3774 drm_vblank_off(dev, pipe);
0b8765c6 3775 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3776 intel_crtc_update_cursor(crtc, false);
0b8765c6 3777
973d04f9
CW		 3778 if (dev_priv->cfb_plane == plane)
3779 intel_disable_fbc(dev);
79e53945 3780
b24e7179 3781 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3782 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3783
87476d63 3784 i9xx_pfit_disable(intel_crtc);
24a1f16d 3785
89b667f8
JB		 3786 for_each_encoder_on_crtc(dev, crtc, encoder)
3787 if (encoder->post_disable)
3788 encoder->post_disable(encoder);
3789
63d7bbe9 3790 intel_disable_pll(dev_priv, pipe);
0b8765c6 3791
f7abfe8b 3792 intel_crtc->active = false;
6b383a7f
CW		 3793 intel_update_fbc(dev);
3794 intel_update_watermarks(dev);
0b8765c6
JB		 3795}
3796
ee7b9f93
JB		 3797static void i9xx_crtc_off(struct drm_crtc *crtc)
3798{
3799}
3800
976f8a20
DV		 3801static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3802 bool enabled)
2c07245f
ZW		 3803{
3804 struct drm_device *dev = crtc->dev;
3805 struct drm_i915_master_private *master_priv;
3806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3807 int pipe = intel_crtc->pipe;
79e53945
JB		 3808
3809 if (!dev->primary->master)
3810 return;
3811
3812 master_priv = dev->primary->master->driver_priv;
3813 if (!master_priv->sarea_priv)
3814 return;
3815
79e53945
JB		 3816 switch (pipe) {
3817 case 0:
3818 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3819 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3820 break;
3821 case 1:
3822 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3823 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3824 break;
3825 default:
9db4a9c7 3826 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3827 break;
3828 }
79e53945
JB		 3829}
3830
976f8a20
DV		 3831/**
3832 * Sets the power management mode of the pipe and plane.
3833 */
3834void intel_crtc_update_dpms(struct drm_crtc *crtc)
3835{
3836 struct drm_device *dev = crtc->dev;
3837 struct drm_i915_private *dev_priv = dev->dev_private;
3838 struct intel_encoder *intel_encoder;
3839 bool enable = false;
3840
3841 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3842 enable |= intel_encoder->connectors_active;
3843
3844 if (enable)
3845 dev_priv->display.crtc_enable(crtc);
3846 else
3847 dev_priv->display.crtc_disable(crtc);
3848
3849 intel_crtc_update_sarea(crtc, enable);
3850}
3851
cdd59983
CW		 3852static void intel_crtc_disable(struct drm_crtc *crtc)
3853{
cdd59983 3854 struct drm_device *dev = crtc->dev;
976f8a20 3855 struct drm_connector *connector;
ee7b9f93 3856 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3857 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3858
976f8a20
DV		 3859 /* crtc should still be enabled when we disable it. */
3860 WARN_ON(!crtc->enabled);
3861
3862 dev_priv->display.crtc_disable(crtc);
c77bf565 3863 intel_crtc->eld_vld = false;
976f8a20 3864 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3865 dev_priv->display.off(crtc);
3866
931872fc
CW		 3867 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3868 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3869
3870 if (crtc->fb) {
3871 mutex_lock(&dev->struct_mutex);
1690e1eb 3872 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3873 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3874 crtc->fb = NULL;
3875 }
3876
3877 /* Update computed state. */
3878 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3879 if (!connector->encoder || !connector->encoder->crtc)
3880 continue;
3881
3882 if (connector->encoder->crtc != crtc)
3883 continue;
3884
3885 connector->dpms = DRM_MODE_DPMS_OFF;
3886 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3887 }
3888}
3889
a261b246 3890void intel_modeset_disable(struct drm_device *dev)
79e53945 3891{
a261b246
DV		 3892 struct drm_crtc *crtc;
3893
3894 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3895 if (crtc->enabled)
3896 intel_crtc_disable(crtc);
3897 }
79e53945
JB		 3898}
3899
ea5b213a 3900void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3901{
4ef69c7a 3902 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3903
ea5b213a
CW		 3904 drm_encoder_cleanup(encoder);
3905 kfree(intel_encoder);
7e7d76c3
JB		 3906}
3907
5ab432ef
DV		 3908/* Simple dpms helper for encodres with just one connector, no cloning and only
3909 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3910 * state of the entire output pipe. */
3911void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3912{
5ab432ef
DV		 3913 if (mode == DRM_MODE_DPMS_ON) {
3914 encoder->connectors_active = true;
3915
b2cabb0e 3916 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3917 } else {
3918 encoder->connectors_active = false;
3919
b2cabb0e 3920 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3921 }
79e53945
JB		 3922}
3923
0a91ca29
DV		 3924/* Cross check the actual hw state with our own modeset state tracking (and it's
3925 * internal consistency). */
b980514c 3926static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3927{
0a91ca29
DV		 3928 if (connector->get_hw_state(connector)) {
3929 struct intel_encoder *encoder = connector->encoder;
3930 struct drm_crtc *crtc;
3931 bool encoder_enabled;
3932 enum pipe pipe;
3933
3934 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3935 connector->base.base.id,
3936 drm_get_connector_name(&connector->base));
3937
3938 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3939 "wrong connector dpms state\n");
3940 WARN(connector->base.encoder != &encoder->base,
3941 "active connector not linked to encoder\n");
3942 WARN(!encoder->connectors_active,
3943 "encoder->connectors_active not set\n");
3944
3945 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3946 WARN(!encoder_enabled, "encoder not enabled\n");
3947 if (WARN_ON(!encoder->base.crtc))
3948 return;
3949
3950 crtc = encoder->base.crtc;
3951
3952 WARN(!crtc->enabled, "crtc not enabled\n");
3953 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3954 WARN(pipe != to_intel_crtc(crtc)->pipe,
3955 "encoder active on the wrong pipe\n");
3956 }
79e53945
JB		 3957}
3958
5ab432ef
DV		 3959/* Even simpler default implementation, if there's really no special case to
3960 * consider. */
3961void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3962{
5ab432ef 3963 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3964
5ab432ef
DV		 3965 /* All the simple cases only support two dpms states. */
3966 if (mode != DRM_MODE_DPMS_ON)
3967 mode = DRM_MODE_DPMS_OFF;
d4270e57 3968
5ab432ef
DV		 3969 if (mode == connector->dpms)
3970 return;
3971
3972 connector->dpms = mode;
3973
3974 /* Only need to change hw state when actually enabled */
3975 if (encoder->base.crtc)
3976 intel_encoder_dpms(encoder, mode);
3977 else
8af6cf88 3978 WARN_ON(encoder->connectors_active != false);
0a91ca29 3979
b980514c 3980 intel_modeset_check_state(connector->dev);
79e53945
JB		 3981}
3982
f0947c37
DV		 3983/* Simple connector->get_hw_state implementation for encoders that support only
3984 * one connector and no cloning and hence the encoder state determines the state
3985 * of the connector. */
3986bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3987{
24929352 3988 enum pipe pipe = 0;
f0947c37 3989 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3990
f0947c37 3991 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3992}
3993
1857e1da
DV		 3994static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3995 struct intel_crtc_config *pipe_config)
3996{
3997 struct drm_i915_private *dev_priv = dev->dev_private;
3998 struct intel_crtc *pipe_B_crtc =
3999 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4000
4001 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4002 pipe_name(pipe), pipe_config->fdi_lanes);
4003 if (pipe_config->fdi_lanes > 4) {
4004 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4005 pipe_name(pipe), pipe_config->fdi_lanes);
4006 return false;
4007 }
4008
4009 if (IS_HASWELL(dev)) {
4010 if (pipe_config->fdi_lanes > 2) {
4011 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4012 pipe_config->fdi_lanes);
4013 return false;
4014 } else {
4015 return true;
4016 }
4017 }
4018
4019 if (INTEL_INFO(dev)->num_pipes == 2)
4020 return true;
4021
4022 /* Ivybridge 3 pipe is really complicated */
4023 switch (pipe) {
4024 case PIPE_A:
4025 return true;
4026 case PIPE_B:
4027 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4028 pipe_config->fdi_lanes > 2) {
4029 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4030 pipe_name(pipe), pipe_config->fdi_lanes);
4031 return false;
4032 }
4033 return true;
4034 case PIPE_C:
1e833f40 4035 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4036 pipe_B_crtc->config.fdi_lanes <= 2) {
4037 if (pipe_config->fdi_lanes > 2) {
4038 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4039 pipe_name(pipe), pipe_config->fdi_lanes);
4040 return false;
4041 }
4042 } else {
4043 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4044 return false;
4045 }
4046 return true;
4047 default:
4048 BUG();
4049 }
4050}
4051
e29c22c0
DV		 4052#define RETRY 1
4053static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4054 struct intel_crtc_config *pipe_config)
877d48d5 4055{
1857e1da 4056 struct drm_device *dev = intel_crtc->base.dev;
877d48d5
DV		 4057 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4058 int target_clock, lane, link_bw;
e29c22c0 4059 bool setup_ok, needs_recompute = false;
877d48d5 4060
e29c22c0 4061retry:
877d48d5
DV		 4062 /* FDI is a binary signal running at ~2.7GHz, encoding
4063 * each output octet as 10 bits. The actual frequency
4064 * is stored as a divider into a 100MHz clock, and the
4065 * mode pixel clock is stored in units of 1KHz.
4066 * Hence the bw of each lane in terms of the mode signal
4067 * is:
4068 */
4069 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4070
4071 if (pipe_config->pixel_target_clock)
4072 target_clock = pipe_config->pixel_target_clock;
4073 else
4074 target_clock = adjusted_mode->clock;
4075
4076 lane = ironlake_get_lanes_required(target_clock, link_bw,
4077 pipe_config->pipe_bpp);
4078
4079 pipe_config->fdi_lanes = lane;
4080
4081 if (pipe_config->pixel_multiplier > 1)
4082 link_bw *= pipe_config->pixel_multiplier;
4083 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4084 link_bw, &pipe_config->fdi_m_n);
1857e1da 4085
e29c22c0
DV		 4086 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4087 intel_crtc->pipe, pipe_config);
4088 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4089 pipe_config->pipe_bpp -= 2*3;
4090 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4091 pipe_config->pipe_bpp);
4092 needs_recompute = true;
4093 pipe_config->bw_constrained = true;
4094
4095 goto retry;
4096 }
4097
4098 if (needs_recompute)
4099 return RETRY;
4100
4101 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4102}
4103
e29c22c0
DV		 4104static int intel_crtc_compute_config(struct drm_crtc *crtc,
4105 struct intel_crtc_config *pipe_config)
79e53945 4106{
2c07245f 4107 struct drm_device *dev = crtc->dev;
b8cecdf5 4108 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4109
bad720ff 4110 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4111 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4112 if (pipe_config->requested_mode.clock * 3
4113 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4114 return -EINVAL;
2c07245f 4115 }
89749350 4116
f9bef081
DV		 4117 /* All interlaced capable intel hw wants timings in frames. Note though
4118 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4119 * timings, so we need to be careful not to clobber these.*/
7ae89233 4120 if (!pipe_config->timings_set)
f9bef081 4121 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4122
8693a824
DL		 4123 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4124 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4125 */
4126 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4127 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4128 return -EINVAL;
44f46b42 4129
bd080ee5 4130 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4131 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4132 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4133 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4134 * for lvds. */
4135 pipe_config->pipe_bpp = 8*3;
4136 }
4137
877d48d5 4138 if (pipe_config->has_pch_encoder)
1857e1da 4139 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
877d48d5 4140
e29c22c0 4141 return 0;
79e53945
JB		 4142}
4143
25eb05fc
JB		 4144static int valleyview_get_display_clock_speed(struct drm_device *dev)
4145{
4146 return 400000; /* FIXME */
4147}
4148
e70236a8
JB		 4149static int i945_get_display_clock_speed(struct drm_device *dev)
4150{
4151 return 400000;
4152}
79e53945 4153
e70236a8 4154static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4155{
e70236a8
JB		 4156 return 333000;
4157}
79e53945 4158
e70236a8
JB		 4159static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4160{
4161 return 200000;
4162}
79e53945 4163
e70236a8
JB		 4164static int i915gm_get_display_clock_speed(struct drm_device *dev)
4165{
4166 u16 gcfgc = 0;
79e53945 4167
e70236a8
JB		 4168 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4169
4170 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4171 return 133000;
4172 else {
4173 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4174 case GC_DISPLAY_CLOCK_333_MHZ:
4175 return 333000;
4176 default:
4177 case GC_DISPLAY_CLOCK_190_200_MHZ:
4178 return 190000;
79e53945 4179 }
e70236a8
JB		 4180 }
4181}
4182
4183static int i865_get_display_clock_speed(struct drm_device *dev)
4184{
4185 return 266000;
4186}
4187
4188static int i855_get_display_clock_speed(struct drm_device *dev)
4189{
4190 u16 hpllcc = 0;
4191 /* Assume that the hardware is in the high speed state. This
4192 * should be the default.
4193 */
4194 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4195 case GC_CLOCK_133_200:
4196 case GC_CLOCK_100_200:
4197 return 200000;
4198 case GC_CLOCK_166_250:
4199 return 250000;
4200 case GC_CLOCK_100_133:
79e53945 4201 return 133000;
e70236a8 4202 }
79e53945 4203
e70236a8
JB		 4204 /* Shouldn't happen */
4205 return 0;
4206}
79e53945 4207
e70236a8
JB		 4208static int i830_get_display_clock_speed(struct drm_device *dev)
4209{
4210 return 133000;
79e53945
JB		 4211}
4212
2c07245f 4213static void
a65851af 4214intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4215{
a65851af
VS		 4216 while (*num > DATA_LINK_M_N_MASK ||
4217 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4218 *num >>= 1;
4219 *den >>= 1;
4220 }
4221}
4222
a65851af
VS		 4223static void compute_m_n(unsigned int m, unsigned int n,
4224 uint32_t *ret_m, uint32_t *ret_n)
4225{
4226 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4227 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4228 intel_reduce_m_n_ratio(ret_m, ret_n);
4229}
4230
e69d0bc1
DV		 4231void
4232intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4233 int pixel_clock, int link_clock,
4234 struct intel_link_m_n *m_n)
2c07245f 4235{
e69d0bc1 4236 m_n->tu = 64;
a65851af
VS		 4237
4238 compute_m_n(bits_per_pixel * pixel_clock,
4239 link_clock * nlanes * 8,
4240 &m_n->gmch_m, &m_n->gmch_n);
4241
4242 compute_m_n(pixel_clock, link_clock,
4243 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4244}
4245
a7615030
CW		 4246static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4247{
72bbe58c
KP		 4248 if (i915_panel_use_ssc >= 0)
4249 return i915_panel_use_ssc != 0;
41aa3448 4250 return dev_priv->vbt.lvds_use_ssc
435793df 4251 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4252}
4253
a0c4da24
JB		 4254static int vlv_get_refclk(struct drm_crtc *crtc)
4255{
4256 struct drm_device *dev = crtc->dev;
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258 int refclk = 27000; /* for DP & HDMI */
4259
4260 return 100000; /* only one validated so far */
4261
4262 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4263 refclk = 96000;
4264 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4265 if (intel_panel_use_ssc(dev_priv))
4266 refclk = 100000;
4267 else
4268 refclk = 96000;
4269 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4270 refclk = 100000;
4271 }
4272
4273 return refclk;
4274}
4275
c65d77d8
JB		 4276static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4277{
4278 struct drm_device *dev = crtc->dev;
4279 struct drm_i915_private *dev_priv = dev->dev_private;
4280 int refclk;
4281
a0c4da24
JB		 4282 if (IS_VALLEYVIEW(dev)) {
4283 refclk = vlv_get_refclk(crtc);
4284 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4285 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4286 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4287 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4288 refclk / 1000);
4289 } else if (!IS_GEN2(dev)) {
4290 refclk = 96000;
4291 } else {
4292 refclk = 48000;
4293 }
4294
4295 return refclk;
4296}
4297
7429e9d4 4298static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4299{
7429e9d4
DV		 4300 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4301}
f47709a9 4302
7429e9d4
DV		 4303static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4304{
4305 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4306}
4307
f47709a9 4308static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4309 intel_clock_t *reduced_clock)
4310{
f47709a9 4311 struct drm_device *dev = crtc->base.dev;
a7516a05 4312 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4313 int pipe = crtc->pipe;
a7516a05
JB		 4314 u32 fp, fp2 = 0;
4315
4316 if (IS_PINEVIEW(dev)) {
7429e9d4 4317 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4318 if (reduced_clock)
7429e9d4 4319 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4320 } else {
7429e9d4 4321 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4322 if (reduced_clock)
7429e9d4 4323 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4324 }
4325
4326 I915_WRITE(FP0(pipe), fp);
4327
f47709a9
DV		 4328 crtc->lowfreq_avail = false;
4329 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4330 reduced_clock && i915_powersave) {
4331 I915_WRITE(FP1(pipe), fp2);
f47709a9 4332 crtc->lowfreq_avail = true;
a7516a05
JB		 4333 } else {
4334 I915_WRITE(FP1(pipe), fp);
4335 }
4336}
4337
89b667f8
JB		 4338static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4339{
4340 u32 reg_val;
4341
4342 /*
4343 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4344 * and set it to a reasonable value instead.
4345 */
4346 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4347 reg_val &= 0xffffff00;
4348 reg_val |= 0x00000030;
4349 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4350
4351 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4352 reg_val &= 0x8cffffff;
4353 reg_val = 0x8c000000;
4354 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4355
4356 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4357 reg_val &= 0xffffff00;
4358 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4359
4360 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4361 reg_val &= 0x00ffffff;
4362 reg_val |= 0xb0000000;
4363 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4364}
4365
b551842d
DV		 4366static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4367 struct intel_link_m_n *m_n)
4368{
4369 struct drm_device *dev = crtc->base.dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371 int pipe = crtc->pipe;
4372
e3b95f1e
DV		 4373 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4374 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4375 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4376 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4377}
4378
4379static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4380 struct intel_link_m_n *m_n)
4381{
4382 struct drm_device *dev = crtc->base.dev;
4383 struct drm_i915_private *dev_priv = dev->dev_private;
4384 int pipe = crtc->pipe;
4385 enum transcoder transcoder = crtc->config.cpu_transcoder;
4386
4387 if (INTEL_INFO(dev)->gen >= 5) {
4388 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4389 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4390 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4391 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4392 } else {
e3b95f1e
DV		 4393 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4394 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4395 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4396 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4397 }
4398}
4399
03afc4a2
DV		 4400static void intel_dp_set_m_n(struct intel_crtc *crtc)
4401{
4402 if (crtc->config.has_pch_encoder)
4403 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4404 else
4405 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4406}
4407
f47709a9 4408static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4409{
f47709a9 4410 struct drm_device *dev = crtc->base.dev;
a0c4da24 4411 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4412 struct drm_display_mode *adjusted_mode =
4413 &crtc->config.adjusted_mode;
4414 struct intel_encoder *encoder;
f47709a9 4415 int pipe = crtc->pipe;
89b667f8 4416 u32 dpll, mdiv;
a0c4da24 4417 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4418 bool is_hdmi;
198a037f 4419 u32 coreclk, reg_val, dpll_md;
a0c4da24 4420
09153000
DV		 4421 mutex_lock(&dev_priv->dpio_lock);
4422
89b667f8 4423 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4424
f47709a9
DV		 4425 bestn = crtc->config.dpll.n;
4426 bestm1 = crtc->config.dpll.m1;
4427 bestm2 = crtc->config.dpll.m2;
4428 bestp1 = crtc->config.dpll.p1;
4429 bestp2 = crtc->config.dpll.p2;
a0c4da24 4430
89b667f8
JB		 4431 /* See eDP HDMI DPIO driver vbios notes doc */
4432
4433 /* PLL B needs special handling */
4434 if (pipe)
4435 vlv_pllb_recal_opamp(dev_priv);
4436
4437 /* Set up Tx target for periodic Rcomp update */
4438 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4439
4440 /* Disable target IRef on PLL */
4441 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4442 reg_val &= 0x00ffffff;
4443 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4444
4445 /* Disable fast lock */
4446 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4447
4448 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4449 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4450 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4451 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4452 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4453
4454 /*
4455 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4456 * but we don't support that).
4457 * Note: don't use the DAC post divider as it seems unstable.
4458 */
4459 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4460 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4461
a0c4da24
JB		 4462 mdiv |= DPIO_ENABLE_CALIBRATION;
4463 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4464
89b667f8
JB		 4465 /* Set HBR and RBR LPF coefficients */
4466 if (adjusted_mode->clock == 162000 ||
4467 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4468 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4469 0x005f0021);
4470 else
4471 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4472 0x00d0000f);
4473
4474 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4475 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4476 /* Use SSC source */
4477 if (!pipe)
4478 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4479 0x0df40000);
4480 else
4481 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4482 0x0df70000);
4483 } else { /* HDMI or VGA */
4484 /* Use bend source */
4485 if (!pipe)
4486 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4487 0x0df70000);
4488 else
4489 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4490 0x0df40000);
4491 }
a0c4da24 4492
89b667f8
JB		 4493 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4494 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4495 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4496 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4497 coreclk |= 0x01000000;
4498 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4499
89b667f8 4500 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4501
89b667f8
JB		 4502 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4503 if (encoder->pre_pll_enable)
4504 encoder->pre_pll_enable(encoder);
a0c4da24 4505
89b667f8
JB		 4506 /* Enable DPIO clock input */
4507 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4508 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4509 if (pipe)
4510 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4511
4512 dpll |= DPLL_VCO_ENABLE;
4513 I915_WRITE(DPLL(pipe), dpll);
4514 POSTING_READ(DPLL(pipe));
2a8f64ca 4515 udelay(150);
a0c4da24 4516
a0c4da24
JB		 4517 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4518 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4519
198a037f
DV		 4520 dpll_md = 0;
4521 if (crtc->config.pixel_multiplier > 1) {
4522 dpll_md = (crtc->config.pixel_multiplier - 1)
4523 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
a0c4da24 4524 }
198a037f 4525 I915_WRITE(DPLL_MD(pipe), dpll_md);
2a8f64ca 4526 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4527
89b667f8
JB		 4528 if (crtc->config.has_dp_encoder)
4529 intel_dp_set_m_n(crtc);
09153000
DV		 4530
4531 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4532}
4533
f47709a9
DV		 4534static void i9xx_update_pll(struct intel_crtc *crtc,
4535 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4536 int num_connectors)
4537{
f47709a9 4538 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4539 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4540 struct intel_encoder *encoder;
f47709a9 4541 int pipe = crtc->pipe;
eb1cbe48
DV		 4542 u32 dpll;
4543 bool is_sdvo;
f47709a9 4544 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4545
f47709a9 4546 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4547
f47709a9
DV		 4548 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4549 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4550
4551 dpll = DPLL_VGA_MODE_DIS;
4552
f47709a9 4553 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4554 dpll |= DPLLB_MODE_LVDS;
4555 else
4556 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4557
198a037f
DV		 4558 if ((crtc->config.pixel_multiplier > 1) &&
4559 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4560 dpll |= (crtc->config.pixel_multiplier - 1)
4561 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4562 }
198a037f
DV		 4563
4564 if (is_sdvo)
4565 dpll |= DPLL_DVO_HIGH_SPEED;
4566
f47709a9 4567 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4568 dpll |= DPLL_DVO_HIGH_SPEED;
4569
4570 /* compute bitmask from p1 value */
4571 if (IS_PINEVIEW(dev))
4572 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4573 else {
4574 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4575 if (IS_G4X(dev) && reduced_clock)
4576 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4577 }
4578 switch (clock->p2) {
4579 case 5:
4580 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4581 break;
4582 case 7:
4583 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4584 break;
4585 case 10:
4586 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4587 break;
4588 case 14:
4589 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4590 break;
4591 }
4592 if (INTEL_INFO(dev)->gen >= 4)
4593 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4594
09ede541 4595 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4596 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4597 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4598 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4599 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4600 else
4601 dpll |= PLL_REF_INPUT_DREFCLK;
4602
4603 dpll |= DPLL_VCO_ENABLE;
4604 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4605 POSTING_READ(DPLL(pipe));
4606 udelay(150);
4607
f47709a9 4608 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4609 if (encoder->pre_pll_enable)
4610 encoder->pre_pll_enable(encoder);
eb1cbe48 4611
f47709a9
DV		 4612 if (crtc->config.has_dp_encoder)
4613 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4614
4615 I915_WRITE(DPLL(pipe), dpll);
4616
4617 /* Wait for the clocks to stabilize. */
4618 POSTING_READ(DPLL(pipe));
4619 udelay(150);
4620
4621 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4622 u32 dpll_md = 0;
4623 if (crtc->config.pixel_multiplier > 1) {
4624 dpll_md = (crtc->config.pixel_multiplier - 1)
4625 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4626 }
198a037f 4627 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4628 } else {
4629 /* The pixel multiplier can only be updated once the
4630 * DPLL is enabled and the clocks are stable.
4631 *
4632 * So write it again.
4633 */
4634 I915_WRITE(DPLL(pipe), dpll);
4635 }
4636}
4637
f47709a9 4638static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4639 struct drm_display_mode *adjusted_mode,
f47709a9 4640 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4641 int num_connectors)
4642{
f47709a9 4643 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4644 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4645 struct intel_encoder *encoder;
f47709a9 4646 int pipe = crtc->pipe;
eb1cbe48 4647 u32 dpll;
f47709a9 4648 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4649
f47709a9 4650 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4651
eb1cbe48
DV		 4652 dpll = DPLL_VGA_MODE_DIS;
4653
f47709a9 4654 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4655 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4656 } else {
4657 if (clock->p1 == 2)
4658 dpll |= PLL_P1_DIVIDE_BY_TWO;
4659 else
4660 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4661 if (clock->p2 == 4)
4662 dpll |= PLL_P2_DIVIDE_BY_4;
4663 }
4664
f47709a9 4665 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4666 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4667 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4668 else
4669 dpll |= PLL_REF_INPUT_DREFCLK;
4670
4671 dpll |= DPLL_VCO_ENABLE;
4672 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4673 POSTING_READ(DPLL(pipe));
4674 udelay(150);
4675
f47709a9 4676 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4677 if (encoder->pre_pll_enable)
4678 encoder->pre_pll_enable(encoder);
eb1cbe48 4679
5b5896e4
DV		 4680 I915_WRITE(DPLL(pipe), dpll);
4681
4682 /* Wait for the clocks to stabilize. */
4683 POSTING_READ(DPLL(pipe));
4684 udelay(150);
4685
eb1cbe48
DV		 4686 /* The pixel multiplier can only be updated once the
4687 * DPLL is enabled and the clocks are stable.
4688 *
4689 * So write it again.
4690 */
4691 I915_WRITE(DPLL(pipe), dpll);
4692}
4693
b0e77b9c
PZ		 4694static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4695 struct drm_display_mode *mode,
4696 struct drm_display_mode *adjusted_mode)
4697{
4698 struct drm_device *dev = intel_crtc->base.dev;
4699 struct drm_i915_private *dev_priv = dev->dev_private;
4700 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4701 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4d8a62ea
DV		 4702 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4703
4704 /* We need to be careful not to changed the adjusted mode, for otherwise
4705 * the hw state checker will get angry at the mismatch. */
4706 crtc_vtotal = adjusted_mode->crtc_vtotal;
4707 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4708
4709 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4710 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4711 crtc_vtotal -= 1;
4712 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4713 vsyncshift = adjusted_mode->crtc_hsync_start
4714 - adjusted_mode->crtc_htotal / 2;
4715 } else {
4716 vsyncshift = 0;
4717 }
4718
4719 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4720 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4721
fe2b8f9d 4722 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4723 (adjusted_mode->crtc_hdisplay - 1) |
4724 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4725 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4726 (adjusted_mode->crtc_hblank_start - 1) |
4727 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4728 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4729 (adjusted_mode->crtc_hsync_start - 1) |
4730 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4731
fe2b8f9d 4732 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4733 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4734 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4735 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4736 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4737 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4738 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4739 (adjusted_mode->crtc_vsync_start - 1) |
4740 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4741
b5e508d4
PZ		 4742 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4743 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4744 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4745 * bits. */
4746 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4747 (pipe == PIPE_B || pipe == PIPE_C))
4748 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4749
b0e77b9c
PZ		 4750 /* pipesrc controls the size that is scaled from, which should
4751 * always be the user's requested size.
4752 */
4753 I915_WRITE(PIPESRC(pipe),
4754 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4755}
4756
1bd1bd80
DV		 4757static void intel_get_pipe_timings(struct intel_crtc *crtc,
4758 struct intel_crtc_config *pipe_config)
4759{
4760 struct drm_device *dev = crtc->base.dev;
4761 struct drm_i915_private *dev_priv = dev->dev_private;
4762 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4763 uint32_t tmp;
4764
4765 tmp = I915_READ(HTOTAL(cpu_transcoder));
4766 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4767 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4768 tmp = I915_READ(HBLANK(cpu_transcoder));
4769 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4770 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4771 tmp = I915_READ(HSYNC(cpu_transcoder));
4772 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4773 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4774
4775 tmp = I915_READ(VTOTAL(cpu_transcoder));
4776 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4777 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4778 tmp = I915_READ(VBLANK(cpu_transcoder));
4779 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4780 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4781 tmp = I915_READ(VSYNC(cpu_transcoder));
4782 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4783 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4784
4785 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4786 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4787 pipe_config->adjusted_mode.crtc_vtotal += 1;
4788 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4789 }
4790
4791 tmp = I915_READ(PIPESRC(crtc->pipe));
4792 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4793 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4794}
4795
84b046f3
DV		 4796static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4797{
4798 struct drm_device *dev = intel_crtc->base.dev;
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800 uint32_t pipeconf;
4801
4802 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4803
4804 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4805 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4806 * core speed.
4807 *
4808 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4809 * pipe == 0 check?
4810 */
4811 if (intel_crtc->config.requested_mode.clock >
4812 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4813 pipeconf |= PIPECONF_DOUBLE_WIDE;
4814 else
4815 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4816 }
4817
ff9ce46e
DV		 4818 /* only g4x and later have fancy bpc/dither controls */
4819 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4820 pipeconf &= ~(PIPECONF_BPC_MASK |
4821 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4822
4823 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4824 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4825 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4826 PIPECONF_DITHER_TYPE_SP;
84b046f3 4827
ff9ce46e
DV		 4828 switch (intel_crtc->config.pipe_bpp) {
4829 case 18:
4830 pipeconf |= PIPECONF_6BPC;
4831 break;
4832 case 24:
4833 pipeconf |= PIPECONF_8BPC;
4834 break;
4835 case 30:
4836 pipeconf |= PIPECONF_10BPC;
4837 break;
4838 default:
4839 /* Case prevented by intel_choose_pipe_bpp_dither. */
4840 BUG();
84b046f3
DV		 4841 }
4842 }
4843
4844 if (HAS_PIPE_CXSR(dev)) {
4845 if (intel_crtc->lowfreq_avail) {
4846 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4847 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4848 } else {
4849 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4850 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4851 }
4852 }
4853
4854 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4855 if (!IS_GEN2(dev) &&
4856 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4857 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4858 else
4859 pipeconf |= PIPECONF_PROGRESSIVE;
4860
9c8e09b7
VS		 4861 if (IS_VALLEYVIEW(dev)) {
4862 if (intel_crtc->config.limited_color_range)
4863 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4864 else
4865 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4866 }
4867
84b046f3
DV		 4868 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4869 POSTING_READ(PIPECONF(intel_crtc->pipe));
4870}
4871
f564048e 4872static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4873 int x, int y,
94352cf9 4874 struct drm_framebuffer *fb)
79e53945
JB		 4875{
4876 struct drm_device *dev = crtc->dev;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4879 struct drm_display_mode *adjusted_mode =
4880 &intel_crtc->config.adjusted_mode;
4881 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4882 int pipe = intel_crtc->pipe;
80824003 4883 int plane = intel_crtc->plane;
c751ce4f 4884 int refclk, num_connectors = 0;
652c393a 4885 intel_clock_t clock, reduced_clock;
84b046f3 4886 u32 dspcntr;
a16af721
DV		 4887 bool ok, has_reduced_clock = false;
4888 bool is_lvds = false;
5eddb70b 4889 struct intel_encoder *encoder;
d4906093 4890 const intel_limit_t *limit;
5c3b82e2 4891 int ret;
79e53945 4892
6c2b7c12 4893 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4894 switch (encoder->type) {
79e53945
JB		 4895 case INTEL_OUTPUT_LVDS:
4896 is_lvds = true;
4897 break;
79e53945 4898 }
43565a06 4899
c751ce4f 4900 num_connectors++;
79e53945
JB		 4901 }
4902
c65d77d8 4903 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4904
d4906093
ML		 4905 /*
4906 * Returns a set of divisors for the desired target clock with the given
4907 * refclk, or FALSE. The returned values represent the clock equation:
4908 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4909 */
1b894b59 4910 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4911 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4912 &clock);
79e53945
JB		 4913 if (!ok) {
4914 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4915 return -EINVAL;
79e53945
JB		 4916 }
4917
cda4b7d3 4918 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4919 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4920
ddc9003c 4921 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4922 /*
4923 * Ensure we match the reduced clock's P to the target clock.
4924 * If the clocks don't match, we can't switch the display clock
4925 * by using the FP0/FP1. In such case we will disable the LVDS
4926 * downclock feature.
4927 */
ddc9003c 4928 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4929 dev_priv->lvds_downclock,
4930 refclk,
cec2f356 4931 &clock,
5eddb70b 4932 &reduced_clock);
7026d4ac 4933 }
f47709a9
DV		 4934 /* Compat-code for transition, will disappear. */
4935 if (!intel_crtc->config.clock_set) {
4936 intel_crtc->config.dpll.n = clock.n;
4937 intel_crtc->config.dpll.m1 = clock.m1;
4938 intel_crtc->config.dpll.m2 = clock.m2;
4939 intel_crtc->config.dpll.p1 = clock.p1;
4940 intel_crtc->config.dpll.p2 = clock.p2;
4941 }
7026d4ac 4942
eb1cbe48 4943 if (IS_GEN2(dev))
f47709a9 4944 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4945 has_reduced_clock ? &reduced_clock : NULL,
4946 num_connectors);
a0c4da24 4947 else if (IS_VALLEYVIEW(dev))
f47709a9 4948 vlv_update_pll(intel_crtc);
79e53945 4949 else
f47709a9 4950 i9xx_update_pll(intel_crtc,
eb1cbe48 4951 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4952 num_connectors);
79e53945 4953
79e53945
JB		 4954 /* Set up the display plane register */
4955 dspcntr = DISPPLANE_GAMMA_ENABLE;
4956
da6ecc5d
JB		 4957 if (!IS_VALLEYVIEW(dev)) {
4958 if (pipe == 0)
4959 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4960 else
4961 dspcntr |= DISPPLANE_SEL_PIPE_B;
4962 }
79e53945 4963
2582a850 4964 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4965 drm_mode_debug_printmodeline(mode);
4966
b0e77b9c 4967 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4968
4969 /* pipesrc and dspsize control the size that is scaled from,
4970 * which should always be the user's requested size.
79e53945 4971 */
929c77fb
EA		 4972 I915_WRITE(DSPSIZE(plane),
4973 ((mode->vdisplay - 1) << 16) |
4974 (mode->hdisplay - 1));
4975 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4976
84b046f3
DV		 4977 i9xx_set_pipeconf(intel_crtc);
4978
f564048e
EA		 4979 I915_WRITE(DSPCNTR(plane), dspcntr);
4980 POSTING_READ(DSPCNTR(plane));
4981
94352cf9 4982 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4983
4984 intel_update_watermarks(dev);
4985
f564048e
EA		 4986 return ret;
4987}
4988
2fa2fe9a
DV		 4989static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4990 struct intel_crtc_config *pipe_config)
4991{
4992 struct drm_device *dev = crtc->base.dev;
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4994 uint32_t tmp;
4995
4996 tmp = I915_READ(PFIT_CONTROL);
4997
4998 if (INTEL_INFO(dev)->gen < 4) {
4999 if (crtc->pipe != PIPE_B)
5000 return;
5001
5002 /* gen2/3 store dither state in pfit control, needs to match */
5003 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
5004 } else {
5005 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5006 return;
5007 }
5008
5009 if (!(tmp & PFIT_ENABLE))
5010 return;
5011
5012 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
5013 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5014 if (INTEL_INFO(dev)->gen < 5)
5015 pipe_config->gmch_pfit.lvds_border_bits =
5016 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5017}
5018
0e8ffe1b
DV		 5019static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5020 struct intel_crtc_config *pipe_config)
5021{
5022 struct drm_device *dev = crtc->base.dev;
5023 struct drm_i915_private *dev_priv = dev->dev_private;
5024 uint32_t tmp;
5025
5026 tmp = I915_READ(PIPECONF(crtc->pipe));
5027 if (!(tmp & PIPECONF_ENABLE))
5028 return false;
5029
1bd1bd80
DV		 5030 intel_get_pipe_timings(crtc, pipe_config);
5031
2fa2fe9a
DV		 5032 i9xx_get_pfit_config(crtc, pipe_config);
5033
0e8ffe1b
DV		 5034 return true;
5035}
5036
dde86e2d 5037static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5038{
5039 struct drm_i915_private *dev_priv = dev->dev_private;
5040 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5041 struct intel_encoder *encoder;
74cfd7ac 5042 u32 val, final;
13d83a67 5043 bool has_lvds = false;
199e5d79 5044 bool has_cpu_edp = false;
199e5d79 5045 bool has_panel = false;
99eb6a01
KP		 5046 bool has_ck505 = false;
5047 bool can_ssc = false;
13d83a67
JB		 5048
5049 /* We need to take the global config into account */
199e5d79
KP		 5050 list_for_each_entry(encoder, &mode_config->encoder_list,
5051 base.head) {
5052 switch (encoder->type) {
5053 case INTEL_OUTPUT_LVDS:
5054 has_panel = true;
5055 has_lvds = true;
5056 break;
5057 case INTEL_OUTPUT_EDP:
5058 has_panel = true;
2de6905f 5059 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5060 has_cpu_edp = true;
5061 break;
13d83a67
JB		 5062 }
5063 }
5064
99eb6a01 5065 if (HAS_PCH_IBX(dev)) {
41aa3448 5066 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5067 can_ssc = has_ck505;
5068 } else {
5069 has_ck505 = false;
5070 can_ssc = true;
5071 }
5072
2de6905f
ID		 5073 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5074 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5075
5076 /* Ironlake: try to setup display ref clock before DPLL
5077 * enabling. This is only under driver's control after
5078 * PCH B stepping, previous chipset stepping should be
5079 * ignoring this setting.
5080 */
74cfd7ac
CW		 5081 val = I915_READ(PCH_DREF_CONTROL);
5082
5083 /* As we must carefully and slowly disable/enable each source in turn,
5084 * compute the final state we want first and check if we need to
5085 * make any changes at all.
5086 */
5087 final = val;
5088 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5089 if (has_ck505)
5090 final |= DREF_NONSPREAD_CK505_ENABLE;
5091 else
5092 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5093
5094 final &= ~DREF_SSC_SOURCE_MASK;
5095 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5096 final &= ~DREF_SSC1_ENABLE;
5097
5098 if (has_panel) {
5099 final |= DREF_SSC_SOURCE_ENABLE;
5100
5101 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5102 final |= DREF_SSC1_ENABLE;
5103
5104 if (has_cpu_edp) {
5105 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5106 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5107 else
5108 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5109 } else
5110 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5111 } else {
5112 final |= DREF_SSC_SOURCE_DISABLE;
5113 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5114 }
5115
5116 if (final == val)
5117 return;
5118
13d83a67 5119 /* Always enable nonspread source */
74cfd7ac 5120 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5121
99eb6a01 5122 if (has_ck505)
74cfd7ac 5123 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5124 else
74cfd7ac 5125 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5126
199e5d79 5127 if (has_panel) {
74cfd7ac
CW		 5128 val &= ~DREF_SSC_SOURCE_MASK;
5129 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5130
199e5d79 5131 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5132 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5133 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5134 val |= DREF_SSC1_ENABLE;
e77166b5 5135 } else
74cfd7ac 5136 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5137
5138 /* Get SSC going before enabling the outputs */
74cfd7ac 5139 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5140 POSTING_READ(PCH_DREF_CONTROL);
5141 udelay(200);
5142
74cfd7ac 5143 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5144
5145 /* Enable CPU source on CPU attached eDP */
199e5d79 5146 if (has_cpu_edp) {
99eb6a01 5147 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5148 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5149 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5150 }
13d83a67 5151 else
74cfd7ac 5152 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5153 } else
74cfd7ac 5154 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5155
74cfd7ac 5156 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5157 POSTING_READ(PCH_DREF_CONTROL);
5158 udelay(200);
5159 } else {
5160 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5161
74cfd7ac 5162 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5163
5164 /* Turn off CPU output */
74cfd7ac 5165 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5166
74cfd7ac 5167 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5168 POSTING_READ(PCH_DREF_CONTROL);
5169 udelay(200);
5170
5171 /* Turn off the SSC source */
74cfd7ac
CW		 5172 val &= ~DREF_SSC_SOURCE_MASK;
5173 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5174
5175 /* Turn off SSC1 */
74cfd7ac 5176 val &= ~DREF_SSC1_ENABLE;
199e5d79 5177
74cfd7ac 5178 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5179 POSTING_READ(PCH_DREF_CONTROL);
5180 udelay(200);
5181 }
74cfd7ac
CW		 5182
5183 BUG_ON(val != final);
13d83a67
JB		 5184}
5185
dde86e2d
PZ		 5186/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5187static void lpt_init_pch_refclk(struct drm_device *dev)
5188{
5189 struct drm_i915_private *dev_priv = dev->dev_private;
5190 struct drm_mode_config *mode_config = &dev->mode_config;
5191 struct intel_encoder *encoder;
5192 bool has_vga = false;
5193 bool is_sdv = false;
5194 u32 tmp;
5195
5196 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5197 switch (encoder->type) {
5198 case INTEL_OUTPUT_ANALOG:
5199 has_vga = true;
5200 break;
5201 }
5202 }
5203
5204 if (!has_vga)
5205 return;
5206
c00db246
DV		 5207 mutex_lock(&dev_priv->dpio_lock);
5208
dde86e2d
PZ		 5209 /* XXX: Rip out SDV support once Haswell ships for real. */
5210 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5211 is_sdv = true;
5212
5213 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5214 tmp &= ~SBI_SSCCTL_DISABLE;
5215 tmp |= SBI_SSCCTL_PATHALT;
5216 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5217
5218 udelay(24);
5219
5220 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5221 tmp &= ~SBI_SSCCTL_PATHALT;
5222 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5223
5224 if (!is_sdv) {
5225 tmp = I915_READ(SOUTH_CHICKEN2);
5226 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5227 I915_WRITE(SOUTH_CHICKEN2, tmp);
5228
5229 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5230 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5231 DRM_ERROR("FDI mPHY reset assert timeout\n");
5232
5233 tmp = I915_READ(SOUTH_CHICKEN2);
5234 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5235 I915_WRITE(SOUTH_CHICKEN2, tmp);
5236
5237 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5238 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5239 100))
5240 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5241 }
5242
5243 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5244 tmp &= ~(0xFF << 24);
5245 tmp |= (0x12 << 24);
5246 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5247
dde86e2d
PZ		 5248 if (is_sdv) {
5249 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5250 tmp |= 0x7FFF;
5251 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5252 }
5253
5254 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5255 tmp |= (1 << 11);
5256 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5257
5258 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5259 tmp |= (1 << 11);
5260 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5261
5262 if (is_sdv) {
5263 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5264 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5265 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5266
5267 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5268 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5269 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5270
5271 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5272 tmp |= (0x3F << 8);
5273 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5274
5275 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5276 tmp |= (0x3F << 8);
5277 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5278 }
5279
5280 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5281 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5282 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5283
5284 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5285 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5286 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5287
5288 if (!is_sdv) {
5289 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5290 tmp &= ~(7 << 13);
5291 tmp |= (5 << 13);
5292 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5293
5294 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5295 tmp &= ~(7 << 13);
5296 tmp |= (5 << 13);
5297 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5298 }
5299
5300 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5301 tmp &= ~0xFF;
5302 tmp |= 0x1C;
5303 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5304
5305 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5306 tmp &= ~0xFF;
5307 tmp |= 0x1C;
5308 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5309
5310 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5311 tmp &= ~(0xFF << 16);
5312 tmp |= (0x1C << 16);
5313 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5314
5315 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5316 tmp &= ~(0xFF << 16);
5317 tmp |= (0x1C << 16);
5318 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5319
5320 if (!is_sdv) {
5321 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5322 tmp |= (1 << 27);
5323 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5324
5325 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5326 tmp |= (1 << 27);
5327 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5328
5329 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5330 tmp &= ~(0xF << 28);
5331 tmp |= (4 << 28);
5332 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5333
5334 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5335 tmp &= ~(0xF << 28);
5336 tmp |= (4 << 28);
5337 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5338 }
5339
5340 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5341 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5342 tmp |= SBI_DBUFF0_ENABLE;
5343 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5344
5345 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5346}
5347
5348/*
5349 * Initialize reference clocks when the driver loads
5350 */
5351void intel_init_pch_refclk(struct drm_device *dev)
5352{
5353 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5354 ironlake_init_pch_refclk(dev);
5355 else if (HAS_PCH_LPT(dev))
5356 lpt_init_pch_refclk(dev);
5357}
5358
d9d444cb
JB		 5359static int ironlake_get_refclk(struct drm_crtc *crtc)
5360{
5361 struct drm_device *dev = crtc->dev;
5362 struct drm_i915_private *dev_priv = dev->dev_private;
5363 struct intel_encoder *encoder;
d9d444cb
JB		 5364 int num_connectors = 0;
5365 bool is_lvds = false;
5366
6c2b7c12 5367 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5368 switch (encoder->type) {
5369 case INTEL_OUTPUT_LVDS:
5370 is_lvds = true;
5371 break;
d9d444cb
JB		 5372 }
5373 num_connectors++;
5374 }
5375
5376 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5377 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5378 dev_priv->vbt.lvds_ssc_freq);
5379 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5380 }
5381
5382 return 120000;
5383}
5384
6ff93609 5385static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5386{
c8203565 5387 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5389 int pipe = intel_crtc->pipe;
c8203565
PZ		 5390 uint32_t val;
5391
5392 val = I915_READ(PIPECONF(pipe));
5393
dfd07d72 5394 val &= ~PIPECONF_BPC_MASK;
965e0c48 5395 switch (intel_crtc->config.pipe_bpp) {
c8203565 5396 case 18:
dfd07d72 5397 val |= PIPECONF_6BPC;
c8203565
PZ		 5398 break;
5399 case 24:
dfd07d72 5400 val |= PIPECONF_8BPC;
c8203565
PZ		 5401 break;
5402 case 30:
dfd07d72 5403 val |= PIPECONF_10BPC;
c8203565
PZ		 5404 break;
5405 case 36:
dfd07d72 5406 val |= PIPECONF_12BPC;
c8203565
PZ		 5407 break;
5408 default:
cc769b62
PZ		 5409 /* Case prevented by intel_choose_pipe_bpp_dither. */
5410 BUG();
c8203565
PZ		 5411 }
5412
5413 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5414 if (intel_crtc->config.dither)
c8203565
PZ		 5415 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5416
5417 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5418 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5419 val |= PIPECONF_INTERLACED_ILK;
5420 else
5421 val |= PIPECONF_PROGRESSIVE;
5422
50f3b016 5423 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5424 val |= PIPECONF_COLOR_RANGE_SELECT;
5425 else
5426 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5427
c8203565
PZ		 5428 I915_WRITE(PIPECONF(pipe), val);
5429 POSTING_READ(PIPECONF(pipe));
5430}
5431
86d3efce
VS		 5432/*
5433 * Set up the pipe CSC unit.
5434 *
5435 * Currently only full range RGB to limited range RGB conversion
5436 * is supported, but eventually this should handle various
5437 * RGB<->YCbCr scenarios as well.
5438 */
50f3b016 5439static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5440{
5441 struct drm_device *dev = crtc->dev;
5442 struct drm_i915_private *dev_priv = dev->dev_private;
5443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5444 int pipe = intel_crtc->pipe;
5445 uint16_t coeff = 0x7800; /* 1.0 */
5446
5447 /*
5448 * TODO: Check what kind of values actually come out of the pipe
5449 * with these coeff/postoff values and adjust to get the best
5450 * accuracy. Perhaps we even need to take the bpc value into
5451 * consideration.
5452 */
5453
50f3b016 5454 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5455 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5456
5457 /*
5458 * GY/GU and RY/RU should be the other way around according
5459 * to BSpec, but reality doesn't agree. Just set them up in
5460 * a way that results in the correct picture.
5461 */
5462 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5463 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5464
5465 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5466 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5467
5468 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5469 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5470
5471 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5472 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5473 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5474
5475 if (INTEL_INFO(dev)->gen > 6) {
5476 uint16_t postoff = 0;
5477
50f3b016 5478 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5479 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5480
5481 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5482 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5483 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5484
5485 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5486 } else {
5487 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5488
50f3b016 5489 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5490 mode |= CSC_BLACK_SCREEN_OFFSET;
5491
5492 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5493 }
5494}
5495
6ff93609 5496static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5497{
5498 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5499 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5500 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5501 uint32_t val;
5502
702e7a56 5503 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5504
5505 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5506 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5507 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5508
5509 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5510 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5511 val |= PIPECONF_INTERLACED_ILK;
5512 else
5513 val |= PIPECONF_PROGRESSIVE;
5514
702e7a56
PZ		 5515 I915_WRITE(PIPECONF(cpu_transcoder), val);
5516 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5517}
5518
6591c6e4
PZ		 5519static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5520 struct drm_display_mode *adjusted_mode,
5521 intel_clock_t *clock,
5522 bool *has_reduced_clock,
5523 intel_clock_t *reduced_clock)
5524{
5525 struct drm_device *dev = crtc->dev;
5526 struct drm_i915_private *dev_priv = dev->dev_private;
5527 struct intel_encoder *intel_encoder;
5528 int refclk;
d4906093 5529 const intel_limit_t *limit;
a16af721 5530 bool ret, is_lvds = false;
79e53945 5531
6591c6e4
PZ		 5532 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5533 switch (intel_encoder->type) {
79e53945
JB		 5534 case INTEL_OUTPUT_LVDS:
5535 is_lvds = true;
5536 break;
79e53945
JB		 5537 }
5538 }
5539
d9d444cb 5540 refclk = ironlake_get_refclk(crtc);
79e53945 5541
d4906093
ML		 5542 /*
5543 * Returns a set of divisors for the desired target clock with the given
5544 * refclk, or FALSE. The returned values represent the clock equation:
5545 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5546 */
1b894b59 5547 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5548 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5549 clock);
5550 if (!ret)
5551 return false;
cda4b7d3 5552
ddc9003c 5553 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5554 /*
5555 * Ensure we match the reduced clock's P to the target clock.
5556 * If the clocks don't match, we can't switch the display clock
5557 * by using the FP0/FP1. In such case we will disable the LVDS
5558 * downclock feature.
5559 */
6591c6e4
PZ		 5560 *has_reduced_clock = limit->find_pll(limit, crtc,
5561 dev_priv->lvds_downclock,
5562 refclk,
5563 clock,
5564 reduced_clock);
652c393a 5565 }
61e9653f 5566
6591c6e4
PZ		 5567 return true;
5568}
5569
01a415fd
DV		 5570static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5571{
5572 struct drm_i915_private *dev_priv = dev->dev_private;
5573 uint32_t temp;
5574
5575 temp = I915_READ(SOUTH_CHICKEN1);
5576 if (temp & FDI_BC_BIFURCATION_SELECT)
5577 return;
5578
5579 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5580 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5581
5582 temp |= FDI_BC_BIFURCATION_SELECT;
5583 DRM_DEBUG_KMS("enabling fdi C rx\n");
5584 I915_WRITE(SOUTH_CHICKEN1, temp);
5585 POSTING_READ(SOUTH_CHICKEN1);
5586}
5587
ebfd86fd 5588static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5589{
5590 struct drm_device *dev = intel_crtc->base.dev;
5591 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5592
5593 switch (intel_crtc->pipe) {
5594 case PIPE_A:
ebfd86fd 5595 break;
01a415fd 5596 case PIPE_B:
ebfd86fd 5597 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5598 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5599 else
5600 cpt_enable_fdi_bc_bifurcation(dev);
5601
ebfd86fd 5602 break;
01a415fd 5603 case PIPE_C:
01a415fd
DV		 5604 cpt_enable_fdi_bc_bifurcation(dev);
5605
ebfd86fd 5606 break;
01a415fd
DV		 5607 default:
5608 BUG();
5609 }
5610}
5611
d4b1931c
PZ		 5612int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5613{
5614 /*
5615 * Account for spread spectrum to avoid
5616 * oversubscribing the link. Max center spread
5617 * is 2.5%; use 5% for safety's sake.
5618 */
5619 u32 bps = target_clock * bpp * 21 / 20;
5620 return bps / (link_bw * 8) + 1;
5621}
5622
7429e9d4 5623static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5624{
7429e9d4 5625 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5626}
5627
de13a2e3 5628static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5629 u32 *fp,
9a7c7890 5630 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5631{
de13a2e3 5632 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5633 struct drm_device *dev = crtc->dev;
5634 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5635 struct intel_encoder *intel_encoder;
5636 uint32_t dpll;
6cc5f341 5637 int factor, num_connectors = 0;
09ede541 5638 bool is_lvds = false, is_sdvo = false;
79e53945 5639
de13a2e3
PZ		 5640 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5641 switch (intel_encoder->type) {
79e53945
JB		 5642 case INTEL_OUTPUT_LVDS:
5643 is_lvds = true;
5644 break;
5645 case INTEL_OUTPUT_SDVO:
7d57382e 5646 case INTEL_OUTPUT_HDMI:
79e53945 5647 is_sdvo = true;
79e53945 5648 break;
79e53945 5649 }
43565a06 5650
c751ce4f 5651 num_connectors++;
79e53945 5652 }
79e53945 5653
c1858123 5654 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5655 factor = 21;
5656 if (is_lvds) {
5657 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5658 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5659 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5660 factor = 25;
09ede541 5661 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5662 factor = 20;
c1858123 5663
7429e9d4 5664 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5665 *fp |= FP_CB_TUNE;
2c07245f 5666
9a7c7890
DV		 5667 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5668 *fp2 |= FP_CB_TUNE;
5669
5eddb70b 5670 dpll = 0;
2c07245f 5671
a07d6787
EA		 5672 if (is_lvds)
5673 dpll |= DPLLB_MODE_LVDS;
5674 else
5675 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5676
5677 if (intel_crtc->config.pixel_multiplier > 1) {
5678 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5679 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5680 }
198a037f
DV		 5681
5682 if (is_sdvo)
5683 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5684 if (intel_crtc->config.has_dp_encoder)
a07d6787 5685 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5686
a07d6787 5687 /* compute bitmask from p1 value */
7429e9d4 5688 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5689 /* also FPA1 */
7429e9d4 5690 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5691
7429e9d4 5692 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5693 case 5:
5694 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5695 break;
5696 case 7:
5697 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5698 break;
5699 case 10:
5700 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5701 break;
5702 case 14:
5703 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5704 break;
79e53945
JB		 5705 }
5706
b4c09f3b 5707 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5708 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5709 else
5710 dpll |= PLL_REF_INPUT_DREFCLK;
5711
de13a2e3
PZ		 5712 return dpll;
5713}
5714
5715static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5716 int x, int y,
5717 struct drm_framebuffer *fb)
5718{
5719 struct drm_device *dev = crtc->dev;
5720 struct drm_i915_private *dev_priv = dev->dev_private;
5721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5722 struct drm_display_mode *adjusted_mode =
5723 &intel_crtc->config.adjusted_mode;
5724 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5725 int pipe = intel_crtc->pipe;
5726 int plane = intel_crtc->plane;
5727 int num_connectors = 0;
5728 intel_clock_t clock, reduced_clock;
cbbab5bd 5729 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5730 bool ok, has_reduced_clock = false;
8b47047b 5731 bool is_lvds = false;
de13a2e3 5732 struct intel_encoder *encoder;
de13a2e3 5733 int ret;
de13a2e3
PZ		 5734
5735 for_each_encoder_on_crtc(dev, crtc, encoder) {
5736 switch (encoder->type) {
5737 case INTEL_OUTPUT_LVDS:
5738 is_lvds = true;
5739 break;
de13a2e3
PZ		 5740 }
5741
5742 num_connectors++;
a07d6787 5743 }
79e53945 5744
5dc5298b
PZ		 5745 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5746 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5747
3b117c8f 5748 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5749
de13a2e3
PZ		 5750 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5751 &has_reduced_clock, &reduced_clock);
5752 if (!ok) {
5753 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5754 return -EINVAL;
79e53945 5755 }
f47709a9
DV		 5756 /* Compat-code for transition, will disappear. */
5757 if (!intel_crtc->config.clock_set) {
5758 intel_crtc->config.dpll.n = clock.n;
5759 intel_crtc->config.dpll.m1 = clock.m1;
5760 intel_crtc->config.dpll.m2 = clock.m2;
5761 intel_crtc->config.dpll.p1 = clock.p1;
5762 intel_crtc->config.dpll.p2 = clock.p2;
5763 }
79e53945 5764
de13a2e3
PZ		 5765 /* Ensure that the cursor is valid for the new mode before changing... */
5766 intel_crtc_update_cursor(crtc, true);
5767
84f44ce7 5768 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5769 drm_mode_debug_printmodeline(mode);
5770
5dc5298b 5771 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5772 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5773 struct intel_pch_pll *pll;
4b645f14 5774
7429e9d4 5775 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5776 if (has_reduced_clock)
7429e9d4 5777 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5778
7429e9d4 5779 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5780 &fp, &reduced_clock,
5781 has_reduced_clock ? &fp2 : NULL);
5782
ee7b9f93
JB		 5783 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5784 if (pll == NULL) {
84f44ce7
VS		 5785 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5786 pipe_name(pipe));
4b645f14
JB		 5787 return -EINVAL;
5788 }
ee7b9f93
JB		 5789 } else
5790 intel_put_pch_pll(intel_crtc);
79e53945 5791
03afc4a2
DV		 5792 if (intel_crtc->config.has_dp_encoder)
5793 intel_dp_set_m_n(intel_crtc);
79e53945 5794
dafd226c
DV		 5795 for_each_encoder_on_crtc(dev, crtc, encoder)
5796 if (encoder->pre_pll_enable)
5797 encoder->pre_pll_enable(encoder);
79e53945 5798
ee7b9f93
JB		 5799 if (intel_crtc->pch_pll) {
5800 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5801
32f9d658 5802 /* Wait for the clocks to stabilize. */
ee7b9f93 5803 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5804 udelay(150);
5805
8febb297
EA		 5806 /* The pixel multiplier can only be updated once the
5807 * DPLL is enabled and the clocks are stable.
5808 *
5809 * So write it again.
5810 */
ee7b9f93 5811 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5812 }
79e53945 5813
5eddb70b 5814 intel_crtc->lowfreq_avail = false;
ee7b9f93 5815 if (intel_crtc->pch_pll) {
4b645f14 5816 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5817 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5818 intel_crtc->lowfreq_avail = true;
4b645f14 5819 } else {
ee7b9f93 5820 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5821 }
5822 }
5823
b0e77b9c 5824 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5825
ca3a0ff8 5826 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5827 intel_cpu_transcoder_set_m_n(intel_crtc,
5828 &intel_crtc->config.fdi_m_n);
5829 }
2c07245f 5830
ebfd86fd
DV		 5831 if (IS_IVYBRIDGE(dev))
5832 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5833
6ff93609 5834 ironlake_set_pipeconf(crtc);
79e53945 5835
a1f9e77e
PZ		 5836 /* Set up the display plane register */
5837 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5838 POSTING_READ(DSPCNTR(plane));
79e53945 5839
94352cf9 5840 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5841
5842 intel_update_watermarks(dev);
5843
1f8eeabf
ED		 5844 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5845
1857e1da 5846 return ret;
79e53945
JB		 5847}
5848
72419203
DV		 5849static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5850 struct intel_crtc_config *pipe_config)
5851{
5852 struct drm_device *dev = crtc->base.dev;
5853 struct drm_i915_private *dev_priv = dev->dev_private;
5854 enum transcoder transcoder = pipe_config->cpu_transcoder;
5855
5856 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5857 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5858 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5859 & ~TU_SIZE_MASK;
5860 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5861 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5862 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5863}
5864
2fa2fe9a
DV		 5865static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5866 struct intel_crtc_config *pipe_config)
5867{
5868 struct drm_device *dev = crtc->base.dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 uint32_t tmp;
5871
5872 tmp = I915_READ(PF_CTL(crtc->pipe));
5873
5874 if (tmp & PF_ENABLE) {
5875 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5876 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5877 }
79e53945
JB		 5878}
5879
0e8ffe1b
DV		 5880static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5881 struct intel_crtc_config *pipe_config)
5882{
5883 struct drm_device *dev = crtc->base.dev;
5884 struct drm_i915_private *dev_priv = dev->dev_private;
5885 uint32_t tmp;
5886
5887 tmp = I915_READ(PIPECONF(crtc->pipe));
5888 if (!(tmp & PIPECONF_ENABLE))
5889 return false;
5890
ab9412ba 5891 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5892 pipe_config->has_pch_encoder = true;
5893
627eb5a3
DV		 5894 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5895 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5896 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5897
5898 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5899 }
5900
1bd1bd80
DV		 5901 intel_get_pipe_timings(crtc, pipe_config);
5902
2fa2fe9a
DV		 5903 ironlake_get_pfit_config(crtc, pipe_config);
5904
0e8ffe1b
DV		 5905 return true;
5906}
5907
d6dd9eb1
DV		 5908static void haswell_modeset_global_resources(struct drm_device *dev)
5909{
d6dd9eb1
DV		 5910 bool enable = false;
5911 struct intel_crtc *crtc;
5912 struct intel_encoder *encoder;
5913
5914 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5915 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5916 enable = true;
5917 /* XXX: Should check for edp transcoder here, but thanks to init
5918 * sequence that's not yet available. Just in case desktop eDP
5919 * on PORT D is possible on haswell, too. */
b074cec8 5920 /* Even the eDP panel fitter is outside the always-on well. */
2b87f3b1 5921 if (crtc->config.pch_pfit.size && crtc->base.enabled)
b074cec8 5922 enable = true;
d6dd9eb1
DV		 5923 }
5924
5925 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5926 base.head) {
5927 if (encoder->type != INTEL_OUTPUT_EDP &&
5928 encoder->connectors_active)
5929 enable = true;
5930 }
5931
d6dd9eb1
DV		 5932 intel_set_power_well(dev, enable);
5933}
5934
09b4ddf9 5935static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5936 int x, int y,
5937 struct drm_framebuffer *fb)
5938{
5939 struct drm_device *dev = crtc->dev;
5940 struct drm_i915_private *dev_priv = dev->dev_private;
5941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5942 struct drm_display_mode *adjusted_mode =
5943 &intel_crtc->config.adjusted_mode;
5944 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5945 int pipe = intel_crtc->pipe;
5946 int plane = intel_crtc->plane;
5947 int num_connectors = 0;
8b47047b 5948 bool is_cpu_edp = false;
09b4ddf9 5949 struct intel_encoder *encoder;
09b4ddf9 5950 int ret;
09b4ddf9
PZ		 5951
5952 for_each_encoder_on_crtc(dev, crtc, encoder) {
5953 switch (encoder->type) {
09b4ddf9 5954 case INTEL_OUTPUT_EDP:
d8e8b582 5955 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
09b4ddf9
PZ		 5956 is_cpu_edp = true;
5957 break;
5958 }
5959
5960 num_connectors++;
5961 }
5962
bba2181c 5963 if (is_cpu_edp)
3b117c8f 5964 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5965 else
3b117c8f 5966 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5967
5dc5298b
PZ		 5968 /* We are not sure yet this won't happen. */
5969 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5970 INTEL_PCH_TYPE(dev));
5971
5972 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5973 num_connectors, pipe_name(pipe));
5974
3b117c8f 5975 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5976 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5977
5978 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5979
6441ab5f
PZ		 5980 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5981 return -EINVAL;
5982
09b4ddf9
PZ		 5983 /* Ensure that the cursor is valid for the new mode before changing... */
5984 intel_crtc_update_cursor(crtc, true);
5985
84f44ce7 5986 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5987 drm_mode_debug_printmodeline(mode);
5988
03afc4a2
DV		 5989 if (intel_crtc->config.has_dp_encoder)
5990 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5991
5992 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5993
5994 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5995
ca3a0ff8 5996 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5997 intel_cpu_transcoder_set_m_n(intel_crtc,
5998 &intel_crtc->config.fdi_m_n);
5999 }
09b4ddf9 6000
6ff93609 6001 haswell_set_pipeconf(crtc);
09b4ddf9 6002
50f3b016 6003 intel_set_pipe_csc(crtc);
86d3efce 6004
09b4ddf9 6005 /* Set up the display plane register */
86d3efce 6006 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6007 POSTING_READ(DSPCNTR(plane));
6008
6009 ret = intel_pipe_set_base(crtc, x, y, fb);
6010
6011 intel_update_watermarks(dev);
6012
6013 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
6014
1f803ee5 6015 return ret;
79e53945
JB		 6016}
6017
0e8ffe1b
DV		 6018static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6019 struct intel_crtc_config *pipe_config)
6020{
6021 struct drm_device *dev = crtc->base.dev;
6022 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 6023 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2fa2fe9a 6024 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6025 uint32_t tmp;
6026
b97186f0
PZ		 6027 if (!intel_display_power_enabled(dev,
6028 POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
2bfce950
PZ		 6029 return false;
6030
6031 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 6032 if (!(tmp & PIPECONF_ENABLE))
6033 return false;
6034
88adfff1 6035 /*
f196e6be 6036 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6037 * DDI E. So just check whether this pipe is wired to DDI E and whether
6038 * the PCH transcoder is on.
6039 */
f196e6be 6040 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1 6041 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6042 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6043 pipe_config->has_pch_encoder = true;
6044
627eb5a3
DV		 6045 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6046 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6047 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6048
6049 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6050 }
6051
1bd1bd80
DV		 6052 intel_get_pipe_timings(crtc, pipe_config);
6053
2fa2fe9a
DV		 6054 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6055 if (intel_display_power_enabled(dev, pfit_domain))
6056 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6057
0e8ffe1b
DV		 6058 return true;
6059}
6060
f564048e 6061static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6062 int x, int y,
94352cf9 6063 struct drm_framebuffer *fb)
f564048e
EA		 6064{
6065 struct drm_device *dev = crtc->dev;
6066 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6067 struct drm_encoder_helper_funcs *encoder_funcs;
6068 struct intel_encoder *encoder;
0b701d27 6069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6070 struct drm_display_mode *adjusted_mode =
6071 &intel_crtc->config.adjusted_mode;
6072 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6073 int pipe = intel_crtc->pipe;
f564048e
EA		 6074 int ret;
6075
0b701d27 6076 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6077
b8cecdf5
DV		 6078 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6079
79e53945 6080 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6081
9256aa19
DV		 6082 if (ret != 0)
6083 return ret;
6084
6085 for_each_encoder_on_crtc(dev, crtc, encoder) {
6086 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6087 encoder->base.base.id,
6088 drm_get_encoder_name(&encoder->base),
6089 mode->base.id, mode->name);
6cc5f341
DV		 6090 if (encoder->mode_set) {
6091 encoder->mode_set(encoder);
6092 } else {
6093 encoder_funcs = encoder->base.helper_private;
6094 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6095 }
9256aa19
DV		 6096 }
6097
6098 return 0;
79e53945
JB		 6099}
6100
3a9627f4
WF		 6101static bool intel_eld_uptodate(struct drm_connector *connector,
6102 int reg_eldv, uint32_t bits_eldv,
6103 int reg_elda, uint32_t bits_elda,
6104 int reg_edid)
6105{
6106 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6107 uint8_t *eld = connector->eld;
6108 uint32_t i;
6109
6110 i = I915_READ(reg_eldv);
6111 i &= bits_eldv;
6112
6113 if (!eld[0])
6114 return !i;
6115
6116 if (!i)
6117 return false;
6118
6119 i = I915_READ(reg_elda);
6120 i &= ~bits_elda;
6121 I915_WRITE(reg_elda, i);
6122
6123 for (i = 0; i < eld[2]; i++)
6124 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6125 return false;
6126
6127 return true;
6128}
6129
e0dac65e
WF		 6130static void g4x_write_eld(struct drm_connector *connector,
6131 struct drm_crtc *crtc)
6132{
6133 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6134 uint8_t *eld = connector->eld;
6135 uint32_t eldv;
6136 uint32_t len;
6137 uint32_t i;
6138
6139 i = I915_READ(G4X_AUD_VID_DID);
6140
6141 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6142 eldv = G4X_ELDV_DEVCL_DEVBLC;
6143 else
6144 eldv = G4X_ELDV_DEVCTG;
6145
3a9627f4
WF		 6146 if (intel_eld_uptodate(connector,
6147 G4X_AUD_CNTL_ST, eldv,
6148 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6149 G4X_HDMIW_HDMIEDID))
6150 return;
6151
e0dac65e
WF		 6152 i = I915_READ(G4X_AUD_CNTL_ST);
6153 i &= ~(eldv | G4X_ELD_ADDR);
6154 len = (i >> 9) & 0x1f; /* ELD buffer size */
6155 I915_WRITE(G4X_AUD_CNTL_ST, i);
6156
6157 if (!eld[0])
6158 return;
6159
6160 len = min_t(uint8_t, eld[2], len);
6161 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6162 for (i = 0; i < len; i++)
6163 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6164
6165 i = I915_READ(G4X_AUD_CNTL_ST);
6166 i |= eldv;
6167 I915_WRITE(G4X_AUD_CNTL_ST, i);
6168}
6169
83358c85
WX		 6170static void haswell_write_eld(struct drm_connector *connector,
6171 struct drm_crtc *crtc)
6172{
6173 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6174 uint8_t *eld = connector->eld;
6175 struct drm_device *dev = crtc->dev;
7b9f35a6 6176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6177 uint32_t eldv;
6178 uint32_t i;
6179 int len;
6180 int pipe = to_intel_crtc(crtc)->pipe;
6181 int tmp;
6182
6183 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6184 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6185 int aud_config = HSW_AUD_CFG(pipe);
6186 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6187
6188
6189 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6190
6191 /* Audio output enable */
6192 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6193 tmp = I915_READ(aud_cntrl_st2);
6194 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6195 I915_WRITE(aud_cntrl_st2, tmp);
6196
6197 /* Wait for 1 vertical blank */
6198 intel_wait_for_vblank(dev, pipe);
6199
6200 /* Set ELD valid state */
6201 tmp = I915_READ(aud_cntrl_st2);
6202 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6203 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6204 I915_WRITE(aud_cntrl_st2, tmp);
6205 tmp = I915_READ(aud_cntrl_st2);
6206 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6207
6208 /* Enable HDMI mode */
6209 tmp = I915_READ(aud_config);
6210 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6211 /* clear N_programing_enable and N_value_index */
6212 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6213 I915_WRITE(aud_config, tmp);
6214
6215 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6216
6217 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6218 intel_crtc->eld_vld = true;
83358c85
WX		 6219
6220 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6221 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6222 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6223 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6224 } else
6225 I915_WRITE(aud_config, 0);
6226
6227 if (intel_eld_uptodate(connector,
6228 aud_cntrl_st2, eldv,
6229 aud_cntl_st, IBX_ELD_ADDRESS,
6230 hdmiw_hdmiedid))
6231 return;
6232
6233 i = I915_READ(aud_cntrl_st2);
6234 i &= ~eldv;
6235 I915_WRITE(aud_cntrl_st2, i);
6236
6237 if (!eld[0])
6238 return;
6239
6240 i = I915_READ(aud_cntl_st);
6241 i &= ~IBX_ELD_ADDRESS;
6242 I915_WRITE(aud_cntl_st, i);
6243 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6244 DRM_DEBUG_DRIVER("port num:%d\n", i);
6245
6246 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6247 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6248 for (i = 0; i < len; i++)
6249 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6250
6251 i = I915_READ(aud_cntrl_st2);
6252 i |= eldv;
6253 I915_WRITE(aud_cntrl_st2, i);
6254
6255}
6256
e0dac65e
WF		 6257static void ironlake_write_eld(struct drm_connector *connector,
6258 struct drm_crtc *crtc)
6259{
6260 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6261 uint8_t *eld = connector->eld;
6262 uint32_t eldv;
6263 uint32_t i;
6264 int len;
6265 int hdmiw_hdmiedid;
b6daa025 6266 int aud_config;
e0dac65e
WF		 6267 int aud_cntl_st;
6268 int aud_cntrl_st2;
9b138a83 6269 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6270
b3f33cbf 6271 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6272 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6273 aud_config = IBX_AUD_CFG(pipe);
6274 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6275 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6276 } else {
9b138a83
WX		 6277 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6278 aud_config = CPT_AUD_CFG(pipe);
6279 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6280 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6281 }
6282
9b138a83 6283 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6284
6285 i = I915_READ(aud_cntl_st);
9b138a83 6286 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6287 if (!i) {
6288 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6289 /* operate blindly on all ports */
1202b4c6
WF		 6290 eldv = IBX_ELD_VALIDB;
6291 eldv |= IBX_ELD_VALIDB << 4;
6292 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6293 } else {
2582a850 6294 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6295 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6296 }
6297
3a9627f4
WF		 6298 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6299 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6300 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6301 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6302 } else
6303 I915_WRITE(aud_config, 0);
e0dac65e 6304
3a9627f4
WF		 6305 if (intel_eld_uptodate(connector,
6306 aud_cntrl_st2, eldv,
6307 aud_cntl_st, IBX_ELD_ADDRESS,
6308 hdmiw_hdmiedid))
6309 return;
6310
e0dac65e
WF		 6311 i = I915_READ(aud_cntrl_st2);
6312 i &= ~eldv;
6313 I915_WRITE(aud_cntrl_st2, i);
6314
6315 if (!eld[0])
6316 return;
6317
e0dac65e 6318 i = I915_READ(aud_cntl_st);
1202b4c6 6319 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6320 I915_WRITE(aud_cntl_st, i);
6321
6322 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6323 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6324 for (i = 0; i < len; i++)
6325 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6326
6327 i = I915_READ(aud_cntrl_st2);
6328 i |= eldv;
6329 I915_WRITE(aud_cntrl_st2, i);
6330}
6331
6332void intel_write_eld(struct drm_encoder *encoder,
6333 struct drm_display_mode *mode)
6334{
6335 struct drm_crtc *crtc = encoder->crtc;
6336 struct drm_connector *connector;
6337 struct drm_device *dev = encoder->dev;
6338 struct drm_i915_private *dev_priv = dev->dev_private;
6339
6340 connector = drm_select_eld(encoder, mode);
6341 if (!connector)
6342 return;
6343
6344 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6345 connector->base.id,
6346 drm_get_connector_name(connector),
6347 connector->encoder->base.id,
6348 drm_get_encoder_name(connector->encoder));
6349
6350 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6351
6352 if (dev_priv->display.write_eld)
6353 dev_priv->display.write_eld(connector, crtc);
6354}
6355
79e53945
JB		 6356/** Loads the palette/gamma unit for the CRTC with the prepared values */
6357void intel_crtc_load_lut(struct drm_crtc *crtc)
6358{
6359 struct drm_device *dev = crtc->dev;
6360 struct drm_i915_private *dev_priv = dev->dev_private;
6361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6362 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6363 int i;
6364
6365 /* The clocks have to be on to load the palette. */
aed3f09d 6366 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6367 return;
6368
f2b115e6 6369 /* use legacy palette for Ironlake */
bad720ff 6370 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6371 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6372
79e53945
JB		 6373 for (i = 0; i < 256; i++) {
6374 I915_WRITE(palreg + 4 * i,
6375 (intel_crtc->lut_r[i] << 16) |
6376 (intel_crtc->lut_g[i] << 8) |
6377 intel_crtc->lut_b[i]);
6378 }
6379}
6380
560b85bb
CW		 6381static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6382{
6383 struct drm_device *dev = crtc->dev;
6384 struct drm_i915_private *dev_priv = dev->dev_private;
6385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386 bool visible = base != 0;
6387 u32 cntl;
6388
6389 if (intel_crtc->cursor_visible == visible)
6390 return;
6391
9db4a9c7 6392 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6393 if (visible) {
6394 /* On these chipsets we can only modify the base whilst
6395 * the cursor is disabled.
6396 */
9db4a9c7 6397 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6398
6399 cntl &= ~(CURSOR_FORMAT_MASK);
6400 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6401 cntl |= CURSOR_ENABLE |
6402 CURSOR_GAMMA_ENABLE |
6403 CURSOR_FORMAT_ARGB;
6404 } else
6405 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6406 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6407
6408 intel_crtc->cursor_visible = visible;
6409}
6410
6411static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6412{
6413 struct drm_device *dev = crtc->dev;
6414 struct drm_i915_private *dev_priv = dev->dev_private;
6415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6416 int pipe = intel_crtc->pipe;
6417 bool visible = base != 0;
6418
6419 if (intel_crtc->cursor_visible != visible) {
548f245b 6420 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6421 if (base) {
6422 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6423 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6424 cntl |= pipe << 28; /* Connect to correct pipe */
6425 } else {
6426 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6427 cntl |= CURSOR_MODE_DISABLE;
6428 }
9db4a9c7 6429 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6430
6431 intel_crtc->cursor_visible = visible;
6432 }
6433 /* and commit changes on next vblank */
9db4a9c7 6434 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6435}
6436
65a21cd6
JB		 6437static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6438{
6439 struct drm_device *dev = crtc->dev;
6440 struct drm_i915_private *dev_priv = dev->dev_private;
6441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6442 int pipe = intel_crtc->pipe;
6443 bool visible = base != 0;
6444
6445 if (intel_crtc->cursor_visible != visible) {
6446 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6447 if (base) {
6448 cntl &= ~CURSOR_MODE;
6449 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6450 } else {
6451 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6452 cntl |= CURSOR_MODE_DISABLE;
6453 }
86d3efce
VS		 6454 if (IS_HASWELL(dev))
6455 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6456 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6457
6458 intel_crtc->cursor_visible = visible;
6459 }
6460 /* and commit changes on next vblank */
6461 I915_WRITE(CURBASE_IVB(pipe), base);
6462}
6463
cda4b7d3 6464/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6465static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6466 bool on)
cda4b7d3
CW		 6467{
6468 struct drm_device *dev = crtc->dev;
6469 struct drm_i915_private *dev_priv = dev->dev_private;
6470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6471 int pipe = intel_crtc->pipe;
6472 int x = intel_crtc->cursor_x;
6473 int y = intel_crtc->cursor_y;
560b85bb 6474 u32 base, pos;
cda4b7d3
CW		 6475 bool visible;
6476
6477 pos = 0;
6478
6b383a7f 6479 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6480 base = intel_crtc->cursor_addr;
6481 if (x > (int) crtc->fb->width)
6482 base = 0;
6483
6484 if (y > (int) crtc->fb->height)
6485 base = 0;
6486 } else
6487 base = 0;
6488
6489 if (x < 0) {
6490 if (x + intel_crtc->cursor_width < 0)
6491 base = 0;
6492
6493 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6494 x = -x;
6495 }
6496 pos |= x << CURSOR_X_SHIFT;
6497
6498 if (y < 0) {
6499 if (y + intel_crtc->cursor_height < 0)
6500 base = 0;
6501
6502 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6503 y = -y;
6504 }
6505 pos |= y << CURSOR_Y_SHIFT;
6506
6507 visible = base != 0;
560b85bb 6508 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6509 return;
6510
0cd83aa9 6511 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6512 I915_WRITE(CURPOS_IVB(pipe), pos);
6513 ivb_update_cursor(crtc, base);
6514 } else {
6515 I915_WRITE(CURPOS(pipe), pos);
6516 if (IS_845G(dev) || IS_I865G(dev))
6517 i845_update_cursor(crtc, base);
6518 else
6519 i9xx_update_cursor(crtc, base);
6520 }
cda4b7d3
CW		 6521}
6522
79e53945 6523static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6524 struct drm_file *file,
79e53945
JB		 6525 uint32_t handle,
6526 uint32_t width, uint32_t height)
6527{
6528 struct drm_device *dev = crtc->dev;
6529 struct drm_i915_private *dev_priv = dev->dev_private;
6530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6531 struct drm_i915_gem_object *obj;
cda4b7d3 6532 uint32_t addr;
3f8bc370 6533 int ret;
79e53945 6534
79e53945
JB		 6535 /* if we want to turn off the cursor ignore width and height */
6536 if (!handle) {
28c97730 6537 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6538 addr = 0;
05394f39 6539 obj = NULL;
5004417d 6540 mutex_lock(&dev->struct_mutex);
3f8bc370 6541 goto finish;
79e53945
JB		 6542 }
6543
6544 /* Currently we only support 64x64 cursors */
6545 if (width != 64 || height != 64) {
6546 DRM_ERROR("we currently only support 64x64 cursors\n");
6547 return -EINVAL;
6548 }
6549
05394f39 6550 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6551 if (&obj->base == NULL)
79e53945
JB		 6552 return -ENOENT;
6553
05394f39 6554 if (obj->base.size < width * height * 4) {
79e53945 6555 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6556 ret = -ENOMEM;
6557 goto fail;
79e53945
JB		 6558 }
6559
71acb5eb 6560 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6561 mutex_lock(&dev->struct_mutex);
b295d1b6 6562 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6563 unsigned alignment;
6564
d9e86c0e
CW		 6565 if (obj->tiling_mode) {
6566 DRM_ERROR("cursor cannot be tiled\n");
6567 ret = -EINVAL;
6568 goto fail_locked;
6569 }
6570
693db184
CW		 6571 /* Note that the w/a also requires 2 PTE of padding following
6572 * the bo. We currently fill all unused PTE with the shadow
6573 * page and so we should always have valid PTE following the
6574 * cursor preventing the VT-d warning.
6575 */
6576 alignment = 0;
6577 if (need_vtd_wa(dev))
6578 alignment = 64*1024;
6579
6580 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6581 if (ret) {
6582 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6583 goto fail_locked;
e7b526bb
CW		 6584 }
6585
d9e86c0e
CW		 6586 ret = i915_gem_object_put_fence(obj);
6587 if (ret) {
2da3b9b9 6588 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6589 goto fail_unpin;
6590 }
6591
05394f39 6592 addr = obj->gtt_offset;
71acb5eb 6593 } else {
6eeefaf3 6594 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6595 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6596 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6597 align);
71acb5eb
DA		 6598 if (ret) {
6599 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6600 goto fail_locked;
71acb5eb 6601 }
05394f39 6602 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6603 }
6604
a6c45cf0 6605 if (IS_GEN2(dev))
14b60391
JB		 6606 I915_WRITE(CURSIZE, (height << 12) | width);
6607
3f8bc370 6608 finish:
3f8bc370 6609 if (intel_crtc->cursor_bo) {
b295d1b6 6610 if (dev_priv->info->cursor_needs_physical) {
05394f39 6611 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6612 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6613 } else
6614 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6615 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6616 }
80824003 6617
7f9872e0 6618 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6619
6620 intel_crtc->cursor_addr = addr;
05394f39 6621 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6622 intel_crtc->cursor_width = width;
6623 intel_crtc->cursor_height = height;
6624
6b383a7f 6625 intel_crtc_update_cursor(crtc, true);
3f8bc370 6626
79e53945 6627 return 0;
e7b526bb 6628fail_unpin:
05394f39 6629 i915_gem_object_unpin(obj);
7f9872e0 6630fail_locked:
34b8686e 6631 mutex_unlock(&dev->struct_mutex);
bc9025bd 6632fail:
05394f39 6633 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6634 return ret;
79e53945
JB		 6635}
6636
6637static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6638{
79e53945 6639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6640
cda4b7d3
CW		 6641 intel_crtc->cursor_x = x;
6642 intel_crtc->cursor_y = y;
652c393a 6643
6b383a7f 6644 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6645
6646 return 0;
6647}
6648
6649/** Sets the color ramps on behalf of RandR */
6650void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6651 u16 blue, int regno)
6652{
6653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654
6655 intel_crtc->lut_r[regno] = red >> 8;
6656 intel_crtc->lut_g[regno] = green >> 8;
6657 intel_crtc->lut_b[regno] = blue >> 8;
6658}
6659
b8c00ac5
DA		 6660void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6661 u16 *blue, int regno)
6662{
6663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6664
6665 *red = intel_crtc->lut_r[regno] << 8;
6666 *green = intel_crtc->lut_g[regno] << 8;
6667 *blue = intel_crtc->lut_b[regno] << 8;
6668}
6669
79e53945 6670static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6671 u16 *blue, uint32_t start, uint32_t size)
79e53945 6672{
7203425a 6673 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6675
7203425a 6676 for (i = start; i < end; i++) {
79e53945
JB		 6677 intel_crtc->lut_r[i] = red[i] >> 8;
6678 intel_crtc->lut_g[i] = green[i] >> 8;
6679 intel_crtc->lut_b[i] = blue[i] >> 8;
6680 }
6681
6682 intel_crtc_load_lut(crtc);
6683}
6684
79e53945
JB		 6685/* VESA 640x480x72Hz mode to set on the pipe */
6686static struct drm_display_mode load_detect_mode = {
6687 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6688 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6689};
6690
d2dff872
CW		 6691static struct drm_framebuffer *
6692intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6693 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6694 struct drm_i915_gem_object *obj)
6695{
6696 struct intel_framebuffer *intel_fb;
6697 int ret;
6698
6699 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6700 if (!intel_fb) {
6701 drm_gem_object_unreference_unlocked(&obj->base);
6702 return ERR_PTR(-ENOMEM);
6703 }
6704
6705 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6706 if (ret) {
6707 drm_gem_object_unreference_unlocked(&obj->base);
6708 kfree(intel_fb);
6709 return ERR_PTR(ret);
6710 }
6711
6712 return &intel_fb->base;
6713}
6714
6715static u32
6716intel_framebuffer_pitch_for_width(int width, int bpp)
6717{
6718 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6719 return ALIGN(pitch, 64);
6720}
6721
6722static u32
6723intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6724{
6725 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6726 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6727}
6728
6729static struct drm_framebuffer *
6730intel_framebuffer_create_for_mode(struct drm_device *dev,
6731 struct drm_display_mode *mode,
6732 int depth, int bpp)
6733{
6734 struct drm_i915_gem_object *obj;
0fed39bd 6735 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6736
6737 obj = i915_gem_alloc_object(dev,
6738 intel_framebuffer_size_for_mode(mode, bpp));
6739 if (obj == NULL)
6740 return ERR_PTR(-ENOMEM);
6741
6742 mode_cmd.width = mode->hdisplay;
6743 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6744 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6745 bpp);
5ca0c34a 6746 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6747
6748 return intel_framebuffer_create(dev, &mode_cmd, obj);
6749}
6750
6751static struct drm_framebuffer *
6752mode_fits_in_fbdev(struct drm_device *dev,
6753 struct drm_display_mode *mode)
6754{
6755 struct drm_i915_private *dev_priv = dev->dev_private;
6756 struct drm_i915_gem_object *obj;
6757 struct drm_framebuffer *fb;
6758
6759 if (dev_priv->fbdev == NULL)
6760 return NULL;
6761
6762 obj = dev_priv->fbdev->ifb.obj;
6763 if (obj == NULL)
6764 return NULL;
6765
6766 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6767 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6768 fb->bits_per_pixel))
d2dff872
CW		 6769 return NULL;
6770
01f2c773 6771 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6772 return NULL;
6773
6774 return fb;
6775}
6776
d2434ab7 6777bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6778 struct drm_display_mode *mode,
8261b191 6779 struct intel_load_detect_pipe *old)
79e53945
JB		 6780{
6781 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6782 struct intel_encoder *intel_encoder =
6783 intel_attached_encoder(connector);
79e53945 6784 struct drm_crtc *possible_crtc;
4ef69c7a 6785 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6786 struct drm_crtc *crtc = NULL;
6787 struct drm_device *dev = encoder->dev;
94352cf9 6788 struct drm_framebuffer *fb;
79e53945
JB		 6789 int i = -1;
6790
d2dff872
CW		 6791 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6792 connector->base.id, drm_get_connector_name(connector),
6793 encoder->base.id, drm_get_encoder_name(encoder));
6794
79e53945
JB		 6795 /*
6796 * Algorithm gets a little messy:
7a5e4805 6797 *
79e53945
JB		 6798 * - if the connector already has an assigned crtc, use it (but make
6799 * sure it's on first)
7a5e4805 6800 *
79e53945
JB		 6801 * - try to find the first unused crtc that can drive this connector,
6802 * and use that if we find one
79e53945
JB		 6803 */
6804
6805 /* See if we already have a CRTC for this connector */
6806 if (encoder->crtc) {
6807 crtc = encoder->crtc;
8261b191 6808
7b24056b
DV		 6809 mutex_lock(&crtc->mutex);
6810
24218aac 6811 old->dpms_mode = connector->dpms;
8261b191
CW		 6812 old->load_detect_temp = false;
6813
6814 /* Make sure the crtc and connector are running */
24218aac
DV		 6815 if (connector->dpms != DRM_MODE_DPMS_ON)
6816 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6817
7173188d 6818 return true;
79e53945
JB		 6819 }
6820
6821 /* Find an unused one (if possible) */
6822 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6823 i++;
6824 if (!(encoder->possible_crtcs & (1 << i)))
6825 continue;
6826 if (!possible_crtc->enabled) {
6827 crtc = possible_crtc;
6828 break;
6829 }
79e53945
JB		 6830 }
6831
6832 /*
6833 * If we didn't find an unused CRTC, don't use any.
6834 */
6835 if (!crtc) {
7173188d
CW		 6836 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6837 return false;
79e53945
JB		 6838 }
6839
7b24056b 6840 mutex_lock(&crtc->mutex);
fc303101
DV		 6841 intel_encoder->new_crtc = to_intel_crtc(crtc);
6842 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6843
6844 intel_crtc = to_intel_crtc(crtc);
24218aac 6845 old->dpms_mode = connector->dpms;
8261b191 6846 old->load_detect_temp = true;
d2dff872 6847 old->release_fb = NULL;
79e53945 6848
6492711d
CW		 6849 if (!mode)
6850 mode = &load_detect_mode;
79e53945 6851
d2dff872
CW		 6852 /* We need a framebuffer large enough to accommodate all accesses
6853 * that the plane may generate whilst we perform load detection.
6854 * We can not rely on the fbcon either being present (we get called
6855 * during its initialisation to detect all boot displays, or it may
6856 * not even exist) or that it is large enough to satisfy the
6857 * requested mode.
6858 */
94352cf9
DV		 6859 fb = mode_fits_in_fbdev(dev, mode);
6860 if (fb == NULL) {
d2dff872 6861 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6862 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6863 old->release_fb = fb;
d2dff872
CW		 6864 } else
6865 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6866 if (IS_ERR(fb)) {
d2dff872 6867 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6868 mutex_unlock(&crtc->mutex);
0e8b3d3e 6869 return false;
79e53945 6870 }
79e53945 6871
c0c36b94 6872 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6873 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6874 if (old->release_fb)
6875 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6876 mutex_unlock(&crtc->mutex);
0e8b3d3e 6877 return false;
79e53945 6878 }
7173188d 6879
79e53945 6880 /* let the connector get through one full cycle before testing */
9d0498a2 6881 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6882 return true;
79e53945
JB		 6883}
6884
d2434ab7 6885void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6886 struct intel_load_detect_pipe *old)
79e53945 6887{
d2434ab7
DV		 6888 struct intel_encoder *intel_encoder =
6889 intel_attached_encoder(connector);
4ef69c7a 6890 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6891 struct drm_crtc *crtc = encoder->crtc;
79e53945 6892
d2dff872
CW		 6893 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6894 connector->base.id, drm_get_connector_name(connector),
6895 encoder->base.id, drm_get_encoder_name(encoder));
6896
8261b191 6897 if (old->load_detect_temp) {
fc303101
DV		 6898 to_intel_connector(connector)->new_encoder = NULL;
6899 intel_encoder->new_crtc = NULL;
6900 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6901
36206361
DV		 6902 if (old->release_fb) {
6903 drm_framebuffer_unregister_private(old->release_fb);
6904 drm_framebuffer_unreference(old->release_fb);
6905 }
d2dff872 6906
67c96400 6907 mutex_unlock(&crtc->mutex);
0622a53c 6908 return;
79e53945
JB		 6909 }
6910
c751ce4f 6911 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6912 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6913 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6914
6915 mutex_unlock(&crtc->mutex);
79e53945
JB		 6916}
6917
6918/* Returns the clock of the currently programmed mode of the given pipe. */
6919static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6920{
6921 struct drm_i915_private *dev_priv = dev->dev_private;
6922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6923 int pipe = intel_crtc->pipe;
548f245b 6924 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6925 u32 fp;
6926 intel_clock_t clock;
6927
6928 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6929 fp = I915_READ(FP0(pipe));
79e53945 6930 else
39adb7a5 6931 fp = I915_READ(FP1(pipe));
79e53945
JB		 6932
6933 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6934 if (IS_PINEVIEW(dev)) {
6935 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6936 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6937 } else {
6938 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6939 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6940 }
6941
a6c45cf0 6942 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6943 if (IS_PINEVIEW(dev))
6944 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6945 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6946 else
6947 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6948 DPLL_FPA01_P1_POST_DIV_SHIFT);
6949
6950 switch (dpll & DPLL_MODE_MASK) {
6951 case DPLLB_MODE_DAC_SERIAL:
6952 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6953 5 : 10;
6954 break;
6955 case DPLLB_MODE_LVDS:
6956 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6957 7 : 14;
6958 break;
6959 default:
28c97730 6960 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6961 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6962 return 0;
6963 }
6964
6965 /* XXX: Handle the 100Mhz refclk */
2177832f 6966 intel_clock(dev, 96000, &clock);
79e53945
JB		 6967 } else {
6968 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6969
6970 if (is_lvds) {
6971 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6972 DPLL_FPA01_P1_POST_DIV_SHIFT);
6973 clock.p2 = 14;
6974
6975 if ((dpll & PLL_REF_INPUT_MASK) ==
6976 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6977 /* XXX: might not be 66MHz */
2177832f 6978 intel_clock(dev, 66000, &clock);
79e53945 6979 } else
2177832f 6980 intel_clock(dev, 48000, &clock);
79e53945
JB		 6981 } else {
6982 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6983 clock.p1 = 2;
6984 else {
6985 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6986 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6987 }
6988 if (dpll & PLL_P2_DIVIDE_BY_4)
6989 clock.p2 = 4;
6990 else
6991 clock.p2 = 2;
6992
2177832f 6993 intel_clock(dev, 48000, &clock);
79e53945
JB		 6994 }
6995 }
6996
6997 /* XXX: It would be nice to validate the clocks, but we can't reuse
6998 * i830PllIsValid() because it relies on the xf86_config connector
6999 * configuration being accurate, which it isn't necessarily.
7000 */
7001
7002 return clock.dot;
7003}
7004
7005/** Returns the currently programmed mode of the given pipe. */
7006struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7007 struct drm_crtc *crtc)
7008{
548f245b 7009 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7011 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7012 struct drm_display_mode *mode;
fe2b8f9d
PZ		 7013 int htot = I915_READ(HTOTAL(cpu_transcoder));
7014 int hsync = I915_READ(HSYNC(cpu_transcoder));
7015 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7016 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7017
7018 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7019 if (!mode)
7020 return NULL;
7021
7022 mode->clock = intel_crtc_clock_get(dev, crtc);
7023 mode->hdisplay = (htot & 0xffff) + 1;
7024 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7025 mode->hsync_start = (hsync & 0xffff) + 1;
7026 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7027 mode->vdisplay = (vtot & 0xffff) + 1;
7028 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7029 mode->vsync_start = (vsync & 0xffff) + 1;
7030 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7031
7032 drm_mode_set_name(mode);
79e53945
JB		 7033
7034 return mode;
7035}
7036
3dec0095 7037static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7038{
7039 struct drm_device *dev = crtc->dev;
7040 drm_i915_private_t *dev_priv = dev->dev_private;
7041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7042 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7043 int dpll_reg = DPLL(pipe);
7044 int dpll;
652c393a 7045
bad720ff 7046 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7047 return;
7048
7049 if (!dev_priv->lvds_downclock_avail)
7050 return;
7051
dbdc6479 7052 dpll = I915_READ(dpll_reg);
652c393a 7053 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7054 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7055
8ac5a6d5 7056 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7057
7058 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7059 I915_WRITE(dpll_reg, dpll);
9d0498a2 7060 intel_wait_for_vblank(dev, pipe);
dbdc6479 7061
652c393a
JB		 7062 dpll = I915_READ(dpll_reg);
7063 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7064 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7065 }
652c393a
JB		 7066}
7067
7068static void intel_decrease_pllclock(struct drm_crtc *crtc)
7069{
7070 struct drm_device *dev = crtc->dev;
7071 drm_i915_private_t *dev_priv = dev->dev_private;
7072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7073
bad720ff 7074 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7075 return;
7076
7077 if (!dev_priv->lvds_downclock_avail)
7078 return;
7079
7080 /*
7081 * Since this is called by a timer, we should never get here in
7082 * the manual case.
7083 */
7084 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7085 int pipe = intel_crtc->pipe;
7086 int dpll_reg = DPLL(pipe);
7087 int dpll;
f6e5b160 7088
44d98a61 7089 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7090
8ac5a6d5 7091 assert_panel_unlocked(dev_priv, pipe);
652c393a 7092
dc257cf1 7093 dpll = I915_READ(dpll_reg);
652c393a
JB		 7094 dpll |= DISPLAY_RATE_SELECT_FPA1;
7095 I915_WRITE(dpll_reg, dpll);
9d0498a2 7096 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7097 dpll = I915_READ(dpll_reg);
7098 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7099 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7100 }
7101
7102}
7103
f047e395
CW		 7104void intel_mark_busy(struct drm_device *dev)
7105{
f047e395
CW		 7106 i915_update_gfx_val(dev->dev_private);
7107}
7108
7109void intel_mark_idle(struct drm_device *dev)
652c393a 7110{
652c393a 7111 struct drm_crtc *crtc;
652c393a
JB		 7112
7113 if (!i915_powersave)
7114 return;
7115
652c393a 7116 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7117 if (!crtc->fb)
7118 continue;
7119
725a5b54 7120 intel_decrease_pllclock(crtc);
652c393a 7121 }
652c393a
JB		 7122}
7123
725a5b54 7124void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7125{
f047e395
CW		 7126 struct drm_device *dev = obj->base.dev;
7127 struct drm_crtc *crtc;
652c393a 7128
f047e395 7129 if (!i915_powersave)
acb87dfb
CW		 7130 return;
7131
652c393a
JB		 7132 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7133 if (!crtc->fb)
7134 continue;
7135
f047e395 7136 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7137 intel_increase_pllclock(crtc);
652c393a
JB		 7138 }
7139}
7140
79e53945
JB		 7141static void intel_crtc_destroy(struct drm_crtc *crtc)
7142{
7143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7144 struct drm_device *dev = crtc->dev;
7145 struct intel_unpin_work *work;
7146 unsigned long flags;
7147
7148 spin_lock_irqsave(&dev->event_lock, flags);
7149 work = intel_crtc->unpin_work;
7150 intel_crtc->unpin_work = NULL;
7151 spin_unlock_irqrestore(&dev->event_lock, flags);
7152
7153 if (work) {
7154 cancel_work_sync(&work->work);
7155 kfree(work);
7156 }
79e53945
JB		 7157
7158 drm_crtc_cleanup(crtc);
67e77c5a 7159
79e53945
JB		 7160 kfree(intel_crtc);
7161}
7162
6b95a207
KH		 7163static void intel_unpin_work_fn(struct work_struct *__work)
7164{
7165 struct intel_unpin_work *work =
7166 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7167 struct drm_device *dev = work->crtc->dev;
6b95a207 7168
b4a98e57 7169 mutex_lock(&dev->struct_mutex);
1690e1eb 7170 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7171 drm_gem_object_unreference(&work->pending_flip_obj->base);
7172 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7173
b4a98e57
CW		 7174 intel_update_fbc(dev);
7175 mutex_unlock(&dev->struct_mutex);
7176
7177 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7178 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7179
6b95a207
KH		 7180 kfree(work);
7181}
7182
1afe3e9d 7183static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7184 struct drm_crtc *crtc)
6b95a207
KH		 7185{
7186 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7188 struct intel_unpin_work *work;
6b95a207
KH		 7189 unsigned long flags;
7190
7191 /* Ignore early vblank irqs */
7192 if (intel_crtc == NULL)
7193 return;
7194
7195 spin_lock_irqsave(&dev->event_lock, flags);
7196 work = intel_crtc->unpin_work;
e7d841ca
CW		 7197
7198 /* Ensure we don't miss a work->pending update ... */
7199 smp_rmb();
7200
7201 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7202 spin_unlock_irqrestore(&dev->event_lock, flags);
7203 return;
7204 }
7205
e7d841ca
CW		 7206 /* and that the unpin work is consistent wrt ->pending. */
7207 smp_rmb();
7208
6b95a207 7209 intel_crtc->unpin_work = NULL;
6b95a207 7210
45a066eb
RC		 7211 if (work->event)
7212 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7213
0af7e4df
MK		 7214 drm_vblank_put(dev, intel_crtc->pipe);
7215
6b95a207
KH		 7216 spin_unlock_irqrestore(&dev->event_lock, flags);
7217
2c10d571 7218 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7219
7220 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7221
7222 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7223}
7224
1afe3e9d
JB		 7225void intel_finish_page_flip(struct drm_device *dev, int pipe)
7226{
7227 drm_i915_private_t *dev_priv = dev->dev_private;
7228 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7229
49b14a5c 7230 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7231}
7232
7233void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7234{
7235 drm_i915_private_t *dev_priv = dev->dev_private;
7236 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7237
49b14a5c 7238 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7239}
7240
6b95a207
KH		 7241void intel_prepare_page_flip(struct drm_device *dev, int plane)
7242{
7243 drm_i915_private_t *dev_priv = dev->dev_private;
7244 struct intel_crtc *intel_crtc =
7245 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7246 unsigned long flags;
7247
e7d841ca
CW		 7248 /* NB: An MMIO update of the plane base pointer will also
7249 * generate a page-flip completion irq, i.e. every modeset
7250 * is also accompanied by a spurious intel_prepare_page_flip().
7251 */
6b95a207 7252 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7253 if (intel_crtc->unpin_work)
7254 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7255 spin_unlock_irqrestore(&dev->event_lock, flags);
7256}
7257
e7d841ca
CW		 7258inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7259{
7260 /* Ensure that the work item is consistent when activating it ... */
7261 smp_wmb();
7262 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7263 /* and that it is marked active as soon as the irq could fire. */
7264 smp_wmb();
7265}
7266
8c9f3aaf
JB		 7267static int intel_gen2_queue_flip(struct drm_device *dev,
7268 struct drm_crtc *crtc,
7269 struct drm_framebuffer *fb,
7270 struct drm_i915_gem_object *obj)
7271{
7272 struct drm_i915_private *dev_priv = dev->dev_private;
7273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7274 u32 flip_mask;
6d90c952 7275 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7276 int ret;
7277
6d90c952 7278 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7279 if (ret)
83d4092b 7280 goto err;
8c9f3aaf 7281
6d90c952 7282 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7283 if (ret)
83d4092b 7284 goto err_unpin;
8c9f3aaf
JB		 7285
7286 /* Can't queue multiple flips, so wait for the previous
7287 * one to finish before executing the next.
7288 */
7289 if (intel_crtc->plane)
7290 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7291 else
7292 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7293 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7294 intel_ring_emit(ring, MI_NOOP);
7295 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7296 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7297 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7298 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7299 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7300
7301 intel_mark_page_flip_active(intel_crtc);
6d90c952 7302 intel_ring_advance(ring);
83d4092b
CW		 7303 return 0;
7304
7305err_unpin:
7306 intel_unpin_fb_obj(obj);
7307err:
8c9f3aaf
JB		 7308 return ret;
7309}
7310
7311static int intel_gen3_queue_flip(struct drm_device *dev,
7312 struct drm_crtc *crtc,
7313 struct drm_framebuffer *fb,
7314 struct drm_i915_gem_object *obj)
7315{
7316 struct drm_i915_private *dev_priv = dev->dev_private;
7317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7318 u32 flip_mask;
6d90c952 7319 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7320 int ret;
7321
6d90c952 7322 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7323 if (ret)
83d4092b 7324 goto err;
8c9f3aaf 7325
6d90c952 7326 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7327 if (ret)
83d4092b 7328 goto err_unpin;
8c9f3aaf
JB		 7329
7330 if (intel_crtc->plane)
7331 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7332 else
7333 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7334 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7335 intel_ring_emit(ring, MI_NOOP);
7336 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7337 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7338 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7339 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7340 intel_ring_emit(ring, MI_NOOP);
7341
e7d841ca 7342 intel_mark_page_flip_active(intel_crtc);
6d90c952 7343 intel_ring_advance(ring);
83d4092b
CW		 7344 return 0;
7345
7346err_unpin:
7347 intel_unpin_fb_obj(obj);
7348err:
8c9f3aaf
JB		 7349 return ret;
7350}
7351
7352static int intel_gen4_queue_flip(struct drm_device *dev,
7353 struct drm_crtc *crtc,
7354 struct drm_framebuffer *fb,
7355 struct drm_i915_gem_object *obj)
7356{
7357 struct drm_i915_private *dev_priv = dev->dev_private;
7358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7359 uint32_t pf, pipesrc;
6d90c952 7360 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7361 int ret;
7362
6d90c952 7363 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7364 if (ret)
83d4092b 7365 goto err;
8c9f3aaf 7366
6d90c952 7367 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7368 if (ret)
83d4092b 7369 goto err_unpin;
8c9f3aaf
JB		 7370
7371 /* i965+ uses the linear or tiled offsets from the
7372 * Display Registers (which do not change across a page-flip)
7373 * so we need only reprogram the base address.
7374 */
6d90c952
DV		 7375 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7376 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7377 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7378 intel_ring_emit(ring,
7379 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7380 obj->tiling_mode);
8c9f3aaf
JB		 7381
7382 /* XXX Enabling the panel-fitter across page-flip is so far
7383 * untested on non-native modes, so ignore it for now.
7384 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7385 */
7386 pf = 0;
7387 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7388 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7389
7390 intel_mark_page_flip_active(intel_crtc);
6d90c952 7391 intel_ring_advance(ring);
83d4092b
CW		 7392 return 0;
7393
7394err_unpin:
7395 intel_unpin_fb_obj(obj);
7396err:
8c9f3aaf
JB		 7397 return ret;
7398}
7399
7400static int intel_gen6_queue_flip(struct drm_device *dev,
7401 struct drm_crtc *crtc,
7402 struct drm_framebuffer *fb,
7403 struct drm_i915_gem_object *obj)
7404{
7405 struct drm_i915_private *dev_priv = dev->dev_private;
7406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7407 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7408 uint32_t pf, pipesrc;
7409 int ret;
7410
6d90c952 7411 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7412 if (ret)
83d4092b 7413 goto err;
8c9f3aaf 7414
6d90c952 7415 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7416 if (ret)
83d4092b 7417 goto err_unpin;
8c9f3aaf 7418
6d90c952
DV		 7419 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7420 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7421 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7422 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7423
dc257cf1
DV		 7424 /* Contrary to the suggestions in the documentation,
7425 * "Enable Panel Fitter" does not seem to be required when page
7426 * flipping with a non-native mode, and worse causes a normal
7427 * modeset to fail.
7428 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7429 */
7430 pf = 0;
8c9f3aaf 7431 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7432 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7433
7434 intel_mark_page_flip_active(intel_crtc);
6d90c952 7435 intel_ring_advance(ring);
83d4092b
CW		 7436 return 0;
7437
7438err_unpin:
7439 intel_unpin_fb_obj(obj);
7440err:
8c9f3aaf
JB		 7441 return ret;
7442}
7443
7c9017e5
JB		 7444/*
7445 * On gen7 we currently use the blit ring because (in early silicon at least)
7446 * the render ring doesn't give us interrpts for page flip completion, which
7447 * means clients will hang after the first flip is queued. Fortunately the
7448 * blit ring generates interrupts properly, so use it instead.
7449 */
7450static int intel_gen7_queue_flip(struct drm_device *dev,
7451 struct drm_crtc *crtc,
7452 struct drm_framebuffer *fb,
7453 struct drm_i915_gem_object *obj)
7454{
7455 struct drm_i915_private *dev_priv = dev->dev_private;
7456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7457 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7458 uint32_t plane_bit = 0;
7c9017e5
JB		 7459 int ret;
7460
7461 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7462 if (ret)
83d4092b 7463 goto err;
7c9017e5 7464
cb05d8de
DV		 7465 switch(intel_crtc->plane) {
7466 case PLANE_A:
7467 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7468 break;
7469 case PLANE_B:
7470 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7471 break;
7472 case PLANE_C:
7473 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7474 break;
7475 default:
7476 WARN_ONCE(1, "unknown plane in flip command\n");
7477 ret = -ENODEV;
ab3951eb 7478 goto err_unpin;
cb05d8de
DV		 7479 }
7480
7c9017e5
JB		 7481 ret = intel_ring_begin(ring, 4);
7482 if (ret)
83d4092b 7483 goto err_unpin;
7c9017e5 7484
cb05d8de 7485 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7486 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7487 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7488 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7489
7490 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7491 intel_ring_advance(ring);
83d4092b
CW		 7492 return 0;
7493
7494err_unpin:
7495 intel_unpin_fb_obj(obj);
7496err:
7c9017e5
JB		 7497 return ret;
7498}
7499
8c9f3aaf
JB		 7500static int intel_default_queue_flip(struct drm_device *dev,
7501 struct drm_crtc *crtc,
7502 struct drm_framebuffer *fb,
7503 struct drm_i915_gem_object *obj)
7504{
7505 return -ENODEV;
7506}
7507
6b95a207
KH		 7508static int intel_crtc_page_flip(struct drm_crtc *crtc,
7509 struct drm_framebuffer *fb,
7510 struct drm_pending_vblank_event *event)
7511{
7512 struct drm_device *dev = crtc->dev;
7513 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7514 struct drm_framebuffer *old_fb = crtc->fb;
7515 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7517 struct intel_unpin_work *work;
8c9f3aaf 7518 unsigned long flags;
52e68630 7519 int ret;
6b95a207 7520
e6a595d2
VS		 7521 /* Can't change pixel format via MI display flips. */
7522 if (fb->pixel_format != crtc->fb->pixel_format)
7523 return -EINVAL;
7524
7525 /*
7526 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7527 * Note that pitch changes could also affect these register.
7528 */
7529 if (INTEL_INFO(dev)->gen > 3 &&
7530 (fb->offsets[0] != crtc->fb->offsets[0] ||
7531 fb->pitches[0] != crtc->fb->pitches[0]))
7532 return -EINVAL;
7533
6b95a207
KH		 7534 work = kzalloc(sizeof *work, GFP_KERNEL);
7535 if (work == NULL)
7536 return -ENOMEM;
7537
6b95a207 7538 work->event = event;
b4a98e57 7539 work->crtc = crtc;
4a35f83b 7540 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7541 INIT_WORK(&work->work, intel_unpin_work_fn);
7542
7317c75e
JB		 7543 ret = drm_vblank_get(dev, intel_crtc->pipe);
7544 if (ret)
7545 goto free_work;
7546
6b95a207
KH		 7547 /* We borrow the event spin lock for protecting unpin_work */
7548 spin_lock_irqsave(&dev->event_lock, flags);
7549 if (intel_crtc->unpin_work) {
7550 spin_unlock_irqrestore(&dev->event_lock, flags);
7551 kfree(work);
7317c75e 7552 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7553
7554 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7555 return -EBUSY;
7556 }
7557 intel_crtc->unpin_work = work;
7558 spin_unlock_irqrestore(&dev->event_lock, flags);
7559
b4a98e57
CW		 7560 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7561 flush_workqueue(dev_priv->wq);
7562
79158103
CW		 7563 ret = i915_mutex_lock_interruptible(dev);
7564 if (ret)
7565 goto cleanup;
6b95a207 7566
75dfca80 7567 /* Reference the objects for the scheduled work. */
05394f39
CW		 7568 drm_gem_object_reference(&work->old_fb_obj->base);
7569 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7570
7571 crtc->fb = fb;
96b099fd 7572
e1f99ce6 7573 work->pending_flip_obj = obj;
e1f99ce6 7574
4e5359cd
SF		 7575 work->enable_stall_check = true;
7576
b4a98e57 7577 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7578 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7579
8c9f3aaf
JB		 7580 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7581 if (ret)
7582 goto cleanup_pending;
6b95a207 7583
7782de3b 7584 intel_disable_fbc(dev);
f047e395 7585 intel_mark_fb_busy(obj);
6b95a207
KH		 7586 mutex_unlock(&dev->struct_mutex);
7587
e5510fac
JB		 7588 trace_i915_flip_request(intel_crtc->plane, obj);
7589
6b95a207 7590 return 0;
96b099fd 7591
8c9f3aaf 7592cleanup_pending:
b4a98e57 7593 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7594 crtc->fb = old_fb;
05394f39
CW		 7595 drm_gem_object_unreference(&work->old_fb_obj->base);
7596 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7597 mutex_unlock(&dev->struct_mutex);
7598
79158103 7599cleanup:
96b099fd
CW		 7600 spin_lock_irqsave(&dev->event_lock, flags);
7601 intel_crtc->unpin_work = NULL;
7602 spin_unlock_irqrestore(&dev->event_lock, flags);
7603
7317c75e
JB		 7604 drm_vblank_put(dev, intel_crtc->pipe);
7605free_work:
96b099fd
CW		 7606 kfree(work);
7607
7608 return ret;
6b95a207
KH		 7609}
7610
f6e5b160 7611static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7612 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7613 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7614};
7615
6ed0f796 7616bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7617{
6ed0f796
DV		 7618 struct intel_encoder *other_encoder;
7619 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7620
6ed0f796
DV		 7621 if (WARN_ON(!crtc))
7622 return false;
7623
7624 list_for_each_entry(other_encoder,
7625 &crtc->dev->mode_config.encoder_list,
7626 base.head) {
7627
7628 if (&other_encoder->new_crtc->base != crtc ||
7629 encoder == other_encoder)
7630 continue;
7631 else
7632 return true;
f47166d2
CW		 7633 }
7634
6ed0f796
DV		 7635 return false;
7636}
47f1c6c9 7637
50f56119
DV		 7638static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7639 struct drm_crtc *crtc)
7640{
7641 struct drm_device *dev;
7642 struct drm_crtc *tmp;
7643 int crtc_mask = 1;
47f1c6c9 7644
50f56119 7645 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7646
50f56119 7647 dev = crtc->dev;
47f1c6c9 7648
50f56119
DV		 7649 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7650 if (tmp == crtc)
7651 break;
7652 crtc_mask <<= 1;
7653 }
47f1c6c9 7654
50f56119
DV		 7655 if (encoder->possible_crtcs & crtc_mask)
7656 return true;
7657 return false;
47f1c6c9 7658}
79e53945 7659
9a935856
DV		 7660/**
7661 * intel_modeset_update_staged_output_state
7662 *
7663 * Updates the staged output configuration state, e.g. after we've read out the
7664 * current hw state.
7665 */
7666static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7667{
9a935856
DV		 7668 struct intel_encoder *encoder;
7669 struct intel_connector *connector;
f6e5b160 7670
9a935856
DV		 7671 list_for_each_entry(connector, &dev->mode_config.connector_list,
7672 base.head) {
7673 connector->new_encoder =
7674 to_intel_encoder(connector->base.encoder);
7675 }
f6e5b160 7676
9a935856
DV		 7677 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7678 base.head) {
7679 encoder->new_crtc =
7680 to_intel_crtc(encoder->base.crtc);
7681 }
f6e5b160
CW		 7682}
7683
9a935856
DV		 7684/**
7685 * intel_modeset_commit_output_state
7686 *
7687 * This function copies the stage display pipe configuration to the real one.
7688 */
7689static void intel_modeset_commit_output_state(struct drm_device *dev)
7690{
7691 struct intel_encoder *encoder;
7692 struct intel_connector *connector;
f6e5b160 7693
9a935856
DV		 7694 list_for_each_entry(connector, &dev->mode_config.connector_list,
7695 base.head) {
7696 connector->base.encoder = &connector->new_encoder->base;
7697 }
f6e5b160 7698
9a935856
DV		 7699 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7700 base.head) {
7701 encoder->base.crtc = &encoder->new_crtc->base;
7702 }
7703}
7704
4e53c2e0
DV		 7705static int
7706pipe_config_set_bpp(struct drm_crtc *crtc,
7707 struct drm_framebuffer *fb,
7708 struct intel_crtc_config *pipe_config)
7709{
7710 struct drm_device *dev = crtc->dev;
7711 struct drm_connector *connector;
7712 int bpp;
7713
d42264b1
DV		 7714 switch (fb->pixel_format) {
7715 case DRM_FORMAT_C8:
4e53c2e0
DV		 7716 bpp = 8*3; /* since we go through a colormap */
7717 break;
d42264b1
DV		 7718 case DRM_FORMAT_XRGB1555:
7719 case DRM_FORMAT_ARGB1555:
7720 /* checked in intel_framebuffer_init already */
7721 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7722 return -EINVAL;
7723 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7724 bpp = 6*3; /* min is 18bpp */
7725 break;
d42264b1
DV		 7726 case DRM_FORMAT_XBGR8888:
7727 case DRM_FORMAT_ABGR8888:
7728 /* checked in intel_framebuffer_init already */
7729 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7730 return -EINVAL;
7731 case DRM_FORMAT_XRGB8888:
7732 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7733 bpp = 8*3;
7734 break;
d42264b1
DV		 7735 case DRM_FORMAT_XRGB2101010:
7736 case DRM_FORMAT_ARGB2101010:
7737 case DRM_FORMAT_XBGR2101010:
7738 case DRM_FORMAT_ABGR2101010:
7739 /* checked in intel_framebuffer_init already */
7740 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7741 return -EINVAL;
4e53c2e0
DV		 7742 bpp = 10*3;
7743 break;
baba133a 7744 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7745 default:
7746 DRM_DEBUG_KMS("unsupported depth\n");
7747 return -EINVAL;
7748 }
7749
4e53c2e0
DV		 7750 pipe_config->pipe_bpp = bpp;
7751
7752 /* Clamp display bpp to EDID value */
7753 list_for_each_entry(connector, &dev->mode_config.connector_list,
7754 head) {
7755 if (connector->encoder && connector->encoder->crtc != crtc)
7756 continue;
7757
7758 /* Don't use an invalid EDID bpc value */
7759 if (connector->display_info.bpc &&
7760 connector->display_info.bpc * 3 < bpp) {
7761 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7762 bpp, connector->display_info.bpc*3);
7763 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7764 }
996a2239
DV		 7765
7766 /* Clamp bpp to 8 on screens without EDID 1.4 */
7767 if (connector->display_info.bpc == 0 && bpp > 24) {
7768 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7769 bpp);
7770 pipe_config->pipe_bpp = 24;
7771 }
4e53c2e0
DV		 7772 }
7773
7774 return bpp;
7775}
7776
b8cecdf5
DV		 7777static struct intel_crtc_config *
7778intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7779 struct drm_framebuffer *fb,
b8cecdf5 7780 struct drm_display_mode *mode)
ee7b9f93 7781{
7758a113 7782 struct drm_device *dev = crtc->dev;
7758a113
DV		 7783 struct drm_encoder_helper_funcs *encoder_funcs;
7784 struct intel_encoder *encoder;
b8cecdf5 7785 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7786 int plane_bpp, ret = -EINVAL;
7787 bool retry = true;
ee7b9f93 7788
b8cecdf5
DV		 7789 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7790 if (!pipe_config)
7758a113
DV		 7791 return ERR_PTR(-ENOMEM);
7792
b8cecdf5
DV		 7793 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7794 drm_mode_copy(&pipe_config->requested_mode, mode);
7795
4e53c2e0
DV		 7796 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7797 if (plane_bpp < 0)
7798 goto fail;
7799
e29c22c0 7800encoder_retry:
7758a113
DV		 7801 /* Pass our mode to the connectors and the CRTC to give them a chance to
7802 * adjust it according to limitations or connector properties, and also
7803 * a chance to reject the mode entirely.
47f1c6c9 7804 */
7758a113
DV		 7805 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7806 base.head) {
47f1c6c9 7807
7758a113
DV		 7808 if (&encoder->new_crtc->base != crtc)
7809 continue;
7ae89233
DV		 7810
7811 if (encoder->compute_config) {
7812 if (!(encoder->compute_config(encoder, pipe_config))) {
7813 DRM_DEBUG_KMS("Encoder config failure\n");
7814 goto fail;
7815 }
7816
7817 continue;
7818 }
7819
7758a113 7820 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7821 if (!(encoder_funcs->mode_fixup(&encoder->base,
7822 &pipe_config->requested_mode,
7823 &pipe_config->adjusted_mode))) {
7758a113
DV		 7824 DRM_DEBUG_KMS("Encoder fixup failed\n");
7825 goto fail;
7826 }
ee7b9f93 7827 }
47f1c6c9 7828
e29c22c0
DV		 7829 ret = intel_crtc_compute_config(crtc, pipe_config);
7830 if (ret < 0) {
7758a113
DV		 7831 DRM_DEBUG_KMS("CRTC fixup failed\n");
7832 goto fail;
ee7b9f93 7833 }
e29c22c0
DV		 7834
7835 if (ret == RETRY) {
7836 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7837 ret = -EINVAL;
7838 goto fail;
7839 }
7840
7841 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7842 retry = false;
7843 goto encoder_retry;
7844 }
7845
7758a113 7846 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7847
4e53c2e0
DV		 7848 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7849 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7850 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7851
b8cecdf5 7852 return pipe_config;
7758a113 7853fail:
b8cecdf5 7854 kfree(pipe_config);
e29c22c0 7855 return ERR_PTR(ret);
ee7b9f93 7856}
47f1c6c9 7857
e2e1ed41
DV		 7858/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7859 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7860static void
7861intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7862 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7863{
7864 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7865 struct drm_device *dev = crtc->dev;
7866 struct intel_encoder *encoder;
7867 struct intel_connector *connector;
7868 struct drm_crtc *tmp_crtc;
79e53945 7869
e2e1ed41 7870 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7871
e2e1ed41
DV		 7872 /* Check which crtcs have changed outputs connected to them, these need
7873 * to be part of the prepare_pipes mask. We don't (yet) support global
7874 * modeset across multiple crtcs, so modeset_pipes will only have one
7875 * bit set at most. */
7876 list_for_each_entry(connector, &dev->mode_config.connector_list,
7877 base.head) {
7878 if (connector->base.encoder == &connector->new_encoder->base)
7879 continue;
79e53945 7880
e2e1ed41
DV		 7881 if (connector->base.encoder) {
7882 tmp_crtc = connector->base.encoder->crtc;
7883
7884 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7885 }
7886
7887 if (connector->new_encoder)
7888 *prepare_pipes |=
7889 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7890 }
7891
e2e1ed41
DV		 7892 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7893 base.head) {
7894 if (encoder->base.crtc == &encoder->new_crtc->base)
7895 continue;
7896
7897 if (encoder->base.crtc) {
7898 tmp_crtc = encoder->base.crtc;
7899
7900 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7901 }
7902
7903 if (encoder->new_crtc)
7904 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7905 }
7906
e2e1ed41
DV		 7907 /* Check for any pipes that will be fully disabled ... */
7908 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7909 base.head) {
7910 bool used = false;
22fd0fab 7911
e2e1ed41
DV		 7912 /* Don't try to disable disabled crtcs. */
7913 if (!intel_crtc->base.enabled)
7914 continue;
7e7d76c3 7915
e2e1ed41
DV		 7916 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7917 base.head) {
7918 if (encoder->new_crtc == intel_crtc)
7919 used = true;
7920 }
7921
7922 if (!used)
7923 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7924 }
7925
e2e1ed41
DV		 7926
7927 /* set_mode is also used to update properties on life display pipes. */
7928 intel_crtc = to_intel_crtc(crtc);
7929 if (crtc->enabled)
7930 *prepare_pipes |= 1 << intel_crtc->pipe;
7931
b6c5164d
DV		 7932 /*
7933 * For simplicity do a full modeset on any pipe where the output routing
7934 * changed. We could be more clever, but that would require us to be
7935 * more careful with calling the relevant encoder->mode_set functions.
7936 */
e2e1ed41
DV		 7937 if (*prepare_pipes)
7938 *modeset_pipes = *prepare_pipes;
7939
7940 /* ... and mask these out. */
7941 *modeset_pipes &= ~(*disable_pipes);
7942 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7943
7944 /*
7945 * HACK: We don't (yet) fully support global modesets. intel_set_config
7946 * obies this rule, but the modeset restore mode of
7947 * intel_modeset_setup_hw_state does not.
7948 */
7949 *modeset_pipes &= 1 << intel_crtc->pipe;
7950 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7951
7952 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7953 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7954}
79e53945 7955
ea9d758d 7956static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7957{
ea9d758d 7958 struct drm_encoder *encoder;
f6e5b160 7959 struct drm_device *dev = crtc->dev;
f6e5b160 7960
ea9d758d
DV		 7961 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7962 if (encoder->crtc == crtc)
7963 return true;
7964
7965 return false;
7966}
7967
7968static void
7969intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7970{
7971 struct intel_encoder *intel_encoder;
7972 struct intel_crtc *intel_crtc;
7973 struct drm_connector *connector;
7974
7975 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7976 base.head) {
7977 if (!intel_encoder->base.crtc)
7978 continue;
7979
7980 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7981
7982 if (prepare_pipes & (1 << intel_crtc->pipe))
7983 intel_encoder->connectors_active = false;
7984 }
7985
7986 intel_modeset_commit_output_state(dev);
7987
7988 /* Update computed state. */
7989 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7990 base.head) {
7991 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7992 }
7993
7994 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7995 if (!connector->encoder || !connector->encoder->crtc)
7996 continue;
7997
7998 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7999
8000 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8001 struct drm_property *dpms_property =
8002 dev->mode_config.dpms_property;
8003
ea9d758d 8004 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8005 drm_object_property_set_value(&connector->base,
68d34720
DV		 8006 dpms_property,
8007 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8008
8009 intel_encoder = to_intel_encoder(connector->encoder);
8010 intel_encoder->connectors_active = true;
8011 }
8012 }
8013
8014}
8015
25c5b266
DV		 8016#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8017 list_for_each_entry((intel_crtc), \
8018 &(dev)->mode_config.crtc_list, \
8019 base.head) \
0973f18f 8020 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8021
0e8ffe1b 8022static bool
2fa2fe9a
DV		 8023intel_pipe_config_compare(struct drm_device *dev,
8024 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8025 struct intel_crtc_config *pipe_config)
8026{
08a24034
DV		 8027#define PIPE_CONF_CHECK_I(name) \
8028 if (current_config->name != pipe_config->name) { \
8029 DRM_ERROR("mismatch in " #name " " \
8030 "(expected %i, found %i)\n", \
8031 current_config->name, \
8032 pipe_config->name); \
8033 return false; \
88adfff1
DV		 8034 }
8035
1bd1bd80
DV		 8036#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8037 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8038 DRM_ERROR("mismatch in " #name " " \
8039 "(expected %i, found %i)\n", \
8040 current_config->name & (mask), \
8041 pipe_config->name & (mask)); \
8042 return false; \
8043 }
8044
08a24034
DV		 8045 PIPE_CONF_CHECK_I(has_pch_encoder);
8046 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8047 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8048 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8049 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8050 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8051 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8052
1bd1bd80
DV		 8053 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8054 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8055 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8056 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8057 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8058 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8059
8060 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8061 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8062 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8063 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8064 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8065 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8066
8067 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8068 DRM_MODE_FLAG_INTERLACE);
8069
8070 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8071 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8072
2fa2fe9a
DV		 8073 PIPE_CONF_CHECK_I(gmch_pfit.control);
8074 /* pfit ratios are autocomputed by the hw on gen4+ */
8075 if (INTEL_INFO(dev)->gen < 4)
8076 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8077 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8078 PIPE_CONF_CHECK_I(pch_pfit.pos);
8079 PIPE_CONF_CHECK_I(pch_pfit.size);
8080
08a24034 8081#undef PIPE_CONF_CHECK_I
1bd1bd80 8082#undef PIPE_CONF_CHECK_FLAGS
88adfff1 8083
0e8ffe1b
DV		 8084 return true;
8085}
8086
b980514c 8087void
8af6cf88
DV		 8088intel_modeset_check_state(struct drm_device *dev)
8089{
0e8ffe1b 8090 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8091 struct intel_crtc *crtc;
8092 struct intel_encoder *encoder;
8093 struct intel_connector *connector;
0e8ffe1b 8094 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8095
8096 list_for_each_entry(connector, &dev->mode_config.connector_list,
8097 base.head) {
8098 /* This also checks the encoder/connector hw state with the
8099 * ->get_hw_state callbacks. */
8100 intel_connector_check_state(connector);
8101
8102 WARN(&connector->new_encoder->base != connector->base.encoder,
8103 "connector's staged encoder doesn't match current encoder\n");
8104 }
8105
8106 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8107 base.head) {
8108 bool enabled = false;
8109 bool active = false;
8110 enum pipe pipe, tracked_pipe;
8111
8112 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8113 encoder->base.base.id,
8114 drm_get_encoder_name(&encoder->base));
8115
8116 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8117 "encoder's stage crtc doesn't match current crtc\n");
8118 WARN(encoder->connectors_active && !encoder->base.crtc,
8119 "encoder's active_connectors set, but no crtc\n");
8120
8121 list_for_each_entry(connector, &dev->mode_config.connector_list,
8122 base.head) {
8123 if (connector->base.encoder != &encoder->base)
8124 continue;
8125 enabled = true;
8126 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8127 active = true;
8128 }
8129 WARN(!!encoder->base.crtc != enabled,
8130 "encoder's enabled state mismatch "
8131 "(expected %i, found %i)\n",
8132 !!encoder->base.crtc, enabled);
8133 WARN(active && !encoder->base.crtc,
8134 "active encoder with no crtc\n");
8135
8136 WARN(encoder->connectors_active != active,
8137 "encoder's computed active state doesn't match tracked active state "
8138 "(expected %i, found %i)\n", active, encoder->connectors_active);
8139
8140 active = encoder->get_hw_state(encoder, &pipe);
8141 WARN(active != encoder->connectors_active,
8142 "encoder's hw state doesn't match sw tracking "
8143 "(expected %i, found %i)\n",
8144 encoder->connectors_active, active);
8145
8146 if (!encoder->base.crtc)
8147 continue;
8148
8149 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8150 WARN(active && pipe != tracked_pipe,
8151 "active encoder's pipe doesn't match"
8152 "(expected %i, found %i)\n",
8153 tracked_pipe, pipe);
8154
8155 }
8156
8157 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8158 base.head) {
8159 bool enabled = false;
8160 bool active = false;
8161
8162 DRM_DEBUG_KMS("[CRTC:%d]\n",
8163 crtc->base.base.id);
8164
8165 WARN(crtc->active && !crtc->base.enabled,
8166 "active crtc, but not enabled in sw tracking\n");
8167
8168 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8169 base.head) {
8170 if (encoder->base.crtc != &crtc->base)
8171 continue;
8172 enabled = true;
8173 if (encoder->connectors_active)
8174 active = true;
8175 }
8176 WARN(active != crtc->active,
8177 "crtc's computed active state doesn't match tracked active state "
8178 "(expected %i, found %i)\n", active, crtc->active);
8179 WARN(enabled != crtc->base.enabled,
8180 "crtc's computed enabled state doesn't match tracked enabled state "
8181 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8182
88adfff1 8183 memset(&pipe_config, 0, sizeof(pipe_config));
60c4ae10 8184 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 8185 active = dev_priv->display.get_pipe_config(crtc,
8186 &pipe_config);
8187 WARN(crtc->active != active,
8188 "crtc active state doesn't match with hw state "
8189 "(expected %i, found %i)\n", crtc->active, active);
8190
8191 WARN(active &&
2fa2fe9a 8192 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config),
0e8ffe1b 8193 "pipe state doesn't match!\n");
8af6cf88
DV		 8194 }
8195}
8196
f30da187
DV		 8197static int __intel_set_mode(struct drm_crtc *crtc,
8198 struct drm_display_mode *mode,
8199 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8200{
8201 struct drm_device *dev = crtc->dev;
dbf2b54e 8202 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8203 struct drm_display_mode *saved_mode, *saved_hwmode;
8204 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8205 struct intel_crtc *intel_crtc;
8206 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8207 int ret = 0;
a6778b3c 8208
3ac18232 8209 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8210 if (!saved_mode)
8211 return -ENOMEM;
3ac18232 8212 saved_hwmode = saved_mode + 1;
a6778b3c 8213
e2e1ed41 8214 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8215 &prepare_pipes, &disable_pipes);
8216
3ac18232
TG		 8217 *saved_hwmode = crtc->hwmode;
8218 *saved_mode = crtc->mode;
a6778b3c 8219
25c5b266
DV		 8220 /* Hack: Because we don't (yet) support global modeset on multiple
8221 * crtcs, we don't keep track of the new mode for more than one crtc.
8222 * Hence simply check whether any bit is set in modeset_pipes in all the
8223 * pieces of code that are not yet converted to deal with mutliple crtcs
8224 * changing their mode at the same time. */
25c5b266 8225 if (modeset_pipes) {
4e53c2e0 8226 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8227 if (IS_ERR(pipe_config)) {
8228 ret = PTR_ERR(pipe_config);
8229 pipe_config = NULL;
8230
3ac18232 8231 goto out;
25c5b266 8232 }
25c5b266 8233 }
a6778b3c 8234
460da916
DV		 8235 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8236 intel_crtc_disable(&intel_crtc->base);
8237
ea9d758d
DV		 8238 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8239 if (intel_crtc->base.enabled)
8240 dev_priv->display.crtc_disable(&intel_crtc->base);
8241 }
a6778b3c 8242
6c4c86f5
DV		 8243 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8244 * to set it here already despite that we pass it down the callchain.
f6e5b160 8245 */
b8cecdf5 8246 if (modeset_pipes) {
3b117c8f 8247 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8248 crtc->mode = *mode;
b8cecdf5
DV		 8249 /* mode_set/enable/disable functions rely on a correct pipe
8250 * config. */
8251 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8252 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8253 }
7758a113 8254
ea9d758d
DV		 8255 /* Only after disabling all output pipelines that will be changed can we
8256 * update the the output configuration. */
8257 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8258
47fab737
DV		 8259 if (dev_priv->display.modeset_global_resources)
8260 dev_priv->display.modeset_global_resources(dev);
8261
a6778b3c
DV		 8262 /* Set up the DPLL and any encoders state that needs to adjust or depend
8263 * on the DPLL.
f6e5b160 8264 */
25c5b266 8265 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8266 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8267 x, y, fb);
8268 if (ret)
8269 goto done;
a6778b3c
DV		 8270 }
8271
8272 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8273 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8274 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8275
25c5b266
DV		 8276 if (modeset_pipes) {
8277 /* Store real post-adjustment hardware mode. */
b8cecdf5 8278 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8279
25c5b266
DV		 8280 /* Calculate and store various constants which
8281 * are later needed by vblank and swap-completion
8282 * timestamping. They are derived from true hwmode.
8283 */
8284 drm_calc_timestamping_constants(crtc);
8285 }
a6778b3c
DV		 8286
8287 /* FIXME: add subpixel order */
8288done:
c0c36b94 8289 if (ret && crtc->enabled) {
3ac18232
TG		 8290 crtc->hwmode = *saved_hwmode;
8291 crtc->mode = *saved_mode;
a6778b3c
DV		 8292 }
8293
3ac18232 8294out:
b8cecdf5 8295 kfree(pipe_config);
3ac18232 8296 kfree(saved_mode);
a6778b3c 8297 return ret;
f6e5b160
CW		 8298}
8299
f30da187
DV		 8300int intel_set_mode(struct drm_crtc *crtc,
8301 struct drm_display_mode *mode,
8302 int x, int y, struct drm_framebuffer *fb)
8303{
8304 int ret;
8305
8306 ret = __intel_set_mode(crtc, mode, x, y, fb);
8307
8308 if (ret == 0)
8309 intel_modeset_check_state(crtc->dev);
8310
8311 return ret;
8312}
8313
c0c36b94
CW		 8314void intel_crtc_restore_mode(struct drm_crtc *crtc)
8315{
8316 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8317}
8318
25c5b266
DV		 8319#undef for_each_intel_crtc_masked
8320
d9e55608
DV		 8321static void intel_set_config_free(struct intel_set_config *config)
8322{
8323 if (!config)
8324 return;
8325
1aa4b628
DV		 8326 kfree(config->save_connector_encoders);
8327 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8328 kfree(config);
8329}
8330
85f9eb71
DV		 8331static int intel_set_config_save_state(struct drm_device *dev,
8332 struct intel_set_config *config)
8333{
85f9eb71
DV		 8334 struct drm_encoder *encoder;
8335 struct drm_connector *connector;
8336 int count;
8337
1aa4b628
DV		 8338 config->save_encoder_crtcs =
8339 kcalloc(dev->mode_config.num_encoder,
8340 sizeof(struct drm_crtc *), GFP_KERNEL);
8341 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8342 return -ENOMEM;
8343
1aa4b628
DV		 8344 config->save_connector_encoders =
8345 kcalloc(dev->mode_config.num_connector,
8346 sizeof(struct drm_encoder *), GFP_KERNEL);
8347 if (!config->save_connector_encoders)
85f9eb71
DV		 8348 return -ENOMEM;
8349
8350 /* Copy data. Note that driver private data is not affected.
8351 * Should anything bad happen only the expected state is
8352 * restored, not the drivers personal bookkeeping.
8353 */
85f9eb71
DV		 8354 count = 0;
8355 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8356 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8357 }
8358
8359 count = 0;
8360 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8361 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8362 }
8363
8364 return 0;
8365}
8366
8367static void intel_set_config_restore_state(struct drm_device *dev,
8368 struct intel_set_config *config)
8369{
9a935856
DV		 8370 struct intel_encoder *encoder;
8371 struct intel_connector *connector;
85f9eb71
DV		 8372 int count;
8373
85f9eb71 8374 count = 0;
9a935856
DV		 8375 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8376 encoder->new_crtc =
8377 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8378 }
8379
8380 count = 0;
9a935856
DV		 8381 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8382 connector->new_encoder =
8383 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8384 }
8385}
8386
e3de42b6
ID		 8387static bool
8388is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8389 int num_connectors)
8390{
8391 int i;
8392
8393 for (i = 0; i < num_connectors; i++)
8394 if (connectors[i].encoder &&
8395 connectors[i].encoder->crtc == crtc &&
8396 connectors[i].dpms != DRM_MODE_DPMS_ON)
8397 return true;
8398
8399 return false;
8400}
8401
5e2b584e
DV		 8402static void
8403intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8404 struct intel_set_config *config)
8405{
8406
8407 /* We should be able to check here if the fb has the same properties
8408 * and then just flip_or_move it */
e3de42b6
ID		 8409 if (set->connectors != NULL &&
8410 is_crtc_connector_off(set->crtc, *set->connectors,
8411 set->num_connectors)) {
8412 config->mode_changed = true;
8413 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8414 /* If we have no fb then treat it as a full mode set */
8415 if (set->crtc->fb == NULL) {
8416 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8417 config->mode_changed = true;
8418 } else if (set->fb == NULL) {
8419 config->mode_changed = true;
72f4901e
DV		 8420 } else if (set->fb->pixel_format !=
8421 set->crtc->fb->pixel_format) {
5e2b584e 8422 config->mode_changed = true;
e3de42b6 8423 } else {
5e2b584e 8424 config->fb_changed = true;
e3de42b6 8425 }
5e2b584e
DV		 8426 }
8427
835c5873 8428 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8429 config->fb_changed = true;
8430
8431 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8432 DRM_DEBUG_KMS("modes are different, full mode set\n");
8433 drm_mode_debug_printmodeline(&set->crtc->mode);
8434 drm_mode_debug_printmodeline(set->mode);
8435 config->mode_changed = true;
8436 }
8437}
8438
2e431051 8439static int
9a935856
DV		 8440intel_modeset_stage_output_state(struct drm_device *dev,
8441 struct drm_mode_set *set,
8442 struct intel_set_config *config)
50f56119 8443{
85f9eb71 8444 struct drm_crtc *new_crtc;
9a935856
DV		 8445 struct intel_connector *connector;
8446 struct intel_encoder *encoder;
2e431051 8447 int count, ro;
50f56119 8448
9abdda74 8449 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8450 * of connectors. For paranoia, double-check this. */
8451 WARN_ON(!set->fb && (set->num_connectors != 0));
8452 WARN_ON(set->fb && (set->num_connectors == 0));
8453
50f56119 8454 count = 0;
9a935856
DV		 8455 list_for_each_entry(connector, &dev->mode_config.connector_list,
8456 base.head) {
8457 /* Otherwise traverse passed in connector list and get encoders
8458 * for them. */
50f56119 8459 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8460 if (set->connectors[ro] == &connector->base) {
8461 connector->new_encoder = connector->encoder;
50f56119
DV		 8462 break;
8463 }
8464 }
8465
9a935856
DV		 8466 /* If we disable the crtc, disable all its connectors. Also, if
8467 * the connector is on the changing crtc but not on the new
8468 * connector list, disable it. */
8469 if ((!set->fb || ro == set->num_connectors) &&
8470 connector->base.encoder &&
8471 connector->base.encoder->crtc == set->crtc) {
8472 connector->new_encoder = NULL;
8473
8474 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8475 connector->base.base.id,
8476 drm_get_connector_name(&connector->base));
8477 }
8478
8479
8480 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8481 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8482 config->mode_changed = true;
50f56119
DV		 8483 }
8484 }
9a935856 8485 /* connector->new_encoder is now updated for all connectors. */
50f56119 8486
9a935856 8487 /* Update crtc of enabled connectors. */
50f56119 8488 count = 0;
9a935856
DV		 8489 list_for_each_entry(connector, &dev->mode_config.connector_list,
8490 base.head) {
8491 if (!connector->new_encoder)
50f56119
DV		 8492 continue;
8493
9a935856 8494 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8495
8496 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8497 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8498 new_crtc = set->crtc;
8499 }
8500
8501 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8502 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8503 new_crtc)) {
5e2b584e 8504 return -EINVAL;
50f56119 8505 }
9a935856
DV		 8506 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8507
8508 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8509 connector->base.base.id,
8510 drm_get_connector_name(&connector->base),
8511 new_crtc->base.id);
8512 }
8513
8514 /* Check for any encoders that needs to be disabled. */
8515 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8516 base.head) {
8517 list_for_each_entry(connector,
8518 &dev->mode_config.connector_list,
8519 base.head) {
8520 if (connector->new_encoder == encoder) {
8521 WARN_ON(!connector->new_encoder->new_crtc);
8522
8523 goto next_encoder;
8524 }
8525 }
8526 encoder->new_crtc = NULL;
8527next_encoder:
8528 /* Only now check for crtc changes so we don't miss encoders
8529 * that will be disabled. */
8530 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8531 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8532 config->mode_changed = true;
50f56119
DV		 8533 }
8534 }
9a935856 8535 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8536
2e431051
DV		 8537 return 0;
8538}
8539
8540static int intel_crtc_set_config(struct drm_mode_set *set)
8541{
8542 struct drm_device *dev;
2e431051
DV		 8543 struct drm_mode_set save_set;
8544 struct intel_set_config *config;
8545 int ret;
2e431051 8546
8d3e375e
DV		 8547 BUG_ON(!set);
8548 BUG_ON(!set->crtc);
8549 BUG_ON(!set->crtc->helper_private);
2e431051 8550
7e53f3a4
DV		 8551 /* Enforce sane interface api - has been abused by the fb helper. */
8552 BUG_ON(!set->mode && set->fb);
8553 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8554
2e431051
DV		 8555 if (set->fb) {
8556 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8557 set->crtc->base.id, set->fb->base.id,
8558 (int)set->num_connectors, set->x, set->y);
8559 } else {
8560 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8561 }
8562
8563 dev = set->crtc->dev;
8564
8565 ret = -ENOMEM;
8566 config = kzalloc(sizeof(*config), GFP_KERNEL);
8567 if (!config)
8568 goto out_config;
8569
8570 ret = intel_set_config_save_state(dev, config);
8571 if (ret)
8572 goto out_config;
8573
8574 save_set.crtc = set->crtc;
8575 save_set.mode = &set->crtc->mode;
8576 save_set.x = set->crtc->x;
8577 save_set.y = set->crtc->y;
8578 save_set.fb = set->crtc->fb;
8579
8580 /* Compute whether we need a full modeset, only an fb base update or no
8581 * change at all. In the future we might also check whether only the
8582 * mode changed, e.g. for LVDS where we only change the panel fitter in
8583 * such cases. */
8584 intel_set_config_compute_mode_changes(set, config);
8585
9a935856 8586 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8587 if (ret)
8588 goto fail;
8589
5e2b584e 8590 if (config->mode_changed) {
87f1faa6 8591 if (set->mode) {
50f56119
DV		 8592 DRM_DEBUG_KMS("attempting to set mode from"
8593 " userspace\n");
8594 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8595 }
8596
c0c36b94
CW		 8597 ret = intel_set_mode(set->crtc, set->mode,
8598 set->x, set->y, set->fb);
5e2b584e 8599 } else if (config->fb_changed) {
4878cae2
VS		 8600 intel_crtc_wait_for_pending_flips(set->crtc);
8601
4f660f49 8602 ret = intel_pipe_set_base(set->crtc,
94352cf9 8603 set->x, set->y, set->fb);
50f56119
DV		 8604 }
8605
2d05eae1
CW		 8606 if (ret) {
8607 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8608 set->crtc->base.id, ret);
50f56119 8609fail:
2d05eae1 8610 intel_set_config_restore_state(dev, config);
50f56119 8611
2d05eae1
CW		 8612 /* Try to restore the config */
8613 if (config->mode_changed &&
8614 intel_set_mode(save_set.crtc, save_set.mode,
8615 save_set.x, save_set.y, save_set.fb))
8616 DRM_ERROR("failed to restore config after modeset failure\n");
8617 }
50f56119 8618
d9e55608
DV		 8619out_config:
8620 intel_set_config_free(config);
50f56119
DV		 8621 return ret;
8622}
f6e5b160
CW		 8623
8624static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8625 .cursor_set = intel_crtc_cursor_set,
8626 .cursor_move = intel_crtc_cursor_move,
8627 .gamma_set = intel_crtc_gamma_set,
50f56119 8628 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8629 .destroy = intel_crtc_destroy,
8630 .page_flip = intel_crtc_page_flip,
8631};
8632
79f689aa
PZ		 8633static void intel_cpu_pll_init(struct drm_device *dev)
8634{
affa9354 8635 if (HAS_DDI(dev))
79f689aa
PZ		 8636 intel_ddi_pll_init(dev);
8637}
8638
ee7b9f93
JB		 8639static void intel_pch_pll_init(struct drm_device *dev)
8640{
8641 drm_i915_private_t *dev_priv = dev->dev_private;
8642 int i;
8643
8644 if (dev_priv->num_pch_pll == 0) {
8645 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8646 return;
8647 }
8648
8649 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8650 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8651 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8652 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8653 }
8654}
8655
b358d0a6 8656static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8657{
22fd0fab 8658 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8659 struct intel_crtc *intel_crtc;
8660 int i;
8661
8662 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8663 if (intel_crtc == NULL)
8664 return;
8665
8666 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8667
8668 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8669 for (i = 0; i < 256; i++) {
8670 intel_crtc->lut_r[i] = i;
8671 intel_crtc->lut_g[i] = i;
8672 intel_crtc->lut_b[i] = i;
8673 }
8674
80824003
JB		 8675 /* Swap pipes & planes for FBC on pre-965 */
8676 intel_crtc->pipe = pipe;
8677 intel_crtc->plane = pipe;
3b117c8f 8678 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8679 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8680 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8681 intel_crtc->plane = !pipe;
80824003
JB		 8682 }
8683
22fd0fab
JB		 8684 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8685 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8686 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8687 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8688
79e53945 8689 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8690}
8691
08d7b3d1 8692int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8693 struct drm_file *file)
08d7b3d1 8694{
08d7b3d1 8695 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8696 struct drm_mode_object *drmmode_obj;
8697 struct intel_crtc *crtc;
08d7b3d1 8698
1cff8f6b
DV		 8699 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8700 return -ENODEV;
08d7b3d1 8701
c05422d5
DV		 8702 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8703 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8704
c05422d5 8705 if (!drmmode_obj) {
08d7b3d1
CW		 8706 DRM_ERROR("no such CRTC id\n");
8707 return -EINVAL;
8708 }
8709
c05422d5
DV		 8710 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8711 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8712
c05422d5 8713 return 0;
08d7b3d1
CW		 8714}
8715
66a9278e 8716static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8717{
66a9278e
DV		 8718 struct drm_device *dev = encoder->base.dev;
8719 struct intel_encoder *source_encoder;
79e53945 8720 int index_mask = 0;
79e53945
JB		 8721 int entry = 0;
8722
66a9278e
DV		 8723 list_for_each_entry(source_encoder,
8724 &dev->mode_config.encoder_list, base.head) {
8725
8726 if (encoder == source_encoder)
79e53945 8727 index_mask |= (1 << entry);
66a9278e
DV		 8728
8729 /* Intel hw has only one MUX where enocoders could be cloned. */
8730 if (encoder->cloneable && source_encoder->cloneable)
8731 index_mask |= (1 << entry);
8732
79e53945
JB		 8733 entry++;
8734 }
4ef69c7a 8735
79e53945
JB		 8736 return index_mask;
8737}
8738
4d302442
CW		 8739static bool has_edp_a(struct drm_device *dev)
8740{
8741 struct drm_i915_private *dev_priv = dev->dev_private;
8742
8743 if (!IS_MOBILE(dev))
8744 return false;
8745
8746 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8747 return false;
8748
8749 if (IS_GEN5(dev) &&
8750 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8751 return false;
8752
8753 return true;
8754}
8755
79e53945
JB		 8756static void intel_setup_outputs(struct drm_device *dev)
8757{
725e30ad 8758 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8759 struct intel_encoder *encoder;
cb0953d7 8760 bool dpd_is_edp = false;
f3cfcba6 8761 bool has_lvds;
79e53945 8762
f3cfcba6 8763 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8764 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8765 /* disable the panel fitter on everything but LVDS */
8766 I915_WRITE(PFIT_CONTROL, 0);
8767 }
79e53945 8768
c40c0f5b 8769 if (!IS_ULT(dev))
79935fca 8770 intel_crt_init(dev);
cb0953d7 8771
affa9354 8772 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8773 int found;
8774
8775 /* Haswell uses DDI functions to detect digital outputs */
8776 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8777 /* DDI A only supports eDP */
8778 if (found)
8779 intel_ddi_init(dev, PORT_A);
8780
8781 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8782 * register */
8783 found = I915_READ(SFUSE_STRAP);
8784
8785 if (found & SFUSE_STRAP_DDIB_DETECTED)
8786 intel_ddi_init(dev, PORT_B);
8787 if (found & SFUSE_STRAP_DDIC_DETECTED)
8788 intel_ddi_init(dev, PORT_C);
8789 if (found & SFUSE_STRAP_DDID_DETECTED)
8790 intel_ddi_init(dev, PORT_D);
8791 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8792 int found;
270b3042
DV		 8793 dpd_is_edp = intel_dpd_is_edp(dev);
8794
8795 if (has_edp_a(dev))
8796 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8797
dc0fa718 8798 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8799 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8800 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8801 if (!found)
e2debe91 8802 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8803 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8804 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8805 }
8806
dc0fa718 8807 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8808 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8809
dc0fa718 8810 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8811 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8812
5eb08b69 8813 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8814 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8815
270b3042 8816 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8817 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8818 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8819 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8820 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8821 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8822
dc0fa718 8823 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8824 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8825 PORT_B);
67cfc203
VS		 8826 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8827 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8828 }
103a196f 8829 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8830 bool found = false;
7d57382e 8831
e2debe91 8832 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8833 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8834 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8835 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8836 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8837 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8838 }
27185ae1 8839
e7281eab 8840 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8841 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8842 }
13520b05
KH		 8843
8844 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8845
e2debe91 8846 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8847 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8848 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8849 }
27185ae1 8850
e2debe91 8851 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8852
b01f2c3a
JB		 8853 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8854 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8855 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8856 }
e7281eab 8857 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8858 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8859 }
27185ae1 8860
b01f2c3a 8861 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8862 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8863 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8864 } else if (IS_GEN2(dev))
79e53945
JB		 8865 intel_dvo_init(dev);
8866
103a196f 8867 if (SUPPORTS_TV(dev))
79e53945
JB		 8868 intel_tv_init(dev);
8869
4ef69c7a
CW		 8870 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8871 encoder->base.possible_crtcs = encoder->crtc_mask;
8872 encoder->base.possible_clones =
66a9278e 8873 intel_encoder_clones(encoder);
79e53945 8874 }
47356eb6 8875
dde86e2d 8876 intel_init_pch_refclk(dev);
270b3042
DV		 8877
8878 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8879}
8880
8881static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8882{
8883 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8884
8885 drm_framebuffer_cleanup(fb);
05394f39 8886 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8887
8888 kfree(intel_fb);
8889}
8890
8891static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8892 struct drm_file *file,
79e53945
JB		 8893 unsigned int *handle)
8894{
8895 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8896 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8897
05394f39 8898 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8899}
8900
8901static const struct drm_framebuffer_funcs intel_fb_funcs = {
8902 .destroy = intel_user_framebuffer_destroy,
8903 .create_handle = intel_user_framebuffer_create_handle,
8904};
8905
38651674
DA		 8906int intel_framebuffer_init(struct drm_device *dev,
8907 struct intel_framebuffer *intel_fb,
308e5bcb 8908 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8909 struct drm_i915_gem_object *obj)
79e53945 8910{
79e53945
JB		 8911 int ret;
8912
c16ed4be
CW		 8913 if (obj->tiling_mode == I915_TILING_Y) {
8914 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8915 return -EINVAL;
c16ed4be 8916 }
57cd6508 8917
c16ed4be
CW		 8918 if (mode_cmd->pitches[0] & 63) {
8919 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8920 mode_cmd->pitches[0]);
57cd6508 8921 return -EINVAL;
c16ed4be 8922 }
57cd6508 8923
5d7bd705 8924 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8925 if (mode_cmd->pitches[0] > 32768) {
8926 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8927 mode_cmd->pitches[0]);
5d7bd705 8928 return -EINVAL;
c16ed4be 8929 }
5d7bd705
VS		 8930
8931 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8932 mode_cmd->pitches[0] != obj->stride) {
8933 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8934 mode_cmd->pitches[0], obj->stride);
5d7bd705 8935 return -EINVAL;
c16ed4be 8936 }
5d7bd705 8937
57779d06 8938 /* Reject formats not supported by any plane early. */
308e5bcb 8939 switch (mode_cmd->pixel_format) {
57779d06 8940 case DRM_FORMAT_C8:
04b3924d
VS		 8941 case DRM_FORMAT_RGB565:
8942 case DRM_FORMAT_XRGB8888:
8943 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8944 break;
8945 case DRM_FORMAT_XRGB1555:
8946 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8947 if (INTEL_INFO(dev)->gen > 3) {
8948 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8949 return -EINVAL;
c16ed4be 8950 }
57779d06
VS		 8951 break;
8952 case DRM_FORMAT_XBGR8888:
8953 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8954 case DRM_FORMAT_XRGB2101010:
8955 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8956 case DRM_FORMAT_XBGR2101010:
8957 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8958 if (INTEL_INFO(dev)->gen < 4) {
8959 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8960 return -EINVAL;
c16ed4be 8961 }
b5626747 8962 break;
04b3924d
VS		 8963 case DRM_FORMAT_YUYV:
8964 case DRM_FORMAT_UYVY:
8965 case DRM_FORMAT_YVYU:
8966 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8967 if (INTEL_INFO(dev)->gen < 5) {
8968 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8969 return -EINVAL;
c16ed4be 8970 }
57cd6508
CW		 8971 break;
8972 default:
c16ed4be 8973 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8974 return -EINVAL;
8975 }
8976
90f9a336
VS		 8977 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8978 if (mode_cmd->offsets[0] != 0)
8979 return -EINVAL;
8980
c7d73f6a
DV		 8981 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8982 intel_fb->obj = obj;
8983
79e53945
JB		 8984 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8985 if (ret) {
8986 DRM_ERROR("framebuffer init failed %d\n", ret);
8987 return ret;
8988 }
8989
79e53945
JB		 8990 return 0;
8991}
8992
79e53945
JB		 8993static struct drm_framebuffer *
8994intel_user_framebuffer_create(struct drm_device *dev,
8995 struct drm_file *filp,
308e5bcb 8996 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8997{
05394f39 8998 struct drm_i915_gem_object *obj;
79e53945 8999
308e5bcb
JB		 9000 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9001 mode_cmd->handles[0]));
c8725226 9002 if (&obj->base == NULL)
cce13ff7 9003 return ERR_PTR(-ENOENT);
79e53945 9004
d2dff872 9005 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9006}
9007
79e53945 9008static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9009 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9010 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9011};
9012
e70236a8
JB		 9013/* Set up chip specific display functions */
9014static void intel_init_display(struct drm_device *dev)
9015{
9016 struct drm_i915_private *dev_priv = dev->dev_private;
9017
affa9354 9018 if (HAS_DDI(dev)) {
0e8ffe1b 9019 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9020 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9021 dev_priv->display.crtc_enable = haswell_crtc_enable;
9022 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9023 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9024 dev_priv->display.update_plane = ironlake_update_plane;
9025 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9026 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9027 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9028 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9029 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9030 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9031 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9032 } else if (IS_VALLEYVIEW(dev)) {
9033 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9034 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9035 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9036 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9037 dev_priv->display.off = i9xx_crtc_off;
9038 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9039 } else {
0e8ffe1b 9040 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9041 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9042 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9043 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9044 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9045 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9046 }
e70236a8 9047
e70236a8 9048 /* Returns the core display clock speed */
25eb05fc
JB		 9049 if (IS_VALLEYVIEW(dev))
9050 dev_priv->display.get_display_clock_speed =
9051 valleyview_get_display_clock_speed;
9052 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9053 dev_priv->display.get_display_clock_speed =
9054 i945_get_display_clock_speed;
9055 else if (IS_I915G(dev))
9056 dev_priv->display.get_display_clock_speed =
9057 i915_get_display_clock_speed;
f2b115e6 9058 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9059 dev_priv->display.get_display_clock_speed =
9060 i9xx_misc_get_display_clock_speed;
9061 else if (IS_I915GM(dev))
9062 dev_priv->display.get_display_clock_speed =
9063 i915gm_get_display_clock_speed;
9064 else if (IS_I865G(dev))
9065 dev_priv->display.get_display_clock_speed =
9066 i865_get_display_clock_speed;
f0f8a9ce 9067 else if (IS_I85X(dev))
e70236a8
JB		 9068 dev_priv->display.get_display_clock_speed =
9069 i855_get_display_clock_speed;
9070 else /* 852, 830 */
9071 dev_priv->display.get_display_clock_speed =
9072 i830_get_display_clock_speed;
9073
7f8a8569 9074 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9075 if (IS_GEN5(dev)) {
674cf967 9076 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9077 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9078 } else if (IS_GEN6(dev)) {
674cf967 9079 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9080 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9081 } else if (IS_IVYBRIDGE(dev)) {
9082 /* FIXME: detect B0+ stepping and use auto training */
9083 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9084 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9085 dev_priv->display.modeset_global_resources =
9086 ivb_modeset_global_resources;
c82e4d26
ED		 9087 } else if (IS_HASWELL(dev)) {
9088 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9089 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9090 dev_priv->display.modeset_global_resources =
9091 haswell_modeset_global_resources;
a0e63c22 9092 }
6067aaea 9093 } else if (IS_G4X(dev)) {
e0dac65e 9094 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9095 }
8c9f3aaf
JB		 9096
9097 /* Default just returns -ENODEV to indicate unsupported */
9098 dev_priv->display.queue_flip = intel_default_queue_flip;
9099
9100 switch (INTEL_INFO(dev)->gen) {
9101 case 2:
9102 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9103 break;
9104
9105 case 3:
9106 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9107 break;
9108
9109 case 4:
9110 case 5:
9111 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9112 break;
9113
9114 case 6:
9115 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9116 break;
7c9017e5
JB		 9117 case 7:
9118 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9119 break;
8c9f3aaf 9120 }
e70236a8
JB		 9121}
9122
b690e96c
JB		 9123/*
9124 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9125 * resume, or other times. This quirk makes sure that's the case for
9126 * affected systems.
9127 */
0206e353 9128static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9129{
9130 struct drm_i915_private *dev_priv = dev->dev_private;
9131
9132 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9133 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9134}
9135
435793df
KP		 9136/*
9137 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9138 */
9139static void quirk_ssc_force_disable(struct drm_device *dev)
9140{
9141 struct drm_i915_private *dev_priv = dev->dev_private;
9142 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9143 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9144}
9145
4dca20ef 9146/*
5a15ab5b
CE		 9147 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9148 * brightness value
4dca20ef
CE		 9149 */
9150static void quirk_invert_brightness(struct drm_device *dev)
9151{
9152 struct drm_i915_private *dev_priv = dev->dev_private;
9153 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9154 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9155}
9156
b690e96c
JB		 9157struct intel_quirk {
9158 int device;
9159 int subsystem_vendor;
9160 int subsystem_device;
9161 void (*hook)(struct drm_device *dev);
9162};
9163
5f85f176
EE		 9164/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9165struct intel_dmi_quirk {
9166 void (*hook)(struct drm_device *dev);
9167 const struct dmi_system_id (*dmi_id_list)[];
9168};
9169
9170static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9171{
9172 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9173 return 1;
9174}
9175
9176static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9177 {
9178 .dmi_id_list = &(const struct dmi_system_id[]) {
9179 {
9180 .callback = intel_dmi_reverse_brightness,
9181 .ident = "NCR Corporation",
9182 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9183 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9184 },
9185 },
9186 { } /* terminating entry */
9187 },
9188 .hook = quirk_invert_brightness,
9189 },
9190};
9191
c43b5634 9192static struct intel_quirk intel_quirks[] = {
b690e96c 9193 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9194 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9195
b690e96c
JB		 9196 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9197 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9198
b690e96c
JB		 9199 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9200 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9201
ccd0d36e 9202 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9203 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9204 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9205
9206 /* Lenovo U160 cannot use SSC on LVDS */
9207 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9208
9209 /* Sony Vaio Y cannot use SSC on LVDS */
9210 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9211
9212 /* Acer Aspire 5734Z must invert backlight brightness */
9213 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9214
9215 /* Acer/eMachines G725 */
9216 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9217
9218 /* Acer/eMachines e725 */
9219 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9220
9221 /* Acer/Packard Bell NCL20 */
9222 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9223
9224 /* Acer Aspire 4736Z */
9225 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9226};
9227
9228static void intel_init_quirks(struct drm_device *dev)
9229{
9230 struct pci_dev *d = dev->pdev;
9231 int i;
9232
9233 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9234 struct intel_quirk *q = &intel_quirks[i];
9235
9236 if (d->device == q->device &&
9237 (d->subsystem_vendor == q->subsystem_vendor ||
9238 q->subsystem_vendor == PCI_ANY_ID) &&
9239 (d->subsystem_device == q->subsystem_device ||
9240 q->subsystem_device == PCI_ANY_ID))
9241 q->hook(dev);
9242 }
5f85f176
EE		 9243 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9244 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9245 intel_dmi_quirks[i].hook(dev);
9246 }
b690e96c
JB		 9247}
9248
9cce37f4
JB		 9249/* Disable the VGA plane that we never use */
9250static void i915_disable_vga(struct drm_device *dev)
9251{
9252 struct drm_i915_private *dev_priv = dev->dev_private;
9253 u8 sr1;
766aa1c4 9254 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9255
9256 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9257 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9258 sr1 = inb(VGA_SR_DATA);
9259 outb(sr1 | 1<<5, VGA_SR_DATA);
9260 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9261 udelay(300);
9262
9263 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9264 POSTING_READ(vga_reg);
9265}
9266
f817586c
DV		 9267void intel_modeset_init_hw(struct drm_device *dev)
9268{
fa42e23c 9269 intel_init_power_well(dev);
0232e927 9270
a8f78b58
ED		 9271 intel_prepare_ddi(dev);
9272
f817586c
DV		 9273 intel_init_clock_gating(dev);
9274
79f5b2c7 9275 mutex_lock(&dev->struct_mutex);
8090c6b9 9276 intel_enable_gt_powersave(dev);
79f5b2c7 9277 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9278}
9279
7d708ee4
ID		 9280void intel_modeset_suspend_hw(struct drm_device *dev)
9281{
9282 intel_suspend_hw(dev);
9283}
9284
79e53945
JB		 9285void intel_modeset_init(struct drm_device *dev)
9286{
652c393a 9287 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9288 int i, j, ret;
79e53945
JB		 9289
9290 drm_mode_config_init(dev);
9291
9292 dev->mode_config.min_width = 0;
9293 dev->mode_config.min_height = 0;
9294
019d96cb
DA		 9295 dev->mode_config.preferred_depth = 24;
9296 dev->mode_config.prefer_shadow = 1;
9297
e6ecefaa 9298 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9299
b690e96c
JB		 9300 intel_init_quirks(dev);
9301
1fa61106
ED		 9302 intel_init_pm(dev);
9303
e3c74757
BW		 9304 if (INTEL_INFO(dev)->num_pipes == 0)
9305 return;
9306
e70236a8
JB		 9307 intel_init_display(dev);
9308
a6c45cf0
CW		 9309 if (IS_GEN2(dev)) {
9310 dev->mode_config.max_width = 2048;
9311 dev->mode_config.max_height = 2048;
9312 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9313 dev->mode_config.max_width = 4096;
9314 dev->mode_config.max_height = 4096;
79e53945 9315 } else {
a6c45cf0
CW		 9316 dev->mode_config.max_width = 8192;
9317 dev->mode_config.max_height = 8192;
79e53945 9318 }
5d4545ae 9319 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9320
28c97730 9321 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9322 INTEL_INFO(dev)->num_pipes,
9323 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9324
7eb552ae 9325 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9326 intel_crtc_init(dev, i);
7f1f3851
JB		 9327 for (j = 0; j < dev_priv->num_plane; j++) {
9328 ret = intel_plane_init(dev, i, j);
9329 if (ret)
06da8da2
VS		 9330 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9331 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9332 }
79e53945
JB		 9333 }
9334
79f689aa 9335 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9336 intel_pch_pll_init(dev);
9337
9cce37f4
JB		 9338 /* Just disable it once at startup */
9339 i915_disable_vga(dev);
79e53945 9340 intel_setup_outputs(dev);
11be49eb
CW		 9341
9342 /* Just in case the BIOS is doing something questionable. */
9343 intel_disable_fbc(dev);
2c7111db
CW		 9344}
9345
24929352
DV		 9346static void
9347intel_connector_break_all_links(struct intel_connector *connector)
9348{
9349 connector->base.dpms = DRM_MODE_DPMS_OFF;
9350 connector->base.encoder = NULL;
9351 connector->encoder->connectors_active = false;
9352 connector->encoder->base.crtc = NULL;
9353}
9354
7fad798e
DV		 9355static void intel_enable_pipe_a(struct drm_device *dev)
9356{
9357 struct intel_connector *connector;
9358 struct drm_connector *crt = NULL;
9359 struct intel_load_detect_pipe load_detect_temp;
9360
9361 /* We can't just switch on the pipe A, we need to set things up with a
9362 * proper mode and output configuration. As a gross hack, enable pipe A
9363 * by enabling the load detect pipe once. */
9364 list_for_each_entry(connector,
9365 &dev->mode_config.connector_list,
9366 base.head) {
9367 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9368 crt = &connector->base;
9369 break;
9370 }
9371 }
9372
9373 if (!crt)
9374 return;
9375
9376 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9377 intel_release_load_detect_pipe(crt, &load_detect_temp);
9378
652c393a 9379
7fad798e
DV		 9380}
9381
fa555837
DV		 9382static bool
9383intel_check_plane_mapping(struct intel_crtc *crtc)
9384{
7eb552ae
BW		 9385 struct drm_device *dev = crtc->base.dev;
9386 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9387 u32 reg, val;
9388
7eb552ae 9389 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9390 return true;
9391
9392 reg = DSPCNTR(!crtc->plane);
9393 val = I915_READ(reg);
9394
9395 if ((val & DISPLAY_PLANE_ENABLE) &&
9396 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9397 return false;
9398
9399 return true;
9400}
9401
24929352
DV		 9402static void intel_sanitize_crtc(struct intel_crtc *crtc)
9403{
9404 struct drm_device *dev = crtc->base.dev;
9405 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9406 u32 reg;
24929352 9407
24929352 9408 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9409 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9410 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9411
9412 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9413 * disable the crtc (and hence change the state) if it is wrong. Note
9414 * that gen4+ has a fixed plane -> pipe mapping. */
9415 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9416 struct intel_connector *connector;
9417 bool plane;
9418
24929352
DV		 9419 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9420 crtc->base.base.id);
9421
9422 /* Pipe has the wrong plane attached and the plane is active.
9423 * Temporarily change the plane mapping and disable everything
9424 * ... */
9425 plane = crtc->plane;
9426 crtc->plane = !plane;
9427 dev_priv->display.crtc_disable(&crtc->base);
9428 crtc->plane = plane;
9429
9430 /* ... and break all links. */
9431 list_for_each_entry(connector, &dev->mode_config.connector_list,
9432 base.head) {
9433 if (connector->encoder->base.crtc != &crtc->base)
9434 continue;
9435
9436 intel_connector_break_all_links(connector);
9437 }
9438
9439 WARN_ON(crtc->active);
9440 crtc->base.enabled = false;
9441 }
24929352 9442
7fad798e
DV		 9443 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9444 crtc->pipe == PIPE_A && !crtc->active) {
9445 /* BIOS forgot to enable pipe A, this mostly happens after
9446 * resume. Force-enable the pipe to fix this, the update_dpms
9447 * call below we restore the pipe to the right state, but leave
9448 * the required bits on. */
9449 intel_enable_pipe_a(dev);
9450 }
9451
24929352
DV		 9452 /* Adjust the state of the output pipe according to whether we
9453 * have active connectors/encoders. */
9454 intel_crtc_update_dpms(&crtc->base);
9455
9456 if (crtc->active != crtc->base.enabled) {
9457 struct intel_encoder *encoder;
9458
9459 /* This can happen either due to bugs in the get_hw_state
9460 * functions or because the pipe is force-enabled due to the
9461 * pipe A quirk. */
9462 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9463 crtc->base.base.id,
9464 crtc->base.enabled ? "enabled" : "disabled",
9465 crtc->active ? "enabled" : "disabled");
9466
9467 crtc->base.enabled = crtc->active;
9468
9469 /* Because we only establish the connector -> encoder ->
9470 * crtc links if something is active, this means the
9471 * crtc is now deactivated. Break the links. connector
9472 * -> encoder links are only establish when things are
9473 * actually up, hence no need to break them. */
9474 WARN_ON(crtc->active);
9475
9476 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9477 WARN_ON(encoder->connectors_active);
9478 encoder->base.crtc = NULL;
9479 }
9480 }
9481}
9482
9483static void intel_sanitize_encoder(struct intel_encoder *encoder)
9484{
9485 struct intel_connector *connector;
9486 struct drm_device *dev = encoder->base.dev;
9487
9488 /* We need to check both for a crtc link (meaning that the
9489 * encoder is active and trying to read from a pipe) and the
9490 * pipe itself being active. */
9491 bool has_active_crtc = encoder->base.crtc &&
9492 to_intel_crtc(encoder->base.crtc)->active;
9493
9494 if (encoder->connectors_active && !has_active_crtc) {
9495 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9496 encoder->base.base.id,
9497 drm_get_encoder_name(&encoder->base));
9498
9499 /* Connector is active, but has no active pipe. This is
9500 * fallout from our resume register restoring. Disable
9501 * the encoder manually again. */
9502 if (encoder->base.crtc) {
9503 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9504 encoder->base.base.id,
9505 drm_get_encoder_name(&encoder->base));
9506 encoder->disable(encoder);
9507 }
9508
9509 /* Inconsistent output/port/pipe state happens presumably due to
9510 * a bug in one of the get_hw_state functions. Or someplace else
9511 * in our code, like the register restore mess on resume. Clamp
9512 * things to off as a safer default. */
9513 list_for_each_entry(connector,
9514 &dev->mode_config.connector_list,
9515 base.head) {
9516 if (connector->encoder != encoder)
9517 continue;
9518
9519 intel_connector_break_all_links(connector);
9520 }
9521 }
9522 /* Enabled encoders without active connectors will be fixed in
9523 * the crtc fixup. */
9524}
9525
44cec740 9526void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9527{
9528 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9529 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9530
9531 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9532 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9533 i915_disable_vga(dev);
0fde901f
KM		 9534 }
9535}
9536
24929352
DV		 9537/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9538 * and i915 state tracking structures. */
45e2b5f6
DV		 9539void intel_modeset_setup_hw_state(struct drm_device *dev,
9540 bool force_restore)
24929352
DV		 9541{
9542 struct drm_i915_private *dev_priv = dev->dev_private;
9543 enum pipe pipe;
9544 u32 tmp;
b5644d05 9545 struct drm_plane *plane;
24929352
DV		 9546 struct intel_crtc *crtc;
9547 struct intel_encoder *encoder;
9548 struct intel_connector *connector;
9549
affa9354 9550 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9551 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9552
9553 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9554 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9555 case TRANS_DDI_EDP_INPUT_A_ON:
9556 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9557 pipe = PIPE_A;
9558 break;
9559 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9560 pipe = PIPE_B;
9561 break;
9562 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9563 pipe = PIPE_C;
9564 break;
aaa148ec
DL		 9565 default:
9566 /* A bogus value has been programmed, disable
9567 * the transcoder */
9568 WARN(1, "Bogus eDP source %08x\n", tmp);
9569 intel_ddi_disable_transcoder_func(dev_priv,
9570 TRANSCODER_EDP);
9571 goto setup_pipes;
e28d54cb
PZ		 9572 }
9573
9574 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9575 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9576
9577 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9578 pipe_name(pipe));
9579 }
9580 }
9581
aaa148ec 9582setup_pipes:
0e8ffe1b
DV		 9583 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9584 base.head) {
3b117c8f 9585 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9586 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9587 crtc->config.cpu_transcoder = tmp;
9588
0e8ffe1b
DV		 9589 crtc->active = dev_priv->display.get_pipe_config(crtc,
9590 &crtc->config);
24929352
DV		 9591
9592 crtc->base.enabled = crtc->active;
9593
9594 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9595 crtc->base.base.id,
9596 crtc->active ? "enabled" : "disabled");
9597 }
9598
affa9354 9599 if (HAS_DDI(dev))
6441ab5f
PZ		 9600 intel_ddi_setup_hw_pll_state(dev);
9601
24929352
DV		 9602 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9603 base.head) {
9604 pipe = 0;
9605
9606 if (encoder->get_hw_state(encoder, &pipe)) {
9607 encoder->base.crtc =
9608 dev_priv->pipe_to_crtc_mapping[pipe];
9609 } else {
9610 encoder->base.crtc = NULL;
9611 }
9612
9613 encoder->connectors_active = false;
9614 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9615 encoder->base.base.id,
9616 drm_get_encoder_name(&encoder->base),
9617 encoder->base.crtc ? "enabled" : "disabled",
9618 pipe);
9619 }
9620
9621 list_for_each_entry(connector, &dev->mode_config.connector_list,
9622 base.head) {
9623 if (connector->get_hw_state(connector)) {
9624 connector->base.dpms = DRM_MODE_DPMS_ON;
9625 connector->encoder->connectors_active = true;
9626 connector->base.encoder = &connector->encoder->base;
9627 } else {
9628 connector->base.dpms = DRM_MODE_DPMS_OFF;
9629 connector->base.encoder = NULL;
9630 }
9631 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9632 connector->base.base.id,
9633 drm_get_connector_name(&connector->base),
9634 connector->base.encoder ? "enabled" : "disabled");
9635 }
9636
9637 /* HW state is read out, now we need to sanitize this mess. */
9638 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9639 base.head) {
9640 intel_sanitize_encoder(encoder);
9641 }
9642
9643 for_each_pipe(pipe) {
9644 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9645 intel_sanitize_crtc(crtc);
9646 }
9a935856 9647
45e2b5f6 9648 if (force_restore) {
f30da187
DV		 9649 /*
9650 * We need to use raw interfaces for restoring state to avoid
9651 * checking (bogus) intermediate states.
9652 */
45e2b5f6 9653 for_each_pipe(pipe) {
b5644d05
JB		 9654 struct drm_crtc *crtc =
9655 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9656
9657 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9658 crtc->fb);
45e2b5f6 9659 }
b5644d05
JB		 9660 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9661 intel_plane_restore(plane);
0fde901f
KM		 9662
9663 i915_redisable_vga(dev);
45e2b5f6
DV		 9664 } else {
9665 intel_modeset_update_staged_output_state(dev);
9666 }
8af6cf88
DV		 9667
9668 intel_modeset_check_state(dev);
2e938892
DV		 9669
9670 drm_mode_config_reset(dev);
2c7111db
CW		 9671}
9672
9673void intel_modeset_gem_init(struct drm_device *dev)
9674{
1833b134 9675 intel_modeset_init_hw(dev);
02e792fb
DV		 9676
9677 intel_setup_overlay(dev);
24929352 9678
45e2b5f6 9679 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9680}
9681
9682void intel_modeset_cleanup(struct drm_device *dev)
9683{
652c393a
JB		 9684 struct drm_i915_private *dev_priv = dev->dev_private;
9685 struct drm_crtc *crtc;
9686 struct intel_crtc *intel_crtc;
9687
fd0c0642
DV		 9688 /*
9689 * Interrupts and polling as the first thing to avoid creating havoc.
9690 * Too much stuff here (turning of rps, connectors, ...) would
9691 * experience fancy races otherwise.
9692 */
9693 drm_irq_uninstall(dev);
9694 cancel_work_sync(&dev_priv->hotplug_work);
9695 /*
9696 * Due to the hpd irq storm handling the hotplug work can re-arm the
9697 * poll handlers. Hence disable polling after hpd handling is shut down.
9698 */
f87ea761 9699 drm_kms_helper_poll_fini(dev);
fd0c0642 9700
652c393a
JB		 9701 mutex_lock(&dev->struct_mutex);
9702
723bfd70
JB		 9703 intel_unregister_dsm_handler();
9704
652c393a
JB		 9705 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9706 /* Skip inactive CRTCs */
9707 if (!crtc->fb)
9708 continue;
9709
9710 intel_crtc = to_intel_crtc(crtc);
3dec0095 9711 intel_increase_pllclock(crtc);
652c393a
JB		 9712 }
9713
973d04f9 9714 intel_disable_fbc(dev);
e70236a8 9715
8090c6b9 9716 intel_disable_gt_powersave(dev);
0cdab21f 9717
930ebb46
DV		 9718 ironlake_teardown_rc6(dev);
9719
69341a5e
KH		 9720 mutex_unlock(&dev->struct_mutex);
9721
1630fe75
CW		 9722 /* flush any delayed tasks or pending work */
9723 flush_scheduled_work();
9724
dc652f90
JN		 9725 /* destroy backlight, if any, before the connectors */
9726 intel_panel_destroy_backlight(dev);
9727
79e53945 9728 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9729
9730 intel_cleanup_overlay(dev);
79e53945
JB		 9731}
9732
f1c79df3
ZW		 9733/*
9734 * Return which encoder is currently attached for connector.
9735 */
df0e9248 9736struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9737{
df0e9248
CW		 9738 return &intel_attached_encoder(connector)->base;
9739}
f1c79df3 9740
df0e9248
CW		 9741void intel_connector_attach_encoder(struct intel_connector *connector,
9742 struct intel_encoder *encoder)
9743{
9744 connector->encoder = encoder;
9745 drm_mode_connector_attach_encoder(&connector->base,
9746 &encoder->base);
79e53945 9747}
28d52043
DA		 9748
9749/*
9750 * set vga decode state - true == enable VGA decode
9751 */
9752int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9753{
9754 struct drm_i915_private *dev_priv = dev->dev_private;
9755 u16 gmch_ctrl;
9756
9757 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9758 if (state)
9759 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9760 else
9761 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9762 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9763 return 0;
9764}
c4a1d9e4
CW		 9765
9766#ifdef CONFIG_DEBUG_FS
9767#include <linux/seq_file.h>
9768
9769struct intel_display_error_state {
ff57f1b0
PZ		 9770
9771 u32 power_well_driver;
9772
c4a1d9e4
CW		 9773 struct intel_cursor_error_state {
9774 u32 control;
9775 u32 position;
9776 u32 base;
9777 u32 size;
52331309 9778 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9779
9780 struct intel_pipe_error_state {
ff57f1b0 9781 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9782 u32 conf;
9783 u32 source;
9784
9785 u32 htotal;
9786 u32 hblank;
9787 u32 hsync;
9788 u32 vtotal;
9789 u32 vblank;
9790 u32 vsync;
52331309 9791 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9792
9793 struct intel_plane_error_state {
9794 u32 control;
9795 u32 stride;
9796 u32 size;
9797 u32 pos;
9798 u32 addr;
9799 u32 surface;
9800 u32 tile_offset;
52331309 9801 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9802};
9803
9804struct intel_display_error_state *
9805intel_display_capture_error_state(struct drm_device *dev)
9806{
0206e353 9807 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9808 struct intel_display_error_state *error;
702e7a56 9809 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9810 int i;
9811
9812 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9813 if (error == NULL)
9814 return NULL;
9815
ff57f1b0
PZ		 9816 if (HAS_POWER_WELL(dev))
9817 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9818
52331309 9819 for_each_pipe(i) {
702e7a56 9820 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9821 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9822
a18c4c3d
PZ		 9823 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9824 error->cursor[i].control = I915_READ(CURCNTR(i));
9825 error->cursor[i].position = I915_READ(CURPOS(i));
9826 error->cursor[i].base = I915_READ(CURBASE(i));
9827 } else {
9828 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9829 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9830 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9831 }
c4a1d9e4
CW		 9832
9833 error->plane[i].control = I915_READ(DSPCNTR(i));
9834 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9835 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9836 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9837 error->plane[i].pos = I915_READ(DSPPOS(i));
9838 }
ca291363
PZ		 9839 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9840 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9841 if (INTEL_INFO(dev)->gen >= 4) {
9842 error->plane[i].surface = I915_READ(DSPSURF(i));
9843 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9844 }
9845
702e7a56 9846 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9847 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9848 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9849 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9850 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9851 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9852 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9853 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9854 }
9855
12d217c7
PZ		 9856 /* In the code above we read the registers without checking if the power
9857 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9858 * prevent the next I915_WRITE from detecting it and printing an error
9859 * message. */
9860 if (HAS_POWER_WELL(dev))
9861 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9862
c4a1d9e4
CW		 9863 return error;
9864}
9865
9866void
9867intel_display_print_error_state(struct seq_file *m,
9868 struct drm_device *dev,
9869 struct intel_display_error_state *error)
9870{
9871 int i;
9872
7eb552ae 9873 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0
PZ		 9874 if (HAS_POWER_WELL(dev))
9875 seq_printf(m, "PWR_WELL_CTL2: %08x\n",
9876 error->power_well_driver);
52331309 9877 for_each_pipe(i) {
c4a1d9e4 9878 seq_printf(m, "Pipe [%d]:\n", i);
ff57f1b0
PZ		 9879 seq_printf(m, " CPU transcoder: %c\n",
9880 transcoder_name(error->pipe[i].cpu_transcoder));
c4a1d9e4
CW		 9881 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9882 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9883 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9884 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9885 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9886 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9887 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9888 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9889
9890 seq_printf(m, "Plane [%d]:\n", i);
9891 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9892 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9893 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9894 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9895 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9896 }
4b71a570 9897 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9898 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9899 if (INTEL_INFO(dev)->gen >= 4) {
9900 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9901 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9902 }
9903
9904 seq_printf(m, "Cursor [%d]:\n", i);
9905 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9906 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9907 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9908 }
9909}
9910#endif
Linux kernel - Deliverables
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