projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Add a simple atomic crtc check function, v2.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
568c634a 89static int intel_set_mode(struct drm_atomic_state *state);
eb1bfe80
JB		 90static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
5b18e57c
DV		 94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
29407aab 99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 102static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
d288f65f 104static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 105 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 106static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 108static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
ce22dba9
ML		 112static void intel_crtc_enable_planes(struct drm_crtc *crtc);
113static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 114
0e32b39c
DA		 115static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
116{
117 if (!connector->mst_port)
118 return connector->encoder;
119 else
120 return &connector->mst_port->mst_encoders[pipe]->base;
121}
122
79e53945 123typedef struct {
0206e353 124 int min, max;
79e53945
JB		 125} intel_range_t;
126
127typedef struct {
0206e353
AJ		 128 int dot_limit;
129 int p2_slow, p2_fast;
79e53945
JB		 130} intel_p2_t;
131
d4906093
ML		 132typedef struct intel_limit intel_limit_t;
133struct intel_limit {
0206e353
AJ		 134 intel_range_t dot, vco, n, m, m1, m2, p, p1;
135 intel_p2_t p2;
d4906093 136};
79e53945 137
d2acd215
DV		 138int
139intel_pch_rawclk(struct drm_device *dev)
140{
141 struct drm_i915_private *dev_priv = dev->dev_private;
142
143 WARN_ON(!HAS_PCH_SPLIT(dev));
144
145 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
146}
147
021357ac
CW		 148static inline u32 /* units of 100MHz */
149intel_fdi_link_freq(struct drm_device *dev)
150{
8b99e68c
CW		 151 if (IS_GEN5(dev)) {
152 struct drm_i915_private *dev_priv = dev->dev_private;
153 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
154 } else
155 return 27;
021357ac
CW		 156}
157
5d536e28 158static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 159 .dot = { .min = 25000, .max = 350000 },
9c333719 160 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 161 .n = { .min = 2, .max = 16 },
0206e353
AJ		 162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 169};
170
5d536e28
DV		 171static const intel_limit_t intel_limits_i8xx_dvo = {
172 .dot = { .min = 25000, .max = 350000 },
9c333719 173 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 174 .n = { .min = 2, .max = 16 },
5d536e28
DV		 175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 2, .max = 33 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 4, .p2_fast = 4 },
182};
183
e4b36699 184static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 185 .dot = { .min = 25000, .max = 350000 },
9c333719 186 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 187 .n = { .min = 2, .max = 16 },
0206e353
AJ		 188 .m = { .min = 96, .max = 140 },
189 .m1 = { .min = 18, .max = 26 },
190 .m2 = { .min = 6, .max = 16 },
191 .p = { .min = 4, .max = 128 },
192 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 14, .p2_fast = 7 },
e4b36699 195};
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 206 .p2 = { .dot_limit = 200000,
207 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 208};
209
210static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 211 .dot = { .min = 20000, .max = 400000 },
212 .vco = { .min = 1400000, .max = 2800000 },
213 .n = { .min = 1, .max = 6 },
214 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 215 .m1 = { .min = 8, .max = 18 },
216 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 217 .p = { .min = 7, .max = 98 },
218 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 219 .p2 = { .dot_limit = 112000,
220 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 221};
222
273e27ca 223
e4b36699 224static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 225 .dot = { .min = 25000, .max = 270000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 4 },
228 .m = { .min = 104, .max = 138 },
229 .m1 = { .min = 17, .max = 23 },
230 .m2 = { .min = 5, .max = 11 },
231 .p = { .min = 10, .max = 30 },
232 .p1 = { .min = 1, .max = 3},
233 .p2 = { .dot_limit = 270000,
234 .p2_slow = 10,
235 .p2_fast = 10
044c7c41 236 },
e4b36699
KP		 237};
238
239static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 240 .dot = { .min = 22000, .max = 400000 },
241 .vco = { .min = 1750000, .max = 3500000},
242 .n = { .min = 1, .max = 4 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 16, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 5, .max = 80 },
247 .p1 = { .min = 1, .max = 8},
248 .p2 = { .dot_limit = 165000,
249 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 250};
251
252static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 253 .dot = { .min = 20000, .max = 115000 },
254 .vco = { .min = 1750000, .max = 3500000 },
255 .n = { .min = 1, .max = 3 },
256 .m = { .min = 104, .max = 138 },
257 .m1 = { .min = 17, .max = 23 },
258 .m2 = { .min = 5, .max = 11 },
259 .p = { .min = 28, .max = 112 },
260 .p1 = { .min = 2, .max = 8 },
261 .p2 = { .dot_limit = 0,
262 .p2_slow = 14, .p2_fast = 14
044c7c41 263 },
e4b36699
KP		 264};
265
266static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 267 .dot = { .min = 80000, .max = 224000 },
268 .vco = { .min = 1750000, .max = 3500000 },
269 .n = { .min = 1, .max = 3 },
270 .m = { .min = 104, .max = 138 },
271 .m1 = { .min = 17, .max = 23 },
272 .m2 = { .min = 5, .max = 11 },
273 .p = { .min = 14, .max = 42 },
274 .p1 = { .min = 2, .max = 6 },
275 .p2 = { .dot_limit = 0,
276 .p2_slow = 7, .p2_fast = 7
044c7c41 277 },
e4b36699
KP		 278};
279
f2b115e6 280static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 281 .dot = { .min = 20000, .max = 400000},
282 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 283 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 284 .n = { .min = 3, .max = 6 },
285 .m = { .min = 2, .max = 256 },
273e27ca 286 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 291 .p2 = { .dot_limit = 200000,
292 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 293};
294
f2b115e6 295static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 296 .dot = { .min = 20000, .max = 400000 },
297 .vco = { .min = 1700000, .max = 3500000 },
298 .n = { .min = 3, .max = 6 },
299 .m = { .min = 2, .max = 256 },
300 .m1 = { .min = 0, .max = 0 },
301 .m2 = { .min = 0, .max = 254 },
302 .p = { .min = 7, .max = 112 },
303 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 304 .p2 = { .dot_limit = 112000,
305 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 306};
307
273e27ca
EA		 308/* Ironlake / Sandybridge
309 *
310 * We calculate clock using (register_value + 2) for N/M1/M2, so here
311 * the range value for them is (actual_value - 2).
312 */
b91ad0ec 313static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 5 },
317 .m = { .min = 79, .max = 127 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 5, .max = 80 },
321 .p1 = { .min = 1, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 324};
325
b91ad0ec 326static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 118 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 28, .max = 112 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 127 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 56 },
347 .p1 = { .min = 2, .max = 8 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 350};
351
273e27ca 352/* LVDS 100mhz refclk limits. */
b91ad0ec 353static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 28, .max = 112 },
0206e353 361 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 364};
365
366static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 367 .dot = { .min = 25000, .max = 350000 },
368 .vco = { .min = 1760000, .max = 3510000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 79, .max = 126 },
371 .m1 = { .min = 12, .max = 22 },
372 .m2 = { .min = 5, .max = 9 },
373 .p = { .min = 14, .max = 42 },
0206e353 374 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 375 .p2 = { .dot_limit = 225000,
376 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 377};
378
dc730512 379static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 380 /*
381 * These are the data rate limits (measured in fast clocks)
382 * since those are the strictest limits we have. The fast
383 * clock and actual rate limits are more relaxed, so checking
384 * them would make no difference.
385 */
386 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 387 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 388 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 389 .m1 = { .min = 2, .max = 3 },
390 .m2 = { .min = 11, .max = 156 },
b99ab663 391 .p1 = { .min = 2, .max = 3 },
5fdc9c49 392 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 393};
394
ef9348c8
CML		 395static const intel_limit_t intel_limits_chv = {
396 /*
397 * These are the data rate limits (measured in fast clocks)
398 * since those are the strictest limits we have. The fast
399 * clock and actual rate limits are more relaxed, so checking
400 * them would make no difference.
401 */
402 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 403 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 404 .n = { .min = 1, .max = 1 },
405 .m1 = { .min = 2, .max = 2 },
406 .m2 = { .min = 24 << 22, .max = 175 << 22 },
407 .p1 = { .min = 2, .max = 4 },
408 .p2 = { .p2_slow = 1, .p2_fast = 14 },
409};
410
5ab7b0b7
ID		 411static const intel_limit_t intel_limits_bxt = {
412 /* FIXME: find real dot limits */
413 .dot = { .min = 0, .max = INT_MAX },
414 .vco = { .min = 4800000, .max = 6480000 },
415 .n = { .min = 1, .max = 1 },
416 .m1 = { .min = 2, .max = 2 },
417 /* FIXME: find real m2 limits */
418 .m2 = { .min = 2 << 22, .max = 255 << 22 },
419 .p1 = { .min = 2, .max = 4 },
420 .p2 = { .p2_slow = 1, .p2_fast = 20 },
421};
422
6b4bf1c4
VS		 423static void vlv_clock(int refclk, intel_clock_t *clock)
424{
425 clock->m = clock->m1 * clock->m2;
426 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 427 if (WARN_ON(clock->n == 0 || clock->p == 0))
428 return;
fb03ac01
VS		 429 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
430 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 431}
432
cdba954e
ACO		 433static bool
434needs_modeset(struct drm_crtc_state *state)
435{
436 return state->mode_changed || state->active_changed;
437}
438
e0638cdf
PZ		 439/**
440 * Returns whether any output on the specified pipe is of the specified type
441 */
4093561b 442bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 443{
409ee761 444 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 445 struct intel_encoder *encoder;
446
409ee761 447 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 448 if (encoder->type == type)
449 return true;
450
451 return false;
452}
453
d0737e1d
ACO		 454/**
455 * Returns whether any output on the specified pipe will have the specified
456 * type after a staged modeset is complete, i.e., the same as
457 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
458 * encoder->crtc.
459 */
a93e255f
ACO		 460static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
461 int type)
d0737e1d 462{
a93e255f 463 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 464 struct drm_connector *connector;
a93e255f 465 struct drm_connector_state *connector_state;
d0737e1d 466 struct intel_encoder *encoder;
a93e255f
ACO		 467 int i, num_connectors = 0;
468
da3ced29 469 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 470 if (connector_state->crtc != crtc_state->base.crtc)
471 continue;
472
473 num_connectors++;
d0737e1d 474
a93e255f
ACO		 475 encoder = to_intel_encoder(connector_state->best_encoder);
476 if (encoder->type == type)
d0737e1d 477 return true;
a93e255f
ACO		 478 }
479
480 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 481
482 return false;
483}
484
a93e255f
ACO		 485static const intel_limit_t *
486intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 487{
a93e255f 488 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 489 const intel_limit_t *limit;
b91ad0ec 490
a93e255f 491 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 492 if (intel_is_dual_link_lvds(dev)) {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_dual_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_dual_lvds;
497 } else {
1b894b59 498 if (refclk == 100000)
b91ad0ec
ZW		 499 limit = &intel_limits_ironlake_single_lvds_100m;
500 else
501 limit = &intel_limits_ironlake_single_lvds;
502 }
c6bb3538 503 } else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
a93e255f
ACO		 509static const intel_limit_t *
510intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 511{
a93e255f 512 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 513 const intel_limit_t *limit;
514
a93e255f 515 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 516 if (intel_is_dual_link_lvds(dev))
e4b36699 517 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 518 else
e4b36699 519 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 520 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
521 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 522 limit = &intel_limits_g4x_hdmi;
a93e255f 523 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 524 limit = &intel_limits_g4x_sdvo;
044c7c41 525 } else /* The option is for other outputs */
e4b36699 526 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 527
528 return limit;
529}
530
a93e255f
ACO		 531static const intel_limit_t *
532intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 533{
a93e255f 534 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 535 const intel_limit_t *limit;
536
5ab7b0b7
ID		 537 if (IS_BROXTON(dev))
538 limit = &intel_limits_bxt;
539 else if (HAS_PCH_SPLIT(dev))
a93e255f 540 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 541 else if (IS_G4X(dev)) {
a93e255f 542 limit = intel_g4x_limit(crtc_state);
f2b115e6 543 } else if (IS_PINEVIEW(dev)) {
a93e255f 544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 545 limit = &intel_limits_pineview_lvds;
2177832f 546 else
f2b115e6 547 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 548 } else if (IS_CHERRYVIEW(dev)) {
549 limit = &intel_limits_chv;
a0c4da24 550 } else if (IS_VALLEYVIEW(dev)) {
dc730512 551 limit = &intel_limits_vlv;
a6c45cf0 552 } else if (!IS_GEN2(dev)) {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 554 limit = &intel_limits_i9xx_lvds;
555 else
556 limit = &intel_limits_i9xx_sdvo;
79e53945 557 } else {
a93e255f 558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 559 limit = &intel_limits_i8xx_lvds;
a93e255f 560 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 561 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 562 else
563 limit = &intel_limits_i8xx_dac;
79e53945
JB		 564 }
565 return limit;
566}
567
f2b115e6
AJ		 568/* m1 is reserved as 0 in Pineview, n is a ring counter */
569static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 570{
2177832f
SL		 571 clock->m = clock->m2 + 2;
572 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 573 if (WARN_ON(clock->n == 0 || clock->p == 0))
574 return;
fb03ac01
VS		 575 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
576 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 577}
578
7429e9d4
DV		 579static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
580{
581 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
582}
583
ac58c3f0 584static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 585{
7429e9d4 586 clock->m = i9xx_dpll_compute_m(clock);
79e53945 587 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 588 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
589 return;
fb03ac01
VS		 590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 592}
593
ef9348c8
CML		 594static void chv_clock(int refclk, intel_clock_t *clock)
595{
596 clock->m = clock->m1 * clock->m2;
597 clock->p = clock->p1 * clock->p2;
598 if (WARN_ON(clock->n == 0 || clock->p == 0))
599 return;
600 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
601 clock->n << 22);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
603}
604
7c04d1d9 605#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 606/**
607 * Returns whether the given set of divisors are valid for a given refclk with
608 * the given connectors.
609 */
610
1b894b59
CW		 611static bool intel_PLL_is_valid(struct drm_device *dev,
612 const intel_limit_t *limit,
613 const intel_clock_t *clock)
79e53945 614{
f01b7962
VS		 615 if (clock->n < limit->n.min || limit->n.max < clock->n)
616 INTELPllInvalid("n out of range\n");
79e53945 617 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 618 INTELPllInvalid("p1 out of range\n");
79e53945 619 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 620 INTELPllInvalid("m2 out of range\n");
79e53945 621 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 622 INTELPllInvalid("m1 out of range\n");
f01b7962 623
5ab7b0b7 624 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 625 if (clock->m1 <= clock->m2)
626 INTELPllInvalid("m1 <= m2\n");
627
5ab7b0b7 628 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 629 if (clock->p < limit->p.min || limit->p.max < clock->p)
630 INTELPllInvalid("p out of range\n");
631 if (clock->m < limit->m.min || limit->m.max < clock->m)
632 INTELPllInvalid("m out of range\n");
633 }
634
79e53945 635 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 636 INTELPllInvalid("vco out of range\n");
79e53945
JB		 637 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
638 * connector, etc., rather than just a single range.
639 */
640 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 641 INTELPllInvalid("dot out of range\n");
79e53945
JB		 642
643 return true;
644}
645
d4906093 646static bool
a93e255f
ACO		 647i9xx_find_best_dpll(const intel_limit_t *limit,
648 struct intel_crtc_state *crtc_state,
cec2f356
SP		 649 int target, int refclk, intel_clock_t *match_clock,
650 intel_clock_t *best_clock)
79e53945 651{
a93e255f 652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 653 struct drm_device *dev = crtc->base.dev;
79e53945 654 intel_clock_t clock;
79e53945
JB		 655 int err = target;
656
a93e255f 657 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 658 /*
a210b028
DV		 659 * For LVDS just rely on its current settings for dual-channel.
660 * We haven't figured out how to reliably set up different
661 * single/dual channel state, if we even can.
79e53945 662 */
1974cad0 663 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 664 clock.p2 = limit->p2.p2_fast;
665 else
666 clock.p2 = limit->p2.p2_slow;
667 } else {
668 if (target < limit->p2.dot_limit)
669 clock.p2 = limit->p2.p2_slow;
670 else
671 clock.p2 = limit->p2.p2_fast;
672 }
673
0206e353 674 memset(best_clock, 0, sizeof(*best_clock));
79e53945 675
42158660
ZY		 676 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
677 clock.m1++) {
678 for (clock.m2 = limit->m2.min;
679 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 680 if (clock.m2 >= clock.m1)
42158660
ZY		 681 break;
682 for (clock.n = limit->n.min;
683 clock.n <= limit->n.max; clock.n++) {
684 for (clock.p1 = limit->p1.min;
685 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 686 int this_err;
687
ac58c3f0
DV		 688 i9xx_clock(refclk, &clock);
689 if (!intel_PLL_is_valid(dev, limit,
690 &clock))
691 continue;
692 if (match_clock &&
693 clock.p != match_clock->p)
694 continue;
695
696 this_err = abs(clock.dot - target);
697 if (this_err < err) {
698 *best_clock = clock;
699 err = this_err;
700 }
701 }
702 }
703 }
704 }
705
706 return (err != target);
707}
708
709static bool
a93e255f
ACO		 710pnv_find_best_dpll(const intel_limit_t *limit,
711 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 712 int target, int refclk, intel_clock_t *match_clock,
713 intel_clock_t *best_clock)
79e53945 714{
a93e255f 715 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 716 struct drm_device *dev = crtc->base.dev;
79e53945 717 intel_clock_t clock;
79e53945
JB		 718 int err = target;
719
a93e255f 720 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 721 /*
a210b028
DV		 722 * For LVDS just rely on its current settings for dual-channel.
723 * We haven't figured out how to reliably set up different
724 * single/dual channel state, if we even can.
79e53945 725 */
1974cad0 726 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 727 clock.p2 = limit->p2.p2_fast;
728 else
729 clock.p2 = limit->p2.p2_slow;
730 } else {
731 if (target < limit->p2.dot_limit)
732 clock.p2 = limit->p2.p2_slow;
733 else
734 clock.p2 = limit->p2.p2_fast;
735 }
736
0206e353 737 memset(best_clock, 0, sizeof(*best_clock));
79e53945 738
42158660
ZY		 739 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
740 clock.m1++) {
741 for (clock.m2 = limit->m2.min;
742 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 743 for (clock.n = limit->n.min;
744 clock.n <= limit->n.max; clock.n++) {
745 for (clock.p1 = limit->p1.min;
746 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 747 int this_err;
748
ac58c3f0 749 pineview_clock(refclk, &clock);
1b894b59
CW		 750 if (!intel_PLL_is_valid(dev, limit,
751 &clock))
79e53945 752 continue;
cec2f356
SP		 753 if (match_clock &&
754 clock.p != match_clock->p)
755 continue;
79e53945
JB		 756
757 this_err = abs(clock.dot - target);
758 if (this_err < err) {
759 *best_clock = clock;
760 err = this_err;
761 }
762 }
763 }
764 }
765 }
766
767 return (err != target);
768}
769
d4906093 770static bool
a93e255f
ACO		 771g4x_find_best_dpll(const intel_limit_t *limit,
772 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 773 int target, int refclk, intel_clock_t *match_clock,
774 intel_clock_t *best_clock)
d4906093 775{
a93e255f 776 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 777 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 778 intel_clock_t clock;
779 int max_n;
780 bool found;
6ba770dc
AJ		 781 /* approximately equals target * 0.00585 */
782 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 783 found = false;
784
a93e255f 785 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 786 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 787 clock.p2 = limit->p2.p2_fast;
788 else
789 clock.p2 = limit->p2.p2_slow;
790 } else {
791 if (target < limit->p2.dot_limit)
792 clock.p2 = limit->p2.p2_slow;
793 else
794 clock.p2 = limit->p2.p2_fast;
795 }
796
797 memset(best_clock, 0, sizeof(*best_clock));
798 max_n = limit->n.max;
f77f13e2 799 /* based on hardware requirement, prefer smaller n to precision */
d4906093 800 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 801 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 802 for (clock.m1 = limit->m1.max;
803 clock.m1 >= limit->m1.min; clock.m1--) {
804 for (clock.m2 = limit->m2.max;
805 clock.m2 >= limit->m2.min; clock.m2--) {
806 for (clock.p1 = limit->p1.max;
807 clock.p1 >= limit->p1.min; clock.p1--) {
808 int this_err;
809
ac58c3f0 810 i9xx_clock(refclk, &clock);
1b894b59
CW		 811 if (!intel_PLL_is_valid(dev, limit,
812 &clock))
d4906093 813 continue;
1b894b59
CW		 814
815 this_err = abs(clock.dot - target);
d4906093
ML		 816 if (this_err < err_most) {
817 *best_clock = clock;
818 err_most = this_err;
819 max_n = clock.n;
820 found = true;
821 }
822 }
823 }
824 }
825 }
2c07245f
ZW		 826 return found;
827}
828
d5dd62bd
ID		 829/*
830 * Check if the calculated PLL configuration is more optimal compared to the
831 * best configuration and error found so far. Return the calculated error.
832 */
833static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
834 const intel_clock_t *calculated_clock,
835 const intel_clock_t *best_clock,
836 unsigned int best_error_ppm,
837 unsigned int *error_ppm)
838{
9ca3ba01
ID		 839 /*
840 * For CHV ignore the error and consider only the P value.
841 * Prefer a bigger P value based on HW requirements.
842 */
843 if (IS_CHERRYVIEW(dev)) {
844 *error_ppm = 0;
845
846 return calculated_clock->p > best_clock->p;
847 }
848
24be4e46
ID		 849 if (WARN_ON_ONCE(!target_freq))
850 return false;
851
d5dd62bd
ID		 852 *error_ppm = div_u64(1000000ULL *
853 abs(target_freq - calculated_clock->dot),
854 target_freq);
855 /*
856 * Prefer a better P value over a better (smaller) error if the error
857 * is small. Ensure this preference for future configurations too by
858 * setting the error to 0.
859 */
860 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
861 *error_ppm = 0;
862
863 return true;
864 }
865
866 return *error_ppm + 10 < best_error_ppm;
867}
868
a0c4da24 869static bool
a93e255f
ACO		 870vlv_find_best_dpll(const intel_limit_t *limit,
871 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 872 int target, int refclk, intel_clock_t *match_clock,
873 intel_clock_t *best_clock)
a0c4da24 874{
a93e255f 875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 876 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 877 intel_clock_t clock;
69e4f900 878 unsigned int bestppm = 1000000;
27e639bf
VS		 879 /* min update 19.2 MHz */
880 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 881 bool found = false;
a0c4da24 882
6b4bf1c4
VS		 883 target *= 5; /* fast clock */
884
885 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 886
887 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 888 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 889 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 890 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 891 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 892 clock.p = clock.p1 * clock.p2;
a0c4da24 893 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 894 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 895 unsigned int ppm;
69e4f900 896
6b4bf1c4
VS		 897 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
898 refclk * clock.m1);
899
900 vlv_clock(refclk, &clock);
43b0ac53 901
f01b7962
VS		 902 if (!intel_PLL_is_valid(dev, limit,
903 &clock))
43b0ac53
VS		 904 continue;
905
d5dd62bd
ID		 906 if (!vlv_PLL_is_optimal(dev, target,
907 &clock,
908 best_clock,
909 bestppm, &ppm))
910 continue;
6b4bf1c4 911
d5dd62bd
ID		 912 *best_clock = clock;
913 bestppm = ppm;
914 found = true;
a0c4da24
JB		 915 }
916 }
917 }
918 }
a0c4da24 919
49e497ef 920 return found;
a0c4da24 921}
a4fc5ed6 922
ef9348c8 923static bool
a93e255f
ACO		 924chv_find_best_dpll(const intel_limit_t *limit,
925 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 926 int target, int refclk, intel_clock_t *match_clock,
927 intel_clock_t *best_clock)
928{
a93e255f 929 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 930 struct drm_device *dev = crtc->base.dev;
9ca3ba01 931 unsigned int best_error_ppm;
ef9348c8
CML		 932 intel_clock_t clock;
933 uint64_t m2;
934 int found = false;
935
936 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 937 best_error_ppm = 1000000;
ef9348c8
CML		 938
939 /*
940 * Based on hardware doc, the n always set to 1, and m1 always
941 * set to 2. If requires to support 200Mhz refclk, we need to
942 * revisit this because n may not 1 anymore.
943 */
944 clock.n = 1, clock.m1 = 2;
945 target *= 5; /* fast clock */
946
947 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
948 for (clock.p2 = limit->p2.p2_fast;
949 clock.p2 >= limit->p2.p2_slow;
950 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 951 unsigned int error_ppm;
ef9348c8
CML		 952
953 clock.p = clock.p1 * clock.p2;
954
955 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
956 clock.n) << 22, refclk * clock.m1);
957
958 if (m2 > INT_MAX/clock.m1)
959 continue;
960
961 clock.m2 = m2;
962
963 chv_clock(refclk, &clock);
964
965 if (!intel_PLL_is_valid(dev, limit, &clock))
966 continue;
967
9ca3ba01
ID		 968 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
969 best_error_ppm, &error_ppm))
970 continue;
971
972 *best_clock = clock;
973 best_error_ppm = error_ppm;
974 found = true;
ef9348c8
CML		 975 }
976 }
977
978 return found;
979}
980
5ab7b0b7
ID		 981bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
982 intel_clock_t *best_clock)
983{
984 int refclk = i9xx_get_refclk(crtc_state, 0);
985
986 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
987 target_clock, refclk, NULL, best_clock);
988}
989
20ddf665
VS		 990bool intel_crtc_active(struct drm_crtc *crtc)
991{
992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
993
994 /* Be paranoid as we can arrive here with only partial
995 * state retrieved from the hardware during setup.
996 *
241bfc38 997 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 998 * as Haswell has gained clock readout/fastboot support.
999 *
66e514c1 1000 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 1001 * properly reconstruct framebuffers.
c3d1f436
MR		 1002 *
1003 * FIXME: The intel_crtc->active here should be switched to
1004 * crtc->state->active once we have proper CRTC states wired up
1005 * for atomic.
20ddf665 1006 */
c3d1f436 1007 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1008 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1009}
1010
a5c961d1
PZ		 1011enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1012 enum pipe pipe)
1013{
1014 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1015 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1016
6e3c9717 1017 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1018}
1019
fbf49ea2
VS		 1020static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1021{
1022 struct drm_i915_private *dev_priv = dev->dev_private;
1023 u32 reg = PIPEDSL(pipe);
1024 u32 line1, line2;
1025 u32 line_mask;
1026
1027 if (IS_GEN2(dev))
1028 line_mask = DSL_LINEMASK_GEN2;
1029 else
1030 line_mask = DSL_LINEMASK_GEN3;
1031
1032 line1 = I915_READ(reg) & line_mask;
1033 mdelay(5);
1034 line2 = I915_READ(reg) & line_mask;
1035
1036 return line1 == line2;
1037}
1038
ab7ad7f6
KP		 1039/*
1040 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1041 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1042 *
1043 * After disabling a pipe, we can't wait for vblank in the usual way,
1044 * spinning on the vblank interrupt status bit, since we won't actually
1045 * see an interrupt when the pipe is disabled.
1046 *
ab7ad7f6
KP		 1047 * On Gen4 and above:
1048 * wait for the pipe register state bit to turn off
1049 *
1050 * Otherwise:
1051 * wait for the display line value to settle (it usually
1052 * ends up stopping at the start of the next frame).
58e10eb9 1053 *
9d0498a2 1054 */
575f7ab7 1055static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1056{
575f7ab7 1057 struct drm_device *dev = crtc->base.dev;
9d0498a2 1058 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1059 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1060 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1061
1062 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1063 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1064
1065 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1066 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1067 100))
284637d9 1068 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1069 } else {
ab7ad7f6 1070 /* Wait for the display line to settle */
fbf49ea2 1071 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1072 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1073 }
79e53945
JB		 1074}
1075
b0ea7d37
DL		 1076/*
1077 * ibx_digital_port_connected - is the specified port connected?
1078 * @dev_priv: i915 private structure
1079 * @port: the port to test
1080 *
1081 * Returns true if @port is connected, false otherwise.
1082 */
1083bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1084 struct intel_digital_port *port)
1085{
1086 u32 bit;
1087
c36346e3 1088 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1089 switch (port->port) {
c36346e3
DL		 1090 case PORT_B:
1091 bit = SDE_PORTB_HOTPLUG;
1092 break;
1093 case PORT_C:
1094 bit = SDE_PORTC_HOTPLUG;
1095 break;
1096 case PORT_D:
1097 bit = SDE_PORTD_HOTPLUG;
1098 break;
1099 default:
1100 return true;
1101 }
1102 } else {
eba905b2 1103 switch (port->port) {
c36346e3
DL		 1104 case PORT_B:
1105 bit = SDE_PORTB_HOTPLUG_CPT;
1106 break;
1107 case PORT_C:
1108 bit = SDE_PORTC_HOTPLUG_CPT;
1109 break;
1110 case PORT_D:
1111 bit = SDE_PORTD_HOTPLUG_CPT;
1112 break;
1113 default:
1114 return true;
1115 }
b0ea7d37
DL		 1116 }
1117
1118 return I915_READ(SDEISR) & bit;
1119}
1120
b24e7179
JB		 1121static const char *state_string(bool enabled)
1122{
1123 return enabled ? "on" : "off";
1124}
1125
1126/* Only for pre-ILK configs */
55607e8a
DV		 1127void assert_pll(struct drm_i915_private *dev_priv,
1128 enum pipe pipe, bool state)
b24e7179
JB		 1129{
1130 int reg;
1131 u32 val;
1132 bool cur_state;
1133
1134 reg = DPLL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1137 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1138 "PLL state assertion failure (expected %s, current %s)\n",
1139 state_string(state), state_string(cur_state));
1140}
b24e7179 1141
23538ef1
JN		 1142/* XXX: the dsi pll is shared between MIPI DSI ports */
1143static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1144{
1145 u32 val;
1146 bool cur_state;
1147
a580516d 1148 mutex_lock(&dev_priv->sb_lock);
23538ef1 1149 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1150 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1151
1152 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1153 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1154 "DSI PLL state assertion failure (expected %s, current %s)\n",
1155 state_string(state), state_string(cur_state));
1156}
1157#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1158#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1159
55607e8a 1160struct intel_shared_dpll *
e2b78267
DV		 1161intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1162{
1163 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1164
6e3c9717 1165 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1166 return NULL;
1167
6e3c9717 1168 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1169}
1170
040484af 1171/* For ILK+ */
55607e8a
DV		 1172void assert_shared_dpll(struct drm_i915_private *dev_priv,
1173 struct intel_shared_dpll *pll,
1174 bool state)
040484af 1175{
040484af 1176 bool cur_state;
5358901f 1177 struct intel_dpll_hw_state hw_state;
040484af 1178
92b27b08 1179 if (WARN (!pll,
46edb027 1180 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1181 return;
ee7b9f93 1182
5358901f 1183 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1184 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1185 "%s assertion failure (expected %s, current %s)\n",
1186 pll->name, state_string(state), state_string(cur_state));
040484af 1187}
040484af
JB		 1188
1189static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, bool state)
1191{
1192 int reg;
1193 u32 val;
1194 bool cur_state;
ad80a810
PZ		 1195 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1196 pipe);
040484af 1197
affa9354
PZ		 1198 if (HAS_DDI(dev_priv->dev)) {
1199 /* DDI does not have a specific FDI_TX register */
ad80a810 1200 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1201 val = I915_READ(reg);
ad80a810 1202 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1203 } else {
1204 reg = FDI_TX_CTL(pipe);
1205 val = I915_READ(reg);
1206 cur_state = !!(val & FDI_TX_ENABLE);
1207 }
e2c719b7 1208 I915_STATE_WARN(cur_state != state,
040484af
JB		 1209 "FDI TX state assertion failure (expected %s, current %s)\n",
1210 state_string(state), state_string(cur_state));
1211}
1212#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1213#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1214
1215static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, bool state)
1217{
1218 int reg;
1219 u32 val;
1220 bool cur_state;
1221
d63fa0dc
PZ		 1222 reg = FDI_RX_CTL(pipe);
1223 val = I915_READ(reg);
1224 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1225 I915_STATE_WARN(cur_state != state,
040484af
JB		 1226 "FDI RX state assertion failure (expected %s, current %s)\n",
1227 state_string(state), state_string(cur_state));
1228}
1229#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1230#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1231
1232static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234{
1235 int reg;
1236 u32 val;
1237
1238 /* ILK FDI PLL is always enabled */
3d13ef2e 1239 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1240 return;
1241
bf507ef7 1242 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1243 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1244 return;
1245
040484af
JB		 1246 reg = FDI_TX_CTL(pipe);
1247 val = I915_READ(reg);
e2c719b7 1248 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1249}
1250
55607e8a
DV		 1251void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, bool state)
040484af
JB		 1253{
1254 int reg;
1255 u32 val;
55607e8a 1256 bool cur_state;
040484af
JB		 1257
1258 reg = FDI_RX_CTL(pipe);
1259 val = I915_READ(reg);
55607e8a 1260 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1261 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1262 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1263 state_string(state), state_string(cur_state));
040484af
JB		 1264}
1265
b680c37a
DV		 1266void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1267 enum pipe pipe)
ea0760cf 1268{
bedd4dba
JN		 1269 struct drm_device *dev = dev_priv->dev;
1270 int pp_reg;
ea0760cf
JB		 1271 u32 val;
1272 enum pipe panel_pipe = PIPE_A;
0de3b485 1273 bool locked = true;
ea0760cf 1274
bedd4dba
JN		 1275 if (WARN_ON(HAS_DDI(dev)))
1276 return;
1277
1278 if (HAS_PCH_SPLIT(dev)) {
1279 u32 port_sel;
1280
ea0760cf 1281 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1282 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1283
1284 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1285 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 /* XXX: else fix for eDP */
1288 } else if (IS_VALLEYVIEW(dev)) {
1289 /* presumably write lock depends on pipe, not port select */
1290 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1291 panel_pipe = pipe;
ea0760cf
JB		 1292 } else {
1293 pp_reg = PP_CONTROL;
bedd4dba
JN		 1294 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1295 panel_pipe = PIPE_B;
ea0760cf
JB		 1296 }
1297
1298 val = I915_READ(pp_reg);
1299 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1300 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1301 locked = false;
1302
e2c719b7 1303 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1304 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1305 pipe_name(pipe));
ea0760cf
JB		 1306}
1307
93ce0ba6
JN		 1308static void assert_cursor(struct drm_i915_private *dev_priv,
1309 enum pipe pipe, bool state)
1310{
1311 struct drm_device *dev = dev_priv->dev;
1312 bool cur_state;
1313
d9d82081 1314 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1315 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1316 else
5efb3e28 1317 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1318
e2c719b7 1319 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1320 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1321 pipe_name(pipe), state_string(state), state_string(cur_state));
1322}
1323#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1324#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1325
b840d907
JB		 1326void assert_pipe(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
b24e7179
JB		 1328{
1329 int reg;
1330 u32 val;
63d7bbe9 1331 bool cur_state;
702e7a56
PZ		 1332 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1333 pipe);
b24e7179 1334
b6b5d049
VS		 1335 /* if we need the pipe quirk it must be always on */
1336 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1337 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1338 state = true;
1339
f458ebbc 1340 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1341 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1342 cur_state = false;
1343 } else {
1344 reg = PIPECONF(cpu_transcoder);
1345 val = I915_READ(reg);
1346 cur_state = !!(val & PIPECONF_ENABLE);
1347 }
1348
e2c719b7 1349 I915_STATE_WARN(cur_state != state,
63d7bbe9 1350 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1351 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1352}
1353
931872fc
CW		 1354static void assert_plane(struct drm_i915_private *dev_priv,
1355 enum plane plane, bool state)
b24e7179
JB		 1356{
1357 int reg;
1358 u32 val;
931872fc 1359 bool cur_state;
b24e7179
JB		 1360
1361 reg = DSPCNTR(plane);
1362 val = I915_READ(reg);
931872fc 1363 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1364 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1365 "plane %c assertion failure (expected %s, current %s)\n",
1366 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1367}
1368
931872fc
CW		 1369#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1370#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1371
b24e7179
JB		 1372static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe)
1374{
653e1026 1375 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1376 int reg, i;
1377 u32 val;
1378 int cur_pipe;
1379
653e1026
VS		 1380 /* Primary planes are fixed to pipes on gen4+ */
1381 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1382 reg = DSPCNTR(pipe);
1383 val = I915_READ(reg);
e2c719b7 1384 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1385 "plane %c assertion failure, should be disabled but not\n",
1386 plane_name(pipe));
19ec1358 1387 return;
28c05794 1388 }
19ec1358 1389
b24e7179 1390 /* Need to check both planes against the pipe */
055e393f 1391 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1392 reg = DSPCNTR(i);
1393 val = I915_READ(reg);
1394 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1395 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1396 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1397 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1398 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1399 }
1400}
1401
19332d7a
JB		 1402static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1403 enum pipe pipe)
1404{
20674eef 1405 struct drm_device *dev = dev_priv->dev;
1fe47785 1406 int reg, sprite;
19332d7a
JB		 1407 u32 val;
1408
7feb8b88 1409 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1410 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1411 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1412 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1413 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1414 sprite, pipe_name(pipe));
1415 }
1416 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1417 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1418 reg = SPCNTR(pipe, sprite);
20674eef 1419 val = I915_READ(reg);
e2c719b7 1420 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1422 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1423 }
1424 } else if (INTEL_INFO(dev)->gen >= 7) {
1425 reg = SPRCTL(pipe);
19332d7a 1426 val = I915_READ(reg);
e2c719b7 1427 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1429 plane_name(pipe), pipe_name(pipe));
1430 } else if (INTEL_INFO(dev)->gen >= 5) {
1431 reg = DVSCNTR(pipe);
19332d7a 1432 val = I915_READ(reg);
e2c719b7 1433 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1435 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1436 }
1437}
1438
08c71e5e
VS		 1439static void assert_vblank_disabled(struct drm_crtc *crtc)
1440{
e2c719b7 1441 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1442 drm_crtc_vblank_put(crtc);
1443}
1444
89eff4be 1445static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1446{
1447 u32 val;
1448 bool enabled;
1449
e2c719b7 1450 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1451
92f2584a
JB		 1452 val = I915_READ(PCH_DREF_CONTROL);
1453 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1454 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1455 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1456}
1457
ab9412ba
DV		 1458static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1459 enum pipe pipe)
92f2584a
JB		 1460{
1461 int reg;
1462 u32 val;
1463 bool enabled;
1464
ab9412ba 1465 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1466 val = I915_READ(reg);
1467 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1468 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1469 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1470 pipe_name(pipe));
92f2584a
JB		 1471}
1472
4e634389
KP		 1473static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1475{
1476 if ((val & DP_PORT_EN) == 0)
1477 return false;
1478
1479 if (HAS_PCH_CPT(dev_priv->dev)) {
1480 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1481 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1482 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1483 return false;
44f37d1f
CML		 1484 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1485 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1486 return false;
f0575e92
KP		 1487 } else {
1488 if ((val & DP_PIPE_MASK) != (pipe << 30))
1489 return false;
1490 }
1491 return true;
1492}
1493
1519b995
KP		 1494static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, u32 val)
1496{
dc0fa718 1497 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1498 return false;
1499
1500 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1501 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1502 return false;
44f37d1f
CML		 1503 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1504 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1505 return false;
1519b995 1506 } else {
dc0fa718 1507 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1508 return false;
1509 }
1510 return true;
1511}
1512
1513static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1514 enum pipe pipe, u32 val)
1515{
1516 if ((val & LVDS_PORT_EN) == 0)
1517 return false;
1518
1519 if (HAS_PCH_CPT(dev_priv->dev)) {
1520 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1521 return false;
1522 } else {
1523 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1524 return false;
1525 }
1526 return true;
1527}
1528
1529static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1530 enum pipe pipe, u32 val)
1531{
1532 if ((val & ADPA_DAC_ENABLE) == 0)
1533 return false;
1534 if (HAS_PCH_CPT(dev_priv->dev)) {
1535 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1536 return false;
1537 } else {
1538 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1539 return false;
1540 }
1541 return true;
1542}
1543
291906f1 1544static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1545 enum pipe pipe, int reg, u32 port_sel)
291906f1 1546{
47a05eca 1547 u32 val = I915_READ(reg);
e2c719b7 1548 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1549 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1550 reg, pipe_name(pipe));
de9a35ab 1551
e2c719b7 1552 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1553 && (val & DP_PIPEB_SELECT),
de9a35ab 1554 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1555}
1556
1557static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1558 enum pipe pipe, int reg)
1559{
47a05eca 1560 u32 val = I915_READ(reg);
e2c719b7 1561 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1562 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1563 reg, pipe_name(pipe));
de9a35ab 1564
e2c719b7 1565 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1566 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1567 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1568}
1569
1570static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1571 enum pipe pipe)
1572{
1573 int reg;
1574 u32 val;
291906f1 1575
f0575e92
KP		 1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1577 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1579
1580 reg = PCH_ADPA;
1581 val = I915_READ(reg);
e2c719b7 1582 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1583 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1584 pipe_name(pipe));
291906f1
JB		 1585
1586 reg = PCH_LVDS;
1587 val = I915_READ(reg);
e2c719b7 1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1590 pipe_name(pipe));
291906f1 1591
e2debe91
PZ		 1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1595}
1596
40e9cf64
JB		 1597static void intel_init_dpio(struct drm_device *dev)
1598{
1599 struct drm_i915_private *dev_priv = dev->dev_private;
1600
1601 if (!IS_VALLEYVIEW(dev))
1602 return;
1603
a09caddd
CML		 1604 /*
1605 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1606 * CHV x1 PHY (DP/HDMI D)
1607 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1608 */
1609 if (IS_CHERRYVIEW(dev)) {
1610 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1611 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1612 } else {
1613 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1614 }
5382f5f3
JB		 1615}
1616
d288f65f 1617static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1618 const struct intel_crtc_state *pipe_config)
87442f73 1619{
426115cf
DV		 1620 struct drm_device *dev = crtc->base.dev;
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 int reg = DPLL(crtc->pipe);
d288f65f 1623 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1624
426115cf 1625 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1626
1627 /* No really, not for ILK+ */
1628 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1629
1630 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1631 if (IS_MOBILE(dev_priv->dev))
426115cf 1632 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1633
426115cf
DV		 1634 I915_WRITE(reg, dpll);
1635 POSTING_READ(reg);
1636 udelay(150);
1637
1638 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1639 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1640
d288f65f 1641 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1642 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1643
1644 /* We do this three times for luck */
426115cf 1645 I915_WRITE(reg, dpll);
87442f73
DV		 1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
426115cf 1648 I915_WRITE(reg, dpll);
87442f73
DV		 1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
426115cf 1651 I915_WRITE(reg, dpll);
87442f73
DV		 1652 POSTING_READ(reg);
1653 udelay(150); /* wait for warmup */
1654}
1655
d288f65f 1656static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1657 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1658{
1659 struct drm_device *dev = crtc->base.dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 int pipe = crtc->pipe;
1662 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1663 u32 tmp;
1664
1665 assert_pipe_disabled(dev_priv, crtc->pipe);
1666
1667 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1668
a580516d 1669 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1670
1671 /* Enable back the 10bit clock to display controller */
1672 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1673 tmp |= DPIO_DCLKP_EN;
1674 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1675
54433e91
VS		 1676 mutex_unlock(&dev_priv->sb_lock);
1677
9d556c99
CML		 1678 /*
1679 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1680 */
1681 udelay(1);
1682
1683 /* Enable PLL */
d288f65f 1684 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1685
1686 /* Check PLL is locked */
a11b0703 1687 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1688 DRM_ERROR("PLL %d failed to lock\n", pipe);
1689
a11b0703 1690 /* not sure when this should be written */
d288f65f 1691 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1692 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1693}
1694
1c4e0274
VS		 1695static int intel_num_dvo_pipes(struct drm_device *dev)
1696{
1697 struct intel_crtc *crtc;
1698 int count = 0;
1699
1700 for_each_intel_crtc(dev, crtc)
3538b9df 1701 count += crtc->base.state->active &&
409ee761 1702 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1703
1704 return count;
1705}
1706
66e3d5c0 1707static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1708{
66e3d5c0
DV		 1709 struct drm_device *dev = crtc->base.dev;
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 int reg = DPLL(crtc->pipe);
6e3c9717 1712 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1713
66e3d5c0 1714 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1715
63d7bbe9 1716 /* No really, not for ILK+ */
3d13ef2e 1717 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1718
1719 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1720 if (IS_MOBILE(dev) && !IS_I830(dev))
1721 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1722
1c4e0274
VS		 1723 /* Enable DVO 2x clock on both PLLs if necessary */
1724 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1725 /*
1726 * It appears to be important that we don't enable this
1727 * for the current pipe before otherwise configuring the
1728 * PLL. No idea how this should be handled if multiple
1729 * DVO outputs are enabled simultaneosly.
1730 */
1731 dpll |= DPLL_DVO_2X_MODE;
1732 I915_WRITE(DPLL(!crtc->pipe),
1733 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1734 }
66e3d5c0
DV		 1735
1736 /* Wait for the clocks to stabilize. */
1737 POSTING_READ(reg);
1738 udelay(150);
1739
1740 if (INTEL_INFO(dev)->gen >= 4) {
1741 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1742 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1743 } else {
1744 /* The pixel multiplier can only be updated once the
1745 * DPLL is enabled and the clocks are stable.
1746 *
1747 * So write it again.
1748 */
1749 I915_WRITE(reg, dpll);
1750 }
63d7bbe9
JB		 1751
1752 /* We do this three times for luck */
66e3d5c0 1753 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1754 POSTING_READ(reg);
1755 udelay(150); /* wait for warmup */
66e3d5c0 1756 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1757 POSTING_READ(reg);
1758 udelay(150); /* wait for warmup */
66e3d5c0 1759 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1760 POSTING_READ(reg);
1761 udelay(150); /* wait for warmup */
1762}
1763
1764/**
50b44a44 1765 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe PLL to disable
1768 *
1769 * Disable the PLL for @pipe, making sure the pipe is off first.
1770 *
1771 * Note! This is for pre-ILK only.
1772 */
1c4e0274 1773static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1774{
1c4e0274
VS		 1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 enum pipe pipe = crtc->pipe;
1778
1779 /* Disable DVO 2x clock on both PLLs if necessary */
1780 if (IS_I830(dev) &&
409ee761 1781 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1782 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1783 I915_WRITE(DPLL(PIPE_B),
1784 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1785 I915_WRITE(DPLL(PIPE_A),
1786 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1787 }
1788
b6b5d049
VS		 1789 /* Don't disable pipe or pipe PLLs if needed */
1790 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1791 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1792 return;
1793
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1796
50b44a44
DV		 1797 I915_WRITE(DPLL(pipe), 0);
1798 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1799}
1800
f6071166
JB		 1801static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1802{
1803 u32 val = 0;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
e5cbfbfb
ID		 1808 /*
1809 * Leave integrated clock source and reference clock enabled for pipe B.
1810 * The latter is needed for VGA hotplug / manual detection.
1811 */
f6071166 1812 if (pipe == PIPE_B)
e5cbfbfb 1813 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1814 I915_WRITE(DPLL(pipe), val);
1815 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1816
1817}
1818
1819static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1820{
d752048d 1821 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1822 u32 val;
1823
a11b0703
VS		 1824 /* Make sure the pipe isn't still relying on us */
1825 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1826
a11b0703 1827 /* Set PLL en = 0 */
d17ec4ce 1828 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1829 if (pipe != PIPE_A)
1830 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1831 I915_WRITE(DPLL(pipe), val);
1832 POSTING_READ(DPLL(pipe));
d752048d 1833
a580516d 1834 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1835
1836 /* Disable 10bit clock to display controller */
1837 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1838 val &= ~DPIO_DCLKP_EN;
1839 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1840
61407f6d
VS		 1841 /* disable left/right clock distribution */
1842 if (pipe != PIPE_B) {
1843 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1844 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1845 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1846 } else {
1847 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1848 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1849 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1850 }
1851
a580516d 1852 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1853}
1854
e4607fcf 1855void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1856 struct intel_digital_port *dport,
1857 unsigned int expected_mask)
89b667f8
JB		 1858{
1859 u32 port_mask;
00fc31b7 1860 int dpll_reg;
89b667f8 1861
e4607fcf
CML		 1862 switch (dport->port) {
1863 case PORT_B:
89b667f8 1864 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1865 dpll_reg = DPLL(0);
e4607fcf
CML		 1866 break;
1867 case PORT_C:
89b667f8 1868 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1869 dpll_reg = DPLL(0);
9b6de0a1 1870 expected_mask <<= 4;
00fc31b7
CML		 1871 break;
1872 case PORT_D:
1873 port_mask = DPLL_PORTD_READY_MASK;
1874 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1875 break;
1876 default:
1877 BUG();
1878 }
89b667f8 1879
9b6de0a1
VS		 1880 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1881 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1882 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1883}
1884
b14b1055
DV		 1885static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1886{
1887 struct drm_device *dev = crtc->base.dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
1889 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1890
be19f0ff
CW		 1891 if (WARN_ON(pll == NULL))
1892 return;
1893
3e369b76 1894 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1895 if (pll->active == 0) {
1896 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1897 WARN_ON(pll->on);
1898 assert_shared_dpll_disabled(dev_priv, pll);
1899
1900 pll->mode_set(dev_priv, pll);
1901 }
1902}
1903
92f2584a 1904/**
85b3894f 1905 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1906 * @dev_priv: i915 private structure
1907 * @pipe: pipe PLL to enable
1908 *
1909 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1910 * drives the transcoder clock.
1911 */
85b3894f 1912static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1913{
3d13ef2e
DL		 1914 struct drm_device *dev = crtc->base.dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1916 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1917
87a875bb 1918 if (WARN_ON(pll == NULL))
48da64a8
CW		 1919 return;
1920
3e369b76 1921 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1922 return;
ee7b9f93 1923
74dd6928 1924 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1925 pll->name, pll->active, pll->on,
e2b78267 1926 crtc->base.base.id);
92f2584a 1927
cdbd2316
DV		 1928 if (pll->active++) {
1929 WARN_ON(!pll->on);
e9d6944e 1930 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1931 return;
1932 }
f4a091c7 1933 WARN_ON(pll->on);
ee7b9f93 1934
bd2bb1b9
PZ		 1935 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1936
46edb027 1937 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1938 pll->enable(dev_priv, pll);
ee7b9f93 1939 pll->on = true;
92f2584a
JB		 1940}
1941
f6daaec2 1942static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1943{
3d13ef2e
DL		 1944 struct drm_device *dev = crtc->base.dev;
1945 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1946 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1947
92f2584a 1948 /* PCH only available on ILK+ */
3d13ef2e 1949 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1950 if (WARN_ON(pll == NULL))
ee7b9f93 1951 return;
92f2584a 1952
3e369b76 1953 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1954 return;
7a419866 1955
46edb027
DV		 1956 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1957 pll->name, pll->active, pll->on,
e2b78267 1958 crtc->base.base.id);
7a419866 1959
48da64a8 1960 if (WARN_ON(pll->active == 0)) {
e9d6944e 1961 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1962 return;
1963 }
1964
e9d6944e 1965 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1966 WARN_ON(!pll->on);
cdbd2316 1967 if (--pll->active)
7a419866 1968 return;
ee7b9f93 1969
46edb027 1970 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1971 pll->disable(dev_priv, pll);
ee7b9f93 1972 pll->on = false;
bd2bb1b9
PZ		 1973
1974 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1975}
1976
b8a4f404
PZ		 1977static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1978 enum pipe pipe)
040484af 1979{
23670b32 1980 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1981 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1983 uint32_t reg, val, pipeconf_val;
040484af
JB		 1984
1985 /* PCH only available on ILK+ */
55522f37 1986 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1987
1988 /* Make sure PCH DPLL is enabled */
e72f9fbf 1989 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1990 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1991
1992 /* FDI must be feeding us bits for PCH ports */
1993 assert_fdi_tx_enabled(dev_priv, pipe);
1994 assert_fdi_rx_enabled(dev_priv, pipe);
1995
23670b32
DV		 1996 if (HAS_PCH_CPT(dev)) {
1997 /* Workaround: Set the timing override bit before enabling the
1998 * pch transcoder. */
1999 reg = TRANS_CHICKEN2(pipe);
2000 val = I915_READ(reg);
2001 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2002 I915_WRITE(reg, val);
59c859d6 2003 }
23670b32 2004
ab9412ba 2005 reg = PCH_TRANSCONF(pipe);
040484af 2006 val = I915_READ(reg);
5f7f726d 2007 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2008
2009 if (HAS_PCH_IBX(dev_priv->dev)) {
2010 /*
c5de7c6f
VS		 2011 * Make the BPC in transcoder be consistent with
2012 * that in pipeconf reg. For HDMI we must use 8bpc
2013 * here for both 8bpc and 12bpc.
e9bcff5c 2014 */
dfd07d72 2015 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2016 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2017 val |= PIPECONF_8BPC;
2018 else
2019 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2020 }
5f7f726d
PZ		 2021
2022 val &= ~TRANS_INTERLACE_MASK;
2023 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2024 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2025 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2026 val |= TRANS_LEGACY_INTERLACED_ILK;
2027 else
2028 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2029 else
2030 val |= TRANS_PROGRESSIVE;
2031
040484af
JB		 2032 I915_WRITE(reg, val | TRANS_ENABLE);
2033 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2034 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2035}
2036
8fb033d7 2037static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2038 enum transcoder cpu_transcoder)
040484af 2039{
8fb033d7 2040 u32 val, pipeconf_val;
8fb033d7
PZ		 2041
2042 /* PCH only available on ILK+ */
55522f37 2043 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2044
8fb033d7 2045 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2046 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2047 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2048
223a6fdf
PZ		 2049 /* Workaround: set timing override bit. */
2050 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2051 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2052 I915_WRITE(_TRANSA_CHICKEN2, val);
2053
25f3ef11 2054 val = TRANS_ENABLE;
937bb610 2055 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2056
9a76b1c6
PZ		 2057 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2058 PIPECONF_INTERLACED_ILK)
a35f2679 2059 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2060 else
2061 val |= TRANS_PROGRESSIVE;
2062
ab9412ba
DV		 2063 I915_WRITE(LPT_TRANSCONF, val);
2064 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2065 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2066}
2067
b8a4f404
PZ		 2068static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2069 enum pipe pipe)
040484af 2070{
23670b32
DV		 2071 struct drm_device *dev = dev_priv->dev;
2072 uint32_t reg, val;
040484af
JB		 2073
2074 /* FDI relies on the transcoder */
2075 assert_fdi_tx_disabled(dev_priv, pipe);
2076 assert_fdi_rx_disabled(dev_priv, pipe);
2077
291906f1
JB		 2078 /* Ports must be off as well */
2079 assert_pch_ports_disabled(dev_priv, pipe);
2080
ab9412ba 2081 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2082 val = I915_READ(reg);
2083 val &= ~TRANS_ENABLE;
2084 I915_WRITE(reg, val);
2085 /* wait for PCH transcoder off, transcoder state */
2086 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2087 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2088
2089 if (!HAS_PCH_IBX(dev)) {
2090 /* Workaround: Clear the timing override chicken bit again. */
2091 reg = TRANS_CHICKEN2(pipe);
2092 val = I915_READ(reg);
2093 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2094 I915_WRITE(reg, val);
2095 }
040484af
JB		 2096}
2097
ab4d966c 2098static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2099{
8fb033d7
PZ		 2100 u32 val;
2101
ab9412ba 2102 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2103 val &= ~TRANS_ENABLE;
ab9412ba 2104 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2105 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2106 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2107 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2108
2109 /* Workaround: clear timing override bit. */
2110 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2111 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2112 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2113}
2114
b24e7179 2115/**
309cfea8 2116 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2117 * @crtc: crtc responsible for the pipe
b24e7179 2118 *
0372264a 2119 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2120 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2121 */
e1fdc473 2122static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2123{
0372264a
PZ		 2124 struct drm_device *dev = crtc->base.dev;
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2128 pipe);
1a240d4d 2129 enum pipe pch_transcoder;
b24e7179
JB		 2130 int reg;
2131 u32 val;
2132
58c6eaa2 2133 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2134 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2135 assert_sprites_disabled(dev_priv, pipe);
2136
681e5811 2137 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2138 pch_transcoder = TRANSCODER_A;
2139 else
2140 pch_transcoder = pipe;
2141
b24e7179
JB		 2142 /*
2143 * A pipe without a PLL won't actually be able to drive bits from
2144 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2145 * need the check.
2146 */
50360403 2147 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2148 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2149 assert_dsi_pll_enabled(dev_priv);
2150 else
2151 assert_pll_enabled(dev_priv, pipe);
040484af 2152 else {
6e3c9717 2153 if (crtc->config->has_pch_encoder) {
040484af 2154 /* if driving the PCH, we need FDI enabled */
cc391bbb 2155 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2156 assert_fdi_tx_pll_enabled(dev_priv,
2157 (enum pipe) cpu_transcoder);
040484af
JB		 2158 }
2159 /* FIXME: assert CPU port conditions for SNB+ */
2160 }
b24e7179 2161
702e7a56 2162 reg = PIPECONF(cpu_transcoder);
b24e7179 2163 val = I915_READ(reg);
7ad25d48 2164 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2165 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2166 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2167 return;
7ad25d48 2168 }
00d70b15
CW		 2169
2170 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2171 POSTING_READ(reg);
b24e7179
JB		 2172}
2173
2174/**
309cfea8 2175 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2176 * @crtc: crtc whose pipes is to be disabled
b24e7179 2177 *
575f7ab7
VS		 2178 * Disable the pipe of @crtc, making sure that various hardware
2179 * specific requirements are met, if applicable, e.g. plane
2180 * disabled, panel fitter off, etc.
b24e7179
JB		 2181 *
2182 * Will wait until the pipe has shut down before returning.
2183 */
575f7ab7 2184static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2185{
575f7ab7 2186 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2187 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2188 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2189 int reg;
2190 u32 val;
2191
2192 /*
2193 * Make sure planes won't keep trying to pump pixels to us,
2194 * or we might hang the display.
2195 */
2196 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2197 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2198 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2199
702e7a56 2200 reg = PIPECONF(cpu_transcoder);
b24e7179 2201 val = I915_READ(reg);
00d70b15
CW		 2202 if ((val & PIPECONF_ENABLE) == 0)
2203 return;
2204
67adc644
VS		 2205 /*
2206 * Double wide has implications for planes
2207 * so best keep it disabled when not needed.
2208 */
6e3c9717 2209 if (crtc->config->double_wide)
67adc644
VS		 2210 val &= ~PIPECONF_DOUBLE_WIDE;
2211
2212 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2213 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2214 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2215 val &= ~PIPECONF_ENABLE;
2216
2217 I915_WRITE(reg, val);
2218 if ((val & PIPECONF_ENABLE) == 0)
2219 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2220}
2221
2222/**
262ca2b0 2223 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2224 * @plane: plane to be enabled
2225 * @crtc: crtc for the plane
b24e7179 2226 *
fdd508a6 2227 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2228 */
fdd508a6
VS		 2229static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2230 struct drm_crtc *crtc)
b24e7179 2231{
fdd508a6
VS		 2232 struct drm_device *dev = plane->dev;
2233 struct drm_i915_private *dev_priv = dev->dev_private;
2234 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2235
2236 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2237 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2238 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2239
fdd508a6
VS		 2240 dev_priv->display.update_primary_plane(crtc, plane->fb,
2241 crtc->x, crtc->y);
b24e7179
JB		 2242}
2243
693db184
CW		 2244static bool need_vtd_wa(struct drm_device *dev)
2245{
2246#ifdef CONFIG_INTEL_IOMMU
2247 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2248 return true;
2249#endif
2250 return false;
2251}
2252
50470bb0 2253unsigned int
6761dd31
TU		 2254intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2255 uint64_t fb_format_modifier)
a57ce0b2 2256{
6761dd31
TU		 2257 unsigned int tile_height;
2258 uint32_t pixel_bytes;
a57ce0b2 2259
b5d0e9bf
DL		 2260 switch (fb_format_modifier) {
2261 case DRM_FORMAT_MOD_NONE:
2262 tile_height = 1;
2263 break;
2264 case I915_FORMAT_MOD_X_TILED:
2265 tile_height = IS_GEN2(dev) ? 16 : 8;
2266 break;
2267 case I915_FORMAT_MOD_Y_TILED:
2268 tile_height = 32;
2269 break;
2270 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2271 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2272 switch (pixel_bytes) {
b5d0e9bf 2273 default:
6761dd31 2274 case 1:
b5d0e9bf
DL		 2275 tile_height = 64;
2276 break;
6761dd31
TU		 2277 case 2:
2278 case 4:
b5d0e9bf
DL		 2279 tile_height = 32;
2280 break;
6761dd31 2281 case 8:
b5d0e9bf
DL		 2282 tile_height = 16;
2283 break;
6761dd31 2284 case 16:
b5d0e9bf
DL		 2285 WARN_ONCE(1,
2286 "128-bit pixels are not supported for display!");
2287 tile_height = 16;
2288 break;
2289 }
2290 break;
2291 default:
2292 MISSING_CASE(fb_format_modifier);
2293 tile_height = 1;
2294 break;
2295 }
091df6cb 2296
6761dd31
TU		 2297 return tile_height;
2298}
2299
2300unsigned int
2301intel_fb_align_height(struct drm_device *dev, unsigned int height,
2302 uint32_t pixel_format, uint64_t fb_format_modifier)
2303{
2304 return ALIGN(height, intel_tile_height(dev, pixel_format,
2305 fb_format_modifier));
a57ce0b2
JB		 2306}
2307
f64b98cd
TU		 2308static int
2309intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2310 const struct drm_plane_state *plane_state)
2311{
50470bb0 2312 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2313
f64b98cd
TU		 2314 *view = i915_ggtt_view_normal;
2315
50470bb0
TU		 2316 if (!plane_state)
2317 return 0;
2318
121920fa 2319 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2320 return 0;
2321
9abc4648 2322 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2323
2324 info->height = fb->height;
2325 info->pixel_format = fb->pixel_format;
2326 info->pitch = fb->pitches[0];
2327 info->fb_modifier = fb->modifier[0];
2328
f64b98cd
TU		 2329 return 0;
2330}
2331
4e9a86b6
VS		 2332static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2333{
2334 if (INTEL_INFO(dev_priv)->gen >= 9)
2335 return 256 * 1024;
985b8bb4
VS		 2336 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2337 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2338 return 128 * 1024;
2339 else if (INTEL_INFO(dev_priv)->gen >= 4)
2340 return 4 * 1024;
2341 else
44c5905e 2342 return 0;
4e9a86b6
VS		 2343}
2344
127bd2ac 2345int
850c4cdc
TU		 2346intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2347 struct drm_framebuffer *fb,
82bc3b2d 2348 const struct drm_plane_state *plane_state,
a4872ba6 2349 struct intel_engine_cs *pipelined)
6b95a207 2350{
850c4cdc 2351 struct drm_device *dev = fb->dev;
ce453d81 2352 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2353 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2354 struct i915_ggtt_view view;
6b95a207
KH		 2355 u32 alignment;
2356 int ret;
2357
ebcdd39e
MR		 2358 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2359
7b911adc
TU		 2360 switch (fb->modifier[0]) {
2361 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2362 alignment = intel_linear_alignment(dev_priv);
6b95a207 2363 break;
7b911adc 2364 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2365 if (INTEL_INFO(dev)->gen >= 9)
2366 alignment = 256 * 1024;
2367 else {
2368 /* pin() will align the object as required by fence */
2369 alignment = 0;
2370 }
6b95a207 2371 break;
7b911adc 2372 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2373 case I915_FORMAT_MOD_Yf_TILED:
2374 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2375 "Y tiling bo slipped through, driver bug!\n"))
2376 return -EINVAL;
2377 alignment = 1 * 1024 * 1024;
2378 break;
6b95a207 2379 default:
7b911adc
TU		 2380 MISSING_CASE(fb->modifier[0]);
2381 return -EINVAL;
6b95a207
KH		 2382 }
2383
f64b98cd
TU		 2384 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2385 if (ret)
2386 return ret;
2387
693db184
CW		 2388 /* Note that the w/a also requires 64 PTE of padding following the
2389 * bo. We currently fill all unused PTE with the shadow page and so
2390 * we should always have valid PTE following the scanout preventing
2391 * the VT-d warning.
2392 */
2393 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2394 alignment = 256 * 1024;
2395
d6dd6843
PZ		 2396 /*
2397 * Global gtt pte registers are special registers which actually forward
2398 * writes to a chunk of system memory. Which means that there is no risk
2399 * that the register values disappear as soon as we call
2400 * intel_runtime_pm_put(), so it is correct to wrap only the
2401 * pin/unpin/fence and not more.
2402 */
2403 intel_runtime_pm_get(dev_priv);
2404
ce453d81 2405 dev_priv->mm.interruptible = false;
e6617330 2406 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2407 &view);
48b956c5 2408 if (ret)
ce453d81 2409 goto err_interruptible;
6b95a207
KH		 2410
2411 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2412 * fence, whereas 965+ only requires a fence if using
2413 * framebuffer compression. For simplicity, we always install
2414 * a fence as the cost is not that onerous.
2415 */
06d98131 2416 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2417 if (ret)
2418 goto err_unpin;
1690e1eb 2419
9a5a53b3 2420 i915_gem_object_pin_fence(obj);
6b95a207 2421
ce453d81 2422 dev_priv->mm.interruptible = true;
d6dd6843 2423 intel_runtime_pm_put(dev_priv);
6b95a207 2424 return 0;
48b956c5
CW		 2425
2426err_unpin:
f64b98cd 2427 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2428err_interruptible:
2429 dev_priv->mm.interruptible = true;
d6dd6843 2430 intel_runtime_pm_put(dev_priv);
48b956c5 2431 return ret;
6b95a207
KH		 2432}
2433
82bc3b2d
TU		 2434static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2435 const struct drm_plane_state *plane_state)
1690e1eb 2436{
82bc3b2d 2437 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2438 struct i915_ggtt_view view;
2439 int ret;
82bc3b2d 2440
ebcdd39e
MR		 2441 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2442
f64b98cd
TU		 2443 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2444 WARN_ONCE(ret, "Couldn't get view from plane state!");
2445
1690e1eb 2446 i915_gem_object_unpin_fence(obj);
f64b98cd 2447 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2448}
2449
c2c75131
DV		 2450/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2452unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2453 int *x, int *y,
bc752862
CW		 2454 unsigned int tiling_mode,
2455 unsigned int cpp,
2456 unsigned int pitch)
c2c75131 2457{
bc752862
CW		 2458 if (tiling_mode != I915_TILING_NONE) {
2459 unsigned int tile_rows, tiles;
c2c75131 2460
bc752862
CW		 2461 tile_rows = *y / 8;
2462 *y %= 8;
c2c75131 2463
bc752862
CW		 2464 tiles = *x / (512/cpp);
2465 *x %= 512/cpp;
2466
2467 return tile_rows * pitch * 8 + tiles * 4096;
2468 } else {
4e9a86b6 2469 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2470 unsigned int offset;
2471
2472 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2473 *y = (offset & alignment) / pitch;
2474 *x = ((offset & alignment) - *y * pitch) / cpp;
2475 return offset & ~alignment;
bc752862 2476 }
c2c75131
DV		 2477}
2478
b35d63fa 2479static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2480{
2481 switch (format) {
2482 case DISPPLANE_8BPP:
2483 return DRM_FORMAT_C8;
2484 case DISPPLANE_BGRX555:
2485 return DRM_FORMAT_XRGB1555;
2486 case DISPPLANE_BGRX565:
2487 return DRM_FORMAT_RGB565;
2488 default:
2489 case DISPPLANE_BGRX888:
2490 return DRM_FORMAT_XRGB8888;
2491 case DISPPLANE_RGBX888:
2492 return DRM_FORMAT_XBGR8888;
2493 case DISPPLANE_BGRX101010:
2494 return DRM_FORMAT_XRGB2101010;
2495 case DISPPLANE_RGBX101010:
2496 return DRM_FORMAT_XBGR2101010;
2497 }
2498}
2499
bc8d7dff
DL		 2500static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2501{
2502 switch (format) {
2503 case PLANE_CTL_FORMAT_RGB_565:
2504 return DRM_FORMAT_RGB565;
2505 default:
2506 case PLANE_CTL_FORMAT_XRGB_8888:
2507 if (rgb_order) {
2508 if (alpha)
2509 return DRM_FORMAT_ABGR8888;
2510 else
2511 return DRM_FORMAT_XBGR8888;
2512 } else {
2513 if (alpha)
2514 return DRM_FORMAT_ARGB8888;
2515 else
2516 return DRM_FORMAT_XRGB8888;
2517 }
2518 case PLANE_CTL_FORMAT_XRGB_2101010:
2519 if (rgb_order)
2520 return DRM_FORMAT_XBGR2101010;
2521 else
2522 return DRM_FORMAT_XRGB2101010;
2523 }
2524}
2525
5724dbd1 2526static bool
f6936e29
DV		 2527intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2528 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2529{
2530 struct drm_device *dev = crtc->base.dev;
2531 struct drm_i915_gem_object *obj = NULL;
2532 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2533 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2534 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2535 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2536 PAGE_SIZE);
2537
2538 size_aligned -= base_aligned;
46f297fb 2539
ff2652ea
CW		 2540 if (plane_config->size == 0)
2541 return false;
2542
f37b5c2b
DV		 2543 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2544 base_aligned,
2545 base_aligned,
2546 size_aligned);
46f297fb 2547 if (!obj)
484b41dd 2548 return false;
46f297fb 2549
49af449b
DL		 2550 obj->tiling_mode = plane_config->tiling;
2551 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2552 obj->stride = fb->pitches[0];
46f297fb 2553
6bf129df
DL		 2554 mode_cmd.pixel_format = fb->pixel_format;
2555 mode_cmd.width = fb->width;
2556 mode_cmd.height = fb->height;
2557 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2558 mode_cmd.modifier[0] = fb->modifier[0];
2559 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2560
2561 mutex_lock(&dev->struct_mutex);
6bf129df 2562 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2563 &mode_cmd, obj)) {
46f297fb
JB		 2564 DRM_DEBUG_KMS("intel fb init failed\n");
2565 goto out_unref_obj;
2566 }
46f297fb 2567 mutex_unlock(&dev->struct_mutex);
484b41dd 2568
f6936e29 2569 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2570 return true;
46f297fb
JB		 2571
2572out_unref_obj:
2573 drm_gem_object_unreference(&obj->base);
2574 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2575 return false;
2576}
2577
afd65eb4
MR		 2578/* Update plane->state->fb to match plane->fb after driver-internal updates */
2579static void
2580update_state_fb(struct drm_plane *plane)
2581{
2582 if (plane->fb == plane->state->fb)
2583 return;
2584
2585 if (plane->state->fb)
2586 drm_framebuffer_unreference(plane->state->fb);
2587 plane->state->fb = plane->fb;
2588 if (plane->state->fb)
2589 drm_framebuffer_reference(plane->state->fb);
2590}
2591
5724dbd1 2592static void
f6936e29
DV		 2593intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2594 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2595{
2596 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2597 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2598 struct drm_crtc *c;
2599 struct intel_crtc *i;
2ff8fde1 2600 struct drm_i915_gem_object *obj;
88595ac9
DV		 2601 struct drm_plane *primary = intel_crtc->base.primary;
2602 struct drm_framebuffer *fb;
484b41dd 2603
2d14030b 2604 if (!plane_config->fb)
484b41dd
JB		 2605 return;
2606
f6936e29 2607 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2608 fb = &plane_config->fb->base;
2609 goto valid_fb;
f55548b5 2610 }
484b41dd 2611
2d14030b 2612 kfree(plane_config->fb);
484b41dd
JB		 2613
2614 /*
2615 * Failed to alloc the obj, check to see if we should share
2616 * an fb with another CRTC instead
2617 */
70e1e0ec 2618 for_each_crtc(dev, c) {
484b41dd
JB		 2619 i = to_intel_crtc(c);
2620
2621 if (c == &intel_crtc->base)
2622 continue;
2623
2ff8fde1
MR		 2624 if (!i->active)
2625 continue;
2626
88595ac9
DV		 2627 fb = c->primary->fb;
2628 if (!fb)
484b41dd
JB		 2629 continue;
2630
88595ac9 2631 obj = intel_fb_obj(fb);
2ff8fde1 2632 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2633 drm_framebuffer_reference(fb);
2634 goto valid_fb;
484b41dd
JB		 2635 }
2636 }
88595ac9
DV		 2637
2638 return;
2639
2640valid_fb:
2641 obj = intel_fb_obj(fb);
2642 if (obj->tiling_mode != I915_TILING_NONE)
2643 dev_priv->preserve_bios_swizzle = true;
2644
2645 primary->fb = fb;
36750f28 2646 primary->crtc = primary->state->crtc = &intel_crtc->base;
88595ac9 2647 update_state_fb(primary);
36750f28 2648 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
88595ac9 2649 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2650}
2651
29b9bde6
DV		 2652static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2653 struct drm_framebuffer *fb,
2654 int x, int y)
81255565
JB		 2655{
2656 struct drm_device *dev = crtc->dev;
2657 struct drm_i915_private *dev_priv = dev->dev_private;
2658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2659 struct drm_plane *primary = crtc->primary;
2660 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2661 struct drm_i915_gem_object *obj;
81255565 2662 int plane = intel_crtc->plane;
e506a0c6 2663 unsigned long linear_offset;
81255565 2664 u32 dspcntr;
f45651ba 2665 u32 reg = DSPCNTR(plane);
48404c1e 2666 int pixel_size;
f45651ba 2667
b70709a6 2668 if (!visible || !fb) {
fdd508a6
VS		 2669 I915_WRITE(reg, 0);
2670 if (INTEL_INFO(dev)->gen >= 4)
2671 I915_WRITE(DSPSURF(plane), 0);
2672 else
2673 I915_WRITE(DSPADDR(plane), 0);
2674 POSTING_READ(reg);
2675 return;
2676 }
2677
c9ba6fad
VS		 2678 obj = intel_fb_obj(fb);
2679 if (WARN_ON(obj == NULL))
2680 return;
2681
2682 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2683
f45651ba
VS		 2684 dspcntr = DISPPLANE_GAMMA_ENABLE;
2685
fdd508a6 2686 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2687
2688 if (INTEL_INFO(dev)->gen < 4) {
2689 if (intel_crtc->pipe == PIPE_B)
2690 dspcntr |= DISPPLANE_SEL_PIPE_B;
2691
2692 /* pipesrc and dspsize control the size that is scaled from,
2693 * which should always be the user's requested size.
2694 */
2695 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2696 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2697 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2698 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2699 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2700 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2701 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2702 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2703 I915_WRITE(PRIMPOS(plane), 0);
2704 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2705 }
81255565 2706
57779d06
VS		 2707 switch (fb->pixel_format) {
2708 case DRM_FORMAT_C8:
81255565
JB		 2709 dspcntr |= DISPPLANE_8BPP;
2710 break;
57779d06 2711 case DRM_FORMAT_XRGB1555:
57779d06 2712 dspcntr |= DISPPLANE_BGRX555;
81255565 2713 break;
57779d06
VS		 2714 case DRM_FORMAT_RGB565:
2715 dspcntr |= DISPPLANE_BGRX565;
2716 break;
2717 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2718 dspcntr |= DISPPLANE_BGRX888;
2719 break;
2720 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2721 dspcntr |= DISPPLANE_RGBX888;
2722 break;
2723 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2724 dspcntr |= DISPPLANE_BGRX101010;
2725 break;
2726 case DRM_FORMAT_XBGR2101010:
57779d06 2727 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2728 break;
2729 default:
baba133a 2730 BUG();
81255565 2731 }
57779d06 2732
f45651ba
VS		 2733 if (INTEL_INFO(dev)->gen >= 4 &&
2734 obj->tiling_mode != I915_TILING_NONE)
2735 dspcntr |= DISPPLANE_TILED;
81255565 2736
de1aa629
VS		 2737 if (IS_G4X(dev))
2738 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2739
b9897127 2740 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2741
c2c75131
DV		 2742 if (INTEL_INFO(dev)->gen >= 4) {
2743 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2744 intel_gen4_compute_page_offset(dev_priv,
2745 &x, &y, obj->tiling_mode,
b9897127 2746 pixel_size,
bc752862 2747 fb->pitches[0]);
c2c75131
DV		 2748 linear_offset -= intel_crtc->dspaddr_offset;
2749 } else {
e506a0c6 2750 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2751 }
e506a0c6 2752
8e7d688b 2753 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2754 dspcntr |= DISPPLANE_ROTATE_180;
2755
6e3c9717
ACO		 2756 x += (intel_crtc->config->pipe_src_w - 1);
2757 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2758
2759 /* Finding the last pixel of the last line of the display
2760 data and adding to linear_offset*/
2761 linear_offset +=
6e3c9717
ACO		 2762 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2763 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2764 }
2765
2766 I915_WRITE(reg, dspcntr);
2767
01f2c773 2768 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2769 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2770 I915_WRITE(DSPSURF(plane),
2771 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2772 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2773 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2774 } else
f343c5f6 2775 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2776 POSTING_READ(reg);
17638cd6
JB		 2777}
2778
29b9bde6
DV		 2779static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2780 struct drm_framebuffer *fb,
2781 int x, int y)
17638cd6
JB		 2782{
2783 struct drm_device *dev = crtc->dev;
2784 struct drm_i915_private *dev_priv = dev->dev_private;
2785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2786 struct drm_plane *primary = crtc->primary;
2787 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2788 struct drm_i915_gem_object *obj;
17638cd6 2789 int plane = intel_crtc->plane;
e506a0c6 2790 unsigned long linear_offset;
17638cd6 2791 u32 dspcntr;
f45651ba 2792 u32 reg = DSPCNTR(plane);
48404c1e 2793 int pixel_size;
f45651ba 2794
b70709a6 2795 if (!visible || !fb) {
fdd508a6
VS		 2796 I915_WRITE(reg, 0);
2797 I915_WRITE(DSPSURF(plane), 0);
2798 POSTING_READ(reg);
2799 return;
2800 }
2801
c9ba6fad
VS		 2802 obj = intel_fb_obj(fb);
2803 if (WARN_ON(obj == NULL))
2804 return;
2805
2806 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2807
f45651ba
VS		 2808 dspcntr = DISPPLANE_GAMMA_ENABLE;
2809
fdd508a6 2810 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2811
2812 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2813 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2814
57779d06
VS		 2815 switch (fb->pixel_format) {
2816 case DRM_FORMAT_C8:
17638cd6
JB		 2817 dspcntr |= DISPPLANE_8BPP;
2818 break;
57779d06
VS		 2819 case DRM_FORMAT_RGB565:
2820 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2821 break;
57779d06 2822 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2823 dspcntr |= DISPPLANE_BGRX888;
2824 break;
2825 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2826 dspcntr |= DISPPLANE_RGBX888;
2827 break;
2828 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
57779d06 2832 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2833 break;
2834 default:
baba133a 2835 BUG();
17638cd6
JB		 2836 }
2837
2838 if (obj->tiling_mode != I915_TILING_NONE)
2839 dspcntr |= DISPPLANE_TILED;
17638cd6 2840
f45651ba 2841 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2842 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2843
b9897127 2844 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2845 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2846 intel_gen4_compute_page_offset(dev_priv,
2847 &x, &y, obj->tiling_mode,
b9897127 2848 pixel_size,
bc752862 2849 fb->pitches[0]);
c2c75131 2850 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
6e3c9717
ACO		 2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2863 }
2864 }
2865
2866 I915_WRITE(reg, dspcntr);
17638cd6 2867
01f2c773 2868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873 } else {
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876 }
17638cd6 2877 POSTING_READ(reg);
17638cd6
JB		 2878}
2879
b321803d
DL		 2880u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881 uint32_t pixel_format)
2882{
2883 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885 /*
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2888 * buffers.
2889 */
2890 switch (fb_modifier) {
2891 case DRM_FORMAT_MOD_NONE:
2892 return 64;
2893 case I915_FORMAT_MOD_X_TILED:
2894 if (INTEL_INFO(dev)->gen == 2)
2895 return 128;
2896 return 512;
2897 case I915_FORMAT_MOD_Y_TILED:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2900 * we get here.
2901 */
2902 return 128;
2903 case I915_FORMAT_MOD_Yf_TILED:
2904 if (bits_per_pixel == 8)
2905 return 64;
2906 else
2907 return 128;
2908 default:
2909 MISSING_CASE(fb_modifier);
2910 return 64;
2911 }
2912}
2913
121920fa
TU		 2914unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915 struct drm_i915_gem_object *obj)
2916{
9abc4648 2917 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2918
2919 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2920 view = &i915_ggtt_view_rotated;
121920fa
TU		 2921
2922 return i915_gem_obj_ggtt_offset_view(obj, view);
2923}
2924
a1b2278e
CK		 2925/*
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2927 */
2928void skl_detach_scalers(struct intel_crtc *intel_crtc)
2929{
2930 struct drm_device *dev;
2931 struct drm_i915_private *dev_priv;
2932 struct intel_crtc_scaler_state *scaler_state;
2933 int i;
2934
2935 if (!intel_crtc || !intel_crtc->config)
2936 return;
2937
2938 dev = intel_crtc->base.dev;
2939 dev_priv = dev->dev_private;
2940 scaler_state = &intel_crtc->config->scaler_state;
2941
2942 /* loop through and disable scalers that aren't in use */
2943 for (i = 0; i < intel_crtc->num_scalers; i++) {
2944 if (!scaler_state->scalers[i].in_use) {
2945 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2947 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2948 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949 intel_crtc->base.base.id, intel_crtc->pipe, i);
2950 }
2951 }
2952}
2953
6156a456 2954u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2955{
6156a456 2956 switch (pixel_format) {
d161cf7a 2957 case DRM_FORMAT_C8:
c34ce3d1 2958 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2959 case DRM_FORMAT_RGB565:
c34ce3d1 2960 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2961 case DRM_FORMAT_XBGR8888:
c34ce3d1 2962 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2963 case DRM_FORMAT_XRGB8888:
c34ce3d1 2964 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2965 /*
2966 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2967 * to be already pre-multiplied. We need to add a knob (or a different
2968 * DRM_FORMAT) for user-space to configure that.
2969 */
f75fb42a 2970 case DRM_FORMAT_ABGR8888:
c34ce3d1 2971 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2972 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2973 case DRM_FORMAT_ARGB8888:
c34ce3d1 2974 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2975 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2976 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2977 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2978 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2979 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2980 case DRM_FORMAT_YUYV:
c34ce3d1 2981 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2982 case DRM_FORMAT_YVYU:
c34ce3d1 2983 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2984 case DRM_FORMAT_UYVY:
c34ce3d1 2985 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2986 case DRM_FORMAT_VYUY:
c34ce3d1 2987 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2988 default:
4249eeef 2989 MISSING_CASE(pixel_format);
70d21f0e 2990 }
8cfcba41 2991
c34ce3d1 2992 return 0;
6156a456 2993}
70d21f0e 2994
6156a456
CK		 2995u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2996{
6156a456 2997 switch (fb_modifier) {
30af77c4 2998 case DRM_FORMAT_MOD_NONE:
70d21f0e 2999 break;
30af77c4 3000 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3001 return PLANE_CTL_TILED_X;
b321803d 3002 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3003 return PLANE_CTL_TILED_Y;
b321803d 3004 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3005 return PLANE_CTL_TILED_YF;
70d21f0e 3006 default:
6156a456 3007 MISSING_CASE(fb_modifier);
70d21f0e 3008 }
8cfcba41 3009
c34ce3d1 3010 return 0;
6156a456 3011}
70d21f0e 3012
6156a456
CK		 3013u32 skl_plane_ctl_rotation(unsigned int rotation)
3014{
3b7a5119 3015 switch (rotation) {
6156a456
CK		 3016 case BIT(DRM_ROTATE_0):
3017 break;
1e8df167
SJ		 3018 /*
3019 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3020 * while i915 HW rotation is clockwise, thats why this swapping.
3021 */
3b7a5119 3022 case BIT(DRM_ROTATE_90):
1e8df167 3023 return PLANE_CTL_ROTATE_270;
3b7a5119 3024 case BIT(DRM_ROTATE_180):
c34ce3d1 3025 return PLANE_CTL_ROTATE_180;
3b7a5119 3026 case BIT(DRM_ROTATE_270):
1e8df167 3027 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3028 default:
3029 MISSING_CASE(rotation);
3030 }
3031
c34ce3d1 3032 return 0;
6156a456
CK		 3033}
3034
3035static void skylake_update_primary_plane(struct drm_crtc *crtc,
3036 struct drm_framebuffer *fb,
3037 int x, int y)
3038{
3039 struct drm_device *dev = crtc->dev;
3040 struct drm_i915_private *dev_priv = dev->dev_private;
3041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3042 struct drm_plane *plane = crtc->primary;
3043 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3044 struct drm_i915_gem_object *obj;
3045 int pipe = intel_crtc->pipe;
3046 u32 plane_ctl, stride_div, stride;
3047 u32 tile_height, plane_offset, plane_size;
3048 unsigned int rotation;
3049 int x_offset, y_offset;
3050 unsigned long surf_addr;
6156a456
CK		 3051 struct intel_crtc_state *crtc_state = intel_crtc->config;
3052 struct intel_plane_state *plane_state;
3053 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3054 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3055 int scaler_id = -1;
3056
6156a456
CK		 3057 plane_state = to_intel_plane_state(plane->state);
3058
b70709a6 3059 if (!visible || !fb) {
6156a456
CK		 3060 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3061 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3062 POSTING_READ(PLANE_CTL(pipe, 0));
3063 return;
3b7a5119 3064 }
70d21f0e 3065
6156a456
CK		 3066 plane_ctl = PLANE_CTL_ENABLE |
3067 PLANE_CTL_PIPE_GAMMA_ENABLE |
3068 PLANE_CTL_PIPE_CSC_ENABLE;
3069
3070 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3071 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3072 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3073
3074 rotation = plane->state->rotation;
3075 plane_ctl |= skl_plane_ctl_rotation(rotation);
3076
b321803d
DL		 3077 obj = intel_fb_obj(fb);
3078 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3079 fb->pixel_format);
3b7a5119
SJ		 3080 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3081
6156a456
CK		 3082 /*
3083 * FIXME: intel_plane_state->src, dst aren't set when transitional
3084 * update_plane helpers are called from legacy paths.
3085 * Once full atomic crtc is available, below check can be avoided.
3086 */
3087 if (drm_rect_width(&plane_state->src)) {
3088 scaler_id = plane_state->scaler_id;
3089 src_x = plane_state->src.x1 >> 16;
3090 src_y = plane_state->src.y1 >> 16;
3091 src_w = drm_rect_width(&plane_state->src) >> 16;
3092 src_h = drm_rect_height(&plane_state->src) >> 16;
3093 dst_x = plane_state->dst.x1;
3094 dst_y = plane_state->dst.y1;
3095 dst_w = drm_rect_width(&plane_state->dst);
3096 dst_h = drm_rect_height(&plane_state->dst);
3097
3098 WARN_ON(x != src_x || y != src_y);
3099 } else {
3100 src_w = intel_crtc->config->pipe_src_w;
3101 src_h = intel_crtc->config->pipe_src_h;
3102 }
3103
3b7a5119
SJ		 3104 if (intel_rotation_90_or_270(rotation)) {
3105 /* stride = Surface height in tiles */
2614f17d 3106 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3107 fb->modifier[0]);
3108 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3109 x_offset = stride * tile_height - y - src_h;
3b7a5119 3110 y_offset = x;
6156a456 3111 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3112 } else {
3113 stride = fb->pitches[0] / stride_div;
3114 x_offset = x;
3115 y_offset = y;
6156a456 3116 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3117 }
3118 plane_offset = y_offset << 16 | x_offset;
b321803d 3119
70d21f0e 3120 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3121 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3122 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3123 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3124
3125 if (scaler_id >= 0) {
3126 uint32_t ps_ctrl = 0;
3127
3128 WARN_ON(!dst_w || !dst_h);
3129 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3130 crtc_state->scaler_state.scalers[scaler_id].mode;
3131 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3132 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3133 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3134 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3135 I915_WRITE(PLANE_POS(pipe, 0), 0);
3136 } else {
3137 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3138 }
3139
121920fa 3140 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3141
3142 POSTING_READ(PLANE_SURF(pipe, 0));
3143}
3144
17638cd6
JB		 3145/* Assume fb object is pinned & idle & fenced and just update base pointers */
3146static int
3147intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3148 int x, int y, enum mode_set_atomic state)
3149{
3150 struct drm_device *dev = crtc->dev;
3151 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3152
6b8e6ed0
CW		 3153 if (dev_priv->display.disable_fbc)
3154 dev_priv->display.disable_fbc(dev);
81255565 3155
29b9bde6
DV		 3156 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3157
3158 return 0;
81255565
JB		 3159}
3160
7514747d 3161static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3162{
96a02917
VS		 3163 struct drm_crtc *crtc;
3164
70e1e0ec 3165 for_each_crtc(dev, crtc) {
96a02917
VS		 3166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3167 enum plane plane = intel_crtc->plane;
3168
3169 intel_prepare_page_flip(dev, plane);
3170 intel_finish_page_flip_plane(dev, plane);
3171 }
7514747d
VS		 3172}
3173
3174static void intel_update_primary_planes(struct drm_device *dev)
3175{
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177 struct drm_crtc *crtc;
96a02917 3178
70e1e0ec 3179 for_each_crtc(dev, crtc) {
96a02917
VS		 3180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3181
51fd371b 3182 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3183 /*
3184 * FIXME: Once we have proper support for primary planes (and
3185 * disabling them without disabling the entire crtc) allow again
66e514c1 3186 * a NULL crtc->primary->fb.
947fdaad 3187 */
f4510a27 3188 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3189 dev_priv->display.update_primary_plane(crtc,
66e514c1 3190 crtc->primary->fb,
262ca2b0
MR		 3191 crtc->x,
3192 crtc->y);
51fd371b 3193 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3194 }
3195}
3196
7514747d
VS		 3197void intel_prepare_reset(struct drm_device *dev)
3198{
3199 /* no reset support for gen2 */
3200 if (IS_GEN2(dev))
3201 return;
3202
3203 /* reset doesn't touch the display */
3204 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3205 return;
3206
3207 drm_modeset_lock_all(dev);
f98ce92f
VS		 3208 /*
3209 * Disabling the crtcs gracefully seems nicer. Also the
3210 * g33 docs say we should at least disable all the planes.
3211 */
6b72d486 3212 intel_display_suspend(dev);
7514747d
VS		 3213}
3214
3215void intel_finish_reset(struct drm_device *dev)
3216{
3217 struct drm_i915_private *dev_priv = to_i915(dev);
3218
3219 /*
3220 * Flips in the rings will be nuked by the reset,
3221 * so complete all pending flips so that user space
3222 * will get its events and not get stuck.
3223 */
3224 intel_complete_page_flips(dev);
3225
3226 /* no reset support for gen2 */
3227 if (IS_GEN2(dev))
3228 return;
3229
3230 /* reset doesn't touch the display */
3231 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3232 /*
3233 * Flips in the rings have been nuked by the reset,
3234 * so update the base address of all primary
3235 * planes to the the last fb to make sure we're
3236 * showing the correct fb after a reset.
3237 */
3238 intel_update_primary_planes(dev);
3239 return;
3240 }
3241
3242 /*
3243 * The display has been reset as well,
3244 * so need a full re-initialization.
3245 */
3246 intel_runtime_pm_disable_interrupts(dev_priv);
3247 intel_runtime_pm_enable_interrupts(dev_priv);
3248
3249 intel_modeset_init_hw(dev);
3250
3251 spin_lock_irq(&dev_priv->irq_lock);
3252 if (dev_priv->display.hpd_irq_setup)
3253 dev_priv->display.hpd_irq_setup(dev);
3254 spin_unlock_irq(&dev_priv->irq_lock);
3255
3256 intel_modeset_setup_hw_state(dev, true);
3257
3258 intel_hpd_init(dev_priv);
3259
3260 drm_modeset_unlock_all(dev);
3261}
3262
2e2f351d 3263static void
14667a4b
CW		 3264intel_finish_fb(struct drm_framebuffer *old_fb)
3265{
2ff8fde1 3266 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3267 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3268 bool was_interruptible = dev_priv->mm.interruptible;
3269 int ret;
3270
14667a4b
CW		 3271 /* Big Hammer, we also need to ensure that any pending
3272 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3273 * current scanout is retired before unpinning the old
2e2f351d
CW		 3274 * framebuffer. Note that we rely on userspace rendering
3275 * into the buffer attached to the pipe they are waiting
3276 * on. If not, userspace generates a GPU hang with IPEHR
3277 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3278 *
3279 * This should only fail upon a hung GPU, in which case we
3280 * can safely continue.
3281 */
3282 dev_priv->mm.interruptible = false;
2e2f351d 3283 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3284 dev_priv->mm.interruptible = was_interruptible;
3285
2e2f351d 3286 WARN_ON(ret);
14667a4b
CW		 3287}
3288
7d5e3799
CW		 3289static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3290{
3291 struct drm_device *dev = crtc->dev;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3294 bool pending;
3295
3296 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3297 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3298 return false;
3299
5e2d7afc 3300 spin_lock_irq(&dev->event_lock);
7d5e3799 3301 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3302 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3303
3304 return pending;
3305}
3306
e30e8f75
GP		 3307static void intel_update_pipe_size(struct intel_crtc *crtc)
3308{
3309 struct drm_device *dev = crtc->base.dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 const struct drm_display_mode *adjusted_mode;
3312
3313 if (!i915.fastboot)
3314 return;
3315
3316 /*
3317 * Update pipe size and adjust fitter if needed: the reason for this is
3318 * that in compute_mode_changes we check the native mode (not the pfit
3319 * mode) to see if we can flip rather than do a full mode set. In the
3320 * fastboot case, we'll flip, but if we don't update the pipesrc and
3321 * pfit state, we'll end up with a big fb scanned out into the wrong
3322 * sized surface.
3323 *
3324 * To fix this properly, we need to hoist the checks up into
3325 * compute_mode_changes (or above), check the actual pfit state and
3326 * whether the platform allows pfit disable with pipe active, and only
3327 * then update the pipesrc and pfit state, even on the flip path.
3328 */
3329
6e3c9717 3330 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3331
3332 I915_WRITE(PIPESRC(crtc->pipe),
3333 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3334 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3335 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3336 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3337 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3338 I915_WRITE(PF_CTL(crtc->pipe), 0);
3339 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3340 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3341 }
6e3c9717
ACO		 3342 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3343 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3344}
3345
5e84e1a4
ZW		 3346static void intel_fdi_normal_train(struct drm_crtc *crtc)
3347{
3348 struct drm_device *dev = crtc->dev;
3349 struct drm_i915_private *dev_priv = dev->dev_private;
3350 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3351 int pipe = intel_crtc->pipe;
3352 u32 reg, temp;
3353
3354 /* enable normal train */
3355 reg = FDI_TX_CTL(pipe);
3356 temp = I915_READ(reg);
61e499bf 3357 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3358 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3359 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3360 } else {
3361 temp &= ~FDI_LINK_TRAIN_NONE;
3362 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3363 }
5e84e1a4
ZW		 3364 I915_WRITE(reg, temp);
3365
3366 reg = FDI_RX_CTL(pipe);
3367 temp = I915_READ(reg);
3368 if (HAS_PCH_CPT(dev)) {
3369 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3370 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3371 } else {
3372 temp &= ~FDI_LINK_TRAIN_NONE;
3373 temp |= FDI_LINK_TRAIN_NONE;
3374 }
3375 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3376
3377 /* wait one idle pattern time */
3378 POSTING_READ(reg);
3379 udelay(1000);
357555c0
JB		 3380
3381 /* IVB wants error correction enabled */
3382 if (IS_IVYBRIDGE(dev))
3383 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3384 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3385}
3386
8db9d77b
ZW		 3387/* The FDI link training functions for ILK/Ibexpeak. */
3388static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3389{
3390 struct drm_device *dev = crtc->dev;
3391 struct drm_i915_private *dev_priv = dev->dev_private;
3392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3393 int pipe = intel_crtc->pipe;
5eddb70b 3394 u32 reg, temp, tries;
8db9d77b 3395
1c8562f6 3396 /* FDI needs bits from pipe first */
0fc932b8 3397 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3398
e1a44743
AJ		 3399 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3400 for train result */
5eddb70b
CW		 3401 reg = FDI_RX_IMR(pipe);
3402 temp = I915_READ(reg);
e1a44743
AJ		 3403 temp &= ~FDI_RX_SYMBOL_LOCK;
3404 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3405 I915_WRITE(reg, temp);
3406 I915_READ(reg);
e1a44743
AJ		 3407 udelay(150);
3408
8db9d77b 3409 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3410 reg = FDI_TX_CTL(pipe);
3411 temp = I915_READ(reg);
627eb5a3 3412 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3413 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3414 temp &= ~FDI_LINK_TRAIN_NONE;
3415 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3416 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3417
5eddb70b
CW		 3418 reg = FDI_RX_CTL(pipe);
3419 temp = I915_READ(reg);
8db9d77b
ZW		 3420 temp &= ~FDI_LINK_TRAIN_NONE;
3421 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3422 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3423
3424 POSTING_READ(reg);
8db9d77b
ZW		 3425 udelay(150);
3426
5b2adf89 3427 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3428 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3429 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3430 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3431
5eddb70b 3432 reg = FDI_RX_IIR(pipe);
e1a44743 3433 for (tries = 0; tries < 5; tries++) {
5eddb70b 3434 temp = I915_READ(reg);
8db9d77b
ZW		 3435 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3436
3437 if ((temp & FDI_RX_BIT_LOCK)) {
3438 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3439 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3440 break;
3441 }
8db9d77b 3442 }
e1a44743 3443 if (tries == 5)
5eddb70b 3444 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3445
3446 /* Train 2 */
5eddb70b
CW		 3447 reg = FDI_TX_CTL(pipe);
3448 temp = I915_READ(reg);
8db9d77b
ZW		 3449 temp &= ~FDI_LINK_TRAIN_NONE;
3450 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3451 I915_WRITE(reg, temp);
8db9d77b 3452
5eddb70b
CW		 3453 reg = FDI_RX_CTL(pipe);
3454 temp = I915_READ(reg);
8db9d77b
ZW		 3455 temp &= ~FDI_LINK_TRAIN_NONE;
3456 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3457 I915_WRITE(reg, temp);
8db9d77b 3458
5eddb70b
CW		 3459 POSTING_READ(reg);
3460 udelay(150);
8db9d77b 3461
5eddb70b 3462 reg = FDI_RX_IIR(pipe);
e1a44743 3463 for (tries = 0; tries < 5; tries++) {
5eddb70b 3464 temp = I915_READ(reg);
8db9d77b
ZW		 3465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3466
3467 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3468 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3469 DRM_DEBUG_KMS("FDI train 2 done.\n");
3470 break;
3471 }
8db9d77b 3472 }
e1a44743 3473 if (tries == 5)
5eddb70b 3474 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3475
3476 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3477
8db9d77b
ZW		 3478}
3479
0206e353 3480static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3481 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3482 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3483 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3484 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3485};
3486
3487/* The FDI link training functions for SNB/Cougarpoint. */
3488static void gen6_fdi_link_train(struct drm_crtc *crtc)
3489{
3490 struct drm_device *dev = crtc->dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3493 int pipe = intel_crtc->pipe;
fa37d39e 3494 u32 reg, temp, i, retry;
8db9d77b 3495
e1a44743
AJ		 3496 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3497 for train result */
5eddb70b
CW		 3498 reg = FDI_RX_IMR(pipe);
3499 temp = I915_READ(reg);
e1a44743
AJ		 3500 temp &= ~FDI_RX_SYMBOL_LOCK;
3501 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3502 I915_WRITE(reg, temp);
3503
3504 POSTING_READ(reg);
e1a44743
AJ		 3505 udelay(150);
3506
8db9d77b 3507 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3508 reg = FDI_TX_CTL(pipe);
3509 temp = I915_READ(reg);
627eb5a3 3510 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3511 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3512 temp &= ~FDI_LINK_TRAIN_NONE;
3513 temp |= FDI_LINK_TRAIN_PATTERN_1;
3514 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3515 /* SNB-B */
3516 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3517 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3518
d74cf324
DV		 3519 I915_WRITE(FDI_RX_MISC(pipe),
3520 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3521
5eddb70b
CW		 3522 reg = FDI_RX_CTL(pipe);
3523 temp = I915_READ(reg);
8db9d77b
ZW		 3524 if (HAS_PCH_CPT(dev)) {
3525 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3526 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3527 } else {
3528 temp &= ~FDI_LINK_TRAIN_NONE;
3529 temp |= FDI_LINK_TRAIN_PATTERN_1;
3530 }
5eddb70b
CW		 3531 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3532
3533 POSTING_READ(reg);
8db9d77b
ZW		 3534 udelay(150);
3535
0206e353 3536 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3537 reg = FDI_TX_CTL(pipe);
3538 temp = I915_READ(reg);
8db9d77b
ZW		 3539 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3540 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3541 I915_WRITE(reg, temp);
3542
3543 POSTING_READ(reg);
8db9d77b
ZW		 3544 udelay(500);
3545
fa37d39e
SP		 3546 for (retry = 0; retry < 5; retry++) {
3547 reg = FDI_RX_IIR(pipe);
3548 temp = I915_READ(reg);
3549 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3550 if (temp & FDI_RX_BIT_LOCK) {
3551 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3552 DRM_DEBUG_KMS("FDI train 1 done.\n");
3553 break;
3554 }
3555 udelay(50);
8db9d77b 3556 }
fa37d39e
SP		 3557 if (retry < 5)
3558 break;
8db9d77b
ZW		 3559 }
3560 if (i == 4)
5eddb70b 3561 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3562
3563 /* Train 2 */
5eddb70b
CW		 3564 reg = FDI_TX_CTL(pipe);
3565 temp = I915_READ(reg);
8db9d77b
ZW		 3566 temp &= ~FDI_LINK_TRAIN_NONE;
3567 temp |= FDI_LINK_TRAIN_PATTERN_2;
3568 if (IS_GEN6(dev)) {
3569 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3570 /* SNB-B */
3571 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3572 }
5eddb70b 3573 I915_WRITE(reg, temp);
8db9d77b 3574
5eddb70b
CW		 3575 reg = FDI_RX_CTL(pipe);
3576 temp = I915_READ(reg);
8db9d77b
ZW		 3577 if (HAS_PCH_CPT(dev)) {
3578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3579 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3580 } else {
3581 temp &= ~FDI_LINK_TRAIN_NONE;
3582 temp |= FDI_LINK_TRAIN_PATTERN_2;
3583 }
5eddb70b
CW		 3584 I915_WRITE(reg, temp);
3585
3586 POSTING_READ(reg);
8db9d77b
ZW		 3587 udelay(150);
3588
0206e353 3589 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3590 reg = FDI_TX_CTL(pipe);
3591 temp = I915_READ(reg);
8db9d77b
ZW		 3592 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3594 I915_WRITE(reg, temp);
3595
3596 POSTING_READ(reg);
8db9d77b
ZW		 3597 udelay(500);
3598
fa37d39e
SP		 3599 for (retry = 0; retry < 5; retry++) {
3600 reg = FDI_RX_IIR(pipe);
3601 temp = I915_READ(reg);
3602 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603 if (temp & FDI_RX_SYMBOL_LOCK) {
3604 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3605 DRM_DEBUG_KMS("FDI train 2 done.\n");
3606 break;
3607 }
3608 udelay(50);
8db9d77b 3609 }
fa37d39e
SP		 3610 if (retry < 5)
3611 break;
8db9d77b
ZW		 3612 }
3613 if (i == 4)
5eddb70b 3614 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3615
3616 DRM_DEBUG_KMS("FDI train done.\n");
3617}
3618
357555c0
JB		 3619/* Manual link training for Ivy Bridge A0 parts */
3620static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3621{
3622 struct drm_device *dev = crtc->dev;
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3625 int pipe = intel_crtc->pipe;
139ccd3f 3626 u32 reg, temp, i, j;
357555c0
JB		 3627
3628 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3629 for train result */
3630 reg = FDI_RX_IMR(pipe);
3631 temp = I915_READ(reg);
3632 temp &= ~FDI_RX_SYMBOL_LOCK;
3633 temp &= ~FDI_RX_BIT_LOCK;
3634 I915_WRITE(reg, temp);
3635
3636 POSTING_READ(reg);
3637 udelay(150);
3638
01a415fd
DV		 3639 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3640 I915_READ(FDI_RX_IIR(pipe)));
3641
139ccd3f
JB		 3642 /* Try each vswing and preemphasis setting twice before moving on */
3643 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3644 /* disable first in case we need to retry */
3645 reg = FDI_TX_CTL(pipe);
3646 temp = I915_READ(reg);
3647 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3648 temp &= ~FDI_TX_ENABLE;
3649 I915_WRITE(reg, temp);
357555c0 3650
139ccd3f
JB		 3651 reg = FDI_RX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~FDI_LINK_TRAIN_AUTO;
3654 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3655 temp &= ~FDI_RX_ENABLE;
3656 I915_WRITE(reg, temp);
357555c0 3657
139ccd3f 3658 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3659 reg = FDI_TX_CTL(pipe);
3660 temp = I915_READ(reg);
139ccd3f 3661 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3662 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3663 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3664 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3665 temp |= snb_b_fdi_train_param[j/2];
3666 temp |= FDI_COMPOSITE_SYNC;
3667 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3668
139ccd3f
JB		 3669 I915_WRITE(FDI_RX_MISC(pipe),
3670 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3671
139ccd3f 3672 reg = FDI_RX_CTL(pipe);
357555c0 3673 temp = I915_READ(reg);
139ccd3f
JB		 3674 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3675 temp |= FDI_COMPOSITE_SYNC;
3676 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3677
139ccd3f
JB		 3678 POSTING_READ(reg);
3679 udelay(1); /* should be 0.5us */
357555c0 3680
139ccd3f
JB		 3681 for (i = 0; i < 4; i++) {
3682 reg = FDI_RX_IIR(pipe);
3683 temp = I915_READ(reg);
3684 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3685
139ccd3f
JB		 3686 if (temp & FDI_RX_BIT_LOCK ||
3687 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3688 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3689 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3690 i);
3691 break;
3692 }
3693 udelay(1); /* should be 0.5us */
3694 }
3695 if (i == 4) {
3696 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3697 continue;
3698 }
357555c0 3699
139ccd3f 3700 /* Train 2 */
357555c0
JB		 3701 reg = FDI_TX_CTL(pipe);
3702 temp = I915_READ(reg);
139ccd3f
JB		 3703 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3704 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3705 I915_WRITE(reg, temp);
3706
3707 reg = FDI_RX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3710 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3711 I915_WRITE(reg, temp);
3712
3713 POSTING_READ(reg);
139ccd3f 3714 udelay(2); /* should be 1.5us */
357555c0 3715
139ccd3f
JB		 3716 for (i = 0; i < 4; i++) {
3717 reg = FDI_RX_IIR(pipe);
3718 temp = I915_READ(reg);
3719 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3720
139ccd3f
JB		 3721 if (temp & FDI_RX_SYMBOL_LOCK ||
3722 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3723 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3724 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3725 i);
3726 goto train_done;
3727 }
3728 udelay(2); /* should be 1.5us */
357555c0 3729 }
139ccd3f
JB		 3730 if (i == 4)
3731 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3732 }
357555c0 3733
139ccd3f 3734train_done:
357555c0
JB		 3735 DRM_DEBUG_KMS("FDI train done.\n");
3736}
3737
88cefb6c 3738static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3739{
88cefb6c 3740 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3741 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3742 int pipe = intel_crtc->pipe;
5eddb70b 3743 u32 reg, temp;
79e53945 3744
c64e311e 3745
c98e9dcf 3746 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3747 reg = FDI_RX_CTL(pipe);
3748 temp = I915_READ(reg);
627eb5a3 3749 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3750 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3751 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3752 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3753
3754 POSTING_READ(reg);
c98e9dcf
JB		 3755 udelay(200);
3756
3757 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3758 temp = I915_READ(reg);
3759 I915_WRITE(reg, temp | FDI_PCDCLK);
3760
3761 POSTING_READ(reg);
c98e9dcf
JB		 3762 udelay(200);
3763
20749730
PZ		 3764 /* Enable CPU FDI TX PLL, always on for Ironlake */
3765 reg = FDI_TX_CTL(pipe);
3766 temp = I915_READ(reg);
3767 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3768 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3769
20749730
PZ		 3770 POSTING_READ(reg);
3771 udelay(100);
6be4a607 3772 }
0e23b99d
JB		 3773}
3774
88cefb6c
DV		 3775static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3776{
3777 struct drm_device *dev = intel_crtc->base.dev;
3778 struct drm_i915_private *dev_priv = dev->dev_private;
3779 int pipe = intel_crtc->pipe;
3780 u32 reg, temp;
3781
3782 /* Switch from PCDclk to Rawclk */
3783 reg = FDI_RX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3786
3787 /* Disable CPU FDI TX PLL */
3788 reg = FDI_TX_CTL(pipe);
3789 temp = I915_READ(reg);
3790 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3791
3792 POSTING_READ(reg);
3793 udelay(100);
3794
3795 reg = FDI_RX_CTL(pipe);
3796 temp = I915_READ(reg);
3797 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3798
3799 /* Wait for the clocks to turn off. */
3800 POSTING_READ(reg);
3801 udelay(100);
3802}
3803
0fc932b8
JB		 3804static void ironlake_fdi_disable(struct drm_crtc *crtc)
3805{
3806 struct drm_device *dev = crtc->dev;
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3809 int pipe = intel_crtc->pipe;
3810 u32 reg, temp;
3811
3812 /* disable CPU FDI tx and PCH FDI rx */
3813 reg = FDI_TX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3816 POSTING_READ(reg);
3817
3818 reg = FDI_RX_CTL(pipe);
3819 temp = I915_READ(reg);
3820 temp &= ~(0x7 << 16);
dfd07d72 3821 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3822 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3823
3824 POSTING_READ(reg);
3825 udelay(100);
3826
3827 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3828 if (HAS_PCH_IBX(dev))
6f06ce18 3829 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3830
3831 /* still set train pattern 1 */
3832 reg = FDI_TX_CTL(pipe);
3833 temp = I915_READ(reg);
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_1;
3836 I915_WRITE(reg, temp);
3837
3838 reg = FDI_RX_CTL(pipe);
3839 temp = I915_READ(reg);
3840 if (HAS_PCH_CPT(dev)) {
3841 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3842 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3843 } else {
3844 temp &= ~FDI_LINK_TRAIN_NONE;
3845 temp |= FDI_LINK_TRAIN_PATTERN_1;
3846 }
3847 /* BPC in FDI rx is consistent with that in PIPECONF */
3848 temp &= ~(0x07 << 16);
dfd07d72 3849 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3850 I915_WRITE(reg, temp);
3851
3852 POSTING_READ(reg);
3853 udelay(100);
3854}
3855
5dce5b93
CW		 3856bool intel_has_pending_fb_unpin(struct drm_device *dev)
3857{
3858 struct intel_crtc *crtc;
3859
3860 /* Note that we don't need to be called with mode_config.lock here
3861 * as our list of CRTC objects is static for the lifetime of the
3862 * device and so cannot disappear as we iterate. Similarly, we can
3863 * happily treat the predicates as racy, atomic checks as userspace
3864 * cannot claim and pin a new fb without at least acquring the
3865 * struct_mutex and so serialising with us.
3866 */
d3fcc808 3867 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3868 if (atomic_read(&crtc->unpin_work_count) == 0)
3869 continue;
3870
3871 if (crtc->unpin_work)
3872 intel_wait_for_vblank(dev, crtc->pipe);
3873
3874 return true;
3875 }
3876
3877 return false;
3878}
3879
d6bbafa1
CW		 3880static void page_flip_completed(struct intel_crtc *intel_crtc)
3881{
3882 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3883 struct intel_unpin_work *work = intel_crtc->unpin_work;
3884
3885 /* ensure that the unpin work is consistent wrt ->pending. */
3886 smp_rmb();
3887 intel_crtc->unpin_work = NULL;
3888
3889 if (work->event)
3890 drm_send_vblank_event(intel_crtc->base.dev,
3891 intel_crtc->pipe,
3892 work->event);
3893
3894 drm_crtc_vblank_put(&intel_crtc->base);
3895
3896 wake_up_all(&dev_priv->pending_flip_queue);
3897 queue_work(dev_priv->wq, &work->work);
3898
3899 trace_i915_flip_complete(intel_crtc->plane,
3900 work->pending_flip_obj);
3901}
3902
46a55d30 3903void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3904{
0f91128d 3905 struct drm_device *dev = crtc->dev;
5bb61643 3906 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3907
2c10d571 3908 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3909 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3910 !intel_crtc_has_pending_flip(crtc),
3911 60*HZ) == 0)) {
3912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3913
5e2d7afc 3914 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3915 if (intel_crtc->unpin_work) {
3916 WARN_ONCE(1, "Removing stuck page flip\n");
3917 page_flip_completed(intel_crtc);
3918 }
5e2d7afc 3919 spin_unlock_irq(&dev->event_lock);
9c787942 3920 }
5bb61643 3921
975d568a
CW		 3922 if (crtc->primary->fb) {
3923 mutex_lock(&dev->struct_mutex);
3924 intel_finish_fb(crtc->primary->fb);
3925 mutex_unlock(&dev->struct_mutex);
3926 }
e6c3a2a6
CW		 3927}
3928
e615efe4
ED		 3929/* Program iCLKIP clock to the desired frequency */
3930static void lpt_program_iclkip(struct drm_crtc *crtc)
3931{
3932 struct drm_device *dev = crtc->dev;
3933 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3934 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3935 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3936 u32 temp;
3937
a580516d 3938 mutex_lock(&dev_priv->sb_lock);
09153000 3939
e615efe4
ED		 3940 /* It is necessary to ungate the pixclk gate prior to programming
3941 * the divisors, and gate it back when it is done.
3942 */
3943 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3944
3945 /* Disable SSCCTL */
3946 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3947 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3948 SBI_SSCCTL_DISABLE,
3949 SBI_ICLK);
e615efe4
ED		 3950
3951 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3952 if (clock == 20000) {
e615efe4
ED		 3953 auxdiv = 1;
3954 divsel = 0x41;
3955 phaseinc = 0x20;
3956 } else {
3957 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3958 * but the adjusted_mode->crtc_clock in in KHz. To get the
3959 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3960 * convert the virtual clock precision to KHz here for higher
3961 * precision.
3962 */
3963 u32 iclk_virtual_root_freq = 172800 * 1000;
3964 u32 iclk_pi_range = 64;
3965 u32 desired_divisor, msb_divisor_value, pi_value;
3966
12d7ceed 3967 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3968 msb_divisor_value = desired_divisor / iclk_pi_range;
3969 pi_value = desired_divisor % iclk_pi_range;
3970
3971 auxdiv = 0;
3972 divsel = msb_divisor_value - 2;
3973 phaseinc = pi_value;
3974 }
3975
3976 /* This should not happen with any sane values */
3977 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3978 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3979 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3980 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3981
3982 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3983 clock,
e615efe4
ED		 3984 auxdiv,
3985 divsel,
3986 phasedir,
3987 phaseinc);
3988
3989 /* Program SSCDIVINTPHASE6 */
988d6ee8 3990 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3991 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3992 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3993 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3994 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3995 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3996 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3997 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3998
3999 /* Program SSCAUXDIV */
988d6ee8 4000 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4001 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4002 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4003 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4004
4005 /* Enable modulator and associated divider */
988d6ee8 4006 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4007 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4008 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4009
4010 /* Wait for initialization time */
4011 udelay(24);
4012
4013 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4014
a580516d 4015 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4016}
4017
275f01b2
DV		 4018static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4019 enum pipe pch_transcoder)
4020{
4021 struct drm_device *dev = crtc->base.dev;
4022 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4023 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4024
4025 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4026 I915_READ(HTOTAL(cpu_transcoder)));
4027 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4028 I915_READ(HBLANK(cpu_transcoder)));
4029 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4030 I915_READ(HSYNC(cpu_transcoder)));
4031
4032 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4033 I915_READ(VTOTAL(cpu_transcoder)));
4034 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4035 I915_READ(VBLANK(cpu_transcoder)));
4036 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4037 I915_READ(VSYNC(cpu_transcoder)));
4038 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4039 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4040}
4041
003632d9 4042static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4043{
4044 struct drm_i915_private *dev_priv = dev->dev_private;
4045 uint32_t temp;
4046
4047 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4048 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4049 return;
4050
4051 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4052 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4053
003632d9
ACO		 4054 temp &= ~FDI_BC_BIFURCATION_SELECT;
4055 if (enable)
4056 temp |= FDI_BC_BIFURCATION_SELECT;
4057
4058 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4059 I915_WRITE(SOUTH_CHICKEN1, temp);
4060 POSTING_READ(SOUTH_CHICKEN1);
4061}
4062
4063static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4064{
4065 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4066
4067 switch (intel_crtc->pipe) {
4068 case PIPE_A:
4069 break;
4070 case PIPE_B:
6e3c9717 4071 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4072 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4073 else
003632d9 4074 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4075
4076 break;
4077 case PIPE_C:
003632d9 4078 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4079
4080 break;
4081 default:
4082 BUG();
4083 }
4084}
4085
f67a559d
JB		 4086/*
4087 * Enable PCH resources required for PCH ports:
4088 * - PCH PLLs
4089 * - FDI training & RX/TX
4090 * - update transcoder timings
4091 * - DP transcoding bits
4092 * - transcoder
4093 */
4094static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4095{
4096 struct drm_device *dev = crtc->dev;
4097 struct drm_i915_private *dev_priv = dev->dev_private;
4098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4099 int pipe = intel_crtc->pipe;
ee7b9f93 4100 u32 reg, temp;
2c07245f 4101
ab9412ba 4102 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4103
1fbc0d78
DV		 4104 if (IS_IVYBRIDGE(dev))
4105 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4106
cd986abb
DV		 4107 /* Write the TU size bits before fdi link training, so that error
4108 * detection works. */
4109 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4110 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4111
c98e9dcf 4112 /* For PCH output, training FDI link */
674cf967 4113 dev_priv->display.fdi_link_train(crtc);
2c07245f 4114
3ad8a208
DV		 4115 /* We need to program the right clock selection before writing the pixel
4116 * mutliplier into the DPLL. */
303b81e0 4117 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4118 u32 sel;
4b645f14 4119
c98e9dcf 4120 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4121 temp |= TRANS_DPLL_ENABLE(pipe);
4122 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4123 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4124 temp |= sel;
4125 else
4126 temp &= ~sel;
c98e9dcf 4127 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4128 }
5eddb70b 4129
3ad8a208
DV		 4130 /* XXX: pch pll's can be enabled any time before we enable the PCH
4131 * transcoder, and we actually should do this to not upset any PCH
4132 * transcoder that already use the clock when we share it.
4133 *
4134 * Note that enable_shared_dpll tries to do the right thing, but
4135 * get_shared_dpll unconditionally resets the pll - we need that to have
4136 * the right LVDS enable sequence. */
85b3894f 4137 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4138
d9b6cb56
JB		 4139 /* set transcoder timing, panel must allow it */
4140 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4141 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4142
303b81e0 4143 intel_fdi_normal_train(crtc);
5e84e1a4 4144
c98e9dcf 4145 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4146 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4147 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4148 reg = TRANS_DP_CTL(pipe);
4149 temp = I915_READ(reg);
4150 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4151 TRANS_DP_SYNC_MASK |
4152 TRANS_DP_BPC_MASK);
e3ef4479 4153 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4154 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4155
4156 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4157 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4158 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4159 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4160
4161 switch (intel_trans_dp_port_sel(crtc)) {
4162 case PCH_DP_B:
5eddb70b 4163 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4164 break;
4165 case PCH_DP_C:
5eddb70b 4166 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4167 break;
4168 case PCH_DP_D:
5eddb70b 4169 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4170 break;
4171 default:
e95d41e1 4172 BUG();
32f9d658 4173 }
2c07245f 4174
5eddb70b 4175 I915_WRITE(reg, temp);
6be4a607 4176 }
b52eb4dc 4177
b8a4f404 4178 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4179}
4180
1507e5bd
PZ		 4181static void lpt_pch_enable(struct drm_crtc *crtc)
4182{
4183 struct drm_device *dev = crtc->dev;
4184 struct drm_i915_private *dev_priv = dev->dev_private;
4185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4186 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4187
ab9412ba 4188 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4189
8c52b5e8 4190 lpt_program_iclkip(crtc);
1507e5bd 4191
0540e488 4192 /* Set transcoder timing. */
275f01b2 4193 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4194
937bb610 4195 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4196}
4197
190f68c5
ACO		 4198struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4199 struct intel_crtc_state *crtc_state)
ee7b9f93 4200{
e2b78267 4201 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4202 struct intel_shared_dpll *pll;
de419ab6 4203 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4204 enum intel_dpll_id i;
ee7b9f93 4205
de419ab6
ML		 4206 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4207
98b6bd99
DV		 4208 if (HAS_PCH_IBX(dev_priv->dev)) {
4209 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4210 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4211 pll = &dev_priv->shared_dplls[i];
98b6bd99 4212
46edb027
DV		 4213 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4214 crtc->base.base.id, pll->name);
98b6bd99 4215
de419ab6 4216 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4217
98b6bd99
DV		 4218 goto found;
4219 }
4220
bcddf610
S		 4221 if (IS_BROXTON(dev_priv->dev)) {
4222 /* PLL is attached to port in bxt */
4223 struct intel_encoder *encoder;
4224 struct intel_digital_port *intel_dig_port;
4225
4226 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4227 if (WARN_ON(!encoder))
4228 return NULL;
4229
4230 intel_dig_port = enc_to_dig_port(&encoder->base);
4231 /* 1:1 mapping between ports and PLLs */
4232 i = (enum intel_dpll_id)intel_dig_port->port;
4233 pll = &dev_priv->shared_dplls[i];
4234 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4235 crtc->base.base.id, pll->name);
de419ab6 4236 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4237
4238 goto found;
4239 }
4240
e72f9fbf
DV		 4241 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4242 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4243
4244 /* Only want to check enabled timings first */
de419ab6 4245 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4246 continue;
4247
190f68c5 4248 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4249 &shared_dpll[i].hw_state,
4250 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4251 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4252 crtc->base.base.id, pll->name,
de419ab6 4253 shared_dpll[i].crtc_mask,
8bd31e67 4254 pll->active);
ee7b9f93
JB		 4255 goto found;
4256 }
4257 }
4258
4259 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4260 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4261 pll = &dev_priv->shared_dplls[i];
de419ab6 4262 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4263 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4264 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4265 goto found;
4266 }
4267 }
4268
4269 return NULL;
4270
4271found:
de419ab6
ML		 4272 if (shared_dpll[i].crtc_mask == 0)
4273 shared_dpll[i].hw_state =
4274 crtc_state->dpll_hw_state;
f2a69f44 4275
190f68c5 4276 crtc_state->shared_dpll = i;
46edb027
DV		 4277 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4278 pipe_name(crtc->pipe));
ee7b9f93 4279
de419ab6 4280 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4281
ee7b9f93
JB		 4282 return pll;
4283}
4284
de419ab6 4285static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4286{
de419ab6
ML		 4287 struct drm_i915_private *dev_priv = to_i915(state->dev);
4288 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4289 struct intel_shared_dpll *pll;
4290 enum intel_dpll_id i;
4291
de419ab6
ML		 4292 if (!to_intel_atomic_state(state)->dpll_set)
4293 return;
8bd31e67 4294
de419ab6 4295 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4296 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4297 pll = &dev_priv->shared_dplls[i];
de419ab6 4298 pll->config = shared_dpll[i];
8bd31e67
ACO		 4299 }
4300}
4301
a1520318 4302static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4303{
4304 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4305 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4306 u32 temp;
4307
4308 temp = I915_READ(dslreg);
4309 udelay(500);
4310 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4311 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4312 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4313 }
4314}
4315
a1b2278e
CK		 4316/**
4317 * skl_update_scaler_users - Stages update to crtc's scaler state
4318 * @intel_crtc: crtc
4319 * @crtc_state: crtc_state
4320 * @plane: plane (NULL indicates crtc is requesting update)
4321 * @plane_state: plane's state
4322 * @force_detach: request unconditional detachment of scaler
4323 *
4324 * This function updates scaler state for requested plane or crtc.
4325 * To request scaler usage update for a plane, caller shall pass plane pointer.
4326 * To request scaler usage update for crtc, caller shall pass plane pointer
4327 * as NULL.
4328 *
4329 * Return
4330 * 0 - scaler_usage updated successfully
4331 * error - requested scaling cannot be supported or other error condition
4332 */
4333int
4334skl_update_scaler_users(
4335 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4336 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4337 int force_detach)
4338{
4339 int need_scaling;
4340 int idx;
4341 int src_w, src_h, dst_w, dst_h;
4342 int *scaler_id;
4343 struct drm_framebuffer *fb;
4344 struct intel_crtc_scaler_state *scaler_state;
6156a456 4345 unsigned int rotation;
a1b2278e
CK		 4346
4347 if (!intel_crtc || !crtc_state)
4348 return 0;
4349
4350 scaler_state = &crtc_state->scaler_state;
4351
4352 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4353 fb = intel_plane ? plane_state->base.fb : NULL;
4354
4355 if (intel_plane) {
4356 src_w = drm_rect_width(&plane_state->src) >> 16;
4357 src_h = drm_rect_height(&plane_state->src) >> 16;
4358 dst_w = drm_rect_width(&plane_state->dst);
4359 dst_h = drm_rect_height(&plane_state->dst);
4360 scaler_id = &plane_state->scaler_id;
6156a456 4361 rotation = plane_state->base.rotation;
a1b2278e
CK		 4362 } else {
4363 struct drm_display_mode *adjusted_mode =
4364 &crtc_state->base.adjusted_mode;
4365 src_w = crtc_state->pipe_src_w;
4366 src_h = crtc_state->pipe_src_h;
4367 dst_w = adjusted_mode->hdisplay;
4368 dst_h = adjusted_mode->vdisplay;
4369 scaler_id = &scaler_state->scaler_id;
6156a456 4370 rotation = DRM_ROTATE_0;
a1b2278e 4371 }
6156a456
CK		 4372
4373 need_scaling = intel_rotation_90_or_270(rotation) ?
4374 (src_h != dst_w || src_w != dst_h):
4375 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4376
4377 /*
4378 * if plane is being disabled or scaler is no more required or force detach
4379 * - free scaler binded to this plane/crtc
4380 * - in order to do this, update crtc->scaler_usage
4381 *
4382 * Here scaler state in crtc_state is set free so that
4383 * scaler can be assigned to other user. Actual register
4384 * update to free the scaler is done in plane/panel-fit programming.
4385 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4386 */
4387 if (force_detach || !need_scaling || (intel_plane &&
4388 (!fb || !plane_state->visible))) {
4389 if (*scaler_id >= 0) {
4390 scaler_state->scaler_users &= ~(1 << idx);
4391 scaler_state->scalers[*scaler_id].in_use = 0;
4392
4393 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4394 "crtc_state = %p scaler_users = 0x%x\n",
4395 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4396 intel_plane ? intel_plane->base.base.id :
4397 intel_crtc->base.base.id, crtc_state,
4398 scaler_state->scaler_users);
4399 *scaler_id = -1;
4400 }
4401 return 0;
4402 }
4403
4404 /* range checks */
4405 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4406 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4407
4408 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4409 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4410 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4411 "size is out of scaler range\n",
4412 intel_plane ? "PLANE" : "CRTC",
4413 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4414 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4415 return -EINVAL;
4416 }
4417
4418 /* check colorkey */
225c228a
CK		 4419 if (WARN_ON(intel_plane &&
4420 intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)) {
4421 DRM_DEBUG_KMS("PLANE:%d scaling %ux%u->%ux%u not allowed with colorkey",
4422 intel_plane->base.base.id, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4423 return -EINVAL;
4424 }
4425
4426 /* Check src format */
4427 if (intel_plane) {
4428 switch (fb->pixel_format) {
4429 case DRM_FORMAT_RGB565:
4430 case DRM_FORMAT_XBGR8888:
4431 case DRM_FORMAT_XRGB8888:
4432 case DRM_FORMAT_ABGR8888:
4433 case DRM_FORMAT_ARGB8888:
4434 case DRM_FORMAT_XRGB2101010:
a1b2278e 4435 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4436 case DRM_FORMAT_YUYV:
4437 case DRM_FORMAT_YVYU:
4438 case DRM_FORMAT_UYVY:
4439 case DRM_FORMAT_VYUY:
4440 break;
4441 default:
4442 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4443 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4444 return -EINVAL;
4445 }
4446 }
4447
4448 /* mark this plane as a scaler user in crtc_state */
4449 scaler_state->scaler_users |= (1 << idx);
4450 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4451 "crtc_state = %p scaler_users = 0x%x\n",
4452 intel_plane ? "PLANE" : "CRTC",
4453 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4454 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4455 return 0;
4456}
4457
4458static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4459{
4460 struct drm_device *dev = crtc->base.dev;
4461 struct drm_i915_private *dev_priv = dev->dev_private;
4462 int pipe = crtc->pipe;
a1b2278e
CK		 4463 struct intel_crtc_scaler_state *scaler_state =
4464 &crtc->config->scaler_state;
4465
4466 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4467
4468 /* To update pfit, first update scaler state */
4469 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4470 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4471 skl_detach_scalers(crtc);
4472 if (!enable)
4473 return;
bd2e244f 4474
6e3c9717 4475 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4476 int id;
4477
4478 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4479 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4480 return;
4481 }
4482
4483 id = scaler_state->scaler_id;
4484 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4485 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4486 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4487 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4488
4489 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4490 }
4491}
4492
b074cec8
JB		 4493static void ironlake_pfit_enable(struct intel_crtc *crtc)
4494{
4495 struct drm_device *dev = crtc->base.dev;
4496 struct drm_i915_private *dev_priv = dev->dev_private;
4497 int pipe = crtc->pipe;
4498
6e3c9717 4499 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4500 /* Force use of hard-coded filter coefficients
4501 * as some pre-programmed values are broken,
4502 * e.g. x201.
4503 */
4504 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4505 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4506 PF_PIPE_SEL_IVB(pipe));
4507 else
4508 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4509 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4510 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4511 }
4512}
4513
4a3b8769 4514static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4515{
4516 struct drm_device *dev = crtc->dev;
4517 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4518 struct drm_plane *plane;
bb53d4ae
VS		 4519 struct intel_plane *intel_plane;
4520
af2b653b
MR		 4521 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4522 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4523 if (intel_plane->pipe == pipe)
4524 intel_plane_restore(&intel_plane->base);
af2b653b 4525 }
bb53d4ae
VS		 4526}
4527
20bc8673 4528void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4529{
cea165c3
VS		 4530 struct drm_device *dev = crtc->base.dev;
4531 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4532
6e3c9717 4533 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4534 return;
4535
cea165c3
VS		 4536 /* We can only enable IPS after we enable a plane and wait for a vblank */
4537 intel_wait_for_vblank(dev, crtc->pipe);
4538
d77e4531 4539 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4540 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4541 mutex_lock(&dev_priv->rps.hw_lock);
4542 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4543 mutex_unlock(&dev_priv->rps.hw_lock);
4544 /* Quoting Art Runyan: "its not safe to expect any particular
4545 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4546 * mailbox." Moreover, the mailbox may return a bogus state,
4547 * so we need to just enable it and continue on.
2a114cc1
BW		 4548 */
4549 } else {
4550 I915_WRITE(IPS_CTL, IPS_ENABLE);
4551 /* The bit only becomes 1 in the next vblank, so this wait here
4552 * is essentially intel_wait_for_vblank. If we don't have this
4553 * and don't wait for vblanks until the end of crtc_enable, then
4554 * the HW state readout code will complain that the expected
4555 * IPS_CTL value is not the one we read. */
4556 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4557 DRM_ERROR("Timed out waiting for IPS enable\n");
4558 }
d77e4531
PZ		 4559}
4560
20bc8673 4561void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4562{
4563 struct drm_device *dev = crtc->base.dev;
4564 struct drm_i915_private *dev_priv = dev->dev_private;
4565
6e3c9717 4566 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4567 return;
4568
4569 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4570 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4571 mutex_lock(&dev_priv->rps.hw_lock);
4572 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4573 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4574 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4575 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4576 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4577 } else {
2a114cc1 4578 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4579 POSTING_READ(IPS_CTL);
4580 }
d77e4531
PZ		 4581
4582 /* We need to wait for a vblank before we can disable the plane. */
4583 intel_wait_for_vblank(dev, crtc->pipe);
4584}
4585
4586/** Loads the palette/gamma unit for the CRTC with the prepared values */
4587static void intel_crtc_load_lut(struct drm_crtc *crtc)
4588{
4589 struct drm_device *dev = crtc->dev;
4590 struct drm_i915_private *dev_priv = dev->dev_private;
4591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4592 enum pipe pipe = intel_crtc->pipe;
4593 int palreg = PALETTE(pipe);
4594 int i;
4595 bool reenable_ips = false;
4596
4597 /* The clocks have to be on to load the palette. */
53d9f4e9 4598 if (!crtc->state->active)
d77e4531
PZ		 4599 return;
4600
50360403 4601 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4602 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4603 assert_dsi_pll_enabled(dev_priv);
4604 else
4605 assert_pll_enabled(dev_priv, pipe);
4606 }
4607
4608 /* use legacy palette for Ironlake */
7a1db49a 4609 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4610 palreg = LGC_PALETTE(pipe);
4611
4612 /* Workaround : Do not read or write the pipe palette/gamma data while
4613 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4614 */
6e3c9717 4615 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4616 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4617 GAMMA_MODE_MODE_SPLIT)) {
4618 hsw_disable_ips(intel_crtc);
4619 reenable_ips = true;
4620 }
4621
4622 for (i = 0; i < 256; i++) {
4623 I915_WRITE(palreg + 4 * i,
4624 (intel_crtc->lut_r[i] << 16) |
4625 (intel_crtc->lut_g[i] << 8) |
4626 intel_crtc->lut_b[i]);
4627 }
4628
4629 if (reenable_ips)
4630 hsw_enable_ips(intel_crtc);
4631}
4632
7cac945f 4633static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4634{
7cac945f 4635 if (intel_crtc->overlay) {
d3eedb1a
VS		 4636 struct drm_device *dev = intel_crtc->base.dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638
4639 mutex_lock(&dev->struct_mutex);
4640 dev_priv->mm.interruptible = false;
4641 (void) intel_overlay_switch_off(intel_crtc->overlay);
4642 dev_priv->mm.interruptible = true;
4643 mutex_unlock(&dev->struct_mutex);
4644 }
4645
4646 /* Let userspace switch the overlay on again. In most cases userspace
4647 * has to recompute where to put it anyway.
4648 */
4649}
4650
87d4300a
ML		 4651/**
4652 * intel_post_enable_primary - Perform operations after enabling primary plane
4653 * @crtc: the CRTC whose primary plane was just enabled
4654 *
4655 * Performs potentially sleeping operations that must be done after the primary
4656 * plane is enabled, such as updating FBC and IPS. Note that this may be
4657 * called due to an explicit primary plane update, or due to an implicit
4658 * re-enable that is caused when a sprite plane is updated to no longer
4659 * completely hide the primary plane.
4660 */
4661static void
4662intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4663{
4664 struct drm_device *dev = crtc->dev;
87d4300a 4665 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4667 int pipe = intel_crtc->pipe;
a5c4d7bc 4668
87d4300a
ML		 4669 /*
4670 * BDW signals flip done immediately if the plane
4671 * is disabled, even if the plane enable is already
4672 * armed to occur at the next vblank :(
4673 */
4674 if (IS_BROADWELL(dev))
4675 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4676
87d4300a
ML		 4677 /*
4678 * FIXME IPS should be fine as long as one plane is
4679 * enabled, but in practice it seems to have problems
4680 * when going from primary only to sprite only and vice
4681 * versa.
4682 */
a5c4d7bc
VS		 4683 hsw_enable_ips(intel_crtc);
4684
4685 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4686 intel_fbc_update(dev);
a5c4d7bc 4687 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4688
4689 /*
87d4300a
ML		 4690 * Gen2 reports pipe underruns whenever all planes are disabled.
4691 * So don't enable underrun reporting before at least some planes
4692 * are enabled.
4693 * FIXME: Need to fix the logic to work when we turn off all planes
4694 * but leave the pipe running.
f99d7069 4695 */
87d4300a
ML		 4696 if (IS_GEN2(dev))
4697 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4698
4699 /* Underruns don't raise interrupts, so check manually. */
4700 if (HAS_GMCH_DISPLAY(dev))
4701 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4702}
4703
87d4300a
ML		 4704/**
4705 * intel_pre_disable_primary - Perform operations before disabling primary plane
4706 * @crtc: the CRTC whose primary plane is to be disabled
4707 *
4708 * Performs potentially sleeping operations that must be done before the
4709 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4710 * be called due to an explicit primary plane update, or due to an implicit
4711 * disable that is caused when a sprite plane completely hides the primary
4712 * plane.
4713 */
4714static void
4715intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4716{
4717 struct drm_device *dev = crtc->dev;
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4720 int pipe = intel_crtc->pipe;
a5c4d7bc 4721
87d4300a
ML		 4722 /*
4723 * Gen2 reports pipe underruns whenever all planes are disabled.
4724 * So diasble underrun reporting before all the planes get disabled.
4725 * FIXME: Need to fix the logic to work when we turn off all planes
4726 * but leave the pipe running.
4727 */
4728 if (IS_GEN2(dev))
4729 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4730
87d4300a
ML		 4731 /*
4732 * Vblank time updates from the shadow to live plane control register
4733 * are blocked if the memory self-refresh mode is active at that
4734 * moment. So to make sure the plane gets truly disabled, disable
4735 * first the self-refresh mode. The self-refresh enable bit in turn
4736 * will be checked/applied by the HW only at the next frame start
4737 * event which is after the vblank start event, so we need to have a
4738 * wait-for-vblank between disabling the plane and the pipe.
4739 */
4740 if (HAS_GMCH_DISPLAY(dev))
4741 intel_set_memory_cxsr(dev_priv, false);
4742
4743 mutex_lock(&dev->struct_mutex);
e35fef21 4744 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4745 intel_fbc_disable(dev);
87d4300a 4746 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4747
87d4300a
ML		 4748 /*
4749 * FIXME IPS should be fine as long as one plane is
4750 * enabled, but in practice it seems to have problems
4751 * when going from primary only to sprite only and vice
4752 * versa.
4753 */
a5c4d7bc 4754 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4755}
4756
4757static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4758{
2d847d45
RV		 4759 struct drm_device *dev = crtc->dev;
4760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4761 int pipe = intel_crtc->pipe;
4762
87d4300a
ML		 4763 intel_enable_primary_hw_plane(crtc->primary, crtc);
4764 intel_enable_sprite_planes(crtc);
c0165304
ML		 4765 if (to_intel_plane_state(crtc->cursor->state)->visible)
4766 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4767
4768 intel_post_enable_primary(crtc);
2d847d45
RV		 4769
4770 /*
4771 * FIXME: Once we grow proper nuclear flip support out of this we need
4772 * to compute the mask of flip planes precisely. For the time being
4773 * consider this a flip to a NULL plane.
4774 */
4775 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
87d4300a
ML		 4776}
4777
4778static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4779{
4780 struct drm_device *dev = crtc->dev;
4781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4782 struct intel_plane *intel_plane;
4783 int pipe = intel_crtc->pipe;
4784
4785 intel_crtc_wait_for_pending_flips(crtc);
4786
4787 intel_pre_disable_primary(crtc);
a5c4d7bc 4788
7cac945f 4789 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4790 for_each_intel_plane(dev, intel_plane) {
4791 if (intel_plane->pipe == pipe) {
4792 struct drm_crtc *from = intel_plane->base.crtc;
4793
4794 intel_plane->disable_plane(&intel_plane->base,
4795 from ?: crtc, true);
4796 }
4797 }
f98551ae 4798
f99d7069
DV		 4799 /*
4800 * FIXME: Once we grow proper nuclear flip support out of this we need
4801 * to compute the mask of flip planes precisely. For the time being
4802 * consider this a flip to a NULL plane.
4803 */
4804 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4805}
4806
f67a559d
JB		 4807static void ironlake_crtc_enable(struct drm_crtc *crtc)
4808{
4809 struct drm_device *dev = crtc->dev;
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4812 struct intel_encoder *encoder;
f67a559d 4813 int pipe = intel_crtc->pipe;
f67a559d 4814
53d9f4e9 4815 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4816 return;
4817
6e3c9717 4818 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4819 intel_prepare_shared_dpll(intel_crtc);
4820
6e3c9717 4821 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4822 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4823
4824 intel_set_pipe_timings(intel_crtc);
4825
6e3c9717 4826 if (intel_crtc->config->has_pch_encoder) {
29407aab 4827 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4828 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4829 }
4830
4831 ironlake_set_pipeconf(crtc);
4832
f67a559d 4833 intel_crtc->active = true;
8664281b 4834
a72e4c9f
DV		 4835 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4836 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4837
f6736a1a 4838 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4839 if (encoder->pre_enable)
4840 encoder->pre_enable(encoder);
f67a559d 4841
6e3c9717 4842 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4843 /* Note: FDI PLL enabling _must_ be done before we enable the
4844 * cpu pipes, hence this is separate from all the other fdi/pch
4845 * enabling. */
88cefb6c 4846 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4847 } else {
4848 assert_fdi_tx_disabled(dev_priv, pipe);
4849 assert_fdi_rx_disabled(dev_priv, pipe);
4850 }
f67a559d 4851
b074cec8 4852 ironlake_pfit_enable(intel_crtc);
f67a559d 4853
9c54c0dd
JB		 4854 /*
4855 * On ILK+ LUT must be loaded before the pipe is running but with
4856 * clocks enabled
4857 */
4858 intel_crtc_load_lut(crtc);
4859
f37fcc2a 4860 intel_update_watermarks(crtc);
e1fdc473 4861 intel_enable_pipe(intel_crtc);
f67a559d 4862
6e3c9717 4863 if (intel_crtc->config->has_pch_encoder)
f67a559d 4864 ironlake_pch_enable(crtc);
c98e9dcf 4865
f9b61ff6
DV		 4866 assert_vblank_disabled(crtc);
4867 drm_crtc_vblank_on(crtc);
4868
fa5c73b1
DV		 4869 for_each_encoder_on_crtc(dev, crtc, encoder)
4870 encoder->enable(encoder);
61b77ddd
DV		 4871
4872 if (HAS_PCH_CPT(dev))
a1520318 4873 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4874}
4875
42db64ef
PZ		 4876/* IPS only exists on ULT machines and is tied to pipe A. */
4877static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4878{
f5adf94e 4879 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4880}
4881
4f771f10
PZ		 4882static void haswell_crtc_enable(struct drm_crtc *crtc)
4883{
4884 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4887 struct intel_encoder *encoder;
99d736a2
ML		 4888 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4889 struct intel_crtc_state *pipe_config =
4890 to_intel_crtc_state(crtc->state);
4f771f10 4891
53d9f4e9 4892 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4893 return;
4894
df8ad70c
DV		 4895 if (intel_crtc_to_shared_dpll(intel_crtc))
4896 intel_enable_shared_dpll(intel_crtc);
4897
6e3c9717 4898 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4899 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4900
4901 intel_set_pipe_timings(intel_crtc);
4902
6e3c9717
ACO		 4903 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4904 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4905 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4906 }
4907
6e3c9717 4908 if (intel_crtc->config->has_pch_encoder) {
229fca97 4909 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4910 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4911 }
4912
4913 haswell_set_pipeconf(crtc);
4914
4915 intel_set_pipe_csc(crtc);
4916
4f771f10 4917 intel_crtc->active = true;
8664281b 4918
a72e4c9f 4919 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4920 for_each_encoder_on_crtc(dev, crtc, encoder)
4921 if (encoder->pre_enable)
4922 encoder->pre_enable(encoder);
4923
6e3c9717 4924 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4925 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4926 true);
4fe9467d
ID		 4927 dev_priv->display.fdi_link_train(crtc);
4928 }
4929
1f544388 4930 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4931
ff6d9f55 4932 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4933 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4934 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4935 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4936 else
4937 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4938
4939 /*
4940 * On ILK+ LUT must be loaded before the pipe is running but with
4941 * clocks enabled
4942 */
4943 intel_crtc_load_lut(crtc);
4944
1f544388 4945 intel_ddi_set_pipe_settings(crtc);
8228c251 4946 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4947
f37fcc2a 4948 intel_update_watermarks(crtc);
e1fdc473 4949 intel_enable_pipe(intel_crtc);
42db64ef 4950
6e3c9717 4951 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4952 lpt_pch_enable(crtc);
4f771f10 4953
6e3c9717 4954 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4955 intel_ddi_set_vc_payload_alloc(crtc, true);
4956
f9b61ff6
DV		 4957 assert_vblank_disabled(crtc);
4958 drm_crtc_vblank_on(crtc);
4959
8807e55b 4960 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4961 encoder->enable(encoder);
8807e55b
JN		 4962 intel_opregion_notify_encoder(encoder, true);
4963 }
4f771f10 4964
e4916946
PZ		 4965 /* If we change the relative order between pipe/planes enabling, we need
4966 * to change the workaround. */
99d736a2
ML		 4967 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4968 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4969 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4970 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4971 }
4f771f10
PZ		 4972}
4973
3f8dce3a
DV		 4974static void ironlake_pfit_disable(struct intel_crtc *crtc)
4975{
4976 struct drm_device *dev = crtc->base.dev;
4977 struct drm_i915_private *dev_priv = dev->dev_private;
4978 int pipe = crtc->pipe;
4979
4980 /* To avoid upsetting the power well on haswell only disable the pfit if
4981 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4982 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4983 I915_WRITE(PF_CTL(pipe), 0);
4984 I915_WRITE(PF_WIN_POS(pipe), 0);
4985 I915_WRITE(PF_WIN_SZ(pipe), 0);
4986 }
4987}
4988
6be4a607
JB		 4989static void ironlake_crtc_disable(struct drm_crtc *crtc)
4990{
4991 struct drm_device *dev = crtc->dev;
4992 struct drm_i915_private *dev_priv = dev->dev_private;
4993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4994 struct intel_encoder *encoder;
6be4a607 4995 int pipe = intel_crtc->pipe;
5eddb70b 4996 u32 reg, temp;
b52eb4dc 4997
53d9f4e9 4998 if (WARN_ON(!intel_crtc->active))
f7abfe8b
CW		 4999 return;
5000
ea9d758d
DV		 5001 for_each_encoder_on_crtc(dev, crtc, encoder)
5002 encoder->disable(encoder);
5003
f9b61ff6
DV		 5004 drm_crtc_vblank_off(crtc);
5005 assert_vblank_disabled(crtc);
5006
6e3c9717 5007 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5008 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5009
575f7ab7 5010 intel_disable_pipe(intel_crtc);
32f9d658 5011
3f8dce3a 5012 ironlake_pfit_disable(intel_crtc);
2c07245f 5013
5a74f70a
VS		 5014 if (intel_crtc->config->has_pch_encoder)
5015 ironlake_fdi_disable(crtc);
5016
bf49ec8c
DV		 5017 for_each_encoder_on_crtc(dev, crtc, encoder)
5018 if (encoder->post_disable)
5019 encoder->post_disable(encoder);
2c07245f 5020
6e3c9717 5021 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5022 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5023
d925c59a
DV		 5024 if (HAS_PCH_CPT(dev)) {
5025 /* disable TRANS_DP_CTL */
5026 reg = TRANS_DP_CTL(pipe);
5027 temp = I915_READ(reg);
5028 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5029 TRANS_DP_PORT_SEL_MASK);
5030 temp |= TRANS_DP_PORT_SEL_NONE;
5031 I915_WRITE(reg, temp);
5032
5033 /* disable DPLL_SEL */
5034 temp = I915_READ(PCH_DPLL_SEL);
11887397 5035 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5036 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5037 }
e3421a18 5038
d925c59a 5039 /* disable PCH DPLL */
e72f9fbf 5040 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5041
d925c59a
DV		 5042 ironlake_fdi_pll_disable(intel_crtc);
5043 }
6b383a7f 5044
f7abfe8b 5045 intel_crtc->active = false;
46ba614c 5046 intel_update_watermarks(crtc);
d1ebd816
BW		 5047
5048 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5049 intel_fbc_update(dev);
d1ebd816 5050 mutex_unlock(&dev->struct_mutex);
6be4a607 5051}
1b3c7a47 5052
4f771f10 5053static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5054{
4f771f10
PZ		 5055 struct drm_device *dev = crtc->dev;
5056 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5058 struct intel_encoder *encoder;
6e3c9717 5059 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5060
53d9f4e9 5061 if (WARN_ON(!intel_crtc->active))
4f771f10
PZ		 5062 return;
5063
8807e55b
JN		 5064 for_each_encoder_on_crtc(dev, crtc, encoder) {
5065 intel_opregion_notify_encoder(encoder, false);
4f771f10 5066 encoder->disable(encoder);
8807e55b 5067 }
4f771f10 5068
f9b61ff6
DV		 5069 drm_crtc_vblank_off(crtc);
5070 assert_vblank_disabled(crtc);
5071
6e3c9717 5072 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5073 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5074 false);
575f7ab7 5075 intel_disable_pipe(intel_crtc);
4f771f10 5076
6e3c9717 5077 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5078 intel_ddi_set_vc_payload_alloc(crtc, false);
5079
ad80a810 5080 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5081
ff6d9f55 5082 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5083 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5084 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5085 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5086 else
5087 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5088
1f544388 5089 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5090
6e3c9717 5091 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5092 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5093 intel_ddi_fdi_disable(crtc);
83616634 5094 }
4f771f10 5095
97b040aa
ID		 5096 for_each_encoder_on_crtc(dev, crtc, encoder)
5097 if (encoder->post_disable)
5098 encoder->post_disable(encoder);
5099
4f771f10 5100 intel_crtc->active = false;
46ba614c 5101 intel_update_watermarks(crtc);
4f771f10
PZ		 5102
5103 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5104 intel_fbc_update(dev);
4f771f10 5105 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5106
5107 if (intel_crtc_to_shared_dpll(intel_crtc))
5108 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5109}
5110
2dd24552
JB		 5111static void i9xx_pfit_enable(struct intel_crtc *crtc)
5112{
5113 struct drm_device *dev = crtc->base.dev;
5114 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5115 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5116
681a8504 5117 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5118 return;
5119
2dd24552 5120 /*
c0b03411
DV		 5121 * The panel fitter should only be adjusted whilst the pipe is disabled,
5122 * according to register description and PRM.
2dd24552 5123 */
c0b03411
DV		 5124 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5125 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5126
b074cec8
JB		 5127 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5128 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5129
5130 /* Border color in case we don't scale up to the full screen. Black by
5131 * default, change to something else for debugging. */
5132 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5133}
5134
d05410f9
DA		 5135static enum intel_display_power_domain port_to_power_domain(enum port port)
5136{
5137 switch (port) {
5138 case PORT_A:
5139 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5140 case PORT_B:
5141 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5142 case PORT_C:
5143 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5144 case PORT_D:
5145 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5146 default:
5147 WARN_ON_ONCE(1);
5148 return POWER_DOMAIN_PORT_OTHER;
5149 }
5150}
5151
77d22dca
ID		 5152#define for_each_power_domain(domain, mask) \
5153 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5154 if ((1 << (domain)) & (mask))
5155
319be8ae
ID		 5156enum intel_display_power_domain
5157intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5158{
5159 struct drm_device *dev = intel_encoder->base.dev;
5160 struct intel_digital_port *intel_dig_port;
5161
5162 switch (intel_encoder->type) {
5163 case INTEL_OUTPUT_UNKNOWN:
5164 /* Only DDI platforms should ever use this output type */
5165 WARN_ON_ONCE(!HAS_DDI(dev));
5166 case INTEL_OUTPUT_DISPLAYPORT:
5167 case INTEL_OUTPUT_HDMI:
5168 case INTEL_OUTPUT_EDP:
5169 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5170 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5171 case INTEL_OUTPUT_DP_MST:
5172 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5173 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5174 case INTEL_OUTPUT_ANALOG:
5175 return POWER_DOMAIN_PORT_CRT;
5176 case INTEL_OUTPUT_DSI:
5177 return POWER_DOMAIN_PORT_DSI;
5178 default:
5179 return POWER_DOMAIN_PORT_OTHER;
5180 }
5181}
5182
5183static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5184{
319be8ae
ID		 5185 struct drm_device *dev = crtc->dev;
5186 struct intel_encoder *intel_encoder;
5187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5188 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5189 unsigned long mask;
5190 enum transcoder transcoder;
5191
5192 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5193
5194 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5195 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5196 if (intel_crtc->config->pch_pfit.enabled ||
5197 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5198 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5199
319be8ae
ID		 5200 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5201 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5202
77d22dca
ID		 5203 return mask;
5204}
5205
679dacd4 5206static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5207{
679dacd4 5208 struct drm_device *dev = state->dev;
77d22dca
ID		 5209 struct drm_i915_private *dev_priv = dev->dev_private;
5210 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5211 struct intel_crtc *crtc;
5212
5213 /*
5214 * First get all needed power domains, then put all unneeded, to avoid
5215 * any unnecessary toggling of the power wells.
5216 */
d3fcc808 5217 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5218 enum intel_display_power_domain domain;
5219
83d65738 5220 if (!crtc->base.state->enable)
77d22dca
ID		 5221 continue;
5222
319be8ae 5223 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5224
5225 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5226 intel_display_power_get(dev_priv, domain);
5227 }
5228
50f6e502 5229 if (dev_priv->display.modeset_global_resources)
679dacd4 5230 dev_priv->display.modeset_global_resources(state);
50f6e502 5231
d3fcc808 5232 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5233 enum intel_display_power_domain domain;
5234
5235 for_each_power_domain(domain, crtc->enabled_power_domains)
5236 intel_display_power_put(dev_priv, domain);
5237
5238 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5239 }
5240
5241 intel_display_set_init_power(dev_priv, false);
5242}
5243
560a7ae4
DL		 5244static void intel_update_max_cdclk(struct drm_device *dev)
5245{
5246 struct drm_i915_private *dev_priv = dev->dev_private;
5247
5248 if (IS_SKYLAKE(dev)) {
5249 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5250
5251 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5252 dev_priv->max_cdclk_freq = 675000;
5253 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5254 dev_priv->max_cdclk_freq = 540000;
5255 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5256 dev_priv->max_cdclk_freq = 450000;
5257 else
5258 dev_priv->max_cdclk_freq = 337500;
5259 } else if (IS_BROADWELL(dev)) {
5260 /*
5261 * FIXME with extra cooling we can allow
5262 * 540 MHz for ULX and 675 Mhz for ULT.
5263 * How can we know if extra cooling is
5264 * available? PCI ID, VTB, something else?
5265 */
5266 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5267 dev_priv->max_cdclk_freq = 450000;
5268 else if (IS_BDW_ULX(dev))
5269 dev_priv->max_cdclk_freq = 450000;
5270 else if (IS_BDW_ULT(dev))
5271 dev_priv->max_cdclk_freq = 540000;
5272 else
5273 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5274 } else if (IS_CHERRYVIEW(dev)) {
5275 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5276 } else if (IS_VALLEYVIEW(dev)) {
5277 dev_priv->max_cdclk_freq = 400000;
5278 } else {
5279 /* otherwise assume cdclk is fixed */
5280 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5281 }
5282
5283 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5284 dev_priv->max_cdclk_freq);
5285}
5286
5287static void intel_update_cdclk(struct drm_device *dev)
5288{
5289 struct drm_i915_private *dev_priv = dev->dev_private;
5290
5291 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5292 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5293 dev_priv->cdclk_freq);
5294
5295 /*
5296 * Program the gmbus_freq based on the cdclk frequency.
5297 * BSpec erroneously claims we should aim for 4MHz, but
5298 * in fact 1MHz is the correct frequency.
5299 */
5300 if (IS_VALLEYVIEW(dev)) {
5301 /*
5302 * Program the gmbus_freq based on the cdclk frequency.
5303 * BSpec erroneously claims we should aim for 4MHz, but
5304 * in fact 1MHz is the correct frequency.
5305 */
5306 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5307 }
5308
5309 if (dev_priv->max_cdclk_freq == 0)
5310 intel_update_max_cdclk(dev);
5311}
5312
70d0c574 5313static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5314{
5315 struct drm_i915_private *dev_priv = dev->dev_private;
5316 uint32_t divider;
5317 uint32_t ratio;
5318 uint32_t current_freq;
5319 int ret;
5320
5321 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5322 switch (frequency) {
5323 case 144000:
5324 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5325 ratio = BXT_DE_PLL_RATIO(60);
5326 break;
5327 case 288000:
5328 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5329 ratio = BXT_DE_PLL_RATIO(60);
5330 break;
5331 case 384000:
5332 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5333 ratio = BXT_DE_PLL_RATIO(60);
5334 break;
5335 case 576000:
5336 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5337 ratio = BXT_DE_PLL_RATIO(60);
5338 break;
5339 case 624000:
5340 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5341 ratio = BXT_DE_PLL_RATIO(65);
5342 break;
5343 case 19200:
5344 /*
5345 * Bypass frequency with DE PLL disabled. Init ratio, divider
5346 * to suppress GCC warning.
5347 */
5348 ratio = 0;
5349 divider = 0;
5350 break;
5351 default:
5352 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5353
5354 return;
5355 }
5356
5357 mutex_lock(&dev_priv->rps.hw_lock);
5358 /* Inform power controller of upcoming frequency change */
5359 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5360 0x80000000);
5361 mutex_unlock(&dev_priv->rps.hw_lock);
5362
5363 if (ret) {
5364 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5365 ret, frequency);
5366 return;
5367 }
5368
5369 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5370 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5371 current_freq = current_freq * 500 + 1000;
5372
5373 /*
5374 * DE PLL has to be disabled when
5375 * - setting to 19.2MHz (bypass, PLL isn't used)
5376 * - before setting to 624MHz (PLL needs toggling)
5377 * - before setting to any frequency from 624MHz (PLL needs toggling)
5378 */
5379 if (frequency == 19200 || frequency == 624000 ||
5380 current_freq == 624000) {
5381 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5382 /* Timeout 200us */
5383 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5384 1))
5385 DRM_ERROR("timout waiting for DE PLL unlock\n");
5386 }
5387
5388 if (frequency != 19200) {
5389 uint32_t val;
5390
5391 val = I915_READ(BXT_DE_PLL_CTL);
5392 val &= ~BXT_DE_PLL_RATIO_MASK;
5393 val |= ratio;
5394 I915_WRITE(BXT_DE_PLL_CTL, val);
5395
5396 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5397 /* Timeout 200us */
5398 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5399 DRM_ERROR("timeout waiting for DE PLL lock\n");
5400
5401 val = I915_READ(CDCLK_CTL);
5402 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5403 val |= divider;
5404 /*
5405 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5406 * enable otherwise.
5407 */
5408 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5409 if (frequency >= 500000)
5410 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5411
5412 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5413 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5414 val |= (frequency - 1000) / 500;
5415 I915_WRITE(CDCLK_CTL, val);
5416 }
5417
5418 mutex_lock(&dev_priv->rps.hw_lock);
5419 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5420 DIV_ROUND_UP(frequency, 25000));
5421 mutex_unlock(&dev_priv->rps.hw_lock);
5422
5423 if (ret) {
5424 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5425 ret, frequency);
5426 return;
5427 }
5428
a47871bd 5429 intel_update_cdclk(dev);
f8437dd1
VK		 5430}
5431
5432void broxton_init_cdclk(struct drm_device *dev)
5433{
5434 struct drm_i915_private *dev_priv = dev->dev_private;
5435 uint32_t val;
5436
5437 /*
5438 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5439 * or else the reset will hang because there is no PCH to respond.
5440 * Move the handshake programming to initialization sequence.
5441 * Previously was left up to BIOS.
5442 */
5443 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5444 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5445 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5446
5447 /* Enable PG1 for cdclk */
5448 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5449
5450 /* check if cd clock is enabled */
5451 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5452 DRM_DEBUG_KMS("Display already initialized\n");
5453 return;
5454 }
5455
5456 /*
5457 * FIXME:
5458 * - The initial CDCLK needs to be read from VBT.
5459 * Need to make this change after VBT has changes for BXT.
5460 * - check if setting the max (or any) cdclk freq is really necessary
5461 * here, it belongs to modeset time
5462 */
5463 broxton_set_cdclk(dev, 624000);
5464
5465 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5466 POSTING_READ(DBUF_CTL);
5467
f8437dd1
VK		 5468 udelay(10);
5469
5470 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5471 DRM_ERROR("DBuf power enable timeout!\n");
5472}
5473
5474void broxton_uninit_cdclk(struct drm_device *dev)
5475{
5476 struct drm_i915_private *dev_priv = dev->dev_private;
5477
5478 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5479 POSTING_READ(DBUF_CTL);
5480
f8437dd1
VK		 5481 udelay(10);
5482
5483 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5484 DRM_ERROR("DBuf power disable timeout!\n");
5485
5486 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5487 broxton_set_cdclk(dev, 19200);
5488
5489 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5490}
5491
5d96d8af
DL		 5492static const struct skl_cdclk_entry {
5493 unsigned int freq;
5494 unsigned int vco;
5495} skl_cdclk_frequencies[] = {
5496 { .freq = 308570, .vco = 8640 },
5497 { .freq = 337500, .vco = 8100 },
5498 { .freq = 432000, .vco = 8640 },
5499 { .freq = 450000, .vco = 8100 },
5500 { .freq = 540000, .vco = 8100 },
5501 { .freq = 617140, .vco = 8640 },
5502 { .freq = 675000, .vco = 8100 },
5503};
5504
5505static unsigned int skl_cdclk_decimal(unsigned int freq)
5506{
5507 return (freq - 1000) / 500;
5508}
5509
5510static unsigned int skl_cdclk_get_vco(unsigned int freq)
5511{
5512 unsigned int i;
5513
5514 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5515 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5516
5517 if (e->freq == freq)
5518 return e->vco;
5519 }
5520
5521 return 8100;
5522}
5523
5524static void
5525skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5526{
5527 unsigned int min_freq;
5528 u32 val;
5529
5530 /* select the minimum CDCLK before enabling DPLL 0 */
5531 val = I915_READ(CDCLK_CTL);
5532 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5533 val |= CDCLK_FREQ_337_308;
5534
5535 if (required_vco == 8640)
5536 min_freq = 308570;
5537 else
5538 min_freq = 337500;
5539
5540 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5541
5542 I915_WRITE(CDCLK_CTL, val);
5543 POSTING_READ(CDCLK_CTL);
5544
5545 /*
5546 * We always enable DPLL0 with the lowest link rate possible, but still
5547 * taking into account the VCO required to operate the eDP panel at the
5548 * desired frequency. The usual DP link rates operate with a VCO of
5549 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5550 * The modeset code is responsible for the selection of the exact link
5551 * rate later on, with the constraint of choosing a frequency that
5552 * works with required_vco.
5553 */
5554 val = I915_READ(DPLL_CTRL1);
5555
5556 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5557 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5558 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5559 if (required_vco == 8640)
5560 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5561 SKL_DPLL0);
5562 else
5563 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5564 SKL_DPLL0);
5565
5566 I915_WRITE(DPLL_CTRL1, val);
5567 POSTING_READ(DPLL_CTRL1);
5568
5569 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5570
5571 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5572 DRM_ERROR("DPLL0 not locked\n");
5573}
5574
5575static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5576{
5577 int ret;
5578 u32 val;
5579
5580 /* inform PCU we want to change CDCLK */
5581 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5582 mutex_lock(&dev_priv->rps.hw_lock);
5583 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5584 mutex_unlock(&dev_priv->rps.hw_lock);
5585
5586 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5587}
5588
5589static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5590{
5591 unsigned int i;
5592
5593 for (i = 0; i < 15; i++) {
5594 if (skl_cdclk_pcu_ready(dev_priv))
5595 return true;
5596 udelay(10);
5597 }
5598
5599 return false;
5600}
5601
5602static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5603{
560a7ae4 5604 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5605 u32 freq_select, pcu_ack;
5606
5607 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5608
5609 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5610 DRM_ERROR("failed to inform PCU about cdclk change\n");
5611 return;
5612 }
5613
5614 /* set CDCLK_CTL */
5615 switch(freq) {
5616 case 450000:
5617 case 432000:
5618 freq_select = CDCLK_FREQ_450_432;
5619 pcu_ack = 1;
5620 break;
5621 case 540000:
5622 freq_select = CDCLK_FREQ_540;
5623 pcu_ack = 2;
5624 break;
5625 case 308570:
5626 case 337500:
5627 default:
5628 freq_select = CDCLK_FREQ_337_308;
5629 pcu_ack = 0;
5630 break;
5631 case 617140:
5632 case 675000:
5633 freq_select = CDCLK_FREQ_675_617;
5634 pcu_ack = 3;
5635 break;
5636 }
5637
5638 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5639 POSTING_READ(CDCLK_CTL);
5640
5641 /* inform PCU of the change */
5642 mutex_lock(&dev_priv->rps.hw_lock);
5643 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5644 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5645
5646 intel_update_cdclk(dev);
5d96d8af
DL		 5647}
5648
5649void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5650{
5651 /* disable DBUF power */
5652 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5653 POSTING_READ(DBUF_CTL);
5654
5655 udelay(10);
5656
5657 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5658 DRM_ERROR("DBuf power disable timeout\n");
5659
5660 /* disable DPLL0 */
5661 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5662 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5663 DRM_ERROR("Couldn't disable DPLL0\n");
5664
5665 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5666}
5667
5668void skl_init_cdclk(struct drm_i915_private *dev_priv)
5669{
5670 u32 val;
5671 unsigned int required_vco;
5672
5673 /* enable PCH reset handshake */
5674 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5675 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5676
5677 /* enable PG1 and Misc I/O */
5678 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5679
5680 /* DPLL0 already enabed !? */
5681 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5682 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5683 return;
5684 }
5685
5686 /* enable DPLL0 */
5687 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5688 skl_dpll0_enable(dev_priv, required_vco);
5689
5690 /* set CDCLK to the frequency the BIOS chose */
5691 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5692
5693 /* enable DBUF power */
5694 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5695 POSTING_READ(DBUF_CTL);
5696
5697 udelay(10);
5698
5699 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5700 DRM_ERROR("DBuf power enable timeout\n");
5701}
5702
dfcab17e 5703/* returns HPLL frequency in kHz */
f8bf63fd 5704static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5705{
586f49dc 5706 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5707
586f49dc 5708 /* Obtain SKU information */
a580516d 5709 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5710 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5711 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5712 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5713
dfcab17e 5714 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5715}
5716
5717/* Adjust CDclk dividers to allow high res or save power if possible */
5718static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5719{
5720 struct drm_i915_private *dev_priv = dev->dev_private;
5721 u32 val, cmd;
5722
164dfd28
VK		 5723 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5724 != dev_priv->cdclk_freq);
d60c4473 5725
dfcab17e 5726 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5727 cmd = 2;
dfcab17e 5728 else if (cdclk == 266667)
30a970c6
JB		 5729 cmd = 1;
5730 else
5731 cmd = 0;
5732
5733 mutex_lock(&dev_priv->rps.hw_lock);
5734 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5735 val &= ~DSPFREQGUAR_MASK;
5736 val |= (cmd << DSPFREQGUAR_SHIFT);
5737 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5738 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5739 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5740 50)) {
5741 DRM_ERROR("timed out waiting for CDclk change\n");
5742 }
5743 mutex_unlock(&dev_priv->rps.hw_lock);
5744
54433e91
VS		 5745 mutex_lock(&dev_priv->sb_lock);
5746
dfcab17e 5747 if (cdclk == 400000) {
6bcda4f0 5748 u32 divider;
30a970c6 5749
6bcda4f0 5750 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5751
30a970c6
JB		 5752 /* adjust cdclk divider */
5753 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5754 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5755 val |= divider;
5756 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5757
5758 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5759 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5760 50))
5761 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5762 }
5763
30a970c6
JB		 5764 /* adjust self-refresh exit latency value */
5765 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5766 val &= ~0x7f;
5767
5768 /*
5769 * For high bandwidth configs, we set a higher latency in the bunit
5770 * so that the core display fetch happens in time to avoid underruns.
5771 */
dfcab17e 5772 if (cdclk == 400000)
30a970c6
JB		 5773 val |= 4500 / 250; /* 4.5 usec */
5774 else
5775 val |= 3000 / 250; /* 3.0 usec */
5776 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5777
a580516d 5778 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5779
b6283055 5780 intel_update_cdclk(dev);
30a970c6
JB		 5781}
5782
383c5a6a
VS		 5783static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5784{
5785 struct drm_i915_private *dev_priv = dev->dev_private;
5786 u32 val, cmd;
5787
164dfd28
VK		 5788 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5789 != dev_priv->cdclk_freq);
383c5a6a
VS		 5790
5791 switch (cdclk) {
383c5a6a
VS		 5792 case 333333:
5793 case 320000:
383c5a6a 5794 case 266667:
383c5a6a 5795 case 200000:
383c5a6a
VS		 5796 break;
5797 default:
5f77eeb0 5798 MISSING_CASE(cdclk);
383c5a6a
VS		 5799 return;
5800 }
5801
9d0d3fda
VS		 5802 /*
5803 * Specs are full of misinformation, but testing on actual
5804 * hardware has shown that we just need to write the desired
5805 * CCK divider into the Punit register.
5806 */
5807 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5808
383c5a6a
VS		 5809 mutex_lock(&dev_priv->rps.hw_lock);
5810 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5811 val &= ~DSPFREQGUAR_MASK_CHV;
5812 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5813 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5814 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5815 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5816 50)) {
5817 DRM_ERROR("timed out waiting for CDclk change\n");
5818 }
5819 mutex_unlock(&dev_priv->rps.hw_lock);
5820
b6283055 5821 intel_update_cdclk(dev);
383c5a6a
VS		 5822}
5823
30a970c6
JB		 5824static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5825 int max_pixclk)
5826{
6bcda4f0 5827 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5828 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5829
30a970c6
JB		 5830 /*
5831 * Really only a few cases to deal with, as only 4 CDclks are supported:
5832 * 200MHz
5833 * 267MHz
29dc7ef3 5834 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5835 * 400MHz (VLV only)
5836 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5837 * of the lower bin and adjust if needed.
e37c67a1
VS		 5838 *
5839 * We seem to get an unstable or solid color picture at 200MHz.
5840 * Not sure what's wrong. For now use 200MHz only when all pipes
5841 * are off.
30a970c6 5842 */
6cca3195
VS		 5843 if (!IS_CHERRYVIEW(dev_priv) &&
5844 max_pixclk > freq_320*limit/100)
dfcab17e 5845 return 400000;
6cca3195 5846 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5847 return freq_320;
e37c67a1 5848 else if (max_pixclk > 0)
dfcab17e 5849 return 266667;
e37c67a1
VS		 5850 else
5851 return 200000;
30a970c6
JB		 5852}
5853
f8437dd1
VK		 5854static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5855 int max_pixclk)
5856{
5857 /*
5858 * FIXME:
5859 * - remove the guardband, it's not needed on BXT
5860 * - set 19.2MHz bypass frequency if there are no active pipes
5861 */
5862 if (max_pixclk > 576000*9/10)
5863 return 624000;
5864 else if (max_pixclk > 384000*9/10)
5865 return 576000;
5866 else if (max_pixclk > 288000*9/10)
5867 return 384000;
5868 else if (max_pixclk > 144000*9/10)
5869 return 288000;
5870 else
5871 return 144000;
5872}
5873
a821fc46
ACO		 5874/* Compute the max pixel clock for new configuration. Uses atomic state if
5875 * that's non-NULL, look at current state otherwise. */
5876static int intel_mode_max_pixclk(struct drm_device *dev,
5877 struct drm_atomic_state *state)
30a970c6 5878{
30a970c6 5879 struct intel_crtc *intel_crtc;
304603f4 5880 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5881 int max_pixclk = 0;
5882
d3fcc808 5883 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5884 if (state)
5885 crtc_state =
5886 intel_atomic_get_crtc_state(state, intel_crtc);
5887 else
5888 crtc_state = intel_crtc->config;
304603f4
ACO		 5889 if (IS_ERR(crtc_state))
5890 return PTR_ERR(crtc_state);
5891
5892 if (!crtc_state->base.enable)
5893 continue;
5894
5895 max_pixclk = max(max_pixclk,
5896 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5897 }
5898
5899 return max_pixclk;
5900}
5901
0a9ab303 5902static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5903{
304603f4 5904 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5905 struct drm_crtc *crtc;
5906 struct drm_crtc_state *crtc_state;
a821fc46 5907 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
85a96e7a 5908 int cdclk, ret = 0;
30a970c6 5909
304603f4
ACO		 5910 if (max_pixclk < 0)
5911 return max_pixclk;
30a970c6 5912
f8437dd1
VK		 5913 if (IS_VALLEYVIEW(dev_priv))
5914 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5915 else
5916 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5917
5918 if (cdclk == dev_priv->cdclk_freq)
304603f4 5919 return 0;
30a970c6 5920
0a9ab303
ACO		 5921 /* add all active pipes to the state */
5922 for_each_crtc(state->dev, crtc) {
0a9ab303
ACO		 5923 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5924 if (IS_ERR(crtc_state))
5925 return PTR_ERR(crtc_state);
0a9ab303 5926
85a96e7a
ML		 5927 if (!crtc_state->active || needs_modeset(crtc_state))
5928 continue;
304603f4 5929
85a96e7a
ML		 5930 crtc_state->mode_changed = true;
5931
5932 ret = drm_atomic_add_affected_connectors(state, crtc);
5933 if (ret)
5934 break;
5935
5936 ret = drm_atomic_add_affected_planes(state, crtc);
5937 if (ret)
5938 break;
5939 }
5940
5941 return ret;
30a970c6
JB		 5942}
5943
1e69cd74
VS		 5944static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5945{
5946 unsigned int credits, default_credits;
5947
5948 if (IS_CHERRYVIEW(dev_priv))
5949 default_credits = PFI_CREDIT(12);
5950 else
5951 default_credits = PFI_CREDIT(8);
5952
164dfd28 5953 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5954 /* CHV suggested value is 31 or 63 */
5955 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5956 credits = PFI_CREDIT_63;
1e69cd74
VS		 5957 else
5958 credits = PFI_CREDIT(15);
5959 } else {
5960 credits = default_credits;
5961 }
5962
5963 /*
5964 * WA - write default credits before re-programming
5965 * FIXME: should we also set the resend bit here?
5966 */
5967 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5968 default_credits);
5969
5970 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5971 credits | PFI_CREDIT_RESEND);
5972
5973 /*
5974 * FIXME is this guaranteed to clear
5975 * immediately or should we poll for it?
5976 */
5977 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5978}
5979
a821fc46 5980static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 5981{
a821fc46 5982 struct drm_device *dev = old_state->dev;
30a970c6 5983 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 5984 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 5985 int req_cdclk;
5986
a821fc46
ACO		 5987 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5988 * never fail. */
304603f4
ACO		 5989 if (WARN_ON(max_pixclk < 0))
5990 return;
30a970c6 5991
304603f4 5992 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5993
164dfd28 5994 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5995 /*
5996 * FIXME: We can end up here with all power domains off, yet
5997 * with a CDCLK frequency other than the minimum. To account
5998 * for this take the PIPE-A power domain, which covers the HW
5999 * blocks needed for the following programming. This can be
6000 * removed once it's guaranteed that we get here either with
6001 * the minimum CDCLK set, or the required power domains
6002 * enabled.
6003 */
6004 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6005
383c5a6a
VS		 6006 if (IS_CHERRYVIEW(dev))
6007 cherryview_set_cdclk(dev, req_cdclk);
6008 else
6009 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6010
1e69cd74
VS		 6011 vlv_program_pfi_credits(dev_priv);
6012
738c05c0 6013 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6014 }
30a970c6
JB		 6015}
6016
89b667f8
JB		 6017static void valleyview_crtc_enable(struct drm_crtc *crtc)
6018{
6019 struct drm_device *dev = crtc->dev;
a72e4c9f 6020 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6022 struct intel_encoder *encoder;
6023 int pipe = intel_crtc->pipe;
23538ef1 6024 bool is_dsi;
89b667f8 6025
53d9f4e9 6026 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6027 return;
6028
409ee761 6029 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6030
1ae0d137
VS		 6031 if (!is_dsi) {
6032 if (IS_CHERRYVIEW(dev))
6e3c9717 6033 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6034 else
6e3c9717 6035 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6036 }
5b18e57c 6037
6e3c9717 6038 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6039 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6040
6041 intel_set_pipe_timings(intel_crtc);
6042
c14b0485
VS		 6043 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6044 struct drm_i915_private *dev_priv = dev->dev_private;
6045
6046 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6047 I915_WRITE(CHV_CANVAS(pipe), 0);
6048 }
6049
5b18e57c
DV		 6050 i9xx_set_pipeconf(intel_crtc);
6051
89b667f8 6052 intel_crtc->active = true;
89b667f8 6053
a72e4c9f 6054 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6055
89b667f8
JB		 6056 for_each_encoder_on_crtc(dev, crtc, encoder)
6057 if (encoder->pre_pll_enable)
6058 encoder->pre_pll_enable(encoder);
6059
9d556c99
CML		 6060 if (!is_dsi) {
6061 if (IS_CHERRYVIEW(dev))
6e3c9717 6062 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6063 else
6e3c9717 6064 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6065 }
89b667f8
JB		 6066
6067 for_each_encoder_on_crtc(dev, crtc, encoder)
6068 if (encoder->pre_enable)
6069 encoder->pre_enable(encoder);
6070
2dd24552
JB		 6071 i9xx_pfit_enable(intel_crtc);
6072
63cbb074
VS		 6073 intel_crtc_load_lut(crtc);
6074
f37fcc2a 6075 intel_update_watermarks(crtc);
e1fdc473 6076 intel_enable_pipe(intel_crtc);
be6a6f8e 6077
4b3a9526
VS		 6078 assert_vblank_disabled(crtc);
6079 drm_crtc_vblank_on(crtc);
6080
f9b61ff6
DV		 6081 for_each_encoder_on_crtc(dev, crtc, encoder)
6082 encoder->enable(encoder);
89b667f8
JB		 6083}
6084
f13c2ef3
DV		 6085static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6086{
6087 struct drm_device *dev = crtc->base.dev;
6088 struct drm_i915_private *dev_priv = dev->dev_private;
6089
6e3c9717
ACO		 6090 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6091 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6092}
6093
0b8765c6 6094static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6095{
6096 struct drm_device *dev = crtc->dev;
a72e4c9f 6097 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6099 struct intel_encoder *encoder;
79e53945 6100 int pipe = intel_crtc->pipe;
79e53945 6101
53d9f4e9 6102 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6103 return;
6104
f13c2ef3
DV		 6105 i9xx_set_pll_dividers(intel_crtc);
6106
6e3c9717 6107 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6108 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6109
6110 intel_set_pipe_timings(intel_crtc);
6111
5b18e57c
DV		 6112 i9xx_set_pipeconf(intel_crtc);
6113
f7abfe8b 6114 intel_crtc->active = true;
6b383a7f 6115
4a3436e8 6116 if (!IS_GEN2(dev))
a72e4c9f 6117 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6118
9d6d9f19
MK		 6119 for_each_encoder_on_crtc(dev, crtc, encoder)
6120 if (encoder->pre_enable)
6121 encoder->pre_enable(encoder);
6122
f6736a1a
DV		 6123 i9xx_enable_pll(intel_crtc);
6124
2dd24552
JB		 6125 i9xx_pfit_enable(intel_crtc);
6126
63cbb074
VS		 6127 intel_crtc_load_lut(crtc);
6128
f37fcc2a 6129 intel_update_watermarks(crtc);
e1fdc473 6130 intel_enable_pipe(intel_crtc);
be6a6f8e 6131
4b3a9526
VS		 6132 assert_vblank_disabled(crtc);
6133 drm_crtc_vblank_on(crtc);
6134
f9b61ff6
DV		 6135 for_each_encoder_on_crtc(dev, crtc, encoder)
6136 encoder->enable(encoder);
0b8765c6 6137}
79e53945 6138
87476d63
DV		 6139static void i9xx_pfit_disable(struct intel_crtc *crtc)
6140{
6141 struct drm_device *dev = crtc->base.dev;
6142 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6143
6e3c9717 6144 if (!crtc->config->gmch_pfit.control)
328d8e82 6145 return;
87476d63 6146
328d8e82 6147 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6148
328d8e82
DV		 6149 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6150 I915_READ(PFIT_CONTROL));
6151 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6152}
6153
0b8765c6
JB		 6154static void i9xx_crtc_disable(struct drm_crtc *crtc)
6155{
6156 struct drm_device *dev = crtc->dev;
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6159 struct intel_encoder *encoder;
0b8765c6 6160 int pipe = intel_crtc->pipe;
ef9c3aee 6161
53d9f4e9 6162 if (WARN_ON(!intel_crtc->active))
f7abfe8b
CW		 6163 return;
6164
6304cd91
VS		 6165 /*
6166 * On gen2 planes are double buffered but the pipe isn't, so we must
6167 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6168 * We also need to wait on all gmch platforms because of the
6169 * self-refresh mode constraint explained above.
6304cd91 6170 */
564ed191 6171 intel_wait_for_vblank(dev, pipe);
6304cd91 6172
4b3a9526
VS		 6173 for_each_encoder_on_crtc(dev, crtc, encoder)
6174 encoder->disable(encoder);
6175
f9b61ff6
DV		 6176 drm_crtc_vblank_off(crtc);
6177 assert_vblank_disabled(crtc);
6178
575f7ab7 6179 intel_disable_pipe(intel_crtc);
24a1f16d 6180
87476d63 6181 i9xx_pfit_disable(intel_crtc);
24a1f16d 6182
89b667f8
JB		 6183 for_each_encoder_on_crtc(dev, crtc, encoder)
6184 if (encoder->post_disable)
6185 encoder->post_disable(encoder);
6186
409ee761 6187 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6188 if (IS_CHERRYVIEW(dev))
6189 chv_disable_pll(dev_priv, pipe);
6190 else if (IS_VALLEYVIEW(dev))
6191 vlv_disable_pll(dev_priv, pipe);
6192 else
1c4e0274 6193 i9xx_disable_pll(intel_crtc);
076ed3b2 6194 }
0b8765c6 6195
4a3436e8 6196 if (!IS_GEN2(dev))
a72e4c9f 6197 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6198
f7abfe8b 6199 intel_crtc->active = false;
46ba614c 6200 intel_update_watermarks(crtc);
f37fcc2a 6201
efa9624e 6202 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6203 intel_fbc_update(dev);
efa9624e 6204 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6205}
6206
b17d48e2
ML		 6207static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6208{
6209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6211 enum intel_display_power_domain domain;
6212 unsigned long domains;
6213
6214 if (!intel_crtc->active)
6215 return;
6216
6217 intel_crtc_disable_planes(crtc);
6218 dev_priv->display.crtc_disable(crtc);
6219
6220 domains = intel_crtc->enabled_power_domains;
6221 for_each_power_domain(domain, domains)
6222 intel_display_power_put(dev_priv, domain);
6223 intel_crtc->enabled_power_domains = 0;
6224}
6225
6b72d486
ML		 6226/*
6227 * turn all crtc's off, but do not adjust state
6228 * This has to be paired with a call to intel_modeset_setup_hw_state.
6229 */
9716c691 6230void intel_display_suspend(struct drm_device *dev)
ee7b9f93 6231{
6b72d486
ML		 6232 struct drm_crtc *crtc;
6233
b17d48e2
ML		 6234 for_each_crtc(dev, crtc)
6235 intel_crtc_disable_noatomic(crtc);
ee7b9f93
JB		 6236}
6237
b04c5bd6 6238/* Master function to enable/disable CRTC and corresponding power wells */
5da76e94 6239int intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6240{
6241 struct drm_device *dev = crtc->dev;
5da76e94
ML		 6242 struct drm_mode_config *config = &dev->mode_config;
6243 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
0e572fe7 6244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5da76e94
ML		 6245 struct intel_crtc_state *pipe_config;
6246 struct drm_atomic_state *state;
6247 int ret;
976f8a20 6248
1b509259 6249 if (enable == intel_crtc->active)
5da76e94 6250 return 0;
0e572fe7 6251
1b509259 6252 if (enable && !crtc->state->enable)
5da76e94 6253 return 0;
1b509259 6254
5da76e94
ML		 6255 /* this function should be called with drm_modeset_lock_all for now */
6256 if (WARN_ON(!ctx))
6257 return -EIO;
6258 lockdep_assert_held(&ctx->ww_ctx);
1b509259 6259
5da76e94
ML		 6260 state = drm_atomic_state_alloc(dev);
6261 if (WARN_ON(!state))
6262 return -ENOMEM;
1b509259 6263
5da76e94
ML		 6264 state->acquire_ctx = ctx;
6265 state->allow_modeset = true;
6266
6267 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6268 if (IS_ERR(pipe_config)) {
6269 ret = PTR_ERR(pipe_config);
6270 goto err;
0e572fe7 6271 }
5da76e94
ML		 6272 pipe_config->base.active = enable;
6273
6274 ret = intel_set_mode(state);
6275 if (!ret)
6276 return ret;
6277
6278err:
6279 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6280 drm_atomic_state_free(state);
6281 return ret;
b04c5bd6
BF		 6282}
6283
6284/**
6285 * Sets the power management mode of the pipe and plane.
6286 */
6287void intel_crtc_update_dpms(struct drm_crtc *crtc)
6288{
6289 struct drm_device *dev = crtc->dev;
6290 struct intel_encoder *intel_encoder;
6291 bool enable = false;
6292
6293 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6294 enable |= intel_encoder->connectors_active;
6295
6296 intel_crtc_control(crtc, enable);
cdd59983
CW		 6297}
6298
ea5b213a 6299void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6300{
4ef69c7a 6301 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6302
ea5b213a
CW		 6303 drm_encoder_cleanup(encoder);
6304 kfree(intel_encoder);
7e7d76c3
JB		 6305}
6306
9237329d 6307/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6308 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6309 * state of the entire output pipe. */
9237329d 6310static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6311{
5ab432ef
DV		 6312 if (mode == DRM_MODE_DPMS_ON) {
6313 encoder->connectors_active = true;
6314
b2cabb0e 6315 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6316 } else {
6317 encoder->connectors_active = false;
6318
b2cabb0e 6319 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6320 }
79e53945
JB		 6321}
6322
0a91ca29
DV		 6323/* Cross check the actual hw state with our own modeset state tracking (and it's
6324 * internal consistency). */
b980514c 6325static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6326{
0a91ca29
DV		 6327 if (connector->get_hw_state(connector)) {
6328 struct intel_encoder *encoder = connector->encoder;
6329 struct drm_crtc *crtc;
6330 bool encoder_enabled;
6331 enum pipe pipe;
6332
6333 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6334 connector->base.base.id,
c23cc417 6335 connector->base.name);
0a91ca29 6336
0e32b39c
DA		 6337 /* there is no real hw state for MST connectors */
6338 if (connector->mst_port)
6339 return;
6340
e2c719b7 6341 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6342 "wrong connector dpms state\n");
e2c719b7 6343 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6344 "active connector not linked to encoder\n");
0a91ca29 6345
36cd7444 6346 if (encoder) {
e2c719b7 6347 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6348 "encoder->connectors_active not set\n");
6349
6350 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6351 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6352 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6353 return;
0a91ca29 6354
36cd7444 6355 crtc = encoder->base.crtc;
0a91ca29 6356
83d65738
MR		 6357 I915_STATE_WARN(!crtc->state->enable,
6358 "crtc not enabled\n");
e2c719b7
RC		 6359 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6360 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6361 "encoder active on the wrong pipe\n");
6362 }
0a91ca29 6363 }
79e53945
JB		 6364}
6365
08d9bc92
ACO		 6366int intel_connector_init(struct intel_connector *connector)
6367{
6368 struct drm_connector_state *connector_state;
6369
6370 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6371 if (!connector_state)
6372 return -ENOMEM;
6373
6374 connector->base.state = connector_state;
6375 return 0;
6376}
6377
6378struct intel_connector *intel_connector_alloc(void)
6379{
6380 struct intel_connector *connector;
6381
6382 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6383 if (!connector)
6384 return NULL;
6385
6386 if (intel_connector_init(connector) < 0) {
6387 kfree(connector);
6388 return NULL;
6389 }
6390
6391 return connector;
6392}
6393
5ab432ef
DV		 6394/* Even simpler default implementation, if there's really no special case to
6395 * consider. */
6396void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6397{
5ab432ef
DV		 6398 /* All the simple cases only support two dpms states. */
6399 if (mode != DRM_MODE_DPMS_ON)
6400 mode = DRM_MODE_DPMS_OFF;
d4270e57 6401
5ab432ef
DV		 6402 if (mode == connector->dpms)
6403 return;
6404
6405 connector->dpms = mode;
6406
6407 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6408 if (connector->encoder)
6409 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6410
b980514c 6411 intel_modeset_check_state(connector->dev);
79e53945
JB		 6412}
6413
f0947c37
DV		 6414/* Simple connector->get_hw_state implementation for encoders that support only
6415 * one connector and no cloning and hence the encoder state determines the state
6416 * of the connector. */
6417bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6418{
24929352 6419 enum pipe pipe = 0;
f0947c37 6420 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6421
f0947c37 6422 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6423}
6424
6d293983 6425static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6426{
6d293983
ACO		 6427 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6428 return crtc_state->fdi_lanes;
d272ddfa
VS		 6429
6430 return 0;
6431}
6432
6d293983 6433static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6434 struct intel_crtc_state *pipe_config)
1857e1da 6435{
6d293983
ACO		 6436 struct drm_atomic_state *state = pipe_config->base.state;
6437 struct intel_crtc *other_crtc;
6438 struct intel_crtc_state *other_crtc_state;
6439
1857e1da
DV		 6440 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6441 pipe_name(pipe), pipe_config->fdi_lanes);
6442 if (pipe_config->fdi_lanes > 4) {
6443 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6444 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6445 return -EINVAL;
1857e1da
DV		 6446 }
6447
bafb6553 6448 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6449 if (pipe_config->fdi_lanes > 2) {
6450 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6451 pipe_config->fdi_lanes);
6d293983 6452 return -EINVAL;
1857e1da 6453 } else {
6d293983 6454 return 0;
1857e1da
DV		 6455 }
6456 }
6457
6458 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6459 return 0;
1857e1da
DV		 6460
6461 /* Ivybridge 3 pipe is really complicated */
6462 switch (pipe) {
6463 case PIPE_A:
6d293983 6464 return 0;
1857e1da 6465 case PIPE_B:
6d293983
ACO		 6466 if (pipe_config->fdi_lanes <= 2)
6467 return 0;
6468
6469 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6470 other_crtc_state =
6471 intel_atomic_get_crtc_state(state, other_crtc);
6472 if (IS_ERR(other_crtc_state))
6473 return PTR_ERR(other_crtc_state);
6474
6475 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6476 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6477 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6478 return -EINVAL;
1857e1da 6479 }
6d293983 6480 return 0;
1857e1da 6481 case PIPE_C:
251cc67c
VS		 6482 if (pipe_config->fdi_lanes > 2) {
6483 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6484 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6485 return -EINVAL;
251cc67c 6486 }
6d293983
ACO		 6487
6488 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6489 other_crtc_state =
6490 intel_atomic_get_crtc_state(state, other_crtc);
6491 if (IS_ERR(other_crtc_state))
6492 return PTR_ERR(other_crtc_state);
6493
6494 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6495 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6496 return -EINVAL;
1857e1da 6497 }
6d293983 6498 return 0;
1857e1da
DV		 6499 default:
6500 BUG();
6501 }
6502}
6503
e29c22c0
DV		 6504#define RETRY 1
6505static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6506 struct intel_crtc_state *pipe_config)
877d48d5 6507{
1857e1da 6508 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6509 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6510 int lane, link_bw, fdi_dotclock, ret;
6511 bool needs_recompute = false;
877d48d5 6512
e29c22c0 6513retry:
877d48d5
DV		 6514 /* FDI is a binary signal running at ~2.7GHz, encoding
6515 * each output octet as 10 bits. The actual frequency
6516 * is stored as a divider into a 100MHz clock, and the
6517 * mode pixel clock is stored in units of 1KHz.
6518 * Hence the bw of each lane in terms of the mode signal
6519 * is:
6520 */
6521 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6522
241bfc38 6523 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6524
2bd89a07 6525 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6526 pipe_config->pipe_bpp);
6527
6528 pipe_config->fdi_lanes = lane;
6529
2bd89a07 6530 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6531 link_bw, &pipe_config->fdi_m_n);
1857e1da 6532
6d293983
ACO		 6533 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6534 intel_crtc->pipe, pipe_config);
6535 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6536 pipe_config->pipe_bpp -= 2*3;
6537 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6538 pipe_config->pipe_bpp);
6539 needs_recompute = true;
6540 pipe_config->bw_constrained = true;
6541
6542 goto retry;
6543 }
6544
6545 if (needs_recompute)
6546 return RETRY;
6547
6d293983 6548 return ret;
877d48d5
DV		 6549}
6550
8cfb3407
VS		 6551static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6552 struct intel_crtc_state *pipe_config)
6553{
6554 if (pipe_config->pipe_bpp > 24)
6555 return false;
6556
6557 /* HSW can handle pixel rate up to cdclk? */
6558 if (IS_HASWELL(dev_priv->dev))
6559 return true;
6560
6561 /*
b432e5cf
VS		 6562 * We compare against max which means we must take
6563 * the increased cdclk requirement into account when
6564 * calculating the new cdclk.
6565 *
6566 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6567 */
6568 return ilk_pipe_pixel_rate(pipe_config) <=
6569 dev_priv->max_cdclk_freq * 95 / 100;
6570}
6571
42db64ef 6572static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6573 struct intel_crtc_state *pipe_config)
42db64ef 6574{
8cfb3407
VS		 6575 struct drm_device *dev = crtc->base.dev;
6576 struct drm_i915_private *dev_priv = dev->dev_private;
6577
d330a953 6578 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6579 hsw_crtc_supports_ips(crtc) &&
6580 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6581}
6582
a43f6e0f 6583static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6584 struct intel_crtc_state *pipe_config)
79e53945 6585{
a43f6e0f 6586 struct drm_device *dev = crtc->base.dev;
8bd31e67 6587 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6588 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6589 int ret;
89749350 6590
ad3a4479 6591 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6592 if (INTEL_INFO(dev)->gen < 4) {
44913155 6593 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6594
6595 /*
6596 * Enable pixel doubling when the dot clock
6597 * is > 90% of the (display) core speed.
6598 *
b397c96b
VS		 6599 * GDG double wide on either pipe,
6600 * otherwise pipe A only.
cf532bb2 6601 */
b397c96b 6602 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6603 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6604 clock_limit *= 2;
cf532bb2 6605 pipe_config->double_wide = true;
ad3a4479
VS		 6606 }
6607
241bfc38 6608 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6609 return -EINVAL;
2c07245f 6610 }
89749350 6611
1d1d0e27
VS		 6612 /*
6613 * Pipe horizontal size must be even in:
6614 * - DVO ganged mode
6615 * - LVDS dual channel mode
6616 * - Double wide pipe
6617 */
a93e255f 6618 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6619 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6620 pipe_config->pipe_src_w &= ~1;
6621
8693a824
DL		 6622 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6623 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6624 */
6625 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6626 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6627 return -EINVAL;
44f46b42 6628
f5adf94e 6629 if (HAS_IPS(dev))
a43f6e0f
DV		 6630 hsw_compute_ips_config(crtc, pipe_config);
6631
877d48d5 6632 if (pipe_config->has_pch_encoder)
a43f6e0f 6633 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6634
d03c93d4
CK		 6635 /* FIXME: remove below call once atomic mode set is place and all crtc
6636 * related checks called from atomic_crtc_check function */
6637 ret = 0;
6638 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6639 crtc, pipe_config->base.state);
6640 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6641
6642 return ret;
79e53945
JB		 6643}
6644
1652d19e
VS		 6645static int skylake_get_display_clock_speed(struct drm_device *dev)
6646{
6647 struct drm_i915_private *dev_priv = to_i915(dev);
6648 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6649 uint32_t cdctl = I915_READ(CDCLK_CTL);
6650 uint32_t linkrate;
6651
414355a7 6652 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6653 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6654
6655 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6656 return 540000;
6657
6658 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6659 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6660
71cd8423
DL		 6661 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6662 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6663 /* vco 8640 */
6664 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6665 case CDCLK_FREQ_450_432:
6666 return 432000;
6667 case CDCLK_FREQ_337_308:
6668 return 308570;
6669 case CDCLK_FREQ_675_617:
6670 return 617140;
6671 default:
6672 WARN(1, "Unknown cd freq selection\n");
6673 }
6674 } else {
6675 /* vco 8100 */
6676 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6677 case CDCLK_FREQ_450_432:
6678 return 450000;
6679 case CDCLK_FREQ_337_308:
6680 return 337500;
6681 case CDCLK_FREQ_675_617:
6682 return 675000;
6683 default:
6684 WARN(1, "Unknown cd freq selection\n");
6685 }
6686 }
6687
6688 /* error case, do as if DPLL0 isn't enabled */
6689 return 24000;
6690}
6691
6692static int broadwell_get_display_clock_speed(struct drm_device *dev)
6693{
6694 struct drm_i915_private *dev_priv = dev->dev_private;
6695 uint32_t lcpll = I915_READ(LCPLL_CTL);
6696 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6697
6698 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6699 return 800000;
6700 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6701 return 450000;
6702 else if (freq == LCPLL_CLK_FREQ_450)
6703 return 450000;
6704 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6705 return 540000;
6706 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6707 return 337500;
6708 else
6709 return 675000;
6710}
6711
6712static int haswell_get_display_clock_speed(struct drm_device *dev)
6713{
6714 struct drm_i915_private *dev_priv = dev->dev_private;
6715 uint32_t lcpll = I915_READ(LCPLL_CTL);
6716 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6717
6718 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6719 return 800000;
6720 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6721 return 450000;
6722 else if (freq == LCPLL_CLK_FREQ_450)
6723 return 450000;
6724 else if (IS_HSW_ULT(dev))
6725 return 337500;
6726 else
6727 return 540000;
79e53945
JB		 6728}
6729
25eb05fc
JB		 6730static int valleyview_get_display_clock_speed(struct drm_device *dev)
6731{
d197b7d3 6732 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6733 u32 val;
6734 int divider;
6735
6bcda4f0
VS		 6736 if (dev_priv->hpll_freq == 0)
6737 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6738
a580516d 6739 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6740 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6741 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6742
6743 divider = val & DISPLAY_FREQUENCY_VALUES;
6744
7d007f40
VS		 6745 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6746 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6747 "cdclk change in progress\n");
6748
6bcda4f0 6749 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6750}
6751
b37a6434
VS		 6752static int ilk_get_display_clock_speed(struct drm_device *dev)
6753{
6754 return 450000;
6755}
6756
e70236a8
JB		 6757static int i945_get_display_clock_speed(struct drm_device *dev)
6758{
6759 return 400000;
6760}
79e53945 6761
e70236a8 6762static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6763{
e907f170 6764 return 333333;
e70236a8 6765}
79e53945 6766
e70236a8
JB		 6767static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6768{
6769 return 200000;
6770}
79e53945 6771
257a7ffc
DV		 6772static int pnv_get_display_clock_speed(struct drm_device *dev)
6773{
6774 u16 gcfgc = 0;
6775
6776 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6777
6778 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6779 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6780 return 266667;
257a7ffc 6781 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6782 return 333333;
257a7ffc 6783 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6784 return 444444;
257a7ffc
DV		 6785 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6786 return 200000;
6787 default:
6788 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6789 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6790 return 133333;
257a7ffc 6791 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6792 return 166667;
257a7ffc
DV		 6793 }
6794}
6795
e70236a8
JB		 6796static int i915gm_get_display_clock_speed(struct drm_device *dev)
6797{
6798 u16 gcfgc = 0;
79e53945 6799
e70236a8
JB		 6800 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6801
6802 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6803 return 133333;
e70236a8
JB		 6804 else {
6805 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6806 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6807 return 333333;
e70236a8
JB		 6808 default:
6809 case GC_DISPLAY_CLOCK_190_200_MHZ:
6810 return 190000;
79e53945 6811 }
e70236a8
JB		 6812 }
6813}
6814
6815static int i865_get_display_clock_speed(struct drm_device *dev)
6816{
e907f170 6817 return 266667;
e70236a8
JB		 6818}
6819
1b1d2716 6820static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6821{
6822 u16 hpllcc = 0;
1b1d2716 6823
65cd2b3f
VS		 6824 /*
6825 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6826 * encoding is different :(
6827 * FIXME is this the right way to detect 852GM/852GMV?
6828 */
6829 if (dev->pdev->revision == 0x1)
6830 return 133333;
6831
1b1d2716
VS		 6832 pci_bus_read_config_word(dev->pdev->bus,
6833 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6834
e70236a8
JB		 6835 /* Assume that the hardware is in the high speed state. This
6836 * should be the default.
6837 */
6838 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6839 case GC_CLOCK_133_200:
1b1d2716 6840 case GC_CLOCK_133_200_2:
e70236a8
JB		 6841 case GC_CLOCK_100_200:
6842 return 200000;
6843 case GC_CLOCK_166_250:
6844 return 250000;
6845 case GC_CLOCK_100_133:
e907f170 6846 return 133333;
1b1d2716
VS		 6847 case GC_CLOCK_133_266:
6848 case GC_CLOCK_133_266_2:
6849 case GC_CLOCK_166_266:
6850 return 266667;
e70236a8 6851 }
79e53945 6852
e70236a8
JB		 6853 /* Shouldn't happen */
6854 return 0;
6855}
79e53945 6856
e70236a8
JB		 6857static int i830_get_display_clock_speed(struct drm_device *dev)
6858{
e907f170 6859 return 133333;
79e53945
JB		 6860}
6861
34edce2f
VS		 6862static unsigned int intel_hpll_vco(struct drm_device *dev)
6863{
6864 struct drm_i915_private *dev_priv = dev->dev_private;
6865 static const unsigned int blb_vco[8] = {
6866 [0] = 3200000,
6867 [1] = 4000000,
6868 [2] = 5333333,
6869 [3] = 4800000,
6870 [4] = 6400000,
6871 };
6872 static const unsigned int pnv_vco[8] = {
6873 [0] = 3200000,
6874 [1] = 4000000,
6875 [2] = 5333333,
6876 [3] = 4800000,
6877 [4] = 2666667,
6878 };
6879 static const unsigned int cl_vco[8] = {
6880 [0] = 3200000,
6881 [1] = 4000000,
6882 [2] = 5333333,
6883 [3] = 6400000,
6884 [4] = 3333333,
6885 [5] = 3566667,
6886 [6] = 4266667,
6887 };
6888 static const unsigned int elk_vco[8] = {
6889 [0] = 3200000,
6890 [1] = 4000000,
6891 [2] = 5333333,
6892 [3] = 4800000,
6893 };
6894 static const unsigned int ctg_vco[8] = {
6895 [0] = 3200000,
6896 [1] = 4000000,
6897 [2] = 5333333,
6898 [3] = 6400000,
6899 [4] = 2666667,
6900 [5] = 4266667,
6901 };
6902 const unsigned int *vco_table;
6903 unsigned int vco;
6904 uint8_t tmp = 0;
6905
6906 /* FIXME other chipsets? */
6907 if (IS_GM45(dev))
6908 vco_table = ctg_vco;
6909 else if (IS_G4X(dev))
6910 vco_table = elk_vco;
6911 else if (IS_CRESTLINE(dev))
6912 vco_table = cl_vco;
6913 else if (IS_PINEVIEW(dev))
6914 vco_table = pnv_vco;
6915 else if (IS_G33(dev))
6916 vco_table = blb_vco;
6917 else
6918 return 0;
6919
6920 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6921
6922 vco = vco_table[tmp & 0x7];
6923 if (vco == 0)
6924 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6925 else
6926 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6927
6928 return vco;
6929}
6930
6931static int gm45_get_display_clock_speed(struct drm_device *dev)
6932{
6933 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6934 uint16_t tmp = 0;
6935
6936 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6937
6938 cdclk_sel = (tmp >> 12) & 0x1;
6939
6940 switch (vco) {
6941 case 2666667:
6942 case 4000000:
6943 case 5333333:
6944 return cdclk_sel ? 333333 : 222222;
6945 case 3200000:
6946 return cdclk_sel ? 320000 : 228571;
6947 default:
6948 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6949 return 222222;
6950 }
6951}
6952
6953static int i965gm_get_display_clock_speed(struct drm_device *dev)
6954{
6955 static const uint8_t div_3200[] = { 16, 10, 8 };
6956 static const uint8_t div_4000[] = { 20, 12, 10 };
6957 static const uint8_t div_5333[] = { 24, 16, 14 };
6958 const uint8_t *div_table;
6959 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6960 uint16_t tmp = 0;
6961
6962 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6963
6964 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6965
6966 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6967 goto fail;
6968
6969 switch (vco) {
6970 case 3200000:
6971 div_table = div_3200;
6972 break;
6973 case 4000000:
6974 div_table = div_4000;
6975 break;
6976 case 5333333:
6977 div_table = div_5333;
6978 break;
6979 default:
6980 goto fail;
6981 }
6982
6983 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6984
caf4e252 6985fail:
34edce2f
VS		 6986 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6987 return 200000;
6988}
6989
6990static int g33_get_display_clock_speed(struct drm_device *dev)
6991{
6992 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6993 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6994 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6995 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6996 const uint8_t *div_table;
6997 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6998 uint16_t tmp = 0;
6999
7000 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7001
7002 cdclk_sel = (tmp >> 4) & 0x7;
7003
7004 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7005 goto fail;
7006
7007 switch (vco) {
7008 case 3200000:
7009 div_table = div_3200;
7010 break;
7011 case 4000000:
7012 div_table = div_4000;
7013 break;
7014 case 4800000:
7015 div_table = div_4800;
7016 break;
7017 case 5333333:
7018 div_table = div_5333;
7019 break;
7020 default:
7021 goto fail;
7022 }
7023
7024 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7025
caf4e252 7026fail:
34edce2f
VS		 7027 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7028 return 190476;
7029}
7030
2c07245f 7031static void
a65851af 7032intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7033{
a65851af
VS		 7034 while (*num > DATA_LINK_M_N_MASK ||
7035 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7036 *num >>= 1;
7037 *den >>= 1;
7038 }
7039}
7040
a65851af
VS		 7041static void compute_m_n(unsigned int m, unsigned int n,
7042 uint32_t *ret_m, uint32_t *ret_n)
7043{
7044 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7045 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7046 intel_reduce_m_n_ratio(ret_m, ret_n);
7047}
7048
e69d0bc1
DV		 7049void
7050intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7051 int pixel_clock, int link_clock,
7052 struct intel_link_m_n *m_n)
2c07245f 7053{
e69d0bc1 7054 m_n->tu = 64;
a65851af
VS		 7055
7056 compute_m_n(bits_per_pixel * pixel_clock,
7057 link_clock * nlanes * 8,
7058 &m_n->gmch_m, &m_n->gmch_n);
7059
7060 compute_m_n(pixel_clock, link_clock,
7061 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7062}
7063
a7615030
CW		 7064static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7065{
d330a953
JN		 7066 if (i915.panel_use_ssc >= 0)
7067 return i915.panel_use_ssc != 0;
41aa3448 7068 return dev_priv->vbt.lvds_use_ssc
435793df 7069 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7070}
7071
a93e255f
ACO		 7072static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7073 int num_connectors)
c65d77d8 7074{
a93e255f 7075 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7076 struct drm_i915_private *dev_priv = dev->dev_private;
7077 int refclk;
7078
a93e255f
ACO		 7079 WARN_ON(!crtc_state->base.state);
7080
5ab7b0b7 7081 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7082 refclk = 100000;
a93e255f 7083 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7084 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7085 refclk = dev_priv->vbt.lvds_ssc_freq;
7086 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7087 } else if (!IS_GEN2(dev)) {
7088 refclk = 96000;
7089 } else {
7090 refclk = 48000;
7091 }
7092
7093 return refclk;
7094}
7095
7429e9d4 7096static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7097{
7df00d7a 7098 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7099}
f47709a9 7100
7429e9d4
DV		 7101static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7102{
7103 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7104}
7105
f47709a9 7106static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7107 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7108 intel_clock_t *reduced_clock)
7109{
f47709a9 7110 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7111 u32 fp, fp2 = 0;
7112
7113 if (IS_PINEVIEW(dev)) {
190f68c5 7114 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7115 if (reduced_clock)
7429e9d4 7116 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7117 } else {
190f68c5 7118 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7119 if (reduced_clock)
7429e9d4 7120 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7121 }
7122
190f68c5 7123 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7124
f47709a9 7125 crtc->lowfreq_avail = false;
a93e255f 7126 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7127 reduced_clock) {
190f68c5 7128 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7129 crtc->lowfreq_avail = true;
a7516a05 7130 } else {
190f68c5 7131 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7132 }
7133}
7134
5e69f97f
CML		 7135static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7136 pipe)
89b667f8
JB		 7137{
7138 u32 reg_val;
7139
7140 /*
7141 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7142 * and set it to a reasonable value instead.
7143 */
ab3c759a 7144 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7145 reg_val &= 0xffffff00;
7146 reg_val |= 0x00000030;
ab3c759a 7147 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7148
ab3c759a 7149 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7150 reg_val &= 0x8cffffff;
7151 reg_val = 0x8c000000;
ab3c759a 7152 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7153
ab3c759a 7154 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7155 reg_val &= 0xffffff00;
ab3c759a 7156 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7157
ab3c759a 7158 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7159 reg_val &= 0x00ffffff;
7160 reg_val |= 0xb0000000;
ab3c759a 7161 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7162}
7163
b551842d
DV		 7164static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7165 struct intel_link_m_n *m_n)
7166{
7167 struct drm_device *dev = crtc->base.dev;
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169 int pipe = crtc->pipe;
7170
e3b95f1e
DV		 7171 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7172 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7173 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7174 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7175}
7176
7177static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7178 struct intel_link_m_n *m_n,
7179 struct intel_link_m_n *m2_n2)
b551842d
DV		 7180{
7181 struct drm_device *dev = crtc->base.dev;
7182 struct drm_i915_private *dev_priv = dev->dev_private;
7183 int pipe = crtc->pipe;
6e3c9717 7184 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7185
7186 if (INTEL_INFO(dev)->gen >= 5) {
7187 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7188 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7189 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7190 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7191 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7192 * for gen < 8) and if DRRS is supported (to make sure the
7193 * registers are not unnecessarily accessed).
7194 */
44395bfe 7195 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7196 crtc->config->has_drrs) {
f769cd24
VK		 7197 I915_WRITE(PIPE_DATA_M2(transcoder),
7198 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7199 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7200 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7201 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7202 }
b551842d 7203 } else {
e3b95f1e
DV		 7204 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7205 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7206 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7207 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7208 }
7209}
7210
fe3cd48d 7211void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7212{
fe3cd48d
R		 7213 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7214
7215 if (m_n == M1_N1) {
7216 dp_m_n = &crtc->config->dp_m_n;
7217 dp_m2_n2 = &crtc->config->dp_m2_n2;
7218 } else if (m_n == M2_N2) {
7219
7220 /*
7221 * M2_N2 registers are not supported. Hence m2_n2 divider value
7222 * needs to be programmed into M1_N1.
7223 */
7224 dp_m_n = &crtc->config->dp_m2_n2;
7225 } else {
7226 DRM_ERROR("Unsupported divider value\n");
7227 return;
7228 }
7229
6e3c9717
ACO		 7230 if (crtc->config->has_pch_encoder)
7231 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7232 else
fe3cd48d 7233 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7234}
7235
d288f65f 7236static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7237 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7238{
7239 u32 dpll, dpll_md;
7240
7241 /*
7242 * Enable DPIO clock input. We should never disable the reference
7243 * clock for pipe B, since VGA hotplug / manual detection depends
7244 * on it.
7245 */
7246 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7247 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7248 /* We should never disable this, set it here for state tracking */
7249 if (crtc->pipe == PIPE_B)
7250 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7251 dpll |= DPLL_VCO_ENABLE;
d288f65f 7252 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7253
d288f65f 7254 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7255 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7256 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7257}
7258
d288f65f 7259static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7260 const struct intel_crtc_state *pipe_config)
a0c4da24 7261{
f47709a9 7262 struct drm_device *dev = crtc->base.dev;
a0c4da24 7263 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7264 int pipe = crtc->pipe;
bdd4b6a6 7265 u32 mdiv;
a0c4da24 7266 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7267 u32 coreclk, reg_val;
a0c4da24 7268
a580516d 7269 mutex_lock(&dev_priv->sb_lock);
09153000 7270
d288f65f
VS		 7271 bestn = pipe_config->dpll.n;
7272 bestm1 = pipe_config->dpll.m1;
7273 bestm2 = pipe_config->dpll.m2;
7274 bestp1 = pipe_config->dpll.p1;
7275 bestp2 = pipe_config->dpll.p2;
a0c4da24 7276
89b667f8
JB		 7277 /* See eDP HDMI DPIO driver vbios notes doc */
7278
7279 /* PLL B needs special handling */
bdd4b6a6 7280 if (pipe == PIPE_B)
5e69f97f 7281 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7282
7283 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7285
7286 /* Disable target IRef on PLL */
ab3c759a 7287 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7288 reg_val &= 0x00ffffff;
ab3c759a 7289 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7290
7291 /* Disable fast lock */
ab3c759a 7292 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7293
7294 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7295 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7296 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7297 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7298 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7299
7300 /*
7301 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7302 * but we don't support that).
7303 * Note: don't use the DAC post divider as it seems unstable.
7304 */
7305 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7306 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7307
a0c4da24 7308 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7309 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7310
89b667f8 7311 /* Set HBR and RBR LPF coefficients */
d288f65f 7312 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7313 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7314 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7315 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7316 0x009f0003);
89b667f8 7317 else
ab3c759a 7318 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7319 0x00d0000f);
7320
681a8504 7321 if (pipe_config->has_dp_encoder) {
89b667f8 7322 /* Use SSC source */
bdd4b6a6 7323 if (pipe == PIPE_A)
ab3c759a 7324 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7325 0x0df40000);
7326 else
ab3c759a 7327 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7328 0x0df70000);
7329 } else { /* HDMI or VGA */
7330 /* Use bend source */
bdd4b6a6 7331 if (pipe == PIPE_A)
ab3c759a 7332 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7333 0x0df70000);
7334 else
ab3c759a 7335 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7336 0x0df40000);
7337 }
a0c4da24 7338
ab3c759a 7339 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7340 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7341 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7342 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7343 coreclk |= 0x01000000;
ab3c759a 7344 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7345
ab3c759a 7346 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7347 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7348}
7349
d288f65f 7350static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7351 struct intel_crtc_state *pipe_config)
1ae0d137 7352{
d288f65f 7353 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7354 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7355 DPLL_VCO_ENABLE;
7356 if (crtc->pipe != PIPE_A)
d288f65f 7357 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7358
d288f65f
VS		 7359 pipe_config->dpll_hw_state.dpll_md =
7360 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7361}
7362
d288f65f 7363static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7364 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7365{
7366 struct drm_device *dev = crtc->base.dev;
7367 struct drm_i915_private *dev_priv = dev->dev_private;
7368 int pipe = crtc->pipe;
7369 int dpll_reg = DPLL(crtc->pipe);
7370 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7371 u32 loopfilter, tribuf_calcntr;
9d556c99 7372 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7373 u32 dpio_val;
9cbe40c1 7374 int vco;
9d556c99 7375
d288f65f
VS		 7376 bestn = pipe_config->dpll.n;
7377 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7378 bestm1 = pipe_config->dpll.m1;
7379 bestm2 = pipe_config->dpll.m2 >> 22;
7380 bestp1 = pipe_config->dpll.p1;
7381 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7382 vco = pipe_config->dpll.vco;
a945ce7e 7383 dpio_val = 0;
9cbe40c1 7384 loopfilter = 0;
9d556c99
CML		 7385
7386 /*
7387 * Enable Refclk and SSC
7388 */
a11b0703 7389 I915_WRITE(dpll_reg,
d288f65f 7390 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7391
a580516d 7392 mutex_lock(&dev_priv->sb_lock);
9d556c99 7393
9d556c99
CML		 7394 /* p1 and p2 divider */
7395 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7396 5 << DPIO_CHV_S1_DIV_SHIFT |
7397 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7398 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7399 1 << DPIO_CHV_K_DIV_SHIFT);
7400
7401 /* Feedback post-divider - m2 */
7402 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7403
7404 /* Feedback refclk divider - n and m1 */
7405 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7406 DPIO_CHV_M1_DIV_BY_2 |
7407 1 << DPIO_CHV_N_DIV_SHIFT);
7408
7409 /* M2 fraction division */
a945ce7e
VP		 7410 if (bestm2_frac)
7411 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7412
7413 /* M2 fraction division enable */
a945ce7e
VP		 7414 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7415 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7416 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7417 if (bestm2_frac)
7418 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7419 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7420
de3a0fde
VP		 7421 /* Program digital lock detect threshold */
7422 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7423 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7424 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7425 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7426 if (!bestm2_frac)
7427 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7428 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7429
9d556c99 7430 /* Loop filter */
9cbe40c1
VP		 7431 if (vco == 5400000) {
7432 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7433 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7434 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7435 tribuf_calcntr = 0x9;
7436 } else if (vco <= 6200000) {
7437 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7438 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7439 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7440 tribuf_calcntr = 0x9;
7441 } else if (vco <= 6480000) {
7442 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7443 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7444 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7445 tribuf_calcntr = 0x8;
7446 } else {
7447 /* Not supported. Apply the same limits as in the max case */
7448 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7449 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7450 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7451 tribuf_calcntr = 0;
7452 }
9d556c99
CML		 7453 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7454
968040b2 7455 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7456 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7457 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7458 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7459
9d556c99
CML		 7460 /* AFC Recal */
7461 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7462 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7463 DPIO_AFC_RECAL);
7464
a580516d 7465 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7466}
7467
d288f65f
VS		 7468/**
7469 * vlv_force_pll_on - forcibly enable just the PLL
7470 * @dev_priv: i915 private structure
7471 * @pipe: pipe PLL to enable
7472 * @dpll: PLL configuration
7473 *
7474 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7475 * in cases where we need the PLL enabled even when @pipe is not going to
7476 * be enabled.
7477 */
7478void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7479 const struct dpll *dpll)
7480{
7481 struct intel_crtc *crtc =
7482 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7483 struct intel_crtc_state pipe_config = {
a93e255f 7484 .base.crtc = &crtc->base,
d288f65f
VS		 7485 .pixel_multiplier = 1,
7486 .dpll = *dpll,
7487 };
7488
7489 if (IS_CHERRYVIEW(dev)) {
7490 chv_update_pll(crtc, &pipe_config);
7491 chv_prepare_pll(crtc, &pipe_config);
7492 chv_enable_pll(crtc, &pipe_config);
7493 } else {
7494 vlv_update_pll(crtc, &pipe_config);
7495 vlv_prepare_pll(crtc, &pipe_config);
7496 vlv_enable_pll(crtc, &pipe_config);
7497 }
7498}
7499
7500/**
7501 * vlv_force_pll_off - forcibly disable just the PLL
7502 * @dev_priv: i915 private structure
7503 * @pipe: pipe PLL to disable
7504 *
7505 * Disable the PLL for @pipe. To be used in cases where we need
7506 * the PLL enabled even when @pipe is not going to be enabled.
7507 */
7508void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7509{
7510 if (IS_CHERRYVIEW(dev))
7511 chv_disable_pll(to_i915(dev), pipe);
7512 else
7513 vlv_disable_pll(to_i915(dev), pipe);
7514}
7515
f47709a9 7516static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7517 struct intel_crtc_state *crtc_state,
f47709a9 7518 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7519 int num_connectors)
7520{
f47709a9 7521 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7522 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7523 u32 dpll;
7524 bool is_sdvo;
190f68c5 7525 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7526
190f68c5 7527 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7528
a93e255f
ACO		 7529 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7530 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7531
7532 dpll = DPLL_VGA_MODE_DIS;
7533
a93e255f 7534 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7535 dpll |= DPLLB_MODE_LVDS;
7536 else
7537 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7538
ef1b460d 7539 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7540 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7541 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7542 }
198a037f
DV		 7543
7544 if (is_sdvo)
4a33e48d 7545 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7546
190f68c5 7547 if (crtc_state->has_dp_encoder)
4a33e48d 7548 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7549
7550 /* compute bitmask from p1 value */
7551 if (IS_PINEVIEW(dev))
7552 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7553 else {
7554 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7555 if (IS_G4X(dev) && reduced_clock)
7556 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7557 }
7558 switch (clock->p2) {
7559 case 5:
7560 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7561 break;
7562 case 7:
7563 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7564 break;
7565 case 10:
7566 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7567 break;
7568 case 14:
7569 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7570 break;
7571 }
7572 if (INTEL_INFO(dev)->gen >= 4)
7573 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7574
190f68c5 7575 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7576 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7577 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7578 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7579 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7580 else
7581 dpll |= PLL_REF_INPUT_DREFCLK;
7582
7583 dpll |= DPLL_VCO_ENABLE;
190f68c5 7584 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7585
eb1cbe48 7586 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7587 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7588 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7589 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7590 }
7591}
7592
f47709a9 7593static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7594 struct intel_crtc_state *crtc_state,
f47709a9 7595 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7596 int num_connectors)
7597{
f47709a9 7598 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7599 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7600 u32 dpll;
190f68c5 7601 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7602
190f68c5 7603 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7604
eb1cbe48
DV		 7605 dpll = DPLL_VGA_MODE_DIS;
7606
a93e255f 7607 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7608 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7609 } else {
7610 if (clock->p1 == 2)
7611 dpll |= PLL_P1_DIVIDE_BY_TWO;
7612 else
7613 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7614 if (clock->p2 == 4)
7615 dpll |= PLL_P2_DIVIDE_BY_4;
7616 }
7617
a93e255f 7618 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7619 dpll |= DPLL_DVO_2X_MODE;
7620
a93e255f 7621 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7622 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7623 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7624 else
7625 dpll |= PLL_REF_INPUT_DREFCLK;
7626
7627 dpll |= DPLL_VCO_ENABLE;
190f68c5 7628 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7629}
7630
8a654f3b 7631static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7632{
7633 struct drm_device *dev = intel_crtc->base.dev;
7634 struct drm_i915_private *dev_priv = dev->dev_private;
7635 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7636 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7637 struct drm_display_mode *adjusted_mode =
6e3c9717 7638 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7639 uint32_t crtc_vtotal, crtc_vblank_end;
7640 int vsyncshift = 0;
4d8a62ea
DV		 7641
7642 /* We need to be careful not to changed the adjusted mode, for otherwise
7643 * the hw state checker will get angry at the mismatch. */
7644 crtc_vtotal = adjusted_mode->crtc_vtotal;
7645 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7646
609aeaca 7647 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7648 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7649 crtc_vtotal -= 1;
7650 crtc_vblank_end -= 1;
609aeaca 7651
409ee761 7652 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7653 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7654 else
7655 vsyncshift = adjusted_mode->crtc_hsync_start -
7656 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7657 if (vsyncshift < 0)
7658 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7659 }
7660
7661 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7662 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7663
fe2b8f9d 7664 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7665 (adjusted_mode->crtc_hdisplay - 1) |
7666 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7667 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7668 (adjusted_mode->crtc_hblank_start - 1) |
7669 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7670 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7671 (adjusted_mode->crtc_hsync_start - 1) |
7672 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7673
fe2b8f9d 7674 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7675 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7676 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7677 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7678 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7679 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7680 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7681 (adjusted_mode->crtc_vsync_start - 1) |
7682 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7683
b5e508d4
PZ		 7684 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7685 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7686 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7687 * bits. */
7688 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7689 (pipe == PIPE_B || pipe == PIPE_C))
7690 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7691
b0e77b9c
PZ		 7692 /* pipesrc controls the size that is scaled from, which should
7693 * always be the user's requested size.
7694 */
7695 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7696 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7697 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7698}
7699
1bd1bd80 7700static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7701 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7702{
7703 struct drm_device *dev = crtc->base.dev;
7704 struct drm_i915_private *dev_priv = dev->dev_private;
7705 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7706 uint32_t tmp;
7707
7708 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7709 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7710 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7711 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7712 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7713 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7714 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7715 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7716 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7717
7718 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7719 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7720 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7721 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7722 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7723 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7724 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7725 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7726 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7727
7728 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7729 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7730 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7731 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7732 }
7733
7734 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7735 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7736 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7737
2d112de7
ACO		 7738 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7739 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7740}
7741
f6a83288 7742void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7743 struct intel_crtc_state *pipe_config)
babea61d 7744{
2d112de7
ACO		 7745 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7746 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7747 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7748 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7749
2d112de7
ACO		 7750 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7751 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7752 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7753 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7754
2d112de7 7755 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7756
2d112de7
ACO		 7757 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7758 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7759}
7760
84b046f3
DV		 7761static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7762{
7763 struct drm_device *dev = intel_crtc->base.dev;
7764 struct drm_i915_private *dev_priv = dev->dev_private;
7765 uint32_t pipeconf;
7766
9f11a9e4 7767 pipeconf = 0;
84b046f3 7768
b6b5d049
VS		 7769 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7770 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7771 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7772
6e3c9717 7773 if (intel_crtc->config->double_wide)
cf532bb2 7774 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7775
ff9ce46e
DV		 7776 /* only g4x and later have fancy bpc/dither controls */
7777 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7778 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7779 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7780 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7781 PIPECONF_DITHER_TYPE_SP;
84b046f3 7782
6e3c9717 7783 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7784 case 18:
7785 pipeconf |= PIPECONF_6BPC;
7786 break;
7787 case 24:
7788 pipeconf |= PIPECONF_8BPC;
7789 break;
7790 case 30:
7791 pipeconf |= PIPECONF_10BPC;
7792 break;
7793 default:
7794 /* Case prevented by intel_choose_pipe_bpp_dither. */
7795 BUG();
84b046f3
DV		 7796 }
7797 }
7798
7799 if (HAS_PIPE_CXSR(dev)) {
7800 if (intel_crtc->lowfreq_avail) {
7801 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7802 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7803 } else {
7804 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7805 }
7806 }
7807
6e3c9717 7808 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7809 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7810 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7811 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7812 else
7813 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7814 } else
84b046f3
DV		 7815 pipeconf |= PIPECONF_PROGRESSIVE;
7816
6e3c9717 7817 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7818 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7819
84b046f3
DV		 7820 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7821 POSTING_READ(PIPECONF(intel_crtc->pipe));
7822}
7823
190f68c5
ACO		 7824static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7825 struct intel_crtc_state *crtc_state)
79e53945 7826{
c7653199 7827 struct drm_device *dev = crtc->base.dev;
79e53945 7828 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7829 int refclk, num_connectors = 0;
652c393a 7830 intel_clock_t clock, reduced_clock;
a16af721 7831 bool ok, has_reduced_clock = false;
e9fd1c02 7832 bool is_lvds = false, is_dsi = false;
5eddb70b 7833 struct intel_encoder *encoder;
d4906093 7834 const intel_limit_t *limit;
55bb9992 7835 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7836 struct drm_connector *connector;
55bb9992
ACO		 7837 struct drm_connector_state *connector_state;
7838 int i;
79e53945 7839
dd3cd74a
ACO		 7840 memset(&crtc_state->dpll_hw_state, 0,
7841 sizeof(crtc_state->dpll_hw_state));
7842
da3ced29 7843 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7844 if (connector_state->crtc != &crtc->base)
7845 continue;
7846
7847 encoder = to_intel_encoder(connector_state->best_encoder);
7848
5eddb70b 7849 switch (encoder->type) {
79e53945
JB		 7850 case INTEL_OUTPUT_LVDS:
7851 is_lvds = true;
7852 break;
e9fd1c02
JN		 7853 case INTEL_OUTPUT_DSI:
7854 is_dsi = true;
7855 break;
6847d71b
PZ		 7856 default:
7857 break;
79e53945 7858 }
43565a06 7859
c751ce4f 7860 num_connectors++;
79e53945
JB		 7861 }
7862
f2335330 7863 if (is_dsi)
5b18e57c 7864 return 0;
f2335330 7865
190f68c5 7866 if (!crtc_state->clock_set) {
a93e255f 7867 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7868
e9fd1c02
JN		 7869 /*
7870 * Returns a set of divisors for the desired target clock with
7871 * the given refclk, or FALSE. The returned values represent
7872 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7873 * 2) / p1 / p2.
7874 */
a93e255f
ACO		 7875 limit = intel_limit(crtc_state, refclk);
7876 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7877 crtc_state->port_clock,
e9fd1c02 7878 refclk, NULL, &clock);
f2335330 7879 if (!ok) {
e9fd1c02
JN		 7880 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7881 return -EINVAL;
7882 }
79e53945 7883
f2335330
JN		 7884 if (is_lvds && dev_priv->lvds_downclock_avail) {
7885 /*
7886 * Ensure we match the reduced clock's P to the target
7887 * clock. If the clocks don't match, we can't switch
7888 * the display clock by using the FP0/FP1. In such case
7889 * we will disable the LVDS downclock feature.
7890 */
7891 has_reduced_clock =
a93e255f 7892 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7893 dev_priv->lvds_downclock,
7894 refclk, &clock,
7895 &reduced_clock);
7896 }
7897 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7898 crtc_state->dpll.n = clock.n;
7899 crtc_state->dpll.m1 = clock.m1;
7900 crtc_state->dpll.m2 = clock.m2;
7901 crtc_state->dpll.p1 = clock.p1;
7902 crtc_state->dpll.p2 = clock.p2;
f47709a9 7903 }
7026d4ac 7904
e9fd1c02 7905 if (IS_GEN2(dev)) {
190f68c5 7906 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7907 has_reduced_clock ? &reduced_clock : NULL,
7908 num_connectors);
9d556c99 7909 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7910 chv_update_pll(crtc, crtc_state);
e9fd1c02 7911 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7912 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7913 } else {
190f68c5 7914 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7915 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7916 num_connectors);
e9fd1c02 7917 }
79e53945 7918
c8f7a0db 7919 return 0;
f564048e
EA		 7920}
7921
2fa2fe9a 7922static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7923 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7924{
7925 struct drm_device *dev = crtc->base.dev;
7926 struct drm_i915_private *dev_priv = dev->dev_private;
7927 uint32_t tmp;
7928
dc9e7dec
VS		 7929 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7930 return;
7931
2fa2fe9a 7932 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7933 if (!(tmp & PFIT_ENABLE))
7934 return;
2fa2fe9a 7935
06922821 7936 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7937 if (INTEL_INFO(dev)->gen < 4) {
7938 if (crtc->pipe != PIPE_B)
7939 return;
2fa2fe9a
DV		 7940 } else {
7941 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7942 return;
7943 }
7944
06922821 7945 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7946 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7947 if (INTEL_INFO(dev)->gen < 5)
7948 pipe_config->gmch_pfit.lvds_border_bits =
7949 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7950}
7951
acbec814 7952static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7953 struct intel_crtc_state *pipe_config)
acbec814
JB		 7954{
7955 struct drm_device *dev = crtc->base.dev;
7956 struct drm_i915_private *dev_priv = dev->dev_private;
7957 int pipe = pipe_config->cpu_transcoder;
7958 intel_clock_t clock;
7959 u32 mdiv;
662c6ecb 7960 int refclk = 100000;
acbec814 7961
f573de5a
SK		 7962 /* In case of MIPI DPLL will not even be used */
7963 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7964 return;
7965
a580516d 7966 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7967 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7968 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7969
7970 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7971 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7972 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7973 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7974 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7975
f646628b 7976 vlv_clock(refclk, &clock);
acbec814 7977
f646628b
VS		 7978 /* clock.dot is the fast clock */
7979 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7980}
7981
5724dbd1
DL		 7982static void
7983i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7984 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7985{
7986 struct drm_device *dev = crtc->base.dev;
7987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 u32 val, base, offset;
7989 int pipe = crtc->pipe, plane = crtc->plane;
7990 int fourcc, pixel_format;
6761dd31 7991 unsigned int aligned_height;
b113d5ee 7992 struct drm_framebuffer *fb;
1b842c89 7993 struct intel_framebuffer *intel_fb;
1ad292b5 7994
42a7b088
DL		 7995 val = I915_READ(DSPCNTR(plane));
7996 if (!(val & DISPLAY_PLANE_ENABLE))
7997 return;
7998
d9806c9f 7999 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8000 if (!intel_fb) {
1ad292b5
JB		 8001 DRM_DEBUG_KMS("failed to alloc fb\n");
8002 return;
8003 }
8004
1b842c89
DL		 8005 fb = &intel_fb->base;
8006
18c5247e
DV		 8007 if (INTEL_INFO(dev)->gen >= 4) {
8008 if (val & DISPPLANE_TILED) {
49af449b 8009 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8010 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8011 }
8012 }
1ad292b5
JB		 8013
8014 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8015 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8016 fb->pixel_format = fourcc;
8017 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8018
8019 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8020 if (plane_config->tiling)
1ad292b5
JB		 8021 offset = I915_READ(DSPTILEOFF(plane));
8022 else
8023 offset = I915_READ(DSPLINOFF(plane));
8024 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8025 } else {
8026 base = I915_READ(DSPADDR(plane));
8027 }
8028 plane_config->base = base;
8029
8030 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8031 fb->width = ((val >> 16) & 0xfff) + 1;
8032 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8033
8034 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8035 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8036
b113d5ee 8037 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8038 fb->pixel_format,
8039 fb->modifier[0]);
1ad292b5 8040
f37b5c2b 8041 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8042
2844a921
DL		 8043 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8044 pipe_name(pipe), plane, fb->width, fb->height,
8045 fb->bits_per_pixel, base, fb->pitches[0],
8046 plane_config->size);
1ad292b5 8047
2d14030b 8048 plane_config->fb = intel_fb;
1ad292b5
JB		 8049}
8050
70b23a98 8051static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8052 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8053{
8054 struct drm_device *dev = crtc->base.dev;
8055 struct drm_i915_private *dev_priv = dev->dev_private;
8056 int pipe = pipe_config->cpu_transcoder;
8057 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8058 intel_clock_t clock;
8059 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8060 int refclk = 100000;
8061
a580516d 8062 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8063 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8064 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8065 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8066 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8067 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8068
8069 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8070 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8071 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8072 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8073 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8074
8075 chv_clock(refclk, &clock);
8076
8077 /* clock.dot is the fast clock */
8078 pipe_config->port_clock = clock.dot / 5;
8079}
8080
0e8ffe1b 8081static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8082 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8083{
8084 struct drm_device *dev = crtc->base.dev;
8085 struct drm_i915_private *dev_priv = dev->dev_private;
8086 uint32_t tmp;
8087
f458ebbc
DV		 8088 if (!intel_display_power_is_enabled(dev_priv,
8089 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8090 return false;
8091
e143a21c 8092 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8093 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8094
0e8ffe1b
DV		 8095 tmp = I915_READ(PIPECONF(crtc->pipe));
8096 if (!(tmp & PIPECONF_ENABLE))
8097 return false;
8098
42571aef
VS		 8099 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8100 switch (tmp & PIPECONF_BPC_MASK) {
8101 case PIPECONF_6BPC:
8102 pipe_config->pipe_bpp = 18;
8103 break;
8104 case PIPECONF_8BPC:
8105 pipe_config->pipe_bpp = 24;
8106 break;
8107 case PIPECONF_10BPC:
8108 pipe_config->pipe_bpp = 30;
8109 break;
8110 default:
8111 break;
8112 }
8113 }
8114
b5a9fa09
DV		 8115 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8116 pipe_config->limited_color_range = true;
8117
282740f7
VS		 8118 if (INTEL_INFO(dev)->gen < 4)
8119 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8120
1bd1bd80
DV		 8121 intel_get_pipe_timings(crtc, pipe_config);
8122
2fa2fe9a
DV		 8123 i9xx_get_pfit_config(crtc, pipe_config);
8124
6c49f241
DV		 8125 if (INTEL_INFO(dev)->gen >= 4) {
8126 tmp = I915_READ(DPLL_MD(crtc->pipe));
8127 pipe_config->pixel_multiplier =
8128 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8129 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8130 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8131 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8132 tmp = I915_READ(DPLL(crtc->pipe));
8133 pipe_config->pixel_multiplier =
8134 ((tmp & SDVO_MULTIPLIER_MASK)
8135 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8136 } else {
8137 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8138 * port and will be fixed up in the encoder->get_config
8139 * function. */
8140 pipe_config->pixel_multiplier = 1;
8141 }
8bcc2795
DV		 8142 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8143 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8144 /*
8145 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8146 * on 830. Filter it out here so that we don't
8147 * report errors due to that.
8148 */
8149 if (IS_I830(dev))
8150 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8151
8bcc2795
DV		 8152 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8153 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8154 } else {
8155 /* Mask out read-only status bits. */
8156 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8157 DPLL_PORTC_READY_MASK |
8158 DPLL_PORTB_READY_MASK);
8bcc2795 8159 }
6c49f241 8160
70b23a98
VS		 8161 if (IS_CHERRYVIEW(dev))
8162 chv_crtc_clock_get(crtc, pipe_config);
8163 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8164 vlv_crtc_clock_get(crtc, pipe_config);
8165 else
8166 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8167
0e8ffe1b
DV		 8168 return true;
8169}
8170
dde86e2d 8171static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8172{
8173 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8174 struct intel_encoder *encoder;
74cfd7ac 8175 u32 val, final;
13d83a67 8176 bool has_lvds = false;
199e5d79 8177 bool has_cpu_edp = false;
199e5d79 8178 bool has_panel = false;
99eb6a01
KP		 8179 bool has_ck505 = false;
8180 bool can_ssc = false;
13d83a67
JB		 8181
8182 /* We need to take the global config into account */
b2784e15 8183 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8184 switch (encoder->type) {
8185 case INTEL_OUTPUT_LVDS:
8186 has_panel = true;
8187 has_lvds = true;
8188 break;
8189 case INTEL_OUTPUT_EDP:
8190 has_panel = true;
2de6905f 8191 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8192 has_cpu_edp = true;
8193 break;
6847d71b
PZ		 8194 default:
8195 break;
13d83a67
JB		 8196 }
8197 }
8198
99eb6a01 8199 if (HAS_PCH_IBX(dev)) {
41aa3448 8200 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8201 can_ssc = has_ck505;
8202 } else {
8203 has_ck505 = false;
8204 can_ssc = true;
8205 }
8206
2de6905f
ID		 8207 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8208 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8209
8210 /* Ironlake: try to setup display ref clock before DPLL
8211 * enabling. This is only under driver's control after
8212 * PCH B stepping, previous chipset stepping should be
8213 * ignoring this setting.
8214 */
74cfd7ac
CW		 8215 val = I915_READ(PCH_DREF_CONTROL);
8216
8217 /* As we must carefully and slowly disable/enable each source in turn,
8218 * compute the final state we want first and check if we need to
8219 * make any changes at all.
8220 */
8221 final = val;
8222 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8223 if (has_ck505)
8224 final |= DREF_NONSPREAD_CK505_ENABLE;
8225 else
8226 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8227
8228 final &= ~DREF_SSC_SOURCE_MASK;
8229 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8230 final &= ~DREF_SSC1_ENABLE;
8231
8232 if (has_panel) {
8233 final |= DREF_SSC_SOURCE_ENABLE;
8234
8235 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8236 final |= DREF_SSC1_ENABLE;
8237
8238 if (has_cpu_edp) {
8239 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8240 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8241 else
8242 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8243 } else
8244 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8245 } else {
8246 final |= DREF_SSC_SOURCE_DISABLE;
8247 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8248 }
8249
8250 if (final == val)
8251 return;
8252
13d83a67 8253 /* Always enable nonspread source */
74cfd7ac 8254 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8255
99eb6a01 8256 if (has_ck505)
74cfd7ac 8257 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8258 else
74cfd7ac 8259 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8260
199e5d79 8261 if (has_panel) {
74cfd7ac
CW		 8262 val &= ~DREF_SSC_SOURCE_MASK;
8263 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8264
199e5d79 8265 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8266 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8267 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8268 val |= DREF_SSC1_ENABLE;
e77166b5 8269 } else
74cfd7ac 8270 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8271
8272 /* Get SSC going before enabling the outputs */
74cfd7ac 8273 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8274 POSTING_READ(PCH_DREF_CONTROL);
8275 udelay(200);
8276
74cfd7ac 8277 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8278
8279 /* Enable CPU source on CPU attached eDP */
199e5d79 8280 if (has_cpu_edp) {
99eb6a01 8281 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8282 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8283 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8284 } else
74cfd7ac 8285 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8286 } else
74cfd7ac 8287 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8288
74cfd7ac 8289 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8290 POSTING_READ(PCH_DREF_CONTROL);
8291 udelay(200);
8292 } else {
8293 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8294
74cfd7ac 8295 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8296
8297 /* Turn off CPU output */
74cfd7ac 8298 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8299
74cfd7ac 8300 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8301 POSTING_READ(PCH_DREF_CONTROL);
8302 udelay(200);
8303
8304 /* Turn off the SSC source */
74cfd7ac
CW		 8305 val &= ~DREF_SSC_SOURCE_MASK;
8306 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8307
8308 /* Turn off SSC1 */
74cfd7ac 8309 val &= ~DREF_SSC1_ENABLE;
199e5d79 8310
74cfd7ac 8311 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8312 POSTING_READ(PCH_DREF_CONTROL);
8313 udelay(200);
8314 }
74cfd7ac
CW		 8315
8316 BUG_ON(val != final);
13d83a67
JB		 8317}
8318
f31f2d55 8319static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8320{
f31f2d55 8321 uint32_t tmp;
dde86e2d 8322
0ff066a9
PZ		 8323 tmp = I915_READ(SOUTH_CHICKEN2);
8324 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8325 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8326
0ff066a9
PZ		 8327 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8328 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8329 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8330
0ff066a9
PZ		 8331 tmp = I915_READ(SOUTH_CHICKEN2);
8332 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8333 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8334
0ff066a9
PZ		 8335 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8336 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8337 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8338}
8339
8340/* WaMPhyProgramming:hsw */
8341static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8342{
8343 uint32_t tmp;
dde86e2d
PZ		 8344
8345 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8346 tmp &= ~(0xFF << 24);
8347 tmp |= (0x12 << 24);
8348 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8349
dde86e2d
PZ		 8350 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8351 tmp |= (1 << 11);
8352 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8353
8354 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8355 tmp |= (1 << 11);
8356 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8357
dde86e2d
PZ		 8358 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8359 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8360 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8361
8362 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8363 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8364 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8365
0ff066a9
PZ		 8366 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8367 tmp &= ~(7 << 13);
8368 tmp |= (5 << 13);
8369 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8370
0ff066a9
PZ		 8371 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8372 tmp &= ~(7 << 13);
8373 tmp |= (5 << 13);
8374 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8375
8376 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8377 tmp &= ~0xFF;
8378 tmp |= 0x1C;
8379 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8380
8381 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8382 tmp &= ~0xFF;
8383 tmp |= 0x1C;
8384 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8385
8386 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8387 tmp &= ~(0xFF << 16);
8388 tmp |= (0x1C << 16);
8389 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8390
8391 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8392 tmp &= ~(0xFF << 16);
8393 tmp |= (0x1C << 16);
8394 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8395
0ff066a9
PZ		 8396 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8397 tmp |= (1 << 27);
8398 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8399
0ff066a9
PZ		 8400 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8401 tmp |= (1 << 27);
8402 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8403
0ff066a9
PZ		 8404 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8405 tmp &= ~(0xF << 28);
8406 tmp |= (4 << 28);
8407 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8408
0ff066a9
PZ		 8409 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8410 tmp &= ~(0xF << 28);
8411 tmp |= (4 << 28);
8412 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8413}
8414
2fa86a1f
PZ		 8415/* Implements 3 different sequences from BSpec chapter "Display iCLK
8416 * Programming" based on the parameters passed:
8417 * - Sequence to enable CLKOUT_DP
8418 * - Sequence to enable CLKOUT_DP without spread
8419 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8420 */
8421static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8422 bool with_fdi)
f31f2d55
PZ		 8423{
8424 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8425 uint32_t reg, tmp;
8426
8427 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8428 with_spread = true;
8429 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8430 with_fdi, "LP PCH doesn't have FDI\n"))
8431 with_fdi = false;
f31f2d55 8432
a580516d 8433 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8434
8435 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8436 tmp &= ~SBI_SSCCTL_DISABLE;
8437 tmp |= SBI_SSCCTL_PATHALT;
8438 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8439
8440 udelay(24);
8441
2fa86a1f
PZ		 8442 if (with_spread) {
8443 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8444 tmp &= ~SBI_SSCCTL_PATHALT;
8445 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8446
2fa86a1f
PZ		 8447 if (with_fdi) {
8448 lpt_reset_fdi_mphy(dev_priv);
8449 lpt_program_fdi_mphy(dev_priv);
8450 }
8451 }
dde86e2d 8452
2fa86a1f
PZ		 8453 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8454 SBI_GEN0 : SBI_DBUFF0;
8455 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8456 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8457 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8458
a580516d 8459 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8460}
8461
47701c3b
PZ		 8462/* Sequence to disable CLKOUT_DP */
8463static void lpt_disable_clkout_dp(struct drm_device *dev)
8464{
8465 struct drm_i915_private *dev_priv = dev->dev_private;
8466 uint32_t reg, tmp;
8467
a580516d 8468 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8469
8470 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8471 SBI_GEN0 : SBI_DBUFF0;
8472 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8473 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8474 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8475
8476 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8477 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8478 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8479 tmp |= SBI_SSCCTL_PATHALT;
8480 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8481 udelay(32);
8482 }
8483 tmp |= SBI_SSCCTL_DISABLE;
8484 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8485 }
8486
a580516d 8487 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8488}
8489
bf8fa3d3
PZ		 8490static void lpt_init_pch_refclk(struct drm_device *dev)
8491{
bf8fa3d3
PZ		 8492 struct intel_encoder *encoder;
8493 bool has_vga = false;
8494
b2784e15 8495 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8496 switch (encoder->type) {
8497 case INTEL_OUTPUT_ANALOG:
8498 has_vga = true;
8499 break;
6847d71b
PZ		 8500 default:
8501 break;
bf8fa3d3
PZ		 8502 }
8503 }
8504
47701c3b
PZ		 8505 if (has_vga)
8506 lpt_enable_clkout_dp(dev, true, true);
8507 else
8508 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8509}
8510
dde86e2d
PZ		 8511/*
8512 * Initialize reference clocks when the driver loads
8513 */
8514void intel_init_pch_refclk(struct drm_device *dev)
8515{
8516 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8517 ironlake_init_pch_refclk(dev);
8518 else if (HAS_PCH_LPT(dev))
8519 lpt_init_pch_refclk(dev);
8520}
8521
55bb9992 8522static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8523{
55bb9992 8524 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8525 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8526 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8527 struct drm_connector *connector;
55bb9992 8528 struct drm_connector_state *connector_state;
d9d444cb 8529 struct intel_encoder *encoder;
55bb9992 8530 int num_connectors = 0, i;
d9d444cb
JB		 8531 bool is_lvds = false;
8532
da3ced29 8533 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8534 if (connector_state->crtc != crtc_state->base.crtc)
8535 continue;
8536
8537 encoder = to_intel_encoder(connector_state->best_encoder);
8538
d9d444cb
JB		 8539 switch (encoder->type) {
8540 case INTEL_OUTPUT_LVDS:
8541 is_lvds = true;
8542 break;
6847d71b
PZ		 8543 default:
8544 break;
d9d444cb
JB		 8545 }
8546 num_connectors++;
8547 }
8548
8549 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8550 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8551 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8552 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8553 }
8554
8555 return 120000;
8556}
8557
6ff93609 8558static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8559{
c8203565 8560 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8562 int pipe = intel_crtc->pipe;
c8203565
PZ		 8563 uint32_t val;
8564
78114071 8565 val = 0;
c8203565 8566
6e3c9717 8567 switch (intel_crtc->config->pipe_bpp) {
c8203565 8568 case 18:
dfd07d72 8569 val |= PIPECONF_6BPC;
c8203565
PZ		 8570 break;
8571 case 24:
dfd07d72 8572 val |= PIPECONF_8BPC;
c8203565
PZ		 8573 break;
8574 case 30:
dfd07d72 8575 val |= PIPECONF_10BPC;
c8203565
PZ		 8576 break;
8577 case 36:
dfd07d72 8578 val |= PIPECONF_12BPC;
c8203565
PZ		 8579 break;
8580 default:
cc769b62
PZ		 8581 /* Case prevented by intel_choose_pipe_bpp_dither. */
8582 BUG();
c8203565
PZ		 8583 }
8584
6e3c9717 8585 if (intel_crtc->config->dither)
c8203565
PZ		 8586 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8587
6e3c9717 8588 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8589 val |= PIPECONF_INTERLACED_ILK;
8590 else
8591 val |= PIPECONF_PROGRESSIVE;
8592
6e3c9717 8593 if (intel_crtc->config->limited_color_range)
3685a8f3 8594 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8595
c8203565
PZ		 8596 I915_WRITE(PIPECONF(pipe), val);
8597 POSTING_READ(PIPECONF(pipe));
8598}
8599
86d3efce
VS		 8600/*
8601 * Set up the pipe CSC unit.
8602 *
8603 * Currently only full range RGB to limited range RGB conversion
8604 * is supported, but eventually this should handle various
8605 * RGB<->YCbCr scenarios as well.
8606 */
50f3b016 8607static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8608{
8609 struct drm_device *dev = crtc->dev;
8610 struct drm_i915_private *dev_priv = dev->dev_private;
8611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8612 int pipe = intel_crtc->pipe;
8613 uint16_t coeff = 0x7800; /* 1.0 */
8614
8615 /*
8616 * TODO: Check what kind of values actually come out of the pipe
8617 * with these coeff/postoff values and adjust to get the best
8618 * accuracy. Perhaps we even need to take the bpc value into
8619 * consideration.
8620 */
8621
6e3c9717 8622 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8623 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8624
8625 /*
8626 * GY/GU and RY/RU should be the other way around according
8627 * to BSpec, but reality doesn't agree. Just set them up in
8628 * a way that results in the correct picture.
8629 */
8630 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8631 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8632
8633 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8634 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8635
8636 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8637 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8638
8639 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8640 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8641 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8642
8643 if (INTEL_INFO(dev)->gen > 6) {
8644 uint16_t postoff = 0;
8645
6e3c9717 8646 if (intel_crtc->config->limited_color_range)
32cf0cb0 8647 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8648
8649 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8650 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8651 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8652
8653 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8654 } else {
8655 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8656
6e3c9717 8657 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8658 mode |= CSC_BLACK_SCREEN_OFFSET;
8659
8660 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8661 }
8662}
8663
6ff93609 8664static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8665{
756f85cf
PZ		 8666 struct drm_device *dev = crtc->dev;
8667 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8669 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8670 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8671 uint32_t val;
8672
3eff4faa 8673 val = 0;
ee2b0b38 8674
6e3c9717 8675 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8676 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8677
6e3c9717 8678 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8679 val |= PIPECONF_INTERLACED_ILK;
8680 else
8681 val |= PIPECONF_PROGRESSIVE;
8682
702e7a56
PZ		 8683 I915_WRITE(PIPECONF(cpu_transcoder), val);
8684 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8685
8686 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8687 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8688
3cdf122c 8689 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8690 val = 0;
8691
6e3c9717 8692 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8693 case 18:
8694 val |= PIPEMISC_DITHER_6_BPC;
8695 break;
8696 case 24:
8697 val |= PIPEMISC_DITHER_8_BPC;
8698 break;
8699 case 30:
8700 val |= PIPEMISC_DITHER_10_BPC;
8701 break;
8702 case 36:
8703 val |= PIPEMISC_DITHER_12_BPC;
8704 break;
8705 default:
8706 /* Case prevented by pipe_config_set_bpp. */
8707 BUG();
8708 }
8709
6e3c9717 8710 if (intel_crtc->config->dither)
756f85cf
PZ		 8711 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8712
8713 I915_WRITE(PIPEMISC(pipe), val);
8714 }
ee2b0b38
PZ		 8715}
8716
6591c6e4 8717static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8718 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8719 intel_clock_t *clock,
8720 bool *has_reduced_clock,
8721 intel_clock_t *reduced_clock)
8722{
8723 struct drm_device *dev = crtc->dev;
8724 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8725 int refclk;
d4906093 8726 const intel_limit_t *limit;
a16af721 8727 bool ret, is_lvds = false;
79e53945 8728
a93e255f 8729 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8730
55bb9992 8731 refclk = ironlake_get_refclk(crtc_state);
79e53945 8732
d4906093
ML		 8733 /*
8734 * Returns a set of divisors for the desired target clock with the given
8735 * refclk, or FALSE. The returned values represent the clock equation:
8736 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8737 */
a93e255f
ACO		 8738 limit = intel_limit(crtc_state, refclk);
8739 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8740 crtc_state->port_clock,
ee9300bb 8741 refclk, NULL, clock);
6591c6e4
PZ		 8742 if (!ret)
8743 return false;
cda4b7d3 8744
ddc9003c 8745 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8746 /*
8747 * Ensure we match the reduced clock's P to the target clock.
8748 * If the clocks don't match, we can't switch the display clock
8749 * by using the FP0/FP1. In such case we will disable the LVDS
8750 * downclock feature.
8751 */
ee9300bb 8752 *has_reduced_clock =
a93e255f 8753 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8754 dev_priv->lvds_downclock,
8755 refclk, clock,
8756 reduced_clock);
652c393a 8757 }
61e9653f 8758
6591c6e4
PZ		 8759 return true;
8760}
8761
d4b1931c
PZ		 8762int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8763{
8764 /*
8765 * Account for spread spectrum to avoid
8766 * oversubscribing the link. Max center spread
8767 * is 2.5%; use 5% for safety's sake.
8768 */
8769 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8770 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8771}
8772
7429e9d4 8773static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8774{
7429e9d4 8775 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8776}
8777
de13a2e3 8778static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8779 struct intel_crtc_state *crtc_state,
7429e9d4 8780 u32 *fp,
9a7c7890 8781 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8782{
de13a2e3 8783 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8784 struct drm_device *dev = crtc->dev;
8785 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8786 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8787 struct drm_connector *connector;
55bb9992
ACO		 8788 struct drm_connector_state *connector_state;
8789 struct intel_encoder *encoder;
de13a2e3 8790 uint32_t dpll;
55bb9992 8791 int factor, num_connectors = 0, i;
09ede541 8792 bool is_lvds = false, is_sdvo = false;
79e53945 8793
da3ced29 8794 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8795 if (connector_state->crtc != crtc_state->base.crtc)
8796 continue;
8797
8798 encoder = to_intel_encoder(connector_state->best_encoder);
8799
8800 switch (encoder->type) {
79e53945
JB		 8801 case INTEL_OUTPUT_LVDS:
8802 is_lvds = true;
8803 break;
8804 case INTEL_OUTPUT_SDVO:
7d57382e 8805 case INTEL_OUTPUT_HDMI:
79e53945 8806 is_sdvo = true;
79e53945 8807 break;
6847d71b
PZ		 8808 default:
8809 break;
79e53945 8810 }
43565a06 8811
c751ce4f 8812 num_connectors++;
79e53945 8813 }
79e53945 8814
c1858123 8815 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8816 factor = 21;
8817 if (is_lvds) {
8818 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8819 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8820 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8821 factor = 25;
190f68c5 8822 } else if (crtc_state->sdvo_tv_clock)
8febb297 8823 factor = 20;
c1858123 8824
190f68c5 8825 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8826 *fp |= FP_CB_TUNE;
2c07245f 8827
9a7c7890
DV		 8828 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8829 *fp2 |= FP_CB_TUNE;
8830
5eddb70b 8831 dpll = 0;
2c07245f 8832
a07d6787
EA		 8833 if (is_lvds)
8834 dpll |= DPLLB_MODE_LVDS;
8835 else
8836 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8837
190f68c5 8838 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8839 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8840
8841 if (is_sdvo)
4a33e48d 8842 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8843 if (crtc_state->has_dp_encoder)
4a33e48d 8844 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8845
a07d6787 8846 /* compute bitmask from p1 value */
190f68c5 8847 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8848 /* also FPA1 */
190f68c5 8849 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8850
190f68c5 8851 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8852 case 5:
8853 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8854 break;
8855 case 7:
8856 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8857 break;
8858 case 10:
8859 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8860 break;
8861 case 14:
8862 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8863 break;
79e53945
JB		 8864 }
8865
b4c09f3b 8866 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8867 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8868 else
8869 dpll |= PLL_REF_INPUT_DREFCLK;
8870
959e16d6 8871 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8872}
8873
190f68c5
ACO		 8874static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8875 struct intel_crtc_state *crtc_state)
de13a2e3 8876{
c7653199 8877 struct drm_device *dev = crtc->base.dev;
de13a2e3 8878 intel_clock_t clock, reduced_clock;
cbbab5bd 8879 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8880 bool ok, has_reduced_clock = false;
8b47047b 8881 bool is_lvds = false;
e2b78267 8882 struct intel_shared_dpll *pll;
de13a2e3 8883
dd3cd74a
ACO		 8884 memset(&crtc_state->dpll_hw_state, 0,
8885 sizeof(crtc_state->dpll_hw_state));
8886
409ee761 8887 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8888
5dc5298b
PZ		 8889 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8890 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8891
190f68c5 8892 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8893 &has_reduced_clock, &reduced_clock);
190f68c5 8894 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8895 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8896 return -EINVAL;
79e53945 8897 }
f47709a9 8898 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8899 if (!crtc_state->clock_set) {
8900 crtc_state->dpll.n = clock.n;
8901 crtc_state->dpll.m1 = clock.m1;
8902 crtc_state->dpll.m2 = clock.m2;
8903 crtc_state->dpll.p1 = clock.p1;
8904 crtc_state->dpll.p2 = clock.p2;
f47709a9 8905 }
79e53945 8906
5dc5298b 8907 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8908 if (crtc_state->has_pch_encoder) {
8909 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8910 if (has_reduced_clock)
7429e9d4 8911 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8912
190f68c5 8913 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8914 &fp, &reduced_clock,
8915 has_reduced_clock ? &fp2 : NULL);
8916
190f68c5
ACO		 8917 crtc_state->dpll_hw_state.dpll = dpll;
8918 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8919 if (has_reduced_clock)
190f68c5 8920 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8921 else
190f68c5 8922 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8923
190f68c5 8924 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8925 if (pll == NULL) {
84f44ce7 8926 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8927 pipe_name(crtc->pipe));
4b645f14
JB		 8928 return -EINVAL;
8929 }
3fb37703 8930 }
79e53945 8931
ab585dea 8932 if (is_lvds && has_reduced_clock)
c7653199 8933 crtc->lowfreq_avail = true;
bcd644e0 8934 else
c7653199 8935 crtc->lowfreq_avail = false;
e2b78267 8936
c8f7a0db 8937 return 0;
79e53945
JB		 8938}
8939
eb14cb74
VS		 8940static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8941 struct intel_link_m_n *m_n)
8942{
8943 struct drm_device *dev = crtc->base.dev;
8944 struct drm_i915_private *dev_priv = dev->dev_private;
8945 enum pipe pipe = crtc->pipe;
8946
8947 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8948 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8949 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8950 & ~TU_SIZE_MASK;
8951 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8952 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8953 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8954}
8955
8956static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8957 enum transcoder transcoder,
b95af8be
VK		 8958 struct intel_link_m_n *m_n,
8959 struct intel_link_m_n *m2_n2)
72419203
DV		 8960{
8961 struct drm_device *dev = crtc->base.dev;
8962 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8963 enum pipe pipe = crtc->pipe;
72419203 8964
eb14cb74
VS		 8965 if (INTEL_INFO(dev)->gen >= 5) {
8966 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8967 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8968 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8969 & ~TU_SIZE_MASK;
8970 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8971 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8972 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8973 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8974 * gen < 8) and if DRRS is supported (to make sure the
8975 * registers are not unnecessarily read).
8976 */
8977 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8978 crtc->config->has_drrs) {
b95af8be
VK		 8979 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8980 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8981 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8982 & ~TU_SIZE_MASK;
8983 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8984 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8985 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8986 }
eb14cb74
VS		 8987 } else {
8988 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8989 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8990 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8991 & ~TU_SIZE_MASK;
8992 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8993 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8994 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8995 }
8996}
8997
8998void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8999 struct intel_crtc_state *pipe_config)
eb14cb74 9000{
681a8504 9001 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9002 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9003 else
9004 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9005 &pipe_config->dp_m_n,
9006 &pipe_config->dp_m2_n2);
eb14cb74 9007}
72419203 9008
eb14cb74 9009static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9010 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9011{
9012 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9013 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9014}
9015
bd2e244f 9016static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9017 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9018{
9019 struct drm_device *dev = crtc->base.dev;
9020 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9021 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9022 uint32_t ps_ctrl = 0;
9023 int id = -1;
9024 int i;
bd2e244f 9025
a1b2278e
CK		 9026 /* find scaler attached to this pipe */
9027 for (i = 0; i < crtc->num_scalers; i++) {
9028 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9029 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9030 id = i;
9031 pipe_config->pch_pfit.enabled = true;
9032 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9033 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9034 break;
9035 }
9036 }
bd2e244f 9037
a1b2278e
CK		 9038 scaler_state->scaler_id = id;
9039 if (id >= 0) {
9040 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9041 } else {
9042 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9043 }
9044}
9045
5724dbd1
DL		 9046static void
9047skylake_get_initial_plane_config(struct intel_crtc *crtc,
9048 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9049{
9050 struct drm_device *dev = crtc->base.dev;
9051 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9052 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9053 int pipe = crtc->pipe;
9054 int fourcc, pixel_format;
6761dd31 9055 unsigned int aligned_height;
bc8d7dff 9056 struct drm_framebuffer *fb;
1b842c89 9057 struct intel_framebuffer *intel_fb;
bc8d7dff 9058
d9806c9f 9059 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9060 if (!intel_fb) {
bc8d7dff
DL		 9061 DRM_DEBUG_KMS("failed to alloc fb\n");
9062 return;
9063 }
9064
1b842c89
DL		 9065 fb = &intel_fb->base;
9066
bc8d7dff 9067 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9068 if (!(val & PLANE_CTL_ENABLE))
9069 goto error;
9070
bc8d7dff
DL		 9071 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9072 fourcc = skl_format_to_fourcc(pixel_format,
9073 val & PLANE_CTL_ORDER_RGBX,
9074 val & PLANE_CTL_ALPHA_MASK);
9075 fb->pixel_format = fourcc;
9076 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9077
40f46283
DL		 9078 tiling = val & PLANE_CTL_TILED_MASK;
9079 switch (tiling) {
9080 case PLANE_CTL_TILED_LINEAR:
9081 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9082 break;
9083 case PLANE_CTL_TILED_X:
9084 plane_config->tiling = I915_TILING_X;
9085 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9086 break;
9087 case PLANE_CTL_TILED_Y:
9088 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9089 break;
9090 case PLANE_CTL_TILED_YF:
9091 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9092 break;
9093 default:
9094 MISSING_CASE(tiling);
9095 goto error;
9096 }
9097
bc8d7dff
DL		 9098 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9099 plane_config->base = base;
9100
9101 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9102
9103 val = I915_READ(PLANE_SIZE(pipe, 0));
9104 fb->height = ((val >> 16) & 0xfff) + 1;
9105 fb->width = ((val >> 0) & 0x1fff) + 1;
9106
9107 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9108 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9109 fb->pixel_format);
bc8d7dff
DL		 9110 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9111
9112 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9113 fb->pixel_format,
9114 fb->modifier[0]);
bc8d7dff 9115
f37b5c2b 9116 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9117
9118 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9119 pipe_name(pipe), fb->width, fb->height,
9120 fb->bits_per_pixel, base, fb->pitches[0],
9121 plane_config->size);
9122
2d14030b 9123 plane_config->fb = intel_fb;
bc8d7dff
DL		 9124 return;
9125
9126error:
9127 kfree(fb);
9128}
9129
2fa2fe9a 9130static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9131 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9132{
9133 struct drm_device *dev = crtc->base.dev;
9134 struct drm_i915_private *dev_priv = dev->dev_private;
9135 uint32_t tmp;
9136
9137 tmp = I915_READ(PF_CTL(crtc->pipe));
9138
9139 if (tmp & PF_ENABLE) {
fd4daa9c 9140 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9141 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9142 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9143
9144 /* We currently do not free assignements of panel fitters on
9145 * ivb/hsw (since we don't use the higher upscaling modes which
9146 * differentiates them) so just WARN about this case for now. */
9147 if (IS_GEN7(dev)) {
9148 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9149 PF_PIPE_SEL_IVB(crtc->pipe));
9150 }
2fa2fe9a 9151 }
79e53945
JB		 9152}
9153
5724dbd1
DL		 9154static void
9155ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9156 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9157{
9158 struct drm_device *dev = crtc->base.dev;
9159 struct drm_i915_private *dev_priv = dev->dev_private;
9160 u32 val, base, offset;
aeee5a49 9161 int pipe = crtc->pipe;
4c6baa59 9162 int fourcc, pixel_format;
6761dd31 9163 unsigned int aligned_height;
b113d5ee 9164 struct drm_framebuffer *fb;
1b842c89 9165 struct intel_framebuffer *intel_fb;
4c6baa59 9166
42a7b088
DL		 9167 val = I915_READ(DSPCNTR(pipe));
9168 if (!(val & DISPLAY_PLANE_ENABLE))
9169 return;
9170
d9806c9f 9171 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9172 if (!intel_fb) {
4c6baa59
JB		 9173 DRM_DEBUG_KMS("failed to alloc fb\n");
9174 return;
9175 }
9176
1b842c89
DL		 9177 fb = &intel_fb->base;
9178
18c5247e
DV		 9179 if (INTEL_INFO(dev)->gen >= 4) {
9180 if (val & DISPPLANE_TILED) {
49af449b 9181 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9182 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9183 }
9184 }
4c6baa59
JB		 9185
9186 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9187 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9188 fb->pixel_format = fourcc;
9189 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9190
aeee5a49 9191 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9192 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9193 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9194 } else {
49af449b 9195 if (plane_config->tiling)
aeee5a49 9196 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9197 else
aeee5a49 9198 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9199 }
9200 plane_config->base = base;
9201
9202 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9203 fb->width = ((val >> 16) & 0xfff) + 1;
9204 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9205
9206 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9207 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9208
b113d5ee 9209 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9210 fb->pixel_format,
9211 fb->modifier[0]);
4c6baa59 9212
f37b5c2b 9213 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9214
2844a921
DL		 9215 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9216 pipe_name(pipe), fb->width, fb->height,
9217 fb->bits_per_pixel, base, fb->pitches[0],
9218 plane_config->size);
b113d5ee 9219
2d14030b 9220 plane_config->fb = intel_fb;
4c6baa59
JB		 9221}
9222
0e8ffe1b 9223static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9224 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9225{
9226 struct drm_device *dev = crtc->base.dev;
9227 struct drm_i915_private *dev_priv = dev->dev_private;
9228 uint32_t tmp;
9229
f458ebbc
DV		 9230 if (!intel_display_power_is_enabled(dev_priv,
9231 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9232 return false;
9233
e143a21c 9234 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9235 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9236
0e8ffe1b
DV		 9237 tmp = I915_READ(PIPECONF(crtc->pipe));
9238 if (!(tmp & PIPECONF_ENABLE))
9239 return false;
9240
42571aef
VS		 9241 switch (tmp & PIPECONF_BPC_MASK) {
9242 case PIPECONF_6BPC:
9243 pipe_config->pipe_bpp = 18;
9244 break;
9245 case PIPECONF_8BPC:
9246 pipe_config->pipe_bpp = 24;
9247 break;
9248 case PIPECONF_10BPC:
9249 pipe_config->pipe_bpp = 30;
9250 break;
9251 case PIPECONF_12BPC:
9252 pipe_config->pipe_bpp = 36;
9253 break;
9254 default:
9255 break;
9256 }
9257
b5a9fa09
DV		 9258 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9259 pipe_config->limited_color_range = true;
9260
ab9412ba 9261 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9262 struct intel_shared_dpll *pll;
9263
88adfff1
DV		 9264 pipe_config->has_pch_encoder = true;
9265
627eb5a3
DV		 9266 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9267 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9268 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9269
9270 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9271
c0d43d62 9272 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9273 pipe_config->shared_dpll =
9274 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9275 } else {
9276 tmp = I915_READ(PCH_DPLL_SEL);
9277 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9278 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9279 else
9280 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9281 }
66e985c0
DV		 9282
9283 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9284
9285 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9286 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9287
9288 tmp = pipe_config->dpll_hw_state.dpll;
9289 pipe_config->pixel_multiplier =
9290 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9291 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9292
9293 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9294 } else {
9295 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9296 }
9297
1bd1bd80
DV		 9298 intel_get_pipe_timings(crtc, pipe_config);
9299
2fa2fe9a
DV		 9300 ironlake_get_pfit_config(crtc, pipe_config);
9301
0e8ffe1b
DV		 9302 return true;
9303}
9304
be256dc7
PZ		 9305static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9306{
9307 struct drm_device *dev = dev_priv->dev;
be256dc7 9308 struct intel_crtc *crtc;
be256dc7 9309
d3fcc808 9310 for_each_intel_crtc(dev, crtc)
e2c719b7 9311 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9312 pipe_name(crtc->pipe));
9313
e2c719b7
RC		 9314 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9315 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9316 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9317 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9318 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9319 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9320 "CPU PWM1 enabled\n");
c5107b87 9321 if (IS_HASWELL(dev))
e2c719b7 9322 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9323 "CPU PWM2 enabled\n");
e2c719b7 9324 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9325 "PCH PWM1 enabled\n");
e2c719b7 9326 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9327 "Utility pin enabled\n");
e2c719b7 9328 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9329
9926ada1
PZ		 9330 /*
9331 * In theory we can still leave IRQs enabled, as long as only the HPD
9332 * interrupts remain enabled. We used to check for that, but since it's
9333 * gen-specific and since we only disable LCPLL after we fully disable
9334 * the interrupts, the check below should be enough.
9335 */
e2c719b7 9336 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9337}
9338
9ccd5aeb
PZ		 9339static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9340{
9341 struct drm_device *dev = dev_priv->dev;
9342
9343 if (IS_HASWELL(dev))
9344 return I915_READ(D_COMP_HSW);
9345 else
9346 return I915_READ(D_COMP_BDW);
9347}
9348
3c4c9b81
PZ		 9349static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9350{
9351 struct drm_device *dev = dev_priv->dev;
9352
9353 if (IS_HASWELL(dev)) {
9354 mutex_lock(&dev_priv->rps.hw_lock);
9355 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9356 val))
f475dadf 9357 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9358 mutex_unlock(&dev_priv->rps.hw_lock);
9359 } else {
9ccd5aeb
PZ		 9360 I915_WRITE(D_COMP_BDW, val);
9361 POSTING_READ(D_COMP_BDW);
3c4c9b81 9362 }
be256dc7
PZ		 9363}
9364
9365/*
9366 * This function implements pieces of two sequences from BSpec:
9367 * - Sequence for display software to disable LCPLL
9368 * - Sequence for display software to allow package C8+
9369 * The steps implemented here are just the steps that actually touch the LCPLL
9370 * register. Callers should take care of disabling all the display engine
9371 * functions, doing the mode unset, fixing interrupts, etc.
9372 */
6ff58d53
PZ		 9373static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9374 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9375{
9376 uint32_t val;
9377
9378 assert_can_disable_lcpll(dev_priv);
9379
9380 val = I915_READ(LCPLL_CTL);
9381
9382 if (switch_to_fclk) {
9383 val |= LCPLL_CD_SOURCE_FCLK;
9384 I915_WRITE(LCPLL_CTL, val);
9385
9386 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9387 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9388 DRM_ERROR("Switching to FCLK failed\n");
9389
9390 val = I915_READ(LCPLL_CTL);
9391 }
9392
9393 val |= LCPLL_PLL_DISABLE;
9394 I915_WRITE(LCPLL_CTL, val);
9395 POSTING_READ(LCPLL_CTL);
9396
9397 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9398 DRM_ERROR("LCPLL still locked\n");
9399
9ccd5aeb 9400 val = hsw_read_dcomp(dev_priv);
be256dc7 9401 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9402 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9403 ndelay(100);
9404
9ccd5aeb
PZ		 9405 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9406 1))
be256dc7
PZ		 9407 DRM_ERROR("D_COMP RCOMP still in progress\n");
9408
9409 if (allow_power_down) {
9410 val = I915_READ(LCPLL_CTL);
9411 val |= LCPLL_POWER_DOWN_ALLOW;
9412 I915_WRITE(LCPLL_CTL, val);
9413 POSTING_READ(LCPLL_CTL);
9414 }
9415}
9416
9417/*
9418 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9419 * source.
9420 */
6ff58d53 9421static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9422{
9423 uint32_t val;
9424
9425 val = I915_READ(LCPLL_CTL);
9426
9427 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9428 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9429 return;
9430
a8a8bd54
PZ		 9431 /*
9432 * Make sure we're not on PC8 state before disabling PC8, otherwise
9433 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9434 */
59bad947 9435 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9436
be256dc7
PZ		 9437 if (val & LCPLL_POWER_DOWN_ALLOW) {
9438 val &= ~LCPLL_POWER_DOWN_ALLOW;
9439 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9440 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9441 }
9442
9ccd5aeb 9443 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9444 val |= D_COMP_COMP_FORCE;
9445 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9446 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9447
9448 val = I915_READ(LCPLL_CTL);
9449 val &= ~LCPLL_PLL_DISABLE;
9450 I915_WRITE(LCPLL_CTL, val);
9451
9452 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9453 DRM_ERROR("LCPLL not locked yet\n");
9454
9455 if (val & LCPLL_CD_SOURCE_FCLK) {
9456 val = I915_READ(LCPLL_CTL);
9457 val &= ~LCPLL_CD_SOURCE_FCLK;
9458 I915_WRITE(LCPLL_CTL, val);
9459
9460 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9461 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9462 DRM_ERROR("Switching back to LCPLL failed\n");
9463 }
215733fa 9464
59bad947 9465 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9466 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9467}
9468
765dab67
PZ		 9469/*
9470 * Package states C8 and deeper are really deep PC states that can only be
9471 * reached when all the devices on the system allow it, so even if the graphics
9472 * device allows PC8+, it doesn't mean the system will actually get to these
9473 * states. Our driver only allows PC8+ when going into runtime PM.
9474 *
9475 * The requirements for PC8+ are that all the outputs are disabled, the power
9476 * well is disabled and most interrupts are disabled, and these are also
9477 * requirements for runtime PM. When these conditions are met, we manually do
9478 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9479 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9480 * hang the machine.
9481 *
9482 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9483 * the state of some registers, so when we come back from PC8+ we need to
9484 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9485 * need to take care of the registers kept by RC6. Notice that this happens even
9486 * if we don't put the device in PCI D3 state (which is what currently happens
9487 * because of the runtime PM support).
9488 *
9489 * For more, read "Display Sequences for Package C8" on the hardware
9490 * documentation.
9491 */
a14cb6fc 9492void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9493{
c67a470b
PZ		 9494 struct drm_device *dev = dev_priv->dev;
9495 uint32_t val;
9496
c67a470b
PZ		 9497 DRM_DEBUG_KMS("Enabling package C8+\n");
9498
c67a470b
PZ		 9499 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9500 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9501 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9502 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9503 }
9504
9505 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9506 hsw_disable_lcpll(dev_priv, true, true);
9507}
9508
a14cb6fc 9509void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9510{
9511 struct drm_device *dev = dev_priv->dev;
9512 uint32_t val;
9513
c67a470b
PZ		 9514 DRM_DEBUG_KMS("Disabling package C8+\n");
9515
9516 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9517 lpt_init_pch_refclk(dev);
9518
9519 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9520 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9521 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9522 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9523 }
9524
9525 intel_prepare_ddi(dev);
c67a470b
PZ		 9526}
9527
a821fc46 9528static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9529{
a821fc46 9530 struct drm_device *dev = old_state->dev;
f8437dd1 9531 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9532 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9533 int req_cdclk;
9534
9535 /* see the comment in valleyview_modeset_global_resources */
9536 if (WARN_ON(max_pixclk < 0))
9537 return;
9538
9539 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9540
9541 if (req_cdclk != dev_priv->cdclk_freq)
9542 broxton_set_cdclk(dev, req_cdclk);
9543}
9544
b432e5cf
VS		 9545/* compute the max rate for new configuration */
9546static int ilk_max_pixel_rate(struct drm_i915_private *dev_priv)
9547{
9548 struct drm_device *dev = dev_priv->dev;
9549 struct intel_crtc *intel_crtc;
9550 struct drm_crtc *crtc;
9551 int max_pixel_rate = 0;
9552 int pixel_rate;
9553
9554 for_each_crtc(dev, crtc) {
9555 if (!crtc->state->enable)
9556 continue;
9557
9558 intel_crtc = to_intel_crtc(crtc);
9559 pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
9560
9561 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9562 if (IS_BROADWELL(dev) && intel_crtc->config->ips_enabled)
9563 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9564
9565 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9566 }
9567
9568 return max_pixel_rate;
9569}
9570
9571static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9572{
9573 struct drm_i915_private *dev_priv = dev->dev_private;
9574 uint32_t val, data;
9575 int ret;
9576
9577 if (WARN((I915_READ(LCPLL_CTL) &
9578 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9579 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9580 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9581 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9582 "trying to change cdclk frequency with cdclk not enabled\n"))
9583 return;
9584
9585 mutex_lock(&dev_priv->rps.hw_lock);
9586 ret = sandybridge_pcode_write(dev_priv,
9587 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9588 mutex_unlock(&dev_priv->rps.hw_lock);
9589 if (ret) {
9590 DRM_ERROR("failed to inform pcode about cdclk change\n");
9591 return;
9592 }
9593
9594 val = I915_READ(LCPLL_CTL);
9595 val |= LCPLL_CD_SOURCE_FCLK;
9596 I915_WRITE(LCPLL_CTL, val);
9597
9598 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9599 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9600 DRM_ERROR("Switching to FCLK failed\n");
9601
9602 val = I915_READ(LCPLL_CTL);
9603 val &= ~LCPLL_CLK_FREQ_MASK;
9604
9605 switch (cdclk) {
9606 case 450000:
9607 val |= LCPLL_CLK_FREQ_450;
9608 data = 0;
9609 break;
9610 case 540000:
9611 val |= LCPLL_CLK_FREQ_54O_BDW;
9612 data = 1;
9613 break;
9614 case 337500:
9615 val |= LCPLL_CLK_FREQ_337_5_BDW;
9616 data = 2;
9617 break;
9618 case 675000:
9619 val |= LCPLL_CLK_FREQ_675_BDW;
9620 data = 3;
9621 break;
9622 default:
9623 WARN(1, "invalid cdclk frequency\n");
9624 return;
9625 }
9626
9627 I915_WRITE(LCPLL_CTL, val);
9628
9629 val = I915_READ(LCPLL_CTL);
9630 val &= ~LCPLL_CD_SOURCE_FCLK;
9631 I915_WRITE(LCPLL_CTL, val);
9632
9633 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9634 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9635 DRM_ERROR("Switching back to LCPLL failed\n");
9636
9637 mutex_lock(&dev_priv->rps.hw_lock);
9638 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9639 mutex_unlock(&dev_priv->rps.hw_lock);
9640
9641 intel_update_cdclk(dev);
9642
9643 WARN(cdclk != dev_priv->cdclk_freq,
9644 "cdclk requested %d kHz but got %d kHz\n",
9645 cdclk, dev_priv->cdclk_freq);
9646}
9647
9648static int broadwell_calc_cdclk(struct drm_i915_private *dev_priv,
9649 int max_pixel_rate)
9650{
9651 int cdclk;
9652
9653 /*
9654 * FIXME should also account for plane ratio
9655 * once 64bpp pixel formats are supported.
9656 */
9657 if (max_pixel_rate > 540000)
9658 cdclk = 675000;
9659 else if (max_pixel_rate > 450000)
9660 cdclk = 540000;
9661 else if (max_pixel_rate > 337500)
9662 cdclk = 450000;
9663 else
9664 cdclk = 337500;
9665
9666 /*
9667 * FIXME move the cdclk caclulation to
9668 * compute_config() so we can fail gracegully.
9669 */
9670 if (cdclk > dev_priv->max_cdclk_freq) {
9671 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9672 cdclk, dev_priv->max_cdclk_freq);
9673 cdclk = dev_priv->max_cdclk_freq;
9674 }
9675
9676 return cdclk;
9677}
9678
9679static int broadwell_modeset_global_pipes(struct drm_atomic_state *state)
9680{
9681 struct drm_i915_private *dev_priv = to_i915(state->dev);
9682 struct drm_crtc *crtc;
9683 struct drm_crtc_state *crtc_state;
9684 int max_pixclk = ilk_max_pixel_rate(dev_priv);
9685 int cdclk, i;
9686
9687 cdclk = broadwell_calc_cdclk(dev_priv, max_pixclk);
9688
9689 if (cdclk == dev_priv->cdclk_freq)
9690 return 0;
9691
9692 /* add all active pipes to the state */
9693 for_each_crtc(state->dev, crtc) {
9694 if (!crtc->state->enable)
9695 continue;
9696
9697 crtc_state = drm_atomic_get_crtc_state(state, crtc);
9698 if (IS_ERR(crtc_state))
9699 return PTR_ERR(crtc_state);
9700 }
9701
9702 /* disable/enable all currently active pipes while we change cdclk */
9703 for_each_crtc_in_state(state, crtc, crtc_state, i)
9704 if (crtc_state->enable)
9705 crtc_state->mode_changed = true;
9706
9707 return 0;
9708}
9709
9710static void broadwell_modeset_global_resources(struct drm_atomic_state *state)
9711{
9712 struct drm_device *dev = state->dev;
9713 struct drm_i915_private *dev_priv = dev->dev_private;
9714 int max_pixel_rate = ilk_max_pixel_rate(dev_priv);
9715 int req_cdclk = broadwell_calc_cdclk(dev_priv, max_pixel_rate);
9716
9717 if (req_cdclk != dev_priv->cdclk_freq)
9718 broadwell_set_cdclk(dev, req_cdclk);
9719}
9720
190f68c5
ACO		 9721static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9722 struct intel_crtc_state *crtc_state)
09b4ddf9 9723{
190f68c5 9724 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9725 return -EINVAL;
716c2e55 9726
c7653199 9727 crtc->lowfreq_avail = false;
644cef34 9728
c8f7a0db 9729 return 0;
79e53945
JB		 9730}
9731
3760b59c
S		 9732static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9733 enum port port,
9734 struct intel_crtc_state *pipe_config)
9735{
9736 switch (port) {
9737 case PORT_A:
9738 pipe_config->ddi_pll_sel = SKL_DPLL0;
9739 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9740 break;
9741 case PORT_B:
9742 pipe_config->ddi_pll_sel = SKL_DPLL1;
9743 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9744 break;
9745 case PORT_C:
9746 pipe_config->ddi_pll_sel = SKL_DPLL2;
9747 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9748 break;
9749 default:
9750 DRM_ERROR("Incorrect port type\n");
9751 }
9752}
9753
96b7dfb7
S		 9754static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9755 enum port port,
5cec258b 9756 struct intel_crtc_state *pipe_config)
96b7dfb7 9757{
3148ade7 9758 u32 temp, dpll_ctl1;
96b7dfb7
S		 9759
9760 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9761 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9762
9763 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9764 case SKL_DPLL0:
9765 /*
9766 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9767 * of the shared DPLL framework and thus needs to be read out
9768 * separately
9769 */
9770 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9771 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9772 break;
96b7dfb7
S		 9773 case SKL_DPLL1:
9774 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9775 break;
9776 case SKL_DPLL2:
9777 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9778 break;
9779 case SKL_DPLL3:
9780 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9781 break;
96b7dfb7
S		 9782 }
9783}
9784
7d2c8175
DL		 9785static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9786 enum port port,
5cec258b 9787 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9788{
9789 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9790
9791 switch (pipe_config->ddi_pll_sel) {
9792 case PORT_CLK_SEL_WRPLL1:
9793 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9794 break;
9795 case PORT_CLK_SEL_WRPLL2:
9796 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9797 break;
9798 }
9799}
9800
26804afd 9801static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9802 struct intel_crtc_state *pipe_config)
26804afd
DV		 9803{
9804 struct drm_device *dev = crtc->base.dev;
9805 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9806 struct intel_shared_dpll *pll;
26804afd
DV		 9807 enum port port;
9808 uint32_t tmp;
9809
9810 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9811
9812 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9813
96b7dfb7
S		 9814 if (IS_SKYLAKE(dev))
9815 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9816 else if (IS_BROXTON(dev))
9817 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9818 else
9819 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9820
d452c5b6
DV		 9821 if (pipe_config->shared_dpll >= 0) {
9822 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9823
9824 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9825 &pipe_config->dpll_hw_state));
9826 }
9827
26804afd
DV		 9828 /*
9829 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9830 * DDI E. So just check whether this pipe is wired to DDI E and whether
9831 * the PCH transcoder is on.
9832 */
ca370455
DL		 9833 if (INTEL_INFO(dev)->gen < 9 &&
9834 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9835 pipe_config->has_pch_encoder = true;
9836
9837 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9838 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9839 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9840
9841 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9842 }
9843}
9844
0e8ffe1b 9845static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9846 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9847{
9848 struct drm_device *dev = crtc->base.dev;
9849 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9850 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9851 uint32_t tmp;
9852
f458ebbc 9853 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9854 POWER_DOMAIN_PIPE(crtc->pipe)))
9855 return false;
9856
e143a21c 9857 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9858 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9859
eccb140b
DV		 9860 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9861 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9862 enum pipe trans_edp_pipe;
9863 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9864 default:
9865 WARN(1, "unknown pipe linked to edp transcoder\n");
9866 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9867 case TRANS_DDI_EDP_INPUT_A_ON:
9868 trans_edp_pipe = PIPE_A;
9869 break;
9870 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9871 trans_edp_pipe = PIPE_B;
9872 break;
9873 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9874 trans_edp_pipe = PIPE_C;
9875 break;
9876 }
9877
9878 if (trans_edp_pipe == crtc->pipe)
9879 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9880 }
9881
f458ebbc 9882 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9883 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9884 return false;
9885
eccb140b 9886 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9887 if (!(tmp & PIPECONF_ENABLE))
9888 return false;
9889
26804afd 9890 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9891
1bd1bd80
DV		 9892 intel_get_pipe_timings(crtc, pipe_config);
9893
a1b2278e
CK		 9894 if (INTEL_INFO(dev)->gen >= 9) {
9895 skl_init_scalers(dev, crtc, pipe_config);
9896 }
9897
2fa2fe9a 9898 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9899
9900 if (INTEL_INFO(dev)->gen >= 9) {
9901 pipe_config->scaler_state.scaler_id = -1;
9902 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9903 }
9904
bd2e244f 9905 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9906 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9907 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9908 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9909 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9910 else
9911 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9912 }
88adfff1 9913
e59150dc
JB		 9914 if (IS_HASWELL(dev))
9915 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9916 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9917
ebb69c95
CT		 9918 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9919 pipe_config->pixel_multiplier =
9920 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9921 } else {
9922 pipe_config->pixel_multiplier = 1;
9923 }
6c49f241 9924
0e8ffe1b
DV		 9925 return true;
9926}
9927
560b85bb
CW		 9928static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9929{
9930 struct drm_device *dev = crtc->dev;
9931 struct drm_i915_private *dev_priv = dev->dev_private;
9932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9933 uint32_t cntl = 0, size = 0;
560b85bb 9934
dc41c154 9935 if (base) {
3dd512fb
MR		 9936 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9937 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9938 unsigned int stride = roundup_pow_of_two(width) * 4;
9939
9940 switch (stride) {
9941 default:
9942 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9943 width, stride);
9944 stride = 256;
9945 /* fallthrough */
9946 case 256:
9947 case 512:
9948 case 1024:
9949 case 2048:
9950 break;
4b0e333e
CW		 9951 }
9952
dc41c154
VS		 9953 cntl |= CURSOR_ENABLE |
9954 CURSOR_GAMMA_ENABLE |
9955 CURSOR_FORMAT_ARGB |
9956 CURSOR_STRIDE(stride);
9957
9958 size = (height << 12) | width;
4b0e333e 9959 }
560b85bb 9960
dc41c154
VS		 9961 if (intel_crtc->cursor_cntl != 0 &&
9962 (intel_crtc->cursor_base != base ||
9963 intel_crtc->cursor_size != size ||
9964 intel_crtc->cursor_cntl != cntl)) {
9965 /* On these chipsets we can only modify the base/size/stride
9966 * whilst the cursor is disabled.
9967 */
9968 I915_WRITE(_CURACNTR, 0);
4b0e333e 9969 POSTING_READ(_CURACNTR);
dc41c154 9970 intel_crtc->cursor_cntl = 0;
4b0e333e 9971 }
560b85bb 9972
99d1f387 9973 if (intel_crtc->cursor_base != base) {
9db4a9c7 9974 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9975 intel_crtc->cursor_base = base;
9976 }
4726e0b0 9977
dc41c154
VS		 9978 if (intel_crtc->cursor_size != size) {
9979 I915_WRITE(CURSIZE, size);
9980 intel_crtc->cursor_size = size;
4b0e333e 9981 }
560b85bb 9982
4b0e333e 9983 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9984 I915_WRITE(_CURACNTR, cntl);
9985 POSTING_READ(_CURACNTR);
4b0e333e 9986 intel_crtc->cursor_cntl = cntl;
560b85bb 9987 }
560b85bb
CW		 9988}
9989
560b85bb 9990static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9991{
9992 struct drm_device *dev = crtc->dev;
9993 struct drm_i915_private *dev_priv = dev->dev_private;
9994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9995 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9996 uint32_t cntl;
9997
9998 cntl = 0;
9999 if (base) {
10000 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 10001 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 10002 case 64:
10003 cntl |= CURSOR_MODE_64_ARGB_AX;
10004 break;
10005 case 128:
10006 cntl |= CURSOR_MODE_128_ARGB_AX;
10007 break;
10008 case 256:
10009 cntl |= CURSOR_MODE_256_ARGB_AX;
10010 break;
10011 default:
3dd512fb 10012 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 10013 return;
65a21cd6 10014 }
4b0e333e 10015 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 10016
10017 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10018 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 10019 }
65a21cd6 10020
8e7d688b 10021 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 10022 cntl |= CURSOR_ROTATE_180;
10023
4b0e333e
CW		 10024 if (intel_crtc->cursor_cntl != cntl) {
10025 I915_WRITE(CURCNTR(pipe), cntl);
10026 POSTING_READ(CURCNTR(pipe));
10027 intel_crtc->cursor_cntl = cntl;
65a21cd6 10028 }
4b0e333e 10029
65a21cd6 10030 /* and commit changes on next vblank */
5efb3e28
VS		 10031 I915_WRITE(CURBASE(pipe), base);
10032 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 10033
10034 intel_crtc->cursor_base = base;
65a21cd6
JB		 10035}
10036
cda4b7d3 10037/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 10038static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10039 bool on)
cda4b7d3
CW		 10040{
10041 struct drm_device *dev = crtc->dev;
10042 struct drm_i915_private *dev_priv = dev->dev_private;
10043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10044 int pipe = intel_crtc->pipe;
3d7d6510
MR		 10045 int x = crtc->cursor_x;
10046 int y = crtc->cursor_y;
d6e4db15 10047 u32 base = 0, pos = 0;
cda4b7d3 10048
d6e4db15 10049 if (on)
cda4b7d3 10050 base = intel_crtc->cursor_addr;
cda4b7d3 10051
6e3c9717 10052 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 10053 base = 0;
10054
6e3c9717 10055 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 10056 base = 0;
10057
10058 if (x < 0) {
3dd512fb 10059 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 10060 base = 0;
10061
10062 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10063 x = -x;
10064 }
10065 pos |= x << CURSOR_X_SHIFT;
10066
10067 if (y < 0) {
3dd512fb 10068 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 10069 base = 0;
10070
10071 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10072 y = -y;
10073 }
10074 pos |= y << CURSOR_Y_SHIFT;
10075
4b0e333e 10076 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10077 return;
10078
5efb3e28
VS		 10079 I915_WRITE(CURPOS(pipe), pos);
10080
4398ad45
VS		 10081 /* ILK+ do this automagically */
10082 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10083 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 10084 base += (intel_crtc->base.cursor->state->crtc_h *
10085 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 10086 }
10087
8ac54669 10088 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10089 i845_update_cursor(crtc, base);
10090 else
10091 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10092}
10093
dc41c154
VS		 10094static bool cursor_size_ok(struct drm_device *dev,
10095 uint32_t width, uint32_t height)
10096{
10097 if (width == 0 || height == 0)
10098 return false;
10099
10100 /*
10101 * 845g/865g are special in that they are only limited by
10102 * the width of their cursors, the height is arbitrary up to
10103 * the precision of the register. Everything else requires
10104 * square cursors, limited to a few power-of-two sizes.
10105 */
10106 if (IS_845G(dev) || IS_I865G(dev)) {
10107 if ((width & 63) != 0)
10108 return false;
10109
10110 if (width > (IS_845G(dev) ? 64 : 512))
10111 return false;
10112
10113 if (height > 1023)
10114 return false;
10115 } else {
10116 switch (width | height) {
10117 case 256:
10118 case 128:
10119 if (IS_GEN2(dev))
10120 return false;
10121 case 64:
10122 break;
10123 default:
10124 return false;
10125 }
10126 }
10127
10128 return true;
10129}
10130
79e53945 10131static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10132 u16 *blue, uint32_t start, uint32_t size)
79e53945 10133{
7203425a 10134 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10136
7203425a 10137 for (i = start; i < end; i++) {
79e53945
JB		 10138 intel_crtc->lut_r[i] = red[i] >> 8;
10139 intel_crtc->lut_g[i] = green[i] >> 8;
10140 intel_crtc->lut_b[i] = blue[i] >> 8;
10141 }
10142
10143 intel_crtc_load_lut(crtc);
10144}
10145
79e53945
JB		 10146/* VESA 640x480x72Hz mode to set on the pipe */
10147static struct drm_display_mode load_detect_mode = {
10148 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10149 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10150};
10151
a8bb6818
DV		 10152struct drm_framebuffer *
10153__intel_framebuffer_create(struct drm_device *dev,
10154 struct drm_mode_fb_cmd2 *mode_cmd,
10155 struct drm_i915_gem_object *obj)
d2dff872
CW		 10156{
10157 struct intel_framebuffer *intel_fb;
10158 int ret;
10159
10160 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10161 if (!intel_fb) {
6ccb81f2 10162 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10163 return ERR_PTR(-ENOMEM);
10164 }
10165
10166 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10167 if (ret)
10168 goto err;
d2dff872
CW		 10169
10170 return &intel_fb->base;
dd4916c5 10171err:
6ccb81f2 10172 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10173 kfree(intel_fb);
10174
10175 return ERR_PTR(ret);
d2dff872
CW		 10176}
10177
b5ea642a 10178static struct drm_framebuffer *
a8bb6818
DV		 10179intel_framebuffer_create(struct drm_device *dev,
10180 struct drm_mode_fb_cmd2 *mode_cmd,
10181 struct drm_i915_gem_object *obj)
10182{
10183 struct drm_framebuffer *fb;
10184 int ret;
10185
10186 ret = i915_mutex_lock_interruptible(dev);
10187 if (ret)
10188 return ERR_PTR(ret);
10189 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10190 mutex_unlock(&dev->struct_mutex);
10191
10192 return fb;
10193}
10194
d2dff872
CW		 10195static u32
10196intel_framebuffer_pitch_for_width(int width, int bpp)
10197{
10198 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10199 return ALIGN(pitch, 64);
10200}
10201
10202static u32
10203intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10204{
10205 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10206 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10207}
10208
10209static struct drm_framebuffer *
10210intel_framebuffer_create_for_mode(struct drm_device *dev,
10211 struct drm_display_mode *mode,
10212 int depth, int bpp)
10213{
10214 struct drm_i915_gem_object *obj;
0fed39bd 10215 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10216
10217 obj = i915_gem_alloc_object(dev,
10218 intel_framebuffer_size_for_mode(mode, bpp));
10219 if (obj == NULL)
10220 return ERR_PTR(-ENOMEM);
10221
10222 mode_cmd.width = mode->hdisplay;
10223 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10224 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10225 bpp);
5ca0c34a 10226 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10227
10228 return intel_framebuffer_create(dev, &mode_cmd, obj);
10229}
10230
10231static struct drm_framebuffer *
10232mode_fits_in_fbdev(struct drm_device *dev,
10233 struct drm_display_mode *mode)
10234{
4520f53a 10235#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10236 struct drm_i915_private *dev_priv = dev->dev_private;
10237 struct drm_i915_gem_object *obj;
10238 struct drm_framebuffer *fb;
10239
4c0e5528 10240 if (!dev_priv->fbdev)
d2dff872
CW		 10241 return NULL;
10242
4c0e5528 10243 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10244 return NULL;
10245
4c0e5528
DV		 10246 obj = dev_priv->fbdev->fb->obj;
10247 BUG_ON(!obj);
10248
8bcd4553 10249 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10250 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10251 fb->bits_per_pixel))
d2dff872
CW		 10252 return NULL;
10253
01f2c773 10254 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10255 return NULL;
10256
10257 return fb;
4520f53a
DV		 10258#else
10259 return NULL;
10260#endif
d2dff872
CW		 10261}
10262
d3a40d1b
ACO		 10263static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10264 struct drm_crtc *crtc,
10265 struct drm_display_mode *mode,
10266 struct drm_framebuffer *fb,
10267 int x, int y)
10268{
10269 struct drm_plane_state *plane_state;
10270 int hdisplay, vdisplay;
10271 int ret;
10272
10273 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10274 if (IS_ERR(plane_state))
10275 return PTR_ERR(plane_state);
10276
10277 if (mode)
10278 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10279 else
10280 hdisplay = vdisplay = 0;
10281
10282 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10283 if (ret)
10284 return ret;
10285 drm_atomic_set_fb_for_plane(plane_state, fb);
10286 plane_state->crtc_x = 0;
10287 plane_state->crtc_y = 0;
10288 plane_state->crtc_w = hdisplay;
10289 plane_state->crtc_h = vdisplay;
10290 plane_state->src_x = x << 16;
10291 plane_state->src_y = y << 16;
10292 plane_state->src_w = hdisplay << 16;
10293 plane_state->src_h = vdisplay << 16;
10294
10295 return 0;
10296}
10297
d2434ab7 10298bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10299 struct drm_display_mode *mode,
51fd371b
RC		 10300 struct intel_load_detect_pipe *old,
10301 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10302{
10303 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10304 struct intel_encoder *intel_encoder =
10305 intel_attached_encoder(connector);
79e53945 10306 struct drm_crtc *possible_crtc;
4ef69c7a 10307 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10308 struct drm_crtc *crtc = NULL;
10309 struct drm_device *dev = encoder->dev;
94352cf9 10310 struct drm_framebuffer *fb;
51fd371b 10311 struct drm_mode_config *config = &dev->mode_config;
83a57153 10312 struct drm_atomic_state *state = NULL;
944b0c76 10313 struct drm_connector_state *connector_state;
4be07317 10314 struct intel_crtc_state *crtc_state;
51fd371b 10315 int ret, i = -1;
79e53945 10316
d2dff872 10317 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10318 connector->base.id, connector->name,
8e329a03 10319 encoder->base.id, encoder->name);
d2dff872 10320
51fd371b
RC		 10321retry:
10322 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10323 if (ret)
10324 goto fail_unlock;
6e9f798d 10325
79e53945
JB		 10326 /*
10327 * Algorithm gets a little messy:
7a5e4805 10328 *
79e53945
JB		 10329 * - if the connector already has an assigned crtc, use it (but make
10330 * sure it's on first)
7a5e4805 10331 *
79e53945
JB		 10332 * - try to find the first unused crtc that can drive this connector,
10333 * and use that if we find one
79e53945
JB		 10334 */
10335
10336 /* See if we already have a CRTC for this connector */
10337 if (encoder->crtc) {
10338 crtc = encoder->crtc;
8261b191 10339
51fd371b 10340 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10341 if (ret)
10342 goto fail_unlock;
10343 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10344 if (ret)
10345 goto fail_unlock;
7b24056b 10346
24218aac 10347 old->dpms_mode = connector->dpms;
8261b191
CW		 10348 old->load_detect_temp = false;
10349
10350 /* Make sure the crtc and connector are running */
24218aac
DV		 10351 if (connector->dpms != DRM_MODE_DPMS_ON)
10352 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10353
7173188d 10354 return true;
79e53945
JB		 10355 }
10356
10357 /* Find an unused one (if possible) */
70e1e0ec 10358 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10359 i++;
10360 if (!(encoder->possible_crtcs & (1 << i)))
10361 continue;
83d65738 10362 if (possible_crtc->state->enable)
a459249c
VS		 10363 continue;
10364 /* This can occur when applying the pipe A quirk on resume. */
10365 if (to_intel_crtc(possible_crtc)->new_enabled)
10366 continue;
10367
10368 crtc = possible_crtc;
10369 break;
79e53945
JB		 10370 }
10371
10372 /*
10373 * If we didn't find an unused CRTC, don't use any.
10374 */
10375 if (!crtc) {
7173188d 10376 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10377 goto fail_unlock;
79e53945
JB		 10378 }
10379
51fd371b
RC		 10380 ret = drm_modeset_lock(&crtc->mutex, ctx);
10381 if (ret)
4d02e2de
DV		 10382 goto fail_unlock;
10383 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10384 if (ret)
51fd371b 10385 goto fail_unlock;
fc303101
DV		 10386 intel_encoder->new_crtc = to_intel_crtc(crtc);
10387 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10388
10389 intel_crtc = to_intel_crtc(crtc);
412b61d8 10390 intel_crtc->new_enabled = true;
24218aac 10391 old->dpms_mode = connector->dpms;
8261b191 10392 old->load_detect_temp = true;
d2dff872 10393 old->release_fb = NULL;
79e53945 10394
83a57153
ACO		 10395 state = drm_atomic_state_alloc(dev);
10396 if (!state)
10397 return false;
10398
10399 state->acquire_ctx = ctx;
10400
944b0c76
ACO		 10401 connector_state = drm_atomic_get_connector_state(state, connector);
10402 if (IS_ERR(connector_state)) {
10403 ret = PTR_ERR(connector_state);
10404 goto fail;
10405 }
10406
10407 connector_state->crtc = crtc;
10408 connector_state->best_encoder = &intel_encoder->base;
10409
4be07317
ACO		 10410 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10411 if (IS_ERR(crtc_state)) {
10412 ret = PTR_ERR(crtc_state);
10413 goto fail;
10414 }
10415
49d6fa21 10416 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10417
6492711d
CW		 10418 if (!mode)
10419 mode = &load_detect_mode;
79e53945 10420
d2dff872
CW		 10421 /* We need a framebuffer large enough to accommodate all accesses
10422 * that the plane may generate whilst we perform load detection.
10423 * We can not rely on the fbcon either being present (we get called
10424 * during its initialisation to detect all boot displays, or it may
10425 * not even exist) or that it is large enough to satisfy the
10426 * requested mode.
10427 */
94352cf9
DV		 10428 fb = mode_fits_in_fbdev(dev, mode);
10429 if (fb == NULL) {
d2dff872 10430 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10431 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10432 old->release_fb = fb;
d2dff872
CW		 10433 } else
10434 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10435 if (IS_ERR(fb)) {
d2dff872 10436 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10437 goto fail;
79e53945 10438 }
79e53945 10439
d3a40d1b
ACO		 10440 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10441 if (ret)
10442 goto fail;
10443
8c7b5ccb
ACO		 10444 drm_mode_copy(&crtc_state->base.mode, mode);
10445
568c634a 10446 if (intel_set_mode(state)) {
6492711d 10447 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10448 if (old->release_fb)
10449 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10450 goto fail;
79e53945 10451 }
9128b040 10452 crtc->primary->crtc = crtc;
7173188d 10453
79e53945 10454 /* let the connector get through one full cycle before testing */
9d0498a2 10455 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10456 return true;
412b61d8
VS		 10457
10458 fail:
83d65738 10459 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10460fail_unlock:
e5d958ef
ACO		 10461 drm_atomic_state_free(state);
10462 state = NULL;
83a57153 10463
51fd371b
RC		 10464 if (ret == -EDEADLK) {
10465 drm_modeset_backoff(ctx);
10466 goto retry;
10467 }
10468
412b61d8 10469 return false;
79e53945
JB		 10470}
10471
d2434ab7 10472void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10473 struct intel_load_detect_pipe *old,
10474 struct drm_modeset_acquire_ctx *ctx)
79e53945 10475{
83a57153 10476 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10477 struct intel_encoder *intel_encoder =
10478 intel_attached_encoder(connector);
4ef69c7a 10479 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10480 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10482 struct drm_atomic_state *state;
944b0c76 10483 struct drm_connector_state *connector_state;
4be07317 10484 struct intel_crtc_state *crtc_state;
d3a40d1b 10485 int ret;
79e53945 10486
d2dff872 10487 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10488 connector->base.id, connector->name,
8e329a03 10489 encoder->base.id, encoder->name);
d2dff872 10490
8261b191 10491 if (old->load_detect_temp) {
83a57153 10492 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10493 if (!state)
10494 goto fail;
83a57153
ACO		 10495
10496 state->acquire_ctx = ctx;
10497
944b0c76
ACO		 10498 connector_state = drm_atomic_get_connector_state(state, connector);
10499 if (IS_ERR(connector_state))
10500 goto fail;
10501
4be07317
ACO		 10502 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10503 if (IS_ERR(crtc_state))
10504 goto fail;
10505
fc303101
DV		 10506 to_intel_connector(connector)->new_encoder = NULL;
10507 intel_encoder->new_crtc = NULL;
412b61d8 10508 intel_crtc->new_enabled = false;
944b0c76
ACO		 10509
10510 connector_state->best_encoder = NULL;
10511 connector_state->crtc = NULL;
10512
49d6fa21 10513 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10514
d3a40d1b
ACO		 10515 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10516 0, 0);
10517 if (ret)
10518 goto fail;
10519
568c634a 10520 ret = intel_set_mode(state);
2bfb4627
ACO		 10521 if (ret)
10522 goto fail;
d2dff872 10523
36206361
DV		 10524 if (old->release_fb) {
10525 drm_framebuffer_unregister_private(old->release_fb);
10526 drm_framebuffer_unreference(old->release_fb);
10527 }
d2dff872 10528
0622a53c 10529 return;
79e53945
JB		 10530 }
10531
c751ce4f 10532 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10533 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10534 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10535
10536 return;
10537fail:
10538 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10539 drm_atomic_state_free(state);
79e53945
JB		 10540}
10541
da4a1efa 10542static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10543 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10544{
10545 struct drm_i915_private *dev_priv = dev->dev_private;
10546 u32 dpll = pipe_config->dpll_hw_state.dpll;
10547
10548 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10549 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10550 else if (HAS_PCH_SPLIT(dev))
10551 return 120000;
10552 else if (!IS_GEN2(dev))
10553 return 96000;
10554 else
10555 return 48000;
10556}
10557
79e53945 10558/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10559static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10560 struct intel_crtc_state *pipe_config)
79e53945 10561{
f1f644dc 10562 struct drm_device *dev = crtc->base.dev;
79e53945 10563 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10564 int pipe = pipe_config->cpu_transcoder;
293623f7 10565 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10566 u32 fp;
10567 intel_clock_t clock;
da4a1efa 10568 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10569
10570 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10571 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10572 else
293623f7 10573 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10574
10575 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10576 if (IS_PINEVIEW(dev)) {
10577 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10578 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10579 } else {
10580 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10581 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10582 }
10583
a6c45cf0 10584 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10585 if (IS_PINEVIEW(dev))
10586 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10587 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10588 else
10589 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10590 DPLL_FPA01_P1_POST_DIV_SHIFT);
10591
10592 switch (dpll & DPLL_MODE_MASK) {
10593 case DPLLB_MODE_DAC_SERIAL:
10594 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10595 5 : 10;
10596 break;
10597 case DPLLB_MODE_LVDS:
10598 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10599 7 : 14;
10600 break;
10601 default:
28c97730 10602 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10603 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10604 return;
79e53945
JB		 10605 }
10606
ac58c3f0 10607 if (IS_PINEVIEW(dev))
da4a1efa 10608 pineview_clock(refclk, &clock);
ac58c3f0 10609 else
da4a1efa 10610 i9xx_clock(refclk, &clock);
79e53945 10611 } else {
0fb58223 10612 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10613 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10614
10615 if (is_lvds) {
10616 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10617 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10618
10619 if (lvds & LVDS_CLKB_POWER_UP)
10620 clock.p2 = 7;
10621 else
10622 clock.p2 = 14;
79e53945
JB		 10623 } else {
10624 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10625 clock.p1 = 2;
10626 else {
10627 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10628 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10629 }
10630 if (dpll & PLL_P2_DIVIDE_BY_4)
10631 clock.p2 = 4;
10632 else
10633 clock.p2 = 2;
79e53945 10634 }
da4a1efa
VS		 10635
10636 i9xx_clock(refclk, &clock);
79e53945
JB		 10637 }
10638
18442d08
VS		 10639 /*
10640 * This value includes pixel_multiplier. We will use
241bfc38 10641 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10642 * encoder's get_config() function.
10643 */
10644 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10645}
10646
6878da05
VS		 10647int intel_dotclock_calculate(int link_freq,
10648 const struct intel_link_m_n *m_n)
f1f644dc 10649{
f1f644dc
JB		 10650 /*
10651 * The calculation for the data clock is:
1041a02f 10652 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10653 * But we want to avoid losing precison if possible, so:
1041a02f 10654 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10655 *
10656 * and the link clock is simpler:
1041a02f 10657 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10658 */
10659
6878da05
VS		 10660 if (!m_n->link_n)
10661 return 0;
f1f644dc 10662
6878da05
VS		 10663 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10664}
f1f644dc 10665
18442d08 10666static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10667 struct intel_crtc_state *pipe_config)
6878da05
VS		 10668{
10669 struct drm_device *dev = crtc->base.dev;
79e53945 10670
18442d08
VS		 10671 /* read out port_clock from the DPLL */
10672 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10673
f1f644dc 10674 /*
18442d08 10675 * This value does not include pixel_multiplier.
241bfc38 10676 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10677 * agree once we know their relationship in the encoder's
10678 * get_config() function.
79e53945 10679 */
2d112de7 10680 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10681 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10682 &pipe_config->fdi_m_n);
79e53945
JB		 10683}
10684
10685/** Returns the currently programmed mode of the given pipe. */
10686struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10687 struct drm_crtc *crtc)
10688{
548f245b 10689 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10691 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10692 struct drm_display_mode *mode;
5cec258b 10693 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10694 int htot = I915_READ(HTOTAL(cpu_transcoder));
10695 int hsync = I915_READ(HSYNC(cpu_transcoder));
10696 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10697 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10698 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10699
10700 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10701 if (!mode)
10702 return NULL;
10703
f1f644dc
JB		 10704 /*
10705 * Construct a pipe_config sufficient for getting the clock info
10706 * back out of crtc_clock_get.
10707 *
10708 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10709 * to use a real value here instead.
10710 */
293623f7 10711 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10712 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10713 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10714 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10715 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10716 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10717
773ae034 10718 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10719 mode->hdisplay = (htot & 0xffff) + 1;
10720 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10721 mode->hsync_start = (hsync & 0xffff) + 1;
10722 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10723 mode->vdisplay = (vtot & 0xffff) + 1;
10724 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10725 mode->vsync_start = (vsync & 0xffff) + 1;
10726 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10727
10728 drm_mode_set_name(mode);
79e53945
JB		 10729
10730 return mode;
10731}
10732
652c393a
JB		 10733static void intel_decrease_pllclock(struct drm_crtc *crtc)
10734{
10735 struct drm_device *dev = crtc->dev;
fbee40df 10736 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10738
baff296c 10739 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10740 return;
10741
10742 if (!dev_priv->lvds_downclock_avail)
10743 return;
10744
10745 /*
10746 * Since this is called by a timer, we should never get here in
10747 * the manual case.
10748 */
10749 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10750 int pipe = intel_crtc->pipe;
10751 int dpll_reg = DPLL(pipe);
10752 int dpll;
f6e5b160 10753
44d98a61 10754 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10755
8ac5a6d5 10756 assert_panel_unlocked(dev_priv, pipe);
652c393a 10757
dc257cf1 10758 dpll = I915_READ(dpll_reg);
652c393a
JB		 10759 dpll |= DISPLAY_RATE_SELECT_FPA1;
10760 I915_WRITE(dpll_reg, dpll);
9d0498a2 10761 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10762 dpll = I915_READ(dpll_reg);
10763 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10764 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10765 }
10766
10767}
10768
f047e395
CW		 10769void intel_mark_busy(struct drm_device *dev)
10770{
c67a470b
PZ		 10771 struct drm_i915_private *dev_priv = dev->dev_private;
10772
f62a0076
CW		 10773 if (dev_priv->mm.busy)
10774 return;
10775
43694d69 10776 intel_runtime_pm_get(dev_priv);
c67a470b 10777 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10778 if (INTEL_INFO(dev)->gen >= 6)
10779 gen6_rps_busy(dev_priv);
f62a0076 10780 dev_priv->mm.busy = true;
f047e395
CW		 10781}
10782
10783void intel_mark_idle(struct drm_device *dev)
652c393a 10784{
c67a470b 10785 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10786 struct drm_crtc *crtc;
652c393a 10787
f62a0076
CW		 10788 if (!dev_priv->mm.busy)
10789 return;
10790
10791 dev_priv->mm.busy = false;
10792
70e1e0ec 10793 for_each_crtc(dev, crtc) {
f4510a27 10794 if (!crtc->primary->fb)
652c393a
JB		 10795 continue;
10796
725a5b54 10797 intel_decrease_pllclock(crtc);
652c393a 10798 }
b29c19b6 10799
3d13ef2e 10800 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10801 gen6_rps_idle(dev->dev_private);
bb4cdd53 10802
43694d69 10803 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10804}
10805
79e53945
JB		 10806static void intel_crtc_destroy(struct drm_crtc *crtc)
10807{
10808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10809 struct drm_device *dev = crtc->dev;
10810 struct intel_unpin_work *work;
67e77c5a 10811
5e2d7afc 10812 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10813 work = intel_crtc->unpin_work;
10814 intel_crtc->unpin_work = NULL;
5e2d7afc 10815 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10816
10817 if (work) {
10818 cancel_work_sync(&work->work);
10819 kfree(work);
10820 }
79e53945
JB		 10821
10822 drm_crtc_cleanup(crtc);
67e77c5a 10823
79e53945
JB		 10824 kfree(intel_crtc);
10825}
10826
6b95a207
KH		 10827static void intel_unpin_work_fn(struct work_struct *__work)
10828{
10829 struct intel_unpin_work *work =
10830 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10831 struct drm_device *dev = work->crtc->dev;
f99d7069 10832 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10833
b4a98e57 10834 mutex_lock(&dev->struct_mutex);
82bc3b2d 10835 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10836 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10837
7ff0ebcc 10838 intel_fbc_update(dev);
f06cc1b9
JH		 10839
10840 if (work->flip_queued_req)
146d84f0 10841 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10842 mutex_unlock(&dev->struct_mutex);
10843
f99d7069 10844 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10845 drm_framebuffer_unreference(work->old_fb);
f99d7069 10846
b4a98e57
CW		 10847 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10848 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10849
6b95a207
KH		 10850 kfree(work);
10851}
10852
1afe3e9d 10853static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10854 struct drm_crtc *crtc)
6b95a207 10855{
6b95a207
KH		 10856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10857 struct intel_unpin_work *work;
6b95a207
KH		 10858 unsigned long flags;
10859
10860 /* Ignore early vblank irqs */
10861 if (intel_crtc == NULL)
10862 return;
10863
f326038a
DV		 10864 /*
10865 * This is called both by irq handlers and the reset code (to complete
10866 * lost pageflips) so needs the full irqsave spinlocks.
10867 */
6b95a207
KH		 10868 spin_lock_irqsave(&dev->event_lock, flags);
10869 work = intel_crtc->unpin_work;
e7d841ca
CW		 10870
10871 /* Ensure we don't miss a work->pending update ... */
10872 smp_rmb();
10873
10874 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10875 spin_unlock_irqrestore(&dev->event_lock, flags);
10876 return;
10877 }
10878
d6bbafa1 10879 page_flip_completed(intel_crtc);
0af7e4df 10880
6b95a207 10881 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10882}
10883
1afe3e9d
JB		 10884void intel_finish_page_flip(struct drm_device *dev, int pipe)
10885{
fbee40df 10886 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10887 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10888
49b14a5c 10889 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10890}
10891
10892void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10893{
fbee40df 10894 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10895 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10896
49b14a5c 10897 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10898}
10899
75f7f3ec
VS		 10900/* Is 'a' after or equal to 'b'? */
10901static bool g4x_flip_count_after_eq(u32 a, u32 b)
10902{
10903 return !((a - b) & 0x80000000);
10904}
10905
10906static bool page_flip_finished(struct intel_crtc *crtc)
10907{
10908 struct drm_device *dev = crtc->base.dev;
10909 struct drm_i915_private *dev_priv = dev->dev_private;
10910
bdfa7542
VS		 10911 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10912 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10913 return true;
10914
75f7f3ec
VS		 10915 /*
10916 * The relevant registers doen't exist on pre-ctg.
10917 * As the flip done interrupt doesn't trigger for mmio
10918 * flips on gmch platforms, a flip count check isn't
10919 * really needed there. But since ctg has the registers,
10920 * include it in the check anyway.
10921 */
10922 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10923 return true;
10924
10925 /*
10926 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10927 * used the same base address. In that case the mmio flip might
10928 * have completed, but the CS hasn't even executed the flip yet.
10929 *
10930 * A flip count check isn't enough as the CS might have updated
10931 * the base address just after start of vblank, but before we
10932 * managed to process the interrupt. This means we'd complete the
10933 * CS flip too soon.
10934 *
10935 * Combining both checks should get us a good enough result. It may
10936 * still happen that the CS flip has been executed, but has not
10937 * yet actually completed. But in case the base address is the same
10938 * anyway, we don't really care.
10939 */
10940 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10941 crtc->unpin_work->gtt_offset &&
10942 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10943 crtc->unpin_work->flip_count);
10944}
10945
6b95a207
KH		 10946void intel_prepare_page_flip(struct drm_device *dev, int plane)
10947{
fbee40df 10948 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10949 struct intel_crtc *intel_crtc =
10950 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10951 unsigned long flags;
10952
f326038a
DV		 10953
10954 /*
10955 * This is called both by irq handlers and the reset code (to complete
10956 * lost pageflips) so needs the full irqsave spinlocks.
10957 *
10958 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10959 * generate a page-flip completion irq, i.e. every modeset
10960 * is also accompanied by a spurious intel_prepare_page_flip().
10961 */
6b95a207 10962 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10963 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10964 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10965 spin_unlock_irqrestore(&dev->event_lock, flags);
10966}
10967
eba905b2 10968static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10969{
10970 /* Ensure that the work item is consistent when activating it ... */
10971 smp_wmb();
10972 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10973 /* and that it is marked active as soon as the irq could fire. */
10974 smp_wmb();
10975}
10976
8c9f3aaf
JB		 10977static int intel_gen2_queue_flip(struct drm_device *dev,
10978 struct drm_crtc *crtc,
10979 struct drm_framebuffer *fb,
ed8d1975 10980 struct drm_i915_gem_object *obj,
a4872ba6 10981 struct intel_engine_cs *ring,
ed8d1975 10982 uint32_t flags)
8c9f3aaf 10983{
8c9f3aaf 10984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10985 u32 flip_mask;
10986 int ret;
10987
6d90c952 10988 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10989 if (ret)
4fa62c89 10990 return ret;
8c9f3aaf
JB		 10991
10992 /* Can't queue multiple flips, so wait for the previous
10993 * one to finish before executing the next.
10994 */
10995 if (intel_crtc->plane)
10996 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10997 else
10998 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10999 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11000 intel_ring_emit(ring, MI_NOOP);
11001 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11002 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11003 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11004 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 11005 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 11006
11007 intel_mark_page_flip_active(intel_crtc);
09246732 11008 __intel_ring_advance(ring);
83d4092b 11009 return 0;
8c9f3aaf
JB		 11010}
11011
11012static int intel_gen3_queue_flip(struct drm_device *dev,
11013 struct drm_crtc *crtc,
11014 struct drm_framebuffer *fb,
ed8d1975 11015 struct drm_i915_gem_object *obj,
a4872ba6 11016 struct intel_engine_cs *ring,
ed8d1975 11017 uint32_t flags)
8c9f3aaf 11018{
8c9f3aaf 11019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 11020 u32 flip_mask;
11021 int ret;
11022
6d90c952 11023 ret = intel_ring_begin(ring, 6);
8c9f3aaf 11024 if (ret)
4fa62c89 11025 return ret;
8c9f3aaf
JB		 11026
11027 if (intel_crtc->plane)
11028 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11029 else
11030 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 11031 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11032 intel_ring_emit(ring, MI_NOOP);
11033 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11034 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11035 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11036 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 11037 intel_ring_emit(ring, MI_NOOP);
11038
e7d841ca 11039 intel_mark_page_flip_active(intel_crtc);
09246732 11040 __intel_ring_advance(ring);
83d4092b 11041 return 0;
8c9f3aaf
JB		 11042}
11043
11044static int intel_gen4_queue_flip(struct drm_device *dev,
11045 struct drm_crtc *crtc,
11046 struct drm_framebuffer *fb,
ed8d1975 11047 struct drm_i915_gem_object *obj,
a4872ba6 11048 struct intel_engine_cs *ring,
ed8d1975 11049 uint32_t flags)
8c9f3aaf
JB		 11050{
11051 struct drm_i915_private *dev_priv = dev->dev_private;
11052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11053 uint32_t pf, pipesrc;
11054 int ret;
11055
6d90c952 11056 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11057 if (ret)
4fa62c89 11058 return ret;
8c9f3aaf
JB		 11059
11060 /* i965+ uses the linear or tiled offsets from the
11061 * Display Registers (which do not change across a page-flip)
11062 * so we need only reprogram the base address.
11063 */
6d90c952
DV		 11064 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11065 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11066 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 11067 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 11068 obj->tiling_mode);
8c9f3aaf
JB		 11069
11070 /* XXX Enabling the panel-fitter across page-flip is so far
11071 * untested on non-native modes, so ignore it for now.
11072 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11073 */
11074 pf = 0;
11075 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11076 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11077
11078 intel_mark_page_flip_active(intel_crtc);
09246732 11079 __intel_ring_advance(ring);
83d4092b 11080 return 0;
8c9f3aaf
JB		 11081}
11082
11083static int intel_gen6_queue_flip(struct drm_device *dev,
11084 struct drm_crtc *crtc,
11085 struct drm_framebuffer *fb,
ed8d1975 11086 struct drm_i915_gem_object *obj,
a4872ba6 11087 struct intel_engine_cs *ring,
ed8d1975 11088 uint32_t flags)
8c9f3aaf
JB		 11089{
11090 struct drm_i915_private *dev_priv = dev->dev_private;
11091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11092 uint32_t pf, pipesrc;
11093 int ret;
11094
6d90c952 11095 ret = intel_ring_begin(ring, 4);
8c9f3aaf 11096 if (ret)
4fa62c89 11097 return ret;
8c9f3aaf 11098
6d90c952
DV		 11099 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11100 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11101 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 11102 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 11103
dc257cf1
DV		 11104 /* Contrary to the suggestions in the documentation,
11105 * "Enable Panel Fitter" does not seem to be required when page
11106 * flipping with a non-native mode, and worse causes a normal
11107 * modeset to fail.
11108 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11109 */
11110 pf = 0;
8c9f3aaf 11111 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11112 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11113
11114 intel_mark_page_flip_active(intel_crtc);
09246732 11115 __intel_ring_advance(ring);
83d4092b 11116 return 0;
8c9f3aaf
JB		 11117}
11118
7c9017e5
JB		 11119static int intel_gen7_queue_flip(struct drm_device *dev,
11120 struct drm_crtc *crtc,
11121 struct drm_framebuffer *fb,
ed8d1975 11122 struct drm_i915_gem_object *obj,
a4872ba6 11123 struct intel_engine_cs *ring,
ed8d1975 11124 uint32_t flags)
7c9017e5 11125{
7c9017e5 11126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11127 uint32_t plane_bit = 0;
ffe74d75
CW		 11128 int len, ret;
11129
eba905b2 11130 switch (intel_crtc->plane) {
cb05d8de
DV		 11131 case PLANE_A:
11132 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11133 break;
11134 case PLANE_B:
11135 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11136 break;
11137 case PLANE_C:
11138 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11139 break;
11140 default:
11141 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11142 return -ENODEV;
cb05d8de
DV		 11143 }
11144
ffe74d75 11145 len = 4;
f476828a 11146 if (ring->id == RCS) {
ffe74d75 11147 len += 6;
f476828a
DL		 11148 /*
11149 * On Gen 8, SRM is now taking an extra dword to accommodate
11150 * 48bits addresses, and we need a NOOP for the batch size to
11151 * stay even.
11152 */
11153 if (IS_GEN8(dev))
11154 len += 2;
11155 }
ffe74d75 11156
f66fab8e
VS		 11157 /*
11158 * BSpec MI_DISPLAY_FLIP for IVB:
11159 * "The full packet must be contained within the same cache line."
11160 *
11161 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11162 * cacheline, if we ever start emitting more commands before
11163 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11164 * then do the cacheline alignment, and finally emit the
11165 * MI_DISPLAY_FLIP.
11166 */
11167 ret = intel_ring_cacheline_align(ring);
11168 if (ret)
4fa62c89 11169 return ret;
f66fab8e 11170
ffe74d75 11171 ret = intel_ring_begin(ring, len);
7c9017e5 11172 if (ret)
4fa62c89 11173 return ret;
7c9017e5 11174
ffe74d75
CW		 11175 /* Unmask the flip-done completion message. Note that the bspec says that
11176 * we should do this for both the BCS and RCS, and that we must not unmask
11177 * more than one flip event at any time (or ensure that one flip message
11178 * can be sent by waiting for flip-done prior to queueing new flips).
11179 * Experimentation says that BCS works despite DERRMR masking all
11180 * flip-done completion events and that unmasking all planes at once
11181 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11182 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11183 */
11184 if (ring->id == RCS) {
11185 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11186 intel_ring_emit(ring, DERRMR);
11187 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11188 DERRMR_PIPEB_PRI_FLIP_DONE |
11189 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11190 if (IS_GEN8(dev))
11191 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11192 MI_SRM_LRM_GLOBAL_GTT);
11193 else
11194 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11195 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11196 intel_ring_emit(ring, DERRMR);
11197 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11198 if (IS_GEN8(dev)) {
11199 intel_ring_emit(ring, 0);
11200 intel_ring_emit(ring, MI_NOOP);
11201 }
ffe74d75
CW		 11202 }
11203
cb05d8de 11204 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11205 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11206 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11207 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11208
11209 intel_mark_page_flip_active(intel_crtc);
09246732 11210 __intel_ring_advance(ring);
83d4092b 11211 return 0;
7c9017e5
JB		 11212}
11213
84c33a64
SG		 11214static bool use_mmio_flip(struct intel_engine_cs *ring,
11215 struct drm_i915_gem_object *obj)
11216{
11217 /*
11218 * This is not being used for older platforms, because
11219 * non-availability of flip done interrupt forces us to use
11220 * CS flips. Older platforms derive flip done using some clever
11221 * tricks involving the flip_pending status bits and vblank irqs.
11222 * So using MMIO flips there would disrupt this mechanism.
11223 */
11224
8e09bf83
CW		 11225 if (ring == NULL)
11226 return true;
11227
84c33a64
SG		 11228 if (INTEL_INFO(ring->dev)->gen < 5)
11229 return false;
11230
11231 if (i915.use_mmio_flip < 0)
11232 return false;
11233 else if (i915.use_mmio_flip > 0)
11234 return true;
14bf993e
OM		 11235 else if (i915.enable_execlists)
11236 return true;
84c33a64 11237 else
b4716185 11238 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11239}
11240
ff944564
DL		 11241static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11242{
11243 struct drm_device *dev = intel_crtc->base.dev;
11244 struct drm_i915_private *dev_priv = dev->dev_private;
11245 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11246 const enum pipe pipe = intel_crtc->pipe;
11247 u32 ctl, stride;
11248
11249 ctl = I915_READ(PLANE_CTL(pipe, 0));
11250 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11251 switch (fb->modifier[0]) {
11252 case DRM_FORMAT_MOD_NONE:
11253 break;
11254 case I915_FORMAT_MOD_X_TILED:
ff944564 11255 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11256 break;
11257 case I915_FORMAT_MOD_Y_TILED:
11258 ctl |= PLANE_CTL_TILED_Y;
11259 break;
11260 case I915_FORMAT_MOD_Yf_TILED:
11261 ctl |= PLANE_CTL_TILED_YF;
11262 break;
11263 default:
11264 MISSING_CASE(fb->modifier[0]);
11265 }
ff944564
DL		 11266
11267 /*
11268 * The stride is either expressed as a multiple of 64 bytes chunks for
11269 * linear buffers or in number of tiles for tiled buffers.
11270 */
2ebef630
TU		 11271 stride = fb->pitches[0] /
11272 intel_fb_stride_alignment(dev, fb->modifier[0],
11273 fb->pixel_format);
ff944564
DL		 11274
11275 /*
11276 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11277 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11278 */
11279 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11280 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11281
11282 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11283 POSTING_READ(PLANE_SURF(pipe, 0));
11284}
11285
11286static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11287{
11288 struct drm_device *dev = intel_crtc->base.dev;
11289 struct drm_i915_private *dev_priv = dev->dev_private;
11290 struct intel_framebuffer *intel_fb =
11291 to_intel_framebuffer(intel_crtc->base.primary->fb);
11292 struct drm_i915_gem_object *obj = intel_fb->obj;
11293 u32 dspcntr;
11294 u32 reg;
11295
84c33a64
SG		 11296 reg = DSPCNTR(intel_crtc->plane);
11297 dspcntr = I915_READ(reg);
11298
c5d97472
DL		 11299 if (obj->tiling_mode != I915_TILING_NONE)
11300 dspcntr |= DISPPLANE_TILED;
11301 else
11302 dspcntr &= ~DISPPLANE_TILED;
11303
84c33a64
SG		 11304 I915_WRITE(reg, dspcntr);
11305
11306 I915_WRITE(DSPSURF(intel_crtc->plane),
11307 intel_crtc->unpin_work->gtt_offset);
11308 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11309
ff944564
DL		 11310}
11311
11312/*
11313 * XXX: This is the temporary way to update the plane registers until we get
11314 * around to using the usual plane update functions for MMIO flips
11315 */
11316static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11317{
11318 struct drm_device *dev = intel_crtc->base.dev;
11319 bool atomic_update;
11320 u32 start_vbl_count;
11321
11322 intel_mark_page_flip_active(intel_crtc);
11323
11324 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11325
11326 if (INTEL_INFO(dev)->gen >= 9)
11327 skl_do_mmio_flip(intel_crtc);
11328 else
11329 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11330 ilk_do_mmio_flip(intel_crtc);
11331
9362c7c5
ACO		 11332 if (atomic_update)
11333 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11334}
11335
9362c7c5 11336static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11337{
b2cfe0ab
CW		 11338 struct intel_mmio_flip *mmio_flip =
11339 container_of(work, struct intel_mmio_flip, work);
84c33a64 11340
eed29a5b
DV		 11341 if (mmio_flip->req)
11342 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11343 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11344 false, NULL,
11345 &mmio_flip->i915->rps.mmioflips));
84c33a64 11346
b2cfe0ab
CW		 11347 intel_do_mmio_flip(mmio_flip->crtc);
11348
eed29a5b 11349 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11350 kfree(mmio_flip);
84c33a64
SG		 11351}
11352
11353static int intel_queue_mmio_flip(struct drm_device *dev,
11354 struct drm_crtc *crtc,
11355 struct drm_framebuffer *fb,
11356 struct drm_i915_gem_object *obj,
11357 struct intel_engine_cs *ring,
11358 uint32_t flags)
11359{
b2cfe0ab
CW		 11360 struct intel_mmio_flip *mmio_flip;
11361
11362 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11363 if (mmio_flip == NULL)
11364 return -ENOMEM;
84c33a64 11365
bcafc4e3 11366 mmio_flip->i915 = to_i915(dev);
eed29a5b 11367 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11368 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11369
b2cfe0ab
CW		 11370 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11371 schedule_work(&mmio_flip->work);
84c33a64 11372
84c33a64
SG		 11373 return 0;
11374}
11375
8c9f3aaf
JB		 11376static int intel_default_queue_flip(struct drm_device *dev,
11377 struct drm_crtc *crtc,
11378 struct drm_framebuffer *fb,
ed8d1975 11379 struct drm_i915_gem_object *obj,
a4872ba6 11380 struct intel_engine_cs *ring,
ed8d1975 11381 uint32_t flags)
8c9f3aaf
JB		 11382{
11383 return -ENODEV;
11384}
11385
d6bbafa1
CW		 11386static bool __intel_pageflip_stall_check(struct drm_device *dev,
11387 struct drm_crtc *crtc)
11388{
11389 struct drm_i915_private *dev_priv = dev->dev_private;
11390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11391 struct intel_unpin_work *work = intel_crtc->unpin_work;
11392 u32 addr;
11393
11394 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11395 return true;
11396
11397 if (!work->enable_stall_check)
11398 return false;
11399
11400 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11401 if (work->flip_queued_req &&
11402 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11403 return false;
11404
1e3feefd 11405 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11406 }
11407
1e3feefd 11408 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11409 return false;
11410
11411 /* Potential stall - if we see that the flip has happened,
11412 * assume a missed interrupt. */
11413 if (INTEL_INFO(dev)->gen >= 4)
11414 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11415 else
11416 addr = I915_READ(DSPADDR(intel_crtc->plane));
11417
11418 /* There is a potential issue here with a false positive after a flip
11419 * to the same address. We could address this by checking for a
11420 * non-incrementing frame counter.
11421 */
11422 return addr == work->gtt_offset;
11423}
11424
11425void intel_check_page_flip(struct drm_device *dev, int pipe)
11426{
11427 struct drm_i915_private *dev_priv = dev->dev_private;
11428 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11430 struct intel_unpin_work *work;
f326038a 11431
6c51d46f 11432 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11433
11434 if (crtc == NULL)
11435 return;
11436
f326038a 11437 spin_lock(&dev->event_lock);
6ad790c0
CW		 11438 work = intel_crtc->unpin_work;
11439 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11440 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11441 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11442 page_flip_completed(intel_crtc);
6ad790c0 11443 work = NULL;
d6bbafa1 11444 }
6ad790c0
CW		 11445 if (work != NULL &&
11446 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11447 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11448 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11449}
11450
6b95a207
KH		 11451static int intel_crtc_page_flip(struct drm_crtc *crtc,
11452 struct drm_framebuffer *fb,
ed8d1975
KP		 11453 struct drm_pending_vblank_event *event,
11454 uint32_t page_flip_flags)
6b95a207
KH		 11455{
11456 struct drm_device *dev = crtc->dev;
11457 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11458 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11459 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11461 struct drm_plane *primary = crtc->primary;
a071fa00 11462 enum pipe pipe = intel_crtc->pipe;
6b95a207 11463 struct intel_unpin_work *work;
a4872ba6 11464 struct intel_engine_cs *ring;
cf5d8a46 11465 bool mmio_flip;
52e68630 11466 int ret;
6b95a207 11467
2ff8fde1
MR		 11468 /*
11469 * drm_mode_page_flip_ioctl() should already catch this, but double
11470 * check to be safe. In the future we may enable pageflipping from
11471 * a disabled primary plane.
11472 */
11473 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11474 return -EBUSY;
11475
e6a595d2 11476 /* Can't change pixel format via MI display flips. */
f4510a27 11477 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11478 return -EINVAL;
11479
11480 /*
11481 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11482 * Note that pitch changes could also affect these register.
11483 */
11484 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11485 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11486 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11487 return -EINVAL;
11488
f900db47
CW		 11489 if (i915_terminally_wedged(&dev_priv->gpu_error))
11490 goto out_hang;
11491
b14c5679 11492 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11493 if (work == NULL)
11494 return -ENOMEM;
11495
6b95a207 11496 work->event = event;
b4a98e57 11497 work->crtc = crtc;
ab8d6675 11498 work->old_fb = old_fb;
6b95a207
KH		 11499 INIT_WORK(&work->work, intel_unpin_work_fn);
11500
87b6b101 11501 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11502 if (ret)
11503 goto free_work;
11504
6b95a207 11505 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11506 spin_lock_irq(&dev->event_lock);
6b95a207 11507 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11508 /* Before declaring the flip queue wedged, check if
11509 * the hardware completed the operation behind our backs.
11510 */
11511 if (__intel_pageflip_stall_check(dev, crtc)) {
11512 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11513 page_flip_completed(intel_crtc);
11514 } else {
11515 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11516 spin_unlock_irq(&dev->event_lock);
468f0b44 11517
d6bbafa1
CW		 11518 drm_crtc_vblank_put(crtc);
11519 kfree(work);
11520 return -EBUSY;
11521 }
6b95a207
KH		 11522 }
11523 intel_crtc->unpin_work = work;
5e2d7afc 11524 spin_unlock_irq(&dev->event_lock);
6b95a207 11525
b4a98e57
CW		 11526 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11527 flush_workqueue(dev_priv->wq);
11528
75dfca80 11529 /* Reference the objects for the scheduled work. */
ab8d6675 11530 drm_framebuffer_reference(work->old_fb);
05394f39 11531 drm_gem_object_reference(&obj->base);
6b95a207 11532
f4510a27 11533 crtc->primary->fb = fb;
afd65eb4 11534 update_state_fb(crtc->primary);
1ed1f968 11535
e1f99ce6 11536 work->pending_flip_obj = obj;
e1f99ce6 11537
89ed88ba
CW		 11538 ret = i915_mutex_lock_interruptible(dev);
11539 if (ret)
11540 goto cleanup;
11541
b4a98e57 11542 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11543 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11544
75f7f3ec 11545 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11546 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11547
4fa62c89
VS		 11548 if (IS_VALLEYVIEW(dev)) {
11549 ring = &dev_priv->ring[BCS];
ab8d6675 11550 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11551 /* vlv: DISPLAY_FLIP fails to change tiling */
11552 ring = NULL;
48bf5b2d 11553 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11554 ring = &dev_priv->ring[BCS];
4fa62c89 11555 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11556 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11557 if (ring == NULL || ring->id != RCS)
11558 ring = &dev_priv->ring[BCS];
11559 } else {
11560 ring = &dev_priv->ring[RCS];
11561 }
11562
cf5d8a46
CW		 11563 mmio_flip = use_mmio_flip(ring, obj);
11564
11565 /* When using CS flips, we want to emit semaphores between rings.
11566 * However, when using mmio flips we will create a task to do the
11567 * synchronisation, so all we want here is to pin the framebuffer
11568 * into the display plane and skip any waits.
11569 */
82bc3b2d 11570 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11571 crtc->primary->state,
b4716185 11572 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11573 if (ret)
11574 goto cleanup_pending;
6b95a207 11575
121920fa
TU		 11576 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11577 + intel_crtc->dspaddr_offset;
4fa62c89 11578
cf5d8a46 11579 if (mmio_flip) {
84c33a64
SG		 11580 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11581 page_flip_flags);
d6bbafa1
CW		 11582 if (ret)
11583 goto cleanup_unpin;
11584
f06cc1b9
JH		 11585 i915_gem_request_assign(&work->flip_queued_req,
11586 obj->last_write_req);
d6bbafa1 11587 } else {
d94b5030
CW		 11588 if (obj->last_write_req) {
11589 ret = i915_gem_check_olr(obj->last_write_req);
11590 if (ret)
11591 goto cleanup_unpin;
11592 }
11593
84c33a64 11594 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11595 page_flip_flags);
11596 if (ret)
11597 goto cleanup_unpin;
11598
f06cc1b9
JH		 11599 i915_gem_request_assign(&work->flip_queued_req,
11600 intel_ring_get_request(ring));
d6bbafa1
CW		 11601 }
11602
1e3feefd 11603 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11604 work->enable_stall_check = true;
4fa62c89 11605
ab8d6675 11606 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11607 INTEL_FRONTBUFFER_PRIMARY(pipe));
11608
7ff0ebcc 11609 intel_fbc_disable(dev);
f99d7069 11610 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11611 mutex_unlock(&dev->struct_mutex);
11612
e5510fac
JB		 11613 trace_i915_flip_request(intel_crtc->plane, obj);
11614
6b95a207 11615 return 0;
96b099fd 11616
4fa62c89 11617cleanup_unpin:
82bc3b2d 11618 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11619cleanup_pending:
b4a98e57 11620 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11621 mutex_unlock(&dev->struct_mutex);
11622cleanup:
f4510a27 11623 crtc->primary->fb = old_fb;
afd65eb4 11624 update_state_fb(crtc->primary);
89ed88ba
CW		 11625
11626 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11627 drm_framebuffer_unreference(work->old_fb);
96b099fd 11628
5e2d7afc 11629 spin_lock_irq(&dev->event_lock);
96b099fd 11630 intel_crtc->unpin_work = NULL;
5e2d7afc 11631 spin_unlock_irq(&dev->event_lock);
96b099fd 11632
87b6b101 11633 drm_crtc_vblank_put(crtc);
7317c75e 11634free_work:
96b099fd
CW		 11635 kfree(work);
11636
f900db47 11637 if (ret == -EIO) {
02e0efb5
ML		 11638 struct drm_atomic_state *state;
11639 struct drm_plane_state *plane_state;
11640
f900db47 11641out_hang:
02e0efb5
ML		 11642 state = drm_atomic_state_alloc(dev);
11643 if (!state)
11644 return -ENOMEM;
11645 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11646
11647retry:
11648 plane_state = drm_atomic_get_plane_state(state, primary);
11649 ret = PTR_ERR_OR_ZERO(plane_state);
11650 if (!ret) {
11651 drm_atomic_set_fb_for_plane(plane_state, fb);
11652
11653 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11654 if (!ret)
11655 ret = drm_atomic_commit(state);
11656 }
11657
11658 if (ret == -EDEADLK) {
11659 drm_modeset_backoff(state->acquire_ctx);
11660 drm_atomic_state_clear(state);
11661 goto retry;
11662 }
11663
11664 if (ret)
11665 drm_atomic_state_free(state);
11666
f0d3dad3 11667 if (ret == 0 && event) {
5e2d7afc 11668 spin_lock_irq(&dev->event_lock);
a071fa00 11669 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11670 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11671 }
f900db47 11672 }
96b099fd 11673 return ret;
6b95a207
KH		 11674}
11675
6d3a1ce7
ML		 11676static bool encoders_cloneable(const struct intel_encoder *a,
11677 const struct intel_encoder *b)
11678{
11679 /* masks could be asymmetric, so check both ways */
11680 return a == b || (a->cloneable & (1 << b->type) &&
11681 b->cloneable & (1 << a->type));
11682}
11683
11684static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11685 struct intel_crtc *crtc,
11686 struct intel_encoder *encoder)
11687{
11688 struct intel_encoder *source_encoder;
11689 struct drm_connector *connector;
11690 struct drm_connector_state *connector_state;
11691 int i;
11692
11693 for_each_connector_in_state(state, connector, connector_state, i) {
11694 if (connector_state->crtc != &crtc->base)
11695 continue;
11696
11697 source_encoder =
11698 to_intel_encoder(connector_state->best_encoder);
11699 if (!encoders_cloneable(encoder, source_encoder))
11700 return false;
11701 }
11702
11703 return true;
11704}
11705
11706static bool check_encoder_cloning(struct drm_atomic_state *state,
11707 struct intel_crtc *crtc)
11708{
11709 struct intel_encoder *encoder;
11710 struct drm_connector *connector;
11711 struct drm_connector_state *connector_state;
11712 int i;
11713
11714 for_each_connector_in_state(state, connector, connector_state, i) {
11715 if (connector_state->crtc != &crtc->base)
11716 continue;
11717
11718 encoder = to_intel_encoder(connector_state->best_encoder);
11719 if (!check_single_encoder_cloning(state, crtc, encoder))
11720 return false;
11721 }
11722
11723 return true;
11724}
11725
11726static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11727 struct drm_crtc_state *crtc_state)
11728{
11729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11730 struct drm_atomic_state *state = crtc_state->state;
11731 int idx = crtc->base.id;
11732 bool mode_changed = needs_modeset(crtc_state);
11733
11734 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11735 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11736 return -EINVAL;
11737 }
11738
11739 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11740 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11741 idx, crtc->state->active, intel_crtc->active);
11742
11743 return 0;
11744}
11745
65b38e0d 11746static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11747 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11748 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11749 .atomic_begin = intel_begin_crtc_commit,
11750 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11751 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11752};
11753
9a935856
DV		 11754/**
11755 * intel_modeset_update_staged_output_state
11756 *
11757 * Updates the staged output configuration state, e.g. after we've read out the
11758 * current hw state.
11759 */
11760static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11761{
7668851f 11762 struct intel_crtc *crtc;
9a935856
DV		 11763 struct intel_encoder *encoder;
11764 struct intel_connector *connector;
f6e5b160 11765
3a3371ff 11766 for_each_intel_connector(dev, connector) {
9a935856
DV		 11767 connector->new_encoder =
11768 to_intel_encoder(connector->base.encoder);
11769 }
f6e5b160 11770
b2784e15 11771 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11772 encoder->new_crtc =
11773 to_intel_crtc(encoder->base.crtc);
11774 }
7668851f 11775
d3fcc808 11776 for_each_intel_crtc(dev, crtc) {
83d65738 11777 crtc->new_enabled = crtc->base.state->enable;
7668851f 11778 }
f6e5b160
CW		 11779}
11780
d29b2f9d
ACO		 11781/* Transitional helper to copy current connector/encoder state to
11782 * connector->state. This is needed so that code that is partially
11783 * converted to atomic does the right thing.
11784 */
11785static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11786{
11787 struct intel_connector *connector;
11788
11789 for_each_intel_connector(dev, connector) {
11790 if (connector->base.encoder) {
11791 connector->base.state->best_encoder =
11792 connector->base.encoder;
11793 connector->base.state->crtc =
11794 connector->base.encoder->crtc;
11795 } else {
11796 connector->base.state->best_encoder = NULL;
11797 connector->base.state->crtc = NULL;
11798 }
11799 }
11800}
11801
050f7aeb 11802static void
eba905b2 11803connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11804 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11805{
11806 int bpp = pipe_config->pipe_bpp;
11807
11808 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11809 connector->base.base.id,
c23cc417 11810 connector->base.name);
050f7aeb
DV		 11811
11812 /* Don't use an invalid EDID bpc value */
11813 if (connector->base.display_info.bpc &&
11814 connector->base.display_info.bpc * 3 < bpp) {
11815 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11816 bpp, connector->base.display_info.bpc*3);
11817 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11818 }
11819
11820 /* Clamp bpp to 8 on screens without EDID 1.4 */
11821 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11822 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11823 bpp);
11824 pipe_config->pipe_bpp = 24;
11825 }
11826}
11827
4e53c2e0 11828static int
050f7aeb 11829compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11830 struct intel_crtc_state *pipe_config)
4e53c2e0 11831{
050f7aeb 11832 struct drm_device *dev = crtc->base.dev;
1486017f 11833 struct drm_atomic_state *state;
da3ced29
ACO		 11834 struct drm_connector *connector;
11835 struct drm_connector_state *connector_state;
1486017f 11836 int bpp, i;
4e53c2e0 11837
d328c9d7 11838 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11839 bpp = 10*3;
d328c9d7
DV		 11840 else if (INTEL_INFO(dev)->gen >= 5)
11841 bpp = 12*3;
11842 else
11843 bpp = 8*3;
11844
4e53c2e0 11845
4e53c2e0
DV		 11846 pipe_config->pipe_bpp = bpp;
11847
1486017f
ACO		 11848 state = pipe_config->base.state;
11849
4e53c2e0 11850 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11851 for_each_connector_in_state(state, connector, connector_state, i) {
11852 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11853 continue;
11854
da3ced29
ACO		 11855 connected_sink_compute_bpp(to_intel_connector(connector),
11856 pipe_config);
4e53c2e0
DV		 11857 }
11858
11859 return bpp;
11860}
11861
644db711
DV		 11862static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11863{
11864 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11865 "type: 0x%x flags: 0x%x\n",
1342830c 11866 mode->crtc_clock,
644db711
DV		 11867 mode->crtc_hdisplay, mode->crtc_hsync_start,
11868 mode->crtc_hsync_end, mode->crtc_htotal,
11869 mode->crtc_vdisplay, mode->crtc_vsync_start,
11870 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11871}
11872
c0b03411 11873static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11874 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11875 const char *context)
11876{
6a60cd87
CK		 11877 struct drm_device *dev = crtc->base.dev;
11878 struct drm_plane *plane;
11879 struct intel_plane *intel_plane;
11880 struct intel_plane_state *state;
11881 struct drm_framebuffer *fb;
11882
11883 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11884 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11885
11886 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11887 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11888 pipe_config->pipe_bpp, pipe_config->dither);
11889 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11890 pipe_config->has_pch_encoder,
11891 pipe_config->fdi_lanes,
11892 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11893 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11894 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11895 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11896 pipe_config->has_dp_encoder,
11897 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11898 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11899 pipe_config->dp_m_n.tu);
b95af8be
VK		 11900
11901 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11902 pipe_config->has_dp_encoder,
11903 pipe_config->dp_m2_n2.gmch_m,
11904 pipe_config->dp_m2_n2.gmch_n,
11905 pipe_config->dp_m2_n2.link_m,
11906 pipe_config->dp_m2_n2.link_n,
11907 pipe_config->dp_m2_n2.tu);
11908
55072d19
DV		 11909 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11910 pipe_config->has_audio,
11911 pipe_config->has_infoframe);
11912
c0b03411 11913 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11914 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11915 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11916 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11917 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11918 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11919 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11920 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11921 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11922 crtc->num_scalers,
11923 pipe_config->scaler_state.scaler_users,
11924 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11925 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11926 pipe_config->gmch_pfit.control,
11927 pipe_config->gmch_pfit.pgm_ratios,
11928 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11929 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11930 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11931 pipe_config->pch_pfit.size,
11932 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11933 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11934 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11935
415ff0f6
TU		 11936 if (IS_BROXTON(dev)) {
11937 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11938 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11939 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11940 pipe_config->ddi_pll_sel,
11941 pipe_config->dpll_hw_state.ebb0,
11942 pipe_config->dpll_hw_state.pll0,
11943 pipe_config->dpll_hw_state.pll1,
11944 pipe_config->dpll_hw_state.pll2,
11945 pipe_config->dpll_hw_state.pll3,
11946 pipe_config->dpll_hw_state.pll6,
11947 pipe_config->dpll_hw_state.pll8,
11948 pipe_config->dpll_hw_state.pcsdw12);
11949 } else if (IS_SKYLAKE(dev)) {
11950 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11951 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11952 pipe_config->ddi_pll_sel,
11953 pipe_config->dpll_hw_state.ctrl1,
11954 pipe_config->dpll_hw_state.cfgcr1,
11955 pipe_config->dpll_hw_state.cfgcr2);
11956 } else if (HAS_DDI(dev)) {
11957 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11958 pipe_config->ddi_pll_sel,
11959 pipe_config->dpll_hw_state.wrpll);
11960 } else {
11961 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11962 "fp0: 0x%x, fp1: 0x%x\n",
11963 pipe_config->dpll_hw_state.dpll,
11964 pipe_config->dpll_hw_state.dpll_md,
11965 pipe_config->dpll_hw_state.fp0,
11966 pipe_config->dpll_hw_state.fp1);
11967 }
11968
6a60cd87
CK		 11969 DRM_DEBUG_KMS("planes on this crtc\n");
11970 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11971 intel_plane = to_intel_plane(plane);
11972 if (intel_plane->pipe != crtc->pipe)
11973 continue;
11974
11975 state = to_intel_plane_state(plane->state);
11976 fb = state->base.fb;
11977 if (!fb) {
11978 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11979 "disabled, scaler_id = %d\n",
11980 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11981 plane->base.id, intel_plane->pipe,
11982 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11983 drm_plane_index(plane), state->scaler_id);
11984 continue;
11985 }
11986
11987 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11988 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11989 plane->base.id, intel_plane->pipe,
11990 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11991 drm_plane_index(plane));
11992 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11993 fb->base.id, fb->width, fb->height, fb->pixel_format);
11994 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11995 state->scaler_id,
11996 state->src.x1 >> 16, state->src.y1 >> 16,
11997 drm_rect_width(&state->src) >> 16,
11998 drm_rect_height(&state->src) >> 16,
11999 state->dst.x1, state->dst.y1,
12000 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12001 }
c0b03411
DV		 12002}
12003
5448a00d 12004static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12005{
5448a00d
ACO		 12006 struct drm_device *dev = state->dev;
12007 struct intel_encoder *encoder;
da3ced29 12008 struct drm_connector *connector;
5448a00d 12009 struct drm_connector_state *connector_state;
00f0b378 12010 unsigned int used_ports = 0;
5448a00d 12011 int i;
00f0b378
VS		 12012
12013 /*
12014 * Walk the connector list instead of the encoder
12015 * list to detect the problem on ddi platforms
12016 * where there's just one encoder per digital port.
12017 */
da3ced29 12018 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12019 if (!connector_state->best_encoder)
00f0b378
VS		 12020 continue;
12021
5448a00d
ACO		 12022 encoder = to_intel_encoder(connector_state->best_encoder);
12023
12024 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12025
12026 switch (encoder->type) {
12027 unsigned int port_mask;
12028 case INTEL_OUTPUT_UNKNOWN:
12029 if (WARN_ON(!HAS_DDI(dev)))
12030 break;
12031 case INTEL_OUTPUT_DISPLAYPORT:
12032 case INTEL_OUTPUT_HDMI:
12033 case INTEL_OUTPUT_EDP:
12034 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12035
12036 /* the same port mustn't appear more than once */
12037 if (used_ports & port_mask)
12038 return false;
12039
12040 used_ports |= port_mask;
12041 default:
12042 break;
12043 }
12044 }
12045
12046 return true;
12047}
12048
83a57153
ACO		 12049static void
12050clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12051{
12052 struct drm_crtc_state tmp_state;
663a3640 12053 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12054 struct intel_dpll_hw_state dpll_hw_state;
12055 enum intel_dpll_id shared_dpll;
8504c74c 12056 uint32_t ddi_pll_sel;
83a57153 12057
7546a384
ACO		 12058 /* FIXME: before the switch to atomic started, a new pipe_config was
12059 * kzalloc'd. Code that depends on any field being zero should be
12060 * fixed, so that the crtc_state can be safely duplicated. For now,
12061 * only fields that are know to not cause problems are preserved. */
12062
83a57153 12063 tmp_state = crtc_state->base;
663a3640 12064 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12065 shared_dpll = crtc_state->shared_dpll;
12066 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12067 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12068
83a57153 12069 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12070
83a57153 12071 crtc_state->base = tmp_state;
663a3640 12072 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12073 crtc_state->shared_dpll = shared_dpll;
12074 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12075 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12076}
12077
548ee15b 12078static int
b8cecdf5 12079intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12080 struct intel_crtc_state *pipe_config)
ee7b9f93 12081{
b359283a 12082 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12083 struct intel_encoder *encoder;
da3ced29 12084 struct drm_connector *connector;
0b901879 12085 struct drm_connector_state *connector_state;
d328c9d7 12086 int base_bpp, ret = -EINVAL;
0b901879 12087 int i;
e29c22c0 12088 bool retry = true;
ee7b9f93 12089
83a57153 12090 clear_intel_crtc_state(pipe_config);
7758a113 12091
e143a21c
DV		 12092 pipe_config->cpu_transcoder =
12093 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12094
2960bc9c
ID		 12095 /*
12096 * Sanitize sync polarity flags based on requested ones. If neither
12097 * positive or negative polarity is requested, treat this as meaning
12098 * negative polarity.
12099 */
2d112de7 12100 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12101 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12102 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12103
2d112de7 12104 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12105 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12106 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12107
050f7aeb
DV		 12108 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12109 * plane pixel format and any sink constraints into account. Returns the
12110 * source plane bpp so that dithering can be selected on mismatches
12111 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12112 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12113 pipe_config);
12114 if (base_bpp < 0)
4e53c2e0
DV		 12115 goto fail;
12116
e41a56be
VS		 12117 /*
12118 * Determine the real pipe dimensions. Note that stereo modes can
12119 * increase the actual pipe size due to the frame doubling and
12120 * insertion of additional space for blanks between the frame. This
12121 * is stored in the crtc timings. We use the requested mode to do this
12122 * computation to clearly distinguish it from the adjusted mode, which
12123 * can be changed by the connectors in the below retry loop.
12124 */
2d112de7 12125 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12126 &pipe_config->pipe_src_w,
12127 &pipe_config->pipe_src_h);
e41a56be 12128
e29c22c0 12129encoder_retry:
ef1b460d 12130 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12131 pipe_config->port_clock = 0;
ef1b460d 12132 pipe_config->pixel_multiplier = 1;
ff9a6750 12133
135c81b8 12134 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12135 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12136 CRTC_STEREO_DOUBLE);
135c81b8 12137
7758a113
DV		 12138 /* Pass our mode to the connectors and the CRTC to give them a chance to
12139 * adjust it according to limitations or connector properties, and also
12140 * a chance to reject the mode entirely.
47f1c6c9 12141 */
da3ced29 12142 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12143 if (connector_state->crtc != crtc)
7758a113 12144 continue;
7ae89233 12145
0b901879
ACO		 12146 encoder = to_intel_encoder(connector_state->best_encoder);
12147
efea6e8e
DV		 12148 if (!(encoder->compute_config(encoder, pipe_config))) {
12149 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12150 goto fail;
12151 }
ee7b9f93 12152 }
47f1c6c9 12153
ff9a6750
DV		 12154 /* Set default port clock if not overwritten by the encoder. Needs to be
12155 * done afterwards in case the encoder adjusts the mode. */
12156 if (!pipe_config->port_clock)
2d112de7 12157 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12158 * pipe_config->pixel_multiplier;
ff9a6750 12159
a43f6e0f 12160 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12161 if (ret < 0) {
7758a113
DV		 12162 DRM_DEBUG_KMS("CRTC fixup failed\n");
12163 goto fail;
ee7b9f93 12164 }
e29c22c0
DV		 12165
12166 if (ret == RETRY) {
12167 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12168 ret = -EINVAL;
12169 goto fail;
12170 }
12171
12172 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12173 retry = false;
12174 goto encoder_retry;
12175 }
12176
d328c9d7 12177 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12178 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12179 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12180
cdba954e
ACO		 12181 /* Check if we need to force a modeset */
12182 if (pipe_config->has_audio !=
85a96e7a 12183 to_intel_crtc_state(crtc->state)->has_audio) {
cdba954e 12184 pipe_config->base.mode_changed = true;
85a96e7a
ML		 12185 ret = drm_atomic_add_affected_planes(state, crtc);
12186 }
cdba954e
ACO		 12187
12188 /*
12189 * Note we have an issue here with infoframes: current code
12190 * only updates them on the full mode set path per hw
12191 * requirements. So here we should be checking for any
12192 * required changes and forcing a mode set.
12193 */
7758a113 12194fail:
548ee15b 12195 return ret;
ee7b9f93 12196}
47f1c6c9 12197
ea9d758d 12198static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12199{
ea9d758d 12200 struct drm_encoder *encoder;
f6e5b160 12201 struct drm_device *dev = crtc->dev;
f6e5b160 12202
ea9d758d
DV		 12203 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12204 if (encoder->crtc == crtc)
12205 return true;
12206
12207 return false;
12208}
12209
12210static void
0a9ab303 12211intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12212{
0a9ab303 12213 struct drm_device *dev = state->dev;
ea9d758d 12214 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12215 struct drm_crtc *crtc;
12216 struct drm_crtc_state *crtc_state;
ea9d758d
DV		 12217 struct drm_connector *connector;
12218
de419ab6 12219 intel_shared_dpll_commit(state);
ba41c0de 12220
b2784e15 12221 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12222 if (!intel_encoder->base.crtc)
12223 continue;
12224
69024de8
ML		 12225 crtc = intel_encoder->base.crtc;
12226 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12227 if (!crtc_state || !needs_modeset(crtc->state))
12228 continue;
ea9d758d 12229
69024de8 12230 intel_encoder->connectors_active = false;
ea9d758d
DV		 12231 }
12232
3cb480bc 12233 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
f7217905 12234 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12235
7668851f 12236 /* Double check state. */
0a9ab303
ACO		 12237 for_each_crtc(dev, crtc) {
12238 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12239
12240 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12241
12242 /* Update hwmode for vblank functions */
12243 if (crtc->state->active)
12244 crtc->hwmode = crtc->state->adjusted_mode;
12245 else
12246 crtc->hwmode.crtc_clock = 0;
ea9d758d
DV		 12247 }
12248
12249 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12250 if (!connector->encoder || !connector->encoder->crtc)
12251 continue;
12252
69024de8
ML		 12253 crtc = connector->encoder->crtc;
12254 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12255 if (!crtc_state || !needs_modeset(crtc->state))
12256 continue;
ea9d758d 12257
53d9f4e9 12258 if (crtc->state->active) {
69024de8
ML		 12259 struct drm_property *dpms_property =
12260 dev->mode_config.dpms_property;
68d34720 12261
69024de8
ML		 12262 connector->dpms = DRM_MODE_DPMS_ON;
12263 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12264
69024de8
ML		 12265 intel_encoder = to_intel_encoder(connector->encoder);
12266 intel_encoder->connectors_active = true;
12267 } else
12268 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12269 }
ea9d758d
DV		 12270}
12271
3bd26263 12272static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12273{
3bd26263 12274 int diff;
f1f644dc
JB		 12275
12276 if (clock1 == clock2)
12277 return true;
12278
12279 if (!clock1 || !clock2)
12280 return false;
12281
12282 diff = abs(clock1 - clock2);
12283
12284 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12285 return true;
12286
12287 return false;
12288}
12289
25c5b266
DV		 12290#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12291 list_for_each_entry((intel_crtc), \
12292 &(dev)->mode_config.crtc_list, \
12293 base.head) \
0973f18f 12294 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12295
0e8ffe1b 12296static bool
2fa2fe9a 12297intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12298 struct intel_crtc_state *current_config,
12299 struct intel_crtc_state *pipe_config)
0e8ffe1b 12300{
66e985c0
DV		 12301#define PIPE_CONF_CHECK_X(name) \
12302 if (current_config->name != pipe_config->name) { \
12303 DRM_ERROR("mismatch in " #name " " \
12304 "(expected 0x%08x, found 0x%08x)\n", \
12305 current_config->name, \
12306 pipe_config->name); \
12307 return false; \
12308 }
12309
08a24034
DV		 12310#define PIPE_CONF_CHECK_I(name) \
12311 if (current_config->name != pipe_config->name) { \
12312 DRM_ERROR("mismatch in " #name " " \
12313 "(expected %i, found %i)\n", \
12314 current_config->name, \
12315 pipe_config->name); \
12316 return false; \
88adfff1
DV		 12317 }
12318
b95af8be
VK		 12319/* This is required for BDW+ where there is only one set of registers for
12320 * switching between high and low RR.
12321 * This macro can be used whenever a comparison has to be made between one
12322 * hw state and multiple sw state variables.
12323 */
12324#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12325 if ((current_config->name != pipe_config->name) && \
12326 (current_config->alt_name != pipe_config->name)) { \
12327 DRM_ERROR("mismatch in " #name " " \
12328 "(expected %i or %i, found %i)\n", \
12329 current_config->name, \
12330 current_config->alt_name, \
12331 pipe_config->name); \
12332 return false; \
12333 }
12334
1bd1bd80
DV		 12335#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12336 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12337 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12338 "(expected %i, found %i)\n", \
12339 current_config->name & (mask), \
12340 pipe_config->name & (mask)); \
12341 return false; \
12342 }
12343
5e550656
VS		 12344#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12345 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12346 DRM_ERROR("mismatch in " #name " " \
12347 "(expected %i, found %i)\n", \
12348 current_config->name, \
12349 pipe_config->name); \
12350 return false; \
12351 }
12352
bb760063
DV		 12353#define PIPE_CONF_QUIRK(quirk) \
12354 ((current_config->quirks | pipe_config->quirks) & (quirk))
12355
eccb140b
DV		 12356 PIPE_CONF_CHECK_I(cpu_transcoder);
12357
08a24034
DV		 12358 PIPE_CONF_CHECK_I(has_pch_encoder);
12359 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12360 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12361 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12362 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12363 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12364 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12365
eb14cb74 12366 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12367
12368 if (INTEL_INFO(dev)->gen < 8) {
12369 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12370 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12371 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12372 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12373 PIPE_CONF_CHECK_I(dp_m_n.tu);
12374
12375 if (current_config->has_drrs) {
12376 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12377 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12378 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12379 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12380 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12381 }
12382 } else {
12383 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12384 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12385 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12386 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12387 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12388 }
eb14cb74 12389
2d112de7
ACO		 12390 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12391 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12392 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12393 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12394 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12395 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12396
2d112de7
ACO		 12397 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12398 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12399 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12400 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12401 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12402 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12403
c93f54cf 12404 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12405 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12406 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12407 IS_VALLEYVIEW(dev))
12408 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12409 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12410
9ed109a7
DV		 12411 PIPE_CONF_CHECK_I(has_audio);
12412
2d112de7 12413 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12414 DRM_MODE_FLAG_INTERLACE);
12415
bb760063 12416 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12417 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12418 DRM_MODE_FLAG_PHSYNC);
2d112de7 12419 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12420 DRM_MODE_FLAG_NHSYNC);
2d112de7 12421 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12422 DRM_MODE_FLAG_PVSYNC);
2d112de7 12423 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12424 DRM_MODE_FLAG_NVSYNC);
12425 }
045ac3b5 12426
37327abd
VS		 12427 PIPE_CONF_CHECK_I(pipe_src_w);
12428 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12429
9953599b
DV		 12430 /*
12431 * FIXME: BIOS likes to set up a cloned config with lvds+external
12432 * screen. Since we don't yet re-compute the pipe config when moving
12433 * just the lvds port away to another pipe the sw tracking won't match.
12434 *
12435 * Proper atomic modesets with recomputed global state will fix this.
12436 * Until then just don't check gmch state for inherited modes.
12437 */
12438 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12439 PIPE_CONF_CHECK_I(gmch_pfit.control);
12440 /* pfit ratios are autocomputed by the hw on gen4+ */
12441 if (INTEL_INFO(dev)->gen < 4)
12442 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12443 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12444 }
12445
fd4daa9c
CW		 12446 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12447 if (current_config->pch_pfit.enabled) {
12448 PIPE_CONF_CHECK_I(pch_pfit.pos);
12449 PIPE_CONF_CHECK_I(pch_pfit.size);
12450 }
2fa2fe9a 12451
a1b2278e
CK		 12452 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12453
e59150dc
JB		 12454 /* BDW+ don't expose a synchronous way to read the state */
12455 if (IS_HASWELL(dev))
12456 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12457
282740f7
VS		 12458 PIPE_CONF_CHECK_I(double_wide);
12459
26804afd
DV		 12460 PIPE_CONF_CHECK_X(ddi_pll_sel);
12461
c0d43d62 12462 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12463 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12464 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12465 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12466 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12467 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12468 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12469 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12470 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12471
42571aef
VS		 12472 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12473 PIPE_CONF_CHECK_I(pipe_bpp);
12474
2d112de7 12475 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12476 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12477
66e985c0 12478#undef PIPE_CONF_CHECK_X
08a24034 12479#undef PIPE_CONF_CHECK_I
b95af8be 12480#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12481#undef PIPE_CONF_CHECK_FLAGS
5e550656 12482#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12483#undef PIPE_CONF_QUIRK
88adfff1 12484
0e8ffe1b
DV		 12485 return true;
12486}
12487
08db6652
DL		 12488static void check_wm_state(struct drm_device *dev)
12489{
12490 struct drm_i915_private *dev_priv = dev->dev_private;
12491 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12492 struct intel_crtc *intel_crtc;
12493 int plane;
12494
12495 if (INTEL_INFO(dev)->gen < 9)
12496 return;
12497
12498 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12499 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12500
12501 for_each_intel_crtc(dev, intel_crtc) {
12502 struct skl_ddb_entry *hw_entry, *sw_entry;
12503 const enum pipe pipe = intel_crtc->pipe;
12504
12505 if (!intel_crtc->active)
12506 continue;
12507
12508 /* planes */
dd740780 12509 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12510 hw_entry = &hw_ddb.plane[pipe][plane];
12511 sw_entry = &sw_ddb->plane[pipe][plane];
12512
12513 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12514 continue;
12515
12516 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12517 "(expected (%u,%u), found (%u,%u))\n",
12518 pipe_name(pipe), plane + 1,
12519 sw_entry->start, sw_entry->end,
12520 hw_entry->start, hw_entry->end);
12521 }
12522
12523 /* cursor */
12524 hw_entry = &hw_ddb.cursor[pipe];
12525 sw_entry = &sw_ddb->cursor[pipe];
12526
12527 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12528 continue;
12529
12530 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12531 "(expected (%u,%u), found (%u,%u))\n",
12532 pipe_name(pipe),
12533 sw_entry->start, sw_entry->end,
12534 hw_entry->start, hw_entry->end);
12535 }
12536}
12537
91d1b4bd
DV		 12538static void
12539check_connector_state(struct drm_device *dev)
8af6cf88 12540{
8af6cf88
DV		 12541 struct intel_connector *connector;
12542
3a3371ff 12543 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12544 /* This also checks the encoder/connector hw state with the
12545 * ->get_hw_state callbacks. */
12546 intel_connector_check_state(connector);
12547
e2c719b7 12548 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12549 "connector's staged encoder doesn't match current encoder\n");
12550 }
91d1b4bd
DV		 12551}
12552
12553static void
12554check_encoder_state(struct drm_device *dev)
12555{
12556 struct intel_encoder *encoder;
12557 struct intel_connector *connector;
8af6cf88 12558
b2784e15 12559 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12560 bool enabled = false;
12561 bool active = false;
12562 enum pipe pipe, tracked_pipe;
12563
12564 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12565 encoder->base.base.id,
8e329a03 12566 encoder->base.name);
8af6cf88 12567
e2c719b7 12568 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12569 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12570 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12571 "encoder's active_connectors set, but no crtc\n");
12572
3a3371ff 12573 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12574 if (connector->base.encoder != &encoder->base)
12575 continue;
12576 enabled = true;
12577 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12578 active = true;
12579 }
0e32b39c
DA		 12580 /*
12581 * for MST connectors if we unplug the connector is gone
12582 * away but the encoder is still connected to a crtc
12583 * until a modeset happens in response to the hotplug.
12584 */
12585 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12586 continue;
12587
e2c719b7 12588 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12589 "encoder's enabled state mismatch "
12590 "(expected %i, found %i)\n",
12591 !!encoder->base.crtc, enabled);
e2c719b7 12592 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12593 "active encoder with no crtc\n");
12594
e2c719b7 12595 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12596 "encoder's computed active state doesn't match tracked active state "
12597 "(expected %i, found %i)\n", active, encoder->connectors_active);
12598
12599 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12600 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12601 "encoder's hw state doesn't match sw tracking "
12602 "(expected %i, found %i)\n",
12603 encoder->connectors_active, active);
12604
12605 if (!encoder->base.crtc)
12606 continue;
12607
12608 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12609 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12610 "active encoder's pipe doesn't match"
12611 "(expected %i, found %i)\n",
12612 tracked_pipe, pipe);
12613
12614 }
91d1b4bd
DV		 12615}
12616
12617static void
12618check_crtc_state(struct drm_device *dev)
12619{
fbee40df 12620 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12621 struct intel_crtc *crtc;
12622 struct intel_encoder *encoder;
5cec258b 12623 struct intel_crtc_state pipe_config;
8af6cf88 12624
d3fcc808 12625 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12626 bool enabled = false;
12627 bool active = false;
12628
045ac3b5
JB		 12629 memset(&pipe_config, 0, sizeof(pipe_config));
12630
8af6cf88
DV		 12631 DRM_DEBUG_KMS("[CRTC:%d]\n",
12632 crtc->base.base.id);
12633
83d65738 12634 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12635 "active crtc, but not enabled in sw tracking\n");
12636
b2784e15 12637 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12638 if (encoder->base.crtc != &crtc->base)
12639 continue;
12640 enabled = true;
12641 if (encoder->connectors_active)
12642 active = true;
12643 }
6c49f241 12644
e2c719b7 12645 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12646 "crtc's computed active state doesn't match tracked active state "
12647 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12648 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12649 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12650 "(expected %i, found %i)\n", enabled,
12651 crtc->base.state->enable);
8af6cf88 12652
0e8ffe1b
DV		 12653 active = dev_priv->display.get_pipe_config(crtc,
12654 &pipe_config);
d62cf62a 12655
b6b5d049
VS		 12656 /* hw state is inconsistent with the pipe quirk */
12657 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12658 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12659 active = crtc->active;
12660
b2784e15 12661 for_each_intel_encoder(dev, encoder) {
3eaba51c 12662 enum pipe pipe;
6c49f241
DV		 12663 if (encoder->base.crtc != &crtc->base)
12664 continue;
1d37b689 12665 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12666 encoder->get_config(encoder, &pipe_config);
12667 }
12668
e2c719b7 12669 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12670 "crtc active state doesn't match with hw state "
12671 "(expected %i, found %i)\n", crtc->active, active);
12672
53d9f4e9
ML		 12673 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12674 "transitional active state does not match atomic hw state "
12675 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12676
c0b03411 12677 if (active &&
6e3c9717 12678 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12679 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12680 intel_dump_pipe_config(crtc, &pipe_config,
12681 "[hw state]");
6e3c9717 12682 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12683 "[sw state]");
12684 }
8af6cf88
DV		 12685 }
12686}
12687
91d1b4bd
DV		 12688static void
12689check_shared_dpll_state(struct drm_device *dev)
12690{
fbee40df 12691 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12692 struct intel_crtc *crtc;
12693 struct intel_dpll_hw_state dpll_hw_state;
12694 int i;
5358901f
DV		 12695
12696 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12697 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12698 int enabled_crtcs = 0, active_crtcs = 0;
12699 bool active;
12700
12701 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12702
12703 DRM_DEBUG_KMS("%s\n", pll->name);
12704
12705 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12706
e2c719b7 12707 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12708 "more active pll users than references: %i vs %i\n",
3e369b76 12709 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12710 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12711 "pll in active use but not on in sw tracking\n");
e2c719b7 12712 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12713 "pll in on but not on in use in sw tracking\n");
e2c719b7 12714 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12715 "pll on state mismatch (expected %i, found %i)\n",
12716 pll->on, active);
12717
d3fcc808 12718 for_each_intel_crtc(dev, crtc) {
83d65738 12719 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12720 enabled_crtcs++;
12721 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12722 active_crtcs++;
12723 }
e2c719b7 12724 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12725 "pll active crtcs mismatch (expected %i, found %i)\n",
12726 pll->active, active_crtcs);
e2c719b7 12727 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12728 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12729 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12730
e2c719b7 12731 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12732 sizeof(dpll_hw_state)),
12733 "pll hw state mismatch\n");
5358901f 12734 }
8af6cf88
DV		 12735}
12736
91d1b4bd
DV		 12737void
12738intel_modeset_check_state(struct drm_device *dev)
12739{
08db6652 12740 check_wm_state(dev);
91d1b4bd
DV		 12741 check_connector_state(dev);
12742 check_encoder_state(dev);
12743 check_crtc_state(dev);
12744 check_shared_dpll_state(dev);
12745}
12746
5cec258b 12747void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12748 int dotclock)
12749{
12750 /*
12751 * FDI already provided one idea for the dotclock.
12752 * Yell if the encoder disagrees.
12753 */
2d112de7 12754 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12755 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12756 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12757}
12758
80715b2f
VS		 12759static void update_scanline_offset(struct intel_crtc *crtc)
12760{
12761 struct drm_device *dev = crtc->base.dev;
12762
12763 /*
12764 * The scanline counter increments at the leading edge of hsync.
12765 *
12766 * On most platforms it starts counting from vtotal-1 on the
12767 * first active line. That means the scanline counter value is
12768 * always one less than what we would expect. Ie. just after
12769 * start of vblank, which also occurs at start of hsync (on the
12770 * last active line), the scanline counter will read vblank_start-1.
12771 *
12772 * On gen2 the scanline counter starts counting from 1 instead
12773 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12774 * to keep the value positive), instead of adding one.
12775 *
12776 * On HSW+ the behaviour of the scanline counter depends on the output
12777 * type. For DP ports it behaves like most other platforms, but on HDMI
12778 * there's an extra 1 line difference. So we need to add two instead of
12779 * one to the value.
12780 */
12781 if (IS_GEN2(dev)) {
6e3c9717 12782 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12783 int vtotal;
12784
12785 vtotal = mode->crtc_vtotal;
12786 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12787 vtotal /= 2;
12788
12789 crtc->scanline_offset = vtotal - 1;
12790 } else if (HAS_DDI(dev) &&
409ee761 12791 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12792 crtc->scanline_offset = 2;
12793 } else
12794 crtc->scanline_offset = 1;
12795}
12796
c347a676 12797static int intel_modeset_setup_plls(struct drm_atomic_state *state)
ed6739ef 12798{
225da59b 12799 struct drm_device *dev = state->dev;
ed6739ef 12800 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12801 unsigned clear_pipes = 0;
ed6739ef 12802 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12803 struct intel_crtc_state *intel_crtc_state;
12804 struct drm_crtc *crtc;
12805 struct drm_crtc_state *crtc_state;
ed6739ef 12806 int ret = 0;
0a9ab303 12807 int i;
ed6739ef
ACO		 12808
12809 if (!dev_priv->display.crtc_compute_clock)
12810 return 0;
12811
0a9ab303
ACO		 12812 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12813 intel_crtc = to_intel_crtc(crtc);
4978cc93 12814 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12815
4978cc93 12816 if (needs_modeset(crtc_state)) {
0a9ab303 12817 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12818 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12819 }
0a9ab303
ACO		 12820 }
12821
de419ab6
ML		 12822 if (clear_pipes) {
12823 struct intel_shared_dpll_config *shared_dpll =
12824 intel_atomic_get_shared_dpll_state(state);
12825
12826 for (i = 0; i < dev_priv->num_shared_dpll; i++)
12827 shared_dpll[i].crtc_mask &= ~clear_pipes;
12828 }
ed6739ef 12829
0a9ab303
ACO		 12830 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12831 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12832 continue;
12833
0a9ab303
ACO		 12834 intel_crtc = to_intel_crtc(crtc);
12835 intel_crtc_state = to_intel_crtc_state(crtc_state);
12836
ed6739ef 12837 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12838 intel_crtc_state);
de419ab6
ML		 12839 if (ret)
12840 return ret;
ed6739ef
ACO		 12841 }
12842
ed6739ef
ACO		 12843 return ret;
12844}
12845
99d736a2
ML		 12846/*
12847 * This implements the workaround described in the "notes" section of the mode
12848 * set sequence documentation. When going from no pipes or single pipe to
12849 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12850 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12851 */
12852static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12853{
12854 struct drm_crtc_state *crtc_state;
12855 struct intel_crtc *intel_crtc;
12856 struct drm_crtc *crtc;
12857 struct intel_crtc_state *first_crtc_state = NULL;
12858 struct intel_crtc_state *other_crtc_state = NULL;
12859 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12860 int i;
12861
12862 /* look at all crtc's that are going to be enabled in during modeset */
12863 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12864 intel_crtc = to_intel_crtc(crtc);
12865
12866 if (!crtc_state->active || !needs_modeset(crtc_state))
12867 continue;
12868
12869 if (first_crtc_state) {
12870 other_crtc_state = to_intel_crtc_state(crtc_state);
12871 break;
12872 } else {
12873 first_crtc_state = to_intel_crtc_state(crtc_state);
12874 first_pipe = intel_crtc->pipe;
12875 }
12876 }
12877
12878 /* No workaround needed? */
12879 if (!first_crtc_state)
12880 return 0;
12881
12882 /* w/a possibly needed, check how many crtc's are already enabled. */
12883 for_each_intel_crtc(state->dev, intel_crtc) {
12884 struct intel_crtc_state *pipe_config;
12885
12886 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12887 if (IS_ERR(pipe_config))
12888 return PTR_ERR(pipe_config);
12889
12890 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12891
12892 if (!pipe_config->base.active ||
12893 needs_modeset(&pipe_config->base))
12894 continue;
12895
12896 /* 2 or more enabled crtcs means no need for w/a */
12897 if (enabled_pipe != INVALID_PIPE)
12898 return 0;
12899
12900 enabled_pipe = intel_crtc->pipe;
12901 }
12902
12903 if (enabled_pipe != INVALID_PIPE)
12904 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12905 else if (other_crtc_state)
12906 other_crtc_state->hsw_workaround_pipe = first_pipe;
12907
12908 return 0;
12909}
12910
054518dd 12911/* Code that should eventually be part of atomic_check() */
c347a676 12912static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12913{
12914 struct drm_device *dev = state->dev;
12915 int ret;
12916
b359283a
ML		 12917 if (!check_digital_port_conflicts(state)) {
12918 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12919 return -EINVAL;
12920 }
12921
054518dd
ACO		 12922 /*
12923 * See if the config requires any additional preparation, e.g.
12924 * to adjust global state with pipes off. We need to do this
12925 * here so we can get the modeset_pipe updated config for the new
12926 * mode set on this crtc. For other crtcs we need to use the
12927 * adjusted_mode bits in the crtc directly.
12928 */
b432e5cf
VS		 12929 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev) || IS_BROADWELL(dev)) {
12930 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev))
12931 ret = valleyview_modeset_global_pipes(state);
12932 else
12933 ret = broadwell_modeset_global_pipes(state);
12934
054518dd
ACO		 12935 if (ret)
12936 return ret;
12937 }
12938
99d736a2 12939 ret = intel_modeset_setup_plls(state);
054518dd
ACO		 12940 if (ret)
12941 return ret;
12942
99d736a2
ML		 12943 if (IS_HASWELL(dev))
12944 ret = haswell_mode_set_planes_workaround(state);
12945
12946 return ret;
c347a676
ACO		 12947}
12948
12949static int
12950intel_modeset_compute_config(struct drm_atomic_state *state)
12951{
12952 struct drm_crtc *crtc;
12953 struct drm_crtc_state *crtc_state;
12954 int ret, i;
12955
12956 ret = drm_atomic_helper_check_modeset(state->dev, state);
054518dd
ACO		 12957 if (ret)
12958 return ret;
12959
c347a676
ACO		 12960 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12961 if (!crtc_state->enable &&
12962 WARN_ON(crtc_state->active))
12963 crtc_state->active = false;
12964
12965 if (!crtc_state->enable)
12966 continue;
12967
b359283a
ML		 12968 if (!needs_modeset(crtc_state)) {
12969 ret = drm_atomic_add_affected_connectors(state, crtc);
12970 if (ret)
12971 return ret;
12972 }
12973
12974 ret = intel_modeset_pipe_config(crtc,
12975 to_intel_crtc_state(crtc_state));
c347a676
ACO		 12976 if (ret)
12977 return ret;
12978
12979 intel_dump_pipe_config(to_intel_crtc(crtc),
12980 to_intel_crtc_state(crtc_state),
12981 "[modeset]");
12982 }
12983
12984 ret = intel_modeset_checks(state);
12985 if (ret)
12986 return ret;
12987
12988 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 12989}
12990
c72d969b 12991static int __intel_set_mode(struct drm_atomic_state *state)
a6778b3c 12992{
c72d969b 12993 struct drm_device *dev = state->dev;
fbee40df 12994 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 12995 struct drm_crtc *crtc;
12996 struct drm_crtc_state *crtc_state;
c0c36b94 12997 int ret = 0;
0a9ab303 12998 int i;
a6778b3c 12999
d4afb8cc
ACO		 13000 ret = drm_atomic_helper_prepare_planes(dev, state);
13001 if (ret)
13002 return ret;
13003
1c5e19f8
ML		 13004 drm_atomic_helper_swap_state(dev, state);
13005
0a9ab303 13006 for_each_crtc_in_state(state, crtc, crtc_state, i) {
1c5e19f8 13007 if (!needs_modeset(crtc->state) || !crtc_state->active)
0a9ab303 13008 continue;
460da916 13009
69024de8
ML		 13010 intel_crtc_disable_planes(crtc);
13011 dev_priv->display.crtc_disable(crtc);
b8cecdf5 13012 }
7758a113 13013
ea9d758d
DV		 13014 /* Only after disabling all output pipelines that will be changed can we
13015 * update the the output configuration. */
0a9ab303 13016 intel_modeset_update_state(state);
f6e5b160 13017
a821fc46
ACO		 13018 /* The state has been swaped above, so state actually contains the
13019 * old state now. */
13020
304603f4 13021 modeset_update_crtc_power_domains(state);
47fab737 13022
a6778b3c 13023 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13024 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5ac1c4bc
ML		 13025 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13026
53d9f4e9 13027 if (!needs_modeset(crtc->state) || !crtc->state->active)
0a9ab303
ACO		 13028 continue;
13029
13030 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 13031
0a9ab303
ACO		 13032 dev_priv->display.crtc_enable(crtc);
13033 intel_crtc_enable_planes(crtc);
80715b2f 13034 }
a6778b3c 13035
a6778b3c 13036 /* FIXME: add subpixel order */
83a57153 13037
d4afb8cc
ACO		 13038 drm_atomic_helper_cleanup_planes(dev, state);
13039
2bfb4627
ACO		 13040 drm_atomic_state_free(state);
13041
9eb45f22 13042 return 0;
f6e5b160
CW		 13043}
13044
568c634a 13045static int intel_set_mode_checked(struct drm_atomic_state *state)
f30da187 13046{
568c634a 13047 struct drm_device *dev = state->dev;
f30da187
DV		 13048 int ret;
13049
568c634a 13050 ret = __intel_set_mode(state);
f30da187 13051 if (ret == 0)
568c634a 13052 intel_modeset_check_state(dev);
f30da187
DV		 13053
13054 return ret;
13055}
13056
568c634a 13057static int intel_set_mode(struct drm_atomic_state *state)
7f27126e 13058{
568c634a 13059 int ret;
83a57153 13060
568c634a 13061 ret = intel_modeset_compute_config(state);
83a57153 13062 if (ret)
568c634a 13063 return ret;
7f27126e 13064
568c634a 13065 return intel_set_mode_checked(state);
7f27126e
JB		 13066}
13067
c0c36b94
CW		 13068void intel_crtc_restore_mode(struct drm_crtc *crtc)
13069{
83a57153
ACO		 13070 struct drm_device *dev = crtc->dev;
13071 struct drm_atomic_state *state;
4be07317 13072 struct intel_crtc *intel_crtc;
83a57153
ACO		 13073 struct intel_encoder *encoder;
13074 struct intel_connector *connector;
13075 struct drm_connector_state *connector_state;
4be07317 13076 struct intel_crtc_state *crtc_state;
2bfb4627 13077 int ret;
83a57153
ACO		 13078
13079 state = drm_atomic_state_alloc(dev);
13080 if (!state) {
13081 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13082 crtc->base.id);
13083 return;
13084 }
13085
13086 state->acquire_ctx = dev->mode_config.acquire_ctx;
13087
13088 /* The force restore path in the HW readout code relies on the staged
13089 * config still keeping the user requested config while the actual
13090 * state has been overwritten by the configuration read from HW. We
13091 * need to copy the staged config to the atomic state, otherwise the
13092 * mode set will just reapply the state the HW is already in. */
13093 for_each_intel_encoder(dev, encoder) {
13094 if (&encoder->new_crtc->base != crtc)
13095 continue;
13096
13097 for_each_intel_connector(dev, connector) {
13098 if (connector->new_encoder != encoder)
13099 continue;
13100
13101 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13102 if (IS_ERR(connector_state)) {
13103 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13104 connector->base.base.id,
13105 connector->base.name,
13106 PTR_ERR(connector_state));
13107 continue;
13108 }
13109
13110 connector_state->crtc = crtc;
13111 connector_state->best_encoder = &encoder->base;
13112 }
13113 }
13114
4be07317
ACO		 13115 for_each_intel_crtc(dev, intel_crtc) {
13116 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
13117 continue;
13118
13119 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
13120 if (IS_ERR(crtc_state)) {
13121 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13122 intel_crtc->base.base.id,
13123 PTR_ERR(crtc_state));
13124 continue;
13125 }
13126
49d6fa21
ML		 13127 crtc_state->base.active = crtc_state->base.enable =
13128 intel_crtc->new_enabled;
8c7b5ccb
ACO		 13129
13130 if (&intel_crtc->base == crtc)
13131 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 13132 }
13133
d3a40d1b
ACO		 13134 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13135 crtc->primary->fb, crtc->x, crtc->y);
13136
568c634a 13137 ret = intel_set_mode(state);
2bfb4627
ACO		 13138 if (ret)
13139 drm_atomic_state_free(state);
c0c36b94
CW		 13140}
13141
25c5b266
DV		 13142#undef for_each_intel_crtc_masked
13143
b7885264
ACO		 13144static bool intel_connector_in_mode_set(struct intel_connector *connector,
13145 struct drm_mode_set *set)
13146{
13147 int ro;
13148
13149 for (ro = 0; ro < set->num_connectors; ro++)
13150 if (set->connectors[ro] == &connector->base)
13151 return true;
13152
13153 return false;
13154}
13155
2e431051 13156static int
9a935856
DV		 13157intel_modeset_stage_output_state(struct drm_device *dev,
13158 struct drm_mode_set *set,
944b0c76 13159 struct drm_atomic_state *state)
50f56119 13160{
9a935856 13161 struct intel_connector *connector;
d5432a9d 13162 struct drm_connector *drm_connector;
944b0c76 13163 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13164 struct drm_crtc *crtc;
13165 struct drm_crtc_state *crtc_state;
13166 int i, ret;
50f56119 13167
9abdda74 13168 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13169 * of connectors. For paranoia, double-check this. */
13170 WARN_ON(!set->fb && (set->num_connectors != 0));
13171 WARN_ON(set->fb && (set->num_connectors == 0));
13172
3a3371ff 13173 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13174 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13175
d5432a9d
ACO		 13176 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13177 continue;
13178
13179 connector_state =
13180 drm_atomic_get_connector_state(state, &connector->base);
13181 if (IS_ERR(connector_state))
13182 return PTR_ERR(connector_state);
13183
b7885264
ACO		 13184 if (in_mode_set) {
13185 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13186 connector_state->best_encoder =
13187 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13188 }
13189
d5432a9d 13190 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13191 continue;
13192
9a935856
DV		 13193 /* If we disable the crtc, disable all its connectors. Also, if
13194 * the connector is on the changing crtc but not on the new
13195 * connector list, disable it. */
b7885264 13196 if (!set->fb || !in_mode_set) {
d5432a9d 13197 connector_state->best_encoder = NULL;
9a935856
DV		 13198
13199 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13200 connector->base.base.id,
c23cc417 13201 connector->base.name);
9a935856 13202 }
50f56119 13203 }
9a935856 13204 /* connector->new_encoder is now updated for all connectors. */
50f56119 13205
d5432a9d
ACO		 13206 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13207 connector = to_intel_connector(drm_connector);
13208
13209 if (!connector_state->best_encoder) {
13210 ret = drm_atomic_set_crtc_for_connector(connector_state,
13211 NULL);
13212 if (ret)
13213 return ret;
7668851f 13214
50f56119 13215 continue;
d5432a9d 13216 }
50f56119 13217
d5432a9d
ACO		 13218 if (intel_connector_in_mode_set(connector, set)) {
13219 struct drm_crtc *crtc = connector->base.state->crtc;
13220
13221 /* If this connector was in a previous crtc, add it
13222 * to the state. We might need to disable it. */
13223 if (crtc) {
13224 crtc_state =
13225 drm_atomic_get_crtc_state(state, crtc);
13226 if (IS_ERR(crtc_state))
13227 return PTR_ERR(crtc_state);
13228 }
13229
13230 ret = drm_atomic_set_crtc_for_connector(connector_state,
13231 set->crtc);
13232 if (ret)
13233 return ret;
13234 }
50f56119
DV		 13235
13236 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13237 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13238 connector_state->crtc)) {
5e2b584e 13239 return -EINVAL;
50f56119 13240 }
944b0c76 13241
9a935856
DV		 13242 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13243 connector->base.base.id,
c23cc417 13244 connector->base.name,
d5432a9d 13245 connector_state->crtc->base.id);
944b0c76 13246
d5432a9d
ACO		 13247 if (connector_state->best_encoder != &connector->encoder->base)
13248 connector->encoder =
13249 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13250 }
7668851f 13251
d5432a9d 13252 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13253 bool has_connectors;
13254
d5432a9d
ACO		 13255 ret = drm_atomic_add_affected_connectors(state, crtc);
13256 if (ret)
13257 return ret;
4be07317 13258
49d6fa21
ML		 13259 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13260 if (has_connectors != crtc_state->enable)
13261 crtc_state->enable =
13262 crtc_state->active = has_connectors;
7668851f
VS		 13263 }
13264
8c7b5ccb
ACO		 13265 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13266 set->fb, set->x, set->y);
13267 if (ret)
13268 return ret;
13269
13270 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13271 if (IS_ERR(crtc_state))
13272 return PTR_ERR(crtc_state);
13273
ce52299c
MR		 13274 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13275 if (ret)
13276 return ret;
8c7b5ccb
ACO		 13277
13278 if (set->num_connectors)
13279 crtc_state->active = true;
13280
2e431051
DV		 13281 return 0;
13282}
13283
13284static int intel_crtc_set_config(struct drm_mode_set *set)
13285{
13286 struct drm_device *dev;
83a57153 13287 struct drm_atomic_state *state = NULL;
2e431051 13288 int ret;
2e431051 13289
8d3e375e
DV		 13290 BUG_ON(!set);
13291 BUG_ON(!set->crtc);
13292 BUG_ON(!set->crtc->helper_private);
2e431051 13293
7e53f3a4
DV		 13294 /* Enforce sane interface api - has been abused by the fb helper. */
13295 BUG_ON(!set->mode && set->fb);
13296 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13297
2e431051
DV		 13298 if (set->fb) {
13299 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13300 set->crtc->base.id, set->fb->base.id,
13301 (int)set->num_connectors, set->x, set->y);
13302 } else {
13303 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13304 }
13305
13306 dev = set->crtc->dev;
13307
83a57153 13308 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13309 if (!state)
13310 return -ENOMEM;
83a57153
ACO		 13311
13312 state->acquire_ctx = dev->mode_config.acquire_ctx;
13313
462a425a 13314 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13315 if (ret)
7cbf41d6 13316 goto out;
2e431051 13317
568c634a
ACO		 13318 ret = intel_modeset_compute_config(state);
13319 if (ret)
7cbf41d6 13320 goto out;
50f52756 13321
1f9954d0
JB		 13322 intel_update_pipe_size(to_intel_crtc(set->crtc));
13323
568c634a 13324 ret = intel_set_mode_checked(state);
2d05eae1 13325 if (ret) {
bf67dfeb
DV		 13326 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13327 set->crtc->base.id, ret);
2d05eae1 13328 }
50f56119 13329
7cbf41d6 13330out:
2bfb4627
ACO		 13331 if (ret)
13332 drm_atomic_state_free(state);
50f56119
DV		 13333 return ret;
13334}
f6e5b160
CW		 13335
13336static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13337 .gamma_set = intel_crtc_gamma_set,
50f56119 13338 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13339 .destroy = intel_crtc_destroy,
13340 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13341 .atomic_duplicate_state = intel_crtc_duplicate_state,
13342 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13343};
13344
5358901f
DV		 13345static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13346 struct intel_shared_dpll *pll,
13347 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13348{
5358901f 13349 uint32_t val;
ee7b9f93 13350
f458ebbc 13351 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13352 return false;
13353
5358901f 13354 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13355 hw_state->dpll = val;
13356 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13357 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13358
13359 return val & DPLL_VCO_ENABLE;
13360}
13361
15bdd4cf
DV		 13362static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13363 struct intel_shared_dpll *pll)
13364{
3e369b76
ACO		 13365 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13366 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13367}
13368
e7b903d2
DV		 13369static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13370 struct intel_shared_dpll *pll)
13371{
e7b903d2 13372 /* PCH refclock must be enabled first */
89eff4be 13373 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13374
3e369b76 13375 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13376
13377 /* Wait for the clocks to stabilize. */
13378 POSTING_READ(PCH_DPLL(pll->id));
13379 udelay(150);
13380
13381 /* The pixel multiplier can only be updated once the
13382 * DPLL is enabled and the clocks are stable.
13383 *
13384 * So write it again.
13385 */
3e369b76 13386 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13387 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13388 udelay(200);
13389}
13390
13391static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13392 struct intel_shared_dpll *pll)
13393{
13394 struct drm_device *dev = dev_priv->dev;
13395 struct intel_crtc *crtc;
e7b903d2
DV		 13396
13397 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13398 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13399 if (intel_crtc_to_shared_dpll(crtc) == pll)
13400 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13401 }
13402
15bdd4cf
DV		 13403 I915_WRITE(PCH_DPLL(pll->id), 0);
13404 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13405 udelay(200);
13406}
13407
46edb027
DV		 13408static char *ibx_pch_dpll_names[] = {
13409 "PCH DPLL A",
13410 "PCH DPLL B",
13411};
13412
7c74ade1 13413static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13414{
e7b903d2 13415 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13416 int i;
13417
7c74ade1 13418 dev_priv->num_shared_dpll = 2;
ee7b9f93 13419
e72f9fbf 13420 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13421 dev_priv->shared_dplls[i].id = i;
13422 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13423 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13424 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13425 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13426 dev_priv->shared_dplls[i].get_hw_state =
13427 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13428 }
13429}
13430
7c74ade1
DV		 13431static void intel_shared_dpll_init(struct drm_device *dev)
13432{
e7b903d2 13433 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13434
b6283055
VS		 13435 intel_update_cdclk(dev);
13436
9cd86933
DV		 13437 if (HAS_DDI(dev))
13438 intel_ddi_pll_init(dev);
13439 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13440 ibx_pch_dpll_init(dev);
13441 else
13442 dev_priv->num_shared_dpll = 0;
13443
13444 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13445}
13446
1fc0a8f7
TU		 13447/**
13448 * intel_wm_need_update - Check whether watermarks need updating
13449 * @plane: drm plane
13450 * @state: new plane state
13451 *
13452 * Check current plane state versus the new one to determine whether
13453 * watermarks need to be recalculated.
13454 *
13455 * Returns true or false.
13456 */
13457bool intel_wm_need_update(struct drm_plane *plane,
13458 struct drm_plane_state *state)
13459{
13460 /* Update watermarks on tiling changes. */
13461 if (!plane->state->fb || !state->fb ||
13462 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13463 plane->state->rotation != state->rotation)
13464 return true;
13465
13466 return false;
13467}
13468
6beb8c23
MR		 13469/**
13470 * intel_prepare_plane_fb - Prepare fb for usage on plane
13471 * @plane: drm plane to prepare for
13472 * @fb: framebuffer to prepare for presentation
13473 *
13474 * Prepares a framebuffer for usage on a display plane. Generally this
13475 * involves pinning the underlying object and updating the frontbuffer tracking
13476 * bits. Some older platforms need special physical address handling for
13477 * cursor planes.
13478 *
13479 * Returns 0 on success, negative error code on failure.
13480 */
13481int
13482intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13483 struct drm_framebuffer *fb,
13484 const struct drm_plane_state *new_state)
465c120c
MR		 13485{
13486 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13487 struct intel_plane *intel_plane = to_intel_plane(plane);
13488 enum pipe pipe = intel_plane->pipe;
13489 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13490 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13491 unsigned frontbuffer_bits = 0;
13492 int ret = 0;
465c120c 13493
ea2c67bb 13494 if (!obj)
465c120c
MR		 13495 return 0;
13496
6beb8c23
MR		 13497 switch (plane->type) {
13498 case DRM_PLANE_TYPE_PRIMARY:
13499 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13500 break;
13501 case DRM_PLANE_TYPE_CURSOR:
13502 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13503 break;
13504 case DRM_PLANE_TYPE_OVERLAY:
13505 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13506 break;
13507 }
465c120c 13508
6beb8c23 13509 mutex_lock(&dev->struct_mutex);
465c120c 13510
6beb8c23
MR		 13511 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13512 INTEL_INFO(dev)->cursor_needs_physical) {
13513 int align = IS_I830(dev) ? 16 * 1024 : 256;
13514 ret = i915_gem_object_attach_phys(obj, align);
13515 if (ret)
13516 DRM_DEBUG_KMS("failed to attach phys object\n");
13517 } else {
82bc3b2d 13518 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13519 }
465c120c 13520
6beb8c23
MR		 13521 if (ret == 0)
13522 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13523
4c34574f 13524 mutex_unlock(&dev->struct_mutex);
465c120c 13525
6beb8c23
MR		 13526 return ret;
13527}
13528
38f3ce3a
MR		 13529/**
13530 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13531 * @plane: drm plane to clean up for
13532 * @fb: old framebuffer that was on plane
13533 *
13534 * Cleans up a framebuffer that has just been removed from a plane.
13535 */
13536void
13537intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13538 struct drm_framebuffer *fb,
13539 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13540{
13541 struct drm_device *dev = plane->dev;
13542 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13543
13544 if (WARN_ON(!obj))
13545 return;
13546
13547 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13548 !INTEL_INFO(dev)->cursor_needs_physical) {
13549 mutex_lock(&dev->struct_mutex);
82bc3b2d 13550 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13551 mutex_unlock(&dev->struct_mutex);
13552 }
465c120c
MR		 13553}
13554
6156a456
CK		 13555int
13556skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13557{
13558 int max_scale;
13559 struct drm_device *dev;
13560 struct drm_i915_private *dev_priv;
13561 int crtc_clock, cdclk;
13562
13563 if (!intel_crtc || !crtc_state)
13564 return DRM_PLANE_HELPER_NO_SCALING;
13565
13566 dev = intel_crtc->base.dev;
13567 dev_priv = dev->dev_private;
13568 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13569 cdclk = dev_priv->display.get_display_clock_speed(dev);
13570
13571 if (!crtc_clock || !cdclk)
13572 return DRM_PLANE_HELPER_NO_SCALING;
13573
13574 /*
13575 * skl max scale is lower of:
13576 * close to 3 but not 3, -1 is for that purpose
13577 * or
13578 * cdclk/crtc_clock
13579 */
13580 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13581
13582 return max_scale;
13583}
13584
465c120c 13585static int
3c692a41
GP		 13586intel_check_primary_plane(struct drm_plane *plane,
13587 struct intel_plane_state *state)
13588{
32b7eeec
MR		 13589 struct drm_device *dev = plane->dev;
13590 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13591 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13592 struct intel_crtc *intel_crtc;
6156a456 13593 struct intel_crtc_state *crtc_state;
2b875c22 13594 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13595 struct drm_rect *dest = &state->dst;
13596 struct drm_rect *src = &state->src;
13597 const struct drm_rect *clip = &state->clip;
d8106366 13598 bool can_position = false;
6156a456
CK		 13599 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13600 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13601 int ret;
13602
ea2c67bb
MR		 13603 crtc = crtc ? crtc : plane->crtc;
13604 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13605 crtc_state = state->base.state ?
13606 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13607
6156a456 13608 if (INTEL_INFO(dev)->gen >= 9) {
225c228a
CK		 13609 /* use scaler when colorkey is not required */
13610 if (to_intel_plane(plane)->ckey.flags == I915_SET_COLORKEY_NONE) {
13611 min_scale = 1;
13612 max_scale = skl_max_scale(intel_crtc, crtc_state);
13613 }
d8106366 13614 can_position = true;
6156a456 13615 }
d8106366 13616
c59cb179
MR		 13617 ret = drm_plane_helper_check_update(plane, crtc, fb,
13618 src, dest, clip,
6156a456
CK		 13619 min_scale,
13620 max_scale,
d8106366
SJ		 13621 can_position, true,
13622 &state->visible);
c59cb179
MR		 13623 if (ret)
13624 return ret;
465c120c 13625
32b7eeec 13626 if (intel_crtc->active) {
b70709a6
ML		 13627 struct intel_plane_state *old_state =
13628 to_intel_plane_state(plane->state);
13629
32b7eeec
MR		 13630 intel_crtc->atomic.wait_for_flips = true;
13631
13632 /*
13633 * FBC does not work on some platforms for rotated
13634 * planes, so disable it when rotation is not 0 and
13635 * update it when rotation is set back to 0.
13636 *
13637 * FIXME: This is redundant with the fbc update done in
13638 * the primary plane enable function except that that
13639 * one is done too late. We eventually need to unify
13640 * this.
13641 */
b70709a6 13642 if (state->visible &&
32b7eeec 13643 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13644 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13645 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13646 intel_crtc->atomic.disable_fbc = true;
13647 }
13648
b70709a6 13649 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13650 /*
13651 * BDW signals flip done immediately if the plane
13652 * is disabled, even if the plane enable is already
13653 * armed to occur at the next vblank :(
13654 */
b70709a6 13655 if (IS_BROADWELL(dev))
32b7eeec 13656 intel_crtc->atomic.wait_vblank = true;
fb9d6cf8
ML		 13657
13658 if (crtc_state && !needs_modeset(&crtc_state->base))
13659 intel_crtc->atomic.post_enable_primary = true;
32b7eeec
MR		 13660 }
13661
fb9d6cf8
ML		 13662 if (!state->visible && old_state->visible &&
13663 crtc_state && !needs_modeset(&crtc_state->base))
13664 intel_crtc->atomic.pre_disable_primary = true;
13665
32b7eeec
MR		 13666 intel_crtc->atomic.fb_bits |=
13667 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13668
13669 intel_crtc->atomic.update_fbc = true;
0fda6568 13670
1fc0a8f7 13671 if (intel_wm_need_update(plane, &state->base))
0fda6568 13672 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13673 }
13674
6156a456
CK		 13675 if (INTEL_INFO(dev)->gen >= 9) {
13676 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13677 to_intel_plane(plane), state, 0);
13678 if (ret)
13679 return ret;
13680 }
13681
14af293f
GP		 13682 return 0;
13683}
13684
13685static void
13686intel_commit_primary_plane(struct drm_plane *plane,
13687 struct intel_plane_state *state)
13688{
2b875c22
MR		 13689 struct drm_crtc *crtc = state->base.crtc;
13690 struct drm_framebuffer *fb = state->base.fb;
13691 struct drm_device *dev = plane->dev;
14af293f 13692 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13693 struct intel_crtc *intel_crtc;
14af293f
GP		 13694 struct drm_rect *src = &state->src;
13695
ea2c67bb
MR		 13696 crtc = crtc ? crtc : plane->crtc;
13697 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13698
13699 plane->fb = fb;
9dc806fc
MR		 13700 crtc->x = src->x1 >> 16;
13701 crtc->y = src->y1 >> 16;
ccc759dc 13702
ccc759dc 13703 if (intel_crtc->active) {
27321ae8 13704 if (state->visible)
ccc759dc
GP		 13705 /* FIXME: kill this fastboot hack */
13706 intel_update_pipe_size(intel_crtc);
465c120c 13707
27321ae8
ML		 13708 dev_priv->display.update_primary_plane(crtc, plane->fb,
13709 crtc->x, crtc->y);
ccc759dc 13710 }
465c120c
MR		 13711}
13712
a8ad0d8e
ML		 13713static void
13714intel_disable_primary_plane(struct drm_plane *plane,
13715 struct drm_crtc *crtc,
13716 bool force)
13717{
13718 struct drm_device *dev = plane->dev;
13719 struct drm_i915_private *dev_priv = dev->dev_private;
13720
a8ad0d8e
ML		 13721 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13722}
13723
32b7eeec 13724static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13725{
32b7eeec 13726 struct drm_device *dev = crtc->dev;
140fd38d 13727 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c2db188 13729 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
ea2c67bb
MR		 13730 struct intel_plane *intel_plane;
13731 struct drm_plane *p;
13732 unsigned fb_bits = 0;
13733
13734 /* Track fb's for any planes being disabled */
13735 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13736 intel_plane = to_intel_plane(p);
13737
13738 if (intel_crtc->atomic.disabled_planes &
13739 (1 << drm_plane_index(p))) {
13740 switch (p->type) {
13741 case DRM_PLANE_TYPE_PRIMARY:
13742 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13743 break;
13744 case DRM_PLANE_TYPE_CURSOR:
13745 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13746 break;
13747 case DRM_PLANE_TYPE_OVERLAY:
13748 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13749 break;
13750 }
3c692a41 13751
ea2c67bb
MR		 13752 mutex_lock(&dev->struct_mutex);
13753 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13754 mutex_unlock(&dev->struct_mutex);
13755 }
13756 }
3c692a41 13757
32b7eeec
MR		 13758 if (intel_crtc->atomic.wait_for_flips)
13759 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13760
32b7eeec
MR		 13761 if (intel_crtc->atomic.disable_fbc)
13762 intel_fbc_disable(dev);
3c692a41 13763
32b7eeec
MR		 13764 if (intel_crtc->atomic.pre_disable_primary)
13765 intel_pre_disable_primary(crtc);
3c692a41 13766
32b7eeec
MR		 13767 if (intel_crtc->atomic.update_wm)
13768 intel_update_watermarks(crtc);
3c692a41 13769
32b7eeec 13770 intel_runtime_pm_get(dev_priv);
3c692a41 13771
c34c9ee4 13772 /* Perform vblank evasion around commit operation */
5c2db188 13773 if (crtc_state->active && !needs_modeset(crtc_state))
c34c9ee4
MR		 13774 intel_crtc->atomic.evade =
13775 intel_pipe_update_start(intel_crtc,
13776 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13777}
13778
13779static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13780{
13781 struct drm_device *dev = crtc->dev;
13782 struct drm_i915_private *dev_priv = dev->dev_private;
13783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13784 struct drm_plane *p;
13785
c34c9ee4
MR		 13786 if (intel_crtc->atomic.evade)
13787 intel_pipe_update_end(intel_crtc,
13788 intel_crtc->atomic.start_vbl_count);
3c692a41 13789
140fd38d 13790 intel_runtime_pm_put(dev_priv);
3c692a41 13791
8a8f7f44 13792 if (intel_crtc->atomic.wait_vblank && intel_crtc->active)
32b7eeec
MR		 13793 intel_wait_for_vblank(dev, intel_crtc->pipe);
13794
13795 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13796
13797 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13798 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13799 intel_fbc_update(dev);
ccc759dc 13800 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13801 }
3c692a41 13802
32b7eeec
MR		 13803 if (intel_crtc->atomic.post_enable_primary)
13804 intel_post_enable_primary(crtc);
3c692a41 13805
32b7eeec
MR		 13806 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13807 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13808 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13809 false, false);
13810
13811 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13812}
13813
cf4c7c12 13814/**
4a3b8769
MR		 13815 * intel_plane_destroy - destroy a plane
13816 * @plane: plane to destroy
cf4c7c12 13817 *
4a3b8769
MR		 13818 * Common destruction function for all types of planes (primary, cursor,
13819 * sprite).
cf4c7c12 13820 */
4a3b8769 13821void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13822{
13823 struct intel_plane *intel_plane = to_intel_plane(plane);
13824 drm_plane_cleanup(plane);
13825 kfree(intel_plane);
13826}
13827
65a3fea0 13828const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13829 .update_plane = drm_atomic_helper_update_plane,
13830 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13831 .destroy = intel_plane_destroy,
c196e1d6 13832 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13833 .atomic_get_property = intel_plane_atomic_get_property,
13834 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13835 .atomic_duplicate_state = intel_plane_duplicate_state,
13836 .atomic_destroy_state = intel_plane_destroy_state,
13837
465c120c
MR		 13838};
13839
13840static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13841 int pipe)
13842{
13843 struct intel_plane *primary;
8e7d688b 13844 struct intel_plane_state *state;
465c120c
MR		 13845 const uint32_t *intel_primary_formats;
13846 int num_formats;
13847
13848 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13849 if (primary == NULL)
13850 return NULL;
13851
8e7d688b
MR		 13852 state = intel_create_plane_state(&primary->base);
13853 if (!state) {
ea2c67bb
MR		 13854 kfree(primary);
13855 return NULL;
13856 }
8e7d688b 13857 primary->base.state = &state->base;
ea2c67bb 13858
465c120c
MR		 13859 primary->can_scale = false;
13860 primary->max_downscale = 1;
6156a456
CK		 13861 if (INTEL_INFO(dev)->gen >= 9) {
13862 primary->can_scale = true;
af99ceda 13863 state->scaler_id = -1;
6156a456 13864 }
465c120c
MR		 13865 primary->pipe = pipe;
13866 primary->plane = pipe;
c59cb179
MR		 13867 primary->check_plane = intel_check_primary_plane;
13868 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13869 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13870 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13871 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13872 primary->plane = !pipe;
13873
6c0fd451
DL		 13874 if (INTEL_INFO(dev)->gen >= 9) {
13875 intel_primary_formats = skl_primary_formats;
13876 num_formats = ARRAY_SIZE(skl_primary_formats);
13877 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13878 intel_primary_formats = i965_primary_formats;
13879 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13880 } else {
13881 intel_primary_formats = i8xx_primary_formats;
13882 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13883 }
13884
13885 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13886 &intel_plane_funcs,
465c120c
MR		 13887 intel_primary_formats, num_formats,
13888 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13889
3b7a5119
SJ		 13890 if (INTEL_INFO(dev)->gen >= 4)
13891 intel_create_rotation_property(dev, primary);
48404c1e 13892
ea2c67bb
MR		 13893 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13894
465c120c
MR		 13895 return &primary->base;
13896}
13897
3b7a5119
SJ		 13898void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13899{
13900 if (!dev->mode_config.rotation_property) {
13901 unsigned long flags = BIT(DRM_ROTATE_0) |
13902 BIT(DRM_ROTATE_180);
13903
13904 if (INTEL_INFO(dev)->gen >= 9)
13905 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13906
13907 dev->mode_config.rotation_property =
13908 drm_mode_create_rotation_property(dev, flags);
13909 }
13910 if (dev->mode_config.rotation_property)
13911 drm_object_attach_property(&plane->base.base,
13912 dev->mode_config.rotation_property,
13913 plane->base.state->rotation);
13914}
13915
3d7d6510 13916static int
852e787c
GP		 13917intel_check_cursor_plane(struct drm_plane *plane,
13918 struct intel_plane_state *state)
3d7d6510 13919{
2b875c22 13920 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13921 struct drm_device *dev = plane->dev;
2b875c22 13922 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13923 struct drm_rect *dest = &state->dst;
13924 struct drm_rect *src = &state->src;
13925 const struct drm_rect *clip = &state->clip;
757f9a3e 13926 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13927 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13928 unsigned stride;
13929 int ret;
3d7d6510 13930
ea2c67bb
MR		 13931 crtc = crtc ? crtc : plane->crtc;
13932 intel_crtc = to_intel_crtc(crtc);
13933
757f9a3e 13934 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13935 src, dest, clip,
3d7d6510
MR		 13936 DRM_PLANE_HELPER_NO_SCALING,
13937 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13938 true, true, &state->visible);
757f9a3e
GP		 13939 if (ret)
13940 return ret;
13941
13942
13943 /* if we want to turn off the cursor ignore width and height */
13944 if (!obj)
32b7eeec 13945 goto finish;
757f9a3e 13946
757f9a3e 13947 /* Check for which cursor types we support */
ea2c67bb
MR		 13948 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13949 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13950 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13951 return -EINVAL;
13952 }
13953
ea2c67bb
MR		 13954 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13955 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13956 DRM_DEBUG_KMS("buffer is too small\n");
13957 return -ENOMEM;
13958 }
13959
3a656b54 13960 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13961 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13962 ret = -EINVAL;
13963 }
757f9a3e 13964
32b7eeec
MR		 13965finish:
13966 if (intel_crtc->active) {
3749f463 13967 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13968 intel_crtc->atomic.update_wm = true;
13969
13970 intel_crtc->atomic.fb_bits |=
13971 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13972 }
13973
757f9a3e 13974 return ret;
852e787c 13975}
3d7d6510 13976
a8ad0d8e
ML		 13977static void
13978intel_disable_cursor_plane(struct drm_plane *plane,
13979 struct drm_crtc *crtc,
13980 bool force)
13981{
13982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13983
13984 if (!force) {
13985 plane->fb = NULL;
13986 intel_crtc->cursor_bo = NULL;
13987 intel_crtc->cursor_addr = 0;
13988 }
13989
13990 intel_crtc_update_cursor(crtc, false);
13991}
13992
f4a2cf29 13993static void
852e787c
GP		 13994intel_commit_cursor_plane(struct drm_plane *plane,
13995 struct intel_plane_state *state)
13996{
2b875c22 13997 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13998 struct drm_device *dev = plane->dev;
13999 struct intel_crtc *intel_crtc;
2b875c22 14000 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 14001 uint32_t addr;
852e787c 14002
ea2c67bb
MR		 14003 crtc = crtc ? crtc : plane->crtc;
14004 intel_crtc = to_intel_crtc(crtc);
14005
2b875c22 14006 plane->fb = state->base.fb;
ea2c67bb
MR		 14007 crtc->cursor_x = state->base.crtc_x;
14008 crtc->cursor_y = state->base.crtc_y;
14009
a912f12f
GP		 14010 if (intel_crtc->cursor_bo == obj)
14011 goto update;
4ed91096 14012
f4a2cf29 14013 if (!obj)
a912f12f 14014 addr = 0;
f4a2cf29 14015 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 14016 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 14017 else
a912f12f 14018 addr = obj->phys_handle->busaddr;
852e787c 14019
a912f12f
GP		 14020 intel_crtc->cursor_addr = addr;
14021 intel_crtc->cursor_bo = obj;
14022update:
852e787c 14023
32b7eeec 14024 if (intel_crtc->active)
a912f12f 14025 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 14026}
14027
3d7d6510
MR		 14028static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14029 int pipe)
14030{
14031 struct intel_plane *cursor;
8e7d688b 14032 struct intel_plane_state *state;
3d7d6510
MR		 14033
14034 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14035 if (cursor == NULL)
14036 return NULL;
14037
8e7d688b
MR		 14038 state = intel_create_plane_state(&cursor->base);
14039 if (!state) {
ea2c67bb
MR		 14040 kfree(cursor);
14041 return NULL;
14042 }
8e7d688b 14043 cursor->base.state = &state->base;
ea2c67bb 14044
3d7d6510
MR		 14045 cursor->can_scale = false;
14046 cursor->max_downscale = 1;
14047 cursor->pipe = pipe;
14048 cursor->plane = pipe;
c59cb179
MR		 14049 cursor->check_plane = intel_check_cursor_plane;
14050 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 14051 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 14052
14053 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14054 &intel_plane_funcs,
3d7d6510
MR		 14055 intel_cursor_formats,
14056 ARRAY_SIZE(intel_cursor_formats),
14057 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14058
14059 if (INTEL_INFO(dev)->gen >= 4) {
14060 if (!dev->mode_config.rotation_property)
14061 dev->mode_config.rotation_property =
14062 drm_mode_create_rotation_property(dev,
14063 BIT(DRM_ROTATE_0) |
14064 BIT(DRM_ROTATE_180));
14065 if (dev->mode_config.rotation_property)
14066 drm_object_attach_property(&cursor->base.base,
14067 dev->mode_config.rotation_property,
8e7d688b 14068 state->base.rotation);
4398ad45
VS		 14069 }
14070
af99ceda
CK		 14071 if (INTEL_INFO(dev)->gen >=9)
14072 state->scaler_id = -1;
14073
ea2c67bb
MR		 14074 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14075
3d7d6510
MR		 14076 return &cursor->base;
14077}
14078
549e2bfb
CK		 14079static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14080 struct intel_crtc_state *crtc_state)
14081{
14082 int i;
14083 struct intel_scaler *intel_scaler;
14084 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14085
14086 for (i = 0; i < intel_crtc->num_scalers; i++) {
14087 intel_scaler = &scaler_state->scalers[i];
14088 intel_scaler->in_use = 0;
549e2bfb
CK		 14089 intel_scaler->mode = PS_SCALER_MODE_DYN;
14090 }
14091
14092 scaler_state->scaler_id = -1;
14093}
14094
b358d0a6 14095static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14096{
fbee40df 14097 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14098 struct intel_crtc *intel_crtc;
f5de6e07 14099 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14100 struct drm_plane *primary = NULL;
14101 struct drm_plane *cursor = NULL;
465c120c 14102 int i, ret;
79e53945 14103
955382f3 14104 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14105 if (intel_crtc == NULL)
14106 return;
14107
f5de6e07
ACO		 14108 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14109 if (!crtc_state)
14110 goto fail;
550acefd
ACO		 14111 intel_crtc->config = crtc_state;
14112 intel_crtc->base.state = &crtc_state->base;
07878248 14113 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14114
549e2bfb
CK		 14115 /* initialize shared scalers */
14116 if (INTEL_INFO(dev)->gen >= 9) {
14117 if (pipe == PIPE_C)
14118 intel_crtc->num_scalers = 1;
14119 else
14120 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14121
14122 skl_init_scalers(dev, intel_crtc, crtc_state);
14123 }
14124
465c120c 14125 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14126 if (!primary)
14127 goto fail;
14128
14129 cursor = intel_cursor_plane_create(dev, pipe);
14130 if (!cursor)
14131 goto fail;
14132
465c120c 14133 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14134 cursor, &intel_crtc_funcs);
14135 if (ret)
14136 goto fail;
79e53945
JB		 14137
14138 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14139 for (i = 0; i < 256; i++) {
14140 intel_crtc->lut_r[i] = i;
14141 intel_crtc->lut_g[i] = i;
14142 intel_crtc->lut_b[i] = i;
14143 }
14144
1f1c2e24
VS		 14145 /*
14146 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14147 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14148 */
80824003
JB		 14149 intel_crtc->pipe = pipe;
14150 intel_crtc->plane = pipe;
3a77c4c4 14151 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14152 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14153 intel_crtc->plane = !pipe;
80824003
JB		 14154 }
14155
4b0e333e
CW		 14156 intel_crtc->cursor_base = ~0;
14157 intel_crtc->cursor_cntl = ~0;
dc41c154 14158 intel_crtc->cursor_size = ~0;
8d7849db 14159
22fd0fab
JB		 14160 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14161 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14162 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14163 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14164
79e53945 14165 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14166
14167 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14168 return;
14169
14170fail:
14171 if (primary)
14172 drm_plane_cleanup(primary);
14173 if (cursor)
14174 drm_plane_cleanup(cursor);
f5de6e07 14175 kfree(crtc_state);
3d7d6510 14176 kfree(intel_crtc);
79e53945
JB		 14177}
14178
752aa88a
JB		 14179enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14180{
14181 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14182 struct drm_device *dev = connector->base.dev;
752aa88a 14183
51fd371b 14184 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14185
d3babd3f 14186 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14187 return INVALID_PIPE;
14188
14189 return to_intel_crtc(encoder->crtc)->pipe;
14190}
14191
08d7b3d1 14192int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14193 struct drm_file *file)
08d7b3d1 14194{
08d7b3d1 14195 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14196 struct drm_crtc *drmmode_crtc;
c05422d5 14197 struct intel_crtc *crtc;
08d7b3d1 14198
7707e653 14199 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14200
7707e653 14201 if (!drmmode_crtc) {
08d7b3d1 14202 DRM_ERROR("no such CRTC id\n");
3f2c2057 14203 return -ENOENT;
08d7b3d1
CW		 14204 }
14205
7707e653 14206 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14207 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14208
c05422d5 14209 return 0;
08d7b3d1
CW		 14210}
14211
66a9278e 14212static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14213{
66a9278e
DV		 14214 struct drm_device *dev = encoder->base.dev;
14215 struct intel_encoder *source_encoder;
79e53945 14216 int index_mask = 0;
79e53945
JB		 14217 int entry = 0;
14218
b2784e15 14219 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14220 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14221 index_mask |= (1 << entry);
14222
79e53945
JB		 14223 entry++;
14224 }
4ef69c7a 14225
79e53945
JB		 14226 return index_mask;
14227}
14228
4d302442
CW		 14229static bool has_edp_a(struct drm_device *dev)
14230{
14231 struct drm_i915_private *dev_priv = dev->dev_private;
14232
14233 if (!IS_MOBILE(dev))
14234 return false;
14235
14236 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14237 return false;
14238
e3589908 14239 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14240 return false;
14241
14242 return true;
14243}
14244
84b4e042
JB		 14245static bool intel_crt_present(struct drm_device *dev)
14246{
14247 struct drm_i915_private *dev_priv = dev->dev_private;
14248
884497ed
DL		 14249 if (INTEL_INFO(dev)->gen >= 9)
14250 return false;
14251
cf404ce4 14252 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14253 return false;
14254
14255 if (IS_CHERRYVIEW(dev))
14256 return false;
14257
14258 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14259 return false;
14260
14261 return true;
14262}
14263
79e53945
JB		 14264static void intel_setup_outputs(struct drm_device *dev)
14265{
725e30ad 14266 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14267 struct intel_encoder *encoder;
cb0953d7 14268 bool dpd_is_edp = false;
79e53945 14269
c9093354 14270 intel_lvds_init(dev);
79e53945 14271
84b4e042 14272 if (intel_crt_present(dev))
79935fca 14273 intel_crt_init(dev);
cb0953d7 14274
c776eb2e
VK		 14275 if (IS_BROXTON(dev)) {
14276 /*
14277 * FIXME: Broxton doesn't support port detection via the
14278 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14279 * detect the ports.
14280 */
14281 intel_ddi_init(dev, PORT_A);
14282 intel_ddi_init(dev, PORT_B);
14283 intel_ddi_init(dev, PORT_C);
14284 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14285 int found;
14286
de31facd
JB		 14287 /*
14288 * Haswell uses DDI functions to detect digital outputs.
14289 * On SKL pre-D0 the strap isn't connected, so we assume
14290 * it's there.
14291 */
0e72a5b5 14292 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14293 /* WaIgnoreDDIAStrap: skl */
14294 if (found ||
14295 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14296 intel_ddi_init(dev, PORT_A);
14297
14298 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14299 * register */
14300 found = I915_READ(SFUSE_STRAP);
14301
14302 if (found & SFUSE_STRAP_DDIB_DETECTED)
14303 intel_ddi_init(dev, PORT_B);
14304 if (found & SFUSE_STRAP_DDIC_DETECTED)
14305 intel_ddi_init(dev, PORT_C);
14306 if (found & SFUSE_STRAP_DDID_DETECTED)
14307 intel_ddi_init(dev, PORT_D);
14308 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14309 int found;
5d8a7752 14310 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14311
14312 if (has_edp_a(dev))
14313 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14314
dc0fa718 14315 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14316 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14317 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14318 if (!found)
e2debe91 14319 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14320 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14321 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14322 }
14323
dc0fa718 14324 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14325 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14326
dc0fa718 14327 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14328 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14329
5eb08b69 14330 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14331 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14332
270b3042 14333 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14334 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14335 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14336 /*
14337 * The DP_DETECTED bit is the latched state of the DDC
14338 * SDA pin at boot. However since eDP doesn't require DDC
14339 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14340 * eDP ports may have been muxed to an alternate function.
14341 * Thus we can't rely on the DP_DETECTED bit alone to detect
14342 * eDP ports. Consult the VBT as well as DP_DETECTED to
14343 * detect eDP ports.
14344 */
d2182a66
VS		 14345 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14346 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14347 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14348 PORT_B);
e17ac6db
VS		 14349 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14350 intel_dp_is_edp(dev, PORT_B))
14351 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14352
d2182a66
VS		 14353 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14354 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14355 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14356 PORT_C);
e17ac6db
VS		 14357 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14358 intel_dp_is_edp(dev, PORT_C))
14359 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14360
9418c1f1 14361 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14362 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14363 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14364 PORT_D);
e17ac6db
VS		 14365 /* eDP not supported on port D, so don't check VBT */
14366 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14367 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14368 }
14369
3cfca973 14370 intel_dsi_init(dev);
103a196f 14371 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14372 bool found = false;
7d57382e 14373
e2debe91 14374 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14375 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14376 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14377 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14378 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14379 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14380 }
27185ae1 14381
e7281eab 14382 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14383 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14384 }
13520b05
KH		 14385
14386 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14387
e2debe91 14388 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14389 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14390 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14391 }
27185ae1 14392
e2debe91 14393 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14394
b01f2c3a
JB		 14395 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14396 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14397 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14398 }
e7281eab 14399 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14400 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14401 }
27185ae1 14402
b01f2c3a 14403 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14404 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14405 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14406 } else if (IS_GEN2(dev))
79e53945
JB		 14407 intel_dvo_init(dev);
14408
103a196f 14409 if (SUPPORTS_TV(dev))
79e53945
JB		 14410 intel_tv_init(dev);
14411
0bc12bcb 14412 intel_psr_init(dev);
7c8f8a70 14413
b2784e15 14414 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14415 encoder->base.possible_crtcs = encoder->crtc_mask;
14416 encoder->base.possible_clones =
66a9278e 14417 intel_encoder_clones(encoder);
79e53945 14418 }
47356eb6 14419
dde86e2d 14420 intel_init_pch_refclk(dev);
270b3042
DV		 14421
14422 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14423}
14424
14425static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14426{
60a5ca01 14427 struct drm_device *dev = fb->dev;
79e53945 14428 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14429
ef2d633e 14430 drm_framebuffer_cleanup(fb);
60a5ca01 14431 mutex_lock(&dev->struct_mutex);
ef2d633e 14432 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14433 drm_gem_object_unreference(&intel_fb->obj->base);
14434 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14435 kfree(intel_fb);
14436}
14437
14438static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14439 struct drm_file *file,
79e53945
JB		 14440 unsigned int *handle)
14441{
14442 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14443 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14444
05394f39 14445 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14446}
14447
14448static const struct drm_framebuffer_funcs intel_fb_funcs = {
14449 .destroy = intel_user_framebuffer_destroy,
14450 .create_handle = intel_user_framebuffer_create_handle,
14451};
14452
b321803d
DL		 14453static
14454u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14455 uint32_t pixel_format)
14456{
14457 u32 gen = INTEL_INFO(dev)->gen;
14458
14459 if (gen >= 9) {
14460 /* "The stride in bytes must not exceed the of the size of 8K
14461 * pixels and 32K bytes."
14462 */
14463 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14464 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14465 return 32*1024;
14466 } else if (gen >= 4) {
14467 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14468 return 16*1024;
14469 else
14470 return 32*1024;
14471 } else if (gen >= 3) {
14472 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14473 return 8*1024;
14474 else
14475 return 16*1024;
14476 } else {
14477 /* XXX DSPC is limited to 4k tiled */
14478 return 8*1024;
14479 }
14480}
14481
b5ea642a
DV		 14482static int intel_framebuffer_init(struct drm_device *dev,
14483 struct intel_framebuffer *intel_fb,
14484 struct drm_mode_fb_cmd2 *mode_cmd,
14485 struct drm_i915_gem_object *obj)
79e53945 14486{
6761dd31 14487 unsigned int aligned_height;
79e53945 14488 int ret;
b321803d 14489 u32 pitch_limit, stride_alignment;
79e53945 14490
dd4916c5
DV		 14491 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14492
2a80eada
DV		 14493 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14494 /* Enforce that fb modifier and tiling mode match, but only for
14495 * X-tiled. This is needed for FBC. */
14496 if (!!(obj->tiling_mode == I915_TILING_X) !=
14497 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14498 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14499 return -EINVAL;
14500 }
14501 } else {
14502 if (obj->tiling_mode == I915_TILING_X)
14503 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14504 else if (obj->tiling_mode == I915_TILING_Y) {
14505 DRM_DEBUG("No Y tiling for legacy addfb\n");
14506 return -EINVAL;
14507 }
14508 }
14509
9a8f0a12
TU		 14510 /* Passed in modifier sanity checking. */
14511 switch (mode_cmd->modifier[0]) {
14512 case I915_FORMAT_MOD_Y_TILED:
14513 case I915_FORMAT_MOD_Yf_TILED:
14514 if (INTEL_INFO(dev)->gen < 9) {
14515 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14516 mode_cmd->modifier[0]);
14517 return -EINVAL;
14518 }
14519 case DRM_FORMAT_MOD_NONE:
14520 case I915_FORMAT_MOD_X_TILED:
14521 break;
14522 default:
c0f40428
JB		 14523 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14524 mode_cmd->modifier[0]);
57cd6508 14525 return -EINVAL;
c16ed4be 14526 }
57cd6508 14527
b321803d
DL		 14528 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14529 mode_cmd->pixel_format);
14530 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14531 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14532 mode_cmd->pitches[0], stride_alignment);
57cd6508 14533 return -EINVAL;
c16ed4be 14534 }
57cd6508 14535
b321803d
DL		 14536 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14537 mode_cmd->pixel_format);
a35cdaa0 14538 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14539 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14540 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14541 "tiled" : "linear",
a35cdaa0 14542 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14543 return -EINVAL;
c16ed4be 14544 }
5d7bd705 14545
2a80eada 14546 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14547 mode_cmd->pitches[0] != obj->stride) {
14548 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14549 mode_cmd->pitches[0], obj->stride);
5d7bd705 14550 return -EINVAL;
c16ed4be 14551 }
5d7bd705 14552
57779d06 14553 /* Reject formats not supported by any plane early. */
308e5bcb 14554 switch (mode_cmd->pixel_format) {
57779d06 14555 case DRM_FORMAT_C8:
04b3924d
VS		 14556 case DRM_FORMAT_RGB565:
14557 case DRM_FORMAT_XRGB8888:
14558 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14559 break;
14560 case DRM_FORMAT_XRGB1555:
c16ed4be 14561 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14562 DRM_DEBUG("unsupported pixel format: %s\n",
14563 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14564 return -EINVAL;
c16ed4be 14565 }
57779d06 14566 break;
57779d06 14567 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14568 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14569 DRM_DEBUG("unsupported pixel format: %s\n",
14570 drm_get_format_name(mode_cmd->pixel_format));
14571 return -EINVAL;
14572 }
14573 break;
14574 case DRM_FORMAT_XBGR8888:
04b3924d 14575 case DRM_FORMAT_XRGB2101010:
57779d06 14576 case DRM_FORMAT_XBGR2101010:
c16ed4be 14577 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14578 DRM_DEBUG("unsupported pixel format: %s\n",
14579 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14580 return -EINVAL;
c16ed4be 14581 }
b5626747 14582 break;
7531208b
DL		 14583 case DRM_FORMAT_ABGR2101010:
14584 if (!IS_VALLEYVIEW(dev)) {
14585 DRM_DEBUG("unsupported pixel format: %s\n",
14586 drm_get_format_name(mode_cmd->pixel_format));
14587 return -EINVAL;
14588 }
14589 break;
04b3924d
VS		 14590 case DRM_FORMAT_YUYV:
14591 case DRM_FORMAT_UYVY:
14592 case DRM_FORMAT_YVYU:
14593 case DRM_FORMAT_VYUY:
c16ed4be 14594 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14595 DRM_DEBUG("unsupported pixel format: %s\n",
14596 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14597 return -EINVAL;
c16ed4be 14598 }
57cd6508
CW		 14599 break;
14600 default:
4ee62c76
VS		 14601 DRM_DEBUG("unsupported pixel format: %s\n",
14602 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14603 return -EINVAL;
14604 }
14605
90f9a336
VS		 14606 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14607 if (mode_cmd->offsets[0] != 0)
14608 return -EINVAL;
14609
ec2c981e 14610 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14611 mode_cmd->pixel_format,
14612 mode_cmd->modifier[0]);
53155c0a
DV		 14613 /* FIXME drm helper for size checks (especially planar formats)? */
14614 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14615 return -EINVAL;
14616
c7d73f6a
DV		 14617 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14618 intel_fb->obj = obj;
80075d49 14619 intel_fb->obj->framebuffer_references++;
c7d73f6a 14620
79e53945
JB		 14621 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14622 if (ret) {
14623 DRM_ERROR("framebuffer init failed %d\n", ret);
14624 return ret;
14625 }
14626
79e53945
JB		 14627 return 0;
14628}
14629
79e53945
JB		 14630static struct drm_framebuffer *
14631intel_user_framebuffer_create(struct drm_device *dev,
14632 struct drm_file *filp,
308e5bcb 14633 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14634{
05394f39 14635 struct drm_i915_gem_object *obj;
79e53945 14636
308e5bcb
JB		 14637 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14638 mode_cmd->handles[0]));
c8725226 14639 if (&obj->base == NULL)
cce13ff7 14640 return ERR_PTR(-ENOENT);
79e53945 14641
d2dff872 14642 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14643}
14644
4520f53a 14645#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14646static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14647{
14648}
14649#endif
14650
79e53945 14651static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14652 .fb_create = intel_user_framebuffer_create,
0632fef6 14653 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14654 .atomic_check = intel_atomic_check,
14655 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14656 .atomic_state_alloc = intel_atomic_state_alloc,
14657 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14658};
14659
e70236a8
JB		 14660/* Set up chip specific display functions */
14661static void intel_init_display(struct drm_device *dev)
14662{
14663 struct drm_i915_private *dev_priv = dev->dev_private;
14664
ee9300bb
DV		 14665 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14666 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14667 else if (IS_CHERRYVIEW(dev))
14668 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14669 else if (IS_VALLEYVIEW(dev))
14670 dev_priv->display.find_dpll = vlv_find_best_dpll;
14671 else if (IS_PINEVIEW(dev))
14672 dev_priv->display.find_dpll = pnv_find_best_dpll;
14673 else
14674 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14675
bc8d7dff
DL		 14676 if (INTEL_INFO(dev)->gen >= 9) {
14677 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14678 dev_priv->display.get_initial_plane_config =
14679 skylake_get_initial_plane_config;
bc8d7dff
DL		 14680 dev_priv->display.crtc_compute_clock =
14681 haswell_crtc_compute_clock;
14682 dev_priv->display.crtc_enable = haswell_crtc_enable;
14683 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14684 dev_priv->display.update_primary_plane =
14685 skylake_update_primary_plane;
14686 } else if (HAS_DDI(dev)) {
0e8ffe1b 14687 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14688 dev_priv->display.get_initial_plane_config =
14689 ironlake_get_initial_plane_config;
797d0259
ACO		 14690 dev_priv->display.crtc_compute_clock =
14691 haswell_crtc_compute_clock;
4f771f10
PZ		 14692 dev_priv->display.crtc_enable = haswell_crtc_enable;
14693 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14694 dev_priv->display.update_primary_plane =
14695 ironlake_update_primary_plane;
09b4ddf9 14696 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14697 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14698 dev_priv->display.get_initial_plane_config =
14699 ironlake_get_initial_plane_config;
3fb37703
ACO		 14700 dev_priv->display.crtc_compute_clock =
14701 ironlake_crtc_compute_clock;
76e5a89c
DV		 14702 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14703 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14704 dev_priv->display.update_primary_plane =
14705 ironlake_update_primary_plane;
89b667f8
JB		 14706 } else if (IS_VALLEYVIEW(dev)) {
14707 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14708 dev_priv->display.get_initial_plane_config =
14709 i9xx_get_initial_plane_config;
d6dfee7a 14710 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14711 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14712 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14713 dev_priv->display.update_primary_plane =
14714 i9xx_update_primary_plane;
f564048e 14715 } else {
0e8ffe1b 14716 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14717 dev_priv->display.get_initial_plane_config =
14718 i9xx_get_initial_plane_config;
d6dfee7a 14719 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14720 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14721 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14722 dev_priv->display.update_primary_plane =
14723 i9xx_update_primary_plane;
f564048e 14724 }
e70236a8 14725
e70236a8 14726 /* Returns the core display clock speed */
1652d19e
VS		 14727 if (IS_SKYLAKE(dev))
14728 dev_priv->display.get_display_clock_speed =
14729 skylake_get_display_clock_speed;
14730 else if (IS_BROADWELL(dev))
14731 dev_priv->display.get_display_clock_speed =
14732 broadwell_get_display_clock_speed;
14733 else if (IS_HASWELL(dev))
14734 dev_priv->display.get_display_clock_speed =
14735 haswell_get_display_clock_speed;
14736 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14737 dev_priv->display.get_display_clock_speed =
14738 valleyview_get_display_clock_speed;
b37a6434
VS		 14739 else if (IS_GEN5(dev))
14740 dev_priv->display.get_display_clock_speed =
14741 ilk_get_display_clock_speed;
a7c66cd8 14742 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14743 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14744 dev_priv->display.get_display_clock_speed =
14745 i945_get_display_clock_speed;
34edce2f
VS		 14746 else if (IS_GM45(dev))
14747 dev_priv->display.get_display_clock_speed =
14748 gm45_get_display_clock_speed;
14749 else if (IS_CRESTLINE(dev))
14750 dev_priv->display.get_display_clock_speed =
14751 i965gm_get_display_clock_speed;
14752 else if (IS_PINEVIEW(dev))
14753 dev_priv->display.get_display_clock_speed =
14754 pnv_get_display_clock_speed;
14755 else if (IS_G33(dev) || IS_G4X(dev))
14756 dev_priv->display.get_display_clock_speed =
14757 g33_get_display_clock_speed;
e70236a8
JB		 14758 else if (IS_I915G(dev))
14759 dev_priv->display.get_display_clock_speed =
14760 i915_get_display_clock_speed;
257a7ffc 14761 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14762 dev_priv->display.get_display_clock_speed =
14763 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14764 else if (IS_PINEVIEW(dev))
14765 dev_priv->display.get_display_clock_speed =
14766 pnv_get_display_clock_speed;
e70236a8
JB		 14767 else if (IS_I915GM(dev))
14768 dev_priv->display.get_display_clock_speed =
14769 i915gm_get_display_clock_speed;
14770 else if (IS_I865G(dev))
14771 dev_priv->display.get_display_clock_speed =
14772 i865_get_display_clock_speed;
f0f8a9ce 14773 else if (IS_I85X(dev))
e70236a8 14774 dev_priv->display.get_display_clock_speed =
1b1d2716 14775 i85x_get_display_clock_speed;
623e01e5
VS		 14776 else { /* 830 */
14777 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14778 dev_priv->display.get_display_clock_speed =
14779 i830_get_display_clock_speed;
623e01e5 14780 }
e70236a8 14781
7c10a2b5 14782 if (IS_GEN5(dev)) {
3bb11b53 14783 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14784 } else if (IS_GEN6(dev)) {
14785 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14786 } else if (IS_IVYBRIDGE(dev)) {
14787 /* FIXME: detect B0+ stepping and use auto training */
14788 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14789 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14790 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
b432e5cf
VS		 14791 if (IS_BROADWELL(dev))
14792 dev_priv->display.modeset_global_resources =
14793 broadwell_modeset_global_resources;
30a970c6
JB		 14794 } else if (IS_VALLEYVIEW(dev)) {
14795 dev_priv->display.modeset_global_resources =
14796 valleyview_modeset_global_resources;
f8437dd1
VK		 14797 } else if (IS_BROXTON(dev)) {
14798 dev_priv->display.modeset_global_resources =
14799 broxton_modeset_global_resources;
e70236a8 14800 }
8c9f3aaf 14801
8c9f3aaf
JB		 14802 switch (INTEL_INFO(dev)->gen) {
14803 case 2:
14804 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14805 break;
14806
14807 case 3:
14808 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14809 break;
14810
14811 case 4:
14812 case 5:
14813 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14814 break;
14815
14816 case 6:
14817 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14818 break;
7c9017e5 14819 case 7:
4e0bbc31 14820 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14821 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14822 break;
830c81db 14823 case 9:
ba343e02
TU		 14824 /* Drop through - unsupported since execlist only. */
14825 default:
14826 /* Default just returns -ENODEV to indicate unsupported */
14827 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14828 }
7bd688cd
JN		 14829
14830 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14831
14832 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14833}
14834
b690e96c
JB		 14835/*
14836 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14837 * resume, or other times. This quirk makes sure that's the case for
14838 * affected systems.
14839 */
0206e353 14840static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14841{
14842 struct drm_i915_private *dev_priv = dev->dev_private;
14843
14844 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14845 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14846}
14847
b6b5d049
VS		 14848static void quirk_pipeb_force(struct drm_device *dev)
14849{
14850 struct drm_i915_private *dev_priv = dev->dev_private;
14851
14852 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14853 DRM_INFO("applying pipe b force quirk\n");
14854}
14855
435793df
KP		 14856/*
14857 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14858 */
14859static void quirk_ssc_force_disable(struct drm_device *dev)
14860{
14861 struct drm_i915_private *dev_priv = dev->dev_private;
14862 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14863 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14864}
14865
4dca20ef 14866/*
5a15ab5b
CE		 14867 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14868 * brightness value
4dca20ef
CE		 14869 */
14870static void quirk_invert_brightness(struct drm_device *dev)
14871{
14872 struct drm_i915_private *dev_priv = dev->dev_private;
14873 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14874 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14875}
14876
9c72cc6f
SD		 14877/* Some VBT's incorrectly indicate no backlight is present */
14878static void quirk_backlight_present(struct drm_device *dev)
14879{
14880 struct drm_i915_private *dev_priv = dev->dev_private;
14881 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14882 DRM_INFO("applying backlight present quirk\n");
14883}
14884
b690e96c
JB		 14885struct intel_quirk {
14886 int device;
14887 int subsystem_vendor;
14888 int subsystem_device;
14889 void (*hook)(struct drm_device *dev);
14890};
14891
5f85f176
EE		 14892/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14893struct intel_dmi_quirk {
14894 void (*hook)(struct drm_device *dev);
14895 const struct dmi_system_id (*dmi_id_list)[];
14896};
14897
14898static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14899{
14900 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14901 return 1;
14902}
14903
14904static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14905 {
14906 .dmi_id_list = &(const struct dmi_system_id[]) {
14907 {
14908 .callback = intel_dmi_reverse_brightness,
14909 .ident = "NCR Corporation",
14910 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14911 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14912 },
14913 },
14914 { } /* terminating entry */
14915 },
14916 .hook = quirk_invert_brightness,
14917 },
14918};
14919
c43b5634 14920static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14921 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14922 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14923
b690e96c
JB		 14924 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14925 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14926
5f080c0f
VS		 14927 /* 830 needs to leave pipe A & dpll A up */
14928 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14929
b6b5d049
VS		 14930 /* 830 needs to leave pipe B & dpll B up */
14931 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14932
435793df
KP		 14933 /* Lenovo U160 cannot use SSC on LVDS */
14934 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14935
14936 /* Sony Vaio Y cannot use SSC on LVDS */
14937 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14938
be505f64
AH		 14939 /* Acer Aspire 5734Z must invert backlight brightness */
14940 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14941
14942 /* Acer/eMachines G725 */
14943 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14944
14945 /* Acer/eMachines e725 */
14946 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14947
14948 /* Acer/Packard Bell NCL20 */
14949 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14950
14951 /* Acer Aspire 4736Z */
14952 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14953
14954 /* Acer Aspire 5336 */
14955 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14956
14957 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14958 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14959
dfb3d47b
SD		 14960 /* Acer C720 Chromebook (Core i3 4005U) */
14961 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14962
b2a9601c 14963 /* Apple Macbook 2,1 (Core 2 T7400) */
14964 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14965
d4967d8c
SD		 14966 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14967 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14968
14969 /* HP Chromebook 14 (Celeron 2955U) */
14970 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14971
14972 /* Dell Chromebook 11 */
14973 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14974};
14975
14976static void intel_init_quirks(struct drm_device *dev)
14977{
14978 struct pci_dev *d = dev->pdev;
14979 int i;
14980
14981 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14982 struct intel_quirk *q = &intel_quirks[i];
14983
14984 if (d->device == q->device &&
14985 (d->subsystem_vendor == q->subsystem_vendor ||
14986 q->subsystem_vendor == PCI_ANY_ID) &&
14987 (d->subsystem_device == q->subsystem_device ||
14988 q->subsystem_device == PCI_ANY_ID))
14989 q->hook(dev);
14990 }
5f85f176
EE		 14991 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14992 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14993 intel_dmi_quirks[i].hook(dev);
14994 }
b690e96c
JB		 14995}
14996
9cce37f4
JB		 14997/* Disable the VGA plane that we never use */
14998static void i915_disable_vga(struct drm_device *dev)
14999{
15000 struct drm_i915_private *dev_priv = dev->dev_private;
15001 u8 sr1;
766aa1c4 15002 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 15003
2b37c616 15004 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 15005 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 15006 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 15007 sr1 = inb(VGA_SR_DATA);
15008 outb(sr1 | 1<<5, VGA_SR_DATA);
15009 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15010 udelay(300);
15011
01f5a626 15012 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 15013 POSTING_READ(vga_reg);
15014}
15015
f817586c
DV		 15016void intel_modeset_init_hw(struct drm_device *dev)
15017{
b6283055 15018 intel_update_cdclk(dev);
a8f78b58 15019 intel_prepare_ddi(dev);
f817586c 15020 intel_init_clock_gating(dev);
8090c6b9 15021 intel_enable_gt_powersave(dev);
f817586c
DV		 15022}
15023
79e53945
JB		 15024void intel_modeset_init(struct drm_device *dev)
15025{
652c393a 15026 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 15027 int sprite, ret;
8cc87b75 15028 enum pipe pipe;
46f297fb 15029 struct intel_crtc *crtc;
79e53945
JB		 15030
15031 drm_mode_config_init(dev);
15032
15033 dev->mode_config.min_width = 0;
15034 dev->mode_config.min_height = 0;
15035
019d96cb
DA		 15036 dev->mode_config.preferred_depth = 24;
15037 dev->mode_config.prefer_shadow = 1;
15038
25bab385
TU		 15039 dev->mode_config.allow_fb_modifiers = true;
15040
e6ecefaa 15041 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15042
b690e96c
JB		 15043 intel_init_quirks(dev);
15044
1fa61106
ED		 15045 intel_init_pm(dev);
15046
e3c74757
BW		 15047 if (INTEL_INFO(dev)->num_pipes == 0)
15048 return;
15049
e70236a8 15050 intel_init_display(dev);
7c10a2b5 15051 intel_init_audio(dev);
e70236a8 15052
a6c45cf0
CW		 15053 if (IS_GEN2(dev)) {
15054 dev->mode_config.max_width = 2048;
15055 dev->mode_config.max_height = 2048;
15056 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15057 dev->mode_config.max_width = 4096;
15058 dev->mode_config.max_height = 4096;
79e53945 15059 } else {
a6c45cf0
CW		 15060 dev->mode_config.max_width = 8192;
15061 dev->mode_config.max_height = 8192;
79e53945 15062 }
068be561 15063
dc41c154
VS		 15064 if (IS_845G(dev) || IS_I865G(dev)) {
15065 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15066 dev->mode_config.cursor_height = 1023;
15067 } else if (IS_GEN2(dev)) {
068be561
DL		 15068 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15069 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15070 } else {
15071 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15072 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15073 }
15074
5d4545ae 15075 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15076
28c97730 15077 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15078 INTEL_INFO(dev)->num_pipes,
15079 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15080
055e393f 15081 for_each_pipe(dev_priv, pipe) {
8cc87b75 15082 intel_crtc_init(dev, pipe);
3bdcfc0c 15083 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15084 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15085 if (ret)
06da8da2 15086 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15087 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15088 }
79e53945
JB		 15089 }
15090
f42bb70d
JB		 15091 intel_init_dpio(dev);
15092
e72f9fbf 15093 intel_shared_dpll_init(dev);
ee7b9f93 15094
9cce37f4
JB		 15095 /* Just disable it once at startup */
15096 i915_disable_vga(dev);
79e53945 15097 intel_setup_outputs(dev);
11be49eb
CW		 15098
15099 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15100 intel_fbc_disable(dev);
fa9fa083 15101
6e9f798d 15102 drm_modeset_lock_all(dev);
fa9fa083 15103 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15104 drm_modeset_unlock_all(dev);
46f297fb 15105
d3fcc808 15106 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15107 if (!crtc->active)
15108 continue;
15109
46f297fb 15110 /*
46f297fb
JB		 15111 * Note that reserving the BIOS fb up front prevents us
15112 * from stuffing other stolen allocations like the ring
15113 * on top. This prevents some ugliness at boot time, and
15114 * can even allow for smooth boot transitions if the BIOS
15115 * fb is large enough for the active pipe configuration.
15116 */
5724dbd1
DL		 15117 if (dev_priv->display.get_initial_plane_config) {
15118 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15119 &crtc->plane_config);
15120 /*
15121 * If the fb is shared between multiple heads, we'll
15122 * just get the first one.
15123 */
f6936e29 15124 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15125 }
46f297fb 15126 }
2c7111db
CW		 15127}
15128
7fad798e
DV		 15129static void intel_enable_pipe_a(struct drm_device *dev)
15130{
15131 struct intel_connector *connector;
15132 struct drm_connector *crt = NULL;
15133 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15134 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15135
15136 /* We can't just switch on the pipe A, we need to set things up with a
15137 * proper mode and output configuration. As a gross hack, enable pipe A
15138 * by enabling the load detect pipe once. */
3a3371ff 15139 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15140 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15141 crt = &connector->base;
15142 break;
15143 }
15144 }
15145
15146 if (!crt)
15147 return;
15148
208bf9fd 15149 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15150 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15151}
15152
fa555837
DV		 15153static bool
15154intel_check_plane_mapping(struct intel_crtc *crtc)
15155{
7eb552ae
BW		 15156 struct drm_device *dev = crtc->base.dev;
15157 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15158 u32 reg, val;
15159
7eb552ae 15160 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15161 return true;
15162
15163 reg = DSPCNTR(!crtc->plane);
15164 val = I915_READ(reg);
15165
15166 if ((val & DISPLAY_PLANE_ENABLE) &&
15167 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15168 return false;
15169
15170 return true;
15171}
15172
24929352
DV		 15173static void intel_sanitize_crtc(struct intel_crtc *crtc)
15174{
15175 struct drm_device *dev = crtc->base.dev;
15176 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 15177 struct intel_encoder *encoder;
fa555837 15178 u32 reg;
b17d48e2 15179 bool enable;
24929352 15180
24929352 15181 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15182 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15183 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15184
d3eaf884 15185 /* restore vblank interrupts to correct state */
9625604c 15186 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15187 if (crtc->active) {
15188 update_scanline_offset(crtc);
9625604c
DV		 15189 drm_crtc_vblank_on(&crtc->base);
15190 }
d3eaf884 15191
24929352 15192 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15193 * disable the crtc (and hence change the state) if it is wrong. Note
15194 * that gen4+ has a fixed plane -> pipe mapping. */
15195 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15196 bool plane;
15197
24929352
DV		 15198 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15199 crtc->base.base.id);
15200
15201 /* Pipe has the wrong plane attached and the plane is active.
15202 * Temporarily change the plane mapping and disable everything
15203 * ... */
15204 plane = crtc->plane;
b70709a6 15205 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15206 crtc->plane = !plane;
b17d48e2 15207 intel_crtc_disable_noatomic(&crtc->base);
24929352 15208 crtc->plane = plane;
24929352 15209 }
24929352 15210
7fad798e
DV		 15211 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15212 crtc->pipe == PIPE_A && !crtc->active) {
15213 /* BIOS forgot to enable pipe A, this mostly happens after
15214 * resume. Force-enable the pipe to fix this, the update_dpms
15215 * call below we restore the pipe to the right state, but leave
15216 * the required bits on. */
15217 intel_enable_pipe_a(dev);
15218 }
15219
24929352
DV		 15220 /* Adjust the state of the output pipe according to whether we
15221 * have active connectors/encoders. */
b17d48e2
ML		 15222 enable = false;
15223 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15224 enable |= encoder->connectors_active;
24929352 15225
b17d48e2
ML		 15226 if (!enable)
15227 intel_crtc_disable_noatomic(&crtc->base);
24929352 15228
53d9f4e9 15229 if (crtc->active != crtc->base.state->active) {
24929352
DV		 15230
15231 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15232 * functions or because of calls to intel_crtc_disable_noatomic,
15233 * or because the pipe is force-enabled due to the
24929352
DV		 15234 * pipe A quirk. */
15235 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15236 crtc->base.base.id,
83d65738 15237 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15238 crtc->active ? "enabled" : "disabled");
15239
83d65738 15240 crtc->base.state->enable = crtc->active;
49d6fa21 15241 crtc->base.state->active = crtc->active;
24929352
DV		 15242 crtc->base.enabled = crtc->active;
15243
15244 /* Because we only establish the connector -> encoder ->
15245 * crtc links if something is active, this means the
15246 * crtc is now deactivated. Break the links. connector
15247 * -> encoder links are only establish when things are
15248 * actually up, hence no need to break them. */
15249 WARN_ON(crtc->active);
15250
15251 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15252 WARN_ON(encoder->connectors_active);
15253 encoder->base.crtc = NULL;
15254 }
15255 }
c5ab3bc0 15256
a3ed6aad 15257 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15258 /*
15259 * We start out with underrun reporting disabled to avoid races.
15260 * For correct bookkeeping mark this on active crtcs.
15261 *
c5ab3bc0
DV		 15262 * Also on gmch platforms we dont have any hardware bits to
15263 * disable the underrun reporting. Which means we need to start
15264 * out with underrun reporting disabled also on inactive pipes,
15265 * since otherwise we'll complain about the garbage we read when
15266 * e.g. coming up after runtime pm.
15267 *
4cc31489
DV		 15268 * No protection against concurrent access is required - at
15269 * worst a fifo underrun happens which also sets this to false.
15270 */
15271 crtc->cpu_fifo_underrun_disabled = true;
15272 crtc->pch_fifo_underrun_disabled = true;
15273 }
24929352
DV		 15274}
15275
15276static void intel_sanitize_encoder(struct intel_encoder *encoder)
15277{
15278 struct intel_connector *connector;
15279 struct drm_device *dev = encoder->base.dev;
15280
15281 /* We need to check both for a crtc link (meaning that the
15282 * encoder is active and trying to read from a pipe) and the
15283 * pipe itself being active. */
15284 bool has_active_crtc = encoder->base.crtc &&
15285 to_intel_crtc(encoder->base.crtc)->active;
15286
15287 if (encoder->connectors_active && !has_active_crtc) {
15288 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15289 encoder->base.base.id,
8e329a03 15290 encoder->base.name);
24929352
DV		 15291
15292 /* Connector is active, but has no active pipe. This is
15293 * fallout from our resume register restoring. Disable
15294 * the encoder manually again. */
15295 if (encoder->base.crtc) {
15296 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15297 encoder->base.base.id,
8e329a03 15298 encoder->base.name);
24929352 15299 encoder->disable(encoder);
a62d1497
VS		 15300 if (encoder->post_disable)
15301 encoder->post_disable(encoder);
24929352 15302 }
7f1950fb
EE		 15303 encoder->base.crtc = NULL;
15304 encoder->connectors_active = false;
24929352
DV		 15305
15306 /* Inconsistent output/port/pipe state happens presumably due to
15307 * a bug in one of the get_hw_state functions. Or someplace else
15308 * in our code, like the register restore mess on resume. Clamp
15309 * things to off as a safer default. */
3a3371ff 15310 for_each_intel_connector(dev, connector) {
24929352
DV		 15311 if (connector->encoder != encoder)
15312 continue;
7f1950fb
EE		 15313 connector->base.dpms = DRM_MODE_DPMS_OFF;
15314 connector->base.encoder = NULL;
24929352
DV		 15315 }
15316 }
15317 /* Enabled encoders without active connectors will be fixed in
15318 * the crtc fixup. */
15319}
15320
04098753 15321void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15322{
15323 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15324 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15325
04098753
ID		 15326 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15327 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15328 i915_disable_vga(dev);
15329 }
15330}
15331
15332void i915_redisable_vga(struct drm_device *dev)
15333{
15334 struct drm_i915_private *dev_priv = dev->dev_private;
15335
8dc8a27c
PZ		 15336 /* This function can be called both from intel_modeset_setup_hw_state or
15337 * at a very early point in our resume sequence, where the power well
15338 * structures are not yet restored. Since this function is at a very
15339 * paranoid "someone might have enabled VGA while we were not looking"
15340 * level, just check if the power well is enabled instead of trying to
15341 * follow the "don't touch the power well if we don't need it" policy
15342 * the rest of the driver uses. */
f458ebbc 15343 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15344 return;
15345
04098753 15346 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15347}
15348
98ec7739
VS		 15349static bool primary_get_hw_state(struct intel_crtc *crtc)
15350{
15351 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15352
15353 if (!crtc->active)
15354 return false;
15355
15356 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15357}
15358
30e984df 15359static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15360{
15361 struct drm_i915_private *dev_priv = dev->dev_private;
15362 enum pipe pipe;
24929352
DV		 15363 struct intel_crtc *crtc;
15364 struct intel_encoder *encoder;
15365 struct intel_connector *connector;
5358901f 15366 int i;
24929352 15367
d3fcc808 15368 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15369 struct drm_plane *primary = crtc->base.primary;
15370 struct intel_plane_state *plane_state;
15371
6e3c9717 15372 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15373 crtc->config->base.crtc = &crtc->base;
3b117c8f 15374
6e3c9717 15375 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15376
0e8ffe1b 15377 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15378 crtc->config);
24929352 15379
83d65738 15380 crtc->base.state->enable = crtc->active;
49d6fa21 15381 crtc->base.state->active = crtc->active;
24929352 15382 crtc->base.enabled = crtc->active;
b8b7fade 15383 crtc->base.hwmode = crtc->config->base.adjusted_mode;
b70709a6
ML		 15384
15385 plane_state = to_intel_plane_state(primary->state);
15386 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15387
15388 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15389 crtc->base.base.id,
15390 crtc->active ? "enabled" : "disabled");
15391 }
15392
5358901f
DV		 15393 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15394 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15395
3e369b76
ACO		 15396 pll->on = pll->get_hw_state(dev_priv, pll,
15397 &pll->config.hw_state);
5358901f 15398 pll->active = 0;
3e369b76 15399 pll->config.crtc_mask = 0;
d3fcc808 15400 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15401 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15402 pll->active++;
3e369b76 15403 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15404 }
5358901f 15405 }
5358901f 15406
1e6f2ddc 15407 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15408 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15409
3e369b76 15410 if (pll->config.crtc_mask)
bd2bb1b9 15411 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15412 }
15413
b2784e15 15414 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15415 pipe = 0;
15416
15417 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15418 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15419 encoder->base.crtc = &crtc->base;
6e3c9717 15420 encoder->get_config(encoder, crtc->config);
24929352
DV		 15421 } else {
15422 encoder->base.crtc = NULL;
15423 }
15424
15425 encoder->connectors_active = false;
6f2bcceb 15426 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15427 encoder->base.base.id,
8e329a03 15428 encoder->base.name,
24929352 15429 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15430 pipe_name(pipe));
24929352
DV		 15431 }
15432
3a3371ff 15433 for_each_intel_connector(dev, connector) {
24929352
DV		 15434 if (connector->get_hw_state(connector)) {
15435 connector->base.dpms = DRM_MODE_DPMS_ON;
15436 connector->encoder->connectors_active = true;
15437 connector->base.encoder = &connector->encoder->base;
15438 } else {
15439 connector->base.dpms = DRM_MODE_DPMS_OFF;
15440 connector->base.encoder = NULL;
15441 }
15442 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15443 connector->base.base.id,
c23cc417 15444 connector->base.name,
24929352
DV		 15445 connector->base.encoder ? "enabled" : "disabled");
15446 }
30e984df
DV		 15447}
15448
15449/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15450 * and i915 state tracking structures. */
15451void intel_modeset_setup_hw_state(struct drm_device *dev,
15452 bool force_restore)
15453{
15454 struct drm_i915_private *dev_priv = dev->dev_private;
15455 enum pipe pipe;
30e984df
DV		 15456 struct intel_crtc *crtc;
15457 struct intel_encoder *encoder;
35c95375 15458 int i;
30e984df
DV		 15459
15460 intel_modeset_readout_hw_state(dev);
24929352 15461
babea61d
JB		 15462 /*
15463 * Now that we have the config, copy it to each CRTC struct
15464 * Note that this could go away if we move to using crtc_config
15465 * checking everywhere.
15466 */
d3fcc808 15467 for_each_intel_crtc(dev, crtc) {
d330a953 15468 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15469 intel_mode_from_pipe_config(&crtc->base.mode,
15470 crtc->config);
babea61d
JB		 15471 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15472 crtc->base.base.id);
15473 drm_mode_debug_printmodeline(&crtc->base.mode);
15474 }
15475 }
15476
24929352 15477 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15478 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15479 intel_sanitize_encoder(encoder);
15480 }
15481
055e393f 15482 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15483 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15484 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15485 intel_dump_pipe_config(crtc, crtc->config,
15486 "[setup_hw_state]");
24929352 15487 }
9a935856 15488
d29b2f9d
ACO		 15489 intel_modeset_update_connector_atomic_state(dev);
15490
35c95375
DV		 15491 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15492 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15493
15494 if (!pll->on || pll->active)
15495 continue;
15496
15497 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15498
15499 pll->disable(dev_priv, pll);
15500 pll->on = false;
15501 }
15502
3078999f
PB		 15503 if (IS_GEN9(dev))
15504 skl_wm_get_hw_state(dev);
15505 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15506 ilk_wm_get_hw_state(dev);
15507
45e2b5f6 15508 if (force_restore) {
7d0bc1ea
VS		 15509 i915_redisable_vga(dev);
15510
f30da187
DV		 15511 /*
15512 * We need to use raw interfaces for restoring state to avoid
15513 * checking (bogus) intermediate states.
15514 */
055e393f 15515 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15516 struct drm_crtc *crtc =
15517 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15518
83a57153 15519 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15520 }
15521 } else {
15522 intel_modeset_update_staged_output_state(dev);
15523 }
8af6cf88
DV		 15524
15525 intel_modeset_check_state(dev);
2c7111db
CW		 15526}
15527
15528void intel_modeset_gem_init(struct drm_device *dev)
15529{
92122789 15530 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15531 struct drm_crtc *c;
2ff8fde1 15532 struct drm_i915_gem_object *obj;
e0d6149b 15533 int ret;
484b41dd 15534
ae48434c
ID		 15535 mutex_lock(&dev->struct_mutex);
15536 intel_init_gt_powersave(dev);
15537 mutex_unlock(&dev->struct_mutex);
15538
92122789
JB		 15539 /*
15540 * There may be no VBT; and if the BIOS enabled SSC we can
15541 * just keep using it to avoid unnecessary flicker. Whereas if the
15542 * BIOS isn't using it, don't assume it will work even if the VBT
15543 * indicates as much.
15544 */
15545 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15546 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15547 DREF_SSC1_ENABLE);
15548
1833b134 15549 intel_modeset_init_hw(dev);
02e792fb
DV		 15550
15551 intel_setup_overlay(dev);
484b41dd
JB		 15552
15553 /*
15554 * Make sure any fbs we allocated at startup are properly
15555 * pinned & fenced. When we do the allocation it's too early
15556 * for this.
15557 */
70e1e0ec 15558 for_each_crtc(dev, c) {
2ff8fde1
MR		 15559 obj = intel_fb_obj(c->primary->fb);
15560 if (obj == NULL)
484b41dd
JB		 15561 continue;
15562
e0d6149b
TU		 15563 mutex_lock(&dev->struct_mutex);
15564 ret = intel_pin_and_fence_fb_obj(c->primary,
15565 c->primary->fb,
15566 c->primary->state,
15567 NULL);
15568 mutex_unlock(&dev->struct_mutex);
15569 if (ret) {
484b41dd
JB		 15570 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15571 to_intel_crtc(c)->pipe);
66e514c1
DA		 15572 drm_framebuffer_unreference(c->primary->fb);
15573 c->primary->fb = NULL;
36750f28 15574 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15575 update_state_fb(c->primary);
36750f28 15576 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15577 }
15578 }
0962c3c9
VS		 15579
15580 intel_backlight_register(dev);
79e53945
JB		 15581}
15582
4932e2c3
ID		 15583void intel_connector_unregister(struct intel_connector *intel_connector)
15584{
15585 struct drm_connector *connector = &intel_connector->base;
15586
15587 intel_panel_destroy_backlight(connector);
34ea3d38 15588 drm_connector_unregister(connector);
4932e2c3
ID		 15589}
15590
79e53945
JB		 15591void intel_modeset_cleanup(struct drm_device *dev)
15592{
652c393a 15593 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15594 struct drm_connector *connector;
652c393a 15595
2eb5252e
ID		 15596 intel_disable_gt_powersave(dev);
15597
0962c3c9
VS		 15598 intel_backlight_unregister(dev);
15599
fd0c0642
DV		 15600 /*
15601 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15602 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15603 * experience fancy races otherwise.
15604 */
2aeb7d3a 15605 intel_irq_uninstall(dev_priv);
eb21b92b 15606
fd0c0642
DV		 15607 /*
15608 * Due to the hpd irq storm handling the hotplug work can re-arm the
15609 * poll handlers. Hence disable polling after hpd handling is shut down.
15610 */
f87ea761 15611 drm_kms_helper_poll_fini(dev);
fd0c0642 15612
652c393a
JB		 15613 mutex_lock(&dev->struct_mutex);
15614
723bfd70
JB		 15615 intel_unregister_dsm_handler();
15616
7ff0ebcc 15617 intel_fbc_disable(dev);
e70236a8 15618
69341a5e
KH		 15619 mutex_unlock(&dev->struct_mutex);
15620
1630fe75
CW		 15621 /* flush any delayed tasks or pending work */
15622 flush_scheduled_work();
15623
db31af1d
JN		 15624 /* destroy the backlight and sysfs files before encoders/connectors */
15625 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15626 struct intel_connector *intel_connector;
15627
15628 intel_connector = to_intel_connector(connector);
15629 intel_connector->unregister(intel_connector);
db31af1d 15630 }
d9255d57 15631
79e53945 15632 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15633
15634 intel_cleanup_overlay(dev);
ae48434c
ID		 15635
15636 mutex_lock(&dev->struct_mutex);
15637 intel_cleanup_gt_powersave(dev);
15638 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15639}
15640
f1c79df3
ZW		 15641/*
15642 * Return which encoder is currently attached for connector.
15643 */
df0e9248 15644struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15645{
df0e9248
CW		 15646 return &intel_attached_encoder(connector)->base;
15647}
f1c79df3 15648
df0e9248
CW		 15649void intel_connector_attach_encoder(struct intel_connector *connector,
15650 struct intel_encoder *encoder)
15651{
15652 connector->encoder = encoder;
15653 drm_mode_connector_attach_encoder(&connector->base,
15654 &encoder->base);
79e53945 15655}
28d52043
DA		 15656
15657/*
15658 * set vga decode state - true == enable VGA decode
15659 */
15660int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15661{
15662 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15663 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15664 u16 gmch_ctrl;
15665
75fa041d
CW		 15666 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15667 DRM_ERROR("failed to read control word\n");
15668 return -EIO;
15669 }
15670
c0cc8a55
CW		 15671 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15672 return 0;
15673
28d52043
DA		 15674 if (state)
15675 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15676 else
15677 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15678
15679 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15680 DRM_ERROR("failed to write control word\n");
15681 return -EIO;
15682 }
15683
28d52043
DA		 15684 return 0;
15685}
c4a1d9e4 15686
c4a1d9e4 15687struct intel_display_error_state {
ff57f1b0
PZ		 15688
15689 u32 power_well_driver;
15690
63b66e5b
CW		 15691 int num_transcoders;
15692
c4a1d9e4
CW		 15693 struct intel_cursor_error_state {
15694 u32 control;
15695 u32 position;
15696 u32 base;
15697 u32 size;
52331309 15698 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15699
15700 struct intel_pipe_error_state {
ddf9c536 15701 bool power_domain_on;
c4a1d9e4 15702 u32 source;
f301b1e1 15703 u32 stat;
52331309 15704 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15705
15706 struct intel_plane_error_state {
15707 u32 control;
15708 u32 stride;
15709 u32 size;
15710 u32 pos;
15711 u32 addr;
15712 u32 surface;
15713 u32 tile_offset;
52331309 15714 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15715
15716 struct intel_transcoder_error_state {
ddf9c536 15717 bool power_domain_on;
63b66e5b
CW		 15718 enum transcoder cpu_transcoder;
15719
15720 u32 conf;
15721
15722 u32 htotal;
15723 u32 hblank;
15724 u32 hsync;
15725 u32 vtotal;
15726 u32 vblank;
15727 u32 vsync;
15728 } transcoder[4];
c4a1d9e4
CW		 15729};
15730
15731struct intel_display_error_state *
15732intel_display_capture_error_state(struct drm_device *dev)
15733{
fbee40df 15734 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15735 struct intel_display_error_state *error;
63b66e5b
CW		 15736 int transcoders[] = {
15737 TRANSCODER_A,
15738 TRANSCODER_B,
15739 TRANSCODER_C,
15740 TRANSCODER_EDP,
15741 };
c4a1d9e4
CW		 15742 int i;
15743
63b66e5b
CW		 15744 if (INTEL_INFO(dev)->num_pipes == 0)
15745 return NULL;
15746
9d1cb914 15747 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15748 if (error == NULL)
15749 return NULL;
15750
190be112 15751 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15752 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15753
055e393f 15754 for_each_pipe(dev_priv, i) {
ddf9c536 15755 error->pipe[i].power_domain_on =
f458ebbc
DV		 15756 __intel_display_power_is_enabled(dev_priv,
15757 POWER_DOMAIN_PIPE(i));
ddf9c536 15758 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15759 continue;
15760
5efb3e28
VS		 15761 error->cursor[i].control = I915_READ(CURCNTR(i));
15762 error->cursor[i].position = I915_READ(CURPOS(i));
15763 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15764
15765 error->plane[i].control = I915_READ(DSPCNTR(i));
15766 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15767 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15768 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15769 error->plane[i].pos = I915_READ(DSPPOS(i));
15770 }
ca291363
PZ		 15771 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15772 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15773 if (INTEL_INFO(dev)->gen >= 4) {
15774 error->plane[i].surface = I915_READ(DSPSURF(i));
15775 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15776 }
15777
c4a1d9e4 15778 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15779
3abfce77 15780 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15781 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15782 }
15783
15784 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15785 if (HAS_DDI(dev_priv->dev))
15786 error->num_transcoders++; /* Account for eDP. */
15787
15788 for (i = 0; i < error->num_transcoders; i++) {
15789 enum transcoder cpu_transcoder = transcoders[i];
15790
ddf9c536 15791 error->transcoder[i].power_domain_on =
f458ebbc 15792 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15793 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15794 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15795 continue;
15796
63b66e5b
CW		 15797 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15798
15799 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15800 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15801 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15802 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15803 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15804 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15805 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15806 }
15807
15808 return error;
15809}
15810
edc3d884
MK		 15811#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15812
c4a1d9e4 15813void
edc3d884 15814intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15815 struct drm_device *dev,
15816 struct intel_display_error_state *error)
15817{
055e393f 15818 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15819 int i;
15820
63b66e5b
CW		 15821 if (!error)
15822 return;
15823
edc3d884 15824 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15825 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15826 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15827 error->power_well_driver);
055e393f 15828 for_each_pipe(dev_priv, i) {
edc3d884 15829 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15830 err_printf(m, " Power: %s\n",
15831 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15832 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15833 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15834
15835 err_printf(m, "Plane [%d]:\n", i);
15836 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15837 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15838 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15839 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15840 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15841 }
4b71a570 15842 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15843 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15844 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15845 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15846 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15847 }
15848
edc3d884
MK		 15849 err_printf(m, "Cursor [%d]:\n", i);
15850 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15851 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15852 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15853 }
63b66e5b
CW		 15854
15855 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15856 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15857 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15858 err_printf(m, " Power: %s\n",
15859 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15860 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15861 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15862 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15863 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15864 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15865 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15866 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15867 }
c4a1d9e4 15868}
e2fcdaa9
VS		 15869
15870void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15871{
15872 struct intel_crtc *crtc;
15873
15874 for_each_intel_crtc(dev, crtc) {
15875 struct intel_unpin_work *work;
e2fcdaa9 15876
5e2d7afc 15877 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15878
15879 work = crtc->unpin_work;
15880
15881 if (work && work->event &&
15882 work->event->base.file_priv == file) {
15883 kfree(work->event);
15884 work->event = NULL;
15885 }
15886
5e2d7afc 15887 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15888 }
15889}
Linux kernel - Deliverables
This page took 3.140863 seconds and 5 git commands to generate.