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drm/i915: Read wm values from hardware at init on CHV
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
568c634a 89static int intel_set_mode(struct drm_atomic_state *state);
eb1bfe80
JB		 90static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
5b18e57c
DV		 94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
29407aab 99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 102static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
d288f65f 104static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 105 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 106static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 108static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
e7457a9a 112
0e32b39c
DA		 113static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
114{
115 if (!connector->mst_port)
116 return connector->encoder;
117 else
118 return &connector->mst_port->mst_encoders[pipe]->base;
119}
120
79e53945 121typedef struct {
0206e353 122 int min, max;
79e53945
JB		 123} intel_range_t;
124
125typedef struct {
0206e353
AJ		 126 int dot_limit;
127 int p2_slow, p2_fast;
79e53945
JB		 128} intel_p2_t;
129
d4906093
ML		 130typedef struct intel_limit intel_limit_t;
131struct intel_limit {
0206e353
AJ		 132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
d4906093 134};
79e53945 135
d2acd215
DV		 136int
137intel_pch_rawclk(struct drm_device *dev)
138{
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 WARN_ON(!HAS_PCH_SPLIT(dev));
142
143 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
144}
145
021357ac
CW		 146static inline u32 /* units of 100MHz */
147intel_fdi_link_freq(struct drm_device *dev)
148{
8b99e68c
CW		 149 if (IS_GEN5(dev)) {
150 struct drm_i915_private *dev_priv = dev->dev_private;
151 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
152 } else
153 return 27;
021357ac
CW		 154}
155
5d536e28 156static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 157 .dot = { .min = 25000, .max = 350000 },
9c333719 158 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 159 .n = { .min = 2, .max = 16 },
0206e353
AJ		 160 .m = { .min = 96, .max = 140 },
161 .m1 = { .min = 18, .max = 26 },
162 .m2 = { .min = 6, .max = 16 },
163 .p = { .min = 4, .max = 128 },
164 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 165 .p2 = { .dot_limit = 165000,
166 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 167};
168
5d536e28
DV		 169static const intel_limit_t intel_limits_i8xx_dvo = {
170 .dot = { .min = 25000, .max = 350000 },
9c333719 171 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 172 .n = { .min = 2, .max = 16 },
5d536e28
DV		 173 .m = { .min = 96, .max = 140 },
174 .m1 = { .min = 18, .max = 26 },
175 .m2 = { .min = 6, .max = 16 },
176 .p = { .min = 4, .max = 128 },
177 .p1 = { .min = 2, .max = 33 },
178 .p2 = { .dot_limit = 165000,
179 .p2_slow = 4, .p2_fast = 4 },
180};
181
e4b36699 182static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 183 .dot = { .min = 25000, .max = 350000 },
9c333719 184 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 185 .n = { .min = 2, .max = 16 },
0206e353
AJ		 186 .m = { .min = 96, .max = 140 },
187 .m1 = { .min = 18, .max = 26 },
188 .m2 = { .min = 6, .max = 16 },
189 .p = { .min = 4, .max = 128 },
190 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 191 .p2 = { .dot_limit = 165000,
192 .p2_slow = 14, .p2_fast = 7 },
e4b36699 193};
273e27ca 194
e4b36699 195static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 196 .dot = { .min = 20000, .max = 400000 },
197 .vco = { .min = 1400000, .max = 2800000 },
198 .n = { .min = 1, .max = 6 },
199 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 200 .m1 = { .min = 8, .max = 18 },
201 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 202 .p = { .min = 5, .max = 80 },
203 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 204 .p2 = { .dot_limit = 200000,
205 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 206};
207
208static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 209 .dot = { .min = 20000, .max = 400000 },
210 .vco = { .min = 1400000, .max = 2800000 },
211 .n = { .min = 1, .max = 6 },
212 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 213 .m1 = { .min = 8, .max = 18 },
214 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 215 .p = { .min = 7, .max = 98 },
216 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 217 .p2 = { .dot_limit = 112000,
218 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 219};
220
273e27ca 221
e4b36699 222static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 223 .dot = { .min = 25000, .max = 270000 },
224 .vco = { .min = 1750000, .max = 3500000},
225 .n = { .min = 1, .max = 4 },
226 .m = { .min = 104, .max = 138 },
227 .m1 = { .min = 17, .max = 23 },
228 .m2 = { .min = 5, .max = 11 },
229 .p = { .min = 10, .max = 30 },
230 .p1 = { .min = 1, .max = 3},
231 .p2 = { .dot_limit = 270000,
232 .p2_slow = 10,
233 .p2_fast = 10
044c7c41 234 },
e4b36699
KP		 235};
236
237static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 238 .dot = { .min = 22000, .max = 400000 },
239 .vco = { .min = 1750000, .max = 3500000},
240 .n = { .min = 1, .max = 4 },
241 .m = { .min = 104, .max = 138 },
242 .m1 = { .min = 16, .max = 23 },
243 .m2 = { .min = 5, .max = 11 },
244 .p = { .min = 5, .max = 80 },
245 .p1 = { .min = 1, .max = 8},
246 .p2 = { .dot_limit = 165000,
247 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 248};
249
250static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 251 .dot = { .min = 20000, .max = 115000 },
252 .vco = { .min = 1750000, .max = 3500000 },
253 .n = { .min = 1, .max = 3 },
254 .m = { .min = 104, .max = 138 },
255 .m1 = { .min = 17, .max = 23 },
256 .m2 = { .min = 5, .max = 11 },
257 .p = { .min = 28, .max = 112 },
258 .p1 = { .min = 2, .max = 8 },
259 .p2 = { .dot_limit = 0,
260 .p2_slow = 14, .p2_fast = 14
044c7c41 261 },
e4b36699
KP		 262};
263
264static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 265 .dot = { .min = 80000, .max = 224000 },
266 .vco = { .min = 1750000, .max = 3500000 },
267 .n = { .min = 1, .max = 3 },
268 .m = { .min = 104, .max = 138 },
269 .m1 = { .min = 17, .max = 23 },
270 .m2 = { .min = 5, .max = 11 },
271 .p = { .min = 14, .max = 42 },
272 .p1 = { .min = 2, .max = 6 },
273 .p2 = { .dot_limit = 0,
274 .p2_slow = 7, .p2_fast = 7
044c7c41 275 },
e4b36699
KP		 276};
277
f2b115e6 278static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 279 .dot = { .min = 20000, .max = 400000},
280 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 281 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 282 .n = { .min = 3, .max = 6 },
283 .m = { .min = 2, .max = 256 },
273e27ca 284 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 285 .m1 = { .min = 0, .max = 0 },
286 .m2 = { .min = 0, .max = 254 },
287 .p = { .min = 5, .max = 80 },
288 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 289 .p2 = { .dot_limit = 200000,
290 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 291};
292
f2b115e6 293static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 294 .dot = { .min = 20000, .max = 400000 },
295 .vco = { .min = 1700000, .max = 3500000 },
296 .n = { .min = 3, .max = 6 },
297 .m = { .min = 2, .max = 256 },
298 .m1 = { .min = 0, .max = 0 },
299 .m2 = { .min = 0, .max = 254 },
300 .p = { .min = 7, .max = 112 },
301 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 302 .p2 = { .dot_limit = 112000,
303 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 304};
305
273e27ca
EA		 306/* Ironlake / Sandybridge
307 *
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
310 */
b91ad0ec 311static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 312 .dot = { .min = 25000, .max = 350000 },
313 .vco = { .min = 1760000, .max = 3510000 },
314 .n = { .min = 1, .max = 5 },
315 .m = { .min = 79, .max = 127 },
316 .m1 = { .min = 12, .max = 22 },
317 .m2 = { .min = 5, .max = 9 },
318 .p = { .min = 5, .max = 80 },
319 .p1 = { .min = 1, .max = 8 },
320 .p2 = { .dot_limit = 225000,
321 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 322};
323
b91ad0ec 324static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 325 .dot = { .min = 25000, .max = 350000 },
326 .vco = { .min = 1760000, .max = 3510000 },
327 .n = { .min = 1, .max = 3 },
328 .m = { .min = 79, .max = 118 },
329 .m1 = { .min = 12, .max = 22 },
330 .m2 = { .min = 5, .max = 9 },
331 .p = { .min = 28, .max = 112 },
332 .p1 = { .min = 2, .max = 8 },
333 .p2 = { .dot_limit = 225000,
334 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 335};
336
337static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 338 .dot = { .min = 25000, .max = 350000 },
339 .vco = { .min = 1760000, .max = 3510000 },
340 .n = { .min = 1, .max = 3 },
341 .m = { .min = 79, .max = 127 },
342 .m1 = { .min = 12, .max = 22 },
343 .m2 = { .min = 5, .max = 9 },
344 .p = { .min = 14, .max = 56 },
345 .p1 = { .min = 2, .max = 8 },
346 .p2 = { .dot_limit = 225000,
347 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 348};
349
273e27ca 350/* LVDS 100mhz refclk limits. */
b91ad0ec 351static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 352 .dot = { .min = 25000, .max = 350000 },
353 .vco = { .min = 1760000, .max = 3510000 },
354 .n = { .min = 1, .max = 2 },
355 .m = { .min = 79, .max = 126 },
356 .m1 = { .min = 12, .max = 22 },
357 .m2 = { .min = 5, .max = 9 },
358 .p = { .min = 28, .max = 112 },
0206e353 359 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 360 .p2 = { .dot_limit = 225000,
361 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 362};
363
364static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 365 .dot = { .min = 25000, .max = 350000 },
366 .vco = { .min = 1760000, .max = 3510000 },
367 .n = { .min = 1, .max = 3 },
368 .m = { .min = 79, .max = 126 },
369 .m1 = { .min = 12, .max = 22 },
370 .m2 = { .min = 5, .max = 9 },
371 .p = { .min = 14, .max = 42 },
0206e353 372 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 373 .p2 = { .dot_limit = 225000,
374 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 375};
376
dc730512 377static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 378 /*
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
383 */
384 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 385 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 386 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 387 .m1 = { .min = 2, .max = 3 },
388 .m2 = { .min = 11, .max = 156 },
b99ab663 389 .p1 = { .min = 2, .max = 3 },
5fdc9c49 390 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 391};
392
ef9348c8
CML		 393static const intel_limit_t intel_limits_chv = {
394 /*
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
399 */
400 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 401 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 402 .n = { .min = 1, .max = 1 },
403 .m1 = { .min = 2, .max = 2 },
404 .m2 = { .min = 24 << 22, .max = 175 << 22 },
405 .p1 = { .min = 2, .max = 4 },
406 .p2 = { .p2_slow = 1, .p2_fast = 14 },
407};
408
5ab7b0b7
ID		 409static const intel_limit_t intel_limits_bxt = {
410 /* FIXME: find real dot limits */
411 .dot = { .min = 0, .max = INT_MAX },
412 .vco = { .min = 4800000, .max = 6480000 },
413 .n = { .min = 1, .max = 1 },
414 .m1 = { .min = 2, .max = 2 },
415 /* FIXME: find real m2 limits */
416 .m2 = { .min = 2 << 22, .max = 255 << 22 },
417 .p1 = { .min = 2, .max = 4 },
418 .p2 = { .p2_slow = 1, .p2_fast = 20 },
419};
420
6b4bf1c4
VS		 421static void vlv_clock(int refclk, intel_clock_t *clock)
422{
423 clock->m = clock->m1 * clock->m2;
424 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 425 if (WARN_ON(clock->n == 0 || clock->p == 0))
426 return;
fb03ac01
VS		 427 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
428 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 429}
430
cdba954e
ACO		 431static bool
432needs_modeset(struct drm_crtc_state *state)
433{
434 return state->mode_changed || state->active_changed;
435}
436
e0638cdf
PZ		 437/**
438 * Returns whether any output on the specified pipe is of the specified type
439 */
4093561b 440bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 441{
409ee761 442 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 443 struct intel_encoder *encoder;
444
409ee761 445 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 446 if (encoder->type == type)
447 return true;
448
449 return false;
450}
451
d0737e1d
ACO		 452/**
453 * Returns whether any output on the specified pipe will have the specified
454 * type after a staged modeset is complete, i.e., the same as
455 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
456 * encoder->crtc.
457 */
a93e255f
ACO		 458static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
459 int type)
d0737e1d 460{
a93e255f 461 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 462 struct drm_connector *connector;
a93e255f 463 struct drm_connector_state *connector_state;
d0737e1d 464 struct intel_encoder *encoder;
a93e255f
ACO		 465 int i, num_connectors = 0;
466
da3ced29 467 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 468 if (connector_state->crtc != crtc_state->base.crtc)
469 continue;
470
471 num_connectors++;
d0737e1d 472
a93e255f
ACO		 473 encoder = to_intel_encoder(connector_state->best_encoder);
474 if (encoder->type == type)
d0737e1d 475 return true;
a93e255f
ACO		 476 }
477
478 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 479
480 return false;
481}
482
a93e255f
ACO		 483static const intel_limit_t *
484intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 485{
a93e255f 486 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 487 const intel_limit_t *limit;
b91ad0ec 488
a93e255f 489 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 490 if (intel_is_dual_link_lvds(dev)) {
1b894b59 491 if (refclk == 100000)
b91ad0ec
ZW		 492 limit = &intel_limits_ironlake_dual_lvds_100m;
493 else
494 limit = &intel_limits_ironlake_dual_lvds;
495 } else {
1b894b59 496 if (refclk == 100000)
b91ad0ec
ZW		 497 limit = &intel_limits_ironlake_single_lvds_100m;
498 else
499 limit = &intel_limits_ironlake_single_lvds;
500 }
c6bb3538 501 } else
b91ad0ec 502 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 503
504 return limit;
505}
506
a93e255f
ACO		 507static const intel_limit_t *
508intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 509{
a93e255f 510 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 511 const intel_limit_t *limit;
512
a93e255f 513 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 514 if (intel_is_dual_link_lvds(dev))
e4b36699 515 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 516 else
e4b36699 517 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
519 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 520 limit = &intel_limits_g4x_hdmi;
a93e255f 521 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 522 limit = &intel_limits_g4x_sdvo;
044c7c41 523 } else /* The option is for other outputs */
e4b36699 524 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 525
526 return limit;
527}
528
a93e255f
ACO		 529static const intel_limit_t *
530intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 531{
a93e255f 532 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 533 const intel_limit_t *limit;
534
5ab7b0b7
ID		 535 if (IS_BROXTON(dev))
536 limit = &intel_limits_bxt;
537 else if (HAS_PCH_SPLIT(dev))
a93e255f 538 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
a93e255f 540 limit = intel_g4x_limit(crtc_state);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
a93e255f 542 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 546 } else if (IS_CHERRYVIEW(dev)) {
547 limit = &intel_limits_chv;
a0c4da24 548 } else if (IS_VALLEYVIEW(dev)) {
dc730512 549 limit = &intel_limits_vlv;
a6c45cf0 550 } else if (!IS_GEN2(dev)) {
a93e255f 551 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 552 limit = &intel_limits_i9xx_lvds;
553 else
554 limit = &intel_limits_i9xx_sdvo;
79e53945 555 } else {
a93e255f 556 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 557 limit = &intel_limits_i8xx_lvds;
a93e255f 558 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 559 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 560 else
561 limit = &intel_limits_i8xx_dac;
79e53945
JB		 562 }
563 return limit;
564}
565
f2b115e6
AJ		 566/* m1 is reserved as 0 in Pineview, n is a ring counter */
567static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 568{
2177832f
SL		 569 clock->m = clock->m2 + 2;
570 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 571 if (WARN_ON(clock->n == 0 || clock->p == 0))
572 return;
fb03ac01
VS		 573 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
574 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 575}
576
7429e9d4
DV		 577static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
578{
579 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
580}
581
ac58c3f0 582static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 583{
7429e9d4 584 clock->m = i9xx_dpll_compute_m(clock);
79e53945 585 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 586 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
587 return;
fb03ac01
VS		 588 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
589 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 590}
591
ef9348c8
CML		 592static void chv_clock(int refclk, intel_clock_t *clock)
593{
594 clock->m = clock->m1 * clock->m2;
595 clock->p = clock->p1 * clock->p2;
596 if (WARN_ON(clock->n == 0 || clock->p == 0))
597 return;
598 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
599 clock->n << 22);
600 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
f01b7962
VS		 613 if (clock->n < limit->n.min || limit->n.max < clock->n)
614 INTELPllInvalid("n out of range\n");
79e53945 615 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 616 INTELPllInvalid("p1 out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f01b7962 621
5ab7b0b7 622 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 623 if (clock->m1 <= clock->m2)
624 INTELPllInvalid("m1 <= m2\n");
625
5ab7b0b7 626 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 627 if (clock->p < limit->p.min || limit->p.max < clock->p)
628 INTELPllInvalid("p out of range\n");
629 if (clock->m < limit->m.min || limit->m.max < clock->m)
630 INTELPllInvalid("m out of range\n");
631 }
632
79e53945 633 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 634 INTELPllInvalid("vco out of range\n");
79e53945
JB		 635 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
636 * connector, etc., rather than just a single range.
637 */
638 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 639 INTELPllInvalid("dot out of range\n");
79e53945
JB		 640
641 return true;
642}
643
3b1429d9
VS		 644static int
645i9xx_select_p2_div(const intel_limit_t *limit,
646 const struct intel_crtc_state *crtc_state,
647 int target)
79e53945 648{
3b1429d9 649 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 650
a93e255f 651 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 652 /*
a210b028
DV		 653 * For LVDS just rely on its current settings for dual-channel.
654 * We haven't figured out how to reliably set up different
655 * single/dual channel state, if we even can.
79e53945 656 */
1974cad0 657 if (intel_is_dual_link_lvds(dev))
3b1429d9 658 return limit->p2.p2_fast;
79e53945 659 else
3b1429d9 660 return limit->p2.p2_slow;
79e53945
JB		 661 } else {
662 if (target < limit->p2.dot_limit)
3b1429d9 663 return limit->p2.p2_slow;
79e53945 664 else
3b1429d9 665 return limit->p2.p2_fast;
79e53945 666 }
3b1429d9
VS		 667}
668
669static bool
670i9xx_find_best_dpll(const intel_limit_t *limit,
671 struct intel_crtc_state *crtc_state,
672 int target, int refclk, intel_clock_t *match_clock,
673 intel_clock_t *best_clock)
674{
675 struct drm_device *dev = crtc_state->base.crtc->dev;
676 intel_clock_t clock;
677 int err = target;
79e53945 678
0206e353 679 memset(best_clock, 0, sizeof(*best_clock));
79e53945 680
3b1429d9
VS		 681 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
682
42158660
ZY		 683 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
684 clock.m1++) {
685 for (clock.m2 = limit->m2.min;
686 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 687 if (clock.m2 >= clock.m1)
42158660
ZY		 688 break;
689 for (clock.n = limit->n.min;
690 clock.n <= limit->n.max; clock.n++) {
691 for (clock.p1 = limit->p1.min;
692 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 693 int this_err;
694
ac58c3f0
DV		 695 i9xx_clock(refclk, &clock);
696 if (!intel_PLL_is_valid(dev, limit,
697 &clock))
698 continue;
699 if (match_clock &&
700 clock.p != match_clock->p)
701 continue;
702
703 this_err = abs(clock.dot - target);
704 if (this_err < err) {
705 *best_clock = clock;
706 err = this_err;
707 }
708 }
709 }
710 }
711 }
712
713 return (err != target);
714}
715
716static bool
a93e255f
ACO		 717pnv_find_best_dpll(const intel_limit_t *limit,
718 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 719 int target, int refclk, intel_clock_t *match_clock,
720 intel_clock_t *best_clock)
79e53945 721{
3b1429d9 722 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 723 intel_clock_t clock;
79e53945
JB		 724 int err = target;
725
0206e353 726 memset(best_clock, 0, sizeof(*best_clock));
79e53945 727
3b1429d9
VS		 728 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
729
42158660
ZY		 730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 738 int this_err;
739
ac58c3f0 740 pineview_clock(refclk, &clock);
1b894b59
CW		 741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
79e53945 743 continue;
cec2f356
SP		 744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
79e53945
JB		 747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759}
760
d4906093 761static bool
a93e255f
ACO		 762g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
d4906093 766{
3b1429d9 767 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 768 intel_clock_t clock;
769 int max_n;
3b1429d9 770 bool found = false;
6ba770dc
AJ		 771 /* approximately equals target * 0.00585 */
772 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 773
774 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
d4906093 778 max_n = limit->n.max;
f77f13e2 779 /* based on hardware requirement, prefer smaller n to precision */
d4906093 780 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 781 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 782 for (clock.m1 = limit->m1.max;
783 clock.m1 >= limit->m1.min; clock.m1--) {
784 for (clock.m2 = limit->m2.max;
785 clock.m2 >= limit->m2.min; clock.m2--) {
786 for (clock.p1 = limit->p1.max;
787 clock.p1 >= limit->p1.min; clock.p1--) {
788 int this_err;
789
ac58c3f0 790 i9xx_clock(refclk, &clock);
1b894b59
CW		 791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
d4906093 793 continue;
1b894b59
CW		 794
795 this_err = abs(clock.dot - target);
d4906093
ML		 796 if (this_err < err_most) {
797 *best_clock = clock;
798 err_most = this_err;
799 max_n = clock.n;
800 found = true;
801 }
802 }
803 }
804 }
805 }
2c07245f
ZW		 806 return found;
807}
808
d5dd62bd
ID		 809/*
810 * Check if the calculated PLL configuration is more optimal compared to the
811 * best configuration and error found so far. Return the calculated error.
812 */
813static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
814 const intel_clock_t *calculated_clock,
815 const intel_clock_t *best_clock,
816 unsigned int best_error_ppm,
817 unsigned int *error_ppm)
818{
9ca3ba01
ID		 819 /*
820 * For CHV ignore the error and consider only the P value.
821 * Prefer a bigger P value based on HW requirements.
822 */
823 if (IS_CHERRYVIEW(dev)) {
824 *error_ppm = 0;
825
826 return calculated_clock->p > best_clock->p;
827 }
828
24be4e46
ID		 829 if (WARN_ON_ONCE(!target_freq))
830 return false;
831
d5dd62bd
ID		 832 *error_ppm = div_u64(1000000ULL *
833 abs(target_freq - calculated_clock->dot),
834 target_freq);
835 /*
836 * Prefer a better P value over a better (smaller) error if the error
837 * is small. Ensure this preference for future configurations too by
838 * setting the error to 0.
839 */
840 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
841 *error_ppm = 0;
842
843 return true;
844 }
845
846 return *error_ppm + 10 < best_error_ppm;
847}
848
a0c4da24 849static bool
a93e255f
ACO		 850vlv_find_best_dpll(const intel_limit_t *limit,
851 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 852 int target, int refclk, intel_clock_t *match_clock,
853 intel_clock_t *best_clock)
a0c4da24 854{
a93e255f 855 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 856 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 857 intel_clock_t clock;
69e4f900 858 unsigned int bestppm = 1000000;
27e639bf
VS		 859 /* min update 19.2 MHz */
860 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 861 bool found = false;
a0c4da24 862
6b4bf1c4
VS		 863 target *= 5; /* fast clock */
864
865 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 866
867 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 868 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 869 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 870 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 871 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 872 clock.p = clock.p1 * clock.p2;
a0c4da24 873 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 874 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 875 unsigned int ppm;
69e4f900 876
6b4bf1c4
VS		 877 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
878 refclk * clock.m1);
879
880 vlv_clock(refclk, &clock);
43b0ac53 881
f01b7962
VS		 882 if (!intel_PLL_is_valid(dev, limit,
883 &clock))
43b0ac53
VS		 884 continue;
885
d5dd62bd
ID		 886 if (!vlv_PLL_is_optimal(dev, target,
887 &clock,
888 best_clock,
889 bestppm, &ppm))
890 continue;
6b4bf1c4 891
d5dd62bd
ID		 892 *best_clock = clock;
893 bestppm = ppm;
894 found = true;
a0c4da24
JB		 895 }
896 }
897 }
898 }
a0c4da24 899
49e497ef 900 return found;
a0c4da24 901}
a4fc5ed6 902
ef9348c8 903static bool
a93e255f
ACO		 904chv_find_best_dpll(const intel_limit_t *limit,
905 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 906 int target, int refclk, intel_clock_t *match_clock,
907 intel_clock_t *best_clock)
908{
a93e255f 909 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 910 struct drm_device *dev = crtc->base.dev;
9ca3ba01 911 unsigned int best_error_ppm;
ef9348c8
CML		 912 intel_clock_t clock;
913 uint64_t m2;
914 int found = false;
915
916 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 917 best_error_ppm = 1000000;
ef9348c8
CML		 918
919 /*
920 * Based on hardware doc, the n always set to 1, and m1 always
921 * set to 2. If requires to support 200Mhz refclk, we need to
922 * revisit this because n may not 1 anymore.
923 */
924 clock.n = 1, clock.m1 = 2;
925 target *= 5; /* fast clock */
926
927 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
928 for (clock.p2 = limit->p2.p2_fast;
929 clock.p2 >= limit->p2.p2_slow;
930 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 931 unsigned int error_ppm;
ef9348c8
CML		 932
933 clock.p = clock.p1 * clock.p2;
934
935 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
936 clock.n) << 22, refclk * clock.m1);
937
938 if (m2 > INT_MAX/clock.m1)
939 continue;
940
941 clock.m2 = m2;
942
943 chv_clock(refclk, &clock);
944
945 if (!intel_PLL_is_valid(dev, limit, &clock))
946 continue;
947
9ca3ba01
ID		 948 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
949 best_error_ppm, &error_ppm))
950 continue;
951
952 *best_clock = clock;
953 best_error_ppm = error_ppm;
954 found = true;
ef9348c8
CML		 955 }
956 }
957
958 return found;
959}
960
5ab7b0b7
ID		 961bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
962 intel_clock_t *best_clock)
963{
964 int refclk = i9xx_get_refclk(crtc_state, 0);
965
966 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
967 target_clock, refclk, NULL, best_clock);
968}
969
20ddf665
VS		 970bool intel_crtc_active(struct drm_crtc *crtc)
971{
972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
973
974 /* Be paranoid as we can arrive here with only partial
975 * state retrieved from the hardware during setup.
976 *
241bfc38 977 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 978 * as Haswell has gained clock readout/fastboot support.
979 *
66e514c1 980 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 981 * properly reconstruct framebuffers.
c3d1f436
MR		 982 *
983 * FIXME: The intel_crtc->active here should be switched to
984 * crtc->state->active once we have proper CRTC states wired up
985 * for atomic.
20ddf665 986 */
c3d1f436 987 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 988 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 989}
990
a5c961d1
PZ		 991enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
992 enum pipe pipe)
993{
994 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
996
6e3c9717 997 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 998}
999
fbf49ea2
VS		 1000static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1001{
1002 struct drm_i915_private *dev_priv = dev->dev_private;
1003 u32 reg = PIPEDSL(pipe);
1004 u32 line1, line2;
1005 u32 line_mask;
1006
1007 if (IS_GEN2(dev))
1008 line_mask = DSL_LINEMASK_GEN2;
1009 else
1010 line_mask = DSL_LINEMASK_GEN3;
1011
1012 line1 = I915_READ(reg) & line_mask;
1013 mdelay(5);
1014 line2 = I915_READ(reg) & line_mask;
1015
1016 return line1 == line2;
1017}
1018
ab7ad7f6
KP		 1019/*
1020 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1021 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1022 *
1023 * After disabling a pipe, we can't wait for vblank in the usual way,
1024 * spinning on the vblank interrupt status bit, since we won't actually
1025 * see an interrupt when the pipe is disabled.
1026 *
ab7ad7f6
KP		 1027 * On Gen4 and above:
1028 * wait for the pipe register state bit to turn off
1029 *
1030 * Otherwise:
1031 * wait for the display line value to settle (it usually
1032 * ends up stopping at the start of the next frame).
58e10eb9 1033 *
9d0498a2 1034 */
575f7ab7 1035static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1036{
575f7ab7 1037 struct drm_device *dev = crtc->base.dev;
9d0498a2 1038 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1039 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1040 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1041
1042 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1043 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1044
1045 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1046 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1047 100))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 } else {
ab7ad7f6 1050 /* Wait for the display line to settle */
fbf49ea2 1051 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1052 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1053 }
79e53945
JB		 1054}
1055
b0ea7d37
DL		 1056/*
1057 * ibx_digital_port_connected - is the specified port connected?
1058 * @dev_priv: i915 private structure
1059 * @port: the port to test
1060 *
1061 * Returns true if @port is connected, false otherwise.
1062 */
1063bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1064 struct intel_digital_port *port)
1065{
1066 u32 bit;
1067
c36346e3 1068 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1069 switch (port->port) {
c36346e3
DL		 1070 case PORT_B:
1071 bit = SDE_PORTB_HOTPLUG;
1072 break;
1073 case PORT_C:
1074 bit = SDE_PORTC_HOTPLUG;
1075 break;
1076 case PORT_D:
1077 bit = SDE_PORTD_HOTPLUG;
1078 break;
1079 default:
1080 return true;
1081 }
1082 } else {
eba905b2 1083 switch (port->port) {
c36346e3
DL		 1084 case PORT_B:
1085 bit = SDE_PORTB_HOTPLUG_CPT;
1086 break;
1087 case PORT_C:
1088 bit = SDE_PORTC_HOTPLUG_CPT;
1089 break;
1090 case PORT_D:
1091 bit = SDE_PORTD_HOTPLUG_CPT;
1092 break;
1093 default:
1094 return true;
1095 }
b0ea7d37
DL		 1096 }
1097
1098 return I915_READ(SDEISR) & bit;
1099}
1100
b24e7179
JB		 1101static const char *state_string(bool enabled)
1102{
1103 return enabled ? "on" : "off";
1104}
1105
1106/* Only for pre-ILK configs */
55607e8a
DV		 1107void assert_pll(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
b24e7179
JB		 1109{
1110 int reg;
1111 u32 val;
1112 bool cur_state;
1113
1114 reg = DPLL(pipe);
1115 val = I915_READ(reg);
1116 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1117 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1118 "PLL state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
b24e7179 1121
23538ef1
JN		 1122/* XXX: the dsi pll is shared between MIPI DSI ports */
1123static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1124{
1125 u32 val;
1126 bool cur_state;
1127
a580516d 1128 mutex_lock(&dev_priv->sb_lock);
23538ef1 1129 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1130 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1131
1132 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1133 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1134 "DSI PLL state assertion failure (expected %s, current %s)\n",
1135 state_string(state), state_string(cur_state));
1136}
1137#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1138#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1139
55607e8a 1140struct intel_shared_dpll *
e2b78267
DV		 1141intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1142{
1143 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1144
6e3c9717 1145 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1146 return NULL;
1147
6e3c9717 1148 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1149}
1150
040484af 1151/* For ILK+ */
55607e8a
DV		 1152void assert_shared_dpll(struct drm_i915_private *dev_priv,
1153 struct intel_shared_dpll *pll,
1154 bool state)
040484af 1155{
040484af 1156 bool cur_state;
5358901f 1157 struct intel_dpll_hw_state hw_state;
040484af 1158
92b27b08 1159 if (WARN (!pll,
46edb027 1160 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1161 return;
ee7b9f93 1162
5358901f 1163 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1164 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1165 "%s assertion failure (expected %s, current %s)\n",
1166 pll->name, state_string(state), state_string(cur_state));
040484af 1167}
040484af
JB		 1168
1169static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1170 enum pipe pipe, bool state)
1171{
1172 int reg;
1173 u32 val;
1174 bool cur_state;
ad80a810
PZ		 1175 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1176 pipe);
040484af 1177
affa9354
PZ		 1178 if (HAS_DDI(dev_priv->dev)) {
1179 /* DDI does not have a specific FDI_TX register */
ad80a810 1180 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1181 val = I915_READ(reg);
ad80a810 1182 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1183 } else {
1184 reg = FDI_TX_CTL(pipe);
1185 val = I915_READ(reg);
1186 cur_state = !!(val & FDI_TX_ENABLE);
1187 }
e2c719b7 1188 I915_STATE_WARN(cur_state != state,
040484af
JB		 1189 "FDI TX state assertion failure (expected %s, current %s)\n",
1190 state_string(state), state_string(cur_state));
1191}
1192#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1193#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1194
1195static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1196 enum pipe pipe, bool state)
1197{
1198 int reg;
1199 u32 val;
1200 bool cur_state;
1201
d63fa0dc
PZ		 1202 reg = FDI_RX_CTL(pipe);
1203 val = I915_READ(reg);
1204 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1205 I915_STATE_WARN(cur_state != state,
040484af
JB		 1206 "FDI RX state assertion failure (expected %s, current %s)\n",
1207 state_string(state), state_string(cur_state));
1208}
1209#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1210#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1211
1212static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1213 enum pipe pipe)
1214{
1215 int reg;
1216 u32 val;
1217
1218 /* ILK FDI PLL is always enabled */
3d13ef2e 1219 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1220 return;
1221
bf507ef7 1222 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1223 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1224 return;
1225
040484af
JB		 1226 reg = FDI_TX_CTL(pipe);
1227 val = I915_READ(reg);
e2c719b7 1228 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1229}
1230
55607e8a
DV		 1231void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, bool state)
040484af
JB		 1233{
1234 int reg;
1235 u32 val;
55607e8a 1236 bool cur_state;
040484af
JB		 1237
1238 reg = FDI_RX_CTL(pipe);
1239 val = I915_READ(reg);
55607e8a 1240 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1241 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1242 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1243 state_string(state), state_string(cur_state));
040484af
JB		 1244}
1245
b680c37a
DV		 1246void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
ea0760cf 1248{
bedd4dba
JN		 1249 struct drm_device *dev = dev_priv->dev;
1250 int pp_reg;
ea0760cf
JB		 1251 u32 val;
1252 enum pipe panel_pipe = PIPE_A;
0de3b485 1253 bool locked = true;
ea0760cf 1254
bedd4dba
JN		 1255 if (WARN_ON(HAS_DDI(dev)))
1256 return;
1257
1258 if (HAS_PCH_SPLIT(dev)) {
1259 u32 port_sel;
1260
ea0760cf 1261 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1262 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1263
1264 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1265 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1266 panel_pipe = PIPE_B;
1267 /* XXX: else fix for eDP */
1268 } else if (IS_VALLEYVIEW(dev)) {
1269 /* presumably write lock depends on pipe, not port select */
1270 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1271 panel_pipe = pipe;
ea0760cf
JB		 1272 } else {
1273 pp_reg = PP_CONTROL;
bedd4dba
JN		 1274 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1275 panel_pipe = PIPE_B;
ea0760cf
JB		 1276 }
1277
1278 val = I915_READ(pp_reg);
1279 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1280 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1281 locked = false;
1282
e2c719b7 1283 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1284 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1285 pipe_name(pipe));
ea0760cf
JB		 1286}
1287
93ce0ba6
JN		 1288static void assert_cursor(struct drm_i915_private *dev_priv,
1289 enum pipe pipe, bool state)
1290{
1291 struct drm_device *dev = dev_priv->dev;
1292 bool cur_state;
1293
d9d82081 1294 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1295 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1296 else
5efb3e28 1297 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1298
e2c719b7 1299 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1300 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1301 pipe_name(pipe), state_string(state), state_string(cur_state));
1302}
1303#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1304#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1305
b840d907
JB		 1306void assert_pipe(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, bool state)
b24e7179
JB		 1308{
1309 int reg;
1310 u32 val;
63d7bbe9 1311 bool cur_state;
702e7a56
PZ		 1312 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1313 pipe);
b24e7179 1314
b6b5d049
VS		 1315 /* if we need the pipe quirk it must be always on */
1316 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1317 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1318 state = true;
1319
f458ebbc 1320 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1321 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1322 cur_state = false;
1323 } else {
1324 reg = PIPECONF(cpu_transcoder);
1325 val = I915_READ(reg);
1326 cur_state = !!(val & PIPECONF_ENABLE);
1327 }
1328
e2c719b7 1329 I915_STATE_WARN(cur_state != state,
63d7bbe9 1330 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1331 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1332}
1333
931872fc
CW		 1334static void assert_plane(struct drm_i915_private *dev_priv,
1335 enum plane plane, bool state)
b24e7179
JB		 1336{
1337 int reg;
1338 u32 val;
931872fc 1339 bool cur_state;
b24e7179
JB		 1340
1341 reg = DSPCNTR(plane);
1342 val = I915_READ(reg);
931872fc 1343 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1345 "plane %c assertion failure (expected %s, current %s)\n",
1346 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1350#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1351
b24e7179
JB		 1352static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1353 enum pipe pipe)
1354{
653e1026 1355 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1356 int reg, i;
1357 u32 val;
1358 int cur_pipe;
1359
653e1026
VS		 1360 /* Primary planes are fixed to pipes on gen4+ */
1361 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1362 reg = DSPCNTR(pipe);
1363 val = I915_READ(reg);
e2c719b7 1364 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1365 "plane %c assertion failure, should be disabled but not\n",
1366 plane_name(pipe));
19ec1358 1367 return;
28c05794 1368 }
19ec1358 1369
b24e7179 1370 /* Need to check both planes against the pipe */
055e393f 1371 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1372 reg = DSPCNTR(i);
1373 val = I915_READ(reg);
1374 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1375 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1376 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1377 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1378 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1379 }
1380}
1381
19332d7a
JB		 1382static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1383 enum pipe pipe)
1384{
20674eef 1385 struct drm_device *dev = dev_priv->dev;
1fe47785 1386 int reg, sprite;
19332d7a
JB		 1387 u32 val;
1388
7feb8b88 1389 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1390 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1391 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1392 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1393 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1394 sprite, pipe_name(pipe));
1395 }
1396 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1397 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1398 reg = SPCNTR(pipe, sprite);
20674eef 1399 val = I915_READ(reg);
e2c719b7 1400 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1401 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1402 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1403 }
1404 } else if (INTEL_INFO(dev)->gen >= 7) {
1405 reg = SPRCTL(pipe);
19332d7a 1406 val = I915_READ(reg);
e2c719b7 1407 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1408 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1409 plane_name(pipe), pipe_name(pipe));
1410 } else if (INTEL_INFO(dev)->gen >= 5) {
1411 reg = DVSCNTR(pipe);
19332d7a 1412 val = I915_READ(reg);
e2c719b7 1413 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1414 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1415 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1416 }
1417}
1418
08c71e5e
VS		 1419static void assert_vblank_disabled(struct drm_crtc *crtc)
1420{
e2c719b7 1421 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1422 drm_crtc_vblank_put(crtc);
1423}
1424
89eff4be 1425static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1426{
1427 u32 val;
1428 bool enabled;
1429
e2c719b7 1430 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1431
92f2584a
JB		 1432 val = I915_READ(PCH_DREF_CONTROL);
1433 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1434 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1435 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1436}
1437
ab9412ba
DV		 1438static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1439 enum pipe pipe)
92f2584a
JB		 1440{
1441 int reg;
1442 u32 val;
1443 bool enabled;
1444
ab9412ba 1445 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1446 val = I915_READ(reg);
1447 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1448 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1449 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1450 pipe_name(pipe));
92f2584a
JB		 1451}
1452
4e634389
KP		 1453static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1455{
1456 if ((val & DP_PORT_EN) == 0)
1457 return false;
1458
1459 if (HAS_PCH_CPT(dev_priv->dev)) {
1460 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1461 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1462 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1463 return false;
44f37d1f
CML		 1464 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1465 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1466 return false;
f0575e92
KP		 1467 } else {
1468 if ((val & DP_PIPE_MASK) != (pipe << 30))
1469 return false;
1470 }
1471 return true;
1472}
1473
1519b995
KP		 1474static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1475 enum pipe pipe, u32 val)
1476{
dc0fa718 1477 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1478 return false;
1479
1480 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1481 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1482 return false;
44f37d1f
CML		 1483 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1484 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1485 return false;
1519b995 1486 } else {
dc0fa718 1487 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1488 return false;
1489 }
1490 return true;
1491}
1492
1493static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1494 enum pipe pipe, u32 val)
1495{
1496 if ((val & LVDS_PORT_EN) == 0)
1497 return false;
1498
1499 if (HAS_PCH_CPT(dev_priv->dev)) {
1500 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1501 return false;
1502 } else {
1503 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1504 return false;
1505 }
1506 return true;
1507}
1508
1509static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe, u32 val)
1511{
1512 if ((val & ADPA_DAC_ENABLE) == 0)
1513 return false;
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
291906f1 1524static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1525 enum pipe pipe, int reg, u32 port_sel)
291906f1 1526{
47a05eca 1527 u32 val = I915_READ(reg);
e2c719b7 1528 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1529 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1530 reg, pipe_name(pipe));
de9a35ab 1531
e2c719b7 1532 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1533 && (val & DP_PIPEB_SELECT),
de9a35ab 1534 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1535}
1536
1537static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1538 enum pipe pipe, int reg)
1539{
47a05eca 1540 u32 val = I915_READ(reg);
e2c719b7 1541 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1542 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1543 reg, pipe_name(pipe));
de9a35ab 1544
e2c719b7 1545 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1546 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1547 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1548}
1549
1550static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1551 enum pipe pipe)
1552{
1553 int reg;
1554 u32 val;
291906f1 1555
f0575e92
KP		 1556 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1557 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1558 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1559
1560 reg = PCH_ADPA;
1561 val = I915_READ(reg);
e2c719b7 1562 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1563 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1564 pipe_name(pipe));
291906f1
JB		 1565
1566 reg = PCH_LVDS;
1567 val = I915_READ(reg);
e2c719b7 1568 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1569 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1570 pipe_name(pipe));
291906f1 1571
e2debe91
PZ		 1572 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1573 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1574 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1575}
1576
40e9cf64
JB		 1577static void intel_init_dpio(struct drm_device *dev)
1578{
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580
1581 if (!IS_VALLEYVIEW(dev))
1582 return;
1583
a09caddd
CML		 1584 /*
1585 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1586 * CHV x1 PHY (DP/HDMI D)
1587 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1588 */
1589 if (IS_CHERRYVIEW(dev)) {
1590 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1591 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1592 } else {
1593 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1594 }
5382f5f3
JB		 1595}
1596
d288f65f 1597static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1598 const struct intel_crtc_state *pipe_config)
87442f73 1599{
426115cf
DV		 1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 int reg = DPLL(crtc->pipe);
d288f65f 1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1604
426115cf 1605 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1611 if (IS_MOBILE(dev_priv->dev))
426115cf 1612 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1613
426115cf
DV		 1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
d288f65f 1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1622 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1623
1624 /* We do this three times for luck */
426115cf 1625 I915_WRITE(reg, dpll);
87442f73
DV		 1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
426115cf 1628 I915_WRITE(reg, dpll);
87442f73
DV		 1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
426115cf 1631 I915_WRITE(reg, dpll);
87442f73
DV		 1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634}
1635
d288f65f 1636static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1637 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1638{
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
a580516d 1649 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
54433e91
VS		 1656 mutex_unlock(&dev_priv->sb_lock);
1657
9d556c99
CML		 1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
d288f65f 1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1665
1666 /* Check PLL is locked */
a11b0703 1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
a11b0703 1670 /* not sure when this should be written */
d288f65f 1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1672 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1673}
1674
1c4e0274
VS		 1675static int intel_num_dvo_pipes(struct drm_device *dev)
1676{
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
3538b9df 1681 count += crtc->base.state->active &&
409ee761 1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1683
1684 return count;
1685}
1686
66e3d5c0 1687static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1688{
66e3d5c0
DV		 1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 int reg = DPLL(crtc->pipe);
6e3c9717 1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1693
66e3d5c0 1694 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1695
63d7bbe9 1696 /* No really, not for ILK+ */
3d13ef2e 1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1698
1699 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1702
1c4e0274
VS		 1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
66e3d5c0
DV		 1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1722 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
63d7bbe9
JB		 1731
1732 /* We do this three times for luck */
66e3d5c0 1733 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
66e3d5c0 1736 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
66e3d5c0 1739 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742}
1743
1744/**
50b44a44 1745 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1c4e0274 1753static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1754{
1c4e0274
VS		 1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
409ee761 1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1762 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
b6b5d049
VS		 1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
50b44a44
DV		 1777 I915_WRITE(DPLL(pipe), 0);
1778 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1779}
1780
f6071166
JB		 1781static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782{
1783 u32 val = 0;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
e5cbfbfb
ID		 1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
f6071166 1792 if (pipe == PIPE_B)
e5cbfbfb 1793 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1794 I915_WRITE(DPLL(pipe), val);
1795 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1796
1797}
1798
1799static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1800{
d752048d 1801 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1802 u32 val;
1803
a11b0703
VS		 1804 /* Make sure the pipe isn't still relying on us */
1805 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1806
a11b0703 1807 /* Set PLL en = 0 */
d17ec4ce 1808 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1809 if (pipe != PIPE_A)
1810 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1811 I915_WRITE(DPLL(pipe), val);
1812 POSTING_READ(DPLL(pipe));
d752048d 1813
a580516d 1814 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1815
1816 /* Disable 10bit clock to display controller */
1817 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1818 val &= ~DPIO_DCLKP_EN;
1819 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1820
61407f6d
VS		 1821 /* disable left/right clock distribution */
1822 if (pipe != PIPE_B) {
1823 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1824 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1825 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1826 } else {
1827 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1828 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1829 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1830 }
1831
a580516d 1832 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1833}
1834
e4607fcf 1835void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1836 struct intel_digital_port *dport,
1837 unsigned int expected_mask)
89b667f8
JB		 1838{
1839 u32 port_mask;
00fc31b7 1840 int dpll_reg;
89b667f8 1841
e4607fcf
CML		 1842 switch (dport->port) {
1843 case PORT_B:
89b667f8 1844 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1845 dpll_reg = DPLL(0);
e4607fcf
CML		 1846 break;
1847 case PORT_C:
89b667f8 1848 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1849 dpll_reg = DPLL(0);
9b6de0a1 1850 expected_mask <<= 4;
00fc31b7
CML		 1851 break;
1852 case PORT_D:
1853 port_mask = DPLL_PORTD_READY_MASK;
1854 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1855 break;
1856 default:
1857 BUG();
1858 }
89b667f8 1859
9b6de0a1
VS		 1860 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1863}
1864
b14b1055
DV		 1865static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866{
1867 struct drm_device *dev = crtc->base.dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
be19f0ff
CW		 1871 if (WARN_ON(pll == NULL))
1872 return;
1873
3e369b76 1874 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1875 if (pll->active == 0) {
1876 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877 WARN_ON(pll->on);
1878 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880 pll->mode_set(dev_priv, pll);
1881 }
1882}
1883
92f2584a 1884/**
85b3894f 1885 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1886 * @dev_priv: i915 private structure
1887 * @pipe: pipe PLL to enable
1888 *
1889 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890 * drives the transcoder clock.
1891 */
85b3894f 1892static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1893{
3d13ef2e
DL		 1894 struct drm_device *dev = crtc->base.dev;
1895 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1896 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1897
87a875bb 1898 if (WARN_ON(pll == NULL))
48da64a8
CW		 1899 return;
1900
3e369b76 1901 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1902 return;
ee7b9f93 1903
74dd6928 1904 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1905 pll->name, pll->active, pll->on,
e2b78267 1906 crtc->base.base.id);
92f2584a 1907
cdbd2316
DV		 1908 if (pll->active++) {
1909 WARN_ON(!pll->on);
e9d6944e 1910 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1911 return;
1912 }
f4a091c7 1913 WARN_ON(pll->on);
ee7b9f93 1914
bd2bb1b9
PZ		 1915 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
46edb027 1917 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1918 pll->enable(dev_priv, pll);
ee7b9f93 1919 pll->on = true;
92f2584a
JB		 1920}
1921
f6daaec2 1922static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1923{
3d13ef2e
DL		 1924 struct drm_device *dev = crtc->base.dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1926 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1927
92f2584a 1928 /* PCH only available on ILK+ */
3d13ef2e 1929 BUG_ON(INTEL_INFO(dev)->gen < 5);
eddfcbcd
ML		 1930 if (pll == NULL)
1931 return;
92f2584a 1932
eddfcbcd 1933 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1934 return;
7a419866 1935
46edb027
DV		 1936 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1937 pll->name, pll->active, pll->on,
e2b78267 1938 crtc->base.base.id);
7a419866 1939
48da64a8 1940 if (WARN_ON(pll->active == 0)) {
e9d6944e 1941 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1942 return;
1943 }
1944
e9d6944e 1945 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1946 WARN_ON(!pll->on);
cdbd2316 1947 if (--pll->active)
7a419866 1948 return;
ee7b9f93 1949
46edb027 1950 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1951 pll->disable(dev_priv, pll);
ee7b9f93 1952 pll->on = false;
bd2bb1b9
PZ		 1953
1954 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1955}
1956
b8a4f404
PZ		 1957static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1958 enum pipe pipe)
040484af 1959{
23670b32 1960 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1961 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1962 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1963 uint32_t reg, val, pipeconf_val;
040484af
JB		 1964
1965 /* PCH only available on ILK+ */
55522f37 1966 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1967
1968 /* Make sure PCH DPLL is enabled */
e72f9fbf 1969 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1970 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1971
1972 /* FDI must be feeding us bits for PCH ports */
1973 assert_fdi_tx_enabled(dev_priv, pipe);
1974 assert_fdi_rx_enabled(dev_priv, pipe);
1975
23670b32
DV		 1976 if (HAS_PCH_CPT(dev)) {
1977 /* Workaround: Set the timing override bit before enabling the
1978 * pch transcoder. */
1979 reg = TRANS_CHICKEN2(pipe);
1980 val = I915_READ(reg);
1981 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1982 I915_WRITE(reg, val);
59c859d6 1983 }
23670b32 1984
ab9412ba 1985 reg = PCH_TRANSCONF(pipe);
040484af 1986 val = I915_READ(reg);
5f7f726d 1987 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1988
1989 if (HAS_PCH_IBX(dev_priv->dev)) {
1990 /*
c5de7c6f
VS		 1991 * Make the BPC in transcoder be consistent with
1992 * that in pipeconf reg. For HDMI we must use 8bpc
1993 * here for both 8bpc and 12bpc.
e9bcff5c 1994 */
dfd07d72 1995 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 1996 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1997 val |= PIPECONF_8BPC;
1998 else
1999 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2000 }
5f7f726d
PZ		 2001
2002 val &= ~TRANS_INTERLACE_MASK;
2003 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2004 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2005 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2006 val |= TRANS_LEGACY_INTERLACED_ILK;
2007 else
2008 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2009 else
2010 val |= TRANS_PROGRESSIVE;
2011
040484af
JB		 2012 I915_WRITE(reg, val | TRANS_ENABLE);
2013 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2014 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2015}
2016
8fb033d7 2017static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2018 enum transcoder cpu_transcoder)
040484af 2019{
8fb033d7 2020 u32 val, pipeconf_val;
8fb033d7
PZ		 2021
2022 /* PCH only available on ILK+ */
55522f37 2023 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2024
8fb033d7 2025 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2026 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2027 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2028
223a6fdf
PZ		 2029 /* Workaround: set timing override bit. */
2030 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2031 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2032 I915_WRITE(_TRANSA_CHICKEN2, val);
2033
25f3ef11 2034 val = TRANS_ENABLE;
937bb610 2035 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2036
9a76b1c6
PZ		 2037 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2038 PIPECONF_INTERLACED_ILK)
a35f2679 2039 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2040 else
2041 val |= TRANS_PROGRESSIVE;
2042
ab9412ba
DV		 2043 I915_WRITE(LPT_TRANSCONF, val);
2044 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2045 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2046}
2047
b8a4f404
PZ		 2048static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2049 enum pipe pipe)
040484af 2050{
23670b32
DV		 2051 struct drm_device *dev = dev_priv->dev;
2052 uint32_t reg, val;
040484af
JB		 2053
2054 /* FDI relies on the transcoder */
2055 assert_fdi_tx_disabled(dev_priv, pipe);
2056 assert_fdi_rx_disabled(dev_priv, pipe);
2057
291906f1
JB		 2058 /* Ports must be off as well */
2059 assert_pch_ports_disabled(dev_priv, pipe);
2060
ab9412ba 2061 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2062 val = I915_READ(reg);
2063 val &= ~TRANS_ENABLE;
2064 I915_WRITE(reg, val);
2065 /* wait for PCH transcoder off, transcoder state */
2066 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2067 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2068
2069 if (!HAS_PCH_IBX(dev)) {
2070 /* Workaround: Clear the timing override chicken bit again. */
2071 reg = TRANS_CHICKEN2(pipe);
2072 val = I915_READ(reg);
2073 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2074 I915_WRITE(reg, val);
2075 }
040484af
JB		 2076}
2077
ab4d966c 2078static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2079{
8fb033d7
PZ		 2080 u32 val;
2081
ab9412ba 2082 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2083 val &= ~TRANS_ENABLE;
ab9412ba 2084 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2085 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2086 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2087 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2088
2089 /* Workaround: clear timing override bit. */
2090 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2091 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2092 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2093}
2094
b24e7179 2095/**
309cfea8 2096 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2097 * @crtc: crtc responsible for the pipe
b24e7179 2098 *
0372264a 2099 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2100 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2101 */
e1fdc473 2102static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2103{
0372264a
PZ		 2104 struct drm_device *dev = crtc->base.dev;
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2107 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2108 pipe);
1a240d4d 2109 enum pipe pch_transcoder;
b24e7179
JB		 2110 int reg;
2111 u32 val;
2112
9e2ee2dd
VS		 2113 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2114
58c6eaa2 2115 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2116 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2117 assert_sprites_disabled(dev_priv, pipe);
2118
681e5811 2119 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2120 pch_transcoder = TRANSCODER_A;
2121 else
2122 pch_transcoder = pipe;
2123
b24e7179
JB		 2124 /*
2125 * A pipe without a PLL won't actually be able to drive bits from
2126 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2127 * need the check.
2128 */
50360403 2129 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2130 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2131 assert_dsi_pll_enabled(dev_priv);
2132 else
2133 assert_pll_enabled(dev_priv, pipe);
040484af 2134 else {
6e3c9717 2135 if (crtc->config->has_pch_encoder) {
040484af 2136 /* if driving the PCH, we need FDI enabled */
cc391bbb 2137 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2138 assert_fdi_tx_pll_enabled(dev_priv,
2139 (enum pipe) cpu_transcoder);
040484af
JB		 2140 }
2141 /* FIXME: assert CPU port conditions for SNB+ */
2142 }
b24e7179 2143
702e7a56 2144 reg = PIPECONF(cpu_transcoder);
b24e7179 2145 val = I915_READ(reg);
7ad25d48 2146 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2147 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2148 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2149 return;
7ad25d48 2150 }
00d70b15
CW		 2151
2152 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2153 POSTING_READ(reg);
b24e7179
JB		 2154}
2155
2156/**
309cfea8 2157 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2158 * @crtc: crtc whose pipes is to be disabled
b24e7179 2159 *
575f7ab7
VS		 2160 * Disable the pipe of @crtc, making sure that various hardware
2161 * specific requirements are met, if applicable, e.g. plane
2162 * disabled, panel fitter off, etc.
b24e7179
JB		 2163 *
2164 * Will wait until the pipe has shut down before returning.
2165 */
575f7ab7 2166static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2167{
575f7ab7 2168 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2169 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2170 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2171 int reg;
2172 u32 val;
2173
9e2ee2dd
VS		 2174 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2175
b24e7179
JB		 2176 /*
2177 * Make sure planes won't keep trying to pump pixels to us,
2178 * or we might hang the display.
2179 */
2180 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2181 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2182 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2183
702e7a56 2184 reg = PIPECONF(cpu_transcoder);
b24e7179 2185 val = I915_READ(reg);
00d70b15
CW		 2186 if ((val & PIPECONF_ENABLE) == 0)
2187 return;
2188
67adc644
VS		 2189 /*
2190 * Double wide has implications for planes
2191 * so best keep it disabled when not needed.
2192 */
6e3c9717 2193 if (crtc->config->double_wide)
67adc644
VS		 2194 val &= ~PIPECONF_DOUBLE_WIDE;
2195
2196 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2197 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2198 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2199 val &= ~PIPECONF_ENABLE;
2200
2201 I915_WRITE(reg, val);
2202 if ((val & PIPECONF_ENABLE) == 0)
2203 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2204}
2205
693db184
CW		 2206static bool need_vtd_wa(struct drm_device *dev)
2207{
2208#ifdef CONFIG_INTEL_IOMMU
2209 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2210 return true;
2211#endif
2212 return false;
2213}
2214
50470bb0 2215unsigned int
6761dd31
TU		 2216intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2217 uint64_t fb_format_modifier)
a57ce0b2 2218{
6761dd31
TU		 2219 unsigned int tile_height;
2220 uint32_t pixel_bytes;
a57ce0b2 2221
b5d0e9bf
DL		 2222 switch (fb_format_modifier) {
2223 case DRM_FORMAT_MOD_NONE:
2224 tile_height = 1;
2225 break;
2226 case I915_FORMAT_MOD_X_TILED:
2227 tile_height = IS_GEN2(dev) ? 16 : 8;
2228 break;
2229 case I915_FORMAT_MOD_Y_TILED:
2230 tile_height = 32;
2231 break;
2232 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2233 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2234 switch (pixel_bytes) {
b5d0e9bf 2235 default:
6761dd31 2236 case 1:
b5d0e9bf
DL		 2237 tile_height = 64;
2238 break;
6761dd31
TU		 2239 case 2:
2240 case 4:
b5d0e9bf
DL		 2241 tile_height = 32;
2242 break;
6761dd31 2243 case 8:
b5d0e9bf
DL		 2244 tile_height = 16;
2245 break;
6761dd31 2246 case 16:
b5d0e9bf
DL		 2247 WARN_ONCE(1,
2248 "128-bit pixels are not supported for display!");
2249 tile_height = 16;
2250 break;
2251 }
2252 break;
2253 default:
2254 MISSING_CASE(fb_format_modifier);
2255 tile_height = 1;
2256 break;
2257 }
091df6cb 2258
6761dd31
TU		 2259 return tile_height;
2260}
2261
2262unsigned int
2263intel_fb_align_height(struct drm_device *dev, unsigned int height,
2264 uint32_t pixel_format, uint64_t fb_format_modifier)
2265{
2266 return ALIGN(height, intel_tile_height(dev, pixel_format,
2267 fb_format_modifier));
a57ce0b2
JB		 2268}
2269
f64b98cd
TU		 2270static int
2271intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2272 const struct drm_plane_state *plane_state)
2273{
50470bb0 2274 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2275 unsigned int tile_height, tile_pitch;
50470bb0 2276
f64b98cd
TU		 2277 *view = i915_ggtt_view_normal;
2278
50470bb0
TU		 2279 if (!plane_state)
2280 return 0;
2281
121920fa 2282 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2283 return 0;
2284
9abc4648 2285 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2286
2287 info->height = fb->height;
2288 info->pixel_format = fb->pixel_format;
2289 info->pitch = fb->pitches[0];
2290 info->fb_modifier = fb->modifier[0];
2291
84fe03f7
TU		 2292 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2293 fb->modifier[0]);
2294 tile_pitch = PAGE_SIZE / tile_height;
2295 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2296 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2297 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2298
f64b98cd
TU		 2299 return 0;
2300}
2301
4e9a86b6
VS		 2302static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2303{
2304 if (INTEL_INFO(dev_priv)->gen >= 9)
2305 return 256 * 1024;
985b8bb4
VS		 2306 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2307 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2308 return 128 * 1024;
2309 else if (INTEL_INFO(dev_priv)->gen >= 4)
2310 return 4 * 1024;
2311 else
44c5905e 2312 return 0;
4e9a86b6
VS		 2313}
2314
127bd2ac 2315int
850c4cdc
TU		 2316intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2317 struct drm_framebuffer *fb,
82bc3b2d 2318 const struct drm_plane_state *plane_state,
91af127f
JH		 2319 struct intel_engine_cs *pipelined,
2320 struct drm_i915_gem_request **pipelined_request)
6b95a207 2321{
850c4cdc 2322 struct drm_device *dev = fb->dev;
ce453d81 2323 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2324 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2325 struct i915_ggtt_view view;
6b95a207
KH		 2326 u32 alignment;
2327 int ret;
2328
ebcdd39e
MR		 2329 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2330
7b911adc
TU		 2331 switch (fb->modifier[0]) {
2332 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2333 alignment = intel_linear_alignment(dev_priv);
6b95a207 2334 break;
7b911adc 2335 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2336 if (INTEL_INFO(dev)->gen >= 9)
2337 alignment = 256 * 1024;
2338 else {
2339 /* pin() will align the object as required by fence */
2340 alignment = 0;
2341 }
6b95a207 2342 break;
7b911adc 2343 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2344 case I915_FORMAT_MOD_Yf_TILED:
2345 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2346 "Y tiling bo slipped through, driver bug!\n"))
2347 return -EINVAL;
2348 alignment = 1 * 1024 * 1024;
2349 break;
6b95a207 2350 default:
7b911adc
TU		 2351 MISSING_CASE(fb->modifier[0]);
2352 return -EINVAL;
6b95a207
KH		 2353 }
2354
f64b98cd
TU		 2355 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2356 if (ret)
2357 return ret;
2358
693db184
CW		 2359 /* Note that the w/a also requires 64 PTE of padding following the
2360 * bo. We currently fill all unused PTE with the shadow page and so
2361 * we should always have valid PTE following the scanout preventing
2362 * the VT-d warning.
2363 */
2364 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2365 alignment = 256 * 1024;
2366
d6dd6843
PZ		 2367 /*
2368 * Global gtt pte registers are special registers which actually forward
2369 * writes to a chunk of system memory. Which means that there is no risk
2370 * that the register values disappear as soon as we call
2371 * intel_runtime_pm_put(), so it is correct to wrap only the
2372 * pin/unpin/fence and not more.
2373 */
2374 intel_runtime_pm_get(dev_priv);
2375
ce453d81 2376 dev_priv->mm.interruptible = false;
e6617330 2377 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2378 pipelined_request, &view);
48b956c5 2379 if (ret)
ce453d81 2380 goto err_interruptible;
6b95a207
KH		 2381
2382 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2383 * fence, whereas 965+ only requires a fence if using
2384 * framebuffer compression. For simplicity, we always install
2385 * a fence as the cost is not that onerous.
2386 */
06d98131 2387 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2388 if (ret)
2389 goto err_unpin;
1690e1eb 2390
9a5a53b3 2391 i915_gem_object_pin_fence(obj);
6b95a207 2392
ce453d81 2393 dev_priv->mm.interruptible = true;
d6dd6843 2394 intel_runtime_pm_put(dev_priv);
6b95a207 2395 return 0;
48b956c5
CW		 2396
2397err_unpin:
f64b98cd 2398 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2399err_interruptible:
2400 dev_priv->mm.interruptible = true;
d6dd6843 2401 intel_runtime_pm_put(dev_priv);
48b956c5 2402 return ret;
6b95a207
KH		 2403}
2404
82bc3b2d
TU		 2405static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2406 const struct drm_plane_state *plane_state)
1690e1eb 2407{
82bc3b2d 2408 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2409 struct i915_ggtt_view view;
2410 int ret;
82bc3b2d 2411
ebcdd39e
MR		 2412 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2413
f64b98cd
TU		 2414 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2415 WARN_ONCE(ret, "Couldn't get view from plane state!");
2416
1690e1eb 2417 i915_gem_object_unpin_fence(obj);
f64b98cd 2418 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2419}
2420
c2c75131
DV		 2421/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2422 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2423unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2424 int *x, int *y,
bc752862
CW		 2425 unsigned int tiling_mode,
2426 unsigned int cpp,
2427 unsigned int pitch)
c2c75131 2428{
bc752862
CW		 2429 if (tiling_mode != I915_TILING_NONE) {
2430 unsigned int tile_rows, tiles;
c2c75131 2431
bc752862
CW		 2432 tile_rows = *y / 8;
2433 *y %= 8;
c2c75131 2434
bc752862
CW		 2435 tiles = *x / (512/cpp);
2436 *x %= 512/cpp;
2437
2438 return tile_rows * pitch * 8 + tiles * 4096;
2439 } else {
4e9a86b6 2440 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2441 unsigned int offset;
2442
2443 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2444 *y = (offset & alignment) / pitch;
2445 *x = ((offset & alignment) - *y * pitch) / cpp;
2446 return offset & ~alignment;
bc752862 2447 }
c2c75131
DV		 2448}
2449
b35d63fa 2450static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2451{
2452 switch (format) {
2453 case DISPPLANE_8BPP:
2454 return DRM_FORMAT_C8;
2455 case DISPPLANE_BGRX555:
2456 return DRM_FORMAT_XRGB1555;
2457 case DISPPLANE_BGRX565:
2458 return DRM_FORMAT_RGB565;
2459 default:
2460 case DISPPLANE_BGRX888:
2461 return DRM_FORMAT_XRGB8888;
2462 case DISPPLANE_RGBX888:
2463 return DRM_FORMAT_XBGR8888;
2464 case DISPPLANE_BGRX101010:
2465 return DRM_FORMAT_XRGB2101010;
2466 case DISPPLANE_RGBX101010:
2467 return DRM_FORMAT_XBGR2101010;
2468 }
2469}
2470
bc8d7dff
DL		 2471static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2472{
2473 switch (format) {
2474 case PLANE_CTL_FORMAT_RGB_565:
2475 return DRM_FORMAT_RGB565;
2476 default:
2477 case PLANE_CTL_FORMAT_XRGB_8888:
2478 if (rgb_order) {
2479 if (alpha)
2480 return DRM_FORMAT_ABGR8888;
2481 else
2482 return DRM_FORMAT_XBGR8888;
2483 } else {
2484 if (alpha)
2485 return DRM_FORMAT_ARGB8888;
2486 else
2487 return DRM_FORMAT_XRGB8888;
2488 }
2489 case PLANE_CTL_FORMAT_XRGB_2101010:
2490 if (rgb_order)
2491 return DRM_FORMAT_XBGR2101010;
2492 else
2493 return DRM_FORMAT_XRGB2101010;
2494 }
2495}
2496
5724dbd1 2497static bool
f6936e29
DV		 2498intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2499 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2500{
2501 struct drm_device *dev = crtc->base.dev;
2502 struct drm_i915_gem_object *obj = NULL;
2503 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2504 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2505 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2506 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2507 PAGE_SIZE);
2508
2509 size_aligned -= base_aligned;
46f297fb 2510
ff2652ea
CW		 2511 if (plane_config->size == 0)
2512 return false;
2513
f37b5c2b
DV		 2514 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2515 base_aligned,
2516 base_aligned,
2517 size_aligned);
46f297fb 2518 if (!obj)
484b41dd 2519 return false;
46f297fb 2520
49af449b
DL		 2521 obj->tiling_mode = plane_config->tiling;
2522 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2523 obj->stride = fb->pitches[0];
46f297fb 2524
6bf129df
DL		 2525 mode_cmd.pixel_format = fb->pixel_format;
2526 mode_cmd.width = fb->width;
2527 mode_cmd.height = fb->height;
2528 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2529 mode_cmd.modifier[0] = fb->modifier[0];
2530 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2531
2532 mutex_lock(&dev->struct_mutex);
6bf129df 2533 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2534 &mode_cmd, obj)) {
46f297fb
JB		 2535 DRM_DEBUG_KMS("intel fb init failed\n");
2536 goto out_unref_obj;
2537 }
46f297fb 2538 mutex_unlock(&dev->struct_mutex);
484b41dd 2539
f6936e29 2540 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2541 return true;
46f297fb
JB		 2542
2543out_unref_obj:
2544 drm_gem_object_unreference(&obj->base);
2545 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2546 return false;
2547}
2548
afd65eb4
MR		 2549/* Update plane->state->fb to match plane->fb after driver-internal updates */
2550static void
2551update_state_fb(struct drm_plane *plane)
2552{
2553 if (plane->fb == plane->state->fb)
2554 return;
2555
2556 if (plane->state->fb)
2557 drm_framebuffer_unreference(plane->state->fb);
2558 plane->state->fb = plane->fb;
2559 if (plane->state->fb)
2560 drm_framebuffer_reference(plane->state->fb);
2561}
2562
5724dbd1 2563static void
f6936e29
DV		 2564intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2565 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2566{
2567 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2568 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2569 struct drm_crtc *c;
2570 struct intel_crtc *i;
2ff8fde1 2571 struct drm_i915_gem_object *obj;
88595ac9
DV		 2572 struct drm_plane *primary = intel_crtc->base.primary;
2573 struct drm_framebuffer *fb;
484b41dd 2574
2d14030b 2575 if (!plane_config->fb)
484b41dd
JB		 2576 return;
2577
f6936e29 2578 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2579 fb = &plane_config->fb->base;
2580 goto valid_fb;
f55548b5 2581 }
484b41dd 2582
2d14030b 2583 kfree(plane_config->fb);
484b41dd
JB		 2584
2585 /*
2586 * Failed to alloc the obj, check to see if we should share
2587 * an fb with another CRTC instead
2588 */
70e1e0ec 2589 for_each_crtc(dev, c) {
484b41dd
JB		 2590 i = to_intel_crtc(c);
2591
2592 if (c == &intel_crtc->base)
2593 continue;
2594
2ff8fde1
MR		 2595 if (!i->active)
2596 continue;
2597
88595ac9
DV		 2598 fb = c->primary->fb;
2599 if (!fb)
484b41dd
JB		 2600 continue;
2601
88595ac9 2602 obj = intel_fb_obj(fb);
2ff8fde1 2603 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2604 drm_framebuffer_reference(fb);
2605 goto valid_fb;
484b41dd
JB		 2606 }
2607 }
88595ac9
DV		 2608
2609 return;
2610
2611valid_fb:
2612 obj = intel_fb_obj(fb);
2613 if (obj->tiling_mode != I915_TILING_NONE)
2614 dev_priv->preserve_bios_swizzle = true;
2615
2616 primary->fb = fb;
36750f28 2617 primary->crtc = primary->state->crtc = &intel_crtc->base;
88595ac9 2618 update_state_fb(primary);
36750f28 2619 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2620 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2621}
2622
29b9bde6
DV		 2623static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2624 struct drm_framebuffer *fb,
2625 int x, int y)
81255565
JB		 2626{
2627 struct drm_device *dev = crtc->dev;
2628 struct drm_i915_private *dev_priv = dev->dev_private;
2629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2630 struct drm_plane *primary = crtc->primary;
2631 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2632 struct drm_i915_gem_object *obj;
81255565 2633 int plane = intel_crtc->plane;
e506a0c6 2634 unsigned long linear_offset;
81255565 2635 u32 dspcntr;
f45651ba 2636 u32 reg = DSPCNTR(plane);
48404c1e 2637 int pixel_size;
f45651ba 2638
b70709a6 2639 if (!visible || !fb) {
fdd508a6
VS		 2640 I915_WRITE(reg, 0);
2641 if (INTEL_INFO(dev)->gen >= 4)
2642 I915_WRITE(DSPSURF(plane), 0);
2643 else
2644 I915_WRITE(DSPADDR(plane), 0);
2645 POSTING_READ(reg);
2646 return;
2647 }
2648
c9ba6fad
VS		 2649 obj = intel_fb_obj(fb);
2650 if (WARN_ON(obj == NULL))
2651 return;
2652
2653 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2654
f45651ba
VS		 2655 dspcntr = DISPPLANE_GAMMA_ENABLE;
2656
fdd508a6 2657 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2658
2659 if (INTEL_INFO(dev)->gen < 4) {
2660 if (intel_crtc->pipe == PIPE_B)
2661 dspcntr |= DISPPLANE_SEL_PIPE_B;
2662
2663 /* pipesrc and dspsize control the size that is scaled from,
2664 * which should always be the user's requested size.
2665 */
2666 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2667 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2668 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2669 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2670 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2671 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2672 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2673 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2674 I915_WRITE(PRIMPOS(plane), 0);
2675 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2676 }
81255565 2677
57779d06
VS		 2678 switch (fb->pixel_format) {
2679 case DRM_FORMAT_C8:
81255565
JB		 2680 dspcntr |= DISPPLANE_8BPP;
2681 break;
57779d06 2682 case DRM_FORMAT_XRGB1555:
57779d06 2683 dspcntr |= DISPPLANE_BGRX555;
81255565 2684 break;
57779d06
VS		 2685 case DRM_FORMAT_RGB565:
2686 dspcntr |= DISPPLANE_BGRX565;
2687 break;
2688 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2689 dspcntr |= DISPPLANE_BGRX888;
2690 break;
2691 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2692 dspcntr |= DISPPLANE_RGBX888;
2693 break;
2694 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2695 dspcntr |= DISPPLANE_BGRX101010;
2696 break;
2697 case DRM_FORMAT_XBGR2101010:
57779d06 2698 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2699 break;
2700 default:
baba133a 2701 BUG();
81255565 2702 }
57779d06 2703
f45651ba
VS		 2704 if (INTEL_INFO(dev)->gen >= 4 &&
2705 obj->tiling_mode != I915_TILING_NONE)
2706 dspcntr |= DISPPLANE_TILED;
81255565 2707
de1aa629
VS		 2708 if (IS_G4X(dev))
2709 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2710
b9897127 2711 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2712
c2c75131
DV		 2713 if (INTEL_INFO(dev)->gen >= 4) {
2714 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2715 intel_gen4_compute_page_offset(dev_priv,
2716 &x, &y, obj->tiling_mode,
b9897127 2717 pixel_size,
bc752862 2718 fb->pitches[0]);
c2c75131
DV		 2719 linear_offset -= intel_crtc->dspaddr_offset;
2720 } else {
e506a0c6 2721 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2722 }
e506a0c6 2723
8e7d688b 2724 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2725 dspcntr |= DISPPLANE_ROTATE_180;
2726
6e3c9717
ACO		 2727 x += (intel_crtc->config->pipe_src_w - 1);
2728 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2729
2730 /* Finding the last pixel of the last line of the display
2731 data and adding to linear_offset*/
2732 linear_offset +=
6e3c9717
ACO		 2733 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2734 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2735 }
2736
2737 I915_WRITE(reg, dspcntr);
2738
01f2c773 2739 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2740 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2741 I915_WRITE(DSPSURF(plane),
2742 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2743 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2744 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2745 } else
f343c5f6 2746 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2747 POSTING_READ(reg);
17638cd6
JB		 2748}
2749
29b9bde6
DV		 2750static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2751 struct drm_framebuffer *fb,
2752 int x, int y)
17638cd6
JB		 2753{
2754 struct drm_device *dev = crtc->dev;
2755 struct drm_i915_private *dev_priv = dev->dev_private;
2756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2757 struct drm_plane *primary = crtc->primary;
2758 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2759 struct drm_i915_gem_object *obj;
17638cd6 2760 int plane = intel_crtc->plane;
e506a0c6 2761 unsigned long linear_offset;
17638cd6 2762 u32 dspcntr;
f45651ba 2763 u32 reg = DSPCNTR(plane);
48404c1e 2764 int pixel_size;
f45651ba 2765
b70709a6 2766 if (!visible || !fb) {
fdd508a6
VS		 2767 I915_WRITE(reg, 0);
2768 I915_WRITE(DSPSURF(plane), 0);
2769 POSTING_READ(reg);
2770 return;
2771 }
2772
c9ba6fad
VS		 2773 obj = intel_fb_obj(fb);
2774 if (WARN_ON(obj == NULL))
2775 return;
2776
2777 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2778
f45651ba
VS		 2779 dspcntr = DISPPLANE_GAMMA_ENABLE;
2780
fdd508a6 2781 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2782
2783 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2784 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2785
57779d06
VS		 2786 switch (fb->pixel_format) {
2787 case DRM_FORMAT_C8:
17638cd6
JB		 2788 dspcntr |= DISPPLANE_8BPP;
2789 break;
57779d06
VS		 2790 case DRM_FORMAT_RGB565:
2791 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2792 break;
57779d06 2793 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2794 dspcntr |= DISPPLANE_BGRX888;
2795 break;
2796 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2797 dspcntr |= DISPPLANE_RGBX888;
2798 break;
2799 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2800 dspcntr |= DISPPLANE_BGRX101010;
2801 break;
2802 case DRM_FORMAT_XBGR2101010:
57779d06 2803 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2804 break;
2805 default:
baba133a 2806 BUG();
17638cd6
JB		 2807 }
2808
2809 if (obj->tiling_mode != I915_TILING_NONE)
2810 dspcntr |= DISPPLANE_TILED;
17638cd6 2811
f45651ba 2812 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2813 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2814
b9897127 2815 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2816 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2817 intel_gen4_compute_page_offset(dev_priv,
2818 &x, &y, obj->tiling_mode,
b9897127 2819 pixel_size,
bc752862 2820 fb->pitches[0]);
c2c75131 2821 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2822 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2823 dspcntr |= DISPPLANE_ROTATE_180;
2824
2825 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2826 x += (intel_crtc->config->pipe_src_w - 1);
2827 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2828
2829 /* Finding the last pixel of the last line of the display
2830 data and adding to linear_offset*/
2831 linear_offset +=
6e3c9717
ACO		 2832 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2833 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2834 }
2835 }
2836
2837 I915_WRITE(reg, dspcntr);
17638cd6 2838
01f2c773 2839 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2840 I915_WRITE(DSPSURF(plane),
2841 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2842 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2843 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2844 } else {
2845 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2846 I915_WRITE(DSPLINOFF(plane), linear_offset);
2847 }
17638cd6 2848 POSTING_READ(reg);
17638cd6
JB		 2849}
2850
b321803d
DL		 2851u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2852 uint32_t pixel_format)
2853{
2854 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2855
2856 /*
2857 * The stride is either expressed as a multiple of 64 bytes
2858 * chunks for linear buffers or in number of tiles for tiled
2859 * buffers.
2860 */
2861 switch (fb_modifier) {
2862 case DRM_FORMAT_MOD_NONE:
2863 return 64;
2864 case I915_FORMAT_MOD_X_TILED:
2865 if (INTEL_INFO(dev)->gen == 2)
2866 return 128;
2867 return 512;
2868 case I915_FORMAT_MOD_Y_TILED:
2869 /* No need to check for old gens and Y tiling since this is
2870 * about the display engine and those will be blocked before
2871 * we get here.
2872 */
2873 return 128;
2874 case I915_FORMAT_MOD_Yf_TILED:
2875 if (bits_per_pixel == 8)
2876 return 64;
2877 else
2878 return 128;
2879 default:
2880 MISSING_CASE(fb_modifier);
2881 return 64;
2882 }
2883}
2884
121920fa
TU		 2885unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2886 struct drm_i915_gem_object *obj)
2887{
9abc4648 2888 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2889
2890 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2891 view = &i915_ggtt_view_rotated;
121920fa
TU		 2892
2893 return i915_gem_obj_ggtt_offset_view(obj, view);
2894}
2895
a1b2278e
CK		 2896/*
2897 * This function detaches (aka. unbinds) unused scalers in hardware
2898 */
0583236e 2899static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e
CK		 2900{
2901 struct drm_device *dev;
2902 struct drm_i915_private *dev_priv;
2903 struct intel_crtc_scaler_state *scaler_state;
2904 int i;
2905
a1b2278e
CK		 2906 dev = intel_crtc->base.dev;
2907 dev_priv = dev->dev_private;
2908 scaler_state = &intel_crtc->config->scaler_state;
2909
2910 /* loop through and disable scalers that aren't in use */
2911 for (i = 0; i < intel_crtc->num_scalers; i++) {
2912 if (!scaler_state->scalers[i].in_use) {
2913 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2914 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2915 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2916 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2917 intel_crtc->base.base.id, intel_crtc->pipe, i);
2918 }
2919 }
2920}
2921
6156a456 2922u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2923{
6156a456 2924 switch (pixel_format) {
d161cf7a 2925 case DRM_FORMAT_C8:
c34ce3d1 2926 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2927 case DRM_FORMAT_RGB565:
c34ce3d1 2928 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2929 case DRM_FORMAT_XBGR8888:
c34ce3d1 2930 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2931 case DRM_FORMAT_XRGB8888:
c34ce3d1 2932 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2933 /*
2934 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2935 * to be already pre-multiplied. We need to add a knob (or a different
2936 * DRM_FORMAT) for user-space to configure that.
2937 */
f75fb42a 2938 case DRM_FORMAT_ABGR8888:
c34ce3d1 2939 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2940 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2941 case DRM_FORMAT_ARGB8888:
c34ce3d1 2942 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2943 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2944 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2945 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2946 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2947 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2948 case DRM_FORMAT_YUYV:
c34ce3d1 2949 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2950 case DRM_FORMAT_YVYU:
c34ce3d1 2951 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2952 case DRM_FORMAT_UYVY:
c34ce3d1 2953 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2954 case DRM_FORMAT_VYUY:
c34ce3d1 2955 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2956 default:
4249eeef 2957 MISSING_CASE(pixel_format);
70d21f0e 2958 }
8cfcba41 2959
c34ce3d1 2960 return 0;
6156a456 2961}
70d21f0e 2962
6156a456
CK		 2963u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2964{
6156a456 2965 switch (fb_modifier) {
30af77c4 2966 case DRM_FORMAT_MOD_NONE:
70d21f0e 2967 break;
30af77c4 2968 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2969 return PLANE_CTL_TILED_X;
b321803d 2970 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2971 return PLANE_CTL_TILED_Y;
b321803d 2972 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2973 return PLANE_CTL_TILED_YF;
70d21f0e 2974 default:
6156a456 2975 MISSING_CASE(fb_modifier);
70d21f0e 2976 }
8cfcba41 2977
c34ce3d1 2978 return 0;
6156a456 2979}
70d21f0e 2980
6156a456
CK		 2981u32 skl_plane_ctl_rotation(unsigned int rotation)
2982{
3b7a5119 2983 switch (rotation) {
6156a456
CK		 2984 case BIT(DRM_ROTATE_0):
2985 break;
1e8df167
SJ		 2986 /*
2987 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2988 * while i915 HW rotation is clockwise, thats why this swapping.
2989 */
3b7a5119 2990 case BIT(DRM_ROTATE_90):
1e8df167 2991 return PLANE_CTL_ROTATE_270;
3b7a5119 2992 case BIT(DRM_ROTATE_180):
c34ce3d1 2993 return PLANE_CTL_ROTATE_180;
3b7a5119 2994 case BIT(DRM_ROTATE_270):
1e8df167 2995 return PLANE_CTL_ROTATE_90;
6156a456
CK		 2996 default:
2997 MISSING_CASE(rotation);
2998 }
2999
c34ce3d1 3000 return 0;
6156a456
CK		 3001}
3002
3003static void skylake_update_primary_plane(struct drm_crtc *crtc,
3004 struct drm_framebuffer *fb,
3005 int x, int y)
3006{
3007 struct drm_device *dev = crtc->dev;
3008 struct drm_i915_private *dev_priv = dev->dev_private;
3009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3010 struct drm_plane *plane = crtc->primary;
3011 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3012 struct drm_i915_gem_object *obj;
3013 int pipe = intel_crtc->pipe;
3014 u32 plane_ctl, stride_div, stride;
3015 u32 tile_height, plane_offset, plane_size;
3016 unsigned int rotation;
3017 int x_offset, y_offset;
3018 unsigned long surf_addr;
6156a456
CK		 3019 struct intel_crtc_state *crtc_state = intel_crtc->config;
3020 struct intel_plane_state *plane_state;
3021 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3022 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3023 int scaler_id = -1;
3024
6156a456
CK		 3025 plane_state = to_intel_plane_state(plane->state);
3026
b70709a6 3027 if (!visible || !fb) {
6156a456
CK		 3028 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3029 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3030 POSTING_READ(PLANE_CTL(pipe, 0));
3031 return;
3b7a5119 3032 }
70d21f0e 3033
6156a456
CK		 3034 plane_ctl = PLANE_CTL_ENABLE |
3035 PLANE_CTL_PIPE_GAMMA_ENABLE |
3036 PLANE_CTL_PIPE_CSC_ENABLE;
3037
3038 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3039 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3040 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3041
3042 rotation = plane->state->rotation;
3043 plane_ctl |= skl_plane_ctl_rotation(rotation);
3044
b321803d
DL		 3045 obj = intel_fb_obj(fb);
3046 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3047 fb->pixel_format);
3b7a5119
SJ		 3048 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3049
6156a456
CK		 3050 /*
3051 * FIXME: intel_plane_state->src, dst aren't set when transitional
3052 * update_plane helpers are called from legacy paths.
3053 * Once full atomic crtc is available, below check can be avoided.
3054 */
3055 if (drm_rect_width(&plane_state->src)) {
3056 scaler_id = plane_state->scaler_id;
3057 src_x = plane_state->src.x1 >> 16;
3058 src_y = plane_state->src.y1 >> 16;
3059 src_w = drm_rect_width(&plane_state->src) >> 16;
3060 src_h = drm_rect_height(&plane_state->src) >> 16;
3061 dst_x = plane_state->dst.x1;
3062 dst_y = plane_state->dst.y1;
3063 dst_w = drm_rect_width(&plane_state->dst);
3064 dst_h = drm_rect_height(&plane_state->dst);
3065
3066 WARN_ON(x != src_x || y != src_y);
3067 } else {
3068 src_w = intel_crtc->config->pipe_src_w;
3069 src_h = intel_crtc->config->pipe_src_h;
3070 }
3071
3b7a5119
SJ		 3072 if (intel_rotation_90_or_270(rotation)) {
3073 /* stride = Surface height in tiles */
2614f17d 3074 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3075 fb->modifier[0]);
3076 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3077 x_offset = stride * tile_height - y - src_h;
3b7a5119 3078 y_offset = x;
6156a456 3079 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3080 } else {
3081 stride = fb->pitches[0] / stride_div;
3082 x_offset = x;
3083 y_offset = y;
6156a456 3084 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3085 }
3086 plane_offset = y_offset << 16 | x_offset;
b321803d 3087
70d21f0e 3088 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3089 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3090 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3091 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3092
3093 if (scaler_id >= 0) {
3094 uint32_t ps_ctrl = 0;
3095
3096 WARN_ON(!dst_w || !dst_h);
3097 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3098 crtc_state->scaler_state.scalers[scaler_id].mode;
3099 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3100 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3101 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3102 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3103 I915_WRITE(PLANE_POS(pipe, 0), 0);
3104 } else {
3105 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3106 }
3107
121920fa 3108 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3109
3110 POSTING_READ(PLANE_SURF(pipe, 0));
3111}
3112
17638cd6
JB		 3113/* Assume fb object is pinned & idle & fenced and just update base pointers */
3114static int
3115intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3116 int x, int y, enum mode_set_atomic state)
3117{
3118 struct drm_device *dev = crtc->dev;
3119 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3120
6b8e6ed0
CW		 3121 if (dev_priv->display.disable_fbc)
3122 dev_priv->display.disable_fbc(dev);
81255565 3123
29b9bde6
DV		 3124 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3125
3126 return 0;
81255565
JB		 3127}
3128
7514747d 3129static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3130{
96a02917
VS		 3131 struct drm_crtc *crtc;
3132
70e1e0ec 3133 for_each_crtc(dev, crtc) {
96a02917
VS		 3134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3135 enum plane plane = intel_crtc->plane;
3136
3137 intel_prepare_page_flip(dev, plane);
3138 intel_finish_page_flip_plane(dev, plane);
3139 }
7514747d
VS		 3140}
3141
3142static void intel_update_primary_planes(struct drm_device *dev)
3143{
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 struct drm_crtc *crtc;
96a02917 3146
70e1e0ec 3147 for_each_crtc(dev, crtc) {
96a02917
VS		 3148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3149
51fd371b 3150 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3151 /*
3152 * FIXME: Once we have proper support for primary planes (and
3153 * disabling them without disabling the entire crtc) allow again
66e514c1 3154 * a NULL crtc->primary->fb.
947fdaad 3155 */
f4510a27 3156 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3157 dev_priv->display.update_primary_plane(crtc,
66e514c1 3158 crtc->primary->fb,
262ca2b0
MR		 3159 crtc->x,
3160 crtc->y);
51fd371b 3161 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3162 }
3163}
3164
7514747d
VS		 3165void intel_prepare_reset(struct drm_device *dev)
3166{
3167 /* no reset support for gen2 */
3168 if (IS_GEN2(dev))
3169 return;
3170
3171 /* reset doesn't touch the display */
3172 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3173 return;
3174
3175 drm_modeset_lock_all(dev);
f98ce92f
VS		 3176 /*
3177 * Disabling the crtcs gracefully seems nicer. Also the
3178 * g33 docs say we should at least disable all the planes.
3179 */
6b72d486 3180 intel_display_suspend(dev);
7514747d
VS		 3181}
3182
3183void intel_finish_reset(struct drm_device *dev)
3184{
3185 struct drm_i915_private *dev_priv = to_i915(dev);
3186
3187 /*
3188 * Flips in the rings will be nuked by the reset,
3189 * so complete all pending flips so that user space
3190 * will get its events and not get stuck.
3191 */
3192 intel_complete_page_flips(dev);
3193
3194 /* no reset support for gen2 */
3195 if (IS_GEN2(dev))
3196 return;
3197
3198 /* reset doesn't touch the display */
3199 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3200 /*
3201 * Flips in the rings have been nuked by the reset,
3202 * so update the base address of all primary
3203 * planes to the the last fb to make sure we're
3204 * showing the correct fb after a reset.
3205 */
3206 intel_update_primary_planes(dev);
3207 return;
3208 }
3209
3210 /*
3211 * The display has been reset as well,
3212 * so need a full re-initialization.
3213 */
3214 intel_runtime_pm_disable_interrupts(dev_priv);
3215 intel_runtime_pm_enable_interrupts(dev_priv);
3216
3217 intel_modeset_init_hw(dev);
3218
3219 spin_lock_irq(&dev_priv->irq_lock);
3220 if (dev_priv->display.hpd_irq_setup)
3221 dev_priv->display.hpd_irq_setup(dev);
3222 spin_unlock_irq(&dev_priv->irq_lock);
3223
3224 intel_modeset_setup_hw_state(dev, true);
3225
3226 intel_hpd_init(dev_priv);
3227
3228 drm_modeset_unlock_all(dev);
3229}
3230
2e2f351d 3231static void
14667a4b
CW		 3232intel_finish_fb(struct drm_framebuffer *old_fb)
3233{
2ff8fde1 3234 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3235 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3236 bool was_interruptible = dev_priv->mm.interruptible;
3237 int ret;
3238
14667a4b
CW		 3239 /* Big Hammer, we also need to ensure that any pending
3240 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3241 * current scanout is retired before unpinning the old
2e2f351d
CW		 3242 * framebuffer. Note that we rely on userspace rendering
3243 * into the buffer attached to the pipe they are waiting
3244 * on. If not, userspace generates a GPU hang with IPEHR
3245 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3246 *
3247 * This should only fail upon a hung GPU, in which case we
3248 * can safely continue.
3249 */
3250 dev_priv->mm.interruptible = false;
2e2f351d 3251 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3252 dev_priv->mm.interruptible = was_interruptible;
3253
2e2f351d 3254 WARN_ON(ret);
14667a4b
CW		 3255}
3256
7d5e3799
CW		 3257static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3258{
3259 struct drm_device *dev = crtc->dev;
3260 struct drm_i915_private *dev_priv = dev->dev_private;
3261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3262 bool pending;
3263
3264 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3265 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3266 return false;
3267
5e2d7afc 3268 spin_lock_irq(&dev->event_lock);
7d5e3799 3269 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3270 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3271
3272 return pending;
3273}
3274
e30e8f75
GP		 3275static void intel_update_pipe_size(struct intel_crtc *crtc)
3276{
3277 struct drm_device *dev = crtc->base.dev;
3278 struct drm_i915_private *dev_priv = dev->dev_private;
3279 const struct drm_display_mode *adjusted_mode;
3280
3281 if (!i915.fastboot)
3282 return;
3283
3284 /*
3285 * Update pipe size and adjust fitter if needed: the reason for this is
3286 * that in compute_mode_changes we check the native mode (not the pfit
3287 * mode) to see if we can flip rather than do a full mode set. In the
3288 * fastboot case, we'll flip, but if we don't update the pipesrc and
3289 * pfit state, we'll end up with a big fb scanned out into the wrong
3290 * sized surface.
3291 *
3292 * To fix this properly, we need to hoist the checks up into
3293 * compute_mode_changes (or above), check the actual pfit state and
3294 * whether the platform allows pfit disable with pipe active, and only
3295 * then update the pipesrc and pfit state, even on the flip path.
3296 */
3297
6e3c9717 3298 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3299
3300 I915_WRITE(PIPESRC(crtc->pipe),
3301 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3302 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3303 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3304 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3305 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3306 I915_WRITE(PF_CTL(crtc->pipe), 0);
3307 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3308 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3309 }
6e3c9717
ACO		 3310 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3311 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3312}
3313
5e84e1a4
ZW		 3314static void intel_fdi_normal_train(struct drm_crtc *crtc)
3315{
3316 struct drm_device *dev = crtc->dev;
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3319 int pipe = intel_crtc->pipe;
3320 u32 reg, temp;
3321
3322 /* enable normal train */
3323 reg = FDI_TX_CTL(pipe);
3324 temp = I915_READ(reg);
61e499bf 3325 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3326 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3327 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3328 } else {
3329 temp &= ~FDI_LINK_TRAIN_NONE;
3330 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3331 }
5e84e1a4
ZW		 3332 I915_WRITE(reg, temp);
3333
3334 reg = FDI_RX_CTL(pipe);
3335 temp = I915_READ(reg);
3336 if (HAS_PCH_CPT(dev)) {
3337 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3338 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3339 } else {
3340 temp &= ~FDI_LINK_TRAIN_NONE;
3341 temp |= FDI_LINK_TRAIN_NONE;
3342 }
3343 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3344
3345 /* wait one idle pattern time */
3346 POSTING_READ(reg);
3347 udelay(1000);
357555c0
JB		 3348
3349 /* IVB wants error correction enabled */
3350 if (IS_IVYBRIDGE(dev))
3351 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3352 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3353}
3354
8db9d77b
ZW		 3355/* The FDI link training functions for ILK/Ibexpeak. */
3356static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3357{
3358 struct drm_device *dev = crtc->dev;
3359 struct drm_i915_private *dev_priv = dev->dev_private;
3360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3361 int pipe = intel_crtc->pipe;
5eddb70b 3362 u32 reg, temp, tries;
8db9d77b 3363
1c8562f6 3364 /* FDI needs bits from pipe first */
0fc932b8 3365 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3366
e1a44743
AJ		 3367 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3368 for train result */
5eddb70b
CW		 3369 reg = FDI_RX_IMR(pipe);
3370 temp = I915_READ(reg);
e1a44743
AJ		 3371 temp &= ~FDI_RX_SYMBOL_LOCK;
3372 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3373 I915_WRITE(reg, temp);
3374 I915_READ(reg);
e1a44743
AJ		 3375 udelay(150);
3376
8db9d77b 3377 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3378 reg = FDI_TX_CTL(pipe);
3379 temp = I915_READ(reg);
627eb5a3 3380 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3381 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3382 temp &= ~FDI_LINK_TRAIN_NONE;
3383 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3384 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3385
5eddb70b
CW		 3386 reg = FDI_RX_CTL(pipe);
3387 temp = I915_READ(reg);
8db9d77b
ZW		 3388 temp &= ~FDI_LINK_TRAIN_NONE;
3389 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3390 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3391
3392 POSTING_READ(reg);
8db9d77b
ZW		 3393 udelay(150);
3394
5b2adf89 3395 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3396 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3397 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3398 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3399
5eddb70b 3400 reg = FDI_RX_IIR(pipe);
e1a44743 3401 for (tries = 0; tries < 5; tries++) {
5eddb70b 3402 temp = I915_READ(reg);
8db9d77b
ZW		 3403 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3404
3405 if ((temp & FDI_RX_BIT_LOCK)) {
3406 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3407 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3408 break;
3409 }
8db9d77b 3410 }
e1a44743 3411 if (tries == 5)
5eddb70b 3412 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3413
3414 /* Train 2 */
5eddb70b
CW		 3415 reg = FDI_TX_CTL(pipe);
3416 temp = I915_READ(reg);
8db9d77b
ZW		 3417 temp &= ~FDI_LINK_TRAIN_NONE;
3418 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3419 I915_WRITE(reg, temp);
8db9d77b 3420
5eddb70b
CW		 3421 reg = FDI_RX_CTL(pipe);
3422 temp = I915_READ(reg);
8db9d77b
ZW		 3423 temp &= ~FDI_LINK_TRAIN_NONE;
3424 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3425 I915_WRITE(reg, temp);
8db9d77b 3426
5eddb70b
CW		 3427 POSTING_READ(reg);
3428 udelay(150);
8db9d77b 3429
5eddb70b 3430 reg = FDI_RX_IIR(pipe);
e1a44743 3431 for (tries = 0; tries < 5; tries++) {
5eddb70b 3432 temp = I915_READ(reg);
8db9d77b
ZW		 3433 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3434
3435 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3436 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3437 DRM_DEBUG_KMS("FDI train 2 done.\n");
3438 break;
3439 }
8db9d77b 3440 }
e1a44743 3441 if (tries == 5)
5eddb70b 3442 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3443
3444 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3445
8db9d77b
ZW		 3446}
3447
0206e353 3448static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3449 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3450 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3451 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3452 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3453};
3454
3455/* The FDI link training functions for SNB/Cougarpoint. */
3456static void gen6_fdi_link_train(struct drm_crtc *crtc)
3457{
3458 struct drm_device *dev = crtc->dev;
3459 struct drm_i915_private *dev_priv = dev->dev_private;
3460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3461 int pipe = intel_crtc->pipe;
fa37d39e 3462 u32 reg, temp, i, retry;
8db9d77b 3463
e1a44743
AJ		 3464 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3465 for train result */
5eddb70b
CW		 3466 reg = FDI_RX_IMR(pipe);
3467 temp = I915_READ(reg);
e1a44743
AJ		 3468 temp &= ~FDI_RX_SYMBOL_LOCK;
3469 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3470 I915_WRITE(reg, temp);
3471
3472 POSTING_READ(reg);
e1a44743
AJ		 3473 udelay(150);
3474
8db9d77b 3475 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3476 reg = FDI_TX_CTL(pipe);
3477 temp = I915_READ(reg);
627eb5a3 3478 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3479 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3480 temp &= ~FDI_LINK_TRAIN_NONE;
3481 temp |= FDI_LINK_TRAIN_PATTERN_1;
3482 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3483 /* SNB-B */
3484 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3485 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3486
d74cf324
DV		 3487 I915_WRITE(FDI_RX_MISC(pipe),
3488 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3489
5eddb70b
CW		 3490 reg = FDI_RX_CTL(pipe);
3491 temp = I915_READ(reg);
8db9d77b
ZW		 3492 if (HAS_PCH_CPT(dev)) {
3493 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3494 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3495 } else {
3496 temp &= ~FDI_LINK_TRAIN_NONE;
3497 temp |= FDI_LINK_TRAIN_PATTERN_1;
3498 }
5eddb70b
CW		 3499 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3500
3501 POSTING_READ(reg);
8db9d77b
ZW		 3502 udelay(150);
3503
0206e353 3504 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3505 reg = FDI_TX_CTL(pipe);
3506 temp = I915_READ(reg);
8db9d77b
ZW		 3507 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3508 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3509 I915_WRITE(reg, temp);
3510
3511 POSTING_READ(reg);
8db9d77b
ZW		 3512 udelay(500);
3513
fa37d39e
SP		 3514 for (retry = 0; retry < 5; retry++) {
3515 reg = FDI_RX_IIR(pipe);
3516 temp = I915_READ(reg);
3517 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3518 if (temp & FDI_RX_BIT_LOCK) {
3519 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3520 DRM_DEBUG_KMS("FDI train 1 done.\n");
3521 break;
3522 }
3523 udelay(50);
8db9d77b 3524 }
fa37d39e
SP		 3525 if (retry < 5)
3526 break;
8db9d77b
ZW		 3527 }
3528 if (i == 4)
5eddb70b 3529 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3530
3531 /* Train 2 */
5eddb70b
CW		 3532 reg = FDI_TX_CTL(pipe);
3533 temp = I915_READ(reg);
8db9d77b
ZW		 3534 temp &= ~FDI_LINK_TRAIN_NONE;
3535 temp |= FDI_LINK_TRAIN_PATTERN_2;
3536 if (IS_GEN6(dev)) {
3537 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3538 /* SNB-B */
3539 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3540 }
5eddb70b 3541 I915_WRITE(reg, temp);
8db9d77b 3542
5eddb70b
CW		 3543 reg = FDI_RX_CTL(pipe);
3544 temp = I915_READ(reg);
8db9d77b
ZW		 3545 if (HAS_PCH_CPT(dev)) {
3546 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3547 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3548 } else {
3549 temp &= ~FDI_LINK_TRAIN_NONE;
3550 temp |= FDI_LINK_TRAIN_PATTERN_2;
3551 }
5eddb70b
CW		 3552 I915_WRITE(reg, temp);
3553
3554 POSTING_READ(reg);
8db9d77b
ZW		 3555 udelay(150);
3556
0206e353 3557 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3558 reg = FDI_TX_CTL(pipe);
3559 temp = I915_READ(reg);
8db9d77b
ZW		 3560 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3561 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3562 I915_WRITE(reg, temp);
3563
3564 POSTING_READ(reg);
8db9d77b
ZW		 3565 udelay(500);
3566
fa37d39e
SP		 3567 for (retry = 0; retry < 5; retry++) {
3568 reg = FDI_RX_IIR(pipe);
3569 temp = I915_READ(reg);
3570 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3571 if (temp & FDI_RX_SYMBOL_LOCK) {
3572 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3573 DRM_DEBUG_KMS("FDI train 2 done.\n");
3574 break;
3575 }
3576 udelay(50);
8db9d77b 3577 }
fa37d39e
SP		 3578 if (retry < 5)
3579 break;
8db9d77b
ZW		 3580 }
3581 if (i == 4)
5eddb70b 3582 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3583
3584 DRM_DEBUG_KMS("FDI train done.\n");
3585}
3586
357555c0
JB		 3587/* Manual link training for Ivy Bridge A0 parts */
3588static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3589{
3590 struct drm_device *dev = crtc->dev;
3591 struct drm_i915_private *dev_priv = dev->dev_private;
3592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3593 int pipe = intel_crtc->pipe;
139ccd3f 3594 u32 reg, temp, i, j;
357555c0
JB		 3595
3596 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3597 for train result */
3598 reg = FDI_RX_IMR(pipe);
3599 temp = I915_READ(reg);
3600 temp &= ~FDI_RX_SYMBOL_LOCK;
3601 temp &= ~FDI_RX_BIT_LOCK;
3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
3605 udelay(150);
3606
01a415fd
DV		 3607 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3608 I915_READ(FDI_RX_IIR(pipe)));
3609
139ccd3f
JB		 3610 /* Try each vswing and preemphasis setting twice before moving on */
3611 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3612 /* disable first in case we need to retry */
3613 reg = FDI_TX_CTL(pipe);
3614 temp = I915_READ(reg);
3615 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3616 temp &= ~FDI_TX_ENABLE;
3617 I915_WRITE(reg, temp);
357555c0 3618
139ccd3f
JB		 3619 reg = FDI_RX_CTL(pipe);
3620 temp = I915_READ(reg);
3621 temp &= ~FDI_LINK_TRAIN_AUTO;
3622 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3623 temp &= ~FDI_RX_ENABLE;
3624 I915_WRITE(reg, temp);
357555c0 3625
139ccd3f 3626 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3627 reg = FDI_TX_CTL(pipe);
3628 temp = I915_READ(reg);
139ccd3f 3629 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3630 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3631 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3632 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3633 temp |= snb_b_fdi_train_param[j/2];
3634 temp |= FDI_COMPOSITE_SYNC;
3635 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3636
139ccd3f
JB		 3637 I915_WRITE(FDI_RX_MISC(pipe),
3638 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3639
139ccd3f 3640 reg = FDI_RX_CTL(pipe);
357555c0 3641 temp = I915_READ(reg);
139ccd3f
JB		 3642 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3643 temp |= FDI_COMPOSITE_SYNC;
3644 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3645
139ccd3f
JB		 3646 POSTING_READ(reg);
3647 udelay(1); /* should be 0.5us */
357555c0 3648
139ccd3f
JB		 3649 for (i = 0; i < 4; i++) {
3650 reg = FDI_RX_IIR(pipe);
3651 temp = I915_READ(reg);
3652 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3653
139ccd3f
JB		 3654 if (temp & FDI_RX_BIT_LOCK ||
3655 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3656 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3657 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3658 i);
3659 break;
3660 }
3661 udelay(1); /* should be 0.5us */
3662 }
3663 if (i == 4) {
3664 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3665 continue;
3666 }
357555c0 3667
139ccd3f 3668 /* Train 2 */
357555c0
JB		 3669 reg = FDI_TX_CTL(pipe);
3670 temp = I915_READ(reg);
139ccd3f
JB		 3671 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3672 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3673 I915_WRITE(reg, temp);
3674
3675 reg = FDI_RX_CTL(pipe);
3676 temp = I915_READ(reg);
3677 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3678 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3679 I915_WRITE(reg, temp);
3680
3681 POSTING_READ(reg);
139ccd3f 3682 udelay(2); /* should be 1.5us */
357555c0 3683
139ccd3f
JB		 3684 for (i = 0; i < 4; i++) {
3685 reg = FDI_RX_IIR(pipe);
3686 temp = I915_READ(reg);
3687 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3688
139ccd3f
JB		 3689 if (temp & FDI_RX_SYMBOL_LOCK ||
3690 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3691 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3692 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3693 i);
3694 goto train_done;
3695 }
3696 udelay(2); /* should be 1.5us */
357555c0 3697 }
139ccd3f
JB		 3698 if (i == 4)
3699 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3700 }
357555c0 3701
139ccd3f 3702train_done:
357555c0
JB		 3703 DRM_DEBUG_KMS("FDI train done.\n");
3704}
3705
88cefb6c 3706static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3707{
88cefb6c 3708 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3709 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3710 int pipe = intel_crtc->pipe;
5eddb70b 3711 u32 reg, temp;
79e53945 3712
c64e311e 3713
c98e9dcf 3714 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3715 reg = FDI_RX_CTL(pipe);
3716 temp = I915_READ(reg);
627eb5a3 3717 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3718 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3719 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3720 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3721
3722 POSTING_READ(reg);
c98e9dcf
JB		 3723 udelay(200);
3724
3725 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3726 temp = I915_READ(reg);
3727 I915_WRITE(reg, temp | FDI_PCDCLK);
3728
3729 POSTING_READ(reg);
c98e9dcf
JB		 3730 udelay(200);
3731
20749730
PZ		 3732 /* Enable CPU FDI TX PLL, always on for Ironlake */
3733 reg = FDI_TX_CTL(pipe);
3734 temp = I915_READ(reg);
3735 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3736 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3737
20749730
PZ		 3738 POSTING_READ(reg);
3739 udelay(100);
6be4a607 3740 }
0e23b99d
JB		 3741}
3742
88cefb6c
DV		 3743static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3744{
3745 struct drm_device *dev = intel_crtc->base.dev;
3746 struct drm_i915_private *dev_priv = dev->dev_private;
3747 int pipe = intel_crtc->pipe;
3748 u32 reg, temp;
3749
3750 /* Switch from PCDclk to Rawclk */
3751 reg = FDI_RX_CTL(pipe);
3752 temp = I915_READ(reg);
3753 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3754
3755 /* Disable CPU FDI TX PLL */
3756 reg = FDI_TX_CTL(pipe);
3757 temp = I915_READ(reg);
3758 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3759
3760 POSTING_READ(reg);
3761 udelay(100);
3762
3763 reg = FDI_RX_CTL(pipe);
3764 temp = I915_READ(reg);
3765 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3766
3767 /* Wait for the clocks to turn off. */
3768 POSTING_READ(reg);
3769 udelay(100);
3770}
3771
0fc932b8
JB		 3772static void ironlake_fdi_disable(struct drm_crtc *crtc)
3773{
3774 struct drm_device *dev = crtc->dev;
3775 struct drm_i915_private *dev_priv = dev->dev_private;
3776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777 int pipe = intel_crtc->pipe;
3778 u32 reg, temp;
3779
3780 /* disable CPU FDI tx and PCH FDI rx */
3781 reg = FDI_TX_CTL(pipe);
3782 temp = I915_READ(reg);
3783 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3784 POSTING_READ(reg);
3785
3786 reg = FDI_RX_CTL(pipe);
3787 temp = I915_READ(reg);
3788 temp &= ~(0x7 << 16);
dfd07d72 3789 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3790 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3791
3792 POSTING_READ(reg);
3793 udelay(100);
3794
3795 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3796 if (HAS_PCH_IBX(dev))
6f06ce18 3797 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3798
3799 /* still set train pattern 1 */
3800 reg = FDI_TX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 temp &= ~FDI_LINK_TRAIN_NONE;
3803 temp |= FDI_LINK_TRAIN_PATTERN_1;
3804 I915_WRITE(reg, temp);
3805
3806 reg = FDI_RX_CTL(pipe);
3807 temp = I915_READ(reg);
3808 if (HAS_PCH_CPT(dev)) {
3809 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3810 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3811 } else {
3812 temp &= ~FDI_LINK_TRAIN_NONE;
3813 temp |= FDI_LINK_TRAIN_PATTERN_1;
3814 }
3815 /* BPC in FDI rx is consistent with that in PIPECONF */
3816 temp &= ~(0x07 << 16);
dfd07d72 3817 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3818 I915_WRITE(reg, temp);
3819
3820 POSTING_READ(reg);
3821 udelay(100);
3822}
3823
5dce5b93
CW		 3824bool intel_has_pending_fb_unpin(struct drm_device *dev)
3825{
3826 struct intel_crtc *crtc;
3827
3828 /* Note that we don't need to be called with mode_config.lock here
3829 * as our list of CRTC objects is static for the lifetime of the
3830 * device and so cannot disappear as we iterate. Similarly, we can
3831 * happily treat the predicates as racy, atomic checks as userspace
3832 * cannot claim and pin a new fb without at least acquring the
3833 * struct_mutex and so serialising with us.
3834 */
d3fcc808 3835 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3836 if (atomic_read(&crtc->unpin_work_count) == 0)
3837 continue;
3838
3839 if (crtc->unpin_work)
3840 intel_wait_for_vblank(dev, crtc->pipe);
3841
3842 return true;
3843 }
3844
3845 return false;
3846}
3847
d6bbafa1
CW		 3848static void page_flip_completed(struct intel_crtc *intel_crtc)
3849{
3850 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3851 struct intel_unpin_work *work = intel_crtc->unpin_work;
3852
3853 /* ensure that the unpin work is consistent wrt ->pending. */
3854 smp_rmb();
3855 intel_crtc->unpin_work = NULL;
3856
3857 if (work->event)
3858 drm_send_vblank_event(intel_crtc->base.dev,
3859 intel_crtc->pipe,
3860 work->event);
3861
3862 drm_crtc_vblank_put(&intel_crtc->base);
3863
3864 wake_up_all(&dev_priv->pending_flip_queue);
3865 queue_work(dev_priv->wq, &work->work);
3866
3867 trace_i915_flip_complete(intel_crtc->plane,
3868 work->pending_flip_obj);
3869}
3870
46a55d30 3871void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3872{
0f91128d 3873 struct drm_device *dev = crtc->dev;
5bb61643 3874 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3875
2c10d571 3876 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3877 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3878 !intel_crtc_has_pending_flip(crtc),
3879 60*HZ) == 0)) {
3880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3881
5e2d7afc 3882 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3883 if (intel_crtc->unpin_work) {
3884 WARN_ONCE(1, "Removing stuck page flip\n");
3885 page_flip_completed(intel_crtc);
3886 }
5e2d7afc 3887 spin_unlock_irq(&dev->event_lock);
9c787942 3888 }
5bb61643 3889
975d568a
CW		 3890 if (crtc->primary->fb) {
3891 mutex_lock(&dev->struct_mutex);
3892 intel_finish_fb(crtc->primary->fb);
3893 mutex_unlock(&dev->struct_mutex);
3894 }
e6c3a2a6
CW		 3895}
3896
e615efe4
ED		 3897/* Program iCLKIP clock to the desired frequency */
3898static void lpt_program_iclkip(struct drm_crtc *crtc)
3899{
3900 struct drm_device *dev = crtc->dev;
3901 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3902 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3903 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3904 u32 temp;
3905
a580516d 3906 mutex_lock(&dev_priv->sb_lock);
09153000 3907
e615efe4
ED		 3908 /* It is necessary to ungate the pixclk gate prior to programming
3909 * the divisors, and gate it back when it is done.
3910 */
3911 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3912
3913 /* Disable SSCCTL */
3914 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3915 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3916 SBI_SSCCTL_DISABLE,
3917 SBI_ICLK);
e615efe4
ED		 3918
3919 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3920 if (clock == 20000) {
e615efe4
ED		 3921 auxdiv = 1;
3922 divsel = 0x41;
3923 phaseinc = 0x20;
3924 } else {
3925 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3926 * but the adjusted_mode->crtc_clock in in KHz. To get the
3927 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3928 * convert the virtual clock precision to KHz here for higher
3929 * precision.
3930 */
3931 u32 iclk_virtual_root_freq = 172800 * 1000;
3932 u32 iclk_pi_range = 64;
3933 u32 desired_divisor, msb_divisor_value, pi_value;
3934
12d7ceed 3935 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3936 msb_divisor_value = desired_divisor / iclk_pi_range;
3937 pi_value = desired_divisor % iclk_pi_range;
3938
3939 auxdiv = 0;
3940 divsel = msb_divisor_value - 2;
3941 phaseinc = pi_value;
3942 }
3943
3944 /* This should not happen with any sane values */
3945 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3946 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3947 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3948 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3949
3950 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3951 clock,
e615efe4
ED		 3952 auxdiv,
3953 divsel,
3954 phasedir,
3955 phaseinc);
3956
3957 /* Program SSCDIVINTPHASE6 */
988d6ee8 3958 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3959 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3960 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3961 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3962 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3963 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3964 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3965 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3966
3967 /* Program SSCAUXDIV */
988d6ee8 3968 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3969 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3970 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3971 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3972
3973 /* Enable modulator and associated divider */
988d6ee8 3974 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3975 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3976 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3977
3978 /* Wait for initialization time */
3979 udelay(24);
3980
3981 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 3982
a580516d 3983 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 3984}
3985
275f01b2
DV		 3986static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3987 enum pipe pch_transcoder)
3988{
3989 struct drm_device *dev = crtc->base.dev;
3990 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3991 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3992
3993 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3994 I915_READ(HTOTAL(cpu_transcoder)));
3995 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3996 I915_READ(HBLANK(cpu_transcoder)));
3997 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3998 I915_READ(HSYNC(cpu_transcoder)));
3999
4000 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4001 I915_READ(VTOTAL(cpu_transcoder)));
4002 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4003 I915_READ(VBLANK(cpu_transcoder)));
4004 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4005 I915_READ(VSYNC(cpu_transcoder)));
4006 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4007 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4008}
4009
003632d9 4010static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4011{
4012 struct drm_i915_private *dev_priv = dev->dev_private;
4013 uint32_t temp;
4014
4015 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4016 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4017 return;
4018
4019 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4020 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4021
003632d9
ACO		 4022 temp &= ~FDI_BC_BIFURCATION_SELECT;
4023 if (enable)
4024 temp |= FDI_BC_BIFURCATION_SELECT;
4025
4026 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4027 I915_WRITE(SOUTH_CHICKEN1, temp);
4028 POSTING_READ(SOUTH_CHICKEN1);
4029}
4030
4031static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4032{
4033 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4034
4035 switch (intel_crtc->pipe) {
4036 case PIPE_A:
4037 break;
4038 case PIPE_B:
6e3c9717 4039 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4040 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4041 else
003632d9 4042 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4043
4044 break;
4045 case PIPE_C:
003632d9 4046 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4047
4048 break;
4049 default:
4050 BUG();
4051 }
4052}
4053
f67a559d
JB		 4054/*
4055 * Enable PCH resources required for PCH ports:
4056 * - PCH PLLs
4057 * - FDI training & RX/TX
4058 * - update transcoder timings
4059 * - DP transcoding bits
4060 * - transcoder
4061 */
4062static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4063{
4064 struct drm_device *dev = crtc->dev;
4065 struct drm_i915_private *dev_priv = dev->dev_private;
4066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4067 int pipe = intel_crtc->pipe;
ee7b9f93 4068 u32 reg, temp;
2c07245f 4069
ab9412ba 4070 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4071
1fbc0d78
DV		 4072 if (IS_IVYBRIDGE(dev))
4073 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4074
cd986abb
DV		 4075 /* Write the TU size bits before fdi link training, so that error
4076 * detection works. */
4077 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4078 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4079
c98e9dcf 4080 /* For PCH output, training FDI link */
674cf967 4081 dev_priv->display.fdi_link_train(crtc);
2c07245f 4082
3ad8a208
DV		 4083 /* We need to program the right clock selection before writing the pixel
4084 * mutliplier into the DPLL. */
303b81e0 4085 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4086 u32 sel;
4b645f14 4087
c98e9dcf 4088 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4089 temp |= TRANS_DPLL_ENABLE(pipe);
4090 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4091 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4092 temp |= sel;
4093 else
4094 temp &= ~sel;
c98e9dcf 4095 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4096 }
5eddb70b 4097
3ad8a208
DV		 4098 /* XXX: pch pll's can be enabled any time before we enable the PCH
4099 * transcoder, and we actually should do this to not upset any PCH
4100 * transcoder that already use the clock when we share it.
4101 *
4102 * Note that enable_shared_dpll tries to do the right thing, but
4103 * get_shared_dpll unconditionally resets the pll - we need that to have
4104 * the right LVDS enable sequence. */
85b3894f 4105 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4106
d9b6cb56
JB		 4107 /* set transcoder timing, panel must allow it */
4108 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4109 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4110
303b81e0 4111 intel_fdi_normal_train(crtc);
5e84e1a4 4112
c98e9dcf 4113 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4114 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4115 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4116 reg = TRANS_DP_CTL(pipe);
4117 temp = I915_READ(reg);
4118 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4119 TRANS_DP_SYNC_MASK |
4120 TRANS_DP_BPC_MASK);
e3ef4479 4121 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4122 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4123
4124 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4125 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4126 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4127 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4128
4129 switch (intel_trans_dp_port_sel(crtc)) {
4130 case PCH_DP_B:
5eddb70b 4131 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4132 break;
4133 case PCH_DP_C:
5eddb70b 4134 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4135 break;
4136 case PCH_DP_D:
5eddb70b 4137 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4138 break;
4139 default:
e95d41e1 4140 BUG();
32f9d658 4141 }
2c07245f 4142
5eddb70b 4143 I915_WRITE(reg, temp);
6be4a607 4144 }
b52eb4dc 4145
b8a4f404 4146 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4147}
4148
1507e5bd
PZ		 4149static void lpt_pch_enable(struct drm_crtc *crtc)
4150{
4151 struct drm_device *dev = crtc->dev;
4152 struct drm_i915_private *dev_priv = dev->dev_private;
4153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4154 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4155
ab9412ba 4156 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4157
8c52b5e8 4158 lpt_program_iclkip(crtc);
1507e5bd 4159
0540e488 4160 /* Set transcoder timing. */
275f01b2 4161 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4162
937bb610 4163 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4164}
4165
190f68c5
ACO		 4166struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4167 struct intel_crtc_state *crtc_state)
ee7b9f93 4168{
e2b78267 4169 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4170 struct intel_shared_dpll *pll;
de419ab6 4171 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4172 enum intel_dpll_id i;
ee7b9f93 4173
de419ab6
ML		 4174 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4175
98b6bd99
DV		 4176 if (HAS_PCH_IBX(dev_priv->dev)) {
4177 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4178 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4179 pll = &dev_priv->shared_dplls[i];
98b6bd99 4180
46edb027
DV		 4181 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4182 crtc->base.base.id, pll->name);
98b6bd99 4183
de419ab6 4184 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4185
98b6bd99
DV		 4186 goto found;
4187 }
4188
bcddf610
S		 4189 if (IS_BROXTON(dev_priv->dev)) {
4190 /* PLL is attached to port in bxt */
4191 struct intel_encoder *encoder;
4192 struct intel_digital_port *intel_dig_port;
4193
4194 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4195 if (WARN_ON(!encoder))
4196 return NULL;
4197
4198 intel_dig_port = enc_to_dig_port(&encoder->base);
4199 /* 1:1 mapping between ports and PLLs */
4200 i = (enum intel_dpll_id)intel_dig_port->port;
4201 pll = &dev_priv->shared_dplls[i];
4202 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4203 crtc->base.base.id, pll->name);
de419ab6 4204 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4205
4206 goto found;
4207 }
4208
e72f9fbf
DV		 4209 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4210 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4211
4212 /* Only want to check enabled timings first */
de419ab6 4213 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4214 continue;
4215
190f68c5 4216 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4217 &shared_dpll[i].hw_state,
4218 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4219 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4220 crtc->base.base.id, pll->name,
de419ab6 4221 shared_dpll[i].crtc_mask,
8bd31e67 4222 pll->active);
ee7b9f93
JB		 4223 goto found;
4224 }
4225 }
4226
4227 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4228 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4229 pll = &dev_priv->shared_dplls[i];
de419ab6 4230 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4231 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4232 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4233 goto found;
4234 }
4235 }
4236
4237 return NULL;
4238
4239found:
de419ab6
ML		 4240 if (shared_dpll[i].crtc_mask == 0)
4241 shared_dpll[i].hw_state =
4242 crtc_state->dpll_hw_state;
f2a69f44 4243
190f68c5 4244 crtc_state->shared_dpll = i;
46edb027
DV		 4245 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4246 pipe_name(crtc->pipe));
ee7b9f93 4247
de419ab6 4248 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4249
ee7b9f93
JB		 4250 return pll;
4251}
4252
de419ab6 4253static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4254{
de419ab6
ML		 4255 struct drm_i915_private *dev_priv = to_i915(state->dev);
4256 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4257 struct intel_shared_dpll *pll;
4258 enum intel_dpll_id i;
4259
de419ab6
ML		 4260 if (!to_intel_atomic_state(state)->dpll_set)
4261 return;
8bd31e67 4262
de419ab6 4263 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4264 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4265 pll = &dev_priv->shared_dplls[i];
de419ab6 4266 pll->config = shared_dpll[i];
8bd31e67
ACO		 4267 }
4268}
4269
a1520318 4270static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4271{
4272 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4273 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4274 u32 temp;
4275
4276 temp = I915_READ(dslreg);
4277 udelay(500);
4278 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4279 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4280 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4281 }
4282}
4283
86adf9d7
ML		 4284static int
4285skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4286 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4287 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4288{
86adf9d7
ML		 4289 struct intel_crtc_scaler_state *scaler_state =
4290 &crtc_state->scaler_state;
4291 struct intel_crtc *intel_crtc =
4292 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4293 int need_scaling;
6156a456
CK		 4294
4295 need_scaling = intel_rotation_90_or_270(rotation) ?
4296 (src_h != dst_w || src_w != dst_h):
4297 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4298
4299 /*
4300 * if plane is being disabled or scaler is no more required or force detach
4301 * - free scaler binded to this plane/crtc
4302 * - in order to do this, update crtc->scaler_usage
4303 *
4304 * Here scaler state in crtc_state is set free so that
4305 * scaler can be assigned to other user. Actual register
4306 * update to free the scaler is done in plane/panel-fit programming.
4307 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4308 */
86adf9d7 4309 if (force_detach || !need_scaling) {
a1b2278e 4310 if (*scaler_id >= 0) {
86adf9d7 4311 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4312 scaler_state->scalers[*scaler_id].in_use = 0;
4313
86adf9d7
ML		 4314 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4315 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4316 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4317 scaler_state->scaler_users);
4318 *scaler_id = -1;
4319 }
4320 return 0;
4321 }
4322
4323 /* range checks */
4324 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4325 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4326
4327 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4328 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4329 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4330 "size is out of scaler range\n",
86adf9d7 4331 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4332 return -EINVAL;
4333 }
4334
86adf9d7
ML		 4335 /* mark this plane as a scaler user in crtc_state */
4336 scaler_state->scaler_users |= (1 << scaler_user);
4337 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4338 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4339 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4340 scaler_state->scaler_users);
4341
4342 return 0;
4343}
4344
4345/**
4346 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4347 *
4348 * @state: crtc's scaler state
4349 * @force_detach: whether to forcibly disable scaler
4350 *
4351 * Return
4352 * 0 - scaler_usage updated successfully
4353 * error - requested scaling cannot be supported or other error condition
4354 */
4355int skl_update_scaler_crtc(struct intel_crtc_state *state, int force_detach)
4356{
4357 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4358 struct drm_display_mode *adjusted_mode =
4359 &state->base.adjusted_mode;
4360
4361 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4362 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4363
4364 return skl_update_scaler(state, force_detach, SKL_CRTC_INDEX,
4365 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4366 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4367 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4368}
4369
4370/**
4371 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4372 *
4373 * @state: crtc's scaler state
86adf9d7
ML		 4374 * @plane_state: atomic plane state to update
4375 *
4376 * Return
4377 * 0 - scaler_usage updated successfully
4378 * error - requested scaling cannot be supported or other error condition
4379 */
da20eabd
ML		 4380static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4381 struct intel_plane_state *plane_state)
86adf9d7
ML		 4382{
4383
4384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4385 struct intel_plane *intel_plane =
4386 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4387 struct drm_framebuffer *fb = plane_state->base.fb;
4388 int ret;
4389
4390 bool force_detach = !fb || !plane_state->visible;
4391
4392 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4393 intel_plane->base.base.id, intel_crtc->pipe,
4394 drm_plane_index(&intel_plane->base));
4395
4396 ret = skl_update_scaler(crtc_state, force_detach,
4397 drm_plane_index(&intel_plane->base),
4398 &plane_state->scaler_id,
4399 plane_state->base.rotation,
4400 drm_rect_width(&plane_state->src) >> 16,
4401 drm_rect_height(&plane_state->src) >> 16,
4402 drm_rect_width(&plane_state->dst),
4403 drm_rect_height(&plane_state->dst));
4404
4405 if (ret || plane_state->scaler_id < 0)
4406 return ret;
4407
a1b2278e 4408 /* check colorkey */
818ed961 4409 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4410 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4411 intel_plane->base.base.id);
a1b2278e
CK		 4412 return -EINVAL;
4413 }
4414
4415 /* Check src format */
86adf9d7
ML		 4416 switch (fb->pixel_format) {
4417 case DRM_FORMAT_RGB565:
4418 case DRM_FORMAT_XBGR8888:
4419 case DRM_FORMAT_XRGB8888:
4420 case DRM_FORMAT_ABGR8888:
4421 case DRM_FORMAT_ARGB8888:
4422 case DRM_FORMAT_XRGB2101010:
4423 case DRM_FORMAT_XBGR2101010:
4424 case DRM_FORMAT_YUYV:
4425 case DRM_FORMAT_YVYU:
4426 case DRM_FORMAT_UYVY:
4427 case DRM_FORMAT_VYUY:
4428 break;
4429 default:
4430 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4431 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4432 return -EINVAL;
a1b2278e
CK		 4433 }
4434
a1b2278e
CK		 4435 return 0;
4436}
4437
4438static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4439{
4440 struct drm_device *dev = crtc->base.dev;
4441 struct drm_i915_private *dev_priv = dev->dev_private;
4442 int pipe = crtc->pipe;
a1b2278e
CK		 4443 struct intel_crtc_scaler_state *scaler_state =
4444 &crtc->config->scaler_state;
4445
4446 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4447
4448 /* To update pfit, first update scaler state */
86adf9d7 4449 skl_update_scaler_crtc(crtc->config, !enable);
a1b2278e
CK		 4450 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4451 skl_detach_scalers(crtc);
4452 if (!enable)
4453 return;
bd2e244f 4454
6e3c9717 4455 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4456 int id;
4457
4458 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4459 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4460 return;
4461 }
4462
4463 id = scaler_state->scaler_id;
4464 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4465 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4466 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4467 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4468
4469 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4470 }
4471}
4472
b074cec8
JB		 4473static void ironlake_pfit_enable(struct intel_crtc *crtc)
4474{
4475 struct drm_device *dev = crtc->base.dev;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477 int pipe = crtc->pipe;
4478
6e3c9717 4479 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4480 /* Force use of hard-coded filter coefficients
4481 * as some pre-programmed values are broken,
4482 * e.g. x201.
4483 */
4484 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4485 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4486 PF_PIPE_SEL_IVB(pipe));
4487 else
4488 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4489 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4490 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4491 }
4492}
4493
20bc8673 4494void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4495{
cea165c3
VS		 4496 struct drm_device *dev = crtc->base.dev;
4497 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4498
6e3c9717 4499 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4500 return;
4501
cea165c3
VS		 4502 /* We can only enable IPS after we enable a plane and wait for a vblank */
4503 intel_wait_for_vblank(dev, crtc->pipe);
4504
d77e4531 4505 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4506 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4507 mutex_lock(&dev_priv->rps.hw_lock);
4508 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4509 mutex_unlock(&dev_priv->rps.hw_lock);
4510 /* Quoting Art Runyan: "its not safe to expect any particular
4511 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4512 * mailbox." Moreover, the mailbox may return a bogus state,
4513 * so we need to just enable it and continue on.
2a114cc1
BW		 4514 */
4515 } else {
4516 I915_WRITE(IPS_CTL, IPS_ENABLE);
4517 /* The bit only becomes 1 in the next vblank, so this wait here
4518 * is essentially intel_wait_for_vblank. If we don't have this
4519 * and don't wait for vblanks until the end of crtc_enable, then
4520 * the HW state readout code will complain that the expected
4521 * IPS_CTL value is not the one we read. */
4522 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4523 DRM_ERROR("Timed out waiting for IPS enable\n");
4524 }
d77e4531
PZ		 4525}
4526
20bc8673 4527void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4528{
4529 struct drm_device *dev = crtc->base.dev;
4530 struct drm_i915_private *dev_priv = dev->dev_private;
4531
6e3c9717 4532 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4533 return;
4534
4535 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4536 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4537 mutex_lock(&dev_priv->rps.hw_lock);
4538 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4539 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4540 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4541 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4542 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4543 } else {
2a114cc1 4544 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4545 POSTING_READ(IPS_CTL);
4546 }
d77e4531
PZ		 4547
4548 /* We need to wait for a vblank before we can disable the plane. */
4549 intel_wait_for_vblank(dev, crtc->pipe);
4550}
4551
4552/** Loads the palette/gamma unit for the CRTC with the prepared values */
4553static void intel_crtc_load_lut(struct drm_crtc *crtc)
4554{
4555 struct drm_device *dev = crtc->dev;
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4558 enum pipe pipe = intel_crtc->pipe;
4559 int palreg = PALETTE(pipe);
4560 int i;
4561 bool reenable_ips = false;
4562
4563 /* The clocks have to be on to load the palette. */
53d9f4e9 4564 if (!crtc->state->active)
d77e4531
PZ		 4565 return;
4566
50360403 4567 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4568 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4569 assert_dsi_pll_enabled(dev_priv);
4570 else
4571 assert_pll_enabled(dev_priv, pipe);
4572 }
4573
4574 /* use legacy palette for Ironlake */
7a1db49a 4575 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4576 palreg = LGC_PALETTE(pipe);
4577
4578 /* Workaround : Do not read or write the pipe palette/gamma data while
4579 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4580 */
6e3c9717 4581 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4582 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4583 GAMMA_MODE_MODE_SPLIT)) {
4584 hsw_disable_ips(intel_crtc);
4585 reenable_ips = true;
4586 }
4587
4588 for (i = 0; i < 256; i++) {
4589 I915_WRITE(palreg + 4 * i,
4590 (intel_crtc->lut_r[i] << 16) |
4591 (intel_crtc->lut_g[i] << 8) |
4592 intel_crtc->lut_b[i]);
4593 }
4594
4595 if (reenable_ips)
4596 hsw_enable_ips(intel_crtc);
4597}
4598
7cac945f 4599static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4600{
7cac945f 4601 if (intel_crtc->overlay) {
d3eedb1a
VS		 4602 struct drm_device *dev = intel_crtc->base.dev;
4603 struct drm_i915_private *dev_priv = dev->dev_private;
4604
4605 mutex_lock(&dev->struct_mutex);
4606 dev_priv->mm.interruptible = false;
4607 (void) intel_overlay_switch_off(intel_crtc->overlay);
4608 dev_priv->mm.interruptible = true;
4609 mutex_unlock(&dev->struct_mutex);
4610 }
4611
4612 /* Let userspace switch the overlay on again. In most cases userspace
4613 * has to recompute where to put it anyway.
4614 */
4615}
4616
87d4300a
ML		 4617/**
4618 * intel_post_enable_primary - Perform operations after enabling primary plane
4619 * @crtc: the CRTC whose primary plane was just enabled
4620 *
4621 * Performs potentially sleeping operations that must be done after the primary
4622 * plane is enabled, such as updating FBC and IPS. Note that this may be
4623 * called due to an explicit primary plane update, or due to an implicit
4624 * re-enable that is caused when a sprite plane is updated to no longer
4625 * completely hide the primary plane.
4626 */
4627static void
4628intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4629{
4630 struct drm_device *dev = crtc->dev;
87d4300a 4631 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4632 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4633 int pipe = intel_crtc->pipe;
a5c4d7bc 4634
87d4300a
ML		 4635 /*
4636 * BDW signals flip done immediately if the plane
4637 * is disabled, even if the plane enable is already
4638 * armed to occur at the next vblank :(
4639 */
4640 if (IS_BROADWELL(dev))
4641 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4642
87d4300a
ML		 4643 /*
4644 * FIXME IPS should be fine as long as one plane is
4645 * enabled, but in practice it seems to have problems
4646 * when going from primary only to sprite only and vice
4647 * versa.
4648 */
a5c4d7bc
VS		 4649 hsw_enable_ips(intel_crtc);
4650
f99d7069 4651 /*
87d4300a
ML		 4652 * Gen2 reports pipe underruns whenever all planes are disabled.
4653 * So don't enable underrun reporting before at least some planes
4654 * are enabled.
4655 * FIXME: Need to fix the logic to work when we turn off all planes
4656 * but leave the pipe running.
f99d7069 4657 */
87d4300a
ML		 4658 if (IS_GEN2(dev))
4659 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4660
4661 /* Underruns don't raise interrupts, so check manually. */
4662 if (HAS_GMCH_DISPLAY(dev))
4663 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4664}
4665
87d4300a
ML		 4666/**
4667 * intel_pre_disable_primary - Perform operations before disabling primary plane
4668 * @crtc: the CRTC whose primary plane is to be disabled
4669 *
4670 * Performs potentially sleeping operations that must be done before the
4671 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4672 * be called due to an explicit primary plane update, or due to an implicit
4673 * disable that is caused when a sprite plane completely hides the primary
4674 * plane.
4675 */
4676static void
4677intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4678{
4679 struct drm_device *dev = crtc->dev;
4680 struct drm_i915_private *dev_priv = dev->dev_private;
4681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4682 int pipe = intel_crtc->pipe;
a5c4d7bc 4683
87d4300a
ML		 4684 /*
4685 * Gen2 reports pipe underruns whenever all planes are disabled.
4686 * So diasble underrun reporting before all the planes get disabled.
4687 * FIXME: Need to fix the logic to work when we turn off all planes
4688 * but leave the pipe running.
4689 */
4690 if (IS_GEN2(dev))
4691 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4692
87d4300a
ML		 4693 /*
4694 * Vblank time updates from the shadow to live plane control register
4695 * are blocked if the memory self-refresh mode is active at that
4696 * moment. So to make sure the plane gets truly disabled, disable
4697 * first the self-refresh mode. The self-refresh enable bit in turn
4698 * will be checked/applied by the HW only at the next frame start
4699 * event which is after the vblank start event, so we need to have a
4700 * wait-for-vblank between disabling the plane and the pipe.
4701 */
4702 if (HAS_GMCH_DISPLAY(dev))
4703 intel_set_memory_cxsr(dev_priv, false);
4704
87d4300a
ML		 4705 /*
4706 * FIXME IPS should be fine as long as one plane is
4707 * enabled, but in practice it seems to have problems
4708 * when going from primary only to sprite only and vice
4709 * versa.
4710 */
a5c4d7bc 4711 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4712}
4713
ac21b225
ML		 4714static void intel_post_plane_update(struct intel_crtc *crtc)
4715{
4716 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4717 struct drm_device *dev = crtc->base.dev;
4718 struct drm_plane *plane;
4719
4720 if (atomic->wait_vblank)
4721 intel_wait_for_vblank(dev, crtc->pipe);
4722
4723 intel_frontbuffer_flip(dev, atomic->fb_bits);
4724
f015c551
VS		 4725 if (crtc->atomic.update_wm_post)
4726 intel_update_watermarks(&crtc->base);
4727
ac21b225
ML		 4728 if (atomic->update_fbc) {
4729 mutex_lock(&dev->struct_mutex);
4730 intel_fbc_update(dev);
4731 mutex_unlock(&dev->struct_mutex);
4732 }
4733
4734 if (atomic->post_enable_primary)
4735 intel_post_enable_primary(&crtc->base);
4736
4737 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4738 intel_update_sprite_watermarks(plane, &crtc->base,
4739 0, 0, 0, false, false);
4740
4741 memset(atomic, 0, sizeof(*atomic));
4742}
4743
4744static void intel_pre_plane_update(struct intel_crtc *crtc)
4745{
4746 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4747 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4748 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4749 struct drm_plane *p;
4750
4751 /* Track fb's for any planes being disabled */
ac21b225
ML		 4752 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4753 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4754
4755 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4756 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4757 plane->frontbuffer_bit);
ac21b225
ML		 4758 mutex_unlock(&dev->struct_mutex);
4759 }
4760
4761 if (atomic->wait_for_flips)
4762 intel_crtc_wait_for_pending_flips(&crtc->base);
4763
eddfcbcd
ML		 4764 if (atomic->disable_fbc &&
4765 dev_priv->fbc.crtc == crtc) {
4766 mutex_lock(&dev->struct_mutex);
4767 if (dev_priv->fbc.crtc == crtc)
4768 intel_fbc_disable(dev);
4769 mutex_unlock(&dev->struct_mutex);
4770 }
ac21b225 4771
066cf55b
RV		 4772 if (crtc->atomic.disable_ips)
4773 hsw_disable_ips(crtc);
4774
ac21b225
ML		 4775 if (atomic->pre_disable_primary)
4776 intel_pre_disable_primary(&crtc->base);
4777}
4778
d032ffa0 4779static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4780{
4781 struct drm_device *dev = crtc->dev;
4782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4783 struct drm_plane *p;
87d4300a
ML		 4784 int pipe = intel_crtc->pipe;
4785
7cac945f 4786 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4787
d032ffa0
ML		 4788 drm_for_each_plane_mask(p, dev, plane_mask)
4789 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4790
f99d7069
DV		 4791 /*
4792 * FIXME: Once we grow proper nuclear flip support out of this we need
4793 * to compute the mask of flip planes precisely. For the time being
4794 * consider this a flip to a NULL plane.
4795 */
4796 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4797}
4798
f67a559d
JB		 4799static void ironlake_crtc_enable(struct drm_crtc *crtc)
4800{
4801 struct drm_device *dev = crtc->dev;
4802 struct drm_i915_private *dev_priv = dev->dev_private;
4803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4804 struct intel_encoder *encoder;
f67a559d 4805 int pipe = intel_crtc->pipe;
f67a559d 4806
53d9f4e9 4807 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4808 return;
4809
6e3c9717 4810 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4811 intel_prepare_shared_dpll(intel_crtc);
4812
6e3c9717 4813 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4814 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4815
4816 intel_set_pipe_timings(intel_crtc);
4817
6e3c9717 4818 if (intel_crtc->config->has_pch_encoder) {
29407aab 4819 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4820 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4821 }
4822
4823 ironlake_set_pipeconf(crtc);
4824
f67a559d 4825 intel_crtc->active = true;
8664281b 4826
a72e4c9f
DV		 4827 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4828 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4829
f6736a1a 4830 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4831 if (encoder->pre_enable)
4832 encoder->pre_enable(encoder);
f67a559d 4833
6e3c9717 4834 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4835 /* Note: FDI PLL enabling _must_ be done before we enable the
4836 * cpu pipes, hence this is separate from all the other fdi/pch
4837 * enabling. */
88cefb6c 4838 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4839 } else {
4840 assert_fdi_tx_disabled(dev_priv, pipe);
4841 assert_fdi_rx_disabled(dev_priv, pipe);
4842 }
f67a559d 4843
b074cec8 4844 ironlake_pfit_enable(intel_crtc);
f67a559d 4845
9c54c0dd
JB		 4846 /*
4847 * On ILK+ LUT must be loaded before the pipe is running but with
4848 * clocks enabled
4849 */
4850 intel_crtc_load_lut(crtc);
4851
f37fcc2a 4852 intel_update_watermarks(crtc);
e1fdc473 4853 intel_enable_pipe(intel_crtc);
f67a559d 4854
6e3c9717 4855 if (intel_crtc->config->has_pch_encoder)
f67a559d 4856 ironlake_pch_enable(crtc);
c98e9dcf 4857
f9b61ff6
DV		 4858 assert_vblank_disabled(crtc);
4859 drm_crtc_vblank_on(crtc);
4860
fa5c73b1
DV		 4861 for_each_encoder_on_crtc(dev, crtc, encoder)
4862 encoder->enable(encoder);
61b77ddd
DV		 4863
4864 if (HAS_PCH_CPT(dev))
a1520318 4865 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4866}
4867
42db64ef
PZ		 4868/* IPS only exists on ULT machines and is tied to pipe A. */
4869static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4870{
f5adf94e 4871 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4872}
4873
4f771f10
PZ		 4874static void haswell_crtc_enable(struct drm_crtc *crtc)
4875{
4876 struct drm_device *dev = crtc->dev;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879 struct intel_encoder *encoder;
99d736a2
ML		 4880 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4881 struct intel_crtc_state *pipe_config =
4882 to_intel_crtc_state(crtc->state);
4f771f10 4883
53d9f4e9 4884 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4885 return;
4886
df8ad70c
DV		 4887 if (intel_crtc_to_shared_dpll(intel_crtc))
4888 intel_enable_shared_dpll(intel_crtc);
4889
6e3c9717 4890 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4891 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4892
4893 intel_set_pipe_timings(intel_crtc);
4894
6e3c9717
ACO		 4895 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4896 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4897 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4898 }
4899
6e3c9717 4900 if (intel_crtc->config->has_pch_encoder) {
229fca97 4901 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4902 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4903 }
4904
4905 haswell_set_pipeconf(crtc);
4906
4907 intel_set_pipe_csc(crtc);
4908
4f771f10 4909 intel_crtc->active = true;
8664281b 4910
a72e4c9f 4911 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4912 for_each_encoder_on_crtc(dev, crtc, encoder)
4913 if (encoder->pre_enable)
4914 encoder->pre_enable(encoder);
4915
6e3c9717 4916 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4917 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4918 true);
4fe9467d
ID		 4919 dev_priv->display.fdi_link_train(crtc);
4920 }
4921
1f544388 4922 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4923
ff6d9f55 4924 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4925 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4926 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4927 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4928 else
4929 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4930
4931 /*
4932 * On ILK+ LUT must be loaded before the pipe is running but with
4933 * clocks enabled
4934 */
4935 intel_crtc_load_lut(crtc);
4936
1f544388 4937 intel_ddi_set_pipe_settings(crtc);
8228c251 4938 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4939
f37fcc2a 4940 intel_update_watermarks(crtc);
e1fdc473 4941 intel_enable_pipe(intel_crtc);
42db64ef 4942
6e3c9717 4943 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4944 lpt_pch_enable(crtc);
4f771f10 4945
6e3c9717 4946 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4947 intel_ddi_set_vc_payload_alloc(crtc, true);
4948
f9b61ff6
DV		 4949 assert_vblank_disabled(crtc);
4950 drm_crtc_vblank_on(crtc);
4951
8807e55b 4952 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4953 encoder->enable(encoder);
8807e55b
JN		 4954 intel_opregion_notify_encoder(encoder, true);
4955 }
4f771f10 4956
e4916946
PZ		 4957 /* If we change the relative order between pipe/planes enabling, we need
4958 * to change the workaround. */
99d736a2
ML		 4959 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4960 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4961 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4962 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4963 }
4f771f10
PZ		 4964}
4965
3f8dce3a
DV		 4966static void ironlake_pfit_disable(struct intel_crtc *crtc)
4967{
4968 struct drm_device *dev = crtc->base.dev;
4969 struct drm_i915_private *dev_priv = dev->dev_private;
4970 int pipe = crtc->pipe;
4971
4972 /* To avoid upsetting the power well on haswell only disable the pfit if
4973 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4974 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4975 I915_WRITE(PF_CTL(pipe), 0);
4976 I915_WRITE(PF_WIN_POS(pipe), 0);
4977 I915_WRITE(PF_WIN_SZ(pipe), 0);
4978 }
4979}
4980
6be4a607
JB		 4981static void ironlake_crtc_disable(struct drm_crtc *crtc)
4982{
4983 struct drm_device *dev = crtc->dev;
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4986 struct intel_encoder *encoder;
6be4a607 4987 int pipe = intel_crtc->pipe;
5eddb70b 4988 u32 reg, temp;
b52eb4dc 4989
ea9d758d
DV		 4990 for_each_encoder_on_crtc(dev, crtc, encoder)
4991 encoder->disable(encoder);
4992
f9b61ff6
DV		 4993 drm_crtc_vblank_off(crtc);
4994 assert_vblank_disabled(crtc);
4995
6e3c9717 4996 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4997 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4998
575f7ab7 4999 intel_disable_pipe(intel_crtc);
32f9d658 5000
3f8dce3a 5001 ironlake_pfit_disable(intel_crtc);
2c07245f 5002
5a74f70a
VS		 5003 if (intel_crtc->config->has_pch_encoder)
5004 ironlake_fdi_disable(crtc);
5005
bf49ec8c
DV		 5006 for_each_encoder_on_crtc(dev, crtc, encoder)
5007 if (encoder->post_disable)
5008 encoder->post_disable(encoder);
2c07245f 5009
6e3c9717 5010 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5011 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5012
d925c59a
DV		 5013 if (HAS_PCH_CPT(dev)) {
5014 /* disable TRANS_DP_CTL */
5015 reg = TRANS_DP_CTL(pipe);
5016 temp = I915_READ(reg);
5017 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5018 TRANS_DP_PORT_SEL_MASK);
5019 temp |= TRANS_DP_PORT_SEL_NONE;
5020 I915_WRITE(reg, temp);
5021
5022 /* disable DPLL_SEL */
5023 temp = I915_READ(PCH_DPLL_SEL);
11887397 5024 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5025 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5026 }
e3421a18 5027
d925c59a
DV		 5028 ironlake_fdi_pll_disable(intel_crtc);
5029 }
6be4a607 5030}
1b3c7a47 5031
4f771f10 5032static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5033{
4f771f10
PZ		 5034 struct drm_device *dev = crtc->dev;
5035 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5037 struct intel_encoder *encoder;
6e3c9717 5038 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5039
8807e55b
JN		 5040 for_each_encoder_on_crtc(dev, crtc, encoder) {
5041 intel_opregion_notify_encoder(encoder, false);
4f771f10 5042 encoder->disable(encoder);
8807e55b 5043 }
4f771f10 5044
f9b61ff6
DV		 5045 drm_crtc_vblank_off(crtc);
5046 assert_vblank_disabled(crtc);
5047
6e3c9717 5048 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5049 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5050 false);
575f7ab7 5051 intel_disable_pipe(intel_crtc);
4f771f10 5052
6e3c9717 5053 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5054 intel_ddi_set_vc_payload_alloc(crtc, false);
5055
ad80a810 5056 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5057
ff6d9f55 5058 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5059 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5060 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5061 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5062 else
5063 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5064
1f544388 5065 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5066
6e3c9717 5067 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5068 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5069 intel_ddi_fdi_disable(crtc);
83616634 5070 }
4f771f10 5071
97b040aa
ID		 5072 for_each_encoder_on_crtc(dev, crtc, encoder)
5073 if (encoder->post_disable)
5074 encoder->post_disable(encoder);
4f771f10
PZ		 5075}
5076
2dd24552
JB		 5077static void i9xx_pfit_enable(struct intel_crtc *crtc)
5078{
5079 struct drm_device *dev = crtc->base.dev;
5080 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5081 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5082
681a8504 5083 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5084 return;
5085
2dd24552 5086 /*
c0b03411
DV		 5087 * The panel fitter should only be adjusted whilst the pipe is disabled,
5088 * according to register description and PRM.
2dd24552 5089 */
c0b03411
DV		 5090 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5091 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5092
b074cec8
JB		 5093 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5094 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5095
5096 /* Border color in case we don't scale up to the full screen. Black by
5097 * default, change to something else for debugging. */
5098 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5099}
5100
d05410f9
DA		 5101static enum intel_display_power_domain port_to_power_domain(enum port port)
5102{
5103 switch (port) {
5104 case PORT_A:
5105 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5106 case PORT_B:
5107 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5108 case PORT_C:
5109 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5110 case PORT_D:
5111 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5112 default:
5113 WARN_ON_ONCE(1);
5114 return POWER_DOMAIN_PORT_OTHER;
5115 }
5116}
5117
77d22dca
ID		 5118#define for_each_power_domain(domain, mask) \
5119 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5120 if ((1 << (domain)) & (mask))
5121
319be8ae
ID		 5122enum intel_display_power_domain
5123intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5124{
5125 struct drm_device *dev = intel_encoder->base.dev;
5126 struct intel_digital_port *intel_dig_port;
5127
5128 switch (intel_encoder->type) {
5129 case INTEL_OUTPUT_UNKNOWN:
5130 /* Only DDI platforms should ever use this output type */
5131 WARN_ON_ONCE(!HAS_DDI(dev));
5132 case INTEL_OUTPUT_DISPLAYPORT:
5133 case INTEL_OUTPUT_HDMI:
5134 case INTEL_OUTPUT_EDP:
5135 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5136 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5137 case INTEL_OUTPUT_DP_MST:
5138 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5139 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5140 case INTEL_OUTPUT_ANALOG:
5141 return POWER_DOMAIN_PORT_CRT;
5142 case INTEL_OUTPUT_DSI:
5143 return POWER_DOMAIN_PORT_DSI;
5144 default:
5145 return POWER_DOMAIN_PORT_OTHER;
5146 }
5147}
5148
5149static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5150{
319be8ae
ID		 5151 struct drm_device *dev = crtc->dev;
5152 struct intel_encoder *intel_encoder;
5153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5154 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5155 unsigned long mask;
5156 enum transcoder transcoder;
5157
5158 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5159
5160 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5161 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5162 if (intel_crtc->config->pch_pfit.enabled ||
5163 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5164 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5165
319be8ae
ID		 5166 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5167 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5168
77d22dca
ID		 5169 return mask;
5170}
5171
679dacd4 5172static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5173{
679dacd4 5174 struct drm_device *dev = state->dev;
77d22dca
ID		 5175 struct drm_i915_private *dev_priv = dev->dev_private;
5176 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5177 struct intel_crtc *crtc;
5178
5179 /*
5180 * First get all needed power domains, then put all unneeded, to avoid
5181 * any unnecessary toggling of the power wells.
5182 */
d3fcc808 5183 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5184 enum intel_display_power_domain domain;
5185
83d65738 5186 if (!crtc->base.state->enable)
77d22dca
ID		 5187 continue;
5188
319be8ae 5189 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5190
5191 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5192 intel_display_power_get(dev_priv, domain);
5193 }
5194
27c329ed
ML		 5195 if (dev_priv->display.modeset_commit_cdclk) {
5196 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5197
5198 if (cdclk != dev_priv->cdclk_freq &&
5199 !WARN_ON(!state->allow_modeset))
5200 dev_priv->display.modeset_commit_cdclk(state);
5201 }
50f6e502 5202
d3fcc808 5203 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5204 enum intel_display_power_domain domain;
5205
5206 for_each_power_domain(domain, crtc->enabled_power_domains)
5207 intel_display_power_put(dev_priv, domain);
5208
5209 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5210 }
5211
5212 intel_display_set_init_power(dev_priv, false);
5213}
5214
560a7ae4
DL		 5215static void intel_update_max_cdclk(struct drm_device *dev)
5216{
5217 struct drm_i915_private *dev_priv = dev->dev_private;
5218
5219 if (IS_SKYLAKE(dev)) {
5220 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5221
5222 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5223 dev_priv->max_cdclk_freq = 675000;
5224 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5225 dev_priv->max_cdclk_freq = 540000;
5226 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5227 dev_priv->max_cdclk_freq = 450000;
5228 else
5229 dev_priv->max_cdclk_freq = 337500;
5230 } else if (IS_BROADWELL(dev)) {
5231 /*
5232 * FIXME with extra cooling we can allow
5233 * 540 MHz for ULX and 675 Mhz for ULT.
5234 * How can we know if extra cooling is
5235 * available? PCI ID, VTB, something else?
5236 */
5237 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5238 dev_priv->max_cdclk_freq = 450000;
5239 else if (IS_BDW_ULX(dev))
5240 dev_priv->max_cdclk_freq = 450000;
5241 else if (IS_BDW_ULT(dev))
5242 dev_priv->max_cdclk_freq = 540000;
5243 else
5244 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5245 } else if (IS_CHERRYVIEW(dev)) {
5246 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5247 } else if (IS_VALLEYVIEW(dev)) {
5248 dev_priv->max_cdclk_freq = 400000;
5249 } else {
5250 /* otherwise assume cdclk is fixed */
5251 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5252 }
5253
5254 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5255 dev_priv->max_cdclk_freq);
5256}
5257
5258static void intel_update_cdclk(struct drm_device *dev)
5259{
5260 struct drm_i915_private *dev_priv = dev->dev_private;
5261
5262 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5263 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5264 dev_priv->cdclk_freq);
5265
5266 /*
5267 * Program the gmbus_freq based on the cdclk frequency.
5268 * BSpec erroneously claims we should aim for 4MHz, but
5269 * in fact 1MHz is the correct frequency.
5270 */
5271 if (IS_VALLEYVIEW(dev)) {
5272 /*
5273 * Program the gmbus_freq based on the cdclk frequency.
5274 * BSpec erroneously claims we should aim for 4MHz, but
5275 * in fact 1MHz is the correct frequency.
5276 */
5277 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5278 }
5279
5280 if (dev_priv->max_cdclk_freq == 0)
5281 intel_update_max_cdclk(dev);
5282}
5283
70d0c574 5284static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5285{
5286 struct drm_i915_private *dev_priv = dev->dev_private;
5287 uint32_t divider;
5288 uint32_t ratio;
5289 uint32_t current_freq;
5290 int ret;
5291
5292 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5293 switch (frequency) {
5294 case 144000:
5295 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5296 ratio = BXT_DE_PLL_RATIO(60);
5297 break;
5298 case 288000:
5299 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5300 ratio = BXT_DE_PLL_RATIO(60);
5301 break;
5302 case 384000:
5303 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5304 ratio = BXT_DE_PLL_RATIO(60);
5305 break;
5306 case 576000:
5307 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5308 ratio = BXT_DE_PLL_RATIO(60);
5309 break;
5310 case 624000:
5311 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5312 ratio = BXT_DE_PLL_RATIO(65);
5313 break;
5314 case 19200:
5315 /*
5316 * Bypass frequency with DE PLL disabled. Init ratio, divider
5317 * to suppress GCC warning.
5318 */
5319 ratio = 0;
5320 divider = 0;
5321 break;
5322 default:
5323 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5324
5325 return;
5326 }
5327
5328 mutex_lock(&dev_priv->rps.hw_lock);
5329 /* Inform power controller of upcoming frequency change */
5330 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5331 0x80000000);
5332 mutex_unlock(&dev_priv->rps.hw_lock);
5333
5334 if (ret) {
5335 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5336 ret, frequency);
5337 return;
5338 }
5339
5340 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5341 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5342 current_freq = current_freq * 500 + 1000;
5343
5344 /*
5345 * DE PLL has to be disabled when
5346 * - setting to 19.2MHz (bypass, PLL isn't used)
5347 * - before setting to 624MHz (PLL needs toggling)
5348 * - before setting to any frequency from 624MHz (PLL needs toggling)
5349 */
5350 if (frequency == 19200 || frequency == 624000 ||
5351 current_freq == 624000) {
5352 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5353 /* Timeout 200us */
5354 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5355 1))
5356 DRM_ERROR("timout waiting for DE PLL unlock\n");
5357 }
5358
5359 if (frequency != 19200) {
5360 uint32_t val;
5361
5362 val = I915_READ(BXT_DE_PLL_CTL);
5363 val &= ~BXT_DE_PLL_RATIO_MASK;
5364 val |= ratio;
5365 I915_WRITE(BXT_DE_PLL_CTL, val);
5366
5367 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5368 /* Timeout 200us */
5369 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5370 DRM_ERROR("timeout waiting for DE PLL lock\n");
5371
5372 val = I915_READ(CDCLK_CTL);
5373 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5374 val |= divider;
5375 /*
5376 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5377 * enable otherwise.
5378 */
5379 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5380 if (frequency >= 500000)
5381 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5382
5383 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5384 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5385 val |= (frequency - 1000) / 500;
5386 I915_WRITE(CDCLK_CTL, val);
5387 }
5388
5389 mutex_lock(&dev_priv->rps.hw_lock);
5390 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5391 DIV_ROUND_UP(frequency, 25000));
5392 mutex_unlock(&dev_priv->rps.hw_lock);
5393
5394 if (ret) {
5395 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5396 ret, frequency);
5397 return;
5398 }
5399
a47871bd 5400 intel_update_cdclk(dev);
f8437dd1
VK		 5401}
5402
5403void broxton_init_cdclk(struct drm_device *dev)
5404{
5405 struct drm_i915_private *dev_priv = dev->dev_private;
5406 uint32_t val;
5407
5408 /*
5409 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5410 * or else the reset will hang because there is no PCH to respond.
5411 * Move the handshake programming to initialization sequence.
5412 * Previously was left up to BIOS.
5413 */
5414 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5415 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5416 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5417
5418 /* Enable PG1 for cdclk */
5419 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5420
5421 /* check if cd clock is enabled */
5422 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5423 DRM_DEBUG_KMS("Display already initialized\n");
5424 return;
5425 }
5426
5427 /*
5428 * FIXME:
5429 * - The initial CDCLK needs to be read from VBT.
5430 * Need to make this change after VBT has changes for BXT.
5431 * - check if setting the max (or any) cdclk freq is really necessary
5432 * here, it belongs to modeset time
5433 */
5434 broxton_set_cdclk(dev, 624000);
5435
5436 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5437 POSTING_READ(DBUF_CTL);
5438
f8437dd1
VK		 5439 udelay(10);
5440
5441 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5442 DRM_ERROR("DBuf power enable timeout!\n");
5443}
5444
5445void broxton_uninit_cdclk(struct drm_device *dev)
5446{
5447 struct drm_i915_private *dev_priv = dev->dev_private;
5448
5449 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5450 POSTING_READ(DBUF_CTL);
5451
f8437dd1
VK		 5452 udelay(10);
5453
5454 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5455 DRM_ERROR("DBuf power disable timeout!\n");
5456
5457 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5458 broxton_set_cdclk(dev, 19200);
5459
5460 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5461}
5462
5d96d8af
DL		 5463static const struct skl_cdclk_entry {
5464 unsigned int freq;
5465 unsigned int vco;
5466} skl_cdclk_frequencies[] = {
5467 { .freq = 308570, .vco = 8640 },
5468 { .freq = 337500, .vco = 8100 },
5469 { .freq = 432000, .vco = 8640 },
5470 { .freq = 450000, .vco = 8100 },
5471 { .freq = 540000, .vco = 8100 },
5472 { .freq = 617140, .vco = 8640 },
5473 { .freq = 675000, .vco = 8100 },
5474};
5475
5476static unsigned int skl_cdclk_decimal(unsigned int freq)
5477{
5478 return (freq - 1000) / 500;
5479}
5480
5481static unsigned int skl_cdclk_get_vco(unsigned int freq)
5482{
5483 unsigned int i;
5484
5485 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5486 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5487
5488 if (e->freq == freq)
5489 return e->vco;
5490 }
5491
5492 return 8100;
5493}
5494
5495static void
5496skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5497{
5498 unsigned int min_freq;
5499 u32 val;
5500
5501 /* select the minimum CDCLK before enabling DPLL 0 */
5502 val = I915_READ(CDCLK_CTL);
5503 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5504 val |= CDCLK_FREQ_337_308;
5505
5506 if (required_vco == 8640)
5507 min_freq = 308570;
5508 else
5509 min_freq = 337500;
5510
5511 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5512
5513 I915_WRITE(CDCLK_CTL, val);
5514 POSTING_READ(CDCLK_CTL);
5515
5516 /*
5517 * We always enable DPLL0 with the lowest link rate possible, but still
5518 * taking into account the VCO required to operate the eDP panel at the
5519 * desired frequency. The usual DP link rates operate with a VCO of
5520 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5521 * The modeset code is responsible for the selection of the exact link
5522 * rate later on, with the constraint of choosing a frequency that
5523 * works with required_vco.
5524 */
5525 val = I915_READ(DPLL_CTRL1);
5526
5527 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5528 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5529 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5530 if (required_vco == 8640)
5531 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5532 SKL_DPLL0);
5533 else
5534 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5535 SKL_DPLL0);
5536
5537 I915_WRITE(DPLL_CTRL1, val);
5538 POSTING_READ(DPLL_CTRL1);
5539
5540 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5541
5542 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5543 DRM_ERROR("DPLL0 not locked\n");
5544}
5545
5546static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5547{
5548 int ret;
5549 u32 val;
5550
5551 /* inform PCU we want to change CDCLK */
5552 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5553 mutex_lock(&dev_priv->rps.hw_lock);
5554 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5555 mutex_unlock(&dev_priv->rps.hw_lock);
5556
5557 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5558}
5559
5560static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5561{
5562 unsigned int i;
5563
5564 for (i = 0; i < 15; i++) {
5565 if (skl_cdclk_pcu_ready(dev_priv))
5566 return true;
5567 udelay(10);
5568 }
5569
5570 return false;
5571}
5572
5573static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5574{
560a7ae4 5575 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5576 u32 freq_select, pcu_ack;
5577
5578 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5579
5580 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5581 DRM_ERROR("failed to inform PCU about cdclk change\n");
5582 return;
5583 }
5584
5585 /* set CDCLK_CTL */
5586 switch(freq) {
5587 case 450000:
5588 case 432000:
5589 freq_select = CDCLK_FREQ_450_432;
5590 pcu_ack = 1;
5591 break;
5592 case 540000:
5593 freq_select = CDCLK_FREQ_540;
5594 pcu_ack = 2;
5595 break;
5596 case 308570:
5597 case 337500:
5598 default:
5599 freq_select = CDCLK_FREQ_337_308;
5600 pcu_ack = 0;
5601 break;
5602 case 617140:
5603 case 675000:
5604 freq_select = CDCLK_FREQ_675_617;
5605 pcu_ack = 3;
5606 break;
5607 }
5608
5609 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5610 POSTING_READ(CDCLK_CTL);
5611
5612 /* inform PCU of the change */
5613 mutex_lock(&dev_priv->rps.hw_lock);
5614 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5615 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5616
5617 intel_update_cdclk(dev);
5d96d8af
DL		 5618}
5619
5620void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5621{
5622 /* disable DBUF power */
5623 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5624 POSTING_READ(DBUF_CTL);
5625
5626 udelay(10);
5627
5628 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5629 DRM_ERROR("DBuf power disable timeout\n");
5630
5631 /* disable DPLL0 */
5632 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5633 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5634 DRM_ERROR("Couldn't disable DPLL0\n");
5635
5636 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5637}
5638
5639void skl_init_cdclk(struct drm_i915_private *dev_priv)
5640{
5641 u32 val;
5642 unsigned int required_vco;
5643
5644 /* enable PCH reset handshake */
5645 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5646 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5647
5648 /* enable PG1 and Misc I/O */
5649 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5650
5651 /* DPLL0 already enabed !? */
5652 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5653 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5654 return;
5655 }
5656
5657 /* enable DPLL0 */
5658 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5659 skl_dpll0_enable(dev_priv, required_vco);
5660
5661 /* set CDCLK to the frequency the BIOS chose */
5662 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5663
5664 /* enable DBUF power */
5665 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5666 POSTING_READ(DBUF_CTL);
5667
5668 udelay(10);
5669
5670 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5671 DRM_ERROR("DBuf power enable timeout\n");
5672}
5673
dfcab17e 5674/* returns HPLL frequency in kHz */
f8bf63fd 5675static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5676{
586f49dc 5677 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5678
586f49dc 5679 /* Obtain SKU information */
a580516d 5680 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5681 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5682 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5683 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5684
dfcab17e 5685 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5686}
5687
5688/* Adjust CDclk dividers to allow high res or save power if possible */
5689static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5690{
5691 struct drm_i915_private *dev_priv = dev->dev_private;
5692 u32 val, cmd;
5693
164dfd28
VK		 5694 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5695 != dev_priv->cdclk_freq);
d60c4473 5696
dfcab17e 5697 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5698 cmd = 2;
dfcab17e 5699 else if (cdclk == 266667)
30a970c6
JB		 5700 cmd = 1;
5701 else
5702 cmd = 0;
5703
5704 mutex_lock(&dev_priv->rps.hw_lock);
5705 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5706 val &= ~DSPFREQGUAR_MASK;
5707 val |= (cmd << DSPFREQGUAR_SHIFT);
5708 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5709 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5710 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5711 50)) {
5712 DRM_ERROR("timed out waiting for CDclk change\n");
5713 }
5714 mutex_unlock(&dev_priv->rps.hw_lock);
5715
54433e91
VS		 5716 mutex_lock(&dev_priv->sb_lock);
5717
dfcab17e 5718 if (cdclk == 400000) {
6bcda4f0 5719 u32 divider;
30a970c6 5720
6bcda4f0 5721 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5722
30a970c6
JB		 5723 /* adjust cdclk divider */
5724 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5725 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5726 val |= divider;
5727 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5728
5729 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5730 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5731 50))
5732 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5733 }
5734
30a970c6
JB		 5735 /* adjust self-refresh exit latency value */
5736 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5737 val &= ~0x7f;
5738
5739 /*
5740 * For high bandwidth configs, we set a higher latency in the bunit
5741 * so that the core display fetch happens in time to avoid underruns.
5742 */
dfcab17e 5743 if (cdclk == 400000)
30a970c6
JB		 5744 val |= 4500 / 250; /* 4.5 usec */
5745 else
5746 val |= 3000 / 250; /* 3.0 usec */
5747 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5748
a580516d 5749 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5750
b6283055 5751 intel_update_cdclk(dev);
30a970c6
JB		 5752}
5753
383c5a6a
VS		 5754static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5755{
5756 struct drm_i915_private *dev_priv = dev->dev_private;
5757 u32 val, cmd;
5758
164dfd28
VK		 5759 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5760 != dev_priv->cdclk_freq);
383c5a6a
VS		 5761
5762 switch (cdclk) {
383c5a6a
VS		 5763 case 333333:
5764 case 320000:
383c5a6a 5765 case 266667:
383c5a6a 5766 case 200000:
383c5a6a
VS		 5767 break;
5768 default:
5f77eeb0 5769 MISSING_CASE(cdclk);
383c5a6a
VS		 5770 return;
5771 }
5772
9d0d3fda
VS		 5773 /*
5774 * Specs are full of misinformation, but testing on actual
5775 * hardware has shown that we just need to write the desired
5776 * CCK divider into the Punit register.
5777 */
5778 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5779
383c5a6a
VS		 5780 mutex_lock(&dev_priv->rps.hw_lock);
5781 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5782 val &= ~DSPFREQGUAR_MASK_CHV;
5783 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5784 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5785 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5786 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5787 50)) {
5788 DRM_ERROR("timed out waiting for CDclk change\n");
5789 }
5790 mutex_unlock(&dev_priv->rps.hw_lock);
5791
b6283055 5792 intel_update_cdclk(dev);
383c5a6a
VS		 5793}
5794
30a970c6
JB		 5795static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5796 int max_pixclk)
5797{
6bcda4f0 5798 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5799 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5800
30a970c6
JB		 5801 /*
5802 * Really only a few cases to deal with, as only 4 CDclks are supported:
5803 * 200MHz
5804 * 267MHz
29dc7ef3 5805 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5806 * 400MHz (VLV only)
5807 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5808 * of the lower bin and adjust if needed.
e37c67a1
VS		 5809 *
5810 * We seem to get an unstable or solid color picture at 200MHz.
5811 * Not sure what's wrong. For now use 200MHz only when all pipes
5812 * are off.
30a970c6 5813 */
6cca3195
VS		 5814 if (!IS_CHERRYVIEW(dev_priv) &&
5815 max_pixclk > freq_320*limit/100)
dfcab17e 5816 return 400000;
6cca3195 5817 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5818 return freq_320;
e37c67a1 5819 else if (max_pixclk > 0)
dfcab17e 5820 return 266667;
e37c67a1
VS		 5821 else
5822 return 200000;
30a970c6
JB		 5823}
5824
f8437dd1
VK		 5825static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5826 int max_pixclk)
5827{
5828 /*
5829 * FIXME:
5830 * - remove the guardband, it's not needed on BXT
5831 * - set 19.2MHz bypass frequency if there are no active pipes
5832 */
5833 if (max_pixclk > 576000*9/10)
5834 return 624000;
5835 else if (max_pixclk > 384000*9/10)
5836 return 576000;
5837 else if (max_pixclk > 288000*9/10)
5838 return 384000;
5839 else if (max_pixclk > 144000*9/10)
5840 return 288000;
5841 else
5842 return 144000;
5843}
5844
a821fc46
ACO		 5845/* Compute the max pixel clock for new configuration. Uses atomic state if
5846 * that's non-NULL, look at current state otherwise. */
5847static int intel_mode_max_pixclk(struct drm_device *dev,
5848 struct drm_atomic_state *state)
30a970c6 5849{
30a970c6 5850 struct intel_crtc *intel_crtc;
304603f4 5851 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5852 int max_pixclk = 0;
5853
d3fcc808 5854 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5855 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5856 if (IS_ERR(crtc_state))
5857 return PTR_ERR(crtc_state);
5858
5859 if (!crtc_state->base.enable)
5860 continue;
5861
5862 max_pixclk = max(max_pixclk,
5863 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5864 }
5865
5866 return max_pixclk;
5867}
5868
27c329ed 5869static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5870{
27c329ed
ML		 5871 struct drm_device *dev = state->dev;
5872 struct drm_i915_private *dev_priv = dev->dev_private;
5873 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5874
304603f4
ACO		 5875 if (max_pixclk < 0)
5876 return max_pixclk;
30a970c6 5877
27c329ed
ML		 5878 to_intel_atomic_state(state)->cdclk =
5879 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5880
27c329ed
ML		 5881 return 0;
5882}
304603f4 5883
27c329ed
ML		 5884static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5885{
5886 struct drm_device *dev = state->dev;
5887 struct drm_i915_private *dev_priv = dev->dev_private;
5888 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5889
27c329ed
ML		 5890 if (max_pixclk < 0)
5891 return max_pixclk;
85a96e7a 5892
27c329ed
ML		 5893 to_intel_atomic_state(state)->cdclk =
5894 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5895
27c329ed 5896 return 0;
30a970c6
JB		 5897}
5898
1e69cd74
VS		 5899static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5900{
5901 unsigned int credits, default_credits;
5902
5903 if (IS_CHERRYVIEW(dev_priv))
5904 default_credits = PFI_CREDIT(12);
5905 else
5906 default_credits = PFI_CREDIT(8);
5907
164dfd28 5908 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5909 /* CHV suggested value is 31 or 63 */
5910 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5911 credits = PFI_CREDIT_63;
1e69cd74
VS		 5912 else
5913 credits = PFI_CREDIT(15);
5914 } else {
5915 credits = default_credits;
5916 }
5917
5918 /*
5919 * WA - write default credits before re-programming
5920 * FIXME: should we also set the resend bit here?
5921 */
5922 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5923 default_credits);
5924
5925 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5926 credits | PFI_CREDIT_RESEND);
5927
5928 /*
5929 * FIXME is this guaranteed to clear
5930 * immediately or should we poll for it?
5931 */
5932 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5933}
5934
27c329ed 5935static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5936{
a821fc46 5937 struct drm_device *dev = old_state->dev;
27c329ed 5938 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5939 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5940
27c329ed
ML		 5941 /*
5942 * FIXME: We can end up here with all power domains off, yet
5943 * with a CDCLK frequency other than the minimum. To account
5944 * for this take the PIPE-A power domain, which covers the HW
5945 * blocks needed for the following programming. This can be
5946 * removed once it's guaranteed that we get here either with
5947 * the minimum CDCLK set, or the required power domains
5948 * enabled.
5949 */
5950 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5951
27c329ed
ML		 5952 if (IS_CHERRYVIEW(dev))
5953 cherryview_set_cdclk(dev, req_cdclk);
5954 else
5955 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5956
27c329ed 5957 vlv_program_pfi_credits(dev_priv);
1e69cd74 5958
27c329ed 5959 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 5960}
5961
89b667f8
JB		 5962static void valleyview_crtc_enable(struct drm_crtc *crtc)
5963{
5964 struct drm_device *dev = crtc->dev;
a72e4c9f 5965 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5967 struct intel_encoder *encoder;
5968 int pipe = intel_crtc->pipe;
23538ef1 5969 bool is_dsi;
89b667f8 5970
53d9f4e9 5971 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 5972 return;
5973
409ee761 5974 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5975
1ae0d137
VS		 5976 if (!is_dsi) {
5977 if (IS_CHERRYVIEW(dev))
6e3c9717 5978 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5979 else
6e3c9717 5980 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5981 }
5b18e57c 5982
6e3c9717 5983 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5984 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5985
5986 intel_set_pipe_timings(intel_crtc);
5987
c14b0485
VS		 5988 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5989 struct drm_i915_private *dev_priv = dev->dev_private;
5990
5991 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5992 I915_WRITE(CHV_CANVAS(pipe), 0);
5993 }
5994
5b18e57c
DV		 5995 i9xx_set_pipeconf(intel_crtc);
5996
89b667f8 5997 intel_crtc->active = true;
89b667f8 5998
a72e4c9f 5999 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6000
89b667f8
JB		 6001 for_each_encoder_on_crtc(dev, crtc, encoder)
6002 if (encoder->pre_pll_enable)
6003 encoder->pre_pll_enable(encoder);
6004
9d556c99
CML		 6005 if (!is_dsi) {
6006 if (IS_CHERRYVIEW(dev))
6e3c9717 6007 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6008 else
6e3c9717 6009 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6010 }
89b667f8
JB		 6011
6012 for_each_encoder_on_crtc(dev, crtc, encoder)
6013 if (encoder->pre_enable)
6014 encoder->pre_enable(encoder);
6015
2dd24552
JB		 6016 i9xx_pfit_enable(intel_crtc);
6017
63cbb074
VS		 6018 intel_crtc_load_lut(crtc);
6019
f37fcc2a 6020 intel_update_watermarks(crtc);
e1fdc473 6021 intel_enable_pipe(intel_crtc);
be6a6f8e 6022
4b3a9526
VS		 6023 assert_vblank_disabled(crtc);
6024 drm_crtc_vblank_on(crtc);
6025
f9b61ff6
DV		 6026 for_each_encoder_on_crtc(dev, crtc, encoder)
6027 encoder->enable(encoder);
89b667f8
JB		 6028}
6029
f13c2ef3
DV		 6030static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6031{
6032 struct drm_device *dev = crtc->base.dev;
6033 struct drm_i915_private *dev_priv = dev->dev_private;
6034
6e3c9717
ACO		 6035 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6036 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6037}
6038
0b8765c6 6039static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6040{
6041 struct drm_device *dev = crtc->dev;
a72e4c9f 6042 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6044 struct intel_encoder *encoder;
79e53945 6045 int pipe = intel_crtc->pipe;
79e53945 6046
53d9f4e9 6047 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6048 return;
6049
f13c2ef3
DV		 6050 i9xx_set_pll_dividers(intel_crtc);
6051
6e3c9717 6052 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6053 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6054
6055 intel_set_pipe_timings(intel_crtc);
6056
5b18e57c
DV		 6057 i9xx_set_pipeconf(intel_crtc);
6058
f7abfe8b 6059 intel_crtc->active = true;
6b383a7f 6060
4a3436e8 6061 if (!IS_GEN2(dev))
a72e4c9f 6062 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6063
9d6d9f19
MK		 6064 for_each_encoder_on_crtc(dev, crtc, encoder)
6065 if (encoder->pre_enable)
6066 encoder->pre_enable(encoder);
6067
f6736a1a
DV		 6068 i9xx_enable_pll(intel_crtc);
6069
2dd24552
JB		 6070 i9xx_pfit_enable(intel_crtc);
6071
63cbb074
VS		 6072 intel_crtc_load_lut(crtc);
6073
f37fcc2a 6074 intel_update_watermarks(crtc);
e1fdc473 6075 intel_enable_pipe(intel_crtc);
be6a6f8e 6076
4b3a9526
VS		 6077 assert_vblank_disabled(crtc);
6078 drm_crtc_vblank_on(crtc);
6079
f9b61ff6
DV		 6080 for_each_encoder_on_crtc(dev, crtc, encoder)
6081 encoder->enable(encoder);
0b8765c6 6082}
79e53945 6083
87476d63
DV		 6084static void i9xx_pfit_disable(struct intel_crtc *crtc)
6085{
6086 struct drm_device *dev = crtc->base.dev;
6087 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6088
6e3c9717 6089 if (!crtc->config->gmch_pfit.control)
328d8e82 6090 return;
87476d63 6091
328d8e82 6092 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6093
328d8e82
DV		 6094 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6095 I915_READ(PFIT_CONTROL));
6096 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6097}
6098
0b8765c6
JB		 6099static void i9xx_crtc_disable(struct drm_crtc *crtc)
6100{
6101 struct drm_device *dev = crtc->dev;
6102 struct drm_i915_private *dev_priv = dev->dev_private;
6103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6104 struct intel_encoder *encoder;
0b8765c6 6105 int pipe = intel_crtc->pipe;
ef9c3aee 6106
6304cd91
VS		 6107 /*
6108 * On gen2 planes are double buffered but the pipe isn't, so we must
6109 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6110 * We also need to wait on all gmch platforms because of the
6111 * self-refresh mode constraint explained above.
6304cd91 6112 */
564ed191 6113 intel_wait_for_vblank(dev, pipe);
6304cd91 6114
4b3a9526
VS		 6115 for_each_encoder_on_crtc(dev, crtc, encoder)
6116 encoder->disable(encoder);
6117
f9b61ff6
DV		 6118 drm_crtc_vblank_off(crtc);
6119 assert_vblank_disabled(crtc);
6120
575f7ab7 6121 intel_disable_pipe(intel_crtc);
24a1f16d 6122
87476d63 6123 i9xx_pfit_disable(intel_crtc);
24a1f16d 6124
89b667f8
JB		 6125 for_each_encoder_on_crtc(dev, crtc, encoder)
6126 if (encoder->post_disable)
6127 encoder->post_disable(encoder);
6128
409ee761 6129 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6130 if (IS_CHERRYVIEW(dev))
6131 chv_disable_pll(dev_priv, pipe);
6132 else if (IS_VALLEYVIEW(dev))
6133 vlv_disable_pll(dev_priv, pipe);
6134 else
1c4e0274 6135 i9xx_disable_pll(intel_crtc);
076ed3b2 6136 }
0b8765c6 6137
4a3436e8 6138 if (!IS_GEN2(dev))
a72e4c9f 6139 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
0b8765c6
JB		 6140}
6141
b17d48e2
ML		 6142static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6143{
6144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6145 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6146 enum intel_display_power_domain domain;
6147 unsigned long domains;
6148
6149 if (!intel_crtc->active)
6150 return;
6151
a539205a
ML		 6152 if (to_intel_plane_state(crtc->primary->state)->visible) {
6153 intel_crtc_wait_for_pending_flips(crtc);
6154 intel_pre_disable_primary(crtc);
6155 }
6156
d032ffa0 6157 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2
ML		 6158 dev_priv->display.crtc_disable(crtc);
6159
6160 domains = intel_crtc->enabled_power_domains;
6161 for_each_power_domain(domain, domains)
6162 intel_display_power_put(dev_priv, domain);
6163 intel_crtc->enabled_power_domains = 0;
6164}
6165
6b72d486
ML		 6166/*
6167 * turn all crtc's off, but do not adjust state
6168 * This has to be paired with a call to intel_modeset_setup_hw_state.
6169 */
9716c691 6170void intel_display_suspend(struct drm_device *dev)
ee7b9f93 6171{
6b72d486
ML		 6172 struct drm_crtc *crtc;
6173
b17d48e2
ML		 6174 for_each_crtc(dev, crtc)
6175 intel_crtc_disable_noatomic(crtc);
ee7b9f93
JB		 6176}
6177
b04c5bd6 6178/* Master function to enable/disable CRTC and corresponding power wells */
5da76e94 6179int intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6180{
6181 struct drm_device *dev = crtc->dev;
5da76e94
ML		 6182 struct drm_mode_config *config = &dev->mode_config;
6183 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
0e572fe7 6184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5da76e94
ML		 6185 struct intel_crtc_state *pipe_config;
6186 struct drm_atomic_state *state;
6187 int ret;
976f8a20 6188
1b509259 6189 if (enable == intel_crtc->active)
5da76e94 6190 return 0;
0e572fe7 6191
1b509259 6192 if (enable && !crtc->state->enable)
5da76e94 6193 return 0;
1b509259 6194
5da76e94
ML		 6195 /* this function should be called with drm_modeset_lock_all for now */
6196 if (WARN_ON(!ctx))
6197 return -EIO;
6198 lockdep_assert_held(&ctx->ww_ctx);
1b509259 6199
5da76e94
ML		 6200 state = drm_atomic_state_alloc(dev);
6201 if (WARN_ON(!state))
6202 return -ENOMEM;
1b509259 6203
5da76e94
ML		 6204 state->acquire_ctx = ctx;
6205 state->allow_modeset = true;
6206
6207 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6208 if (IS_ERR(pipe_config)) {
6209 ret = PTR_ERR(pipe_config);
6210 goto err;
0e572fe7 6211 }
5da76e94
ML		 6212 pipe_config->base.active = enable;
6213
6214 ret = intel_set_mode(state);
6215 if (!ret)
6216 return ret;
6217
6218err:
6219 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6220 drm_atomic_state_free(state);
6221 return ret;
b04c5bd6
BF		 6222}
6223
6224/**
6225 * Sets the power management mode of the pipe and plane.
6226 */
6227void intel_crtc_update_dpms(struct drm_crtc *crtc)
6228{
6229 struct drm_device *dev = crtc->dev;
6230 struct intel_encoder *intel_encoder;
6231 bool enable = false;
6232
6233 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6234 enable |= intel_encoder->connectors_active;
6235
6236 intel_crtc_control(crtc, enable);
cdd59983
CW		 6237}
6238
ea5b213a 6239void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6240{
4ef69c7a 6241 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6242
ea5b213a
CW		 6243 drm_encoder_cleanup(encoder);
6244 kfree(intel_encoder);
7e7d76c3
JB		 6245}
6246
9237329d 6247/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6248 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6249 * state of the entire output pipe. */
9237329d 6250static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6251{
5ab432ef
DV		 6252 if (mode == DRM_MODE_DPMS_ON) {
6253 encoder->connectors_active = true;
6254
b2cabb0e 6255 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6256 } else {
6257 encoder->connectors_active = false;
6258
b2cabb0e 6259 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6260 }
79e53945
JB		 6261}
6262
0a91ca29
DV		 6263/* Cross check the actual hw state with our own modeset state tracking (and it's
6264 * internal consistency). */
b980514c 6265static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6266{
0a91ca29
DV		 6267 if (connector->get_hw_state(connector)) {
6268 struct intel_encoder *encoder = connector->encoder;
6269 struct drm_crtc *crtc;
6270 bool encoder_enabled;
6271 enum pipe pipe;
6272
6273 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6274 connector->base.base.id,
c23cc417 6275 connector->base.name);
0a91ca29 6276
0e32b39c
DA		 6277 /* there is no real hw state for MST connectors */
6278 if (connector->mst_port)
6279 return;
6280
e2c719b7 6281 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6282 "wrong connector dpms state\n");
e2c719b7 6283 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6284 "active connector not linked to encoder\n");
0a91ca29 6285
36cd7444 6286 if (encoder) {
e2c719b7 6287 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6288 "encoder->connectors_active not set\n");
6289
6290 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6291 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6292 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6293 return;
0a91ca29 6294
36cd7444 6295 crtc = encoder->base.crtc;
0a91ca29 6296
83d65738
MR		 6297 I915_STATE_WARN(!crtc->state->enable,
6298 "crtc not enabled\n");
e2c719b7
RC		 6299 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6300 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6301 "encoder active on the wrong pipe\n");
6302 }
0a91ca29 6303 }
79e53945
JB		 6304}
6305
08d9bc92
ACO		 6306int intel_connector_init(struct intel_connector *connector)
6307{
6308 struct drm_connector_state *connector_state;
6309
6310 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6311 if (!connector_state)
6312 return -ENOMEM;
6313
6314 connector->base.state = connector_state;
6315 return 0;
6316}
6317
6318struct intel_connector *intel_connector_alloc(void)
6319{
6320 struct intel_connector *connector;
6321
6322 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6323 if (!connector)
6324 return NULL;
6325
6326 if (intel_connector_init(connector) < 0) {
6327 kfree(connector);
6328 return NULL;
6329 }
6330
6331 return connector;
6332}
6333
5ab432ef
DV		 6334/* Even simpler default implementation, if there's really no special case to
6335 * consider. */
6336void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6337{
5ab432ef
DV		 6338 /* All the simple cases only support two dpms states. */
6339 if (mode != DRM_MODE_DPMS_ON)
6340 mode = DRM_MODE_DPMS_OFF;
d4270e57 6341
5ab432ef
DV		 6342 if (mode == connector->dpms)
6343 return;
6344
6345 connector->dpms = mode;
6346
6347 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6348 if (connector->encoder)
6349 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6350
b980514c 6351 intel_modeset_check_state(connector->dev);
79e53945
JB		 6352}
6353
f0947c37
DV		 6354/* Simple connector->get_hw_state implementation for encoders that support only
6355 * one connector and no cloning and hence the encoder state determines the state
6356 * of the connector. */
6357bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6358{
24929352 6359 enum pipe pipe = 0;
f0947c37 6360 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6361
f0947c37 6362 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6363}
6364
6d293983 6365static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6366{
6d293983
ACO		 6367 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6368 return crtc_state->fdi_lanes;
d272ddfa
VS		 6369
6370 return 0;
6371}
6372
6d293983 6373static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6374 struct intel_crtc_state *pipe_config)
1857e1da 6375{
6d293983
ACO		 6376 struct drm_atomic_state *state = pipe_config->base.state;
6377 struct intel_crtc *other_crtc;
6378 struct intel_crtc_state *other_crtc_state;
6379
1857e1da
DV		 6380 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6381 pipe_name(pipe), pipe_config->fdi_lanes);
6382 if (pipe_config->fdi_lanes > 4) {
6383 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6384 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6385 return -EINVAL;
1857e1da
DV		 6386 }
6387
bafb6553 6388 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6389 if (pipe_config->fdi_lanes > 2) {
6390 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6391 pipe_config->fdi_lanes);
6d293983 6392 return -EINVAL;
1857e1da 6393 } else {
6d293983 6394 return 0;
1857e1da
DV		 6395 }
6396 }
6397
6398 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6399 return 0;
1857e1da
DV		 6400
6401 /* Ivybridge 3 pipe is really complicated */
6402 switch (pipe) {
6403 case PIPE_A:
6d293983 6404 return 0;
1857e1da 6405 case PIPE_B:
6d293983
ACO		 6406 if (pipe_config->fdi_lanes <= 2)
6407 return 0;
6408
6409 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6410 other_crtc_state =
6411 intel_atomic_get_crtc_state(state, other_crtc);
6412 if (IS_ERR(other_crtc_state))
6413 return PTR_ERR(other_crtc_state);
6414
6415 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6416 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6417 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6418 return -EINVAL;
1857e1da 6419 }
6d293983 6420 return 0;
1857e1da 6421 case PIPE_C:
251cc67c
VS		 6422 if (pipe_config->fdi_lanes > 2) {
6423 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6424 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6425 return -EINVAL;
251cc67c 6426 }
6d293983
ACO		 6427
6428 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6429 other_crtc_state =
6430 intel_atomic_get_crtc_state(state, other_crtc);
6431 if (IS_ERR(other_crtc_state))
6432 return PTR_ERR(other_crtc_state);
6433
6434 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6435 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6436 return -EINVAL;
1857e1da 6437 }
6d293983 6438 return 0;
1857e1da
DV		 6439 default:
6440 BUG();
6441 }
6442}
6443
e29c22c0
DV		 6444#define RETRY 1
6445static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6446 struct intel_crtc_state *pipe_config)
877d48d5 6447{
1857e1da 6448 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6449 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6450 int lane, link_bw, fdi_dotclock, ret;
6451 bool needs_recompute = false;
877d48d5 6452
e29c22c0 6453retry:
877d48d5
DV		 6454 /* FDI is a binary signal running at ~2.7GHz, encoding
6455 * each output octet as 10 bits. The actual frequency
6456 * is stored as a divider into a 100MHz clock, and the
6457 * mode pixel clock is stored in units of 1KHz.
6458 * Hence the bw of each lane in terms of the mode signal
6459 * is:
6460 */
6461 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6462
241bfc38 6463 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6464
2bd89a07 6465 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6466 pipe_config->pipe_bpp);
6467
6468 pipe_config->fdi_lanes = lane;
6469
2bd89a07 6470 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6471 link_bw, &pipe_config->fdi_m_n);
1857e1da 6472
6d293983
ACO		 6473 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6474 intel_crtc->pipe, pipe_config);
6475 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6476 pipe_config->pipe_bpp -= 2*3;
6477 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6478 pipe_config->pipe_bpp);
6479 needs_recompute = true;
6480 pipe_config->bw_constrained = true;
6481
6482 goto retry;
6483 }
6484
6485 if (needs_recompute)
6486 return RETRY;
6487
6d293983 6488 return ret;
877d48d5
DV		 6489}
6490
8cfb3407
VS		 6491static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6492 struct intel_crtc_state *pipe_config)
6493{
6494 if (pipe_config->pipe_bpp > 24)
6495 return false;
6496
6497 /* HSW can handle pixel rate up to cdclk? */
6498 if (IS_HASWELL(dev_priv->dev))
6499 return true;
6500
6501 /*
b432e5cf
VS		 6502 * We compare against max which means we must take
6503 * the increased cdclk requirement into account when
6504 * calculating the new cdclk.
6505 *
6506 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6507 */
6508 return ilk_pipe_pixel_rate(pipe_config) <=
6509 dev_priv->max_cdclk_freq * 95 / 100;
6510}
6511
42db64ef 6512static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6513 struct intel_crtc_state *pipe_config)
42db64ef 6514{
8cfb3407
VS		 6515 struct drm_device *dev = crtc->base.dev;
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517
d330a953 6518 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6519 hsw_crtc_supports_ips(crtc) &&
6520 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6521}
6522
a43f6e0f 6523static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6524 struct intel_crtc_state *pipe_config)
79e53945 6525{
a43f6e0f 6526 struct drm_device *dev = crtc->base.dev;
8bd31e67 6527 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6528 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6529
ad3a4479 6530 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6531 if (INTEL_INFO(dev)->gen < 4) {
44913155 6532 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6533
6534 /*
6535 * Enable pixel doubling when the dot clock
6536 * is > 90% of the (display) core speed.
6537 *
b397c96b
VS		 6538 * GDG double wide on either pipe,
6539 * otherwise pipe A only.
cf532bb2 6540 */
b397c96b 6541 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6542 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6543 clock_limit *= 2;
cf532bb2 6544 pipe_config->double_wide = true;
ad3a4479
VS		 6545 }
6546
241bfc38 6547 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6548 return -EINVAL;
2c07245f 6549 }
89749350 6550
1d1d0e27
VS		 6551 /*
6552 * Pipe horizontal size must be even in:
6553 * - DVO ganged mode
6554 * - LVDS dual channel mode
6555 * - Double wide pipe
6556 */
a93e255f 6557 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6558 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6559 pipe_config->pipe_src_w &= ~1;
6560
8693a824
DL		 6561 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6562 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6563 */
6564 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6565 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6566 return -EINVAL;
44f46b42 6567
f5adf94e 6568 if (HAS_IPS(dev))
a43f6e0f
DV		 6569 hsw_compute_ips_config(crtc, pipe_config);
6570
877d48d5 6571 if (pipe_config->has_pch_encoder)
a43f6e0f 6572 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6573
cf5a15be 6574 return 0;
79e53945
JB		 6575}
6576
1652d19e
VS		 6577static int skylake_get_display_clock_speed(struct drm_device *dev)
6578{
6579 struct drm_i915_private *dev_priv = to_i915(dev);
6580 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6581 uint32_t cdctl = I915_READ(CDCLK_CTL);
6582 uint32_t linkrate;
6583
414355a7 6584 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6585 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6586
6587 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6588 return 540000;
6589
6590 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6591 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6592
71cd8423
DL		 6593 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6594 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6595 /* vco 8640 */
6596 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6597 case CDCLK_FREQ_450_432:
6598 return 432000;
6599 case CDCLK_FREQ_337_308:
6600 return 308570;
6601 case CDCLK_FREQ_675_617:
6602 return 617140;
6603 default:
6604 WARN(1, "Unknown cd freq selection\n");
6605 }
6606 } else {
6607 /* vco 8100 */
6608 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6609 case CDCLK_FREQ_450_432:
6610 return 450000;
6611 case CDCLK_FREQ_337_308:
6612 return 337500;
6613 case CDCLK_FREQ_675_617:
6614 return 675000;
6615 default:
6616 WARN(1, "Unknown cd freq selection\n");
6617 }
6618 }
6619
6620 /* error case, do as if DPLL0 isn't enabled */
6621 return 24000;
6622}
6623
acd3f3d3
BP		 6624static int broxton_get_display_clock_speed(struct drm_device *dev)
6625{
6626 struct drm_i915_private *dev_priv = to_i915(dev);
6627 uint32_t cdctl = I915_READ(CDCLK_CTL);
6628 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6629 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6630 int cdclk;
6631
6632 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6633 return 19200;
6634
6635 cdclk = 19200 * pll_ratio / 2;
6636
6637 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6638 case BXT_CDCLK_CD2X_DIV_SEL_1:
6639 return cdclk; /* 576MHz or 624MHz */
6640 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6641 return cdclk * 2 / 3; /* 384MHz */
6642 case BXT_CDCLK_CD2X_DIV_SEL_2:
6643 return cdclk / 2; /* 288MHz */
6644 case BXT_CDCLK_CD2X_DIV_SEL_4:
6645 return cdclk / 4; /* 144MHz */
6646 }
6647
6648 /* error case, do as if DE PLL isn't enabled */
6649 return 19200;
6650}
6651
1652d19e
VS		 6652static int broadwell_get_display_clock_speed(struct drm_device *dev)
6653{
6654 struct drm_i915_private *dev_priv = dev->dev_private;
6655 uint32_t lcpll = I915_READ(LCPLL_CTL);
6656 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6657
6658 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6659 return 800000;
6660 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6661 return 450000;
6662 else if (freq == LCPLL_CLK_FREQ_450)
6663 return 450000;
6664 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6665 return 540000;
6666 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6667 return 337500;
6668 else
6669 return 675000;
6670}
6671
6672static int haswell_get_display_clock_speed(struct drm_device *dev)
6673{
6674 struct drm_i915_private *dev_priv = dev->dev_private;
6675 uint32_t lcpll = I915_READ(LCPLL_CTL);
6676 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6677
6678 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6679 return 800000;
6680 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6681 return 450000;
6682 else if (freq == LCPLL_CLK_FREQ_450)
6683 return 450000;
6684 else if (IS_HSW_ULT(dev))
6685 return 337500;
6686 else
6687 return 540000;
79e53945
JB		 6688}
6689
25eb05fc
JB		 6690static int valleyview_get_display_clock_speed(struct drm_device *dev)
6691{
d197b7d3 6692 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6693 u32 val;
6694 int divider;
6695
6bcda4f0
VS		 6696 if (dev_priv->hpll_freq == 0)
6697 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6698
a580516d 6699 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6700 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6701 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6702
6703 divider = val & DISPLAY_FREQUENCY_VALUES;
6704
7d007f40
VS		 6705 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6706 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6707 "cdclk change in progress\n");
6708
6bcda4f0 6709 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6710}
6711
b37a6434
VS		 6712static int ilk_get_display_clock_speed(struct drm_device *dev)
6713{
6714 return 450000;
6715}
6716
e70236a8
JB		 6717static int i945_get_display_clock_speed(struct drm_device *dev)
6718{
6719 return 400000;
6720}
79e53945 6721
e70236a8 6722static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6723{
e907f170 6724 return 333333;
e70236a8 6725}
79e53945 6726
e70236a8
JB		 6727static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6728{
6729 return 200000;
6730}
79e53945 6731
257a7ffc
DV		 6732static int pnv_get_display_clock_speed(struct drm_device *dev)
6733{
6734 u16 gcfgc = 0;
6735
6736 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6737
6738 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6739 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6740 return 266667;
257a7ffc 6741 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6742 return 333333;
257a7ffc 6743 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6744 return 444444;
257a7ffc
DV		 6745 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6746 return 200000;
6747 default:
6748 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6749 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6750 return 133333;
257a7ffc 6751 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6752 return 166667;
257a7ffc
DV		 6753 }
6754}
6755
e70236a8
JB		 6756static int i915gm_get_display_clock_speed(struct drm_device *dev)
6757{
6758 u16 gcfgc = 0;
79e53945 6759
e70236a8
JB		 6760 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6761
6762 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6763 return 133333;
e70236a8
JB		 6764 else {
6765 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6766 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6767 return 333333;
e70236a8
JB		 6768 default:
6769 case GC_DISPLAY_CLOCK_190_200_MHZ:
6770 return 190000;
79e53945 6771 }
e70236a8
JB		 6772 }
6773}
6774
6775static int i865_get_display_clock_speed(struct drm_device *dev)
6776{
e907f170 6777 return 266667;
e70236a8
JB		 6778}
6779
1b1d2716 6780static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6781{
6782 u16 hpllcc = 0;
1b1d2716 6783
65cd2b3f
VS		 6784 /*
6785 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6786 * encoding is different :(
6787 * FIXME is this the right way to detect 852GM/852GMV?
6788 */
6789 if (dev->pdev->revision == 0x1)
6790 return 133333;
6791
1b1d2716
VS		 6792 pci_bus_read_config_word(dev->pdev->bus,
6793 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6794
e70236a8
JB		 6795 /* Assume that the hardware is in the high speed state. This
6796 * should be the default.
6797 */
6798 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6799 case GC_CLOCK_133_200:
1b1d2716 6800 case GC_CLOCK_133_200_2:
e70236a8
JB		 6801 case GC_CLOCK_100_200:
6802 return 200000;
6803 case GC_CLOCK_166_250:
6804 return 250000;
6805 case GC_CLOCK_100_133:
e907f170 6806 return 133333;
1b1d2716
VS		 6807 case GC_CLOCK_133_266:
6808 case GC_CLOCK_133_266_2:
6809 case GC_CLOCK_166_266:
6810 return 266667;
e70236a8 6811 }
79e53945 6812
e70236a8
JB		 6813 /* Shouldn't happen */
6814 return 0;
6815}
79e53945 6816
e70236a8
JB		 6817static int i830_get_display_clock_speed(struct drm_device *dev)
6818{
e907f170 6819 return 133333;
79e53945
JB		 6820}
6821
34edce2f
VS		 6822static unsigned int intel_hpll_vco(struct drm_device *dev)
6823{
6824 struct drm_i915_private *dev_priv = dev->dev_private;
6825 static const unsigned int blb_vco[8] = {
6826 [0] = 3200000,
6827 [1] = 4000000,
6828 [2] = 5333333,
6829 [3] = 4800000,
6830 [4] = 6400000,
6831 };
6832 static const unsigned int pnv_vco[8] = {
6833 [0] = 3200000,
6834 [1] = 4000000,
6835 [2] = 5333333,
6836 [3] = 4800000,
6837 [4] = 2666667,
6838 };
6839 static const unsigned int cl_vco[8] = {
6840 [0] = 3200000,
6841 [1] = 4000000,
6842 [2] = 5333333,
6843 [3] = 6400000,
6844 [4] = 3333333,
6845 [5] = 3566667,
6846 [6] = 4266667,
6847 };
6848 static const unsigned int elk_vco[8] = {
6849 [0] = 3200000,
6850 [1] = 4000000,
6851 [2] = 5333333,
6852 [3] = 4800000,
6853 };
6854 static const unsigned int ctg_vco[8] = {
6855 [0] = 3200000,
6856 [1] = 4000000,
6857 [2] = 5333333,
6858 [3] = 6400000,
6859 [4] = 2666667,
6860 [5] = 4266667,
6861 };
6862 const unsigned int *vco_table;
6863 unsigned int vco;
6864 uint8_t tmp = 0;
6865
6866 /* FIXME other chipsets? */
6867 if (IS_GM45(dev))
6868 vco_table = ctg_vco;
6869 else if (IS_G4X(dev))
6870 vco_table = elk_vco;
6871 else if (IS_CRESTLINE(dev))
6872 vco_table = cl_vco;
6873 else if (IS_PINEVIEW(dev))
6874 vco_table = pnv_vco;
6875 else if (IS_G33(dev))
6876 vco_table = blb_vco;
6877 else
6878 return 0;
6879
6880 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6881
6882 vco = vco_table[tmp & 0x7];
6883 if (vco == 0)
6884 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6885 else
6886 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6887
6888 return vco;
6889}
6890
6891static int gm45_get_display_clock_speed(struct drm_device *dev)
6892{
6893 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6894 uint16_t tmp = 0;
6895
6896 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6897
6898 cdclk_sel = (tmp >> 12) & 0x1;
6899
6900 switch (vco) {
6901 case 2666667:
6902 case 4000000:
6903 case 5333333:
6904 return cdclk_sel ? 333333 : 222222;
6905 case 3200000:
6906 return cdclk_sel ? 320000 : 228571;
6907 default:
6908 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6909 return 222222;
6910 }
6911}
6912
6913static int i965gm_get_display_clock_speed(struct drm_device *dev)
6914{
6915 static const uint8_t div_3200[] = { 16, 10, 8 };
6916 static const uint8_t div_4000[] = { 20, 12, 10 };
6917 static const uint8_t div_5333[] = { 24, 16, 14 };
6918 const uint8_t *div_table;
6919 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6920 uint16_t tmp = 0;
6921
6922 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6923
6924 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6925
6926 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6927 goto fail;
6928
6929 switch (vco) {
6930 case 3200000:
6931 div_table = div_3200;
6932 break;
6933 case 4000000:
6934 div_table = div_4000;
6935 break;
6936 case 5333333:
6937 div_table = div_5333;
6938 break;
6939 default:
6940 goto fail;
6941 }
6942
6943 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6944
caf4e252 6945fail:
34edce2f
VS		 6946 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6947 return 200000;
6948}
6949
6950static int g33_get_display_clock_speed(struct drm_device *dev)
6951{
6952 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6953 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6954 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6955 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6956 const uint8_t *div_table;
6957 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6958 uint16_t tmp = 0;
6959
6960 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6961
6962 cdclk_sel = (tmp >> 4) & 0x7;
6963
6964 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6965 goto fail;
6966
6967 switch (vco) {
6968 case 3200000:
6969 div_table = div_3200;
6970 break;
6971 case 4000000:
6972 div_table = div_4000;
6973 break;
6974 case 4800000:
6975 div_table = div_4800;
6976 break;
6977 case 5333333:
6978 div_table = div_5333;
6979 break;
6980 default:
6981 goto fail;
6982 }
6983
6984 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6985
caf4e252 6986fail:
34edce2f
VS		 6987 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6988 return 190476;
6989}
6990
2c07245f 6991static void
a65851af 6992intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6993{
a65851af
VS		 6994 while (*num > DATA_LINK_M_N_MASK ||
6995 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6996 *num >>= 1;
6997 *den >>= 1;
6998 }
6999}
7000
a65851af
VS		 7001static void compute_m_n(unsigned int m, unsigned int n,
7002 uint32_t *ret_m, uint32_t *ret_n)
7003{
7004 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7005 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7006 intel_reduce_m_n_ratio(ret_m, ret_n);
7007}
7008
e69d0bc1
DV		 7009void
7010intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7011 int pixel_clock, int link_clock,
7012 struct intel_link_m_n *m_n)
2c07245f 7013{
e69d0bc1 7014 m_n->tu = 64;
a65851af
VS		 7015
7016 compute_m_n(bits_per_pixel * pixel_clock,
7017 link_clock * nlanes * 8,
7018 &m_n->gmch_m, &m_n->gmch_n);
7019
7020 compute_m_n(pixel_clock, link_clock,
7021 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7022}
7023
a7615030
CW		 7024static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7025{
d330a953
JN		 7026 if (i915.panel_use_ssc >= 0)
7027 return i915.panel_use_ssc != 0;
41aa3448 7028 return dev_priv->vbt.lvds_use_ssc
435793df 7029 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7030}
7031
a93e255f
ACO		 7032static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7033 int num_connectors)
c65d77d8 7034{
a93e255f 7035 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7036 struct drm_i915_private *dev_priv = dev->dev_private;
7037 int refclk;
7038
a93e255f
ACO		 7039 WARN_ON(!crtc_state->base.state);
7040
5ab7b0b7 7041 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7042 refclk = 100000;
a93e255f 7043 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7044 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7045 refclk = dev_priv->vbt.lvds_ssc_freq;
7046 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7047 } else if (!IS_GEN2(dev)) {
7048 refclk = 96000;
7049 } else {
7050 refclk = 48000;
7051 }
7052
7053 return refclk;
7054}
7055
7429e9d4 7056static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7057{
7df00d7a 7058 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7059}
f47709a9 7060
7429e9d4
DV		 7061static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7062{
7063 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7064}
7065
f47709a9 7066static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7067 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7068 intel_clock_t *reduced_clock)
7069{
f47709a9 7070 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7071 u32 fp, fp2 = 0;
7072
7073 if (IS_PINEVIEW(dev)) {
190f68c5 7074 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7075 if (reduced_clock)
7429e9d4 7076 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7077 } else {
190f68c5 7078 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7079 if (reduced_clock)
7429e9d4 7080 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7081 }
7082
190f68c5 7083 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7084
f47709a9 7085 crtc->lowfreq_avail = false;
a93e255f 7086 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7087 reduced_clock) {
190f68c5 7088 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7089 crtc->lowfreq_avail = true;
a7516a05 7090 } else {
190f68c5 7091 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7092 }
7093}
7094
5e69f97f
CML		 7095static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7096 pipe)
89b667f8
JB		 7097{
7098 u32 reg_val;
7099
7100 /*
7101 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7102 * and set it to a reasonable value instead.
7103 */
ab3c759a 7104 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7105 reg_val &= 0xffffff00;
7106 reg_val |= 0x00000030;
ab3c759a 7107 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7108
ab3c759a 7109 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7110 reg_val &= 0x8cffffff;
7111 reg_val = 0x8c000000;
ab3c759a 7112 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7113
ab3c759a 7114 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7115 reg_val &= 0xffffff00;
ab3c759a 7116 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7117
ab3c759a 7118 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7119 reg_val &= 0x00ffffff;
7120 reg_val |= 0xb0000000;
ab3c759a 7121 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7122}
7123
b551842d
DV		 7124static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7125 struct intel_link_m_n *m_n)
7126{
7127 struct drm_device *dev = crtc->base.dev;
7128 struct drm_i915_private *dev_priv = dev->dev_private;
7129 int pipe = crtc->pipe;
7130
e3b95f1e
DV		 7131 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7132 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7133 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7134 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7135}
7136
7137static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7138 struct intel_link_m_n *m_n,
7139 struct intel_link_m_n *m2_n2)
b551842d
DV		 7140{
7141 struct drm_device *dev = crtc->base.dev;
7142 struct drm_i915_private *dev_priv = dev->dev_private;
7143 int pipe = crtc->pipe;
6e3c9717 7144 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7145
7146 if (INTEL_INFO(dev)->gen >= 5) {
7147 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7148 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7149 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7150 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7151 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7152 * for gen < 8) and if DRRS is supported (to make sure the
7153 * registers are not unnecessarily accessed).
7154 */
44395bfe 7155 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7156 crtc->config->has_drrs) {
f769cd24
VK		 7157 I915_WRITE(PIPE_DATA_M2(transcoder),
7158 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7159 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7160 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7161 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7162 }
b551842d 7163 } else {
e3b95f1e
DV		 7164 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7165 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7166 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7167 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7168 }
7169}
7170
fe3cd48d 7171void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7172{
fe3cd48d
R		 7173 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7174
7175 if (m_n == M1_N1) {
7176 dp_m_n = &crtc->config->dp_m_n;
7177 dp_m2_n2 = &crtc->config->dp_m2_n2;
7178 } else if (m_n == M2_N2) {
7179
7180 /*
7181 * M2_N2 registers are not supported. Hence m2_n2 divider value
7182 * needs to be programmed into M1_N1.
7183 */
7184 dp_m_n = &crtc->config->dp_m2_n2;
7185 } else {
7186 DRM_ERROR("Unsupported divider value\n");
7187 return;
7188 }
7189
6e3c9717
ACO		 7190 if (crtc->config->has_pch_encoder)
7191 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7192 else
fe3cd48d 7193 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7194}
7195
251ac862
DV		 7196static void vlv_compute_dpll(struct intel_crtc *crtc,
7197 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7198{
7199 u32 dpll, dpll_md;
7200
7201 /*
7202 * Enable DPIO clock input. We should never disable the reference
7203 * clock for pipe B, since VGA hotplug / manual detection depends
7204 * on it.
7205 */
7206 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7207 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7208 /* We should never disable this, set it here for state tracking */
7209 if (crtc->pipe == PIPE_B)
7210 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7211 dpll |= DPLL_VCO_ENABLE;
d288f65f 7212 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7213
d288f65f 7214 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7215 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7216 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7217}
7218
d288f65f 7219static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7220 const struct intel_crtc_state *pipe_config)
a0c4da24 7221{
f47709a9 7222 struct drm_device *dev = crtc->base.dev;
a0c4da24 7223 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7224 int pipe = crtc->pipe;
bdd4b6a6 7225 u32 mdiv;
a0c4da24 7226 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7227 u32 coreclk, reg_val;
a0c4da24 7228
a580516d 7229 mutex_lock(&dev_priv->sb_lock);
09153000 7230
d288f65f
VS		 7231 bestn = pipe_config->dpll.n;
7232 bestm1 = pipe_config->dpll.m1;
7233 bestm2 = pipe_config->dpll.m2;
7234 bestp1 = pipe_config->dpll.p1;
7235 bestp2 = pipe_config->dpll.p2;
a0c4da24 7236
89b667f8
JB		 7237 /* See eDP HDMI DPIO driver vbios notes doc */
7238
7239 /* PLL B needs special handling */
bdd4b6a6 7240 if (pipe == PIPE_B)
5e69f97f 7241 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7242
7243 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7244 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7245
7246 /* Disable target IRef on PLL */
ab3c759a 7247 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7248 reg_val &= 0x00ffffff;
ab3c759a 7249 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7250
7251 /* Disable fast lock */
ab3c759a 7252 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7253
7254 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7255 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7256 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7257 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7258 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7259
7260 /*
7261 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7262 * but we don't support that).
7263 * Note: don't use the DAC post divider as it seems unstable.
7264 */
7265 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7266 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7267
a0c4da24 7268 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7269 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7270
89b667f8 7271 /* Set HBR and RBR LPF coefficients */
d288f65f 7272 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7273 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7274 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7275 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7276 0x009f0003);
89b667f8 7277 else
ab3c759a 7278 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7279 0x00d0000f);
7280
681a8504 7281 if (pipe_config->has_dp_encoder) {
89b667f8 7282 /* Use SSC source */
bdd4b6a6 7283 if (pipe == PIPE_A)
ab3c759a 7284 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7285 0x0df40000);
7286 else
ab3c759a 7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7288 0x0df70000);
7289 } else { /* HDMI or VGA */
7290 /* Use bend source */
bdd4b6a6 7291 if (pipe == PIPE_A)
ab3c759a 7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7293 0x0df70000);
7294 else
ab3c759a 7295 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7296 0x0df40000);
7297 }
a0c4da24 7298
ab3c759a 7299 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7300 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7301 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7302 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7303 coreclk |= 0x01000000;
ab3c759a 7304 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7305
ab3c759a 7306 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7307 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7308}
7309
251ac862
DV		 7310static void chv_compute_dpll(struct intel_crtc *crtc,
7311 struct intel_crtc_state *pipe_config)
1ae0d137 7312{
d288f65f 7313 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7314 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7315 DPLL_VCO_ENABLE;
7316 if (crtc->pipe != PIPE_A)
d288f65f 7317 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7318
d288f65f
VS		 7319 pipe_config->dpll_hw_state.dpll_md =
7320 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7321}
7322
d288f65f 7323static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7324 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7325{
7326 struct drm_device *dev = crtc->base.dev;
7327 struct drm_i915_private *dev_priv = dev->dev_private;
7328 int pipe = crtc->pipe;
7329 int dpll_reg = DPLL(crtc->pipe);
7330 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7331 u32 loopfilter, tribuf_calcntr;
9d556c99 7332 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7333 u32 dpio_val;
9cbe40c1 7334 int vco;
9d556c99 7335
d288f65f
VS		 7336 bestn = pipe_config->dpll.n;
7337 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7338 bestm1 = pipe_config->dpll.m1;
7339 bestm2 = pipe_config->dpll.m2 >> 22;
7340 bestp1 = pipe_config->dpll.p1;
7341 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7342 vco = pipe_config->dpll.vco;
a945ce7e 7343 dpio_val = 0;
9cbe40c1 7344 loopfilter = 0;
9d556c99
CML		 7345
7346 /*
7347 * Enable Refclk and SSC
7348 */
a11b0703 7349 I915_WRITE(dpll_reg,
d288f65f 7350 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7351
a580516d 7352 mutex_lock(&dev_priv->sb_lock);
9d556c99 7353
9d556c99
CML		 7354 /* p1 and p2 divider */
7355 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7356 5 << DPIO_CHV_S1_DIV_SHIFT |
7357 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7358 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7359 1 << DPIO_CHV_K_DIV_SHIFT);
7360
7361 /* Feedback post-divider - m2 */
7362 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7363
7364 /* Feedback refclk divider - n and m1 */
7365 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7366 DPIO_CHV_M1_DIV_BY_2 |
7367 1 << DPIO_CHV_N_DIV_SHIFT);
7368
7369 /* M2 fraction division */
a945ce7e
VP		 7370 if (bestm2_frac)
7371 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7372
7373 /* M2 fraction division enable */
a945ce7e
VP		 7374 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7375 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7376 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7377 if (bestm2_frac)
7378 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7379 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7380
de3a0fde
VP		 7381 /* Program digital lock detect threshold */
7382 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7383 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7384 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7385 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7386 if (!bestm2_frac)
7387 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7388 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7389
9d556c99 7390 /* Loop filter */
9cbe40c1
VP		 7391 if (vco == 5400000) {
7392 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7393 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7394 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7395 tribuf_calcntr = 0x9;
7396 } else if (vco <= 6200000) {
7397 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7398 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7399 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7400 tribuf_calcntr = 0x9;
7401 } else if (vco <= 6480000) {
7402 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7403 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7404 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7405 tribuf_calcntr = 0x8;
7406 } else {
7407 /* Not supported. Apply the same limits as in the max case */
7408 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7409 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7410 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7411 tribuf_calcntr = 0;
7412 }
9d556c99
CML		 7413 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7414
968040b2 7415 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7416 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7417 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7418 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7419
9d556c99
CML		 7420 /* AFC Recal */
7421 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7422 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7423 DPIO_AFC_RECAL);
7424
a580516d 7425 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7426}
7427
d288f65f
VS		 7428/**
7429 * vlv_force_pll_on - forcibly enable just the PLL
7430 * @dev_priv: i915 private structure
7431 * @pipe: pipe PLL to enable
7432 * @dpll: PLL configuration
7433 *
7434 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7435 * in cases where we need the PLL enabled even when @pipe is not going to
7436 * be enabled.
7437 */
7438void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7439 const struct dpll *dpll)
7440{
7441 struct intel_crtc *crtc =
7442 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7443 struct intel_crtc_state pipe_config = {
a93e255f 7444 .base.crtc = &crtc->base,
d288f65f
VS		 7445 .pixel_multiplier = 1,
7446 .dpll = *dpll,
7447 };
7448
7449 if (IS_CHERRYVIEW(dev)) {
251ac862 7450 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7451 chv_prepare_pll(crtc, &pipe_config);
7452 chv_enable_pll(crtc, &pipe_config);
7453 } else {
251ac862 7454 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7455 vlv_prepare_pll(crtc, &pipe_config);
7456 vlv_enable_pll(crtc, &pipe_config);
7457 }
7458}
7459
7460/**
7461 * vlv_force_pll_off - forcibly disable just the PLL
7462 * @dev_priv: i915 private structure
7463 * @pipe: pipe PLL to disable
7464 *
7465 * Disable the PLL for @pipe. To be used in cases where we need
7466 * the PLL enabled even when @pipe is not going to be enabled.
7467 */
7468void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7469{
7470 if (IS_CHERRYVIEW(dev))
7471 chv_disable_pll(to_i915(dev), pipe);
7472 else
7473 vlv_disable_pll(to_i915(dev), pipe);
7474}
7475
251ac862
DV		 7476static void i9xx_compute_dpll(struct intel_crtc *crtc,
7477 struct intel_crtc_state *crtc_state,
7478 intel_clock_t *reduced_clock,
7479 int num_connectors)
eb1cbe48 7480{
f47709a9 7481 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7482 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7483 u32 dpll;
7484 bool is_sdvo;
190f68c5 7485 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7486
190f68c5 7487 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7488
a93e255f
ACO		 7489 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7490 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7491
7492 dpll = DPLL_VGA_MODE_DIS;
7493
a93e255f 7494 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7495 dpll |= DPLLB_MODE_LVDS;
7496 else
7497 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7498
ef1b460d 7499 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7500 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7501 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7502 }
198a037f
DV		 7503
7504 if (is_sdvo)
4a33e48d 7505 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7506
190f68c5 7507 if (crtc_state->has_dp_encoder)
4a33e48d 7508 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7509
7510 /* compute bitmask from p1 value */
7511 if (IS_PINEVIEW(dev))
7512 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7513 else {
7514 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7515 if (IS_G4X(dev) && reduced_clock)
7516 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7517 }
7518 switch (clock->p2) {
7519 case 5:
7520 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7521 break;
7522 case 7:
7523 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7524 break;
7525 case 10:
7526 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7527 break;
7528 case 14:
7529 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7530 break;
7531 }
7532 if (INTEL_INFO(dev)->gen >= 4)
7533 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7534
190f68c5 7535 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7536 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7537 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7538 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7539 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7540 else
7541 dpll |= PLL_REF_INPUT_DREFCLK;
7542
7543 dpll |= DPLL_VCO_ENABLE;
190f68c5 7544 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7545
eb1cbe48 7546 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7547 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7548 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7549 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7550 }
7551}
7552
251ac862
DV		 7553static void i8xx_compute_dpll(struct intel_crtc *crtc,
7554 struct intel_crtc_state *crtc_state,
7555 intel_clock_t *reduced_clock,
7556 int num_connectors)
eb1cbe48 7557{
f47709a9 7558 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7559 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7560 u32 dpll;
190f68c5 7561 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7562
190f68c5 7563 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7564
eb1cbe48
DV		 7565 dpll = DPLL_VGA_MODE_DIS;
7566
a93e255f 7567 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7568 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7569 } else {
7570 if (clock->p1 == 2)
7571 dpll |= PLL_P1_DIVIDE_BY_TWO;
7572 else
7573 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7574 if (clock->p2 == 4)
7575 dpll |= PLL_P2_DIVIDE_BY_4;
7576 }
7577
a93e255f 7578 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7579 dpll |= DPLL_DVO_2X_MODE;
7580
a93e255f 7581 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7582 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7583 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7584 else
7585 dpll |= PLL_REF_INPUT_DREFCLK;
7586
7587 dpll |= DPLL_VCO_ENABLE;
190f68c5 7588 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7589}
7590
8a654f3b 7591static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7592{
7593 struct drm_device *dev = intel_crtc->base.dev;
7594 struct drm_i915_private *dev_priv = dev->dev_private;
7595 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7596 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7597 struct drm_display_mode *adjusted_mode =
6e3c9717 7598 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7599 uint32_t crtc_vtotal, crtc_vblank_end;
7600 int vsyncshift = 0;
4d8a62ea
DV		 7601
7602 /* We need to be careful not to changed the adjusted mode, for otherwise
7603 * the hw state checker will get angry at the mismatch. */
7604 crtc_vtotal = adjusted_mode->crtc_vtotal;
7605 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7606
609aeaca 7607 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7608 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7609 crtc_vtotal -= 1;
7610 crtc_vblank_end -= 1;
609aeaca 7611
409ee761 7612 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7613 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7614 else
7615 vsyncshift = adjusted_mode->crtc_hsync_start -
7616 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7617 if (vsyncshift < 0)
7618 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7619 }
7620
7621 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7622 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7623
fe2b8f9d 7624 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7625 (adjusted_mode->crtc_hdisplay - 1) |
7626 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7627 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7628 (adjusted_mode->crtc_hblank_start - 1) |
7629 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7630 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7631 (adjusted_mode->crtc_hsync_start - 1) |
7632 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7633
fe2b8f9d 7634 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7635 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7636 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7637 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7638 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7639 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7640 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7641 (adjusted_mode->crtc_vsync_start - 1) |
7642 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7643
b5e508d4
PZ		 7644 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7645 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7646 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7647 * bits. */
7648 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7649 (pipe == PIPE_B || pipe == PIPE_C))
7650 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7651
b0e77b9c
PZ		 7652 /* pipesrc controls the size that is scaled from, which should
7653 * always be the user's requested size.
7654 */
7655 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7656 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7657 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7658}
7659
1bd1bd80 7660static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7661 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7662{
7663 struct drm_device *dev = crtc->base.dev;
7664 struct drm_i915_private *dev_priv = dev->dev_private;
7665 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7666 uint32_t tmp;
7667
7668 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7669 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7670 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7671 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7672 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7673 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7674 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7675 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7676 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7677
7678 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7679 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7680 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7681 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7682 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7683 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7684 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7685 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7686 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7687
7688 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7689 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7690 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7691 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7692 }
7693
7694 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7695 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7696 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7697
2d112de7
ACO		 7698 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7699 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7700}
7701
f6a83288 7702void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7703 struct intel_crtc_state *pipe_config)
babea61d 7704{
2d112de7
ACO		 7705 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7706 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7707 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7708 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7709
2d112de7
ACO		 7710 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7711 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7712 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7713 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7714
2d112de7 7715 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7716
2d112de7
ACO		 7717 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7718 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7719}
7720
84b046f3
DV		 7721static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7722{
7723 struct drm_device *dev = intel_crtc->base.dev;
7724 struct drm_i915_private *dev_priv = dev->dev_private;
7725 uint32_t pipeconf;
7726
9f11a9e4 7727 pipeconf = 0;
84b046f3 7728
b6b5d049
VS		 7729 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7730 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7731 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7732
6e3c9717 7733 if (intel_crtc->config->double_wide)
cf532bb2 7734 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7735
ff9ce46e
DV		 7736 /* only g4x and later have fancy bpc/dither controls */
7737 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7738 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7739 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7740 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7741 PIPECONF_DITHER_TYPE_SP;
84b046f3 7742
6e3c9717 7743 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7744 case 18:
7745 pipeconf |= PIPECONF_6BPC;
7746 break;
7747 case 24:
7748 pipeconf |= PIPECONF_8BPC;
7749 break;
7750 case 30:
7751 pipeconf |= PIPECONF_10BPC;
7752 break;
7753 default:
7754 /* Case prevented by intel_choose_pipe_bpp_dither. */
7755 BUG();
84b046f3
DV		 7756 }
7757 }
7758
7759 if (HAS_PIPE_CXSR(dev)) {
7760 if (intel_crtc->lowfreq_avail) {
7761 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7762 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7763 } else {
7764 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7765 }
7766 }
7767
6e3c9717 7768 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7769 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7770 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7771 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7772 else
7773 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7774 } else
84b046f3
DV		 7775 pipeconf |= PIPECONF_PROGRESSIVE;
7776
6e3c9717 7777 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7778 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7779
84b046f3
DV		 7780 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7781 POSTING_READ(PIPECONF(intel_crtc->pipe));
7782}
7783
190f68c5
ACO		 7784static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7785 struct intel_crtc_state *crtc_state)
79e53945 7786{
c7653199 7787 struct drm_device *dev = crtc->base.dev;
79e53945 7788 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7789 int refclk, num_connectors = 0;
c329a4ec
DV		 7790 intel_clock_t clock;
7791 bool ok;
7792 bool is_dsi = false;
5eddb70b 7793 struct intel_encoder *encoder;
d4906093 7794 const intel_limit_t *limit;
55bb9992 7795 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7796 struct drm_connector *connector;
55bb9992
ACO		 7797 struct drm_connector_state *connector_state;
7798 int i;
79e53945 7799
dd3cd74a
ACO		 7800 memset(&crtc_state->dpll_hw_state, 0,
7801 sizeof(crtc_state->dpll_hw_state));
7802
da3ced29 7803 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7804 if (connector_state->crtc != &crtc->base)
7805 continue;
7806
7807 encoder = to_intel_encoder(connector_state->best_encoder);
7808
5eddb70b 7809 switch (encoder->type) {
e9fd1c02
JN		 7810 case INTEL_OUTPUT_DSI:
7811 is_dsi = true;
7812 break;
6847d71b
PZ		 7813 default:
7814 break;
79e53945 7815 }
43565a06 7816
c751ce4f 7817 num_connectors++;
79e53945
JB		 7818 }
7819
f2335330 7820 if (is_dsi)
5b18e57c 7821 return 0;
f2335330 7822
190f68c5 7823 if (!crtc_state->clock_set) {
a93e255f 7824 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7825
e9fd1c02
JN		 7826 /*
7827 * Returns a set of divisors for the desired target clock with
7828 * the given refclk, or FALSE. The returned values represent
7829 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7830 * 2) / p1 / p2.
7831 */
a93e255f
ACO		 7832 limit = intel_limit(crtc_state, refclk);
7833 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7834 crtc_state->port_clock,
e9fd1c02 7835 refclk, NULL, &clock);
f2335330 7836 if (!ok) {
e9fd1c02
JN		 7837 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7838 return -EINVAL;
7839 }
79e53945 7840
f2335330 7841 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7842 crtc_state->dpll.n = clock.n;
7843 crtc_state->dpll.m1 = clock.m1;
7844 crtc_state->dpll.m2 = clock.m2;
7845 crtc_state->dpll.p1 = clock.p1;
7846 crtc_state->dpll.p2 = clock.p2;
f47709a9 7847 }
7026d4ac 7848
e9fd1c02 7849 if (IS_GEN2(dev)) {
c329a4ec 7850 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7851 num_connectors);
9d556c99 7852 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7853 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7854 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7855 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7856 } else {
c329a4ec 7857 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7858 num_connectors);
e9fd1c02 7859 }
79e53945 7860
c8f7a0db 7861 return 0;
f564048e
EA		 7862}
7863
2fa2fe9a 7864static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7865 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7866{
7867 struct drm_device *dev = crtc->base.dev;
7868 struct drm_i915_private *dev_priv = dev->dev_private;
7869 uint32_t tmp;
7870
dc9e7dec
VS		 7871 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7872 return;
7873
2fa2fe9a 7874 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7875 if (!(tmp & PFIT_ENABLE))
7876 return;
2fa2fe9a 7877
06922821 7878 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7879 if (INTEL_INFO(dev)->gen < 4) {
7880 if (crtc->pipe != PIPE_B)
7881 return;
2fa2fe9a
DV		 7882 } else {
7883 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7884 return;
7885 }
7886
06922821 7887 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7888 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7889 if (INTEL_INFO(dev)->gen < 5)
7890 pipe_config->gmch_pfit.lvds_border_bits =
7891 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7892}
7893
acbec814 7894static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7895 struct intel_crtc_state *pipe_config)
acbec814
JB		 7896{
7897 struct drm_device *dev = crtc->base.dev;
7898 struct drm_i915_private *dev_priv = dev->dev_private;
7899 int pipe = pipe_config->cpu_transcoder;
7900 intel_clock_t clock;
7901 u32 mdiv;
662c6ecb 7902 int refclk = 100000;
acbec814 7903
f573de5a
SK		 7904 /* In case of MIPI DPLL will not even be used */
7905 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7906 return;
7907
a580516d 7908 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7909 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7910 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7911
7912 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7913 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7914 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7915 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7916 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7917
f646628b 7918 vlv_clock(refclk, &clock);
acbec814 7919
f646628b
VS		 7920 /* clock.dot is the fast clock */
7921 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7922}
7923
5724dbd1
DL		 7924static void
7925i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7926 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7927{
7928 struct drm_device *dev = crtc->base.dev;
7929 struct drm_i915_private *dev_priv = dev->dev_private;
7930 u32 val, base, offset;
7931 int pipe = crtc->pipe, plane = crtc->plane;
7932 int fourcc, pixel_format;
6761dd31 7933 unsigned int aligned_height;
b113d5ee 7934 struct drm_framebuffer *fb;
1b842c89 7935 struct intel_framebuffer *intel_fb;
1ad292b5 7936
42a7b088
DL		 7937 val = I915_READ(DSPCNTR(plane));
7938 if (!(val & DISPLAY_PLANE_ENABLE))
7939 return;
7940
d9806c9f 7941 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7942 if (!intel_fb) {
1ad292b5
JB		 7943 DRM_DEBUG_KMS("failed to alloc fb\n");
7944 return;
7945 }
7946
1b842c89
DL		 7947 fb = &intel_fb->base;
7948
18c5247e
DV		 7949 if (INTEL_INFO(dev)->gen >= 4) {
7950 if (val & DISPPLANE_TILED) {
49af449b 7951 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7952 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7953 }
7954 }
1ad292b5
JB		 7955
7956 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7957 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7958 fb->pixel_format = fourcc;
7959 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7960
7961 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7962 if (plane_config->tiling)
1ad292b5
JB		 7963 offset = I915_READ(DSPTILEOFF(plane));
7964 else
7965 offset = I915_READ(DSPLINOFF(plane));
7966 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7967 } else {
7968 base = I915_READ(DSPADDR(plane));
7969 }
7970 plane_config->base = base;
7971
7972 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7973 fb->width = ((val >> 16) & 0xfff) + 1;
7974 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7975
7976 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7977 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7978
b113d5ee 7979 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7980 fb->pixel_format,
7981 fb->modifier[0]);
1ad292b5 7982
f37b5c2b 7983 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7984
2844a921
DL		 7985 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7986 pipe_name(pipe), plane, fb->width, fb->height,
7987 fb->bits_per_pixel, base, fb->pitches[0],
7988 plane_config->size);
1ad292b5 7989
2d14030b 7990 plane_config->fb = intel_fb;
1ad292b5
JB		 7991}
7992
70b23a98 7993static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7994 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7995{
7996 struct drm_device *dev = crtc->base.dev;
7997 struct drm_i915_private *dev_priv = dev->dev_private;
7998 int pipe = pipe_config->cpu_transcoder;
7999 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8000 intel_clock_t clock;
8001 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8002 int refclk = 100000;
8003
a580516d 8004 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8005 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8006 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8007 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8008 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8009 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8010
8011 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8012 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8013 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8014 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8015 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8016
8017 chv_clock(refclk, &clock);
8018
8019 /* clock.dot is the fast clock */
8020 pipe_config->port_clock = clock.dot / 5;
8021}
8022
0e8ffe1b 8023static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8024 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8025{
8026 struct drm_device *dev = crtc->base.dev;
8027 struct drm_i915_private *dev_priv = dev->dev_private;
8028 uint32_t tmp;
8029
f458ebbc
DV		 8030 if (!intel_display_power_is_enabled(dev_priv,
8031 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8032 return false;
8033
e143a21c 8034 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8035 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8036
0e8ffe1b
DV		 8037 tmp = I915_READ(PIPECONF(crtc->pipe));
8038 if (!(tmp & PIPECONF_ENABLE))
8039 return false;
8040
42571aef
VS		 8041 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8042 switch (tmp & PIPECONF_BPC_MASK) {
8043 case PIPECONF_6BPC:
8044 pipe_config->pipe_bpp = 18;
8045 break;
8046 case PIPECONF_8BPC:
8047 pipe_config->pipe_bpp = 24;
8048 break;
8049 case PIPECONF_10BPC:
8050 pipe_config->pipe_bpp = 30;
8051 break;
8052 default:
8053 break;
8054 }
8055 }
8056
b5a9fa09
DV		 8057 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8058 pipe_config->limited_color_range = true;
8059
282740f7
VS		 8060 if (INTEL_INFO(dev)->gen < 4)
8061 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8062
1bd1bd80
DV		 8063 intel_get_pipe_timings(crtc, pipe_config);
8064
2fa2fe9a
DV		 8065 i9xx_get_pfit_config(crtc, pipe_config);
8066
6c49f241
DV		 8067 if (INTEL_INFO(dev)->gen >= 4) {
8068 tmp = I915_READ(DPLL_MD(crtc->pipe));
8069 pipe_config->pixel_multiplier =
8070 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8071 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8072 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8073 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8074 tmp = I915_READ(DPLL(crtc->pipe));
8075 pipe_config->pixel_multiplier =
8076 ((tmp & SDVO_MULTIPLIER_MASK)
8077 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8078 } else {
8079 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8080 * port and will be fixed up in the encoder->get_config
8081 * function. */
8082 pipe_config->pixel_multiplier = 1;
8083 }
8bcc2795
DV		 8084 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8085 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8086 /*
8087 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8088 * on 830. Filter it out here so that we don't
8089 * report errors due to that.
8090 */
8091 if (IS_I830(dev))
8092 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8093
8bcc2795
DV		 8094 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8095 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8096 } else {
8097 /* Mask out read-only status bits. */
8098 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8099 DPLL_PORTC_READY_MASK |
8100 DPLL_PORTB_READY_MASK);
8bcc2795 8101 }
6c49f241 8102
70b23a98
VS		 8103 if (IS_CHERRYVIEW(dev))
8104 chv_crtc_clock_get(crtc, pipe_config);
8105 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8106 vlv_crtc_clock_get(crtc, pipe_config);
8107 else
8108 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8109
0e8ffe1b
DV		 8110 return true;
8111}
8112
dde86e2d 8113static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8114{
8115 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8116 struct intel_encoder *encoder;
74cfd7ac 8117 u32 val, final;
13d83a67 8118 bool has_lvds = false;
199e5d79 8119 bool has_cpu_edp = false;
199e5d79 8120 bool has_panel = false;
99eb6a01
KP		 8121 bool has_ck505 = false;
8122 bool can_ssc = false;
13d83a67
JB		 8123
8124 /* We need to take the global config into account */
b2784e15 8125 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8126 switch (encoder->type) {
8127 case INTEL_OUTPUT_LVDS:
8128 has_panel = true;
8129 has_lvds = true;
8130 break;
8131 case INTEL_OUTPUT_EDP:
8132 has_panel = true;
2de6905f 8133 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8134 has_cpu_edp = true;
8135 break;
6847d71b
PZ		 8136 default:
8137 break;
13d83a67
JB		 8138 }
8139 }
8140
99eb6a01 8141 if (HAS_PCH_IBX(dev)) {
41aa3448 8142 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8143 can_ssc = has_ck505;
8144 } else {
8145 has_ck505 = false;
8146 can_ssc = true;
8147 }
8148
2de6905f
ID		 8149 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8150 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8151
8152 /* Ironlake: try to setup display ref clock before DPLL
8153 * enabling. This is only under driver's control after
8154 * PCH B stepping, previous chipset stepping should be
8155 * ignoring this setting.
8156 */
74cfd7ac
CW		 8157 val = I915_READ(PCH_DREF_CONTROL);
8158
8159 /* As we must carefully and slowly disable/enable each source in turn,
8160 * compute the final state we want first and check if we need to
8161 * make any changes at all.
8162 */
8163 final = val;
8164 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8165 if (has_ck505)
8166 final |= DREF_NONSPREAD_CK505_ENABLE;
8167 else
8168 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8169
8170 final &= ~DREF_SSC_SOURCE_MASK;
8171 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8172 final &= ~DREF_SSC1_ENABLE;
8173
8174 if (has_panel) {
8175 final |= DREF_SSC_SOURCE_ENABLE;
8176
8177 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8178 final |= DREF_SSC1_ENABLE;
8179
8180 if (has_cpu_edp) {
8181 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8182 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8183 else
8184 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8185 } else
8186 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8187 } else {
8188 final |= DREF_SSC_SOURCE_DISABLE;
8189 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8190 }
8191
8192 if (final == val)
8193 return;
8194
13d83a67 8195 /* Always enable nonspread source */
74cfd7ac 8196 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8197
99eb6a01 8198 if (has_ck505)
74cfd7ac 8199 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8200 else
74cfd7ac 8201 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8202
199e5d79 8203 if (has_panel) {
74cfd7ac
CW		 8204 val &= ~DREF_SSC_SOURCE_MASK;
8205 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8206
199e5d79 8207 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8208 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8209 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8210 val |= DREF_SSC1_ENABLE;
e77166b5 8211 } else
74cfd7ac 8212 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8213
8214 /* Get SSC going before enabling the outputs */
74cfd7ac 8215 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8216 POSTING_READ(PCH_DREF_CONTROL);
8217 udelay(200);
8218
74cfd7ac 8219 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8220
8221 /* Enable CPU source on CPU attached eDP */
199e5d79 8222 if (has_cpu_edp) {
99eb6a01 8223 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8224 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8225 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8226 } else
74cfd7ac 8227 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8228 } else
74cfd7ac 8229 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8230
74cfd7ac 8231 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8232 POSTING_READ(PCH_DREF_CONTROL);
8233 udelay(200);
8234 } else {
8235 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8236
74cfd7ac 8237 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8238
8239 /* Turn off CPU output */
74cfd7ac 8240 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8241
74cfd7ac 8242 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8243 POSTING_READ(PCH_DREF_CONTROL);
8244 udelay(200);
8245
8246 /* Turn off the SSC source */
74cfd7ac
CW		 8247 val &= ~DREF_SSC_SOURCE_MASK;
8248 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8249
8250 /* Turn off SSC1 */
74cfd7ac 8251 val &= ~DREF_SSC1_ENABLE;
199e5d79 8252
74cfd7ac 8253 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8254 POSTING_READ(PCH_DREF_CONTROL);
8255 udelay(200);
8256 }
74cfd7ac
CW		 8257
8258 BUG_ON(val != final);
13d83a67
JB		 8259}
8260
f31f2d55 8261static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8262{
f31f2d55 8263 uint32_t tmp;
dde86e2d 8264
0ff066a9
PZ		 8265 tmp = I915_READ(SOUTH_CHICKEN2);
8266 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8267 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8268
0ff066a9
PZ		 8269 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8270 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8271 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8272
0ff066a9
PZ		 8273 tmp = I915_READ(SOUTH_CHICKEN2);
8274 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8275 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8276
0ff066a9
PZ		 8277 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8278 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8279 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8280}
8281
8282/* WaMPhyProgramming:hsw */
8283static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8284{
8285 uint32_t tmp;
dde86e2d
PZ		 8286
8287 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8288 tmp &= ~(0xFF << 24);
8289 tmp |= (0x12 << 24);
8290 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8291
dde86e2d
PZ		 8292 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8293 tmp |= (1 << 11);
8294 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8295
8296 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8297 tmp |= (1 << 11);
8298 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8299
dde86e2d
PZ		 8300 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8301 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8302 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8303
8304 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8305 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8306 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8307
0ff066a9
PZ		 8308 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8309 tmp &= ~(7 << 13);
8310 tmp |= (5 << 13);
8311 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8312
0ff066a9
PZ		 8313 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8314 tmp &= ~(7 << 13);
8315 tmp |= (5 << 13);
8316 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8317
8318 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8319 tmp &= ~0xFF;
8320 tmp |= 0x1C;
8321 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8322
8323 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8324 tmp &= ~0xFF;
8325 tmp |= 0x1C;
8326 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8327
8328 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8329 tmp &= ~(0xFF << 16);
8330 tmp |= (0x1C << 16);
8331 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8332
8333 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8334 tmp &= ~(0xFF << 16);
8335 tmp |= (0x1C << 16);
8336 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8337
0ff066a9
PZ		 8338 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8339 tmp |= (1 << 27);
8340 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8341
0ff066a9
PZ		 8342 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8343 tmp |= (1 << 27);
8344 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8345
0ff066a9
PZ		 8346 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8347 tmp &= ~(0xF << 28);
8348 tmp |= (4 << 28);
8349 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8350
0ff066a9
PZ		 8351 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8352 tmp &= ~(0xF << 28);
8353 tmp |= (4 << 28);
8354 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8355}
8356
2fa86a1f
PZ		 8357/* Implements 3 different sequences from BSpec chapter "Display iCLK
8358 * Programming" based on the parameters passed:
8359 * - Sequence to enable CLKOUT_DP
8360 * - Sequence to enable CLKOUT_DP without spread
8361 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8362 */
8363static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8364 bool with_fdi)
f31f2d55
PZ		 8365{
8366 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8367 uint32_t reg, tmp;
8368
8369 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8370 with_spread = true;
8371 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8372 with_fdi, "LP PCH doesn't have FDI\n"))
8373 with_fdi = false;
f31f2d55 8374
a580516d 8375 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8376
8377 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8378 tmp &= ~SBI_SSCCTL_DISABLE;
8379 tmp |= SBI_SSCCTL_PATHALT;
8380 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8381
8382 udelay(24);
8383
2fa86a1f
PZ		 8384 if (with_spread) {
8385 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8386 tmp &= ~SBI_SSCCTL_PATHALT;
8387 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8388
2fa86a1f
PZ		 8389 if (with_fdi) {
8390 lpt_reset_fdi_mphy(dev_priv);
8391 lpt_program_fdi_mphy(dev_priv);
8392 }
8393 }
dde86e2d 8394
2fa86a1f
PZ		 8395 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8396 SBI_GEN0 : SBI_DBUFF0;
8397 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8398 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8399 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8400
a580516d 8401 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8402}
8403
47701c3b
PZ		 8404/* Sequence to disable CLKOUT_DP */
8405static void lpt_disable_clkout_dp(struct drm_device *dev)
8406{
8407 struct drm_i915_private *dev_priv = dev->dev_private;
8408 uint32_t reg, tmp;
8409
a580516d 8410 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8411
8412 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8413 SBI_GEN0 : SBI_DBUFF0;
8414 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8415 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8416 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8417
8418 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8419 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8420 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8421 tmp |= SBI_SSCCTL_PATHALT;
8422 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8423 udelay(32);
8424 }
8425 tmp |= SBI_SSCCTL_DISABLE;
8426 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8427 }
8428
a580516d 8429 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8430}
8431
bf8fa3d3
PZ		 8432static void lpt_init_pch_refclk(struct drm_device *dev)
8433{
bf8fa3d3
PZ		 8434 struct intel_encoder *encoder;
8435 bool has_vga = false;
8436
b2784e15 8437 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8438 switch (encoder->type) {
8439 case INTEL_OUTPUT_ANALOG:
8440 has_vga = true;
8441 break;
6847d71b
PZ		 8442 default:
8443 break;
bf8fa3d3
PZ		 8444 }
8445 }
8446
47701c3b
PZ		 8447 if (has_vga)
8448 lpt_enable_clkout_dp(dev, true, true);
8449 else
8450 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8451}
8452
dde86e2d
PZ		 8453/*
8454 * Initialize reference clocks when the driver loads
8455 */
8456void intel_init_pch_refclk(struct drm_device *dev)
8457{
8458 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8459 ironlake_init_pch_refclk(dev);
8460 else if (HAS_PCH_LPT(dev))
8461 lpt_init_pch_refclk(dev);
8462}
8463
55bb9992 8464static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8465{
55bb9992 8466 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8467 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8468 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8469 struct drm_connector *connector;
55bb9992 8470 struct drm_connector_state *connector_state;
d9d444cb 8471 struct intel_encoder *encoder;
55bb9992 8472 int num_connectors = 0, i;
d9d444cb
JB		 8473 bool is_lvds = false;
8474
da3ced29 8475 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8476 if (connector_state->crtc != crtc_state->base.crtc)
8477 continue;
8478
8479 encoder = to_intel_encoder(connector_state->best_encoder);
8480
d9d444cb
JB		 8481 switch (encoder->type) {
8482 case INTEL_OUTPUT_LVDS:
8483 is_lvds = true;
8484 break;
6847d71b
PZ		 8485 default:
8486 break;
d9d444cb
JB		 8487 }
8488 num_connectors++;
8489 }
8490
8491 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8492 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8493 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8494 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8495 }
8496
8497 return 120000;
8498}
8499
6ff93609 8500static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8501{
c8203565 8502 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8504 int pipe = intel_crtc->pipe;
c8203565
PZ		 8505 uint32_t val;
8506
78114071 8507 val = 0;
c8203565 8508
6e3c9717 8509 switch (intel_crtc->config->pipe_bpp) {
c8203565 8510 case 18:
dfd07d72 8511 val |= PIPECONF_6BPC;
c8203565
PZ		 8512 break;
8513 case 24:
dfd07d72 8514 val |= PIPECONF_8BPC;
c8203565
PZ		 8515 break;
8516 case 30:
dfd07d72 8517 val |= PIPECONF_10BPC;
c8203565
PZ		 8518 break;
8519 case 36:
dfd07d72 8520 val |= PIPECONF_12BPC;
c8203565
PZ		 8521 break;
8522 default:
cc769b62
PZ		 8523 /* Case prevented by intel_choose_pipe_bpp_dither. */
8524 BUG();
c8203565
PZ		 8525 }
8526
6e3c9717 8527 if (intel_crtc->config->dither)
c8203565
PZ		 8528 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8529
6e3c9717 8530 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8531 val |= PIPECONF_INTERLACED_ILK;
8532 else
8533 val |= PIPECONF_PROGRESSIVE;
8534
6e3c9717 8535 if (intel_crtc->config->limited_color_range)
3685a8f3 8536 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8537
c8203565
PZ		 8538 I915_WRITE(PIPECONF(pipe), val);
8539 POSTING_READ(PIPECONF(pipe));
8540}
8541
86d3efce
VS		 8542/*
8543 * Set up the pipe CSC unit.
8544 *
8545 * Currently only full range RGB to limited range RGB conversion
8546 * is supported, but eventually this should handle various
8547 * RGB<->YCbCr scenarios as well.
8548 */
50f3b016 8549static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8550{
8551 struct drm_device *dev = crtc->dev;
8552 struct drm_i915_private *dev_priv = dev->dev_private;
8553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8554 int pipe = intel_crtc->pipe;
8555 uint16_t coeff = 0x7800; /* 1.0 */
8556
8557 /*
8558 * TODO: Check what kind of values actually come out of the pipe
8559 * with these coeff/postoff values and adjust to get the best
8560 * accuracy. Perhaps we even need to take the bpc value into
8561 * consideration.
8562 */
8563
6e3c9717 8564 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8565 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8566
8567 /*
8568 * GY/GU and RY/RU should be the other way around according
8569 * to BSpec, but reality doesn't agree. Just set them up in
8570 * a way that results in the correct picture.
8571 */
8572 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8573 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8574
8575 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8576 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8577
8578 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8579 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8580
8581 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8582 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8583 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8584
8585 if (INTEL_INFO(dev)->gen > 6) {
8586 uint16_t postoff = 0;
8587
6e3c9717 8588 if (intel_crtc->config->limited_color_range)
32cf0cb0 8589 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8590
8591 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8592 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8593 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8594
8595 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8596 } else {
8597 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8598
6e3c9717 8599 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8600 mode |= CSC_BLACK_SCREEN_OFFSET;
8601
8602 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8603 }
8604}
8605
6ff93609 8606static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8607{
756f85cf
PZ		 8608 struct drm_device *dev = crtc->dev;
8609 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8611 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8612 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8613 uint32_t val;
8614
3eff4faa 8615 val = 0;
ee2b0b38 8616
6e3c9717 8617 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8618 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8619
6e3c9717 8620 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8621 val |= PIPECONF_INTERLACED_ILK;
8622 else
8623 val |= PIPECONF_PROGRESSIVE;
8624
702e7a56
PZ		 8625 I915_WRITE(PIPECONF(cpu_transcoder), val);
8626 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8627
8628 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8629 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8630
3cdf122c 8631 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8632 val = 0;
8633
6e3c9717 8634 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8635 case 18:
8636 val |= PIPEMISC_DITHER_6_BPC;
8637 break;
8638 case 24:
8639 val |= PIPEMISC_DITHER_8_BPC;
8640 break;
8641 case 30:
8642 val |= PIPEMISC_DITHER_10_BPC;
8643 break;
8644 case 36:
8645 val |= PIPEMISC_DITHER_12_BPC;
8646 break;
8647 default:
8648 /* Case prevented by pipe_config_set_bpp. */
8649 BUG();
8650 }
8651
6e3c9717 8652 if (intel_crtc->config->dither)
756f85cf
PZ		 8653 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8654
8655 I915_WRITE(PIPEMISC(pipe), val);
8656 }
ee2b0b38
PZ		 8657}
8658
6591c6e4 8659static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8660 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8661 intel_clock_t *clock,
8662 bool *has_reduced_clock,
8663 intel_clock_t *reduced_clock)
8664{
8665 struct drm_device *dev = crtc->dev;
8666 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8667 int refclk;
d4906093 8668 const intel_limit_t *limit;
c329a4ec 8669 bool ret;
79e53945 8670
55bb9992 8671 refclk = ironlake_get_refclk(crtc_state);
79e53945 8672
d4906093
ML		 8673 /*
8674 * Returns a set of divisors for the desired target clock with the given
8675 * refclk, or FALSE. The returned values represent the clock equation:
8676 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8677 */
a93e255f
ACO		 8678 limit = intel_limit(crtc_state, refclk);
8679 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8680 crtc_state->port_clock,
ee9300bb 8681 refclk, NULL, clock);
6591c6e4
PZ		 8682 if (!ret)
8683 return false;
cda4b7d3 8684
6591c6e4
PZ		 8685 return true;
8686}
8687
d4b1931c
PZ		 8688int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8689{
8690 /*
8691 * Account for spread spectrum to avoid
8692 * oversubscribing the link. Max center spread
8693 * is 2.5%; use 5% for safety's sake.
8694 */
8695 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8696 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8697}
8698
7429e9d4 8699static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8700{
7429e9d4 8701 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8702}
8703
de13a2e3 8704static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8705 struct intel_crtc_state *crtc_state,
7429e9d4 8706 u32 *fp,
9a7c7890 8707 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8708{
de13a2e3 8709 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8710 struct drm_device *dev = crtc->dev;
8711 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8712 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8713 struct drm_connector *connector;
55bb9992
ACO		 8714 struct drm_connector_state *connector_state;
8715 struct intel_encoder *encoder;
de13a2e3 8716 uint32_t dpll;
55bb9992 8717 int factor, num_connectors = 0, i;
09ede541 8718 bool is_lvds = false, is_sdvo = false;
79e53945 8719
da3ced29 8720 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8721 if (connector_state->crtc != crtc_state->base.crtc)
8722 continue;
8723
8724 encoder = to_intel_encoder(connector_state->best_encoder);
8725
8726 switch (encoder->type) {
79e53945
JB		 8727 case INTEL_OUTPUT_LVDS:
8728 is_lvds = true;
8729 break;
8730 case INTEL_OUTPUT_SDVO:
7d57382e 8731 case INTEL_OUTPUT_HDMI:
79e53945 8732 is_sdvo = true;
79e53945 8733 break;
6847d71b
PZ		 8734 default:
8735 break;
79e53945 8736 }
43565a06 8737
c751ce4f 8738 num_connectors++;
79e53945 8739 }
79e53945 8740
c1858123 8741 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8742 factor = 21;
8743 if (is_lvds) {
8744 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8745 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8746 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8747 factor = 25;
190f68c5 8748 } else if (crtc_state->sdvo_tv_clock)
8febb297 8749 factor = 20;
c1858123 8750
190f68c5 8751 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8752 *fp |= FP_CB_TUNE;
2c07245f 8753
9a7c7890
DV		 8754 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8755 *fp2 |= FP_CB_TUNE;
8756
5eddb70b 8757 dpll = 0;
2c07245f 8758
a07d6787
EA		 8759 if (is_lvds)
8760 dpll |= DPLLB_MODE_LVDS;
8761 else
8762 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8763
190f68c5 8764 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8765 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8766
8767 if (is_sdvo)
4a33e48d 8768 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8769 if (crtc_state->has_dp_encoder)
4a33e48d 8770 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8771
a07d6787 8772 /* compute bitmask from p1 value */
190f68c5 8773 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8774 /* also FPA1 */
190f68c5 8775 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8776
190f68c5 8777 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8778 case 5:
8779 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8780 break;
8781 case 7:
8782 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8783 break;
8784 case 10:
8785 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8786 break;
8787 case 14:
8788 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8789 break;
79e53945
JB		 8790 }
8791
b4c09f3b 8792 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8793 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8794 else
8795 dpll |= PLL_REF_INPUT_DREFCLK;
8796
959e16d6 8797 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8798}
8799
190f68c5
ACO		 8800static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8801 struct intel_crtc_state *crtc_state)
de13a2e3 8802{
c7653199 8803 struct drm_device *dev = crtc->base.dev;
de13a2e3 8804 intel_clock_t clock, reduced_clock;
cbbab5bd 8805 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8806 bool ok, has_reduced_clock = false;
8b47047b 8807 bool is_lvds = false;
e2b78267 8808 struct intel_shared_dpll *pll;
de13a2e3 8809
dd3cd74a
ACO		 8810 memset(&crtc_state->dpll_hw_state, 0,
8811 sizeof(crtc_state->dpll_hw_state));
8812
409ee761 8813 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8814
5dc5298b
PZ		 8815 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8816 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8817
190f68c5 8818 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8819 &has_reduced_clock, &reduced_clock);
190f68c5 8820 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8821 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8822 return -EINVAL;
79e53945 8823 }
f47709a9 8824 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8825 if (!crtc_state->clock_set) {
8826 crtc_state->dpll.n = clock.n;
8827 crtc_state->dpll.m1 = clock.m1;
8828 crtc_state->dpll.m2 = clock.m2;
8829 crtc_state->dpll.p1 = clock.p1;
8830 crtc_state->dpll.p2 = clock.p2;
f47709a9 8831 }
79e53945 8832
5dc5298b 8833 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8834 if (crtc_state->has_pch_encoder) {
8835 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8836 if (has_reduced_clock)
7429e9d4 8837 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8838
190f68c5 8839 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8840 &fp, &reduced_clock,
8841 has_reduced_clock ? &fp2 : NULL);
8842
190f68c5
ACO		 8843 crtc_state->dpll_hw_state.dpll = dpll;
8844 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8845 if (has_reduced_clock)
190f68c5 8846 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8847 else
190f68c5 8848 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8849
190f68c5 8850 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8851 if (pll == NULL) {
84f44ce7 8852 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8853 pipe_name(crtc->pipe));
4b645f14
JB		 8854 return -EINVAL;
8855 }
3fb37703 8856 }
79e53945 8857
ab585dea 8858 if (is_lvds && has_reduced_clock)
c7653199 8859 crtc->lowfreq_avail = true;
bcd644e0 8860 else
c7653199 8861 crtc->lowfreq_avail = false;
e2b78267 8862
c8f7a0db 8863 return 0;
79e53945
JB		 8864}
8865
eb14cb74
VS		 8866static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8867 struct intel_link_m_n *m_n)
8868{
8869 struct drm_device *dev = crtc->base.dev;
8870 struct drm_i915_private *dev_priv = dev->dev_private;
8871 enum pipe pipe = crtc->pipe;
8872
8873 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8874 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8875 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8876 & ~TU_SIZE_MASK;
8877 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8878 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8879 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8880}
8881
8882static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8883 enum transcoder transcoder,
b95af8be
VK		 8884 struct intel_link_m_n *m_n,
8885 struct intel_link_m_n *m2_n2)
72419203
DV		 8886{
8887 struct drm_device *dev = crtc->base.dev;
8888 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8889 enum pipe pipe = crtc->pipe;
72419203 8890
eb14cb74
VS		 8891 if (INTEL_INFO(dev)->gen >= 5) {
8892 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8893 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8894 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8895 & ~TU_SIZE_MASK;
8896 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8897 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8898 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8899 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8900 * gen < 8) and if DRRS is supported (to make sure the
8901 * registers are not unnecessarily read).
8902 */
8903 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8904 crtc->config->has_drrs) {
b95af8be
VK		 8905 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8906 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8907 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8908 & ~TU_SIZE_MASK;
8909 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8910 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8911 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8912 }
eb14cb74
VS		 8913 } else {
8914 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8915 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8916 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8917 & ~TU_SIZE_MASK;
8918 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8919 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8920 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8921 }
8922}
8923
8924void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8925 struct intel_crtc_state *pipe_config)
eb14cb74 8926{
681a8504 8927 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8928 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8929 else
8930 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8931 &pipe_config->dp_m_n,
8932 &pipe_config->dp_m2_n2);
eb14cb74 8933}
72419203 8934
eb14cb74 8935static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8936 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8937{
8938 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8939 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8940}
8941
bd2e244f 8942static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8943 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8944{
8945 struct drm_device *dev = crtc->base.dev;
8946 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8947 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8948 uint32_t ps_ctrl = 0;
8949 int id = -1;
8950 int i;
bd2e244f 8951
a1b2278e
CK		 8952 /* find scaler attached to this pipe */
8953 for (i = 0; i < crtc->num_scalers; i++) {
8954 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8955 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8956 id = i;
8957 pipe_config->pch_pfit.enabled = true;
8958 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8959 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8960 break;
8961 }
8962 }
bd2e244f 8963
a1b2278e
CK		 8964 scaler_state->scaler_id = id;
8965 if (id >= 0) {
8966 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8967 } else {
8968 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8969 }
8970}
8971
5724dbd1
DL		 8972static void
8973skylake_get_initial_plane_config(struct intel_crtc *crtc,
8974 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8975{
8976 struct drm_device *dev = crtc->base.dev;
8977 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8978 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8979 int pipe = crtc->pipe;
8980 int fourcc, pixel_format;
6761dd31 8981 unsigned int aligned_height;
bc8d7dff 8982 struct drm_framebuffer *fb;
1b842c89 8983 struct intel_framebuffer *intel_fb;
bc8d7dff 8984
d9806c9f 8985 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8986 if (!intel_fb) {
bc8d7dff
DL		 8987 DRM_DEBUG_KMS("failed to alloc fb\n");
8988 return;
8989 }
8990
1b842c89
DL		 8991 fb = &intel_fb->base;
8992
bc8d7dff 8993 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8994 if (!(val & PLANE_CTL_ENABLE))
8995 goto error;
8996
bc8d7dff
DL		 8997 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8998 fourcc = skl_format_to_fourcc(pixel_format,
8999 val & PLANE_CTL_ORDER_RGBX,
9000 val & PLANE_CTL_ALPHA_MASK);
9001 fb->pixel_format = fourcc;
9002 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9003
40f46283
DL		 9004 tiling = val & PLANE_CTL_TILED_MASK;
9005 switch (tiling) {
9006 case PLANE_CTL_TILED_LINEAR:
9007 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9008 break;
9009 case PLANE_CTL_TILED_X:
9010 plane_config->tiling = I915_TILING_X;
9011 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9012 break;
9013 case PLANE_CTL_TILED_Y:
9014 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9015 break;
9016 case PLANE_CTL_TILED_YF:
9017 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9018 break;
9019 default:
9020 MISSING_CASE(tiling);
9021 goto error;
9022 }
9023
bc8d7dff
DL		 9024 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9025 plane_config->base = base;
9026
9027 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9028
9029 val = I915_READ(PLANE_SIZE(pipe, 0));
9030 fb->height = ((val >> 16) & 0xfff) + 1;
9031 fb->width = ((val >> 0) & 0x1fff) + 1;
9032
9033 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9034 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9035 fb->pixel_format);
bc8d7dff
DL		 9036 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9037
9038 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9039 fb->pixel_format,
9040 fb->modifier[0]);
bc8d7dff 9041
f37b5c2b 9042 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9043
9044 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9045 pipe_name(pipe), fb->width, fb->height,
9046 fb->bits_per_pixel, base, fb->pitches[0],
9047 plane_config->size);
9048
2d14030b 9049 plane_config->fb = intel_fb;
bc8d7dff
DL		 9050 return;
9051
9052error:
9053 kfree(fb);
9054}
9055
2fa2fe9a 9056static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9057 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9058{
9059 struct drm_device *dev = crtc->base.dev;
9060 struct drm_i915_private *dev_priv = dev->dev_private;
9061 uint32_t tmp;
9062
9063 tmp = I915_READ(PF_CTL(crtc->pipe));
9064
9065 if (tmp & PF_ENABLE) {
fd4daa9c 9066 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9067 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9068 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9069
9070 /* We currently do not free assignements of panel fitters on
9071 * ivb/hsw (since we don't use the higher upscaling modes which
9072 * differentiates them) so just WARN about this case for now. */
9073 if (IS_GEN7(dev)) {
9074 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9075 PF_PIPE_SEL_IVB(crtc->pipe));
9076 }
2fa2fe9a 9077 }
79e53945
JB		 9078}
9079
5724dbd1
DL		 9080static void
9081ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9082 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9083{
9084 struct drm_device *dev = crtc->base.dev;
9085 struct drm_i915_private *dev_priv = dev->dev_private;
9086 u32 val, base, offset;
aeee5a49 9087 int pipe = crtc->pipe;
4c6baa59 9088 int fourcc, pixel_format;
6761dd31 9089 unsigned int aligned_height;
b113d5ee 9090 struct drm_framebuffer *fb;
1b842c89 9091 struct intel_framebuffer *intel_fb;
4c6baa59 9092
42a7b088
DL		 9093 val = I915_READ(DSPCNTR(pipe));
9094 if (!(val & DISPLAY_PLANE_ENABLE))
9095 return;
9096
d9806c9f 9097 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9098 if (!intel_fb) {
4c6baa59
JB		 9099 DRM_DEBUG_KMS("failed to alloc fb\n");
9100 return;
9101 }
9102
1b842c89
DL		 9103 fb = &intel_fb->base;
9104
18c5247e
DV		 9105 if (INTEL_INFO(dev)->gen >= 4) {
9106 if (val & DISPPLANE_TILED) {
49af449b 9107 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9108 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9109 }
9110 }
4c6baa59
JB		 9111
9112 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9113 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9114 fb->pixel_format = fourcc;
9115 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9116
aeee5a49 9117 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9118 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9119 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9120 } else {
49af449b 9121 if (plane_config->tiling)
aeee5a49 9122 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9123 else
aeee5a49 9124 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9125 }
9126 plane_config->base = base;
9127
9128 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9129 fb->width = ((val >> 16) & 0xfff) + 1;
9130 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9131
9132 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9133 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9134
b113d5ee 9135 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9136 fb->pixel_format,
9137 fb->modifier[0]);
4c6baa59 9138
f37b5c2b 9139 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9140
2844a921
DL		 9141 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9142 pipe_name(pipe), fb->width, fb->height,
9143 fb->bits_per_pixel, base, fb->pitches[0],
9144 plane_config->size);
b113d5ee 9145
2d14030b 9146 plane_config->fb = intel_fb;
4c6baa59
JB		 9147}
9148
0e8ffe1b 9149static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9150 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9151{
9152 struct drm_device *dev = crtc->base.dev;
9153 struct drm_i915_private *dev_priv = dev->dev_private;
9154 uint32_t tmp;
9155
f458ebbc
DV		 9156 if (!intel_display_power_is_enabled(dev_priv,
9157 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9158 return false;
9159
e143a21c 9160 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9161 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9162
0e8ffe1b
DV		 9163 tmp = I915_READ(PIPECONF(crtc->pipe));
9164 if (!(tmp & PIPECONF_ENABLE))
9165 return false;
9166
42571aef
VS		 9167 switch (tmp & PIPECONF_BPC_MASK) {
9168 case PIPECONF_6BPC:
9169 pipe_config->pipe_bpp = 18;
9170 break;
9171 case PIPECONF_8BPC:
9172 pipe_config->pipe_bpp = 24;
9173 break;
9174 case PIPECONF_10BPC:
9175 pipe_config->pipe_bpp = 30;
9176 break;
9177 case PIPECONF_12BPC:
9178 pipe_config->pipe_bpp = 36;
9179 break;
9180 default:
9181 break;
9182 }
9183
b5a9fa09
DV		 9184 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9185 pipe_config->limited_color_range = true;
9186
ab9412ba 9187 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9188 struct intel_shared_dpll *pll;
9189
88adfff1
DV		 9190 pipe_config->has_pch_encoder = true;
9191
627eb5a3
DV		 9192 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9193 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9194 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9195
9196 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9197
c0d43d62 9198 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9199 pipe_config->shared_dpll =
9200 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9201 } else {
9202 tmp = I915_READ(PCH_DPLL_SEL);
9203 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9204 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9205 else
9206 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9207 }
66e985c0
DV		 9208
9209 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9210
9211 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9212 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9213
9214 tmp = pipe_config->dpll_hw_state.dpll;
9215 pipe_config->pixel_multiplier =
9216 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9217 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9218
9219 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9220 } else {
9221 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9222 }
9223
1bd1bd80
DV		 9224 intel_get_pipe_timings(crtc, pipe_config);
9225
2fa2fe9a
DV		 9226 ironlake_get_pfit_config(crtc, pipe_config);
9227
0e8ffe1b
DV		 9228 return true;
9229}
9230
be256dc7
PZ		 9231static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9232{
9233 struct drm_device *dev = dev_priv->dev;
be256dc7 9234 struct intel_crtc *crtc;
be256dc7 9235
d3fcc808 9236 for_each_intel_crtc(dev, crtc)
e2c719b7 9237 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9238 pipe_name(crtc->pipe));
9239
e2c719b7
RC		 9240 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9241 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9242 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9243 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9244 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9245 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9246 "CPU PWM1 enabled\n");
c5107b87 9247 if (IS_HASWELL(dev))
e2c719b7 9248 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9249 "CPU PWM2 enabled\n");
e2c719b7 9250 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9251 "PCH PWM1 enabled\n");
e2c719b7 9252 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9253 "Utility pin enabled\n");
e2c719b7 9254 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9255
9926ada1
PZ		 9256 /*
9257 * In theory we can still leave IRQs enabled, as long as only the HPD
9258 * interrupts remain enabled. We used to check for that, but since it's
9259 * gen-specific and since we only disable LCPLL after we fully disable
9260 * the interrupts, the check below should be enough.
9261 */
e2c719b7 9262 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9263}
9264
9ccd5aeb
PZ		 9265static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9266{
9267 struct drm_device *dev = dev_priv->dev;
9268
9269 if (IS_HASWELL(dev))
9270 return I915_READ(D_COMP_HSW);
9271 else
9272 return I915_READ(D_COMP_BDW);
9273}
9274
3c4c9b81
PZ		 9275static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9276{
9277 struct drm_device *dev = dev_priv->dev;
9278
9279 if (IS_HASWELL(dev)) {
9280 mutex_lock(&dev_priv->rps.hw_lock);
9281 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9282 val))
f475dadf 9283 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9284 mutex_unlock(&dev_priv->rps.hw_lock);
9285 } else {
9ccd5aeb
PZ		 9286 I915_WRITE(D_COMP_BDW, val);
9287 POSTING_READ(D_COMP_BDW);
3c4c9b81 9288 }
be256dc7
PZ		 9289}
9290
9291/*
9292 * This function implements pieces of two sequences from BSpec:
9293 * - Sequence for display software to disable LCPLL
9294 * - Sequence for display software to allow package C8+
9295 * The steps implemented here are just the steps that actually touch the LCPLL
9296 * register. Callers should take care of disabling all the display engine
9297 * functions, doing the mode unset, fixing interrupts, etc.
9298 */
6ff58d53
PZ		 9299static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9300 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9301{
9302 uint32_t val;
9303
9304 assert_can_disable_lcpll(dev_priv);
9305
9306 val = I915_READ(LCPLL_CTL);
9307
9308 if (switch_to_fclk) {
9309 val |= LCPLL_CD_SOURCE_FCLK;
9310 I915_WRITE(LCPLL_CTL, val);
9311
9312 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9313 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9314 DRM_ERROR("Switching to FCLK failed\n");
9315
9316 val = I915_READ(LCPLL_CTL);
9317 }
9318
9319 val |= LCPLL_PLL_DISABLE;
9320 I915_WRITE(LCPLL_CTL, val);
9321 POSTING_READ(LCPLL_CTL);
9322
9323 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9324 DRM_ERROR("LCPLL still locked\n");
9325
9ccd5aeb 9326 val = hsw_read_dcomp(dev_priv);
be256dc7 9327 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9328 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9329 ndelay(100);
9330
9ccd5aeb
PZ		 9331 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9332 1))
be256dc7
PZ		 9333 DRM_ERROR("D_COMP RCOMP still in progress\n");
9334
9335 if (allow_power_down) {
9336 val = I915_READ(LCPLL_CTL);
9337 val |= LCPLL_POWER_DOWN_ALLOW;
9338 I915_WRITE(LCPLL_CTL, val);
9339 POSTING_READ(LCPLL_CTL);
9340 }
9341}
9342
9343/*
9344 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9345 * source.
9346 */
6ff58d53 9347static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9348{
9349 uint32_t val;
9350
9351 val = I915_READ(LCPLL_CTL);
9352
9353 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9354 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9355 return;
9356
a8a8bd54
PZ		 9357 /*
9358 * Make sure we're not on PC8 state before disabling PC8, otherwise
9359 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9360 */
59bad947 9361 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9362
be256dc7
PZ		 9363 if (val & LCPLL_POWER_DOWN_ALLOW) {
9364 val &= ~LCPLL_POWER_DOWN_ALLOW;
9365 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9366 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9367 }
9368
9ccd5aeb 9369 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9370 val |= D_COMP_COMP_FORCE;
9371 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9372 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9373
9374 val = I915_READ(LCPLL_CTL);
9375 val &= ~LCPLL_PLL_DISABLE;
9376 I915_WRITE(LCPLL_CTL, val);
9377
9378 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9379 DRM_ERROR("LCPLL not locked yet\n");
9380
9381 if (val & LCPLL_CD_SOURCE_FCLK) {
9382 val = I915_READ(LCPLL_CTL);
9383 val &= ~LCPLL_CD_SOURCE_FCLK;
9384 I915_WRITE(LCPLL_CTL, val);
9385
9386 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9387 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9388 DRM_ERROR("Switching back to LCPLL failed\n");
9389 }
215733fa 9390
59bad947 9391 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9392 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9393}
9394
765dab67
PZ		 9395/*
9396 * Package states C8 and deeper are really deep PC states that can only be
9397 * reached when all the devices on the system allow it, so even if the graphics
9398 * device allows PC8+, it doesn't mean the system will actually get to these
9399 * states. Our driver only allows PC8+ when going into runtime PM.
9400 *
9401 * The requirements for PC8+ are that all the outputs are disabled, the power
9402 * well is disabled and most interrupts are disabled, and these are also
9403 * requirements for runtime PM. When these conditions are met, we manually do
9404 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9405 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9406 * hang the machine.
9407 *
9408 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9409 * the state of some registers, so when we come back from PC8+ we need to
9410 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9411 * need to take care of the registers kept by RC6. Notice that this happens even
9412 * if we don't put the device in PCI D3 state (which is what currently happens
9413 * because of the runtime PM support).
9414 *
9415 * For more, read "Display Sequences for Package C8" on the hardware
9416 * documentation.
9417 */
a14cb6fc 9418void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9419{
c67a470b
PZ		 9420 struct drm_device *dev = dev_priv->dev;
9421 uint32_t val;
9422
c67a470b
PZ		 9423 DRM_DEBUG_KMS("Enabling package C8+\n");
9424
c67a470b
PZ		 9425 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9426 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9427 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9428 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9429 }
9430
9431 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9432 hsw_disable_lcpll(dev_priv, true, true);
9433}
9434
a14cb6fc 9435void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9436{
9437 struct drm_device *dev = dev_priv->dev;
9438 uint32_t val;
9439
c67a470b
PZ		 9440 DRM_DEBUG_KMS("Disabling package C8+\n");
9441
9442 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9443 lpt_init_pch_refclk(dev);
9444
9445 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9446 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9447 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9448 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9449 }
9450
9451 intel_prepare_ddi(dev);
c67a470b
PZ		 9452}
9453
27c329ed 9454static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9455{
a821fc46 9456 struct drm_device *dev = old_state->dev;
27c329ed 9457 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9458
27c329ed 9459 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9460}
9461
b432e5cf 9462/* compute the max rate for new configuration */
27c329ed 9463static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9464{
b432e5cf 9465 struct intel_crtc *intel_crtc;
27c329ed 9466 struct intel_crtc_state *crtc_state;
b432e5cf 9467 int max_pixel_rate = 0;
b432e5cf 9468
27c329ed
ML		 9469 for_each_intel_crtc(state->dev, intel_crtc) {
9470 int pixel_rate;
9471
9472 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9473 if (IS_ERR(crtc_state))
9474 return PTR_ERR(crtc_state);
9475
9476 if (!crtc_state->base.enable)
b432e5cf
VS		 9477 continue;
9478
27c329ed 9479 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9480
9481 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9482 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9483 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9484
9485 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9486 }
9487
9488 return max_pixel_rate;
9489}
9490
9491static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9492{
9493 struct drm_i915_private *dev_priv = dev->dev_private;
9494 uint32_t val, data;
9495 int ret;
9496
9497 if (WARN((I915_READ(LCPLL_CTL) &
9498 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9499 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9500 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9501 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9502 "trying to change cdclk frequency with cdclk not enabled\n"))
9503 return;
9504
9505 mutex_lock(&dev_priv->rps.hw_lock);
9506 ret = sandybridge_pcode_write(dev_priv,
9507 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9508 mutex_unlock(&dev_priv->rps.hw_lock);
9509 if (ret) {
9510 DRM_ERROR("failed to inform pcode about cdclk change\n");
9511 return;
9512 }
9513
9514 val = I915_READ(LCPLL_CTL);
9515 val |= LCPLL_CD_SOURCE_FCLK;
9516 I915_WRITE(LCPLL_CTL, val);
9517
9518 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9519 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9520 DRM_ERROR("Switching to FCLK failed\n");
9521
9522 val = I915_READ(LCPLL_CTL);
9523 val &= ~LCPLL_CLK_FREQ_MASK;
9524
9525 switch (cdclk) {
9526 case 450000:
9527 val |= LCPLL_CLK_FREQ_450;
9528 data = 0;
9529 break;
9530 case 540000:
9531 val |= LCPLL_CLK_FREQ_54O_BDW;
9532 data = 1;
9533 break;
9534 case 337500:
9535 val |= LCPLL_CLK_FREQ_337_5_BDW;
9536 data = 2;
9537 break;
9538 case 675000:
9539 val |= LCPLL_CLK_FREQ_675_BDW;
9540 data = 3;
9541 break;
9542 default:
9543 WARN(1, "invalid cdclk frequency\n");
9544 return;
9545 }
9546
9547 I915_WRITE(LCPLL_CTL, val);
9548
9549 val = I915_READ(LCPLL_CTL);
9550 val &= ~LCPLL_CD_SOURCE_FCLK;
9551 I915_WRITE(LCPLL_CTL, val);
9552
9553 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9554 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9555 DRM_ERROR("Switching back to LCPLL failed\n");
9556
9557 mutex_lock(&dev_priv->rps.hw_lock);
9558 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9559 mutex_unlock(&dev_priv->rps.hw_lock);
9560
9561 intel_update_cdclk(dev);
9562
9563 WARN(cdclk != dev_priv->cdclk_freq,
9564 "cdclk requested %d kHz but got %d kHz\n",
9565 cdclk, dev_priv->cdclk_freq);
9566}
9567
27c329ed 9568static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9569{
27c329ed
ML		 9570 struct drm_i915_private *dev_priv = to_i915(state->dev);
9571 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9572 int cdclk;
9573
9574 /*
9575 * FIXME should also account for plane ratio
9576 * once 64bpp pixel formats are supported.
9577 */
27c329ed 9578 if (max_pixclk > 540000)
b432e5cf 9579 cdclk = 675000;
27c329ed 9580 else if (max_pixclk > 450000)
b432e5cf 9581 cdclk = 540000;
27c329ed 9582 else if (max_pixclk > 337500)
b432e5cf
VS		 9583 cdclk = 450000;
9584 else
9585 cdclk = 337500;
9586
9587 /*
9588 * FIXME move the cdclk caclulation to
9589 * compute_config() so we can fail gracegully.
9590 */
9591 if (cdclk > dev_priv->max_cdclk_freq) {
9592 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9593 cdclk, dev_priv->max_cdclk_freq);
9594 cdclk = dev_priv->max_cdclk_freq;
9595 }
9596
27c329ed 9597 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9598
9599 return 0;
9600}
9601
27c329ed 9602static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9603{
27c329ed
ML		 9604 struct drm_device *dev = old_state->dev;
9605 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9606
27c329ed 9607 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9608}
9609
190f68c5
ACO		 9610static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9611 struct intel_crtc_state *crtc_state)
09b4ddf9 9612{
190f68c5 9613 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9614 return -EINVAL;
716c2e55 9615
c7653199 9616 crtc->lowfreq_avail = false;
644cef34 9617
c8f7a0db 9618 return 0;
79e53945
JB		 9619}
9620
3760b59c
S		 9621static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9622 enum port port,
9623 struct intel_crtc_state *pipe_config)
9624{
9625 switch (port) {
9626 case PORT_A:
9627 pipe_config->ddi_pll_sel = SKL_DPLL0;
9628 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9629 break;
9630 case PORT_B:
9631 pipe_config->ddi_pll_sel = SKL_DPLL1;
9632 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9633 break;
9634 case PORT_C:
9635 pipe_config->ddi_pll_sel = SKL_DPLL2;
9636 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9637 break;
9638 default:
9639 DRM_ERROR("Incorrect port type\n");
9640 }
9641}
9642
96b7dfb7
S		 9643static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9644 enum port port,
5cec258b 9645 struct intel_crtc_state *pipe_config)
96b7dfb7 9646{
3148ade7 9647 u32 temp, dpll_ctl1;
96b7dfb7
S		 9648
9649 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9650 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9651
9652 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9653 case SKL_DPLL0:
9654 /*
9655 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9656 * of the shared DPLL framework and thus needs to be read out
9657 * separately
9658 */
9659 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9660 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9661 break;
96b7dfb7
S		 9662 case SKL_DPLL1:
9663 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9664 break;
9665 case SKL_DPLL2:
9666 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9667 break;
9668 case SKL_DPLL3:
9669 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9670 break;
96b7dfb7
S		 9671 }
9672}
9673
7d2c8175
DL		 9674static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9675 enum port port,
5cec258b 9676 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9677{
9678 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9679
9680 switch (pipe_config->ddi_pll_sel) {
9681 case PORT_CLK_SEL_WRPLL1:
9682 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9683 break;
9684 case PORT_CLK_SEL_WRPLL2:
9685 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9686 break;
9687 }
9688}
9689
26804afd 9690static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9691 struct intel_crtc_state *pipe_config)
26804afd
DV		 9692{
9693 struct drm_device *dev = crtc->base.dev;
9694 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9695 struct intel_shared_dpll *pll;
26804afd
DV		 9696 enum port port;
9697 uint32_t tmp;
9698
9699 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9700
9701 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9702
96b7dfb7
S		 9703 if (IS_SKYLAKE(dev))
9704 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9705 else if (IS_BROXTON(dev))
9706 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9707 else
9708 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9709
d452c5b6
DV		 9710 if (pipe_config->shared_dpll >= 0) {
9711 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9712
9713 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9714 &pipe_config->dpll_hw_state));
9715 }
9716
26804afd
DV		 9717 /*
9718 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9719 * DDI E. So just check whether this pipe is wired to DDI E and whether
9720 * the PCH transcoder is on.
9721 */
ca370455
DL		 9722 if (INTEL_INFO(dev)->gen < 9 &&
9723 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9724 pipe_config->has_pch_encoder = true;
9725
9726 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9727 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9728 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9729
9730 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9731 }
9732}
9733
0e8ffe1b 9734static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9735 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9736{
9737 struct drm_device *dev = crtc->base.dev;
9738 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9739 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9740 uint32_t tmp;
9741
f458ebbc 9742 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9743 POWER_DOMAIN_PIPE(crtc->pipe)))
9744 return false;
9745
e143a21c 9746 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9747 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9748
eccb140b
DV		 9749 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9750 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9751 enum pipe trans_edp_pipe;
9752 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9753 default:
9754 WARN(1, "unknown pipe linked to edp transcoder\n");
9755 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9756 case TRANS_DDI_EDP_INPUT_A_ON:
9757 trans_edp_pipe = PIPE_A;
9758 break;
9759 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9760 trans_edp_pipe = PIPE_B;
9761 break;
9762 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9763 trans_edp_pipe = PIPE_C;
9764 break;
9765 }
9766
9767 if (trans_edp_pipe == crtc->pipe)
9768 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9769 }
9770
f458ebbc 9771 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9772 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9773 return false;
9774
eccb140b 9775 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9776 if (!(tmp & PIPECONF_ENABLE))
9777 return false;
9778
26804afd 9779 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9780
1bd1bd80
DV		 9781 intel_get_pipe_timings(crtc, pipe_config);
9782
a1b2278e
CK		 9783 if (INTEL_INFO(dev)->gen >= 9) {
9784 skl_init_scalers(dev, crtc, pipe_config);
9785 }
9786
2fa2fe9a 9787 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9788
9789 if (INTEL_INFO(dev)->gen >= 9) {
9790 pipe_config->scaler_state.scaler_id = -1;
9791 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9792 }
9793
bd2e244f 9794 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9795 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9796 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9797 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9798 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9799 else
9800 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9801 }
88adfff1 9802
e59150dc
JB		 9803 if (IS_HASWELL(dev))
9804 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9805 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9806
ebb69c95
CT		 9807 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9808 pipe_config->pixel_multiplier =
9809 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9810 } else {
9811 pipe_config->pixel_multiplier = 1;
9812 }
6c49f241 9813
0e8ffe1b
DV		 9814 return true;
9815}
9816
560b85bb
CW		 9817static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9818{
9819 struct drm_device *dev = crtc->dev;
9820 struct drm_i915_private *dev_priv = dev->dev_private;
9821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9822 uint32_t cntl = 0, size = 0;
560b85bb 9823
dc41c154 9824 if (base) {
3dd512fb
MR		 9825 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9826 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9827 unsigned int stride = roundup_pow_of_two(width) * 4;
9828
9829 switch (stride) {
9830 default:
9831 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9832 width, stride);
9833 stride = 256;
9834 /* fallthrough */
9835 case 256:
9836 case 512:
9837 case 1024:
9838 case 2048:
9839 break;
4b0e333e
CW		 9840 }
9841
dc41c154
VS		 9842 cntl |= CURSOR_ENABLE |
9843 CURSOR_GAMMA_ENABLE |
9844 CURSOR_FORMAT_ARGB |
9845 CURSOR_STRIDE(stride);
9846
9847 size = (height << 12) | width;
4b0e333e 9848 }
560b85bb 9849
dc41c154
VS		 9850 if (intel_crtc->cursor_cntl != 0 &&
9851 (intel_crtc->cursor_base != base ||
9852 intel_crtc->cursor_size != size ||
9853 intel_crtc->cursor_cntl != cntl)) {
9854 /* On these chipsets we can only modify the base/size/stride
9855 * whilst the cursor is disabled.
9856 */
9857 I915_WRITE(_CURACNTR, 0);
4b0e333e 9858 POSTING_READ(_CURACNTR);
dc41c154 9859 intel_crtc->cursor_cntl = 0;
4b0e333e 9860 }
560b85bb 9861
99d1f387 9862 if (intel_crtc->cursor_base != base) {
9db4a9c7 9863 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9864 intel_crtc->cursor_base = base;
9865 }
4726e0b0 9866
dc41c154
VS		 9867 if (intel_crtc->cursor_size != size) {
9868 I915_WRITE(CURSIZE, size);
9869 intel_crtc->cursor_size = size;
4b0e333e 9870 }
560b85bb 9871
4b0e333e 9872 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9873 I915_WRITE(_CURACNTR, cntl);
9874 POSTING_READ(_CURACNTR);
4b0e333e 9875 intel_crtc->cursor_cntl = cntl;
560b85bb 9876 }
560b85bb
CW		 9877}
9878
560b85bb 9879static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9880{
9881 struct drm_device *dev = crtc->dev;
9882 struct drm_i915_private *dev_priv = dev->dev_private;
9883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9884 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9885 uint32_t cntl;
9886
9887 cntl = 0;
9888 if (base) {
9889 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9890 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9891 case 64:
9892 cntl |= CURSOR_MODE_64_ARGB_AX;
9893 break;
9894 case 128:
9895 cntl |= CURSOR_MODE_128_ARGB_AX;
9896 break;
9897 case 256:
9898 cntl |= CURSOR_MODE_256_ARGB_AX;
9899 break;
9900 default:
3dd512fb 9901 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9902 return;
65a21cd6 9903 }
4b0e333e 9904 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9905
9906 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9907 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9908 }
65a21cd6 9909
8e7d688b 9910 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9911 cntl |= CURSOR_ROTATE_180;
9912
4b0e333e
CW		 9913 if (intel_crtc->cursor_cntl != cntl) {
9914 I915_WRITE(CURCNTR(pipe), cntl);
9915 POSTING_READ(CURCNTR(pipe));
9916 intel_crtc->cursor_cntl = cntl;
65a21cd6 9917 }
4b0e333e 9918
65a21cd6 9919 /* and commit changes on next vblank */
5efb3e28
VS		 9920 I915_WRITE(CURBASE(pipe), base);
9921 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9922
9923 intel_crtc->cursor_base = base;
65a21cd6
JB		 9924}
9925
cda4b7d3 9926/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9927static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9928 bool on)
cda4b7d3
CW		 9929{
9930 struct drm_device *dev = crtc->dev;
9931 struct drm_i915_private *dev_priv = dev->dev_private;
9932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9933 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9934 int x = crtc->cursor_x;
9935 int y = crtc->cursor_y;
d6e4db15 9936 u32 base = 0, pos = 0;
cda4b7d3 9937
d6e4db15 9938 if (on)
cda4b7d3 9939 base = intel_crtc->cursor_addr;
cda4b7d3 9940
6e3c9717 9941 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9942 base = 0;
9943
6e3c9717 9944 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9945 base = 0;
9946
9947 if (x < 0) {
3dd512fb 9948 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9949 base = 0;
9950
9951 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9952 x = -x;
9953 }
9954 pos |= x << CURSOR_X_SHIFT;
9955
9956 if (y < 0) {
3dd512fb 9957 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9958 base = 0;
9959
9960 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9961 y = -y;
9962 }
9963 pos |= y << CURSOR_Y_SHIFT;
9964
4b0e333e 9965 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9966 return;
9967
5efb3e28
VS		 9968 I915_WRITE(CURPOS(pipe), pos);
9969
4398ad45
VS		 9970 /* ILK+ do this automagically */
9971 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9972 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9973 base += (intel_crtc->base.cursor->state->crtc_h *
9974 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9975 }
9976
8ac54669 9977 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9978 i845_update_cursor(crtc, base);
9979 else
9980 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9981}
9982
dc41c154
VS		 9983static bool cursor_size_ok(struct drm_device *dev,
9984 uint32_t width, uint32_t height)
9985{
9986 if (width == 0 || height == 0)
9987 return false;
9988
9989 /*
9990 * 845g/865g are special in that they are only limited by
9991 * the width of their cursors, the height is arbitrary up to
9992 * the precision of the register. Everything else requires
9993 * square cursors, limited to a few power-of-two sizes.
9994 */
9995 if (IS_845G(dev) || IS_I865G(dev)) {
9996 if ((width & 63) != 0)
9997 return false;
9998
9999 if (width > (IS_845G(dev) ? 64 : 512))
10000 return false;
10001
10002 if (height > 1023)
10003 return false;
10004 } else {
10005 switch (width | height) {
10006 case 256:
10007 case 128:
10008 if (IS_GEN2(dev))
10009 return false;
10010 case 64:
10011 break;
10012 default:
10013 return false;
10014 }
10015 }
10016
10017 return true;
10018}
10019
79e53945 10020static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10021 u16 *blue, uint32_t start, uint32_t size)
79e53945 10022{
7203425a 10023 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10025
7203425a 10026 for (i = start; i < end; i++) {
79e53945
JB		 10027 intel_crtc->lut_r[i] = red[i] >> 8;
10028 intel_crtc->lut_g[i] = green[i] >> 8;
10029 intel_crtc->lut_b[i] = blue[i] >> 8;
10030 }
10031
10032 intel_crtc_load_lut(crtc);
10033}
10034
79e53945
JB		 10035/* VESA 640x480x72Hz mode to set on the pipe */
10036static struct drm_display_mode load_detect_mode = {
10037 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10038 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10039};
10040
a8bb6818
DV		 10041struct drm_framebuffer *
10042__intel_framebuffer_create(struct drm_device *dev,
10043 struct drm_mode_fb_cmd2 *mode_cmd,
10044 struct drm_i915_gem_object *obj)
d2dff872
CW		 10045{
10046 struct intel_framebuffer *intel_fb;
10047 int ret;
10048
10049 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10050 if (!intel_fb) {
6ccb81f2 10051 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10052 return ERR_PTR(-ENOMEM);
10053 }
10054
10055 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10056 if (ret)
10057 goto err;
d2dff872
CW		 10058
10059 return &intel_fb->base;
dd4916c5 10060err:
6ccb81f2 10061 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10062 kfree(intel_fb);
10063
10064 return ERR_PTR(ret);
d2dff872
CW		 10065}
10066
b5ea642a 10067static struct drm_framebuffer *
a8bb6818
DV		 10068intel_framebuffer_create(struct drm_device *dev,
10069 struct drm_mode_fb_cmd2 *mode_cmd,
10070 struct drm_i915_gem_object *obj)
10071{
10072 struct drm_framebuffer *fb;
10073 int ret;
10074
10075 ret = i915_mutex_lock_interruptible(dev);
10076 if (ret)
10077 return ERR_PTR(ret);
10078 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10079 mutex_unlock(&dev->struct_mutex);
10080
10081 return fb;
10082}
10083
d2dff872
CW		 10084static u32
10085intel_framebuffer_pitch_for_width(int width, int bpp)
10086{
10087 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10088 return ALIGN(pitch, 64);
10089}
10090
10091static u32
10092intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10093{
10094 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10095 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10096}
10097
10098static struct drm_framebuffer *
10099intel_framebuffer_create_for_mode(struct drm_device *dev,
10100 struct drm_display_mode *mode,
10101 int depth, int bpp)
10102{
10103 struct drm_i915_gem_object *obj;
0fed39bd 10104 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10105
10106 obj = i915_gem_alloc_object(dev,
10107 intel_framebuffer_size_for_mode(mode, bpp));
10108 if (obj == NULL)
10109 return ERR_PTR(-ENOMEM);
10110
10111 mode_cmd.width = mode->hdisplay;
10112 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10113 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10114 bpp);
5ca0c34a 10115 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10116
10117 return intel_framebuffer_create(dev, &mode_cmd, obj);
10118}
10119
10120static struct drm_framebuffer *
10121mode_fits_in_fbdev(struct drm_device *dev,
10122 struct drm_display_mode *mode)
10123{
4520f53a 10124#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10125 struct drm_i915_private *dev_priv = dev->dev_private;
10126 struct drm_i915_gem_object *obj;
10127 struct drm_framebuffer *fb;
10128
4c0e5528 10129 if (!dev_priv->fbdev)
d2dff872
CW		 10130 return NULL;
10131
4c0e5528 10132 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10133 return NULL;
10134
4c0e5528
DV		 10135 obj = dev_priv->fbdev->fb->obj;
10136 BUG_ON(!obj);
10137
8bcd4553 10138 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10139 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10140 fb->bits_per_pixel))
d2dff872
CW		 10141 return NULL;
10142
01f2c773 10143 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10144 return NULL;
10145
10146 return fb;
4520f53a
DV		 10147#else
10148 return NULL;
10149#endif
d2dff872
CW		 10150}
10151
d3a40d1b
ACO		 10152static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10153 struct drm_crtc *crtc,
10154 struct drm_display_mode *mode,
10155 struct drm_framebuffer *fb,
10156 int x, int y)
10157{
10158 struct drm_plane_state *plane_state;
10159 int hdisplay, vdisplay;
10160 int ret;
10161
10162 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10163 if (IS_ERR(plane_state))
10164 return PTR_ERR(plane_state);
10165
10166 if (mode)
10167 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10168 else
10169 hdisplay = vdisplay = 0;
10170
10171 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10172 if (ret)
10173 return ret;
10174 drm_atomic_set_fb_for_plane(plane_state, fb);
10175 plane_state->crtc_x = 0;
10176 plane_state->crtc_y = 0;
10177 plane_state->crtc_w = hdisplay;
10178 plane_state->crtc_h = vdisplay;
10179 plane_state->src_x = x << 16;
10180 plane_state->src_y = y << 16;
10181 plane_state->src_w = hdisplay << 16;
10182 plane_state->src_h = vdisplay << 16;
10183
10184 return 0;
10185}
10186
d2434ab7 10187bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10188 struct drm_display_mode *mode,
51fd371b
RC		 10189 struct intel_load_detect_pipe *old,
10190 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10191{
10192 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10193 struct intel_encoder *intel_encoder =
10194 intel_attached_encoder(connector);
79e53945 10195 struct drm_crtc *possible_crtc;
4ef69c7a 10196 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10197 struct drm_crtc *crtc = NULL;
10198 struct drm_device *dev = encoder->dev;
94352cf9 10199 struct drm_framebuffer *fb;
51fd371b 10200 struct drm_mode_config *config = &dev->mode_config;
83a57153 10201 struct drm_atomic_state *state = NULL;
944b0c76 10202 struct drm_connector_state *connector_state;
4be07317 10203 struct intel_crtc_state *crtc_state;
51fd371b 10204 int ret, i = -1;
79e53945 10205
d2dff872 10206 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10207 connector->base.id, connector->name,
8e329a03 10208 encoder->base.id, encoder->name);
d2dff872 10209
51fd371b
RC		 10210retry:
10211 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10212 if (ret)
10213 goto fail_unlock;
6e9f798d 10214
79e53945
JB		 10215 /*
10216 * Algorithm gets a little messy:
7a5e4805 10217 *
79e53945
JB		 10218 * - if the connector already has an assigned crtc, use it (but make
10219 * sure it's on first)
7a5e4805 10220 *
79e53945
JB		 10221 * - try to find the first unused crtc that can drive this connector,
10222 * and use that if we find one
79e53945
JB		 10223 */
10224
10225 /* See if we already have a CRTC for this connector */
10226 if (encoder->crtc) {
10227 crtc = encoder->crtc;
8261b191 10228
51fd371b 10229 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10230 if (ret)
10231 goto fail_unlock;
10232 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10233 if (ret)
10234 goto fail_unlock;
7b24056b 10235
24218aac 10236 old->dpms_mode = connector->dpms;
8261b191
CW		 10237 old->load_detect_temp = false;
10238
10239 /* Make sure the crtc and connector are running */
24218aac
DV		 10240 if (connector->dpms != DRM_MODE_DPMS_ON)
10241 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10242
7173188d 10243 return true;
79e53945
JB		 10244 }
10245
10246 /* Find an unused one (if possible) */
70e1e0ec 10247 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10248 i++;
10249 if (!(encoder->possible_crtcs & (1 << i)))
10250 continue;
83d65738 10251 if (possible_crtc->state->enable)
a459249c
VS		 10252 continue;
10253 /* This can occur when applying the pipe A quirk on resume. */
10254 if (to_intel_crtc(possible_crtc)->new_enabled)
10255 continue;
10256
10257 crtc = possible_crtc;
10258 break;
79e53945
JB		 10259 }
10260
10261 /*
10262 * If we didn't find an unused CRTC, don't use any.
10263 */
10264 if (!crtc) {
7173188d 10265 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10266 goto fail_unlock;
79e53945
JB		 10267 }
10268
51fd371b
RC		 10269 ret = drm_modeset_lock(&crtc->mutex, ctx);
10270 if (ret)
4d02e2de
DV		 10271 goto fail_unlock;
10272 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10273 if (ret)
51fd371b 10274 goto fail_unlock;
fc303101
DV		 10275 intel_encoder->new_crtc = to_intel_crtc(crtc);
10276 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10277
10278 intel_crtc = to_intel_crtc(crtc);
412b61d8 10279 intel_crtc->new_enabled = true;
24218aac 10280 old->dpms_mode = connector->dpms;
8261b191 10281 old->load_detect_temp = true;
d2dff872 10282 old->release_fb = NULL;
79e53945 10283
83a57153
ACO		 10284 state = drm_atomic_state_alloc(dev);
10285 if (!state)
10286 return false;
10287
10288 state->acquire_ctx = ctx;
10289
944b0c76
ACO		 10290 connector_state = drm_atomic_get_connector_state(state, connector);
10291 if (IS_ERR(connector_state)) {
10292 ret = PTR_ERR(connector_state);
10293 goto fail;
10294 }
10295
10296 connector_state->crtc = crtc;
10297 connector_state->best_encoder = &intel_encoder->base;
10298
4be07317
ACO		 10299 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10300 if (IS_ERR(crtc_state)) {
10301 ret = PTR_ERR(crtc_state);
10302 goto fail;
10303 }
10304
49d6fa21 10305 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10306
6492711d
CW		 10307 if (!mode)
10308 mode = &load_detect_mode;
79e53945 10309
d2dff872
CW		 10310 /* We need a framebuffer large enough to accommodate all accesses
10311 * that the plane may generate whilst we perform load detection.
10312 * We can not rely on the fbcon either being present (we get called
10313 * during its initialisation to detect all boot displays, or it may
10314 * not even exist) or that it is large enough to satisfy the
10315 * requested mode.
10316 */
94352cf9
DV		 10317 fb = mode_fits_in_fbdev(dev, mode);
10318 if (fb == NULL) {
d2dff872 10319 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10320 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10321 old->release_fb = fb;
d2dff872
CW		 10322 } else
10323 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10324 if (IS_ERR(fb)) {
d2dff872 10325 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10326 goto fail;
79e53945 10327 }
79e53945 10328
d3a40d1b
ACO		 10329 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10330 if (ret)
10331 goto fail;
10332
8c7b5ccb
ACO		 10333 drm_mode_copy(&crtc_state->base.mode, mode);
10334
568c634a 10335 if (intel_set_mode(state)) {
6492711d 10336 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10337 if (old->release_fb)
10338 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10339 goto fail;
79e53945 10340 }
9128b040 10341 crtc->primary->crtc = crtc;
7173188d 10342
79e53945 10343 /* let the connector get through one full cycle before testing */
9d0498a2 10344 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10345 return true;
412b61d8
VS		 10346
10347 fail:
83d65738 10348 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10349fail_unlock:
e5d958ef
ACO		 10350 drm_atomic_state_free(state);
10351 state = NULL;
83a57153 10352
51fd371b
RC		 10353 if (ret == -EDEADLK) {
10354 drm_modeset_backoff(ctx);
10355 goto retry;
10356 }
10357
412b61d8 10358 return false;
79e53945
JB		 10359}
10360
d2434ab7 10361void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10362 struct intel_load_detect_pipe *old,
10363 struct drm_modeset_acquire_ctx *ctx)
79e53945 10364{
83a57153 10365 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10366 struct intel_encoder *intel_encoder =
10367 intel_attached_encoder(connector);
4ef69c7a 10368 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10369 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10371 struct drm_atomic_state *state;
944b0c76 10372 struct drm_connector_state *connector_state;
4be07317 10373 struct intel_crtc_state *crtc_state;
d3a40d1b 10374 int ret;
79e53945 10375
d2dff872 10376 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10377 connector->base.id, connector->name,
8e329a03 10378 encoder->base.id, encoder->name);
d2dff872 10379
8261b191 10380 if (old->load_detect_temp) {
83a57153 10381 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10382 if (!state)
10383 goto fail;
83a57153
ACO		 10384
10385 state->acquire_ctx = ctx;
10386
944b0c76
ACO		 10387 connector_state = drm_atomic_get_connector_state(state, connector);
10388 if (IS_ERR(connector_state))
10389 goto fail;
10390
4be07317
ACO		 10391 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10392 if (IS_ERR(crtc_state))
10393 goto fail;
10394
fc303101
DV		 10395 to_intel_connector(connector)->new_encoder = NULL;
10396 intel_encoder->new_crtc = NULL;
412b61d8 10397 intel_crtc->new_enabled = false;
944b0c76
ACO		 10398
10399 connector_state->best_encoder = NULL;
10400 connector_state->crtc = NULL;
10401
49d6fa21 10402 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10403
d3a40d1b
ACO		 10404 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10405 0, 0);
10406 if (ret)
10407 goto fail;
10408
568c634a 10409 ret = intel_set_mode(state);
2bfb4627
ACO		 10410 if (ret)
10411 goto fail;
d2dff872 10412
36206361
DV		 10413 if (old->release_fb) {
10414 drm_framebuffer_unregister_private(old->release_fb);
10415 drm_framebuffer_unreference(old->release_fb);
10416 }
d2dff872 10417
0622a53c 10418 return;
79e53945
JB		 10419 }
10420
c751ce4f 10421 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10422 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10423 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10424
10425 return;
10426fail:
10427 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10428 drm_atomic_state_free(state);
79e53945
JB		 10429}
10430
da4a1efa 10431static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10432 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10433{
10434 struct drm_i915_private *dev_priv = dev->dev_private;
10435 u32 dpll = pipe_config->dpll_hw_state.dpll;
10436
10437 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10438 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10439 else if (HAS_PCH_SPLIT(dev))
10440 return 120000;
10441 else if (!IS_GEN2(dev))
10442 return 96000;
10443 else
10444 return 48000;
10445}
10446
79e53945 10447/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10448static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10449 struct intel_crtc_state *pipe_config)
79e53945 10450{
f1f644dc 10451 struct drm_device *dev = crtc->base.dev;
79e53945 10452 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10453 int pipe = pipe_config->cpu_transcoder;
293623f7 10454 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10455 u32 fp;
10456 intel_clock_t clock;
da4a1efa 10457 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10458
10459 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10460 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10461 else
293623f7 10462 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10463
10464 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10465 if (IS_PINEVIEW(dev)) {
10466 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10467 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10468 } else {
10469 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10470 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10471 }
10472
a6c45cf0 10473 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10474 if (IS_PINEVIEW(dev))
10475 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10476 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10477 else
10478 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10479 DPLL_FPA01_P1_POST_DIV_SHIFT);
10480
10481 switch (dpll & DPLL_MODE_MASK) {
10482 case DPLLB_MODE_DAC_SERIAL:
10483 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10484 5 : 10;
10485 break;
10486 case DPLLB_MODE_LVDS:
10487 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10488 7 : 14;
10489 break;
10490 default:
28c97730 10491 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10492 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10493 return;
79e53945
JB		 10494 }
10495
ac58c3f0 10496 if (IS_PINEVIEW(dev))
da4a1efa 10497 pineview_clock(refclk, &clock);
ac58c3f0 10498 else
da4a1efa 10499 i9xx_clock(refclk, &clock);
79e53945 10500 } else {
0fb58223 10501 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10502 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10503
10504 if (is_lvds) {
10505 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10506 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10507
10508 if (lvds & LVDS_CLKB_POWER_UP)
10509 clock.p2 = 7;
10510 else
10511 clock.p2 = 14;
79e53945
JB		 10512 } else {
10513 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10514 clock.p1 = 2;
10515 else {
10516 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10517 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10518 }
10519 if (dpll & PLL_P2_DIVIDE_BY_4)
10520 clock.p2 = 4;
10521 else
10522 clock.p2 = 2;
79e53945 10523 }
da4a1efa
VS		 10524
10525 i9xx_clock(refclk, &clock);
79e53945
JB		 10526 }
10527
18442d08
VS		 10528 /*
10529 * This value includes pixel_multiplier. We will use
241bfc38 10530 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10531 * encoder's get_config() function.
10532 */
10533 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10534}
10535
6878da05
VS		 10536int intel_dotclock_calculate(int link_freq,
10537 const struct intel_link_m_n *m_n)
f1f644dc 10538{
f1f644dc
JB		 10539 /*
10540 * The calculation for the data clock is:
1041a02f 10541 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10542 * But we want to avoid losing precison if possible, so:
1041a02f 10543 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10544 *
10545 * and the link clock is simpler:
1041a02f 10546 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10547 */
10548
6878da05
VS		 10549 if (!m_n->link_n)
10550 return 0;
f1f644dc 10551
6878da05
VS		 10552 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10553}
f1f644dc 10554
18442d08 10555static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10556 struct intel_crtc_state *pipe_config)
6878da05
VS		 10557{
10558 struct drm_device *dev = crtc->base.dev;
79e53945 10559
18442d08
VS		 10560 /* read out port_clock from the DPLL */
10561 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10562
f1f644dc 10563 /*
18442d08 10564 * This value does not include pixel_multiplier.
241bfc38 10565 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10566 * agree once we know their relationship in the encoder's
10567 * get_config() function.
79e53945 10568 */
2d112de7 10569 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10570 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10571 &pipe_config->fdi_m_n);
79e53945
JB		 10572}
10573
10574/** Returns the currently programmed mode of the given pipe. */
10575struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10576 struct drm_crtc *crtc)
10577{
548f245b 10578 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10580 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10581 struct drm_display_mode *mode;
5cec258b 10582 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10583 int htot = I915_READ(HTOTAL(cpu_transcoder));
10584 int hsync = I915_READ(HSYNC(cpu_transcoder));
10585 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10586 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10587 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10588
10589 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10590 if (!mode)
10591 return NULL;
10592
f1f644dc
JB		 10593 /*
10594 * Construct a pipe_config sufficient for getting the clock info
10595 * back out of crtc_clock_get.
10596 *
10597 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10598 * to use a real value here instead.
10599 */
293623f7 10600 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10601 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10602 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10603 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10604 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10605 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10606
773ae034 10607 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10608 mode->hdisplay = (htot & 0xffff) + 1;
10609 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10610 mode->hsync_start = (hsync & 0xffff) + 1;
10611 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10612 mode->vdisplay = (vtot & 0xffff) + 1;
10613 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10614 mode->vsync_start = (vsync & 0xffff) + 1;
10615 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10616
10617 drm_mode_set_name(mode);
79e53945
JB		 10618
10619 return mode;
10620}
10621
f047e395
CW		 10622void intel_mark_busy(struct drm_device *dev)
10623{
c67a470b
PZ		 10624 struct drm_i915_private *dev_priv = dev->dev_private;
10625
f62a0076
CW		 10626 if (dev_priv->mm.busy)
10627 return;
10628
43694d69 10629 intel_runtime_pm_get(dev_priv);
c67a470b 10630 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10631 if (INTEL_INFO(dev)->gen >= 6)
10632 gen6_rps_busy(dev_priv);
f62a0076 10633 dev_priv->mm.busy = true;
f047e395
CW		 10634}
10635
10636void intel_mark_idle(struct drm_device *dev)
652c393a 10637{
c67a470b 10638 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10639
f62a0076
CW		 10640 if (!dev_priv->mm.busy)
10641 return;
10642
10643 dev_priv->mm.busy = false;
10644
3d13ef2e 10645 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10646 gen6_rps_idle(dev->dev_private);
bb4cdd53 10647
43694d69 10648 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10649}
10650
79e53945
JB		 10651static void intel_crtc_destroy(struct drm_crtc *crtc)
10652{
10653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10654 struct drm_device *dev = crtc->dev;
10655 struct intel_unpin_work *work;
67e77c5a 10656
5e2d7afc 10657 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10658 work = intel_crtc->unpin_work;
10659 intel_crtc->unpin_work = NULL;
5e2d7afc 10660 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10661
10662 if (work) {
10663 cancel_work_sync(&work->work);
10664 kfree(work);
10665 }
79e53945
JB		 10666
10667 drm_crtc_cleanup(crtc);
67e77c5a 10668
79e53945
JB		 10669 kfree(intel_crtc);
10670}
10671
6b95a207
KH		 10672static void intel_unpin_work_fn(struct work_struct *__work)
10673{
10674 struct intel_unpin_work *work =
10675 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10676 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10677 struct drm_device *dev = crtc->base.dev;
10678 struct drm_plane *primary = crtc->base.primary;
6b95a207 10679
b4a98e57 10680 mutex_lock(&dev->struct_mutex);
a9ff8714 10681 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10682 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10683
7ff0ebcc 10684 intel_fbc_update(dev);
f06cc1b9
JH		 10685
10686 if (work->flip_queued_req)
146d84f0 10687 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10688 mutex_unlock(&dev->struct_mutex);
10689
a9ff8714 10690 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10691 drm_framebuffer_unreference(work->old_fb);
f99d7069 10692
a9ff8714
VS		 10693 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10694 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10695
6b95a207
KH		 10696 kfree(work);
10697}
10698
1afe3e9d 10699static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10700 struct drm_crtc *crtc)
6b95a207 10701{
6b95a207
KH		 10702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10703 struct intel_unpin_work *work;
6b95a207
KH		 10704 unsigned long flags;
10705
10706 /* Ignore early vblank irqs */
10707 if (intel_crtc == NULL)
10708 return;
10709
f326038a
DV		 10710 /*
10711 * This is called both by irq handlers and the reset code (to complete
10712 * lost pageflips) so needs the full irqsave spinlocks.
10713 */
6b95a207
KH		 10714 spin_lock_irqsave(&dev->event_lock, flags);
10715 work = intel_crtc->unpin_work;
e7d841ca
CW		 10716
10717 /* Ensure we don't miss a work->pending update ... */
10718 smp_rmb();
10719
10720 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10721 spin_unlock_irqrestore(&dev->event_lock, flags);
10722 return;
10723 }
10724
d6bbafa1 10725 page_flip_completed(intel_crtc);
0af7e4df 10726
6b95a207 10727 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10728}
10729
1afe3e9d
JB		 10730void intel_finish_page_flip(struct drm_device *dev, int pipe)
10731{
fbee40df 10732 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10733 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10734
49b14a5c 10735 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10736}
10737
10738void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10739{
fbee40df 10740 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10741 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10742
49b14a5c 10743 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10744}
10745
75f7f3ec
VS		 10746/* Is 'a' after or equal to 'b'? */
10747static bool g4x_flip_count_after_eq(u32 a, u32 b)
10748{
10749 return !((a - b) & 0x80000000);
10750}
10751
10752static bool page_flip_finished(struct intel_crtc *crtc)
10753{
10754 struct drm_device *dev = crtc->base.dev;
10755 struct drm_i915_private *dev_priv = dev->dev_private;
10756
bdfa7542
VS		 10757 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10758 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10759 return true;
10760
75f7f3ec
VS		 10761 /*
10762 * The relevant registers doen't exist on pre-ctg.
10763 * As the flip done interrupt doesn't trigger for mmio
10764 * flips on gmch platforms, a flip count check isn't
10765 * really needed there. But since ctg has the registers,
10766 * include it in the check anyway.
10767 */
10768 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10769 return true;
10770
10771 /*
10772 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10773 * used the same base address. In that case the mmio flip might
10774 * have completed, but the CS hasn't even executed the flip yet.
10775 *
10776 * A flip count check isn't enough as the CS might have updated
10777 * the base address just after start of vblank, but before we
10778 * managed to process the interrupt. This means we'd complete the
10779 * CS flip too soon.
10780 *
10781 * Combining both checks should get us a good enough result. It may
10782 * still happen that the CS flip has been executed, but has not
10783 * yet actually completed. But in case the base address is the same
10784 * anyway, we don't really care.
10785 */
10786 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10787 crtc->unpin_work->gtt_offset &&
10788 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10789 crtc->unpin_work->flip_count);
10790}
10791
6b95a207
KH		 10792void intel_prepare_page_flip(struct drm_device *dev, int plane)
10793{
fbee40df 10794 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10795 struct intel_crtc *intel_crtc =
10796 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10797 unsigned long flags;
10798
f326038a
DV		 10799
10800 /*
10801 * This is called both by irq handlers and the reset code (to complete
10802 * lost pageflips) so needs the full irqsave spinlocks.
10803 *
10804 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10805 * generate a page-flip completion irq, i.e. every modeset
10806 * is also accompanied by a spurious intel_prepare_page_flip().
10807 */
6b95a207 10808 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10809 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10810 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10811 spin_unlock_irqrestore(&dev->event_lock, flags);
10812}
10813
eba905b2 10814static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10815{
10816 /* Ensure that the work item is consistent when activating it ... */
10817 smp_wmb();
10818 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10819 /* and that it is marked active as soon as the irq could fire. */
10820 smp_wmb();
10821}
10822
8c9f3aaf
JB		 10823static int intel_gen2_queue_flip(struct drm_device *dev,
10824 struct drm_crtc *crtc,
10825 struct drm_framebuffer *fb,
ed8d1975 10826 struct drm_i915_gem_object *obj,
6258fbe2 10827 struct drm_i915_gem_request *req,
ed8d1975 10828 uint32_t flags)
8c9f3aaf 10829{
6258fbe2 10830 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10831 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10832 u32 flip_mask;
10833 int ret;
10834
5fb9de1a 10835 ret = intel_ring_begin(req, 6);
8c9f3aaf 10836 if (ret)
4fa62c89 10837 return ret;
8c9f3aaf
JB		 10838
10839 /* Can't queue multiple flips, so wait for the previous
10840 * one to finish before executing the next.
10841 */
10842 if (intel_crtc->plane)
10843 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10844 else
10845 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10846 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10847 intel_ring_emit(ring, MI_NOOP);
10848 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10849 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10850 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10851 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10852 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10853
10854 intel_mark_page_flip_active(intel_crtc);
83d4092b 10855 return 0;
8c9f3aaf
JB		 10856}
10857
10858static int intel_gen3_queue_flip(struct drm_device *dev,
10859 struct drm_crtc *crtc,
10860 struct drm_framebuffer *fb,
ed8d1975 10861 struct drm_i915_gem_object *obj,
6258fbe2 10862 struct drm_i915_gem_request *req,
ed8d1975 10863 uint32_t flags)
8c9f3aaf 10864{
6258fbe2 10865 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10867 u32 flip_mask;
10868 int ret;
10869
5fb9de1a 10870 ret = intel_ring_begin(req, 6);
8c9f3aaf 10871 if (ret)
4fa62c89 10872 return ret;
8c9f3aaf
JB		 10873
10874 if (intel_crtc->plane)
10875 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10876 else
10877 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10878 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10879 intel_ring_emit(ring, MI_NOOP);
10880 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10881 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10882 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10883 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10884 intel_ring_emit(ring, MI_NOOP);
10885
e7d841ca 10886 intel_mark_page_flip_active(intel_crtc);
83d4092b 10887 return 0;
8c9f3aaf
JB		 10888}
10889
10890static int intel_gen4_queue_flip(struct drm_device *dev,
10891 struct drm_crtc *crtc,
10892 struct drm_framebuffer *fb,
ed8d1975 10893 struct drm_i915_gem_object *obj,
6258fbe2 10894 struct drm_i915_gem_request *req,
ed8d1975 10895 uint32_t flags)
8c9f3aaf 10896{
6258fbe2 10897 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10898 struct drm_i915_private *dev_priv = dev->dev_private;
10899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10900 uint32_t pf, pipesrc;
10901 int ret;
10902
5fb9de1a 10903 ret = intel_ring_begin(req, 4);
8c9f3aaf 10904 if (ret)
4fa62c89 10905 return ret;
8c9f3aaf
JB		 10906
10907 /* i965+ uses the linear or tiled offsets from the
10908 * Display Registers (which do not change across a page-flip)
10909 * so we need only reprogram the base address.
10910 */
6d90c952
DV		 10911 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10912 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10913 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10914 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10915 obj->tiling_mode);
8c9f3aaf
JB		 10916
10917 /* XXX Enabling the panel-fitter across page-flip is so far
10918 * untested on non-native modes, so ignore it for now.
10919 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10920 */
10921 pf = 0;
10922 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10923 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10924
10925 intel_mark_page_flip_active(intel_crtc);
83d4092b 10926 return 0;
8c9f3aaf
JB		 10927}
10928
10929static int intel_gen6_queue_flip(struct drm_device *dev,
10930 struct drm_crtc *crtc,
10931 struct drm_framebuffer *fb,
ed8d1975 10932 struct drm_i915_gem_object *obj,
6258fbe2 10933 struct drm_i915_gem_request *req,
ed8d1975 10934 uint32_t flags)
8c9f3aaf 10935{
6258fbe2 10936 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10937 struct drm_i915_private *dev_priv = dev->dev_private;
10938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10939 uint32_t pf, pipesrc;
10940 int ret;
10941
5fb9de1a 10942 ret = intel_ring_begin(req, 4);
8c9f3aaf 10943 if (ret)
4fa62c89 10944 return ret;
8c9f3aaf 10945
6d90c952
DV		 10946 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10947 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10948 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10949 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10950
dc257cf1
DV		 10951 /* Contrary to the suggestions in the documentation,
10952 * "Enable Panel Fitter" does not seem to be required when page
10953 * flipping with a non-native mode, and worse causes a normal
10954 * modeset to fail.
10955 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10956 */
10957 pf = 0;
8c9f3aaf 10958 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10959 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10960
10961 intel_mark_page_flip_active(intel_crtc);
83d4092b 10962 return 0;
8c9f3aaf
JB		 10963}
10964
7c9017e5
JB		 10965static int intel_gen7_queue_flip(struct drm_device *dev,
10966 struct drm_crtc *crtc,
10967 struct drm_framebuffer *fb,
ed8d1975 10968 struct drm_i915_gem_object *obj,
6258fbe2 10969 struct drm_i915_gem_request *req,
ed8d1975 10970 uint32_t flags)
7c9017e5 10971{
6258fbe2 10972 struct intel_engine_cs *ring = req->ring;
7c9017e5 10973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10974 uint32_t plane_bit = 0;
ffe74d75
CW		 10975 int len, ret;
10976
eba905b2 10977 switch (intel_crtc->plane) {
cb05d8de
DV		 10978 case PLANE_A:
10979 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10980 break;
10981 case PLANE_B:
10982 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10983 break;
10984 case PLANE_C:
10985 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10986 break;
10987 default:
10988 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10989 return -ENODEV;
cb05d8de
DV		 10990 }
10991
ffe74d75 10992 len = 4;
f476828a 10993 if (ring->id == RCS) {
ffe74d75 10994 len += 6;
f476828a
DL		 10995 /*
10996 * On Gen 8, SRM is now taking an extra dword to accommodate
10997 * 48bits addresses, and we need a NOOP for the batch size to
10998 * stay even.
10999 */
11000 if (IS_GEN8(dev))
11001 len += 2;
11002 }
ffe74d75 11003
f66fab8e
VS		 11004 /*
11005 * BSpec MI_DISPLAY_FLIP for IVB:
11006 * "The full packet must be contained within the same cache line."
11007 *
11008 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11009 * cacheline, if we ever start emitting more commands before
11010 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11011 * then do the cacheline alignment, and finally emit the
11012 * MI_DISPLAY_FLIP.
11013 */
bba09b12 11014 ret = intel_ring_cacheline_align(req);
f66fab8e 11015 if (ret)
4fa62c89 11016 return ret;
f66fab8e 11017
5fb9de1a 11018 ret = intel_ring_begin(req, len);
7c9017e5 11019 if (ret)
4fa62c89 11020 return ret;
7c9017e5 11021
ffe74d75
CW		 11022 /* Unmask the flip-done completion message. Note that the bspec says that
11023 * we should do this for both the BCS and RCS, and that we must not unmask
11024 * more than one flip event at any time (or ensure that one flip message
11025 * can be sent by waiting for flip-done prior to queueing new flips).
11026 * Experimentation says that BCS works despite DERRMR masking all
11027 * flip-done completion events and that unmasking all planes at once
11028 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11029 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11030 */
11031 if (ring->id == RCS) {
11032 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11033 intel_ring_emit(ring, DERRMR);
11034 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11035 DERRMR_PIPEB_PRI_FLIP_DONE |
11036 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11037 if (IS_GEN8(dev))
11038 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11039 MI_SRM_LRM_GLOBAL_GTT);
11040 else
11041 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11042 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11043 intel_ring_emit(ring, DERRMR);
11044 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11045 if (IS_GEN8(dev)) {
11046 intel_ring_emit(ring, 0);
11047 intel_ring_emit(ring, MI_NOOP);
11048 }
ffe74d75
CW		 11049 }
11050
cb05d8de 11051 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11052 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11053 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11054 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11055
11056 intel_mark_page_flip_active(intel_crtc);
83d4092b 11057 return 0;
7c9017e5
JB		 11058}
11059
84c33a64
SG		 11060static bool use_mmio_flip(struct intel_engine_cs *ring,
11061 struct drm_i915_gem_object *obj)
11062{
11063 /*
11064 * This is not being used for older platforms, because
11065 * non-availability of flip done interrupt forces us to use
11066 * CS flips. Older platforms derive flip done using some clever
11067 * tricks involving the flip_pending status bits and vblank irqs.
11068 * So using MMIO flips there would disrupt this mechanism.
11069 */
11070
8e09bf83
CW		 11071 if (ring == NULL)
11072 return true;
11073
84c33a64
SG		 11074 if (INTEL_INFO(ring->dev)->gen < 5)
11075 return false;
11076
11077 if (i915.use_mmio_flip < 0)
11078 return false;
11079 else if (i915.use_mmio_flip > 0)
11080 return true;
14bf993e
OM		 11081 else if (i915.enable_execlists)
11082 return true;
84c33a64 11083 else
b4716185 11084 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11085}
11086
ff944564
DL		 11087static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11088{
11089 struct drm_device *dev = intel_crtc->base.dev;
11090 struct drm_i915_private *dev_priv = dev->dev_private;
11091 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11092 const enum pipe pipe = intel_crtc->pipe;
11093 u32 ctl, stride;
11094
11095 ctl = I915_READ(PLANE_CTL(pipe, 0));
11096 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11097 switch (fb->modifier[0]) {
11098 case DRM_FORMAT_MOD_NONE:
11099 break;
11100 case I915_FORMAT_MOD_X_TILED:
ff944564 11101 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11102 break;
11103 case I915_FORMAT_MOD_Y_TILED:
11104 ctl |= PLANE_CTL_TILED_Y;
11105 break;
11106 case I915_FORMAT_MOD_Yf_TILED:
11107 ctl |= PLANE_CTL_TILED_YF;
11108 break;
11109 default:
11110 MISSING_CASE(fb->modifier[0]);
11111 }
ff944564
DL		 11112
11113 /*
11114 * The stride is either expressed as a multiple of 64 bytes chunks for
11115 * linear buffers or in number of tiles for tiled buffers.
11116 */
2ebef630
TU		 11117 stride = fb->pitches[0] /
11118 intel_fb_stride_alignment(dev, fb->modifier[0],
11119 fb->pixel_format);
ff944564
DL		 11120
11121 /*
11122 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11123 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11124 */
11125 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11126 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11127
11128 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11129 POSTING_READ(PLANE_SURF(pipe, 0));
11130}
11131
11132static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11133{
11134 struct drm_device *dev = intel_crtc->base.dev;
11135 struct drm_i915_private *dev_priv = dev->dev_private;
11136 struct intel_framebuffer *intel_fb =
11137 to_intel_framebuffer(intel_crtc->base.primary->fb);
11138 struct drm_i915_gem_object *obj = intel_fb->obj;
11139 u32 dspcntr;
11140 u32 reg;
11141
84c33a64
SG		 11142 reg = DSPCNTR(intel_crtc->plane);
11143 dspcntr = I915_READ(reg);
11144
c5d97472
DL		 11145 if (obj->tiling_mode != I915_TILING_NONE)
11146 dspcntr |= DISPPLANE_TILED;
11147 else
11148 dspcntr &= ~DISPPLANE_TILED;
11149
84c33a64
SG		 11150 I915_WRITE(reg, dspcntr);
11151
11152 I915_WRITE(DSPSURF(intel_crtc->plane),
11153 intel_crtc->unpin_work->gtt_offset);
11154 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11155
ff944564
DL		 11156}
11157
11158/*
11159 * XXX: This is the temporary way to update the plane registers until we get
11160 * around to using the usual plane update functions for MMIO flips
11161 */
11162static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11163{
11164 struct drm_device *dev = intel_crtc->base.dev;
11165 bool atomic_update;
11166 u32 start_vbl_count;
11167
11168 intel_mark_page_flip_active(intel_crtc);
11169
11170 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11171
11172 if (INTEL_INFO(dev)->gen >= 9)
11173 skl_do_mmio_flip(intel_crtc);
11174 else
11175 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11176 ilk_do_mmio_flip(intel_crtc);
11177
9362c7c5
ACO		 11178 if (atomic_update)
11179 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11180}
11181
9362c7c5 11182static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11183{
b2cfe0ab
CW		 11184 struct intel_mmio_flip *mmio_flip =
11185 container_of(work, struct intel_mmio_flip, work);
84c33a64 11186
eed29a5b
DV		 11187 if (mmio_flip->req)
11188 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11189 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11190 false, NULL,
11191 &mmio_flip->i915->rps.mmioflips));
84c33a64 11192
b2cfe0ab
CW		 11193 intel_do_mmio_flip(mmio_flip->crtc);
11194
eed29a5b 11195 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11196 kfree(mmio_flip);
84c33a64
SG		 11197}
11198
11199static int intel_queue_mmio_flip(struct drm_device *dev,
11200 struct drm_crtc *crtc,
11201 struct drm_framebuffer *fb,
11202 struct drm_i915_gem_object *obj,
11203 struct intel_engine_cs *ring,
11204 uint32_t flags)
11205{
b2cfe0ab
CW		 11206 struct intel_mmio_flip *mmio_flip;
11207
11208 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11209 if (mmio_flip == NULL)
11210 return -ENOMEM;
84c33a64 11211
bcafc4e3 11212 mmio_flip->i915 = to_i915(dev);
eed29a5b 11213 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11214 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11215
b2cfe0ab
CW		 11216 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11217 schedule_work(&mmio_flip->work);
84c33a64 11218
84c33a64
SG		 11219 return 0;
11220}
11221
8c9f3aaf
JB		 11222static int intel_default_queue_flip(struct drm_device *dev,
11223 struct drm_crtc *crtc,
11224 struct drm_framebuffer *fb,
ed8d1975 11225 struct drm_i915_gem_object *obj,
6258fbe2 11226 struct drm_i915_gem_request *req,
ed8d1975 11227 uint32_t flags)
8c9f3aaf
JB		 11228{
11229 return -ENODEV;
11230}
11231
d6bbafa1
CW		 11232static bool __intel_pageflip_stall_check(struct drm_device *dev,
11233 struct drm_crtc *crtc)
11234{
11235 struct drm_i915_private *dev_priv = dev->dev_private;
11236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11237 struct intel_unpin_work *work = intel_crtc->unpin_work;
11238 u32 addr;
11239
11240 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11241 return true;
11242
11243 if (!work->enable_stall_check)
11244 return false;
11245
11246 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11247 if (work->flip_queued_req &&
11248 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11249 return false;
11250
1e3feefd 11251 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11252 }
11253
1e3feefd 11254 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11255 return false;
11256
11257 /* Potential stall - if we see that the flip has happened,
11258 * assume a missed interrupt. */
11259 if (INTEL_INFO(dev)->gen >= 4)
11260 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11261 else
11262 addr = I915_READ(DSPADDR(intel_crtc->plane));
11263
11264 /* There is a potential issue here with a false positive after a flip
11265 * to the same address. We could address this by checking for a
11266 * non-incrementing frame counter.
11267 */
11268 return addr == work->gtt_offset;
11269}
11270
11271void intel_check_page_flip(struct drm_device *dev, int pipe)
11272{
11273 struct drm_i915_private *dev_priv = dev->dev_private;
11274 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11276 struct intel_unpin_work *work;
f326038a 11277
6c51d46f 11278 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11279
11280 if (crtc == NULL)
11281 return;
11282
f326038a 11283 spin_lock(&dev->event_lock);
6ad790c0
CW		 11284 work = intel_crtc->unpin_work;
11285 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11286 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11287 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11288 page_flip_completed(intel_crtc);
6ad790c0 11289 work = NULL;
d6bbafa1 11290 }
6ad790c0
CW		 11291 if (work != NULL &&
11292 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11293 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11294 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11295}
11296
6b95a207
KH		 11297static int intel_crtc_page_flip(struct drm_crtc *crtc,
11298 struct drm_framebuffer *fb,
ed8d1975
KP		 11299 struct drm_pending_vblank_event *event,
11300 uint32_t page_flip_flags)
6b95a207
KH		 11301{
11302 struct drm_device *dev = crtc->dev;
11303 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11304 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11305 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11307 struct drm_plane *primary = crtc->primary;
a071fa00 11308 enum pipe pipe = intel_crtc->pipe;
6b95a207 11309 struct intel_unpin_work *work;
a4872ba6 11310 struct intel_engine_cs *ring;
cf5d8a46 11311 bool mmio_flip;
91af127f 11312 struct drm_i915_gem_request *request = NULL;
52e68630 11313 int ret;
6b95a207 11314
2ff8fde1
MR		 11315 /*
11316 * drm_mode_page_flip_ioctl() should already catch this, but double
11317 * check to be safe. In the future we may enable pageflipping from
11318 * a disabled primary plane.
11319 */
11320 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11321 return -EBUSY;
11322
e6a595d2 11323 /* Can't change pixel format via MI display flips. */
f4510a27 11324 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11325 return -EINVAL;
11326
11327 /*
11328 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11329 * Note that pitch changes could also affect these register.
11330 */
11331 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11332 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11333 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11334 return -EINVAL;
11335
f900db47
CW		 11336 if (i915_terminally_wedged(&dev_priv->gpu_error))
11337 goto out_hang;
11338
b14c5679 11339 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11340 if (work == NULL)
11341 return -ENOMEM;
11342
6b95a207 11343 work->event = event;
b4a98e57 11344 work->crtc = crtc;
ab8d6675 11345 work->old_fb = old_fb;
6b95a207
KH		 11346 INIT_WORK(&work->work, intel_unpin_work_fn);
11347
87b6b101 11348 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11349 if (ret)
11350 goto free_work;
11351
6b95a207 11352 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11353 spin_lock_irq(&dev->event_lock);
6b95a207 11354 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11355 /* Before declaring the flip queue wedged, check if
11356 * the hardware completed the operation behind our backs.
11357 */
11358 if (__intel_pageflip_stall_check(dev, crtc)) {
11359 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11360 page_flip_completed(intel_crtc);
11361 } else {
11362 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11363 spin_unlock_irq(&dev->event_lock);
468f0b44 11364
d6bbafa1
CW		 11365 drm_crtc_vblank_put(crtc);
11366 kfree(work);
11367 return -EBUSY;
11368 }
6b95a207
KH		 11369 }
11370 intel_crtc->unpin_work = work;
5e2d7afc 11371 spin_unlock_irq(&dev->event_lock);
6b95a207 11372
b4a98e57
CW		 11373 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11374 flush_workqueue(dev_priv->wq);
11375
75dfca80 11376 /* Reference the objects for the scheduled work. */
ab8d6675 11377 drm_framebuffer_reference(work->old_fb);
05394f39 11378 drm_gem_object_reference(&obj->base);
6b95a207 11379
f4510a27 11380 crtc->primary->fb = fb;
afd65eb4 11381 update_state_fb(crtc->primary);
1ed1f968 11382
e1f99ce6 11383 work->pending_flip_obj = obj;
e1f99ce6 11384
89ed88ba
CW		 11385 ret = i915_mutex_lock_interruptible(dev);
11386 if (ret)
11387 goto cleanup;
11388
b4a98e57 11389 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11390 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11391
75f7f3ec 11392 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11393 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11394
4fa62c89
VS		 11395 if (IS_VALLEYVIEW(dev)) {
11396 ring = &dev_priv->ring[BCS];
ab8d6675 11397 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11398 /* vlv: DISPLAY_FLIP fails to change tiling */
11399 ring = NULL;
48bf5b2d 11400 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11401 ring = &dev_priv->ring[BCS];
4fa62c89 11402 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11403 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11404 if (ring == NULL || ring->id != RCS)
11405 ring = &dev_priv->ring[BCS];
11406 } else {
11407 ring = &dev_priv->ring[RCS];
11408 }
11409
cf5d8a46
CW		 11410 mmio_flip = use_mmio_flip(ring, obj);
11411
11412 /* When using CS flips, we want to emit semaphores between rings.
11413 * However, when using mmio flips we will create a task to do the
11414 * synchronisation, so all we want here is to pin the framebuffer
11415 * into the display plane and skip any waits.
11416 */
82bc3b2d 11417 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11418 crtc->primary->state,
91af127f 11419 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11420 if (ret)
11421 goto cleanup_pending;
6b95a207 11422
121920fa
TU		 11423 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11424 + intel_crtc->dspaddr_offset;
4fa62c89 11425
cf5d8a46 11426 if (mmio_flip) {
84c33a64
SG		 11427 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11428 page_flip_flags);
d6bbafa1
CW		 11429 if (ret)
11430 goto cleanup_unpin;
11431
f06cc1b9
JH		 11432 i915_gem_request_assign(&work->flip_queued_req,
11433 obj->last_write_req);
d6bbafa1 11434 } else {
6258fbe2
JH		 11435 if (!request) {
11436 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11437 if (ret)
11438 goto cleanup_unpin;
11439 }
11440
11441 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11442 page_flip_flags);
11443 if (ret)
11444 goto cleanup_unpin;
11445
6258fbe2 11446 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11447 }
11448
91af127f 11449 if (request)
75289874 11450 i915_add_request_no_flush(request);
91af127f 11451
1e3feefd 11452 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11453 work->enable_stall_check = true;
4fa62c89 11454
ab8d6675 11455 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11456 to_intel_plane(primary)->frontbuffer_bit);
a071fa00 11457
7ff0ebcc 11458 intel_fbc_disable(dev);
a9ff8714
VS		 11459 intel_frontbuffer_flip_prepare(dev,
11460 to_intel_plane(primary)->frontbuffer_bit);
6b95a207
KH		 11461 mutex_unlock(&dev->struct_mutex);
11462
e5510fac
JB		 11463 trace_i915_flip_request(intel_crtc->plane, obj);
11464
6b95a207 11465 return 0;
96b099fd 11466
4fa62c89 11467cleanup_unpin:
82bc3b2d 11468 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11469cleanup_pending:
91af127f
JH		 11470 if (request)
11471 i915_gem_request_cancel(request);
b4a98e57 11472 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11473 mutex_unlock(&dev->struct_mutex);
11474cleanup:
f4510a27 11475 crtc->primary->fb = old_fb;
afd65eb4 11476 update_state_fb(crtc->primary);
89ed88ba
CW		 11477
11478 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11479 drm_framebuffer_unreference(work->old_fb);
96b099fd 11480
5e2d7afc 11481 spin_lock_irq(&dev->event_lock);
96b099fd 11482 intel_crtc->unpin_work = NULL;
5e2d7afc 11483 spin_unlock_irq(&dev->event_lock);
96b099fd 11484
87b6b101 11485 drm_crtc_vblank_put(crtc);
7317c75e 11486free_work:
96b099fd
CW		 11487 kfree(work);
11488
f900db47 11489 if (ret == -EIO) {
02e0efb5
ML		 11490 struct drm_atomic_state *state;
11491 struct drm_plane_state *plane_state;
11492
f900db47 11493out_hang:
02e0efb5
ML		 11494 state = drm_atomic_state_alloc(dev);
11495 if (!state)
11496 return -ENOMEM;
11497 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11498
11499retry:
11500 plane_state = drm_atomic_get_plane_state(state, primary);
11501 ret = PTR_ERR_OR_ZERO(plane_state);
11502 if (!ret) {
11503 drm_atomic_set_fb_for_plane(plane_state, fb);
11504
11505 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11506 if (!ret)
11507 ret = drm_atomic_commit(state);
11508 }
11509
11510 if (ret == -EDEADLK) {
11511 drm_modeset_backoff(state->acquire_ctx);
11512 drm_atomic_state_clear(state);
11513 goto retry;
11514 }
11515
11516 if (ret)
11517 drm_atomic_state_free(state);
11518
f0d3dad3 11519 if (ret == 0 && event) {
5e2d7afc 11520 spin_lock_irq(&dev->event_lock);
a071fa00 11521 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11522 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11523 }
f900db47 11524 }
96b099fd 11525 return ret;
6b95a207
KH		 11526}
11527
da20eabd
ML		 11528
11529/**
11530 * intel_wm_need_update - Check whether watermarks need updating
11531 * @plane: drm plane
11532 * @state: new plane state
11533 *
11534 * Check current plane state versus the new one to determine whether
11535 * watermarks need to be recalculated.
11536 *
11537 * Returns true or false.
11538 */
11539static bool intel_wm_need_update(struct drm_plane *plane,
11540 struct drm_plane_state *state)
11541{
11542 /* Update watermarks on tiling changes. */
11543 if (!plane->state->fb || !state->fb ||
11544 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11545 plane->state->rotation != state->rotation)
11546 return true;
11547
11548 if (plane->state->crtc_w != state->crtc_w)
11549 return true;
11550
11551 return false;
11552}
11553
11554int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11555 struct drm_plane_state *plane_state)
11556{
11557 struct drm_crtc *crtc = crtc_state->crtc;
11558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11559 struct drm_plane *plane = plane_state->plane;
11560 struct drm_device *dev = crtc->dev;
11561 struct drm_i915_private *dev_priv = dev->dev_private;
11562 struct intel_plane_state *old_plane_state =
11563 to_intel_plane_state(plane->state);
11564 int idx = intel_crtc->base.base.id, ret;
11565 int i = drm_plane_index(plane);
11566 bool mode_changed = needs_modeset(crtc_state);
11567 bool was_crtc_enabled = crtc->state->active;
11568 bool is_crtc_enabled = crtc_state->active;
11569
11570 bool turn_off, turn_on, visible, was_visible;
11571 struct drm_framebuffer *fb = plane_state->fb;
11572
11573 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11574 plane->type != DRM_PLANE_TYPE_CURSOR) {
11575 ret = skl_update_scaler_plane(
11576 to_intel_crtc_state(crtc_state),
11577 to_intel_plane_state(plane_state));
11578 if (ret)
11579 return ret;
11580 }
11581
11582 /*
11583 * Disabling a plane is always okay; we just need to update
11584 * fb tracking in a special way since cleanup_fb() won't
11585 * get called by the plane helpers.
11586 */
11587 if (old_plane_state->base.fb && !fb)
11588 intel_crtc->atomic.disabled_planes |= 1 << i;
11589
da20eabd
ML		 11590 was_visible = old_plane_state->visible;
11591 visible = to_intel_plane_state(plane_state)->visible;
11592
11593 if (!was_crtc_enabled && WARN_ON(was_visible))
11594 was_visible = false;
11595
11596 if (!is_crtc_enabled && WARN_ON(visible))
11597 visible = false;
11598
11599 if (!was_visible && !visible)
11600 return 0;
11601
11602 turn_off = was_visible && (!visible || mode_changed);
11603 turn_on = visible && (!was_visible || mode_changed);
11604
11605 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11606 plane->base.id, fb ? fb->base.id : -1);
11607
11608 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11609 plane->base.id, was_visible, visible,
11610 turn_off, turn_on, mode_changed);
11611
f015c551
VS		 11612 if (turn_on)
11613 intel_crtc->atomic.update_wm_pre = true;
11614 else if (turn_off)
11615 intel_crtc->atomic.update_wm_post = true;
11616 else if (intel_wm_need_update(plane, plane_state))
11617 intel_crtc->atomic.update_wm_pre = true;
da20eabd 11618
a9ff8714
VS		 11619 if (visible)
11620 intel_crtc->atomic.fb_bits |=
11621 to_intel_plane(plane)->frontbuffer_bit;
11622
da20eabd
ML		 11623 switch (plane->type) {
11624 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11625 intel_crtc->atomic.wait_for_flips = true;
11626 intel_crtc->atomic.pre_disable_primary = turn_off;
11627 intel_crtc->atomic.post_enable_primary = turn_on;
11628
066cf55b
RV		 11629 if (turn_off) {
11630 /*
11631 * FIXME: Actually if we will still have any other
11632 * plane enabled on the pipe we could let IPS enabled
11633 * still, but for now lets consider that when we make
11634 * primary invisible by setting DSPCNTR to 0 on
11635 * update_primary_plane function IPS needs to be
11636 * disable.
11637 */
11638 intel_crtc->atomic.disable_ips = true;
11639
da20eabd 11640 intel_crtc->atomic.disable_fbc = true;
066cf55b 11641 }
da20eabd
ML		 11642
11643 /*
11644 * FBC does not work on some platforms for rotated
11645 * planes, so disable it when rotation is not 0 and
11646 * update it when rotation is set back to 0.
11647 *
11648 * FIXME: This is redundant with the fbc update done in
11649 * the primary plane enable function except that that
11650 * one is done too late. We eventually need to unify
11651 * this.
11652 */
11653
11654 if (visible &&
11655 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11656 dev_priv->fbc.crtc == intel_crtc &&
11657 plane_state->rotation != BIT(DRM_ROTATE_0))
11658 intel_crtc->atomic.disable_fbc = true;
11659
11660 /*
11661 * BDW signals flip done immediately if the plane
11662 * is disabled, even if the plane enable is already
11663 * armed to occur at the next vblank :(
11664 */
11665 if (turn_on && IS_BROADWELL(dev))
11666 intel_crtc->atomic.wait_vblank = true;
11667
11668 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11669 break;
11670 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11671 break;
11672 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11673 if (turn_off && !mode_changed) {
da20eabd
ML		 11674 intel_crtc->atomic.wait_vblank = true;
11675 intel_crtc->atomic.update_sprite_watermarks |=
11676 1 << i;
11677 }
da20eabd
ML		 11678 }
11679 return 0;
11680}
11681
6d3a1ce7
ML		 11682static bool encoders_cloneable(const struct intel_encoder *a,
11683 const struct intel_encoder *b)
11684{
11685 /* masks could be asymmetric, so check both ways */
11686 return a == b || (a->cloneable & (1 << b->type) &&
11687 b->cloneable & (1 << a->type));
11688}
11689
11690static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11691 struct intel_crtc *crtc,
11692 struct intel_encoder *encoder)
11693{
11694 struct intel_encoder *source_encoder;
11695 struct drm_connector *connector;
11696 struct drm_connector_state *connector_state;
11697 int i;
11698
11699 for_each_connector_in_state(state, connector, connector_state, i) {
11700 if (connector_state->crtc != &crtc->base)
11701 continue;
11702
11703 source_encoder =
11704 to_intel_encoder(connector_state->best_encoder);
11705 if (!encoders_cloneable(encoder, source_encoder))
11706 return false;
11707 }
11708
11709 return true;
11710}
11711
11712static bool check_encoder_cloning(struct drm_atomic_state *state,
11713 struct intel_crtc *crtc)
11714{
11715 struct intel_encoder *encoder;
11716 struct drm_connector *connector;
11717 struct drm_connector_state *connector_state;
11718 int i;
11719
11720 for_each_connector_in_state(state, connector, connector_state, i) {
11721 if (connector_state->crtc != &crtc->base)
11722 continue;
11723
11724 encoder = to_intel_encoder(connector_state->best_encoder);
11725 if (!check_single_encoder_cloning(state, crtc, encoder))
11726 return false;
11727 }
11728
11729 return true;
11730}
11731
d032ffa0
ML		 11732static void intel_crtc_check_initial_planes(struct drm_crtc *crtc,
11733 struct drm_crtc_state *crtc_state)
11734{
11735 struct intel_crtc_state *pipe_config =
11736 to_intel_crtc_state(crtc_state);
11737 struct drm_plane *p;
11738 unsigned visible_mask = 0;
11739
11740 drm_for_each_plane_mask(p, crtc->dev, crtc_state->plane_mask) {
11741 struct drm_plane_state *plane_state =
11742 drm_atomic_get_existing_plane_state(crtc_state->state, p);
11743
11744 if (WARN_ON(!plane_state))
11745 continue;
11746
11747 if (!plane_state->fb)
11748 crtc_state->plane_mask &=
11749 ~(1 << drm_plane_index(p));
11750 else if (to_intel_plane_state(plane_state)->visible)
11751 visible_mask |= 1 << drm_plane_index(p);
11752 }
11753
11754 if (!visible_mask)
11755 return;
11756
11757 pipe_config->quirks &= ~PIPE_CONFIG_QUIRK_INITIAL_PLANES;
11758}
11759
6d3a1ce7
ML		 11760static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11761 struct drm_crtc_state *crtc_state)
11762{
cf5a15be 11763 struct drm_device *dev = crtc->dev;
ad421372 11764 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11766 struct intel_crtc_state *pipe_config =
11767 to_intel_crtc_state(crtc_state);
6d3a1ce7 11768 struct drm_atomic_state *state = crtc_state->state;
ad421372 11769 int ret, idx = crtc->base.id;
6d3a1ce7
ML		 11770 bool mode_changed = needs_modeset(crtc_state);
11771
11772 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11773 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11774 return -EINVAL;
11775 }
11776
11777 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11778 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11779 idx, crtc->state->active, intel_crtc->active);
11780
d032ffa0
ML		 11781 /* plane mask is fixed up after all initial planes are calculated */
11782 if (pipe_config->quirks & PIPE_CONFIG_QUIRK_INITIAL_PLANES)
11783 intel_crtc_check_initial_planes(crtc, crtc_state);
11784
eddfcbcd 11785 if (mode_changed)
f015c551 11786 intel_crtc->atomic.update_wm_post = !crtc_state->active;
eddfcbcd 11787
ad421372
ML		 11788 if (mode_changed && crtc_state->enable &&
11789 dev_priv->display.crtc_compute_clock &&
11790 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11791 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11792 pipe_config);
11793 if (ret)
11794 return ret;
11795 }
11796
cf5a15be 11797 return intel_atomic_setup_scalers(dev, intel_crtc, pipe_config);
6d3a1ce7
ML		 11798}
11799
65b38e0d 11800static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11801 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11802 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11803 .atomic_begin = intel_begin_crtc_commit,
11804 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11805 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11806};
11807
9a935856
DV		 11808/**
11809 * intel_modeset_update_staged_output_state
11810 *
11811 * Updates the staged output configuration state, e.g. after we've read out the
11812 * current hw state.
11813 */
11814static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11815{
7668851f 11816 struct intel_crtc *crtc;
9a935856
DV		 11817 struct intel_encoder *encoder;
11818 struct intel_connector *connector;
f6e5b160 11819
3a3371ff 11820 for_each_intel_connector(dev, connector) {
9a935856
DV		 11821 connector->new_encoder =
11822 to_intel_encoder(connector->base.encoder);
11823 }
f6e5b160 11824
b2784e15 11825 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11826 encoder->new_crtc =
11827 to_intel_crtc(encoder->base.crtc);
11828 }
7668851f 11829
d3fcc808 11830 for_each_intel_crtc(dev, crtc) {
83d65738 11831 crtc->new_enabled = crtc->base.state->enable;
7668851f 11832 }
f6e5b160
CW		 11833}
11834
d29b2f9d
ACO		 11835/* Transitional helper to copy current connector/encoder state to
11836 * connector->state. This is needed so that code that is partially
11837 * converted to atomic does the right thing.
11838 */
11839static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11840{
11841 struct intel_connector *connector;
11842
11843 for_each_intel_connector(dev, connector) {
11844 if (connector->base.encoder) {
11845 connector->base.state->best_encoder =
11846 connector->base.encoder;
11847 connector->base.state->crtc =
11848 connector->base.encoder->crtc;
11849 } else {
11850 connector->base.state->best_encoder = NULL;
11851 connector->base.state->crtc = NULL;
11852 }
11853 }
11854}
11855
050f7aeb 11856static void
eba905b2 11857connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11858 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11859{
11860 int bpp = pipe_config->pipe_bpp;
11861
11862 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11863 connector->base.base.id,
c23cc417 11864 connector->base.name);
050f7aeb
DV		 11865
11866 /* Don't use an invalid EDID bpc value */
11867 if (connector->base.display_info.bpc &&
11868 connector->base.display_info.bpc * 3 < bpp) {
11869 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11870 bpp, connector->base.display_info.bpc*3);
11871 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11872 }
11873
11874 /* Clamp bpp to 8 on screens without EDID 1.4 */
11875 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11876 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11877 bpp);
11878 pipe_config->pipe_bpp = 24;
11879 }
11880}
11881
4e53c2e0 11882static int
050f7aeb 11883compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11884 struct intel_crtc_state *pipe_config)
4e53c2e0 11885{
050f7aeb 11886 struct drm_device *dev = crtc->base.dev;
1486017f 11887 struct drm_atomic_state *state;
da3ced29
ACO		 11888 struct drm_connector *connector;
11889 struct drm_connector_state *connector_state;
1486017f 11890 int bpp, i;
4e53c2e0 11891
d328c9d7 11892 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11893 bpp = 10*3;
d328c9d7
DV		 11894 else if (INTEL_INFO(dev)->gen >= 5)
11895 bpp = 12*3;
11896 else
11897 bpp = 8*3;
11898
4e53c2e0 11899
4e53c2e0
DV		 11900 pipe_config->pipe_bpp = bpp;
11901
1486017f
ACO		 11902 state = pipe_config->base.state;
11903
4e53c2e0 11904 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11905 for_each_connector_in_state(state, connector, connector_state, i) {
11906 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11907 continue;
11908
da3ced29
ACO		 11909 connected_sink_compute_bpp(to_intel_connector(connector),
11910 pipe_config);
4e53c2e0
DV		 11911 }
11912
11913 return bpp;
11914}
11915
644db711
DV		 11916static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11917{
11918 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11919 "type: 0x%x flags: 0x%x\n",
1342830c 11920 mode->crtc_clock,
644db711
DV		 11921 mode->crtc_hdisplay, mode->crtc_hsync_start,
11922 mode->crtc_hsync_end, mode->crtc_htotal,
11923 mode->crtc_vdisplay, mode->crtc_vsync_start,
11924 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11925}
11926
c0b03411 11927static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11928 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11929 const char *context)
11930{
6a60cd87
CK		 11931 struct drm_device *dev = crtc->base.dev;
11932 struct drm_plane *plane;
11933 struct intel_plane *intel_plane;
11934 struct intel_plane_state *state;
11935 struct drm_framebuffer *fb;
11936
11937 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11938 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11939
11940 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11941 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11942 pipe_config->pipe_bpp, pipe_config->dither);
11943 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11944 pipe_config->has_pch_encoder,
11945 pipe_config->fdi_lanes,
11946 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11947 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11948 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11949 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11950 pipe_config->has_dp_encoder,
11951 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11952 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11953 pipe_config->dp_m_n.tu);
b95af8be
VK		 11954
11955 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11956 pipe_config->has_dp_encoder,
11957 pipe_config->dp_m2_n2.gmch_m,
11958 pipe_config->dp_m2_n2.gmch_n,
11959 pipe_config->dp_m2_n2.link_m,
11960 pipe_config->dp_m2_n2.link_n,
11961 pipe_config->dp_m2_n2.tu);
11962
55072d19
DV		 11963 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11964 pipe_config->has_audio,
11965 pipe_config->has_infoframe);
11966
c0b03411 11967 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11968 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11969 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11970 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11971 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11972 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11973 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11974 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11975 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11976 crtc->num_scalers,
11977 pipe_config->scaler_state.scaler_users,
11978 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11979 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11980 pipe_config->gmch_pfit.control,
11981 pipe_config->gmch_pfit.pgm_ratios,
11982 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11983 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11984 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11985 pipe_config->pch_pfit.size,
11986 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11987 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11988 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11989
415ff0f6
TU		 11990 if (IS_BROXTON(dev)) {
11991 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11992 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11993 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11994 pipe_config->ddi_pll_sel,
11995 pipe_config->dpll_hw_state.ebb0,
11996 pipe_config->dpll_hw_state.pll0,
11997 pipe_config->dpll_hw_state.pll1,
11998 pipe_config->dpll_hw_state.pll2,
11999 pipe_config->dpll_hw_state.pll3,
12000 pipe_config->dpll_hw_state.pll6,
12001 pipe_config->dpll_hw_state.pll8,
12002 pipe_config->dpll_hw_state.pcsdw12);
12003 } else if (IS_SKYLAKE(dev)) {
12004 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12005 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12006 pipe_config->ddi_pll_sel,
12007 pipe_config->dpll_hw_state.ctrl1,
12008 pipe_config->dpll_hw_state.cfgcr1,
12009 pipe_config->dpll_hw_state.cfgcr2);
12010 } else if (HAS_DDI(dev)) {
12011 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12012 pipe_config->ddi_pll_sel,
12013 pipe_config->dpll_hw_state.wrpll);
12014 } else {
12015 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12016 "fp0: 0x%x, fp1: 0x%x\n",
12017 pipe_config->dpll_hw_state.dpll,
12018 pipe_config->dpll_hw_state.dpll_md,
12019 pipe_config->dpll_hw_state.fp0,
12020 pipe_config->dpll_hw_state.fp1);
12021 }
12022
6a60cd87
CK		 12023 DRM_DEBUG_KMS("planes on this crtc\n");
12024 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12025 intel_plane = to_intel_plane(plane);
12026 if (intel_plane->pipe != crtc->pipe)
12027 continue;
12028
12029 state = to_intel_plane_state(plane->state);
12030 fb = state->base.fb;
12031 if (!fb) {
12032 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12033 "disabled, scaler_id = %d\n",
12034 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12035 plane->base.id, intel_plane->pipe,
12036 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12037 drm_plane_index(plane), state->scaler_id);
12038 continue;
12039 }
12040
12041 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12042 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12043 plane->base.id, intel_plane->pipe,
12044 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12045 drm_plane_index(plane));
12046 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12047 fb->base.id, fb->width, fb->height, fb->pixel_format);
12048 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12049 state->scaler_id,
12050 state->src.x1 >> 16, state->src.y1 >> 16,
12051 drm_rect_width(&state->src) >> 16,
12052 drm_rect_height(&state->src) >> 16,
12053 state->dst.x1, state->dst.y1,
12054 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12055 }
c0b03411
DV		 12056}
12057
5448a00d 12058static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12059{
5448a00d
ACO		 12060 struct drm_device *dev = state->dev;
12061 struct intel_encoder *encoder;
da3ced29 12062 struct drm_connector *connector;
5448a00d 12063 struct drm_connector_state *connector_state;
00f0b378 12064 unsigned int used_ports = 0;
5448a00d 12065 int i;
00f0b378
VS		 12066
12067 /*
12068 * Walk the connector list instead of the encoder
12069 * list to detect the problem on ddi platforms
12070 * where there's just one encoder per digital port.
12071 */
da3ced29 12072 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12073 if (!connector_state->best_encoder)
00f0b378
VS		 12074 continue;
12075
5448a00d
ACO		 12076 encoder = to_intel_encoder(connector_state->best_encoder);
12077
12078 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12079
12080 switch (encoder->type) {
12081 unsigned int port_mask;
12082 case INTEL_OUTPUT_UNKNOWN:
12083 if (WARN_ON(!HAS_DDI(dev)))
12084 break;
12085 case INTEL_OUTPUT_DISPLAYPORT:
12086 case INTEL_OUTPUT_HDMI:
12087 case INTEL_OUTPUT_EDP:
12088 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12089
12090 /* the same port mustn't appear more than once */
12091 if (used_ports & port_mask)
12092 return false;
12093
12094 used_ports |= port_mask;
12095 default:
12096 break;
12097 }
12098 }
12099
12100 return true;
12101}
12102
83a57153
ACO		 12103static void
12104clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12105{
12106 struct drm_crtc_state tmp_state;
663a3640 12107 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12108 struct intel_dpll_hw_state dpll_hw_state;
12109 enum intel_dpll_id shared_dpll;
8504c74c 12110 uint32_t ddi_pll_sel;
83a57153 12111
7546a384
ACO		 12112 /* FIXME: before the switch to atomic started, a new pipe_config was
12113 * kzalloc'd. Code that depends on any field being zero should be
12114 * fixed, so that the crtc_state can be safely duplicated. For now,
12115 * only fields that are know to not cause problems are preserved. */
12116
83a57153 12117 tmp_state = crtc_state->base;
663a3640 12118 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12119 shared_dpll = crtc_state->shared_dpll;
12120 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12121 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12122
83a57153 12123 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12124
83a57153 12125 crtc_state->base = tmp_state;
663a3640 12126 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12127 crtc_state->shared_dpll = shared_dpll;
12128 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12129 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12130}
12131
548ee15b 12132static int
b8cecdf5 12133intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12134 struct intel_crtc_state *pipe_config)
ee7b9f93 12135{
b359283a 12136 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12137 struct intel_encoder *encoder;
da3ced29 12138 struct drm_connector *connector;
0b901879 12139 struct drm_connector_state *connector_state;
d328c9d7 12140 int base_bpp, ret = -EINVAL;
0b901879 12141 int i;
e29c22c0 12142 bool retry = true;
ee7b9f93 12143
83a57153 12144 clear_intel_crtc_state(pipe_config);
7758a113 12145
e143a21c
DV		 12146 pipe_config->cpu_transcoder =
12147 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12148
2960bc9c
ID		 12149 /*
12150 * Sanitize sync polarity flags based on requested ones. If neither
12151 * positive or negative polarity is requested, treat this as meaning
12152 * negative polarity.
12153 */
2d112de7 12154 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12155 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12156 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12157
2d112de7 12158 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12159 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12160 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12161
050f7aeb
DV		 12162 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12163 * plane pixel format and any sink constraints into account. Returns the
12164 * source plane bpp so that dithering can be selected on mismatches
12165 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12166 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12167 pipe_config);
12168 if (base_bpp < 0)
4e53c2e0
DV		 12169 goto fail;
12170
e41a56be
VS		 12171 /*
12172 * Determine the real pipe dimensions. Note that stereo modes can
12173 * increase the actual pipe size due to the frame doubling and
12174 * insertion of additional space for blanks between the frame. This
12175 * is stored in the crtc timings. We use the requested mode to do this
12176 * computation to clearly distinguish it from the adjusted mode, which
12177 * can be changed by the connectors in the below retry loop.
12178 */
2d112de7 12179 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12180 &pipe_config->pipe_src_w,
12181 &pipe_config->pipe_src_h);
e41a56be 12182
e29c22c0 12183encoder_retry:
ef1b460d 12184 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12185 pipe_config->port_clock = 0;
ef1b460d 12186 pipe_config->pixel_multiplier = 1;
ff9a6750 12187
135c81b8 12188 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12189 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12190 CRTC_STEREO_DOUBLE);
135c81b8 12191
7758a113
DV		 12192 /* Pass our mode to the connectors and the CRTC to give them a chance to
12193 * adjust it according to limitations or connector properties, and also
12194 * a chance to reject the mode entirely.
47f1c6c9 12195 */
da3ced29 12196 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12197 if (connector_state->crtc != crtc)
7758a113 12198 continue;
7ae89233 12199
0b901879
ACO		 12200 encoder = to_intel_encoder(connector_state->best_encoder);
12201
efea6e8e
DV		 12202 if (!(encoder->compute_config(encoder, pipe_config))) {
12203 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12204 goto fail;
12205 }
ee7b9f93 12206 }
47f1c6c9 12207
ff9a6750
DV		 12208 /* Set default port clock if not overwritten by the encoder. Needs to be
12209 * done afterwards in case the encoder adjusts the mode. */
12210 if (!pipe_config->port_clock)
2d112de7 12211 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12212 * pipe_config->pixel_multiplier;
ff9a6750 12213
a43f6e0f 12214 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12215 if (ret < 0) {
7758a113
DV		 12216 DRM_DEBUG_KMS("CRTC fixup failed\n");
12217 goto fail;
ee7b9f93 12218 }
e29c22c0
DV		 12219
12220 if (ret == RETRY) {
12221 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12222 ret = -EINVAL;
12223 goto fail;
12224 }
12225
12226 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12227 retry = false;
12228 goto encoder_retry;
12229 }
12230
d328c9d7 12231 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12232 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12233 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12234
cdba954e
ACO		 12235 /* Check if we need to force a modeset */
12236 if (pipe_config->has_audio !=
85a96e7a 12237 to_intel_crtc_state(crtc->state)->has_audio) {
cdba954e 12238 pipe_config->base.mode_changed = true;
85a96e7a
ML		 12239 ret = drm_atomic_add_affected_planes(state, crtc);
12240 }
cdba954e
ACO		 12241
12242 /*
12243 * Note we have an issue here with infoframes: current code
12244 * only updates them on the full mode set path per hw
12245 * requirements. So here we should be checking for any
12246 * required changes and forcing a mode set.
12247 */
7758a113 12248fail:
548ee15b 12249 return ret;
ee7b9f93 12250}
47f1c6c9 12251
ea9d758d 12252static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12253{
ea9d758d 12254 struct drm_encoder *encoder;
f6e5b160 12255 struct drm_device *dev = crtc->dev;
f6e5b160 12256
ea9d758d
DV		 12257 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12258 if (encoder->crtc == crtc)
12259 return true;
12260
12261 return false;
12262}
12263
12264static void
0a9ab303 12265intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12266{
0a9ab303 12267 struct drm_device *dev = state->dev;
ea9d758d 12268 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12269 struct drm_crtc *crtc;
12270 struct drm_crtc_state *crtc_state;
ea9d758d
DV		 12271 struct drm_connector *connector;
12272
de419ab6 12273 intel_shared_dpll_commit(state);
ba41c0de 12274
b2784e15 12275 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12276 if (!intel_encoder->base.crtc)
12277 continue;
12278
69024de8
ML		 12279 crtc = intel_encoder->base.crtc;
12280 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12281 if (!crtc_state || !needs_modeset(crtc->state))
12282 continue;
ea9d758d 12283
69024de8 12284 intel_encoder->connectors_active = false;
ea9d758d
DV		 12285 }
12286
3cb480bc 12287 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
f7217905 12288 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12289
7668851f 12290 /* Double check state. */
0a9ab303
ACO		 12291 for_each_crtc(dev, crtc) {
12292 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12293
12294 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12295
12296 /* Update hwmode for vblank functions */
12297 if (crtc->state->active)
12298 crtc->hwmode = crtc->state->adjusted_mode;
12299 else
12300 crtc->hwmode.crtc_clock = 0;
ea9d758d
DV		 12301 }
12302
12303 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12304 if (!connector->encoder || !connector->encoder->crtc)
12305 continue;
12306
69024de8
ML		 12307 crtc = connector->encoder->crtc;
12308 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12309 if (!crtc_state || !needs_modeset(crtc->state))
12310 continue;
ea9d758d 12311
53d9f4e9 12312 if (crtc->state->active) {
69024de8
ML		 12313 struct drm_property *dpms_property =
12314 dev->mode_config.dpms_property;
68d34720 12315
69024de8
ML		 12316 connector->dpms = DRM_MODE_DPMS_ON;
12317 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12318
69024de8
ML		 12319 intel_encoder = to_intel_encoder(connector->encoder);
12320 intel_encoder->connectors_active = true;
12321 } else
12322 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12323 }
ea9d758d
DV		 12324}
12325
3bd26263 12326static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12327{
3bd26263 12328 int diff;
f1f644dc
JB		 12329
12330 if (clock1 == clock2)
12331 return true;
12332
12333 if (!clock1 || !clock2)
12334 return false;
12335
12336 diff = abs(clock1 - clock2);
12337
12338 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12339 return true;
12340
12341 return false;
12342}
12343
25c5b266
DV		 12344#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12345 list_for_each_entry((intel_crtc), \
12346 &(dev)->mode_config.crtc_list, \
12347 base.head) \
0973f18f 12348 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12349
0e8ffe1b 12350static bool
2fa2fe9a 12351intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 12352 struct intel_crtc_state *current_config,
12353 struct intel_crtc_state *pipe_config)
0e8ffe1b 12354{
66e985c0
DV		 12355#define PIPE_CONF_CHECK_X(name) \
12356 if (current_config->name != pipe_config->name) { \
12357 DRM_ERROR("mismatch in " #name " " \
12358 "(expected 0x%08x, found 0x%08x)\n", \
12359 current_config->name, \
12360 pipe_config->name); \
12361 return false; \
12362 }
12363
08a24034
DV		 12364#define PIPE_CONF_CHECK_I(name) \
12365 if (current_config->name != pipe_config->name) { \
12366 DRM_ERROR("mismatch in " #name " " \
12367 "(expected %i, found %i)\n", \
12368 current_config->name, \
12369 pipe_config->name); \
12370 return false; \
88adfff1
DV		 12371 }
12372
b95af8be
VK		 12373/* This is required for BDW+ where there is only one set of registers for
12374 * switching between high and low RR.
12375 * This macro can be used whenever a comparison has to be made between one
12376 * hw state and multiple sw state variables.
12377 */
12378#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12379 if ((current_config->name != pipe_config->name) && \
12380 (current_config->alt_name != pipe_config->name)) { \
12381 DRM_ERROR("mismatch in " #name " " \
12382 "(expected %i or %i, found %i)\n", \
12383 current_config->name, \
12384 current_config->alt_name, \
12385 pipe_config->name); \
12386 return false; \
12387 }
12388
1bd1bd80
DV		 12389#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12390 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 12391 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12392 "(expected %i, found %i)\n", \
12393 current_config->name & (mask), \
12394 pipe_config->name & (mask)); \
12395 return false; \
12396 }
12397
5e550656
VS		 12398#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12399 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12400 DRM_ERROR("mismatch in " #name " " \
12401 "(expected %i, found %i)\n", \
12402 current_config->name, \
12403 pipe_config->name); \
12404 return false; \
12405 }
12406
bb760063
DV		 12407#define PIPE_CONF_QUIRK(quirk) \
12408 ((current_config->quirks | pipe_config->quirks) & (quirk))
12409
eccb140b
DV		 12410 PIPE_CONF_CHECK_I(cpu_transcoder);
12411
08a24034
DV		 12412 PIPE_CONF_CHECK_I(has_pch_encoder);
12413 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12414 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12415 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12416 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12417 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12418 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12419
eb14cb74 12420 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12421
12422 if (INTEL_INFO(dev)->gen < 8) {
12423 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12424 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12425 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12426 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12427 PIPE_CONF_CHECK_I(dp_m_n.tu);
12428
12429 if (current_config->has_drrs) {
12430 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12431 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12432 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12433 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12434 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12435 }
12436 } else {
12437 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12438 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12439 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12440 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12441 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12442 }
eb14cb74 12443
2d112de7
ACO		 12444 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12445 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12446 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12447 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12448 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12449 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12450
2d112de7
ACO		 12451 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12452 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12453 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12454 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12455 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12456 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12457
c93f54cf 12458 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12459 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12460 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12461 IS_VALLEYVIEW(dev))
12462 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12463 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12464
9ed109a7
DV		 12465 PIPE_CONF_CHECK_I(has_audio);
12466
2d112de7 12467 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12468 DRM_MODE_FLAG_INTERLACE);
12469
bb760063 12470 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12471 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12472 DRM_MODE_FLAG_PHSYNC);
2d112de7 12473 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12474 DRM_MODE_FLAG_NHSYNC);
2d112de7 12475 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12476 DRM_MODE_FLAG_PVSYNC);
2d112de7 12477 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12478 DRM_MODE_FLAG_NVSYNC);
12479 }
045ac3b5 12480
37327abd
VS		 12481 PIPE_CONF_CHECK_I(pipe_src_w);
12482 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12483
9953599b
DV		 12484 /*
12485 * FIXME: BIOS likes to set up a cloned config with lvds+external
12486 * screen. Since we don't yet re-compute the pipe config when moving
12487 * just the lvds port away to another pipe the sw tracking won't match.
12488 *
12489 * Proper atomic modesets with recomputed global state will fix this.
12490 * Until then just don't check gmch state for inherited modes.
12491 */
12492 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12493 PIPE_CONF_CHECK_I(gmch_pfit.control);
12494 /* pfit ratios are autocomputed by the hw on gen4+ */
12495 if (INTEL_INFO(dev)->gen < 4)
12496 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12497 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12498 }
12499
fd4daa9c
CW		 12500 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12501 if (current_config->pch_pfit.enabled) {
12502 PIPE_CONF_CHECK_I(pch_pfit.pos);
12503 PIPE_CONF_CHECK_I(pch_pfit.size);
12504 }
2fa2fe9a 12505
a1b2278e
CK		 12506 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12507
e59150dc
JB		 12508 /* BDW+ don't expose a synchronous way to read the state */
12509 if (IS_HASWELL(dev))
12510 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12511
282740f7
VS		 12512 PIPE_CONF_CHECK_I(double_wide);
12513
26804afd
DV		 12514 PIPE_CONF_CHECK_X(ddi_pll_sel);
12515
c0d43d62 12516 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12517 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12518 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12519 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12520 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12521 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12522 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12523 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12524 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12525
42571aef
VS		 12526 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12527 PIPE_CONF_CHECK_I(pipe_bpp);
12528
2d112de7 12529 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12530 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12531
66e985c0 12532#undef PIPE_CONF_CHECK_X
08a24034 12533#undef PIPE_CONF_CHECK_I
b95af8be 12534#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12535#undef PIPE_CONF_CHECK_FLAGS
5e550656 12536#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12537#undef PIPE_CONF_QUIRK
88adfff1 12538
0e8ffe1b
DV		 12539 return true;
12540}
12541
08db6652
DL		 12542static void check_wm_state(struct drm_device *dev)
12543{
12544 struct drm_i915_private *dev_priv = dev->dev_private;
12545 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12546 struct intel_crtc *intel_crtc;
12547 int plane;
12548
12549 if (INTEL_INFO(dev)->gen < 9)
12550 return;
12551
12552 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12553 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12554
12555 for_each_intel_crtc(dev, intel_crtc) {
12556 struct skl_ddb_entry *hw_entry, *sw_entry;
12557 const enum pipe pipe = intel_crtc->pipe;
12558
12559 if (!intel_crtc->active)
12560 continue;
12561
12562 /* planes */
dd740780 12563 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12564 hw_entry = &hw_ddb.plane[pipe][plane];
12565 sw_entry = &sw_ddb->plane[pipe][plane];
12566
12567 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12568 continue;
12569
12570 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12571 "(expected (%u,%u), found (%u,%u))\n",
12572 pipe_name(pipe), plane + 1,
12573 sw_entry->start, sw_entry->end,
12574 hw_entry->start, hw_entry->end);
12575 }
12576
12577 /* cursor */
12578 hw_entry = &hw_ddb.cursor[pipe];
12579 sw_entry = &sw_ddb->cursor[pipe];
12580
12581 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12582 continue;
12583
12584 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12585 "(expected (%u,%u), found (%u,%u))\n",
12586 pipe_name(pipe),
12587 sw_entry->start, sw_entry->end,
12588 hw_entry->start, hw_entry->end);
12589 }
12590}
12591
91d1b4bd
DV		 12592static void
12593check_connector_state(struct drm_device *dev)
8af6cf88 12594{
8af6cf88
DV		 12595 struct intel_connector *connector;
12596
3a3371ff 12597 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12598 /* This also checks the encoder/connector hw state with the
12599 * ->get_hw_state callbacks. */
12600 intel_connector_check_state(connector);
12601
e2c719b7 12602 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12603 "connector's staged encoder doesn't match current encoder\n");
12604 }
91d1b4bd
DV		 12605}
12606
12607static void
12608check_encoder_state(struct drm_device *dev)
12609{
12610 struct intel_encoder *encoder;
12611 struct intel_connector *connector;
8af6cf88 12612
b2784e15 12613 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12614 bool enabled = false;
12615 bool active = false;
12616 enum pipe pipe, tracked_pipe;
12617
12618 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12619 encoder->base.base.id,
8e329a03 12620 encoder->base.name);
8af6cf88 12621
e2c719b7 12622 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12623 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12624 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12625 "encoder's active_connectors set, but no crtc\n");
12626
3a3371ff 12627 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12628 if (connector->base.encoder != &encoder->base)
12629 continue;
12630 enabled = true;
12631 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12632 active = true;
12633 }
0e32b39c
DA		 12634 /*
12635 * for MST connectors if we unplug the connector is gone
12636 * away but the encoder is still connected to a crtc
12637 * until a modeset happens in response to the hotplug.
12638 */
12639 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12640 continue;
12641
e2c719b7 12642 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12643 "encoder's enabled state mismatch "
12644 "(expected %i, found %i)\n",
12645 !!encoder->base.crtc, enabled);
e2c719b7 12646 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12647 "active encoder with no crtc\n");
12648
e2c719b7 12649 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12650 "encoder's computed active state doesn't match tracked active state "
12651 "(expected %i, found %i)\n", active, encoder->connectors_active);
12652
12653 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12654 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12655 "encoder's hw state doesn't match sw tracking "
12656 "(expected %i, found %i)\n",
12657 encoder->connectors_active, active);
12658
12659 if (!encoder->base.crtc)
12660 continue;
12661
12662 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12663 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12664 "active encoder's pipe doesn't match"
12665 "(expected %i, found %i)\n",
12666 tracked_pipe, pipe);
12667
12668 }
91d1b4bd
DV		 12669}
12670
12671static void
12672check_crtc_state(struct drm_device *dev)
12673{
fbee40df 12674 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12675 struct intel_crtc *crtc;
12676 struct intel_encoder *encoder;
5cec258b 12677 struct intel_crtc_state pipe_config;
8af6cf88 12678
d3fcc808 12679 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12680 bool enabled = false;
12681 bool active = false;
12682
045ac3b5
JB		 12683 memset(&pipe_config, 0, sizeof(pipe_config));
12684
8af6cf88
DV		 12685 DRM_DEBUG_KMS("[CRTC:%d]\n",
12686 crtc->base.base.id);
12687
83d65738 12688 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12689 "active crtc, but not enabled in sw tracking\n");
12690
b2784e15 12691 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12692 if (encoder->base.crtc != &crtc->base)
12693 continue;
12694 enabled = true;
12695 if (encoder->connectors_active)
12696 active = true;
12697 }
6c49f241 12698
e2c719b7 12699 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12700 "crtc's computed active state doesn't match tracked active state "
12701 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12702 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12703 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12704 "(expected %i, found %i)\n", enabled,
12705 crtc->base.state->enable);
8af6cf88 12706
0e8ffe1b
DV		 12707 active = dev_priv->display.get_pipe_config(crtc,
12708 &pipe_config);
d62cf62a 12709
b6b5d049
VS		 12710 /* hw state is inconsistent with the pipe quirk */
12711 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12712 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12713 active = crtc->active;
12714
b2784e15 12715 for_each_intel_encoder(dev, encoder) {
3eaba51c 12716 enum pipe pipe;
6c49f241
DV		 12717 if (encoder->base.crtc != &crtc->base)
12718 continue;
1d37b689 12719 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12720 encoder->get_config(encoder, &pipe_config);
12721 }
12722
e2c719b7 12723 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12724 "crtc active state doesn't match with hw state "
12725 "(expected %i, found %i)\n", crtc->active, active);
12726
53d9f4e9
ML		 12727 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12728 "transitional active state does not match atomic hw state "
12729 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12730
c0b03411 12731 if (active &&
6e3c9717 12732 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12733 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12734 intel_dump_pipe_config(crtc, &pipe_config,
12735 "[hw state]");
6e3c9717 12736 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12737 "[sw state]");
12738 }
8af6cf88
DV		 12739 }
12740}
12741
91d1b4bd
DV		 12742static void
12743check_shared_dpll_state(struct drm_device *dev)
12744{
fbee40df 12745 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12746 struct intel_crtc *crtc;
12747 struct intel_dpll_hw_state dpll_hw_state;
12748 int i;
5358901f
DV		 12749
12750 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12751 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12752 int enabled_crtcs = 0, active_crtcs = 0;
12753 bool active;
12754
12755 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12756
12757 DRM_DEBUG_KMS("%s\n", pll->name);
12758
12759 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12760
e2c719b7 12761 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12762 "more active pll users than references: %i vs %i\n",
3e369b76 12763 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12764 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12765 "pll in active use but not on in sw tracking\n");
e2c719b7 12766 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12767 "pll in on but not on in use in sw tracking\n");
e2c719b7 12768 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12769 "pll on state mismatch (expected %i, found %i)\n",
12770 pll->on, active);
12771
d3fcc808 12772 for_each_intel_crtc(dev, crtc) {
83d65738 12773 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12774 enabled_crtcs++;
12775 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12776 active_crtcs++;
12777 }
e2c719b7 12778 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12779 "pll active crtcs mismatch (expected %i, found %i)\n",
12780 pll->active, active_crtcs);
e2c719b7 12781 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12782 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12783 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12784
e2c719b7 12785 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12786 sizeof(dpll_hw_state)),
12787 "pll hw state mismatch\n");
5358901f 12788 }
8af6cf88
DV		 12789}
12790
91d1b4bd
DV		 12791void
12792intel_modeset_check_state(struct drm_device *dev)
12793{
08db6652 12794 check_wm_state(dev);
91d1b4bd
DV		 12795 check_connector_state(dev);
12796 check_encoder_state(dev);
12797 check_crtc_state(dev);
12798 check_shared_dpll_state(dev);
12799}
12800
5cec258b 12801void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12802 int dotclock)
12803{
12804 /*
12805 * FDI already provided one idea for the dotclock.
12806 * Yell if the encoder disagrees.
12807 */
2d112de7 12808 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12809 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12810 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12811}
12812
80715b2f
VS		 12813static void update_scanline_offset(struct intel_crtc *crtc)
12814{
12815 struct drm_device *dev = crtc->base.dev;
12816
12817 /*
12818 * The scanline counter increments at the leading edge of hsync.
12819 *
12820 * On most platforms it starts counting from vtotal-1 on the
12821 * first active line. That means the scanline counter value is
12822 * always one less than what we would expect. Ie. just after
12823 * start of vblank, which also occurs at start of hsync (on the
12824 * last active line), the scanline counter will read vblank_start-1.
12825 *
12826 * On gen2 the scanline counter starts counting from 1 instead
12827 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12828 * to keep the value positive), instead of adding one.
12829 *
12830 * On HSW+ the behaviour of the scanline counter depends on the output
12831 * type. For DP ports it behaves like most other platforms, but on HDMI
12832 * there's an extra 1 line difference. So we need to add two instead of
12833 * one to the value.
12834 */
12835 if (IS_GEN2(dev)) {
6e3c9717 12836 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12837 int vtotal;
12838
12839 vtotal = mode->crtc_vtotal;
12840 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12841 vtotal /= 2;
12842
12843 crtc->scanline_offset = vtotal - 1;
12844 } else if (HAS_DDI(dev) &&
409ee761 12845 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12846 crtc->scanline_offset = 2;
12847 } else
12848 crtc->scanline_offset = 1;
12849}
12850
ad421372 12851static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12852{
225da59b 12853 struct drm_device *dev = state->dev;
ed6739ef 12854 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12855 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12856 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12857 struct intel_crtc_state *intel_crtc_state;
12858 struct drm_crtc *crtc;
12859 struct drm_crtc_state *crtc_state;
0a9ab303 12860 int i;
ed6739ef
ACO		 12861
12862 if (!dev_priv->display.crtc_compute_clock)
ad421372 12863 return;
ed6739ef 12864
0a9ab303 12865 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12866 int dpll;
12867
0a9ab303 12868 intel_crtc = to_intel_crtc(crtc);
4978cc93 12869 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12870 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12871
ad421372 12872 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12873 continue;
12874
ad421372 12875 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12876
ad421372
ML		 12877 if (!shared_dpll)
12878 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12879
ad421372
ML		 12880 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12881 }
ed6739ef
ACO		 12882}
12883
99d736a2
ML		 12884/*
12885 * This implements the workaround described in the "notes" section of the mode
12886 * set sequence documentation. When going from no pipes or single pipe to
12887 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12888 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12889 */
12890static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12891{
12892 struct drm_crtc_state *crtc_state;
12893 struct intel_crtc *intel_crtc;
12894 struct drm_crtc *crtc;
12895 struct intel_crtc_state *first_crtc_state = NULL;
12896 struct intel_crtc_state *other_crtc_state = NULL;
12897 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12898 int i;
12899
12900 /* look at all crtc's that are going to be enabled in during modeset */
12901 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12902 intel_crtc = to_intel_crtc(crtc);
12903
12904 if (!crtc_state->active || !needs_modeset(crtc_state))
12905 continue;
12906
12907 if (first_crtc_state) {
12908 other_crtc_state = to_intel_crtc_state(crtc_state);
12909 break;
12910 } else {
12911 first_crtc_state = to_intel_crtc_state(crtc_state);
12912 first_pipe = intel_crtc->pipe;
12913 }
12914 }
12915
12916 /* No workaround needed? */
12917 if (!first_crtc_state)
12918 return 0;
12919
12920 /* w/a possibly needed, check how many crtc's are already enabled. */
12921 for_each_intel_crtc(state->dev, intel_crtc) {
12922 struct intel_crtc_state *pipe_config;
12923
12924 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12925 if (IS_ERR(pipe_config))
12926 return PTR_ERR(pipe_config);
12927
12928 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12929
12930 if (!pipe_config->base.active ||
12931 needs_modeset(&pipe_config->base))
12932 continue;
12933
12934 /* 2 or more enabled crtcs means no need for w/a */
12935 if (enabled_pipe != INVALID_PIPE)
12936 return 0;
12937
12938 enabled_pipe = intel_crtc->pipe;
12939 }
12940
12941 if (enabled_pipe != INVALID_PIPE)
12942 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12943 else if (other_crtc_state)
12944 other_crtc_state->hsw_workaround_pipe = first_pipe;
12945
12946 return 0;
12947}
12948
27c329ed
ML		 12949static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12950{
12951 struct drm_crtc *crtc;
12952 struct drm_crtc_state *crtc_state;
12953 int ret = 0;
12954
12955 /* add all active pipes to the state */
12956 for_each_crtc(state->dev, crtc) {
12957 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12958 if (IS_ERR(crtc_state))
12959 return PTR_ERR(crtc_state);
12960
12961 if (!crtc_state->active || needs_modeset(crtc_state))
12962 continue;
12963
12964 crtc_state->mode_changed = true;
12965
12966 ret = drm_atomic_add_affected_connectors(state, crtc);
12967 if (ret)
12968 break;
12969
12970 ret = drm_atomic_add_affected_planes(state, crtc);
12971 if (ret)
12972 break;
12973 }
12974
12975 return ret;
12976}
12977
12978
054518dd 12979/* Code that should eventually be part of atomic_check() */
c347a676 12980static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 12981{
12982 struct drm_device *dev = state->dev;
27c329ed 12983 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 12984 int ret;
12985
b359283a
ML		 12986 if (!check_digital_port_conflicts(state)) {
12987 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12988 return -EINVAL;
12989 }
12990
054518dd
ACO		 12991 /*
12992 * See if the config requires any additional preparation, e.g.
12993 * to adjust global state with pipes off. We need to do this
12994 * here so we can get the modeset_pipe updated config for the new
12995 * mode set on this crtc. For other crtcs we need to use the
12996 * adjusted_mode bits in the crtc directly.
12997 */
27c329ed
ML		 12998 if (dev_priv->display.modeset_calc_cdclk) {
12999 unsigned int cdclk;
b432e5cf 13000
27c329ed
ML		 13001 ret = dev_priv->display.modeset_calc_cdclk(state);
13002
13003 cdclk = to_intel_atomic_state(state)->cdclk;
13004 if (!ret && cdclk != dev_priv->cdclk_freq)
13005 ret = intel_modeset_all_pipes(state);
13006
13007 if (ret < 0)
054518dd 13008 return ret;
27c329ed
ML		 13009 } else
13010 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13011
ad421372 13012 intel_modeset_clear_plls(state);
054518dd 13013
99d736a2 13014 if (IS_HASWELL(dev))
ad421372 13015 return haswell_mode_set_planes_workaround(state);
99d736a2 13016
ad421372 13017 return 0;
c347a676
ACO		 13018}
13019
13020static int
13021intel_modeset_compute_config(struct drm_atomic_state *state)
13022{
13023 struct drm_crtc *crtc;
13024 struct drm_crtc_state *crtc_state;
13025 int ret, i;
61333b60 13026 bool any_ms = false;
c347a676
ACO		 13027
13028 ret = drm_atomic_helper_check_modeset(state->dev, state);
054518dd
ACO		 13029 if (ret)
13030 return ret;
13031
c347a676 13032 for_each_crtc_in_state(state, crtc, crtc_state, i) {
61333b60
ML		 13033 if (!crtc_state->enable) {
13034 if (needs_modeset(crtc_state))
13035 any_ms = true;
c347a676 13036 continue;
61333b60 13037 }
c347a676 13038
d032ffa0
ML		 13039 if (to_intel_crtc_state(crtc_state)->quirks &
13040 PIPE_CONFIG_QUIRK_INITIAL_PLANES) {
13041 ret = drm_atomic_add_affected_planes(state, crtc);
13042 if (ret)
13043 return ret;
13044
13045 /*
13046 * We ought to handle i915.fastboot here.
13047 * If no modeset is required and the primary plane has
13048 * a fb, update the members of crtc_state as needed,
13049 * and run the necessary updates during vblank evasion.
13050 */
13051 }
13052
b359283a
ML		 13053 if (!needs_modeset(crtc_state)) {
13054 ret = drm_atomic_add_affected_connectors(state, crtc);
13055 if (ret)
13056 return ret;
13057 }
13058
13059 ret = intel_modeset_pipe_config(crtc,
13060 to_intel_crtc_state(crtc_state));
c347a676
ACO		 13061 if (ret)
13062 return ret;
13063
61333b60
ML		 13064 if (needs_modeset(crtc_state))
13065 any_ms = true;
13066
c347a676
ACO		 13067 intel_dump_pipe_config(to_intel_crtc(crtc),
13068 to_intel_crtc_state(crtc_state),
13069 "[modeset]");
13070 }
13071
61333b60
ML		 13072 if (any_ms) {
13073 ret = intel_modeset_checks(state);
13074
13075 if (ret)
13076 return ret;
27c329ed
ML		 13077 } else
13078 to_intel_atomic_state(state)->cdclk =
13079 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13080
13081 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13082}
13083
c72d969b 13084static int __intel_set_mode(struct drm_atomic_state *state)
a6778b3c 13085{
c72d969b 13086 struct drm_device *dev = state->dev;
fbee40df 13087 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13088 struct drm_crtc *crtc;
13089 struct drm_crtc_state *crtc_state;
c0c36b94 13090 int ret = 0;
0a9ab303 13091 int i;
61333b60 13092 bool any_ms = false;
a6778b3c 13093
d4afb8cc
ACO		 13094 ret = drm_atomic_helper_prepare_planes(dev, state);
13095 if (ret)
13096 return ret;
13097
1c5e19f8
ML		 13098 drm_atomic_helper_swap_state(dev, state);
13099
0a9ab303 13100 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13102
61333b60
ML		 13103 if (!needs_modeset(crtc->state))
13104 continue;
13105
13106 any_ms = true;
a539205a 13107 intel_pre_plane_update(intel_crtc);
460da916 13108
a539205a
ML		 13109 if (crtc_state->active) {
13110 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13111 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13112 intel_crtc->active = false;
13113 intel_disable_shared_dpll(intel_crtc);
a539205a 13114 }
b8cecdf5 13115 }
7758a113 13116
ea9d758d
DV		 13117 /* Only after disabling all output pipelines that will be changed can we
13118 * update the the output configuration. */
0a9ab303 13119 intel_modeset_update_state(state);
f6e5b160 13120
a821fc46
ACO		 13121 /* The state has been swaped above, so state actually contains the
13122 * old state now. */
61333b60
ML		 13123 if (any_ms)
13124 modeset_update_crtc_power_domains(state);
47fab737 13125
a6778b3c 13126 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13127 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13128 if (needs_modeset(crtc->state) && crtc->state->active) {
13129 update_scanline_offset(to_intel_crtc(crtc));
13130 dev_priv->display.crtc_enable(crtc);
13131 }
80715b2f 13132
a539205a 13133 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
80715b2f 13134 }
a6778b3c 13135
a6778b3c 13136 /* FIXME: add subpixel order */
83a57153 13137
d4afb8cc
ACO		 13138 drm_atomic_helper_cleanup_planes(dev, state);
13139
2bfb4627
ACO		 13140 drm_atomic_state_free(state);
13141
9eb45f22 13142 return 0;
f6e5b160
CW		 13143}
13144
568c634a 13145static int intel_set_mode_checked(struct drm_atomic_state *state)
f30da187 13146{
568c634a 13147 struct drm_device *dev = state->dev;
f30da187
DV		 13148 int ret;
13149
568c634a 13150 ret = __intel_set_mode(state);
f30da187 13151 if (ret == 0)
568c634a 13152 intel_modeset_check_state(dev);
f30da187
DV		 13153
13154 return ret;
13155}
13156
568c634a 13157static int intel_set_mode(struct drm_atomic_state *state)
7f27126e 13158{
568c634a 13159 int ret;
83a57153 13160
568c634a 13161 ret = intel_modeset_compute_config(state);
83a57153 13162 if (ret)
568c634a 13163 return ret;
7f27126e 13164
568c634a 13165 return intel_set_mode_checked(state);
7f27126e
JB		 13166}
13167
c0c36b94
CW		 13168void intel_crtc_restore_mode(struct drm_crtc *crtc)
13169{
83a57153
ACO		 13170 struct drm_device *dev = crtc->dev;
13171 struct drm_atomic_state *state;
13172 struct intel_encoder *encoder;
13173 struct intel_connector *connector;
13174 struct drm_connector_state *connector_state;
4be07317 13175 struct intel_crtc_state *crtc_state;
2bfb4627 13176 int ret;
83a57153
ACO		 13177
13178 state = drm_atomic_state_alloc(dev);
13179 if (!state) {
13180 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13181 crtc->base.id);
13182 return;
13183 }
13184
13185 state->acquire_ctx = dev->mode_config.acquire_ctx;
13186
13187 /* The force restore path in the HW readout code relies on the staged
13188 * config still keeping the user requested config while the actual
13189 * state has been overwritten by the configuration read from HW. We
13190 * need to copy the staged config to the atomic state, otherwise the
13191 * mode set will just reapply the state the HW is already in. */
13192 for_each_intel_encoder(dev, encoder) {
13193 if (&encoder->new_crtc->base != crtc)
13194 continue;
13195
13196 for_each_intel_connector(dev, connector) {
13197 if (connector->new_encoder != encoder)
13198 continue;
13199
13200 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13201 if (IS_ERR(connector_state)) {
13202 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13203 connector->base.base.id,
13204 connector->base.name,
13205 PTR_ERR(connector_state));
13206 continue;
13207 }
13208
13209 connector_state->crtc = crtc;
13210 connector_state->best_encoder = &encoder->base;
13211 }
13212 }
13213
4ed9fb37
ACO		 13214 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13215 if (IS_ERR(crtc_state)) {
13216 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13217 crtc->base.id, PTR_ERR(crtc_state));
13218 drm_atomic_state_free(state);
13219 return;
13220 }
4be07317 13221
4ed9fb37
ACO		 13222 crtc_state->base.active = crtc_state->base.enable =
13223 to_intel_crtc(crtc)->new_enabled;
8c7b5ccb 13224
4ed9fb37 13225 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317 13226
d3a40d1b
ACO		 13227 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13228 crtc->primary->fb, crtc->x, crtc->y);
13229
568c634a 13230 ret = intel_set_mode(state);
2bfb4627
ACO		 13231 if (ret)
13232 drm_atomic_state_free(state);
c0c36b94
CW		 13233}
13234
25c5b266
DV		 13235#undef for_each_intel_crtc_masked
13236
b7885264
ACO		 13237static bool intel_connector_in_mode_set(struct intel_connector *connector,
13238 struct drm_mode_set *set)
13239{
13240 int ro;
13241
13242 for (ro = 0; ro < set->num_connectors; ro++)
13243 if (set->connectors[ro] == &connector->base)
13244 return true;
13245
13246 return false;
13247}
13248
2e431051 13249static int
9a935856
DV		 13250intel_modeset_stage_output_state(struct drm_device *dev,
13251 struct drm_mode_set *set,
944b0c76 13252 struct drm_atomic_state *state)
50f56119 13253{
9a935856 13254 struct intel_connector *connector;
d5432a9d 13255 struct drm_connector *drm_connector;
944b0c76 13256 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13257 struct drm_crtc *crtc;
13258 struct drm_crtc_state *crtc_state;
13259 int i, ret;
50f56119 13260
9abdda74 13261 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13262 * of connectors. For paranoia, double-check this. */
13263 WARN_ON(!set->fb && (set->num_connectors != 0));
13264 WARN_ON(set->fb && (set->num_connectors == 0));
13265
3a3371ff 13266 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13267 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13268
d5432a9d
ACO		 13269 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13270 continue;
13271
13272 connector_state =
13273 drm_atomic_get_connector_state(state, &connector->base);
13274 if (IS_ERR(connector_state))
13275 return PTR_ERR(connector_state);
13276
b7885264
ACO		 13277 if (in_mode_set) {
13278 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13279 connector_state->best_encoder =
13280 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13281 }
13282
d5432a9d 13283 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13284 continue;
13285
9a935856
DV		 13286 /* If we disable the crtc, disable all its connectors. Also, if
13287 * the connector is on the changing crtc but not on the new
13288 * connector list, disable it. */
b7885264 13289 if (!set->fb || !in_mode_set) {
d5432a9d 13290 connector_state->best_encoder = NULL;
9a935856
DV		 13291
13292 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13293 connector->base.base.id,
c23cc417 13294 connector->base.name);
9a935856 13295 }
50f56119 13296 }
9a935856 13297 /* connector->new_encoder is now updated for all connectors. */
50f56119 13298
d5432a9d
ACO		 13299 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13300 connector = to_intel_connector(drm_connector);
13301
13302 if (!connector_state->best_encoder) {
13303 ret = drm_atomic_set_crtc_for_connector(connector_state,
13304 NULL);
13305 if (ret)
13306 return ret;
7668851f 13307
50f56119 13308 continue;
d5432a9d 13309 }
50f56119 13310
d5432a9d
ACO		 13311 if (intel_connector_in_mode_set(connector, set)) {
13312 struct drm_crtc *crtc = connector->base.state->crtc;
13313
13314 /* If this connector was in a previous crtc, add it
13315 * to the state. We might need to disable it. */
13316 if (crtc) {
13317 crtc_state =
13318 drm_atomic_get_crtc_state(state, crtc);
13319 if (IS_ERR(crtc_state))
13320 return PTR_ERR(crtc_state);
13321 }
13322
13323 ret = drm_atomic_set_crtc_for_connector(connector_state,
13324 set->crtc);
13325 if (ret)
13326 return ret;
13327 }
50f56119
DV		 13328
13329 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13330 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13331 connector_state->crtc)) {
5e2b584e 13332 return -EINVAL;
50f56119 13333 }
944b0c76 13334
9a935856
DV		 13335 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13336 connector->base.base.id,
c23cc417 13337 connector->base.name,
d5432a9d 13338 connector_state->crtc->base.id);
944b0c76 13339
d5432a9d
ACO		 13340 if (connector_state->best_encoder != &connector->encoder->base)
13341 connector->encoder =
13342 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13343 }
7668851f 13344
d5432a9d 13345 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13346 bool has_connectors;
13347
d5432a9d
ACO		 13348 ret = drm_atomic_add_affected_connectors(state, crtc);
13349 if (ret)
13350 return ret;
4be07317 13351
49d6fa21
ML		 13352 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13353 if (has_connectors != crtc_state->enable)
13354 crtc_state->enable =
13355 crtc_state->active = has_connectors;
7668851f
VS		 13356 }
13357
8c7b5ccb
ACO		 13358 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13359 set->fb, set->x, set->y);
13360 if (ret)
13361 return ret;
13362
13363 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13364 if (IS_ERR(crtc_state))
13365 return PTR_ERR(crtc_state);
13366
ce52299c
MR		 13367 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13368 if (ret)
13369 return ret;
8c7b5ccb
ACO		 13370
13371 if (set->num_connectors)
13372 crtc_state->active = true;
13373
2e431051
DV		 13374 return 0;
13375}
13376
13377static int intel_crtc_set_config(struct drm_mode_set *set)
13378{
13379 struct drm_device *dev;
83a57153 13380 struct drm_atomic_state *state = NULL;
2e431051 13381 int ret;
2e431051 13382
8d3e375e
DV		 13383 BUG_ON(!set);
13384 BUG_ON(!set->crtc);
13385 BUG_ON(!set->crtc->helper_private);
2e431051 13386
7e53f3a4
DV		 13387 /* Enforce sane interface api - has been abused by the fb helper. */
13388 BUG_ON(!set->mode && set->fb);
13389 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13390
2e431051
DV		 13391 if (set->fb) {
13392 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13393 set->crtc->base.id, set->fb->base.id,
13394 (int)set->num_connectors, set->x, set->y);
13395 } else {
13396 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13397 }
13398
13399 dev = set->crtc->dev;
13400
83a57153 13401 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13402 if (!state)
13403 return -ENOMEM;
83a57153
ACO		 13404
13405 state->acquire_ctx = dev->mode_config.acquire_ctx;
13406
462a425a 13407 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13408 if (ret)
7cbf41d6 13409 goto out;
2e431051 13410
568c634a
ACO		 13411 ret = intel_modeset_compute_config(state);
13412 if (ret)
7cbf41d6 13413 goto out;
50f52756 13414
1f9954d0
JB		 13415 intel_update_pipe_size(to_intel_crtc(set->crtc));
13416
568c634a 13417 ret = intel_set_mode_checked(state);
2d05eae1 13418 if (ret) {
bf67dfeb
DV		 13419 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13420 set->crtc->base.id, ret);
2d05eae1 13421 }
50f56119 13422
7cbf41d6 13423out:
2bfb4627
ACO		 13424 if (ret)
13425 drm_atomic_state_free(state);
50f56119
DV		 13426 return ret;
13427}
f6e5b160
CW		 13428
13429static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13430 .gamma_set = intel_crtc_gamma_set,
50f56119 13431 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13432 .destroy = intel_crtc_destroy,
13433 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13434 .atomic_duplicate_state = intel_crtc_duplicate_state,
13435 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13436};
13437
5358901f
DV		 13438static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13439 struct intel_shared_dpll *pll,
13440 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13441{
5358901f 13442 uint32_t val;
ee7b9f93 13443
f458ebbc 13444 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13445 return false;
13446
5358901f 13447 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13448 hw_state->dpll = val;
13449 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13450 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13451
13452 return val & DPLL_VCO_ENABLE;
13453}
13454
15bdd4cf
DV		 13455static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13456 struct intel_shared_dpll *pll)
13457{
3e369b76
ACO		 13458 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13459 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13460}
13461
e7b903d2
DV		 13462static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13463 struct intel_shared_dpll *pll)
13464{
e7b903d2 13465 /* PCH refclock must be enabled first */
89eff4be 13466 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13467
3e369b76 13468 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13469
13470 /* Wait for the clocks to stabilize. */
13471 POSTING_READ(PCH_DPLL(pll->id));
13472 udelay(150);
13473
13474 /* The pixel multiplier can only be updated once the
13475 * DPLL is enabled and the clocks are stable.
13476 *
13477 * So write it again.
13478 */
3e369b76 13479 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13480 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13481 udelay(200);
13482}
13483
13484static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13485 struct intel_shared_dpll *pll)
13486{
13487 struct drm_device *dev = dev_priv->dev;
13488 struct intel_crtc *crtc;
e7b903d2
DV		 13489
13490 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13491 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13492 if (intel_crtc_to_shared_dpll(crtc) == pll)
13493 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13494 }
13495
15bdd4cf
DV		 13496 I915_WRITE(PCH_DPLL(pll->id), 0);
13497 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13498 udelay(200);
13499}
13500
46edb027
DV		 13501static char *ibx_pch_dpll_names[] = {
13502 "PCH DPLL A",
13503 "PCH DPLL B",
13504};
13505
7c74ade1 13506static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13507{
e7b903d2 13508 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13509 int i;
13510
7c74ade1 13511 dev_priv->num_shared_dpll = 2;
ee7b9f93 13512
e72f9fbf 13513 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13514 dev_priv->shared_dplls[i].id = i;
13515 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13516 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13517 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13518 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13519 dev_priv->shared_dplls[i].get_hw_state =
13520 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13521 }
13522}
13523
7c74ade1
DV		 13524static void intel_shared_dpll_init(struct drm_device *dev)
13525{
e7b903d2 13526 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13527
b6283055
VS		 13528 intel_update_cdclk(dev);
13529
9cd86933
DV		 13530 if (HAS_DDI(dev))
13531 intel_ddi_pll_init(dev);
13532 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13533 ibx_pch_dpll_init(dev);
13534 else
13535 dev_priv->num_shared_dpll = 0;
13536
13537 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13538}
13539
6beb8c23
MR		 13540/**
13541 * intel_prepare_plane_fb - Prepare fb for usage on plane
13542 * @plane: drm plane to prepare for
13543 * @fb: framebuffer to prepare for presentation
13544 *
13545 * Prepares a framebuffer for usage on a display plane. Generally this
13546 * involves pinning the underlying object and updating the frontbuffer tracking
13547 * bits. Some older platforms need special physical address handling for
13548 * cursor planes.
13549 *
13550 * Returns 0 on success, negative error code on failure.
13551 */
13552int
13553intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13554 struct drm_framebuffer *fb,
13555 const struct drm_plane_state *new_state)
465c120c
MR		 13556{
13557 struct drm_device *dev = plane->dev;
6beb8c23 13558 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13559 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13560 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13561 int ret = 0;
465c120c 13562
ea2c67bb 13563 if (!obj)
465c120c
MR		 13564 return 0;
13565
6beb8c23 13566 mutex_lock(&dev->struct_mutex);
465c120c 13567
6beb8c23
MR		 13568 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13569 INTEL_INFO(dev)->cursor_needs_physical) {
13570 int align = IS_I830(dev) ? 16 * 1024 : 256;
13571 ret = i915_gem_object_attach_phys(obj, align);
13572 if (ret)
13573 DRM_DEBUG_KMS("failed to attach phys object\n");
13574 } else {
91af127f 13575 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13576 }
465c120c 13577
6beb8c23 13578 if (ret == 0)
a9ff8714 13579 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13580
4c34574f 13581 mutex_unlock(&dev->struct_mutex);
465c120c 13582
6beb8c23
MR		 13583 return ret;
13584}
13585
38f3ce3a
MR		 13586/**
13587 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13588 * @plane: drm plane to clean up for
13589 * @fb: old framebuffer that was on plane
13590 *
13591 * Cleans up a framebuffer that has just been removed from a plane.
13592 */
13593void
13594intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13595 struct drm_framebuffer *fb,
13596 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13597{
13598 struct drm_device *dev = plane->dev;
13599 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13600
13601 if (WARN_ON(!obj))
13602 return;
13603
13604 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13605 !INTEL_INFO(dev)->cursor_needs_physical) {
13606 mutex_lock(&dev->struct_mutex);
82bc3b2d 13607 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13608 mutex_unlock(&dev->struct_mutex);
13609 }
465c120c
MR		 13610}
13611
6156a456
CK		 13612int
13613skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13614{
13615 int max_scale;
13616 struct drm_device *dev;
13617 struct drm_i915_private *dev_priv;
13618 int crtc_clock, cdclk;
13619
13620 if (!intel_crtc || !crtc_state)
13621 return DRM_PLANE_HELPER_NO_SCALING;
13622
13623 dev = intel_crtc->base.dev;
13624 dev_priv = dev->dev_private;
13625 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13626 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13627
13628 if (!crtc_clock || !cdclk)
13629 return DRM_PLANE_HELPER_NO_SCALING;
13630
13631 /*
13632 * skl max scale is lower of:
13633 * close to 3 but not 3, -1 is for that purpose
13634 * or
13635 * cdclk/crtc_clock
13636 */
13637 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13638
13639 return max_scale;
13640}
13641
465c120c 13642static int
3c692a41 13643intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13644 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13645 struct intel_plane_state *state)
13646{
2b875c22
MR		 13647 struct drm_crtc *crtc = state->base.crtc;
13648 struct drm_framebuffer *fb = state->base.fb;
6156a456 13649 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13650 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13651 bool can_position = false;
465c120c 13652
061e4b8d
ML		 13653 /* use scaler when colorkey is not required */
13654 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13655 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13656 min_scale = 1;
13657 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13658 can_position = true;
6156a456 13659 }
d8106366 13660
061e4b8d
ML		 13661 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13662 &state->dst, &state->clip,
da20eabd
ML		 13663 min_scale, max_scale,
13664 can_position, true,
13665 &state->visible);
14af293f
GP		 13666}
13667
13668static void
13669intel_commit_primary_plane(struct drm_plane *plane,
13670 struct intel_plane_state *state)
13671{
2b875c22
MR		 13672 struct drm_crtc *crtc = state->base.crtc;
13673 struct drm_framebuffer *fb = state->base.fb;
13674 struct drm_device *dev = plane->dev;
14af293f 13675 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13676 struct intel_crtc *intel_crtc;
14af293f
GP		 13677 struct drm_rect *src = &state->src;
13678
ea2c67bb
MR		 13679 crtc = crtc ? crtc : plane->crtc;
13680 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13681
13682 plane->fb = fb;
9dc806fc
MR		 13683 crtc->x = src->x1 >> 16;
13684 crtc->y = src->y1 >> 16;
ccc759dc 13685
a539205a 13686 if (!crtc->state->active)
302d19ac 13687 return;
465c120c 13688
302d19ac
ML		 13689 if (state->visible)
13690 /* FIXME: kill this fastboot hack */
13691 intel_update_pipe_size(intel_crtc);
13692
13693 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13694}
13695
a8ad0d8e
ML		 13696static void
13697intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13698 struct drm_crtc *crtc)
a8ad0d8e
ML		 13699{
13700 struct drm_device *dev = plane->dev;
13701 struct drm_i915_private *dev_priv = dev->dev_private;
13702
a8ad0d8e
ML		 13703 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13704}
13705
32b7eeec 13706static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13707{
32b7eeec 13708 struct drm_device *dev = crtc->dev;
140fd38d 13709 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13711
a539205a
ML		 13712 if (!needs_modeset(crtc->state))
13713 intel_pre_plane_update(intel_crtc);
3c692a41 13714
f015c551 13715 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13716 intel_update_watermarks(crtc);
3c692a41 13717
32b7eeec 13718 intel_runtime_pm_get(dev_priv);
3c692a41 13719
c34c9ee4 13720 /* Perform vblank evasion around commit operation */
a539205a 13721 if (crtc->state->active)
c34c9ee4
MR		 13722 intel_crtc->atomic.evade =
13723 intel_pipe_update_start(intel_crtc,
13724 &intel_crtc->atomic.start_vbl_count);
0583236e
ML		 13725
13726 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13727 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13728}
13729
13730static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13731{
13732 struct drm_device *dev = crtc->dev;
13733 struct drm_i915_private *dev_priv = dev->dev_private;
13734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13735
c34c9ee4
MR		 13736 if (intel_crtc->atomic.evade)
13737 intel_pipe_update_end(intel_crtc,
13738 intel_crtc->atomic.start_vbl_count);
3c692a41 13739
140fd38d 13740 intel_runtime_pm_put(dev_priv);
3c692a41 13741
ac21b225 13742 intel_post_plane_update(intel_crtc);
3c692a41
GP		 13743}
13744
cf4c7c12 13745/**
4a3b8769
MR		 13746 * intel_plane_destroy - destroy a plane
13747 * @plane: plane to destroy
cf4c7c12 13748 *
4a3b8769
MR		 13749 * Common destruction function for all types of planes (primary, cursor,
13750 * sprite).
cf4c7c12 13751 */
4a3b8769 13752void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13753{
13754 struct intel_plane *intel_plane = to_intel_plane(plane);
13755 drm_plane_cleanup(plane);
13756 kfree(intel_plane);
13757}
13758
65a3fea0 13759const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13760 .update_plane = drm_atomic_helper_update_plane,
13761 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13762 .destroy = intel_plane_destroy,
c196e1d6 13763 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13764 .atomic_get_property = intel_plane_atomic_get_property,
13765 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13766 .atomic_duplicate_state = intel_plane_duplicate_state,
13767 .atomic_destroy_state = intel_plane_destroy_state,
13768
465c120c
MR		 13769};
13770
13771static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13772 int pipe)
13773{
13774 struct intel_plane *primary;
8e7d688b 13775 struct intel_plane_state *state;
465c120c
MR		 13776 const uint32_t *intel_primary_formats;
13777 int num_formats;
13778
13779 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13780 if (primary == NULL)
13781 return NULL;
13782
8e7d688b
MR		 13783 state = intel_create_plane_state(&primary->base);
13784 if (!state) {
ea2c67bb
MR		 13785 kfree(primary);
13786 return NULL;
13787 }
8e7d688b 13788 primary->base.state = &state->base;
ea2c67bb 13789
465c120c
MR		 13790 primary->can_scale = false;
13791 primary->max_downscale = 1;
6156a456
CK		 13792 if (INTEL_INFO(dev)->gen >= 9) {
13793 primary->can_scale = true;
af99ceda 13794 state->scaler_id = -1;
6156a456 13795 }
465c120c
MR		 13796 primary->pipe = pipe;
13797 primary->plane = pipe;
a9ff8714 13798 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13799 primary->check_plane = intel_check_primary_plane;
13800 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13801 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13802 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13803 primary->plane = !pipe;
13804
6c0fd451
DL		 13805 if (INTEL_INFO(dev)->gen >= 9) {
13806 intel_primary_formats = skl_primary_formats;
13807 num_formats = ARRAY_SIZE(skl_primary_formats);
13808 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13809 intel_primary_formats = i965_primary_formats;
13810 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13811 } else {
13812 intel_primary_formats = i8xx_primary_formats;
13813 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13814 }
13815
13816 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13817 &intel_plane_funcs,
465c120c
MR		 13818 intel_primary_formats, num_formats,
13819 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13820
3b7a5119
SJ		 13821 if (INTEL_INFO(dev)->gen >= 4)
13822 intel_create_rotation_property(dev, primary);
48404c1e 13823
ea2c67bb
MR		 13824 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13825
465c120c
MR		 13826 return &primary->base;
13827}
13828
3b7a5119
SJ		 13829void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13830{
13831 if (!dev->mode_config.rotation_property) {
13832 unsigned long flags = BIT(DRM_ROTATE_0) |
13833 BIT(DRM_ROTATE_180);
13834
13835 if (INTEL_INFO(dev)->gen >= 9)
13836 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13837
13838 dev->mode_config.rotation_property =
13839 drm_mode_create_rotation_property(dev, flags);
13840 }
13841 if (dev->mode_config.rotation_property)
13842 drm_object_attach_property(&plane->base.base,
13843 dev->mode_config.rotation_property,
13844 plane->base.state->rotation);
13845}
13846
3d7d6510 13847static int
852e787c 13848intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13849 struct intel_crtc_state *crtc_state,
852e787c 13850 struct intel_plane_state *state)
3d7d6510 13851{
061e4b8d 13852 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13853 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13854 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13855 unsigned stride;
13856 int ret;
3d7d6510 13857
061e4b8d
ML		 13858 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13859 &state->dst, &state->clip,
3d7d6510
MR		 13860 DRM_PLANE_HELPER_NO_SCALING,
13861 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13862 true, true, &state->visible);
757f9a3e
GP		 13863 if (ret)
13864 return ret;
13865
757f9a3e
GP		 13866 /* if we want to turn off the cursor ignore width and height */
13867 if (!obj)
da20eabd 13868 return 0;
757f9a3e 13869
757f9a3e 13870 /* Check for which cursor types we support */
061e4b8d 13871 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13872 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13873 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13874 return -EINVAL;
13875 }
13876
ea2c67bb
MR		 13877 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13878 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13879 DRM_DEBUG_KMS("buffer is too small\n");
13880 return -ENOMEM;
13881 }
13882
3a656b54 13883 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13884 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13885 return -EINVAL;
32b7eeec
MR		 13886 }
13887
da20eabd 13888 return 0;
852e787c 13889}
3d7d6510 13890
a8ad0d8e
ML		 13891static void
13892intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13893 struct drm_crtc *crtc)
a8ad0d8e 13894{
a8ad0d8e
ML		 13895 intel_crtc_update_cursor(crtc, false);
13896}
13897
f4a2cf29 13898static void
852e787c
GP		 13899intel_commit_cursor_plane(struct drm_plane *plane,
13900 struct intel_plane_state *state)
13901{
2b875c22 13902 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13903 struct drm_device *dev = plane->dev;
13904 struct intel_crtc *intel_crtc;
2b875c22 13905 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13906 uint32_t addr;
852e787c 13907
ea2c67bb
MR		 13908 crtc = crtc ? crtc : plane->crtc;
13909 intel_crtc = to_intel_crtc(crtc);
13910
2b875c22 13911 plane->fb = state->base.fb;
ea2c67bb
MR		 13912 crtc->cursor_x = state->base.crtc_x;
13913 crtc->cursor_y = state->base.crtc_y;
13914
a912f12f
GP		 13915 if (intel_crtc->cursor_bo == obj)
13916 goto update;
4ed91096 13917
f4a2cf29 13918 if (!obj)
a912f12f 13919 addr = 0;
f4a2cf29 13920 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13921 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13922 else
a912f12f 13923 addr = obj->phys_handle->busaddr;
852e787c 13924
a912f12f
GP		 13925 intel_crtc->cursor_addr = addr;
13926 intel_crtc->cursor_bo = obj;
852e787c 13927
302d19ac 13928update:
a539205a 13929 if (crtc->state->active)
a912f12f 13930 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13931}
13932
3d7d6510
MR		 13933static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13934 int pipe)
13935{
13936 struct intel_plane *cursor;
8e7d688b 13937 struct intel_plane_state *state;
3d7d6510
MR		 13938
13939 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13940 if (cursor == NULL)
13941 return NULL;
13942
8e7d688b
MR		 13943 state = intel_create_plane_state(&cursor->base);
13944 if (!state) {
ea2c67bb
MR		 13945 kfree(cursor);
13946 return NULL;
13947 }
8e7d688b 13948 cursor->base.state = &state->base;
ea2c67bb 13949
3d7d6510
MR		 13950 cursor->can_scale = false;
13951 cursor->max_downscale = 1;
13952 cursor->pipe = pipe;
13953 cursor->plane = pipe;
a9ff8714 13954 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13955 cursor->check_plane = intel_check_cursor_plane;
13956 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13957 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13958
13959 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13960 &intel_plane_funcs,
3d7d6510
MR		 13961 intel_cursor_formats,
13962 ARRAY_SIZE(intel_cursor_formats),
13963 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13964
13965 if (INTEL_INFO(dev)->gen >= 4) {
13966 if (!dev->mode_config.rotation_property)
13967 dev->mode_config.rotation_property =
13968 drm_mode_create_rotation_property(dev,
13969 BIT(DRM_ROTATE_0) |
13970 BIT(DRM_ROTATE_180));
13971 if (dev->mode_config.rotation_property)
13972 drm_object_attach_property(&cursor->base.base,
13973 dev->mode_config.rotation_property,
8e7d688b 13974 state->base.rotation);
4398ad45
VS		 13975 }
13976
af99ceda
CK		 13977 if (INTEL_INFO(dev)->gen >=9)
13978 state->scaler_id = -1;
13979
ea2c67bb
MR		 13980 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13981
3d7d6510
MR		 13982 return &cursor->base;
13983}
13984
549e2bfb
CK		 13985static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13986 struct intel_crtc_state *crtc_state)
13987{
13988 int i;
13989 struct intel_scaler *intel_scaler;
13990 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13991
13992 for (i = 0; i < intel_crtc->num_scalers; i++) {
13993 intel_scaler = &scaler_state->scalers[i];
13994 intel_scaler->in_use = 0;
549e2bfb
CK		 13995 intel_scaler->mode = PS_SCALER_MODE_DYN;
13996 }
13997
13998 scaler_state->scaler_id = -1;
13999}
14000
b358d0a6 14001static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14002{
fbee40df 14003 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14004 struct intel_crtc *intel_crtc;
f5de6e07 14005 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14006 struct drm_plane *primary = NULL;
14007 struct drm_plane *cursor = NULL;
465c120c 14008 int i, ret;
79e53945 14009
955382f3 14010 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14011 if (intel_crtc == NULL)
14012 return;
14013
f5de6e07
ACO		 14014 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14015 if (!crtc_state)
14016 goto fail;
550acefd
ACO		 14017 intel_crtc->config = crtc_state;
14018 intel_crtc->base.state = &crtc_state->base;
07878248 14019 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14020
549e2bfb
CK		 14021 /* initialize shared scalers */
14022 if (INTEL_INFO(dev)->gen >= 9) {
14023 if (pipe == PIPE_C)
14024 intel_crtc->num_scalers = 1;
14025 else
14026 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14027
14028 skl_init_scalers(dev, intel_crtc, crtc_state);
14029 }
14030
465c120c 14031 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14032 if (!primary)
14033 goto fail;
14034
14035 cursor = intel_cursor_plane_create(dev, pipe);
14036 if (!cursor)
14037 goto fail;
14038
465c120c 14039 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14040 cursor, &intel_crtc_funcs);
14041 if (ret)
14042 goto fail;
79e53945
JB		 14043
14044 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14045 for (i = 0; i < 256; i++) {
14046 intel_crtc->lut_r[i] = i;
14047 intel_crtc->lut_g[i] = i;
14048 intel_crtc->lut_b[i] = i;
14049 }
14050
1f1c2e24
VS		 14051 /*
14052 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14053 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14054 */
80824003
JB		 14055 intel_crtc->pipe = pipe;
14056 intel_crtc->plane = pipe;
3a77c4c4 14057 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14058 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14059 intel_crtc->plane = !pipe;
80824003
JB		 14060 }
14061
4b0e333e
CW		 14062 intel_crtc->cursor_base = ~0;
14063 intel_crtc->cursor_cntl = ~0;
dc41c154 14064 intel_crtc->cursor_size = ~0;
8d7849db 14065
22fd0fab
JB		 14066 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14067 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14068 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14069 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14070
79e53945 14071 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14072
14073 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14074 return;
14075
14076fail:
14077 if (primary)
14078 drm_plane_cleanup(primary);
14079 if (cursor)
14080 drm_plane_cleanup(cursor);
f5de6e07 14081 kfree(crtc_state);
3d7d6510 14082 kfree(intel_crtc);
79e53945
JB		 14083}
14084
752aa88a
JB		 14085enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14086{
14087 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14088 struct drm_device *dev = connector->base.dev;
752aa88a 14089
51fd371b 14090 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14091
d3babd3f 14092 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14093 return INVALID_PIPE;
14094
14095 return to_intel_crtc(encoder->crtc)->pipe;
14096}
14097
08d7b3d1 14098int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14099 struct drm_file *file)
08d7b3d1 14100{
08d7b3d1 14101 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14102 struct drm_crtc *drmmode_crtc;
c05422d5 14103 struct intel_crtc *crtc;
08d7b3d1 14104
7707e653 14105 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14106
7707e653 14107 if (!drmmode_crtc) {
08d7b3d1 14108 DRM_ERROR("no such CRTC id\n");
3f2c2057 14109 return -ENOENT;
08d7b3d1
CW		 14110 }
14111
7707e653 14112 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14113 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14114
c05422d5 14115 return 0;
08d7b3d1
CW		 14116}
14117
66a9278e 14118static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14119{
66a9278e
DV		 14120 struct drm_device *dev = encoder->base.dev;
14121 struct intel_encoder *source_encoder;
79e53945 14122 int index_mask = 0;
79e53945
JB		 14123 int entry = 0;
14124
b2784e15 14125 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14126 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14127 index_mask |= (1 << entry);
14128
79e53945
JB		 14129 entry++;
14130 }
4ef69c7a 14131
79e53945
JB		 14132 return index_mask;
14133}
14134
4d302442
CW		 14135static bool has_edp_a(struct drm_device *dev)
14136{
14137 struct drm_i915_private *dev_priv = dev->dev_private;
14138
14139 if (!IS_MOBILE(dev))
14140 return false;
14141
14142 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14143 return false;
14144
e3589908 14145 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14146 return false;
14147
14148 return true;
14149}
14150
84b4e042
JB		 14151static bool intel_crt_present(struct drm_device *dev)
14152{
14153 struct drm_i915_private *dev_priv = dev->dev_private;
14154
884497ed
DL		 14155 if (INTEL_INFO(dev)->gen >= 9)
14156 return false;
14157
cf404ce4 14158 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14159 return false;
14160
14161 if (IS_CHERRYVIEW(dev))
14162 return false;
14163
14164 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14165 return false;
14166
14167 return true;
14168}
14169
79e53945
JB		 14170static void intel_setup_outputs(struct drm_device *dev)
14171{
725e30ad 14172 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14173 struct intel_encoder *encoder;
cb0953d7 14174 bool dpd_is_edp = false;
79e53945 14175
c9093354 14176 intel_lvds_init(dev);
79e53945 14177
84b4e042 14178 if (intel_crt_present(dev))
79935fca 14179 intel_crt_init(dev);
cb0953d7 14180
c776eb2e
VK		 14181 if (IS_BROXTON(dev)) {
14182 /*
14183 * FIXME: Broxton doesn't support port detection via the
14184 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14185 * detect the ports.
14186 */
14187 intel_ddi_init(dev, PORT_A);
14188 intel_ddi_init(dev, PORT_B);
14189 intel_ddi_init(dev, PORT_C);
14190 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14191 int found;
14192
de31facd
JB		 14193 /*
14194 * Haswell uses DDI functions to detect digital outputs.
14195 * On SKL pre-D0 the strap isn't connected, so we assume
14196 * it's there.
14197 */
0e72a5b5 14198 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14199 /* WaIgnoreDDIAStrap: skl */
14200 if (found ||
14201 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14202 intel_ddi_init(dev, PORT_A);
14203
14204 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14205 * register */
14206 found = I915_READ(SFUSE_STRAP);
14207
14208 if (found & SFUSE_STRAP_DDIB_DETECTED)
14209 intel_ddi_init(dev, PORT_B);
14210 if (found & SFUSE_STRAP_DDIC_DETECTED)
14211 intel_ddi_init(dev, PORT_C);
14212 if (found & SFUSE_STRAP_DDID_DETECTED)
14213 intel_ddi_init(dev, PORT_D);
14214 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14215 int found;
5d8a7752 14216 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14217
14218 if (has_edp_a(dev))
14219 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14220
dc0fa718 14221 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14222 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14223 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14224 if (!found)
e2debe91 14225 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14226 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14227 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14228 }
14229
dc0fa718 14230 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14231 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14232
dc0fa718 14233 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14234 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14235
5eb08b69 14236 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14237 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14238
270b3042 14239 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14240 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14241 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14242 /*
14243 * The DP_DETECTED bit is the latched state of the DDC
14244 * SDA pin at boot. However since eDP doesn't require DDC
14245 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14246 * eDP ports may have been muxed to an alternate function.
14247 * Thus we can't rely on the DP_DETECTED bit alone to detect
14248 * eDP ports. Consult the VBT as well as DP_DETECTED to
14249 * detect eDP ports.
14250 */
d2182a66
VS		 14251 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14252 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14253 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14254 PORT_B);
e17ac6db
VS		 14255 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14256 intel_dp_is_edp(dev, PORT_B))
14257 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14258
d2182a66
VS		 14259 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14260 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14261 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14262 PORT_C);
e17ac6db
VS		 14263 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14264 intel_dp_is_edp(dev, PORT_C))
14265 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14266
9418c1f1 14267 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14268 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14269 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14270 PORT_D);
e17ac6db
VS		 14271 /* eDP not supported on port D, so don't check VBT */
14272 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14273 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14274 }
14275
3cfca973 14276 intel_dsi_init(dev);
103a196f 14277 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14278 bool found = false;
7d57382e 14279
e2debe91 14280 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14281 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14282 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14283 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14284 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14285 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14286 }
27185ae1 14287
e7281eab 14288 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14289 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14290 }
13520b05
KH		 14291
14292 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14293
e2debe91 14294 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14295 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14296 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14297 }
27185ae1 14298
e2debe91 14299 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14300
b01f2c3a
JB		 14301 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14302 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14303 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14304 }
e7281eab 14305 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14306 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14307 }
27185ae1 14308
b01f2c3a 14309 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14310 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14311 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14312 } else if (IS_GEN2(dev))
79e53945
JB		 14313 intel_dvo_init(dev);
14314
103a196f 14315 if (SUPPORTS_TV(dev))
79e53945
JB		 14316 intel_tv_init(dev);
14317
0bc12bcb 14318 intel_psr_init(dev);
7c8f8a70 14319
b2784e15 14320 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14321 encoder->base.possible_crtcs = encoder->crtc_mask;
14322 encoder->base.possible_clones =
66a9278e 14323 intel_encoder_clones(encoder);
79e53945 14324 }
47356eb6 14325
dde86e2d 14326 intel_init_pch_refclk(dev);
270b3042
DV		 14327
14328 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14329}
14330
14331static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14332{
60a5ca01 14333 struct drm_device *dev = fb->dev;
79e53945 14334 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14335
ef2d633e 14336 drm_framebuffer_cleanup(fb);
60a5ca01 14337 mutex_lock(&dev->struct_mutex);
ef2d633e 14338 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14339 drm_gem_object_unreference(&intel_fb->obj->base);
14340 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14341 kfree(intel_fb);
14342}
14343
14344static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14345 struct drm_file *file,
79e53945
JB		 14346 unsigned int *handle)
14347{
14348 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14349 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14350
05394f39 14351 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14352}
14353
14354static const struct drm_framebuffer_funcs intel_fb_funcs = {
14355 .destroy = intel_user_framebuffer_destroy,
14356 .create_handle = intel_user_framebuffer_create_handle,
14357};
14358
b321803d
DL		 14359static
14360u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14361 uint32_t pixel_format)
14362{
14363 u32 gen = INTEL_INFO(dev)->gen;
14364
14365 if (gen >= 9) {
14366 /* "The stride in bytes must not exceed the of the size of 8K
14367 * pixels and 32K bytes."
14368 */
14369 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14370 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14371 return 32*1024;
14372 } else if (gen >= 4) {
14373 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14374 return 16*1024;
14375 else
14376 return 32*1024;
14377 } else if (gen >= 3) {
14378 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14379 return 8*1024;
14380 else
14381 return 16*1024;
14382 } else {
14383 /* XXX DSPC is limited to 4k tiled */
14384 return 8*1024;
14385 }
14386}
14387
b5ea642a
DV		 14388static int intel_framebuffer_init(struct drm_device *dev,
14389 struct intel_framebuffer *intel_fb,
14390 struct drm_mode_fb_cmd2 *mode_cmd,
14391 struct drm_i915_gem_object *obj)
79e53945 14392{
6761dd31 14393 unsigned int aligned_height;
79e53945 14394 int ret;
b321803d 14395 u32 pitch_limit, stride_alignment;
79e53945 14396
dd4916c5
DV		 14397 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14398
2a80eada
DV		 14399 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14400 /* Enforce that fb modifier and tiling mode match, but only for
14401 * X-tiled. This is needed for FBC. */
14402 if (!!(obj->tiling_mode == I915_TILING_X) !=
14403 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14404 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14405 return -EINVAL;
14406 }
14407 } else {
14408 if (obj->tiling_mode == I915_TILING_X)
14409 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14410 else if (obj->tiling_mode == I915_TILING_Y) {
14411 DRM_DEBUG("No Y tiling for legacy addfb\n");
14412 return -EINVAL;
14413 }
14414 }
14415
9a8f0a12
TU		 14416 /* Passed in modifier sanity checking. */
14417 switch (mode_cmd->modifier[0]) {
14418 case I915_FORMAT_MOD_Y_TILED:
14419 case I915_FORMAT_MOD_Yf_TILED:
14420 if (INTEL_INFO(dev)->gen < 9) {
14421 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14422 mode_cmd->modifier[0]);
14423 return -EINVAL;
14424 }
14425 case DRM_FORMAT_MOD_NONE:
14426 case I915_FORMAT_MOD_X_TILED:
14427 break;
14428 default:
c0f40428
JB		 14429 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14430 mode_cmd->modifier[0]);
57cd6508 14431 return -EINVAL;
c16ed4be 14432 }
57cd6508 14433
b321803d
DL		 14434 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14435 mode_cmd->pixel_format);
14436 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14437 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14438 mode_cmd->pitches[0], stride_alignment);
57cd6508 14439 return -EINVAL;
c16ed4be 14440 }
57cd6508 14441
b321803d
DL		 14442 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14443 mode_cmd->pixel_format);
a35cdaa0 14444 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14445 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14446 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14447 "tiled" : "linear",
a35cdaa0 14448 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14449 return -EINVAL;
c16ed4be 14450 }
5d7bd705 14451
2a80eada 14452 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14453 mode_cmd->pitches[0] != obj->stride) {
14454 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14455 mode_cmd->pitches[0], obj->stride);
5d7bd705 14456 return -EINVAL;
c16ed4be 14457 }
5d7bd705 14458
57779d06 14459 /* Reject formats not supported by any plane early. */
308e5bcb 14460 switch (mode_cmd->pixel_format) {
57779d06 14461 case DRM_FORMAT_C8:
04b3924d
VS		 14462 case DRM_FORMAT_RGB565:
14463 case DRM_FORMAT_XRGB8888:
14464 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14465 break;
14466 case DRM_FORMAT_XRGB1555:
c16ed4be 14467 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14468 DRM_DEBUG("unsupported pixel format: %s\n",
14469 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14470 return -EINVAL;
c16ed4be 14471 }
57779d06 14472 break;
57779d06 14473 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14474 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14475 DRM_DEBUG("unsupported pixel format: %s\n",
14476 drm_get_format_name(mode_cmd->pixel_format));
14477 return -EINVAL;
14478 }
14479 break;
14480 case DRM_FORMAT_XBGR8888:
04b3924d 14481 case DRM_FORMAT_XRGB2101010:
57779d06 14482 case DRM_FORMAT_XBGR2101010:
c16ed4be 14483 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14484 DRM_DEBUG("unsupported pixel format: %s\n",
14485 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14486 return -EINVAL;
c16ed4be 14487 }
b5626747 14488 break;
7531208b
DL		 14489 case DRM_FORMAT_ABGR2101010:
14490 if (!IS_VALLEYVIEW(dev)) {
14491 DRM_DEBUG("unsupported pixel format: %s\n",
14492 drm_get_format_name(mode_cmd->pixel_format));
14493 return -EINVAL;
14494 }
14495 break;
04b3924d
VS		 14496 case DRM_FORMAT_YUYV:
14497 case DRM_FORMAT_UYVY:
14498 case DRM_FORMAT_YVYU:
14499 case DRM_FORMAT_VYUY:
c16ed4be 14500 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14501 DRM_DEBUG("unsupported pixel format: %s\n",
14502 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14503 return -EINVAL;
c16ed4be 14504 }
57cd6508
CW		 14505 break;
14506 default:
4ee62c76
VS		 14507 DRM_DEBUG("unsupported pixel format: %s\n",
14508 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14509 return -EINVAL;
14510 }
14511
90f9a336
VS		 14512 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14513 if (mode_cmd->offsets[0] != 0)
14514 return -EINVAL;
14515
ec2c981e 14516 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14517 mode_cmd->pixel_format,
14518 mode_cmd->modifier[0]);
53155c0a
DV		 14519 /* FIXME drm helper for size checks (especially planar formats)? */
14520 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14521 return -EINVAL;
14522
c7d73f6a
DV		 14523 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14524 intel_fb->obj = obj;
80075d49 14525 intel_fb->obj->framebuffer_references++;
c7d73f6a 14526
79e53945
JB		 14527 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14528 if (ret) {
14529 DRM_ERROR("framebuffer init failed %d\n", ret);
14530 return ret;
14531 }
14532
79e53945
JB		 14533 return 0;
14534}
14535
79e53945
JB		 14536static struct drm_framebuffer *
14537intel_user_framebuffer_create(struct drm_device *dev,
14538 struct drm_file *filp,
308e5bcb 14539 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14540{
05394f39 14541 struct drm_i915_gem_object *obj;
79e53945 14542
308e5bcb
JB		 14543 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14544 mode_cmd->handles[0]));
c8725226 14545 if (&obj->base == NULL)
cce13ff7 14546 return ERR_PTR(-ENOENT);
79e53945 14547
d2dff872 14548 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14549}
14550
4520f53a 14551#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14552static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14553{
14554}
14555#endif
14556
79e53945 14557static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14558 .fb_create = intel_user_framebuffer_create,
0632fef6 14559 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14560 .atomic_check = intel_atomic_check,
14561 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14562 .atomic_state_alloc = intel_atomic_state_alloc,
14563 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14564};
14565
e70236a8
JB		 14566/* Set up chip specific display functions */
14567static void intel_init_display(struct drm_device *dev)
14568{
14569 struct drm_i915_private *dev_priv = dev->dev_private;
14570
ee9300bb
DV		 14571 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14572 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14573 else if (IS_CHERRYVIEW(dev))
14574 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14575 else if (IS_VALLEYVIEW(dev))
14576 dev_priv->display.find_dpll = vlv_find_best_dpll;
14577 else if (IS_PINEVIEW(dev))
14578 dev_priv->display.find_dpll = pnv_find_best_dpll;
14579 else
14580 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14581
bc8d7dff
DL		 14582 if (INTEL_INFO(dev)->gen >= 9) {
14583 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14584 dev_priv->display.get_initial_plane_config =
14585 skylake_get_initial_plane_config;
bc8d7dff
DL		 14586 dev_priv->display.crtc_compute_clock =
14587 haswell_crtc_compute_clock;
14588 dev_priv->display.crtc_enable = haswell_crtc_enable;
14589 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14590 dev_priv->display.update_primary_plane =
14591 skylake_update_primary_plane;
14592 } else if (HAS_DDI(dev)) {
0e8ffe1b 14593 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14594 dev_priv->display.get_initial_plane_config =
14595 ironlake_get_initial_plane_config;
797d0259
ACO		 14596 dev_priv->display.crtc_compute_clock =
14597 haswell_crtc_compute_clock;
4f771f10
PZ		 14598 dev_priv->display.crtc_enable = haswell_crtc_enable;
14599 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14600 dev_priv->display.update_primary_plane =
14601 ironlake_update_primary_plane;
09b4ddf9 14602 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14603 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14604 dev_priv->display.get_initial_plane_config =
14605 ironlake_get_initial_plane_config;
3fb37703
ACO		 14606 dev_priv->display.crtc_compute_clock =
14607 ironlake_crtc_compute_clock;
76e5a89c
DV		 14608 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14609 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14610 dev_priv->display.update_primary_plane =
14611 ironlake_update_primary_plane;
89b667f8
JB		 14612 } else if (IS_VALLEYVIEW(dev)) {
14613 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14614 dev_priv->display.get_initial_plane_config =
14615 i9xx_get_initial_plane_config;
d6dfee7a 14616 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14617 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14618 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14619 dev_priv->display.update_primary_plane =
14620 i9xx_update_primary_plane;
f564048e 14621 } else {
0e8ffe1b 14622 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14623 dev_priv->display.get_initial_plane_config =
14624 i9xx_get_initial_plane_config;
d6dfee7a 14625 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14626 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14627 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14628 dev_priv->display.update_primary_plane =
14629 i9xx_update_primary_plane;
f564048e 14630 }
e70236a8 14631
e70236a8 14632 /* Returns the core display clock speed */
1652d19e
VS		 14633 if (IS_SKYLAKE(dev))
14634 dev_priv->display.get_display_clock_speed =
14635 skylake_get_display_clock_speed;
acd3f3d3
BP		 14636 else if (IS_BROXTON(dev))
14637 dev_priv->display.get_display_clock_speed =
14638 broxton_get_display_clock_speed;
1652d19e
VS		 14639 else if (IS_BROADWELL(dev))
14640 dev_priv->display.get_display_clock_speed =
14641 broadwell_get_display_clock_speed;
14642 else if (IS_HASWELL(dev))
14643 dev_priv->display.get_display_clock_speed =
14644 haswell_get_display_clock_speed;
14645 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14646 dev_priv->display.get_display_clock_speed =
14647 valleyview_get_display_clock_speed;
b37a6434
VS		 14648 else if (IS_GEN5(dev))
14649 dev_priv->display.get_display_clock_speed =
14650 ilk_get_display_clock_speed;
a7c66cd8 14651 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14652 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14653 dev_priv->display.get_display_clock_speed =
14654 i945_get_display_clock_speed;
34edce2f
VS		 14655 else if (IS_GM45(dev))
14656 dev_priv->display.get_display_clock_speed =
14657 gm45_get_display_clock_speed;
14658 else if (IS_CRESTLINE(dev))
14659 dev_priv->display.get_display_clock_speed =
14660 i965gm_get_display_clock_speed;
14661 else if (IS_PINEVIEW(dev))
14662 dev_priv->display.get_display_clock_speed =
14663 pnv_get_display_clock_speed;
14664 else if (IS_G33(dev) || IS_G4X(dev))
14665 dev_priv->display.get_display_clock_speed =
14666 g33_get_display_clock_speed;
e70236a8
JB		 14667 else if (IS_I915G(dev))
14668 dev_priv->display.get_display_clock_speed =
14669 i915_get_display_clock_speed;
257a7ffc 14670 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14671 dev_priv->display.get_display_clock_speed =
14672 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14673 else if (IS_PINEVIEW(dev))
14674 dev_priv->display.get_display_clock_speed =
14675 pnv_get_display_clock_speed;
e70236a8
JB		 14676 else if (IS_I915GM(dev))
14677 dev_priv->display.get_display_clock_speed =
14678 i915gm_get_display_clock_speed;
14679 else if (IS_I865G(dev))
14680 dev_priv->display.get_display_clock_speed =
14681 i865_get_display_clock_speed;
f0f8a9ce 14682 else if (IS_I85X(dev))
e70236a8 14683 dev_priv->display.get_display_clock_speed =
1b1d2716 14684 i85x_get_display_clock_speed;
623e01e5
VS		 14685 else { /* 830 */
14686 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14687 dev_priv->display.get_display_clock_speed =
14688 i830_get_display_clock_speed;
623e01e5 14689 }
e70236a8 14690
7c10a2b5 14691 if (IS_GEN5(dev)) {
3bb11b53 14692 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14693 } else if (IS_GEN6(dev)) {
14694 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14695 } else if (IS_IVYBRIDGE(dev)) {
14696 /* FIXME: detect B0+ stepping and use auto training */
14697 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14698 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14699 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14700 if (IS_BROADWELL(dev)) {
14701 dev_priv->display.modeset_commit_cdclk =
14702 broadwell_modeset_commit_cdclk;
14703 dev_priv->display.modeset_calc_cdclk =
14704 broadwell_modeset_calc_cdclk;
14705 }
30a970c6 14706 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14707 dev_priv->display.modeset_commit_cdclk =
14708 valleyview_modeset_commit_cdclk;
14709 dev_priv->display.modeset_calc_cdclk =
14710 valleyview_modeset_calc_cdclk;
f8437dd1 14711 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14712 dev_priv->display.modeset_commit_cdclk =
14713 broxton_modeset_commit_cdclk;
14714 dev_priv->display.modeset_calc_cdclk =
14715 broxton_modeset_calc_cdclk;
e70236a8 14716 }
8c9f3aaf 14717
8c9f3aaf
JB		 14718 switch (INTEL_INFO(dev)->gen) {
14719 case 2:
14720 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14721 break;
14722
14723 case 3:
14724 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14725 break;
14726
14727 case 4:
14728 case 5:
14729 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14730 break;
14731
14732 case 6:
14733 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14734 break;
7c9017e5 14735 case 7:
4e0bbc31 14736 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14737 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14738 break;
830c81db 14739 case 9:
ba343e02
TU		 14740 /* Drop through - unsupported since execlist only. */
14741 default:
14742 /* Default just returns -ENODEV to indicate unsupported */
14743 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14744 }
7bd688cd
JN		 14745
14746 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14747
14748 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14749}
14750
b690e96c
JB		 14751/*
14752 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14753 * resume, or other times. This quirk makes sure that's the case for
14754 * affected systems.
14755 */
0206e353 14756static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14757{
14758 struct drm_i915_private *dev_priv = dev->dev_private;
14759
14760 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14761 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14762}
14763
b6b5d049
VS		 14764static void quirk_pipeb_force(struct drm_device *dev)
14765{
14766 struct drm_i915_private *dev_priv = dev->dev_private;
14767
14768 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14769 DRM_INFO("applying pipe b force quirk\n");
14770}
14771
435793df
KP		 14772/*
14773 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14774 */
14775static void quirk_ssc_force_disable(struct drm_device *dev)
14776{
14777 struct drm_i915_private *dev_priv = dev->dev_private;
14778 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14779 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14780}
14781
4dca20ef 14782/*
5a15ab5b
CE		 14783 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14784 * brightness value
4dca20ef
CE		 14785 */
14786static void quirk_invert_brightness(struct drm_device *dev)
14787{
14788 struct drm_i915_private *dev_priv = dev->dev_private;
14789 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14790 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14791}
14792
9c72cc6f
SD		 14793/* Some VBT's incorrectly indicate no backlight is present */
14794static void quirk_backlight_present(struct drm_device *dev)
14795{
14796 struct drm_i915_private *dev_priv = dev->dev_private;
14797 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14798 DRM_INFO("applying backlight present quirk\n");
14799}
14800
b690e96c
JB		 14801struct intel_quirk {
14802 int device;
14803 int subsystem_vendor;
14804 int subsystem_device;
14805 void (*hook)(struct drm_device *dev);
14806};
14807
5f85f176
EE		 14808/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14809struct intel_dmi_quirk {
14810 void (*hook)(struct drm_device *dev);
14811 const struct dmi_system_id (*dmi_id_list)[];
14812};
14813
14814static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14815{
14816 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14817 return 1;
14818}
14819
14820static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14821 {
14822 .dmi_id_list = &(const struct dmi_system_id[]) {
14823 {
14824 .callback = intel_dmi_reverse_brightness,
14825 .ident = "NCR Corporation",
14826 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14827 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14828 },
14829 },
14830 { } /* terminating entry */
14831 },
14832 .hook = quirk_invert_brightness,
14833 },
14834};
14835
c43b5634 14836static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14837 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14838 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14839
b690e96c
JB		 14840 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14841 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14842
5f080c0f
VS		 14843 /* 830 needs to leave pipe A & dpll A up */
14844 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14845
b6b5d049
VS		 14846 /* 830 needs to leave pipe B & dpll B up */
14847 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14848
435793df
KP		 14849 /* Lenovo U160 cannot use SSC on LVDS */
14850 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14851
14852 /* Sony Vaio Y cannot use SSC on LVDS */
14853 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14854
be505f64
AH		 14855 /* Acer Aspire 5734Z must invert backlight brightness */
14856 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14857
14858 /* Acer/eMachines G725 */
14859 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14860
14861 /* Acer/eMachines e725 */
14862 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14863
14864 /* Acer/Packard Bell NCL20 */
14865 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14866
14867 /* Acer Aspire 4736Z */
14868 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14869
14870 /* Acer Aspire 5336 */
14871 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14872
14873 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14874 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14875
dfb3d47b
SD		 14876 /* Acer C720 Chromebook (Core i3 4005U) */
14877 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14878
b2a9601c 14879 /* Apple Macbook 2,1 (Core 2 T7400) */
14880 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14881
d4967d8c
SD		 14882 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14883 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14884
14885 /* HP Chromebook 14 (Celeron 2955U) */
14886 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14887
14888 /* Dell Chromebook 11 */
14889 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14890};
14891
14892static void intel_init_quirks(struct drm_device *dev)
14893{
14894 struct pci_dev *d = dev->pdev;
14895 int i;
14896
14897 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14898 struct intel_quirk *q = &intel_quirks[i];
14899
14900 if (d->device == q->device &&
14901 (d->subsystem_vendor == q->subsystem_vendor ||
14902 q->subsystem_vendor == PCI_ANY_ID) &&
14903 (d->subsystem_device == q->subsystem_device ||
14904 q->subsystem_device == PCI_ANY_ID))
14905 q->hook(dev);
14906 }
5f85f176
EE		 14907 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14908 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14909 intel_dmi_quirks[i].hook(dev);
14910 }
b690e96c
JB		 14911}
14912
9cce37f4
JB		 14913/* Disable the VGA plane that we never use */
14914static void i915_disable_vga(struct drm_device *dev)
14915{
14916 struct drm_i915_private *dev_priv = dev->dev_private;
14917 u8 sr1;
766aa1c4 14918 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14919
2b37c616 14920 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14921 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14922 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14923 sr1 = inb(VGA_SR_DATA);
14924 outb(sr1 | 1<<5, VGA_SR_DATA);
14925 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14926 udelay(300);
14927
01f5a626 14928 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14929 POSTING_READ(vga_reg);
14930}
14931
f817586c
DV		 14932void intel_modeset_init_hw(struct drm_device *dev)
14933{
b6283055 14934 intel_update_cdclk(dev);
a8f78b58 14935 intel_prepare_ddi(dev);
f817586c 14936 intel_init_clock_gating(dev);
8090c6b9 14937 intel_enable_gt_powersave(dev);
f817586c
DV		 14938}
14939
79e53945
JB		 14940void intel_modeset_init(struct drm_device *dev)
14941{
652c393a 14942 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14943 int sprite, ret;
8cc87b75 14944 enum pipe pipe;
46f297fb 14945 struct intel_crtc *crtc;
79e53945
JB		 14946
14947 drm_mode_config_init(dev);
14948
14949 dev->mode_config.min_width = 0;
14950 dev->mode_config.min_height = 0;
14951
019d96cb
DA		 14952 dev->mode_config.preferred_depth = 24;
14953 dev->mode_config.prefer_shadow = 1;
14954
25bab385
TU		 14955 dev->mode_config.allow_fb_modifiers = true;
14956
e6ecefaa 14957 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14958
b690e96c
JB		 14959 intel_init_quirks(dev);
14960
1fa61106
ED		 14961 intel_init_pm(dev);
14962
e3c74757
BW		 14963 if (INTEL_INFO(dev)->num_pipes == 0)
14964 return;
14965
e70236a8 14966 intel_init_display(dev);
7c10a2b5 14967 intel_init_audio(dev);
e70236a8 14968
a6c45cf0
CW		 14969 if (IS_GEN2(dev)) {
14970 dev->mode_config.max_width = 2048;
14971 dev->mode_config.max_height = 2048;
14972 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14973 dev->mode_config.max_width = 4096;
14974 dev->mode_config.max_height = 4096;
79e53945 14975 } else {
a6c45cf0
CW		 14976 dev->mode_config.max_width = 8192;
14977 dev->mode_config.max_height = 8192;
79e53945 14978 }
068be561 14979
dc41c154
VS		 14980 if (IS_845G(dev) || IS_I865G(dev)) {
14981 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14982 dev->mode_config.cursor_height = 1023;
14983 } else if (IS_GEN2(dev)) {
068be561
DL		 14984 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14985 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14986 } else {
14987 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14988 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14989 }
14990
5d4545ae 14991 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14992
28c97730 14993 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14994 INTEL_INFO(dev)->num_pipes,
14995 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14996
055e393f 14997 for_each_pipe(dev_priv, pipe) {
8cc87b75 14998 intel_crtc_init(dev, pipe);
3bdcfc0c 14999 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15000 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15001 if (ret)
06da8da2 15002 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15003 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15004 }
79e53945
JB		 15005 }
15006
f42bb70d
JB		 15007 intel_init_dpio(dev);
15008
e72f9fbf 15009 intel_shared_dpll_init(dev);
ee7b9f93 15010
9cce37f4
JB		 15011 /* Just disable it once at startup */
15012 i915_disable_vga(dev);
79e53945 15013 intel_setup_outputs(dev);
11be49eb
CW		 15014
15015 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 15016 intel_fbc_disable(dev);
fa9fa083 15017
6e9f798d 15018 drm_modeset_lock_all(dev);
fa9fa083 15019 intel_modeset_setup_hw_state(dev, false);
6e9f798d 15020 drm_modeset_unlock_all(dev);
46f297fb 15021
d3fcc808 15022 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 15023 if (!crtc->active)
15024 continue;
15025
46f297fb 15026 /*
46f297fb
JB		 15027 * Note that reserving the BIOS fb up front prevents us
15028 * from stuffing other stolen allocations like the ring
15029 * on top. This prevents some ugliness at boot time, and
15030 * can even allow for smooth boot transitions if the BIOS
15031 * fb is large enough for the active pipe configuration.
15032 */
5724dbd1
DL		 15033 if (dev_priv->display.get_initial_plane_config) {
15034 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 15035 &crtc->plane_config);
15036 /*
15037 * If the fb is shared between multiple heads, we'll
15038 * just get the first one.
15039 */
f6936e29 15040 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 15041 }
46f297fb 15042 }
2c7111db
CW		 15043}
15044
7fad798e
DV		 15045static void intel_enable_pipe_a(struct drm_device *dev)
15046{
15047 struct intel_connector *connector;
15048 struct drm_connector *crt = NULL;
15049 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15050 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15051
15052 /* We can't just switch on the pipe A, we need to set things up with a
15053 * proper mode and output configuration. As a gross hack, enable pipe A
15054 * by enabling the load detect pipe once. */
3a3371ff 15055 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15056 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15057 crt = &connector->base;
15058 break;
15059 }
15060 }
15061
15062 if (!crt)
15063 return;
15064
208bf9fd 15065 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15066 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15067}
15068
fa555837
DV		 15069static bool
15070intel_check_plane_mapping(struct intel_crtc *crtc)
15071{
7eb552ae
BW		 15072 struct drm_device *dev = crtc->base.dev;
15073 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15074 u32 reg, val;
15075
7eb552ae 15076 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15077 return true;
15078
15079 reg = DSPCNTR(!crtc->plane);
15080 val = I915_READ(reg);
15081
15082 if ((val & DISPLAY_PLANE_ENABLE) &&
15083 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15084 return false;
15085
15086 return true;
15087}
15088
24929352
DV		 15089static void intel_sanitize_crtc(struct intel_crtc *crtc)
15090{
15091 struct drm_device *dev = crtc->base.dev;
15092 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 15093 struct intel_encoder *encoder;
fa555837 15094 u32 reg;
b17d48e2 15095 bool enable;
24929352 15096
24929352 15097 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15098 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15099 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15100
d3eaf884 15101 /* restore vblank interrupts to correct state */
9625604c 15102 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 15103 if (crtc->active) {
15104 update_scanline_offset(crtc);
9625604c
DV		 15105 drm_crtc_vblank_on(&crtc->base);
15106 }
d3eaf884 15107
24929352 15108 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15109 * disable the crtc (and hence change the state) if it is wrong. Note
15110 * that gen4+ has a fixed plane -> pipe mapping. */
15111 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15112 bool plane;
15113
24929352
DV		 15114 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15115 crtc->base.base.id);
15116
15117 /* Pipe has the wrong plane attached and the plane is active.
15118 * Temporarily change the plane mapping and disable everything
15119 * ... */
15120 plane = crtc->plane;
b70709a6 15121 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15122 crtc->plane = !plane;
b17d48e2 15123 intel_crtc_disable_noatomic(&crtc->base);
24929352 15124 crtc->plane = plane;
24929352 15125 }
24929352 15126
7fad798e
DV		 15127 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15128 crtc->pipe == PIPE_A && !crtc->active) {
15129 /* BIOS forgot to enable pipe A, this mostly happens after
15130 * resume. Force-enable the pipe to fix this, the update_dpms
15131 * call below we restore the pipe to the right state, but leave
15132 * the required bits on. */
15133 intel_enable_pipe_a(dev);
15134 }
15135
24929352
DV		 15136 /* Adjust the state of the output pipe according to whether we
15137 * have active connectors/encoders. */
b17d48e2
ML		 15138 enable = false;
15139 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15140 enable |= encoder->connectors_active;
24929352 15141
b17d48e2
ML		 15142 if (!enable)
15143 intel_crtc_disable_noatomic(&crtc->base);
24929352 15144
53d9f4e9 15145 if (crtc->active != crtc->base.state->active) {
24929352
DV		 15146
15147 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15148 * functions or because of calls to intel_crtc_disable_noatomic,
15149 * or because the pipe is force-enabled due to the
24929352
DV		 15150 * pipe A quirk. */
15151 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15152 crtc->base.base.id,
83d65738 15153 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15154 crtc->active ? "enabled" : "disabled");
15155
83d65738 15156 crtc->base.state->enable = crtc->active;
49d6fa21 15157 crtc->base.state->active = crtc->active;
24929352
DV		 15158 crtc->base.enabled = crtc->active;
15159
15160 /* Because we only establish the connector -> encoder ->
15161 * crtc links if something is active, this means the
15162 * crtc is now deactivated. Break the links. connector
15163 * -> encoder links are only establish when things are
15164 * actually up, hence no need to break them. */
15165 WARN_ON(crtc->active);
15166
15167 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15168 WARN_ON(encoder->connectors_active);
15169 encoder->base.crtc = NULL;
15170 }
15171 }
c5ab3bc0 15172
a3ed6aad 15173 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15174 /*
15175 * We start out with underrun reporting disabled to avoid races.
15176 * For correct bookkeeping mark this on active crtcs.
15177 *
c5ab3bc0
DV		 15178 * Also on gmch platforms we dont have any hardware bits to
15179 * disable the underrun reporting. Which means we need to start
15180 * out with underrun reporting disabled also on inactive pipes,
15181 * since otherwise we'll complain about the garbage we read when
15182 * e.g. coming up after runtime pm.
15183 *
4cc31489
DV		 15184 * No protection against concurrent access is required - at
15185 * worst a fifo underrun happens which also sets this to false.
15186 */
15187 crtc->cpu_fifo_underrun_disabled = true;
15188 crtc->pch_fifo_underrun_disabled = true;
15189 }
24929352
DV		 15190}
15191
15192static void intel_sanitize_encoder(struct intel_encoder *encoder)
15193{
15194 struct intel_connector *connector;
15195 struct drm_device *dev = encoder->base.dev;
15196
15197 /* We need to check both for a crtc link (meaning that the
15198 * encoder is active and trying to read from a pipe) and the
15199 * pipe itself being active. */
15200 bool has_active_crtc = encoder->base.crtc &&
15201 to_intel_crtc(encoder->base.crtc)->active;
15202
15203 if (encoder->connectors_active && !has_active_crtc) {
15204 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15205 encoder->base.base.id,
8e329a03 15206 encoder->base.name);
24929352
DV		 15207
15208 /* Connector is active, but has no active pipe. This is
15209 * fallout from our resume register restoring. Disable
15210 * the encoder manually again. */
15211 if (encoder->base.crtc) {
15212 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15213 encoder->base.base.id,
8e329a03 15214 encoder->base.name);
24929352 15215 encoder->disable(encoder);
a62d1497
VS		 15216 if (encoder->post_disable)
15217 encoder->post_disable(encoder);
24929352 15218 }
7f1950fb
EE		 15219 encoder->base.crtc = NULL;
15220 encoder->connectors_active = false;
24929352
DV		 15221
15222 /* Inconsistent output/port/pipe state happens presumably due to
15223 * a bug in one of the get_hw_state functions. Or someplace else
15224 * in our code, like the register restore mess on resume. Clamp
15225 * things to off as a safer default. */
3a3371ff 15226 for_each_intel_connector(dev, connector) {
24929352
DV		 15227 if (connector->encoder != encoder)
15228 continue;
7f1950fb
EE		 15229 connector->base.dpms = DRM_MODE_DPMS_OFF;
15230 connector->base.encoder = NULL;
24929352
DV		 15231 }
15232 }
15233 /* Enabled encoders without active connectors will be fixed in
15234 * the crtc fixup. */
15235}
15236
04098753 15237void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15238{
15239 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15240 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15241
04098753
ID		 15242 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15243 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15244 i915_disable_vga(dev);
15245 }
15246}
15247
15248void i915_redisable_vga(struct drm_device *dev)
15249{
15250 struct drm_i915_private *dev_priv = dev->dev_private;
15251
8dc8a27c
PZ		 15252 /* This function can be called both from intel_modeset_setup_hw_state or
15253 * at a very early point in our resume sequence, where the power well
15254 * structures are not yet restored. Since this function is at a very
15255 * paranoid "someone might have enabled VGA while we were not looking"
15256 * level, just check if the power well is enabled instead of trying to
15257 * follow the "don't touch the power well if we don't need it" policy
15258 * the rest of the driver uses. */
f458ebbc 15259 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15260 return;
15261
04098753 15262 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15263}
15264
98ec7739
VS		 15265static bool primary_get_hw_state(struct intel_crtc *crtc)
15266{
15267 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15268
d032ffa0
ML		 15269 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15270}
15271
15272static void readout_plane_state(struct intel_crtc *crtc,
15273 struct intel_crtc_state *crtc_state)
15274{
15275 struct intel_plane *p;
15276 struct drm_plane_state *drm_plane_state;
15277 bool active = crtc_state->base.active;
15278
15279 if (active) {
15280 crtc_state->quirks |= PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15281
15282 /* apply to previous sw state too */
15283 to_intel_crtc_state(crtc->base.state)->quirks |=
15284 PIPE_CONFIG_QUIRK_INITIAL_PLANES;
15285 }
98ec7739 15286
d032ffa0
ML		 15287 for_each_intel_plane(crtc->base.dev, p) {
15288 bool visible = active;
15289
15290 if (crtc->pipe != p->pipe)
15291 continue;
15292
15293 drm_plane_state = p->base.state;
15294 if (active && p->base.type == DRM_PLANE_TYPE_PRIMARY) {
15295 visible = primary_get_hw_state(crtc);
15296 to_intel_plane_state(drm_plane_state)->visible = visible;
15297 } else {
15298 /*
15299 * unknown state, assume it's off to force a transition
15300 * to on when calculating state changes.
15301 */
15302 to_intel_plane_state(drm_plane_state)->visible = false;
15303 }
15304
15305 if (visible) {
15306 crtc_state->base.plane_mask |=
15307 1 << drm_plane_index(&p->base);
15308 } else if (crtc_state->base.state) {
15309 /* Make this unconditional for atomic hw readout. */
15310 crtc_state->base.plane_mask &=
15311 ~(1 << drm_plane_index(&p->base));
15312 }
15313 }
98ec7739
VS		 15314}
15315
30e984df 15316static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15317{
15318 struct drm_i915_private *dev_priv = dev->dev_private;
15319 enum pipe pipe;
24929352
DV		 15320 struct intel_crtc *crtc;
15321 struct intel_encoder *encoder;
15322 struct intel_connector *connector;
5358901f 15323 int i;
24929352 15324
d3fcc808 15325 for_each_intel_crtc(dev, crtc) {
6e3c9717 15326 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15327 crtc->config->base.crtc = &crtc->base;
3b117c8f 15328
6e3c9717 15329 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15330
0e8ffe1b 15331 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15332 crtc->config);
24929352 15333
83d65738 15334 crtc->base.state->enable = crtc->active;
49d6fa21 15335 crtc->base.state->active = crtc->active;
24929352 15336 crtc->base.enabled = crtc->active;
b8b7fade 15337 crtc->base.hwmode = crtc->config->base.adjusted_mode;
b70709a6 15338
d032ffa0 15339 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15340
15341 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15342 crtc->base.base.id,
15343 crtc->active ? "enabled" : "disabled");
15344 }
15345
5358901f
DV		 15346 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15347 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15348
3e369b76
ACO		 15349 pll->on = pll->get_hw_state(dev_priv, pll,
15350 &pll->config.hw_state);
5358901f 15351 pll->active = 0;
3e369b76 15352 pll->config.crtc_mask = 0;
d3fcc808 15353 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15354 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15355 pll->active++;
3e369b76 15356 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15357 }
5358901f 15358 }
5358901f 15359
1e6f2ddc 15360 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15361 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15362
3e369b76 15363 if (pll->config.crtc_mask)
bd2bb1b9 15364 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15365 }
15366
b2784e15 15367 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15368 pipe = 0;
15369
15370 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15371 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15372 encoder->base.crtc = &crtc->base;
6e3c9717 15373 encoder->get_config(encoder, crtc->config);
24929352
DV		 15374 } else {
15375 encoder->base.crtc = NULL;
15376 }
15377
15378 encoder->connectors_active = false;
6f2bcceb 15379 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15380 encoder->base.base.id,
8e329a03 15381 encoder->base.name,
24929352 15382 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15383 pipe_name(pipe));
24929352
DV		 15384 }
15385
3a3371ff 15386 for_each_intel_connector(dev, connector) {
24929352
DV		 15387 if (connector->get_hw_state(connector)) {
15388 connector->base.dpms = DRM_MODE_DPMS_ON;
15389 connector->encoder->connectors_active = true;
15390 connector->base.encoder = &connector->encoder->base;
15391 } else {
15392 connector->base.dpms = DRM_MODE_DPMS_OFF;
15393 connector->base.encoder = NULL;
15394 }
15395 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15396 connector->base.base.id,
c23cc417 15397 connector->base.name,
24929352
DV		 15398 connector->base.encoder ? "enabled" : "disabled");
15399 }
30e984df
DV		 15400}
15401
15402/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15403 * and i915 state tracking structures. */
15404void intel_modeset_setup_hw_state(struct drm_device *dev,
15405 bool force_restore)
15406{
15407 struct drm_i915_private *dev_priv = dev->dev_private;
15408 enum pipe pipe;
30e984df
DV		 15409 struct intel_crtc *crtc;
15410 struct intel_encoder *encoder;
35c95375 15411 int i;
30e984df
DV		 15412
15413 intel_modeset_readout_hw_state(dev);
24929352 15414
babea61d
JB		 15415 /*
15416 * Now that we have the config, copy it to each CRTC struct
15417 * Note that this could go away if we move to using crtc_config
15418 * checking everywhere.
15419 */
d3fcc808 15420 for_each_intel_crtc(dev, crtc) {
d330a953 15421 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15422 intel_mode_from_pipe_config(&crtc->base.mode,
15423 crtc->config);
babea61d
JB		 15424 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15425 crtc->base.base.id);
15426 drm_mode_debug_printmodeline(&crtc->base.mode);
15427 }
15428 }
15429
24929352 15430 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15431 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15432 intel_sanitize_encoder(encoder);
15433 }
15434
055e393f 15435 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15436 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15437 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15438 intel_dump_pipe_config(crtc, crtc->config,
15439 "[setup_hw_state]");
24929352 15440 }
9a935856 15441
d29b2f9d
ACO		 15442 intel_modeset_update_connector_atomic_state(dev);
15443
35c95375
DV		 15444 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15445 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15446
15447 if (!pll->on || pll->active)
15448 continue;
15449
15450 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15451
15452 pll->disable(dev_priv, pll);
15453 pll->on = false;
15454 }
15455
6eb1a681
VS		 15456 if (IS_CHERRYVIEW(dev))
15457 vlv_wm_get_hw_state(dev);
15458 else if (IS_GEN9(dev))
3078999f
PB		 15459 skl_wm_get_hw_state(dev);
15460 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15461 ilk_wm_get_hw_state(dev);
15462
45e2b5f6 15463 if (force_restore) {
7d0bc1ea
VS		 15464 i915_redisable_vga(dev);
15465
f30da187
DV		 15466 /*
15467 * We need to use raw interfaces for restoring state to avoid
15468 * checking (bogus) intermediate states.
15469 */
055e393f 15470 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15471 struct drm_crtc *crtc =
15472 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15473
83a57153 15474 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15475 }
15476 } else {
15477 intel_modeset_update_staged_output_state(dev);
15478 }
8af6cf88
DV		 15479
15480 intel_modeset_check_state(dev);
2c7111db
CW		 15481}
15482
15483void intel_modeset_gem_init(struct drm_device *dev)
15484{
92122789 15485 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15486 struct drm_crtc *c;
2ff8fde1 15487 struct drm_i915_gem_object *obj;
e0d6149b 15488 int ret;
484b41dd 15489
ae48434c
ID		 15490 mutex_lock(&dev->struct_mutex);
15491 intel_init_gt_powersave(dev);
15492 mutex_unlock(&dev->struct_mutex);
15493
92122789
JB		 15494 /*
15495 * There may be no VBT; and if the BIOS enabled SSC we can
15496 * just keep using it to avoid unnecessary flicker. Whereas if the
15497 * BIOS isn't using it, don't assume it will work even if the VBT
15498 * indicates as much.
15499 */
15500 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15501 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15502 DREF_SSC1_ENABLE);
15503
1833b134 15504 intel_modeset_init_hw(dev);
02e792fb
DV		 15505
15506 intel_setup_overlay(dev);
484b41dd
JB		 15507
15508 /*
15509 * Make sure any fbs we allocated at startup are properly
15510 * pinned & fenced. When we do the allocation it's too early
15511 * for this.
15512 */
70e1e0ec 15513 for_each_crtc(dev, c) {
2ff8fde1
MR		 15514 obj = intel_fb_obj(c->primary->fb);
15515 if (obj == NULL)
484b41dd
JB		 15516 continue;
15517
e0d6149b
TU		 15518 mutex_lock(&dev->struct_mutex);
15519 ret = intel_pin_and_fence_fb_obj(c->primary,
15520 c->primary->fb,
15521 c->primary->state,
91af127f 15522 NULL, NULL);
e0d6149b
TU		 15523 mutex_unlock(&dev->struct_mutex);
15524 if (ret) {
484b41dd
JB		 15525 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15526 to_intel_crtc(c)->pipe);
66e514c1
DA		 15527 drm_framebuffer_unreference(c->primary->fb);
15528 c->primary->fb = NULL;
36750f28 15529 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15530 update_state_fb(c->primary);
36750f28 15531 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15532 }
15533 }
0962c3c9
VS		 15534
15535 intel_backlight_register(dev);
79e53945
JB		 15536}
15537
4932e2c3
ID		 15538void intel_connector_unregister(struct intel_connector *intel_connector)
15539{
15540 struct drm_connector *connector = &intel_connector->base;
15541
15542 intel_panel_destroy_backlight(connector);
34ea3d38 15543 drm_connector_unregister(connector);
4932e2c3
ID		 15544}
15545
79e53945
JB		 15546void intel_modeset_cleanup(struct drm_device *dev)
15547{
652c393a 15548 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15549 struct drm_connector *connector;
652c393a 15550
2eb5252e
ID		 15551 intel_disable_gt_powersave(dev);
15552
0962c3c9
VS		 15553 intel_backlight_unregister(dev);
15554
fd0c0642
DV		 15555 /*
15556 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15557 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15558 * experience fancy races otherwise.
15559 */
2aeb7d3a 15560 intel_irq_uninstall(dev_priv);
eb21b92b 15561
fd0c0642
DV		 15562 /*
15563 * Due to the hpd irq storm handling the hotplug work can re-arm the
15564 * poll handlers. Hence disable polling after hpd handling is shut down.
15565 */
f87ea761 15566 drm_kms_helper_poll_fini(dev);
fd0c0642 15567
652c393a
JB		 15568 mutex_lock(&dev->struct_mutex);
15569
723bfd70
JB		 15570 intel_unregister_dsm_handler();
15571
7ff0ebcc 15572 intel_fbc_disable(dev);
e70236a8 15573
69341a5e
KH		 15574 mutex_unlock(&dev->struct_mutex);
15575
1630fe75
CW		 15576 /* flush any delayed tasks or pending work */
15577 flush_scheduled_work();
15578
db31af1d
JN		 15579 /* destroy the backlight and sysfs files before encoders/connectors */
15580 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15581 struct intel_connector *intel_connector;
15582
15583 intel_connector = to_intel_connector(connector);
15584 intel_connector->unregister(intel_connector);
db31af1d 15585 }
d9255d57 15586
79e53945 15587 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15588
15589 intel_cleanup_overlay(dev);
ae48434c
ID		 15590
15591 mutex_lock(&dev->struct_mutex);
15592 intel_cleanup_gt_powersave(dev);
15593 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15594}
15595
f1c79df3
ZW		 15596/*
15597 * Return which encoder is currently attached for connector.
15598 */
df0e9248 15599struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15600{
df0e9248
CW		 15601 return &intel_attached_encoder(connector)->base;
15602}
f1c79df3 15603
df0e9248
CW		 15604void intel_connector_attach_encoder(struct intel_connector *connector,
15605 struct intel_encoder *encoder)
15606{
15607 connector->encoder = encoder;
15608 drm_mode_connector_attach_encoder(&connector->base,
15609 &encoder->base);
79e53945 15610}
28d52043
DA		 15611
15612/*
15613 * set vga decode state - true == enable VGA decode
15614 */
15615int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15616{
15617 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15618 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15619 u16 gmch_ctrl;
15620
75fa041d
CW		 15621 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15622 DRM_ERROR("failed to read control word\n");
15623 return -EIO;
15624 }
15625
c0cc8a55
CW		 15626 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15627 return 0;
15628
28d52043
DA		 15629 if (state)
15630 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15631 else
15632 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15633
15634 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15635 DRM_ERROR("failed to write control word\n");
15636 return -EIO;
15637 }
15638
28d52043
DA		 15639 return 0;
15640}
c4a1d9e4 15641
c4a1d9e4 15642struct intel_display_error_state {
ff57f1b0
PZ		 15643
15644 u32 power_well_driver;
15645
63b66e5b
CW		 15646 int num_transcoders;
15647
c4a1d9e4
CW		 15648 struct intel_cursor_error_state {
15649 u32 control;
15650 u32 position;
15651 u32 base;
15652 u32 size;
52331309 15653 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15654
15655 struct intel_pipe_error_state {
ddf9c536 15656 bool power_domain_on;
c4a1d9e4 15657 u32 source;
f301b1e1 15658 u32 stat;
52331309 15659 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15660
15661 struct intel_plane_error_state {
15662 u32 control;
15663 u32 stride;
15664 u32 size;
15665 u32 pos;
15666 u32 addr;
15667 u32 surface;
15668 u32 tile_offset;
52331309 15669 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15670
15671 struct intel_transcoder_error_state {
ddf9c536 15672 bool power_domain_on;
63b66e5b
CW		 15673 enum transcoder cpu_transcoder;
15674
15675 u32 conf;
15676
15677 u32 htotal;
15678 u32 hblank;
15679 u32 hsync;
15680 u32 vtotal;
15681 u32 vblank;
15682 u32 vsync;
15683 } transcoder[4];
c4a1d9e4
CW		 15684};
15685
15686struct intel_display_error_state *
15687intel_display_capture_error_state(struct drm_device *dev)
15688{
fbee40df 15689 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15690 struct intel_display_error_state *error;
63b66e5b
CW		 15691 int transcoders[] = {
15692 TRANSCODER_A,
15693 TRANSCODER_B,
15694 TRANSCODER_C,
15695 TRANSCODER_EDP,
15696 };
c4a1d9e4
CW		 15697 int i;
15698
63b66e5b
CW		 15699 if (INTEL_INFO(dev)->num_pipes == 0)
15700 return NULL;
15701
9d1cb914 15702 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15703 if (error == NULL)
15704 return NULL;
15705
190be112 15706 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15707 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15708
055e393f 15709 for_each_pipe(dev_priv, i) {
ddf9c536 15710 error->pipe[i].power_domain_on =
f458ebbc
DV		 15711 __intel_display_power_is_enabled(dev_priv,
15712 POWER_DOMAIN_PIPE(i));
ddf9c536 15713 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15714 continue;
15715
5efb3e28
VS		 15716 error->cursor[i].control = I915_READ(CURCNTR(i));
15717 error->cursor[i].position = I915_READ(CURPOS(i));
15718 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15719
15720 error->plane[i].control = I915_READ(DSPCNTR(i));
15721 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15722 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15723 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15724 error->plane[i].pos = I915_READ(DSPPOS(i));
15725 }
ca291363
PZ		 15726 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15727 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15728 if (INTEL_INFO(dev)->gen >= 4) {
15729 error->plane[i].surface = I915_READ(DSPSURF(i));
15730 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15731 }
15732
c4a1d9e4 15733 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15734
3abfce77 15735 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15736 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15737 }
15738
15739 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15740 if (HAS_DDI(dev_priv->dev))
15741 error->num_transcoders++; /* Account for eDP. */
15742
15743 for (i = 0; i < error->num_transcoders; i++) {
15744 enum transcoder cpu_transcoder = transcoders[i];
15745
ddf9c536 15746 error->transcoder[i].power_domain_on =
f458ebbc 15747 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15748 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15749 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15750 continue;
15751
63b66e5b
CW		 15752 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15753
15754 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15755 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15756 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15757 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15758 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15759 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15760 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15761 }
15762
15763 return error;
15764}
15765
edc3d884
MK		 15766#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15767
c4a1d9e4 15768void
edc3d884 15769intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15770 struct drm_device *dev,
15771 struct intel_display_error_state *error)
15772{
055e393f 15773 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15774 int i;
15775
63b66e5b
CW		 15776 if (!error)
15777 return;
15778
edc3d884 15779 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15780 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15781 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15782 error->power_well_driver);
055e393f 15783 for_each_pipe(dev_priv, i) {
edc3d884 15784 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15785 err_printf(m, " Power: %s\n",
15786 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15787 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15788 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15789
15790 err_printf(m, "Plane [%d]:\n", i);
15791 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15792 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15793 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15794 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15795 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15796 }
4b71a570 15797 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15798 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15799 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15800 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15801 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15802 }
15803
edc3d884
MK		 15804 err_printf(m, "Cursor [%d]:\n", i);
15805 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15806 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15807 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15808 }
63b66e5b
CW		 15809
15810 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15811 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15812 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15813 err_printf(m, " Power: %s\n",
15814 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15815 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15816 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15817 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15818 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15819 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15820 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15821 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15822 }
c4a1d9e4 15823}
e2fcdaa9
VS		 15824
15825void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15826{
15827 struct intel_crtc *crtc;
15828
15829 for_each_intel_crtc(dev, crtc) {
15830 struct intel_unpin_work *work;
e2fcdaa9 15831
5e2d7afc 15832 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15833
15834 work = crtc->unpin_work;
15835
15836 if (work && work->event &&
15837 work->event->base.file_priv == file) {
15838 kfree(work->event);
15839 work->event = NULL;
15840 }
15841
5e2d7afc 15842 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15843 }
15844}
Linux kernel - Deliverables
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