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drm/i915: Use full atomic modeset.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
eb1bfe80
JB		 89static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
5b18e57c
DV		 93static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
94static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 95static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 96 struct intel_link_m_n *m_n,
97 struct intel_link_m_n *m2_n2);
29407aab 98static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 99static void haswell_set_pipeconf(struct drm_crtc *crtc);
100static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 101static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 102 const struct intel_crtc_state *pipe_config);
d288f65f 103static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 105static void intel_begin_crtc_commit(struct drm_crtc *crtc);
106static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 107static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
108 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 109static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
110 int num_connectors);
043e9bda 111static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 112
79e53945 113typedef struct {
0206e353 114 int min, max;
79e53945
JB		 115} intel_range_t;
116
117typedef struct {
0206e353
AJ		 118 int dot_limit;
119 int p2_slow, p2_fast;
79e53945
JB		 120} intel_p2_t;
121
d4906093
ML		 122typedef struct intel_limit intel_limit_t;
123struct intel_limit {
0206e353
AJ		 124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
d4906093 126};
79e53945 127
d2acd215
DV		 128int
129intel_pch_rawclk(struct drm_device *dev)
130{
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136}
137
021357ac
CW		 138static inline u32 /* units of 100MHz */
139intel_fdi_link_freq(struct drm_device *dev)
140{
8b99e68c
CW		 141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
021357ac
CW		 146}
147
5d536e28 148static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 149 .dot = { .min = 25000, .max = 350000 },
9c333719 150 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 151 .n = { .min = 2, .max = 16 },
0206e353
AJ		 152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 159};
160
5d536e28
DV		 161static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
9c333719 163 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 164 .n = { .min = 2, .max = 16 },
5d536e28
DV		 165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172};
173
e4b36699 174static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 175 .dot = { .min = 25000, .max = 350000 },
9c333719 176 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 177 .n = { .min = 2, .max = 16 },
0206e353
AJ		 178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
e4b36699 185};
273e27ca 186
e4b36699 187static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 211};
212
273e27ca 213
e4b36699 214static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
044c7c41 226 },
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
044c7c41 253 },
e4b36699
KP		 254};
255
256static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
044c7c41 267 },
e4b36699
KP		 268};
269
f2b115e6 270static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 273 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
273e27ca 276 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 283};
284
f2b115e6 285static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 296};
297
273e27ca
EA		 298/* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
b91ad0ec 303static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 314};
315
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327};
328
329static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 340};
341
273e27ca 342/* LVDS 100mhz refclk limits. */
b91ad0ec 343static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
0206e353 351 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 354};
355
356static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
0206e353 364 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 367};
368
dc730512 369static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 377 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 378 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
b99ab663 381 .p1 = { .min = 2, .max = 3 },
5fdc9c49 382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 383};
384
ef9348c8
CML		 385static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 393 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399};
400
5ab7b0b7
ID		 401static const intel_limit_t intel_limits_bxt = {
402 /* FIXME: find real dot limits */
403 .dot = { .min = 0, .max = INT_MAX },
e6292556 404 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 /* FIXME: find real m2 limits */
408 .m2 = { .min = 2 << 22, .max = 255 << 22 },
409 .p1 = { .min = 2, .max = 4 },
410 .p2 = { .p2_slow = 1, .p2_fast = 20 },
411};
412
cdba954e
ACO		 413static bool
414needs_modeset(struct drm_crtc_state *state)
415{
416 return state->mode_changed || state->active_changed;
417}
418
e0638cdf
PZ		 419/**
420 * Returns whether any output on the specified pipe is of the specified type
421 */
4093561b 422bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 423{
409ee761 424 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 425 struct intel_encoder *encoder;
426
409ee761 427 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 428 if (encoder->type == type)
429 return true;
430
431 return false;
432}
433
d0737e1d
ACO		 434/**
435 * Returns whether any output on the specified pipe will have the specified
436 * type after a staged modeset is complete, i.e., the same as
437 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
438 * encoder->crtc.
439 */
a93e255f
ACO		 440static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
441 int type)
d0737e1d 442{
a93e255f 443 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 444 struct drm_connector *connector;
a93e255f 445 struct drm_connector_state *connector_state;
d0737e1d 446 struct intel_encoder *encoder;
a93e255f
ACO		 447 int i, num_connectors = 0;
448
da3ced29 449 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 450 if (connector_state->crtc != crtc_state->base.crtc)
451 continue;
452
453 num_connectors++;
d0737e1d 454
a93e255f
ACO		 455 encoder = to_intel_encoder(connector_state->best_encoder);
456 if (encoder->type == type)
d0737e1d 457 return true;
a93e255f
ACO		 458 }
459
460 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 461
462 return false;
463}
464
a93e255f
ACO		 465static const intel_limit_t *
466intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 467{
a93e255f 468 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 469 const intel_limit_t *limit;
b91ad0ec 470
a93e255f 471 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 472 if (intel_is_dual_link_lvds(dev)) {
1b894b59 473 if (refclk == 100000)
b91ad0ec
ZW		 474 limit = &intel_limits_ironlake_dual_lvds_100m;
475 else
476 limit = &intel_limits_ironlake_dual_lvds;
477 } else {
1b894b59 478 if (refclk == 100000)
b91ad0ec
ZW		 479 limit = &intel_limits_ironlake_single_lvds_100m;
480 else
481 limit = &intel_limits_ironlake_single_lvds;
482 }
c6bb3538 483 } else
b91ad0ec 484 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 485
486 return limit;
487}
488
a93e255f
ACO		 489static const intel_limit_t *
490intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 491{
a93e255f 492 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 493 const intel_limit_t *limit;
494
a93e255f 495 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 496 if (intel_is_dual_link_lvds(dev))
e4b36699 497 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 498 else
e4b36699 499 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 500 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
501 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 502 limit = &intel_limits_g4x_hdmi;
a93e255f 503 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 504 limit = &intel_limits_g4x_sdvo;
044c7c41 505 } else /* The option is for other outputs */
e4b36699 506 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 507
508 return limit;
509}
510
a93e255f
ACO		 511static const intel_limit_t *
512intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 513{
a93e255f 514 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 515 const intel_limit_t *limit;
516
5ab7b0b7
ID		 517 if (IS_BROXTON(dev))
518 limit = &intel_limits_bxt;
519 else if (HAS_PCH_SPLIT(dev))
a93e255f 520 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 521 else if (IS_G4X(dev)) {
a93e255f 522 limit = intel_g4x_limit(crtc_state);
f2b115e6 523 } else if (IS_PINEVIEW(dev)) {
a93e255f 524 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 525 limit = &intel_limits_pineview_lvds;
2177832f 526 else
f2b115e6 527 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 528 } else if (IS_CHERRYVIEW(dev)) {
529 limit = &intel_limits_chv;
a0c4da24 530 } else if (IS_VALLEYVIEW(dev)) {
dc730512 531 limit = &intel_limits_vlv;
a6c45cf0 532 } else if (!IS_GEN2(dev)) {
a93e255f 533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 534 limit = &intel_limits_i9xx_lvds;
535 else
536 limit = &intel_limits_i9xx_sdvo;
79e53945 537 } else {
a93e255f 538 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 539 limit = &intel_limits_i8xx_lvds;
a93e255f 540 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 541 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 542 else
543 limit = &intel_limits_i8xx_dac;
79e53945
JB		 544 }
545 return limit;
546}
547
dccbea3b
ID		 548/*
549 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
550 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
551 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
552 * The helpers' return value is the rate of the clock that is fed to the
553 * display engine's pipe which can be the above fast dot clock rate or a
554 * divided-down version of it.
555 */
f2b115e6 556/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 557static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 558{
2177832f
SL		 559 clock->m = clock->m2 + 2;
560 clock->p = clock->p1 * clock->p2;
ed5ca77e 561 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 562 return 0;
fb03ac01
VS		 563 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
564 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 565
566 return clock->dot;
2177832f
SL		 567}
568
7429e9d4
DV		 569static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
570{
571 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
572}
573
dccbea3b 574static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 575{
7429e9d4 576 clock->m = i9xx_dpll_compute_m(clock);
79e53945 577 clock->p = clock->p1 * clock->p2;
ed5ca77e 578 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 579 return 0;
fb03ac01
VS		 580 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
581 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 582
583 return clock->dot;
79e53945
JB		 584}
585
dccbea3b 586static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 587{
588 clock->m = clock->m1 * clock->m2;
589 clock->p = clock->p1 * clock->p2;
590 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 591 return 0;
589eca67
ID		 592 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 594
595 return clock->dot / 5;
589eca67
ID		 596}
597
dccbea3b 598int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 599{
600 clock->m = clock->m1 * clock->m2;
601 clock->p = clock->p1 * clock->p2;
602 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 603 return 0;
ef9348c8
CML		 604 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
605 clock->n << 22);
606 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 607
608 return clock->dot / 5;
ef9348c8
CML		 609}
610
7c04d1d9 611#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 612/**
613 * Returns whether the given set of divisors are valid for a given refclk with
614 * the given connectors.
615 */
616
1b894b59
CW		 617static bool intel_PLL_is_valid(struct drm_device *dev,
618 const intel_limit_t *limit,
619 const intel_clock_t *clock)
79e53945 620{
f01b7962
VS		 621 if (clock->n < limit->n.min || limit->n.max < clock->n)
622 INTELPllInvalid("n out of range\n");
79e53945 623 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 624 INTELPllInvalid("p1 out of range\n");
79e53945 625 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 626 INTELPllInvalid("m2 out of range\n");
79e53945 627 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 628 INTELPllInvalid("m1 out of range\n");
f01b7962 629
5ab7b0b7 630 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 631 if (clock->m1 <= clock->m2)
632 INTELPllInvalid("m1 <= m2\n");
633
5ab7b0b7 634 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 635 if (clock->p < limit->p.min || limit->p.max < clock->p)
636 INTELPllInvalid("p out of range\n");
637 if (clock->m < limit->m.min || limit->m.max < clock->m)
638 INTELPllInvalid("m out of range\n");
639 }
640
79e53945 641 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 642 INTELPllInvalid("vco out of range\n");
79e53945
JB		 643 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
644 * connector, etc., rather than just a single range.
645 */
646 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 647 INTELPllInvalid("dot out of range\n");
79e53945
JB		 648
649 return true;
650}
651
3b1429d9
VS		 652static int
653i9xx_select_p2_div(const intel_limit_t *limit,
654 const struct intel_crtc_state *crtc_state,
655 int target)
79e53945 656{
3b1429d9 657 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 658
a93e255f 659 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 660 /*
a210b028
DV		 661 * For LVDS just rely on its current settings for dual-channel.
662 * We haven't figured out how to reliably set up different
663 * single/dual channel state, if we even can.
79e53945 664 */
1974cad0 665 if (intel_is_dual_link_lvds(dev))
3b1429d9 666 return limit->p2.p2_fast;
79e53945 667 else
3b1429d9 668 return limit->p2.p2_slow;
79e53945
JB		 669 } else {
670 if (target < limit->p2.dot_limit)
3b1429d9 671 return limit->p2.p2_slow;
79e53945 672 else
3b1429d9 673 return limit->p2.p2_fast;
79e53945 674 }
3b1429d9
VS		 675}
676
677static bool
678i9xx_find_best_dpll(const intel_limit_t *limit,
679 struct intel_crtc_state *crtc_state,
680 int target, int refclk, intel_clock_t *match_clock,
681 intel_clock_t *best_clock)
682{
683 struct drm_device *dev = crtc_state->base.crtc->dev;
684 intel_clock_t clock;
685 int err = target;
79e53945 686
0206e353 687 memset(best_clock, 0, sizeof(*best_clock));
79e53945 688
3b1429d9
VS		 689 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
690
42158660
ZY		 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 695 if (clock.m2 >= clock.m1)
42158660
ZY		 696 break;
697 for (clock.n = limit->n.min;
698 clock.n <= limit->n.max; clock.n++) {
699 for (clock.p1 = limit->p1.min;
700 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 701 int this_err;
702
dccbea3b 703 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 704 if (!intel_PLL_is_valid(dev, limit,
705 &clock))
706 continue;
707 if (match_clock &&
708 clock.p != match_clock->p)
709 continue;
710
711 this_err = abs(clock.dot - target);
712 if (this_err < err) {
713 *best_clock = clock;
714 err = this_err;
715 }
716 }
717 }
718 }
719 }
720
721 return (err != target);
722}
723
724static bool
a93e255f
ACO		 725pnv_find_best_dpll(const intel_limit_t *limit,
726 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 727 int target, int refclk, intel_clock_t *match_clock,
728 intel_clock_t *best_clock)
79e53945 729{
3b1429d9 730 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 731 intel_clock_t clock;
79e53945
JB		 732 int err = target;
733
0206e353 734 memset(best_clock, 0, sizeof(*best_clock));
79e53945 735
3b1429d9
VS		 736 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
737
42158660
ZY		 738 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
739 clock.m1++) {
740 for (clock.m2 = limit->m2.min;
741 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 742 for (clock.n = limit->n.min;
743 clock.n <= limit->n.max; clock.n++) {
744 for (clock.p1 = limit->p1.min;
745 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 746 int this_err;
747
dccbea3b 748 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
79e53945 751 continue;
cec2f356
SP		 752 if (match_clock &&
753 clock.p != match_clock->p)
754 continue;
79e53945
JB		 755
756 this_err = abs(clock.dot - target);
757 if (this_err < err) {
758 *best_clock = clock;
759 err = this_err;
760 }
761 }
762 }
763 }
764 }
765
766 return (err != target);
767}
768
d4906093 769static bool
a93e255f
ACO		 770g4x_find_best_dpll(const intel_limit_t *limit,
771 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 772 int target, int refclk, intel_clock_t *match_clock,
773 intel_clock_t *best_clock)
d4906093 774{
3b1429d9 775 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 776 intel_clock_t clock;
777 int max_n;
3b1429d9 778 bool found = false;
6ba770dc
AJ		 779 /* approximately equals target * 0.00585 */
780 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 781
782 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
d4906093 786 max_n = limit->n.max;
f77f13e2 787 /* based on hardware requirement, prefer smaller n to precision */
d4906093 788 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 789 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 790 for (clock.m1 = limit->m1.max;
791 clock.m1 >= limit->m1.min; clock.m1--) {
792 for (clock.m2 = limit->m2.max;
793 clock.m2 >= limit->m2.min; clock.m2--) {
794 for (clock.p1 = limit->p1.max;
795 clock.p1 >= limit->p1.min; clock.p1--) {
796 int this_err;
797
dccbea3b 798 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 799 if (!intel_PLL_is_valid(dev, limit,
800 &clock))
d4906093 801 continue;
1b894b59
CW		 802
803 this_err = abs(clock.dot - target);
d4906093
ML		 804 if (this_err < err_most) {
805 *best_clock = clock;
806 err_most = this_err;
807 max_n = clock.n;
808 found = true;
809 }
810 }
811 }
812 }
813 }
2c07245f
ZW		 814 return found;
815}
816
d5dd62bd
ID		 817/*
818 * Check if the calculated PLL configuration is more optimal compared to the
819 * best configuration and error found so far. Return the calculated error.
820 */
821static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
822 const intel_clock_t *calculated_clock,
823 const intel_clock_t *best_clock,
824 unsigned int best_error_ppm,
825 unsigned int *error_ppm)
826{
9ca3ba01
ID		 827 /*
828 * For CHV ignore the error and consider only the P value.
829 * Prefer a bigger P value based on HW requirements.
830 */
831 if (IS_CHERRYVIEW(dev)) {
832 *error_ppm = 0;
833
834 return calculated_clock->p > best_clock->p;
835 }
836
24be4e46
ID		 837 if (WARN_ON_ONCE(!target_freq))
838 return false;
839
d5dd62bd
ID		 840 *error_ppm = div_u64(1000000ULL *
841 abs(target_freq - calculated_clock->dot),
842 target_freq);
843 /*
844 * Prefer a better P value over a better (smaller) error if the error
845 * is small. Ensure this preference for future configurations too by
846 * setting the error to 0.
847 */
848 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
849 *error_ppm = 0;
850
851 return true;
852 }
853
854 return *error_ppm + 10 < best_error_ppm;
855}
856
a0c4da24 857static bool
a93e255f
ACO		 858vlv_find_best_dpll(const intel_limit_t *limit,
859 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 860 int target, int refclk, intel_clock_t *match_clock,
861 intel_clock_t *best_clock)
a0c4da24 862{
a93e255f 863 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 864 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 865 intel_clock_t clock;
69e4f900 866 unsigned int bestppm = 1000000;
27e639bf
VS		 867 /* min update 19.2 MHz */
868 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 869 bool found = false;
a0c4da24 870
6b4bf1c4
VS		 871 target *= 5; /* fast clock */
872
873 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 874
875 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 876 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 877 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 878 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 879 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 880 clock.p = clock.p1 * clock.p2;
a0c4da24 881 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 882 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 883 unsigned int ppm;
69e4f900 884
6b4bf1c4
VS		 885 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
886 refclk * clock.m1);
887
dccbea3b 888 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 889
f01b7962
VS		 890 if (!intel_PLL_is_valid(dev, limit,
891 &clock))
43b0ac53
VS		 892 continue;
893
d5dd62bd
ID		 894 if (!vlv_PLL_is_optimal(dev, target,
895 &clock,
896 best_clock,
897 bestppm, &ppm))
898 continue;
6b4bf1c4 899
d5dd62bd
ID		 900 *best_clock = clock;
901 bestppm = ppm;
902 found = true;
a0c4da24
JB		 903 }
904 }
905 }
906 }
a0c4da24 907
49e497ef 908 return found;
a0c4da24 909}
a4fc5ed6 910
ef9348c8 911static bool
a93e255f
ACO		 912chv_find_best_dpll(const intel_limit_t *limit,
913 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 914 int target, int refclk, intel_clock_t *match_clock,
915 intel_clock_t *best_clock)
916{
a93e255f 917 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 918 struct drm_device *dev = crtc->base.dev;
9ca3ba01 919 unsigned int best_error_ppm;
ef9348c8
CML		 920 intel_clock_t clock;
921 uint64_t m2;
922 int found = false;
923
924 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 925 best_error_ppm = 1000000;
ef9348c8
CML		 926
927 /*
928 * Based on hardware doc, the n always set to 1, and m1 always
929 * set to 2. If requires to support 200Mhz refclk, we need to
930 * revisit this because n may not 1 anymore.
931 */
932 clock.n = 1, clock.m1 = 2;
933 target *= 5; /* fast clock */
934
935 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
936 for (clock.p2 = limit->p2.p2_fast;
937 clock.p2 >= limit->p2.p2_slow;
938 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 939 unsigned int error_ppm;
ef9348c8
CML		 940
941 clock.p = clock.p1 * clock.p2;
942
943 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
944 clock.n) << 22, refclk * clock.m1);
945
946 if (m2 > INT_MAX/clock.m1)
947 continue;
948
949 clock.m2 = m2;
950
dccbea3b 951 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 952
953 if (!intel_PLL_is_valid(dev, limit, &clock))
954 continue;
955
9ca3ba01
ID		 956 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
957 best_error_ppm, &error_ppm))
958 continue;
959
960 *best_clock = clock;
961 best_error_ppm = error_ppm;
962 found = true;
ef9348c8
CML		 963 }
964 }
965
966 return found;
967}
968
5ab7b0b7
ID		 969bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
970 intel_clock_t *best_clock)
971{
972 int refclk = i9xx_get_refclk(crtc_state, 0);
973
974 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
975 target_clock, refclk, NULL, best_clock);
976}
977
20ddf665
VS		 978bool intel_crtc_active(struct drm_crtc *crtc)
979{
980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
981
982 /* Be paranoid as we can arrive here with only partial
983 * state retrieved from the hardware during setup.
984 *
241bfc38 985 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 986 * as Haswell has gained clock readout/fastboot support.
987 *
66e514c1 988 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 989 * properly reconstruct framebuffers.
c3d1f436
MR		 990 *
991 * FIXME: The intel_crtc->active here should be switched to
992 * crtc->state->active once we have proper CRTC states wired up
993 * for atomic.
20ddf665 994 */
c3d1f436 995 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 996 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 997}
998
a5c961d1
PZ		 999enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1000 enum pipe pipe)
1001{
1002 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1004
6e3c9717 1005 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1006}
1007
fbf49ea2
VS		 1008static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1009{
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 u32 reg = PIPEDSL(pipe);
1012 u32 line1, line2;
1013 u32 line_mask;
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1021 msleep(5);
fbf49ea2
VS		 1022 line2 = I915_READ(reg) & line_mask;
1023
1024 return line1 == line2;
1025}
1026
ab7ad7f6
KP		 1027/*
1028 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1029 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1030 *
1031 * After disabling a pipe, we can't wait for vblank in the usual way,
1032 * spinning on the vblank interrupt status bit, since we won't actually
1033 * see an interrupt when the pipe is disabled.
1034 *
ab7ad7f6
KP		 1035 * On Gen4 and above:
1036 * wait for the pipe register state bit to turn off
1037 *
1038 * Otherwise:
1039 * wait for the display line value to settle (it usually
1040 * ends up stopping at the start of the next frame).
58e10eb9 1041 *
9d0498a2 1042 */
575f7ab7 1043static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1044{
575f7ab7 1045 struct drm_device *dev = crtc->base.dev;
9d0498a2 1046 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1048 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1049
1050 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1051 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1052
1053 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1054 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1055 100))
284637d9 1056 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1057 } else {
ab7ad7f6 1058 /* Wait for the display line to settle */
fbf49ea2 1059 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1060 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1061 }
79e53945
JB		 1062}
1063
b0ea7d37
DL		 1064/*
1065 * ibx_digital_port_connected - is the specified port connected?
1066 * @dev_priv: i915 private structure
1067 * @port: the port to test
1068 *
1069 * Returns true if @port is connected, false otherwise.
1070 */
1071bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1072 struct intel_digital_port *port)
1073{
1074 u32 bit;
1075
c36346e3 1076 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1077 switch (port->port) {
c36346e3
DL		 1078 case PORT_B:
1079 bit = SDE_PORTB_HOTPLUG;
1080 break;
1081 case PORT_C:
1082 bit = SDE_PORTC_HOTPLUG;
1083 break;
1084 case PORT_D:
1085 bit = SDE_PORTD_HOTPLUG;
1086 break;
1087 default:
1088 return true;
1089 }
1090 } else {
eba905b2 1091 switch (port->port) {
c36346e3
DL		 1092 case PORT_B:
1093 bit = SDE_PORTB_HOTPLUG_CPT;
1094 break;
1095 case PORT_C:
1096 bit = SDE_PORTC_HOTPLUG_CPT;
1097 break;
1098 case PORT_D:
1099 bit = SDE_PORTD_HOTPLUG_CPT;
1100 break;
1101 default:
1102 return true;
1103 }
b0ea7d37
DL		 1104 }
1105
1106 return I915_READ(SDEISR) & bit;
1107}
1108
b24e7179
JB		 1109static const char *state_string(bool enabled)
1110{
1111 return enabled ? "on" : "off";
1112}
1113
1114/* Only for pre-ILK configs */
55607e8a
DV		 1115void assert_pll(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
b24e7179
JB		 1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
1121
1122 reg = DPLL(pipe);
1123 val = I915_READ(reg);
1124 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1125 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1126 "PLL state assertion failure (expected %s, current %s)\n",
1127 state_string(state), state_string(cur_state));
1128}
b24e7179 1129
23538ef1
JN		 1130/* XXX: the dsi pll is shared between MIPI DSI ports */
1131static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1132{
1133 u32 val;
1134 bool cur_state;
1135
a580516d 1136 mutex_lock(&dev_priv->sb_lock);
23538ef1 1137 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1138 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1139
1140 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1141 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1142 "DSI PLL state assertion failure (expected %s, current %s)\n",
1143 state_string(state), state_string(cur_state));
1144}
1145#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1146#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1147
55607e8a 1148struct intel_shared_dpll *
e2b78267
DV		 1149intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1150{
1151 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1152
6e3c9717 1153 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1154 return NULL;
1155
6e3c9717 1156 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1157}
1158
040484af 1159/* For ILK+ */
55607e8a
DV		 1160void assert_shared_dpll(struct drm_i915_private *dev_priv,
1161 struct intel_shared_dpll *pll,
1162 bool state)
040484af 1163{
040484af 1164 bool cur_state;
5358901f 1165 struct intel_dpll_hw_state hw_state;
040484af 1166
92b27b08 1167 if (WARN (!pll,
46edb027 1168 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1169 return;
ee7b9f93 1170
5358901f 1171 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1172 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1173 "%s assertion failure (expected %s, current %s)\n",
1174 pll->name, state_string(state), state_string(cur_state));
040484af 1175}
040484af
JB		 1176
1177static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1179{
1180 int reg;
1181 u32 val;
1182 bool cur_state;
ad80a810
PZ		 1183 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1184 pipe);
040484af 1185
affa9354
PZ		 1186 if (HAS_DDI(dev_priv->dev)) {
1187 /* DDI does not have a specific FDI_TX register */
ad80a810 1188 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1189 val = I915_READ(reg);
ad80a810 1190 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1191 } else {
1192 reg = FDI_TX_CTL(pipe);
1193 val = I915_READ(reg);
1194 cur_state = !!(val & FDI_TX_ENABLE);
1195 }
e2c719b7 1196 I915_STATE_WARN(cur_state != state,
040484af
JB		 1197 "FDI TX state assertion failure (expected %s, current %s)\n",
1198 state_string(state), state_string(cur_state));
1199}
1200#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1201#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1202
1203static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1205{
1206 int reg;
1207 u32 val;
1208 bool cur_state;
1209
d63fa0dc
PZ		 1210 reg = FDI_RX_CTL(pipe);
1211 val = I915_READ(reg);
1212 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1213 I915_STATE_WARN(cur_state != state,
040484af
JB		 1214 "FDI RX state assertion failure (expected %s, current %s)\n",
1215 state_string(state), state_string(cur_state));
1216}
1217#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1218#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1219
1220static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe)
1222{
1223 int reg;
1224 u32 val;
1225
1226 /* ILK FDI PLL is always enabled */
3d13ef2e 1227 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1228 return;
1229
bf507ef7 1230 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1231 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1232 return;
1233
040484af
JB		 1234 reg = FDI_TX_CTL(pipe);
1235 val = I915_READ(reg);
e2c719b7 1236 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1237}
1238
55607e8a
DV		 1239void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
040484af
JB		 1241{
1242 int reg;
1243 u32 val;
55607e8a 1244 bool cur_state;
040484af
JB		 1245
1246 reg = FDI_RX_CTL(pipe);
1247 val = I915_READ(reg);
55607e8a 1248 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1249 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1250 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1251 state_string(state), state_string(cur_state));
040484af
JB		 1252}
1253
b680c37a
DV		 1254void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
ea0760cf 1256{
bedd4dba
JN		 1257 struct drm_device *dev = dev_priv->dev;
1258 int pp_reg;
ea0760cf
JB		 1259 u32 val;
1260 enum pipe panel_pipe = PIPE_A;
0de3b485 1261 bool locked = true;
ea0760cf 1262
bedd4dba
JN		 1263 if (WARN_ON(HAS_DDI(dev)))
1264 return;
1265
1266 if (HAS_PCH_SPLIT(dev)) {
1267 u32 port_sel;
1268
ea0760cf 1269 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1270 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1271
1272 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1273 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1274 panel_pipe = PIPE_B;
1275 /* XXX: else fix for eDP */
1276 } else if (IS_VALLEYVIEW(dev)) {
1277 /* presumably write lock depends on pipe, not port select */
1278 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1279 panel_pipe = pipe;
ea0760cf
JB		 1280 } else {
1281 pp_reg = PP_CONTROL;
bedd4dba
JN		 1282 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1283 panel_pipe = PIPE_B;
ea0760cf
JB		 1284 }
1285
1286 val = I915_READ(pp_reg);
1287 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1288 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1289 locked = false;
1290
e2c719b7 1291 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1292 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1293 pipe_name(pipe));
ea0760cf
JB		 1294}
1295
93ce0ba6
JN		 1296static void assert_cursor(struct drm_i915_private *dev_priv,
1297 enum pipe pipe, bool state)
1298{
1299 struct drm_device *dev = dev_priv->dev;
1300 bool cur_state;
1301
d9d82081 1302 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1303 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1304 else
5efb3e28 1305 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1306
e2c719b7 1307 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1308 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1309 pipe_name(pipe), state_string(state), state_string(cur_state));
1310}
1311#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1312#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1313
b840d907
JB		 1314void assert_pipe(struct drm_i915_private *dev_priv,
1315 enum pipe pipe, bool state)
b24e7179
JB		 1316{
1317 int reg;
1318 u32 val;
63d7bbe9 1319 bool cur_state;
702e7a56
PZ		 1320 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1321 pipe);
b24e7179 1322
b6b5d049
VS		 1323 /* if we need the pipe quirk it must be always on */
1324 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1325 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1326 state = true;
1327
f458ebbc 1328 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1329 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1330 cur_state = false;
1331 } else {
1332 reg = PIPECONF(cpu_transcoder);
1333 val = I915_READ(reg);
1334 cur_state = !!(val & PIPECONF_ENABLE);
1335 }
1336
e2c719b7 1337 I915_STATE_WARN(cur_state != state,
63d7bbe9 1338 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1339 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1340}
1341
931872fc
CW		 1342static void assert_plane(struct drm_i915_private *dev_priv,
1343 enum plane plane, bool state)
b24e7179
JB		 1344{
1345 int reg;
1346 u32 val;
931872fc 1347 bool cur_state;
b24e7179
JB		 1348
1349 reg = DSPCNTR(plane);
1350 val = I915_READ(reg);
931872fc 1351 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1352 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1353 "plane %c assertion failure (expected %s, current %s)\n",
1354 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1355}
1356
931872fc
CW		 1357#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1358#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1359
b24e7179
JB		 1360static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1361 enum pipe pipe)
1362{
653e1026 1363 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1364 int reg, i;
1365 u32 val;
1366 int cur_pipe;
1367
653e1026
VS		 1368 /* Primary planes are fixed to pipes on gen4+ */
1369 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1370 reg = DSPCNTR(pipe);
1371 val = I915_READ(reg);
e2c719b7 1372 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1373 "plane %c assertion failure, should be disabled but not\n",
1374 plane_name(pipe));
19ec1358 1375 return;
28c05794 1376 }
19ec1358 1377
b24e7179 1378 /* Need to check both planes against the pipe */
055e393f 1379 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1380 reg = DSPCNTR(i);
1381 val = I915_READ(reg);
1382 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1383 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1384 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1385 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1386 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1387 }
1388}
1389
19332d7a
JB		 1390static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1391 enum pipe pipe)
1392{
20674eef 1393 struct drm_device *dev = dev_priv->dev;
1fe47785 1394 int reg, sprite;
19332d7a
JB		 1395 u32 val;
1396
7feb8b88 1397 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1398 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1399 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1400 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1401 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1402 sprite, pipe_name(pipe));
1403 }
1404 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1406 reg = SPCNTR(pipe, sprite);
20674eef 1407 val = I915_READ(reg);
e2c719b7 1408 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1409 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1410 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1411 }
1412 } else if (INTEL_INFO(dev)->gen >= 7) {
1413 reg = SPRCTL(pipe);
19332d7a 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1417 plane_name(pipe), pipe_name(pipe));
1418 } else if (INTEL_INFO(dev)->gen >= 5) {
1419 reg = DVSCNTR(pipe);
19332d7a 1420 val = I915_READ(reg);
e2c719b7 1421 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1422 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1423 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1424 }
1425}
1426
08c71e5e
VS		 1427static void assert_vblank_disabled(struct drm_crtc *crtc)
1428{
e2c719b7 1429 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1430 drm_crtc_vblank_put(crtc);
1431}
1432
89eff4be 1433static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1434{
1435 u32 val;
1436 bool enabled;
1437
e2c719b7 1438 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1439
92f2584a
JB		 1440 val = I915_READ(PCH_DREF_CONTROL);
1441 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1442 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1443 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1444}
1445
ab9412ba
DV		 1446static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1447 enum pipe pipe)
92f2584a
JB		 1448{
1449 int reg;
1450 u32 val;
1451 bool enabled;
1452
ab9412ba 1453 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1454 val = I915_READ(reg);
1455 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1456 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1457 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1458 pipe_name(pipe));
92f2584a
JB		 1459}
1460
4e634389
KP		 1461static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1462 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1463{
1464 if ((val & DP_PORT_EN) == 0)
1465 return false;
1466
1467 if (HAS_PCH_CPT(dev_priv->dev)) {
1468 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1469 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1470 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1471 return false;
44f37d1f
CML		 1472 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1473 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1474 return false;
f0575e92
KP		 1475 } else {
1476 if ((val & DP_PIPE_MASK) != (pipe << 30))
1477 return false;
1478 }
1479 return true;
1480}
1481
1519b995
KP		 1482static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, u32 val)
1484{
dc0fa718 1485 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1486 return false;
1487
1488 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1489 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1490 return false;
44f37d1f
CML		 1491 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1493 return false;
1519b995 1494 } else {
dc0fa718 1495 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1496 return false;
1497 }
1498 return true;
1499}
1500
1501static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1502 enum pipe pipe, u32 val)
1503{
1504 if ((val & LVDS_PORT_EN) == 0)
1505 return false;
1506
1507 if (HAS_PCH_CPT(dev_priv->dev)) {
1508 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1509 return false;
1510 } else {
1511 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1512 return false;
1513 }
1514 return true;
1515}
1516
1517static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1518 enum pipe pipe, u32 val)
1519{
1520 if ((val & ADPA_DAC_ENABLE) == 0)
1521 return false;
1522 if (HAS_PCH_CPT(dev_priv->dev)) {
1523 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1524 return false;
1525 } else {
1526 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1527 return false;
1528 }
1529 return true;
1530}
1531
291906f1 1532static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1533 enum pipe pipe, int reg, u32 port_sel)
291906f1 1534{
47a05eca 1535 u32 val = I915_READ(reg);
e2c719b7 1536 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1537 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1538 reg, pipe_name(pipe));
de9a35ab 1539
e2c719b7 1540 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1541 && (val & DP_PIPEB_SELECT),
de9a35ab 1542 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1543}
1544
1545static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1546 enum pipe pipe, int reg)
1547{
47a05eca 1548 u32 val = I915_READ(reg);
e2c719b7 1549 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1550 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1551 reg, pipe_name(pipe));
de9a35ab 1552
e2c719b7 1553 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1554 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1555 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1556}
1557
1558static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1559 enum pipe pipe)
1560{
1561 int reg;
1562 u32 val;
291906f1 1563
f0575e92
KP		 1564 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1565 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1566 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1567
1568 reg = PCH_ADPA;
1569 val = I915_READ(reg);
e2c719b7 1570 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1571 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1572 pipe_name(pipe));
291906f1
JB		 1573
1574 reg = PCH_LVDS;
1575 val = I915_READ(reg);
e2c719b7 1576 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1577 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1578 pipe_name(pipe));
291906f1 1579
e2debe91
PZ		 1580 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1581 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1582 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1583}
1584
40e9cf64
JB		 1585static void intel_init_dpio(struct drm_device *dev)
1586{
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588
1589 if (!IS_VALLEYVIEW(dev))
1590 return;
1591
a09caddd
CML		 1592 /*
1593 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1594 * CHV x1 PHY (DP/HDMI D)
1595 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1596 */
1597 if (IS_CHERRYVIEW(dev)) {
1598 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1599 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1600 } else {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1602 }
5382f5f3
JB		 1603}
1604
d288f65f 1605static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1606 const struct intel_crtc_state *pipe_config)
87442f73 1607{
426115cf
DV		 1608 struct drm_device *dev = crtc->base.dev;
1609 struct drm_i915_private *dev_priv = dev->dev_private;
1610 int reg = DPLL(crtc->pipe);
d288f65f 1611 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1612
426115cf 1613 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1614
1615 /* No really, not for ILK+ */
1616 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1617
1618 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1619 if (IS_MOBILE(dev_priv->dev))
426115cf 1620 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1621
426115cf
DV		 1622 I915_WRITE(reg, dpll);
1623 POSTING_READ(reg);
1624 udelay(150);
1625
1626 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1627 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1628
d288f65f 1629 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1630 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1631
1632 /* We do this three times for luck */
426115cf 1633 I915_WRITE(reg, dpll);
87442f73
DV		 1634 POSTING_READ(reg);
1635 udelay(150); /* wait for warmup */
426115cf 1636 I915_WRITE(reg, dpll);
87442f73
DV		 1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
426115cf 1639 I915_WRITE(reg, dpll);
87442f73
DV		 1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
1642}
1643
d288f65f 1644static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1645 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1646{
1647 struct drm_device *dev = crtc->base.dev;
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 int pipe = crtc->pipe;
1650 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1651 u32 tmp;
1652
1653 assert_pipe_disabled(dev_priv, crtc->pipe);
1654
1655 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1656
a580516d 1657 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1658
1659 /* Enable back the 10bit clock to display controller */
1660 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1661 tmp |= DPIO_DCLKP_EN;
1662 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1663
54433e91
VS		 1664 mutex_unlock(&dev_priv->sb_lock);
1665
9d556c99
CML		 1666 /*
1667 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1668 */
1669 udelay(1);
1670
1671 /* Enable PLL */
d288f65f 1672 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1673
1674 /* Check PLL is locked */
a11b0703 1675 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1676 DRM_ERROR("PLL %d failed to lock\n", pipe);
1677
a11b0703 1678 /* not sure when this should be written */
d288f65f 1679 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1680 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1681}
1682
1c4e0274
VS		 1683static int intel_num_dvo_pipes(struct drm_device *dev)
1684{
1685 struct intel_crtc *crtc;
1686 int count = 0;
1687
1688 for_each_intel_crtc(dev, crtc)
3538b9df 1689 count += crtc->base.state->active &&
409ee761 1690 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1691
1692 return count;
1693}
1694
66e3d5c0 1695static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1696{
66e3d5c0
DV		 1697 struct drm_device *dev = crtc->base.dev;
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699 int reg = DPLL(crtc->pipe);
6e3c9717 1700 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1701
66e3d5c0 1702 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1703
63d7bbe9 1704 /* No really, not for ILK+ */
3d13ef2e 1705 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1706
1707 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1708 if (IS_MOBILE(dev) && !IS_I830(dev))
1709 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1710
1c4e0274
VS		 1711 /* Enable DVO 2x clock on both PLLs if necessary */
1712 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1713 /*
1714 * It appears to be important that we don't enable this
1715 * for the current pipe before otherwise configuring the
1716 * PLL. No idea how this should be handled if multiple
1717 * DVO outputs are enabled simultaneosly.
1718 */
1719 dpll |= DPLL_DVO_2X_MODE;
1720 I915_WRITE(DPLL(!crtc->pipe),
1721 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1722 }
66e3d5c0
DV		 1723
1724 /* Wait for the clocks to stabilize. */
1725 POSTING_READ(reg);
1726 udelay(150);
1727
1728 if (INTEL_INFO(dev)->gen >= 4) {
1729 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1730 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1731 } else {
1732 /* The pixel multiplier can only be updated once the
1733 * DPLL is enabled and the clocks are stable.
1734 *
1735 * So write it again.
1736 */
1737 I915_WRITE(reg, dpll);
1738 }
63d7bbe9
JB		 1739
1740 /* We do this three times for luck */
66e3d5c0 1741 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1742 POSTING_READ(reg);
1743 udelay(150); /* wait for warmup */
66e3d5c0 1744 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
66e3d5c0 1747 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750}
1751
1752/**
50b44a44 1753 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1754 * @dev_priv: i915 private structure
1755 * @pipe: pipe PLL to disable
1756 *
1757 * Disable the PLL for @pipe, making sure the pipe is off first.
1758 *
1759 * Note! This is for pre-ILK only.
1760 */
1c4e0274 1761static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1762{
1c4e0274
VS		 1763 struct drm_device *dev = crtc->base.dev;
1764 struct drm_i915_private *dev_priv = dev->dev_private;
1765 enum pipe pipe = crtc->pipe;
1766
1767 /* Disable DVO 2x clock on both PLLs if necessary */
1768 if (IS_I830(dev) &&
409ee761 1769 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1770 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1771 I915_WRITE(DPLL(PIPE_B),
1772 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1773 I915_WRITE(DPLL(PIPE_A),
1774 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1775 }
1776
b6b5d049
VS		 1777 /* Don't disable pipe or pipe PLLs if needed */
1778 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1779 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1780 return;
1781
1782 /* Make sure the pipe isn't still relying on us */
1783 assert_pipe_disabled(dev_priv, pipe);
1784
b8afb911 1785 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1786 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1787}
1788
f6071166
JB		 1789static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1790{
b8afb911 1791 u32 val;
f6071166
JB		 1792
1793 /* Make sure the pipe isn't still relying on us */
1794 assert_pipe_disabled(dev_priv, pipe);
1795
e5cbfbfb
ID		 1796 /*
1797 * Leave integrated clock source and reference clock enabled for pipe B.
1798 * The latter is needed for VGA hotplug / manual detection.
1799 */
b8afb911 1800 val = DPLL_VGA_MODE_DIS;
f6071166 1801 if (pipe == PIPE_B)
60bfe44f 1802 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1803 I915_WRITE(DPLL(pipe), val);
1804 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1805
1806}
1807
1808static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1809{
d752048d 1810 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1811 u32 val;
1812
a11b0703
VS		 1813 /* Make sure the pipe isn't still relying on us */
1814 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1815
a11b0703 1816 /* Set PLL en = 0 */
60bfe44f
VS		 1817 val = DPLL_SSC_REF_CLK_CHV |
1818 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1819 if (pipe != PIPE_A)
1820 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1821 I915_WRITE(DPLL(pipe), val);
1822 POSTING_READ(DPLL(pipe));
d752048d 1823
a580516d 1824 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1825
1826 /* Disable 10bit clock to display controller */
1827 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1828 val &= ~DPIO_DCLKP_EN;
1829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1830
61407f6d
VS		 1831 /* disable left/right clock distribution */
1832 if (pipe != PIPE_B) {
1833 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1834 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1835 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1836 } else {
1837 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1838 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1839 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1840 }
1841
a580516d 1842 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1843}
1844
e4607fcf 1845void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1846 struct intel_digital_port *dport,
1847 unsigned int expected_mask)
89b667f8
JB		 1848{
1849 u32 port_mask;
00fc31b7 1850 int dpll_reg;
89b667f8 1851
e4607fcf
CML		 1852 switch (dport->port) {
1853 case PORT_B:
89b667f8 1854 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1855 dpll_reg = DPLL(0);
e4607fcf
CML		 1856 break;
1857 case PORT_C:
89b667f8 1858 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1859 dpll_reg = DPLL(0);
9b6de0a1 1860 expected_mask <<= 4;
00fc31b7
CML		 1861 break;
1862 case PORT_D:
1863 port_mask = DPLL_PORTD_READY_MASK;
1864 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1865 break;
1866 default:
1867 BUG();
1868 }
89b667f8 1869
9b6de0a1
VS		 1870 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1871 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1872 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1873}
1874
b14b1055
DV		 1875static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1876{
1877 struct drm_device *dev = crtc->base.dev;
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1880
be19f0ff
CW		 1881 if (WARN_ON(pll == NULL))
1882 return;
1883
3e369b76 1884 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1885 if (pll->active == 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1887 WARN_ON(pll->on);
1888 assert_shared_dpll_disabled(dev_priv, pll);
1889
1890 pll->mode_set(dev_priv, pll);
1891 }
1892}
1893
92f2584a 1894/**
85b3894f 1895 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1898 *
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1901 */
85b3894f 1902static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1903{
3d13ef2e
DL		 1904 struct drm_device *dev = crtc->base.dev;
1905 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1906 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1907
87a875bb 1908 if (WARN_ON(pll == NULL))
48da64a8
CW		 1909 return;
1910
3e369b76 1911 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1912 return;
ee7b9f93 1913
74dd6928 1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1915 pll->name, pll->active, pll->on,
e2b78267 1916 crtc->base.base.id);
92f2584a 1917
cdbd2316
DV		 1918 if (pll->active++) {
1919 WARN_ON(!pll->on);
e9d6944e 1920 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1921 return;
1922 }
f4a091c7 1923 WARN_ON(pll->on);
ee7b9f93 1924
bd2bb1b9
PZ		 1925 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1926
46edb027 1927 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1928 pll->enable(dev_priv, pll);
ee7b9f93 1929 pll->on = true;
92f2584a
JB		 1930}
1931
f6daaec2 1932static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1933{
3d13ef2e
DL		 1934 struct drm_device *dev = crtc->base.dev;
1935 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1936 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1937
92f2584a 1938 /* PCH only available on ILK+ */
3d13ef2e 1939 BUG_ON(INTEL_INFO(dev)->gen < 5);
eddfcbcd
ML		 1940 if (pll == NULL)
1941 return;
92f2584a 1942
eddfcbcd 1943 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1944 return;
7a419866 1945
46edb027
DV		 1946 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1947 pll->name, pll->active, pll->on,
e2b78267 1948 crtc->base.base.id);
7a419866 1949
48da64a8 1950 if (WARN_ON(pll->active == 0)) {
e9d6944e 1951 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1952 return;
1953 }
1954
e9d6944e 1955 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1956 WARN_ON(!pll->on);
cdbd2316 1957 if (--pll->active)
7a419866 1958 return;
ee7b9f93 1959
46edb027 1960 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1961 pll->disable(dev_priv, pll);
ee7b9f93 1962 pll->on = false;
bd2bb1b9
PZ		 1963
1964 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1965}
1966
b8a4f404
PZ		 1967static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1968 enum pipe pipe)
040484af 1969{
23670b32 1970 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1971 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1973 uint32_t reg, val, pipeconf_val;
040484af
JB		 1974
1975 /* PCH only available on ILK+ */
55522f37 1976 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1977
1978 /* Make sure PCH DPLL is enabled */
e72f9fbf 1979 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1980 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1981
1982 /* FDI must be feeding us bits for PCH ports */
1983 assert_fdi_tx_enabled(dev_priv, pipe);
1984 assert_fdi_rx_enabled(dev_priv, pipe);
1985
23670b32
DV		 1986 if (HAS_PCH_CPT(dev)) {
1987 /* Workaround: Set the timing override bit before enabling the
1988 * pch transcoder. */
1989 reg = TRANS_CHICKEN2(pipe);
1990 val = I915_READ(reg);
1991 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1992 I915_WRITE(reg, val);
59c859d6 1993 }
23670b32 1994
ab9412ba 1995 reg = PCH_TRANSCONF(pipe);
040484af 1996 val = I915_READ(reg);
5f7f726d 1997 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1998
1999 if (HAS_PCH_IBX(dev_priv->dev)) {
2000 /*
c5de7c6f
VS		 2001 * Make the BPC in transcoder be consistent with
2002 * that in pipeconf reg. For HDMI we must use 8bpc
2003 * here for both 8bpc and 12bpc.
e9bcff5c 2004 */
dfd07d72 2005 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2006 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2007 val |= PIPECONF_8BPC;
2008 else
2009 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2010 }
5f7f726d
PZ		 2011
2012 val &= ~TRANS_INTERLACE_MASK;
2013 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2014 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2015 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2016 val |= TRANS_LEGACY_INTERLACED_ILK;
2017 else
2018 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2019 else
2020 val |= TRANS_PROGRESSIVE;
2021
040484af
JB		 2022 I915_WRITE(reg, val | TRANS_ENABLE);
2023 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2024 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2025}
2026
8fb033d7 2027static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2028 enum transcoder cpu_transcoder)
040484af 2029{
8fb033d7 2030 u32 val, pipeconf_val;
8fb033d7
PZ		 2031
2032 /* PCH only available on ILK+ */
55522f37 2033 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2034
8fb033d7 2035 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2036 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2037 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2038
223a6fdf
PZ		 2039 /* Workaround: set timing override bit. */
2040 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2041 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2042 I915_WRITE(_TRANSA_CHICKEN2, val);
2043
25f3ef11 2044 val = TRANS_ENABLE;
937bb610 2045 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2046
9a76b1c6
PZ		 2047 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2048 PIPECONF_INTERLACED_ILK)
a35f2679 2049 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2050 else
2051 val |= TRANS_PROGRESSIVE;
2052
ab9412ba
DV		 2053 I915_WRITE(LPT_TRANSCONF, val);
2054 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2055 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2056}
2057
b8a4f404
PZ		 2058static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2059 enum pipe pipe)
040484af 2060{
23670b32
DV		 2061 struct drm_device *dev = dev_priv->dev;
2062 uint32_t reg, val;
040484af
JB		 2063
2064 /* FDI relies on the transcoder */
2065 assert_fdi_tx_disabled(dev_priv, pipe);
2066 assert_fdi_rx_disabled(dev_priv, pipe);
2067
291906f1
JB		 2068 /* Ports must be off as well */
2069 assert_pch_ports_disabled(dev_priv, pipe);
2070
ab9412ba 2071 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2072 val = I915_READ(reg);
2073 val &= ~TRANS_ENABLE;
2074 I915_WRITE(reg, val);
2075 /* wait for PCH transcoder off, transcoder state */
2076 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2077 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2078
2079 if (!HAS_PCH_IBX(dev)) {
2080 /* Workaround: Clear the timing override chicken bit again. */
2081 reg = TRANS_CHICKEN2(pipe);
2082 val = I915_READ(reg);
2083 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2084 I915_WRITE(reg, val);
2085 }
040484af
JB		 2086}
2087
ab4d966c 2088static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2089{
8fb033d7
PZ		 2090 u32 val;
2091
ab9412ba 2092 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2093 val &= ~TRANS_ENABLE;
ab9412ba 2094 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2095 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2096 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2097 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2098
2099 /* Workaround: clear timing override bit. */
2100 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2101 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2102 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2103}
2104
b24e7179 2105/**
309cfea8 2106 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2107 * @crtc: crtc responsible for the pipe
b24e7179 2108 *
0372264a 2109 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2110 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2111 */
e1fdc473 2112static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2113{
0372264a
PZ		 2114 struct drm_device *dev = crtc->base.dev;
2115 struct drm_i915_private *dev_priv = dev->dev_private;
2116 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2117 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2118 pipe);
1a240d4d 2119 enum pipe pch_transcoder;
b24e7179
JB		 2120 int reg;
2121 u32 val;
2122
9e2ee2dd
VS		 2123 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2124
58c6eaa2 2125 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2126 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2127 assert_sprites_disabled(dev_priv, pipe);
2128
681e5811 2129 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2130 pch_transcoder = TRANSCODER_A;
2131 else
2132 pch_transcoder = pipe;
2133
b24e7179
JB		 2134 /*
2135 * A pipe without a PLL won't actually be able to drive bits from
2136 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2137 * need the check.
2138 */
50360403 2139 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2140 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2141 assert_dsi_pll_enabled(dev_priv);
2142 else
2143 assert_pll_enabled(dev_priv, pipe);
040484af 2144 else {
6e3c9717 2145 if (crtc->config->has_pch_encoder) {
040484af 2146 /* if driving the PCH, we need FDI enabled */
cc391bbb 2147 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2148 assert_fdi_tx_pll_enabled(dev_priv,
2149 (enum pipe) cpu_transcoder);
040484af
JB		 2150 }
2151 /* FIXME: assert CPU port conditions for SNB+ */
2152 }
b24e7179 2153
702e7a56 2154 reg = PIPECONF(cpu_transcoder);
b24e7179 2155 val = I915_READ(reg);
7ad25d48 2156 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2157 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2158 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2159 return;
7ad25d48 2160 }
00d70b15
CW		 2161
2162 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2163 POSTING_READ(reg);
b24e7179
JB		 2164}
2165
2166/**
309cfea8 2167 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2168 * @crtc: crtc whose pipes is to be disabled
b24e7179 2169 *
575f7ab7
VS		 2170 * Disable the pipe of @crtc, making sure that various hardware
2171 * specific requirements are met, if applicable, e.g. plane
2172 * disabled, panel fitter off, etc.
b24e7179
JB		 2173 *
2174 * Will wait until the pipe has shut down before returning.
2175 */
575f7ab7 2176static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2177{
575f7ab7 2178 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2179 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2180 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2181 int reg;
2182 u32 val;
2183
9e2ee2dd
VS		 2184 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2185
b24e7179
JB		 2186 /*
2187 * Make sure planes won't keep trying to pump pixels to us,
2188 * or we might hang the display.
2189 */
2190 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2191 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2192 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2193
702e7a56 2194 reg = PIPECONF(cpu_transcoder);
b24e7179 2195 val = I915_READ(reg);
00d70b15
CW		 2196 if ((val & PIPECONF_ENABLE) == 0)
2197 return;
2198
67adc644
VS		 2199 /*
2200 * Double wide has implications for planes
2201 * so best keep it disabled when not needed.
2202 */
6e3c9717 2203 if (crtc->config->double_wide)
67adc644
VS		 2204 val &= ~PIPECONF_DOUBLE_WIDE;
2205
2206 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2207 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2208 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2209 val &= ~PIPECONF_ENABLE;
2210
2211 I915_WRITE(reg, val);
2212 if ((val & PIPECONF_ENABLE) == 0)
2213 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2214}
2215
693db184
CW		 2216static bool need_vtd_wa(struct drm_device *dev)
2217{
2218#ifdef CONFIG_INTEL_IOMMU
2219 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2220 return true;
2221#endif
2222 return false;
2223}
2224
50470bb0 2225unsigned int
6761dd31
TU		 2226intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2227 uint64_t fb_format_modifier)
a57ce0b2 2228{
6761dd31
TU		 2229 unsigned int tile_height;
2230 uint32_t pixel_bytes;
a57ce0b2 2231
b5d0e9bf
DL		 2232 switch (fb_format_modifier) {
2233 case DRM_FORMAT_MOD_NONE:
2234 tile_height = 1;
2235 break;
2236 case I915_FORMAT_MOD_X_TILED:
2237 tile_height = IS_GEN2(dev) ? 16 : 8;
2238 break;
2239 case I915_FORMAT_MOD_Y_TILED:
2240 tile_height = 32;
2241 break;
2242 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2243 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2244 switch (pixel_bytes) {
b5d0e9bf 2245 default:
6761dd31 2246 case 1:
b5d0e9bf
DL		 2247 tile_height = 64;
2248 break;
6761dd31
TU		 2249 case 2:
2250 case 4:
b5d0e9bf
DL		 2251 tile_height = 32;
2252 break;
6761dd31 2253 case 8:
b5d0e9bf
DL		 2254 tile_height = 16;
2255 break;
6761dd31 2256 case 16:
b5d0e9bf
DL		 2257 WARN_ONCE(1,
2258 "128-bit pixels are not supported for display!");
2259 tile_height = 16;
2260 break;
2261 }
2262 break;
2263 default:
2264 MISSING_CASE(fb_format_modifier);
2265 tile_height = 1;
2266 break;
2267 }
091df6cb 2268
6761dd31
TU		 2269 return tile_height;
2270}
2271
2272unsigned int
2273intel_fb_align_height(struct drm_device *dev, unsigned int height,
2274 uint32_t pixel_format, uint64_t fb_format_modifier)
2275{
2276 return ALIGN(height, intel_tile_height(dev, pixel_format,
2277 fb_format_modifier));
a57ce0b2
JB		 2278}
2279
f64b98cd
TU		 2280static int
2281intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2282 const struct drm_plane_state *plane_state)
2283{
50470bb0 2284 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2285 unsigned int tile_height, tile_pitch;
50470bb0 2286
f64b98cd
TU		 2287 *view = i915_ggtt_view_normal;
2288
50470bb0
TU		 2289 if (!plane_state)
2290 return 0;
2291
121920fa 2292 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2293 return 0;
2294
9abc4648 2295 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2296
2297 info->height = fb->height;
2298 info->pixel_format = fb->pixel_format;
2299 info->pitch = fb->pitches[0];
2300 info->fb_modifier = fb->modifier[0];
2301
84fe03f7
TU		 2302 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2303 fb->modifier[0]);
2304 tile_pitch = PAGE_SIZE / tile_height;
2305 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2306 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2307 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2308
f64b98cd
TU		 2309 return 0;
2310}
2311
4e9a86b6
VS		 2312static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2313{
2314 if (INTEL_INFO(dev_priv)->gen >= 9)
2315 return 256 * 1024;
985b8bb4
VS		 2316 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2317 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2318 return 128 * 1024;
2319 else if (INTEL_INFO(dev_priv)->gen >= 4)
2320 return 4 * 1024;
2321 else
44c5905e 2322 return 0;
4e9a86b6
VS		 2323}
2324
127bd2ac 2325int
850c4cdc
TU		 2326intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2327 struct drm_framebuffer *fb,
82bc3b2d 2328 const struct drm_plane_state *plane_state,
91af127f
JH		 2329 struct intel_engine_cs *pipelined,
2330 struct drm_i915_gem_request **pipelined_request)
6b95a207 2331{
850c4cdc 2332 struct drm_device *dev = fb->dev;
ce453d81 2333 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2334 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2335 struct i915_ggtt_view view;
6b95a207
KH		 2336 u32 alignment;
2337 int ret;
2338
ebcdd39e
MR		 2339 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2340
7b911adc
TU		 2341 switch (fb->modifier[0]) {
2342 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2343 alignment = intel_linear_alignment(dev_priv);
6b95a207 2344 break;
7b911adc 2345 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2346 if (INTEL_INFO(dev)->gen >= 9)
2347 alignment = 256 * 1024;
2348 else {
2349 /* pin() will align the object as required by fence */
2350 alignment = 0;
2351 }
6b95a207 2352 break;
7b911adc 2353 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2354 case I915_FORMAT_MOD_Yf_TILED:
2355 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2356 "Y tiling bo slipped through, driver bug!\n"))
2357 return -EINVAL;
2358 alignment = 1 * 1024 * 1024;
2359 break;
6b95a207 2360 default:
7b911adc
TU		 2361 MISSING_CASE(fb->modifier[0]);
2362 return -EINVAL;
6b95a207
KH		 2363 }
2364
f64b98cd
TU		 2365 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2366 if (ret)
2367 return ret;
2368
693db184
CW		 2369 /* Note that the w/a also requires 64 PTE of padding following the
2370 * bo. We currently fill all unused PTE with the shadow page and so
2371 * we should always have valid PTE following the scanout preventing
2372 * the VT-d warning.
2373 */
2374 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2375 alignment = 256 * 1024;
2376
d6dd6843
PZ		 2377 /*
2378 * Global gtt pte registers are special registers which actually forward
2379 * writes to a chunk of system memory. Which means that there is no risk
2380 * that the register values disappear as soon as we call
2381 * intel_runtime_pm_put(), so it is correct to wrap only the
2382 * pin/unpin/fence and not more.
2383 */
2384 intel_runtime_pm_get(dev_priv);
2385
ce453d81 2386 dev_priv->mm.interruptible = false;
e6617330 2387 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2388 pipelined_request, &view);
48b956c5 2389 if (ret)
ce453d81 2390 goto err_interruptible;
6b95a207
KH		 2391
2392 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2393 * fence, whereas 965+ only requires a fence if using
2394 * framebuffer compression. For simplicity, we always install
2395 * a fence as the cost is not that onerous.
2396 */
06d98131 2397 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2398 if (ret)
2399 goto err_unpin;
1690e1eb 2400
9a5a53b3 2401 i915_gem_object_pin_fence(obj);
6b95a207 2402
ce453d81 2403 dev_priv->mm.interruptible = true;
d6dd6843 2404 intel_runtime_pm_put(dev_priv);
6b95a207 2405 return 0;
48b956c5
CW		 2406
2407err_unpin:
f64b98cd 2408 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2409err_interruptible:
2410 dev_priv->mm.interruptible = true;
d6dd6843 2411 intel_runtime_pm_put(dev_priv);
48b956c5 2412 return ret;
6b95a207
KH		 2413}
2414
82bc3b2d
TU		 2415static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2416 const struct drm_plane_state *plane_state)
1690e1eb 2417{
82bc3b2d 2418 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2419 struct i915_ggtt_view view;
2420 int ret;
82bc3b2d 2421
ebcdd39e
MR		 2422 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2423
f64b98cd
TU		 2424 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2425 WARN_ONCE(ret, "Couldn't get view from plane state!");
2426
1690e1eb 2427 i915_gem_object_unpin_fence(obj);
f64b98cd 2428 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2429}
2430
c2c75131
DV		 2431/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2432 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2433unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2434 int *x, int *y,
bc752862
CW		 2435 unsigned int tiling_mode,
2436 unsigned int cpp,
2437 unsigned int pitch)
c2c75131 2438{
bc752862
CW		 2439 if (tiling_mode != I915_TILING_NONE) {
2440 unsigned int tile_rows, tiles;
c2c75131 2441
bc752862
CW		 2442 tile_rows = *y / 8;
2443 *y %= 8;
c2c75131 2444
bc752862
CW		 2445 tiles = *x / (512/cpp);
2446 *x %= 512/cpp;
2447
2448 return tile_rows * pitch * 8 + tiles * 4096;
2449 } else {
4e9a86b6 2450 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2451 unsigned int offset;
2452
2453 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2454 *y = (offset & alignment) / pitch;
2455 *x = ((offset & alignment) - *y * pitch) / cpp;
2456 return offset & ~alignment;
bc752862 2457 }
c2c75131
DV		 2458}
2459
b35d63fa 2460static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2461{
2462 switch (format) {
2463 case DISPPLANE_8BPP:
2464 return DRM_FORMAT_C8;
2465 case DISPPLANE_BGRX555:
2466 return DRM_FORMAT_XRGB1555;
2467 case DISPPLANE_BGRX565:
2468 return DRM_FORMAT_RGB565;
2469 default:
2470 case DISPPLANE_BGRX888:
2471 return DRM_FORMAT_XRGB8888;
2472 case DISPPLANE_RGBX888:
2473 return DRM_FORMAT_XBGR8888;
2474 case DISPPLANE_BGRX101010:
2475 return DRM_FORMAT_XRGB2101010;
2476 case DISPPLANE_RGBX101010:
2477 return DRM_FORMAT_XBGR2101010;
2478 }
2479}
2480
bc8d7dff
DL		 2481static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2482{
2483 switch (format) {
2484 case PLANE_CTL_FORMAT_RGB_565:
2485 return DRM_FORMAT_RGB565;
2486 default:
2487 case PLANE_CTL_FORMAT_XRGB_8888:
2488 if (rgb_order) {
2489 if (alpha)
2490 return DRM_FORMAT_ABGR8888;
2491 else
2492 return DRM_FORMAT_XBGR8888;
2493 } else {
2494 if (alpha)
2495 return DRM_FORMAT_ARGB8888;
2496 else
2497 return DRM_FORMAT_XRGB8888;
2498 }
2499 case PLANE_CTL_FORMAT_XRGB_2101010:
2500 if (rgb_order)
2501 return DRM_FORMAT_XBGR2101010;
2502 else
2503 return DRM_FORMAT_XRGB2101010;
2504 }
2505}
2506
5724dbd1 2507static bool
f6936e29
DV		 2508intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2509 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2510{
2511 struct drm_device *dev = crtc->base.dev;
2512 struct drm_i915_gem_object *obj = NULL;
2513 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2514 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2515 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2516 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2517 PAGE_SIZE);
2518
2519 size_aligned -= base_aligned;
46f297fb 2520
ff2652ea
CW		 2521 if (plane_config->size == 0)
2522 return false;
2523
f37b5c2b
DV		 2524 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2525 base_aligned,
2526 base_aligned,
2527 size_aligned);
46f297fb 2528 if (!obj)
484b41dd 2529 return false;
46f297fb 2530
49af449b
DL		 2531 obj->tiling_mode = plane_config->tiling;
2532 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2533 obj->stride = fb->pitches[0];
46f297fb 2534
6bf129df
DL		 2535 mode_cmd.pixel_format = fb->pixel_format;
2536 mode_cmd.width = fb->width;
2537 mode_cmd.height = fb->height;
2538 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2539 mode_cmd.modifier[0] = fb->modifier[0];
2540 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2541
2542 mutex_lock(&dev->struct_mutex);
6bf129df 2543 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2544 &mode_cmd, obj)) {
46f297fb
JB		 2545 DRM_DEBUG_KMS("intel fb init failed\n");
2546 goto out_unref_obj;
2547 }
46f297fb 2548 mutex_unlock(&dev->struct_mutex);
484b41dd 2549
f6936e29 2550 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2551 return true;
46f297fb
JB		 2552
2553out_unref_obj:
2554 drm_gem_object_unreference(&obj->base);
2555 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2556 return false;
2557}
2558
afd65eb4
MR		 2559/* Update plane->state->fb to match plane->fb after driver-internal updates */
2560static void
2561update_state_fb(struct drm_plane *plane)
2562{
2563 if (plane->fb == plane->state->fb)
2564 return;
2565
2566 if (plane->state->fb)
2567 drm_framebuffer_unreference(plane->state->fb);
2568 plane->state->fb = plane->fb;
2569 if (plane->state->fb)
2570 drm_framebuffer_reference(plane->state->fb);
2571}
2572
5724dbd1 2573static void
f6936e29
DV		 2574intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2575 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2576{
2577 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2578 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2579 struct drm_crtc *c;
2580 struct intel_crtc *i;
2ff8fde1 2581 struct drm_i915_gem_object *obj;
88595ac9 2582 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2583 struct drm_plane_state *plane_state = primary->state;
88595ac9 2584 struct drm_framebuffer *fb;
484b41dd 2585
2d14030b 2586 if (!plane_config->fb)
484b41dd
JB		 2587 return;
2588
f6936e29 2589 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2590 fb = &plane_config->fb->base;
2591 goto valid_fb;
f55548b5 2592 }
484b41dd 2593
2d14030b 2594 kfree(plane_config->fb);
484b41dd
JB		 2595
2596 /*
2597 * Failed to alloc the obj, check to see if we should share
2598 * an fb with another CRTC instead
2599 */
70e1e0ec 2600 for_each_crtc(dev, c) {
484b41dd
JB		 2601 i = to_intel_crtc(c);
2602
2603 if (c == &intel_crtc->base)
2604 continue;
2605
2ff8fde1
MR		 2606 if (!i->active)
2607 continue;
2608
88595ac9
DV		 2609 fb = c->primary->fb;
2610 if (!fb)
484b41dd
JB		 2611 continue;
2612
88595ac9 2613 obj = intel_fb_obj(fb);
2ff8fde1 2614 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2615 drm_framebuffer_reference(fb);
2616 goto valid_fb;
484b41dd
JB		 2617 }
2618 }
88595ac9
DV		 2619
2620 return;
2621
2622valid_fb:
be5651f2
ML		 2623 plane_state->src_x = plane_state->src_y = 0;
2624 plane_state->src_w = fb->width << 16;
2625 plane_state->src_h = fb->height << 16;
2626
2627 plane_state->crtc_x = plane_state->src_y = 0;
2628 plane_state->crtc_w = fb->width;
2629 plane_state->crtc_h = fb->height;
2630
88595ac9
DV		 2631 obj = intel_fb_obj(fb);
2632 if (obj->tiling_mode != I915_TILING_NONE)
2633 dev_priv->preserve_bios_swizzle = true;
2634
be5651f2
ML		 2635 drm_framebuffer_reference(fb);
2636 primary->fb = primary->state->fb = fb;
36750f28 2637 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2638 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2639 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2640}
2641
29b9bde6
DV		 2642static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2643 struct drm_framebuffer *fb,
2644 int x, int y)
81255565
JB		 2645{
2646 struct drm_device *dev = crtc->dev;
2647 struct drm_i915_private *dev_priv = dev->dev_private;
2648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2649 struct drm_plane *primary = crtc->primary;
2650 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2651 struct drm_i915_gem_object *obj;
81255565 2652 int plane = intel_crtc->plane;
e506a0c6 2653 unsigned long linear_offset;
81255565 2654 u32 dspcntr;
f45651ba 2655 u32 reg = DSPCNTR(plane);
48404c1e 2656 int pixel_size;
f45651ba 2657
b70709a6 2658 if (!visible || !fb) {
fdd508a6
VS		 2659 I915_WRITE(reg, 0);
2660 if (INTEL_INFO(dev)->gen >= 4)
2661 I915_WRITE(DSPSURF(plane), 0);
2662 else
2663 I915_WRITE(DSPADDR(plane), 0);
2664 POSTING_READ(reg);
2665 return;
2666 }
2667
c9ba6fad
VS		 2668 obj = intel_fb_obj(fb);
2669 if (WARN_ON(obj == NULL))
2670 return;
2671
2672 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2673
f45651ba
VS		 2674 dspcntr = DISPPLANE_GAMMA_ENABLE;
2675
fdd508a6 2676 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2677
2678 if (INTEL_INFO(dev)->gen < 4) {
2679 if (intel_crtc->pipe == PIPE_B)
2680 dspcntr |= DISPPLANE_SEL_PIPE_B;
2681
2682 /* pipesrc and dspsize control the size that is scaled from,
2683 * which should always be the user's requested size.
2684 */
2685 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2686 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2687 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2688 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2689 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2690 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2691 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2692 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2693 I915_WRITE(PRIMPOS(plane), 0);
2694 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2695 }
81255565 2696
57779d06
VS		 2697 switch (fb->pixel_format) {
2698 case DRM_FORMAT_C8:
81255565
JB		 2699 dspcntr |= DISPPLANE_8BPP;
2700 break;
57779d06 2701 case DRM_FORMAT_XRGB1555:
57779d06 2702 dspcntr |= DISPPLANE_BGRX555;
81255565 2703 break;
57779d06
VS		 2704 case DRM_FORMAT_RGB565:
2705 dspcntr |= DISPPLANE_BGRX565;
2706 break;
2707 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2708 dspcntr |= DISPPLANE_BGRX888;
2709 break;
2710 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2711 dspcntr |= DISPPLANE_RGBX888;
2712 break;
2713 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2714 dspcntr |= DISPPLANE_BGRX101010;
2715 break;
2716 case DRM_FORMAT_XBGR2101010:
57779d06 2717 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2718 break;
2719 default:
baba133a 2720 BUG();
81255565 2721 }
57779d06 2722
f45651ba
VS		 2723 if (INTEL_INFO(dev)->gen >= 4 &&
2724 obj->tiling_mode != I915_TILING_NONE)
2725 dspcntr |= DISPPLANE_TILED;
81255565 2726
de1aa629
VS		 2727 if (IS_G4X(dev))
2728 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2729
b9897127 2730 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2731
c2c75131
DV		 2732 if (INTEL_INFO(dev)->gen >= 4) {
2733 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2734 intel_gen4_compute_page_offset(dev_priv,
2735 &x, &y, obj->tiling_mode,
b9897127 2736 pixel_size,
bc752862 2737 fb->pitches[0]);
c2c75131
DV		 2738 linear_offset -= intel_crtc->dspaddr_offset;
2739 } else {
e506a0c6 2740 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2741 }
e506a0c6 2742
8e7d688b 2743 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2744 dspcntr |= DISPPLANE_ROTATE_180;
2745
6e3c9717
ACO		 2746 x += (intel_crtc->config->pipe_src_w - 1);
2747 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2748
2749 /* Finding the last pixel of the last line of the display
2750 data and adding to linear_offset*/
2751 linear_offset +=
6e3c9717
ACO		 2752 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2753 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2754 }
2755
2756 I915_WRITE(reg, dspcntr);
2757
01f2c773 2758 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2759 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2760 I915_WRITE(DSPSURF(plane),
2761 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2762 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2763 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2764 } else
f343c5f6 2765 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2766 POSTING_READ(reg);
17638cd6
JB		 2767}
2768
29b9bde6
DV		 2769static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2770 struct drm_framebuffer *fb,
2771 int x, int y)
17638cd6
JB		 2772{
2773 struct drm_device *dev = crtc->dev;
2774 struct drm_i915_private *dev_priv = dev->dev_private;
2775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2776 struct drm_plane *primary = crtc->primary;
2777 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2778 struct drm_i915_gem_object *obj;
17638cd6 2779 int plane = intel_crtc->plane;
e506a0c6 2780 unsigned long linear_offset;
17638cd6 2781 u32 dspcntr;
f45651ba 2782 u32 reg = DSPCNTR(plane);
48404c1e 2783 int pixel_size;
f45651ba 2784
b70709a6 2785 if (!visible || !fb) {
fdd508a6
VS		 2786 I915_WRITE(reg, 0);
2787 I915_WRITE(DSPSURF(plane), 0);
2788 POSTING_READ(reg);
2789 return;
2790 }
2791
c9ba6fad
VS		 2792 obj = intel_fb_obj(fb);
2793 if (WARN_ON(obj == NULL))
2794 return;
2795
2796 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2797
f45651ba
VS		 2798 dspcntr = DISPPLANE_GAMMA_ENABLE;
2799
fdd508a6 2800 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2801
2802 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2803 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2804
57779d06
VS		 2805 switch (fb->pixel_format) {
2806 case DRM_FORMAT_C8:
17638cd6
JB		 2807 dspcntr |= DISPPLANE_8BPP;
2808 break;
57779d06
VS		 2809 case DRM_FORMAT_RGB565:
2810 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2811 break;
57779d06 2812 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2813 dspcntr |= DISPPLANE_BGRX888;
2814 break;
2815 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2816 dspcntr |= DISPPLANE_RGBX888;
2817 break;
2818 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2819 dspcntr |= DISPPLANE_BGRX101010;
2820 break;
2821 case DRM_FORMAT_XBGR2101010:
57779d06 2822 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2823 break;
2824 default:
baba133a 2825 BUG();
17638cd6
JB		 2826 }
2827
2828 if (obj->tiling_mode != I915_TILING_NONE)
2829 dspcntr |= DISPPLANE_TILED;
17638cd6 2830
f45651ba 2831 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2832 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2833
b9897127 2834 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2835 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2836 intel_gen4_compute_page_offset(dev_priv,
2837 &x, &y, obj->tiling_mode,
b9897127 2838 pixel_size,
bc752862 2839 fb->pitches[0]);
c2c75131 2840 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2841 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2842 dspcntr |= DISPPLANE_ROTATE_180;
2843
2844 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2845 x += (intel_crtc->config->pipe_src_w - 1);
2846 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2847
2848 /* Finding the last pixel of the last line of the display
2849 data and adding to linear_offset*/
2850 linear_offset +=
6e3c9717
ACO		 2851 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2852 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2853 }
2854 }
2855
2856 I915_WRITE(reg, dspcntr);
17638cd6 2857
01f2c773 2858 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2859 I915_WRITE(DSPSURF(plane),
2860 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2861 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2862 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2863 } else {
2864 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2865 I915_WRITE(DSPLINOFF(plane), linear_offset);
2866 }
17638cd6 2867 POSTING_READ(reg);
17638cd6
JB		 2868}
2869
b321803d
DL		 2870u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2871 uint32_t pixel_format)
2872{
2873 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2874
2875 /*
2876 * The stride is either expressed as a multiple of 64 bytes
2877 * chunks for linear buffers or in number of tiles for tiled
2878 * buffers.
2879 */
2880 switch (fb_modifier) {
2881 case DRM_FORMAT_MOD_NONE:
2882 return 64;
2883 case I915_FORMAT_MOD_X_TILED:
2884 if (INTEL_INFO(dev)->gen == 2)
2885 return 128;
2886 return 512;
2887 case I915_FORMAT_MOD_Y_TILED:
2888 /* No need to check for old gens and Y tiling since this is
2889 * about the display engine and those will be blocked before
2890 * we get here.
2891 */
2892 return 128;
2893 case I915_FORMAT_MOD_Yf_TILED:
2894 if (bits_per_pixel == 8)
2895 return 64;
2896 else
2897 return 128;
2898 default:
2899 MISSING_CASE(fb_modifier);
2900 return 64;
2901 }
2902}
2903
121920fa
TU		 2904unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2905 struct drm_i915_gem_object *obj)
2906{
9abc4648 2907 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2908
2909 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2910 view = &i915_ggtt_view_rotated;
121920fa
TU		 2911
2912 return i915_gem_obj_ggtt_offset_view(obj, view);
2913}
2914
e435d6e5
ML		 2915static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2916{
2917 struct drm_device *dev = intel_crtc->base.dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2919
2920 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2921 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2922 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2923 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2924 intel_crtc->base.base.id, intel_crtc->pipe, id);
2925}
2926
a1b2278e
CK		 2927/*
2928 * This function detaches (aka. unbinds) unused scalers in hardware
2929 */
0583236e 2930static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2931{
a1b2278e
CK		 2932 struct intel_crtc_scaler_state *scaler_state;
2933 int i;
2934
a1b2278e
CK		 2935 scaler_state = &intel_crtc->config->scaler_state;
2936
2937 /* loop through and disable scalers that aren't in use */
2938 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2939 if (!scaler_state->scalers[i].in_use)
2940 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2941 }
2942}
2943
6156a456 2944u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2945{
6156a456 2946 switch (pixel_format) {
d161cf7a 2947 case DRM_FORMAT_C8:
c34ce3d1 2948 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2949 case DRM_FORMAT_RGB565:
c34ce3d1 2950 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2951 case DRM_FORMAT_XBGR8888:
c34ce3d1 2952 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2953 case DRM_FORMAT_XRGB8888:
c34ce3d1 2954 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2955 /*
2956 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2957 * to be already pre-multiplied. We need to add a knob (or a different
2958 * DRM_FORMAT) for user-space to configure that.
2959 */
f75fb42a 2960 case DRM_FORMAT_ABGR8888:
c34ce3d1 2961 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2962 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2963 case DRM_FORMAT_ARGB8888:
c34ce3d1 2964 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2965 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2966 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2967 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2968 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2969 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2970 case DRM_FORMAT_YUYV:
c34ce3d1 2971 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2972 case DRM_FORMAT_YVYU:
c34ce3d1 2973 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2974 case DRM_FORMAT_UYVY:
c34ce3d1 2975 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2976 case DRM_FORMAT_VYUY:
c34ce3d1 2977 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2978 default:
4249eeef 2979 MISSING_CASE(pixel_format);
70d21f0e 2980 }
8cfcba41 2981
c34ce3d1 2982 return 0;
6156a456 2983}
70d21f0e 2984
6156a456
CK		 2985u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2986{
6156a456 2987 switch (fb_modifier) {
30af77c4 2988 case DRM_FORMAT_MOD_NONE:
70d21f0e 2989 break;
30af77c4 2990 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2991 return PLANE_CTL_TILED_X;
b321803d 2992 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2993 return PLANE_CTL_TILED_Y;
b321803d 2994 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 2995 return PLANE_CTL_TILED_YF;
70d21f0e 2996 default:
6156a456 2997 MISSING_CASE(fb_modifier);
70d21f0e 2998 }
8cfcba41 2999
c34ce3d1 3000 return 0;
6156a456 3001}
70d21f0e 3002
6156a456
CK		 3003u32 skl_plane_ctl_rotation(unsigned int rotation)
3004{
3b7a5119 3005 switch (rotation) {
6156a456
CK		 3006 case BIT(DRM_ROTATE_0):
3007 break;
1e8df167
SJ		 3008 /*
3009 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3010 * while i915 HW rotation is clockwise, thats why this swapping.
3011 */
3b7a5119 3012 case BIT(DRM_ROTATE_90):
1e8df167 3013 return PLANE_CTL_ROTATE_270;
3b7a5119 3014 case BIT(DRM_ROTATE_180):
c34ce3d1 3015 return PLANE_CTL_ROTATE_180;
3b7a5119 3016 case BIT(DRM_ROTATE_270):
1e8df167 3017 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3018 default:
3019 MISSING_CASE(rotation);
3020 }
3021
c34ce3d1 3022 return 0;
6156a456
CK		 3023}
3024
3025static void skylake_update_primary_plane(struct drm_crtc *crtc,
3026 struct drm_framebuffer *fb,
3027 int x, int y)
3028{
3029 struct drm_device *dev = crtc->dev;
3030 struct drm_i915_private *dev_priv = dev->dev_private;
3031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3032 struct drm_plane *plane = crtc->primary;
3033 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3034 struct drm_i915_gem_object *obj;
3035 int pipe = intel_crtc->pipe;
3036 u32 plane_ctl, stride_div, stride;
3037 u32 tile_height, plane_offset, plane_size;
3038 unsigned int rotation;
3039 int x_offset, y_offset;
3040 unsigned long surf_addr;
6156a456
CK		 3041 struct intel_crtc_state *crtc_state = intel_crtc->config;
3042 struct intel_plane_state *plane_state;
3043 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3044 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3045 int scaler_id = -1;
3046
6156a456
CK		 3047 plane_state = to_intel_plane_state(plane->state);
3048
b70709a6 3049 if (!visible || !fb) {
6156a456
CK		 3050 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3051 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3052 POSTING_READ(PLANE_CTL(pipe, 0));
3053 return;
3b7a5119 3054 }
70d21f0e 3055
6156a456
CK		 3056 plane_ctl = PLANE_CTL_ENABLE |
3057 PLANE_CTL_PIPE_GAMMA_ENABLE |
3058 PLANE_CTL_PIPE_CSC_ENABLE;
3059
3060 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3061 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3062 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3063
3064 rotation = plane->state->rotation;
3065 plane_ctl |= skl_plane_ctl_rotation(rotation);
3066
b321803d
DL		 3067 obj = intel_fb_obj(fb);
3068 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3069 fb->pixel_format);
3b7a5119
SJ		 3070 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3071
6156a456
CK		 3072 /*
3073 * FIXME: intel_plane_state->src, dst aren't set when transitional
3074 * update_plane helpers are called from legacy paths.
3075 * Once full atomic crtc is available, below check can be avoided.
3076 */
3077 if (drm_rect_width(&plane_state->src)) {
3078 scaler_id = plane_state->scaler_id;
3079 src_x = plane_state->src.x1 >> 16;
3080 src_y = plane_state->src.y1 >> 16;
3081 src_w = drm_rect_width(&plane_state->src) >> 16;
3082 src_h = drm_rect_height(&plane_state->src) >> 16;
3083 dst_x = plane_state->dst.x1;
3084 dst_y = plane_state->dst.y1;
3085 dst_w = drm_rect_width(&plane_state->dst);
3086 dst_h = drm_rect_height(&plane_state->dst);
3087
3088 WARN_ON(x != src_x || y != src_y);
3089 } else {
3090 src_w = intel_crtc->config->pipe_src_w;
3091 src_h = intel_crtc->config->pipe_src_h;
3092 }
3093
3b7a5119
SJ		 3094 if (intel_rotation_90_or_270(rotation)) {
3095 /* stride = Surface height in tiles */
2614f17d 3096 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3097 fb->modifier[0]);
3098 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3099 x_offset = stride * tile_height - y - src_h;
3b7a5119 3100 y_offset = x;
6156a456 3101 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3102 } else {
3103 stride = fb->pitches[0] / stride_div;
3104 x_offset = x;
3105 y_offset = y;
6156a456 3106 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3107 }
3108 plane_offset = y_offset << 16 | x_offset;
b321803d 3109
70d21f0e 3110 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3111 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3112 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3113 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3114
3115 if (scaler_id >= 0) {
3116 uint32_t ps_ctrl = 0;
3117
3118 WARN_ON(!dst_w || !dst_h);
3119 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3120 crtc_state->scaler_state.scalers[scaler_id].mode;
3121 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3122 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3123 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3124 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3125 I915_WRITE(PLANE_POS(pipe, 0), 0);
3126 } else {
3127 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3128 }
3129
121920fa 3130 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3131
3132 POSTING_READ(PLANE_SURF(pipe, 0));
3133}
3134
17638cd6
JB		 3135/* Assume fb object is pinned & idle & fenced and just update base pointers */
3136static int
3137intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3138 int x, int y, enum mode_set_atomic state)
3139{
3140 struct drm_device *dev = crtc->dev;
3141 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3142
ff2a3117 3143 if (dev_priv->fbc.disable_fbc)
7733b49b 3144 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3145
29b9bde6
DV		 3146 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3147
3148 return 0;
81255565
JB		 3149}
3150
7514747d 3151static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3152{
96a02917
VS		 3153 struct drm_crtc *crtc;
3154
70e1e0ec 3155 for_each_crtc(dev, crtc) {
96a02917
VS		 3156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3157 enum plane plane = intel_crtc->plane;
3158
3159 intel_prepare_page_flip(dev, plane);
3160 intel_finish_page_flip_plane(dev, plane);
3161 }
7514747d
VS		 3162}
3163
3164static void intel_update_primary_planes(struct drm_device *dev)
3165{
3166 struct drm_i915_private *dev_priv = dev->dev_private;
3167 struct drm_crtc *crtc;
96a02917 3168
70e1e0ec 3169 for_each_crtc(dev, crtc) {
96a02917
VS		 3170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3171
51fd371b 3172 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3173 /*
3174 * FIXME: Once we have proper support for primary planes (and
3175 * disabling them without disabling the entire crtc) allow again
66e514c1 3176 * a NULL crtc->primary->fb.
947fdaad 3177 */
f4510a27 3178 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3179 dev_priv->display.update_primary_plane(crtc,
66e514c1 3180 crtc->primary->fb,
262ca2b0
MR		 3181 crtc->x,
3182 crtc->y);
51fd371b 3183 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3184 }
3185}
3186
7514747d
VS		 3187void intel_prepare_reset(struct drm_device *dev)
3188{
3189 /* no reset support for gen2 */
3190 if (IS_GEN2(dev))
3191 return;
3192
3193 /* reset doesn't touch the display */
3194 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3195 return;
3196
3197 drm_modeset_lock_all(dev);
f98ce92f
VS		 3198 /*
3199 * Disabling the crtcs gracefully seems nicer. Also the
3200 * g33 docs say we should at least disable all the planes.
3201 */
6b72d486 3202 intel_display_suspend(dev);
7514747d
VS		 3203}
3204
3205void intel_finish_reset(struct drm_device *dev)
3206{
3207 struct drm_i915_private *dev_priv = to_i915(dev);
3208
3209 /*
3210 * Flips in the rings will be nuked by the reset,
3211 * so complete all pending flips so that user space
3212 * will get its events and not get stuck.
3213 */
3214 intel_complete_page_flips(dev);
3215
3216 /* no reset support for gen2 */
3217 if (IS_GEN2(dev))
3218 return;
3219
3220 /* reset doesn't touch the display */
3221 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3222 /*
3223 * Flips in the rings have been nuked by the reset,
3224 * so update the base address of all primary
3225 * planes to the the last fb to make sure we're
3226 * showing the correct fb after a reset.
3227 */
3228 intel_update_primary_planes(dev);
3229 return;
3230 }
3231
3232 /*
3233 * The display has been reset as well,
3234 * so need a full re-initialization.
3235 */
3236 intel_runtime_pm_disable_interrupts(dev_priv);
3237 intel_runtime_pm_enable_interrupts(dev_priv);
3238
3239 intel_modeset_init_hw(dev);
3240
3241 spin_lock_irq(&dev_priv->irq_lock);
3242 if (dev_priv->display.hpd_irq_setup)
3243 dev_priv->display.hpd_irq_setup(dev);
3244 spin_unlock_irq(&dev_priv->irq_lock);
3245
043e9bda 3246 intel_display_resume(dev);
7514747d
VS		 3247
3248 intel_hpd_init(dev_priv);
3249
3250 drm_modeset_unlock_all(dev);
3251}
3252
2e2f351d 3253static void
14667a4b
CW		 3254intel_finish_fb(struct drm_framebuffer *old_fb)
3255{
2ff8fde1 3256 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3257 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3258 bool was_interruptible = dev_priv->mm.interruptible;
3259 int ret;
3260
14667a4b
CW		 3261 /* Big Hammer, we also need to ensure that any pending
3262 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3263 * current scanout is retired before unpinning the old
2e2f351d
CW		 3264 * framebuffer. Note that we rely on userspace rendering
3265 * into the buffer attached to the pipe they are waiting
3266 * on. If not, userspace generates a GPU hang with IPEHR
3267 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3268 *
3269 * This should only fail upon a hung GPU, in which case we
3270 * can safely continue.
3271 */
3272 dev_priv->mm.interruptible = false;
2e2f351d 3273 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3274 dev_priv->mm.interruptible = was_interruptible;
3275
2e2f351d 3276 WARN_ON(ret);
14667a4b
CW		 3277}
3278
7d5e3799
CW		 3279static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3280{
3281 struct drm_device *dev = crtc->dev;
3282 struct drm_i915_private *dev_priv = dev->dev_private;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3284 bool pending;
3285
3286 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3287 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3288 return false;
3289
5e2d7afc 3290 spin_lock_irq(&dev->event_lock);
7d5e3799 3291 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3292 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3293
3294 return pending;
3295}
3296
e30e8f75
GP		 3297static void intel_update_pipe_size(struct intel_crtc *crtc)
3298{
3299 struct drm_device *dev = crtc->base.dev;
3300 struct drm_i915_private *dev_priv = dev->dev_private;
3301 const struct drm_display_mode *adjusted_mode;
3302
3303 if (!i915.fastboot)
3304 return;
3305
3306 /*
3307 * Update pipe size and adjust fitter if needed: the reason for this is
3308 * that in compute_mode_changes we check the native mode (not the pfit
3309 * mode) to see if we can flip rather than do a full mode set. In the
3310 * fastboot case, we'll flip, but if we don't update the pipesrc and
3311 * pfit state, we'll end up with a big fb scanned out into the wrong
3312 * sized surface.
3313 *
3314 * To fix this properly, we need to hoist the checks up into
3315 * compute_mode_changes (or above), check the actual pfit state and
3316 * whether the platform allows pfit disable with pipe active, and only
3317 * then update the pipesrc and pfit state, even on the flip path.
3318 */
3319
6e3c9717 3320 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3321
3322 I915_WRITE(PIPESRC(crtc->pipe),
3323 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3324 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3325 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3326 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3327 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3328 I915_WRITE(PF_CTL(crtc->pipe), 0);
3329 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3330 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3331 }
6e3c9717
ACO		 3332 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3333 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3334}
3335
5e84e1a4
ZW		 3336static void intel_fdi_normal_train(struct drm_crtc *crtc)
3337{
3338 struct drm_device *dev = crtc->dev;
3339 struct drm_i915_private *dev_priv = dev->dev_private;
3340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3341 int pipe = intel_crtc->pipe;
3342 u32 reg, temp;
3343
3344 /* enable normal train */
3345 reg = FDI_TX_CTL(pipe);
3346 temp = I915_READ(reg);
61e499bf 3347 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3348 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3349 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3350 } else {
3351 temp &= ~FDI_LINK_TRAIN_NONE;
3352 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3353 }
5e84e1a4
ZW		 3354 I915_WRITE(reg, temp);
3355
3356 reg = FDI_RX_CTL(pipe);
3357 temp = I915_READ(reg);
3358 if (HAS_PCH_CPT(dev)) {
3359 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3360 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3361 } else {
3362 temp &= ~FDI_LINK_TRAIN_NONE;
3363 temp |= FDI_LINK_TRAIN_NONE;
3364 }
3365 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3366
3367 /* wait one idle pattern time */
3368 POSTING_READ(reg);
3369 udelay(1000);
357555c0
JB		 3370
3371 /* IVB wants error correction enabled */
3372 if (IS_IVYBRIDGE(dev))
3373 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3374 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3375}
3376
8db9d77b
ZW		 3377/* The FDI link training functions for ILK/Ibexpeak. */
3378static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3379{
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383 int pipe = intel_crtc->pipe;
5eddb70b 3384 u32 reg, temp, tries;
8db9d77b 3385
1c8562f6 3386 /* FDI needs bits from pipe first */
0fc932b8 3387 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3388
e1a44743
AJ		 3389 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3390 for train result */
5eddb70b
CW		 3391 reg = FDI_RX_IMR(pipe);
3392 temp = I915_READ(reg);
e1a44743
AJ		 3393 temp &= ~FDI_RX_SYMBOL_LOCK;
3394 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3395 I915_WRITE(reg, temp);
3396 I915_READ(reg);
e1a44743
AJ		 3397 udelay(150);
3398
8db9d77b 3399 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3400 reg = FDI_TX_CTL(pipe);
3401 temp = I915_READ(reg);
627eb5a3 3402 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3403 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3406 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3407
5eddb70b
CW		 3408 reg = FDI_RX_CTL(pipe);
3409 temp = I915_READ(reg);
8db9d77b
ZW		 3410 temp &= ~FDI_LINK_TRAIN_NONE;
3411 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3412 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3413
3414 POSTING_READ(reg);
8db9d77b
ZW		 3415 udelay(150);
3416
5b2adf89 3417 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3418 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3419 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3420 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3421
5eddb70b 3422 reg = FDI_RX_IIR(pipe);
e1a44743 3423 for (tries = 0; tries < 5; tries++) {
5eddb70b 3424 temp = I915_READ(reg);
8db9d77b
ZW		 3425 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3426
3427 if ((temp & FDI_RX_BIT_LOCK)) {
3428 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3429 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3430 break;
3431 }
8db9d77b 3432 }
e1a44743 3433 if (tries == 5)
5eddb70b 3434 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3435
3436 /* Train 2 */
5eddb70b
CW		 3437 reg = FDI_TX_CTL(pipe);
3438 temp = I915_READ(reg);
8db9d77b
ZW		 3439 temp &= ~FDI_LINK_TRAIN_NONE;
3440 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3441 I915_WRITE(reg, temp);
8db9d77b 3442
5eddb70b
CW		 3443 reg = FDI_RX_CTL(pipe);
3444 temp = I915_READ(reg);
8db9d77b
ZW		 3445 temp &= ~FDI_LINK_TRAIN_NONE;
3446 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3447 I915_WRITE(reg, temp);
8db9d77b 3448
5eddb70b
CW		 3449 POSTING_READ(reg);
3450 udelay(150);
8db9d77b 3451
5eddb70b 3452 reg = FDI_RX_IIR(pipe);
e1a44743 3453 for (tries = 0; tries < 5; tries++) {
5eddb70b 3454 temp = I915_READ(reg);
8db9d77b
ZW		 3455 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3456
3457 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3458 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3459 DRM_DEBUG_KMS("FDI train 2 done.\n");
3460 break;
3461 }
8db9d77b 3462 }
e1a44743 3463 if (tries == 5)
5eddb70b 3464 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3465
3466 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3467
8db9d77b
ZW		 3468}
3469
0206e353 3470static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3471 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3472 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3473 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3474 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3475};
3476
3477/* The FDI link training functions for SNB/Cougarpoint. */
3478static void gen6_fdi_link_train(struct drm_crtc *crtc)
3479{
3480 struct drm_device *dev = crtc->dev;
3481 struct drm_i915_private *dev_priv = dev->dev_private;
3482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3483 int pipe = intel_crtc->pipe;
fa37d39e 3484 u32 reg, temp, i, retry;
8db9d77b 3485
e1a44743
AJ		 3486 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3487 for train result */
5eddb70b
CW		 3488 reg = FDI_RX_IMR(pipe);
3489 temp = I915_READ(reg);
e1a44743
AJ		 3490 temp &= ~FDI_RX_SYMBOL_LOCK;
3491 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3492 I915_WRITE(reg, temp);
3493
3494 POSTING_READ(reg);
e1a44743
AJ		 3495 udelay(150);
3496
8db9d77b 3497 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3498 reg = FDI_TX_CTL(pipe);
3499 temp = I915_READ(reg);
627eb5a3 3500 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3501 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3502 temp &= ~FDI_LINK_TRAIN_NONE;
3503 temp |= FDI_LINK_TRAIN_PATTERN_1;
3504 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3505 /* SNB-B */
3506 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3507 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3508
d74cf324
DV		 3509 I915_WRITE(FDI_RX_MISC(pipe),
3510 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3511
5eddb70b
CW		 3512 reg = FDI_RX_CTL(pipe);
3513 temp = I915_READ(reg);
8db9d77b
ZW		 3514 if (HAS_PCH_CPT(dev)) {
3515 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3516 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3517 } else {
3518 temp &= ~FDI_LINK_TRAIN_NONE;
3519 temp |= FDI_LINK_TRAIN_PATTERN_1;
3520 }
5eddb70b
CW		 3521 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3522
3523 POSTING_READ(reg);
8db9d77b
ZW		 3524 udelay(150);
3525
0206e353 3526 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3527 reg = FDI_TX_CTL(pipe);
3528 temp = I915_READ(reg);
8db9d77b
ZW		 3529 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3530 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3531 I915_WRITE(reg, temp);
3532
3533 POSTING_READ(reg);
8db9d77b
ZW		 3534 udelay(500);
3535
fa37d39e
SP		 3536 for (retry = 0; retry < 5; retry++) {
3537 reg = FDI_RX_IIR(pipe);
3538 temp = I915_READ(reg);
3539 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3540 if (temp & FDI_RX_BIT_LOCK) {
3541 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3542 DRM_DEBUG_KMS("FDI train 1 done.\n");
3543 break;
3544 }
3545 udelay(50);
8db9d77b 3546 }
fa37d39e
SP		 3547 if (retry < 5)
3548 break;
8db9d77b
ZW		 3549 }
3550 if (i == 4)
5eddb70b 3551 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3552
3553 /* Train 2 */
5eddb70b
CW		 3554 reg = FDI_TX_CTL(pipe);
3555 temp = I915_READ(reg);
8db9d77b
ZW		 3556 temp &= ~FDI_LINK_TRAIN_NONE;
3557 temp |= FDI_LINK_TRAIN_PATTERN_2;
3558 if (IS_GEN6(dev)) {
3559 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3560 /* SNB-B */
3561 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3562 }
5eddb70b 3563 I915_WRITE(reg, temp);
8db9d77b 3564
5eddb70b
CW		 3565 reg = FDI_RX_CTL(pipe);
3566 temp = I915_READ(reg);
8db9d77b
ZW		 3567 if (HAS_PCH_CPT(dev)) {
3568 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3569 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3570 } else {
3571 temp &= ~FDI_LINK_TRAIN_NONE;
3572 temp |= FDI_LINK_TRAIN_PATTERN_2;
3573 }
5eddb70b
CW		 3574 I915_WRITE(reg, temp);
3575
3576 POSTING_READ(reg);
8db9d77b
ZW		 3577 udelay(150);
3578
0206e353 3579 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3580 reg = FDI_TX_CTL(pipe);
3581 temp = I915_READ(reg);
8db9d77b
ZW		 3582 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3583 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3584 I915_WRITE(reg, temp);
3585
3586 POSTING_READ(reg);
8db9d77b
ZW		 3587 udelay(500);
3588
fa37d39e
SP		 3589 for (retry = 0; retry < 5; retry++) {
3590 reg = FDI_RX_IIR(pipe);
3591 temp = I915_READ(reg);
3592 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3593 if (temp & FDI_RX_SYMBOL_LOCK) {
3594 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3595 DRM_DEBUG_KMS("FDI train 2 done.\n");
3596 break;
3597 }
3598 udelay(50);
8db9d77b 3599 }
fa37d39e
SP		 3600 if (retry < 5)
3601 break;
8db9d77b
ZW		 3602 }
3603 if (i == 4)
5eddb70b 3604 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3605
3606 DRM_DEBUG_KMS("FDI train done.\n");
3607}
3608
357555c0
JB		 3609/* Manual link training for Ivy Bridge A0 parts */
3610static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3611{
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615 int pipe = intel_crtc->pipe;
139ccd3f 3616 u32 reg, temp, i, j;
357555c0
JB		 3617
3618 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3619 for train result */
3620 reg = FDI_RX_IMR(pipe);
3621 temp = I915_READ(reg);
3622 temp &= ~FDI_RX_SYMBOL_LOCK;
3623 temp &= ~FDI_RX_BIT_LOCK;
3624 I915_WRITE(reg, temp);
3625
3626 POSTING_READ(reg);
3627 udelay(150);
3628
01a415fd
DV		 3629 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3630 I915_READ(FDI_RX_IIR(pipe)));
3631
139ccd3f
JB		 3632 /* Try each vswing and preemphasis setting twice before moving on */
3633 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3634 /* disable first in case we need to retry */
3635 reg = FDI_TX_CTL(pipe);
3636 temp = I915_READ(reg);
3637 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3638 temp &= ~FDI_TX_ENABLE;
3639 I915_WRITE(reg, temp);
357555c0 3640
139ccd3f
JB		 3641 reg = FDI_RX_CTL(pipe);
3642 temp = I915_READ(reg);
3643 temp &= ~FDI_LINK_TRAIN_AUTO;
3644 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3645 temp &= ~FDI_RX_ENABLE;
3646 I915_WRITE(reg, temp);
357555c0 3647
139ccd3f 3648 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3649 reg = FDI_TX_CTL(pipe);
3650 temp = I915_READ(reg);
139ccd3f 3651 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3652 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3653 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3654 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3655 temp |= snb_b_fdi_train_param[j/2];
3656 temp |= FDI_COMPOSITE_SYNC;
3657 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3658
139ccd3f
JB		 3659 I915_WRITE(FDI_RX_MISC(pipe),
3660 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3661
139ccd3f 3662 reg = FDI_RX_CTL(pipe);
357555c0 3663 temp = I915_READ(reg);
139ccd3f
JB		 3664 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3665 temp |= FDI_COMPOSITE_SYNC;
3666 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3667
139ccd3f
JB		 3668 POSTING_READ(reg);
3669 udelay(1); /* should be 0.5us */
357555c0 3670
139ccd3f
JB		 3671 for (i = 0; i < 4; i++) {
3672 reg = FDI_RX_IIR(pipe);
3673 temp = I915_READ(reg);
3674 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3675
139ccd3f
JB		 3676 if (temp & FDI_RX_BIT_LOCK ||
3677 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3678 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3679 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3680 i);
3681 break;
3682 }
3683 udelay(1); /* should be 0.5us */
3684 }
3685 if (i == 4) {
3686 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3687 continue;
3688 }
357555c0 3689
139ccd3f 3690 /* Train 2 */
357555c0
JB		 3691 reg = FDI_TX_CTL(pipe);
3692 temp = I915_READ(reg);
139ccd3f
JB		 3693 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3694 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3695 I915_WRITE(reg, temp);
3696
3697 reg = FDI_RX_CTL(pipe);
3698 temp = I915_READ(reg);
3699 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3700 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3701 I915_WRITE(reg, temp);
3702
3703 POSTING_READ(reg);
139ccd3f 3704 udelay(2); /* should be 1.5us */
357555c0 3705
139ccd3f
JB		 3706 for (i = 0; i < 4; i++) {
3707 reg = FDI_RX_IIR(pipe);
3708 temp = I915_READ(reg);
3709 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3710
139ccd3f
JB		 3711 if (temp & FDI_RX_SYMBOL_LOCK ||
3712 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3713 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3714 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3715 i);
3716 goto train_done;
3717 }
3718 udelay(2); /* should be 1.5us */
357555c0 3719 }
139ccd3f
JB		 3720 if (i == 4)
3721 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3722 }
357555c0 3723
139ccd3f 3724train_done:
357555c0
JB		 3725 DRM_DEBUG_KMS("FDI train done.\n");
3726}
3727
88cefb6c 3728static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3729{
88cefb6c 3730 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3731 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3732 int pipe = intel_crtc->pipe;
5eddb70b 3733 u32 reg, temp;
79e53945 3734
c64e311e 3735
c98e9dcf 3736 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3737 reg = FDI_RX_CTL(pipe);
3738 temp = I915_READ(reg);
627eb5a3 3739 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3740 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3741 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3742 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3743
3744 POSTING_READ(reg);
c98e9dcf
JB		 3745 udelay(200);
3746
3747 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3748 temp = I915_READ(reg);
3749 I915_WRITE(reg, temp | FDI_PCDCLK);
3750
3751 POSTING_READ(reg);
c98e9dcf
JB		 3752 udelay(200);
3753
20749730
PZ		 3754 /* Enable CPU FDI TX PLL, always on for Ironlake */
3755 reg = FDI_TX_CTL(pipe);
3756 temp = I915_READ(reg);
3757 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3758 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3759
20749730
PZ		 3760 POSTING_READ(reg);
3761 udelay(100);
6be4a607 3762 }
0e23b99d
JB		 3763}
3764
88cefb6c
DV		 3765static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3766{
3767 struct drm_device *dev = intel_crtc->base.dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769 int pipe = intel_crtc->pipe;
3770 u32 reg, temp;
3771
3772 /* Switch from PCDclk to Rawclk */
3773 reg = FDI_RX_CTL(pipe);
3774 temp = I915_READ(reg);
3775 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3776
3777 /* Disable CPU FDI TX PLL */
3778 reg = FDI_TX_CTL(pipe);
3779 temp = I915_READ(reg);
3780 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3781
3782 POSTING_READ(reg);
3783 udelay(100);
3784
3785 reg = FDI_RX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3788
3789 /* Wait for the clocks to turn off. */
3790 POSTING_READ(reg);
3791 udelay(100);
3792}
3793
0fc932b8
JB		 3794static void ironlake_fdi_disable(struct drm_crtc *crtc)
3795{
3796 struct drm_device *dev = crtc->dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3799 int pipe = intel_crtc->pipe;
3800 u32 reg, temp;
3801
3802 /* disable CPU FDI tx and PCH FDI rx */
3803 reg = FDI_TX_CTL(pipe);
3804 temp = I915_READ(reg);
3805 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3806 POSTING_READ(reg);
3807
3808 reg = FDI_RX_CTL(pipe);
3809 temp = I915_READ(reg);
3810 temp &= ~(0x7 << 16);
dfd07d72 3811 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3812 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3813
3814 POSTING_READ(reg);
3815 udelay(100);
3816
3817 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3818 if (HAS_PCH_IBX(dev))
6f06ce18 3819 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3820
3821 /* still set train pattern 1 */
3822 reg = FDI_TX_CTL(pipe);
3823 temp = I915_READ(reg);
3824 temp &= ~FDI_LINK_TRAIN_NONE;
3825 temp |= FDI_LINK_TRAIN_PATTERN_1;
3826 I915_WRITE(reg, temp);
3827
3828 reg = FDI_RX_CTL(pipe);
3829 temp = I915_READ(reg);
3830 if (HAS_PCH_CPT(dev)) {
3831 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3832 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3833 } else {
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_1;
3836 }
3837 /* BPC in FDI rx is consistent with that in PIPECONF */
3838 temp &= ~(0x07 << 16);
dfd07d72 3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3840 I915_WRITE(reg, temp);
3841
3842 POSTING_READ(reg);
3843 udelay(100);
3844}
3845
5dce5b93
CW		 3846bool intel_has_pending_fb_unpin(struct drm_device *dev)
3847{
3848 struct intel_crtc *crtc;
3849
3850 /* Note that we don't need to be called with mode_config.lock here
3851 * as our list of CRTC objects is static for the lifetime of the
3852 * device and so cannot disappear as we iterate. Similarly, we can
3853 * happily treat the predicates as racy, atomic checks as userspace
3854 * cannot claim and pin a new fb without at least acquring the
3855 * struct_mutex and so serialising with us.
3856 */
d3fcc808 3857 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3858 if (atomic_read(&crtc->unpin_work_count) == 0)
3859 continue;
3860
3861 if (crtc->unpin_work)
3862 intel_wait_for_vblank(dev, crtc->pipe);
3863
3864 return true;
3865 }
3866
3867 return false;
3868}
3869
d6bbafa1
CW		 3870static void page_flip_completed(struct intel_crtc *intel_crtc)
3871{
3872 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3873 struct intel_unpin_work *work = intel_crtc->unpin_work;
3874
3875 /* ensure that the unpin work is consistent wrt ->pending. */
3876 smp_rmb();
3877 intel_crtc->unpin_work = NULL;
3878
3879 if (work->event)
3880 drm_send_vblank_event(intel_crtc->base.dev,
3881 intel_crtc->pipe,
3882 work->event);
3883
3884 drm_crtc_vblank_put(&intel_crtc->base);
3885
3886 wake_up_all(&dev_priv->pending_flip_queue);
3887 queue_work(dev_priv->wq, &work->work);
3888
3889 trace_i915_flip_complete(intel_crtc->plane,
3890 work->pending_flip_obj);
3891}
3892
46a55d30 3893void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3894{
0f91128d 3895 struct drm_device *dev = crtc->dev;
5bb61643 3896 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3897
2c10d571 3898 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3899 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3900 !intel_crtc_has_pending_flip(crtc),
3901 60*HZ) == 0)) {
3902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3903
5e2d7afc 3904 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3905 if (intel_crtc->unpin_work) {
3906 WARN_ONCE(1, "Removing stuck page flip\n");
3907 page_flip_completed(intel_crtc);
3908 }
5e2d7afc 3909 spin_unlock_irq(&dev->event_lock);
9c787942 3910 }
5bb61643 3911
975d568a
CW		 3912 if (crtc->primary->fb) {
3913 mutex_lock(&dev->struct_mutex);
3914 intel_finish_fb(crtc->primary->fb);
3915 mutex_unlock(&dev->struct_mutex);
3916 }
e6c3a2a6
CW		 3917}
3918
e615efe4
ED		 3919/* Program iCLKIP clock to the desired frequency */
3920static void lpt_program_iclkip(struct drm_crtc *crtc)
3921{
3922 struct drm_device *dev = crtc->dev;
3923 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3924 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3925 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3926 u32 temp;
3927
a580516d 3928 mutex_lock(&dev_priv->sb_lock);
09153000 3929
e615efe4
ED		 3930 /* It is necessary to ungate the pixclk gate prior to programming
3931 * the divisors, and gate it back when it is done.
3932 */
3933 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3934
3935 /* Disable SSCCTL */
3936 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3937 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3938 SBI_SSCCTL_DISABLE,
3939 SBI_ICLK);
e615efe4
ED		 3940
3941 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3942 if (clock == 20000) {
e615efe4
ED		 3943 auxdiv = 1;
3944 divsel = 0x41;
3945 phaseinc = 0x20;
3946 } else {
3947 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3948 * but the adjusted_mode->crtc_clock in in KHz. To get the
3949 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3950 * convert the virtual clock precision to KHz here for higher
3951 * precision.
3952 */
3953 u32 iclk_virtual_root_freq = 172800 * 1000;
3954 u32 iclk_pi_range = 64;
3955 u32 desired_divisor, msb_divisor_value, pi_value;
3956
12d7ceed 3957 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3958 msb_divisor_value = desired_divisor / iclk_pi_range;
3959 pi_value = desired_divisor % iclk_pi_range;
3960
3961 auxdiv = 0;
3962 divsel = msb_divisor_value - 2;
3963 phaseinc = pi_value;
3964 }
3965
3966 /* This should not happen with any sane values */
3967 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3968 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3969 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3970 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3971
3972 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3973 clock,
e615efe4
ED		 3974 auxdiv,
3975 divsel,
3976 phasedir,
3977 phaseinc);
3978
3979 /* Program SSCDIVINTPHASE6 */
988d6ee8 3980 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3981 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3982 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3983 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3984 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3985 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3986 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3987 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3988
3989 /* Program SSCAUXDIV */
988d6ee8 3990 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3991 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3992 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3993 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3994
3995 /* Enable modulator and associated divider */
988d6ee8 3996 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3997 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3998 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3999
4000 /* Wait for initialization time */
4001 udelay(24);
4002
4003 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4004
a580516d 4005 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4006}
4007
275f01b2
DV		 4008static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4009 enum pipe pch_transcoder)
4010{
4011 struct drm_device *dev = crtc->base.dev;
4012 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4013 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4014
4015 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4016 I915_READ(HTOTAL(cpu_transcoder)));
4017 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4018 I915_READ(HBLANK(cpu_transcoder)));
4019 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4020 I915_READ(HSYNC(cpu_transcoder)));
4021
4022 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4023 I915_READ(VTOTAL(cpu_transcoder)));
4024 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4025 I915_READ(VBLANK(cpu_transcoder)));
4026 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4027 I915_READ(VSYNC(cpu_transcoder)));
4028 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4029 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4030}
4031
003632d9 4032static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4033{
4034 struct drm_i915_private *dev_priv = dev->dev_private;
4035 uint32_t temp;
4036
4037 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4038 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4039 return;
4040
4041 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4042 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4043
003632d9
ACO		 4044 temp &= ~FDI_BC_BIFURCATION_SELECT;
4045 if (enable)
4046 temp |= FDI_BC_BIFURCATION_SELECT;
4047
4048 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4049 I915_WRITE(SOUTH_CHICKEN1, temp);
4050 POSTING_READ(SOUTH_CHICKEN1);
4051}
4052
4053static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4054{
4055 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4056
4057 switch (intel_crtc->pipe) {
4058 case PIPE_A:
4059 break;
4060 case PIPE_B:
6e3c9717 4061 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4062 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4063 else
003632d9 4064 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4065
4066 break;
4067 case PIPE_C:
003632d9 4068 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4069
4070 break;
4071 default:
4072 BUG();
4073 }
4074}
4075
f67a559d
JB		 4076/*
4077 * Enable PCH resources required for PCH ports:
4078 * - PCH PLLs
4079 * - FDI training & RX/TX
4080 * - update transcoder timings
4081 * - DP transcoding bits
4082 * - transcoder
4083 */
4084static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4085{
4086 struct drm_device *dev = crtc->dev;
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089 int pipe = intel_crtc->pipe;
ee7b9f93 4090 u32 reg, temp;
2c07245f 4091
ab9412ba 4092 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4093
1fbc0d78
DV		 4094 if (IS_IVYBRIDGE(dev))
4095 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4096
cd986abb
DV		 4097 /* Write the TU size bits before fdi link training, so that error
4098 * detection works. */
4099 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4100 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4101
c98e9dcf 4102 /* For PCH output, training FDI link */
674cf967 4103 dev_priv->display.fdi_link_train(crtc);
2c07245f 4104
3ad8a208
DV		 4105 /* We need to program the right clock selection before writing the pixel
4106 * mutliplier into the DPLL. */
303b81e0 4107 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4108 u32 sel;
4b645f14 4109
c98e9dcf 4110 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4111 temp |= TRANS_DPLL_ENABLE(pipe);
4112 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4113 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4114 temp |= sel;
4115 else
4116 temp &= ~sel;
c98e9dcf 4117 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4118 }
5eddb70b 4119
3ad8a208
DV		 4120 /* XXX: pch pll's can be enabled any time before we enable the PCH
4121 * transcoder, and we actually should do this to not upset any PCH
4122 * transcoder that already use the clock when we share it.
4123 *
4124 * Note that enable_shared_dpll tries to do the right thing, but
4125 * get_shared_dpll unconditionally resets the pll - we need that to have
4126 * the right LVDS enable sequence. */
85b3894f 4127 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4128
d9b6cb56
JB		 4129 /* set transcoder timing, panel must allow it */
4130 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4131 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4132
303b81e0 4133 intel_fdi_normal_train(crtc);
5e84e1a4 4134
c98e9dcf 4135 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4136 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4137 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4138 reg = TRANS_DP_CTL(pipe);
4139 temp = I915_READ(reg);
4140 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4141 TRANS_DP_SYNC_MASK |
4142 TRANS_DP_BPC_MASK);
e3ef4479 4143 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4144 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4145
4146 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4147 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4148 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4149 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4150
4151 switch (intel_trans_dp_port_sel(crtc)) {
4152 case PCH_DP_B:
5eddb70b 4153 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4154 break;
4155 case PCH_DP_C:
5eddb70b 4156 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4157 break;
4158 case PCH_DP_D:
5eddb70b 4159 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4160 break;
4161 default:
e95d41e1 4162 BUG();
32f9d658 4163 }
2c07245f 4164
5eddb70b 4165 I915_WRITE(reg, temp);
6be4a607 4166 }
b52eb4dc 4167
b8a4f404 4168 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4169}
4170
1507e5bd
PZ		 4171static void lpt_pch_enable(struct drm_crtc *crtc)
4172{
4173 struct drm_device *dev = crtc->dev;
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4176 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4177
ab9412ba 4178 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4179
8c52b5e8 4180 lpt_program_iclkip(crtc);
1507e5bd 4181
0540e488 4182 /* Set transcoder timing. */
275f01b2 4183 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4184
937bb610 4185 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4186}
4187
190f68c5
ACO		 4188struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4189 struct intel_crtc_state *crtc_state)
ee7b9f93 4190{
e2b78267 4191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4192 struct intel_shared_dpll *pll;
de419ab6 4193 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4194 enum intel_dpll_id i;
ee7b9f93 4195
de419ab6
ML		 4196 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4197
98b6bd99
DV		 4198 if (HAS_PCH_IBX(dev_priv->dev)) {
4199 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4200 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4201 pll = &dev_priv->shared_dplls[i];
98b6bd99 4202
46edb027
DV		 4203 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4204 crtc->base.base.id, pll->name);
98b6bd99 4205
de419ab6 4206 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4207
98b6bd99
DV		 4208 goto found;
4209 }
4210
bcddf610
S		 4211 if (IS_BROXTON(dev_priv->dev)) {
4212 /* PLL is attached to port in bxt */
4213 struct intel_encoder *encoder;
4214 struct intel_digital_port *intel_dig_port;
4215
4216 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4217 if (WARN_ON(!encoder))
4218 return NULL;
4219
4220 intel_dig_port = enc_to_dig_port(&encoder->base);
4221 /* 1:1 mapping between ports and PLLs */
4222 i = (enum intel_dpll_id)intel_dig_port->port;
4223 pll = &dev_priv->shared_dplls[i];
4224 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4225 crtc->base.base.id, pll->name);
de419ab6 4226 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4227
4228 goto found;
4229 }
4230
e72f9fbf
DV		 4231 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4232 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4233
4234 /* Only want to check enabled timings first */
de419ab6 4235 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4236 continue;
4237
190f68c5 4238 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4239 &shared_dpll[i].hw_state,
4240 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4241 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4242 crtc->base.base.id, pll->name,
de419ab6 4243 shared_dpll[i].crtc_mask,
8bd31e67 4244 pll->active);
ee7b9f93
JB		 4245 goto found;
4246 }
4247 }
4248
4249 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4250 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4251 pll = &dev_priv->shared_dplls[i];
de419ab6 4252 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4253 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4254 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4255 goto found;
4256 }
4257 }
4258
4259 return NULL;
4260
4261found:
de419ab6
ML		 4262 if (shared_dpll[i].crtc_mask == 0)
4263 shared_dpll[i].hw_state =
4264 crtc_state->dpll_hw_state;
f2a69f44 4265
190f68c5 4266 crtc_state->shared_dpll = i;
46edb027
DV		 4267 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4268 pipe_name(crtc->pipe));
ee7b9f93 4269
de419ab6 4270 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4271
ee7b9f93
JB		 4272 return pll;
4273}
4274
de419ab6 4275static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4276{
de419ab6
ML		 4277 struct drm_i915_private *dev_priv = to_i915(state->dev);
4278 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4279 struct intel_shared_dpll *pll;
4280 enum intel_dpll_id i;
4281
de419ab6
ML		 4282 if (!to_intel_atomic_state(state)->dpll_set)
4283 return;
8bd31e67 4284
de419ab6 4285 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4286 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4287 pll = &dev_priv->shared_dplls[i];
de419ab6 4288 pll->config = shared_dpll[i];
8bd31e67
ACO		 4289 }
4290}
4291
a1520318 4292static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4293{
4294 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4295 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4296 u32 temp;
4297
4298 temp = I915_READ(dslreg);
4299 udelay(500);
4300 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4301 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4302 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4303 }
4304}
4305
86adf9d7
ML		 4306static int
4307skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4308 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4309 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4310{
86adf9d7
ML		 4311 struct intel_crtc_scaler_state *scaler_state =
4312 &crtc_state->scaler_state;
4313 struct intel_crtc *intel_crtc =
4314 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4315 int need_scaling;
6156a456
CK		 4316
4317 need_scaling = intel_rotation_90_or_270(rotation) ?
4318 (src_h != dst_w || src_w != dst_h):
4319 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4320
4321 /*
4322 * if plane is being disabled or scaler is no more required or force detach
4323 * - free scaler binded to this plane/crtc
4324 * - in order to do this, update crtc->scaler_usage
4325 *
4326 * Here scaler state in crtc_state is set free so that
4327 * scaler can be assigned to other user. Actual register
4328 * update to free the scaler is done in plane/panel-fit programming.
4329 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4330 */
86adf9d7 4331 if (force_detach || !need_scaling) {
a1b2278e 4332 if (*scaler_id >= 0) {
86adf9d7 4333 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4334 scaler_state->scalers[*scaler_id].in_use = 0;
4335
86adf9d7
ML		 4336 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4337 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4338 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4339 scaler_state->scaler_users);
4340 *scaler_id = -1;
4341 }
4342 return 0;
4343 }
4344
4345 /* range checks */
4346 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4347 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4348
4349 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4350 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4351 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4352 "size is out of scaler range\n",
86adf9d7 4353 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4354 return -EINVAL;
4355 }
4356
86adf9d7
ML		 4357 /* mark this plane as a scaler user in crtc_state */
4358 scaler_state->scaler_users |= (1 << scaler_user);
4359 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4360 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4361 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4362 scaler_state->scaler_users);
4363
4364 return 0;
4365}
4366
4367/**
4368 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4369 *
4370 * @state: crtc's scaler state
86adf9d7
ML		 4371 *
4372 * Return
4373 * 0 - scaler_usage updated successfully
4374 * error - requested scaling cannot be supported or other error condition
4375 */
e435d6e5 4376int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4377{
4378 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4379 struct drm_display_mode *adjusted_mode =
4380 &state->base.adjusted_mode;
4381
4382 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4383 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4384
e435d6e5 4385 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4386 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4387 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4388 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4389}
4390
4391/**
4392 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4393 *
4394 * @state: crtc's scaler state
86adf9d7
ML		 4395 * @plane_state: atomic plane state to update
4396 *
4397 * Return
4398 * 0 - scaler_usage updated successfully
4399 * error - requested scaling cannot be supported or other error condition
4400 */
da20eabd
ML		 4401static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4402 struct intel_plane_state *plane_state)
86adf9d7
ML		 4403{
4404
4405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4406 struct intel_plane *intel_plane =
4407 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4408 struct drm_framebuffer *fb = plane_state->base.fb;
4409 int ret;
4410
4411 bool force_detach = !fb || !plane_state->visible;
4412
4413 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4414 intel_plane->base.base.id, intel_crtc->pipe,
4415 drm_plane_index(&intel_plane->base));
4416
4417 ret = skl_update_scaler(crtc_state, force_detach,
4418 drm_plane_index(&intel_plane->base),
4419 &plane_state->scaler_id,
4420 plane_state->base.rotation,
4421 drm_rect_width(&plane_state->src) >> 16,
4422 drm_rect_height(&plane_state->src) >> 16,
4423 drm_rect_width(&plane_state->dst),
4424 drm_rect_height(&plane_state->dst));
4425
4426 if (ret || plane_state->scaler_id < 0)
4427 return ret;
4428
a1b2278e 4429 /* check colorkey */
818ed961 4430 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4431 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4432 intel_plane->base.base.id);
a1b2278e
CK		 4433 return -EINVAL;
4434 }
4435
4436 /* Check src format */
86adf9d7
ML		 4437 switch (fb->pixel_format) {
4438 case DRM_FORMAT_RGB565:
4439 case DRM_FORMAT_XBGR8888:
4440 case DRM_FORMAT_XRGB8888:
4441 case DRM_FORMAT_ABGR8888:
4442 case DRM_FORMAT_ARGB8888:
4443 case DRM_FORMAT_XRGB2101010:
4444 case DRM_FORMAT_XBGR2101010:
4445 case DRM_FORMAT_YUYV:
4446 case DRM_FORMAT_YVYU:
4447 case DRM_FORMAT_UYVY:
4448 case DRM_FORMAT_VYUY:
4449 break;
4450 default:
4451 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4452 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4453 return -EINVAL;
a1b2278e
CK		 4454 }
4455
a1b2278e
CK		 4456 return 0;
4457}
4458
e435d6e5
ML		 4459static void skylake_scaler_disable(struct intel_crtc *crtc)
4460{
4461 int i;
4462
4463 for (i = 0; i < crtc->num_scalers; i++)
4464 skl_detach_scaler(crtc, i);
4465}
4466
4467static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4468{
4469 struct drm_device *dev = crtc->base.dev;
4470 struct drm_i915_private *dev_priv = dev->dev_private;
4471 int pipe = crtc->pipe;
a1b2278e
CK		 4472 struct intel_crtc_scaler_state *scaler_state =
4473 &crtc->config->scaler_state;
4474
4475 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4476
6e3c9717 4477 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4478 int id;
4479
4480 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4481 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4482 return;
4483 }
4484
4485 id = scaler_state->scaler_id;
4486 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4487 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4488 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4489 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4490
4491 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4492 }
4493}
4494
b074cec8
JB		 4495static void ironlake_pfit_enable(struct intel_crtc *crtc)
4496{
4497 struct drm_device *dev = crtc->base.dev;
4498 struct drm_i915_private *dev_priv = dev->dev_private;
4499 int pipe = crtc->pipe;
4500
6e3c9717 4501 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4502 /* Force use of hard-coded filter coefficients
4503 * as some pre-programmed values are broken,
4504 * e.g. x201.
4505 */
4506 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4507 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4508 PF_PIPE_SEL_IVB(pipe));
4509 else
4510 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4511 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4512 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4513 }
4514}
4515
20bc8673 4516void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4517{
cea165c3
VS		 4518 struct drm_device *dev = crtc->base.dev;
4519 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4520
6e3c9717 4521 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4522 return;
4523
cea165c3
VS		 4524 /* We can only enable IPS after we enable a plane and wait for a vblank */
4525 intel_wait_for_vblank(dev, crtc->pipe);
4526
d77e4531 4527 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4528 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4529 mutex_lock(&dev_priv->rps.hw_lock);
4530 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4531 mutex_unlock(&dev_priv->rps.hw_lock);
4532 /* Quoting Art Runyan: "its not safe to expect any particular
4533 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4534 * mailbox." Moreover, the mailbox may return a bogus state,
4535 * so we need to just enable it and continue on.
2a114cc1
BW		 4536 */
4537 } else {
4538 I915_WRITE(IPS_CTL, IPS_ENABLE);
4539 /* The bit only becomes 1 in the next vblank, so this wait here
4540 * is essentially intel_wait_for_vblank. If we don't have this
4541 * and don't wait for vblanks until the end of crtc_enable, then
4542 * the HW state readout code will complain that the expected
4543 * IPS_CTL value is not the one we read. */
4544 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4545 DRM_ERROR("Timed out waiting for IPS enable\n");
4546 }
d77e4531
PZ		 4547}
4548
20bc8673 4549void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4550{
4551 struct drm_device *dev = crtc->base.dev;
4552 struct drm_i915_private *dev_priv = dev->dev_private;
4553
6e3c9717 4554 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4555 return;
4556
4557 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4558 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4559 mutex_lock(&dev_priv->rps.hw_lock);
4560 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4561 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4562 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4563 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4564 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4565 } else {
2a114cc1 4566 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4567 POSTING_READ(IPS_CTL);
4568 }
d77e4531
PZ		 4569
4570 /* We need to wait for a vblank before we can disable the plane. */
4571 intel_wait_for_vblank(dev, crtc->pipe);
4572}
4573
4574/** Loads the palette/gamma unit for the CRTC with the prepared values */
4575static void intel_crtc_load_lut(struct drm_crtc *crtc)
4576{
4577 struct drm_device *dev = crtc->dev;
4578 struct drm_i915_private *dev_priv = dev->dev_private;
4579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4580 enum pipe pipe = intel_crtc->pipe;
4581 int palreg = PALETTE(pipe);
4582 int i;
4583 bool reenable_ips = false;
4584
4585 /* The clocks have to be on to load the palette. */
53d9f4e9 4586 if (!crtc->state->active)
d77e4531
PZ		 4587 return;
4588
50360403 4589 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4590 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4591 assert_dsi_pll_enabled(dev_priv);
4592 else
4593 assert_pll_enabled(dev_priv, pipe);
4594 }
4595
4596 /* use legacy palette for Ironlake */
7a1db49a 4597 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4598 palreg = LGC_PALETTE(pipe);
4599
4600 /* Workaround : Do not read or write the pipe palette/gamma data while
4601 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4602 */
6e3c9717 4603 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4604 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4605 GAMMA_MODE_MODE_SPLIT)) {
4606 hsw_disable_ips(intel_crtc);
4607 reenable_ips = true;
4608 }
4609
4610 for (i = 0; i < 256; i++) {
4611 I915_WRITE(palreg + 4 * i,
4612 (intel_crtc->lut_r[i] << 16) |
4613 (intel_crtc->lut_g[i] << 8) |
4614 intel_crtc->lut_b[i]);
4615 }
4616
4617 if (reenable_ips)
4618 hsw_enable_ips(intel_crtc);
4619}
4620
7cac945f 4621static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4622{
7cac945f 4623 if (intel_crtc->overlay) {
d3eedb1a
VS		 4624 struct drm_device *dev = intel_crtc->base.dev;
4625 struct drm_i915_private *dev_priv = dev->dev_private;
4626
4627 mutex_lock(&dev->struct_mutex);
4628 dev_priv->mm.interruptible = false;
4629 (void) intel_overlay_switch_off(intel_crtc->overlay);
4630 dev_priv->mm.interruptible = true;
4631 mutex_unlock(&dev->struct_mutex);
4632 }
4633
4634 /* Let userspace switch the overlay on again. In most cases userspace
4635 * has to recompute where to put it anyway.
4636 */
4637}
4638
87d4300a
ML		 4639/**
4640 * intel_post_enable_primary - Perform operations after enabling primary plane
4641 * @crtc: the CRTC whose primary plane was just enabled
4642 *
4643 * Performs potentially sleeping operations that must be done after the primary
4644 * plane is enabled, such as updating FBC and IPS. Note that this may be
4645 * called due to an explicit primary plane update, or due to an implicit
4646 * re-enable that is caused when a sprite plane is updated to no longer
4647 * completely hide the primary plane.
4648 */
4649static void
4650intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4651{
4652 struct drm_device *dev = crtc->dev;
87d4300a 4653 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4655 int pipe = intel_crtc->pipe;
a5c4d7bc 4656
87d4300a
ML		 4657 /*
4658 * BDW signals flip done immediately if the plane
4659 * is disabled, even if the plane enable is already
4660 * armed to occur at the next vblank :(
4661 */
4662 if (IS_BROADWELL(dev))
4663 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4664
87d4300a
ML		 4665 /*
4666 * FIXME IPS should be fine as long as one plane is
4667 * enabled, but in practice it seems to have problems
4668 * when going from primary only to sprite only and vice
4669 * versa.
4670 */
a5c4d7bc
VS		 4671 hsw_enable_ips(intel_crtc);
4672
f99d7069 4673 /*
87d4300a
ML		 4674 * Gen2 reports pipe underruns whenever all planes are disabled.
4675 * So don't enable underrun reporting before at least some planes
4676 * are enabled.
4677 * FIXME: Need to fix the logic to work when we turn off all planes
4678 * but leave the pipe running.
f99d7069 4679 */
87d4300a
ML		 4680 if (IS_GEN2(dev))
4681 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4682
4683 /* Underruns don't raise interrupts, so check manually. */
4684 if (HAS_GMCH_DISPLAY(dev))
4685 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4686}
4687
87d4300a
ML		 4688/**
4689 * intel_pre_disable_primary - Perform operations before disabling primary plane
4690 * @crtc: the CRTC whose primary plane is to be disabled
4691 *
4692 * Performs potentially sleeping operations that must be done before the
4693 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4694 * be called due to an explicit primary plane update, or due to an implicit
4695 * disable that is caused when a sprite plane completely hides the primary
4696 * plane.
4697 */
4698static void
4699intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4700{
4701 struct drm_device *dev = crtc->dev;
4702 struct drm_i915_private *dev_priv = dev->dev_private;
4703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4704 int pipe = intel_crtc->pipe;
a5c4d7bc 4705
87d4300a
ML		 4706 /*
4707 * Gen2 reports pipe underruns whenever all planes are disabled.
4708 * So diasble underrun reporting before all the planes get disabled.
4709 * FIXME: Need to fix the logic to work when we turn off all planes
4710 * but leave the pipe running.
4711 */
4712 if (IS_GEN2(dev))
4713 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4714
87d4300a
ML		 4715 /*
4716 * Vblank time updates from the shadow to live plane control register
4717 * are blocked if the memory self-refresh mode is active at that
4718 * moment. So to make sure the plane gets truly disabled, disable
4719 * first the self-refresh mode. The self-refresh enable bit in turn
4720 * will be checked/applied by the HW only at the next frame start
4721 * event which is after the vblank start event, so we need to have a
4722 * wait-for-vblank between disabling the plane and the pipe.
4723 */
262cd2e1 4724 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4725 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4726 dev_priv->wm.vlv.cxsr = false;
4727 intel_wait_for_vblank(dev, pipe);
4728 }
87d4300a 4729
87d4300a
ML		 4730 /*
4731 * FIXME IPS should be fine as long as one plane is
4732 * enabled, but in practice it seems to have problems
4733 * when going from primary only to sprite only and vice
4734 * versa.
4735 */
a5c4d7bc 4736 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4737}
4738
ac21b225
ML		 4739static void intel_post_plane_update(struct intel_crtc *crtc)
4740{
4741 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4742 struct drm_device *dev = crtc->base.dev;
7733b49b 4743 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4744 struct drm_plane *plane;
4745
4746 if (atomic->wait_vblank)
4747 intel_wait_for_vblank(dev, crtc->pipe);
4748
4749 intel_frontbuffer_flip(dev, atomic->fb_bits);
4750
852eb00d
VS		 4751 if (atomic->disable_cxsr)
4752 crtc->wm.cxsr_allowed = true;
4753
f015c551
VS		 4754 if (crtc->atomic.update_wm_post)
4755 intel_update_watermarks(&crtc->base);
4756
c80ac854 4757 if (atomic->update_fbc)
7733b49b 4758 intel_fbc_update(dev_priv);
ac21b225
ML		 4759
4760 if (atomic->post_enable_primary)
4761 intel_post_enable_primary(&crtc->base);
4762
4763 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4764 intel_update_sprite_watermarks(plane, &crtc->base,
4765 0, 0, 0, false, false);
4766
4767 memset(atomic, 0, sizeof(*atomic));
4768}
4769
4770static void intel_pre_plane_update(struct intel_crtc *crtc)
4771{
4772 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4773 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4774 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4775 struct drm_plane *p;
4776
4777 /* Track fb's for any planes being disabled */
ac21b225
ML		 4778 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4779 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4780
4781 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4782 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4783 plane->frontbuffer_bit);
ac21b225
ML		 4784 mutex_unlock(&dev->struct_mutex);
4785 }
4786
4787 if (atomic->wait_for_flips)
4788 intel_crtc_wait_for_pending_flips(&crtc->base);
4789
c80ac854 4790 if (atomic->disable_fbc)
25ad93fd 4791 intel_fbc_disable_crtc(crtc);
ac21b225 4792
066cf55b
RV		 4793 if (crtc->atomic.disable_ips)
4794 hsw_disable_ips(crtc);
4795
ac21b225
ML		 4796 if (atomic->pre_disable_primary)
4797 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4798
4799 if (atomic->disable_cxsr) {
4800 crtc->wm.cxsr_allowed = false;
4801 intel_set_memory_cxsr(dev_priv, false);
4802 }
ac21b225
ML		 4803}
4804
d032ffa0 4805static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4806{
4807 struct drm_device *dev = crtc->dev;
4808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4809 struct drm_plane *p;
87d4300a
ML		 4810 int pipe = intel_crtc->pipe;
4811
7cac945f 4812 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4813
d032ffa0
ML		 4814 drm_for_each_plane_mask(p, dev, plane_mask)
4815 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4816
f99d7069
DV		 4817 /*
4818 * FIXME: Once we grow proper nuclear flip support out of this we need
4819 * to compute the mask of flip planes precisely. For the time being
4820 * consider this a flip to a NULL plane.
4821 */
4822 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4823}
4824
f67a559d
JB		 4825static void ironlake_crtc_enable(struct drm_crtc *crtc)
4826{
4827 struct drm_device *dev = crtc->dev;
4828 struct drm_i915_private *dev_priv = dev->dev_private;
4829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4830 struct intel_encoder *encoder;
f67a559d 4831 int pipe = intel_crtc->pipe;
f67a559d 4832
53d9f4e9 4833 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4834 return;
4835
6e3c9717 4836 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4837 intel_prepare_shared_dpll(intel_crtc);
4838
6e3c9717 4839 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4840 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4841
4842 intel_set_pipe_timings(intel_crtc);
4843
6e3c9717 4844 if (intel_crtc->config->has_pch_encoder) {
29407aab 4845 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4846 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4847 }
4848
4849 ironlake_set_pipeconf(crtc);
4850
f67a559d 4851 intel_crtc->active = true;
8664281b 4852
a72e4c9f
DV		 4853 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4854 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4855
f6736a1a 4856 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4857 if (encoder->pre_enable)
4858 encoder->pre_enable(encoder);
f67a559d 4859
6e3c9717 4860 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4861 /* Note: FDI PLL enabling _must_ be done before we enable the
4862 * cpu pipes, hence this is separate from all the other fdi/pch
4863 * enabling. */
88cefb6c 4864 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4865 } else {
4866 assert_fdi_tx_disabled(dev_priv, pipe);
4867 assert_fdi_rx_disabled(dev_priv, pipe);
4868 }
f67a559d 4869
b074cec8 4870 ironlake_pfit_enable(intel_crtc);
f67a559d 4871
9c54c0dd
JB		 4872 /*
4873 * On ILK+ LUT must be loaded before the pipe is running but with
4874 * clocks enabled
4875 */
4876 intel_crtc_load_lut(crtc);
4877
f37fcc2a 4878 intel_update_watermarks(crtc);
e1fdc473 4879 intel_enable_pipe(intel_crtc);
f67a559d 4880
6e3c9717 4881 if (intel_crtc->config->has_pch_encoder)
f67a559d 4882 ironlake_pch_enable(crtc);
c98e9dcf 4883
f9b61ff6
DV		 4884 assert_vblank_disabled(crtc);
4885 drm_crtc_vblank_on(crtc);
4886
fa5c73b1
DV		 4887 for_each_encoder_on_crtc(dev, crtc, encoder)
4888 encoder->enable(encoder);
61b77ddd
DV		 4889
4890 if (HAS_PCH_CPT(dev))
a1520318 4891 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4892}
4893
42db64ef
PZ		 4894/* IPS only exists on ULT machines and is tied to pipe A. */
4895static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4896{
f5adf94e 4897 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4898}
4899
4f771f10
PZ		 4900static void haswell_crtc_enable(struct drm_crtc *crtc)
4901{
4902 struct drm_device *dev = crtc->dev;
4903 struct drm_i915_private *dev_priv = dev->dev_private;
4904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4905 struct intel_encoder *encoder;
99d736a2
ML		 4906 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4907 struct intel_crtc_state *pipe_config =
4908 to_intel_crtc_state(crtc->state);
4f771f10 4909
53d9f4e9 4910 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4911 return;
4912
df8ad70c
DV		 4913 if (intel_crtc_to_shared_dpll(intel_crtc))
4914 intel_enable_shared_dpll(intel_crtc);
4915
6e3c9717 4916 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4917 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4918
4919 intel_set_pipe_timings(intel_crtc);
4920
6e3c9717
ACO		 4921 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4922 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4923 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4924 }
4925
6e3c9717 4926 if (intel_crtc->config->has_pch_encoder) {
229fca97 4927 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4928 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4929 }
4930
4931 haswell_set_pipeconf(crtc);
4932
4933 intel_set_pipe_csc(crtc);
4934
4f771f10 4935 intel_crtc->active = true;
8664281b 4936
a72e4c9f 4937 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4938 for_each_encoder_on_crtc(dev, crtc, encoder)
4939 if (encoder->pre_enable)
4940 encoder->pre_enable(encoder);
4941
6e3c9717 4942 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4943 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4944 true);
4fe9467d
ID		 4945 dev_priv->display.fdi_link_train(crtc);
4946 }
4947
1f544388 4948 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4949
ff6d9f55 4950 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 4951 skylake_pfit_enable(intel_crtc);
ff6d9f55 4952 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4953 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4954 else
4955 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4956
4957 /*
4958 * On ILK+ LUT must be loaded before the pipe is running but with
4959 * clocks enabled
4960 */
4961 intel_crtc_load_lut(crtc);
4962
1f544388 4963 intel_ddi_set_pipe_settings(crtc);
8228c251 4964 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4965
f37fcc2a 4966 intel_update_watermarks(crtc);
e1fdc473 4967 intel_enable_pipe(intel_crtc);
42db64ef 4968
6e3c9717 4969 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4970 lpt_pch_enable(crtc);
4f771f10 4971
6e3c9717 4972 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4973 intel_ddi_set_vc_payload_alloc(crtc, true);
4974
f9b61ff6
DV		 4975 assert_vblank_disabled(crtc);
4976 drm_crtc_vblank_on(crtc);
4977
8807e55b 4978 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4979 encoder->enable(encoder);
8807e55b
JN		 4980 intel_opregion_notify_encoder(encoder, true);
4981 }
4f771f10 4982
e4916946
PZ		 4983 /* If we change the relative order between pipe/planes enabling, we need
4984 * to change the workaround. */
99d736a2
ML		 4985 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4986 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4987 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4988 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4989 }
4f771f10
PZ		 4990}
4991
3f8dce3a
DV		 4992static void ironlake_pfit_disable(struct intel_crtc *crtc)
4993{
4994 struct drm_device *dev = crtc->base.dev;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996 int pipe = crtc->pipe;
4997
4998 /* To avoid upsetting the power well on haswell only disable the pfit if
4999 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5000 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5001 I915_WRITE(PF_CTL(pipe), 0);
5002 I915_WRITE(PF_WIN_POS(pipe), 0);
5003 I915_WRITE(PF_WIN_SZ(pipe), 0);
5004 }
5005}
5006
6be4a607
JB		 5007static void ironlake_crtc_disable(struct drm_crtc *crtc)
5008{
5009 struct drm_device *dev = crtc->dev;
5010 struct drm_i915_private *dev_priv = dev->dev_private;
5011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5012 struct intel_encoder *encoder;
6be4a607 5013 int pipe = intel_crtc->pipe;
5eddb70b 5014 u32 reg, temp;
b52eb4dc 5015
ea9d758d
DV		 5016 for_each_encoder_on_crtc(dev, crtc, encoder)
5017 encoder->disable(encoder);
5018
f9b61ff6
DV		 5019 drm_crtc_vblank_off(crtc);
5020 assert_vblank_disabled(crtc);
5021
6e3c9717 5022 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5023 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5024
575f7ab7 5025 intel_disable_pipe(intel_crtc);
32f9d658 5026
3f8dce3a 5027 ironlake_pfit_disable(intel_crtc);
2c07245f 5028
5a74f70a
VS		 5029 if (intel_crtc->config->has_pch_encoder)
5030 ironlake_fdi_disable(crtc);
5031
bf49ec8c
DV		 5032 for_each_encoder_on_crtc(dev, crtc, encoder)
5033 if (encoder->post_disable)
5034 encoder->post_disable(encoder);
2c07245f 5035
6e3c9717 5036 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5037 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5038
d925c59a
DV		 5039 if (HAS_PCH_CPT(dev)) {
5040 /* disable TRANS_DP_CTL */
5041 reg = TRANS_DP_CTL(pipe);
5042 temp = I915_READ(reg);
5043 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5044 TRANS_DP_PORT_SEL_MASK);
5045 temp |= TRANS_DP_PORT_SEL_NONE;
5046 I915_WRITE(reg, temp);
5047
5048 /* disable DPLL_SEL */
5049 temp = I915_READ(PCH_DPLL_SEL);
11887397 5050 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5051 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5052 }
e3421a18 5053
d925c59a
DV		 5054 ironlake_fdi_pll_disable(intel_crtc);
5055 }
e4ca0612
PJ		 5056
5057 intel_crtc->active = false;
5058 intel_update_watermarks(crtc);
6be4a607 5059}
1b3c7a47 5060
4f771f10 5061static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5062{
4f771f10
PZ		 5063 struct drm_device *dev = crtc->dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5066 struct intel_encoder *encoder;
6e3c9717 5067 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5068
8807e55b
JN		 5069 for_each_encoder_on_crtc(dev, crtc, encoder) {
5070 intel_opregion_notify_encoder(encoder, false);
4f771f10 5071 encoder->disable(encoder);
8807e55b 5072 }
4f771f10 5073
f9b61ff6
DV		 5074 drm_crtc_vblank_off(crtc);
5075 assert_vblank_disabled(crtc);
5076
6e3c9717 5077 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5078 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5079 false);
575f7ab7 5080 intel_disable_pipe(intel_crtc);
4f771f10 5081
6e3c9717 5082 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5083 intel_ddi_set_vc_payload_alloc(crtc, false);
5084
ad80a810 5085 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5086
ff6d9f55 5087 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 5088 skylake_scaler_disable(intel_crtc);
ff6d9f55 5089 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5090 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5091 else
5092 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5093
1f544388 5094 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5095
6e3c9717 5096 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5097 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5098 intel_ddi_fdi_disable(crtc);
83616634 5099 }
4f771f10 5100
97b040aa
ID		 5101 for_each_encoder_on_crtc(dev, crtc, encoder)
5102 if (encoder->post_disable)
5103 encoder->post_disable(encoder);
e4ca0612
PJ		 5104
5105 intel_crtc->active = false;
5106 intel_update_watermarks(crtc);
4f771f10
PZ		 5107}
5108
2dd24552
JB		 5109static void i9xx_pfit_enable(struct intel_crtc *crtc)
5110{
5111 struct drm_device *dev = crtc->base.dev;
5112 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5113 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5114
681a8504 5115 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5116 return;
5117
2dd24552 5118 /*
c0b03411
DV		 5119 * The panel fitter should only be adjusted whilst the pipe is disabled,
5120 * according to register description and PRM.
2dd24552 5121 */
c0b03411
DV		 5122 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5123 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5124
b074cec8
JB		 5125 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5126 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5127
5128 /* Border color in case we don't scale up to the full screen. Black by
5129 * default, change to something else for debugging. */
5130 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5131}
5132
d05410f9
DA		 5133static enum intel_display_power_domain port_to_power_domain(enum port port)
5134{
5135 switch (port) {
5136 case PORT_A:
5137 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5138 case PORT_B:
5139 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5140 case PORT_C:
5141 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5142 case PORT_D:
5143 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5144 default:
5145 WARN_ON_ONCE(1);
5146 return POWER_DOMAIN_PORT_OTHER;
5147 }
5148}
5149
77d22dca
ID		 5150#define for_each_power_domain(domain, mask) \
5151 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5152 if ((1 << (domain)) & (mask))
5153
319be8ae
ID		 5154enum intel_display_power_domain
5155intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5156{
5157 struct drm_device *dev = intel_encoder->base.dev;
5158 struct intel_digital_port *intel_dig_port;
5159
5160 switch (intel_encoder->type) {
5161 case INTEL_OUTPUT_UNKNOWN:
5162 /* Only DDI platforms should ever use this output type */
5163 WARN_ON_ONCE(!HAS_DDI(dev));
5164 case INTEL_OUTPUT_DISPLAYPORT:
5165 case INTEL_OUTPUT_HDMI:
5166 case INTEL_OUTPUT_EDP:
5167 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5168 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5169 case INTEL_OUTPUT_DP_MST:
5170 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5171 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5172 case INTEL_OUTPUT_ANALOG:
5173 return POWER_DOMAIN_PORT_CRT;
5174 case INTEL_OUTPUT_DSI:
5175 return POWER_DOMAIN_PORT_DSI;
5176 default:
5177 return POWER_DOMAIN_PORT_OTHER;
5178 }
5179}
5180
5181static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5182{
319be8ae
ID		 5183 struct drm_device *dev = crtc->dev;
5184 struct intel_encoder *intel_encoder;
5185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5186 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5187 unsigned long mask;
5188 enum transcoder transcoder;
5189
292b990e
ML		 5190 if (!crtc->state->active)
5191 return 0;
5192
77d22dca
ID		 5193 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5194
5195 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5196 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5197 if (intel_crtc->config->pch_pfit.enabled ||
5198 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5199 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5200
319be8ae
ID		 5201 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5202 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5203
77d22dca
ID		 5204 return mask;
5205}
5206
292b990e 5207static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5208{
292b990e
ML		 5209 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5211 enum intel_display_power_domain domain;
5212 unsigned long domains, new_domains, old_domains;
77d22dca 5213
292b990e
ML		 5214 old_domains = intel_crtc->enabled_power_domains;
5215 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
77d22dca 5216
292b990e
ML		 5217 domains = new_domains & ~old_domains;
5218
5219 for_each_power_domain(domain, domains)
5220 intel_display_power_get(dev_priv, domain);
5221
5222 return old_domains & ~new_domains;
5223}
5224
5225static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5226 unsigned long domains)
5227{
5228 enum intel_display_power_domain domain;
5229
5230 for_each_power_domain(domain, domains)
5231 intel_display_power_put(dev_priv, domain);
5232}
77d22dca 5233
292b990e
ML		 5234static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5235{
5236 struct drm_device *dev = state->dev;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 unsigned long put_domains[I915_MAX_PIPES] = {};
5239 struct drm_crtc_state *crtc_state;
5240 struct drm_crtc *crtc;
5241 int i;
77d22dca 5242
292b990e
ML		 5243 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5244 if (needs_modeset(crtc->state))
5245 put_domains[to_intel_crtc(crtc)->pipe] =
5246 modeset_get_crtc_power_domains(crtc);
77d22dca
ID		 5247 }
5248
27c329ed
ML		 5249 if (dev_priv->display.modeset_commit_cdclk) {
5250 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5251
5252 if (cdclk != dev_priv->cdclk_freq &&
5253 !WARN_ON(!state->allow_modeset))
5254 dev_priv->display.modeset_commit_cdclk(state);
5255 }
50f6e502 5256
292b990e
ML		 5257 for (i = 0; i < I915_MAX_PIPES; i++)
5258 if (put_domains[i])
5259 modeset_put_power_domains(dev_priv, put_domains[i]);
77d22dca
ID		 5260}
5261
560a7ae4
DL		 5262static void intel_update_max_cdclk(struct drm_device *dev)
5263{
5264 struct drm_i915_private *dev_priv = dev->dev_private;
5265
5266 if (IS_SKYLAKE(dev)) {
5267 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5268
5269 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5270 dev_priv->max_cdclk_freq = 675000;
5271 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5272 dev_priv->max_cdclk_freq = 540000;
5273 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5274 dev_priv->max_cdclk_freq = 450000;
5275 else
5276 dev_priv->max_cdclk_freq = 337500;
5277 } else if (IS_BROADWELL(dev)) {
5278 /*
5279 * FIXME with extra cooling we can allow
5280 * 540 MHz for ULX and 675 Mhz for ULT.
5281 * How can we know if extra cooling is
5282 * available? PCI ID, VTB, something else?
5283 */
5284 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5285 dev_priv->max_cdclk_freq = 450000;
5286 else if (IS_BDW_ULX(dev))
5287 dev_priv->max_cdclk_freq = 450000;
5288 else if (IS_BDW_ULT(dev))
5289 dev_priv->max_cdclk_freq = 540000;
5290 else
5291 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5292 } else if (IS_CHERRYVIEW(dev)) {
5293 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5294 } else if (IS_VALLEYVIEW(dev)) {
5295 dev_priv->max_cdclk_freq = 400000;
5296 } else {
5297 /* otherwise assume cdclk is fixed */
5298 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5299 }
5300
5301 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5302 dev_priv->max_cdclk_freq);
5303}
5304
5305static void intel_update_cdclk(struct drm_device *dev)
5306{
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5308
5309 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5310 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5311 dev_priv->cdclk_freq);
5312
5313 /*
5314 * Program the gmbus_freq based on the cdclk frequency.
5315 * BSpec erroneously claims we should aim for 4MHz, but
5316 * in fact 1MHz is the correct frequency.
5317 */
5318 if (IS_VALLEYVIEW(dev)) {
5319 /*
5320 * Program the gmbus_freq based on the cdclk frequency.
5321 * BSpec erroneously claims we should aim for 4MHz, but
5322 * in fact 1MHz is the correct frequency.
5323 */
5324 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5325 }
5326
5327 if (dev_priv->max_cdclk_freq == 0)
5328 intel_update_max_cdclk(dev);
5329}
5330
70d0c574 5331static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5332{
5333 struct drm_i915_private *dev_priv = dev->dev_private;
5334 uint32_t divider;
5335 uint32_t ratio;
5336 uint32_t current_freq;
5337 int ret;
5338
5339 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5340 switch (frequency) {
5341 case 144000:
5342 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5343 ratio = BXT_DE_PLL_RATIO(60);
5344 break;
5345 case 288000:
5346 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5347 ratio = BXT_DE_PLL_RATIO(60);
5348 break;
5349 case 384000:
5350 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5351 ratio = BXT_DE_PLL_RATIO(60);
5352 break;
5353 case 576000:
5354 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5355 ratio = BXT_DE_PLL_RATIO(60);
5356 break;
5357 case 624000:
5358 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5359 ratio = BXT_DE_PLL_RATIO(65);
5360 break;
5361 case 19200:
5362 /*
5363 * Bypass frequency with DE PLL disabled. Init ratio, divider
5364 * to suppress GCC warning.
5365 */
5366 ratio = 0;
5367 divider = 0;
5368 break;
5369 default:
5370 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5371
5372 return;
5373 }
5374
5375 mutex_lock(&dev_priv->rps.hw_lock);
5376 /* Inform power controller of upcoming frequency change */
5377 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5378 0x80000000);
5379 mutex_unlock(&dev_priv->rps.hw_lock);
5380
5381 if (ret) {
5382 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5383 ret, frequency);
5384 return;
5385 }
5386
5387 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5388 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5389 current_freq = current_freq * 500 + 1000;
5390
5391 /*
5392 * DE PLL has to be disabled when
5393 * - setting to 19.2MHz (bypass, PLL isn't used)
5394 * - before setting to 624MHz (PLL needs toggling)
5395 * - before setting to any frequency from 624MHz (PLL needs toggling)
5396 */
5397 if (frequency == 19200 || frequency == 624000 ||
5398 current_freq == 624000) {
5399 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5400 /* Timeout 200us */
5401 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5402 1))
5403 DRM_ERROR("timout waiting for DE PLL unlock\n");
5404 }
5405
5406 if (frequency != 19200) {
5407 uint32_t val;
5408
5409 val = I915_READ(BXT_DE_PLL_CTL);
5410 val &= ~BXT_DE_PLL_RATIO_MASK;
5411 val |= ratio;
5412 I915_WRITE(BXT_DE_PLL_CTL, val);
5413
5414 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5415 /* Timeout 200us */
5416 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5417 DRM_ERROR("timeout waiting for DE PLL lock\n");
5418
5419 val = I915_READ(CDCLK_CTL);
5420 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5421 val |= divider;
5422 /*
5423 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5424 * enable otherwise.
5425 */
5426 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5427 if (frequency >= 500000)
5428 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5429
5430 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5431 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5432 val |= (frequency - 1000) / 500;
5433 I915_WRITE(CDCLK_CTL, val);
5434 }
5435
5436 mutex_lock(&dev_priv->rps.hw_lock);
5437 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5438 DIV_ROUND_UP(frequency, 25000));
5439 mutex_unlock(&dev_priv->rps.hw_lock);
5440
5441 if (ret) {
5442 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5443 ret, frequency);
5444 return;
5445 }
5446
a47871bd 5447 intel_update_cdclk(dev);
f8437dd1
VK		 5448}
5449
5450void broxton_init_cdclk(struct drm_device *dev)
5451{
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5453 uint32_t val;
5454
5455 /*
5456 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5457 * or else the reset will hang because there is no PCH to respond.
5458 * Move the handshake programming to initialization sequence.
5459 * Previously was left up to BIOS.
5460 */
5461 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5462 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5463 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5464
5465 /* Enable PG1 for cdclk */
5466 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5467
5468 /* check if cd clock is enabled */
5469 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5470 DRM_DEBUG_KMS("Display already initialized\n");
5471 return;
5472 }
5473
5474 /*
5475 * FIXME:
5476 * - The initial CDCLK needs to be read from VBT.
5477 * Need to make this change after VBT has changes for BXT.
5478 * - check if setting the max (or any) cdclk freq is really necessary
5479 * here, it belongs to modeset time
5480 */
5481 broxton_set_cdclk(dev, 624000);
5482
5483 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5484 POSTING_READ(DBUF_CTL);
5485
f8437dd1
VK		 5486 udelay(10);
5487
5488 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5489 DRM_ERROR("DBuf power enable timeout!\n");
5490}
5491
5492void broxton_uninit_cdclk(struct drm_device *dev)
5493{
5494 struct drm_i915_private *dev_priv = dev->dev_private;
5495
5496 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5497 POSTING_READ(DBUF_CTL);
5498
f8437dd1
VK		 5499 udelay(10);
5500
5501 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5502 DRM_ERROR("DBuf power disable timeout!\n");
5503
5504 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5505 broxton_set_cdclk(dev, 19200);
5506
5507 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5508}
5509
5d96d8af
DL		 5510static const struct skl_cdclk_entry {
5511 unsigned int freq;
5512 unsigned int vco;
5513} skl_cdclk_frequencies[] = {
5514 { .freq = 308570, .vco = 8640 },
5515 { .freq = 337500, .vco = 8100 },
5516 { .freq = 432000, .vco = 8640 },
5517 { .freq = 450000, .vco = 8100 },
5518 { .freq = 540000, .vco = 8100 },
5519 { .freq = 617140, .vco = 8640 },
5520 { .freq = 675000, .vco = 8100 },
5521};
5522
5523static unsigned int skl_cdclk_decimal(unsigned int freq)
5524{
5525 return (freq - 1000) / 500;
5526}
5527
5528static unsigned int skl_cdclk_get_vco(unsigned int freq)
5529{
5530 unsigned int i;
5531
5532 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5533 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5534
5535 if (e->freq == freq)
5536 return e->vco;
5537 }
5538
5539 return 8100;
5540}
5541
5542static void
5543skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5544{
5545 unsigned int min_freq;
5546 u32 val;
5547
5548 /* select the minimum CDCLK before enabling DPLL 0 */
5549 val = I915_READ(CDCLK_CTL);
5550 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5551 val |= CDCLK_FREQ_337_308;
5552
5553 if (required_vco == 8640)
5554 min_freq = 308570;
5555 else
5556 min_freq = 337500;
5557
5558 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5559
5560 I915_WRITE(CDCLK_CTL, val);
5561 POSTING_READ(CDCLK_CTL);
5562
5563 /*
5564 * We always enable DPLL0 with the lowest link rate possible, but still
5565 * taking into account the VCO required to operate the eDP panel at the
5566 * desired frequency. The usual DP link rates operate with a VCO of
5567 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5568 * The modeset code is responsible for the selection of the exact link
5569 * rate later on, with the constraint of choosing a frequency that
5570 * works with required_vco.
5571 */
5572 val = I915_READ(DPLL_CTRL1);
5573
5574 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5575 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5576 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5577 if (required_vco == 8640)
5578 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5579 SKL_DPLL0);
5580 else
5581 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5582 SKL_DPLL0);
5583
5584 I915_WRITE(DPLL_CTRL1, val);
5585 POSTING_READ(DPLL_CTRL1);
5586
5587 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5588
5589 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5590 DRM_ERROR("DPLL0 not locked\n");
5591}
5592
5593static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5594{
5595 int ret;
5596 u32 val;
5597
5598 /* inform PCU we want to change CDCLK */
5599 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5600 mutex_lock(&dev_priv->rps.hw_lock);
5601 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5602 mutex_unlock(&dev_priv->rps.hw_lock);
5603
5604 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5605}
5606
5607static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5608{
5609 unsigned int i;
5610
5611 for (i = 0; i < 15; i++) {
5612 if (skl_cdclk_pcu_ready(dev_priv))
5613 return true;
5614 udelay(10);
5615 }
5616
5617 return false;
5618}
5619
5620static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5621{
560a7ae4 5622 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5623 u32 freq_select, pcu_ack;
5624
5625 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5626
5627 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5628 DRM_ERROR("failed to inform PCU about cdclk change\n");
5629 return;
5630 }
5631
5632 /* set CDCLK_CTL */
5633 switch(freq) {
5634 case 450000:
5635 case 432000:
5636 freq_select = CDCLK_FREQ_450_432;
5637 pcu_ack = 1;
5638 break;
5639 case 540000:
5640 freq_select = CDCLK_FREQ_540;
5641 pcu_ack = 2;
5642 break;
5643 case 308570:
5644 case 337500:
5645 default:
5646 freq_select = CDCLK_FREQ_337_308;
5647 pcu_ack = 0;
5648 break;
5649 case 617140:
5650 case 675000:
5651 freq_select = CDCLK_FREQ_675_617;
5652 pcu_ack = 3;
5653 break;
5654 }
5655
5656 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5657 POSTING_READ(CDCLK_CTL);
5658
5659 /* inform PCU of the change */
5660 mutex_lock(&dev_priv->rps.hw_lock);
5661 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5662 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5663
5664 intel_update_cdclk(dev);
5d96d8af
DL		 5665}
5666
5667void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5668{
5669 /* disable DBUF power */
5670 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5671 POSTING_READ(DBUF_CTL);
5672
5673 udelay(10);
5674
5675 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5676 DRM_ERROR("DBuf power disable timeout\n");
5677
5678 /* disable DPLL0 */
5679 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5680 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5681 DRM_ERROR("Couldn't disable DPLL0\n");
5682
5683 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5684}
5685
5686void skl_init_cdclk(struct drm_i915_private *dev_priv)
5687{
5688 u32 val;
5689 unsigned int required_vco;
5690
5691 /* enable PCH reset handshake */
5692 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5693 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5694
5695 /* enable PG1 and Misc I/O */
5696 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5697
5698 /* DPLL0 already enabed !? */
5699 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5700 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5701 return;
5702 }
5703
5704 /* enable DPLL0 */
5705 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5706 skl_dpll0_enable(dev_priv, required_vco);
5707
5708 /* set CDCLK to the frequency the BIOS chose */
5709 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5710
5711 /* enable DBUF power */
5712 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5713 POSTING_READ(DBUF_CTL);
5714
5715 udelay(10);
5716
5717 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5718 DRM_ERROR("DBuf power enable timeout\n");
5719}
5720
dfcab17e 5721/* returns HPLL frequency in kHz */
f8bf63fd 5722static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5723{
586f49dc 5724 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5725
586f49dc 5726 /* Obtain SKU information */
a580516d 5727 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5728 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5729 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5730 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5731
dfcab17e 5732 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5733}
5734
5735/* Adjust CDclk dividers to allow high res or save power if possible */
5736static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5737{
5738 struct drm_i915_private *dev_priv = dev->dev_private;
5739 u32 val, cmd;
5740
164dfd28
VK		 5741 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5742 != dev_priv->cdclk_freq);
d60c4473 5743
dfcab17e 5744 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5745 cmd = 2;
dfcab17e 5746 else if (cdclk == 266667)
30a970c6
JB		 5747 cmd = 1;
5748 else
5749 cmd = 0;
5750
5751 mutex_lock(&dev_priv->rps.hw_lock);
5752 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5753 val &= ~DSPFREQGUAR_MASK;
5754 val |= (cmd << DSPFREQGUAR_SHIFT);
5755 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5756 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5757 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5758 50)) {
5759 DRM_ERROR("timed out waiting for CDclk change\n");
5760 }
5761 mutex_unlock(&dev_priv->rps.hw_lock);
5762
54433e91
VS		 5763 mutex_lock(&dev_priv->sb_lock);
5764
dfcab17e 5765 if (cdclk == 400000) {
6bcda4f0 5766 u32 divider;
30a970c6 5767
6bcda4f0 5768 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5769
30a970c6
JB		 5770 /* adjust cdclk divider */
5771 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5772 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5773 val |= divider;
5774 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5775
5776 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5777 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5778 50))
5779 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5780 }
5781
30a970c6
JB		 5782 /* adjust self-refresh exit latency value */
5783 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5784 val &= ~0x7f;
5785
5786 /*
5787 * For high bandwidth configs, we set a higher latency in the bunit
5788 * so that the core display fetch happens in time to avoid underruns.
5789 */
dfcab17e 5790 if (cdclk == 400000)
30a970c6
JB		 5791 val |= 4500 / 250; /* 4.5 usec */
5792 else
5793 val |= 3000 / 250; /* 3.0 usec */
5794 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5795
a580516d 5796 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5797
b6283055 5798 intel_update_cdclk(dev);
30a970c6
JB		 5799}
5800
383c5a6a
VS		 5801static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5802{
5803 struct drm_i915_private *dev_priv = dev->dev_private;
5804 u32 val, cmd;
5805
164dfd28
VK		 5806 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5807 != dev_priv->cdclk_freq);
383c5a6a
VS		 5808
5809 switch (cdclk) {
383c5a6a
VS		 5810 case 333333:
5811 case 320000:
383c5a6a 5812 case 266667:
383c5a6a 5813 case 200000:
383c5a6a
VS		 5814 break;
5815 default:
5f77eeb0 5816 MISSING_CASE(cdclk);
383c5a6a
VS		 5817 return;
5818 }
5819
9d0d3fda
VS		 5820 /*
5821 * Specs are full of misinformation, but testing on actual
5822 * hardware has shown that we just need to write the desired
5823 * CCK divider into the Punit register.
5824 */
5825 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5826
383c5a6a
VS		 5827 mutex_lock(&dev_priv->rps.hw_lock);
5828 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5829 val &= ~DSPFREQGUAR_MASK_CHV;
5830 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5831 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5832 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5833 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5834 50)) {
5835 DRM_ERROR("timed out waiting for CDclk change\n");
5836 }
5837 mutex_unlock(&dev_priv->rps.hw_lock);
5838
b6283055 5839 intel_update_cdclk(dev);
383c5a6a
VS		 5840}
5841
30a970c6
JB		 5842static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5843 int max_pixclk)
5844{
6bcda4f0 5845 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5846 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5847
30a970c6
JB		 5848 /*
5849 * Really only a few cases to deal with, as only 4 CDclks are supported:
5850 * 200MHz
5851 * 267MHz
29dc7ef3 5852 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5853 * 400MHz (VLV only)
5854 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5855 * of the lower bin and adjust if needed.
e37c67a1
VS		 5856 *
5857 * We seem to get an unstable or solid color picture at 200MHz.
5858 * Not sure what's wrong. For now use 200MHz only when all pipes
5859 * are off.
30a970c6 5860 */
6cca3195
VS		 5861 if (!IS_CHERRYVIEW(dev_priv) &&
5862 max_pixclk > freq_320*limit/100)
dfcab17e 5863 return 400000;
6cca3195 5864 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5865 return freq_320;
e37c67a1 5866 else if (max_pixclk > 0)
dfcab17e 5867 return 266667;
e37c67a1
VS		 5868 else
5869 return 200000;
30a970c6
JB		 5870}
5871
f8437dd1
VK		 5872static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5873 int max_pixclk)
5874{
5875 /*
5876 * FIXME:
5877 * - remove the guardband, it's not needed on BXT
5878 * - set 19.2MHz bypass frequency if there are no active pipes
5879 */
5880 if (max_pixclk > 576000*9/10)
5881 return 624000;
5882 else if (max_pixclk > 384000*9/10)
5883 return 576000;
5884 else if (max_pixclk > 288000*9/10)
5885 return 384000;
5886 else if (max_pixclk > 144000*9/10)
5887 return 288000;
5888 else
5889 return 144000;
5890}
5891
a821fc46
ACO		 5892/* Compute the max pixel clock for new configuration. Uses atomic state if
5893 * that's non-NULL, look at current state otherwise. */
5894static int intel_mode_max_pixclk(struct drm_device *dev,
5895 struct drm_atomic_state *state)
30a970c6 5896{
30a970c6 5897 struct intel_crtc *intel_crtc;
304603f4 5898 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5899 int max_pixclk = 0;
5900
d3fcc808 5901 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5902 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5903 if (IS_ERR(crtc_state))
5904 return PTR_ERR(crtc_state);
5905
5906 if (!crtc_state->base.enable)
5907 continue;
5908
5909 max_pixclk = max(max_pixclk,
5910 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5911 }
5912
5913 return max_pixclk;
5914}
5915
27c329ed 5916static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5917{
27c329ed
ML		 5918 struct drm_device *dev = state->dev;
5919 struct drm_i915_private *dev_priv = dev->dev_private;
5920 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5921
304603f4
ACO		 5922 if (max_pixclk < 0)
5923 return max_pixclk;
30a970c6 5924
27c329ed
ML		 5925 to_intel_atomic_state(state)->cdclk =
5926 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5927
27c329ed
ML		 5928 return 0;
5929}
304603f4 5930
27c329ed
ML		 5931static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5932{
5933 struct drm_device *dev = state->dev;
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5936
27c329ed
ML		 5937 if (max_pixclk < 0)
5938 return max_pixclk;
85a96e7a 5939
27c329ed
ML		 5940 to_intel_atomic_state(state)->cdclk =
5941 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5942
27c329ed 5943 return 0;
30a970c6
JB		 5944}
5945
1e69cd74
VS		 5946static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5947{
5948 unsigned int credits, default_credits;
5949
5950 if (IS_CHERRYVIEW(dev_priv))
5951 default_credits = PFI_CREDIT(12);
5952 else
5953 default_credits = PFI_CREDIT(8);
5954
164dfd28 5955 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5956 /* CHV suggested value is 31 or 63 */
5957 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5958 credits = PFI_CREDIT_63;
1e69cd74
VS		 5959 else
5960 credits = PFI_CREDIT(15);
5961 } else {
5962 credits = default_credits;
5963 }
5964
5965 /*
5966 * WA - write default credits before re-programming
5967 * FIXME: should we also set the resend bit here?
5968 */
5969 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5970 default_credits);
5971
5972 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5973 credits | PFI_CREDIT_RESEND);
5974
5975 /*
5976 * FIXME is this guaranteed to clear
5977 * immediately or should we poll for it?
5978 */
5979 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5980}
5981
27c329ed 5982static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5983{
a821fc46 5984 struct drm_device *dev = old_state->dev;
27c329ed 5985 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5986 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5987
27c329ed
ML		 5988 /*
5989 * FIXME: We can end up here with all power domains off, yet
5990 * with a CDCLK frequency other than the minimum. To account
5991 * for this take the PIPE-A power domain, which covers the HW
5992 * blocks needed for the following programming. This can be
5993 * removed once it's guaranteed that we get here either with
5994 * the minimum CDCLK set, or the required power domains
5995 * enabled.
5996 */
5997 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5998
27c329ed
ML		 5999 if (IS_CHERRYVIEW(dev))
6000 cherryview_set_cdclk(dev, req_cdclk);
6001 else
6002 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6003
27c329ed 6004 vlv_program_pfi_credits(dev_priv);
1e69cd74 6005
27c329ed 6006 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6007}
6008
89b667f8
JB		 6009static void valleyview_crtc_enable(struct drm_crtc *crtc)
6010{
6011 struct drm_device *dev = crtc->dev;
a72e4c9f 6012 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6014 struct intel_encoder *encoder;
6015 int pipe = intel_crtc->pipe;
23538ef1 6016 bool is_dsi;
89b667f8 6017
53d9f4e9 6018 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6019 return;
6020
409ee761 6021 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6022
1ae0d137
VS		 6023 if (!is_dsi) {
6024 if (IS_CHERRYVIEW(dev))
6e3c9717 6025 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6026 else
6e3c9717 6027 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6028 }
5b18e57c 6029
6e3c9717 6030 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6031 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6032
6033 intel_set_pipe_timings(intel_crtc);
6034
c14b0485
VS		 6035 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6036 struct drm_i915_private *dev_priv = dev->dev_private;
6037
6038 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6039 I915_WRITE(CHV_CANVAS(pipe), 0);
6040 }
6041
5b18e57c
DV		 6042 i9xx_set_pipeconf(intel_crtc);
6043
89b667f8 6044 intel_crtc->active = true;
89b667f8 6045
a72e4c9f 6046 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6047
89b667f8
JB		 6048 for_each_encoder_on_crtc(dev, crtc, encoder)
6049 if (encoder->pre_pll_enable)
6050 encoder->pre_pll_enable(encoder);
6051
9d556c99
CML		 6052 if (!is_dsi) {
6053 if (IS_CHERRYVIEW(dev))
6e3c9717 6054 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6055 else
6e3c9717 6056 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6057 }
89b667f8
JB		 6058
6059 for_each_encoder_on_crtc(dev, crtc, encoder)
6060 if (encoder->pre_enable)
6061 encoder->pre_enable(encoder);
6062
2dd24552
JB		 6063 i9xx_pfit_enable(intel_crtc);
6064
63cbb074
VS		 6065 intel_crtc_load_lut(crtc);
6066
e1fdc473 6067 intel_enable_pipe(intel_crtc);
be6a6f8e 6068
4b3a9526
VS		 6069 assert_vblank_disabled(crtc);
6070 drm_crtc_vblank_on(crtc);
6071
f9b61ff6
DV		 6072 for_each_encoder_on_crtc(dev, crtc, encoder)
6073 encoder->enable(encoder);
89b667f8
JB		 6074}
6075
f13c2ef3
DV		 6076static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6077{
6078 struct drm_device *dev = crtc->base.dev;
6079 struct drm_i915_private *dev_priv = dev->dev_private;
6080
6e3c9717
ACO		 6081 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6082 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6083}
6084
0b8765c6 6085static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6086{
6087 struct drm_device *dev = crtc->dev;
a72e4c9f 6088 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6090 struct intel_encoder *encoder;
79e53945 6091 int pipe = intel_crtc->pipe;
79e53945 6092
53d9f4e9 6093 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6094 return;
6095
f13c2ef3
DV		 6096 i9xx_set_pll_dividers(intel_crtc);
6097
6e3c9717 6098 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6099 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6100
6101 intel_set_pipe_timings(intel_crtc);
6102
5b18e57c
DV		 6103 i9xx_set_pipeconf(intel_crtc);
6104
f7abfe8b 6105 intel_crtc->active = true;
6b383a7f 6106
4a3436e8 6107 if (!IS_GEN2(dev))
a72e4c9f 6108 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6109
9d6d9f19
MK		 6110 for_each_encoder_on_crtc(dev, crtc, encoder)
6111 if (encoder->pre_enable)
6112 encoder->pre_enable(encoder);
6113
f6736a1a
DV		 6114 i9xx_enable_pll(intel_crtc);
6115
2dd24552
JB		 6116 i9xx_pfit_enable(intel_crtc);
6117
63cbb074
VS		 6118 intel_crtc_load_lut(crtc);
6119
f37fcc2a 6120 intel_update_watermarks(crtc);
e1fdc473 6121 intel_enable_pipe(intel_crtc);
be6a6f8e 6122
4b3a9526
VS		 6123 assert_vblank_disabled(crtc);
6124 drm_crtc_vblank_on(crtc);
6125
f9b61ff6
DV		 6126 for_each_encoder_on_crtc(dev, crtc, encoder)
6127 encoder->enable(encoder);
0b8765c6 6128}
79e53945 6129
87476d63
DV		 6130static void i9xx_pfit_disable(struct intel_crtc *crtc)
6131{
6132 struct drm_device *dev = crtc->base.dev;
6133 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6134
6e3c9717 6135 if (!crtc->config->gmch_pfit.control)
328d8e82 6136 return;
87476d63 6137
328d8e82 6138 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6139
328d8e82
DV		 6140 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6141 I915_READ(PFIT_CONTROL));
6142 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6143}
6144
0b8765c6
JB		 6145static void i9xx_crtc_disable(struct drm_crtc *crtc)
6146{
6147 struct drm_device *dev = crtc->dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6150 struct intel_encoder *encoder;
0b8765c6 6151 int pipe = intel_crtc->pipe;
ef9c3aee 6152
6304cd91
VS		 6153 /*
6154 * On gen2 planes are double buffered but the pipe isn't, so we must
6155 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6156 * We also need to wait on all gmch platforms because of the
6157 * self-refresh mode constraint explained above.
6304cd91 6158 */
564ed191 6159 intel_wait_for_vblank(dev, pipe);
6304cd91 6160
4b3a9526
VS		 6161 for_each_encoder_on_crtc(dev, crtc, encoder)
6162 encoder->disable(encoder);
6163
f9b61ff6
DV		 6164 drm_crtc_vblank_off(crtc);
6165 assert_vblank_disabled(crtc);
6166
575f7ab7 6167 intel_disable_pipe(intel_crtc);
24a1f16d 6168
87476d63 6169 i9xx_pfit_disable(intel_crtc);
24a1f16d 6170
89b667f8
JB		 6171 for_each_encoder_on_crtc(dev, crtc, encoder)
6172 if (encoder->post_disable)
6173 encoder->post_disable(encoder);
6174
409ee761 6175 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6176 if (IS_CHERRYVIEW(dev))
6177 chv_disable_pll(dev_priv, pipe);
6178 else if (IS_VALLEYVIEW(dev))
6179 vlv_disable_pll(dev_priv, pipe);
6180 else
1c4e0274 6181 i9xx_disable_pll(intel_crtc);
076ed3b2 6182 }
0b8765c6 6183
4a3436e8 6184 if (!IS_GEN2(dev))
a72e4c9f 6185 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ		 6186
6187 intel_crtc->active = false;
6188 intel_update_watermarks(crtc);
0b8765c6
JB		 6189}
6190
b17d48e2
ML		 6191static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6192{
6193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6194 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6195 enum intel_display_power_domain domain;
6196 unsigned long domains;
6197
6198 if (!intel_crtc->active)
6199 return;
6200
a539205a
ML		 6201 if (to_intel_plane_state(crtc->primary->state)->visible) {
6202 intel_crtc_wait_for_pending_flips(crtc);
6203 intel_pre_disable_primary(crtc);
6204 }
6205
d032ffa0 6206 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2 6207 dev_priv->display.crtc_disable(crtc);
1f7457b1 6208 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML		 6209
6210 domains = intel_crtc->enabled_power_domains;
6211 for_each_power_domain(domain, domains)
6212 intel_display_power_put(dev_priv, domain);
6213 intel_crtc->enabled_power_domains = 0;
6214}
6215
6b72d486
ML		 6216/*
6217 * turn all crtc's off, but do not adjust state
6218 * This has to be paired with a call to intel_modeset_setup_hw_state.
6219 */
70e0bd74 6220int intel_display_suspend(struct drm_device *dev)
ee7b9f93 6221{
70e0bd74
ML		 6222 struct drm_mode_config *config = &dev->mode_config;
6223 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6224 struct drm_atomic_state *state;
6b72d486 6225 struct drm_crtc *crtc;
70e0bd74
ML		 6226 unsigned crtc_mask = 0;
6227 int ret = 0;
6228
6229 if (WARN_ON(!ctx))
6230 return 0;
6231
6232 lockdep_assert_held(&ctx->ww_ctx);
6233 state = drm_atomic_state_alloc(dev);
6234 if (WARN_ON(!state))
6235 return -ENOMEM;
6236
6237 state->acquire_ctx = ctx;
6238 state->allow_modeset = true;
6239
6240 for_each_crtc(dev, crtc) {
6241 struct drm_crtc_state *crtc_state =
6242 drm_atomic_get_crtc_state(state, crtc);
6b72d486 6243
70e0bd74
ML		 6244 ret = PTR_ERR_OR_ZERO(crtc_state);
6245 if (ret)
6246 goto free;
6247
6248 if (!crtc_state->active)
6249 continue;
6250
6251 crtc_state->active = false;
6252 crtc_mask |= 1 << drm_crtc_index(crtc);
6253 }
6254
6255 if (crtc_mask) {
74c090b1 6256 ret = drm_atomic_commit(state);
70e0bd74
ML		 6257
6258 if (!ret) {
6259 for_each_crtc(dev, crtc)
6260 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6261 crtc->state->active = true;
6262
6263 return ret;
6264 }
6265 }
6266
6267free:
6268 if (ret)
6269 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6270 drm_atomic_state_free(state);
6271 return ret;
ee7b9f93
JB		 6272}
6273
b04c5bd6 6274/* Master function to enable/disable CRTC and corresponding power wells */
5da76e94 6275int intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6276{
6277 struct drm_device *dev = crtc->dev;
5da76e94
ML		 6278 struct drm_mode_config *config = &dev->mode_config;
6279 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
0e572fe7 6280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5da76e94
ML		 6281 struct intel_crtc_state *pipe_config;
6282 struct drm_atomic_state *state;
6283 int ret;
976f8a20 6284
1b509259 6285 if (enable == intel_crtc->active)
5da76e94 6286 return 0;
0e572fe7 6287
1b509259 6288 if (enable && !crtc->state->enable)
5da76e94 6289 return 0;
1b509259 6290
5da76e94
ML		 6291 /* this function should be called with drm_modeset_lock_all for now */
6292 if (WARN_ON(!ctx))
6293 return -EIO;
6294 lockdep_assert_held(&ctx->ww_ctx);
1b509259 6295
5da76e94
ML		 6296 state = drm_atomic_state_alloc(dev);
6297 if (WARN_ON(!state))
6298 return -ENOMEM;
1b509259 6299
5da76e94
ML		 6300 state->acquire_ctx = ctx;
6301 state->allow_modeset = true;
6302
6303 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6304 if (IS_ERR(pipe_config)) {
6305 ret = PTR_ERR(pipe_config);
6306 goto err;
0e572fe7 6307 }
5da76e94
ML		 6308 pipe_config->base.active = enable;
6309
74c090b1 6310 ret = drm_atomic_commit(state);
5da76e94
ML		 6311 if (!ret)
6312 return ret;
6313
6314err:
6315 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6316 drm_atomic_state_free(state);
6317 return ret;
b04c5bd6
BF		 6318}
6319
6320/**
6321 * Sets the power management mode of the pipe and plane.
6322 */
6323void intel_crtc_update_dpms(struct drm_crtc *crtc)
6324{
6325 struct drm_device *dev = crtc->dev;
6326 struct intel_encoder *intel_encoder;
6327 bool enable = false;
6328
6329 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6330 enable |= intel_encoder->connectors_active;
6331
6332 intel_crtc_control(crtc, enable);
cdd59983
CW		 6333}
6334
ea5b213a 6335void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6336{
4ef69c7a 6337 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6338
ea5b213a
CW		 6339 drm_encoder_cleanup(encoder);
6340 kfree(intel_encoder);
7e7d76c3
JB		 6341}
6342
9237329d 6343/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6344 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6345 * state of the entire output pipe. */
9237329d 6346static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6347{
5ab432ef
DV		 6348 if (mode == DRM_MODE_DPMS_ON) {
6349 encoder->connectors_active = true;
6350
b2cabb0e 6351 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6352 } else {
6353 encoder->connectors_active = false;
6354
b2cabb0e 6355 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6356 }
79e53945
JB		 6357}
6358
0a91ca29
DV		 6359/* Cross check the actual hw state with our own modeset state tracking (and it's
6360 * internal consistency). */
b980514c 6361static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6362{
0a91ca29
DV		 6363 if (connector->get_hw_state(connector)) {
6364 struct intel_encoder *encoder = connector->encoder;
6365 struct drm_crtc *crtc;
6366 bool encoder_enabled;
6367 enum pipe pipe;
6368
6369 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6370 connector->base.base.id,
c23cc417 6371 connector->base.name);
0a91ca29 6372
0e32b39c
DA		 6373 /* there is no real hw state for MST connectors */
6374 if (connector->mst_port)
6375 return;
6376
e2c719b7 6377 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6378 "wrong connector dpms state\n");
e2c719b7 6379 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6380 "active connector not linked to encoder\n");
0a91ca29 6381
36cd7444 6382 if (encoder) {
e2c719b7 6383 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6384 "encoder->connectors_active not set\n");
6385
6386 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6387 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6388 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6389 return;
0a91ca29 6390
36cd7444 6391 crtc = encoder->base.crtc;
0a91ca29 6392
83d65738
MR		 6393 I915_STATE_WARN(!crtc->state->enable,
6394 "crtc not enabled\n");
e2c719b7
RC		 6395 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6396 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6397 "encoder active on the wrong pipe\n");
6398 }
0a91ca29 6399 }
79e53945
JB		 6400}
6401
08d9bc92
ACO		 6402int intel_connector_init(struct intel_connector *connector)
6403{
6404 struct drm_connector_state *connector_state;
6405
6406 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6407 if (!connector_state)
6408 return -ENOMEM;
6409
6410 connector->base.state = connector_state;
6411 return 0;
6412}
6413
6414struct intel_connector *intel_connector_alloc(void)
6415{
6416 struct intel_connector *connector;
6417
6418 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6419 if (!connector)
6420 return NULL;
6421
6422 if (intel_connector_init(connector) < 0) {
6423 kfree(connector);
6424 return NULL;
6425 }
6426
6427 return connector;
6428}
6429
5ab432ef
DV		 6430/* Even simpler default implementation, if there's really no special case to
6431 * consider. */
6432void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6433{
5ab432ef
DV		 6434 /* All the simple cases only support two dpms states. */
6435 if (mode != DRM_MODE_DPMS_ON)
6436 mode = DRM_MODE_DPMS_OFF;
d4270e57 6437
5ab432ef
DV		 6438 if (mode == connector->dpms)
6439 return;
6440
6441 connector->dpms = mode;
6442
6443 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6444 if (connector->encoder)
6445 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6446
b980514c 6447 intel_modeset_check_state(connector->dev);
79e53945
JB		 6448}
6449
f0947c37
DV		 6450/* Simple connector->get_hw_state implementation for encoders that support only
6451 * one connector and no cloning and hence the encoder state determines the state
6452 * of the connector. */
6453bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6454{
24929352 6455 enum pipe pipe = 0;
f0947c37 6456 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6457
f0947c37 6458 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6459}
6460
6d293983 6461static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6462{
6d293983
ACO		 6463 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6464 return crtc_state->fdi_lanes;
d272ddfa
VS		 6465
6466 return 0;
6467}
6468
6d293983 6469static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6470 struct intel_crtc_state *pipe_config)
1857e1da 6471{
6d293983
ACO		 6472 struct drm_atomic_state *state = pipe_config->base.state;
6473 struct intel_crtc *other_crtc;
6474 struct intel_crtc_state *other_crtc_state;
6475
1857e1da
DV		 6476 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6477 pipe_name(pipe), pipe_config->fdi_lanes);
6478 if (pipe_config->fdi_lanes > 4) {
6479 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6480 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6481 return -EINVAL;
1857e1da
DV		 6482 }
6483
bafb6553 6484 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6485 if (pipe_config->fdi_lanes > 2) {
6486 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6487 pipe_config->fdi_lanes);
6d293983 6488 return -EINVAL;
1857e1da 6489 } else {
6d293983 6490 return 0;
1857e1da
DV		 6491 }
6492 }
6493
6494 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6495 return 0;
1857e1da
DV		 6496
6497 /* Ivybridge 3 pipe is really complicated */
6498 switch (pipe) {
6499 case PIPE_A:
6d293983 6500 return 0;
1857e1da 6501 case PIPE_B:
6d293983
ACO		 6502 if (pipe_config->fdi_lanes <= 2)
6503 return 0;
6504
6505 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6506 other_crtc_state =
6507 intel_atomic_get_crtc_state(state, other_crtc);
6508 if (IS_ERR(other_crtc_state))
6509 return PTR_ERR(other_crtc_state);
6510
6511 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6512 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6513 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6514 return -EINVAL;
1857e1da 6515 }
6d293983 6516 return 0;
1857e1da 6517 case PIPE_C:
251cc67c
VS		 6518 if (pipe_config->fdi_lanes > 2) {
6519 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6520 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6521 return -EINVAL;
251cc67c 6522 }
6d293983
ACO		 6523
6524 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6525 other_crtc_state =
6526 intel_atomic_get_crtc_state(state, other_crtc);
6527 if (IS_ERR(other_crtc_state))
6528 return PTR_ERR(other_crtc_state);
6529
6530 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6531 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6532 return -EINVAL;
1857e1da 6533 }
6d293983 6534 return 0;
1857e1da
DV		 6535 default:
6536 BUG();
6537 }
6538}
6539
e29c22c0
DV		 6540#define RETRY 1
6541static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6542 struct intel_crtc_state *pipe_config)
877d48d5 6543{
1857e1da 6544 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6545 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6546 int lane, link_bw, fdi_dotclock, ret;
6547 bool needs_recompute = false;
877d48d5 6548
e29c22c0 6549retry:
877d48d5
DV		 6550 /* FDI is a binary signal running at ~2.7GHz, encoding
6551 * each output octet as 10 bits. The actual frequency
6552 * is stored as a divider into a 100MHz clock, and the
6553 * mode pixel clock is stored in units of 1KHz.
6554 * Hence the bw of each lane in terms of the mode signal
6555 * is:
6556 */
6557 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6558
241bfc38 6559 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6560
2bd89a07 6561 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6562 pipe_config->pipe_bpp);
6563
6564 pipe_config->fdi_lanes = lane;
6565
2bd89a07 6566 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6567 link_bw, &pipe_config->fdi_m_n);
1857e1da 6568
6d293983
ACO		 6569 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6570 intel_crtc->pipe, pipe_config);
6571 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6572 pipe_config->pipe_bpp -= 2*3;
6573 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6574 pipe_config->pipe_bpp);
6575 needs_recompute = true;
6576 pipe_config->bw_constrained = true;
6577
6578 goto retry;
6579 }
6580
6581 if (needs_recompute)
6582 return RETRY;
6583
6d293983 6584 return ret;
877d48d5
DV		 6585}
6586
8cfb3407
VS		 6587static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6588 struct intel_crtc_state *pipe_config)
6589{
6590 if (pipe_config->pipe_bpp > 24)
6591 return false;
6592
6593 /* HSW can handle pixel rate up to cdclk? */
6594 if (IS_HASWELL(dev_priv->dev))
6595 return true;
6596
6597 /*
b432e5cf
VS		 6598 * We compare against max which means we must take
6599 * the increased cdclk requirement into account when
6600 * calculating the new cdclk.
6601 *
6602 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6603 */
6604 return ilk_pipe_pixel_rate(pipe_config) <=
6605 dev_priv->max_cdclk_freq * 95 / 100;
6606}
6607
42db64ef 6608static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6609 struct intel_crtc_state *pipe_config)
42db64ef 6610{
8cfb3407
VS		 6611 struct drm_device *dev = crtc->base.dev;
6612 struct drm_i915_private *dev_priv = dev->dev_private;
6613
d330a953 6614 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6615 hsw_crtc_supports_ips(crtc) &&
6616 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6617}
6618
a43f6e0f 6619static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6620 struct intel_crtc_state *pipe_config)
79e53945 6621{
a43f6e0f 6622 struct drm_device *dev = crtc->base.dev;
8bd31e67 6623 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6624 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6625
ad3a4479 6626 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6627 if (INTEL_INFO(dev)->gen < 4) {
44913155 6628 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6629
6630 /*
6631 * Enable pixel doubling when the dot clock
6632 * is > 90% of the (display) core speed.
6633 *
b397c96b
VS		 6634 * GDG double wide on either pipe,
6635 * otherwise pipe A only.
cf532bb2 6636 */
b397c96b 6637 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6638 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6639 clock_limit *= 2;
cf532bb2 6640 pipe_config->double_wide = true;
ad3a4479
VS		 6641 }
6642
241bfc38 6643 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6644 return -EINVAL;
2c07245f 6645 }
89749350 6646
1d1d0e27
VS		 6647 /*
6648 * Pipe horizontal size must be even in:
6649 * - DVO ganged mode
6650 * - LVDS dual channel mode
6651 * - Double wide pipe
6652 */
a93e255f 6653 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6654 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6655 pipe_config->pipe_src_w &= ~1;
6656
8693a824
DL		 6657 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6658 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6659 */
6660 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6661 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6662 return -EINVAL;
44f46b42 6663
f5adf94e 6664 if (HAS_IPS(dev))
a43f6e0f
DV		 6665 hsw_compute_ips_config(crtc, pipe_config);
6666
877d48d5 6667 if (pipe_config->has_pch_encoder)
a43f6e0f 6668 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6669
cf5a15be 6670 return 0;
79e53945
JB		 6671}
6672
1652d19e
VS		 6673static int skylake_get_display_clock_speed(struct drm_device *dev)
6674{
6675 struct drm_i915_private *dev_priv = to_i915(dev);
6676 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6677 uint32_t cdctl = I915_READ(CDCLK_CTL);
6678 uint32_t linkrate;
6679
414355a7 6680 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6681 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6682
6683 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6684 return 540000;
6685
6686 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6687 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6688
71cd8423
DL		 6689 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6690 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6691 /* vco 8640 */
6692 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6693 case CDCLK_FREQ_450_432:
6694 return 432000;
6695 case CDCLK_FREQ_337_308:
6696 return 308570;
6697 case CDCLK_FREQ_675_617:
6698 return 617140;
6699 default:
6700 WARN(1, "Unknown cd freq selection\n");
6701 }
6702 } else {
6703 /* vco 8100 */
6704 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6705 case CDCLK_FREQ_450_432:
6706 return 450000;
6707 case CDCLK_FREQ_337_308:
6708 return 337500;
6709 case CDCLK_FREQ_675_617:
6710 return 675000;
6711 default:
6712 WARN(1, "Unknown cd freq selection\n");
6713 }
6714 }
6715
6716 /* error case, do as if DPLL0 isn't enabled */
6717 return 24000;
6718}
6719
acd3f3d3
BP		 6720static int broxton_get_display_clock_speed(struct drm_device *dev)
6721{
6722 struct drm_i915_private *dev_priv = to_i915(dev);
6723 uint32_t cdctl = I915_READ(CDCLK_CTL);
6724 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6725 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6726 int cdclk;
6727
6728 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6729 return 19200;
6730
6731 cdclk = 19200 * pll_ratio / 2;
6732
6733 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6734 case BXT_CDCLK_CD2X_DIV_SEL_1:
6735 return cdclk; /* 576MHz or 624MHz */
6736 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6737 return cdclk * 2 / 3; /* 384MHz */
6738 case BXT_CDCLK_CD2X_DIV_SEL_2:
6739 return cdclk / 2; /* 288MHz */
6740 case BXT_CDCLK_CD2X_DIV_SEL_4:
6741 return cdclk / 4; /* 144MHz */
6742 }
6743
6744 /* error case, do as if DE PLL isn't enabled */
6745 return 19200;
6746}
6747
1652d19e
VS		 6748static int broadwell_get_display_clock_speed(struct drm_device *dev)
6749{
6750 struct drm_i915_private *dev_priv = dev->dev_private;
6751 uint32_t lcpll = I915_READ(LCPLL_CTL);
6752 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6753
6754 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6755 return 800000;
6756 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6757 return 450000;
6758 else if (freq == LCPLL_CLK_FREQ_450)
6759 return 450000;
6760 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6761 return 540000;
6762 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6763 return 337500;
6764 else
6765 return 675000;
6766}
6767
6768static int haswell_get_display_clock_speed(struct drm_device *dev)
6769{
6770 struct drm_i915_private *dev_priv = dev->dev_private;
6771 uint32_t lcpll = I915_READ(LCPLL_CTL);
6772 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6773
6774 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6775 return 800000;
6776 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6777 return 450000;
6778 else if (freq == LCPLL_CLK_FREQ_450)
6779 return 450000;
6780 else if (IS_HSW_ULT(dev))
6781 return 337500;
6782 else
6783 return 540000;
79e53945
JB		 6784}
6785
25eb05fc
JB		 6786static int valleyview_get_display_clock_speed(struct drm_device *dev)
6787{
d197b7d3 6788 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6789 u32 val;
6790 int divider;
6791
6bcda4f0
VS		 6792 if (dev_priv->hpll_freq == 0)
6793 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6794
a580516d 6795 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6796 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6797 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6798
6799 divider = val & DISPLAY_FREQUENCY_VALUES;
6800
7d007f40
VS		 6801 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6802 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6803 "cdclk change in progress\n");
6804
6bcda4f0 6805 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6806}
6807
b37a6434
VS		 6808static int ilk_get_display_clock_speed(struct drm_device *dev)
6809{
6810 return 450000;
6811}
6812
e70236a8
JB		 6813static int i945_get_display_clock_speed(struct drm_device *dev)
6814{
6815 return 400000;
6816}
79e53945 6817
e70236a8 6818static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6819{
e907f170 6820 return 333333;
e70236a8 6821}
79e53945 6822
e70236a8
JB		 6823static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6824{
6825 return 200000;
6826}
79e53945 6827
257a7ffc
DV		 6828static int pnv_get_display_clock_speed(struct drm_device *dev)
6829{
6830 u16 gcfgc = 0;
6831
6832 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6833
6834 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6835 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6836 return 266667;
257a7ffc 6837 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6838 return 333333;
257a7ffc 6839 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6840 return 444444;
257a7ffc
DV		 6841 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6842 return 200000;
6843 default:
6844 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6845 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6846 return 133333;
257a7ffc 6847 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6848 return 166667;
257a7ffc
DV		 6849 }
6850}
6851
e70236a8
JB		 6852static int i915gm_get_display_clock_speed(struct drm_device *dev)
6853{
6854 u16 gcfgc = 0;
79e53945 6855
e70236a8
JB		 6856 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6857
6858 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6859 return 133333;
e70236a8
JB		 6860 else {
6861 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6862 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6863 return 333333;
e70236a8
JB		 6864 default:
6865 case GC_DISPLAY_CLOCK_190_200_MHZ:
6866 return 190000;
79e53945 6867 }
e70236a8
JB		 6868 }
6869}
6870
6871static int i865_get_display_clock_speed(struct drm_device *dev)
6872{
e907f170 6873 return 266667;
e70236a8
JB		 6874}
6875
1b1d2716 6876static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6877{
6878 u16 hpllcc = 0;
1b1d2716 6879
65cd2b3f
VS		 6880 /*
6881 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6882 * encoding is different :(
6883 * FIXME is this the right way to detect 852GM/852GMV?
6884 */
6885 if (dev->pdev->revision == 0x1)
6886 return 133333;
6887
1b1d2716
VS		 6888 pci_bus_read_config_word(dev->pdev->bus,
6889 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6890
e70236a8
JB		 6891 /* Assume that the hardware is in the high speed state. This
6892 * should be the default.
6893 */
6894 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6895 case GC_CLOCK_133_200:
1b1d2716 6896 case GC_CLOCK_133_200_2:
e70236a8
JB		 6897 case GC_CLOCK_100_200:
6898 return 200000;
6899 case GC_CLOCK_166_250:
6900 return 250000;
6901 case GC_CLOCK_100_133:
e907f170 6902 return 133333;
1b1d2716
VS		 6903 case GC_CLOCK_133_266:
6904 case GC_CLOCK_133_266_2:
6905 case GC_CLOCK_166_266:
6906 return 266667;
e70236a8 6907 }
79e53945 6908
e70236a8
JB		 6909 /* Shouldn't happen */
6910 return 0;
6911}
79e53945 6912
e70236a8
JB		 6913static int i830_get_display_clock_speed(struct drm_device *dev)
6914{
e907f170 6915 return 133333;
79e53945
JB		 6916}
6917
34edce2f
VS		 6918static unsigned int intel_hpll_vco(struct drm_device *dev)
6919{
6920 struct drm_i915_private *dev_priv = dev->dev_private;
6921 static const unsigned int blb_vco[8] = {
6922 [0] = 3200000,
6923 [1] = 4000000,
6924 [2] = 5333333,
6925 [3] = 4800000,
6926 [4] = 6400000,
6927 };
6928 static const unsigned int pnv_vco[8] = {
6929 [0] = 3200000,
6930 [1] = 4000000,
6931 [2] = 5333333,
6932 [3] = 4800000,
6933 [4] = 2666667,
6934 };
6935 static const unsigned int cl_vco[8] = {
6936 [0] = 3200000,
6937 [1] = 4000000,
6938 [2] = 5333333,
6939 [3] = 6400000,
6940 [4] = 3333333,
6941 [5] = 3566667,
6942 [6] = 4266667,
6943 };
6944 static const unsigned int elk_vco[8] = {
6945 [0] = 3200000,
6946 [1] = 4000000,
6947 [2] = 5333333,
6948 [3] = 4800000,
6949 };
6950 static const unsigned int ctg_vco[8] = {
6951 [0] = 3200000,
6952 [1] = 4000000,
6953 [2] = 5333333,
6954 [3] = 6400000,
6955 [4] = 2666667,
6956 [5] = 4266667,
6957 };
6958 const unsigned int *vco_table;
6959 unsigned int vco;
6960 uint8_t tmp = 0;
6961
6962 /* FIXME other chipsets? */
6963 if (IS_GM45(dev))
6964 vco_table = ctg_vco;
6965 else if (IS_G4X(dev))
6966 vco_table = elk_vco;
6967 else if (IS_CRESTLINE(dev))
6968 vco_table = cl_vco;
6969 else if (IS_PINEVIEW(dev))
6970 vco_table = pnv_vco;
6971 else if (IS_G33(dev))
6972 vco_table = blb_vco;
6973 else
6974 return 0;
6975
6976 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6977
6978 vco = vco_table[tmp & 0x7];
6979 if (vco == 0)
6980 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6981 else
6982 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6983
6984 return vco;
6985}
6986
6987static int gm45_get_display_clock_speed(struct drm_device *dev)
6988{
6989 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6990 uint16_t tmp = 0;
6991
6992 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6993
6994 cdclk_sel = (tmp >> 12) & 0x1;
6995
6996 switch (vco) {
6997 case 2666667:
6998 case 4000000:
6999 case 5333333:
7000 return cdclk_sel ? 333333 : 222222;
7001 case 3200000:
7002 return cdclk_sel ? 320000 : 228571;
7003 default:
7004 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7005 return 222222;
7006 }
7007}
7008
7009static int i965gm_get_display_clock_speed(struct drm_device *dev)
7010{
7011 static const uint8_t div_3200[] = { 16, 10, 8 };
7012 static const uint8_t div_4000[] = { 20, 12, 10 };
7013 static const uint8_t div_5333[] = { 24, 16, 14 };
7014 const uint8_t *div_table;
7015 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7016 uint16_t tmp = 0;
7017
7018 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7019
7020 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7021
7022 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7023 goto fail;
7024
7025 switch (vco) {
7026 case 3200000:
7027 div_table = div_3200;
7028 break;
7029 case 4000000:
7030 div_table = div_4000;
7031 break;
7032 case 5333333:
7033 div_table = div_5333;
7034 break;
7035 default:
7036 goto fail;
7037 }
7038
7039 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7040
caf4e252 7041fail:
34edce2f
VS		 7042 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7043 return 200000;
7044}
7045
7046static int g33_get_display_clock_speed(struct drm_device *dev)
7047{
7048 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7049 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7050 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7051 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7052 const uint8_t *div_table;
7053 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7054 uint16_t tmp = 0;
7055
7056 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7057
7058 cdclk_sel = (tmp >> 4) & 0x7;
7059
7060 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7061 goto fail;
7062
7063 switch (vco) {
7064 case 3200000:
7065 div_table = div_3200;
7066 break;
7067 case 4000000:
7068 div_table = div_4000;
7069 break;
7070 case 4800000:
7071 div_table = div_4800;
7072 break;
7073 case 5333333:
7074 div_table = div_5333;
7075 break;
7076 default:
7077 goto fail;
7078 }
7079
7080 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7081
caf4e252 7082fail:
34edce2f
VS		 7083 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7084 return 190476;
7085}
7086
2c07245f 7087static void
a65851af 7088intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7089{
a65851af
VS		 7090 while (*num > DATA_LINK_M_N_MASK ||
7091 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7092 *num >>= 1;
7093 *den >>= 1;
7094 }
7095}
7096
a65851af
VS		 7097static void compute_m_n(unsigned int m, unsigned int n,
7098 uint32_t *ret_m, uint32_t *ret_n)
7099{
7100 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7101 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7102 intel_reduce_m_n_ratio(ret_m, ret_n);
7103}
7104
e69d0bc1
DV		 7105void
7106intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7107 int pixel_clock, int link_clock,
7108 struct intel_link_m_n *m_n)
2c07245f 7109{
e69d0bc1 7110 m_n->tu = 64;
a65851af
VS		 7111
7112 compute_m_n(bits_per_pixel * pixel_clock,
7113 link_clock * nlanes * 8,
7114 &m_n->gmch_m, &m_n->gmch_n);
7115
7116 compute_m_n(pixel_clock, link_clock,
7117 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7118}
7119
a7615030
CW		 7120static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7121{
d330a953
JN		 7122 if (i915.panel_use_ssc >= 0)
7123 return i915.panel_use_ssc != 0;
41aa3448 7124 return dev_priv->vbt.lvds_use_ssc
435793df 7125 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7126}
7127
a93e255f
ACO		 7128static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7129 int num_connectors)
c65d77d8 7130{
a93e255f 7131 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7132 struct drm_i915_private *dev_priv = dev->dev_private;
7133 int refclk;
7134
a93e255f
ACO		 7135 WARN_ON(!crtc_state->base.state);
7136
5ab7b0b7 7137 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7138 refclk = 100000;
a93e255f 7139 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7140 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7141 refclk = dev_priv->vbt.lvds_ssc_freq;
7142 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7143 } else if (!IS_GEN2(dev)) {
7144 refclk = 96000;
7145 } else {
7146 refclk = 48000;
7147 }
7148
7149 return refclk;
7150}
7151
7429e9d4 7152static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7153{
7df00d7a 7154 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7155}
f47709a9 7156
7429e9d4
DV		 7157static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7158{
7159 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7160}
7161
f47709a9 7162static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7163 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7164 intel_clock_t *reduced_clock)
7165{
f47709a9 7166 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7167 u32 fp, fp2 = 0;
7168
7169 if (IS_PINEVIEW(dev)) {
190f68c5 7170 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7171 if (reduced_clock)
7429e9d4 7172 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7173 } else {
190f68c5 7174 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7175 if (reduced_clock)
7429e9d4 7176 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7177 }
7178
190f68c5 7179 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7180
f47709a9 7181 crtc->lowfreq_avail = false;
a93e255f 7182 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7183 reduced_clock) {
190f68c5 7184 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7185 crtc->lowfreq_avail = true;
a7516a05 7186 } else {
190f68c5 7187 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7188 }
7189}
7190
5e69f97f
CML		 7191static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7192 pipe)
89b667f8
JB		 7193{
7194 u32 reg_val;
7195
7196 /*
7197 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7198 * and set it to a reasonable value instead.
7199 */
ab3c759a 7200 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7201 reg_val &= 0xffffff00;
7202 reg_val |= 0x00000030;
ab3c759a 7203 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7204
ab3c759a 7205 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7206 reg_val &= 0x8cffffff;
7207 reg_val = 0x8c000000;
ab3c759a 7208 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7209
ab3c759a 7210 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7211 reg_val &= 0xffffff00;
ab3c759a 7212 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7213
ab3c759a 7214 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7215 reg_val &= 0x00ffffff;
7216 reg_val |= 0xb0000000;
ab3c759a 7217 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7218}
7219
b551842d
DV		 7220static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7221 struct intel_link_m_n *m_n)
7222{
7223 struct drm_device *dev = crtc->base.dev;
7224 struct drm_i915_private *dev_priv = dev->dev_private;
7225 int pipe = crtc->pipe;
7226
e3b95f1e
DV		 7227 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7228 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7229 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7230 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7231}
7232
7233static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7234 struct intel_link_m_n *m_n,
7235 struct intel_link_m_n *m2_n2)
b551842d
DV		 7236{
7237 struct drm_device *dev = crtc->base.dev;
7238 struct drm_i915_private *dev_priv = dev->dev_private;
7239 int pipe = crtc->pipe;
6e3c9717 7240 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7241
7242 if (INTEL_INFO(dev)->gen >= 5) {
7243 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7244 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7245 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7246 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7247 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7248 * for gen < 8) and if DRRS is supported (to make sure the
7249 * registers are not unnecessarily accessed).
7250 */
44395bfe 7251 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7252 crtc->config->has_drrs) {
f769cd24
VK		 7253 I915_WRITE(PIPE_DATA_M2(transcoder),
7254 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7255 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7256 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7257 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7258 }
b551842d 7259 } else {
e3b95f1e
DV		 7260 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7261 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7262 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7263 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7264 }
7265}
7266
fe3cd48d 7267void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7268{
fe3cd48d
R		 7269 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7270
7271 if (m_n == M1_N1) {
7272 dp_m_n = &crtc->config->dp_m_n;
7273 dp_m2_n2 = &crtc->config->dp_m2_n2;
7274 } else if (m_n == M2_N2) {
7275
7276 /*
7277 * M2_N2 registers are not supported. Hence m2_n2 divider value
7278 * needs to be programmed into M1_N1.
7279 */
7280 dp_m_n = &crtc->config->dp_m2_n2;
7281 } else {
7282 DRM_ERROR("Unsupported divider value\n");
7283 return;
7284 }
7285
6e3c9717
ACO		 7286 if (crtc->config->has_pch_encoder)
7287 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7288 else
fe3cd48d 7289 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7290}
7291
251ac862
DV		 7292static void vlv_compute_dpll(struct intel_crtc *crtc,
7293 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7294{
7295 u32 dpll, dpll_md;
7296
7297 /*
7298 * Enable DPIO clock input. We should never disable the reference
7299 * clock for pipe B, since VGA hotplug / manual detection depends
7300 * on it.
7301 */
60bfe44f
VS		 7302 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7303 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7304 /* We should never disable this, set it here for state tracking */
7305 if (crtc->pipe == PIPE_B)
7306 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7307 dpll |= DPLL_VCO_ENABLE;
d288f65f 7308 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7309
d288f65f 7310 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7311 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7312 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7313}
7314
d288f65f 7315static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7316 const struct intel_crtc_state *pipe_config)
a0c4da24 7317{
f47709a9 7318 struct drm_device *dev = crtc->base.dev;
a0c4da24 7319 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7320 int pipe = crtc->pipe;
bdd4b6a6 7321 u32 mdiv;
a0c4da24 7322 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7323 u32 coreclk, reg_val;
a0c4da24 7324
a580516d 7325 mutex_lock(&dev_priv->sb_lock);
09153000 7326
d288f65f
VS		 7327 bestn = pipe_config->dpll.n;
7328 bestm1 = pipe_config->dpll.m1;
7329 bestm2 = pipe_config->dpll.m2;
7330 bestp1 = pipe_config->dpll.p1;
7331 bestp2 = pipe_config->dpll.p2;
a0c4da24 7332
89b667f8
JB		 7333 /* See eDP HDMI DPIO driver vbios notes doc */
7334
7335 /* PLL B needs special handling */
bdd4b6a6 7336 if (pipe == PIPE_B)
5e69f97f 7337 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7338
7339 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7340 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7341
7342 /* Disable target IRef on PLL */
ab3c759a 7343 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7344 reg_val &= 0x00ffffff;
ab3c759a 7345 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7346
7347 /* Disable fast lock */
ab3c759a 7348 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7349
7350 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7351 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7352 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7353 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7354 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7355
7356 /*
7357 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7358 * but we don't support that).
7359 * Note: don't use the DAC post divider as it seems unstable.
7360 */
7361 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7362 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7363
a0c4da24 7364 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7365 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7366
89b667f8 7367 /* Set HBR and RBR LPF coefficients */
d288f65f 7368 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7370 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7371 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7372 0x009f0003);
89b667f8 7373 else
ab3c759a 7374 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7375 0x00d0000f);
7376
681a8504 7377 if (pipe_config->has_dp_encoder) {
89b667f8 7378 /* Use SSC source */
bdd4b6a6 7379 if (pipe == PIPE_A)
ab3c759a 7380 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7381 0x0df40000);
7382 else
ab3c759a 7383 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7384 0x0df70000);
7385 } else { /* HDMI or VGA */
7386 /* Use bend source */
bdd4b6a6 7387 if (pipe == PIPE_A)
ab3c759a 7388 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7389 0x0df70000);
7390 else
ab3c759a 7391 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7392 0x0df40000);
7393 }
a0c4da24 7394
ab3c759a 7395 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7396 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7397 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7398 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7399 coreclk |= 0x01000000;
ab3c759a 7400 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7401
ab3c759a 7402 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7403 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7404}
7405
251ac862
DV		 7406static void chv_compute_dpll(struct intel_crtc *crtc,
7407 struct intel_crtc_state *pipe_config)
1ae0d137 7408{
60bfe44f
VS		 7409 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7410 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7411 DPLL_VCO_ENABLE;
7412 if (crtc->pipe != PIPE_A)
d288f65f 7413 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7414
d288f65f
VS		 7415 pipe_config->dpll_hw_state.dpll_md =
7416 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7417}
7418
d288f65f 7419static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7420 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7421{
7422 struct drm_device *dev = crtc->base.dev;
7423 struct drm_i915_private *dev_priv = dev->dev_private;
7424 int pipe = crtc->pipe;
7425 int dpll_reg = DPLL(crtc->pipe);
7426 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7427 u32 loopfilter, tribuf_calcntr;
9d556c99 7428 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7429 u32 dpio_val;
9cbe40c1 7430 int vco;
9d556c99 7431
d288f65f
VS		 7432 bestn = pipe_config->dpll.n;
7433 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7434 bestm1 = pipe_config->dpll.m1;
7435 bestm2 = pipe_config->dpll.m2 >> 22;
7436 bestp1 = pipe_config->dpll.p1;
7437 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7438 vco = pipe_config->dpll.vco;
a945ce7e 7439 dpio_val = 0;
9cbe40c1 7440 loopfilter = 0;
9d556c99
CML		 7441
7442 /*
7443 * Enable Refclk and SSC
7444 */
a11b0703 7445 I915_WRITE(dpll_reg,
d288f65f 7446 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7447
a580516d 7448 mutex_lock(&dev_priv->sb_lock);
9d556c99 7449
9d556c99
CML		 7450 /* p1 and p2 divider */
7451 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7452 5 << DPIO_CHV_S1_DIV_SHIFT |
7453 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7454 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7455 1 << DPIO_CHV_K_DIV_SHIFT);
7456
7457 /* Feedback post-divider - m2 */
7458 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7459
7460 /* Feedback refclk divider - n and m1 */
7461 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7462 DPIO_CHV_M1_DIV_BY_2 |
7463 1 << DPIO_CHV_N_DIV_SHIFT);
7464
7465 /* M2 fraction division */
a945ce7e
VP		 7466 if (bestm2_frac)
7467 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7468
7469 /* M2 fraction division enable */
a945ce7e
VP		 7470 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7471 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7472 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7473 if (bestm2_frac)
7474 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7475 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7476
de3a0fde
VP		 7477 /* Program digital lock detect threshold */
7478 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7479 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7480 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7481 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7482 if (!bestm2_frac)
7483 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7484 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7485
9d556c99 7486 /* Loop filter */
9cbe40c1
VP		 7487 if (vco == 5400000) {
7488 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7489 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7490 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7491 tribuf_calcntr = 0x9;
7492 } else if (vco <= 6200000) {
7493 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7494 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7495 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7496 tribuf_calcntr = 0x9;
7497 } else if (vco <= 6480000) {
7498 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7499 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7500 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7501 tribuf_calcntr = 0x8;
7502 } else {
7503 /* Not supported. Apply the same limits as in the max case */
7504 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7505 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7506 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7507 tribuf_calcntr = 0;
7508 }
9d556c99
CML		 7509 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7510
968040b2 7511 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7512 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7513 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7514 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7515
9d556c99
CML		 7516 /* AFC Recal */
7517 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7518 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7519 DPIO_AFC_RECAL);
7520
a580516d 7521 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7522}
7523
d288f65f
VS		 7524/**
7525 * vlv_force_pll_on - forcibly enable just the PLL
7526 * @dev_priv: i915 private structure
7527 * @pipe: pipe PLL to enable
7528 * @dpll: PLL configuration
7529 *
7530 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7531 * in cases where we need the PLL enabled even when @pipe is not going to
7532 * be enabled.
7533 */
7534void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7535 const struct dpll *dpll)
7536{
7537 struct intel_crtc *crtc =
7538 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7539 struct intel_crtc_state pipe_config = {
a93e255f 7540 .base.crtc = &crtc->base,
d288f65f
VS		 7541 .pixel_multiplier = 1,
7542 .dpll = *dpll,
7543 };
7544
7545 if (IS_CHERRYVIEW(dev)) {
251ac862 7546 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7547 chv_prepare_pll(crtc, &pipe_config);
7548 chv_enable_pll(crtc, &pipe_config);
7549 } else {
251ac862 7550 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7551 vlv_prepare_pll(crtc, &pipe_config);
7552 vlv_enable_pll(crtc, &pipe_config);
7553 }
7554}
7555
7556/**
7557 * vlv_force_pll_off - forcibly disable just the PLL
7558 * @dev_priv: i915 private structure
7559 * @pipe: pipe PLL to disable
7560 *
7561 * Disable the PLL for @pipe. To be used in cases where we need
7562 * the PLL enabled even when @pipe is not going to be enabled.
7563 */
7564void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7565{
7566 if (IS_CHERRYVIEW(dev))
7567 chv_disable_pll(to_i915(dev), pipe);
7568 else
7569 vlv_disable_pll(to_i915(dev), pipe);
7570}
7571
251ac862
DV		 7572static void i9xx_compute_dpll(struct intel_crtc *crtc,
7573 struct intel_crtc_state *crtc_state,
7574 intel_clock_t *reduced_clock,
7575 int num_connectors)
eb1cbe48 7576{
f47709a9 7577 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7578 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7579 u32 dpll;
7580 bool is_sdvo;
190f68c5 7581 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7582
190f68c5 7583 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7584
a93e255f
ACO		 7585 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7586 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7587
7588 dpll = DPLL_VGA_MODE_DIS;
7589
a93e255f 7590 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7591 dpll |= DPLLB_MODE_LVDS;
7592 else
7593 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7594
ef1b460d 7595 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7596 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7597 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7598 }
198a037f
DV		 7599
7600 if (is_sdvo)
4a33e48d 7601 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7602
190f68c5 7603 if (crtc_state->has_dp_encoder)
4a33e48d 7604 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7605
7606 /* compute bitmask from p1 value */
7607 if (IS_PINEVIEW(dev))
7608 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7609 else {
7610 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7611 if (IS_G4X(dev) && reduced_clock)
7612 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7613 }
7614 switch (clock->p2) {
7615 case 5:
7616 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7617 break;
7618 case 7:
7619 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7620 break;
7621 case 10:
7622 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7623 break;
7624 case 14:
7625 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7626 break;
7627 }
7628 if (INTEL_INFO(dev)->gen >= 4)
7629 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7630
190f68c5 7631 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7632 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7633 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7634 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7635 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7636 else
7637 dpll |= PLL_REF_INPUT_DREFCLK;
7638
7639 dpll |= DPLL_VCO_ENABLE;
190f68c5 7640 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7641
eb1cbe48 7642 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7643 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7644 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7645 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7646 }
7647}
7648
251ac862
DV		 7649static void i8xx_compute_dpll(struct intel_crtc *crtc,
7650 struct intel_crtc_state *crtc_state,
7651 intel_clock_t *reduced_clock,
7652 int num_connectors)
eb1cbe48 7653{
f47709a9 7654 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7655 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7656 u32 dpll;
190f68c5 7657 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7658
190f68c5 7659 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7660
eb1cbe48
DV		 7661 dpll = DPLL_VGA_MODE_DIS;
7662
a93e255f 7663 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7664 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7665 } else {
7666 if (clock->p1 == 2)
7667 dpll |= PLL_P1_DIVIDE_BY_TWO;
7668 else
7669 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7670 if (clock->p2 == 4)
7671 dpll |= PLL_P2_DIVIDE_BY_4;
7672 }
7673
a93e255f 7674 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7675 dpll |= DPLL_DVO_2X_MODE;
7676
a93e255f 7677 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7678 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7679 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7680 else
7681 dpll |= PLL_REF_INPUT_DREFCLK;
7682
7683 dpll |= DPLL_VCO_ENABLE;
190f68c5 7684 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7685}
7686
8a654f3b 7687static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7688{
7689 struct drm_device *dev = intel_crtc->base.dev;
7690 struct drm_i915_private *dev_priv = dev->dev_private;
7691 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7692 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7693 struct drm_display_mode *adjusted_mode =
6e3c9717 7694 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7695 uint32_t crtc_vtotal, crtc_vblank_end;
7696 int vsyncshift = 0;
4d8a62ea
DV		 7697
7698 /* We need to be careful not to changed the adjusted mode, for otherwise
7699 * the hw state checker will get angry at the mismatch. */
7700 crtc_vtotal = adjusted_mode->crtc_vtotal;
7701 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7702
609aeaca 7703 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7704 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7705 crtc_vtotal -= 1;
7706 crtc_vblank_end -= 1;
609aeaca 7707
409ee761 7708 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7709 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7710 else
7711 vsyncshift = adjusted_mode->crtc_hsync_start -
7712 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7713 if (vsyncshift < 0)
7714 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7715 }
7716
7717 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7718 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7719
fe2b8f9d 7720 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7721 (adjusted_mode->crtc_hdisplay - 1) |
7722 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7723 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7724 (adjusted_mode->crtc_hblank_start - 1) |
7725 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7726 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7727 (adjusted_mode->crtc_hsync_start - 1) |
7728 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7729
fe2b8f9d 7730 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7731 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7732 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7733 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7734 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7735 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7736 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7737 (adjusted_mode->crtc_vsync_start - 1) |
7738 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7739
b5e508d4
PZ		 7740 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7741 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7742 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7743 * bits. */
7744 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7745 (pipe == PIPE_B || pipe == PIPE_C))
7746 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7747
b0e77b9c
PZ		 7748 /* pipesrc controls the size that is scaled from, which should
7749 * always be the user's requested size.
7750 */
7751 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7752 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7753 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7754}
7755
1bd1bd80 7756static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7757 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7758{
7759 struct drm_device *dev = crtc->base.dev;
7760 struct drm_i915_private *dev_priv = dev->dev_private;
7761 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7762 uint32_t tmp;
7763
7764 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7765 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7766 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7767 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7768 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7769 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7770 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7771 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7772 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7773
7774 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7775 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7776 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7777 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7778 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7779 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7780 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7781 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7782 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7783
7784 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7785 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7786 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7787 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7788 }
7789
7790 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7791 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7792 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7793
2d112de7
ACO		 7794 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7795 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7796}
7797
f6a83288 7798void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7799 struct intel_crtc_state *pipe_config)
babea61d 7800{
2d112de7
ACO		 7801 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7802 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7803 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7804 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7805
2d112de7
ACO		 7806 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7807 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7808 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7809 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7810
2d112de7 7811 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 7812 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7813
2d112de7
ACO		 7814 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7815 mode->flags |= pipe_config->base.adjusted_mode.flags;
cd13f5ab
ML		 7816
7817 mode->hsync = drm_mode_hsync(mode);
7818 mode->vrefresh = drm_mode_vrefresh(mode);
7819 drm_mode_set_name(mode);
babea61d
JB		 7820}
7821
84b046f3
DV		 7822static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7823{
7824 struct drm_device *dev = intel_crtc->base.dev;
7825 struct drm_i915_private *dev_priv = dev->dev_private;
7826 uint32_t pipeconf;
7827
9f11a9e4 7828 pipeconf = 0;
84b046f3 7829
b6b5d049
VS		 7830 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7831 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7832 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7833
6e3c9717 7834 if (intel_crtc->config->double_wide)
cf532bb2 7835 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7836
ff9ce46e
DV		 7837 /* only g4x and later have fancy bpc/dither controls */
7838 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7839 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7840 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7841 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7842 PIPECONF_DITHER_TYPE_SP;
84b046f3 7843
6e3c9717 7844 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7845 case 18:
7846 pipeconf |= PIPECONF_6BPC;
7847 break;
7848 case 24:
7849 pipeconf |= PIPECONF_8BPC;
7850 break;
7851 case 30:
7852 pipeconf |= PIPECONF_10BPC;
7853 break;
7854 default:
7855 /* Case prevented by intel_choose_pipe_bpp_dither. */
7856 BUG();
84b046f3
DV		 7857 }
7858 }
7859
7860 if (HAS_PIPE_CXSR(dev)) {
7861 if (intel_crtc->lowfreq_avail) {
7862 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7863 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7864 } else {
7865 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7866 }
7867 }
7868
6e3c9717 7869 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7870 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7871 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7872 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7873 else
7874 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7875 } else
84b046f3
DV		 7876 pipeconf |= PIPECONF_PROGRESSIVE;
7877
6e3c9717 7878 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7879 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7880
84b046f3
DV		 7881 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7882 POSTING_READ(PIPECONF(intel_crtc->pipe));
7883}
7884
190f68c5
ACO		 7885static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7886 struct intel_crtc_state *crtc_state)
79e53945 7887{
c7653199 7888 struct drm_device *dev = crtc->base.dev;
79e53945 7889 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7890 int refclk, num_connectors = 0;
c329a4ec
DV		 7891 intel_clock_t clock;
7892 bool ok;
7893 bool is_dsi = false;
5eddb70b 7894 struct intel_encoder *encoder;
d4906093 7895 const intel_limit_t *limit;
55bb9992 7896 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7897 struct drm_connector *connector;
55bb9992
ACO		 7898 struct drm_connector_state *connector_state;
7899 int i;
79e53945 7900
dd3cd74a
ACO		 7901 memset(&crtc_state->dpll_hw_state, 0,
7902 sizeof(crtc_state->dpll_hw_state));
7903
da3ced29 7904 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7905 if (connector_state->crtc != &crtc->base)
7906 continue;
7907
7908 encoder = to_intel_encoder(connector_state->best_encoder);
7909
5eddb70b 7910 switch (encoder->type) {
e9fd1c02
JN		 7911 case INTEL_OUTPUT_DSI:
7912 is_dsi = true;
7913 break;
6847d71b
PZ		 7914 default:
7915 break;
79e53945 7916 }
43565a06 7917
c751ce4f 7918 num_connectors++;
79e53945
JB		 7919 }
7920
f2335330 7921 if (is_dsi)
5b18e57c 7922 return 0;
f2335330 7923
190f68c5 7924 if (!crtc_state->clock_set) {
a93e255f 7925 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7926
e9fd1c02
JN		 7927 /*
7928 * Returns a set of divisors for the desired target clock with
7929 * the given refclk, or FALSE. The returned values represent
7930 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7931 * 2) / p1 / p2.
7932 */
a93e255f
ACO		 7933 limit = intel_limit(crtc_state, refclk);
7934 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7935 crtc_state->port_clock,
e9fd1c02 7936 refclk, NULL, &clock);
f2335330 7937 if (!ok) {
e9fd1c02
JN		 7938 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7939 return -EINVAL;
7940 }
79e53945 7941
f2335330 7942 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7943 crtc_state->dpll.n = clock.n;
7944 crtc_state->dpll.m1 = clock.m1;
7945 crtc_state->dpll.m2 = clock.m2;
7946 crtc_state->dpll.p1 = clock.p1;
7947 crtc_state->dpll.p2 = clock.p2;
f47709a9 7948 }
7026d4ac 7949
e9fd1c02 7950 if (IS_GEN2(dev)) {
c329a4ec 7951 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7952 num_connectors);
9d556c99 7953 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7954 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7955 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7956 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7957 } else {
c329a4ec 7958 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7959 num_connectors);
e9fd1c02 7960 }
79e53945 7961
c8f7a0db 7962 return 0;
f564048e
EA		 7963}
7964
2fa2fe9a 7965static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7966 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7967{
7968 struct drm_device *dev = crtc->base.dev;
7969 struct drm_i915_private *dev_priv = dev->dev_private;
7970 uint32_t tmp;
7971
dc9e7dec
VS		 7972 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7973 return;
7974
2fa2fe9a 7975 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7976 if (!(tmp & PFIT_ENABLE))
7977 return;
2fa2fe9a 7978
06922821 7979 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7980 if (INTEL_INFO(dev)->gen < 4) {
7981 if (crtc->pipe != PIPE_B)
7982 return;
2fa2fe9a
DV		 7983 } else {
7984 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7985 return;
7986 }
7987
06922821 7988 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7989 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7990 if (INTEL_INFO(dev)->gen < 5)
7991 pipe_config->gmch_pfit.lvds_border_bits =
7992 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7993}
7994
acbec814 7995static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7996 struct intel_crtc_state *pipe_config)
acbec814
JB		 7997{
7998 struct drm_device *dev = crtc->base.dev;
7999 struct drm_i915_private *dev_priv = dev->dev_private;
8000 int pipe = pipe_config->cpu_transcoder;
8001 intel_clock_t clock;
8002 u32 mdiv;
662c6ecb 8003 int refclk = 100000;
acbec814 8004
f573de5a
SK		 8005 /* In case of MIPI DPLL will not even be used */
8006 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8007 return;
8008
a580516d 8009 mutex_lock(&dev_priv->sb_lock);
ab3c759a 8010 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 8011 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 8012
8013 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8014 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8015 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8016 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8017 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8018
dccbea3b 8019 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 8020}
8021
5724dbd1
DL		 8022static void
8023i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8024 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 8025{
8026 struct drm_device *dev = crtc->base.dev;
8027 struct drm_i915_private *dev_priv = dev->dev_private;
8028 u32 val, base, offset;
8029 int pipe = crtc->pipe, plane = crtc->plane;
8030 int fourcc, pixel_format;
6761dd31 8031 unsigned int aligned_height;
b113d5ee 8032 struct drm_framebuffer *fb;
1b842c89 8033 struct intel_framebuffer *intel_fb;
1ad292b5 8034
42a7b088
DL		 8035 val = I915_READ(DSPCNTR(plane));
8036 if (!(val & DISPLAY_PLANE_ENABLE))
8037 return;
8038
d9806c9f 8039 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8040 if (!intel_fb) {
1ad292b5
JB		 8041 DRM_DEBUG_KMS("failed to alloc fb\n");
8042 return;
8043 }
8044
1b842c89
DL		 8045 fb = &intel_fb->base;
8046
18c5247e
DV		 8047 if (INTEL_INFO(dev)->gen >= 4) {
8048 if (val & DISPPLANE_TILED) {
49af449b 8049 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8050 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8051 }
8052 }
1ad292b5
JB		 8053
8054 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8055 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8056 fb->pixel_format = fourcc;
8057 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8058
8059 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8060 if (plane_config->tiling)
1ad292b5
JB		 8061 offset = I915_READ(DSPTILEOFF(plane));
8062 else
8063 offset = I915_READ(DSPLINOFF(plane));
8064 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8065 } else {
8066 base = I915_READ(DSPADDR(plane));
8067 }
8068 plane_config->base = base;
8069
8070 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8071 fb->width = ((val >> 16) & 0xfff) + 1;
8072 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8073
8074 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8075 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8076
b113d5ee 8077 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8078 fb->pixel_format,
8079 fb->modifier[0]);
1ad292b5 8080
f37b5c2b 8081 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8082
2844a921
DL		 8083 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8084 pipe_name(pipe), plane, fb->width, fb->height,
8085 fb->bits_per_pixel, base, fb->pitches[0],
8086 plane_config->size);
1ad292b5 8087
2d14030b 8088 plane_config->fb = intel_fb;
1ad292b5
JB		 8089}
8090
70b23a98 8091static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8092 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8093{
8094 struct drm_device *dev = crtc->base.dev;
8095 struct drm_i915_private *dev_priv = dev->dev_private;
8096 int pipe = pipe_config->cpu_transcoder;
8097 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8098 intel_clock_t clock;
8099 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8100 int refclk = 100000;
8101
a580516d 8102 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8103 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8104 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8105 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8106 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8107 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8108
8109 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8110 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8111 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8112 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8113 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8114
dccbea3b 8115 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8116}
8117
0e8ffe1b 8118static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8119 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8120{
8121 struct drm_device *dev = crtc->base.dev;
8122 struct drm_i915_private *dev_priv = dev->dev_private;
8123 uint32_t tmp;
8124
f458ebbc
DV		 8125 if (!intel_display_power_is_enabled(dev_priv,
8126 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8127 return false;
8128
e143a21c 8129 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8130 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8131
0e8ffe1b
DV		 8132 tmp = I915_READ(PIPECONF(crtc->pipe));
8133 if (!(tmp & PIPECONF_ENABLE))
8134 return false;
8135
42571aef
VS		 8136 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8137 switch (tmp & PIPECONF_BPC_MASK) {
8138 case PIPECONF_6BPC:
8139 pipe_config->pipe_bpp = 18;
8140 break;
8141 case PIPECONF_8BPC:
8142 pipe_config->pipe_bpp = 24;
8143 break;
8144 case PIPECONF_10BPC:
8145 pipe_config->pipe_bpp = 30;
8146 break;
8147 default:
8148 break;
8149 }
8150 }
8151
b5a9fa09
DV		 8152 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8153 pipe_config->limited_color_range = true;
8154
282740f7
VS		 8155 if (INTEL_INFO(dev)->gen < 4)
8156 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8157
1bd1bd80
DV		 8158 intel_get_pipe_timings(crtc, pipe_config);
8159
2fa2fe9a
DV		 8160 i9xx_get_pfit_config(crtc, pipe_config);
8161
6c49f241
DV		 8162 if (INTEL_INFO(dev)->gen >= 4) {
8163 tmp = I915_READ(DPLL_MD(crtc->pipe));
8164 pipe_config->pixel_multiplier =
8165 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8166 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8167 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8168 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8169 tmp = I915_READ(DPLL(crtc->pipe));
8170 pipe_config->pixel_multiplier =
8171 ((tmp & SDVO_MULTIPLIER_MASK)
8172 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8173 } else {
8174 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8175 * port and will be fixed up in the encoder->get_config
8176 * function. */
8177 pipe_config->pixel_multiplier = 1;
8178 }
8bcc2795
DV		 8179 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8180 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8181 /*
8182 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8183 * on 830. Filter it out here so that we don't
8184 * report errors due to that.
8185 */
8186 if (IS_I830(dev))
8187 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8188
8bcc2795
DV		 8189 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8190 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8191 } else {
8192 /* Mask out read-only status bits. */
8193 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8194 DPLL_PORTC_READY_MASK |
8195 DPLL_PORTB_READY_MASK);
8bcc2795 8196 }
6c49f241 8197
70b23a98
VS		 8198 if (IS_CHERRYVIEW(dev))
8199 chv_crtc_clock_get(crtc, pipe_config);
8200 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8201 vlv_crtc_clock_get(crtc, pipe_config);
8202 else
8203 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8204
0e8ffe1b
DV		 8205 return true;
8206}
8207
dde86e2d 8208static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8209{
8210 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8211 struct intel_encoder *encoder;
74cfd7ac 8212 u32 val, final;
13d83a67 8213 bool has_lvds = false;
199e5d79 8214 bool has_cpu_edp = false;
199e5d79 8215 bool has_panel = false;
99eb6a01
KP		 8216 bool has_ck505 = false;
8217 bool can_ssc = false;
13d83a67
JB		 8218
8219 /* We need to take the global config into account */
b2784e15 8220 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8221 switch (encoder->type) {
8222 case INTEL_OUTPUT_LVDS:
8223 has_panel = true;
8224 has_lvds = true;
8225 break;
8226 case INTEL_OUTPUT_EDP:
8227 has_panel = true;
2de6905f 8228 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8229 has_cpu_edp = true;
8230 break;
6847d71b
PZ		 8231 default:
8232 break;
13d83a67
JB		 8233 }
8234 }
8235
99eb6a01 8236 if (HAS_PCH_IBX(dev)) {
41aa3448 8237 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8238 can_ssc = has_ck505;
8239 } else {
8240 has_ck505 = false;
8241 can_ssc = true;
8242 }
8243
2de6905f
ID		 8244 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8245 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8246
8247 /* Ironlake: try to setup display ref clock before DPLL
8248 * enabling. This is only under driver's control after
8249 * PCH B stepping, previous chipset stepping should be
8250 * ignoring this setting.
8251 */
74cfd7ac
CW		 8252 val = I915_READ(PCH_DREF_CONTROL);
8253
8254 /* As we must carefully and slowly disable/enable each source in turn,
8255 * compute the final state we want first and check if we need to
8256 * make any changes at all.
8257 */
8258 final = val;
8259 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8260 if (has_ck505)
8261 final |= DREF_NONSPREAD_CK505_ENABLE;
8262 else
8263 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8264
8265 final &= ~DREF_SSC_SOURCE_MASK;
8266 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8267 final &= ~DREF_SSC1_ENABLE;
8268
8269 if (has_panel) {
8270 final |= DREF_SSC_SOURCE_ENABLE;
8271
8272 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8273 final |= DREF_SSC1_ENABLE;
8274
8275 if (has_cpu_edp) {
8276 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8277 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8278 else
8279 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8280 } else
8281 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8282 } else {
8283 final |= DREF_SSC_SOURCE_DISABLE;
8284 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8285 }
8286
8287 if (final == val)
8288 return;
8289
13d83a67 8290 /* Always enable nonspread source */
74cfd7ac 8291 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8292
99eb6a01 8293 if (has_ck505)
74cfd7ac 8294 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8295 else
74cfd7ac 8296 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8297
199e5d79 8298 if (has_panel) {
74cfd7ac
CW		 8299 val &= ~DREF_SSC_SOURCE_MASK;
8300 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8301
199e5d79 8302 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8303 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8304 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8305 val |= DREF_SSC1_ENABLE;
e77166b5 8306 } else
74cfd7ac 8307 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8308
8309 /* Get SSC going before enabling the outputs */
74cfd7ac 8310 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8311 POSTING_READ(PCH_DREF_CONTROL);
8312 udelay(200);
8313
74cfd7ac 8314 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8315
8316 /* Enable CPU source on CPU attached eDP */
199e5d79 8317 if (has_cpu_edp) {
99eb6a01 8318 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8319 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8320 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8321 } else
74cfd7ac 8322 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8323 } else
74cfd7ac 8324 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8325
74cfd7ac 8326 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8327 POSTING_READ(PCH_DREF_CONTROL);
8328 udelay(200);
8329 } else {
8330 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8331
74cfd7ac 8332 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8333
8334 /* Turn off CPU output */
74cfd7ac 8335 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8336
74cfd7ac 8337 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8338 POSTING_READ(PCH_DREF_CONTROL);
8339 udelay(200);
8340
8341 /* Turn off the SSC source */
74cfd7ac
CW		 8342 val &= ~DREF_SSC_SOURCE_MASK;
8343 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8344
8345 /* Turn off SSC1 */
74cfd7ac 8346 val &= ~DREF_SSC1_ENABLE;
199e5d79 8347
74cfd7ac 8348 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8349 POSTING_READ(PCH_DREF_CONTROL);
8350 udelay(200);
8351 }
74cfd7ac
CW		 8352
8353 BUG_ON(val != final);
13d83a67
JB		 8354}
8355
f31f2d55 8356static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8357{
f31f2d55 8358 uint32_t tmp;
dde86e2d 8359
0ff066a9
PZ		 8360 tmp = I915_READ(SOUTH_CHICKEN2);
8361 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8362 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8363
0ff066a9
PZ		 8364 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8365 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8366 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8367
0ff066a9
PZ		 8368 tmp = I915_READ(SOUTH_CHICKEN2);
8369 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8370 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8371
0ff066a9
PZ		 8372 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8373 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8374 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8375}
8376
8377/* WaMPhyProgramming:hsw */
8378static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8379{
8380 uint32_t tmp;
dde86e2d
PZ		 8381
8382 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8383 tmp &= ~(0xFF << 24);
8384 tmp |= (0x12 << 24);
8385 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8386
dde86e2d
PZ		 8387 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8388 tmp |= (1 << 11);
8389 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8390
8391 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8392 tmp |= (1 << 11);
8393 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8394
dde86e2d
PZ		 8395 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8396 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8397 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8398
8399 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8400 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8401 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8402
0ff066a9
PZ		 8403 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8404 tmp &= ~(7 << 13);
8405 tmp |= (5 << 13);
8406 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8407
0ff066a9
PZ		 8408 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8409 tmp &= ~(7 << 13);
8410 tmp |= (5 << 13);
8411 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8412
8413 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8414 tmp &= ~0xFF;
8415 tmp |= 0x1C;
8416 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8417
8418 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8419 tmp &= ~0xFF;
8420 tmp |= 0x1C;
8421 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8422
8423 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8424 tmp &= ~(0xFF << 16);
8425 tmp |= (0x1C << 16);
8426 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8427
8428 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8429 tmp &= ~(0xFF << 16);
8430 tmp |= (0x1C << 16);
8431 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8432
0ff066a9
PZ		 8433 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8434 tmp |= (1 << 27);
8435 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8436
0ff066a9
PZ		 8437 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8438 tmp |= (1 << 27);
8439 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8440
0ff066a9
PZ		 8441 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8442 tmp &= ~(0xF << 28);
8443 tmp |= (4 << 28);
8444 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8445
0ff066a9
PZ		 8446 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8447 tmp &= ~(0xF << 28);
8448 tmp |= (4 << 28);
8449 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8450}
8451
2fa86a1f
PZ		 8452/* Implements 3 different sequences from BSpec chapter "Display iCLK
8453 * Programming" based on the parameters passed:
8454 * - Sequence to enable CLKOUT_DP
8455 * - Sequence to enable CLKOUT_DP without spread
8456 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8457 */
8458static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8459 bool with_fdi)
f31f2d55
PZ		 8460{
8461 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8462 uint32_t reg, tmp;
8463
8464 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8465 with_spread = true;
8466 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8467 with_fdi, "LP PCH doesn't have FDI\n"))
8468 with_fdi = false;
f31f2d55 8469
a580516d 8470 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8471
8472 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8473 tmp &= ~SBI_SSCCTL_DISABLE;
8474 tmp |= SBI_SSCCTL_PATHALT;
8475 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8476
8477 udelay(24);
8478
2fa86a1f
PZ		 8479 if (with_spread) {
8480 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8481 tmp &= ~SBI_SSCCTL_PATHALT;
8482 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8483
2fa86a1f
PZ		 8484 if (with_fdi) {
8485 lpt_reset_fdi_mphy(dev_priv);
8486 lpt_program_fdi_mphy(dev_priv);
8487 }
8488 }
dde86e2d 8489
2fa86a1f
PZ		 8490 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8491 SBI_GEN0 : SBI_DBUFF0;
8492 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8493 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8494 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8495
a580516d 8496 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8497}
8498
47701c3b
PZ		 8499/* Sequence to disable CLKOUT_DP */
8500static void lpt_disable_clkout_dp(struct drm_device *dev)
8501{
8502 struct drm_i915_private *dev_priv = dev->dev_private;
8503 uint32_t reg, tmp;
8504
a580516d 8505 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8506
8507 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8508 SBI_GEN0 : SBI_DBUFF0;
8509 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8510 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8511 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8512
8513 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8514 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8515 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8516 tmp |= SBI_SSCCTL_PATHALT;
8517 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8518 udelay(32);
8519 }
8520 tmp |= SBI_SSCCTL_DISABLE;
8521 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8522 }
8523
a580516d 8524 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8525}
8526
bf8fa3d3
PZ		 8527static void lpt_init_pch_refclk(struct drm_device *dev)
8528{
bf8fa3d3
PZ		 8529 struct intel_encoder *encoder;
8530 bool has_vga = false;
8531
b2784e15 8532 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8533 switch (encoder->type) {
8534 case INTEL_OUTPUT_ANALOG:
8535 has_vga = true;
8536 break;
6847d71b
PZ		 8537 default:
8538 break;
bf8fa3d3
PZ		 8539 }
8540 }
8541
47701c3b
PZ		 8542 if (has_vga)
8543 lpt_enable_clkout_dp(dev, true, true);
8544 else
8545 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8546}
8547
dde86e2d
PZ		 8548/*
8549 * Initialize reference clocks when the driver loads
8550 */
8551void intel_init_pch_refclk(struct drm_device *dev)
8552{
8553 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8554 ironlake_init_pch_refclk(dev);
8555 else if (HAS_PCH_LPT(dev))
8556 lpt_init_pch_refclk(dev);
8557}
8558
55bb9992 8559static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8560{
55bb9992 8561 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8562 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8563 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8564 struct drm_connector *connector;
55bb9992 8565 struct drm_connector_state *connector_state;
d9d444cb 8566 struct intel_encoder *encoder;
55bb9992 8567 int num_connectors = 0, i;
d9d444cb
JB		 8568 bool is_lvds = false;
8569
da3ced29 8570 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8571 if (connector_state->crtc != crtc_state->base.crtc)
8572 continue;
8573
8574 encoder = to_intel_encoder(connector_state->best_encoder);
8575
d9d444cb
JB		 8576 switch (encoder->type) {
8577 case INTEL_OUTPUT_LVDS:
8578 is_lvds = true;
8579 break;
6847d71b
PZ		 8580 default:
8581 break;
d9d444cb
JB		 8582 }
8583 num_connectors++;
8584 }
8585
8586 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8587 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8588 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8589 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8590 }
8591
8592 return 120000;
8593}
8594
6ff93609 8595static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8596{
c8203565 8597 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8599 int pipe = intel_crtc->pipe;
c8203565
PZ		 8600 uint32_t val;
8601
78114071 8602 val = 0;
c8203565 8603
6e3c9717 8604 switch (intel_crtc->config->pipe_bpp) {
c8203565 8605 case 18:
dfd07d72 8606 val |= PIPECONF_6BPC;
c8203565
PZ		 8607 break;
8608 case 24:
dfd07d72 8609 val |= PIPECONF_8BPC;
c8203565
PZ		 8610 break;
8611 case 30:
dfd07d72 8612 val |= PIPECONF_10BPC;
c8203565
PZ		 8613 break;
8614 case 36:
dfd07d72 8615 val |= PIPECONF_12BPC;
c8203565
PZ		 8616 break;
8617 default:
cc769b62
PZ		 8618 /* Case prevented by intel_choose_pipe_bpp_dither. */
8619 BUG();
c8203565
PZ		 8620 }
8621
6e3c9717 8622 if (intel_crtc->config->dither)
c8203565
PZ		 8623 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8624
6e3c9717 8625 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8626 val |= PIPECONF_INTERLACED_ILK;
8627 else
8628 val |= PIPECONF_PROGRESSIVE;
8629
6e3c9717 8630 if (intel_crtc->config->limited_color_range)
3685a8f3 8631 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8632
c8203565
PZ		 8633 I915_WRITE(PIPECONF(pipe), val);
8634 POSTING_READ(PIPECONF(pipe));
8635}
8636
86d3efce
VS		 8637/*
8638 * Set up the pipe CSC unit.
8639 *
8640 * Currently only full range RGB to limited range RGB conversion
8641 * is supported, but eventually this should handle various
8642 * RGB<->YCbCr scenarios as well.
8643 */
50f3b016 8644static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8645{
8646 struct drm_device *dev = crtc->dev;
8647 struct drm_i915_private *dev_priv = dev->dev_private;
8648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8649 int pipe = intel_crtc->pipe;
8650 uint16_t coeff = 0x7800; /* 1.0 */
8651
8652 /*
8653 * TODO: Check what kind of values actually come out of the pipe
8654 * with these coeff/postoff values and adjust to get the best
8655 * accuracy. Perhaps we even need to take the bpc value into
8656 * consideration.
8657 */
8658
6e3c9717 8659 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8660 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8661
8662 /*
8663 * GY/GU and RY/RU should be the other way around according
8664 * to BSpec, but reality doesn't agree. Just set them up in
8665 * a way that results in the correct picture.
8666 */
8667 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8668 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8669
8670 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8671 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8672
8673 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8674 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8675
8676 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8677 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8678 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8679
8680 if (INTEL_INFO(dev)->gen > 6) {
8681 uint16_t postoff = 0;
8682
6e3c9717 8683 if (intel_crtc->config->limited_color_range)
32cf0cb0 8684 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8685
8686 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8687 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8688 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8689
8690 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8691 } else {
8692 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8693
6e3c9717 8694 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8695 mode |= CSC_BLACK_SCREEN_OFFSET;
8696
8697 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8698 }
8699}
8700
6ff93609 8701static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8702{
756f85cf
PZ		 8703 struct drm_device *dev = crtc->dev;
8704 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8706 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8707 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8708 uint32_t val;
8709
3eff4faa 8710 val = 0;
ee2b0b38 8711
6e3c9717 8712 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8713 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8714
6e3c9717 8715 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8716 val |= PIPECONF_INTERLACED_ILK;
8717 else
8718 val |= PIPECONF_PROGRESSIVE;
8719
702e7a56
PZ		 8720 I915_WRITE(PIPECONF(cpu_transcoder), val);
8721 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8722
8723 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8724 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8725
3cdf122c 8726 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8727 val = 0;
8728
6e3c9717 8729 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8730 case 18:
8731 val |= PIPEMISC_DITHER_6_BPC;
8732 break;
8733 case 24:
8734 val |= PIPEMISC_DITHER_8_BPC;
8735 break;
8736 case 30:
8737 val |= PIPEMISC_DITHER_10_BPC;
8738 break;
8739 case 36:
8740 val |= PIPEMISC_DITHER_12_BPC;
8741 break;
8742 default:
8743 /* Case prevented by pipe_config_set_bpp. */
8744 BUG();
8745 }
8746
6e3c9717 8747 if (intel_crtc->config->dither)
756f85cf
PZ		 8748 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8749
8750 I915_WRITE(PIPEMISC(pipe), val);
8751 }
ee2b0b38
PZ		 8752}
8753
6591c6e4 8754static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8755 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8756 intel_clock_t *clock,
8757 bool *has_reduced_clock,
8758 intel_clock_t *reduced_clock)
8759{
8760 struct drm_device *dev = crtc->dev;
8761 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8762 int refclk;
d4906093 8763 const intel_limit_t *limit;
c329a4ec 8764 bool ret;
79e53945 8765
55bb9992 8766 refclk = ironlake_get_refclk(crtc_state);
79e53945 8767
d4906093
ML		 8768 /*
8769 * Returns a set of divisors for the desired target clock with the given
8770 * refclk, or FALSE. The returned values represent the clock equation:
8771 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8772 */
a93e255f
ACO		 8773 limit = intel_limit(crtc_state, refclk);
8774 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8775 crtc_state->port_clock,
ee9300bb 8776 refclk, NULL, clock);
6591c6e4
PZ		 8777 if (!ret)
8778 return false;
cda4b7d3 8779
6591c6e4
PZ		 8780 return true;
8781}
8782
d4b1931c
PZ		 8783int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8784{
8785 /*
8786 * Account for spread spectrum to avoid
8787 * oversubscribing the link. Max center spread
8788 * is 2.5%; use 5% for safety's sake.
8789 */
8790 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8791 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8792}
8793
7429e9d4 8794static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8795{
7429e9d4 8796 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8797}
8798
de13a2e3 8799static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8800 struct intel_crtc_state *crtc_state,
7429e9d4 8801 u32 *fp,
9a7c7890 8802 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8803{
de13a2e3 8804 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8805 struct drm_device *dev = crtc->dev;
8806 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8807 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8808 struct drm_connector *connector;
55bb9992
ACO		 8809 struct drm_connector_state *connector_state;
8810 struct intel_encoder *encoder;
de13a2e3 8811 uint32_t dpll;
55bb9992 8812 int factor, num_connectors = 0, i;
09ede541 8813 bool is_lvds = false, is_sdvo = false;
79e53945 8814
da3ced29 8815 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8816 if (connector_state->crtc != crtc_state->base.crtc)
8817 continue;
8818
8819 encoder = to_intel_encoder(connector_state->best_encoder);
8820
8821 switch (encoder->type) {
79e53945
JB		 8822 case INTEL_OUTPUT_LVDS:
8823 is_lvds = true;
8824 break;
8825 case INTEL_OUTPUT_SDVO:
7d57382e 8826 case INTEL_OUTPUT_HDMI:
79e53945 8827 is_sdvo = true;
79e53945 8828 break;
6847d71b
PZ		 8829 default:
8830 break;
79e53945 8831 }
43565a06 8832
c751ce4f 8833 num_connectors++;
79e53945 8834 }
79e53945 8835
c1858123 8836 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8837 factor = 21;
8838 if (is_lvds) {
8839 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8840 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8841 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8842 factor = 25;
190f68c5 8843 } else if (crtc_state->sdvo_tv_clock)
8febb297 8844 factor = 20;
c1858123 8845
190f68c5 8846 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8847 *fp |= FP_CB_TUNE;
2c07245f 8848
9a7c7890
DV		 8849 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8850 *fp2 |= FP_CB_TUNE;
8851
5eddb70b 8852 dpll = 0;
2c07245f 8853
a07d6787
EA		 8854 if (is_lvds)
8855 dpll |= DPLLB_MODE_LVDS;
8856 else
8857 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8858
190f68c5 8859 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8860 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8861
8862 if (is_sdvo)
4a33e48d 8863 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8864 if (crtc_state->has_dp_encoder)
4a33e48d 8865 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8866
a07d6787 8867 /* compute bitmask from p1 value */
190f68c5 8868 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8869 /* also FPA1 */
190f68c5 8870 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8871
190f68c5 8872 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8873 case 5:
8874 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8875 break;
8876 case 7:
8877 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8878 break;
8879 case 10:
8880 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8881 break;
8882 case 14:
8883 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8884 break;
79e53945
JB		 8885 }
8886
b4c09f3b 8887 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8888 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8889 else
8890 dpll |= PLL_REF_INPUT_DREFCLK;
8891
959e16d6 8892 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8893}
8894
190f68c5
ACO		 8895static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8896 struct intel_crtc_state *crtc_state)
de13a2e3 8897{
c7653199 8898 struct drm_device *dev = crtc->base.dev;
de13a2e3 8899 intel_clock_t clock, reduced_clock;
cbbab5bd 8900 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8901 bool ok, has_reduced_clock = false;
8b47047b 8902 bool is_lvds = false;
e2b78267 8903 struct intel_shared_dpll *pll;
de13a2e3 8904
dd3cd74a
ACO		 8905 memset(&crtc_state->dpll_hw_state, 0,
8906 sizeof(crtc_state->dpll_hw_state));
8907
409ee761 8908 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8909
5dc5298b
PZ		 8910 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8911 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8912
190f68c5 8913 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8914 &has_reduced_clock, &reduced_clock);
190f68c5 8915 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8916 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8917 return -EINVAL;
79e53945 8918 }
f47709a9 8919 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8920 if (!crtc_state->clock_set) {
8921 crtc_state->dpll.n = clock.n;
8922 crtc_state->dpll.m1 = clock.m1;
8923 crtc_state->dpll.m2 = clock.m2;
8924 crtc_state->dpll.p1 = clock.p1;
8925 crtc_state->dpll.p2 = clock.p2;
f47709a9 8926 }
79e53945 8927
5dc5298b 8928 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8929 if (crtc_state->has_pch_encoder) {
8930 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8931 if (has_reduced_clock)
7429e9d4 8932 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8933
190f68c5 8934 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8935 &fp, &reduced_clock,
8936 has_reduced_clock ? &fp2 : NULL);
8937
190f68c5
ACO		 8938 crtc_state->dpll_hw_state.dpll = dpll;
8939 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8940 if (has_reduced_clock)
190f68c5 8941 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8942 else
190f68c5 8943 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8944
190f68c5 8945 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8946 if (pll == NULL) {
84f44ce7 8947 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8948 pipe_name(crtc->pipe));
4b645f14
JB		 8949 return -EINVAL;
8950 }
3fb37703 8951 }
79e53945 8952
ab585dea 8953 if (is_lvds && has_reduced_clock)
c7653199 8954 crtc->lowfreq_avail = true;
bcd644e0 8955 else
c7653199 8956 crtc->lowfreq_avail = false;
e2b78267 8957
c8f7a0db 8958 return 0;
79e53945
JB		 8959}
8960
eb14cb74
VS		 8961static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8962 struct intel_link_m_n *m_n)
8963{
8964 struct drm_device *dev = crtc->base.dev;
8965 struct drm_i915_private *dev_priv = dev->dev_private;
8966 enum pipe pipe = crtc->pipe;
8967
8968 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8969 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8970 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8971 & ~TU_SIZE_MASK;
8972 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8973 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8974 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8975}
8976
8977static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8978 enum transcoder transcoder,
b95af8be
VK		 8979 struct intel_link_m_n *m_n,
8980 struct intel_link_m_n *m2_n2)
72419203
DV		 8981{
8982 struct drm_device *dev = crtc->base.dev;
8983 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8984 enum pipe pipe = crtc->pipe;
72419203 8985
eb14cb74
VS		 8986 if (INTEL_INFO(dev)->gen >= 5) {
8987 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8988 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8989 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8990 & ~TU_SIZE_MASK;
8991 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8992 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8993 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8994 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8995 * gen < 8) and if DRRS is supported (to make sure the
8996 * registers are not unnecessarily read).
8997 */
8998 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8999 crtc->config->has_drrs) {
b95af8be
VK		 9000 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9001 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9002 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9003 & ~TU_SIZE_MASK;
9004 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9005 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9006 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9007 }
eb14cb74
VS		 9008 } else {
9009 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9010 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9011 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9012 & ~TU_SIZE_MASK;
9013 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9014 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9015 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9016 }
9017}
9018
9019void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 9020 struct intel_crtc_state *pipe_config)
eb14cb74 9021{
681a8504 9022 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 9023 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9024 else
9025 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 9026 &pipe_config->dp_m_n,
9027 &pipe_config->dp_m2_n2);
eb14cb74 9028}
72419203 9029
eb14cb74 9030static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 9031 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 9032{
9033 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 9034 &pipe_config->fdi_m_n, NULL);
72419203
DV		 9035}
9036
bd2e244f 9037static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9038 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 9039{
9040 struct drm_device *dev = crtc->base.dev;
9041 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 9042 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9043 uint32_t ps_ctrl = 0;
9044 int id = -1;
9045 int i;
bd2e244f 9046
a1b2278e
CK		 9047 /* find scaler attached to this pipe */
9048 for (i = 0; i < crtc->num_scalers; i++) {
9049 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9050 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9051 id = i;
9052 pipe_config->pch_pfit.enabled = true;
9053 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9054 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9055 break;
9056 }
9057 }
bd2e244f 9058
a1b2278e
CK		 9059 scaler_state->scaler_id = id;
9060 if (id >= 0) {
9061 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9062 } else {
9063 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9064 }
9065}
9066
5724dbd1
DL		 9067static void
9068skylake_get_initial_plane_config(struct intel_crtc *crtc,
9069 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9070{
9071 struct drm_device *dev = crtc->base.dev;
9072 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9073 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9074 int pipe = crtc->pipe;
9075 int fourcc, pixel_format;
6761dd31 9076 unsigned int aligned_height;
bc8d7dff 9077 struct drm_framebuffer *fb;
1b842c89 9078 struct intel_framebuffer *intel_fb;
bc8d7dff 9079
d9806c9f 9080 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9081 if (!intel_fb) {
bc8d7dff
DL		 9082 DRM_DEBUG_KMS("failed to alloc fb\n");
9083 return;
9084 }
9085
1b842c89
DL		 9086 fb = &intel_fb->base;
9087
bc8d7dff 9088 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9089 if (!(val & PLANE_CTL_ENABLE))
9090 goto error;
9091
bc8d7dff
DL		 9092 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9093 fourcc = skl_format_to_fourcc(pixel_format,
9094 val & PLANE_CTL_ORDER_RGBX,
9095 val & PLANE_CTL_ALPHA_MASK);
9096 fb->pixel_format = fourcc;
9097 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9098
40f46283
DL		 9099 tiling = val & PLANE_CTL_TILED_MASK;
9100 switch (tiling) {
9101 case PLANE_CTL_TILED_LINEAR:
9102 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9103 break;
9104 case PLANE_CTL_TILED_X:
9105 plane_config->tiling = I915_TILING_X;
9106 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9107 break;
9108 case PLANE_CTL_TILED_Y:
9109 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9110 break;
9111 case PLANE_CTL_TILED_YF:
9112 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9113 break;
9114 default:
9115 MISSING_CASE(tiling);
9116 goto error;
9117 }
9118
bc8d7dff
DL		 9119 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9120 plane_config->base = base;
9121
9122 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9123
9124 val = I915_READ(PLANE_SIZE(pipe, 0));
9125 fb->height = ((val >> 16) & 0xfff) + 1;
9126 fb->width = ((val >> 0) & 0x1fff) + 1;
9127
9128 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9129 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9130 fb->pixel_format);
bc8d7dff
DL		 9131 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9132
9133 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9134 fb->pixel_format,
9135 fb->modifier[0]);
bc8d7dff 9136
f37b5c2b 9137 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9138
9139 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9140 pipe_name(pipe), fb->width, fb->height,
9141 fb->bits_per_pixel, base, fb->pitches[0],
9142 plane_config->size);
9143
2d14030b 9144 plane_config->fb = intel_fb;
bc8d7dff
DL		 9145 return;
9146
9147error:
9148 kfree(fb);
9149}
9150
2fa2fe9a 9151static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9152 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9153{
9154 struct drm_device *dev = crtc->base.dev;
9155 struct drm_i915_private *dev_priv = dev->dev_private;
9156 uint32_t tmp;
9157
9158 tmp = I915_READ(PF_CTL(crtc->pipe));
9159
9160 if (tmp & PF_ENABLE) {
fd4daa9c 9161 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9162 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9163 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9164
9165 /* We currently do not free assignements of panel fitters on
9166 * ivb/hsw (since we don't use the higher upscaling modes which
9167 * differentiates them) so just WARN about this case for now. */
9168 if (IS_GEN7(dev)) {
9169 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9170 PF_PIPE_SEL_IVB(crtc->pipe));
9171 }
2fa2fe9a 9172 }
79e53945
JB		 9173}
9174
5724dbd1
DL		 9175static void
9176ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9177 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9178{
9179 struct drm_device *dev = crtc->base.dev;
9180 struct drm_i915_private *dev_priv = dev->dev_private;
9181 u32 val, base, offset;
aeee5a49 9182 int pipe = crtc->pipe;
4c6baa59 9183 int fourcc, pixel_format;
6761dd31 9184 unsigned int aligned_height;
b113d5ee 9185 struct drm_framebuffer *fb;
1b842c89 9186 struct intel_framebuffer *intel_fb;
4c6baa59 9187
42a7b088
DL		 9188 val = I915_READ(DSPCNTR(pipe));
9189 if (!(val & DISPLAY_PLANE_ENABLE))
9190 return;
9191
d9806c9f 9192 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9193 if (!intel_fb) {
4c6baa59
JB		 9194 DRM_DEBUG_KMS("failed to alloc fb\n");
9195 return;
9196 }
9197
1b842c89
DL		 9198 fb = &intel_fb->base;
9199
18c5247e
DV		 9200 if (INTEL_INFO(dev)->gen >= 4) {
9201 if (val & DISPPLANE_TILED) {
49af449b 9202 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9203 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9204 }
9205 }
4c6baa59
JB		 9206
9207 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9208 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9209 fb->pixel_format = fourcc;
9210 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9211
aeee5a49 9212 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9213 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9214 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9215 } else {
49af449b 9216 if (plane_config->tiling)
aeee5a49 9217 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9218 else
aeee5a49 9219 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9220 }
9221 plane_config->base = base;
9222
9223 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9224 fb->width = ((val >> 16) & 0xfff) + 1;
9225 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9226
9227 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9228 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9229
b113d5ee 9230 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9231 fb->pixel_format,
9232 fb->modifier[0]);
4c6baa59 9233
f37b5c2b 9234 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9235
2844a921
DL		 9236 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9237 pipe_name(pipe), fb->width, fb->height,
9238 fb->bits_per_pixel, base, fb->pitches[0],
9239 plane_config->size);
b113d5ee 9240
2d14030b 9241 plane_config->fb = intel_fb;
4c6baa59
JB		 9242}
9243
0e8ffe1b 9244static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9245 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9246{
9247 struct drm_device *dev = crtc->base.dev;
9248 struct drm_i915_private *dev_priv = dev->dev_private;
9249 uint32_t tmp;
9250
f458ebbc
DV		 9251 if (!intel_display_power_is_enabled(dev_priv,
9252 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9253 return false;
9254
e143a21c 9255 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9256 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9257
0e8ffe1b
DV		 9258 tmp = I915_READ(PIPECONF(crtc->pipe));
9259 if (!(tmp & PIPECONF_ENABLE))
9260 return false;
9261
42571aef
VS		 9262 switch (tmp & PIPECONF_BPC_MASK) {
9263 case PIPECONF_6BPC:
9264 pipe_config->pipe_bpp = 18;
9265 break;
9266 case PIPECONF_8BPC:
9267 pipe_config->pipe_bpp = 24;
9268 break;
9269 case PIPECONF_10BPC:
9270 pipe_config->pipe_bpp = 30;
9271 break;
9272 case PIPECONF_12BPC:
9273 pipe_config->pipe_bpp = 36;
9274 break;
9275 default:
9276 break;
9277 }
9278
b5a9fa09
DV		 9279 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9280 pipe_config->limited_color_range = true;
9281
ab9412ba 9282 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9283 struct intel_shared_dpll *pll;
9284
88adfff1
DV		 9285 pipe_config->has_pch_encoder = true;
9286
627eb5a3
DV		 9287 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9288 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9289 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9290
9291 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9292
c0d43d62 9293 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9294 pipe_config->shared_dpll =
9295 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9296 } else {
9297 tmp = I915_READ(PCH_DPLL_SEL);
9298 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9299 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9300 else
9301 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9302 }
66e985c0
DV		 9303
9304 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9305
9306 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9307 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9308
9309 tmp = pipe_config->dpll_hw_state.dpll;
9310 pipe_config->pixel_multiplier =
9311 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9312 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9313
9314 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9315 } else {
9316 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9317 }
9318
1bd1bd80
DV		 9319 intel_get_pipe_timings(crtc, pipe_config);
9320
2fa2fe9a
DV		 9321 ironlake_get_pfit_config(crtc, pipe_config);
9322
0e8ffe1b
DV		 9323 return true;
9324}
9325
be256dc7
PZ		 9326static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9327{
9328 struct drm_device *dev = dev_priv->dev;
be256dc7 9329 struct intel_crtc *crtc;
be256dc7 9330
d3fcc808 9331 for_each_intel_crtc(dev, crtc)
e2c719b7 9332 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9333 pipe_name(crtc->pipe));
9334
e2c719b7
RC		 9335 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9336 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9337 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9338 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9339 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9340 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9341 "CPU PWM1 enabled\n");
c5107b87 9342 if (IS_HASWELL(dev))
e2c719b7 9343 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9344 "CPU PWM2 enabled\n");
e2c719b7 9345 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9346 "PCH PWM1 enabled\n");
e2c719b7 9347 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9348 "Utility pin enabled\n");
e2c719b7 9349 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9350
9926ada1
PZ		 9351 /*
9352 * In theory we can still leave IRQs enabled, as long as only the HPD
9353 * interrupts remain enabled. We used to check for that, but since it's
9354 * gen-specific and since we only disable LCPLL after we fully disable
9355 * the interrupts, the check below should be enough.
9356 */
e2c719b7 9357 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9358}
9359
9ccd5aeb
PZ		 9360static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9361{
9362 struct drm_device *dev = dev_priv->dev;
9363
9364 if (IS_HASWELL(dev))
9365 return I915_READ(D_COMP_HSW);
9366 else
9367 return I915_READ(D_COMP_BDW);
9368}
9369
3c4c9b81
PZ		 9370static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9371{
9372 struct drm_device *dev = dev_priv->dev;
9373
9374 if (IS_HASWELL(dev)) {
9375 mutex_lock(&dev_priv->rps.hw_lock);
9376 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9377 val))
f475dadf 9378 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9379 mutex_unlock(&dev_priv->rps.hw_lock);
9380 } else {
9ccd5aeb
PZ		 9381 I915_WRITE(D_COMP_BDW, val);
9382 POSTING_READ(D_COMP_BDW);
3c4c9b81 9383 }
be256dc7
PZ		 9384}
9385
9386/*
9387 * This function implements pieces of two sequences from BSpec:
9388 * - Sequence for display software to disable LCPLL
9389 * - Sequence for display software to allow package C8+
9390 * The steps implemented here are just the steps that actually touch the LCPLL
9391 * register. Callers should take care of disabling all the display engine
9392 * functions, doing the mode unset, fixing interrupts, etc.
9393 */
6ff58d53
PZ		 9394static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9395 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9396{
9397 uint32_t val;
9398
9399 assert_can_disable_lcpll(dev_priv);
9400
9401 val = I915_READ(LCPLL_CTL);
9402
9403 if (switch_to_fclk) {
9404 val |= LCPLL_CD_SOURCE_FCLK;
9405 I915_WRITE(LCPLL_CTL, val);
9406
9407 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9408 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9409 DRM_ERROR("Switching to FCLK failed\n");
9410
9411 val = I915_READ(LCPLL_CTL);
9412 }
9413
9414 val |= LCPLL_PLL_DISABLE;
9415 I915_WRITE(LCPLL_CTL, val);
9416 POSTING_READ(LCPLL_CTL);
9417
9418 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9419 DRM_ERROR("LCPLL still locked\n");
9420
9ccd5aeb 9421 val = hsw_read_dcomp(dev_priv);
be256dc7 9422 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9423 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9424 ndelay(100);
9425
9ccd5aeb
PZ		 9426 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9427 1))
be256dc7
PZ		 9428 DRM_ERROR("D_COMP RCOMP still in progress\n");
9429
9430 if (allow_power_down) {
9431 val = I915_READ(LCPLL_CTL);
9432 val |= LCPLL_POWER_DOWN_ALLOW;
9433 I915_WRITE(LCPLL_CTL, val);
9434 POSTING_READ(LCPLL_CTL);
9435 }
9436}
9437
9438/*
9439 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9440 * source.
9441 */
6ff58d53 9442static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9443{
9444 uint32_t val;
9445
9446 val = I915_READ(LCPLL_CTL);
9447
9448 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9449 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9450 return;
9451
a8a8bd54
PZ		 9452 /*
9453 * Make sure we're not on PC8 state before disabling PC8, otherwise
9454 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9455 */
59bad947 9456 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9457
be256dc7
PZ		 9458 if (val & LCPLL_POWER_DOWN_ALLOW) {
9459 val &= ~LCPLL_POWER_DOWN_ALLOW;
9460 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9461 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9462 }
9463
9ccd5aeb 9464 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9465 val |= D_COMP_COMP_FORCE;
9466 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9467 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9468
9469 val = I915_READ(LCPLL_CTL);
9470 val &= ~LCPLL_PLL_DISABLE;
9471 I915_WRITE(LCPLL_CTL, val);
9472
9473 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9474 DRM_ERROR("LCPLL not locked yet\n");
9475
9476 if (val & LCPLL_CD_SOURCE_FCLK) {
9477 val = I915_READ(LCPLL_CTL);
9478 val &= ~LCPLL_CD_SOURCE_FCLK;
9479 I915_WRITE(LCPLL_CTL, val);
9480
9481 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9482 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9483 DRM_ERROR("Switching back to LCPLL failed\n");
9484 }
215733fa 9485
59bad947 9486 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9487 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9488}
9489
765dab67
PZ		 9490/*
9491 * Package states C8 and deeper are really deep PC states that can only be
9492 * reached when all the devices on the system allow it, so even if the graphics
9493 * device allows PC8+, it doesn't mean the system will actually get to these
9494 * states. Our driver only allows PC8+ when going into runtime PM.
9495 *
9496 * The requirements for PC8+ are that all the outputs are disabled, the power
9497 * well is disabled and most interrupts are disabled, and these are also
9498 * requirements for runtime PM. When these conditions are met, we manually do
9499 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9500 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9501 * hang the machine.
9502 *
9503 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9504 * the state of some registers, so when we come back from PC8+ we need to
9505 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9506 * need to take care of the registers kept by RC6. Notice that this happens even
9507 * if we don't put the device in PCI D3 state (which is what currently happens
9508 * because of the runtime PM support).
9509 *
9510 * For more, read "Display Sequences for Package C8" on the hardware
9511 * documentation.
9512 */
a14cb6fc 9513void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9514{
c67a470b
PZ		 9515 struct drm_device *dev = dev_priv->dev;
9516 uint32_t val;
9517
c67a470b
PZ		 9518 DRM_DEBUG_KMS("Enabling package C8+\n");
9519
c67a470b
PZ		 9520 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9521 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9522 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9523 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9524 }
9525
9526 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9527 hsw_disable_lcpll(dev_priv, true, true);
9528}
9529
a14cb6fc 9530void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9531{
9532 struct drm_device *dev = dev_priv->dev;
9533 uint32_t val;
9534
c67a470b
PZ		 9535 DRM_DEBUG_KMS("Disabling package C8+\n");
9536
9537 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9538 lpt_init_pch_refclk(dev);
9539
9540 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9541 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9542 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9543 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9544 }
9545
9546 intel_prepare_ddi(dev);
c67a470b
PZ		 9547}
9548
27c329ed 9549static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9550{
a821fc46 9551 struct drm_device *dev = old_state->dev;
27c329ed 9552 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9553
27c329ed 9554 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9555}
9556
b432e5cf 9557/* compute the max rate for new configuration */
27c329ed 9558static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9559{
b432e5cf 9560 struct intel_crtc *intel_crtc;
27c329ed 9561 struct intel_crtc_state *crtc_state;
b432e5cf 9562 int max_pixel_rate = 0;
b432e5cf 9563
27c329ed
ML		 9564 for_each_intel_crtc(state->dev, intel_crtc) {
9565 int pixel_rate;
9566
9567 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9568 if (IS_ERR(crtc_state))
9569 return PTR_ERR(crtc_state);
9570
9571 if (!crtc_state->base.enable)
b432e5cf
VS		 9572 continue;
9573
27c329ed 9574 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9575
9576 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9577 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9578 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9579
9580 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9581 }
9582
9583 return max_pixel_rate;
9584}
9585
9586static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9587{
9588 struct drm_i915_private *dev_priv = dev->dev_private;
9589 uint32_t val, data;
9590 int ret;
9591
9592 if (WARN((I915_READ(LCPLL_CTL) &
9593 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9594 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9595 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9596 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9597 "trying to change cdclk frequency with cdclk not enabled\n"))
9598 return;
9599
9600 mutex_lock(&dev_priv->rps.hw_lock);
9601 ret = sandybridge_pcode_write(dev_priv,
9602 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9603 mutex_unlock(&dev_priv->rps.hw_lock);
9604 if (ret) {
9605 DRM_ERROR("failed to inform pcode about cdclk change\n");
9606 return;
9607 }
9608
9609 val = I915_READ(LCPLL_CTL);
9610 val |= LCPLL_CD_SOURCE_FCLK;
9611 I915_WRITE(LCPLL_CTL, val);
9612
9613 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9614 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9615 DRM_ERROR("Switching to FCLK failed\n");
9616
9617 val = I915_READ(LCPLL_CTL);
9618 val &= ~LCPLL_CLK_FREQ_MASK;
9619
9620 switch (cdclk) {
9621 case 450000:
9622 val |= LCPLL_CLK_FREQ_450;
9623 data = 0;
9624 break;
9625 case 540000:
9626 val |= LCPLL_CLK_FREQ_54O_BDW;
9627 data = 1;
9628 break;
9629 case 337500:
9630 val |= LCPLL_CLK_FREQ_337_5_BDW;
9631 data = 2;
9632 break;
9633 case 675000:
9634 val |= LCPLL_CLK_FREQ_675_BDW;
9635 data = 3;
9636 break;
9637 default:
9638 WARN(1, "invalid cdclk frequency\n");
9639 return;
9640 }
9641
9642 I915_WRITE(LCPLL_CTL, val);
9643
9644 val = I915_READ(LCPLL_CTL);
9645 val &= ~LCPLL_CD_SOURCE_FCLK;
9646 I915_WRITE(LCPLL_CTL, val);
9647
9648 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9649 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9650 DRM_ERROR("Switching back to LCPLL failed\n");
9651
9652 mutex_lock(&dev_priv->rps.hw_lock);
9653 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9654 mutex_unlock(&dev_priv->rps.hw_lock);
9655
9656 intel_update_cdclk(dev);
9657
9658 WARN(cdclk != dev_priv->cdclk_freq,
9659 "cdclk requested %d kHz but got %d kHz\n",
9660 cdclk, dev_priv->cdclk_freq);
9661}
9662
27c329ed 9663static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9664{
27c329ed
ML		 9665 struct drm_i915_private *dev_priv = to_i915(state->dev);
9666 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9667 int cdclk;
9668
9669 /*
9670 * FIXME should also account for plane ratio
9671 * once 64bpp pixel formats are supported.
9672 */
27c329ed 9673 if (max_pixclk > 540000)
b432e5cf 9674 cdclk = 675000;
27c329ed 9675 else if (max_pixclk > 450000)
b432e5cf 9676 cdclk = 540000;
27c329ed 9677 else if (max_pixclk > 337500)
b432e5cf
VS		 9678 cdclk = 450000;
9679 else
9680 cdclk = 337500;
9681
9682 /*
9683 * FIXME move the cdclk caclulation to
9684 * compute_config() so we can fail gracegully.
9685 */
9686 if (cdclk > dev_priv->max_cdclk_freq) {
9687 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9688 cdclk, dev_priv->max_cdclk_freq);
9689 cdclk = dev_priv->max_cdclk_freq;
9690 }
9691
27c329ed 9692 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9693
9694 return 0;
9695}
9696
27c329ed 9697static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9698{
27c329ed
ML		 9699 struct drm_device *dev = old_state->dev;
9700 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9701
27c329ed 9702 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9703}
9704
190f68c5
ACO		 9705static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9706 struct intel_crtc_state *crtc_state)
09b4ddf9 9707{
190f68c5 9708 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9709 return -EINVAL;
716c2e55 9710
c7653199 9711 crtc->lowfreq_avail = false;
644cef34 9712
c8f7a0db 9713 return 0;
79e53945
JB		 9714}
9715
3760b59c
S		 9716static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9717 enum port port,
9718 struct intel_crtc_state *pipe_config)
9719{
9720 switch (port) {
9721 case PORT_A:
9722 pipe_config->ddi_pll_sel = SKL_DPLL0;
9723 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9724 break;
9725 case PORT_B:
9726 pipe_config->ddi_pll_sel = SKL_DPLL1;
9727 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9728 break;
9729 case PORT_C:
9730 pipe_config->ddi_pll_sel = SKL_DPLL2;
9731 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9732 break;
9733 default:
9734 DRM_ERROR("Incorrect port type\n");
9735 }
9736}
9737
96b7dfb7
S		 9738static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9739 enum port port,
5cec258b 9740 struct intel_crtc_state *pipe_config)
96b7dfb7 9741{
3148ade7 9742 u32 temp, dpll_ctl1;
96b7dfb7
S		 9743
9744 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9745 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9746
9747 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9748 case SKL_DPLL0:
9749 /*
9750 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9751 * of the shared DPLL framework and thus needs to be read out
9752 * separately
9753 */
9754 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9755 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9756 break;
96b7dfb7
S		 9757 case SKL_DPLL1:
9758 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9759 break;
9760 case SKL_DPLL2:
9761 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9762 break;
9763 case SKL_DPLL3:
9764 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9765 break;
96b7dfb7
S		 9766 }
9767}
9768
7d2c8175
DL		 9769static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9770 enum port port,
5cec258b 9771 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9772{
9773 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9774
9775 switch (pipe_config->ddi_pll_sel) {
9776 case PORT_CLK_SEL_WRPLL1:
9777 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9778 break;
9779 case PORT_CLK_SEL_WRPLL2:
9780 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9781 break;
9782 }
9783}
9784
26804afd 9785static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9786 struct intel_crtc_state *pipe_config)
26804afd
DV		 9787{
9788 struct drm_device *dev = crtc->base.dev;
9789 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9790 struct intel_shared_dpll *pll;
26804afd
DV		 9791 enum port port;
9792 uint32_t tmp;
9793
9794 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9795
9796 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9797
96b7dfb7
S		 9798 if (IS_SKYLAKE(dev))
9799 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9800 else if (IS_BROXTON(dev))
9801 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9802 else
9803 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9804
d452c5b6
DV		 9805 if (pipe_config->shared_dpll >= 0) {
9806 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9807
9808 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9809 &pipe_config->dpll_hw_state));
9810 }
9811
26804afd
DV		 9812 /*
9813 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9814 * DDI E. So just check whether this pipe is wired to DDI E and whether
9815 * the PCH transcoder is on.
9816 */
ca370455
DL		 9817 if (INTEL_INFO(dev)->gen < 9 &&
9818 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9819 pipe_config->has_pch_encoder = true;
9820
9821 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9822 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9823 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9824
9825 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9826 }
9827}
9828
0e8ffe1b 9829static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9830 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9831{
9832 struct drm_device *dev = crtc->base.dev;
9833 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9834 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9835 uint32_t tmp;
9836
f458ebbc 9837 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9838 POWER_DOMAIN_PIPE(crtc->pipe)))
9839 return false;
9840
e143a21c 9841 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9842 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9843
eccb140b
DV		 9844 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9845 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9846 enum pipe trans_edp_pipe;
9847 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9848 default:
9849 WARN(1, "unknown pipe linked to edp transcoder\n");
9850 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9851 case TRANS_DDI_EDP_INPUT_A_ON:
9852 trans_edp_pipe = PIPE_A;
9853 break;
9854 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9855 trans_edp_pipe = PIPE_B;
9856 break;
9857 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9858 trans_edp_pipe = PIPE_C;
9859 break;
9860 }
9861
9862 if (trans_edp_pipe == crtc->pipe)
9863 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9864 }
9865
f458ebbc 9866 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9867 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9868 return false;
9869
eccb140b 9870 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9871 if (!(tmp & PIPECONF_ENABLE))
9872 return false;
9873
26804afd 9874 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9875
1bd1bd80
DV		 9876 intel_get_pipe_timings(crtc, pipe_config);
9877
a1b2278e
CK		 9878 if (INTEL_INFO(dev)->gen >= 9) {
9879 skl_init_scalers(dev, crtc, pipe_config);
9880 }
9881
2fa2fe9a 9882 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9883
9884 if (INTEL_INFO(dev)->gen >= 9) {
9885 pipe_config->scaler_state.scaler_id = -1;
9886 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9887 }
9888
bd2e244f 9889 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9890 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9891 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9892 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9893 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9894 else
9895 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9896 }
88adfff1 9897
e59150dc
JB		 9898 if (IS_HASWELL(dev))
9899 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9900 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9901
ebb69c95
CT		 9902 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9903 pipe_config->pixel_multiplier =
9904 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9905 } else {
9906 pipe_config->pixel_multiplier = 1;
9907 }
6c49f241 9908
0e8ffe1b
DV		 9909 return true;
9910}
9911
560b85bb
CW		 9912static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9913{
9914 struct drm_device *dev = crtc->dev;
9915 struct drm_i915_private *dev_priv = dev->dev_private;
9916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9917 uint32_t cntl = 0, size = 0;
560b85bb 9918
dc41c154 9919 if (base) {
3dd512fb
MR		 9920 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9921 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9922 unsigned int stride = roundup_pow_of_two(width) * 4;
9923
9924 switch (stride) {
9925 default:
9926 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9927 width, stride);
9928 stride = 256;
9929 /* fallthrough */
9930 case 256:
9931 case 512:
9932 case 1024:
9933 case 2048:
9934 break;
4b0e333e
CW		 9935 }
9936
dc41c154
VS		 9937 cntl |= CURSOR_ENABLE |
9938 CURSOR_GAMMA_ENABLE |
9939 CURSOR_FORMAT_ARGB |
9940 CURSOR_STRIDE(stride);
9941
9942 size = (height << 12) | width;
4b0e333e 9943 }
560b85bb 9944
dc41c154
VS		 9945 if (intel_crtc->cursor_cntl != 0 &&
9946 (intel_crtc->cursor_base != base ||
9947 intel_crtc->cursor_size != size ||
9948 intel_crtc->cursor_cntl != cntl)) {
9949 /* On these chipsets we can only modify the base/size/stride
9950 * whilst the cursor is disabled.
9951 */
9952 I915_WRITE(_CURACNTR, 0);
4b0e333e 9953 POSTING_READ(_CURACNTR);
dc41c154 9954 intel_crtc->cursor_cntl = 0;
4b0e333e 9955 }
560b85bb 9956
99d1f387 9957 if (intel_crtc->cursor_base != base) {
9db4a9c7 9958 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9959 intel_crtc->cursor_base = base;
9960 }
4726e0b0 9961
dc41c154
VS		 9962 if (intel_crtc->cursor_size != size) {
9963 I915_WRITE(CURSIZE, size);
9964 intel_crtc->cursor_size = size;
4b0e333e 9965 }
560b85bb 9966
4b0e333e 9967 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9968 I915_WRITE(_CURACNTR, cntl);
9969 POSTING_READ(_CURACNTR);
4b0e333e 9970 intel_crtc->cursor_cntl = cntl;
560b85bb 9971 }
560b85bb
CW		 9972}
9973
560b85bb 9974static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9975{
9976 struct drm_device *dev = crtc->dev;
9977 struct drm_i915_private *dev_priv = dev->dev_private;
9978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9979 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9980 uint32_t cntl;
9981
9982 cntl = 0;
9983 if (base) {
9984 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9985 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9986 case 64:
9987 cntl |= CURSOR_MODE_64_ARGB_AX;
9988 break;
9989 case 128:
9990 cntl |= CURSOR_MODE_128_ARGB_AX;
9991 break;
9992 case 256:
9993 cntl |= CURSOR_MODE_256_ARGB_AX;
9994 break;
9995 default:
3dd512fb 9996 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9997 return;
65a21cd6 9998 }
4b0e333e 9999 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 10000
10001 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
10002 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 10003 }
65a21cd6 10004
8e7d688b 10005 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 10006 cntl |= CURSOR_ROTATE_180;
10007
4b0e333e
CW		 10008 if (intel_crtc->cursor_cntl != cntl) {
10009 I915_WRITE(CURCNTR(pipe), cntl);
10010 POSTING_READ(CURCNTR(pipe));
10011 intel_crtc->cursor_cntl = cntl;
65a21cd6 10012 }
4b0e333e 10013
65a21cd6 10014 /* and commit changes on next vblank */
5efb3e28
VS		 10015 I915_WRITE(CURBASE(pipe), base);
10016 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 10017
10018 intel_crtc->cursor_base = base;
65a21cd6
JB		 10019}
10020
cda4b7d3 10021/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 10022static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10023 bool on)
cda4b7d3
CW		 10024{
10025 struct drm_device *dev = crtc->dev;
10026 struct drm_i915_private *dev_priv = dev->dev_private;
10027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10028 int pipe = intel_crtc->pipe;
3d7d6510
MR		 10029 int x = crtc->cursor_x;
10030 int y = crtc->cursor_y;
d6e4db15 10031 u32 base = 0, pos = 0;
cda4b7d3 10032
d6e4db15 10033 if (on)
cda4b7d3 10034 base = intel_crtc->cursor_addr;
cda4b7d3 10035
6e3c9717 10036 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 10037 base = 0;
10038
6e3c9717 10039 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 10040 base = 0;
10041
10042 if (x < 0) {
3dd512fb 10043 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 10044 base = 0;
10045
10046 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10047 x = -x;
10048 }
10049 pos |= x << CURSOR_X_SHIFT;
10050
10051 if (y < 0) {
3dd512fb 10052 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 10053 base = 0;
10054
10055 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10056 y = -y;
10057 }
10058 pos |= y << CURSOR_Y_SHIFT;
10059
4b0e333e 10060 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10061 return;
10062
5efb3e28
VS		 10063 I915_WRITE(CURPOS(pipe), pos);
10064
4398ad45
VS		 10065 /* ILK+ do this automagically */
10066 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10067 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 10068 base += (intel_crtc->base.cursor->state->crtc_h *
10069 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 10070 }
10071
8ac54669 10072 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10073 i845_update_cursor(crtc, base);
10074 else
10075 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10076}
10077
dc41c154
VS		 10078static bool cursor_size_ok(struct drm_device *dev,
10079 uint32_t width, uint32_t height)
10080{
10081 if (width == 0 || height == 0)
10082 return false;
10083
10084 /*
10085 * 845g/865g are special in that they are only limited by
10086 * the width of their cursors, the height is arbitrary up to
10087 * the precision of the register. Everything else requires
10088 * square cursors, limited to a few power-of-two sizes.
10089 */
10090 if (IS_845G(dev) || IS_I865G(dev)) {
10091 if ((width & 63) != 0)
10092 return false;
10093
10094 if (width > (IS_845G(dev) ? 64 : 512))
10095 return false;
10096
10097 if (height > 1023)
10098 return false;
10099 } else {
10100 switch (width | height) {
10101 case 256:
10102 case 128:
10103 if (IS_GEN2(dev))
10104 return false;
10105 case 64:
10106 break;
10107 default:
10108 return false;
10109 }
10110 }
10111
10112 return true;
10113}
10114
79e53945 10115static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10116 u16 *blue, uint32_t start, uint32_t size)
79e53945 10117{
7203425a 10118 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10120
7203425a 10121 for (i = start; i < end; i++) {
79e53945
JB		 10122 intel_crtc->lut_r[i] = red[i] >> 8;
10123 intel_crtc->lut_g[i] = green[i] >> 8;
10124 intel_crtc->lut_b[i] = blue[i] >> 8;
10125 }
10126
10127 intel_crtc_load_lut(crtc);
10128}
10129
79e53945
JB		 10130/* VESA 640x480x72Hz mode to set on the pipe */
10131static struct drm_display_mode load_detect_mode = {
10132 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10133 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10134};
10135
a8bb6818
DV		 10136struct drm_framebuffer *
10137__intel_framebuffer_create(struct drm_device *dev,
10138 struct drm_mode_fb_cmd2 *mode_cmd,
10139 struct drm_i915_gem_object *obj)
d2dff872
CW		 10140{
10141 struct intel_framebuffer *intel_fb;
10142 int ret;
10143
10144 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10145 if (!intel_fb) {
6ccb81f2 10146 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10147 return ERR_PTR(-ENOMEM);
10148 }
10149
10150 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10151 if (ret)
10152 goto err;
d2dff872
CW		 10153
10154 return &intel_fb->base;
dd4916c5 10155err:
6ccb81f2 10156 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10157 kfree(intel_fb);
10158
10159 return ERR_PTR(ret);
d2dff872
CW		 10160}
10161
b5ea642a 10162static struct drm_framebuffer *
a8bb6818
DV		 10163intel_framebuffer_create(struct drm_device *dev,
10164 struct drm_mode_fb_cmd2 *mode_cmd,
10165 struct drm_i915_gem_object *obj)
10166{
10167 struct drm_framebuffer *fb;
10168 int ret;
10169
10170 ret = i915_mutex_lock_interruptible(dev);
10171 if (ret)
10172 return ERR_PTR(ret);
10173 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10174 mutex_unlock(&dev->struct_mutex);
10175
10176 return fb;
10177}
10178
d2dff872
CW		 10179static u32
10180intel_framebuffer_pitch_for_width(int width, int bpp)
10181{
10182 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10183 return ALIGN(pitch, 64);
10184}
10185
10186static u32
10187intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10188{
10189 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10190 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10191}
10192
10193static struct drm_framebuffer *
10194intel_framebuffer_create_for_mode(struct drm_device *dev,
10195 struct drm_display_mode *mode,
10196 int depth, int bpp)
10197{
10198 struct drm_i915_gem_object *obj;
0fed39bd 10199 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10200
10201 obj = i915_gem_alloc_object(dev,
10202 intel_framebuffer_size_for_mode(mode, bpp));
10203 if (obj == NULL)
10204 return ERR_PTR(-ENOMEM);
10205
10206 mode_cmd.width = mode->hdisplay;
10207 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10208 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10209 bpp);
5ca0c34a 10210 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10211
10212 return intel_framebuffer_create(dev, &mode_cmd, obj);
10213}
10214
10215static struct drm_framebuffer *
10216mode_fits_in_fbdev(struct drm_device *dev,
10217 struct drm_display_mode *mode)
10218{
4520f53a 10219#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10220 struct drm_i915_private *dev_priv = dev->dev_private;
10221 struct drm_i915_gem_object *obj;
10222 struct drm_framebuffer *fb;
10223
4c0e5528 10224 if (!dev_priv->fbdev)
d2dff872
CW		 10225 return NULL;
10226
4c0e5528 10227 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10228 return NULL;
10229
4c0e5528
DV		 10230 obj = dev_priv->fbdev->fb->obj;
10231 BUG_ON(!obj);
10232
8bcd4553 10233 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10234 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10235 fb->bits_per_pixel))
d2dff872
CW		 10236 return NULL;
10237
01f2c773 10238 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10239 return NULL;
10240
10241 return fb;
4520f53a
DV		 10242#else
10243 return NULL;
10244#endif
d2dff872
CW		 10245}
10246
d3a40d1b
ACO		 10247static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10248 struct drm_crtc *crtc,
10249 struct drm_display_mode *mode,
10250 struct drm_framebuffer *fb,
10251 int x, int y)
10252{
10253 struct drm_plane_state *plane_state;
10254 int hdisplay, vdisplay;
10255 int ret;
10256
10257 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10258 if (IS_ERR(plane_state))
10259 return PTR_ERR(plane_state);
10260
10261 if (mode)
10262 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10263 else
10264 hdisplay = vdisplay = 0;
10265
10266 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10267 if (ret)
10268 return ret;
10269 drm_atomic_set_fb_for_plane(plane_state, fb);
10270 plane_state->crtc_x = 0;
10271 plane_state->crtc_y = 0;
10272 plane_state->crtc_w = hdisplay;
10273 plane_state->crtc_h = vdisplay;
10274 plane_state->src_x = x << 16;
10275 plane_state->src_y = y << 16;
10276 plane_state->src_w = hdisplay << 16;
10277 plane_state->src_h = vdisplay << 16;
10278
10279 return 0;
10280}
10281
d2434ab7 10282bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10283 struct drm_display_mode *mode,
51fd371b
RC		 10284 struct intel_load_detect_pipe *old,
10285 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10286{
10287 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10288 struct intel_encoder *intel_encoder =
10289 intel_attached_encoder(connector);
79e53945 10290 struct drm_crtc *possible_crtc;
4ef69c7a 10291 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10292 struct drm_crtc *crtc = NULL;
10293 struct drm_device *dev = encoder->dev;
94352cf9 10294 struct drm_framebuffer *fb;
51fd371b 10295 struct drm_mode_config *config = &dev->mode_config;
83a57153 10296 struct drm_atomic_state *state = NULL;
944b0c76 10297 struct drm_connector_state *connector_state;
4be07317 10298 struct intel_crtc_state *crtc_state;
51fd371b 10299 int ret, i = -1;
79e53945 10300
d2dff872 10301 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10302 connector->base.id, connector->name,
8e329a03 10303 encoder->base.id, encoder->name);
d2dff872 10304
51fd371b
RC		 10305retry:
10306 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10307 if (ret)
ad3c558f 10308 goto fail;
6e9f798d 10309
79e53945
JB		 10310 /*
10311 * Algorithm gets a little messy:
7a5e4805 10312 *
79e53945
JB		 10313 * - if the connector already has an assigned crtc, use it (but make
10314 * sure it's on first)
7a5e4805 10315 *
79e53945
JB		 10316 * - try to find the first unused crtc that can drive this connector,
10317 * and use that if we find one
79e53945
JB		 10318 */
10319
10320 /* See if we already have a CRTC for this connector */
10321 if (encoder->crtc) {
10322 crtc = encoder->crtc;
8261b191 10323
51fd371b 10324 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 10325 if (ret)
ad3c558f 10326 goto fail;
4d02e2de 10327 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b 10328 if (ret)
ad3c558f 10329 goto fail;
7b24056b 10330
24218aac 10331 old->dpms_mode = connector->dpms;
8261b191
CW		 10332 old->load_detect_temp = false;
10333
10334 /* Make sure the crtc and connector are running */
24218aac
DV		 10335 if (connector->dpms != DRM_MODE_DPMS_ON)
10336 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10337
7173188d 10338 return true;
79e53945
JB		 10339 }
10340
10341 /* Find an unused one (if possible) */
70e1e0ec 10342 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10343 i++;
10344 if (!(encoder->possible_crtcs & (1 << i)))
10345 continue;
83d65738 10346 if (possible_crtc->state->enable)
a459249c 10347 continue;
a459249c
VS		 10348
10349 crtc = possible_crtc;
10350 break;
79e53945
JB		 10351 }
10352
10353 /*
10354 * If we didn't find an unused CRTC, don't use any.
10355 */
10356 if (!crtc) {
7173188d 10357 DRM_DEBUG_KMS("no pipe available for load-detect\n");
ad3c558f 10358 goto fail;
79e53945
JB		 10359 }
10360
51fd371b
RC		 10361 ret = drm_modeset_lock(&crtc->mutex, ctx);
10362 if (ret)
ad3c558f 10363 goto fail;
4d02e2de
DV		 10364 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10365 if (ret)
ad3c558f 10366 goto fail;
79e53945
JB		 10367
10368 intel_crtc = to_intel_crtc(crtc);
24218aac 10369 old->dpms_mode = connector->dpms;
8261b191 10370 old->load_detect_temp = true;
d2dff872 10371 old->release_fb = NULL;
79e53945 10372
83a57153
ACO		 10373 state = drm_atomic_state_alloc(dev);
10374 if (!state)
10375 return false;
10376
10377 state->acquire_ctx = ctx;
10378
944b0c76
ACO		 10379 connector_state = drm_atomic_get_connector_state(state, connector);
10380 if (IS_ERR(connector_state)) {
10381 ret = PTR_ERR(connector_state);
10382 goto fail;
10383 }
10384
10385 connector_state->crtc = crtc;
10386 connector_state->best_encoder = &intel_encoder->base;
10387
4be07317
ACO		 10388 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10389 if (IS_ERR(crtc_state)) {
10390 ret = PTR_ERR(crtc_state);
10391 goto fail;
10392 }
10393
49d6fa21 10394 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10395
6492711d
CW		 10396 if (!mode)
10397 mode = &load_detect_mode;
79e53945 10398
d2dff872
CW		 10399 /* We need a framebuffer large enough to accommodate all accesses
10400 * that the plane may generate whilst we perform load detection.
10401 * We can not rely on the fbcon either being present (we get called
10402 * during its initialisation to detect all boot displays, or it may
10403 * not even exist) or that it is large enough to satisfy the
10404 * requested mode.
10405 */
94352cf9
DV		 10406 fb = mode_fits_in_fbdev(dev, mode);
10407 if (fb == NULL) {
d2dff872 10408 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10409 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10410 old->release_fb = fb;
d2dff872
CW		 10411 } else
10412 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10413 if (IS_ERR(fb)) {
d2dff872 10414 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10415 goto fail;
79e53945 10416 }
79e53945 10417
d3a40d1b
ACO		 10418 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10419 if (ret)
10420 goto fail;
10421
8c7b5ccb
ACO		 10422 drm_mode_copy(&crtc_state->base.mode, mode);
10423
74c090b1 10424 if (drm_atomic_commit(state)) {
6492711d 10425 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10426 if (old->release_fb)
10427 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10428 goto fail;
79e53945 10429 }
9128b040 10430 crtc->primary->crtc = crtc;
7173188d 10431
79e53945 10432 /* let the connector get through one full cycle before testing */
9d0498a2 10433 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10434 return true;
412b61d8 10435
ad3c558f 10436fail:
e5d958ef
ACO		 10437 drm_atomic_state_free(state);
10438 state = NULL;
83a57153 10439
51fd371b
RC		 10440 if (ret == -EDEADLK) {
10441 drm_modeset_backoff(ctx);
10442 goto retry;
10443 }
10444
412b61d8 10445 return false;
79e53945
JB		 10446}
10447
d2434ab7 10448void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10449 struct intel_load_detect_pipe *old,
10450 struct drm_modeset_acquire_ctx *ctx)
79e53945 10451{
83a57153 10452 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10453 struct intel_encoder *intel_encoder =
10454 intel_attached_encoder(connector);
4ef69c7a 10455 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10456 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10458 struct drm_atomic_state *state;
944b0c76 10459 struct drm_connector_state *connector_state;
4be07317 10460 struct intel_crtc_state *crtc_state;
d3a40d1b 10461 int ret;
79e53945 10462
d2dff872 10463 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10464 connector->base.id, connector->name,
8e329a03 10465 encoder->base.id, encoder->name);
d2dff872 10466
8261b191 10467 if (old->load_detect_temp) {
83a57153 10468 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10469 if (!state)
10470 goto fail;
83a57153
ACO		 10471
10472 state->acquire_ctx = ctx;
10473
944b0c76
ACO		 10474 connector_state = drm_atomic_get_connector_state(state, connector);
10475 if (IS_ERR(connector_state))
10476 goto fail;
10477
4be07317
ACO		 10478 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10479 if (IS_ERR(crtc_state))
10480 goto fail;
10481
944b0c76
ACO		 10482 connector_state->best_encoder = NULL;
10483 connector_state->crtc = NULL;
10484
49d6fa21 10485 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10486
d3a40d1b
ACO		 10487 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10488 0, 0);
10489 if (ret)
10490 goto fail;
10491
74c090b1 10492 ret = drm_atomic_commit(state);
2bfb4627
ACO		 10493 if (ret)
10494 goto fail;
d2dff872 10495
36206361
DV		 10496 if (old->release_fb) {
10497 drm_framebuffer_unregister_private(old->release_fb);
10498 drm_framebuffer_unreference(old->release_fb);
10499 }
d2dff872 10500
0622a53c 10501 return;
79e53945
JB		 10502 }
10503
c751ce4f 10504 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10505 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10506 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10507
10508 return;
10509fail:
10510 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10511 drm_atomic_state_free(state);
79e53945
JB		 10512}
10513
da4a1efa 10514static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10515 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10516{
10517 struct drm_i915_private *dev_priv = dev->dev_private;
10518 u32 dpll = pipe_config->dpll_hw_state.dpll;
10519
10520 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10521 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10522 else if (HAS_PCH_SPLIT(dev))
10523 return 120000;
10524 else if (!IS_GEN2(dev))
10525 return 96000;
10526 else
10527 return 48000;
10528}
10529
79e53945 10530/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10531static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10532 struct intel_crtc_state *pipe_config)
79e53945 10533{
f1f644dc 10534 struct drm_device *dev = crtc->base.dev;
79e53945 10535 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10536 int pipe = pipe_config->cpu_transcoder;
293623f7 10537 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10538 u32 fp;
10539 intel_clock_t clock;
dccbea3b 10540 int port_clock;
da4a1efa 10541 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10542
10543 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10544 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10545 else
293623f7 10546 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10547
10548 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10549 if (IS_PINEVIEW(dev)) {
10550 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10551 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10552 } else {
10553 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10554 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10555 }
10556
a6c45cf0 10557 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10558 if (IS_PINEVIEW(dev))
10559 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10560 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10561 else
10562 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10563 DPLL_FPA01_P1_POST_DIV_SHIFT);
10564
10565 switch (dpll & DPLL_MODE_MASK) {
10566 case DPLLB_MODE_DAC_SERIAL:
10567 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10568 5 : 10;
10569 break;
10570 case DPLLB_MODE_LVDS:
10571 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10572 7 : 14;
10573 break;
10574 default:
28c97730 10575 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10576 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10577 return;
79e53945
JB		 10578 }
10579
ac58c3f0 10580 if (IS_PINEVIEW(dev))
dccbea3b 10581 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10582 else
dccbea3b 10583 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10584 } else {
0fb58223 10585 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10586 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10587
10588 if (is_lvds) {
10589 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10590 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10591
10592 if (lvds & LVDS_CLKB_POWER_UP)
10593 clock.p2 = 7;
10594 else
10595 clock.p2 = 14;
79e53945
JB		 10596 } else {
10597 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10598 clock.p1 = 2;
10599 else {
10600 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10601 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10602 }
10603 if (dpll & PLL_P2_DIVIDE_BY_4)
10604 clock.p2 = 4;
10605 else
10606 clock.p2 = 2;
79e53945 10607 }
da4a1efa 10608
dccbea3b 10609 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10610 }
10611
18442d08
VS		 10612 /*
10613 * This value includes pixel_multiplier. We will use
241bfc38 10614 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10615 * encoder's get_config() function.
10616 */
dccbea3b 10617 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10618}
10619
6878da05
VS		 10620int intel_dotclock_calculate(int link_freq,
10621 const struct intel_link_m_n *m_n)
f1f644dc 10622{
f1f644dc
JB		 10623 /*
10624 * The calculation for the data clock is:
1041a02f 10625 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10626 * But we want to avoid losing precison if possible, so:
1041a02f 10627 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10628 *
10629 * and the link clock is simpler:
1041a02f 10630 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10631 */
10632
6878da05
VS		 10633 if (!m_n->link_n)
10634 return 0;
f1f644dc 10635
6878da05
VS		 10636 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10637}
f1f644dc 10638
18442d08 10639static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10640 struct intel_crtc_state *pipe_config)
6878da05
VS		 10641{
10642 struct drm_device *dev = crtc->base.dev;
79e53945 10643
18442d08
VS		 10644 /* read out port_clock from the DPLL */
10645 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10646
f1f644dc 10647 /*
18442d08 10648 * This value does not include pixel_multiplier.
241bfc38 10649 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10650 * agree once we know their relationship in the encoder's
10651 * get_config() function.
79e53945 10652 */
2d112de7 10653 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10654 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10655 &pipe_config->fdi_m_n);
79e53945
JB		 10656}
10657
10658/** Returns the currently programmed mode of the given pipe. */
10659struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10660 struct drm_crtc *crtc)
10661{
548f245b 10662 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10664 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10665 struct drm_display_mode *mode;
5cec258b 10666 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10667 int htot = I915_READ(HTOTAL(cpu_transcoder));
10668 int hsync = I915_READ(HSYNC(cpu_transcoder));
10669 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10670 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10671 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10672
10673 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10674 if (!mode)
10675 return NULL;
10676
f1f644dc
JB		 10677 /*
10678 * Construct a pipe_config sufficient for getting the clock info
10679 * back out of crtc_clock_get.
10680 *
10681 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10682 * to use a real value here instead.
10683 */
293623f7 10684 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10685 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10686 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10687 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10688 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10689 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10690
773ae034 10691 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10692 mode->hdisplay = (htot & 0xffff) + 1;
10693 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10694 mode->hsync_start = (hsync & 0xffff) + 1;
10695 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10696 mode->vdisplay = (vtot & 0xffff) + 1;
10697 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10698 mode->vsync_start = (vsync & 0xffff) + 1;
10699 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10700
10701 drm_mode_set_name(mode);
79e53945
JB		 10702
10703 return mode;
10704}
10705
f047e395
CW		 10706void intel_mark_busy(struct drm_device *dev)
10707{
c67a470b
PZ		 10708 struct drm_i915_private *dev_priv = dev->dev_private;
10709
f62a0076
CW		 10710 if (dev_priv->mm.busy)
10711 return;
10712
43694d69 10713 intel_runtime_pm_get(dev_priv);
c67a470b 10714 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10715 if (INTEL_INFO(dev)->gen >= 6)
10716 gen6_rps_busy(dev_priv);
f62a0076 10717 dev_priv->mm.busy = true;
f047e395
CW		 10718}
10719
10720void intel_mark_idle(struct drm_device *dev)
652c393a 10721{
c67a470b 10722 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10723
f62a0076
CW		 10724 if (!dev_priv->mm.busy)
10725 return;
10726
10727 dev_priv->mm.busy = false;
10728
3d13ef2e 10729 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10730 gen6_rps_idle(dev->dev_private);
bb4cdd53 10731
43694d69 10732 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10733}
10734
79e53945
JB		 10735static void intel_crtc_destroy(struct drm_crtc *crtc)
10736{
10737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10738 struct drm_device *dev = crtc->dev;
10739 struct intel_unpin_work *work;
67e77c5a 10740
5e2d7afc 10741 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10742 work = intel_crtc->unpin_work;
10743 intel_crtc->unpin_work = NULL;
5e2d7afc 10744 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10745
10746 if (work) {
10747 cancel_work_sync(&work->work);
10748 kfree(work);
10749 }
79e53945
JB		 10750
10751 drm_crtc_cleanup(crtc);
67e77c5a 10752
79e53945
JB		 10753 kfree(intel_crtc);
10754}
10755
6b95a207
KH		 10756static void intel_unpin_work_fn(struct work_struct *__work)
10757{
10758 struct intel_unpin_work *work =
10759 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10760 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10761 struct drm_device *dev = crtc->base.dev;
7733b49b 10762 struct drm_i915_private *dev_priv = dev->dev_private;
a9ff8714 10763 struct drm_plane *primary = crtc->base.primary;
6b95a207 10764
b4a98e57 10765 mutex_lock(&dev->struct_mutex);
a9ff8714 10766 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10767 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10768
7733b49b 10769 intel_fbc_update(dev_priv);
f06cc1b9
JH		 10770
10771 if (work->flip_queued_req)
146d84f0 10772 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10773 mutex_unlock(&dev->struct_mutex);
10774
a9ff8714 10775 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10776 drm_framebuffer_unreference(work->old_fb);
f99d7069 10777
a9ff8714
VS		 10778 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10779 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10780
6b95a207
KH		 10781 kfree(work);
10782}
10783
1afe3e9d 10784static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10785 struct drm_crtc *crtc)
6b95a207 10786{
6b95a207
KH		 10787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10788 struct intel_unpin_work *work;
6b95a207
KH		 10789 unsigned long flags;
10790
10791 /* Ignore early vblank irqs */
10792 if (intel_crtc == NULL)
10793 return;
10794
f326038a
DV		 10795 /*
10796 * This is called both by irq handlers and the reset code (to complete
10797 * lost pageflips) so needs the full irqsave spinlocks.
10798 */
6b95a207
KH		 10799 spin_lock_irqsave(&dev->event_lock, flags);
10800 work = intel_crtc->unpin_work;
e7d841ca
CW		 10801
10802 /* Ensure we don't miss a work->pending update ... */
10803 smp_rmb();
10804
10805 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10806 spin_unlock_irqrestore(&dev->event_lock, flags);
10807 return;
10808 }
10809
d6bbafa1 10810 page_flip_completed(intel_crtc);
0af7e4df 10811
6b95a207 10812 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10813}
10814
1afe3e9d
JB		 10815void intel_finish_page_flip(struct drm_device *dev, int pipe)
10816{
fbee40df 10817 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10818 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10819
49b14a5c 10820 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10821}
10822
10823void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10824{
fbee40df 10825 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10826 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10827
49b14a5c 10828 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10829}
10830
75f7f3ec
VS		 10831/* Is 'a' after or equal to 'b'? */
10832static bool g4x_flip_count_after_eq(u32 a, u32 b)
10833{
10834 return !((a - b) & 0x80000000);
10835}
10836
10837static bool page_flip_finished(struct intel_crtc *crtc)
10838{
10839 struct drm_device *dev = crtc->base.dev;
10840 struct drm_i915_private *dev_priv = dev->dev_private;
10841
bdfa7542
VS		 10842 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10843 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10844 return true;
10845
75f7f3ec
VS		 10846 /*
10847 * The relevant registers doen't exist on pre-ctg.
10848 * As the flip done interrupt doesn't trigger for mmio
10849 * flips on gmch platforms, a flip count check isn't
10850 * really needed there. But since ctg has the registers,
10851 * include it in the check anyway.
10852 */
10853 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10854 return true;
10855
10856 /*
10857 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10858 * used the same base address. In that case the mmio flip might
10859 * have completed, but the CS hasn't even executed the flip yet.
10860 *
10861 * A flip count check isn't enough as the CS might have updated
10862 * the base address just after start of vblank, but before we
10863 * managed to process the interrupt. This means we'd complete the
10864 * CS flip too soon.
10865 *
10866 * Combining both checks should get us a good enough result. It may
10867 * still happen that the CS flip has been executed, but has not
10868 * yet actually completed. But in case the base address is the same
10869 * anyway, we don't really care.
10870 */
10871 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10872 crtc->unpin_work->gtt_offset &&
10873 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10874 crtc->unpin_work->flip_count);
10875}
10876
6b95a207
KH		 10877void intel_prepare_page_flip(struct drm_device *dev, int plane)
10878{
fbee40df 10879 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10880 struct intel_crtc *intel_crtc =
10881 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10882 unsigned long flags;
10883
f326038a
DV		 10884
10885 /*
10886 * This is called both by irq handlers and the reset code (to complete
10887 * lost pageflips) so needs the full irqsave spinlocks.
10888 *
10889 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10890 * generate a page-flip completion irq, i.e. every modeset
10891 * is also accompanied by a spurious intel_prepare_page_flip().
10892 */
6b95a207 10893 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10894 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10895 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10896 spin_unlock_irqrestore(&dev->event_lock, flags);
10897}
10898
eba905b2 10899static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10900{
10901 /* Ensure that the work item is consistent when activating it ... */
10902 smp_wmb();
10903 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10904 /* and that it is marked active as soon as the irq could fire. */
10905 smp_wmb();
10906}
10907
8c9f3aaf
JB		 10908static int intel_gen2_queue_flip(struct drm_device *dev,
10909 struct drm_crtc *crtc,
10910 struct drm_framebuffer *fb,
ed8d1975 10911 struct drm_i915_gem_object *obj,
6258fbe2 10912 struct drm_i915_gem_request *req,
ed8d1975 10913 uint32_t flags)
8c9f3aaf 10914{
6258fbe2 10915 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10917 u32 flip_mask;
10918 int ret;
10919
5fb9de1a 10920 ret = intel_ring_begin(req, 6);
8c9f3aaf 10921 if (ret)
4fa62c89 10922 return ret;
8c9f3aaf
JB		 10923
10924 /* Can't queue multiple flips, so wait for the previous
10925 * one to finish before executing the next.
10926 */
10927 if (intel_crtc->plane)
10928 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10929 else
10930 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10931 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10932 intel_ring_emit(ring, MI_NOOP);
10933 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10934 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10935 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10936 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10937 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10938
10939 intel_mark_page_flip_active(intel_crtc);
83d4092b 10940 return 0;
8c9f3aaf
JB		 10941}
10942
10943static int intel_gen3_queue_flip(struct drm_device *dev,
10944 struct drm_crtc *crtc,
10945 struct drm_framebuffer *fb,
ed8d1975 10946 struct drm_i915_gem_object *obj,
6258fbe2 10947 struct drm_i915_gem_request *req,
ed8d1975 10948 uint32_t flags)
8c9f3aaf 10949{
6258fbe2 10950 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10952 u32 flip_mask;
10953 int ret;
10954
5fb9de1a 10955 ret = intel_ring_begin(req, 6);
8c9f3aaf 10956 if (ret)
4fa62c89 10957 return ret;
8c9f3aaf
JB		 10958
10959 if (intel_crtc->plane)
10960 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10961 else
10962 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10963 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10964 intel_ring_emit(ring, MI_NOOP);
10965 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10966 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10967 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10968 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10969 intel_ring_emit(ring, MI_NOOP);
10970
e7d841ca 10971 intel_mark_page_flip_active(intel_crtc);
83d4092b 10972 return 0;
8c9f3aaf
JB		 10973}
10974
10975static int intel_gen4_queue_flip(struct drm_device *dev,
10976 struct drm_crtc *crtc,
10977 struct drm_framebuffer *fb,
ed8d1975 10978 struct drm_i915_gem_object *obj,
6258fbe2 10979 struct drm_i915_gem_request *req,
ed8d1975 10980 uint32_t flags)
8c9f3aaf 10981{
6258fbe2 10982 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10983 struct drm_i915_private *dev_priv = dev->dev_private;
10984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10985 uint32_t pf, pipesrc;
10986 int ret;
10987
5fb9de1a 10988 ret = intel_ring_begin(req, 4);
8c9f3aaf 10989 if (ret)
4fa62c89 10990 return ret;
8c9f3aaf
JB		 10991
10992 /* i965+ uses the linear or tiled offsets from the
10993 * Display Registers (which do not change across a page-flip)
10994 * so we need only reprogram the base address.
10995 */
6d90c952
DV		 10996 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10997 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10998 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10999 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 11000 obj->tiling_mode);
8c9f3aaf
JB		 11001
11002 /* XXX Enabling the panel-fitter across page-flip is so far
11003 * untested on non-native modes, so ignore it for now.
11004 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11005 */
11006 pf = 0;
11007 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11008 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11009
11010 intel_mark_page_flip_active(intel_crtc);
83d4092b 11011 return 0;
8c9f3aaf
JB		 11012}
11013
11014static int intel_gen6_queue_flip(struct drm_device *dev,
11015 struct drm_crtc *crtc,
11016 struct drm_framebuffer *fb,
ed8d1975 11017 struct drm_i915_gem_object *obj,
6258fbe2 11018 struct drm_i915_gem_request *req,
ed8d1975 11019 uint32_t flags)
8c9f3aaf 11020{
6258fbe2 11021 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 11022 struct drm_i915_private *dev_priv = dev->dev_private;
11023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11024 uint32_t pf, pipesrc;
11025 int ret;
11026
5fb9de1a 11027 ret = intel_ring_begin(req, 4);
8c9f3aaf 11028 if (ret)
4fa62c89 11029 return ret;
8c9f3aaf 11030
6d90c952
DV		 11031 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11032 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11033 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 11034 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 11035
dc257cf1
DV		 11036 /* Contrary to the suggestions in the documentation,
11037 * "Enable Panel Fitter" does not seem to be required when page
11038 * flipping with a non-native mode, and worse causes a normal
11039 * modeset to fail.
11040 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11041 */
11042 pf = 0;
8c9f3aaf 11043 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 11044 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 11045
11046 intel_mark_page_flip_active(intel_crtc);
83d4092b 11047 return 0;
8c9f3aaf
JB		 11048}
11049
7c9017e5
JB		 11050static int intel_gen7_queue_flip(struct drm_device *dev,
11051 struct drm_crtc *crtc,
11052 struct drm_framebuffer *fb,
ed8d1975 11053 struct drm_i915_gem_object *obj,
6258fbe2 11054 struct drm_i915_gem_request *req,
ed8d1975 11055 uint32_t flags)
7c9017e5 11056{
6258fbe2 11057 struct intel_engine_cs *ring = req->ring;
7c9017e5 11058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11059 uint32_t plane_bit = 0;
ffe74d75
CW		 11060 int len, ret;
11061
eba905b2 11062 switch (intel_crtc->plane) {
cb05d8de
DV		 11063 case PLANE_A:
11064 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11065 break;
11066 case PLANE_B:
11067 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11068 break;
11069 case PLANE_C:
11070 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11071 break;
11072 default:
11073 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11074 return -ENODEV;
cb05d8de
DV		 11075 }
11076
ffe74d75 11077 len = 4;
f476828a 11078 if (ring->id == RCS) {
ffe74d75 11079 len += 6;
f476828a
DL		 11080 /*
11081 * On Gen 8, SRM is now taking an extra dword to accommodate
11082 * 48bits addresses, and we need a NOOP for the batch size to
11083 * stay even.
11084 */
11085 if (IS_GEN8(dev))
11086 len += 2;
11087 }
ffe74d75 11088
f66fab8e
VS		 11089 /*
11090 * BSpec MI_DISPLAY_FLIP for IVB:
11091 * "The full packet must be contained within the same cache line."
11092 *
11093 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11094 * cacheline, if we ever start emitting more commands before
11095 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11096 * then do the cacheline alignment, and finally emit the
11097 * MI_DISPLAY_FLIP.
11098 */
bba09b12 11099 ret = intel_ring_cacheline_align(req);
f66fab8e 11100 if (ret)
4fa62c89 11101 return ret;
f66fab8e 11102
5fb9de1a 11103 ret = intel_ring_begin(req, len);
7c9017e5 11104 if (ret)
4fa62c89 11105 return ret;
7c9017e5 11106
ffe74d75
CW		 11107 /* Unmask the flip-done completion message. Note that the bspec says that
11108 * we should do this for both the BCS and RCS, and that we must not unmask
11109 * more than one flip event at any time (or ensure that one flip message
11110 * can be sent by waiting for flip-done prior to queueing new flips).
11111 * Experimentation says that BCS works despite DERRMR masking all
11112 * flip-done completion events and that unmasking all planes at once
11113 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11114 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11115 */
11116 if (ring->id == RCS) {
11117 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11118 intel_ring_emit(ring, DERRMR);
11119 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11120 DERRMR_PIPEB_PRI_FLIP_DONE |
11121 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11122 if (IS_GEN8(dev))
11123 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11124 MI_SRM_LRM_GLOBAL_GTT);
11125 else
11126 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11127 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11128 intel_ring_emit(ring, DERRMR);
11129 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11130 if (IS_GEN8(dev)) {
11131 intel_ring_emit(ring, 0);
11132 intel_ring_emit(ring, MI_NOOP);
11133 }
ffe74d75
CW		 11134 }
11135
cb05d8de 11136 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11137 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11138 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11139 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11140
11141 intel_mark_page_flip_active(intel_crtc);
83d4092b 11142 return 0;
7c9017e5
JB		 11143}
11144
84c33a64
SG		 11145static bool use_mmio_flip(struct intel_engine_cs *ring,
11146 struct drm_i915_gem_object *obj)
11147{
11148 /*
11149 * This is not being used for older platforms, because
11150 * non-availability of flip done interrupt forces us to use
11151 * CS flips. Older platforms derive flip done using some clever
11152 * tricks involving the flip_pending status bits and vblank irqs.
11153 * So using MMIO flips there would disrupt this mechanism.
11154 */
11155
8e09bf83
CW		 11156 if (ring == NULL)
11157 return true;
11158
84c33a64
SG		 11159 if (INTEL_INFO(ring->dev)->gen < 5)
11160 return false;
11161
11162 if (i915.use_mmio_flip < 0)
11163 return false;
11164 else if (i915.use_mmio_flip > 0)
11165 return true;
14bf993e
OM		 11166 else if (i915.enable_execlists)
11167 return true;
84c33a64 11168 else
b4716185 11169 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11170}
11171
ff944564
DL		 11172static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11173{
11174 struct drm_device *dev = intel_crtc->base.dev;
11175 struct drm_i915_private *dev_priv = dev->dev_private;
11176 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11177 const enum pipe pipe = intel_crtc->pipe;
11178 u32 ctl, stride;
11179
11180 ctl = I915_READ(PLANE_CTL(pipe, 0));
11181 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11182 switch (fb->modifier[0]) {
11183 case DRM_FORMAT_MOD_NONE:
11184 break;
11185 case I915_FORMAT_MOD_X_TILED:
ff944564 11186 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11187 break;
11188 case I915_FORMAT_MOD_Y_TILED:
11189 ctl |= PLANE_CTL_TILED_Y;
11190 break;
11191 case I915_FORMAT_MOD_Yf_TILED:
11192 ctl |= PLANE_CTL_TILED_YF;
11193 break;
11194 default:
11195 MISSING_CASE(fb->modifier[0]);
11196 }
ff944564
DL		 11197
11198 /*
11199 * The stride is either expressed as a multiple of 64 bytes chunks for
11200 * linear buffers or in number of tiles for tiled buffers.
11201 */
2ebef630
TU		 11202 stride = fb->pitches[0] /
11203 intel_fb_stride_alignment(dev, fb->modifier[0],
11204 fb->pixel_format);
ff944564
DL		 11205
11206 /*
11207 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11208 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11209 */
11210 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11211 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11212
11213 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11214 POSTING_READ(PLANE_SURF(pipe, 0));
11215}
11216
11217static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11218{
11219 struct drm_device *dev = intel_crtc->base.dev;
11220 struct drm_i915_private *dev_priv = dev->dev_private;
11221 struct intel_framebuffer *intel_fb =
11222 to_intel_framebuffer(intel_crtc->base.primary->fb);
11223 struct drm_i915_gem_object *obj = intel_fb->obj;
11224 u32 dspcntr;
11225 u32 reg;
11226
84c33a64
SG		 11227 reg = DSPCNTR(intel_crtc->plane);
11228 dspcntr = I915_READ(reg);
11229
c5d97472
DL		 11230 if (obj->tiling_mode != I915_TILING_NONE)
11231 dspcntr |= DISPPLANE_TILED;
11232 else
11233 dspcntr &= ~DISPPLANE_TILED;
11234
84c33a64
SG		 11235 I915_WRITE(reg, dspcntr);
11236
11237 I915_WRITE(DSPSURF(intel_crtc->plane),
11238 intel_crtc->unpin_work->gtt_offset);
11239 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11240
ff944564
DL		 11241}
11242
11243/*
11244 * XXX: This is the temporary way to update the plane registers until we get
11245 * around to using the usual plane update functions for MMIO flips
11246 */
11247static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11248{
11249 struct drm_device *dev = intel_crtc->base.dev;
11250 bool atomic_update;
11251 u32 start_vbl_count;
11252
11253 intel_mark_page_flip_active(intel_crtc);
11254
11255 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11256
11257 if (INTEL_INFO(dev)->gen >= 9)
11258 skl_do_mmio_flip(intel_crtc);
11259 else
11260 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11261 ilk_do_mmio_flip(intel_crtc);
11262
9362c7c5
ACO		 11263 if (atomic_update)
11264 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11265}
11266
9362c7c5 11267static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11268{
b2cfe0ab
CW		 11269 struct intel_mmio_flip *mmio_flip =
11270 container_of(work, struct intel_mmio_flip, work);
84c33a64 11271
eed29a5b
DV		 11272 if (mmio_flip->req)
11273 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11274 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11275 false, NULL,
11276 &mmio_flip->i915->rps.mmioflips));
84c33a64 11277
b2cfe0ab
CW		 11278 intel_do_mmio_flip(mmio_flip->crtc);
11279
eed29a5b 11280 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11281 kfree(mmio_flip);
84c33a64
SG		 11282}
11283
11284static int intel_queue_mmio_flip(struct drm_device *dev,
11285 struct drm_crtc *crtc,
11286 struct drm_framebuffer *fb,
11287 struct drm_i915_gem_object *obj,
11288 struct intel_engine_cs *ring,
11289 uint32_t flags)
11290{
b2cfe0ab
CW		 11291 struct intel_mmio_flip *mmio_flip;
11292
11293 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11294 if (mmio_flip == NULL)
11295 return -ENOMEM;
84c33a64 11296
bcafc4e3 11297 mmio_flip->i915 = to_i915(dev);
eed29a5b 11298 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11299 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11300
b2cfe0ab
CW		 11301 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11302 schedule_work(&mmio_flip->work);
84c33a64 11303
84c33a64
SG		 11304 return 0;
11305}
11306
8c9f3aaf
JB		 11307static int intel_default_queue_flip(struct drm_device *dev,
11308 struct drm_crtc *crtc,
11309 struct drm_framebuffer *fb,
ed8d1975 11310 struct drm_i915_gem_object *obj,
6258fbe2 11311 struct drm_i915_gem_request *req,
ed8d1975 11312 uint32_t flags)
8c9f3aaf
JB		 11313{
11314 return -ENODEV;
11315}
11316
d6bbafa1
CW		 11317static bool __intel_pageflip_stall_check(struct drm_device *dev,
11318 struct drm_crtc *crtc)
11319{
11320 struct drm_i915_private *dev_priv = dev->dev_private;
11321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11322 struct intel_unpin_work *work = intel_crtc->unpin_work;
11323 u32 addr;
11324
11325 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11326 return true;
11327
11328 if (!work->enable_stall_check)
11329 return false;
11330
11331 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11332 if (work->flip_queued_req &&
11333 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11334 return false;
11335
1e3feefd 11336 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11337 }
11338
1e3feefd 11339 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11340 return false;
11341
11342 /* Potential stall - if we see that the flip has happened,
11343 * assume a missed interrupt. */
11344 if (INTEL_INFO(dev)->gen >= 4)
11345 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11346 else
11347 addr = I915_READ(DSPADDR(intel_crtc->plane));
11348
11349 /* There is a potential issue here with a false positive after a flip
11350 * to the same address. We could address this by checking for a
11351 * non-incrementing frame counter.
11352 */
11353 return addr == work->gtt_offset;
11354}
11355
11356void intel_check_page_flip(struct drm_device *dev, int pipe)
11357{
11358 struct drm_i915_private *dev_priv = dev->dev_private;
11359 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11361 struct intel_unpin_work *work;
f326038a 11362
6c51d46f 11363 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11364
11365 if (crtc == NULL)
11366 return;
11367
f326038a 11368 spin_lock(&dev->event_lock);
6ad790c0
CW		 11369 work = intel_crtc->unpin_work;
11370 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11371 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11372 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11373 page_flip_completed(intel_crtc);
6ad790c0 11374 work = NULL;
d6bbafa1 11375 }
6ad790c0
CW		 11376 if (work != NULL &&
11377 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11378 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11379 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11380}
11381
6b95a207
KH		 11382static int intel_crtc_page_flip(struct drm_crtc *crtc,
11383 struct drm_framebuffer *fb,
ed8d1975
KP		 11384 struct drm_pending_vblank_event *event,
11385 uint32_t page_flip_flags)
6b95a207
KH		 11386{
11387 struct drm_device *dev = crtc->dev;
11388 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11389 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11390 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11392 struct drm_plane *primary = crtc->primary;
a071fa00 11393 enum pipe pipe = intel_crtc->pipe;
6b95a207 11394 struct intel_unpin_work *work;
a4872ba6 11395 struct intel_engine_cs *ring;
cf5d8a46 11396 bool mmio_flip;
91af127f 11397 struct drm_i915_gem_request *request = NULL;
52e68630 11398 int ret;
6b95a207 11399
2ff8fde1
MR		 11400 /*
11401 * drm_mode_page_flip_ioctl() should already catch this, but double
11402 * check to be safe. In the future we may enable pageflipping from
11403 * a disabled primary plane.
11404 */
11405 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11406 return -EBUSY;
11407
e6a595d2 11408 /* Can't change pixel format via MI display flips. */
f4510a27 11409 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11410 return -EINVAL;
11411
11412 /*
11413 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11414 * Note that pitch changes could also affect these register.
11415 */
11416 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11417 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11418 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11419 return -EINVAL;
11420
f900db47
CW		 11421 if (i915_terminally_wedged(&dev_priv->gpu_error))
11422 goto out_hang;
11423
b14c5679 11424 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11425 if (work == NULL)
11426 return -ENOMEM;
11427
6b95a207 11428 work->event = event;
b4a98e57 11429 work->crtc = crtc;
ab8d6675 11430 work->old_fb = old_fb;
6b95a207
KH		 11431 INIT_WORK(&work->work, intel_unpin_work_fn);
11432
87b6b101 11433 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11434 if (ret)
11435 goto free_work;
11436
6b95a207 11437 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11438 spin_lock_irq(&dev->event_lock);
6b95a207 11439 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11440 /* Before declaring the flip queue wedged, check if
11441 * the hardware completed the operation behind our backs.
11442 */
11443 if (__intel_pageflip_stall_check(dev, crtc)) {
11444 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11445 page_flip_completed(intel_crtc);
11446 } else {
11447 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11448 spin_unlock_irq(&dev->event_lock);
468f0b44 11449
d6bbafa1
CW		 11450 drm_crtc_vblank_put(crtc);
11451 kfree(work);
11452 return -EBUSY;
11453 }
6b95a207
KH		 11454 }
11455 intel_crtc->unpin_work = work;
5e2d7afc 11456 spin_unlock_irq(&dev->event_lock);
6b95a207 11457
b4a98e57
CW		 11458 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11459 flush_workqueue(dev_priv->wq);
11460
75dfca80 11461 /* Reference the objects for the scheduled work. */
ab8d6675 11462 drm_framebuffer_reference(work->old_fb);
05394f39 11463 drm_gem_object_reference(&obj->base);
6b95a207 11464
f4510a27 11465 crtc->primary->fb = fb;
afd65eb4 11466 update_state_fb(crtc->primary);
1ed1f968 11467
e1f99ce6 11468 work->pending_flip_obj = obj;
e1f99ce6 11469
89ed88ba
CW		 11470 ret = i915_mutex_lock_interruptible(dev);
11471 if (ret)
11472 goto cleanup;
11473
b4a98e57 11474 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11475 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11476
75f7f3ec 11477 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11478 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11479
4fa62c89
VS		 11480 if (IS_VALLEYVIEW(dev)) {
11481 ring = &dev_priv->ring[BCS];
ab8d6675 11482 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11483 /* vlv: DISPLAY_FLIP fails to change tiling */
11484 ring = NULL;
48bf5b2d 11485 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11486 ring = &dev_priv->ring[BCS];
4fa62c89 11487 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11488 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11489 if (ring == NULL || ring->id != RCS)
11490 ring = &dev_priv->ring[BCS];
11491 } else {
11492 ring = &dev_priv->ring[RCS];
11493 }
11494
cf5d8a46
CW		 11495 mmio_flip = use_mmio_flip(ring, obj);
11496
11497 /* When using CS flips, we want to emit semaphores between rings.
11498 * However, when using mmio flips we will create a task to do the
11499 * synchronisation, so all we want here is to pin the framebuffer
11500 * into the display plane and skip any waits.
11501 */
82bc3b2d 11502 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11503 crtc->primary->state,
91af127f 11504 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11505 if (ret)
11506 goto cleanup_pending;
6b95a207 11507
121920fa
TU		 11508 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11509 + intel_crtc->dspaddr_offset;
4fa62c89 11510
cf5d8a46 11511 if (mmio_flip) {
84c33a64
SG		 11512 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11513 page_flip_flags);
d6bbafa1
CW		 11514 if (ret)
11515 goto cleanup_unpin;
11516
f06cc1b9
JH		 11517 i915_gem_request_assign(&work->flip_queued_req,
11518 obj->last_write_req);
d6bbafa1 11519 } else {
6258fbe2
JH		 11520 if (!request) {
11521 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11522 if (ret)
11523 goto cleanup_unpin;
11524 }
11525
11526 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11527 page_flip_flags);
11528 if (ret)
11529 goto cleanup_unpin;
11530
6258fbe2 11531 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11532 }
11533
91af127f 11534 if (request)
75289874 11535 i915_add_request_no_flush(request);
91af127f 11536
1e3feefd 11537 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11538 work->enable_stall_check = true;
4fa62c89 11539
ab8d6675 11540 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11541 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11542 mutex_unlock(&dev->struct_mutex);
a071fa00 11543
7733b49b 11544 intel_fbc_disable(dev_priv);
a9ff8714
VS		 11545 intel_frontbuffer_flip_prepare(dev,
11546 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11547
e5510fac
JB		 11548 trace_i915_flip_request(intel_crtc->plane, obj);
11549
6b95a207 11550 return 0;
96b099fd 11551
4fa62c89 11552cleanup_unpin:
82bc3b2d 11553 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11554cleanup_pending:
91af127f
JH		 11555 if (request)
11556 i915_gem_request_cancel(request);
b4a98e57 11557 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11558 mutex_unlock(&dev->struct_mutex);
11559cleanup:
f4510a27 11560 crtc->primary->fb = old_fb;
afd65eb4 11561 update_state_fb(crtc->primary);
89ed88ba
CW		 11562
11563 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11564 drm_framebuffer_unreference(work->old_fb);
96b099fd 11565
5e2d7afc 11566 spin_lock_irq(&dev->event_lock);
96b099fd 11567 intel_crtc->unpin_work = NULL;
5e2d7afc 11568 spin_unlock_irq(&dev->event_lock);
96b099fd 11569
87b6b101 11570 drm_crtc_vblank_put(crtc);
7317c75e 11571free_work:
96b099fd
CW		 11572 kfree(work);
11573
f900db47 11574 if (ret == -EIO) {
02e0efb5
ML		 11575 struct drm_atomic_state *state;
11576 struct drm_plane_state *plane_state;
11577
f900db47 11578out_hang:
02e0efb5
ML		 11579 state = drm_atomic_state_alloc(dev);
11580 if (!state)
11581 return -ENOMEM;
11582 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11583
11584retry:
11585 plane_state = drm_atomic_get_plane_state(state, primary);
11586 ret = PTR_ERR_OR_ZERO(plane_state);
11587 if (!ret) {
11588 drm_atomic_set_fb_for_plane(plane_state, fb);
11589
11590 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11591 if (!ret)
11592 ret = drm_atomic_commit(state);
11593 }
11594
11595 if (ret == -EDEADLK) {
11596 drm_modeset_backoff(state->acquire_ctx);
11597 drm_atomic_state_clear(state);
11598 goto retry;
11599 }
11600
11601 if (ret)
11602 drm_atomic_state_free(state);
11603
f0d3dad3 11604 if (ret == 0 && event) {
5e2d7afc 11605 spin_lock_irq(&dev->event_lock);
a071fa00 11606 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11607 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11608 }
f900db47 11609 }
96b099fd 11610 return ret;
6b95a207
KH		 11611}
11612
da20eabd
ML		 11613
11614/**
11615 * intel_wm_need_update - Check whether watermarks need updating
11616 * @plane: drm plane
11617 * @state: new plane state
11618 *
11619 * Check current plane state versus the new one to determine whether
11620 * watermarks need to be recalculated.
11621 *
11622 * Returns true or false.
11623 */
11624static bool intel_wm_need_update(struct drm_plane *plane,
11625 struct drm_plane_state *state)
11626{
11627 /* Update watermarks on tiling changes. */
11628 if (!plane->state->fb || !state->fb ||
11629 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11630 plane->state->rotation != state->rotation)
11631 return true;
11632
11633 if (plane->state->crtc_w != state->crtc_w)
11634 return true;
11635
11636 return false;
11637}
11638
11639int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11640 struct drm_plane_state *plane_state)
11641{
11642 struct drm_crtc *crtc = crtc_state->crtc;
11643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11644 struct drm_plane *plane = plane_state->plane;
11645 struct drm_device *dev = crtc->dev;
11646 struct drm_i915_private *dev_priv = dev->dev_private;
11647 struct intel_plane_state *old_plane_state =
11648 to_intel_plane_state(plane->state);
11649 int idx = intel_crtc->base.base.id, ret;
11650 int i = drm_plane_index(plane);
11651 bool mode_changed = needs_modeset(crtc_state);
11652 bool was_crtc_enabled = crtc->state->active;
11653 bool is_crtc_enabled = crtc_state->active;
11654
11655 bool turn_off, turn_on, visible, was_visible;
11656 struct drm_framebuffer *fb = plane_state->fb;
11657
11658 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11659 plane->type != DRM_PLANE_TYPE_CURSOR) {
11660 ret = skl_update_scaler_plane(
11661 to_intel_crtc_state(crtc_state),
11662 to_intel_plane_state(plane_state));
11663 if (ret)
11664 return ret;
11665 }
11666
11667 /*
11668 * Disabling a plane is always okay; we just need to update
11669 * fb tracking in a special way since cleanup_fb() won't
11670 * get called by the plane helpers.
11671 */
11672 if (old_plane_state->base.fb && !fb)
11673 intel_crtc->atomic.disabled_planes |= 1 << i;
11674
da20eabd
ML		 11675 was_visible = old_plane_state->visible;
11676 visible = to_intel_plane_state(plane_state)->visible;
11677
11678 if (!was_crtc_enabled && WARN_ON(was_visible))
11679 was_visible = false;
11680
11681 if (!is_crtc_enabled && WARN_ON(visible))
11682 visible = false;
11683
11684 if (!was_visible && !visible)
11685 return 0;
11686
11687 turn_off = was_visible && (!visible || mode_changed);
11688 turn_on = visible && (!was_visible || mode_changed);
11689
11690 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11691 plane->base.id, fb ? fb->base.id : -1);
11692
11693 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11694 plane->base.id, was_visible, visible,
11695 turn_off, turn_on, mode_changed);
11696
852eb00d 11697 if (turn_on) {
f015c551 11698 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11699 /* must disable cxsr around plane enable/disable */
11700 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11701 intel_crtc->atomic.disable_cxsr = true;
11702 /* to potentially re-enable cxsr */
11703 intel_crtc->atomic.wait_vblank = true;
11704 intel_crtc->atomic.update_wm_post = true;
11705 }
11706 } else if (turn_off) {
f015c551 11707 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11708 /* must disable cxsr around plane enable/disable */
11709 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11710 if (is_crtc_enabled)
11711 intel_crtc->atomic.wait_vblank = true;
11712 intel_crtc->atomic.disable_cxsr = true;
11713 }
11714 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11715 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11716 }
da20eabd 11717
a9ff8714
VS		 11718 if (visible)
11719 intel_crtc->atomic.fb_bits |=
11720 to_intel_plane(plane)->frontbuffer_bit;
11721
da20eabd
ML		 11722 switch (plane->type) {
11723 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11724 intel_crtc->atomic.wait_for_flips = true;
11725 intel_crtc->atomic.pre_disable_primary = turn_off;
11726 intel_crtc->atomic.post_enable_primary = turn_on;
11727
066cf55b
RV		 11728 if (turn_off) {
11729 /*
11730 * FIXME: Actually if we will still have any other
11731 * plane enabled on the pipe we could let IPS enabled
11732 * still, but for now lets consider that when we make
11733 * primary invisible by setting DSPCNTR to 0 on
11734 * update_primary_plane function IPS needs to be
11735 * disable.
11736 */
11737 intel_crtc->atomic.disable_ips = true;
11738
da20eabd 11739 intel_crtc->atomic.disable_fbc = true;
066cf55b 11740 }
da20eabd
ML		 11741
11742 /*
11743 * FBC does not work on some platforms for rotated
11744 * planes, so disable it when rotation is not 0 and
11745 * update it when rotation is set back to 0.
11746 *
11747 * FIXME: This is redundant with the fbc update done in
11748 * the primary plane enable function except that that
11749 * one is done too late. We eventually need to unify
11750 * this.
11751 */
11752
11753 if (visible &&
11754 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11755 dev_priv->fbc.crtc == intel_crtc &&
11756 plane_state->rotation != BIT(DRM_ROTATE_0))
11757 intel_crtc->atomic.disable_fbc = true;
11758
11759 /*
11760 * BDW signals flip done immediately if the plane
11761 * is disabled, even if the plane enable is already
11762 * armed to occur at the next vblank :(
11763 */
11764 if (turn_on && IS_BROADWELL(dev))
11765 intel_crtc->atomic.wait_vblank = true;
11766
11767 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11768 break;
11769 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11770 break;
11771 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11772 if (turn_off && !mode_changed) {
da20eabd
ML		 11773 intel_crtc->atomic.wait_vblank = true;
11774 intel_crtc->atomic.update_sprite_watermarks |=
11775 1 << i;
11776 }
da20eabd
ML		 11777 }
11778 return 0;
11779}
11780
6d3a1ce7
ML		 11781static bool encoders_cloneable(const struct intel_encoder *a,
11782 const struct intel_encoder *b)
11783{
11784 /* masks could be asymmetric, so check both ways */
11785 return a == b || (a->cloneable & (1 << b->type) &&
11786 b->cloneable & (1 << a->type));
11787}
11788
11789static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11790 struct intel_crtc *crtc,
11791 struct intel_encoder *encoder)
11792{
11793 struct intel_encoder *source_encoder;
11794 struct drm_connector *connector;
11795 struct drm_connector_state *connector_state;
11796 int i;
11797
11798 for_each_connector_in_state(state, connector, connector_state, i) {
11799 if (connector_state->crtc != &crtc->base)
11800 continue;
11801
11802 source_encoder =
11803 to_intel_encoder(connector_state->best_encoder);
11804 if (!encoders_cloneable(encoder, source_encoder))
11805 return false;
11806 }
11807
11808 return true;
11809}
11810
11811static bool check_encoder_cloning(struct drm_atomic_state *state,
11812 struct intel_crtc *crtc)
11813{
11814 struct intel_encoder *encoder;
11815 struct drm_connector *connector;
11816 struct drm_connector_state *connector_state;
11817 int i;
11818
11819 for_each_connector_in_state(state, connector, connector_state, i) {
11820 if (connector_state->crtc != &crtc->base)
11821 continue;
11822
11823 encoder = to_intel_encoder(connector_state->best_encoder);
11824 if (!check_single_encoder_cloning(state, crtc, encoder))
11825 return false;
11826 }
11827
11828 return true;
11829}
11830
11831static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11832 struct drm_crtc_state *crtc_state)
11833{
cf5a15be 11834 struct drm_device *dev = crtc->dev;
ad421372 11835 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11837 struct intel_crtc_state *pipe_config =
11838 to_intel_crtc_state(crtc_state);
6d3a1ce7 11839 struct drm_atomic_state *state = crtc_state->state;
ad421372 11840 int ret, idx = crtc->base.id;
6d3a1ce7
ML		 11841 bool mode_changed = needs_modeset(crtc_state);
11842
11843 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11844 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11845 return -EINVAL;
11846 }
11847
11848 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11849 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11850 idx, crtc->state->active, intel_crtc->active);
11851
852eb00d
VS		 11852 if (mode_changed && !crtc_state->active)
11853 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11854
ad421372
ML		 11855 if (mode_changed && crtc_state->enable &&
11856 dev_priv->display.crtc_compute_clock &&
11857 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11858 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11859 pipe_config);
11860 if (ret)
11861 return ret;
11862 }
11863
e435d6e5
ML		 11864 ret = 0;
11865 if (INTEL_INFO(dev)->gen >= 9) {
11866 if (mode_changed)
11867 ret = skl_update_scaler_crtc(pipe_config);
11868
11869 if (!ret)
11870 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11871 pipe_config);
11872 }
11873
11874 return ret;
6d3a1ce7
ML		 11875}
11876
65b38e0d 11877static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11878 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11879 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11880 .atomic_begin = intel_begin_crtc_commit,
11881 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11882 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11883};
11884
d29b2f9d
ACO		 11885static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11886{
11887 struct intel_connector *connector;
11888
11889 for_each_intel_connector(dev, connector) {
11890 if (connector->base.encoder) {
11891 connector->base.state->best_encoder =
11892 connector->base.encoder;
11893 connector->base.state->crtc =
11894 connector->base.encoder->crtc;
11895 } else {
11896 connector->base.state->best_encoder = NULL;
11897 connector->base.state->crtc = NULL;
11898 }
11899 }
11900}
11901
050f7aeb 11902static void
eba905b2 11903connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11904 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11905{
11906 int bpp = pipe_config->pipe_bpp;
11907
11908 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11909 connector->base.base.id,
c23cc417 11910 connector->base.name);
050f7aeb
DV		 11911
11912 /* Don't use an invalid EDID bpc value */
11913 if (connector->base.display_info.bpc &&
11914 connector->base.display_info.bpc * 3 < bpp) {
11915 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11916 bpp, connector->base.display_info.bpc*3);
11917 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11918 }
11919
11920 /* Clamp bpp to 8 on screens without EDID 1.4 */
11921 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11922 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11923 bpp);
11924 pipe_config->pipe_bpp = 24;
11925 }
11926}
11927
4e53c2e0 11928static int
050f7aeb 11929compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11930 struct intel_crtc_state *pipe_config)
4e53c2e0 11931{
050f7aeb 11932 struct drm_device *dev = crtc->base.dev;
1486017f 11933 struct drm_atomic_state *state;
da3ced29
ACO		 11934 struct drm_connector *connector;
11935 struct drm_connector_state *connector_state;
1486017f 11936 int bpp, i;
4e53c2e0 11937
d328c9d7 11938 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11939 bpp = 10*3;
d328c9d7
DV		 11940 else if (INTEL_INFO(dev)->gen >= 5)
11941 bpp = 12*3;
11942 else
11943 bpp = 8*3;
11944
4e53c2e0 11945
4e53c2e0
DV		 11946 pipe_config->pipe_bpp = bpp;
11947
1486017f
ACO		 11948 state = pipe_config->base.state;
11949
4e53c2e0 11950 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11951 for_each_connector_in_state(state, connector, connector_state, i) {
11952 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11953 continue;
11954
da3ced29
ACO		 11955 connected_sink_compute_bpp(to_intel_connector(connector),
11956 pipe_config);
4e53c2e0
DV		 11957 }
11958
11959 return bpp;
11960}
11961
644db711
DV		 11962static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11963{
11964 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11965 "type: 0x%x flags: 0x%x\n",
1342830c 11966 mode->crtc_clock,
644db711
DV		 11967 mode->crtc_hdisplay, mode->crtc_hsync_start,
11968 mode->crtc_hsync_end, mode->crtc_htotal,
11969 mode->crtc_vdisplay, mode->crtc_vsync_start,
11970 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11971}
11972
c0b03411 11973static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11974 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11975 const char *context)
11976{
6a60cd87
CK		 11977 struct drm_device *dev = crtc->base.dev;
11978 struct drm_plane *plane;
11979 struct intel_plane *intel_plane;
11980 struct intel_plane_state *state;
11981 struct drm_framebuffer *fb;
11982
11983 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11984 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11985
11986 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11987 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11988 pipe_config->pipe_bpp, pipe_config->dither);
11989 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11990 pipe_config->has_pch_encoder,
11991 pipe_config->fdi_lanes,
11992 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11993 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11994 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11995 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11996 pipe_config->has_dp_encoder,
11997 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11998 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11999 pipe_config->dp_m_n.tu);
b95af8be
VK		 12000
12001 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12002 pipe_config->has_dp_encoder,
12003 pipe_config->dp_m2_n2.gmch_m,
12004 pipe_config->dp_m2_n2.gmch_n,
12005 pipe_config->dp_m2_n2.link_m,
12006 pipe_config->dp_m2_n2.link_n,
12007 pipe_config->dp_m2_n2.tu);
12008
55072d19
DV		 12009 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12010 pipe_config->has_audio,
12011 pipe_config->has_infoframe);
12012
c0b03411 12013 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 12014 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 12015 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 12016 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12017 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 12018 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 12019 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12020 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 12021 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12022 crtc->num_scalers,
12023 pipe_config->scaler_state.scaler_users,
12024 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 12025 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12026 pipe_config->gmch_pfit.control,
12027 pipe_config->gmch_pfit.pgm_ratios,
12028 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12029 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12030 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 12031 pipe_config->pch_pfit.size,
12032 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12033 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12034 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12035
415ff0f6 12036 if (IS_BROXTON(dev)) {
05712c15 12037 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 12038 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 12039 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 12040 pipe_config->ddi_pll_sel,
12041 pipe_config->dpll_hw_state.ebb0,
05712c15 12042 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 12043 pipe_config->dpll_hw_state.pll0,
12044 pipe_config->dpll_hw_state.pll1,
12045 pipe_config->dpll_hw_state.pll2,
12046 pipe_config->dpll_hw_state.pll3,
12047 pipe_config->dpll_hw_state.pll6,
12048 pipe_config->dpll_hw_state.pll8,
05712c15 12049 pipe_config->dpll_hw_state.pll9,
c8453338 12050 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 12051 pipe_config->dpll_hw_state.pcsdw12);
12052 } else if (IS_SKYLAKE(dev)) {
12053 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12054 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12055 pipe_config->ddi_pll_sel,
12056 pipe_config->dpll_hw_state.ctrl1,
12057 pipe_config->dpll_hw_state.cfgcr1,
12058 pipe_config->dpll_hw_state.cfgcr2);
12059 } else if (HAS_DDI(dev)) {
12060 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12061 pipe_config->ddi_pll_sel,
12062 pipe_config->dpll_hw_state.wrpll);
12063 } else {
12064 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12065 "fp0: 0x%x, fp1: 0x%x\n",
12066 pipe_config->dpll_hw_state.dpll,
12067 pipe_config->dpll_hw_state.dpll_md,
12068 pipe_config->dpll_hw_state.fp0,
12069 pipe_config->dpll_hw_state.fp1);
12070 }
12071
6a60cd87
CK		 12072 DRM_DEBUG_KMS("planes on this crtc\n");
12073 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12074 intel_plane = to_intel_plane(plane);
12075 if (intel_plane->pipe != crtc->pipe)
12076 continue;
12077
12078 state = to_intel_plane_state(plane->state);
12079 fb = state->base.fb;
12080 if (!fb) {
12081 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12082 "disabled, scaler_id = %d\n",
12083 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12084 plane->base.id, intel_plane->pipe,
12085 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12086 drm_plane_index(plane), state->scaler_id);
12087 continue;
12088 }
12089
12090 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12091 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12092 plane->base.id, intel_plane->pipe,
12093 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12094 drm_plane_index(plane));
12095 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12096 fb->base.id, fb->width, fb->height, fb->pixel_format);
12097 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12098 state->scaler_id,
12099 state->src.x1 >> 16, state->src.y1 >> 16,
12100 drm_rect_width(&state->src) >> 16,
12101 drm_rect_height(&state->src) >> 16,
12102 state->dst.x1, state->dst.y1,
12103 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12104 }
c0b03411
DV		 12105}
12106
5448a00d 12107static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12108{
5448a00d
ACO		 12109 struct drm_device *dev = state->dev;
12110 struct intel_encoder *encoder;
da3ced29 12111 struct drm_connector *connector;
5448a00d 12112 struct drm_connector_state *connector_state;
00f0b378 12113 unsigned int used_ports = 0;
5448a00d 12114 int i;
00f0b378
VS		 12115
12116 /*
12117 * Walk the connector list instead of the encoder
12118 * list to detect the problem on ddi platforms
12119 * where there's just one encoder per digital port.
12120 */
da3ced29 12121 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12122 if (!connector_state->best_encoder)
00f0b378
VS		 12123 continue;
12124
5448a00d
ACO		 12125 encoder = to_intel_encoder(connector_state->best_encoder);
12126
12127 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12128
12129 switch (encoder->type) {
12130 unsigned int port_mask;
12131 case INTEL_OUTPUT_UNKNOWN:
12132 if (WARN_ON(!HAS_DDI(dev)))
12133 break;
12134 case INTEL_OUTPUT_DISPLAYPORT:
12135 case INTEL_OUTPUT_HDMI:
12136 case INTEL_OUTPUT_EDP:
12137 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12138
12139 /* the same port mustn't appear more than once */
12140 if (used_ports & port_mask)
12141 return false;
12142
12143 used_ports |= port_mask;
12144 default:
12145 break;
12146 }
12147 }
12148
12149 return true;
12150}
12151
83a57153
ACO		 12152static void
12153clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12154{
12155 struct drm_crtc_state tmp_state;
663a3640 12156 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12157 struct intel_dpll_hw_state dpll_hw_state;
12158 enum intel_dpll_id shared_dpll;
8504c74c 12159 uint32_t ddi_pll_sel;
83a57153 12160
7546a384
ACO		 12161 /* FIXME: before the switch to atomic started, a new pipe_config was
12162 * kzalloc'd. Code that depends on any field being zero should be
12163 * fixed, so that the crtc_state can be safely duplicated. For now,
12164 * only fields that are know to not cause problems are preserved. */
12165
83a57153 12166 tmp_state = crtc_state->base;
663a3640 12167 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12168 shared_dpll = crtc_state->shared_dpll;
12169 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12170 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12171
83a57153 12172 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12173
83a57153 12174 crtc_state->base = tmp_state;
663a3640 12175 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12176 crtc_state->shared_dpll = shared_dpll;
12177 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12178 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12179}
12180
548ee15b 12181static int
b8cecdf5 12182intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12183 struct intel_crtc_state *pipe_config)
ee7b9f93 12184{
b359283a 12185 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12186 struct intel_encoder *encoder;
da3ced29 12187 struct drm_connector *connector;
0b901879 12188 struct drm_connector_state *connector_state;
d328c9d7 12189 int base_bpp, ret = -EINVAL;
0b901879 12190 int i;
e29c22c0 12191 bool retry = true;
ee7b9f93 12192
83a57153 12193 clear_intel_crtc_state(pipe_config);
7758a113 12194
e143a21c
DV		 12195 pipe_config->cpu_transcoder =
12196 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12197
2960bc9c
ID		 12198 /*
12199 * Sanitize sync polarity flags based on requested ones. If neither
12200 * positive or negative polarity is requested, treat this as meaning
12201 * negative polarity.
12202 */
2d112de7 12203 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12204 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12205 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12206
2d112de7 12207 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12208 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12209 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12210
050f7aeb
DV		 12211 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12212 * plane pixel format and any sink constraints into account. Returns the
12213 * source plane bpp so that dithering can be selected on mismatches
12214 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12215 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12216 pipe_config);
12217 if (base_bpp < 0)
4e53c2e0
DV		 12218 goto fail;
12219
e41a56be
VS		 12220 /*
12221 * Determine the real pipe dimensions. Note that stereo modes can
12222 * increase the actual pipe size due to the frame doubling and
12223 * insertion of additional space for blanks between the frame. This
12224 * is stored in the crtc timings. We use the requested mode to do this
12225 * computation to clearly distinguish it from the adjusted mode, which
12226 * can be changed by the connectors in the below retry loop.
12227 */
2d112de7 12228 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12229 &pipe_config->pipe_src_w,
12230 &pipe_config->pipe_src_h);
e41a56be 12231
e29c22c0 12232encoder_retry:
ef1b460d 12233 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12234 pipe_config->port_clock = 0;
ef1b460d 12235 pipe_config->pixel_multiplier = 1;
ff9a6750 12236
135c81b8 12237 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12238 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12239 CRTC_STEREO_DOUBLE);
135c81b8 12240
7758a113
DV		 12241 /* Pass our mode to the connectors and the CRTC to give them a chance to
12242 * adjust it according to limitations or connector properties, and also
12243 * a chance to reject the mode entirely.
47f1c6c9 12244 */
da3ced29 12245 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12246 if (connector_state->crtc != crtc)
7758a113 12247 continue;
7ae89233 12248
0b901879
ACO		 12249 encoder = to_intel_encoder(connector_state->best_encoder);
12250
efea6e8e
DV		 12251 if (!(encoder->compute_config(encoder, pipe_config))) {
12252 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12253 goto fail;
12254 }
ee7b9f93 12255 }
47f1c6c9 12256
ff9a6750
DV		 12257 /* Set default port clock if not overwritten by the encoder. Needs to be
12258 * done afterwards in case the encoder adjusts the mode. */
12259 if (!pipe_config->port_clock)
2d112de7 12260 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12261 * pipe_config->pixel_multiplier;
ff9a6750 12262
a43f6e0f 12263 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12264 if (ret < 0) {
7758a113
DV		 12265 DRM_DEBUG_KMS("CRTC fixup failed\n");
12266 goto fail;
ee7b9f93 12267 }
e29c22c0
DV		 12268
12269 if (ret == RETRY) {
12270 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12271 ret = -EINVAL;
12272 goto fail;
12273 }
12274
12275 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12276 retry = false;
12277 goto encoder_retry;
12278 }
12279
d328c9d7 12280 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12281 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12282 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12283
7758a113 12284fail:
548ee15b 12285 return ret;
ee7b9f93 12286}
47f1c6c9 12287
ea9d758d 12288static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12289{
ea9d758d 12290 struct drm_encoder *encoder;
f6e5b160 12291 struct drm_device *dev = crtc->dev;
f6e5b160 12292
ea9d758d
DV		 12293 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12294 if (encoder->crtc == crtc)
12295 return true;
12296
12297 return false;
12298}
12299
12300static void
0a9ab303 12301intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12302{
0a9ab303 12303 struct drm_device *dev = state->dev;
ea9d758d 12304 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12305 struct drm_crtc *crtc;
12306 struct drm_crtc_state *crtc_state;
ea9d758d 12307 struct drm_connector *connector;
8a75d157 12308 int i;
ea9d758d 12309
de419ab6 12310 intel_shared_dpll_commit(state);
ba41c0de 12311
b2784e15 12312 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12313 if (!intel_encoder->base.crtc)
12314 continue;
12315
69024de8
ML		 12316 crtc = intel_encoder->base.crtc;
12317 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12318 if (!crtc_state || !needs_modeset(crtc->state))
12319 continue;
ea9d758d 12320
69024de8 12321 intel_encoder->connectors_active = false;
ea9d758d
DV		 12322 }
12323
3cb480bc 12324 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
ea9d758d 12325
7668851f 12326 /* Double check state. */
8a75d157 12327 for_each_crtc_in_state(state, crtc, crtc_state, i) {
0a9ab303 12328 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12329
12330 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12331
12332 /* Update hwmode for vblank functions */
12333 if (crtc->state->active)
12334 crtc->hwmode = crtc->state->adjusted_mode;
12335 else
12336 crtc->hwmode.crtc_clock = 0;
ea9d758d
DV		 12337 }
12338
12339 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12340 if (!connector->encoder || !connector->encoder->crtc)
12341 continue;
12342
69024de8
ML		 12343 crtc = connector->encoder->crtc;
12344 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12345 if (!crtc_state || !needs_modeset(crtc->state))
12346 continue;
ea9d758d 12347
53d9f4e9 12348 if (crtc->state->active) {
69024de8
ML		 12349 struct drm_property *dpms_property =
12350 dev->mode_config.dpms_property;
68d34720 12351
69024de8
ML		 12352 connector->dpms = DRM_MODE_DPMS_ON;
12353 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12354
69024de8
ML		 12355 intel_encoder = to_intel_encoder(connector->encoder);
12356 intel_encoder->connectors_active = true;
12357 } else
12358 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12359 }
ea9d758d
DV		 12360}
12361
3bd26263 12362static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12363{
3bd26263 12364 int diff;
f1f644dc
JB		 12365
12366 if (clock1 == clock2)
12367 return true;
12368
12369 if (!clock1 || !clock2)
12370 return false;
12371
12372 diff = abs(clock1 - clock2);
12373
12374 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12375 return true;
12376
12377 return false;
12378}
12379
25c5b266
DV		 12380#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12381 list_for_each_entry((intel_crtc), \
12382 &(dev)->mode_config.crtc_list, \
12383 base.head) \
0973f18f 12384 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12385
cfb23ed6
ML		 12386
12387static bool
12388intel_compare_m_n(unsigned int m, unsigned int n,
12389 unsigned int m2, unsigned int n2,
12390 bool exact)
12391{
12392 if (m == m2 && n == n2)
12393 return true;
12394
12395 if (exact || !m || !n || !m2 || !n2)
12396 return false;
12397
12398 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12399
12400 if (m > m2) {
12401 while (m > m2) {
12402 m2 <<= 1;
12403 n2 <<= 1;
12404 }
12405 } else if (m < m2) {
12406 while (m < m2) {
12407 m <<= 1;
12408 n <<= 1;
12409 }
12410 }
12411
12412 return m == m2 && n == n2;
12413}
12414
12415static bool
12416intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12417 struct intel_link_m_n *m2_n2,
12418 bool adjust)
12419{
12420 if (m_n->tu == m2_n2->tu &&
12421 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12422 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12423 intel_compare_m_n(m_n->link_m, m_n->link_n,
12424 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12425 if (adjust)
12426 *m2_n2 = *m_n;
12427
12428 return true;
12429 }
12430
12431 return false;
12432}
12433
0e8ffe1b 12434static bool
2fa2fe9a 12435intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12436 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12437 struct intel_crtc_state *pipe_config,
12438 bool adjust)
0e8ffe1b 12439{
cfb23ed6
ML		 12440 bool ret = true;
12441
12442#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12443 do { \
12444 if (!adjust) \
12445 DRM_ERROR(fmt, ##__VA_ARGS__); \
12446 else \
12447 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12448 } while (0)
12449
66e985c0
DV		 12450#define PIPE_CONF_CHECK_X(name) \
12451 if (current_config->name != pipe_config->name) { \
cfb23ed6 12452 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12453 "(expected 0x%08x, found 0x%08x)\n", \
12454 current_config->name, \
12455 pipe_config->name); \
cfb23ed6 12456 ret = false; \
66e985c0
DV		 12457 }
12458
08a24034
DV		 12459#define PIPE_CONF_CHECK_I(name) \
12460 if (current_config->name != pipe_config->name) { \
cfb23ed6 12461 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12462 "(expected %i, found %i)\n", \
12463 current_config->name, \
12464 pipe_config->name); \
cfb23ed6
ML		 12465 ret = false; \
12466 }
12467
12468#define PIPE_CONF_CHECK_M_N(name) \
12469 if (!intel_compare_link_m_n(&current_config->name, \
12470 &pipe_config->name,\
12471 adjust)) { \
12472 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12473 "(expected tu %i gmch %i/%i link %i/%i, " \
12474 "found tu %i, gmch %i/%i link %i/%i)\n", \
12475 current_config->name.tu, \
12476 current_config->name.gmch_m, \
12477 current_config->name.gmch_n, \
12478 current_config->name.link_m, \
12479 current_config->name.link_n, \
12480 pipe_config->name.tu, \
12481 pipe_config->name.gmch_m, \
12482 pipe_config->name.gmch_n, \
12483 pipe_config->name.link_m, \
12484 pipe_config->name.link_n); \
12485 ret = false; \
12486 }
12487
12488#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12489 if (!intel_compare_link_m_n(&current_config->name, \
12490 &pipe_config->name, adjust) && \
12491 !intel_compare_link_m_n(&current_config->alt_name, \
12492 &pipe_config->name, adjust)) { \
12493 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12494 "(expected tu %i gmch %i/%i link %i/%i, " \
12495 "or tu %i gmch %i/%i link %i/%i, " \
12496 "found tu %i, gmch %i/%i link %i/%i)\n", \
12497 current_config->name.tu, \
12498 current_config->name.gmch_m, \
12499 current_config->name.gmch_n, \
12500 current_config->name.link_m, \
12501 current_config->name.link_n, \
12502 current_config->alt_name.tu, \
12503 current_config->alt_name.gmch_m, \
12504 current_config->alt_name.gmch_n, \
12505 current_config->alt_name.link_m, \
12506 current_config->alt_name.link_n, \
12507 pipe_config->name.tu, \
12508 pipe_config->name.gmch_m, \
12509 pipe_config->name.gmch_n, \
12510 pipe_config->name.link_m, \
12511 pipe_config->name.link_n); \
12512 ret = false; \
88adfff1
DV		 12513 }
12514
b95af8be
VK		 12515/* This is required for BDW+ where there is only one set of registers for
12516 * switching between high and low RR.
12517 * This macro can be used whenever a comparison has to be made between one
12518 * hw state and multiple sw state variables.
12519 */
12520#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12521 if ((current_config->name != pipe_config->name) && \
12522 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12523 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12524 "(expected %i or %i, found %i)\n", \
12525 current_config->name, \
12526 current_config->alt_name, \
12527 pipe_config->name); \
cfb23ed6 12528 ret = false; \
b95af8be
VK		 12529 }
12530
1bd1bd80
DV		 12531#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12532 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12533 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12534 "(expected %i, found %i)\n", \
12535 current_config->name & (mask), \
12536 pipe_config->name & (mask)); \
cfb23ed6 12537 ret = false; \
1bd1bd80
DV		 12538 }
12539
5e550656
VS		 12540#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12541 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12542 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12543 "(expected %i, found %i)\n", \
12544 current_config->name, \
12545 pipe_config->name); \
cfb23ed6 12546 ret = false; \
5e550656
VS		 12547 }
12548
bb760063
DV		 12549#define PIPE_CONF_QUIRK(quirk) \
12550 ((current_config->quirks | pipe_config->quirks) & (quirk))
12551
eccb140b
DV		 12552 PIPE_CONF_CHECK_I(cpu_transcoder);
12553
08a24034
DV		 12554 PIPE_CONF_CHECK_I(has_pch_encoder);
12555 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12556 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12557
eb14cb74 12558 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12559
12560 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12561 PIPE_CONF_CHECK_M_N(dp_m_n);
12562
12563 PIPE_CONF_CHECK_I(has_drrs);
12564 if (current_config->has_drrs)
12565 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12566 } else
12567 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12568
2d112de7
ACO		 12569 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12570 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12571 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12572 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12573 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12574 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12575
2d112de7
ACO		 12576 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12577 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12578 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12579 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12580 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12581 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12582
c93f54cf 12583 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12584 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12585 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12586 IS_VALLEYVIEW(dev))
12587 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12588 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12589
9ed109a7
DV		 12590 PIPE_CONF_CHECK_I(has_audio);
12591
2d112de7 12592 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12593 DRM_MODE_FLAG_INTERLACE);
12594
bb760063 12595 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12596 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12597 DRM_MODE_FLAG_PHSYNC);
2d112de7 12598 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12599 DRM_MODE_FLAG_NHSYNC);
2d112de7 12600 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12601 DRM_MODE_FLAG_PVSYNC);
2d112de7 12602 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12603 DRM_MODE_FLAG_NVSYNC);
12604 }
045ac3b5 12605
37327abd
VS		 12606 PIPE_CONF_CHECK_I(pipe_src_w);
12607 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12608
9953599b
DV		 12609 /*
12610 * FIXME: BIOS likes to set up a cloned config with lvds+external
12611 * screen. Since we don't yet re-compute the pipe config when moving
12612 * just the lvds port away to another pipe the sw tracking won't match.
12613 *
12614 * Proper atomic modesets with recomputed global state will fix this.
12615 * Until then just don't check gmch state for inherited modes.
12616 */
12617 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12618 PIPE_CONF_CHECK_I(gmch_pfit.control);
12619 /* pfit ratios are autocomputed by the hw on gen4+ */
12620 if (INTEL_INFO(dev)->gen < 4)
12621 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12622 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12623 }
12624
fd4daa9c
CW		 12625 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12626 if (current_config->pch_pfit.enabled) {
12627 PIPE_CONF_CHECK_I(pch_pfit.pos);
12628 PIPE_CONF_CHECK_I(pch_pfit.size);
12629 }
2fa2fe9a 12630
a1b2278e
CK		 12631 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12632
e59150dc
JB		 12633 /* BDW+ don't expose a synchronous way to read the state */
12634 if (IS_HASWELL(dev))
12635 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12636
282740f7
VS		 12637 PIPE_CONF_CHECK_I(double_wide);
12638
26804afd
DV		 12639 PIPE_CONF_CHECK_X(ddi_pll_sel);
12640
c0d43d62 12641 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12642 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12643 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12644 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12645 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12646 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12647 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12648 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12649 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12650
42571aef
VS		 12651 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12652 PIPE_CONF_CHECK_I(pipe_bpp);
12653
2d112de7 12654 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12655 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12656
66e985c0 12657#undef PIPE_CONF_CHECK_X
08a24034 12658#undef PIPE_CONF_CHECK_I
b95af8be 12659#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12660#undef PIPE_CONF_CHECK_FLAGS
5e550656 12661#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12662#undef PIPE_CONF_QUIRK
cfb23ed6 12663#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12664
cfb23ed6 12665 return ret;
0e8ffe1b
DV		 12666}
12667
08db6652
DL		 12668static void check_wm_state(struct drm_device *dev)
12669{
12670 struct drm_i915_private *dev_priv = dev->dev_private;
12671 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12672 struct intel_crtc *intel_crtc;
12673 int plane;
12674
12675 if (INTEL_INFO(dev)->gen < 9)
12676 return;
12677
12678 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12679 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12680
12681 for_each_intel_crtc(dev, intel_crtc) {
12682 struct skl_ddb_entry *hw_entry, *sw_entry;
12683 const enum pipe pipe = intel_crtc->pipe;
12684
12685 if (!intel_crtc->active)
12686 continue;
12687
12688 /* planes */
dd740780 12689 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12690 hw_entry = &hw_ddb.plane[pipe][plane];
12691 sw_entry = &sw_ddb->plane[pipe][plane];
12692
12693 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12694 continue;
12695
12696 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12697 "(expected (%u,%u), found (%u,%u))\n",
12698 pipe_name(pipe), plane + 1,
12699 sw_entry->start, sw_entry->end,
12700 hw_entry->start, hw_entry->end);
12701 }
12702
12703 /* cursor */
12704 hw_entry = &hw_ddb.cursor[pipe];
12705 sw_entry = &sw_ddb->cursor[pipe];
12706
12707 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12708 continue;
12709
12710 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12711 "(expected (%u,%u), found (%u,%u))\n",
12712 pipe_name(pipe),
12713 sw_entry->start, sw_entry->end,
12714 hw_entry->start, hw_entry->end);
12715 }
12716}
12717
91d1b4bd
DV		 12718static void
12719check_connector_state(struct drm_device *dev)
8af6cf88 12720{
8af6cf88
DV		 12721 struct intel_connector *connector;
12722
3a3371ff 12723 for_each_intel_connector(dev, connector) {
ad3c558f
ML		 12724 struct drm_encoder *encoder = connector->base.encoder;
12725 struct drm_connector_state *state = connector->base.state;
12726
8af6cf88
DV		 12727 /* This also checks the encoder/connector hw state with the
12728 * ->get_hw_state callbacks. */
12729 intel_connector_check_state(connector);
12730
ad3c558f 12731 I915_STATE_WARN(state->best_encoder != encoder,
8af6cf88
DV		 12732 "connector's staged encoder doesn't match current encoder\n");
12733 }
91d1b4bd
DV		 12734}
12735
12736static void
12737check_encoder_state(struct drm_device *dev)
12738{
12739 struct intel_encoder *encoder;
12740 struct intel_connector *connector;
8af6cf88 12741
b2784e15 12742 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12743 bool enabled = false;
12744 bool active = false;
12745 enum pipe pipe, tracked_pipe;
12746
12747 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12748 encoder->base.base.id,
8e329a03 12749 encoder->base.name);
8af6cf88 12750
e2c719b7 12751 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12752 "encoder's active_connectors set, but no crtc\n");
12753
3a3371ff 12754 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12755 if (connector->base.encoder != &encoder->base)
12756 continue;
12757 enabled = true;
12758 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12759 active = true;
ad3c558f
ML		 12760
12761 I915_STATE_WARN(connector->base.state->crtc !=
12762 encoder->base.crtc,
12763 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 12764 }
0e32b39c
DA		 12765 /*
12766 * for MST connectors if we unplug the connector is gone
12767 * away but the encoder is still connected to a crtc
12768 * until a modeset happens in response to the hotplug.
12769 */
12770 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12771 continue;
12772
e2c719b7 12773 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12774 "encoder's enabled state mismatch "
12775 "(expected %i, found %i)\n",
12776 !!encoder->base.crtc, enabled);
e2c719b7 12777 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12778 "active encoder with no crtc\n");
12779
e2c719b7 12780 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12781 "encoder's computed active state doesn't match tracked active state "
12782 "(expected %i, found %i)\n", active, encoder->connectors_active);
12783
12784 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12785 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12786 "encoder's hw state doesn't match sw tracking "
12787 "(expected %i, found %i)\n",
12788 encoder->connectors_active, active);
12789
12790 if (!encoder->base.crtc)
12791 continue;
12792
12793 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12794 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12795 "active encoder's pipe doesn't match"
12796 "(expected %i, found %i)\n",
12797 tracked_pipe, pipe);
12798
12799 }
91d1b4bd
DV		 12800}
12801
12802static void
12803check_crtc_state(struct drm_device *dev)
12804{
fbee40df 12805 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12806 struct intel_crtc *crtc;
12807 struct intel_encoder *encoder;
5cec258b 12808 struct intel_crtc_state pipe_config;
8af6cf88 12809
d3fcc808 12810 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12811 bool enabled = false;
12812 bool active = false;
12813
045ac3b5
JB		 12814 memset(&pipe_config, 0, sizeof(pipe_config));
12815
8af6cf88
DV		 12816 DRM_DEBUG_KMS("[CRTC:%d]\n",
12817 crtc->base.base.id);
12818
83d65738 12819 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12820 "active crtc, but not enabled in sw tracking\n");
12821
b2784e15 12822 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12823 if (encoder->base.crtc != &crtc->base)
12824 continue;
12825 enabled = true;
12826 if (encoder->connectors_active)
12827 active = true;
12828 }
6c49f241 12829
e2c719b7 12830 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12831 "crtc's computed active state doesn't match tracked active state "
12832 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12833 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12834 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12835 "(expected %i, found %i)\n", enabled,
12836 crtc->base.state->enable);
8af6cf88 12837
0e8ffe1b
DV		 12838 active = dev_priv->display.get_pipe_config(crtc,
12839 &pipe_config);
d62cf62a 12840
b6b5d049
VS		 12841 /* hw state is inconsistent with the pipe quirk */
12842 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12843 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12844 active = crtc->active;
12845
b2784e15 12846 for_each_intel_encoder(dev, encoder) {
3eaba51c 12847 enum pipe pipe;
6c49f241
DV		 12848 if (encoder->base.crtc != &crtc->base)
12849 continue;
1d37b689 12850 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12851 encoder->get_config(encoder, &pipe_config);
12852 }
12853
e2c719b7 12854 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12855 "crtc active state doesn't match with hw state "
12856 "(expected %i, found %i)\n", crtc->active, active);
12857
53d9f4e9
ML		 12858 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12859 "transitional active state does not match atomic hw state "
12860 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12861
cfb23ed6
ML		 12862 if (!active)
12863 continue;
12864
12865 if (!intel_pipe_config_compare(dev, crtc->config,
12866 &pipe_config, false)) {
e2c719b7 12867 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12868 intel_dump_pipe_config(crtc, &pipe_config,
12869 "[hw state]");
6e3c9717 12870 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12871 "[sw state]");
12872 }
8af6cf88
DV		 12873 }
12874}
12875
91d1b4bd
DV		 12876static void
12877check_shared_dpll_state(struct drm_device *dev)
12878{
fbee40df 12879 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12880 struct intel_crtc *crtc;
12881 struct intel_dpll_hw_state dpll_hw_state;
12882 int i;
5358901f
DV		 12883
12884 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12885 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12886 int enabled_crtcs = 0, active_crtcs = 0;
12887 bool active;
12888
12889 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12890
12891 DRM_DEBUG_KMS("%s\n", pll->name);
12892
12893 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12894
e2c719b7 12895 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12896 "more active pll users than references: %i vs %i\n",
3e369b76 12897 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12898 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12899 "pll in active use but not on in sw tracking\n");
e2c719b7 12900 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12901 "pll in on but not on in use in sw tracking\n");
e2c719b7 12902 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12903 "pll on state mismatch (expected %i, found %i)\n",
12904 pll->on, active);
12905
d3fcc808 12906 for_each_intel_crtc(dev, crtc) {
83d65738 12907 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12908 enabled_crtcs++;
12909 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12910 active_crtcs++;
12911 }
e2c719b7 12912 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12913 "pll active crtcs mismatch (expected %i, found %i)\n",
12914 pll->active, active_crtcs);
e2c719b7 12915 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12916 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12917 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12918
e2c719b7 12919 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12920 sizeof(dpll_hw_state)),
12921 "pll hw state mismatch\n");
5358901f 12922 }
8af6cf88
DV		 12923}
12924
91d1b4bd
DV		 12925void
12926intel_modeset_check_state(struct drm_device *dev)
12927{
08db6652 12928 check_wm_state(dev);
91d1b4bd
DV		 12929 check_connector_state(dev);
12930 check_encoder_state(dev);
12931 check_crtc_state(dev);
12932 check_shared_dpll_state(dev);
12933}
12934
5cec258b 12935void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12936 int dotclock)
12937{
12938 /*
12939 * FDI already provided one idea for the dotclock.
12940 * Yell if the encoder disagrees.
12941 */
2d112de7 12942 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12943 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12944 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12945}
12946
80715b2f
VS		 12947static void update_scanline_offset(struct intel_crtc *crtc)
12948{
12949 struct drm_device *dev = crtc->base.dev;
12950
12951 /*
12952 * The scanline counter increments at the leading edge of hsync.
12953 *
12954 * On most platforms it starts counting from vtotal-1 on the
12955 * first active line. That means the scanline counter value is
12956 * always one less than what we would expect. Ie. just after
12957 * start of vblank, which also occurs at start of hsync (on the
12958 * last active line), the scanline counter will read vblank_start-1.
12959 *
12960 * On gen2 the scanline counter starts counting from 1 instead
12961 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12962 * to keep the value positive), instead of adding one.
12963 *
12964 * On HSW+ the behaviour of the scanline counter depends on the output
12965 * type. For DP ports it behaves like most other platforms, but on HDMI
12966 * there's an extra 1 line difference. So we need to add two instead of
12967 * one to the value.
12968 */
12969 if (IS_GEN2(dev)) {
6e3c9717 12970 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12971 int vtotal;
12972
12973 vtotal = mode->crtc_vtotal;
12974 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12975 vtotal /= 2;
12976
12977 crtc->scanline_offset = vtotal - 1;
12978 } else if (HAS_DDI(dev) &&
409ee761 12979 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12980 crtc->scanline_offset = 2;
12981 } else
12982 crtc->scanline_offset = 1;
12983}
12984
ad421372 12985static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12986{
225da59b 12987 struct drm_device *dev = state->dev;
ed6739ef 12988 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12989 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12990 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12991 struct intel_crtc_state *intel_crtc_state;
12992 struct drm_crtc *crtc;
12993 struct drm_crtc_state *crtc_state;
0a9ab303 12994 int i;
ed6739ef
ACO		 12995
12996 if (!dev_priv->display.crtc_compute_clock)
ad421372 12997 return;
ed6739ef 12998
0a9ab303 12999 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 13000 int dpll;
13001
0a9ab303 13002 intel_crtc = to_intel_crtc(crtc);
4978cc93 13003 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 13004 dpll = intel_crtc_state->shared_dpll;
0a9ab303 13005
ad421372 13006 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 13007 continue;
13008
ad421372 13009 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 13010
ad421372
ML		 13011 if (!shared_dpll)
13012 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 13013
ad421372
ML		 13014 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13015 }
ed6739ef
ACO		 13016}
13017
99d736a2
ML		 13018/*
13019 * This implements the workaround described in the "notes" section of the mode
13020 * set sequence documentation. When going from no pipes or single pipe to
13021 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13022 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13023 */
13024static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13025{
13026 struct drm_crtc_state *crtc_state;
13027 struct intel_crtc *intel_crtc;
13028 struct drm_crtc *crtc;
13029 struct intel_crtc_state *first_crtc_state = NULL;
13030 struct intel_crtc_state *other_crtc_state = NULL;
13031 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13032 int i;
13033
13034 /* look at all crtc's that are going to be enabled in during modeset */
13035 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13036 intel_crtc = to_intel_crtc(crtc);
13037
13038 if (!crtc_state->active || !needs_modeset(crtc_state))
13039 continue;
13040
13041 if (first_crtc_state) {
13042 other_crtc_state = to_intel_crtc_state(crtc_state);
13043 break;
13044 } else {
13045 first_crtc_state = to_intel_crtc_state(crtc_state);
13046 first_pipe = intel_crtc->pipe;
13047 }
13048 }
13049
13050 /* No workaround needed? */
13051 if (!first_crtc_state)
13052 return 0;
13053
13054 /* w/a possibly needed, check how many crtc's are already enabled. */
13055 for_each_intel_crtc(state->dev, intel_crtc) {
13056 struct intel_crtc_state *pipe_config;
13057
13058 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13059 if (IS_ERR(pipe_config))
13060 return PTR_ERR(pipe_config);
13061
13062 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13063
13064 if (!pipe_config->base.active ||
13065 needs_modeset(&pipe_config->base))
13066 continue;
13067
13068 /* 2 or more enabled crtcs means no need for w/a */
13069 if (enabled_pipe != INVALID_PIPE)
13070 return 0;
13071
13072 enabled_pipe = intel_crtc->pipe;
13073 }
13074
13075 if (enabled_pipe != INVALID_PIPE)
13076 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13077 else if (other_crtc_state)
13078 other_crtc_state->hsw_workaround_pipe = first_pipe;
13079
13080 return 0;
13081}
13082
27c329ed
ML		 13083static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13084{
13085 struct drm_crtc *crtc;
13086 struct drm_crtc_state *crtc_state;
13087 int ret = 0;
13088
13089 /* add all active pipes to the state */
13090 for_each_crtc(state->dev, crtc) {
13091 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13092 if (IS_ERR(crtc_state))
13093 return PTR_ERR(crtc_state);
13094
13095 if (!crtc_state->active || needs_modeset(crtc_state))
13096 continue;
13097
13098 crtc_state->mode_changed = true;
13099
13100 ret = drm_atomic_add_affected_connectors(state, crtc);
13101 if (ret)
13102 break;
13103
13104 ret = drm_atomic_add_affected_planes(state, crtc);
13105 if (ret)
13106 break;
13107 }
13108
13109 return ret;
13110}
13111
13112
c347a676 13113static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 13114{
13115 struct drm_device *dev = state->dev;
27c329ed 13116 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 13117 int ret;
13118
b359283a
ML		 13119 if (!check_digital_port_conflicts(state)) {
13120 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13121 return -EINVAL;
13122 }
13123
054518dd
ACO		 13124 /*
13125 * See if the config requires any additional preparation, e.g.
13126 * to adjust global state with pipes off. We need to do this
13127 * here so we can get the modeset_pipe updated config for the new
13128 * mode set on this crtc. For other crtcs we need to use the
13129 * adjusted_mode bits in the crtc directly.
13130 */
27c329ed
ML		 13131 if (dev_priv->display.modeset_calc_cdclk) {
13132 unsigned int cdclk;
b432e5cf 13133
27c329ed
ML		 13134 ret = dev_priv->display.modeset_calc_cdclk(state);
13135
13136 cdclk = to_intel_atomic_state(state)->cdclk;
13137 if (!ret && cdclk != dev_priv->cdclk_freq)
13138 ret = intel_modeset_all_pipes(state);
13139
13140 if (ret < 0)
054518dd 13141 return ret;
27c329ed
ML		 13142 } else
13143 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13144
ad421372 13145 intel_modeset_clear_plls(state);
054518dd 13146
99d736a2 13147 if (IS_HASWELL(dev))
ad421372 13148 return haswell_mode_set_planes_workaround(state);
99d736a2 13149
ad421372 13150 return 0;
c347a676
ACO		 13151}
13152
74c090b1
ML		 13153/**
13154 * intel_atomic_check - validate state object
13155 * @dev: drm device
13156 * @state: state to validate
13157 */
13158static int intel_atomic_check(struct drm_device *dev,
13159 struct drm_atomic_state *state)
c347a676
ACO		 13160{
13161 struct drm_crtc *crtc;
13162 struct drm_crtc_state *crtc_state;
13163 int ret, i;
61333b60 13164 bool any_ms = false;
c347a676 13165
74c090b1 13166 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO		 13167 if (ret)
13168 return ret;
13169
c347a676 13170 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 13171 struct intel_crtc_state *pipe_config =
13172 to_intel_crtc_state(crtc_state);
5c1e3426 13173 bool modeset, recalc = false;
cfb23ed6 13174
61333b60
ML		 13175 if (!crtc_state->enable) {
13176 if (needs_modeset(crtc_state))
13177 any_ms = true;
c347a676 13178 continue;
61333b60 13179 }
c347a676 13180
cfb23ed6 13181 modeset = needs_modeset(crtc_state);
5c1e3426
ML		 13182 /* see comment in intel_modeset_readout_hw_state */
13183 if (!modeset && crtc_state->mode_blob != crtc->state->mode_blob &&
13184 pipe_config->quirks & PIPE_CONFIG_QUIRK_INHERITED_MODE)
13185 recalc = true;
cfb23ed6
ML		 13186
13187 if (!modeset && !recalc)
13188 continue;
13189
13190 if (recalc) {
b359283a
ML		 13191 ret = drm_atomic_add_affected_connectors(state, crtc);
13192 if (ret)
13193 return ret;
13194 }
13195
cfb23ed6 13196 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13197 if (ret)
13198 return ret;
13199
5c1e3426
ML		 13200 if (recalc && (!i915.fastboot ||
13201 !intel_pipe_config_compare(state->dev,
cfb23ed6 13202 to_intel_crtc_state(crtc->state),
5c1e3426 13203 pipe_config, true))) {
cfb23ed6
ML		 13204 modeset = crtc_state->mode_changed = true;
13205
13206 ret = drm_atomic_add_affected_planes(state, crtc);
13207 if (ret)
13208 return ret;
13209 }
61333b60 13210
cfb23ed6 13211 any_ms = modeset;
c347a676 13212 intel_dump_pipe_config(to_intel_crtc(crtc),
cfb23ed6
ML		 13213 pipe_config,
13214 modeset ? "[modeset]" : "[fastboot]");
c347a676
ACO		 13215 }
13216
61333b60
ML		 13217 if (any_ms) {
13218 ret = intel_modeset_checks(state);
13219
13220 if (ret)
13221 return ret;
27c329ed
ML		 13222 } else
13223 to_intel_atomic_state(state)->cdclk =
13224 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13225
13226 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13227}
13228
74c090b1
ML		 13229/**
13230 * intel_atomic_commit - commit validated state object
13231 * @dev: DRM device
13232 * @state: the top-level driver state object
13233 * @async: asynchronous commit
13234 *
13235 * This function commits a top-level state object that has been validated
13236 * with drm_atomic_helper_check().
13237 *
13238 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13239 * we can only handle plane-related operations and do not yet support
13240 * asynchronous commit.
13241 *
13242 * RETURNS
13243 * Zero for success or -errno.
13244 */
13245static int intel_atomic_commit(struct drm_device *dev,
13246 struct drm_atomic_state *state,
13247 bool async)
a6778b3c 13248{
fbee40df 13249 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13250 struct drm_crtc *crtc;
13251 struct drm_crtc_state *crtc_state;
c0c36b94 13252 int ret = 0;
0a9ab303 13253 int i;
61333b60 13254 bool any_ms = false;
a6778b3c 13255
74c090b1
ML		 13256 if (async) {
13257 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13258 return -EINVAL;
13259 }
13260
d4afb8cc
ACO		 13261 ret = drm_atomic_helper_prepare_planes(dev, state);
13262 if (ret)
13263 return ret;
13264
1c5e19f8
ML		 13265 drm_atomic_helper_swap_state(dev, state);
13266
0a9ab303 13267 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13269
61333b60
ML		 13270 if (!needs_modeset(crtc->state))
13271 continue;
13272
13273 any_ms = true;
a539205a 13274 intel_pre_plane_update(intel_crtc);
460da916 13275
a539205a
ML		 13276 if (crtc_state->active) {
13277 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13278 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13279 intel_crtc->active = false;
13280 intel_disable_shared_dpll(intel_crtc);
a539205a 13281 }
b8cecdf5 13282 }
7758a113 13283
ea9d758d
DV		 13284 /* Only after disabling all output pipelines that will be changed can we
13285 * update the the output configuration. */
0a9ab303 13286 intel_modeset_update_state(state);
f6e5b160 13287
a821fc46
ACO		 13288 /* The state has been swaped above, so state actually contains the
13289 * old state now. */
61333b60
ML		 13290 if (any_ms)
13291 modeset_update_crtc_power_domains(state);
47fab737 13292
a6778b3c 13293 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13294 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13295 if (needs_modeset(crtc->state) && crtc->state->active) {
13296 update_scanline_offset(to_intel_crtc(crtc));
13297 dev_priv->display.crtc_enable(crtc);
13298 }
80715b2f 13299
a539205a 13300 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
80715b2f 13301 }
a6778b3c 13302
a6778b3c 13303 /* FIXME: add subpixel order */
83a57153 13304
74c090b1 13305 drm_atomic_helper_wait_for_vblanks(dev, state);
d4afb8cc 13306 drm_atomic_helper_cleanup_planes(dev, state);
2bfb4627
ACO		 13307 drm_atomic_state_free(state);
13308
74c090b1 13309 if (any_ms)
568c634a 13310 intel_modeset_check_state(dev);
f30da187 13311
74c090b1 13312 return 0;
7f27126e
JB		 13313}
13314
c0c36b94
CW		 13315void intel_crtc_restore_mode(struct drm_crtc *crtc)
13316{
83a57153
ACO		 13317 struct drm_device *dev = crtc->dev;
13318 struct drm_atomic_state *state;
e694eb02 13319 struct drm_crtc_state *crtc_state;
2bfb4627 13320 int ret;
83a57153
ACO		 13321
13322 state = drm_atomic_state_alloc(dev);
13323 if (!state) {
e694eb02 13324 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
83a57153
ACO		 13325 crtc->base.id);
13326 return;
13327 }
13328
e694eb02 13329 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
83a57153 13330
e694eb02
ML		 13331retry:
13332 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13333 ret = PTR_ERR_OR_ZERO(crtc_state);
13334 if (!ret) {
13335 if (!crtc_state->active)
13336 goto out;
83a57153 13337
e694eb02 13338 crtc_state->mode_changed = true;
74c090b1 13339 ret = drm_atomic_commit(state);
83a57153
ACO		 13340 }
13341
e694eb02
ML		 13342 if (ret == -EDEADLK) {
13343 drm_atomic_state_clear(state);
13344 drm_modeset_backoff(state->acquire_ctx);
13345 goto retry;
4ed9fb37 13346 }
4be07317 13347
2bfb4627 13348 if (ret)
e694eb02 13349out:
2bfb4627 13350 drm_atomic_state_free(state);
c0c36b94
CW		 13351}
13352
25c5b266
DV		 13353#undef for_each_intel_crtc_masked
13354
f6e5b160 13355static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13356 .gamma_set = intel_crtc_gamma_set,
74c090b1 13357 .set_config = drm_atomic_helper_set_config,
f6e5b160
CW		 13358 .destroy = intel_crtc_destroy,
13359 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13360 .atomic_duplicate_state = intel_crtc_duplicate_state,
13361 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13362};
13363
5358901f
DV		 13364static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13365 struct intel_shared_dpll *pll,
13366 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13367{
5358901f 13368 uint32_t val;
ee7b9f93 13369
f458ebbc 13370 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13371 return false;
13372
5358901f 13373 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13374 hw_state->dpll = val;
13375 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13376 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13377
13378 return val & DPLL_VCO_ENABLE;
13379}
13380
15bdd4cf
DV		 13381static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13382 struct intel_shared_dpll *pll)
13383{
3e369b76
ACO		 13384 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13385 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13386}
13387
e7b903d2
DV		 13388static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13389 struct intel_shared_dpll *pll)
13390{
e7b903d2 13391 /* PCH refclock must be enabled first */
89eff4be 13392 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13393
3e369b76 13394 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13395
13396 /* Wait for the clocks to stabilize. */
13397 POSTING_READ(PCH_DPLL(pll->id));
13398 udelay(150);
13399
13400 /* The pixel multiplier can only be updated once the
13401 * DPLL is enabled and the clocks are stable.
13402 *
13403 * So write it again.
13404 */
3e369b76 13405 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13406 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13407 udelay(200);
13408}
13409
13410static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13411 struct intel_shared_dpll *pll)
13412{
13413 struct drm_device *dev = dev_priv->dev;
13414 struct intel_crtc *crtc;
e7b903d2
DV		 13415
13416 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13417 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13418 if (intel_crtc_to_shared_dpll(crtc) == pll)
13419 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13420 }
13421
15bdd4cf
DV		 13422 I915_WRITE(PCH_DPLL(pll->id), 0);
13423 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13424 udelay(200);
13425}
13426
46edb027
DV		 13427static char *ibx_pch_dpll_names[] = {
13428 "PCH DPLL A",
13429 "PCH DPLL B",
13430};
13431
7c74ade1 13432static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13433{
e7b903d2 13434 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13435 int i;
13436
7c74ade1 13437 dev_priv->num_shared_dpll = 2;
ee7b9f93 13438
e72f9fbf 13439 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13440 dev_priv->shared_dplls[i].id = i;
13441 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13442 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13443 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13444 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13445 dev_priv->shared_dplls[i].get_hw_state =
13446 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13447 }
13448}
13449
7c74ade1
DV		 13450static void intel_shared_dpll_init(struct drm_device *dev)
13451{
e7b903d2 13452 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13453
b6283055
VS		 13454 intel_update_cdclk(dev);
13455
9cd86933
DV		 13456 if (HAS_DDI(dev))
13457 intel_ddi_pll_init(dev);
13458 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13459 ibx_pch_dpll_init(dev);
13460 else
13461 dev_priv->num_shared_dpll = 0;
13462
13463 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13464}
13465
6beb8c23
MR		 13466/**
13467 * intel_prepare_plane_fb - Prepare fb for usage on plane
13468 * @plane: drm plane to prepare for
13469 * @fb: framebuffer to prepare for presentation
13470 *
13471 * Prepares a framebuffer for usage on a display plane. Generally this
13472 * involves pinning the underlying object and updating the frontbuffer tracking
13473 * bits. Some older platforms need special physical address handling for
13474 * cursor planes.
13475 *
13476 * Returns 0 on success, negative error code on failure.
13477 */
13478int
13479intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13480 struct drm_framebuffer *fb,
13481 const struct drm_plane_state *new_state)
465c120c
MR		 13482{
13483 struct drm_device *dev = plane->dev;
6beb8c23 13484 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13485 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13486 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13487 int ret = 0;
465c120c 13488
ea2c67bb 13489 if (!obj)
465c120c
MR		 13490 return 0;
13491
6beb8c23 13492 mutex_lock(&dev->struct_mutex);
465c120c 13493
6beb8c23
MR		 13494 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13495 INTEL_INFO(dev)->cursor_needs_physical) {
13496 int align = IS_I830(dev) ? 16 * 1024 : 256;
13497 ret = i915_gem_object_attach_phys(obj, align);
13498 if (ret)
13499 DRM_DEBUG_KMS("failed to attach phys object\n");
13500 } else {
91af127f 13501 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13502 }
465c120c 13503
6beb8c23 13504 if (ret == 0)
a9ff8714 13505 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13506
4c34574f 13507 mutex_unlock(&dev->struct_mutex);
465c120c 13508
6beb8c23
MR		 13509 return ret;
13510}
13511
38f3ce3a
MR		 13512/**
13513 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13514 * @plane: drm plane to clean up for
13515 * @fb: old framebuffer that was on plane
13516 *
13517 * Cleans up a framebuffer that has just been removed from a plane.
13518 */
13519void
13520intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13521 struct drm_framebuffer *fb,
13522 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13523{
13524 struct drm_device *dev = plane->dev;
13525 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13526
13527 if (WARN_ON(!obj))
13528 return;
13529
13530 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13531 !INTEL_INFO(dev)->cursor_needs_physical) {
13532 mutex_lock(&dev->struct_mutex);
82bc3b2d 13533 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13534 mutex_unlock(&dev->struct_mutex);
13535 }
465c120c
MR		 13536}
13537
6156a456
CK		 13538int
13539skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13540{
13541 int max_scale;
13542 struct drm_device *dev;
13543 struct drm_i915_private *dev_priv;
13544 int crtc_clock, cdclk;
13545
13546 if (!intel_crtc || !crtc_state)
13547 return DRM_PLANE_HELPER_NO_SCALING;
13548
13549 dev = intel_crtc->base.dev;
13550 dev_priv = dev->dev_private;
13551 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13552 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13553
13554 if (!crtc_clock || !cdclk)
13555 return DRM_PLANE_HELPER_NO_SCALING;
13556
13557 /*
13558 * skl max scale is lower of:
13559 * close to 3 but not 3, -1 is for that purpose
13560 * or
13561 * cdclk/crtc_clock
13562 */
13563 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13564
13565 return max_scale;
13566}
13567
465c120c 13568static int
3c692a41 13569intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13570 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13571 struct intel_plane_state *state)
13572{
2b875c22
MR		 13573 struct drm_crtc *crtc = state->base.crtc;
13574 struct drm_framebuffer *fb = state->base.fb;
6156a456 13575 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13576 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13577 bool can_position = false;
465c120c 13578
061e4b8d
ML		 13579 /* use scaler when colorkey is not required */
13580 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13581 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13582 min_scale = 1;
13583 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13584 can_position = true;
6156a456 13585 }
d8106366 13586
061e4b8d
ML		 13587 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13588 &state->dst, &state->clip,
da20eabd
ML		 13589 min_scale, max_scale,
13590 can_position, true,
13591 &state->visible);
14af293f
GP		 13592}
13593
13594static void
13595intel_commit_primary_plane(struct drm_plane *plane,
13596 struct intel_plane_state *state)
13597{
2b875c22
MR		 13598 struct drm_crtc *crtc = state->base.crtc;
13599 struct drm_framebuffer *fb = state->base.fb;
13600 struct drm_device *dev = plane->dev;
14af293f 13601 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13602 struct intel_crtc *intel_crtc;
14af293f
GP		 13603 struct drm_rect *src = &state->src;
13604
ea2c67bb
MR		 13605 crtc = crtc ? crtc : plane->crtc;
13606 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13607
13608 plane->fb = fb;
9dc806fc
MR		 13609 crtc->x = src->x1 >> 16;
13610 crtc->y = src->y1 >> 16;
ccc759dc 13611
a539205a 13612 if (!crtc->state->active)
302d19ac 13613 return;
465c120c 13614
302d19ac
ML		 13615 if (state->visible)
13616 /* FIXME: kill this fastboot hack */
13617 intel_update_pipe_size(intel_crtc);
13618
13619 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13620}
13621
a8ad0d8e
ML		 13622static void
13623intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13624 struct drm_crtc *crtc)
a8ad0d8e
ML		 13625{
13626 struct drm_device *dev = plane->dev;
13627 struct drm_i915_private *dev_priv = dev->dev_private;
13628
a8ad0d8e
ML		 13629 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13630}
13631
32b7eeec 13632static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13633{
32b7eeec 13634 struct drm_device *dev = crtc->dev;
140fd38d 13635 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13637
a539205a
ML		 13638 if (!needs_modeset(crtc->state))
13639 intel_pre_plane_update(intel_crtc);
3c692a41 13640
f015c551 13641 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13642 intel_update_watermarks(crtc);
3c692a41 13643
32b7eeec 13644 intel_runtime_pm_get(dev_priv);
3c692a41 13645
c34c9ee4 13646 /* Perform vblank evasion around commit operation */
a539205a 13647 if (crtc->state->active)
c34c9ee4
MR		 13648 intel_crtc->atomic.evade =
13649 intel_pipe_update_start(intel_crtc,
13650 &intel_crtc->atomic.start_vbl_count);
0583236e
ML		 13651
13652 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13653 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13654}
13655
13656static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13657{
13658 struct drm_device *dev = crtc->dev;
13659 struct drm_i915_private *dev_priv = dev->dev_private;
13660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13661
c34c9ee4
MR		 13662 if (intel_crtc->atomic.evade)
13663 intel_pipe_update_end(intel_crtc,
13664 intel_crtc->atomic.start_vbl_count);
3c692a41 13665
140fd38d 13666 intel_runtime_pm_put(dev_priv);
3c692a41 13667
ac21b225 13668 intel_post_plane_update(intel_crtc);
3c692a41
GP		 13669}
13670
cf4c7c12 13671/**
4a3b8769
MR		 13672 * intel_plane_destroy - destroy a plane
13673 * @plane: plane to destroy
cf4c7c12 13674 *
4a3b8769
MR		 13675 * Common destruction function for all types of planes (primary, cursor,
13676 * sprite).
cf4c7c12 13677 */
4a3b8769 13678void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13679{
13680 struct intel_plane *intel_plane = to_intel_plane(plane);
13681 drm_plane_cleanup(plane);
13682 kfree(intel_plane);
13683}
13684
65a3fea0 13685const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13686 .update_plane = drm_atomic_helper_update_plane,
13687 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13688 .destroy = intel_plane_destroy,
c196e1d6 13689 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13690 .atomic_get_property = intel_plane_atomic_get_property,
13691 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13692 .atomic_duplicate_state = intel_plane_duplicate_state,
13693 .atomic_destroy_state = intel_plane_destroy_state,
13694
465c120c
MR		 13695};
13696
13697static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13698 int pipe)
13699{
13700 struct intel_plane *primary;
8e7d688b 13701 struct intel_plane_state *state;
465c120c
MR		 13702 const uint32_t *intel_primary_formats;
13703 int num_formats;
13704
13705 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13706 if (primary == NULL)
13707 return NULL;
13708
8e7d688b
MR		 13709 state = intel_create_plane_state(&primary->base);
13710 if (!state) {
ea2c67bb
MR		 13711 kfree(primary);
13712 return NULL;
13713 }
8e7d688b 13714 primary->base.state = &state->base;
ea2c67bb 13715
465c120c
MR		 13716 primary->can_scale = false;
13717 primary->max_downscale = 1;
6156a456
CK		 13718 if (INTEL_INFO(dev)->gen >= 9) {
13719 primary->can_scale = true;
af99ceda 13720 state->scaler_id = -1;
6156a456 13721 }
465c120c
MR		 13722 primary->pipe = pipe;
13723 primary->plane = pipe;
a9ff8714 13724 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13725 primary->check_plane = intel_check_primary_plane;
13726 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13727 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13728 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13729 primary->plane = !pipe;
13730
6c0fd451
DL		 13731 if (INTEL_INFO(dev)->gen >= 9) {
13732 intel_primary_formats = skl_primary_formats;
13733 num_formats = ARRAY_SIZE(skl_primary_formats);
13734 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13735 intel_primary_formats = i965_primary_formats;
13736 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13737 } else {
13738 intel_primary_formats = i8xx_primary_formats;
13739 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13740 }
13741
13742 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13743 &intel_plane_funcs,
465c120c
MR		 13744 intel_primary_formats, num_formats,
13745 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13746
3b7a5119
SJ		 13747 if (INTEL_INFO(dev)->gen >= 4)
13748 intel_create_rotation_property(dev, primary);
48404c1e 13749
ea2c67bb
MR		 13750 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13751
465c120c
MR		 13752 return &primary->base;
13753}
13754
3b7a5119
SJ		 13755void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13756{
13757 if (!dev->mode_config.rotation_property) {
13758 unsigned long flags = BIT(DRM_ROTATE_0) |
13759 BIT(DRM_ROTATE_180);
13760
13761 if (INTEL_INFO(dev)->gen >= 9)
13762 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13763
13764 dev->mode_config.rotation_property =
13765 drm_mode_create_rotation_property(dev, flags);
13766 }
13767 if (dev->mode_config.rotation_property)
13768 drm_object_attach_property(&plane->base.base,
13769 dev->mode_config.rotation_property,
13770 plane->base.state->rotation);
13771}
13772
3d7d6510 13773static int
852e787c 13774intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13775 struct intel_crtc_state *crtc_state,
852e787c 13776 struct intel_plane_state *state)
3d7d6510 13777{
061e4b8d 13778 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13779 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13780 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13781 unsigned stride;
13782 int ret;
3d7d6510 13783
061e4b8d
ML		 13784 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13785 &state->dst, &state->clip,
3d7d6510
MR		 13786 DRM_PLANE_HELPER_NO_SCALING,
13787 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13788 true, true, &state->visible);
757f9a3e
GP		 13789 if (ret)
13790 return ret;
13791
757f9a3e
GP		 13792 /* if we want to turn off the cursor ignore width and height */
13793 if (!obj)
da20eabd 13794 return 0;
757f9a3e 13795
757f9a3e 13796 /* Check for which cursor types we support */
061e4b8d 13797 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13798 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13799 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13800 return -EINVAL;
13801 }
13802
ea2c67bb
MR		 13803 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13804 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13805 DRM_DEBUG_KMS("buffer is too small\n");
13806 return -ENOMEM;
13807 }
13808
3a656b54 13809 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 13810 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13811 return -EINVAL;
32b7eeec
MR		 13812 }
13813
da20eabd 13814 return 0;
852e787c 13815}
3d7d6510 13816
a8ad0d8e
ML		 13817static void
13818intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13819 struct drm_crtc *crtc)
a8ad0d8e 13820{
a8ad0d8e
ML		 13821 intel_crtc_update_cursor(crtc, false);
13822}
13823
f4a2cf29 13824static void
852e787c
GP		 13825intel_commit_cursor_plane(struct drm_plane *plane,
13826 struct intel_plane_state *state)
13827{
2b875c22 13828 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13829 struct drm_device *dev = plane->dev;
13830 struct intel_crtc *intel_crtc;
2b875c22 13831 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13832 uint32_t addr;
852e787c 13833
ea2c67bb
MR		 13834 crtc = crtc ? crtc : plane->crtc;
13835 intel_crtc = to_intel_crtc(crtc);
13836
2b875c22 13837 plane->fb = state->base.fb;
ea2c67bb
MR		 13838 crtc->cursor_x = state->base.crtc_x;
13839 crtc->cursor_y = state->base.crtc_y;
13840
a912f12f
GP		 13841 if (intel_crtc->cursor_bo == obj)
13842 goto update;
4ed91096 13843
f4a2cf29 13844 if (!obj)
a912f12f 13845 addr = 0;
f4a2cf29 13846 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13847 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13848 else
a912f12f 13849 addr = obj->phys_handle->busaddr;
852e787c 13850
a912f12f
GP		 13851 intel_crtc->cursor_addr = addr;
13852 intel_crtc->cursor_bo = obj;
852e787c 13853
302d19ac 13854update:
a539205a 13855 if (crtc->state->active)
a912f12f 13856 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13857}
13858
3d7d6510
MR		 13859static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13860 int pipe)
13861{
13862 struct intel_plane *cursor;
8e7d688b 13863 struct intel_plane_state *state;
3d7d6510
MR		 13864
13865 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13866 if (cursor == NULL)
13867 return NULL;
13868
8e7d688b
MR		 13869 state = intel_create_plane_state(&cursor->base);
13870 if (!state) {
ea2c67bb
MR		 13871 kfree(cursor);
13872 return NULL;
13873 }
8e7d688b 13874 cursor->base.state = &state->base;
ea2c67bb 13875
3d7d6510
MR		 13876 cursor->can_scale = false;
13877 cursor->max_downscale = 1;
13878 cursor->pipe = pipe;
13879 cursor->plane = pipe;
a9ff8714 13880 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 13881 cursor->check_plane = intel_check_cursor_plane;
13882 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13883 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13884
13885 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13886 &intel_plane_funcs,
3d7d6510
MR		 13887 intel_cursor_formats,
13888 ARRAY_SIZE(intel_cursor_formats),
13889 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13890
13891 if (INTEL_INFO(dev)->gen >= 4) {
13892 if (!dev->mode_config.rotation_property)
13893 dev->mode_config.rotation_property =
13894 drm_mode_create_rotation_property(dev,
13895 BIT(DRM_ROTATE_0) |
13896 BIT(DRM_ROTATE_180));
13897 if (dev->mode_config.rotation_property)
13898 drm_object_attach_property(&cursor->base.base,
13899 dev->mode_config.rotation_property,
8e7d688b 13900 state->base.rotation);
4398ad45
VS		 13901 }
13902
af99ceda
CK		 13903 if (INTEL_INFO(dev)->gen >=9)
13904 state->scaler_id = -1;
13905
ea2c67bb
MR		 13906 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13907
3d7d6510
MR		 13908 return &cursor->base;
13909}
13910
549e2bfb
CK		 13911static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13912 struct intel_crtc_state *crtc_state)
13913{
13914 int i;
13915 struct intel_scaler *intel_scaler;
13916 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13917
13918 for (i = 0; i < intel_crtc->num_scalers; i++) {
13919 intel_scaler = &scaler_state->scalers[i];
13920 intel_scaler->in_use = 0;
549e2bfb
CK		 13921 intel_scaler->mode = PS_SCALER_MODE_DYN;
13922 }
13923
13924 scaler_state->scaler_id = -1;
13925}
13926
b358d0a6 13927static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13928{
fbee40df 13929 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13930 struct intel_crtc *intel_crtc;
f5de6e07 13931 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13932 struct drm_plane *primary = NULL;
13933 struct drm_plane *cursor = NULL;
465c120c 13934 int i, ret;
79e53945 13935
955382f3 13936 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13937 if (intel_crtc == NULL)
13938 return;
13939
f5de6e07
ACO		 13940 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13941 if (!crtc_state)
13942 goto fail;
550acefd
ACO		 13943 intel_crtc->config = crtc_state;
13944 intel_crtc->base.state = &crtc_state->base;
07878248 13945 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13946
549e2bfb
CK		 13947 /* initialize shared scalers */
13948 if (INTEL_INFO(dev)->gen >= 9) {
13949 if (pipe == PIPE_C)
13950 intel_crtc->num_scalers = 1;
13951 else
13952 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13953
13954 skl_init_scalers(dev, intel_crtc, crtc_state);
13955 }
13956
465c120c 13957 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13958 if (!primary)
13959 goto fail;
13960
13961 cursor = intel_cursor_plane_create(dev, pipe);
13962 if (!cursor)
13963 goto fail;
13964
465c120c 13965 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13966 cursor, &intel_crtc_funcs);
13967 if (ret)
13968 goto fail;
79e53945
JB		 13969
13970 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13971 for (i = 0; i < 256; i++) {
13972 intel_crtc->lut_r[i] = i;
13973 intel_crtc->lut_g[i] = i;
13974 intel_crtc->lut_b[i] = i;
13975 }
13976
1f1c2e24
VS		 13977 /*
13978 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13979 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13980 */
80824003
JB		 13981 intel_crtc->pipe = pipe;
13982 intel_crtc->plane = pipe;
3a77c4c4 13983 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13984 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13985 intel_crtc->plane = !pipe;
80824003
JB		 13986 }
13987
4b0e333e
CW		 13988 intel_crtc->cursor_base = ~0;
13989 intel_crtc->cursor_cntl = ~0;
dc41c154 13990 intel_crtc->cursor_size = ~0;
8d7849db 13991
852eb00d
VS		 13992 intel_crtc->wm.cxsr_allowed = true;
13993
22fd0fab
JB		 13994 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13995 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13996 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13997 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13998
79e53945 13999 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14000
14001 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14002 return;
14003
14004fail:
14005 if (primary)
14006 drm_plane_cleanup(primary);
14007 if (cursor)
14008 drm_plane_cleanup(cursor);
f5de6e07 14009 kfree(crtc_state);
3d7d6510 14010 kfree(intel_crtc);
79e53945
JB		 14011}
14012
752aa88a
JB		 14013enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14014{
14015 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14016 struct drm_device *dev = connector->base.dev;
752aa88a 14017
51fd371b 14018 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14019
d3babd3f 14020 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14021 return INVALID_PIPE;
14022
14023 return to_intel_crtc(encoder->crtc)->pipe;
14024}
14025
08d7b3d1 14026int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14027 struct drm_file *file)
08d7b3d1 14028{
08d7b3d1 14029 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14030 struct drm_crtc *drmmode_crtc;
c05422d5 14031 struct intel_crtc *crtc;
08d7b3d1 14032
7707e653 14033 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14034
7707e653 14035 if (!drmmode_crtc) {
08d7b3d1 14036 DRM_ERROR("no such CRTC id\n");
3f2c2057 14037 return -ENOENT;
08d7b3d1
CW		 14038 }
14039
7707e653 14040 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14041 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14042
c05422d5 14043 return 0;
08d7b3d1
CW		 14044}
14045
66a9278e 14046static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14047{
66a9278e
DV		 14048 struct drm_device *dev = encoder->base.dev;
14049 struct intel_encoder *source_encoder;
79e53945 14050 int index_mask = 0;
79e53945
JB		 14051 int entry = 0;
14052
b2784e15 14053 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14054 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14055 index_mask |= (1 << entry);
14056
79e53945
JB		 14057 entry++;
14058 }
4ef69c7a 14059
79e53945
JB		 14060 return index_mask;
14061}
14062
4d302442
CW		 14063static bool has_edp_a(struct drm_device *dev)
14064{
14065 struct drm_i915_private *dev_priv = dev->dev_private;
14066
14067 if (!IS_MOBILE(dev))
14068 return false;
14069
14070 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14071 return false;
14072
e3589908 14073 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14074 return false;
14075
14076 return true;
14077}
14078
84b4e042
JB		 14079static bool intel_crt_present(struct drm_device *dev)
14080{
14081 struct drm_i915_private *dev_priv = dev->dev_private;
14082
884497ed
DL		 14083 if (INTEL_INFO(dev)->gen >= 9)
14084 return false;
14085
cf404ce4 14086 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14087 return false;
14088
14089 if (IS_CHERRYVIEW(dev))
14090 return false;
14091
14092 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14093 return false;
14094
14095 return true;
14096}
14097
79e53945
JB		 14098static void intel_setup_outputs(struct drm_device *dev)
14099{
725e30ad 14100 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14101 struct intel_encoder *encoder;
cb0953d7 14102 bool dpd_is_edp = false;
79e53945 14103
c9093354 14104 intel_lvds_init(dev);
79e53945 14105
84b4e042 14106 if (intel_crt_present(dev))
79935fca 14107 intel_crt_init(dev);
cb0953d7 14108
c776eb2e
VK		 14109 if (IS_BROXTON(dev)) {
14110 /*
14111 * FIXME: Broxton doesn't support port detection via the
14112 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14113 * detect the ports.
14114 */
14115 intel_ddi_init(dev, PORT_A);
14116 intel_ddi_init(dev, PORT_B);
14117 intel_ddi_init(dev, PORT_C);
14118 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14119 int found;
14120
de31facd
JB		 14121 /*
14122 * Haswell uses DDI functions to detect digital outputs.
14123 * On SKL pre-D0 the strap isn't connected, so we assume
14124 * it's there.
14125 */
0e72a5b5 14126 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14127 /* WaIgnoreDDIAStrap: skl */
14128 if (found ||
14129 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14130 intel_ddi_init(dev, PORT_A);
14131
14132 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14133 * register */
14134 found = I915_READ(SFUSE_STRAP);
14135
14136 if (found & SFUSE_STRAP_DDIB_DETECTED)
14137 intel_ddi_init(dev, PORT_B);
14138 if (found & SFUSE_STRAP_DDIC_DETECTED)
14139 intel_ddi_init(dev, PORT_C);
14140 if (found & SFUSE_STRAP_DDID_DETECTED)
14141 intel_ddi_init(dev, PORT_D);
14142 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14143 int found;
5d8a7752 14144 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14145
14146 if (has_edp_a(dev))
14147 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14148
dc0fa718 14149 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14150 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14151 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14152 if (!found)
e2debe91 14153 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14154 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14155 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14156 }
14157
dc0fa718 14158 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14159 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14160
dc0fa718 14161 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14162 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14163
5eb08b69 14164 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14165 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14166
270b3042 14167 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14168 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14169 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14170 /*
14171 * The DP_DETECTED bit is the latched state of the DDC
14172 * SDA pin at boot. However since eDP doesn't require DDC
14173 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14174 * eDP ports may have been muxed to an alternate function.
14175 * Thus we can't rely on the DP_DETECTED bit alone to detect
14176 * eDP ports. Consult the VBT as well as DP_DETECTED to
14177 * detect eDP ports.
14178 */
d2182a66
VS		 14179 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14180 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14181 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14182 PORT_B);
e17ac6db
VS		 14183 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14184 intel_dp_is_edp(dev, PORT_B))
14185 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14186
d2182a66
VS		 14187 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14188 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14189 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14190 PORT_C);
e17ac6db
VS		 14191 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14192 intel_dp_is_edp(dev, PORT_C))
14193 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14194
9418c1f1 14195 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14196 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14197 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14198 PORT_D);
e17ac6db
VS		 14199 /* eDP not supported on port D, so don't check VBT */
14200 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14201 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14202 }
14203
3cfca973 14204 intel_dsi_init(dev);
09da55dc 14205 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14206 bool found = false;
7d57382e 14207
e2debe91 14208 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14209 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14210 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14211 if (!found && IS_G4X(dev)) {
b01f2c3a 14212 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14213 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14214 }
27185ae1 14215
3fec3d2f 14216 if (!found && IS_G4X(dev))
ab9d7c30 14217 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14218 }
13520b05
KH		 14219
14220 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14221
e2debe91 14222 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14223 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14224 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14225 }
27185ae1 14226
e2debe91 14227 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14228
3fec3d2f 14229 if (IS_G4X(dev)) {
b01f2c3a 14230 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14231 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14232 }
3fec3d2f 14233 if (IS_G4X(dev))
ab9d7c30 14234 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14235 }
27185ae1 14236
3fec3d2f 14237 if (IS_G4X(dev) &&
e7281eab 14238 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14239 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14240 } else if (IS_GEN2(dev))
79e53945
JB		 14241 intel_dvo_init(dev);
14242
103a196f 14243 if (SUPPORTS_TV(dev))
79e53945
JB		 14244 intel_tv_init(dev);
14245
0bc12bcb 14246 intel_psr_init(dev);
7c8f8a70 14247
b2784e15 14248 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14249 encoder->base.possible_crtcs = encoder->crtc_mask;
14250 encoder->base.possible_clones =
66a9278e 14251 intel_encoder_clones(encoder);
79e53945 14252 }
47356eb6 14253
dde86e2d 14254 intel_init_pch_refclk(dev);
270b3042
DV		 14255
14256 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14257}
14258
14259static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14260{
60a5ca01 14261 struct drm_device *dev = fb->dev;
79e53945 14262 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14263
ef2d633e 14264 drm_framebuffer_cleanup(fb);
60a5ca01 14265 mutex_lock(&dev->struct_mutex);
ef2d633e 14266 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14267 drm_gem_object_unreference(&intel_fb->obj->base);
14268 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14269 kfree(intel_fb);
14270}
14271
14272static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14273 struct drm_file *file,
79e53945
JB		 14274 unsigned int *handle)
14275{
14276 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14277 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14278
05394f39 14279 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14280}
14281
86c98588
RV		 14282static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14283 struct drm_file *file,
14284 unsigned flags, unsigned color,
14285 struct drm_clip_rect *clips,
14286 unsigned num_clips)
14287{
14288 struct drm_device *dev = fb->dev;
14289 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14290 struct drm_i915_gem_object *obj = intel_fb->obj;
14291
14292 mutex_lock(&dev->struct_mutex);
14293 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
14294 mutex_unlock(&dev->struct_mutex);
14295
14296 return 0;
14297}
14298
79e53945
JB		 14299static const struct drm_framebuffer_funcs intel_fb_funcs = {
14300 .destroy = intel_user_framebuffer_destroy,
14301 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14302 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14303};
14304
b321803d
DL		 14305static
14306u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14307 uint32_t pixel_format)
14308{
14309 u32 gen = INTEL_INFO(dev)->gen;
14310
14311 if (gen >= 9) {
14312 /* "The stride in bytes must not exceed the of the size of 8K
14313 * pixels and 32K bytes."
14314 */
14315 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14316 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14317 return 32*1024;
14318 } else if (gen >= 4) {
14319 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14320 return 16*1024;
14321 else
14322 return 32*1024;
14323 } else if (gen >= 3) {
14324 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14325 return 8*1024;
14326 else
14327 return 16*1024;
14328 } else {
14329 /* XXX DSPC is limited to 4k tiled */
14330 return 8*1024;
14331 }
14332}
14333
b5ea642a
DV		 14334static int intel_framebuffer_init(struct drm_device *dev,
14335 struct intel_framebuffer *intel_fb,
14336 struct drm_mode_fb_cmd2 *mode_cmd,
14337 struct drm_i915_gem_object *obj)
79e53945 14338{
6761dd31 14339 unsigned int aligned_height;
79e53945 14340 int ret;
b321803d 14341 u32 pitch_limit, stride_alignment;
79e53945 14342
dd4916c5
DV		 14343 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14344
2a80eada
DV		 14345 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14346 /* Enforce that fb modifier and tiling mode match, but only for
14347 * X-tiled. This is needed for FBC. */
14348 if (!!(obj->tiling_mode == I915_TILING_X) !=
14349 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14350 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14351 return -EINVAL;
14352 }
14353 } else {
14354 if (obj->tiling_mode == I915_TILING_X)
14355 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14356 else if (obj->tiling_mode == I915_TILING_Y) {
14357 DRM_DEBUG("No Y tiling for legacy addfb\n");
14358 return -EINVAL;
14359 }
14360 }
14361
9a8f0a12
TU		 14362 /* Passed in modifier sanity checking. */
14363 switch (mode_cmd->modifier[0]) {
14364 case I915_FORMAT_MOD_Y_TILED:
14365 case I915_FORMAT_MOD_Yf_TILED:
14366 if (INTEL_INFO(dev)->gen < 9) {
14367 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14368 mode_cmd->modifier[0]);
14369 return -EINVAL;
14370 }
14371 case DRM_FORMAT_MOD_NONE:
14372 case I915_FORMAT_MOD_X_TILED:
14373 break;
14374 default:
c0f40428
JB		 14375 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14376 mode_cmd->modifier[0]);
57cd6508 14377 return -EINVAL;
c16ed4be 14378 }
57cd6508 14379
b321803d
DL		 14380 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14381 mode_cmd->pixel_format);
14382 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14383 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14384 mode_cmd->pitches[0], stride_alignment);
57cd6508 14385 return -EINVAL;
c16ed4be 14386 }
57cd6508 14387
b321803d
DL		 14388 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14389 mode_cmd->pixel_format);
a35cdaa0 14390 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14391 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14392 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14393 "tiled" : "linear",
a35cdaa0 14394 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14395 return -EINVAL;
c16ed4be 14396 }
5d7bd705 14397
2a80eada 14398 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14399 mode_cmd->pitches[0] != obj->stride) {
14400 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14401 mode_cmd->pitches[0], obj->stride);
5d7bd705 14402 return -EINVAL;
c16ed4be 14403 }
5d7bd705 14404
57779d06 14405 /* Reject formats not supported by any plane early. */
308e5bcb 14406 switch (mode_cmd->pixel_format) {
57779d06 14407 case DRM_FORMAT_C8:
04b3924d
VS		 14408 case DRM_FORMAT_RGB565:
14409 case DRM_FORMAT_XRGB8888:
14410 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14411 break;
14412 case DRM_FORMAT_XRGB1555:
c16ed4be 14413 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14414 DRM_DEBUG("unsupported pixel format: %s\n",
14415 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14416 return -EINVAL;
c16ed4be 14417 }
57779d06 14418 break;
57779d06 14419 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14420 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14421 DRM_DEBUG("unsupported pixel format: %s\n",
14422 drm_get_format_name(mode_cmd->pixel_format));
14423 return -EINVAL;
14424 }
14425 break;
14426 case DRM_FORMAT_XBGR8888:
04b3924d 14427 case DRM_FORMAT_XRGB2101010:
57779d06 14428 case DRM_FORMAT_XBGR2101010:
c16ed4be 14429 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14430 DRM_DEBUG("unsupported pixel format: %s\n",
14431 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14432 return -EINVAL;
c16ed4be 14433 }
b5626747 14434 break;
7531208b
DL		 14435 case DRM_FORMAT_ABGR2101010:
14436 if (!IS_VALLEYVIEW(dev)) {
14437 DRM_DEBUG("unsupported pixel format: %s\n",
14438 drm_get_format_name(mode_cmd->pixel_format));
14439 return -EINVAL;
14440 }
14441 break;
04b3924d
VS		 14442 case DRM_FORMAT_YUYV:
14443 case DRM_FORMAT_UYVY:
14444 case DRM_FORMAT_YVYU:
14445 case DRM_FORMAT_VYUY:
c16ed4be 14446 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14447 DRM_DEBUG("unsupported pixel format: %s\n",
14448 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14449 return -EINVAL;
c16ed4be 14450 }
57cd6508
CW		 14451 break;
14452 default:
4ee62c76
VS		 14453 DRM_DEBUG("unsupported pixel format: %s\n",
14454 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14455 return -EINVAL;
14456 }
14457
90f9a336
VS		 14458 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14459 if (mode_cmd->offsets[0] != 0)
14460 return -EINVAL;
14461
ec2c981e 14462 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14463 mode_cmd->pixel_format,
14464 mode_cmd->modifier[0]);
53155c0a
DV		 14465 /* FIXME drm helper for size checks (especially planar formats)? */
14466 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14467 return -EINVAL;
14468
c7d73f6a
DV		 14469 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14470 intel_fb->obj = obj;
80075d49 14471 intel_fb->obj->framebuffer_references++;
c7d73f6a 14472
79e53945
JB		 14473 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14474 if (ret) {
14475 DRM_ERROR("framebuffer init failed %d\n", ret);
14476 return ret;
14477 }
14478
79e53945
JB		 14479 return 0;
14480}
14481
79e53945
JB		 14482static struct drm_framebuffer *
14483intel_user_framebuffer_create(struct drm_device *dev,
14484 struct drm_file *filp,
308e5bcb 14485 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14486{
05394f39 14487 struct drm_i915_gem_object *obj;
79e53945 14488
308e5bcb
JB		 14489 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14490 mode_cmd->handles[0]));
c8725226 14491 if (&obj->base == NULL)
cce13ff7 14492 return ERR_PTR(-ENOENT);
79e53945 14493
d2dff872 14494 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14495}
14496
4520f53a 14497#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14498static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14499{
14500}
14501#endif
14502
79e53945 14503static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14504 .fb_create = intel_user_framebuffer_create,
0632fef6 14505 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14506 .atomic_check = intel_atomic_check,
14507 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14508 .atomic_state_alloc = intel_atomic_state_alloc,
14509 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14510};
14511
e70236a8
JB		 14512/* Set up chip specific display functions */
14513static void intel_init_display(struct drm_device *dev)
14514{
14515 struct drm_i915_private *dev_priv = dev->dev_private;
14516
ee9300bb
DV		 14517 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14518 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14519 else if (IS_CHERRYVIEW(dev))
14520 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14521 else if (IS_VALLEYVIEW(dev))
14522 dev_priv->display.find_dpll = vlv_find_best_dpll;
14523 else if (IS_PINEVIEW(dev))
14524 dev_priv->display.find_dpll = pnv_find_best_dpll;
14525 else
14526 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14527
bc8d7dff
DL		 14528 if (INTEL_INFO(dev)->gen >= 9) {
14529 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14530 dev_priv->display.get_initial_plane_config =
14531 skylake_get_initial_plane_config;
bc8d7dff
DL		 14532 dev_priv->display.crtc_compute_clock =
14533 haswell_crtc_compute_clock;
14534 dev_priv->display.crtc_enable = haswell_crtc_enable;
14535 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14536 dev_priv->display.update_primary_plane =
14537 skylake_update_primary_plane;
14538 } else if (HAS_DDI(dev)) {
0e8ffe1b 14539 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14540 dev_priv->display.get_initial_plane_config =
14541 ironlake_get_initial_plane_config;
797d0259
ACO		 14542 dev_priv->display.crtc_compute_clock =
14543 haswell_crtc_compute_clock;
4f771f10
PZ		 14544 dev_priv->display.crtc_enable = haswell_crtc_enable;
14545 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14546 dev_priv->display.update_primary_plane =
14547 ironlake_update_primary_plane;
09b4ddf9 14548 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14549 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14550 dev_priv->display.get_initial_plane_config =
14551 ironlake_get_initial_plane_config;
3fb37703
ACO		 14552 dev_priv->display.crtc_compute_clock =
14553 ironlake_crtc_compute_clock;
76e5a89c
DV		 14554 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14555 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14556 dev_priv->display.update_primary_plane =
14557 ironlake_update_primary_plane;
89b667f8
JB		 14558 } else if (IS_VALLEYVIEW(dev)) {
14559 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14560 dev_priv->display.get_initial_plane_config =
14561 i9xx_get_initial_plane_config;
d6dfee7a 14562 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14563 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14564 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14565 dev_priv->display.update_primary_plane =
14566 i9xx_update_primary_plane;
f564048e 14567 } else {
0e8ffe1b 14568 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14569 dev_priv->display.get_initial_plane_config =
14570 i9xx_get_initial_plane_config;
d6dfee7a 14571 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14572 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14573 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14574 dev_priv->display.update_primary_plane =
14575 i9xx_update_primary_plane;
f564048e 14576 }
e70236a8 14577
e70236a8 14578 /* Returns the core display clock speed */
1652d19e
VS		 14579 if (IS_SKYLAKE(dev))
14580 dev_priv->display.get_display_clock_speed =
14581 skylake_get_display_clock_speed;
acd3f3d3
BP		 14582 else if (IS_BROXTON(dev))
14583 dev_priv->display.get_display_clock_speed =
14584 broxton_get_display_clock_speed;
1652d19e
VS		 14585 else if (IS_BROADWELL(dev))
14586 dev_priv->display.get_display_clock_speed =
14587 broadwell_get_display_clock_speed;
14588 else if (IS_HASWELL(dev))
14589 dev_priv->display.get_display_clock_speed =
14590 haswell_get_display_clock_speed;
14591 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14592 dev_priv->display.get_display_clock_speed =
14593 valleyview_get_display_clock_speed;
b37a6434
VS		 14594 else if (IS_GEN5(dev))
14595 dev_priv->display.get_display_clock_speed =
14596 ilk_get_display_clock_speed;
a7c66cd8 14597 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14598 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14599 dev_priv->display.get_display_clock_speed =
14600 i945_get_display_clock_speed;
34edce2f
VS		 14601 else if (IS_GM45(dev))
14602 dev_priv->display.get_display_clock_speed =
14603 gm45_get_display_clock_speed;
14604 else if (IS_CRESTLINE(dev))
14605 dev_priv->display.get_display_clock_speed =
14606 i965gm_get_display_clock_speed;
14607 else if (IS_PINEVIEW(dev))
14608 dev_priv->display.get_display_clock_speed =
14609 pnv_get_display_clock_speed;
14610 else if (IS_G33(dev) || IS_G4X(dev))
14611 dev_priv->display.get_display_clock_speed =
14612 g33_get_display_clock_speed;
e70236a8
JB		 14613 else if (IS_I915G(dev))
14614 dev_priv->display.get_display_clock_speed =
14615 i915_get_display_clock_speed;
257a7ffc 14616 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14617 dev_priv->display.get_display_clock_speed =
14618 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14619 else if (IS_PINEVIEW(dev))
14620 dev_priv->display.get_display_clock_speed =
14621 pnv_get_display_clock_speed;
e70236a8
JB		 14622 else if (IS_I915GM(dev))
14623 dev_priv->display.get_display_clock_speed =
14624 i915gm_get_display_clock_speed;
14625 else if (IS_I865G(dev))
14626 dev_priv->display.get_display_clock_speed =
14627 i865_get_display_clock_speed;
f0f8a9ce 14628 else if (IS_I85X(dev))
e70236a8 14629 dev_priv->display.get_display_clock_speed =
1b1d2716 14630 i85x_get_display_clock_speed;
623e01e5
VS		 14631 else { /* 830 */
14632 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14633 dev_priv->display.get_display_clock_speed =
14634 i830_get_display_clock_speed;
623e01e5 14635 }
e70236a8 14636
7c10a2b5 14637 if (IS_GEN5(dev)) {
3bb11b53 14638 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14639 } else if (IS_GEN6(dev)) {
14640 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14641 } else if (IS_IVYBRIDGE(dev)) {
14642 /* FIXME: detect B0+ stepping and use auto training */
14643 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14644 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14645 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14646 if (IS_BROADWELL(dev)) {
14647 dev_priv->display.modeset_commit_cdclk =
14648 broadwell_modeset_commit_cdclk;
14649 dev_priv->display.modeset_calc_cdclk =
14650 broadwell_modeset_calc_cdclk;
14651 }
30a970c6 14652 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14653 dev_priv->display.modeset_commit_cdclk =
14654 valleyview_modeset_commit_cdclk;
14655 dev_priv->display.modeset_calc_cdclk =
14656 valleyview_modeset_calc_cdclk;
f8437dd1 14657 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14658 dev_priv->display.modeset_commit_cdclk =
14659 broxton_modeset_commit_cdclk;
14660 dev_priv->display.modeset_calc_cdclk =
14661 broxton_modeset_calc_cdclk;
e70236a8 14662 }
8c9f3aaf 14663
8c9f3aaf
JB		 14664 switch (INTEL_INFO(dev)->gen) {
14665 case 2:
14666 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14667 break;
14668
14669 case 3:
14670 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14671 break;
14672
14673 case 4:
14674 case 5:
14675 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14676 break;
14677
14678 case 6:
14679 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14680 break;
7c9017e5 14681 case 7:
4e0bbc31 14682 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14683 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14684 break;
830c81db 14685 case 9:
ba343e02
TU		 14686 /* Drop through - unsupported since execlist only. */
14687 default:
14688 /* Default just returns -ENODEV to indicate unsupported */
14689 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14690 }
7bd688cd
JN		 14691
14692 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14693
14694 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14695}
14696
b690e96c
JB		 14697/*
14698 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14699 * resume, or other times. This quirk makes sure that's the case for
14700 * affected systems.
14701 */
0206e353 14702static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14703{
14704 struct drm_i915_private *dev_priv = dev->dev_private;
14705
14706 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14707 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14708}
14709
b6b5d049
VS		 14710static void quirk_pipeb_force(struct drm_device *dev)
14711{
14712 struct drm_i915_private *dev_priv = dev->dev_private;
14713
14714 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14715 DRM_INFO("applying pipe b force quirk\n");
14716}
14717
435793df
KP		 14718/*
14719 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14720 */
14721static void quirk_ssc_force_disable(struct drm_device *dev)
14722{
14723 struct drm_i915_private *dev_priv = dev->dev_private;
14724 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14725 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14726}
14727
4dca20ef 14728/*
5a15ab5b
CE		 14729 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14730 * brightness value
4dca20ef
CE		 14731 */
14732static void quirk_invert_brightness(struct drm_device *dev)
14733{
14734 struct drm_i915_private *dev_priv = dev->dev_private;
14735 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14736 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14737}
14738
9c72cc6f
SD		 14739/* Some VBT's incorrectly indicate no backlight is present */
14740static void quirk_backlight_present(struct drm_device *dev)
14741{
14742 struct drm_i915_private *dev_priv = dev->dev_private;
14743 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14744 DRM_INFO("applying backlight present quirk\n");
14745}
14746
b690e96c
JB		 14747struct intel_quirk {
14748 int device;
14749 int subsystem_vendor;
14750 int subsystem_device;
14751 void (*hook)(struct drm_device *dev);
14752};
14753
5f85f176
EE		 14754/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14755struct intel_dmi_quirk {
14756 void (*hook)(struct drm_device *dev);
14757 const struct dmi_system_id (*dmi_id_list)[];
14758};
14759
14760static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14761{
14762 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14763 return 1;
14764}
14765
14766static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14767 {
14768 .dmi_id_list = &(const struct dmi_system_id[]) {
14769 {
14770 .callback = intel_dmi_reverse_brightness,
14771 .ident = "NCR Corporation",
14772 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14773 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14774 },
14775 },
14776 { } /* terminating entry */
14777 },
14778 .hook = quirk_invert_brightness,
14779 },
14780};
14781
c43b5634 14782static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14783 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14784 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14785
b690e96c
JB		 14786 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14787 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14788
5f080c0f
VS		 14789 /* 830 needs to leave pipe A & dpll A up */
14790 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14791
b6b5d049
VS		 14792 /* 830 needs to leave pipe B & dpll B up */
14793 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14794
435793df
KP		 14795 /* Lenovo U160 cannot use SSC on LVDS */
14796 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14797
14798 /* Sony Vaio Y cannot use SSC on LVDS */
14799 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14800
be505f64
AH		 14801 /* Acer Aspire 5734Z must invert backlight brightness */
14802 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14803
14804 /* Acer/eMachines G725 */
14805 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14806
14807 /* Acer/eMachines e725 */
14808 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14809
14810 /* Acer/Packard Bell NCL20 */
14811 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14812
14813 /* Acer Aspire 4736Z */
14814 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14815
14816 /* Acer Aspire 5336 */
14817 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14818
14819 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14820 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14821
dfb3d47b
SD		 14822 /* Acer C720 Chromebook (Core i3 4005U) */
14823 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14824
b2a9601c 14825 /* Apple Macbook 2,1 (Core 2 T7400) */
14826 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14827
d4967d8c
SD		 14828 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14829 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14830
14831 /* HP Chromebook 14 (Celeron 2955U) */
14832 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14833
14834 /* Dell Chromebook 11 */
14835 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14836};
14837
14838static void intel_init_quirks(struct drm_device *dev)
14839{
14840 struct pci_dev *d = dev->pdev;
14841 int i;
14842
14843 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14844 struct intel_quirk *q = &intel_quirks[i];
14845
14846 if (d->device == q->device &&
14847 (d->subsystem_vendor == q->subsystem_vendor ||
14848 q->subsystem_vendor == PCI_ANY_ID) &&
14849 (d->subsystem_device == q->subsystem_device ||
14850 q->subsystem_device == PCI_ANY_ID))
14851 q->hook(dev);
14852 }
5f85f176
EE		 14853 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14854 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14855 intel_dmi_quirks[i].hook(dev);
14856 }
b690e96c
JB		 14857}
14858
9cce37f4
JB		 14859/* Disable the VGA plane that we never use */
14860static void i915_disable_vga(struct drm_device *dev)
14861{
14862 struct drm_i915_private *dev_priv = dev->dev_private;
14863 u8 sr1;
766aa1c4 14864 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14865
2b37c616 14866 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14867 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14868 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14869 sr1 = inb(VGA_SR_DATA);
14870 outb(sr1 | 1<<5, VGA_SR_DATA);
14871 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14872 udelay(300);
14873
01f5a626 14874 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14875 POSTING_READ(vga_reg);
14876}
14877
f817586c
DV		 14878void intel_modeset_init_hw(struct drm_device *dev)
14879{
b6283055 14880 intel_update_cdclk(dev);
a8f78b58 14881 intel_prepare_ddi(dev);
f817586c 14882 intel_init_clock_gating(dev);
8090c6b9 14883 intel_enable_gt_powersave(dev);
f817586c
DV		 14884}
14885
79e53945
JB		 14886void intel_modeset_init(struct drm_device *dev)
14887{
652c393a 14888 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14889 int sprite, ret;
8cc87b75 14890 enum pipe pipe;
46f297fb 14891 struct intel_crtc *crtc;
79e53945
JB		 14892
14893 drm_mode_config_init(dev);
14894
14895 dev->mode_config.min_width = 0;
14896 dev->mode_config.min_height = 0;
14897
019d96cb
DA		 14898 dev->mode_config.preferred_depth = 24;
14899 dev->mode_config.prefer_shadow = 1;
14900
25bab385
TU		 14901 dev->mode_config.allow_fb_modifiers = true;
14902
e6ecefaa 14903 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14904
b690e96c
JB		 14905 intel_init_quirks(dev);
14906
1fa61106
ED		 14907 intel_init_pm(dev);
14908
e3c74757
BW		 14909 if (INTEL_INFO(dev)->num_pipes == 0)
14910 return;
14911
e70236a8 14912 intel_init_display(dev);
7c10a2b5 14913 intel_init_audio(dev);
e70236a8 14914
a6c45cf0
CW		 14915 if (IS_GEN2(dev)) {
14916 dev->mode_config.max_width = 2048;
14917 dev->mode_config.max_height = 2048;
14918 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14919 dev->mode_config.max_width = 4096;
14920 dev->mode_config.max_height = 4096;
79e53945 14921 } else {
a6c45cf0
CW		 14922 dev->mode_config.max_width = 8192;
14923 dev->mode_config.max_height = 8192;
79e53945 14924 }
068be561 14925
dc41c154
VS		 14926 if (IS_845G(dev) || IS_I865G(dev)) {
14927 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14928 dev->mode_config.cursor_height = 1023;
14929 } else if (IS_GEN2(dev)) {
068be561
DL		 14930 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14931 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14932 } else {
14933 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14934 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14935 }
14936
5d4545ae 14937 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14938
28c97730 14939 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14940 INTEL_INFO(dev)->num_pipes,
14941 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14942
055e393f 14943 for_each_pipe(dev_priv, pipe) {
8cc87b75 14944 intel_crtc_init(dev, pipe);
3bdcfc0c 14945 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14946 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14947 if (ret)
06da8da2 14948 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14949 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14950 }
79e53945
JB		 14951 }
14952
f42bb70d
JB		 14953 intel_init_dpio(dev);
14954
e72f9fbf 14955 intel_shared_dpll_init(dev);
ee7b9f93 14956
9cce37f4
JB		 14957 /* Just disable it once at startup */
14958 i915_disable_vga(dev);
79e53945 14959 intel_setup_outputs(dev);
11be49eb
CW		 14960
14961 /* Just in case the BIOS is doing something questionable. */
7733b49b 14962 intel_fbc_disable(dev_priv);
fa9fa083 14963
6e9f798d 14964 drm_modeset_lock_all(dev);
043e9bda 14965 intel_modeset_setup_hw_state(dev);
6e9f798d 14966 drm_modeset_unlock_all(dev);
46f297fb 14967
d3fcc808 14968 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 14969 struct intel_initial_plane_config plane_config = {};
14970
46f297fb
JB		 14971 if (!crtc->active)
14972 continue;
14973
46f297fb 14974 /*
46f297fb
JB		 14975 * Note that reserving the BIOS fb up front prevents us
14976 * from stuffing other stolen allocations like the ring
14977 * on top. This prevents some ugliness at boot time, and
14978 * can even allow for smooth boot transitions if the BIOS
14979 * fb is large enough for the active pipe configuration.
14980 */
eeebeac5
ML		 14981 dev_priv->display.get_initial_plane_config(crtc,
14982 &plane_config);
14983
14984 /*
14985 * If the fb is shared between multiple heads, we'll
14986 * just get the first one.
14987 */
14988 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 14989 }
2c7111db
CW		 14990}
14991
7fad798e
DV		 14992static void intel_enable_pipe_a(struct drm_device *dev)
14993{
14994 struct intel_connector *connector;
14995 struct drm_connector *crt = NULL;
14996 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14997 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14998
14999 /* We can't just switch on the pipe A, we need to set things up with a
15000 * proper mode and output configuration. As a gross hack, enable pipe A
15001 * by enabling the load detect pipe once. */
3a3371ff 15002 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15003 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15004 crt = &connector->base;
15005 break;
15006 }
15007 }
15008
15009 if (!crt)
15010 return;
15011
208bf9fd 15012 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15013 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15014}
15015
fa555837
DV		 15016static bool
15017intel_check_plane_mapping(struct intel_crtc *crtc)
15018{
7eb552ae
BW		 15019 struct drm_device *dev = crtc->base.dev;
15020 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15021 u32 reg, val;
15022
7eb552ae 15023 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15024 return true;
15025
15026 reg = DSPCNTR(!crtc->plane);
15027 val = I915_READ(reg);
15028
15029 if ((val & DISPLAY_PLANE_ENABLE) &&
15030 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15031 return false;
15032
15033 return true;
15034}
15035
24929352
DV		 15036static void intel_sanitize_crtc(struct intel_crtc *crtc)
15037{
15038 struct drm_device *dev = crtc->base.dev;
15039 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 15040 struct intel_encoder *encoder;
fa555837 15041 u32 reg;
b17d48e2 15042 bool enable;
24929352 15043
24929352 15044 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15045 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15046 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15047
d3eaf884 15048 /* restore vblank interrupts to correct state */
9625604c 15049 drm_crtc_vblank_reset(&crtc->base);
d297e103 15050 if (crtc->active) {
3a03dfb0 15051 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
d297e103 15052 update_scanline_offset(crtc);
9625604c
DV		 15053 drm_crtc_vblank_on(&crtc->base);
15054 }
d3eaf884 15055
24929352 15056 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15057 * disable the crtc (and hence change the state) if it is wrong. Note
15058 * that gen4+ has a fixed plane -> pipe mapping. */
15059 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15060 bool plane;
15061
24929352
DV		 15062 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15063 crtc->base.base.id);
15064
15065 /* Pipe has the wrong plane attached and the plane is active.
15066 * Temporarily change the plane mapping and disable everything
15067 * ... */
15068 plane = crtc->plane;
b70709a6 15069 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15070 crtc->plane = !plane;
b17d48e2 15071 intel_crtc_disable_noatomic(&crtc->base);
24929352 15072 crtc->plane = plane;
24929352 15073 }
24929352 15074
7fad798e
DV		 15075 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15076 crtc->pipe == PIPE_A && !crtc->active) {
15077 /* BIOS forgot to enable pipe A, this mostly happens after
15078 * resume. Force-enable the pipe to fix this, the update_dpms
15079 * call below we restore the pipe to the right state, but leave
15080 * the required bits on. */
15081 intel_enable_pipe_a(dev);
15082 }
15083
24929352
DV		 15084 /* Adjust the state of the output pipe according to whether we
15085 * have active connectors/encoders. */
b17d48e2
ML		 15086 enable = false;
15087 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15088 enable |= encoder->connectors_active;
24929352 15089
b17d48e2
ML		 15090 if (!enable)
15091 intel_crtc_disable_noatomic(&crtc->base);
24929352 15092
53d9f4e9 15093 if (crtc->active != crtc->base.state->active) {
24929352
DV		 15094
15095 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15096 * functions or because of calls to intel_crtc_disable_noatomic,
15097 * or because the pipe is force-enabled due to the
24929352
DV		 15098 * pipe A quirk. */
15099 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15100 crtc->base.base.id,
83d65738 15101 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15102 crtc->active ? "enabled" : "disabled");
15103
4be40c98 15104 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 15105 crtc->base.state->active = crtc->active;
24929352
DV		 15106 crtc->base.enabled = crtc->active;
15107
15108 /* Because we only establish the connector -> encoder ->
15109 * crtc links if something is active, this means the
15110 * crtc is now deactivated. Break the links. connector
15111 * -> encoder links are only establish when things are
15112 * actually up, hence no need to break them. */
15113 WARN_ON(crtc->active);
15114
15115 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15116 WARN_ON(encoder->connectors_active);
15117 encoder->base.crtc = NULL;
15118 }
15119 }
c5ab3bc0 15120
a3ed6aad 15121 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15122 /*
15123 * We start out with underrun reporting disabled to avoid races.
15124 * For correct bookkeeping mark this on active crtcs.
15125 *
c5ab3bc0
DV		 15126 * Also on gmch platforms we dont have any hardware bits to
15127 * disable the underrun reporting. Which means we need to start
15128 * out with underrun reporting disabled also on inactive pipes,
15129 * since otherwise we'll complain about the garbage we read when
15130 * e.g. coming up after runtime pm.
15131 *
4cc31489
DV		 15132 * No protection against concurrent access is required - at
15133 * worst a fifo underrun happens which also sets this to false.
15134 */
15135 crtc->cpu_fifo_underrun_disabled = true;
15136 crtc->pch_fifo_underrun_disabled = true;
15137 }
24929352
DV		 15138}
15139
15140static void intel_sanitize_encoder(struct intel_encoder *encoder)
15141{
15142 struct intel_connector *connector;
15143 struct drm_device *dev = encoder->base.dev;
15144
15145 /* We need to check both for a crtc link (meaning that the
15146 * encoder is active and trying to read from a pipe) and the
15147 * pipe itself being active. */
15148 bool has_active_crtc = encoder->base.crtc &&
15149 to_intel_crtc(encoder->base.crtc)->active;
15150
15151 if (encoder->connectors_active && !has_active_crtc) {
15152 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15153 encoder->base.base.id,
8e329a03 15154 encoder->base.name);
24929352
DV		 15155
15156 /* Connector is active, but has no active pipe. This is
15157 * fallout from our resume register restoring. Disable
15158 * the encoder manually again. */
15159 if (encoder->base.crtc) {
15160 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15161 encoder->base.base.id,
8e329a03 15162 encoder->base.name);
24929352 15163 encoder->disable(encoder);
a62d1497
VS		 15164 if (encoder->post_disable)
15165 encoder->post_disable(encoder);
24929352 15166 }
7f1950fb
EE		 15167 encoder->base.crtc = NULL;
15168 encoder->connectors_active = false;
24929352
DV		 15169
15170 /* Inconsistent output/port/pipe state happens presumably due to
15171 * a bug in one of the get_hw_state functions. Or someplace else
15172 * in our code, like the register restore mess on resume. Clamp
15173 * things to off as a safer default. */
3a3371ff 15174 for_each_intel_connector(dev, connector) {
24929352
DV		 15175 if (connector->encoder != encoder)
15176 continue;
7f1950fb
EE		 15177 connector->base.dpms = DRM_MODE_DPMS_OFF;
15178 connector->base.encoder = NULL;
24929352
DV		 15179 }
15180 }
15181 /* Enabled encoders without active connectors will be fixed in
15182 * the crtc fixup. */
15183}
15184
04098753 15185void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15186{
15187 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15188 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15189
04098753
ID		 15190 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15191 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15192 i915_disable_vga(dev);
15193 }
15194}
15195
15196void i915_redisable_vga(struct drm_device *dev)
15197{
15198 struct drm_i915_private *dev_priv = dev->dev_private;
15199
8dc8a27c
PZ		 15200 /* This function can be called both from intel_modeset_setup_hw_state or
15201 * at a very early point in our resume sequence, where the power well
15202 * structures are not yet restored. Since this function is at a very
15203 * paranoid "someone might have enabled VGA while we were not looking"
15204 * level, just check if the power well is enabled instead of trying to
15205 * follow the "don't touch the power well if we don't need it" policy
15206 * the rest of the driver uses. */
f458ebbc 15207 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15208 return;
15209
04098753 15210 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15211}
15212
98ec7739
VS		 15213static bool primary_get_hw_state(struct intel_crtc *crtc)
15214{
15215 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15216
d032ffa0
ML		 15217 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15218}
15219
15220static void readout_plane_state(struct intel_crtc *crtc,
15221 struct intel_crtc_state *crtc_state)
15222{
15223 struct intel_plane *p;
4cf0ebbd 15224 struct intel_plane_state *plane_state;
d032ffa0
ML		 15225 bool active = crtc_state->base.active;
15226
d032ffa0 15227 for_each_intel_plane(crtc->base.dev, p) {
d032ffa0
ML		 15228 if (crtc->pipe != p->pipe)
15229 continue;
15230
4cf0ebbd 15231 plane_state = to_intel_plane_state(p->base.state);
e435d6e5 15232
4cf0ebbd
ML		 15233 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15234 plane_state->visible = primary_get_hw_state(crtc);
15235 else {
15236 if (active)
15237 p->disable_plane(&p->base, &crtc->base);
d032ffa0 15238
4cf0ebbd 15239 plane_state->visible = false;
d032ffa0
ML		 15240 }
15241 }
98ec7739
VS		 15242}
15243
30e984df 15244static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15245{
15246 struct drm_i915_private *dev_priv = dev->dev_private;
15247 enum pipe pipe;
24929352
DV		 15248 struct intel_crtc *crtc;
15249 struct intel_encoder *encoder;
15250 struct intel_connector *connector;
5358901f 15251 int i;
24929352 15252
d3fcc808 15253 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15254 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15255 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15256 crtc->config->base.crtc = &crtc->base;
3b117c8f 15257
6e3c9717 15258 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15259
0e8ffe1b 15260 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15261 crtc->config);
24929352 15262
49d6fa21 15263 crtc->base.state->active = crtc->active;
24929352 15264 crtc->base.enabled = crtc->active;
b70709a6 15265
5c1e3426
ML		 15266 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15267 if (crtc->base.state->active) {
15268 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15269 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15270 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15271
15272 /*
15273 * The initial mode needs to be set in order to keep
15274 * the atomic core happy. It wants a valid mode if the
15275 * crtc's enabled, so we do the above call.
15276 *
15277 * At this point some state updated by the connectors
15278 * in their ->detect() callback has not run yet, so
15279 * no recalculation can be done yet.
15280 *
15281 * Even if we could do a recalculation and modeset
15282 * right now it would cause a double modeset if
15283 * fbdev or userspace chooses a different initial mode.
15284 *
15285 * So to prevent the double modeset, fail the memcmp
15286 * test in drm_atomic_set_mode_for_crtc to get a new
15287 * mode blob, and compare if the mode blob changed
15288 * when the PIPE_CONFIG_QUIRK_INHERITED_MODE quirk is
15289 * set.
15290 *
15291 * If that happens, someone indicated they wanted a
15292 * mode change, which means it's safe to do a full
15293 * recalculation.
15294 */
15295 crtc->base.state->mode.private_flags = ~0;
15296 }
15297
15298 crtc->base.hwmode = crtc->config->base.adjusted_mode;
d032ffa0 15299 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15300
15301 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15302 crtc->base.base.id,
15303 crtc->active ? "enabled" : "disabled");
15304 }
15305
5358901f
DV		 15306 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15307 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15308
3e369b76
ACO		 15309 pll->on = pll->get_hw_state(dev_priv, pll,
15310 &pll->config.hw_state);
5358901f 15311 pll->active = 0;
3e369b76 15312 pll->config.crtc_mask = 0;
d3fcc808 15313 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15314 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15315 pll->active++;
3e369b76 15316 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15317 }
5358901f 15318 }
5358901f 15319
1e6f2ddc 15320 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15321 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15322
3e369b76 15323 if (pll->config.crtc_mask)
bd2bb1b9 15324 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15325 }
15326
b2784e15 15327 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15328 pipe = 0;
15329
15330 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15331 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15332 encoder->base.crtc = &crtc->base;
6e3c9717 15333 encoder->get_config(encoder, crtc->config);
24929352
DV		 15334 } else {
15335 encoder->base.crtc = NULL;
15336 }
15337
15338 encoder->connectors_active = false;
6f2bcceb 15339 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15340 encoder->base.base.id,
8e329a03 15341 encoder->base.name,
24929352 15342 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15343 pipe_name(pipe));
24929352
DV		 15344 }
15345
3a3371ff 15346 for_each_intel_connector(dev, connector) {
24929352
DV		 15347 if (connector->get_hw_state(connector)) {
15348 connector->base.dpms = DRM_MODE_DPMS_ON;
15349 connector->encoder->connectors_active = true;
15350 connector->base.encoder = &connector->encoder->base;
15351 } else {
15352 connector->base.dpms = DRM_MODE_DPMS_OFF;
15353 connector->base.encoder = NULL;
15354 }
15355 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15356 connector->base.base.id,
c23cc417 15357 connector->base.name,
24929352
DV		 15358 connector->base.encoder ? "enabled" : "disabled");
15359 }
30e984df
DV		 15360}
15361
043e9bda
ML		 15362/* Scan out the current hw modeset state,
15363 * and sanitizes it to the current state
15364 */
15365static void
15366intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15367{
15368 struct drm_i915_private *dev_priv = dev->dev_private;
15369 enum pipe pipe;
30e984df
DV		 15370 struct intel_crtc *crtc;
15371 struct intel_encoder *encoder;
35c95375 15372 int i;
30e984df
DV		 15373
15374 intel_modeset_readout_hw_state(dev);
24929352
DV		 15375
15376 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15377 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15378 intel_sanitize_encoder(encoder);
15379 }
15380
055e393f 15381 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15382 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15383 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15384 intel_dump_pipe_config(crtc, crtc->config,
15385 "[setup_hw_state]");
24929352 15386 }
9a935856 15387
d29b2f9d
ACO		 15388 intel_modeset_update_connector_atomic_state(dev);
15389
35c95375
DV		 15390 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15391 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15392
15393 if (!pll->on || pll->active)
15394 continue;
15395
15396 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15397
15398 pll->disable(dev_priv, pll);
15399 pll->on = false;
15400 }
15401
26e1fe4f 15402 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15403 vlv_wm_get_hw_state(dev);
15404 else if (IS_GEN9(dev))
3078999f
PB		 15405 skl_wm_get_hw_state(dev);
15406 else if (HAS_PCH_SPLIT(dev))
243e6a44 15407 ilk_wm_get_hw_state(dev);
292b990e
ML		 15408
15409 for_each_intel_crtc(dev, crtc) {
15410 unsigned long put_domains;
15411
15412 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15413 if (WARN_ON(put_domains))
15414 modeset_put_power_domains(dev_priv, put_domains);
15415 }
15416 intel_display_set_init_power(dev_priv, false);
043e9bda 15417}
7d0bc1ea 15418
043e9bda
ML		 15419void intel_display_resume(struct drm_device *dev)
15420{
15421 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15422 struct intel_connector *conn;
15423 struct intel_plane *plane;
15424 struct drm_crtc *crtc;
15425 int ret;
f30da187 15426
043e9bda
ML		 15427 if (!state)
15428 return;
15429
15430 state->acquire_ctx = dev->mode_config.acquire_ctx;
15431
15432 /* preserve complete old state, including dpll */
15433 intel_atomic_get_shared_dpll_state(state);
15434
15435 for_each_crtc(dev, crtc) {
15436 struct drm_crtc_state *crtc_state =
15437 drm_atomic_get_crtc_state(state, crtc);
15438
15439 ret = PTR_ERR_OR_ZERO(crtc_state);
15440 if (ret)
15441 goto err;
15442
15443 /* force a restore */
15444 crtc_state->mode_changed = true;
45e2b5f6 15445 }
8af6cf88 15446
043e9bda
ML		 15447 for_each_intel_plane(dev, plane) {
15448 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15449 if (ret)
15450 goto err;
15451 }
15452
15453 for_each_intel_connector(dev, conn) {
15454 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15455 if (ret)
15456 goto err;
15457 }
15458
15459 intel_modeset_setup_hw_state(dev);
15460
15461 i915_redisable_vga(dev);
74c090b1 15462 ret = drm_atomic_commit(state);
043e9bda
ML		 15463 if (!ret)
15464 return;
15465
15466err:
15467 DRM_ERROR("Restoring old state failed with %i\n", ret);
15468 drm_atomic_state_free(state);
2c7111db
CW		 15469}
15470
15471void intel_modeset_gem_init(struct drm_device *dev)
15472{
92122789 15473 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15474 struct drm_crtc *c;
2ff8fde1 15475 struct drm_i915_gem_object *obj;
e0d6149b 15476 int ret;
484b41dd 15477
ae48434c
ID		 15478 mutex_lock(&dev->struct_mutex);
15479 intel_init_gt_powersave(dev);
15480 mutex_unlock(&dev->struct_mutex);
15481
92122789
JB		 15482 /*
15483 * There may be no VBT; and if the BIOS enabled SSC we can
15484 * just keep using it to avoid unnecessary flicker. Whereas if the
15485 * BIOS isn't using it, don't assume it will work even if the VBT
15486 * indicates as much.
15487 */
15488 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15489 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15490 DREF_SSC1_ENABLE);
15491
1833b134 15492 intel_modeset_init_hw(dev);
02e792fb
DV		 15493
15494 intel_setup_overlay(dev);
484b41dd
JB		 15495
15496 /*
15497 * Make sure any fbs we allocated at startup are properly
15498 * pinned & fenced. When we do the allocation it's too early
15499 * for this.
15500 */
70e1e0ec 15501 for_each_crtc(dev, c) {
2ff8fde1
MR		 15502 obj = intel_fb_obj(c->primary->fb);
15503 if (obj == NULL)
484b41dd
JB		 15504 continue;
15505
e0d6149b
TU		 15506 mutex_lock(&dev->struct_mutex);
15507 ret = intel_pin_and_fence_fb_obj(c->primary,
15508 c->primary->fb,
15509 c->primary->state,
91af127f 15510 NULL, NULL);
e0d6149b
TU		 15511 mutex_unlock(&dev->struct_mutex);
15512 if (ret) {
484b41dd
JB		 15513 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15514 to_intel_crtc(c)->pipe);
66e514c1
DA		 15515 drm_framebuffer_unreference(c->primary->fb);
15516 c->primary->fb = NULL;
36750f28 15517 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15518 update_state_fb(c->primary);
36750f28 15519 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15520 }
15521 }
0962c3c9
VS		 15522
15523 intel_backlight_register(dev);
79e53945
JB		 15524}
15525
4932e2c3
ID		 15526void intel_connector_unregister(struct intel_connector *intel_connector)
15527{
15528 struct drm_connector *connector = &intel_connector->base;
15529
15530 intel_panel_destroy_backlight(connector);
34ea3d38 15531 drm_connector_unregister(connector);
4932e2c3
ID		 15532}
15533
79e53945
JB		 15534void intel_modeset_cleanup(struct drm_device *dev)
15535{
652c393a 15536 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15537 struct drm_connector *connector;
652c393a 15538
2eb5252e
ID		 15539 intel_disable_gt_powersave(dev);
15540
0962c3c9
VS		 15541 intel_backlight_unregister(dev);
15542
fd0c0642
DV		 15543 /*
15544 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15545 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15546 * experience fancy races otherwise.
15547 */
2aeb7d3a 15548 intel_irq_uninstall(dev_priv);
eb21b92b 15549
fd0c0642
DV		 15550 /*
15551 * Due to the hpd irq storm handling the hotplug work can re-arm the
15552 * poll handlers. Hence disable polling after hpd handling is shut down.
15553 */
f87ea761 15554 drm_kms_helper_poll_fini(dev);
fd0c0642 15555
723bfd70
JB		 15556 intel_unregister_dsm_handler();
15557
7733b49b 15558 intel_fbc_disable(dev_priv);
69341a5e 15559
1630fe75
CW		 15560 /* flush any delayed tasks or pending work */
15561 flush_scheduled_work();
15562
db31af1d
JN		 15563 /* destroy the backlight and sysfs files before encoders/connectors */
15564 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15565 struct intel_connector *intel_connector;
15566
15567 intel_connector = to_intel_connector(connector);
15568 intel_connector->unregister(intel_connector);
db31af1d 15569 }
d9255d57 15570
79e53945 15571 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15572
15573 intel_cleanup_overlay(dev);
ae48434c
ID		 15574
15575 mutex_lock(&dev->struct_mutex);
15576 intel_cleanup_gt_powersave(dev);
15577 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15578}
15579
f1c79df3
ZW		 15580/*
15581 * Return which encoder is currently attached for connector.
15582 */
df0e9248 15583struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15584{
df0e9248
CW		 15585 return &intel_attached_encoder(connector)->base;
15586}
f1c79df3 15587
df0e9248
CW		 15588void intel_connector_attach_encoder(struct intel_connector *connector,
15589 struct intel_encoder *encoder)
15590{
15591 connector->encoder = encoder;
15592 drm_mode_connector_attach_encoder(&connector->base,
15593 &encoder->base);
79e53945 15594}
28d52043
DA		 15595
15596/*
15597 * set vga decode state - true == enable VGA decode
15598 */
15599int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15600{
15601 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15602 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15603 u16 gmch_ctrl;
15604
75fa041d
CW		 15605 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15606 DRM_ERROR("failed to read control word\n");
15607 return -EIO;
15608 }
15609
c0cc8a55
CW		 15610 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15611 return 0;
15612
28d52043
DA		 15613 if (state)
15614 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15615 else
15616 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15617
15618 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15619 DRM_ERROR("failed to write control word\n");
15620 return -EIO;
15621 }
15622
28d52043
DA		 15623 return 0;
15624}
c4a1d9e4 15625
c4a1d9e4 15626struct intel_display_error_state {
ff57f1b0
PZ		 15627
15628 u32 power_well_driver;
15629
63b66e5b
CW		 15630 int num_transcoders;
15631
c4a1d9e4
CW		 15632 struct intel_cursor_error_state {
15633 u32 control;
15634 u32 position;
15635 u32 base;
15636 u32 size;
52331309 15637 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15638
15639 struct intel_pipe_error_state {
ddf9c536 15640 bool power_domain_on;
c4a1d9e4 15641 u32 source;
f301b1e1 15642 u32 stat;
52331309 15643 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15644
15645 struct intel_plane_error_state {
15646 u32 control;
15647 u32 stride;
15648 u32 size;
15649 u32 pos;
15650 u32 addr;
15651 u32 surface;
15652 u32 tile_offset;
52331309 15653 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15654
15655 struct intel_transcoder_error_state {
ddf9c536 15656 bool power_domain_on;
63b66e5b
CW		 15657 enum transcoder cpu_transcoder;
15658
15659 u32 conf;
15660
15661 u32 htotal;
15662 u32 hblank;
15663 u32 hsync;
15664 u32 vtotal;
15665 u32 vblank;
15666 u32 vsync;
15667 } transcoder[4];
c4a1d9e4
CW		 15668};
15669
15670struct intel_display_error_state *
15671intel_display_capture_error_state(struct drm_device *dev)
15672{
fbee40df 15673 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15674 struct intel_display_error_state *error;
63b66e5b
CW		 15675 int transcoders[] = {
15676 TRANSCODER_A,
15677 TRANSCODER_B,
15678 TRANSCODER_C,
15679 TRANSCODER_EDP,
15680 };
c4a1d9e4
CW		 15681 int i;
15682
63b66e5b
CW		 15683 if (INTEL_INFO(dev)->num_pipes == 0)
15684 return NULL;
15685
9d1cb914 15686 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15687 if (error == NULL)
15688 return NULL;
15689
190be112 15690 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15691 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15692
055e393f 15693 for_each_pipe(dev_priv, i) {
ddf9c536 15694 error->pipe[i].power_domain_on =
f458ebbc
DV		 15695 __intel_display_power_is_enabled(dev_priv,
15696 POWER_DOMAIN_PIPE(i));
ddf9c536 15697 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15698 continue;
15699
5efb3e28
VS		 15700 error->cursor[i].control = I915_READ(CURCNTR(i));
15701 error->cursor[i].position = I915_READ(CURPOS(i));
15702 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15703
15704 error->plane[i].control = I915_READ(DSPCNTR(i));
15705 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15706 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15707 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15708 error->plane[i].pos = I915_READ(DSPPOS(i));
15709 }
ca291363
PZ		 15710 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15711 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15712 if (INTEL_INFO(dev)->gen >= 4) {
15713 error->plane[i].surface = I915_READ(DSPSURF(i));
15714 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15715 }
15716
c4a1d9e4 15717 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15718
3abfce77 15719 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15720 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15721 }
15722
15723 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15724 if (HAS_DDI(dev_priv->dev))
15725 error->num_transcoders++; /* Account for eDP. */
15726
15727 for (i = 0; i < error->num_transcoders; i++) {
15728 enum transcoder cpu_transcoder = transcoders[i];
15729
ddf9c536 15730 error->transcoder[i].power_domain_on =
f458ebbc 15731 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15732 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15733 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15734 continue;
15735
63b66e5b
CW		 15736 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15737
15738 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15739 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15740 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15741 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15742 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15743 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15744 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15745 }
15746
15747 return error;
15748}
15749
edc3d884
MK		 15750#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15751
c4a1d9e4 15752void
edc3d884 15753intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15754 struct drm_device *dev,
15755 struct intel_display_error_state *error)
15756{
055e393f 15757 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15758 int i;
15759
63b66e5b
CW		 15760 if (!error)
15761 return;
15762
edc3d884 15763 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15764 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15765 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15766 error->power_well_driver);
055e393f 15767 for_each_pipe(dev_priv, i) {
edc3d884 15768 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15769 err_printf(m, " Power: %s\n",
15770 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15771 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15772 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15773
15774 err_printf(m, "Plane [%d]:\n", i);
15775 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15776 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15777 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15778 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15779 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15780 }
4b71a570 15781 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15782 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15783 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15784 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15785 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15786 }
15787
edc3d884
MK		 15788 err_printf(m, "Cursor [%d]:\n", i);
15789 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15790 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15791 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15792 }
63b66e5b
CW		 15793
15794 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15795 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15796 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15797 err_printf(m, " Power: %s\n",
15798 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15799 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15800 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15801 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15802 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15803 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15804 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15805 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15806 }
c4a1d9e4 15807}
e2fcdaa9
VS		 15808
15809void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15810{
15811 struct intel_crtc *crtc;
15812
15813 for_each_intel_crtc(dev, crtc) {
15814 struct intel_unpin_work *work;
e2fcdaa9 15815
5e2d7afc 15816 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15817
15818 work = crtc->unpin_work;
15819
15820 if (work && work->event &&
15821 work->event->base.file_priv == file) {
15822 kfree(work->event);
15823 work->event = NULL;
15824 }
15825
5e2d7afc 15826 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15827 }
15828}
Linux kernel - Deliverables
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