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drm/i915: panel: invert brightness via parameter
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 78 int, int, intel_clock_t *, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
d4906093
ML		 88static bool
89intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
79e53945 92
a4fc5ed6
KP		 93static bool
94intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
5eb08b69 97static bool
f2b115e6 98intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
a4fc5ed6 101
021357ac
CW		 102static inline u32 /* units of 100MHz */
103intel_fdi_link_freq(struct drm_device *dev)
104{
8b99e68c
CW		 105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
021357ac
CW		 110}
111
e4b36699 112static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
d4906093 123 .find_pll = intel_find_best_PLL,
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699 138};
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
273e27ca 168
e4b36699 169static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
044c7c41 181 },
d4906093 182 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
044c7c41 210 },
d4906093 211 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
044c7c41 225 },
d4906093 226 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
273e27ca 239 .p2_slow = 10, .p2_fast = 10 },
0206e353 240 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 241};
242
f2b115e6 243static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 246 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
273e27ca 249 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
6115707b 256 .find_pll = intel_find_best_PLL,
e4b36699
KP		 257};
258
f2b115e6 259static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
273e27ca
EA		 273/* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
b91ad0ec 278static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
4547668a 289 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 290};
291
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 303 .find_pll = intel_g4x_find_best_PLL,
304};
305
306static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
273e27ca 320/* LVDS 100mhz refclk limits. */
b91ad0ec 321static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
0206e353 329 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 332 .find_pll = intel_g4x_find_best_PLL,
333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
0206e353 343 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
273e27ca 359 .p2_slow = 10, .p2_fast = 10 },
0206e353 360 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 361};
362
1b894b59
CW		 363static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
2c07245f 365{
b91ad0ec
ZW		 366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 368 const intel_limit_t *limit;
b91ad0ec
ZW		 369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
1b894b59 379 if (refclk == 100000)
b91ad0ec
ZW		 380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
2c07245f 387 else
b91ad0ec 388 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 389
390 return limit;
391}
392
044c7c41
ML		 393static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394{
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
e4b36699 403 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 404 else
405 /* LVDS with dual channel */
e4b36699 406 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 409 limit = &intel_limits_g4x_hdmi;
044c7c41 410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 411 limit = &intel_limits_g4x_sdvo;
0206e353 412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 413 limit = &intel_limits_g4x_display_port;
044c7c41 414 } else /* The option is for other outputs */
e4b36699 415 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 416
417 return limit;
418}
419
1b894b59 420static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 421{
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
bad720ff 425 if (HAS_PCH_SPLIT(dev))
1b894b59 426 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 427 else if (IS_G4X(dev)) {
044c7c41 428 limit = intel_g4x_limit(crtc);
f2b115e6 429 } else if (IS_PINEVIEW(dev)) {
2177832f 430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 431 limit = &intel_limits_pineview_lvds;
2177832f 432 else
f2b115e6 433 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 441 limit = &intel_limits_i8xx_lvds;
79e53945 442 else
e4b36699 443 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 444 }
445 return limit;
446}
447
f2b115e6
AJ		 448/* m1 is reserved as 0 in Pineview, n is a ring counter */
449static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 450{
2177832f
SL		 451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455}
456
457static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458{
f2b115e6
AJ		 459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
2177832f
SL		 461 return;
462 }
79e53945
JB		 463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467}
468
79e53945
JB		 469/**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
4ef69c7a 472bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 473{
4ef69c7a
CW		 474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
79e53945
JB		 483}
484
7c04d1d9 485#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 486/**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
1b894b59
CW		 491static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
79e53945 494{
79e53945 495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 496 INTELPllInvalid("p1 out of range\n");
79e53945 497 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 498 INTELPllInvalid("p out of range\n");
79e53945 499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 500 INTELPllInvalid("m2 out of range\n");
79e53945 501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 502 INTELPllInvalid("m1 out of range\n");
f2b115e6 503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 504 INTELPllInvalid("m1 <= m2\n");
79e53945 505 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 506 INTELPllInvalid("m out of range\n");
79e53945 507 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 508 INTELPllInvalid("n out of range\n");
79e53945 509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 510 INTELPllInvalid("vco out of range\n");
79e53945
JB		 511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 515 INTELPllInvalid("dot out of range\n");
79e53945
JB		 516
517 return true;
518}
519
d4906093
ML		 520static bool
521intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
d4906093 524
79e53945
JB		 525{
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
79e53945
JB		 529 int err = target;
530
bc5e5718 531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 532 (I915_READ(LVDS)) != 0) {
79e53945
JB		 533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
0206e353 551 memset(best_clock, 0, sizeof(*best_clock));
79e53945 552
42158660
ZY		 553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 564 int this_err;
565
2177832f 566 intel_clock(dev, refclk, &clock);
1b894b59
CW		 567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
79e53945 569 continue;
cec2f356
SP		 570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
79e53945
JB		 573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585}
586
d4906093
ML		 587static bool
588intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
d4906093
ML		 591{
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
6ba770dc
AJ		 597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 602 int lvds_reg;
603
c619eed4 604 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
f77f13e2 622 /* based on hardware requirement, prefer smaller n to precision */
d4906093 623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 624 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
2177832f 633 intel_clock(dev, refclk, &clock);
1b894b59
CW		 634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
d4906093 636 continue;
cec2f356
SP		 637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
1b894b59
CW		 640
641 this_err = abs(clock.dot - target);
d4906093
ML		 642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
2c07245f
ZW		 652 return found;
653}
654
5eb08b69 655static bool
f2b115e6 656intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
5eb08b69
ZW		 659{
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
4547668a 662
5eb08b69
ZW		 663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679}
680
a4fc5ed6
KP		 681/* DisplayPort has only two frequencies, 162MHz and 270MHz */
682static bool
683intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
a4fc5ed6 686{
5eddb70b
CW		 687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
a4fc5ed6
KP		 707}
708
9d0498a2
JB		 709/**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 718{
9d0498a2 719 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 720 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 721
300387c0
CW		 722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
9d0498a2 738 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
9d0498a2
JB		 742 DRM_DEBUG_KMS("vblank wait timed out\n");
743}
744
ab7ad7f6
KP		 745/*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
ab7ad7f6
KP		 754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
58e10eb9 760 *
9d0498a2 761 */
58e10eb9 762void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 765
766 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 767 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 768
769 /* Wait for the Pipe State to go off */
58e10eb9
CW		 770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
ab7ad7f6
KP		 772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
58e10eb9 775 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
58e10eb9 780 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 781 mdelay(5);
58e10eb9 782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
79e53945
JB		 787}
788
b24e7179
JB		 789static const char *state_string(bool enabled)
790{
791 return enabled ? "on" : "off";
792}
793
794/* Only for pre-ILK configs */
795static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797{
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808}
809#define assert_pll_enabled(d, p) assert_pll(d, p, true)
810#define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
040484af
JB		 812/* For ILK+ */
813static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815{
816 int reg;
817 u32 val;
818 bool cur_state;
819
d3ccbe86
JB		 820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
040484af
JB		 833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839}
840#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845{
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856}
857#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862{
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873}
874#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879{
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890}
891
892static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894{
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901}
902
ea0760cf
JB		 903static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905{
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
0de3b485 909 bool locked = true;
ea0760cf
JB		 910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 929 pipe_name(pipe));
ea0760cf
JB		 930}
931
b840d907
JB		 932void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
b24e7179
JB		 934{
935 int reg;
936 u32 val;
63d7bbe9 937 bool cur_state;
b24e7179 938
8e636784
DV		 939 /* if we need the pipe A quirk it must be always on */
940 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941 state = true;
942
b24e7179
JB		 943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
63d7bbe9
JB		 945 cur_state = !!(val & PIPECONF_ENABLE);
946 WARN(cur_state != state,
947 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 948 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 949}
950
931872fc
CW		 951static void assert_plane(struct drm_i915_private *dev_priv,
952 enum plane plane, bool state)
b24e7179
JB		 953{
954 int reg;
955 u32 val;
931872fc 956 bool cur_state;
b24e7179
JB		 957
958 reg = DSPCNTR(plane);
959 val = I915_READ(reg);
931872fc
CW		 960 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961 WARN(cur_state != state,
962 "plane %c assertion failure (expected %s, current %s)\n",
963 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 964}
965
931872fc
CW		 966#define assert_plane_enabled(d, p) assert_plane(d, p, true)
967#define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
b24e7179
JB		 969static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971{
972 int reg, i;
973 u32 val;
974 int cur_pipe;
975
19ec1358 976 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 977 if (HAS_PCH_SPLIT(dev_priv->dev)) {
978 reg = DSPCNTR(pipe);
979 val = I915_READ(reg);
980 WARN((val & DISPLAY_PLANE_ENABLE),
981 "plane %c assertion failure, should be disabled but not\n",
982 plane_name(pipe));
19ec1358 983 return;
28c05794 984 }
19ec1358 985
b24e7179
JB		 986 /* Need to check both planes against the pipe */
987 for (i = 0; i < 2; i++) {
988 reg = DSPCNTR(i);
989 val = I915_READ(reg);
990 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991 DISPPLANE_SEL_PIPE_SHIFT;
992 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 993 "plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i), pipe_name(pipe));
b24e7179
JB		 995 }
996}
997
92f2584a
JB		 998static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999{
1000 u32 val;
1001 bool enabled;
1002
1003 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK));
1006 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007}
1008
1009static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014 bool enabled;
1015
1016 reg = TRANSCONF(pipe);
1017 val = I915_READ(reg);
1018 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1019 WARN(enabled,
1020 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021 pipe_name(pipe));
92f2584a
JB		 1022}
1023
4e634389
KP		 1024static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1026{
1027 if ((val & DP_PORT_EN) == 0)
1028 return false;
1029
1030 if (HAS_PCH_CPT(dev_priv->dev)) {
1031 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034 return false;
1035 } else {
1036 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037 return false;
1038 }
1039 return true;
1040}
1041
1519b995
KP		 1042static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043 enum pipe pipe, u32 val)
1044{
1045 if ((val & PORT_ENABLE) == 0)
1046 return false;
1047
1048 if (HAS_PCH_CPT(dev_priv->dev)) {
1049 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050 return false;
1051 } else {
1052 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053 return false;
1054 }
1055 return true;
1056}
1057
1058static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, u32 val)
1060{
1061 if ((val & LVDS_PORT_EN) == 0)
1062 return false;
1063
1064 if (HAS_PCH_CPT(dev_priv->dev)) {
1065 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066 return false;
1067 } else {
1068 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069 return false;
1070 }
1071 return true;
1072}
1073
1074static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075 enum pipe pipe, u32 val)
1076{
1077 if ((val & ADPA_DAC_ENABLE) == 0)
1078 return false;
1079 if (HAS_PCH_CPT(dev_priv->dev)) {
1080 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081 return false;
1082 } else {
1083 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084 return false;
1085 }
1086 return true;
1087}
1088
291906f1 1089static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1090 enum pipe pipe, int reg, u32 port_sel)
291906f1 1091{
47a05eca 1092 u32 val = I915_READ(reg);
4e634389 1093 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1094 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1095 reg, pipe_name(pipe));
291906f1
JB		 1096}
1097
1098static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, int reg)
1100{
47a05eca 1101 u32 val = I915_READ(reg);
1519b995 1102 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1103 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1104 reg, pipe_name(pipe));
291906f1
JB		 1105}
1106
1107static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108 enum pipe pipe)
1109{
1110 int reg;
1111 u32 val;
291906f1 1112
f0575e92
KP		 1113 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1116
1117 reg = PCH_ADPA;
1118 val = I915_READ(reg);
1519b995 1119 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1120 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1121 pipe_name(pipe));
291906f1
JB		 1122
1123 reg = PCH_LVDS;
1124 val = I915_READ(reg);
1519b995 1125 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1126 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1127 pipe_name(pipe));
291906f1
JB		 1128
1129 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132}
1133
63d7bbe9
JB		 1134/**
1135 * intel_enable_pll - enable a PLL
1136 * @dev_priv: i915 private structure
1137 * @pipe: pipe PLL to enable
1138 *
1139 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1140 * make sure the PLL reg is writable first though, since the panel write
1141 * protect mechanism may be enabled.
1142 *
1143 * Note! This is for pre-ILK only.
1144 */
1145static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146{
1147 int reg;
1148 u32 val;
1149
1150 /* No really, not for ILK+ */
1151 BUG_ON(dev_priv->info->gen >= 5);
1152
1153 /* PLL is protected by panel, make sure we can write it */
1154 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155 assert_panel_unlocked(dev_priv, pipe);
1156
1157 reg = DPLL(pipe);
1158 val = I915_READ(reg);
1159 val |= DPLL_VCO_ENABLE;
1160
1161 /* We do this three times for luck */
1162 I915_WRITE(reg, val);
1163 POSTING_READ(reg);
1164 udelay(150); /* wait for warmup */
1165 I915_WRITE(reg, val);
1166 POSTING_READ(reg);
1167 udelay(150); /* wait for warmup */
1168 I915_WRITE(reg, val);
1169 POSTING_READ(reg);
1170 udelay(150); /* wait for warmup */
1171}
1172
1173/**
1174 * intel_disable_pll - disable a PLL
1175 * @dev_priv: i915 private structure
1176 * @pipe: pipe PLL to disable
1177 *
1178 * Disable the PLL for @pipe, making sure the pipe is off first.
1179 *
1180 * Note! This is for pre-ILK only.
1181 */
1182static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183{
1184 int reg;
1185 u32 val;
1186
1187 /* Don't disable pipe A or pipe A PLLs if needed */
1188 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189 return;
1190
1191 /* Make sure the pipe isn't still relying on us */
1192 assert_pipe_disabled(dev_priv, pipe);
1193
1194 reg = DPLL(pipe);
1195 val = I915_READ(reg);
1196 val &= ~DPLL_VCO_ENABLE;
1197 I915_WRITE(reg, val);
1198 POSTING_READ(reg);
1199}
1200
92f2584a
JB		 1201/**
1202 * intel_enable_pch_pll - enable PCH PLL
1203 * @dev_priv: i915 private structure
1204 * @pipe: pipe PLL to enable
1205 *
1206 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207 * drives the transcoder clock.
1208 */
1209static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211{
1212 int reg;
1213 u32 val;
1214
4c609cb8
JB		 1215 if (pipe > 1)
1216 return;
1217
92f2584a
JB		 1218 /* PCH only available on ILK+ */
1219 BUG_ON(dev_priv->info->gen < 5);
1220
1221 /* PCH refclock must be enabled first */
1222 assert_pch_refclk_enabled(dev_priv);
1223
1224 reg = PCH_DPLL(pipe);
1225 val = I915_READ(reg);
1226 val |= DPLL_VCO_ENABLE;
1227 I915_WRITE(reg, val);
1228 POSTING_READ(reg);
1229 udelay(200);
1230}
1231
1232static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234{
1235 int reg;
7a419866
JB		 1236 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237 pll_sel = TRANSC_DPLL_ENABLE;
92f2584a 1238
4c609cb8
JB		 1239 if (pipe > 1)
1240 return;
1241
92f2584a
JB		 1242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5);
1244
1245 /* Make sure transcoder isn't still depending on us */
1246 assert_transcoder_disabled(dev_priv, pipe);
1247
7a419866
JB		 1248 if (pipe == 0)
1249 pll_sel |= TRANSC_DPLLA_SEL;
1250 else if (pipe == 1)
1251 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255 return;
1256
92f2584a
JB		 1257 reg = PCH_DPLL(pipe);
1258 val = I915_READ(reg);
1259 val &= ~DPLL_VCO_ENABLE;
1260 I915_WRITE(reg, val);
1261 POSTING_READ(reg);
1262 udelay(200);
1263}
1264
040484af
JB		 1265static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267{
1268 int reg;
5f7f726d 1269 u32 val, pipeconf_val;
7c26e5c6 1270 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1271
1272 /* PCH only available on ILK+ */
1273 BUG_ON(dev_priv->info->gen < 5);
1274
1275 /* Make sure PCH DPLL is enabled */
1276 assert_pch_pll_enabled(dev_priv, pipe);
1277
1278 /* FDI must be feeding us bits for PCH ports */
1279 assert_fdi_tx_enabled(dev_priv, pipe);
1280 assert_fdi_rx_enabled(dev_priv, pipe);
1281
1282 reg = TRANSCONF(pipe);
1283 val = I915_READ(reg);
5f7f726d 1284 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1285
1286 if (HAS_PCH_IBX(dev_priv->dev)) {
1287 /*
1288 * make the BPC in transcoder be consistent with
1289 * that in pipeconf reg.
1290 */
1291 val &= ~PIPE_BPC_MASK;
5f7f726d 1292 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1293 }
5f7f726d
PZ		 1294
1295 val &= ~TRANS_INTERLACE_MASK;
1296 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1297 if (HAS_PCH_IBX(dev_priv->dev) &&
1298 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1299 val |= TRANS_LEGACY_INTERLACED_ILK;
1300 else
1301 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1302 else
1303 val |= TRANS_PROGRESSIVE;
1304
040484af
JB		 1305 I915_WRITE(reg, val | TRANS_ENABLE);
1306 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1307 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1308}
1309
1310static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1311 enum pipe pipe)
1312{
1313 int reg;
1314 u32 val;
1315
1316 /* FDI relies on the transcoder */
1317 assert_fdi_tx_disabled(dev_priv, pipe);
1318 assert_fdi_rx_disabled(dev_priv, pipe);
1319
291906f1
JB		 1320 /* Ports must be off as well */
1321 assert_pch_ports_disabled(dev_priv, pipe);
1322
040484af
JB		 1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 val &= ~TRANS_ENABLE;
1326 I915_WRITE(reg, val);
1327 /* wait for PCH transcoder off, transcoder state */
1328 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1329 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1330}
1331
b24e7179 1332/**
309cfea8 1333 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1334 * @dev_priv: i915 private structure
1335 * @pipe: pipe to enable
040484af 1336 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1337 *
1338 * Enable @pipe, making sure that various hardware specific requirements
1339 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1340 *
1341 * @pipe should be %PIPE_A or %PIPE_B.
1342 *
1343 * Will wait until the pipe is actually running (i.e. first vblank) before
1344 * returning.
1345 */
040484af
JB		 1346static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1347 bool pch_port)
b24e7179
JB		 1348{
1349 int reg;
1350 u32 val;
1351
1352 /*
1353 * A pipe without a PLL won't actually be able to drive bits from
1354 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1355 * need the check.
1356 */
1357 if (!HAS_PCH_SPLIT(dev_priv->dev))
1358 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1359 else {
1360 if (pch_port) {
1361 /* if driving the PCH, we need FDI enabled */
1362 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1363 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1364 }
1365 /* FIXME: assert CPU port conditions for SNB+ */
1366 }
b24e7179
JB		 1367
1368 reg = PIPECONF(pipe);
1369 val = I915_READ(reg);
00d70b15
CW		 1370 if (val & PIPECONF_ENABLE)
1371 return;
1372
1373 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1374 intel_wait_for_vblank(dev_priv->dev, pipe);
1375}
1376
1377/**
309cfea8 1378 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1379 * @dev_priv: i915 private structure
1380 * @pipe: pipe to disable
1381 *
1382 * Disable @pipe, making sure that various hardware specific requirements
1383 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1384 *
1385 * @pipe should be %PIPE_A or %PIPE_B.
1386 *
1387 * Will wait until the pipe has shut down before returning.
1388 */
1389static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1390 enum pipe pipe)
1391{
1392 int reg;
1393 u32 val;
1394
1395 /*
1396 * Make sure planes won't keep trying to pump pixels to us,
1397 * or we might hang the display.
1398 */
1399 assert_planes_disabled(dev_priv, pipe);
1400
1401 /* Don't disable pipe A or pipe A PLLs if needed */
1402 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1403 return;
1404
1405 reg = PIPECONF(pipe);
1406 val = I915_READ(reg);
00d70b15
CW		 1407 if ((val & PIPECONF_ENABLE) == 0)
1408 return;
1409
1410 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1411 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1412}
1413
d74362c9
KP		 1414/*
1415 * Plane regs are double buffered, going from enabled->disabled needs a
1416 * trigger in order to latch. The display address reg provides this.
1417 */
1418static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1419 enum plane plane)
1420{
1421 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1422 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1423}
1424
b24e7179
JB		 1425/**
1426 * intel_enable_plane - enable a display plane on a given pipe
1427 * @dev_priv: i915 private structure
1428 * @plane: plane to enable
1429 * @pipe: pipe being fed
1430 *
1431 * Enable @plane on @pipe, making sure that @pipe is running first.
1432 */
1433static void intel_enable_plane(struct drm_i915_private *dev_priv,
1434 enum plane plane, enum pipe pipe)
1435{
1436 int reg;
1437 u32 val;
1438
1439 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1440 assert_pipe_enabled(dev_priv, pipe);
1441
1442 reg = DSPCNTR(plane);
1443 val = I915_READ(reg);
00d70b15
CW		 1444 if (val & DISPLAY_PLANE_ENABLE)
1445 return;
1446
1447 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1448 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1449 intel_wait_for_vblank(dev_priv->dev, pipe);
1450}
1451
b24e7179
JB		 1452/**
1453 * intel_disable_plane - disable a display plane
1454 * @dev_priv: i915 private structure
1455 * @plane: plane to disable
1456 * @pipe: pipe consuming the data
1457 *
1458 * Disable @plane; should be an independent operation.
1459 */
1460static void intel_disable_plane(struct drm_i915_private *dev_priv,
1461 enum plane plane, enum pipe pipe)
1462{
1463 int reg;
1464 u32 val;
1465
1466 reg = DSPCNTR(plane);
1467 val = I915_READ(reg);
00d70b15
CW		 1468 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1469 return;
1470
1471 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1472 intel_flush_display_plane(dev_priv, plane);
1473 intel_wait_for_vblank(dev_priv->dev, pipe);
1474}
1475
47a05eca 1476static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1477 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1478{
1479 u32 val = I915_READ(reg);
4e634389 1480 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1481 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1482 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1483 }
47a05eca
JB		 1484}
1485
1486static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1487 enum pipe pipe, int reg)
1488{
1489 u32 val = I915_READ(reg);
1519b995 1490 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1491 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1492 reg, pipe);
47a05eca 1493 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1494 }
47a05eca
JB		 1495}
1496
1497/* Disable any ports connected to this transcoder */
1498static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1499 enum pipe pipe)
1500{
1501 u32 reg, val;
1502
1503 val = I915_READ(PCH_PP_CONTROL);
1504 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1505
f0575e92
KP		 1506 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1507 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1508 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1509
1510 reg = PCH_ADPA;
1511 val = I915_READ(reg);
1519b995 1512 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1513 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1514
1515 reg = PCH_LVDS;
1516 val = I915_READ(reg);
1519b995
KP		 1517 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1518 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1519 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1520 POSTING_READ(reg);
1521 udelay(100);
1522 }
1523
1524 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1525 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1526 disable_pch_hdmi(dev_priv, pipe, HDMID);
1527}
1528
43a9539f
CW		 1529static void i8xx_disable_fbc(struct drm_device *dev)
1530{
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 u32 fbc_ctl;
1533
1534 /* Disable compression */
1535 fbc_ctl = I915_READ(FBC_CONTROL);
1536 if ((fbc_ctl & FBC_CTL_EN) == 0)
1537 return;
1538
1539 fbc_ctl &= ~FBC_CTL_EN;
1540 I915_WRITE(FBC_CONTROL, fbc_ctl);
1541
1542 /* Wait for compressing bit to clear */
1543 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1544 DRM_DEBUG_KMS("FBC idle timed out\n");
1545 return;
1546 }
1547
1548 DRM_DEBUG_KMS("disabled FBC\n");
1549}
1550
80824003
JB		 1551static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552{
1553 struct drm_device *dev = crtc->dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_framebuffer *fb = crtc->fb;
1556 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1557 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1559 int cfb_pitch;
80824003
JB		 1560 int plane, i;
1561 u32 fbc_ctl, fbc_ctl2;
1562
016b9b61 1563 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
01f2c773
VS		 1564 if (fb->pitches[0] < cfb_pitch)
1565 cfb_pitch = fb->pitches[0];
80824003
JB		 1566
1567 /* FBC_CTL wants 64B units */
016b9b61
CW		 1568 cfb_pitch = (cfb_pitch / 64) - 1;
1569 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1570
1571 /* Clear old tags */
1572 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1573 I915_WRITE(FBC_TAG + (i * 4), 0);
1574
1575 /* Set it up... */
de568510
CW		 1576 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1577 fbc_ctl2 |= plane;
80824003
JB		 1578 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1579 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1580
1581 /* enable it... */
1582 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1583 if (IS_I945GM(dev))
49677901 1584 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1585 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1586 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1587 fbc_ctl |= obj->fence_reg;
80824003
JB		 1588 I915_WRITE(FBC_CONTROL, fbc_ctl);
1589
016b9b61
CW		 1590 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1591 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1592}
1593
ee5382ae 1594static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1595{
80824003
JB		 1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597
1598 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1599}
1600
74dff282
JB		 1601static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1602{
1603 struct drm_device *dev = crtc->dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 struct drm_framebuffer *fb = crtc->fb;
1606 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1607 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1609 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1610 unsigned long stall_watermark = 200;
1611 u32 dpfc_ctl;
1612
74dff282 1613 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1614 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1615 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1616
74dff282
JB		 1617 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1618 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1619 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1620 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1621
1622 /* enable it... */
1623 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1624
28c97730 1625 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1626}
1627
43a9539f 1628static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1629{
1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 u32 dpfc_ctl;
1632
1633 /* Disable compression */
1634 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1635 if (dpfc_ctl & DPFC_CTL_EN) {
1636 dpfc_ctl &= ~DPFC_CTL_EN;
1637 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1638
bed4a673
CW		 1639 DRM_DEBUG_KMS("disabled FBC\n");
1640 }
74dff282
JB		 1641}
1642
ee5382ae 1643static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1644{
74dff282
JB		 1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646
1647 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1648}
1649
4efe0708
JB		 1650static void sandybridge_blit_fbc_update(struct drm_device *dev)
1651{
1652 struct drm_i915_private *dev_priv = dev->dev_private;
1653 u32 blt_ecoskpd;
1654
1655 /* Make sure blitter notifies FBC of writes */
fcca7926 1656 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1657 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1658 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1659 GEN6_BLITTER_LOCK_SHIFT;
1660 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1661 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1662 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1663 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1664 GEN6_BLITTER_LOCK_SHIFT);
1665 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1666 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1667 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1668}
1669
b52eb4dc
ZY		 1670static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1671{
1672 struct drm_device *dev = crtc->dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 struct drm_framebuffer *fb = crtc->fb;
1675 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1676 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1678 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1679 unsigned long stall_watermark = 200;
1680 u32 dpfc_ctl;
1681
bed4a673 1682 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1683 dpfc_ctl &= DPFC_RESERVED;
1684 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1685 /* Set persistent mode for front-buffer rendering, ala X. */
1686 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1687 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1688 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1689
b52eb4dc
ZY		 1690 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1691 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1692 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1693 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1694 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1695 /* enable it... */
bed4a673 1696 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1697
9c04f015
YL		 1698 if (IS_GEN6(dev)) {
1699 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1700 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1701 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1702 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1703 }
1704
b52eb4dc
ZY		 1705 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1706}
1707
43a9539f 1708static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1709{
1710 struct drm_i915_private *dev_priv = dev->dev_private;
1711 u32 dpfc_ctl;
1712
1713 /* Disable compression */
1714 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1715 if (dpfc_ctl & DPFC_CTL_EN) {
1716 dpfc_ctl &= ~DPFC_CTL_EN;
1717 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1718
bed4a673
CW		 1719 DRM_DEBUG_KMS("disabled FBC\n");
1720 }
b52eb4dc
ZY		 1721}
1722
1723static bool ironlake_fbc_enabled(struct drm_device *dev)
1724{
1725 struct drm_i915_private *dev_priv = dev->dev_private;
1726
1727 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1728}
1729
ee5382ae
AJ		 1730bool intel_fbc_enabled(struct drm_device *dev)
1731{
1732 struct drm_i915_private *dev_priv = dev->dev_private;
1733
1734 if (!dev_priv->display.fbc_enabled)
1735 return false;
1736
1737 return dev_priv->display.fbc_enabled(dev);
1738}
1739
1630fe75
CW		 1740static void intel_fbc_work_fn(struct work_struct *__work)
1741{
1742 struct intel_fbc_work *work =
1743 container_of(to_delayed_work(__work),
1744 struct intel_fbc_work, work);
1745 struct drm_device *dev = work->crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748 mutex_lock(&dev->struct_mutex);
1749 if (work == dev_priv->fbc_work) {
1750 /* Double check that we haven't switched fb without cancelling
1751 * the prior work.
1752 */
016b9b61 1753 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1754 dev_priv->display.enable_fbc(work->crtc,
1755 work->interval);
1756
016b9b61
CW		 1757 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1758 dev_priv->cfb_fb = work->crtc->fb->base.id;
1759 dev_priv->cfb_y = work->crtc->y;
1760 }
1761
1630fe75
CW		 1762 dev_priv->fbc_work = NULL;
1763 }
1764 mutex_unlock(&dev->struct_mutex);
1765
1766 kfree(work);
1767}
1768
1769static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1770{
1771 if (dev_priv->fbc_work == NULL)
1772 return;
1773
1774 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1775
1776 /* Synchronisation is provided by struct_mutex and checking of
1777 * dev_priv->fbc_work, so we can perform the cancellation
1778 * entirely asynchronously.
1779 */
1780 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1781 /* tasklet was killed before being run, clean up */
1782 kfree(dev_priv->fbc_work);
1783
1784 /* Mark the work as no longer wanted so that if it does
1785 * wake-up (because the work was already running and waiting
1786 * for our mutex), it will discover that is no longer
1787 * necessary to run.
1788 */
1789 dev_priv->fbc_work = NULL;
1790}
1791
43a9539f 1792static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1793{
1630fe75
CW		 1794 struct intel_fbc_work *work;
1795 struct drm_device *dev = crtc->dev;
1796 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1797
1798 if (!dev_priv->display.enable_fbc)
1799 return;
1800
1630fe75
CW		 1801 intel_cancel_fbc_work(dev_priv);
1802
1803 work = kzalloc(sizeof *work, GFP_KERNEL);
1804 if (work == NULL) {
1805 dev_priv->display.enable_fbc(crtc, interval);
1806 return;
1807 }
1808
1809 work->crtc = crtc;
1810 work->fb = crtc->fb;
1811 work->interval = interval;
1812 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1813
1814 dev_priv->fbc_work = work;
1815
1816 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1817
1818 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1819 * display to settle before starting the compression. Note that
1820 * this delay also serves a second purpose: it allows for a
1821 * vblank to pass after disabling the FBC before we attempt
1822 * to modify the control registers.
1630fe75
CW		 1823 *
1824 * A more complicated solution would involve tracking vblanks
1825 * following the termination of the page-flipping sequence
1826 * and indeed performing the enable as a co-routine and not
1827 * waiting synchronously upon the vblank.
1828 */
1829 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1830}
1831
1832void intel_disable_fbc(struct drm_device *dev)
1833{
1834 struct drm_i915_private *dev_priv = dev->dev_private;
1835
1630fe75
CW		 1836 intel_cancel_fbc_work(dev_priv);
1837
ee5382ae
AJ		 1838 if (!dev_priv->display.disable_fbc)
1839 return;
1840
1841 dev_priv->display.disable_fbc(dev);
016b9b61 1842 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1843}
1844
80824003
JB		 1845/**
1846 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1847 * @dev: the drm_device
80824003
JB		 1848 *
1849 * Set up the framebuffer compression hardware at mode set time. We
1850 * enable it if possible:
1851 * - plane A only (on pre-965)
1852 * - no pixel mulitply/line duplication
1853 * - no alpha buffer discard
1854 * - no dual wide
1855 * - framebuffer <= 2048 in width, 1536 in height
1856 *
1857 * We can't assume that any compression will take place (worst case),
1858 * so the compressed buffer has to be the same size as the uncompressed
1859 * one. It also must reside (along with the line length buffer) in
1860 * stolen memory.
1861 *
1862 * We need to enable/disable FBC on a global basis.
1863 */
bed4a673 1864static void intel_update_fbc(struct drm_device *dev)
80824003 1865{
80824003 1866 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1867 struct drm_crtc *crtc = NULL, *tmp_crtc;
1868 struct intel_crtc *intel_crtc;
1869 struct drm_framebuffer *fb;
80824003 1870 struct intel_framebuffer *intel_fb;
05394f39 1871 struct drm_i915_gem_object *obj;
cd0de039 1872 int enable_fbc;
9c928d16
JB		 1873
1874 DRM_DEBUG_KMS("\n");
80824003
JB		 1875
1876 if (!i915_powersave)
1877 return;
1878
ee5382ae 1879 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1880 return;
1881
80824003
JB		 1882 /*
1883 * If FBC is already on, we just have to verify that we can
1884 * keep it that way...
1885 * Need to disable if:
9c928d16 1886 * - more than one pipe is active
80824003
JB		 1887 * - changing FBC params (stride, fence, mode)
1888 * - new fb is too large to fit in compressed buffer
1889 * - going to an unsupported config (interlace, pixel multiply, etc.)
1890 */
9c928d16 1891 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1892 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1893 if (crtc) {
1894 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1895 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1896 goto out_disable;
1897 }
1898 crtc = tmp_crtc;
1899 }
9c928d16 1900 }
bed4a673
CW		 1901
1902 if (!crtc || crtc->fb == NULL) {
1903 DRM_DEBUG_KMS("no output, disabling\n");
1904 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1905 goto out_disable;
1906 }
bed4a673
CW		 1907
1908 intel_crtc = to_intel_crtc(crtc);
1909 fb = crtc->fb;
1910 intel_fb = to_intel_framebuffer(fb);
05394f39 1911 obj = intel_fb->obj;
bed4a673 1912
cd0de039
KP		 1913 enable_fbc = i915_enable_fbc;
1914 if (enable_fbc < 0) {
1915 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1916 enable_fbc = 1;
d56d8b28 1917 if (INTEL_INFO(dev)->gen <= 6)
cd0de039
KP		 1918 enable_fbc = 0;
1919 }
1920 if (!enable_fbc) {
1921 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1922 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1923 goto out_disable;
1924 }
05394f39 1925 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1926 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1927 "compression\n");
b5e50c3f 1928 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1929 goto out_disable;
1930 }
bed4a673
CW		 1931 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1932 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1933 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1934 "disabling\n");
b5e50c3f 1935 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1936 goto out_disable;
1937 }
bed4a673
CW		 1938 if ((crtc->mode.hdisplay > 2048) ||
1939 (crtc->mode.vdisplay > 1536)) {
28c97730 1940 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1941 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1942 goto out_disable;
1943 }
bed4a673 1944 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1945 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1946 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1947 goto out_disable;
1948 }
de568510
CW		 1949
1950 /* The use of a CPU fence is mandatory in order to detect writes
1951 * by the CPU to the scanout and trigger updates to the FBC.
1952 */
1953 if (obj->tiling_mode != I915_TILING_X ||
1954 obj->fence_reg == I915_FENCE_REG_NONE) {
1955 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1956 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1957 goto out_disable;
1958 }
1959
c924b934
JW		 1960 /* If the kernel debugger is active, always disable compression */
1961 if (in_dbg_master())
1962 goto out_disable;
1963
016b9b61
CW		 1964 /* If the scanout has not changed, don't modify the FBC settings.
1965 * Note that we make the fundamental assumption that the fb->obj
1966 * cannot be unpinned (and have its GTT offset and fence revoked)
1967 * without first being decoupled from the scanout and FBC disabled.
1968 */
1969 if (dev_priv->cfb_plane == intel_crtc->plane &&
1970 dev_priv->cfb_fb == fb->base.id &&
1971 dev_priv->cfb_y == crtc->y)
1972 return;
1973
1974 if (intel_fbc_enabled(dev)) {
1975 /* We update FBC along two paths, after changing fb/crtc
1976 * configuration (modeswitching) and after page-flipping
1977 * finishes. For the latter, we know that not only did
1978 * we disable the FBC at the start of the page-flip
1979 * sequence, but also more than one vblank has passed.
1980 *
1981 * For the former case of modeswitching, it is possible
1982 * to switch between two FBC valid configurations
1983 * instantaneously so we do need to disable the FBC
1984 * before we can modify its control registers. We also
1985 * have to wait for the next vblank for that to take
1986 * effect. However, since we delay enabling FBC we can
1987 * assume that a vblank has passed since disabling and
1988 * that we can safely alter the registers in the deferred
1989 * callback.
1990 *
1991 * In the scenario that we go from a valid to invalid
1992 * and then back to valid FBC configuration we have
1993 * no strict enforcement that a vblank occurred since
1994 * disabling the FBC. However, along all current pipe
1995 * disabling paths we do need to wait for a vblank at
1996 * some point. And we wait before enabling FBC anyway.
1997 */
1998 DRM_DEBUG_KMS("disabling active FBC for update\n");
1999 intel_disable_fbc(dev);
2000 }
2001
bed4a673 2002 intel_enable_fbc(crtc, 500);
80824003
JB		 2003 return;
2004
2005out_disable:
80824003 2006 /* Multiple disables should be harmless */
a939406f
CW		 2007 if (intel_fbc_enabled(dev)) {
2008 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 2009 intel_disable_fbc(dev);
a939406f 2010 }
80824003
JB		 2011}
2012
127bd2ac 2013int
48b956c5 2014intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 2015 struct drm_i915_gem_object *obj,
919926ae 2016 struct intel_ring_buffer *pipelined)
6b95a207 2017{
ce453d81 2018 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 2019 u32 alignment;
2020 int ret;
2021
05394f39 2022 switch (obj->tiling_mode) {
6b95a207 2023 case I915_TILING_NONE:
534843da
CW		 2024 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2025 alignment = 128 * 1024;
a6c45cf0 2026 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2027 alignment = 4 * 1024;
2028 else
2029 alignment = 64 * 1024;
6b95a207
KH		 2030 break;
2031 case I915_TILING_X:
2032 /* pin() will align the object as required by fence */
2033 alignment = 0;
2034 break;
2035 case I915_TILING_Y:
2036 /* FIXME: Is this true? */
2037 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2038 return -EINVAL;
2039 default:
2040 BUG();
2041 }
2042
ce453d81 2043 dev_priv->mm.interruptible = false;
2da3b9b9 2044 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2045 if (ret)
ce453d81 2046 goto err_interruptible;
6b95a207
KH		 2047
2048 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2049 * fence, whereas 965+ only requires a fence if using
2050 * framebuffer compression. For simplicity, we always install
2051 * a fence as the cost is not that onerous.
2052 */
05394f39 2053 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2054 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2055 if (ret)
2056 goto err_unpin;
1690e1eb
CW		 2057
2058 i915_gem_object_pin_fence(obj);
6b95a207
KH		 2059 }
2060
ce453d81 2061 dev_priv->mm.interruptible = true;
6b95a207 2062 return 0;
48b956c5
CW		 2063
2064err_unpin:
2065 i915_gem_object_unpin(obj);
ce453d81
CW		 2066err_interruptible:
2067 dev_priv->mm.interruptible = true;
48b956c5 2068 return ret;
6b95a207
KH		 2069}
2070
1690e1eb
CW		 2071void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2072{
2073 i915_gem_object_unpin_fence(obj);
2074 i915_gem_object_unpin(obj);
2075}
2076
17638cd6
JB		 2077static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2078 int x, int y)
81255565
JB		 2079{
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
05394f39 2084 struct drm_i915_gem_object *obj;
81255565
JB		 2085 int plane = intel_crtc->plane;
2086 unsigned long Start, Offset;
81255565 2087 u32 dspcntr;
5eddb70b 2088 u32 reg;
81255565
JB		 2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
2093 break;
2094 default:
2095 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2096 return -EINVAL;
2097 }
2098
2099 intel_fb = to_intel_framebuffer(fb);
2100 obj = intel_fb->obj;
81255565 2101
5eddb70b
CW		 2102 reg = DSPCNTR(plane);
2103 dspcntr = I915_READ(reg);
81255565
JB		 2104 /* Mask out pixel format bits in case we change it */
2105 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2106 switch (fb->bits_per_pixel) {
2107 case 8:
2108 dspcntr |= DISPPLANE_8BPP;
2109 break;
2110 case 16:
2111 if (fb->depth == 15)
2112 dspcntr |= DISPPLANE_15_16BPP;
2113 else
2114 dspcntr |= DISPPLANE_16BPP;
2115 break;
2116 case 24:
2117 case 32:
2118 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2119 break;
2120 default:
17638cd6 2121 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2122 return -EINVAL;
2123 }
a6c45cf0 2124 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2125 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2126 dspcntr |= DISPPLANE_TILED;
2127 else
2128 dspcntr &= ~DISPPLANE_TILED;
2129 }
2130
5eddb70b 2131 I915_WRITE(reg, dspcntr);
81255565 2132
05394f39 2133 Start = obj->gtt_offset;
01f2c773 2134 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2135
4e6cfefc 2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2137 Start, Offset, x, y, fb->pitches[0]);
2138 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2139 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2140 I915_WRITE(DSPSURF(plane), Start);
2141 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2142 I915_WRITE(DSPADDR(plane), Offset);
2143 } else
2144 I915_WRITE(DSPADDR(plane), Start + Offset);
2145 POSTING_READ(reg);
81255565 2146
17638cd6
JB		 2147 return 0;
2148}
2149
2150static int ironlake_update_plane(struct drm_crtc *crtc,
2151 struct drm_framebuffer *fb, int x, int y)
2152{
2153 struct drm_device *dev = crtc->dev;
2154 struct drm_i915_private *dev_priv = dev->dev_private;
2155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2156 struct intel_framebuffer *intel_fb;
2157 struct drm_i915_gem_object *obj;
2158 int plane = intel_crtc->plane;
2159 unsigned long Start, Offset;
2160 u32 dspcntr;
2161 u32 reg;
2162
2163 switch (plane) {
2164 case 0:
2165 case 1:
27f8227b 2166 case 2:
17638cd6
JB		 2167 break;
2168 default:
2169 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2170 return -EINVAL;
2171 }
2172
2173 intel_fb = to_intel_framebuffer(fb);
2174 obj = intel_fb->obj;
2175
2176 reg = DSPCNTR(plane);
2177 dspcntr = I915_READ(reg);
2178 /* Mask out pixel format bits in case we change it */
2179 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2180 switch (fb->bits_per_pixel) {
2181 case 8:
2182 dspcntr |= DISPPLANE_8BPP;
2183 break;
2184 case 16:
2185 if (fb->depth != 16)
2186 return -EINVAL;
2187
2188 dspcntr |= DISPPLANE_16BPP;
2189 break;
2190 case 24:
2191 case 32:
2192 if (fb->depth == 24)
2193 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2194 else if (fb->depth == 30)
2195 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2196 else
2197 return -EINVAL;
2198 break;
2199 default:
2200 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2201 return -EINVAL;
2202 }
2203
2204 if (obj->tiling_mode != I915_TILING_NONE)
2205 dspcntr |= DISPPLANE_TILED;
2206 else
2207 dspcntr &= ~DISPPLANE_TILED;
2208
2209 /* must disable */
2210 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2211
2212 I915_WRITE(reg, dspcntr);
2213
2214 Start = obj->gtt_offset;
01f2c773 2215 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 2216
2217 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2218 Start, Offset, x, y, fb->pitches[0]);
2219 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
17638cd6
JB		 2220 I915_WRITE(DSPSURF(plane), Start);
2221 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2222 I915_WRITE(DSPADDR(plane), Offset);
2223 POSTING_READ(reg);
2224
2225 return 0;
2226}
2227
2228/* Assume fb object is pinned & idle & fenced and just update base pointers */
2229static int
2230intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2231 int x, int y, enum mode_set_atomic state)
2232{
2233 struct drm_device *dev = crtc->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 int ret;
2236
2237 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2238 if (ret)
2239 return ret;
2240
bed4a673 2241 intel_update_fbc(dev);
3dec0095 2242 intel_increase_pllclock(crtc);
81255565
JB		 2243
2244 return 0;
2245}
2246
5c3b82e2 2247static int
3c4fdcfb
KH		 2248intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2249 struct drm_framebuffer *old_fb)
79e53945
JB		 2250{
2251 struct drm_device *dev = crtc->dev;
79e53945
JB		 2252 struct drm_i915_master_private *master_priv;
2253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2254 int ret;
79e53945
JB		 2255
2256 /* no fb bound */
2257 if (!crtc->fb) {
a5071c2f 2258 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2259 return 0;
2260 }
2261
265db958 2262 switch (intel_crtc->plane) {
5c3b82e2
CW		 2263 case 0:
2264 case 1:
2265 break;
27f8227b
JB		 2266 case 2:
2267 if (IS_IVYBRIDGE(dev))
2268 break;
2269 /* fall through otherwise */
5c3b82e2 2270 default:
a5071c2f 2271 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2272 return -EINVAL;
79e53945
JB		 2273 }
2274
5c3b82e2 2275 mutex_lock(&dev->struct_mutex);
265db958
CW		 2276 ret = intel_pin_and_fence_fb_obj(dev,
2277 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2278 NULL);
5c3b82e2
CW		 2279 if (ret != 0) {
2280 mutex_unlock(&dev->struct_mutex);
a5071c2f 2281 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2282 return ret;
2283 }
79e53945 2284
265db958 2285 if (old_fb) {
e6c3a2a6 2286 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2287 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2288
e6c3a2a6 2289 wait_event(dev_priv->pending_flip_queue,
01eec727 2290 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2291 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2292
2293 /* Big Hammer, we also need to ensure that any pending
2294 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2295 * current scanout is retired before unpinning the old
2296 * framebuffer.
01eec727
CW		 2297 *
2298 * This should only fail upon a hung GPU, in which case we
2299 * can safely continue.
85345517 2300 */
a8198eea 2301 ret = i915_gem_object_finish_gpu(obj);
01eec727 2302 (void) ret;
265db958
CW		 2303 }
2304
21c74a8e
JW		 2305 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2306 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2307 if (ret) {
1690e1eb 2308 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2309 mutex_unlock(&dev->struct_mutex);
a5071c2f 2310 DRM_ERROR("failed to update base address\n");
4e6cfefc 2311 return ret;
79e53945 2312 }
3c4fdcfb 2313
b7f1de28
CW		 2314 if (old_fb) {
2315 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2316 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2317 }
652c393a 2318
5c3b82e2 2319 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2320
2321 if (!dev->primary->master)
5c3b82e2 2322 return 0;
79e53945
JB		 2323
2324 master_priv = dev->primary->master->driver_priv;
2325 if (!master_priv->sarea_priv)
5c3b82e2 2326 return 0;
79e53945 2327
265db958 2328 if (intel_crtc->pipe) {
79e53945
JB		 2329 master_priv->sarea_priv->pipeB_x = x;
2330 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2331 } else {
2332 master_priv->sarea_priv->pipeA_x = x;
2333 master_priv->sarea_priv->pipeA_y = y;
79e53945 2334 }
5c3b82e2
CW		 2335
2336 return 0;
79e53945
JB		 2337}
2338
5eddb70b 2339static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2340{
2341 struct drm_device *dev = crtc->dev;
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 u32 dpa_ctl;
2344
28c97730 2345 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2346 dpa_ctl = I915_READ(DP_A);
2347 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2348
2349 if (clock < 200000) {
2350 u32 temp;
2351 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2352 /* workaround for 160Mhz:
2353 1) program 0x4600c bits 15:0 = 0x8124
2354 2) program 0x46010 bit 0 = 1
2355 3) program 0x46034 bit 24 = 1
2356 4) program 0x64000 bit 14 = 1
2357 */
2358 temp = I915_READ(0x4600c);
2359 temp &= 0xffff0000;
2360 I915_WRITE(0x4600c, temp | 0x8124);
2361
2362 temp = I915_READ(0x46010);
2363 I915_WRITE(0x46010, temp | 1);
2364
2365 temp = I915_READ(0x46034);
2366 I915_WRITE(0x46034, temp | (1 << 24));
2367 } else {
2368 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2369 }
2370 I915_WRITE(DP_A, dpa_ctl);
2371
5eddb70b 2372 POSTING_READ(DP_A);
32f9d658
ZW		 2373 udelay(500);
2374}
2375
5e84e1a4
ZW		 2376static void intel_fdi_normal_train(struct drm_crtc *crtc)
2377{
2378 struct drm_device *dev = crtc->dev;
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2381 int pipe = intel_crtc->pipe;
2382 u32 reg, temp;
2383
2384 /* enable normal train */
2385 reg = FDI_TX_CTL(pipe);
2386 temp = I915_READ(reg);
61e499bf 2387 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2388 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2389 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2390 } else {
2391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2393 }
5e84e1a4
ZW		 2394 I915_WRITE(reg, temp);
2395
2396 reg = FDI_RX_CTL(pipe);
2397 temp = I915_READ(reg);
2398 if (HAS_PCH_CPT(dev)) {
2399 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2400 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2401 } else {
2402 temp &= ~FDI_LINK_TRAIN_NONE;
2403 temp |= FDI_LINK_TRAIN_NONE;
2404 }
2405 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2406
2407 /* wait one idle pattern time */
2408 POSTING_READ(reg);
2409 udelay(1000);
357555c0
JB		 2410
2411 /* IVB wants error correction enabled */
2412 if (IS_IVYBRIDGE(dev))
2413 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2414 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2415}
2416
291427f5
JB		 2417static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2418{
2419 struct drm_i915_private *dev_priv = dev->dev_private;
2420 u32 flags = I915_READ(SOUTH_CHICKEN1);
2421
2422 flags |= FDI_PHASE_SYNC_OVR(pipe);
2423 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2424 flags |= FDI_PHASE_SYNC_EN(pipe);
2425 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2426 POSTING_READ(SOUTH_CHICKEN1);
2427}
2428
8db9d77b
ZW		 2429/* The FDI link training functions for ILK/Ibexpeak. */
2430static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2431{
2432 struct drm_device *dev = crtc->dev;
2433 struct drm_i915_private *dev_priv = dev->dev_private;
2434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2435 int pipe = intel_crtc->pipe;
0fc932b8 2436 int plane = intel_crtc->plane;
5eddb70b 2437 u32 reg, temp, tries;
8db9d77b 2438
0fc932b8
JB		 2439 /* FDI needs bits from pipe & plane first */
2440 assert_pipe_enabled(dev_priv, pipe);
2441 assert_plane_enabled(dev_priv, plane);
2442
e1a44743
AJ		 2443 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2444 for train result */
5eddb70b
CW		 2445 reg = FDI_RX_IMR(pipe);
2446 temp = I915_READ(reg);
e1a44743
AJ		 2447 temp &= ~FDI_RX_SYMBOL_LOCK;
2448 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2449 I915_WRITE(reg, temp);
2450 I915_READ(reg);
e1a44743
AJ		 2451 udelay(150);
2452
8db9d77b 2453 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2454 reg = FDI_TX_CTL(pipe);
2455 temp = I915_READ(reg);
77ffb597
AJ		 2456 temp &= ~(7 << 19);
2457 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2458 temp &= ~FDI_LINK_TRAIN_NONE;
2459 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2460 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2461
5eddb70b
CW		 2462 reg = FDI_RX_CTL(pipe);
2463 temp = I915_READ(reg);
8db9d77b
ZW		 2464 temp &= ~FDI_LINK_TRAIN_NONE;
2465 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2466 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2467
2468 POSTING_READ(reg);
8db9d77b
ZW		 2469 udelay(150);
2470
5b2adf89 2471 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2472 if (HAS_PCH_IBX(dev)) {
2473 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2474 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2475 FDI_RX_PHASE_SYNC_POINTER_EN);
2476 }
5b2adf89 2477
5eddb70b 2478 reg = FDI_RX_IIR(pipe);
e1a44743 2479 for (tries = 0; tries < 5; tries++) {
5eddb70b 2480 temp = I915_READ(reg);
8db9d77b
ZW		 2481 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2482
2483 if ((temp & FDI_RX_BIT_LOCK)) {
2484 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2485 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2486 break;
2487 }
8db9d77b 2488 }
e1a44743 2489 if (tries == 5)
5eddb70b 2490 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2491
2492 /* Train 2 */
5eddb70b
CW		 2493 reg = FDI_TX_CTL(pipe);
2494 temp = I915_READ(reg);
8db9d77b
ZW		 2495 temp &= ~FDI_LINK_TRAIN_NONE;
2496 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2497 I915_WRITE(reg, temp);
8db9d77b 2498
5eddb70b
CW		 2499 reg = FDI_RX_CTL(pipe);
2500 temp = I915_READ(reg);
8db9d77b
ZW		 2501 temp &= ~FDI_LINK_TRAIN_NONE;
2502 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2503 I915_WRITE(reg, temp);
8db9d77b 2504
5eddb70b
CW		 2505 POSTING_READ(reg);
2506 udelay(150);
8db9d77b 2507
5eddb70b 2508 reg = FDI_RX_IIR(pipe);
e1a44743 2509 for (tries = 0; tries < 5; tries++) {
5eddb70b 2510 temp = I915_READ(reg);
8db9d77b
ZW		 2511 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2512
2513 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2514 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2515 DRM_DEBUG_KMS("FDI train 2 done.\n");
2516 break;
2517 }
8db9d77b 2518 }
e1a44743 2519 if (tries == 5)
5eddb70b 2520 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2521
2522 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2523
8db9d77b
ZW		 2524}
2525
0206e353 2526static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2527 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2528 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2529 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2530 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2531};
2532
2533/* The FDI link training functions for SNB/Cougarpoint. */
2534static void gen6_fdi_link_train(struct drm_crtc *crtc)
2535{
2536 struct drm_device *dev = crtc->dev;
2537 struct drm_i915_private *dev_priv = dev->dev_private;
2538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2539 int pipe = intel_crtc->pipe;
fa37d39e 2540 u32 reg, temp, i, retry;
8db9d77b 2541
e1a44743
AJ		 2542 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2543 for train result */
5eddb70b
CW		 2544 reg = FDI_RX_IMR(pipe);
2545 temp = I915_READ(reg);
e1a44743
AJ		 2546 temp &= ~FDI_RX_SYMBOL_LOCK;
2547 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2548 I915_WRITE(reg, temp);
2549
2550 POSTING_READ(reg);
e1a44743
AJ		 2551 udelay(150);
2552
8db9d77b 2553 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2554 reg = FDI_TX_CTL(pipe);
2555 temp = I915_READ(reg);
77ffb597
AJ		 2556 temp &= ~(7 << 19);
2557 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_1;
2560 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2561 /* SNB-B */
2562 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2563 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2564
5eddb70b
CW		 2565 reg = FDI_RX_CTL(pipe);
2566 temp = I915_READ(reg);
8db9d77b
ZW		 2567 if (HAS_PCH_CPT(dev)) {
2568 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2569 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2570 } else {
2571 temp &= ~FDI_LINK_TRAIN_NONE;
2572 temp |= FDI_LINK_TRAIN_PATTERN_1;
2573 }
5eddb70b
CW		 2574 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2575
2576 POSTING_READ(reg);
8db9d77b
ZW		 2577 udelay(150);
2578
291427f5
JB		 2579 if (HAS_PCH_CPT(dev))
2580 cpt_phase_pointer_enable(dev, pipe);
2581
0206e353 2582 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2583 reg = FDI_TX_CTL(pipe);
2584 temp = I915_READ(reg);
8db9d77b
ZW		 2585 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2586 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2587 I915_WRITE(reg, temp);
2588
2589 POSTING_READ(reg);
8db9d77b
ZW		 2590 udelay(500);
2591
fa37d39e
SP		 2592 for (retry = 0; retry < 5; retry++) {
2593 reg = FDI_RX_IIR(pipe);
2594 temp = I915_READ(reg);
2595 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2596 if (temp & FDI_RX_BIT_LOCK) {
2597 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2598 DRM_DEBUG_KMS("FDI train 1 done.\n");
2599 break;
2600 }
2601 udelay(50);
8db9d77b 2602 }
fa37d39e
SP		 2603 if (retry < 5)
2604 break;
8db9d77b
ZW		 2605 }
2606 if (i == 4)
5eddb70b 2607 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2608
2609 /* Train 2 */
5eddb70b
CW		 2610 reg = FDI_TX_CTL(pipe);
2611 temp = I915_READ(reg);
8db9d77b
ZW		 2612 temp &= ~FDI_LINK_TRAIN_NONE;
2613 temp |= FDI_LINK_TRAIN_PATTERN_2;
2614 if (IS_GEN6(dev)) {
2615 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616 /* SNB-B */
2617 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2618 }
5eddb70b 2619 I915_WRITE(reg, temp);
8db9d77b 2620
5eddb70b
CW		 2621 reg = FDI_RX_CTL(pipe);
2622 temp = I915_READ(reg);
8db9d77b
ZW		 2623 if (HAS_PCH_CPT(dev)) {
2624 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2625 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2626 } else {
2627 temp &= ~FDI_LINK_TRAIN_NONE;
2628 temp |= FDI_LINK_TRAIN_PATTERN_2;
2629 }
5eddb70b
CW		 2630 I915_WRITE(reg, temp);
2631
2632 POSTING_READ(reg);
8db9d77b
ZW		 2633 udelay(150);
2634
0206e353 2635 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2636 reg = FDI_TX_CTL(pipe);
2637 temp = I915_READ(reg);
8db9d77b
ZW		 2638 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2640 I915_WRITE(reg, temp);
2641
2642 POSTING_READ(reg);
8db9d77b
ZW		 2643 udelay(500);
2644
fa37d39e
SP		 2645 for (retry = 0; retry < 5; retry++) {
2646 reg = FDI_RX_IIR(pipe);
2647 temp = I915_READ(reg);
2648 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2649 if (temp & FDI_RX_SYMBOL_LOCK) {
2650 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2651 DRM_DEBUG_KMS("FDI train 2 done.\n");
2652 break;
2653 }
2654 udelay(50);
8db9d77b 2655 }
fa37d39e
SP		 2656 if (retry < 5)
2657 break;
8db9d77b
ZW		 2658 }
2659 if (i == 4)
5eddb70b 2660 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2661
2662 DRM_DEBUG_KMS("FDI train done.\n");
2663}
2664
357555c0
JB		 2665/* Manual link training for Ivy Bridge A0 parts */
2666static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2667{
2668 struct drm_device *dev = crtc->dev;
2669 struct drm_i915_private *dev_priv = dev->dev_private;
2670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2671 int pipe = intel_crtc->pipe;
2672 u32 reg, temp, i;
2673
2674 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2675 for train result */
2676 reg = FDI_RX_IMR(pipe);
2677 temp = I915_READ(reg);
2678 temp &= ~FDI_RX_SYMBOL_LOCK;
2679 temp &= ~FDI_RX_BIT_LOCK;
2680 I915_WRITE(reg, temp);
2681
2682 POSTING_READ(reg);
2683 udelay(150);
2684
2685 /* enable CPU FDI TX and PCH FDI RX */
2686 reg = FDI_TX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 temp &= ~(7 << 19);
2689 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2690 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2691 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2692 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2693 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2694 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2695 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2696
2697 reg = FDI_RX_CTL(pipe);
2698 temp = I915_READ(reg);
2699 temp &= ~FDI_LINK_TRAIN_AUTO;
2700 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2701 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2702 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2703 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2704
2705 POSTING_READ(reg);
2706 udelay(150);
2707
291427f5
JB		 2708 if (HAS_PCH_CPT(dev))
2709 cpt_phase_pointer_enable(dev, pipe);
2710
0206e353 2711 for (i = 0; i < 4; i++) {
357555c0
JB		 2712 reg = FDI_TX_CTL(pipe);
2713 temp = I915_READ(reg);
2714 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2715 temp |= snb_b_fdi_train_param[i];
2716 I915_WRITE(reg, temp);
2717
2718 POSTING_READ(reg);
2719 udelay(500);
2720
2721 reg = FDI_RX_IIR(pipe);
2722 temp = I915_READ(reg);
2723 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2724
2725 if (temp & FDI_RX_BIT_LOCK ||
2726 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2727 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2728 DRM_DEBUG_KMS("FDI train 1 done.\n");
2729 break;
2730 }
2731 }
2732 if (i == 4)
2733 DRM_ERROR("FDI train 1 fail!\n");
2734
2735 /* Train 2 */
2736 reg = FDI_TX_CTL(pipe);
2737 temp = I915_READ(reg);
2738 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2739 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2740 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2741 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2742 I915_WRITE(reg, temp);
2743
2744 reg = FDI_RX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2747 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2748 I915_WRITE(reg, temp);
2749
2750 POSTING_READ(reg);
2751 udelay(150);
2752
0206e353 2753 for (i = 0; i < 4; i++) {
357555c0
JB		 2754 reg = FDI_TX_CTL(pipe);
2755 temp = I915_READ(reg);
2756 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2757 temp |= snb_b_fdi_train_param[i];
2758 I915_WRITE(reg, temp);
2759
2760 POSTING_READ(reg);
2761 udelay(500);
2762
2763 reg = FDI_RX_IIR(pipe);
2764 temp = I915_READ(reg);
2765 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2766
2767 if (temp & FDI_RX_SYMBOL_LOCK) {
2768 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2769 DRM_DEBUG_KMS("FDI train 2 done.\n");
2770 break;
2771 }
2772 }
2773 if (i == 4)
2774 DRM_ERROR("FDI train 2 fail!\n");
2775
2776 DRM_DEBUG_KMS("FDI train done.\n");
2777}
2778
2779static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2780{
2781 struct drm_device *dev = crtc->dev;
2782 struct drm_i915_private *dev_priv = dev->dev_private;
2783 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2784 int pipe = intel_crtc->pipe;
5eddb70b 2785 u32 reg, temp;
79e53945 2786
c64e311e 2787 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2788 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2789 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2790
c98e9dcf 2791 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2795 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2796 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2797 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2798
2799 POSTING_READ(reg);
c98e9dcf
JB		 2800 udelay(200);
2801
2802 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2803 temp = I915_READ(reg);
2804 I915_WRITE(reg, temp | FDI_PCDCLK);
2805
2806 POSTING_READ(reg);
c98e9dcf
JB		 2807 udelay(200);
2808
2809 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2810 reg = FDI_TX_CTL(pipe);
2811 temp = I915_READ(reg);
c98e9dcf 2812 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2813 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2814
2815 POSTING_READ(reg);
c98e9dcf 2816 udelay(100);
6be4a607 2817 }
0e23b99d
JB		 2818}
2819
291427f5
JB		 2820static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2821{
2822 struct drm_i915_private *dev_priv = dev->dev_private;
2823 u32 flags = I915_READ(SOUTH_CHICKEN1);
2824
2825 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2826 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2827 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2828 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2829 POSTING_READ(SOUTH_CHICKEN1);
2830}
0fc932b8
JB		 2831static void ironlake_fdi_disable(struct drm_crtc *crtc)
2832{
2833 struct drm_device *dev = crtc->dev;
2834 struct drm_i915_private *dev_priv = dev->dev_private;
2835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2836 int pipe = intel_crtc->pipe;
2837 u32 reg, temp;
2838
2839 /* disable CPU FDI tx and PCH FDI rx */
2840 reg = FDI_TX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2843 POSTING_READ(reg);
2844
2845 reg = FDI_RX_CTL(pipe);
2846 temp = I915_READ(reg);
2847 temp &= ~(0x7 << 16);
2848 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2849 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2850
2851 POSTING_READ(reg);
2852 udelay(100);
2853
2854 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2855 if (HAS_PCH_IBX(dev)) {
2856 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2857 I915_WRITE(FDI_RX_CHICKEN(pipe),
2858 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2859 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2860 } else if (HAS_PCH_CPT(dev)) {
2861 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2862 }
0fc932b8
JB		 2863
2864 /* still set train pattern 1 */
2865 reg = FDI_TX_CTL(pipe);
2866 temp = I915_READ(reg);
2867 temp &= ~FDI_LINK_TRAIN_NONE;
2868 temp |= FDI_LINK_TRAIN_PATTERN_1;
2869 I915_WRITE(reg, temp);
2870
2871 reg = FDI_RX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 if (HAS_PCH_CPT(dev)) {
2874 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2875 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2876 } else {
2877 temp &= ~FDI_LINK_TRAIN_NONE;
2878 temp |= FDI_LINK_TRAIN_PATTERN_1;
2879 }
2880 /* BPC in FDI rx is consistent with that in PIPECONF */
2881 temp &= ~(0x07 << 16);
2882 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2883 I915_WRITE(reg, temp);
2884
2885 POSTING_READ(reg);
2886 udelay(100);
2887}
2888
6b383a7f
CW		 2889/*
2890 * When we disable a pipe, we need to clear any pending scanline wait events
2891 * to avoid hanging the ring, which we assume we are waiting on.
2892 */
2893static void intel_clear_scanline_wait(struct drm_device *dev)
2894{
2895 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2896 struct intel_ring_buffer *ring;
6b383a7f
CW		 2897 u32 tmp;
2898
2899 if (IS_GEN2(dev))
2900 /* Can't break the hang on i8xx */
2901 return;
2902
1ec14ad3 2903 ring = LP_RING(dev_priv);
8168bd48
CW		 2904 tmp = I915_READ_CTL(ring);
2905 if (tmp & RING_WAIT)
2906 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2907}
2908
e6c3a2a6
CW		 2909static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2910{
05394f39 2911 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2912 struct drm_i915_private *dev_priv;
2913
2914 if (crtc->fb == NULL)
2915 return;
2916
05394f39 2917 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2918 dev_priv = crtc->dev->dev_private;
2919 wait_event(dev_priv->pending_flip_queue,
05394f39 2920 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2921}
2922
040484af
JB		 2923static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2924{
2925 struct drm_device *dev = crtc->dev;
2926 struct drm_mode_config *mode_config = &dev->mode_config;
2927 struct intel_encoder *encoder;
2928
2929 /*
2930 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2931 * must be driven by its own crtc; no sharing is possible.
2932 */
2933 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2934 if (encoder->base.crtc != crtc)
2935 continue;
2936
2937 switch (encoder->type) {
2938 case INTEL_OUTPUT_EDP:
2939 if (!intel_encoder_is_pch_edp(&encoder->base))
2940 return false;
2941 continue;
2942 }
2943 }
2944
2945 return true;
2946}
2947
f67a559d
JB		 2948/*
2949 * Enable PCH resources required for PCH ports:
2950 * - PCH PLLs
2951 * - FDI training & RX/TX
2952 * - update transcoder timings
2953 * - DP transcoding bits
2954 * - transcoder
2955 */
2956static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2957{
2958 struct drm_device *dev = crtc->dev;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2961 int pipe = intel_crtc->pipe;
4b645f14 2962 u32 reg, temp, transc_sel;
2c07245f 2963
c98e9dcf 2964 /* For PCH output, training FDI link */
674cf967 2965 dev_priv->display.fdi_link_train(crtc);
2c07245f 2966
92f2584a 2967 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2968
c98e9dcf 2969 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2970 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2971 TRANSC_DPLLB_SEL;
2972
c98e9dcf
JB		 2973 /* Be sure PCH DPLL SEL is set */
2974 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 2975 if (pipe == 0) {
2976 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 2977 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 2978 } else if (pipe == 1) {
2979 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 2980 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 2981 } else if (pipe == 2) {
2982 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 2983 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 2984 }
c98e9dcf 2985 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2986 }
5eddb70b 2987
d9b6cb56
JB		 2988 /* set transcoder timing, panel must allow it */
2989 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2990 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2991 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2992 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2993
5eddb70b
CW		 2994 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2995 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2996 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2997 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2998
5e84e1a4
ZW		 2999 intel_fdi_normal_train(crtc);
3000
c98e9dcf
JB		 3001 /* For PCH DP, enable TRANS_DP_CTL */
3002 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3003 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3004 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3005 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3006 reg = TRANS_DP_CTL(pipe);
3007 temp = I915_READ(reg);
3008 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3009 TRANS_DP_SYNC_MASK |
3010 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3011 temp |= (TRANS_DP_OUTPUT_ENABLE |
3012 TRANS_DP_ENH_FRAMING);
9325c9f0 3013 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3014
3015 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3016 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3017 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3018 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3019
3020 switch (intel_trans_dp_port_sel(crtc)) {
3021 case PCH_DP_B:
5eddb70b 3022 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3023 break;
3024 case PCH_DP_C:
5eddb70b 3025 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3026 break;
3027 case PCH_DP_D:
5eddb70b 3028 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3029 break;
3030 default:
3031 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3032 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3033 break;
32f9d658 3034 }
2c07245f 3035
5eddb70b 3036 I915_WRITE(reg, temp);
6be4a607 3037 }
b52eb4dc 3038
040484af 3039 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3040}
3041
d4270e57
JB		 3042void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3043{
3044 struct drm_i915_private *dev_priv = dev->dev_private;
3045 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3046 u32 temp;
3047
3048 temp = I915_READ(dslreg);
3049 udelay(500);
3050 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3051 /* Without this, mode sets may fail silently on FDI */
3052 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3053 udelay(250);
3054 I915_WRITE(tc2reg, 0);
3055 if (wait_for(I915_READ(dslreg) != temp, 5))
3056 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3057 }
3058}
3059
f67a559d
JB		 3060static void ironlake_crtc_enable(struct drm_crtc *crtc)
3061{
3062 struct drm_device *dev = crtc->dev;
3063 struct drm_i915_private *dev_priv = dev->dev_private;
3064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3065 int pipe = intel_crtc->pipe;
3066 int plane = intel_crtc->plane;
3067 u32 temp;
3068 bool is_pch_port;
3069
3070 if (intel_crtc->active)
3071 return;
3072
3073 intel_crtc->active = true;
3074 intel_update_watermarks(dev);
3075
3076 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3077 temp = I915_READ(PCH_LVDS);
3078 if ((temp & LVDS_PORT_EN) == 0)
3079 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3080 }
3081
3082 is_pch_port = intel_crtc_driving_pch(crtc);
3083
3084 if (is_pch_port)
357555c0 3085 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3086 else
3087 ironlake_fdi_disable(crtc);
3088
3089 /* Enable panel fitting for LVDS */
3090 if (dev_priv->pch_pf_size &&
3091 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3092 /* Force use of hard-coded filter coefficients
3093 * as some pre-programmed values are broken,
3094 * e.g. x201.
3095 */
9db4a9c7
JB		 3096 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3097 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3098 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3099 }
3100
9c54c0dd
JB		 3101 /*
3102 * On ILK+ LUT must be loaded before the pipe is running but with
3103 * clocks enabled
3104 */
3105 intel_crtc_load_lut(crtc);
3106
f67a559d
JB		 3107 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3108 intel_enable_plane(dev_priv, plane, pipe);
3109
3110 if (is_pch_port)
3111 ironlake_pch_enable(crtc);
c98e9dcf 3112
d1ebd816 3113 mutex_lock(&dev->struct_mutex);
bed4a673 3114 intel_update_fbc(dev);
d1ebd816
BW		 3115 mutex_unlock(&dev->struct_mutex);
3116
6b383a7f 3117 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3118}
3119
3120static void ironlake_crtc_disable(struct drm_crtc *crtc)
3121{
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3125 int pipe = intel_crtc->pipe;
3126 int plane = intel_crtc->plane;
5eddb70b 3127 u32 reg, temp;
b52eb4dc 3128
f7abfe8b
CW		 3129 if (!intel_crtc->active)
3130 return;
3131
e6c3a2a6 3132 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3133 drm_vblank_off(dev, pipe);
6b383a7f 3134 intel_crtc_update_cursor(crtc, false);
5eddb70b 3135
b24e7179 3136 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3137
973d04f9
CW		 3138 if (dev_priv->cfb_plane == plane)
3139 intel_disable_fbc(dev);
2c07245f 3140
b24e7179 3141 intel_disable_pipe(dev_priv, pipe);
32f9d658 3142
6be4a607 3143 /* Disable PF */
9db4a9c7
JB		 3144 I915_WRITE(PF_CTL(pipe), 0);
3145 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3146
0fc932b8 3147 ironlake_fdi_disable(crtc);
2c07245f 3148
47a05eca
JB		 3149 /* This is a horrible layering violation; we should be doing this in
3150 * the connector/encoder ->prepare instead, but we don't always have
3151 * enough information there about the config to know whether it will
3152 * actually be necessary or just cause undesired flicker.
3153 */
3154 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3155
040484af 3156 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3157
6be4a607
JB		 3158 if (HAS_PCH_CPT(dev)) {
3159 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3160 reg = TRANS_DP_CTL(pipe);
3161 temp = I915_READ(reg);
3162 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3163 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3164 I915_WRITE(reg, temp);
6be4a607
JB		 3165
3166 /* disable DPLL_SEL */
3167 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3168 switch (pipe) {
3169 case 0:
d64311ab 3170 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3171 break;
3172 case 1:
6be4a607 3173 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3174 break;
3175 case 2:
4b645f14 3176 /* C shares PLL A or B */
d64311ab 3177 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3178 break;
3179 default:
3180 BUG(); /* wtf */
3181 }
6be4a607 3182 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3183 }
e3421a18 3184
6be4a607 3185 /* disable PCH DPLL */
4b645f14
JB		 3186 if (!intel_crtc->no_pll)
3187 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3188
6be4a607 3189 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3190 reg = FDI_RX_CTL(pipe);
3191 temp = I915_READ(reg);
3192 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3193
6be4a607 3194 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3195 reg = FDI_TX_CTL(pipe);
3196 temp = I915_READ(reg);
3197 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3198
3199 POSTING_READ(reg);
6be4a607 3200 udelay(100);
8db9d77b 3201
5eddb70b
CW		 3202 reg = FDI_RX_CTL(pipe);
3203 temp = I915_READ(reg);
3204 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3205
6be4a607 3206 /* Wait for the clocks to turn off. */
5eddb70b 3207 POSTING_READ(reg);
6be4a607 3208 udelay(100);
6b383a7f 3209
f7abfe8b 3210 intel_crtc->active = false;
6b383a7f 3211 intel_update_watermarks(dev);
d1ebd816
BW		 3212
3213 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3214 intel_update_fbc(dev);
3215 intel_clear_scanline_wait(dev);
d1ebd816 3216 mutex_unlock(&dev->struct_mutex);
6be4a607 3217}
1b3c7a47 3218
6be4a607
JB		 3219static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3220{
3221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3222 int pipe = intel_crtc->pipe;
3223 int plane = intel_crtc->plane;
8db9d77b 3224
6be4a607
JB		 3225 /* XXX: When our outputs are all unaware of DPMS modes other than off
3226 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3227 */
3228 switch (mode) {
3229 case DRM_MODE_DPMS_ON:
3230 case DRM_MODE_DPMS_STANDBY:
3231 case DRM_MODE_DPMS_SUSPEND:
3232 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3233 ironlake_crtc_enable(crtc);
3234 break;
1b3c7a47 3235
6be4a607
JB		 3236 case DRM_MODE_DPMS_OFF:
3237 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3238 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3239 break;
3240 }
3241}
3242
02e792fb
DV		 3243static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3244{
02e792fb 3245 if (!enable && intel_crtc->overlay) {
23f09ce3 3246 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3247 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3248
23f09ce3 3249 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3250 dev_priv->mm.interruptible = false;
3251 (void) intel_overlay_switch_off(intel_crtc->overlay);
3252 dev_priv->mm.interruptible = true;
23f09ce3 3253 mutex_unlock(&dev->struct_mutex);
02e792fb 3254 }
02e792fb 3255
5dcdbcb0
CW		 3256 /* Let userspace switch the overlay on again. In most cases userspace
3257 * has to recompute where to put it anyway.
3258 */
02e792fb
DV		 3259}
3260
0b8765c6 3261static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3262{
3263 struct drm_device *dev = crtc->dev;
79e53945
JB		 3264 struct drm_i915_private *dev_priv = dev->dev_private;
3265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3266 int pipe = intel_crtc->pipe;
80824003 3267 int plane = intel_crtc->plane;
79e53945 3268
f7abfe8b
CW		 3269 if (intel_crtc->active)
3270 return;
3271
3272 intel_crtc->active = true;
6b383a7f
CW		 3273 intel_update_watermarks(dev);
3274
63d7bbe9 3275 intel_enable_pll(dev_priv, pipe);
040484af 3276 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3277 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3278
0b8765c6 3279 intel_crtc_load_lut(crtc);
bed4a673 3280 intel_update_fbc(dev);
79e53945 3281
0b8765c6
JB		 3282 /* Give the overlay scaler a chance to enable if it's on this pipe */
3283 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3284 intel_crtc_update_cursor(crtc, true);
0b8765c6 3285}
79e53945 3286
0b8765c6
JB		 3287static void i9xx_crtc_disable(struct drm_crtc *crtc)
3288{
3289 struct drm_device *dev = crtc->dev;
3290 struct drm_i915_private *dev_priv = dev->dev_private;
3291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
b690e96c 3294
f7abfe8b
CW		 3295 if (!intel_crtc->active)
3296 return;
3297
0b8765c6 3298 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3299 intel_crtc_wait_for_pending_flips(crtc);
3300 drm_vblank_off(dev, pipe);
0b8765c6 3301 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3302 intel_crtc_update_cursor(crtc, false);
0b8765c6 3303
973d04f9
CW		 3304 if (dev_priv->cfb_plane == plane)
3305 intel_disable_fbc(dev);
79e53945 3306
b24e7179 3307 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3308 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3309 intel_disable_pll(dev_priv, pipe);
0b8765c6 3310
f7abfe8b 3311 intel_crtc->active = false;
6b383a7f
CW		 3312 intel_update_fbc(dev);
3313 intel_update_watermarks(dev);
3314 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3315}
3316
3317static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3318{
3319 /* XXX: When our outputs are all unaware of DPMS modes other than off
3320 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3321 */
3322 switch (mode) {
3323 case DRM_MODE_DPMS_ON:
3324 case DRM_MODE_DPMS_STANDBY:
3325 case DRM_MODE_DPMS_SUSPEND:
3326 i9xx_crtc_enable(crtc);
3327 break;
3328 case DRM_MODE_DPMS_OFF:
3329 i9xx_crtc_disable(crtc);
79e53945
JB		 3330 break;
3331 }
2c07245f
ZW		 3332}
3333
3334/**
3335 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3336 */
3337static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3338{
3339 struct drm_device *dev = crtc->dev;
e70236a8 3340 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3341 struct drm_i915_master_private *master_priv;
3342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3343 int pipe = intel_crtc->pipe;
3344 bool enabled;
3345
032d2a0d
CW		 3346 if (intel_crtc->dpms_mode == mode)
3347 return;
3348
65655d4a 3349 intel_crtc->dpms_mode = mode;
debcaddc 3350
e70236a8 3351 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3352
3353 if (!dev->primary->master)
3354 return;
3355
3356 master_priv = dev->primary->master->driver_priv;
3357 if (!master_priv->sarea_priv)
3358 return;
3359
3360 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3361
3362 switch (pipe) {
3363 case 0:
3364 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3365 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3366 break;
3367 case 1:
3368 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3369 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3370 break;
3371 default:
9db4a9c7 3372 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3373 break;
3374 }
79e53945
JB		 3375}
3376
cdd59983
CW		 3377static void intel_crtc_disable(struct drm_crtc *crtc)
3378{
3379 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3380 struct drm_device *dev = crtc->dev;
3381
3382 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
931872fc
CW		 3383 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3384 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3385
3386 if (crtc->fb) {
3387 mutex_lock(&dev->struct_mutex);
1690e1eb 3388 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3389 mutex_unlock(&dev->struct_mutex);
3390 }
3391}
3392
7e7d76c3
JB		 3393/* Prepare for a mode set.
3394 *
3395 * Note we could be a lot smarter here. We need to figure out which outputs
3396 * will be enabled, which disabled (in short, how the config will changes)
3397 * and perform the minimum necessary steps to accomplish that, e.g. updating
3398 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3399 * panel fitting is in the proper state, etc.
3400 */
3401static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3402{
7e7d76c3 3403 i9xx_crtc_disable(crtc);
79e53945
JB		 3404}
3405
7e7d76c3 3406static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3407{
7e7d76c3 3408 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3409}
3410
3411static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3412{
7e7d76c3 3413 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3414}
3415
3416static void ironlake_crtc_commit(struct drm_crtc *crtc)
3417{
7e7d76c3 3418 ironlake_crtc_enable(crtc);
79e53945
JB		 3419}
3420
0206e353 3421void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3422{
3423 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3424 /* lvds has its own version of prepare see intel_lvds_prepare */
3425 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3426}
3427
0206e353 3428void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3429{
3430 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3431 struct drm_device *dev = encoder->dev;
3432 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3433 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3434
79e53945
JB		 3435 /* lvds has its own version of commit see intel_lvds_commit */
3436 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3437
3438 if (HAS_PCH_CPT(dev))
3439 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3440}
3441
ea5b213a
CW		 3442void intel_encoder_destroy(struct drm_encoder *encoder)
3443{
4ef69c7a 3444 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3445
ea5b213a
CW		 3446 drm_encoder_cleanup(encoder);
3447 kfree(intel_encoder);
3448}
3449
79e53945
JB		 3450static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3451 struct drm_display_mode *mode,
3452 struct drm_display_mode *adjusted_mode)
3453{
2c07245f 3454 struct drm_device *dev = crtc->dev;
89749350 3455
bad720ff 3456 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3457 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3458 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3459 return false;
2c07245f 3460 }
89749350 3461
ca9bfa7e
DV		 3462 /* All interlaced capable intel hw wants timings in frames. */
3463 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3464
79e53945
JB		 3465 return true;
3466}
3467
e70236a8
JB		 3468static int i945_get_display_clock_speed(struct drm_device *dev)
3469{
3470 return 400000;
3471}
79e53945 3472
e70236a8 3473static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3474{
e70236a8
JB		 3475 return 333000;
3476}
79e53945 3477
e70236a8
JB		 3478static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3479{
3480 return 200000;
3481}
79e53945 3482
e70236a8
JB		 3483static int i915gm_get_display_clock_speed(struct drm_device *dev)
3484{
3485 u16 gcfgc = 0;
79e53945 3486
e70236a8
JB		 3487 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3488
3489 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3490 return 133000;
3491 else {
3492 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3493 case GC_DISPLAY_CLOCK_333_MHZ:
3494 return 333000;
3495 default:
3496 case GC_DISPLAY_CLOCK_190_200_MHZ:
3497 return 190000;
79e53945 3498 }
e70236a8
JB		 3499 }
3500}
3501
3502static int i865_get_display_clock_speed(struct drm_device *dev)
3503{
3504 return 266000;
3505}
3506
3507static int i855_get_display_clock_speed(struct drm_device *dev)
3508{
3509 u16 hpllcc = 0;
3510 /* Assume that the hardware is in the high speed state. This
3511 * should be the default.
3512 */
3513 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3514 case GC_CLOCK_133_200:
3515 case GC_CLOCK_100_200:
3516 return 200000;
3517 case GC_CLOCK_166_250:
3518 return 250000;
3519 case GC_CLOCK_100_133:
79e53945 3520 return 133000;
e70236a8 3521 }
79e53945 3522
e70236a8
JB		 3523 /* Shouldn't happen */
3524 return 0;
3525}
79e53945 3526
e70236a8
JB		 3527static int i830_get_display_clock_speed(struct drm_device *dev)
3528{
3529 return 133000;
79e53945
JB		 3530}
3531
2c07245f
ZW		 3532struct fdi_m_n {
3533 u32 tu;
3534 u32 gmch_m;
3535 u32 gmch_n;
3536 u32 link_m;
3537 u32 link_n;
3538};
3539
3540static void
3541fdi_reduce_ratio(u32 *num, u32 *den)
3542{
3543 while (*num > 0xffffff || *den > 0xffffff) {
3544 *num >>= 1;
3545 *den >>= 1;
3546 }
3547}
3548
2c07245f 3549static void
f2b115e6
AJ		 3550ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3551 int link_clock, struct fdi_m_n *m_n)
2c07245f 3552{
2c07245f
ZW		 3553 m_n->tu = 64; /* default size */
3554
22ed1113
CW		 3555 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3556 m_n->gmch_m = bits_per_pixel * pixel_clock;
3557 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3558 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3559
22ed1113
CW		 3560 m_n->link_m = pixel_clock;
3561 m_n->link_n = link_clock;
2c07245f
ZW		 3562 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3563}
3564
3565
7662c8bd
SL		 3566struct intel_watermark_params {
3567 unsigned long fifo_size;
3568 unsigned long max_wm;
3569 unsigned long default_wm;
3570 unsigned long guard_size;
3571 unsigned long cacheline_size;
3572};
3573
f2b115e6 3574/* Pineview has different values for various configs */
d210246a 3575static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3576 PINEVIEW_DISPLAY_FIFO,
3577 PINEVIEW_MAX_WM,
3578 PINEVIEW_DFT_WM,
3579 PINEVIEW_GUARD_WM,
3580 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3581};
d210246a 3582static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3583 PINEVIEW_DISPLAY_FIFO,
3584 PINEVIEW_MAX_WM,
3585 PINEVIEW_DFT_HPLLOFF_WM,
3586 PINEVIEW_GUARD_WM,
3587 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3588};
d210246a 3589static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3590 PINEVIEW_CURSOR_FIFO,
3591 PINEVIEW_CURSOR_MAX_WM,
3592 PINEVIEW_CURSOR_DFT_WM,
3593 PINEVIEW_CURSOR_GUARD_WM,
3594 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3595};
d210246a 3596static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3597 PINEVIEW_CURSOR_FIFO,
3598 PINEVIEW_CURSOR_MAX_WM,
3599 PINEVIEW_CURSOR_DFT_WM,
3600 PINEVIEW_CURSOR_GUARD_WM,
3601 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3602};
d210246a 3603static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3604 G4X_FIFO_SIZE,
3605 G4X_MAX_WM,
3606 G4X_MAX_WM,
3607 2,
3608 G4X_FIFO_LINE_SIZE,
3609};
d210246a 3610static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3611 I965_CURSOR_FIFO,
3612 I965_CURSOR_MAX_WM,
3613 I965_CURSOR_DFT_WM,
3614 2,
3615 G4X_FIFO_LINE_SIZE,
3616};
d210246a 3617static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3618 I965_CURSOR_FIFO,
3619 I965_CURSOR_MAX_WM,
3620 I965_CURSOR_DFT_WM,
3621 2,
3622 I915_FIFO_LINE_SIZE,
3623};
d210246a 3624static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3625 I945_FIFO_SIZE,
7662c8bd
SL		 3626 I915_MAX_WM,
3627 1,
dff33cfc
JB		 3628 2,
3629 I915_FIFO_LINE_SIZE
7662c8bd 3630};
d210246a 3631static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3632 I915_FIFO_SIZE,
7662c8bd
SL		 3633 I915_MAX_WM,
3634 1,
dff33cfc 3635 2,
7662c8bd
SL		 3636 I915_FIFO_LINE_SIZE
3637};
d210246a 3638static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3639 I855GM_FIFO_SIZE,
3640 I915_MAX_WM,
3641 1,
dff33cfc 3642 2,
7662c8bd
SL		 3643 I830_FIFO_LINE_SIZE
3644};
d210246a 3645static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3646 I830_FIFO_SIZE,
3647 I915_MAX_WM,
3648 1,
dff33cfc 3649 2,
7662c8bd
SL		 3650 I830_FIFO_LINE_SIZE
3651};
3652
d210246a 3653static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3654 ILK_DISPLAY_FIFO,
3655 ILK_DISPLAY_MAXWM,
3656 ILK_DISPLAY_DFTWM,
3657 2,
3658 ILK_FIFO_LINE_SIZE
3659};
d210246a 3660static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3661 ILK_CURSOR_FIFO,
3662 ILK_CURSOR_MAXWM,
3663 ILK_CURSOR_DFTWM,
3664 2,
3665 ILK_FIFO_LINE_SIZE
3666};
d210246a 3667static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3668 ILK_DISPLAY_SR_FIFO,
3669 ILK_DISPLAY_MAX_SRWM,
3670 ILK_DISPLAY_DFT_SRWM,
3671 2,
3672 ILK_FIFO_LINE_SIZE
3673};
d210246a 3674static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3675 ILK_CURSOR_SR_FIFO,
3676 ILK_CURSOR_MAX_SRWM,
3677 ILK_CURSOR_DFT_SRWM,
3678 2,
3679 ILK_FIFO_LINE_SIZE
3680};
3681
d210246a 3682static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3683 SNB_DISPLAY_FIFO,
3684 SNB_DISPLAY_MAXWM,
3685 SNB_DISPLAY_DFTWM,
3686 2,
3687 SNB_FIFO_LINE_SIZE
3688};
d210246a 3689static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3690 SNB_CURSOR_FIFO,
3691 SNB_CURSOR_MAXWM,
3692 SNB_CURSOR_DFTWM,
3693 2,
3694 SNB_FIFO_LINE_SIZE
3695};
d210246a 3696static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3697 SNB_DISPLAY_SR_FIFO,
3698 SNB_DISPLAY_MAX_SRWM,
3699 SNB_DISPLAY_DFT_SRWM,
3700 2,
3701 SNB_FIFO_LINE_SIZE
3702};
d210246a 3703static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3704 SNB_CURSOR_SR_FIFO,
3705 SNB_CURSOR_MAX_SRWM,
3706 SNB_CURSOR_DFT_SRWM,
3707 2,
3708 SNB_FIFO_LINE_SIZE
3709};
3710
3711
dff33cfc
JB		 3712/**
3713 * intel_calculate_wm - calculate watermark level
3714 * @clock_in_khz: pixel clock
3715 * @wm: chip FIFO params
3716 * @pixel_size: display pixel size
3717 * @latency_ns: memory latency for the platform
3718 *
3719 * Calculate the watermark level (the level at which the display plane will
3720 * start fetching from memory again). Each chip has a different display
3721 * FIFO size and allocation, so the caller needs to figure that out and pass
3722 * in the correct intel_watermark_params structure.
3723 *
3724 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3725 * on the pixel size. When it reaches the watermark level, it'll start
3726 * fetching FIFO line sized based chunks from memory until the FIFO fills
3727 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3728 * will occur, and a display engine hang could result.
3729 */
7662c8bd 3730static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3731 const struct intel_watermark_params *wm,
3732 int fifo_size,
7662c8bd
SL		 3733 int pixel_size,
3734 unsigned long latency_ns)
3735{
390c4dd4 3736 long entries_required, wm_size;
dff33cfc 3737
d660467c
JB		 3738 /*
3739 * Note: we need to make sure we don't overflow for various clock &
3740 * latency values.
3741 * clocks go from a few thousand to several hundred thousand.
3742 * latency is usually a few thousand
3743 */
3744 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3745 1000;
8de9b311 3746 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3747
bbb0aef5 3748 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3749
d210246a 3750 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3751
bbb0aef5 3752 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3753
390c4dd4
JB		 3754 /* Don't promote wm_size to unsigned... */
3755 if (wm_size > (long)wm->max_wm)
7662c8bd 3756 wm_size = wm->max_wm;
c3add4b6 3757 if (wm_size <= 0)
7662c8bd
SL		 3758 wm_size = wm->default_wm;
3759 return wm_size;
3760}
3761
3762struct cxsr_latency {
3763 int is_desktop;
95534263 3764 int is_ddr3;
7662c8bd
SL		 3765 unsigned long fsb_freq;
3766 unsigned long mem_freq;
3767 unsigned long display_sr;
3768 unsigned long display_hpll_disable;
3769 unsigned long cursor_sr;
3770 unsigned long cursor_hpll_disable;
3771};
3772
403c89ff 3773static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3774 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3775 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3776 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3777 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3778 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3779
3780 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3781 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3782 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3783 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3784 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3785
3786 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3787 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3788 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3789 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3790 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3791
3792 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3793 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3794 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3795 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3796 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3797
3798 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3799 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3800 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3801 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3802 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3803
3804 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3805 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3806 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3807 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3808 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3809};
3810
403c89ff
CW		 3811static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3812 int is_ddr3,
3813 int fsb,
3814 int mem)
7662c8bd 3815{
403c89ff 3816 const struct cxsr_latency *latency;
7662c8bd 3817 int i;
7662c8bd
SL		 3818
3819 if (fsb == 0 || mem == 0)
3820 return NULL;
3821
3822 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3823 latency = &cxsr_latency_table[i];
3824 if (is_desktop == latency->is_desktop &&
95534263 3825 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3826 fsb == latency->fsb_freq && mem == latency->mem_freq)
3827 return latency;
7662c8bd 3828 }
decbbcda 3829
28c97730 3830 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3831
3832 return NULL;
7662c8bd
SL		 3833}
3834
f2b115e6 3835static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3836{
3837 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3838
3839 /* deactivate cxsr */
3e33d94d 3840 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3841}
3842
bcc24fb4
JB		 3843/*
3844 * Latency for FIFO fetches is dependent on several factors:
3845 * - memory configuration (speed, channels)
3846 * - chipset
3847 * - current MCH state
3848 * It can be fairly high in some situations, so here we assume a fairly
3849 * pessimal value. It's a tradeoff between extra memory fetches (if we
3850 * set this value too high, the FIFO will fetch frequently to stay full)
3851 * and power consumption (set it too low to save power and we might see
3852 * FIFO underruns and display "flicker").
3853 *
3854 * A value of 5us seems to be a good balance; safe for very low end
3855 * platforms but not overly aggressive on lower latency configs.
3856 */
69e302a9 3857static const int latency_ns = 5000;
7662c8bd 3858
e70236a8 3859static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3860{
3861 struct drm_i915_private *dev_priv = dev->dev_private;
3862 uint32_t dsparb = I915_READ(DSPARB);
3863 int size;
3864
8de9b311
CW		 3865 size = dsparb & 0x7f;
3866 if (plane)
3867 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3868
28c97730 3869 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3870 plane ? "B" : "A", size);
dff33cfc
JB		 3871
3872 return size;
3873}
7662c8bd 3874
e70236a8
JB		 3875static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3876{
3877 struct drm_i915_private *dev_priv = dev->dev_private;
3878 uint32_t dsparb = I915_READ(DSPARB);
3879 int size;
3880
8de9b311
CW		 3881 size = dsparb & 0x1ff;
3882 if (plane)
3883 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3884 size >>= 1; /* Convert to cachelines */
dff33cfc 3885
28c97730 3886 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3887 plane ? "B" : "A", size);
dff33cfc
JB		 3888
3889 return size;
3890}
7662c8bd 3891
e70236a8
JB		 3892static int i845_get_fifo_size(struct drm_device *dev, int plane)
3893{
3894 struct drm_i915_private *dev_priv = dev->dev_private;
3895 uint32_t dsparb = I915_READ(DSPARB);
3896 int size;
3897
3898 size = dsparb & 0x7f;
3899 size >>= 2; /* Convert to cachelines */
3900
28c97730 3901 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3902 plane ? "B" : "A",
3903 size);
e70236a8
JB		 3904
3905 return size;
3906}
3907
3908static int i830_get_fifo_size(struct drm_device *dev, int plane)
3909{
3910 struct drm_i915_private *dev_priv = dev->dev_private;
3911 uint32_t dsparb = I915_READ(DSPARB);
3912 int size;
3913
3914 size = dsparb & 0x7f;
3915 size >>= 1; /* Convert to cachelines */
3916
28c97730 3917 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3918 plane ? "B" : "A", size);
e70236a8
JB		 3919
3920 return size;
3921}
3922
d210246a
CW		 3923static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3924{
3925 struct drm_crtc *crtc, *enabled = NULL;
3926
3927 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3928 if (crtc->enabled && crtc->fb) {
3929 if (enabled)
3930 return NULL;
3931 enabled = crtc;
3932 }
3933 }
3934
3935 return enabled;
3936}
3937
3938static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3939{
3940 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3941 struct drm_crtc *crtc;
403c89ff 3942 const struct cxsr_latency *latency;
d4294342
ZY		 3943 u32 reg;
3944 unsigned long wm;
d4294342 3945
403c89ff 3946 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3947 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3948 if (!latency) {
3949 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3950 pineview_disable_cxsr(dev);
3951 return;
3952 }
3953
d210246a
CW		 3954 crtc = single_enabled_crtc(dev);
3955 if (crtc) {
3956 int clock = crtc->mode.clock;
3957 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3958
3959 /* Display SR */
d210246a
CW		 3960 wm = intel_calculate_wm(clock, &pineview_display_wm,
3961 pineview_display_wm.fifo_size,
d4294342
ZY		 3962 pixel_size, latency->display_sr);
3963 reg = I915_READ(DSPFW1);
3964 reg &= ~DSPFW_SR_MASK;
3965 reg |= wm << DSPFW_SR_SHIFT;
3966 I915_WRITE(DSPFW1, reg);
3967 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3968
3969 /* cursor SR */
d210246a
CW		 3970 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3971 pineview_display_wm.fifo_size,
d4294342
ZY		 3972 pixel_size, latency->cursor_sr);
3973 reg = I915_READ(DSPFW3);
3974 reg &= ~DSPFW_CURSOR_SR_MASK;
3975 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3976 I915_WRITE(DSPFW3, reg);
3977
3978 /* Display HPLL off SR */
d210246a
CW		 3979 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3980 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3981 pixel_size, latency->display_hpll_disable);
3982 reg = I915_READ(DSPFW3);
3983 reg &= ~DSPFW_HPLL_SR_MASK;
3984 reg |= wm & DSPFW_HPLL_SR_MASK;
3985 I915_WRITE(DSPFW3, reg);
3986
3987 /* cursor HPLL off SR */
d210246a
CW		 3988 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3989 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3990 pixel_size, latency->cursor_hpll_disable);
3991 reg = I915_READ(DSPFW3);
3992 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3993 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3994 I915_WRITE(DSPFW3, reg);
3995 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3996
3997 /* activate cxsr */
3e33d94d
CW		 3998 I915_WRITE(DSPFW3,
3999 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 4000 DRM_DEBUG_KMS("Self-refresh is enabled\n");
4001 } else {
4002 pineview_disable_cxsr(dev);
4003 DRM_DEBUG_KMS("Self-refresh is disabled\n");
4004 }
4005}
4006
417ae147
CW		 4007static bool g4x_compute_wm0(struct drm_device *dev,
4008 int plane,
4009 const struct intel_watermark_params *display,
4010 int display_latency_ns,
4011 const struct intel_watermark_params *cursor,
4012 int cursor_latency_ns,
4013 int *plane_wm,
4014 int *cursor_wm)
4015{
4016 struct drm_crtc *crtc;
4017 int htotal, hdisplay, clock, pixel_size;
4018 int line_time_us, line_count;
4019 int entries, tlb_miss;
4020
4021 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 4022 if (crtc->fb == NULL || !crtc->enabled) {
4023 *cursor_wm = cursor->guard_size;
4024 *plane_wm = display->guard_size;
417ae147 4025 return false;
5c72d064 4026 }
417ae147
CW		 4027
4028 htotal = crtc->mode.htotal;
4029 hdisplay = crtc->mode.hdisplay;
4030 clock = crtc->mode.clock;
4031 pixel_size = crtc->fb->bits_per_pixel / 8;
4032
4033 /* Use the small buffer method to calculate plane watermark */
4034 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4035 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4036 if (tlb_miss > 0)
4037 entries += tlb_miss;
4038 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4039 *plane_wm = entries + display->guard_size;
4040 if (*plane_wm > (int)display->max_wm)
4041 *plane_wm = display->max_wm;
4042
4043 /* Use the large buffer method to calculate cursor watermark */
4044 line_time_us = ((htotal * 1000) / clock);
4045 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4046 entries = line_count * 64 * pixel_size;
4047 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4048 if (tlb_miss > 0)
4049 entries += tlb_miss;
4050 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4051 *cursor_wm = entries + cursor->guard_size;
4052 if (*cursor_wm > (int)cursor->max_wm)
4053 *cursor_wm = (int)cursor->max_wm;
4054
4055 return true;
4056}
4057
4058/*
4059 * Check the wm result.
4060 *
4061 * If any calculated watermark values is larger than the maximum value that
4062 * can be programmed into the associated watermark register, that watermark
4063 * must be disabled.
4064 */
4065static bool g4x_check_srwm(struct drm_device *dev,
4066 int display_wm, int cursor_wm,
4067 const struct intel_watermark_params *display,
4068 const struct intel_watermark_params *cursor)
652c393a 4069{
417ae147
CW		 4070 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4071 display_wm, cursor_wm);
652c393a 4072
417ae147 4073 if (display_wm > display->max_wm) {
bbb0aef5 4074 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4075 display_wm, display->max_wm);
4076 return false;
4077 }
0e442c60 4078
417ae147 4079 if (cursor_wm > cursor->max_wm) {
bbb0aef5 4080 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4081 cursor_wm, cursor->max_wm);
4082 return false;
4083 }
0e442c60 4084
417ae147
CW		 4085 if (!(display_wm || cursor_wm)) {
4086 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4087 return false;
4088 }
0e442c60 4089
417ae147
CW		 4090 return true;
4091}
0e442c60 4092
417ae147 4093static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 4094 int plane,
4095 int latency_ns,
417ae147
CW		 4096 const struct intel_watermark_params *display,
4097 const struct intel_watermark_params *cursor,
4098 int *display_wm, int *cursor_wm)
4099{
d210246a
CW		 4100 struct drm_crtc *crtc;
4101 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4102 unsigned long line_time_us;
4103 int line_count, line_size;
4104 int small, large;
4105 int entries;
0e442c60 4106
417ae147
CW		 4107 if (!latency_ns) {
4108 *display_wm = *cursor_wm = 0;
4109 return false;
4110 }
0e442c60 4111
d210246a
CW		 4112 crtc = intel_get_crtc_for_plane(dev, plane);
4113 hdisplay = crtc->mode.hdisplay;
4114 htotal = crtc->mode.htotal;
4115 clock = crtc->mode.clock;
4116 pixel_size = crtc->fb->bits_per_pixel / 8;
4117
417ae147
CW		 4118 line_time_us = (htotal * 1000) / clock;
4119 line_count = (latency_ns / line_time_us + 1000) / 1000;
4120 line_size = hdisplay * pixel_size;
0e442c60 4121
417ae147
CW		 4122 /* Use the minimum of the small and large buffer method for primary */
4123 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4124 large = line_count * line_size;
0e442c60 4125
417ae147
CW		 4126 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4127 *display_wm = entries + display->guard_size;
4fe5e611 4128
417ae147
CW		 4129 /* calculate the self-refresh watermark for display cursor */
4130 entries = line_count * pixel_size * 64;
4131 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4132 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4133
417ae147
CW		 4134 return g4x_check_srwm(dev,
4135 *display_wm, *cursor_wm,
4136 display, cursor);
4137}
4fe5e611 4138
7ccb4a53 4139#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4140
4141static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4142{
4143 static const int sr_latency_ns = 12000;
4144 struct drm_i915_private *dev_priv = dev->dev_private;
4145 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4146 int plane_sr, cursor_sr;
4147 unsigned int enabled = 0;
417ae147
CW		 4148
4149 if (g4x_compute_wm0(dev, 0,
4150 &g4x_wm_info, latency_ns,
4151 &g4x_cursor_wm_info, latency_ns,
4152 &planea_wm, &cursora_wm))
d210246a 4153 enabled |= 1;
417ae147
CW		 4154
4155 if (g4x_compute_wm0(dev, 1,
4156 &g4x_wm_info, latency_ns,
4157 &g4x_cursor_wm_info, latency_ns,
4158 &planeb_wm, &cursorb_wm))
d210246a 4159 enabled |= 2;
417ae147
CW		 4160
4161 plane_sr = cursor_sr = 0;
d210246a
CW		 4162 if (single_plane_enabled(enabled) &&
4163 g4x_compute_srwm(dev, ffs(enabled) - 1,
4164 sr_latency_ns,
417ae147
CW		 4165 &g4x_wm_info,
4166 &g4x_cursor_wm_info,
4167 &plane_sr, &cursor_sr))
0e442c60 4168 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4169 else
4170 I915_WRITE(FW_BLC_SELF,
4171 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4172
308977ac
CW		 4173 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4174 planea_wm, cursora_wm,
4175 planeb_wm, cursorb_wm,
4176 plane_sr, cursor_sr);
0e442c60 4177
417ae147
CW		 4178 I915_WRITE(DSPFW1,
4179 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4180 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4181 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4182 planea_wm);
4183 I915_WRITE(DSPFW2,
4184 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4185 (cursora_wm << DSPFW_CURSORA_SHIFT));
4186 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4187 I915_WRITE(DSPFW3,
4188 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4189 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4190}
4191
d210246a 4192static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4193{
4194 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4195 struct drm_crtc *crtc;
4196 int srwm = 1;
4fe5e611 4197 int cursor_sr = 16;
1dc7546d
JB		 4198
4199 /* Calc sr entries for one plane configs */
d210246a
CW		 4200 crtc = single_enabled_crtc(dev);
4201 if (crtc) {
1dc7546d 4202 /* self-refresh has much higher latency */
69e302a9 4203 static const int sr_latency_ns = 12000;
d210246a
CW		 4204 int clock = crtc->mode.clock;
4205 int htotal = crtc->mode.htotal;
4206 int hdisplay = crtc->mode.hdisplay;
4207 int pixel_size = crtc->fb->bits_per_pixel / 8;
4208 unsigned long line_time_us;
4209 int entries;
1dc7546d 4210
d210246a 4211 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4212
4213 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4214 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4215 pixel_size * hdisplay;
4216 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4217 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4218 if (srwm < 0)
4219 srwm = 1;
1b07e04e 4220 srwm &= 0x1ff;
308977ac
CW		 4221 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4222 entries, srwm);
4fe5e611 4223
d210246a 4224 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4225 pixel_size * 64;
d210246a 4226 entries = DIV_ROUND_UP(entries,
8de9b311 4227 i965_cursor_wm_info.cacheline_size);
4fe5e611 4228 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4229 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4230
4231 if (cursor_sr > i965_cursor_wm_info.max_wm)
4232 cursor_sr = i965_cursor_wm_info.max_wm;
4233
4234 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4235 "cursor %d\n", srwm, cursor_sr);
4236
a6c45cf0 4237 if (IS_CRESTLINE(dev))
adcdbc66 4238 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4239 } else {
4240 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4241 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4242 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4243 & ~FW_BLC_SELF_EN);
1dc7546d 4244 }
7662c8bd 4245
1dc7546d
JB		 4246 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4247 srwm);
7662c8bd
SL		 4248
4249 /* 965 has limitations... */
417ae147
CW		 4250 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4251 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4252 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4253 /* update cursor SR watermark */
4254 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4255}
4256
d210246a 4257static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4258{
4259 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4260 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4261 uint32_t fwater_lo;
4262 uint32_t fwater_hi;
d210246a
CW		 4263 int cwm, srwm = 1;
4264 int fifo_size;
dff33cfc 4265 int planea_wm, planeb_wm;
d210246a 4266 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4267
72557b4f 4268 if (IS_I945GM(dev))
d210246a 4269 wm_info = &i945_wm_info;
a6c45cf0 4270 else if (!IS_GEN2(dev))
d210246a 4271 wm_info = &i915_wm_info;
7662c8bd 4272 else
d210246a
CW		 4273 wm_info = &i855_wm_info;
4274
4275 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4276 crtc = intel_get_crtc_for_plane(dev, 0);
4277 if (crtc->enabled && crtc->fb) {
4278 planea_wm = intel_calculate_wm(crtc->mode.clock,
4279 wm_info, fifo_size,
4280 crtc->fb->bits_per_pixel / 8,
4281 latency_ns);
4282 enabled = crtc;
4283 } else
4284 planea_wm = fifo_size - wm_info->guard_size;
4285
4286 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4287 crtc = intel_get_crtc_for_plane(dev, 1);
4288 if (crtc->enabled && crtc->fb) {
4289 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4290 wm_info, fifo_size,
4291 crtc->fb->bits_per_pixel / 8,
4292 latency_ns);
4293 if (enabled == NULL)
4294 enabled = crtc;
4295 else
4296 enabled = NULL;
4297 } else
4298 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4299
28c97730 4300 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4301
4302 /*
4303 * Overlay gets an aggressive default since video jitter is bad.
4304 */
4305 cwm = 2;
4306
18b2190c
AL		 4307 /* Play safe and disable self-refresh before adjusting watermarks. */
4308 if (IS_I945G(dev) || IS_I945GM(dev))
4309 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4310 else if (IS_I915GM(dev))
4311 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4312
dff33cfc 4313 /* Calc sr entries for one plane configs */
d210246a 4314 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4315 /* self-refresh has much higher latency */
69e302a9 4316 static const int sr_latency_ns = 6000;
d210246a
CW		 4317 int clock = enabled->mode.clock;
4318 int htotal = enabled->mode.htotal;
4319 int hdisplay = enabled->mode.hdisplay;
4320 int pixel_size = enabled->fb->bits_per_pixel / 8;
4321 unsigned long line_time_us;
4322 int entries;
dff33cfc 4323
d210246a 4324 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4325
4326 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4327 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4328 pixel_size * hdisplay;
4329 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4330 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4331 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4332 if (srwm < 0)
4333 srwm = 1;
ee980b80
LP		 4334
4335 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4336 I915_WRITE(FW_BLC_SELF,
4337 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4338 else if (IS_I915GM(dev))
ee980b80 4339 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4340 }
4341
28c97730 4342 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4343 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4344
dff33cfc
JB		 4345 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4346 fwater_hi = (cwm & 0x1f);
4347
4348 /* Set request length to 8 cachelines per fetch */
4349 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4350 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4351
4352 I915_WRITE(FW_BLC, fwater_lo);
4353 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4354
d210246a
CW		 4355 if (HAS_FW_BLC(dev)) {
4356 if (enabled) {
4357 if (IS_I945G(dev) || IS_I945GM(dev))
4358 I915_WRITE(FW_BLC_SELF,
4359 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4360 else if (IS_I915GM(dev))
4361 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4362 DRM_DEBUG_KMS("memory self refresh enabled\n");
4363 } else
4364 DRM_DEBUG_KMS("memory self refresh disabled\n");
4365 }
7662c8bd
SL		 4366}
4367
d210246a 4368static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4369{
4370 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4371 struct drm_crtc *crtc;
4372 uint32_t fwater_lo;
dff33cfc 4373 int planea_wm;
7662c8bd 4374
d210246a
CW		 4375 crtc = single_enabled_crtc(dev);
4376 if (crtc == NULL)
4377 return;
7662c8bd 4378
d210246a
CW		 4379 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4380 dev_priv->display.get_fifo_size(dev, 0),
4381 crtc->fb->bits_per_pixel / 8,
4382 latency_ns);
4383 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4384 fwater_lo |= (3<<8) | planea_wm;
4385
28c97730 4386 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4387
4388 I915_WRITE(FW_BLC, fwater_lo);
4389}
4390
7f8a8569 4391#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4392#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4393
1398261a
YL		 4394/*
4395 * Check the wm result.
4396 *
4397 * If any calculated watermark values is larger than the maximum value that
4398 * can be programmed into the associated watermark register, that watermark
4399 * must be disabled.
1398261a 4400 */
b79d4990
JB		 4401static bool ironlake_check_srwm(struct drm_device *dev, int level,
4402 int fbc_wm, int display_wm, int cursor_wm,
4403 const struct intel_watermark_params *display,
4404 const struct intel_watermark_params *cursor)
1398261a
YL		 4405{
4406 struct drm_i915_private *dev_priv = dev->dev_private;
4407
4408 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4409 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4410
4411 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4412 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4413 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4414
4415 /* fbc has it's own way to disable FBC WM */
4416 I915_WRITE(DISP_ARB_CTL,
4417 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4418 return false;
4419 }
4420
b79d4990 4421 if (display_wm > display->max_wm) {
1398261a 4422 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4423 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4424 return false;
4425 }
4426
b79d4990 4427 if (cursor_wm > cursor->max_wm) {
1398261a 4428 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4429 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4430 return false;
4431 }
4432
4433 if (!(fbc_wm || display_wm || cursor_wm)) {
4434 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4435 return false;
4436 }
4437
4438 return true;
4439}
4440
4441/*
4442 * Compute watermark values of WM[1-3],
4443 */
d210246a
CW		 4444static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4445 int latency_ns,
b79d4990
JB		 4446 const struct intel_watermark_params *display,
4447 const struct intel_watermark_params *cursor,
4448 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4449{
d210246a 4450 struct drm_crtc *crtc;
1398261a 4451 unsigned long line_time_us;
d210246a 4452 int hdisplay, htotal, pixel_size, clock;
b79d4990 4453 int line_count, line_size;
1398261a
YL		 4454 int small, large;
4455 int entries;
1398261a
YL		 4456
4457 if (!latency_ns) {
4458 *fbc_wm = *display_wm = *cursor_wm = 0;
4459 return false;
4460 }
4461
d210246a
CW		 4462 crtc = intel_get_crtc_for_plane(dev, plane);
4463 hdisplay = crtc->mode.hdisplay;
4464 htotal = crtc->mode.htotal;
4465 clock = crtc->mode.clock;
4466 pixel_size = crtc->fb->bits_per_pixel / 8;
4467
1398261a
YL		 4468 line_time_us = (htotal * 1000) / clock;
4469 line_count = (latency_ns / line_time_us + 1000) / 1000;
4470 line_size = hdisplay * pixel_size;
4471
4472 /* Use the minimum of the small and large buffer method for primary */
4473 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4474 large = line_count * line_size;
4475
b79d4990
JB		 4476 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4477 *display_wm = entries + display->guard_size;
1398261a
YL		 4478
4479 /*
b79d4990 4480 * Spec says:
1398261a
YL		 4481 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4482 */
4483 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4484
4485 /* calculate the self-refresh watermark for display cursor */
4486 entries = line_count * pixel_size * 64;
b79d4990
JB		 4487 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4488 *cursor_wm = entries + cursor->guard_size;
1398261a 4489
b79d4990
JB		 4490 return ironlake_check_srwm(dev, level,
4491 *fbc_wm, *display_wm, *cursor_wm,
4492 display, cursor);
4493}
4494
d210246a 4495static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4496{
4497 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4498 int fbc_wm, plane_wm, cursor_wm;
4499 unsigned int enabled;
b79d4990
JB		 4500
4501 enabled = 0;
9f405100
CW		 4502 if (g4x_compute_wm0(dev, 0,
4503 &ironlake_display_wm_info,
4504 ILK_LP0_PLANE_LATENCY,
4505 &ironlake_cursor_wm_info,
4506 ILK_LP0_CURSOR_LATENCY,
4507 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4508 I915_WRITE(WM0_PIPEA_ILK,
4509 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4510 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4511 " plane %d, " "cursor: %d\n",
4512 plane_wm, cursor_wm);
d210246a 4513 enabled |= 1;
b79d4990
JB		 4514 }
4515
9f405100
CW		 4516 if (g4x_compute_wm0(dev, 1,
4517 &ironlake_display_wm_info,
4518 ILK_LP0_PLANE_LATENCY,
4519 &ironlake_cursor_wm_info,
4520 ILK_LP0_CURSOR_LATENCY,
4521 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4522 I915_WRITE(WM0_PIPEB_ILK,
4523 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4524 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4525 " plane %d, cursor: %d\n",
4526 plane_wm, cursor_wm);
d210246a 4527 enabled |= 2;
b79d4990
JB		 4528 }
4529
4530 /*
4531 * Calculate and update the self-refresh watermark only when one
4532 * display plane is used.
4533 */
4534 I915_WRITE(WM3_LP_ILK, 0);
4535 I915_WRITE(WM2_LP_ILK, 0);
4536 I915_WRITE(WM1_LP_ILK, 0);
4537
d210246a 4538 if (!single_plane_enabled(enabled))
b79d4990 4539 return;
d210246a 4540 enabled = ffs(enabled) - 1;
b79d4990
JB		 4541
4542 /* WM1 */
d210246a
CW		 4543 if (!ironlake_compute_srwm(dev, 1, enabled,
4544 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4545 &ironlake_display_srwm_info,
4546 &ironlake_cursor_srwm_info,
4547 &fbc_wm, &plane_wm, &cursor_wm))
4548 return;
4549
4550 I915_WRITE(WM1_LP_ILK,
4551 WM1_LP_SR_EN |
4552 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4553 (fbc_wm << WM1_LP_FBC_SHIFT) |
4554 (plane_wm << WM1_LP_SR_SHIFT) |
4555 cursor_wm);
4556
4557 /* WM2 */
d210246a
CW		 4558 if (!ironlake_compute_srwm(dev, 2, enabled,
4559 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4560 &ironlake_display_srwm_info,
4561 &ironlake_cursor_srwm_info,
4562 &fbc_wm, &plane_wm, &cursor_wm))
4563 return;
4564
4565 I915_WRITE(WM2_LP_ILK,
4566 WM2_LP_EN |
4567 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4568 (fbc_wm << WM1_LP_FBC_SHIFT) |
4569 (plane_wm << WM1_LP_SR_SHIFT) |
4570 cursor_wm);
4571
4572 /*
4573 * WM3 is unsupported on ILK, probably because we don't have latency
4574 * data for that power state
4575 */
1398261a
YL		 4576}
4577
b840d907 4578void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4579{
4580 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4581 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4582 u32 val;
d210246a
CW		 4583 int fbc_wm, plane_wm, cursor_wm;
4584 unsigned int enabled;
1398261a
YL		 4585
4586 enabled = 0;
9f405100
CW		 4587 if (g4x_compute_wm0(dev, 0,
4588 &sandybridge_display_wm_info, latency,
4589 &sandybridge_cursor_wm_info, latency,
4590 &plane_wm, &cursor_wm)) {
47842649
JB		 4591 val = I915_READ(WM0_PIPEA_ILK);
4592 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4593 I915_WRITE(WM0_PIPEA_ILK, val |
4594 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4595 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4596 " plane %d, " "cursor: %d\n",
4597 plane_wm, cursor_wm);
d210246a 4598 enabled |= 1;
1398261a
YL		 4599 }
4600
9f405100
CW		 4601 if (g4x_compute_wm0(dev, 1,
4602 &sandybridge_display_wm_info, latency,
4603 &sandybridge_cursor_wm_info, latency,
4604 &plane_wm, &cursor_wm)) {
47842649
JB		 4605 val = I915_READ(WM0_PIPEB_ILK);
4606 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4607 I915_WRITE(WM0_PIPEB_ILK, val |
4608 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4609 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4610 " plane %d, cursor: %d\n",
4611 plane_wm, cursor_wm);
d210246a 4612 enabled |= 2;
1398261a
YL		 4613 }
4614
d6c892df
JB		 4615 /* IVB has 3 pipes */
4616 if (IS_IVYBRIDGE(dev) &&
4617 g4x_compute_wm0(dev, 2,
4618 &sandybridge_display_wm_info, latency,
4619 &sandybridge_cursor_wm_info, latency,
4620 &plane_wm, &cursor_wm)) {
47842649
JB		 4621 val = I915_READ(WM0_PIPEC_IVB);
4622 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4623 I915_WRITE(WM0_PIPEC_IVB, val |
4624 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
d6c892df
JB		 4625 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4626 " plane %d, cursor: %d\n",
4627 plane_wm, cursor_wm);
4628 enabled |= 3;
4629 }
4630
1398261a
YL		 4631 /*
4632 * Calculate and update the self-refresh watermark only when one
4633 * display plane is used.
4634 *
4635 * SNB support 3 levels of watermark.
4636 *
4637 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4638 * and disabled in the descending order
4639 *
4640 */
4641 I915_WRITE(WM3_LP_ILK, 0);
4642 I915_WRITE(WM2_LP_ILK, 0);
4643 I915_WRITE(WM1_LP_ILK, 0);
4644
b840d907
JB		 4645 if (!single_plane_enabled(enabled) ||
4646 dev_priv->sprite_scaling_enabled)
1398261a 4647 return;
d210246a 4648 enabled = ffs(enabled) - 1;
1398261a
YL		 4649
4650 /* WM1 */
d210246a
CW		 4651 if (!ironlake_compute_srwm(dev, 1, enabled,
4652 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4653 &sandybridge_display_srwm_info,
4654 &sandybridge_cursor_srwm_info,
4655 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4656 return;
4657
4658 I915_WRITE(WM1_LP_ILK,
4659 WM1_LP_SR_EN |
4660 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4661 (fbc_wm << WM1_LP_FBC_SHIFT) |
4662 (plane_wm << WM1_LP_SR_SHIFT) |
4663 cursor_wm);
4664
4665 /* WM2 */
d210246a
CW		 4666 if (!ironlake_compute_srwm(dev, 2, enabled,
4667 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4668 &sandybridge_display_srwm_info,
4669 &sandybridge_cursor_srwm_info,
4670 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4671 return;
4672
4673 I915_WRITE(WM2_LP_ILK,
4674 WM2_LP_EN |
4675 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4676 (fbc_wm << WM1_LP_FBC_SHIFT) |
4677 (plane_wm << WM1_LP_SR_SHIFT) |
4678 cursor_wm);
4679
4680 /* WM3 */
d210246a
CW		 4681 if (!ironlake_compute_srwm(dev, 3, enabled,
4682 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4683 &sandybridge_display_srwm_info,
4684 &sandybridge_cursor_srwm_info,
4685 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4686 return;
4687
4688 I915_WRITE(WM3_LP_ILK,
4689 WM3_LP_EN |
4690 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4691 (fbc_wm << WM1_LP_FBC_SHIFT) |
4692 (plane_wm << WM1_LP_SR_SHIFT) |
4693 cursor_wm);
4694}
4695
b840d907
JB		 4696static bool
4697sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4698 uint32_t sprite_width, int pixel_size,
4699 const struct intel_watermark_params *display,
4700 int display_latency_ns, int *sprite_wm)
4701{
4702 struct drm_crtc *crtc;
4703 int clock;
4704 int entries, tlb_miss;
4705
4706 crtc = intel_get_crtc_for_plane(dev, plane);
4707 if (crtc->fb == NULL || !crtc->enabled) {
4708 *sprite_wm = display->guard_size;
4709 return false;
4710 }
4711
4712 clock = crtc->mode.clock;
4713
4714 /* Use the small buffer method to calculate the sprite watermark */
4715 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4716 tlb_miss = display->fifo_size*display->cacheline_size -
4717 sprite_width * 8;
4718 if (tlb_miss > 0)
4719 entries += tlb_miss;
4720 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4721 *sprite_wm = entries + display->guard_size;
4722 if (*sprite_wm > (int)display->max_wm)
4723 *sprite_wm = display->max_wm;
4724
4725 return true;
4726}
4727
4728static bool
4729sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4730 uint32_t sprite_width, int pixel_size,
4731 const struct intel_watermark_params *display,
4732 int latency_ns, int *sprite_wm)
4733{
4734 struct drm_crtc *crtc;
4735 unsigned long line_time_us;
4736 int clock;
4737 int line_count, line_size;
4738 int small, large;
4739 int entries;
4740
4741 if (!latency_ns) {
4742 *sprite_wm = 0;
4743 return false;
4744 }
4745
4746 crtc = intel_get_crtc_for_plane(dev, plane);
4747 clock = crtc->mode.clock;
4748
4749 line_time_us = (sprite_width * 1000) / clock;
4750 line_count = (latency_ns / line_time_us + 1000) / 1000;
4751 line_size = sprite_width * pixel_size;
4752
4753 /* Use the minimum of the small and large buffer method for primary */
4754 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4755 large = line_count * line_size;
4756
4757 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4758 *sprite_wm = entries + display->guard_size;
4759
4760 return *sprite_wm > 0x3ff ? false : true;
4761}
4762
4763static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4764 uint32_t sprite_width, int pixel_size)
4765{
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4768 u32 val;
b840d907
JB		 4769 int sprite_wm, reg;
4770 int ret;
4771
4772 switch (pipe) {
4773 case 0:
4774 reg = WM0_PIPEA_ILK;
4775 break;
4776 case 1:
4777 reg = WM0_PIPEB_ILK;
4778 break;
4779 case 2:
4780 reg = WM0_PIPEC_IVB;
4781 break;
4782 default:
4783 return; /* bad pipe */
4784 }
4785
4786 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4787 &sandybridge_display_wm_info,
4788 latency, &sprite_wm);
4789 if (!ret) {
4790 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4791 pipe);
4792 return;
4793 }
4794
47842649
JB		 4795 val = I915_READ(reg);
4796 val &= ~WM0_PIPE_SPRITE_MASK;
4797 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
b840d907
JB		 4798 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4799
4800
4801 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4802 pixel_size,
4803 &sandybridge_display_srwm_info,
4804 SNB_READ_WM1_LATENCY() * 500,
4805 &sprite_wm);
4806 if (!ret) {
4807 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4808 pipe);
4809 return;
4810 }
4811 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4812
4813 /* Only IVB has two more LP watermarks for sprite */
4814 if (!IS_IVYBRIDGE(dev))
4815 return;
4816
4817 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4818 pixel_size,
4819 &sandybridge_display_srwm_info,
4820 SNB_READ_WM2_LATENCY() * 500,
4821 &sprite_wm);
4822 if (!ret) {
4823 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4824 pipe);
4825 return;
4826 }
4827 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4828
4829 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4830 pixel_size,
4831 &sandybridge_display_srwm_info,
4832 SNB_READ_WM3_LATENCY() * 500,
4833 &sprite_wm);
4834 if (!ret) {
4835 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4836 pipe);
4837 return;
4838 }
4839 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4840}
4841
7662c8bd
SL		 4842/**
4843 * intel_update_watermarks - update FIFO watermark values based on current modes
4844 *
4845 * Calculate watermark values for the various WM regs based on current mode
4846 * and plane configuration.
4847 *
4848 * There are several cases to deal with here:
4849 * - normal (i.e. non-self-refresh)
4850 * - self-refresh (SR) mode
4851 * - lines are large relative to FIFO size (buffer can hold up to 2)
4852 * - lines are small relative to FIFO size (buffer can hold more than 2
4853 * lines), so need to account for TLB latency
4854 *
4855 * The normal calculation is:
4856 * watermark = dotclock * bytes per pixel * latency
4857 * where latency is platform & configuration dependent (we assume pessimal
4858 * values here).
4859 *
4860 * The SR calculation is:
4861 * watermark = (trunc(latency/line time)+1) * surface width *
4862 * bytes per pixel
4863 * where
4864 * line time = htotal / dotclock
fa143215 4865 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4866 * and latency is assumed to be high, as above.
4867 *
4868 * The final value programmed to the register should always be rounded up,
4869 * and include an extra 2 entries to account for clock crossings.
4870 *
4871 * We don't use the sprite, so we can ignore that. And on Crestline we have
4872 * to set the non-SR watermarks to 8.
5eddb70b 4873 */
7662c8bd
SL		 4874static void intel_update_watermarks(struct drm_device *dev)
4875{
e70236a8 4876 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4877
d210246a
CW		 4878 if (dev_priv->display.update_wm)
4879 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4880}
4881
b840d907
JB		 4882void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4883 uint32_t sprite_width, int pixel_size)
4884{
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886
4887 if (dev_priv->display.update_sprite_wm)
4888 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4889 pixel_size);
4890}
4891
a7615030
CW		 4892static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4893{
72bbe58c
KP		 4894 if (i915_panel_use_ssc >= 0)
4895 return i915_panel_use_ssc != 0;
4896 return dev_priv->lvds_use_ssc
435793df 4897 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4898}
4899
5a354204
JB		 4900/**
4901 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4902 * @crtc: CRTC structure
3b5c78a3 4903 * @mode: requested mode
5a354204
JB		 4904 *
4905 * A pipe may be connected to one or more outputs. Based on the depth of the
4906 * attached framebuffer, choose a good color depth to use on the pipe.
4907 *
4908 * If possible, match the pipe depth to the fb depth. In some cases, this
4909 * isn't ideal, because the connected output supports a lesser or restricted
4910 * set of depths. Resolve that here:
4911 * LVDS typically supports only 6bpc, so clamp down in that case
4912 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4913 * Displays may support a restricted set as well, check EDID and clamp as
4914 * appropriate.
3b5c78a3 4915 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4916 *
4917 * RETURNS:
4918 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4919 * true if they don't match).
4920 */
4921static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 4922 unsigned int *pipe_bpp,
4923 struct drm_display_mode *mode)
5a354204
JB		 4924{
4925 struct drm_device *dev = crtc->dev;
4926 struct drm_i915_private *dev_priv = dev->dev_private;
4927 struct drm_encoder *encoder;
4928 struct drm_connector *connector;
4929 unsigned int display_bpc = UINT_MAX, bpc;
4930
4931 /* Walk the encoders & connectors on this crtc, get min bpc */
4932 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4933 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4934
4935 if (encoder->crtc != crtc)
4936 continue;
4937
4938 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4939 unsigned int lvds_bpc;
4940
4941 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4942 LVDS_A3_POWER_UP)
4943 lvds_bpc = 8;
4944 else
4945 lvds_bpc = 6;
4946
4947 if (lvds_bpc < display_bpc) {
82820490 4948 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4949 display_bpc = lvds_bpc;
4950 }
4951 continue;
4952 }
4953
4954 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4955 /* Use VBT settings if we have an eDP panel */
4956 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4957
4958 if (edp_bpc < display_bpc) {
82820490 4959 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 4960 display_bpc = edp_bpc;
4961 }
4962 continue;
4963 }
4964
4965 /* Not one of the known troublemakers, check the EDID */
4966 list_for_each_entry(connector, &dev->mode_config.connector_list,
4967 head) {
4968 if (connector->encoder != encoder)
4969 continue;
4970
62ac41a6
JB		 4971 /* Don't use an invalid EDID bpc value */
4972 if (connector->display_info.bpc &&
4973 connector->display_info.bpc < display_bpc) {
82820490 4974 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4975 display_bpc = connector->display_info.bpc;
4976 }
4977 }
4978
4979 /*
4980 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4981 * through, clamp it down. (Note: >12bpc will be caught below.)
4982 */
4983 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4984 if (display_bpc > 8 && display_bpc < 12) {
82820490 4985 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4986 display_bpc = 12;
4987 } else {
82820490 4988 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4989 display_bpc = 8;
4990 }
4991 }
4992 }
4993
3b5c78a3
AJ		 4994 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4995 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4996 display_bpc = 6;
4997 }
4998
5a354204
JB		 4999 /*
5000 * We could just drive the pipe at the highest bpc all the time and
5001 * enable dithering as needed, but that costs bandwidth. So choose
5002 * the minimum value that expresses the full color range of the fb but
5003 * also stays within the max display bpc discovered above.
5004 */
5005
5006 switch (crtc->fb->depth) {
5007 case 8:
5008 bpc = 8; /* since we go through a colormap */
5009 break;
5010 case 15:
5011 case 16:
5012 bpc = 6; /* min is 18bpp */
5013 break;
5014 case 24:
578393cd 5015 bpc = 8;
5a354204
JB		 5016 break;
5017 case 30:
578393cd 5018 bpc = 10;
5a354204
JB		 5019 break;
5020 case 48:
578393cd 5021 bpc = 12;
5a354204
JB		 5022 break;
5023 default:
5024 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5025 bpc = min((unsigned int)8, display_bpc);
5026 break;
5027 }
5028
578393cd
KP		 5029 display_bpc = min(display_bpc, bpc);
5030
82820490
AJ		 5031 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5032 bpc, display_bpc);
5a354204 5033
578393cd 5034 *pipe_bpp = display_bpc * 3;
5a354204
JB		 5035
5036 return display_bpc != bpc;
5037}
5038
c65d77d8
JB		 5039static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5040{
5041 struct drm_device *dev = crtc->dev;
5042 struct drm_i915_private *dev_priv = dev->dev_private;
5043 int refclk;
5044
5045 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5046 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5047 refclk = dev_priv->lvds_ssc_freq * 1000;
5048 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5049 refclk / 1000);
5050 } else if (!IS_GEN2(dev)) {
5051 refclk = 96000;
5052 } else {
5053 refclk = 48000;
5054 }
5055
5056 return refclk;
5057}
5058
5059static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5060 intel_clock_t *clock)
5061{
5062 /* SDVO TV has fixed PLL values depend on its clock range,
5063 this mirrors vbios setting. */
5064 if (adjusted_mode->clock >= 100000
5065 && adjusted_mode->clock < 140500) {
5066 clock->p1 = 2;
5067 clock->p2 = 10;
5068 clock->n = 3;
5069 clock->m1 = 16;
5070 clock->m2 = 8;
5071 } else if (adjusted_mode->clock >= 140500
5072 && adjusted_mode->clock <= 200000) {
5073 clock->p1 = 1;
5074 clock->p2 = 10;
5075 clock->n = 6;
5076 clock->m1 = 12;
5077 clock->m2 = 8;
5078 }
5079}
5080
a7516a05
JB		 5081static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5082 intel_clock_t *clock,
5083 intel_clock_t *reduced_clock)
5084{
5085 struct drm_device *dev = crtc->dev;
5086 struct drm_i915_private *dev_priv = dev->dev_private;
5087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5088 int pipe = intel_crtc->pipe;
5089 u32 fp, fp2 = 0;
5090
5091 if (IS_PINEVIEW(dev)) {
5092 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5093 if (reduced_clock)
5094 fp2 = (1 << reduced_clock->n) << 16 |
5095 reduced_clock->m1 << 8 | reduced_clock->m2;
5096 } else {
5097 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5098 if (reduced_clock)
5099 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5100 reduced_clock->m2;
5101 }
5102
5103 I915_WRITE(FP0(pipe), fp);
5104
5105 intel_crtc->lowfreq_avail = false;
5106 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5107 reduced_clock && i915_powersave) {
5108 I915_WRITE(FP1(pipe), fp2);
5109 intel_crtc->lowfreq_avail = true;
5110 } else {
5111 I915_WRITE(FP1(pipe), fp);
5112 }
5113}
5114
f564048e
EA		 5115static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5116 struct drm_display_mode *mode,
5117 struct drm_display_mode *adjusted_mode,
5118 int x, int y,
5119 struct drm_framebuffer *old_fb)
79e53945
JB		 5120{
5121 struct drm_device *dev = crtc->dev;
5122 struct drm_i915_private *dev_priv = dev->dev_private;
5123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5124 int pipe = intel_crtc->pipe;
80824003 5125 int plane = intel_crtc->plane;
c751ce4f 5126 int refclk, num_connectors = 0;
652c393a 5127 intel_clock_t clock, reduced_clock;
0529a0d9 5128 u32 dpll, dspcntr, pipeconf, vsyncshift;
652c393a 5129 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 5130 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 5131 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5132 struct intel_encoder *encoder;
d4906093 5133 const intel_limit_t *limit;
5c3b82e2 5134 int ret;
fae14981 5135 u32 temp;
aa9b500d 5136 u32 lvds_sync = 0;
79e53945 5137
5eddb70b
CW		 5138 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5139 if (encoder->base.crtc != crtc)
79e53945
JB		 5140 continue;
5141
5eddb70b 5142 switch (encoder->type) {
79e53945
JB		 5143 case INTEL_OUTPUT_LVDS:
5144 is_lvds = true;
5145 break;
5146 case INTEL_OUTPUT_SDVO:
7d57382e 5147 case INTEL_OUTPUT_HDMI:
79e53945 5148 is_sdvo = true;
5eddb70b 5149 if (encoder->needs_tv_clock)
e2f0ba97 5150 is_tv = true;
79e53945
JB		 5151 break;
5152 case INTEL_OUTPUT_DVO:
5153 is_dvo = true;
5154 break;
5155 case INTEL_OUTPUT_TVOUT:
5156 is_tv = true;
5157 break;
5158 case INTEL_OUTPUT_ANALOG:
5159 is_crt = true;
5160 break;
a4fc5ed6
KP		 5161 case INTEL_OUTPUT_DISPLAYPORT:
5162 is_dp = true;
5163 break;
79e53945 5164 }
43565a06 5165
c751ce4f 5166 num_connectors++;
79e53945
JB		 5167 }
5168
c65d77d8 5169 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5170
d4906093
ML		 5171 /*
5172 * Returns a set of divisors for the desired target clock with the given
5173 * refclk, or FALSE. The returned values represent the clock equation:
5174 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5175 */
1b894b59 5176 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5177 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5178 &clock);
79e53945
JB		 5179 if (!ok) {
5180 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5181 return -EINVAL;
79e53945
JB		 5182 }
5183
cda4b7d3 5184 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5185 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5186
ddc9003c 5187 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5188 /*
5189 * Ensure we match the reduced clock's P to the target clock.
5190 * If the clocks don't match, we can't switch the display clock
5191 * by using the FP0/FP1. In such case we will disable the LVDS
5192 * downclock feature.
5193 */
ddc9003c 5194 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5195 dev_priv->lvds_downclock,
5196 refclk,
cec2f356 5197 &clock,
5eddb70b 5198 &reduced_clock);
652c393a 5199 }
c65d77d8
JB		 5200
5201 if (is_sdvo && is_tv)
5202 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 5203
a7516a05
JB		 5204 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5205 &reduced_clock : NULL);
79e53945 5206
929c77fb 5207 dpll = DPLL_VGA_MODE_DIS;
2c07245f 5208
a6c45cf0 5209 if (!IS_GEN2(dev)) {
79e53945
JB		 5210 if (is_lvds)
5211 dpll |= DPLLB_MODE_LVDS;
5212 else
5213 dpll |= DPLLB_MODE_DAC_SERIAL;
5214 if (is_sdvo) {
6c9547ff
CW		 5215 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5216 if (pixel_multiplier > 1) {
5217 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5218 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 5219 }
79e53945 5220 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5221 }
929c77fb 5222 if (is_dp)
a4fc5ed6 5223 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 5224
5225 /* compute bitmask from p1 value */
f2b115e6
AJ		 5226 if (IS_PINEVIEW(dev))
5227 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 5228 else {
2177832f 5229 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 5230 if (IS_G4X(dev) && has_reduced_clock)
5231 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 5232 }
79e53945
JB		 5233 switch (clock.p2) {
5234 case 5:
5235 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5236 break;
5237 case 7:
5238 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5239 break;
5240 case 10:
5241 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5242 break;
5243 case 14:
5244 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5245 break;
5246 }
929c77fb 5247 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 5248 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5249 } else {
5250 if (is_lvds) {
5251 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5252 } else {
5253 if (clock.p1 == 2)
5254 dpll |= PLL_P1_DIVIDE_BY_TWO;
5255 else
5256 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5257 if (clock.p2 == 4)
5258 dpll |= PLL_P2_DIVIDE_BY_4;
5259 }
5260 }
5261
43565a06
KH		 5262 if (is_sdvo && is_tv)
5263 dpll |= PLL_REF_INPUT_TVCLKINBC;
5264 else if (is_tv)
79e53945 5265 /* XXX: just matching BIOS for now */
43565a06 5266 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5267 dpll |= 3;
a7615030 5268 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5269 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5270 else
5271 dpll |= PLL_REF_INPUT_DREFCLK;
5272
5273 /* setup pipeconf */
5eddb70b 5274 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5275
5276 /* Set up the display plane register */
5277 dspcntr = DISPPLANE_GAMMA_ENABLE;
5278
929c77fb
EA		 5279 if (pipe == 0)
5280 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5281 else
5282 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 5283
a6c45cf0 5284 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 5285 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5286 * core speed.
5287 *
5288 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5289 * pipe == 0 check?
5290 */
e70236a8
JB		 5291 if (mode->clock >
5292 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 5293 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 5294 else
5eddb70b 5295 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 5296 }
5297
3b5c78a3
AJ		 5298 /* default to 8bpc */
5299 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5300 if (is_dp) {
5301 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5302 pipeconf |= PIPECONF_BPP_6 |
5303 PIPECONF_DITHER_EN |
5304 PIPECONF_DITHER_TYPE_SP;
5305 }
5306 }
5307
929c77fb 5308 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 5309
28c97730 5310 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5311 drm_mode_debug_printmodeline(mode);
5312
fae14981 5313 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5314
fae14981 5315 POSTING_READ(DPLL(pipe));
c713bb08 5316 udelay(150);
8db9d77b 5317
79e53945
JB		 5318 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5319 * This is an exception to the general rule that mode_set doesn't turn
5320 * things on.
5321 */
5322 if (is_lvds) {
fae14981 5323 temp = I915_READ(LVDS);
5eddb70b 5324 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 5325 if (pipe == 1) {
929c77fb 5326 temp |= LVDS_PIPEB_SELECT;
b3b095b3 5327 } else {
929c77fb 5328 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5329 }
a3e17eb8 5330 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5331 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5332 /* Set the B0-B3 data pairs corresponding to whether we're going to
5333 * set the DPLLs for dual-channel mode or not.
5334 */
5335 if (clock.p2 == 7)
5eddb70b 5336 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5337 else
5eddb70b 5338 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5339
5340 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5341 * appropriately here, but we need to look more thoroughly into how
5342 * panels behave in the two modes.
5343 */
929c77fb
EA		 5344 /* set the dithering flag on LVDS as needed */
5345 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5346 if (dev_priv->lvds_dither)
5eddb70b 5347 temp |= LVDS_ENABLE_DITHER;
434ed097 5348 else
5eddb70b 5349 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5350 }
aa9b500d
BF		 5351 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5352 lvds_sync |= LVDS_HSYNC_POLARITY;
5353 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5354 lvds_sync |= LVDS_VSYNC_POLARITY;
5355 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5356 != lvds_sync) {
5357 char flags[2] = "-+";
5358 DRM_INFO("Changing LVDS panel from "
5359 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5360 flags[!(temp & LVDS_HSYNC_POLARITY)],
5361 flags[!(temp & LVDS_VSYNC_POLARITY)],
5362 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5363 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5364 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5365 temp |= lvds_sync;
5366 }
fae14981 5367 I915_WRITE(LVDS, temp);
79e53945 5368 }
434ed097 5369
929c77fb 5370 if (is_dp) {
a4fc5ed6 5371 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5372 }
5373
fae14981 5374 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5375
c713bb08 5376 /* Wait for the clocks to stabilize. */
fae14981 5377 POSTING_READ(DPLL(pipe));
c713bb08 5378 udelay(150);
32f9d658 5379
c713bb08
EA		 5380 if (INTEL_INFO(dev)->gen >= 4) {
5381 temp = 0;
5382 if (is_sdvo) {
5383 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5384 if (temp > 1)
5385 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5386 else
5387 temp = 0;
32f9d658 5388 }
c713bb08
EA		 5389 I915_WRITE(DPLL_MD(pipe), temp);
5390 } else {
5391 /* The pixel multiplier can only be updated once the
5392 * DPLL is enabled and the clocks are stable.
5393 *
5394 * So write it again.
5395 */
fae14981 5396 I915_WRITE(DPLL(pipe), dpll);
79e53945 5397 }
79e53945 5398
a7516a05
JB		 5399 if (HAS_PIPE_CXSR(dev)) {
5400 if (intel_crtc->lowfreq_avail) {
28c97730 5401 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 5402 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 5403 } else {
28c97730 5404 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5405 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5406 }
5407 }
5408
617cf884 5409 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 5410 if (!IS_GEN2(dev) &&
5411 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 5412 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5413 /* the chip adds 2 halflines automatically */
734b4157 5414 adjusted_mode->crtc_vtotal -= 1;
734b4157 5415 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 5416 vsyncshift = adjusted_mode->crtc_hsync_start
5417 - adjusted_mode->crtc_htotal/2;
5418 } else {
617cf884 5419 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 5420 vsyncshift = 0;
5421 }
5422
5423 if (!IS_GEN3(dev))
5424 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 5425
5eddb70b
CW		 5426 I915_WRITE(HTOTAL(pipe),
5427 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5428 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5429 I915_WRITE(HBLANK(pipe),
5430 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5431 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5432 I915_WRITE(HSYNC(pipe),
5433 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5434 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5435
5436 I915_WRITE(VTOTAL(pipe),
5437 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5438 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5439 I915_WRITE(VBLANK(pipe),
5440 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5441 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5442 I915_WRITE(VSYNC(pipe),
5443 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5444 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5445
5446 /* pipesrc and dspsize control the size that is scaled from,
5447 * which should always be the user's requested size.
79e53945 5448 */
929c77fb
EA		 5449 I915_WRITE(DSPSIZE(plane),
5450 ((mode->vdisplay - 1) << 16) |
5451 (mode->hdisplay - 1));
5452 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5453 I915_WRITE(PIPESRC(pipe),
5454 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5455
f564048e
EA		 5456 I915_WRITE(PIPECONF(pipe), pipeconf);
5457 POSTING_READ(PIPECONF(pipe));
929c77fb 5458 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5459
5460 intel_wait_for_vblank(dev, pipe);
5461
f564048e
EA		 5462 I915_WRITE(DSPCNTR(plane), dspcntr);
5463 POSTING_READ(DSPCNTR(plane));
284d9529 5464 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5465
5466 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5467
5468 intel_update_watermarks(dev);
5469
f564048e
EA		 5470 return ret;
5471}
5472
9fb526db
KP		 5473/*
5474 * Initialize reference clocks when the driver loads
5475 */
5476void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5477{
5478 struct drm_i915_private *dev_priv = dev->dev_private;
5479 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5480 struct intel_encoder *encoder;
13d83a67
JB		 5481 u32 temp;
5482 bool has_lvds = false;
199e5d79
KP		 5483 bool has_cpu_edp = false;
5484 bool has_pch_edp = false;
5485 bool has_panel = false;
99eb6a01
KP		 5486 bool has_ck505 = false;
5487 bool can_ssc = false;
13d83a67
JB		 5488
5489 /* We need to take the global config into account */
199e5d79
KP		 5490 list_for_each_entry(encoder, &mode_config->encoder_list,
5491 base.head) {
5492 switch (encoder->type) {
5493 case INTEL_OUTPUT_LVDS:
5494 has_panel = true;
5495 has_lvds = true;
5496 break;
5497 case INTEL_OUTPUT_EDP:
5498 has_panel = true;
5499 if (intel_encoder_is_pch_edp(&encoder->base))
5500 has_pch_edp = true;
5501 else
5502 has_cpu_edp = true;
5503 break;
13d83a67
JB		 5504 }
5505 }
5506
99eb6a01
KP		 5507 if (HAS_PCH_IBX(dev)) {
5508 has_ck505 = dev_priv->display_clock_mode;
5509 can_ssc = has_ck505;
5510 } else {
5511 has_ck505 = false;
5512 can_ssc = true;
5513 }
5514
5515 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5516 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5517 has_ck505);
13d83a67
JB		 5518
5519 /* Ironlake: try to setup display ref clock before DPLL
5520 * enabling. This is only under driver's control after
5521 * PCH B stepping, previous chipset stepping should be
5522 * ignoring this setting.
5523 */
5524 temp = I915_READ(PCH_DREF_CONTROL);
5525 /* Always enable nonspread source */
5526 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5527
99eb6a01
KP		 5528 if (has_ck505)
5529 temp |= DREF_NONSPREAD_CK505_ENABLE;
5530 else
5531 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5532
199e5d79
KP		 5533 if (has_panel) {
5534 temp &= ~DREF_SSC_SOURCE_MASK;
5535 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5536
199e5d79 5537 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5538 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5539 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5540 temp |= DREF_SSC1_ENABLE;
13d83a67 5541 }
199e5d79
KP		 5542
5543 /* Get SSC going before enabling the outputs */
5544 I915_WRITE(PCH_DREF_CONTROL, temp);
5545 POSTING_READ(PCH_DREF_CONTROL);
5546 udelay(200);
5547
13d83a67
JB		 5548 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5549
5550 /* Enable CPU source on CPU attached eDP */
199e5d79 5551 if (has_cpu_edp) {
99eb6a01 5552 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5553 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5554 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5555 }
13d83a67
JB		 5556 else
5557 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5558 } else
5559 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5560
5561 I915_WRITE(PCH_DREF_CONTROL, temp);
5562 POSTING_READ(PCH_DREF_CONTROL);
5563 udelay(200);
5564 } else {
5565 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5566
5567 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5568
5569 /* Turn off CPU output */
5570 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5571
5572 I915_WRITE(PCH_DREF_CONTROL, temp);
5573 POSTING_READ(PCH_DREF_CONTROL);
5574 udelay(200);
5575
5576 /* Turn off the SSC source */
5577 temp &= ~DREF_SSC_SOURCE_MASK;
5578 temp |= DREF_SSC_SOURCE_DISABLE;
5579
5580 /* Turn off SSC1 */
5581 temp &= ~ DREF_SSC1_ENABLE;
5582
13d83a67
JB		 5583 I915_WRITE(PCH_DREF_CONTROL, temp);
5584 POSTING_READ(PCH_DREF_CONTROL);
5585 udelay(200);
5586 }
5587}
5588
d9d444cb
JB		 5589static int ironlake_get_refclk(struct drm_crtc *crtc)
5590{
5591 struct drm_device *dev = crtc->dev;
5592 struct drm_i915_private *dev_priv = dev->dev_private;
5593 struct intel_encoder *encoder;
5594 struct drm_mode_config *mode_config = &dev->mode_config;
5595 struct intel_encoder *edp_encoder = NULL;
5596 int num_connectors = 0;
5597 bool is_lvds = false;
5598
5599 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5600 if (encoder->base.crtc != crtc)
5601 continue;
5602
5603 switch (encoder->type) {
5604 case INTEL_OUTPUT_LVDS:
5605 is_lvds = true;
5606 break;
5607 case INTEL_OUTPUT_EDP:
5608 edp_encoder = encoder;
5609 break;
5610 }
5611 num_connectors++;
5612 }
5613
5614 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5615 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5616 dev_priv->lvds_ssc_freq);
5617 return dev_priv->lvds_ssc_freq * 1000;
5618 }
5619
5620 return 120000;
5621}
5622
f564048e
EA		 5623static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5624 struct drm_display_mode *mode,
5625 struct drm_display_mode *adjusted_mode,
5626 int x, int y,
5627 struct drm_framebuffer *old_fb)
79e53945
JB		 5628{
5629 struct drm_device *dev = crtc->dev;
5630 struct drm_i915_private *dev_priv = dev->dev_private;
5631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5632 int pipe = intel_crtc->pipe;
80824003 5633 int plane = intel_crtc->plane;
c751ce4f 5634 int refclk, num_connectors = 0;
652c393a 5635 intel_clock_t clock, reduced_clock;
5eddb70b 5636 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5637 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5638 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5639 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5640 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5641 struct intel_encoder *encoder;
d4906093 5642 const intel_limit_t *limit;
5c3b82e2 5643 int ret;
2c07245f 5644 struct fdi_m_n m_n = {0};
fae14981 5645 u32 temp;
aa9b500d 5646 u32 lvds_sync = 0;
5a354204
JB		 5647 int target_clock, pixel_multiplier, lane, link_bw, factor;
5648 unsigned int pipe_bpp;
5649 bool dither;
79e53945 5650
5eddb70b
CW		 5651 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5652 if (encoder->base.crtc != crtc)
79e53945
JB		 5653 continue;
5654
5eddb70b 5655 switch (encoder->type) {
79e53945
JB		 5656 case INTEL_OUTPUT_LVDS:
5657 is_lvds = true;
5658 break;
5659 case INTEL_OUTPUT_SDVO:
7d57382e 5660 case INTEL_OUTPUT_HDMI:
79e53945 5661 is_sdvo = true;
5eddb70b 5662 if (encoder->needs_tv_clock)
e2f0ba97 5663 is_tv = true;
79e53945 5664 break;
79e53945
JB		 5665 case INTEL_OUTPUT_TVOUT:
5666 is_tv = true;
5667 break;
5668 case INTEL_OUTPUT_ANALOG:
5669 is_crt = true;
5670 break;
a4fc5ed6
KP		 5671 case INTEL_OUTPUT_DISPLAYPORT:
5672 is_dp = true;
5673 break;
32f9d658 5674 case INTEL_OUTPUT_EDP:
5eddb70b 5675 has_edp_encoder = encoder;
32f9d658 5676 break;
79e53945 5677 }
43565a06 5678
c751ce4f 5679 num_connectors++;
79e53945
JB		 5680 }
5681
d9d444cb 5682 refclk = ironlake_get_refclk(crtc);
79e53945 5683
d4906093
ML		 5684 /*
5685 * Returns a set of divisors for the desired target clock with the given
5686 * refclk, or FALSE. The returned values represent the clock equation:
5687 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5688 */
1b894b59 5689 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5690 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5691 &clock);
79e53945
JB		 5692 if (!ok) {
5693 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5694 return -EINVAL;
79e53945
JB		 5695 }
5696
cda4b7d3 5697 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5698 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5699
ddc9003c 5700 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5701 /*
5702 * Ensure we match the reduced clock's P to the target clock.
5703 * If the clocks don't match, we can't switch the display clock
5704 * by using the FP0/FP1. In such case we will disable the LVDS
5705 * downclock feature.
5706 */
ddc9003c 5707 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5708 dev_priv->lvds_downclock,
5709 refclk,
cec2f356 5710 &clock,
5eddb70b 5711 &reduced_clock);
652c393a 5712 }
7026d4ac
ZW		 5713 /* SDVO TV has fixed PLL values depend on its clock range,
5714 this mirrors vbios setting. */
5715 if (is_sdvo && is_tv) {
5716 if (adjusted_mode->clock >= 100000
5eddb70b 5717 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5718 clock.p1 = 2;
5719 clock.p2 = 10;
5720 clock.n = 3;
5721 clock.m1 = 16;
5722 clock.m2 = 8;
5723 } else if (adjusted_mode->clock >= 140500
5eddb70b 5724 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5725 clock.p1 = 1;
5726 clock.p2 = 10;
5727 clock.n = 6;
5728 clock.m1 = 12;
5729 clock.m2 = 8;
5730 }
5731 }
5732
2c07245f 5733 /* FDI link */
8febb297
EA		 5734 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5735 lane = 0;
5736 /* CPU eDP doesn't require FDI link, so just set DP M/N
5737 according to current link config */
5738 if (has_edp_encoder &&
5739 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5740 target_clock = mode->clock;
5741 intel_edp_link_config(has_edp_encoder,
5742 &lane, &link_bw);
5743 } else {
5744 /* [e]DP over FDI requires target mode clock
5745 instead of link clock */
5746 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5747 target_clock = mode->clock;
8febb297
EA		 5748 else
5749 target_clock = adjusted_mode->clock;
5750
5751 /* FDI is a binary signal running at ~2.7GHz, encoding
5752 * each output octet as 10 bits. The actual frequency
5753 * is stored as a divider into a 100MHz clock, and the
5754 * mode pixel clock is stored in units of 1KHz.
5755 * Hence the bw of each lane in terms of the mode signal
5756 * is:
5757 */
5758 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5759 }
58a27471 5760
8febb297
EA		 5761 /* determine panel color depth */
5762 temp = I915_READ(PIPECONF(pipe));
5763 temp &= ~PIPE_BPC_MASK;
3b5c78a3 5764 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 5765 switch (pipe_bpp) {
5766 case 18:
5767 temp |= PIPE_6BPC;
8febb297 5768 break;
5a354204
JB		 5769 case 24:
5770 temp |= PIPE_8BPC;
8febb297 5771 break;
5a354204
JB		 5772 case 30:
5773 temp |= PIPE_10BPC;
8febb297 5774 break;
5a354204
JB		 5775 case 36:
5776 temp |= PIPE_12BPC;
8febb297
EA		 5777 break;
5778 default:
62ac41a6
JB		 5779 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5780 pipe_bpp);
5a354204
JB		 5781 temp |= PIPE_8BPC;
5782 pipe_bpp = 24;
5783 break;
8febb297 5784 }
77ffb597 5785
5a354204
JB		 5786 intel_crtc->bpp = pipe_bpp;
5787 I915_WRITE(PIPECONF(pipe), temp);
5788
8febb297
EA		 5789 if (!lane) {
5790 /*
5791 * Account for spread spectrum to avoid
5792 * oversubscribing the link. Max center spread
5793 * is 2.5%; use 5% for safety's sake.
5794 */
5a354204 5795 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5796 lane = bps / (link_bw * 8) + 1;
5eb08b69 5797 }
2c07245f 5798
8febb297
EA		 5799 intel_crtc->fdi_lanes = lane;
5800
5801 if (pixel_multiplier > 1)
5802 link_bw *= pixel_multiplier;
5a354204
JB		 5803 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5804 &m_n);
8febb297 5805
a07d6787
EA		 5806 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5807 if (has_reduced_clock)
5808 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5809 reduced_clock.m2;
79e53945 5810
c1858123 5811 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5812 factor = 21;
5813 if (is_lvds) {
5814 if ((intel_panel_use_ssc(dev_priv) &&
5815 dev_priv->lvds_ssc_freq == 100) ||
5816 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5817 factor = 25;
5818 } else if (is_sdvo && is_tv)
5819 factor = 20;
c1858123 5820
cb0e0931 5821 if (clock.m < factor * clock.n)
8febb297 5822 fp |= FP_CB_TUNE;
2c07245f 5823
5eddb70b 5824 dpll = 0;
2c07245f 5825
a07d6787
EA		 5826 if (is_lvds)
5827 dpll |= DPLLB_MODE_LVDS;
5828 else
5829 dpll |= DPLLB_MODE_DAC_SERIAL;
5830 if (is_sdvo) {
5831 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5832 if (pixel_multiplier > 1) {
5833 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5834 }
a07d6787
EA		 5835 dpll |= DPLL_DVO_HIGH_SPEED;
5836 }
5837 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5838 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5839
a07d6787
EA		 5840 /* compute bitmask from p1 value */
5841 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5842 /* also FPA1 */
5843 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5844
5845 switch (clock.p2) {
5846 case 5:
5847 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5848 break;
5849 case 7:
5850 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5851 break;
5852 case 10:
5853 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5854 break;
5855 case 14:
5856 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5857 break;
79e53945
JB		 5858 }
5859
43565a06
KH		 5860 if (is_sdvo && is_tv)
5861 dpll |= PLL_REF_INPUT_TVCLKINBC;
5862 else if (is_tv)
79e53945 5863 /* XXX: just matching BIOS for now */
43565a06 5864 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5865 dpll |= 3;
a7615030 5866 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5867 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5868 else
5869 dpll |= PLL_REF_INPUT_DREFCLK;
5870
5871 /* setup pipeconf */
5eddb70b 5872 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5873
5874 /* Set up the display plane register */
5875 dspcntr = DISPPLANE_GAMMA_ENABLE;
5876
f7cb34d4 5877 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5878 drm_mode_debug_printmodeline(mode);
5879
5c5313c8 5880 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14
JB		 5881 if (!intel_crtc->no_pll) {
5882 if (!has_edp_encoder ||
5883 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5884 I915_WRITE(PCH_FP0(pipe), fp);
5885 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5886
5887 POSTING_READ(PCH_DPLL(pipe));
5888 udelay(150);
5889 }
5890 } else {
5891 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5892 fp == I915_READ(PCH_FP0(0))) {
5893 intel_crtc->use_pll_a = true;
5894 DRM_DEBUG_KMS("using pipe a dpll\n");
5895 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5896 fp == I915_READ(PCH_FP0(1))) {
5897 intel_crtc->use_pll_a = false;
5898 DRM_DEBUG_KMS("using pipe b dpll\n");
5899 } else {
5900 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5901 return -EINVAL;
5902 }
79e53945
JB		 5903 }
5904
5905 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5906 * This is an exception to the general rule that mode_set doesn't turn
5907 * things on.
5908 */
5909 if (is_lvds) {
fae14981 5910 temp = I915_READ(PCH_LVDS);
5eddb70b 5911 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5912 if (HAS_PCH_CPT(dev)) {
5913 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5914 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5915 } else {
5916 if (pipe == 1)
5917 temp |= LVDS_PIPEB_SELECT;
5918 else
5919 temp &= ~LVDS_PIPEB_SELECT;
5920 }
4b645f14 5921
a3e17eb8 5922 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5923 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5924 /* Set the B0-B3 data pairs corresponding to whether we're going to
5925 * set the DPLLs for dual-channel mode or not.
5926 */
5927 if (clock.p2 == 7)
5eddb70b 5928 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5929 else
5eddb70b 5930 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5931
5932 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5933 * appropriately here, but we need to look more thoroughly into how
5934 * panels behave in the two modes.
5935 */
aa9b500d
BF		 5936 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5937 lvds_sync |= LVDS_HSYNC_POLARITY;
5938 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5939 lvds_sync |= LVDS_VSYNC_POLARITY;
5940 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5941 != lvds_sync) {
5942 char flags[2] = "-+";
5943 DRM_INFO("Changing LVDS panel from "
5944 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5945 flags[!(temp & LVDS_HSYNC_POLARITY)],
5946 flags[!(temp & LVDS_VSYNC_POLARITY)],
5947 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5948 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5949 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5950 temp |= lvds_sync;
5951 }
fae14981 5952 I915_WRITE(PCH_LVDS, temp);
79e53945 5953 }
434ed097 5954
8febb297
EA		 5955 pipeconf &= ~PIPECONF_DITHER_EN;
5956 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5957 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 5958 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 5959 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 5960 }
5c5313c8 5961 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5962 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5963 } else {
8db9d77b 5964 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5965 I915_WRITE(TRANSDATA_M1(pipe), 0);
5966 I915_WRITE(TRANSDATA_N1(pipe), 0);
5967 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5968 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5969 }
79e53945 5970
4b645f14
JB		 5971 if (!intel_crtc->no_pll &&
5972 (!has_edp_encoder ||
5973 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
fae14981 5974 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5975
32f9d658 5976 /* Wait for the clocks to stabilize. */
fae14981 5977 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5978 udelay(150);
5979
8febb297
EA		 5980 /* The pixel multiplier can only be updated once the
5981 * DPLL is enabled and the clocks are stable.
5982 *
5983 * So write it again.
5984 */
fae14981 5985 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5986 }
79e53945 5987
5eddb70b 5988 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 5989 if (!intel_crtc->no_pll) {
5990 if (is_lvds && has_reduced_clock && i915_powersave) {
5991 I915_WRITE(PCH_FP1(pipe), fp2);
5992 intel_crtc->lowfreq_avail = true;
5993 if (HAS_PIPE_CXSR(dev)) {
5994 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5995 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5996 }
5997 } else {
5998 I915_WRITE(PCH_FP1(pipe), fp);
5999 if (HAS_PIPE_CXSR(dev)) {
6000 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6001 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
6002 }
652c393a
JB		 6003 }
6004 }
6005
617cf884 6006 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 6007 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 6008 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 6009 /* the chip adds 2 halflines automatically */
734b4157 6010 adjusted_mode->crtc_vtotal -= 1;
734b4157 6011 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 6012 I915_WRITE(VSYNCSHIFT(pipe),
6013 adjusted_mode->crtc_hsync_start
6014 - adjusted_mode->crtc_htotal/2);
6015 } else {
617cf884 6016 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 6017 I915_WRITE(VSYNCSHIFT(pipe), 0);
6018 }
734b4157 6019
5eddb70b
CW		 6020 I915_WRITE(HTOTAL(pipe),
6021 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 6022 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 6023 I915_WRITE(HBLANK(pipe),
6024 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 6025 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 6026 I915_WRITE(HSYNC(pipe),
6027 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 6028 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 6029
6030 I915_WRITE(VTOTAL(pipe),
6031 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 6032 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 6033 I915_WRITE(VBLANK(pipe),
6034 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 6035 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 6036 I915_WRITE(VSYNC(pipe),
6037 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 6038 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 6039
8febb297
EA		 6040 /* pipesrc controls the size that is scaled from, which should
6041 * always be the user's requested size.
79e53945 6042 */
5eddb70b
CW		 6043 I915_WRITE(PIPESRC(pipe),
6044 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 6045
8febb297
EA		 6046 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6047 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6048 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6049 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 6050
8febb297
EA		 6051 if (has_edp_encoder &&
6052 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6053 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 6054 }
6055
5eddb70b
CW		 6056 I915_WRITE(PIPECONF(pipe), pipeconf);
6057 POSTING_READ(PIPECONF(pipe));
79e53945 6058
9d0498a2 6059 intel_wait_for_vblank(dev, pipe);
79e53945 6060
5eddb70b 6061 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 6062 POSTING_READ(DSPCNTR(plane));
79e53945 6063
5c3b82e2 6064 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 6065
6066 intel_update_watermarks(dev);
6067
1f803ee5 6068 return ret;
79e53945
JB		 6069}
6070
f564048e
EA		 6071static int intel_crtc_mode_set(struct drm_crtc *crtc,
6072 struct drm_display_mode *mode,
6073 struct drm_display_mode *adjusted_mode,
6074 int x, int y,
6075 struct drm_framebuffer *old_fb)
6076{
6077 struct drm_device *dev = crtc->dev;
6078 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 6079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6080 int pipe = intel_crtc->pipe;
f564048e
EA		 6081 int ret;
6082
0b701d27 6083 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6084
f564048e
EA		 6085 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6086 x, y, old_fb);
79e53945 6087 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6088
d8e70a25
JB		 6089 if (ret)
6090 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6091 else
6092 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 6093
1f803ee5 6094 return ret;
79e53945
JB		 6095}
6096
3a9627f4
WF		 6097static bool intel_eld_uptodate(struct drm_connector *connector,
6098 int reg_eldv, uint32_t bits_eldv,
6099 int reg_elda, uint32_t bits_elda,
6100 int reg_edid)
6101{
6102 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6103 uint8_t *eld = connector->eld;
6104 uint32_t i;
6105
6106 i = I915_READ(reg_eldv);
6107 i &= bits_eldv;
6108
6109 if (!eld[0])
6110 return !i;
6111
6112 if (!i)
6113 return false;
6114
6115 i = I915_READ(reg_elda);
6116 i &= ~bits_elda;
6117 I915_WRITE(reg_elda, i);
6118
6119 for (i = 0; i < eld[2]; i++)
6120 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6121 return false;
6122
6123 return true;
6124}
6125
e0dac65e
WF		 6126static void g4x_write_eld(struct drm_connector *connector,
6127 struct drm_crtc *crtc)
6128{
6129 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6130 uint8_t *eld = connector->eld;
6131 uint32_t eldv;
6132 uint32_t len;
6133 uint32_t i;
6134
6135 i = I915_READ(G4X_AUD_VID_DID);
6136
6137 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6138 eldv = G4X_ELDV_DEVCL_DEVBLC;
6139 else
6140 eldv = G4X_ELDV_DEVCTG;
6141
3a9627f4
WF		 6142 if (intel_eld_uptodate(connector,
6143 G4X_AUD_CNTL_ST, eldv,
6144 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6145 G4X_HDMIW_HDMIEDID))
6146 return;
6147
e0dac65e
WF		 6148 i = I915_READ(G4X_AUD_CNTL_ST);
6149 i &= ~(eldv | G4X_ELD_ADDR);
6150 len = (i >> 9) & 0x1f; /* ELD buffer size */
6151 I915_WRITE(G4X_AUD_CNTL_ST, i);
6152
6153 if (!eld[0])
6154 return;
6155
6156 len = min_t(uint8_t, eld[2], len);
6157 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6158 for (i = 0; i < len; i++)
6159 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6160
6161 i = I915_READ(G4X_AUD_CNTL_ST);
6162 i |= eldv;
6163 I915_WRITE(G4X_AUD_CNTL_ST, i);
6164}
6165
6166static void ironlake_write_eld(struct drm_connector *connector,
6167 struct drm_crtc *crtc)
6168{
6169 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6170 uint8_t *eld = connector->eld;
6171 uint32_t eldv;
6172 uint32_t i;
6173 int len;
6174 int hdmiw_hdmiedid;
b6daa025 6175 int aud_config;
e0dac65e
WF		 6176 int aud_cntl_st;
6177 int aud_cntrl_st2;
6178
b3f33cbf 6179 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 6180 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 6181 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 6182 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6183 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6184 } else {
1202b4c6 6185 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 6186 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 6187 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6188 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6189 }
6190
6191 i = to_intel_crtc(crtc)->pipe;
6192 hdmiw_hdmiedid += i * 0x100;
6193 aud_cntl_st += i * 0x100;
b6daa025 6194 aud_config += i * 0x100;
e0dac65e
WF		 6195
6196 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6197
6198 i = I915_READ(aud_cntl_st);
6199 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6200 if (!i) {
6201 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6202 /* operate blindly on all ports */
1202b4c6
WF		 6203 eldv = IBX_ELD_VALIDB;
6204 eldv |= IBX_ELD_VALIDB << 4;
6205 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6206 } else {
6207 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6208 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6209 }
6210
3a9627f4
WF		 6211 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6212 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6213 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6214 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6215 } else
6216 I915_WRITE(aud_config, 0);
e0dac65e 6217
3a9627f4
WF		 6218 if (intel_eld_uptodate(connector,
6219 aud_cntrl_st2, eldv,
6220 aud_cntl_st, IBX_ELD_ADDRESS,
6221 hdmiw_hdmiedid))
6222 return;
6223
e0dac65e
WF		 6224 i = I915_READ(aud_cntrl_st2);
6225 i &= ~eldv;
6226 I915_WRITE(aud_cntrl_st2, i);
6227
6228 if (!eld[0])
6229 return;
6230
e0dac65e 6231 i = I915_READ(aud_cntl_st);
1202b4c6 6232 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6233 I915_WRITE(aud_cntl_st, i);
6234
6235 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6236 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6237 for (i = 0; i < len; i++)
6238 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6239
6240 i = I915_READ(aud_cntrl_st2);
6241 i |= eldv;
6242 I915_WRITE(aud_cntrl_st2, i);
6243}
6244
6245void intel_write_eld(struct drm_encoder *encoder,
6246 struct drm_display_mode *mode)
6247{
6248 struct drm_crtc *crtc = encoder->crtc;
6249 struct drm_connector *connector;
6250 struct drm_device *dev = encoder->dev;
6251 struct drm_i915_private *dev_priv = dev->dev_private;
6252
6253 connector = drm_select_eld(encoder, mode);
6254 if (!connector)
6255 return;
6256
6257 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6258 connector->base.id,
6259 drm_get_connector_name(connector),
6260 connector->encoder->base.id,
6261 drm_get_encoder_name(connector->encoder));
6262
6263 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6264
6265 if (dev_priv->display.write_eld)
6266 dev_priv->display.write_eld(connector, crtc);
6267}
6268
79e53945
JB		 6269/** Loads the palette/gamma unit for the CRTC with the prepared values */
6270void intel_crtc_load_lut(struct drm_crtc *crtc)
6271{
6272 struct drm_device *dev = crtc->dev;
6273 struct drm_i915_private *dev_priv = dev->dev_private;
6274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6275 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6276 int i;
6277
6278 /* The clocks have to be on to load the palette. */
6279 if (!crtc->enabled)
6280 return;
6281
f2b115e6 6282 /* use legacy palette for Ironlake */
bad720ff 6283 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6284 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6285
79e53945
JB		 6286 for (i = 0; i < 256; i++) {
6287 I915_WRITE(palreg + 4 * i,
6288 (intel_crtc->lut_r[i] << 16) |
6289 (intel_crtc->lut_g[i] << 8) |
6290 intel_crtc->lut_b[i]);
6291 }
6292}
6293
560b85bb
CW		 6294static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6295{
6296 struct drm_device *dev = crtc->dev;
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6299 bool visible = base != 0;
6300 u32 cntl;
6301
6302 if (intel_crtc->cursor_visible == visible)
6303 return;
6304
9db4a9c7 6305 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6306 if (visible) {
6307 /* On these chipsets we can only modify the base whilst
6308 * the cursor is disabled.
6309 */
9db4a9c7 6310 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6311
6312 cntl &= ~(CURSOR_FORMAT_MASK);
6313 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6314 cntl |= CURSOR_ENABLE |
6315 CURSOR_GAMMA_ENABLE |
6316 CURSOR_FORMAT_ARGB;
6317 } else
6318 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6319 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6320
6321 intel_crtc->cursor_visible = visible;
6322}
6323
6324static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6325{
6326 struct drm_device *dev = crtc->dev;
6327 struct drm_i915_private *dev_priv = dev->dev_private;
6328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6329 int pipe = intel_crtc->pipe;
6330 bool visible = base != 0;
6331
6332 if (intel_crtc->cursor_visible != visible) {
548f245b 6333 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6334 if (base) {
6335 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6336 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6337 cntl |= pipe << 28; /* Connect to correct pipe */
6338 } else {
6339 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6340 cntl |= CURSOR_MODE_DISABLE;
6341 }
9db4a9c7 6342 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6343
6344 intel_crtc->cursor_visible = visible;
6345 }
6346 /* and commit changes on next vblank */
9db4a9c7 6347 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6348}
6349
65a21cd6
JB		 6350static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6351{
6352 struct drm_device *dev = crtc->dev;
6353 struct drm_i915_private *dev_priv = dev->dev_private;
6354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6355 int pipe = intel_crtc->pipe;
6356 bool visible = base != 0;
6357
6358 if (intel_crtc->cursor_visible != visible) {
6359 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6360 if (base) {
6361 cntl &= ~CURSOR_MODE;
6362 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6363 } else {
6364 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6365 cntl |= CURSOR_MODE_DISABLE;
6366 }
6367 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6368
6369 intel_crtc->cursor_visible = visible;
6370 }
6371 /* and commit changes on next vblank */
6372 I915_WRITE(CURBASE_IVB(pipe), base);
6373}
6374
cda4b7d3 6375/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6376static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6377 bool on)
cda4b7d3
CW		 6378{
6379 struct drm_device *dev = crtc->dev;
6380 struct drm_i915_private *dev_priv = dev->dev_private;
6381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6382 int pipe = intel_crtc->pipe;
6383 int x = intel_crtc->cursor_x;
6384 int y = intel_crtc->cursor_y;
560b85bb 6385 u32 base, pos;
cda4b7d3
CW		 6386 bool visible;
6387
6388 pos = 0;
6389
6b383a7f 6390 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6391 base = intel_crtc->cursor_addr;
6392 if (x > (int) crtc->fb->width)
6393 base = 0;
6394
6395 if (y > (int) crtc->fb->height)
6396 base = 0;
6397 } else
6398 base = 0;
6399
6400 if (x < 0) {
6401 if (x + intel_crtc->cursor_width < 0)
6402 base = 0;
6403
6404 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6405 x = -x;
6406 }
6407 pos |= x << CURSOR_X_SHIFT;
6408
6409 if (y < 0) {
6410 if (y + intel_crtc->cursor_height < 0)
6411 base = 0;
6412
6413 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6414 y = -y;
6415 }
6416 pos |= y << CURSOR_Y_SHIFT;
6417
6418 visible = base != 0;
560b85bb 6419 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6420 return;
6421
65a21cd6
JB		 6422 if (IS_IVYBRIDGE(dev)) {
6423 I915_WRITE(CURPOS_IVB(pipe), pos);
6424 ivb_update_cursor(crtc, base);
6425 } else {
6426 I915_WRITE(CURPOS(pipe), pos);
6427 if (IS_845G(dev) || IS_I865G(dev))
6428 i845_update_cursor(crtc, base);
6429 else
6430 i9xx_update_cursor(crtc, base);
6431 }
cda4b7d3
CW		 6432
6433 if (visible)
6434 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6435}
6436
79e53945 6437static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6438 struct drm_file *file,
79e53945
JB		 6439 uint32_t handle,
6440 uint32_t width, uint32_t height)
6441{
6442 struct drm_device *dev = crtc->dev;
6443 struct drm_i915_private *dev_priv = dev->dev_private;
6444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6445 struct drm_i915_gem_object *obj;
cda4b7d3 6446 uint32_t addr;
3f8bc370 6447 int ret;
79e53945 6448
28c97730 6449 DRM_DEBUG_KMS("\n");
79e53945
JB		 6450
6451 /* if we want to turn off the cursor ignore width and height */
6452 if (!handle) {
28c97730 6453 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6454 addr = 0;
05394f39 6455 obj = NULL;
5004417d 6456 mutex_lock(&dev->struct_mutex);
3f8bc370 6457 goto finish;
79e53945
JB		 6458 }
6459
6460 /* Currently we only support 64x64 cursors */
6461 if (width != 64 || height != 64) {
6462 DRM_ERROR("we currently only support 64x64 cursors\n");
6463 return -EINVAL;
6464 }
6465
05394f39 6466 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6467 if (&obj->base == NULL)
79e53945
JB		 6468 return -ENOENT;
6469
05394f39 6470 if (obj->base.size < width * height * 4) {
79e53945 6471 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6472 ret = -ENOMEM;
6473 goto fail;
79e53945
JB		 6474 }
6475
71acb5eb 6476 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6477 mutex_lock(&dev->struct_mutex);
b295d1b6 6478 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6479 if (obj->tiling_mode) {
6480 DRM_ERROR("cursor cannot be tiled\n");
6481 ret = -EINVAL;
6482 goto fail_locked;
6483 }
6484
2da3b9b9 6485 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6486 if (ret) {
6487 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6488 goto fail_locked;
e7b526bb
CW		 6489 }
6490
d9e86c0e
CW		 6491 ret = i915_gem_object_put_fence(obj);
6492 if (ret) {
2da3b9b9 6493 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6494 goto fail_unpin;
6495 }
6496
05394f39 6497 addr = obj->gtt_offset;
71acb5eb 6498 } else {
6eeefaf3 6499 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6500 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6501 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6502 align);
71acb5eb
DA		 6503 if (ret) {
6504 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6505 goto fail_locked;
71acb5eb 6506 }
05394f39 6507 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6508 }
6509
a6c45cf0 6510 if (IS_GEN2(dev))
14b60391
JB		 6511 I915_WRITE(CURSIZE, (height << 12) | width);
6512
3f8bc370 6513 finish:
3f8bc370 6514 if (intel_crtc->cursor_bo) {
b295d1b6 6515 if (dev_priv->info->cursor_needs_physical) {
05394f39 6516 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6517 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6518 } else
6519 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6520 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6521 }
80824003 6522
7f9872e0 6523 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6524
6525 intel_crtc->cursor_addr = addr;
05394f39 6526 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6527 intel_crtc->cursor_width = width;
6528 intel_crtc->cursor_height = height;
6529
6b383a7f 6530 intel_crtc_update_cursor(crtc, true);
3f8bc370 6531
79e53945 6532 return 0;
e7b526bb 6533fail_unpin:
05394f39 6534 i915_gem_object_unpin(obj);
7f9872e0 6535fail_locked:
34b8686e 6536 mutex_unlock(&dev->struct_mutex);
bc9025bd 6537fail:
05394f39 6538 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6539 return ret;
79e53945
JB		 6540}
6541
6542static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6543{
79e53945 6544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6545
cda4b7d3
CW		 6546 intel_crtc->cursor_x = x;
6547 intel_crtc->cursor_y = y;
652c393a 6548
6b383a7f 6549 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6550
6551 return 0;
6552}
6553
6554/** Sets the color ramps on behalf of RandR */
6555void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6556 u16 blue, int regno)
6557{
6558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6559
6560 intel_crtc->lut_r[regno] = red >> 8;
6561 intel_crtc->lut_g[regno] = green >> 8;
6562 intel_crtc->lut_b[regno] = blue >> 8;
6563}
6564
b8c00ac5
DA		 6565void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6566 u16 *blue, int regno)
6567{
6568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6569
6570 *red = intel_crtc->lut_r[regno] << 8;
6571 *green = intel_crtc->lut_g[regno] << 8;
6572 *blue = intel_crtc->lut_b[regno] << 8;
6573}
6574
79e53945 6575static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6576 u16 *blue, uint32_t start, uint32_t size)
79e53945 6577{
7203425a 6578 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6580
7203425a 6581 for (i = start; i < end; i++) {
79e53945
JB		 6582 intel_crtc->lut_r[i] = red[i] >> 8;
6583 intel_crtc->lut_g[i] = green[i] >> 8;
6584 intel_crtc->lut_b[i] = blue[i] >> 8;
6585 }
6586
6587 intel_crtc_load_lut(crtc);
6588}
6589
6590/**
6591 * Get a pipe with a simple mode set on it for doing load-based monitor
6592 * detection.
6593 *
6594 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6595 * its requirements. The pipe will be connected to no other encoders.
79e53945 6596 *
c751ce4f 6597 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6598 * configured for it. In the future, it could choose to temporarily disable
6599 * some outputs to free up a pipe for its use.
6600 *
6601 * \return crtc, or NULL if no pipes are available.
6602 */
6603
6604/* VESA 640x480x72Hz mode to set on the pipe */
6605static struct drm_display_mode load_detect_mode = {
6606 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6607 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6608};
6609
d2dff872
CW		 6610static struct drm_framebuffer *
6611intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6612 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6613 struct drm_i915_gem_object *obj)
6614{
6615 struct intel_framebuffer *intel_fb;
6616 int ret;
6617
6618 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6619 if (!intel_fb) {
6620 drm_gem_object_unreference_unlocked(&obj->base);
6621 return ERR_PTR(-ENOMEM);
6622 }
6623
6624 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6625 if (ret) {
6626 drm_gem_object_unreference_unlocked(&obj->base);
6627 kfree(intel_fb);
6628 return ERR_PTR(ret);
6629 }
6630
6631 return &intel_fb->base;
6632}
6633
6634static u32
6635intel_framebuffer_pitch_for_width(int width, int bpp)
6636{
6637 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6638 return ALIGN(pitch, 64);
6639}
6640
6641static u32
6642intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6643{
6644 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6645 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6646}
6647
6648static struct drm_framebuffer *
6649intel_framebuffer_create_for_mode(struct drm_device *dev,
6650 struct drm_display_mode *mode,
6651 int depth, int bpp)
6652{
6653 struct drm_i915_gem_object *obj;
308e5bcb 6654 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6655
6656 obj = i915_gem_alloc_object(dev,
6657 intel_framebuffer_size_for_mode(mode, bpp));
6658 if (obj == NULL)
6659 return ERR_PTR(-ENOMEM);
6660
6661 mode_cmd.width = mode->hdisplay;
6662 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6663 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6664 bpp);
6665 mode_cmd.pixel_format = 0;
d2dff872
CW		 6666
6667 return intel_framebuffer_create(dev, &mode_cmd, obj);
6668}
6669
6670static struct drm_framebuffer *
6671mode_fits_in_fbdev(struct drm_device *dev,
6672 struct drm_display_mode *mode)
6673{
6674 struct drm_i915_private *dev_priv = dev->dev_private;
6675 struct drm_i915_gem_object *obj;
6676 struct drm_framebuffer *fb;
6677
6678 if (dev_priv->fbdev == NULL)
6679 return NULL;
6680
6681 obj = dev_priv->fbdev->ifb.obj;
6682 if (obj == NULL)
6683 return NULL;
6684
6685 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6686 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6687 fb->bits_per_pixel))
d2dff872
CW		 6688 return NULL;
6689
01f2c773 6690 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6691 return NULL;
6692
6693 return fb;
6694}
6695
7173188d
CW		 6696bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6697 struct drm_connector *connector,
6698 struct drm_display_mode *mode,
8261b191 6699 struct intel_load_detect_pipe *old)
79e53945
JB		 6700{
6701 struct intel_crtc *intel_crtc;
6702 struct drm_crtc *possible_crtc;
4ef69c7a 6703 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6704 struct drm_crtc *crtc = NULL;
6705 struct drm_device *dev = encoder->dev;
d2dff872 6706 struct drm_framebuffer *old_fb;
79e53945
JB		 6707 int i = -1;
6708
d2dff872
CW		 6709 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6710 connector->base.id, drm_get_connector_name(connector),
6711 encoder->base.id, drm_get_encoder_name(encoder));
6712
79e53945
JB		 6713 /*
6714 * Algorithm gets a little messy:
7a5e4805 6715 *
79e53945
JB		 6716 * - if the connector already has an assigned crtc, use it (but make
6717 * sure it's on first)
7a5e4805 6718 *
79e53945
JB		 6719 * - try to find the first unused crtc that can drive this connector,
6720 * and use that if we find one
79e53945
JB		 6721 */
6722
6723 /* See if we already have a CRTC for this connector */
6724 if (encoder->crtc) {
6725 crtc = encoder->crtc;
8261b191 6726
79e53945 6727 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6728 old->dpms_mode = intel_crtc->dpms_mode;
6729 old->load_detect_temp = false;
6730
6731 /* Make sure the crtc and connector are running */
79e53945 6732 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6733 struct drm_encoder_helper_funcs *encoder_funcs;
6734 struct drm_crtc_helper_funcs *crtc_funcs;
6735
79e53945
JB		 6736 crtc_funcs = crtc->helper_private;
6737 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6738
6739 encoder_funcs = encoder->helper_private;
79e53945
JB		 6740 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6741 }
8261b191 6742
7173188d 6743 return true;
79e53945
JB		 6744 }
6745
6746 /* Find an unused one (if possible) */
6747 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6748 i++;
6749 if (!(encoder->possible_crtcs & (1 << i)))
6750 continue;
6751 if (!possible_crtc->enabled) {
6752 crtc = possible_crtc;
6753 break;
6754 }
79e53945
JB		 6755 }
6756
6757 /*
6758 * If we didn't find an unused CRTC, don't use any.
6759 */
6760 if (!crtc) {
7173188d
CW		 6761 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6762 return false;
79e53945
JB		 6763 }
6764
6765 encoder->crtc = crtc;
c1c43977 6766 connector->encoder = encoder;
79e53945
JB		 6767
6768 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6769 old->dpms_mode = intel_crtc->dpms_mode;
6770 old->load_detect_temp = true;
d2dff872 6771 old->release_fb = NULL;
79e53945 6772
6492711d
CW		 6773 if (!mode)
6774 mode = &load_detect_mode;
79e53945 6775
d2dff872
CW		 6776 old_fb = crtc->fb;
6777
6778 /* We need a framebuffer large enough to accommodate all accesses
6779 * that the plane may generate whilst we perform load detection.
6780 * We can not rely on the fbcon either being present (we get called
6781 * during its initialisation to detect all boot displays, or it may
6782 * not even exist) or that it is large enough to satisfy the
6783 * requested mode.
6784 */
6785 crtc->fb = mode_fits_in_fbdev(dev, mode);
6786 if (crtc->fb == NULL) {
6787 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6788 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6789 old->release_fb = crtc->fb;
6790 } else
6791 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6792 if (IS_ERR(crtc->fb)) {
6793 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6794 crtc->fb = old_fb;
6795 return false;
79e53945 6796 }
79e53945 6797
d2dff872 6798 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6799 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6800 if (old->release_fb)
6801 old->release_fb->funcs->destroy(old->release_fb);
6802 crtc->fb = old_fb;
6492711d 6803 return false;
79e53945 6804 }
7173188d 6805
79e53945 6806 /* let the connector get through one full cycle before testing */
9d0498a2 6807 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6808
7173188d 6809 return true;
79e53945
JB		 6810}
6811
c1c43977 6812void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6813 struct drm_connector *connector,
6814 struct intel_load_detect_pipe *old)
79e53945 6815{
4ef69c7a 6816 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6817 struct drm_device *dev = encoder->dev;
6818 struct drm_crtc *crtc = encoder->crtc;
6819 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6820 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6821
d2dff872
CW		 6822 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6823 connector->base.id, drm_get_connector_name(connector),
6824 encoder->base.id, drm_get_encoder_name(encoder));
6825
8261b191 6826 if (old->load_detect_temp) {
c1c43977 6827 connector->encoder = NULL;
79e53945 6828 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6829
6830 if (old->release_fb)
6831 old->release_fb->funcs->destroy(old->release_fb);
6832
0622a53c 6833 return;
79e53945
JB		 6834 }
6835
c751ce4f 6836 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6837 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6838 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6839 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6840 }
6841}
6842
6843/* Returns the clock of the currently programmed mode of the given pipe. */
6844static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6845{
6846 struct drm_i915_private *dev_priv = dev->dev_private;
6847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6848 int pipe = intel_crtc->pipe;
548f245b 6849 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6850 u32 fp;
6851 intel_clock_t clock;
6852
6853 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6854 fp = I915_READ(FP0(pipe));
79e53945 6855 else
39adb7a5 6856 fp = I915_READ(FP1(pipe));
79e53945
JB		 6857
6858 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6859 if (IS_PINEVIEW(dev)) {
6860 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6861 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6862 } else {
6863 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6864 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6865 }
6866
a6c45cf0 6867 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6868 if (IS_PINEVIEW(dev))
6869 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6870 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6871 else
6872 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6873 DPLL_FPA01_P1_POST_DIV_SHIFT);
6874
6875 switch (dpll & DPLL_MODE_MASK) {
6876 case DPLLB_MODE_DAC_SERIAL:
6877 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6878 5 : 10;
6879 break;
6880 case DPLLB_MODE_LVDS:
6881 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6882 7 : 14;
6883 break;
6884 default:
28c97730 6885 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6886 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6887 return 0;
6888 }
6889
6890 /* XXX: Handle the 100Mhz refclk */
2177832f 6891 intel_clock(dev, 96000, &clock);
79e53945
JB		 6892 } else {
6893 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6894
6895 if (is_lvds) {
6896 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6897 DPLL_FPA01_P1_POST_DIV_SHIFT);
6898 clock.p2 = 14;
6899
6900 if ((dpll & PLL_REF_INPUT_MASK) ==
6901 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6902 /* XXX: might not be 66MHz */
2177832f 6903 intel_clock(dev, 66000, &clock);
79e53945 6904 } else
2177832f 6905 intel_clock(dev, 48000, &clock);
79e53945
JB		 6906 } else {
6907 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6908 clock.p1 = 2;
6909 else {
6910 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6911 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6912 }
6913 if (dpll & PLL_P2_DIVIDE_BY_4)
6914 clock.p2 = 4;
6915 else
6916 clock.p2 = 2;
6917
2177832f 6918 intel_clock(dev, 48000, &clock);
79e53945
JB		 6919 }
6920 }
6921
6922 /* XXX: It would be nice to validate the clocks, but we can't reuse
6923 * i830PllIsValid() because it relies on the xf86_config connector
6924 * configuration being accurate, which it isn't necessarily.
6925 */
6926
6927 return clock.dot;
6928}
6929
6930/** Returns the currently programmed mode of the given pipe. */
6931struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6932 struct drm_crtc *crtc)
6933{
548f245b 6934 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6936 int pipe = intel_crtc->pipe;
6937 struct drm_display_mode *mode;
548f245b
JB		 6938 int htot = I915_READ(HTOTAL(pipe));
6939 int hsync = I915_READ(HSYNC(pipe));
6940 int vtot = I915_READ(VTOTAL(pipe));
6941 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6942
6943 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6944 if (!mode)
6945 return NULL;
6946
6947 mode->clock = intel_crtc_clock_get(dev, crtc);
6948 mode->hdisplay = (htot & 0xffff) + 1;
6949 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6950 mode->hsync_start = (hsync & 0xffff) + 1;
6951 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6952 mode->vdisplay = (vtot & 0xffff) + 1;
6953 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6954 mode->vsync_start = (vsync & 0xffff) + 1;
6955 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6956
6957 drm_mode_set_name(mode);
6958 drm_mode_set_crtcinfo(mode, 0);
6959
6960 return mode;
6961}
6962
652c393a
JB		 6963#define GPU_IDLE_TIMEOUT 500 /* ms */
6964
6965/* When this timer fires, we've been idle for awhile */
6966static void intel_gpu_idle_timer(unsigned long arg)
6967{
6968 struct drm_device *dev = (struct drm_device *)arg;
6969 drm_i915_private_t *dev_priv = dev->dev_private;
6970
ff7ea4c0
CW		 6971 if (!list_empty(&dev_priv->mm.active_list)) {
6972 /* Still processing requests, so just re-arm the timer. */
6973 mod_timer(&dev_priv->idle_timer, jiffies +
6974 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6975 return;
6976 }
652c393a 6977
ff7ea4c0 6978 dev_priv->busy = false;
01dfba93 6979 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6980}
6981
652c393a
JB		 6982#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6983
6984static void intel_crtc_idle_timer(unsigned long arg)
6985{
6986 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6987 struct drm_crtc *crtc = &intel_crtc->base;
6988 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6989 struct intel_framebuffer *intel_fb;
652c393a 6990
ff7ea4c0
CW		 6991 intel_fb = to_intel_framebuffer(crtc->fb);
6992 if (intel_fb && intel_fb->obj->active) {
6993 /* The framebuffer is still being accessed by the GPU. */
6994 mod_timer(&intel_crtc->idle_timer, jiffies +
6995 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6996 return;
6997 }
652c393a 6998
ff7ea4c0 6999 intel_crtc->busy = false;
01dfba93 7000 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 7001}
7002
3dec0095 7003static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7004{
7005 struct drm_device *dev = crtc->dev;
7006 drm_i915_private_t *dev_priv = dev->dev_private;
7007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7008 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7009 int dpll_reg = DPLL(pipe);
7010 int dpll;
652c393a 7011
bad720ff 7012 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7013 return;
7014
7015 if (!dev_priv->lvds_downclock_avail)
7016 return;
7017
dbdc6479 7018 dpll = I915_READ(dpll_reg);
652c393a 7019 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7020 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7021
8ac5a6d5 7022 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7023
7024 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7025 I915_WRITE(dpll_reg, dpll);
9d0498a2 7026 intel_wait_for_vblank(dev, pipe);
dbdc6479 7027
652c393a
JB		 7028 dpll = I915_READ(dpll_reg);
7029 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7030 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 7031 }
7032
7033 /* Schedule downclock */
3dec0095
DV		 7034 mod_timer(&intel_crtc->idle_timer, jiffies +
7035 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 7036}
7037
7038static void intel_decrease_pllclock(struct drm_crtc *crtc)
7039{
7040 struct drm_device *dev = crtc->dev;
7041 drm_i915_private_t *dev_priv = dev->dev_private;
7042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7043 int pipe = intel_crtc->pipe;
9db4a9c7 7044 int dpll_reg = DPLL(pipe);
652c393a
JB		 7045 int dpll = I915_READ(dpll_reg);
7046
bad720ff 7047 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7048 return;
7049
7050 if (!dev_priv->lvds_downclock_avail)
7051 return;
7052
7053 /*
7054 * Since this is called by a timer, we should never get here in
7055 * the manual case.
7056 */
7057 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 7058 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7059
8ac5a6d5 7060 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7061
7062 dpll |= DISPLAY_RATE_SELECT_FPA1;
7063 I915_WRITE(dpll_reg, dpll);
9d0498a2 7064 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7065 dpll = I915_READ(dpll_reg);
7066 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7067 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7068 }
7069
7070}
7071
7072/**
7073 * intel_idle_update - adjust clocks for idleness
7074 * @work: work struct
7075 *
7076 * Either the GPU or display (or both) went idle. Check the busy status
7077 * here and adjust the CRTC and GPU clocks as necessary.
7078 */
7079static void intel_idle_update(struct work_struct *work)
7080{
7081 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7082 idle_work);
7083 struct drm_device *dev = dev_priv->dev;
7084 struct drm_crtc *crtc;
7085 struct intel_crtc *intel_crtc;
7086
7087 if (!i915_powersave)
7088 return;
7089
7090 mutex_lock(&dev->struct_mutex);
7091
7648fa99
JB		 7092 i915_update_gfx_val(dev_priv);
7093
652c393a
JB		 7094 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7095 /* Skip inactive CRTCs */
7096 if (!crtc->fb)
7097 continue;
7098
7099 intel_crtc = to_intel_crtc(crtc);
7100 if (!intel_crtc->busy)
7101 intel_decrease_pllclock(crtc);
7102 }
7103
45ac22c8 7104
652c393a
JB		 7105 mutex_unlock(&dev->struct_mutex);
7106}
7107
7108/**
7109 * intel_mark_busy - mark the GPU and possibly the display busy
7110 * @dev: drm device
7111 * @obj: object we're operating on
7112 *
7113 * Callers can use this function to indicate that the GPU is busy processing
7114 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7115 * buffer), we'll also mark the display as busy, so we know to increase its
7116 * clock frequency.
7117 */
05394f39 7118void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 7119{
7120 drm_i915_private_t *dev_priv = dev->dev_private;
7121 struct drm_crtc *crtc = NULL;
7122 struct intel_framebuffer *intel_fb;
7123 struct intel_crtc *intel_crtc;
7124
5e17ee74
ZW		 7125 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7126 return;
7127
18b2190c 7128 if (!dev_priv->busy)
28cf798f 7129 dev_priv->busy = true;
18b2190c 7130 else
28cf798f
CW		 7131 mod_timer(&dev_priv->idle_timer, jiffies +
7132 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 7133
7134 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7135 if (!crtc->fb)
7136 continue;
7137
7138 intel_crtc = to_intel_crtc(crtc);
7139 intel_fb = to_intel_framebuffer(crtc->fb);
7140 if (intel_fb->obj == obj) {
7141 if (!intel_crtc->busy) {
7142 /* Non-busy -> busy, upclock */
3dec0095 7143 intel_increase_pllclock(crtc);
652c393a
JB		 7144 intel_crtc->busy = true;
7145 } else {
7146 /* Busy -> busy, put off timer */
7147 mod_timer(&intel_crtc->idle_timer, jiffies +
7148 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7149 }
7150 }
7151 }
7152}
7153
79e53945
JB		 7154static void intel_crtc_destroy(struct drm_crtc *crtc)
7155{
7156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7157 struct drm_device *dev = crtc->dev;
7158 struct intel_unpin_work *work;
7159 unsigned long flags;
7160
7161 spin_lock_irqsave(&dev->event_lock, flags);
7162 work = intel_crtc->unpin_work;
7163 intel_crtc->unpin_work = NULL;
7164 spin_unlock_irqrestore(&dev->event_lock, flags);
7165
7166 if (work) {
7167 cancel_work_sync(&work->work);
7168 kfree(work);
7169 }
79e53945
JB		 7170
7171 drm_crtc_cleanup(crtc);
67e77c5a 7172
79e53945
JB		 7173 kfree(intel_crtc);
7174}
7175
6b95a207
KH		 7176static void intel_unpin_work_fn(struct work_struct *__work)
7177{
7178 struct intel_unpin_work *work =
7179 container_of(__work, struct intel_unpin_work, work);
7180
7181 mutex_lock(&work->dev->struct_mutex);
1690e1eb 7182 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7183 drm_gem_object_unreference(&work->pending_flip_obj->base);
7184 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7185
7782de3b 7186 intel_update_fbc(work->dev);
6b95a207
KH		 7187 mutex_unlock(&work->dev->struct_mutex);
7188 kfree(work);
7189}
7190
1afe3e9d 7191static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7192 struct drm_crtc *crtc)
6b95a207
KH		 7193{
7194 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7196 struct intel_unpin_work *work;
05394f39 7197 struct drm_i915_gem_object *obj;
6b95a207 7198 struct drm_pending_vblank_event *e;
49b14a5c 7199 struct timeval tnow, tvbl;
6b95a207
KH		 7200 unsigned long flags;
7201
7202 /* Ignore early vblank irqs */
7203 if (intel_crtc == NULL)
7204 return;
7205
49b14a5c
MK		 7206 do_gettimeofday(&tnow);
7207
6b95a207
KH		 7208 spin_lock_irqsave(&dev->event_lock, flags);
7209 work = intel_crtc->unpin_work;
7210 if (work == NULL || !work->pending) {
7211 spin_unlock_irqrestore(&dev->event_lock, flags);
7212 return;
7213 }
7214
7215 intel_crtc->unpin_work = NULL;
6b95a207
KH		 7216
7217 if (work->event) {
7218 e = work->event;
49b14a5c 7219 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 7220
7221 /* Called before vblank count and timestamps have
7222 * been updated for the vblank interval of flip
7223 * completion? Need to increment vblank count and
7224 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 7225 * to account for this. We assume this happened if we
7226 * get called over 0.9 frame durations after the last
7227 * timestamped vblank.
7228 *
7229 * This calculation can not be used with vrefresh rates
7230 * below 5Hz (10Hz to be on the safe side) without
7231 * promoting to 64 integers.
0af7e4df 7232 */
49b14a5c
MK		 7233 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7234 9 * crtc->framedur_ns) {
0af7e4df 7235 e->event.sequence++;
49b14a5c
MK		 7236 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7237 crtc->framedur_ns);
0af7e4df
MK		 7238 }
7239
49b14a5c
MK		 7240 e->event.tv_sec = tvbl.tv_sec;
7241 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 7242
6b95a207
KH		 7243 list_add_tail(&e->base.link,
7244 &e->base.file_priv->event_list);
7245 wake_up_interruptible(&e->base.file_priv->event_wait);
7246 }
7247
0af7e4df
MK		 7248 drm_vblank_put(dev, intel_crtc->pipe);
7249
6b95a207
KH		 7250 spin_unlock_irqrestore(&dev->event_lock, flags);
7251
05394f39 7252 obj = work->old_fb_obj;
d9e86c0e 7253
e59f2bac 7254 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 7255 &obj->pending_flip.counter);
7256 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 7257 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 7258
6b95a207 7259 schedule_work(&work->work);
e5510fac
JB		 7260
7261 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7262}
7263
1afe3e9d
JB		 7264void intel_finish_page_flip(struct drm_device *dev, int pipe)
7265{
7266 drm_i915_private_t *dev_priv = dev->dev_private;
7267 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7268
49b14a5c 7269 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7270}
7271
7272void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7273{
7274 drm_i915_private_t *dev_priv = dev->dev_private;
7275 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7276
49b14a5c 7277 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7278}
7279
6b95a207
KH		 7280void intel_prepare_page_flip(struct drm_device *dev, int plane)
7281{
7282 drm_i915_private_t *dev_priv = dev->dev_private;
7283 struct intel_crtc *intel_crtc =
7284 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7285 unsigned long flags;
7286
7287 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7288 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7289 if ((++intel_crtc->unpin_work->pending) > 1)
7290 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7291 } else {
7292 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7293 }
6b95a207
KH		 7294 spin_unlock_irqrestore(&dev->event_lock, flags);
7295}
7296
8c9f3aaf
JB		 7297static int intel_gen2_queue_flip(struct drm_device *dev,
7298 struct drm_crtc *crtc,
7299 struct drm_framebuffer *fb,
7300 struct drm_i915_gem_object *obj)
7301{
7302 struct drm_i915_private *dev_priv = dev->dev_private;
7303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7304 unsigned long offset;
7305 u32 flip_mask;
7306 int ret;
7307
7308 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7309 if (ret)
7310 goto out;
7311
7312 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7313 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7314
7315 ret = BEGIN_LP_RING(6);
7316 if (ret)
7317 goto out;
7318
7319 /* Can't queue multiple flips, so wait for the previous
7320 * one to finish before executing the next.
7321 */
7322 if (intel_crtc->plane)
7323 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7324 else
7325 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7326 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7327 OUT_RING(MI_NOOP);
7328 OUT_RING(MI_DISPLAY_FLIP |
7329 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7330 OUT_RING(fb->pitches[0]);
8c9f3aaf 7331 OUT_RING(obj->gtt_offset + offset);
c6a32fcb 7332 OUT_RING(0); /* aux display base address, unused */
8c9f3aaf
JB		 7333 ADVANCE_LP_RING();
7334out:
7335 return ret;
7336}
7337
7338static int intel_gen3_queue_flip(struct drm_device *dev,
7339 struct drm_crtc *crtc,
7340 struct drm_framebuffer *fb,
7341 struct drm_i915_gem_object *obj)
7342{
7343 struct drm_i915_private *dev_priv = dev->dev_private;
7344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7345 unsigned long offset;
7346 u32 flip_mask;
7347 int ret;
7348
7349 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7350 if (ret)
7351 goto out;
7352
7353 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7354 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7355
7356 ret = BEGIN_LP_RING(6);
7357 if (ret)
7358 goto out;
7359
7360 if (intel_crtc->plane)
7361 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7362 else
7363 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7364 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7365 OUT_RING(MI_NOOP);
7366 OUT_RING(MI_DISPLAY_FLIP_I915 |
7367 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7368 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7369 OUT_RING(obj->gtt_offset + offset);
7370 OUT_RING(MI_NOOP);
7371
7372 ADVANCE_LP_RING();
7373out:
7374 return ret;
7375}
7376
7377static int intel_gen4_queue_flip(struct drm_device *dev,
7378 struct drm_crtc *crtc,
7379 struct drm_framebuffer *fb,
7380 struct drm_i915_gem_object *obj)
7381{
7382 struct drm_i915_private *dev_priv = dev->dev_private;
7383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7384 uint32_t pf, pipesrc;
7385 int ret;
7386
7387 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7388 if (ret)
7389 goto out;
7390
7391 ret = BEGIN_LP_RING(4);
7392 if (ret)
7393 goto out;
7394
7395 /* i965+ uses the linear or tiled offsets from the
7396 * Display Registers (which do not change across a page-flip)
7397 * so we need only reprogram the base address.
7398 */
7399 OUT_RING(MI_DISPLAY_FLIP |
7400 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7401 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7402 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7403
7404 /* XXX Enabling the panel-fitter across page-flip is so far
7405 * untested on non-native modes, so ignore it for now.
7406 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7407 */
7408 pf = 0;
7409 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7410 OUT_RING(pf | pipesrc);
7411 ADVANCE_LP_RING();
7412out:
7413 return ret;
7414}
7415
7416static int intel_gen6_queue_flip(struct drm_device *dev,
7417 struct drm_crtc *crtc,
7418 struct drm_framebuffer *fb,
7419 struct drm_i915_gem_object *obj)
7420{
7421 struct drm_i915_private *dev_priv = dev->dev_private;
7422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7423 uint32_t pf, pipesrc;
7424 int ret;
7425
7426 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7427 if (ret)
7428 goto out;
7429
7430 ret = BEGIN_LP_RING(4);
7431 if (ret)
7432 goto out;
7433
7434 OUT_RING(MI_DISPLAY_FLIP |
7435 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7436 OUT_RING(fb->pitches[0] | obj->tiling_mode);
8c9f3aaf
JB		 7437 OUT_RING(obj->gtt_offset);
7438
7439 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7440 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7441 OUT_RING(pf | pipesrc);
7442 ADVANCE_LP_RING();
7443out:
7444 return ret;
7445}
7446
7c9017e5
JB		 7447/*
7448 * On gen7 we currently use the blit ring because (in early silicon at least)
7449 * the render ring doesn't give us interrpts for page flip completion, which
7450 * means clients will hang after the first flip is queued. Fortunately the
7451 * blit ring generates interrupts properly, so use it instead.
7452 */
7453static int intel_gen7_queue_flip(struct drm_device *dev,
7454 struct drm_crtc *crtc,
7455 struct drm_framebuffer *fb,
7456 struct drm_i915_gem_object *obj)
7457{
7458 struct drm_i915_private *dev_priv = dev->dev_private;
7459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7460 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7461 int ret;
7462
7463 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7464 if (ret)
7465 goto out;
7466
7467 ret = intel_ring_begin(ring, 4);
7468 if (ret)
7469 goto out;
7470
7471 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 7472 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 7473 intel_ring_emit(ring, (obj->gtt_offset));
7474 intel_ring_emit(ring, (MI_NOOP));
7475 intel_ring_advance(ring);
7476out:
7477 return ret;
7478}
7479
8c9f3aaf
JB		 7480static int intel_default_queue_flip(struct drm_device *dev,
7481 struct drm_crtc *crtc,
7482 struct drm_framebuffer *fb,
7483 struct drm_i915_gem_object *obj)
7484{
7485 return -ENODEV;
7486}
7487
6b95a207
KH		 7488static int intel_crtc_page_flip(struct drm_crtc *crtc,
7489 struct drm_framebuffer *fb,
7490 struct drm_pending_vblank_event *event)
7491{
7492 struct drm_device *dev = crtc->dev;
7493 struct drm_i915_private *dev_priv = dev->dev_private;
7494 struct intel_framebuffer *intel_fb;
05394f39 7495 struct drm_i915_gem_object *obj;
6b95a207
KH		 7496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7497 struct intel_unpin_work *work;
8c9f3aaf 7498 unsigned long flags;
52e68630 7499 int ret;
6b95a207
KH		 7500
7501 work = kzalloc(sizeof *work, GFP_KERNEL);
7502 if (work == NULL)
7503 return -ENOMEM;
7504
6b95a207
KH		 7505 work->event = event;
7506 work->dev = crtc->dev;
7507 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7508 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7509 INIT_WORK(&work->work, intel_unpin_work_fn);
7510
7317c75e
JB		 7511 ret = drm_vblank_get(dev, intel_crtc->pipe);
7512 if (ret)
7513 goto free_work;
7514
6b95a207
KH		 7515 /* We borrow the event spin lock for protecting unpin_work */
7516 spin_lock_irqsave(&dev->event_lock, flags);
7517 if (intel_crtc->unpin_work) {
7518 spin_unlock_irqrestore(&dev->event_lock, flags);
7519 kfree(work);
7317c75e 7520 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7521
7522 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7523 return -EBUSY;
7524 }
7525 intel_crtc->unpin_work = work;
7526 spin_unlock_irqrestore(&dev->event_lock, flags);
7527
7528 intel_fb = to_intel_framebuffer(fb);
7529 obj = intel_fb->obj;
7530
468f0b44 7531 mutex_lock(&dev->struct_mutex);
6b95a207 7532
75dfca80 7533 /* Reference the objects for the scheduled work. */
05394f39
CW		 7534 drm_gem_object_reference(&work->old_fb_obj->base);
7535 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7536
7537 crtc->fb = fb;
96b099fd 7538
e1f99ce6 7539 work->pending_flip_obj = obj;
e1f99ce6 7540
4e5359cd
SF		 7541 work->enable_stall_check = true;
7542
e1f99ce6
CW		 7543 /* Block clients from rendering to the new back buffer until
7544 * the flip occurs and the object is no longer visible.
7545 */
05394f39 7546 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7547
8c9f3aaf
JB		 7548 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7549 if (ret)
7550 goto cleanup_pending;
6b95a207 7551
7782de3b 7552 intel_disable_fbc(dev);
6b95a207
KH		 7553 mutex_unlock(&dev->struct_mutex);
7554
e5510fac
JB		 7555 trace_i915_flip_request(intel_crtc->plane, obj);
7556
6b95a207 7557 return 0;
96b099fd 7558
8c9f3aaf
JB		 7559cleanup_pending:
7560 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7561 drm_gem_object_unreference(&work->old_fb_obj->base);
7562 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7563 mutex_unlock(&dev->struct_mutex);
7564
7565 spin_lock_irqsave(&dev->event_lock, flags);
7566 intel_crtc->unpin_work = NULL;
7567 spin_unlock_irqrestore(&dev->event_lock, flags);
7568
7317c75e
JB		 7569 drm_vblank_put(dev, intel_crtc->pipe);
7570free_work:
96b099fd
CW		 7571 kfree(work);
7572
7573 return ret;
6b95a207
KH		 7574}
7575
47f1c6c9
CW		 7576static void intel_sanitize_modesetting(struct drm_device *dev,
7577 int pipe, int plane)
7578{
7579 struct drm_i915_private *dev_priv = dev->dev_private;
7580 u32 reg, val;
7581
7582 if (HAS_PCH_SPLIT(dev))
7583 return;
7584
7585 /* Who knows what state these registers were left in by the BIOS or
7586 * grub?
7587 *
7588 * If we leave the registers in a conflicting state (e.g. with the
7589 * display plane reading from the other pipe than the one we intend
7590 * to use) then when we attempt to teardown the active mode, we will
7591 * not disable the pipes and planes in the correct order -- leaving
7592 * a plane reading from a disabled pipe and possibly leading to
7593 * undefined behaviour.
7594 */
7595
7596 reg = DSPCNTR(plane);
7597 val = I915_READ(reg);
7598
7599 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7600 return;
7601 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7602 return;
7603
7604 /* This display plane is active and attached to the other CPU pipe. */
7605 pipe = !pipe;
7606
7607 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7608 intel_disable_plane(dev_priv, plane, pipe);
7609 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7610}
79e53945 7611
f6e5b160
CW		 7612static void intel_crtc_reset(struct drm_crtc *crtc)
7613{
7614 struct drm_device *dev = crtc->dev;
7615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7616
7617 /* Reset flags back to the 'unknown' status so that they
7618 * will be correctly set on the initial modeset.
7619 */
7620 intel_crtc->dpms_mode = -1;
7621
7622 /* We need to fix up any BIOS configuration that conflicts with
7623 * our expectations.
7624 */
7625 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7626}
7627
7628static struct drm_crtc_helper_funcs intel_helper_funcs = {
7629 .dpms = intel_crtc_dpms,
7630 .mode_fixup = intel_crtc_mode_fixup,
7631 .mode_set = intel_crtc_mode_set,
7632 .mode_set_base = intel_pipe_set_base,
7633 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7634 .load_lut = intel_crtc_load_lut,
7635 .disable = intel_crtc_disable,
7636};
7637
7638static const struct drm_crtc_funcs intel_crtc_funcs = {
7639 .reset = intel_crtc_reset,
7640 .cursor_set = intel_crtc_cursor_set,
7641 .cursor_move = intel_crtc_cursor_move,
7642 .gamma_set = intel_crtc_gamma_set,
7643 .set_config = drm_crtc_helper_set_config,
7644 .destroy = intel_crtc_destroy,
7645 .page_flip = intel_crtc_page_flip,
7646};
7647
b358d0a6 7648static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7649{
22fd0fab 7650 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7651 struct intel_crtc *intel_crtc;
7652 int i;
7653
7654 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7655 if (intel_crtc == NULL)
7656 return;
7657
7658 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7659
7660 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7661 for (i = 0; i < 256; i++) {
7662 intel_crtc->lut_r[i] = i;
7663 intel_crtc->lut_g[i] = i;
7664 intel_crtc->lut_b[i] = i;
7665 }
7666
80824003
JB		 7667 /* Swap pipes & planes for FBC on pre-965 */
7668 intel_crtc->pipe = pipe;
7669 intel_crtc->plane = pipe;
e2e767ab 7670 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7671 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7672 intel_crtc->plane = !pipe;
80824003
JB		 7673 }
7674
22fd0fab
JB		 7675 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7676 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7677 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7678 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7679
5d1d0cc8 7680 intel_crtc_reset(&intel_crtc->base);
04dbff52 7681 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7682 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7683
7684 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 7685 if (pipe == 2 && IS_IVYBRIDGE(dev))
7686 intel_crtc->no_pll = true;
7e7d76c3
JB		 7687 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7688 intel_helper_funcs.commit = ironlake_crtc_commit;
7689 } else {
7690 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7691 intel_helper_funcs.commit = i9xx_crtc_commit;
7692 }
7693
79e53945
JB		 7694 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7695
652c393a
JB		 7696 intel_crtc->busy = false;
7697
7698 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7699 (unsigned long)intel_crtc);
79e53945
JB		 7700}
7701
08d7b3d1 7702int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7703 struct drm_file *file)
08d7b3d1
CW		 7704{
7705 drm_i915_private_t *dev_priv = dev->dev_private;
7706 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7707 struct drm_mode_object *drmmode_obj;
7708 struct intel_crtc *crtc;
08d7b3d1
CW		 7709
7710 if (!dev_priv) {
7711 DRM_ERROR("called with no initialization\n");
7712 return -EINVAL;
7713 }
7714
c05422d5
DV		 7715 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7716 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7717
c05422d5 7718 if (!drmmode_obj) {
08d7b3d1
CW		 7719 DRM_ERROR("no such CRTC id\n");
7720 return -EINVAL;
7721 }
7722
c05422d5
DV		 7723 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7724 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7725
c05422d5 7726 return 0;
08d7b3d1
CW		 7727}
7728
c5e4df33 7729static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7730{
4ef69c7a 7731 struct intel_encoder *encoder;
79e53945 7732 int index_mask = 0;
79e53945
JB		 7733 int entry = 0;
7734
4ef69c7a
CW		 7735 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7736 if (type_mask & encoder->clone_mask)
79e53945
JB		 7737 index_mask |= (1 << entry);
7738 entry++;
7739 }
4ef69c7a 7740
79e53945
JB		 7741 return index_mask;
7742}
7743
4d302442
CW		 7744static bool has_edp_a(struct drm_device *dev)
7745{
7746 struct drm_i915_private *dev_priv = dev->dev_private;
7747
7748 if (!IS_MOBILE(dev))
7749 return false;
7750
7751 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7752 return false;
7753
7754 if (IS_GEN5(dev) &&
7755 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7756 return false;
7757
7758 return true;
7759}
7760
79e53945
JB		 7761static void intel_setup_outputs(struct drm_device *dev)
7762{
725e30ad 7763 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7764 struct intel_encoder *encoder;
cb0953d7 7765 bool dpd_is_edp = false;
f3cfcba6 7766 bool has_lvds;
79e53945 7767
f3cfcba6 7768 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7769 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7770 /* disable the panel fitter on everything but LVDS */
7771 I915_WRITE(PFIT_CONTROL, 0);
7772 }
79e53945 7773
bad720ff 7774 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7775 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7776
4d302442 7777 if (has_edp_a(dev))
32f9d658
ZW		 7778 intel_dp_init(dev, DP_A);
7779
cb0953d7
AJ		 7780 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7781 intel_dp_init(dev, PCH_DP_D);
7782 }
7783
7784 intel_crt_init(dev);
7785
7786 if (HAS_PCH_SPLIT(dev)) {
7787 int found;
7788
30ad48b7 7789 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7790 /* PCH SDVOB multiplex with HDMIB */
7791 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7792 if (!found)
7793 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7794 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7795 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7796 }
7797
7798 if (I915_READ(HDMIC) & PORT_DETECTED)
7799 intel_hdmi_init(dev, HDMIC);
7800
7801 if (I915_READ(HDMID) & PORT_DETECTED)
7802 intel_hdmi_init(dev, HDMID);
7803
5eb08b69
ZW		 7804 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7805 intel_dp_init(dev, PCH_DP_C);
7806
cb0953d7 7807 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7808 intel_dp_init(dev, PCH_DP_D);
7809
103a196f 7810 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7811 bool found = false;
7d57382e 7812
725e30ad 7813 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7814 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7815 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7816 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7817 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7818 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7819 }
27185ae1 7820
b01f2c3a
JB		 7821 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7822 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7823 intel_dp_init(dev, DP_B);
b01f2c3a 7824 }
725e30ad 7825 }
13520b05
KH		 7826
7827 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7828
b01f2c3a
JB		 7829 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7830 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7831 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7832 }
27185ae1
ML		 7833
7834 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7835
b01f2c3a
JB		 7836 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7837 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7838 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7839 }
7840 if (SUPPORTS_INTEGRATED_DP(dev)) {
7841 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7842 intel_dp_init(dev, DP_C);
b01f2c3a 7843 }
725e30ad 7844 }
27185ae1 7845
b01f2c3a
JB		 7846 if (SUPPORTS_INTEGRATED_DP(dev) &&
7847 (I915_READ(DP_D) & DP_DETECTED)) {
7848 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7849 intel_dp_init(dev, DP_D);
b01f2c3a 7850 }
bad720ff 7851 } else if (IS_GEN2(dev))
79e53945
JB		 7852 intel_dvo_init(dev);
7853
103a196f 7854 if (SUPPORTS_TV(dev))
79e53945
JB		 7855 intel_tv_init(dev);
7856
4ef69c7a
CW		 7857 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7858 encoder->base.possible_crtcs = encoder->crtc_mask;
7859 encoder->base.possible_clones =
7860 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7861 }
47356eb6 7862
2c7111db
CW		 7863 /* disable all the possible outputs/crtcs before entering KMS mode */
7864 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7865
7866 if (HAS_PCH_SPLIT(dev))
7867 ironlake_init_pch_refclk(dev);
79e53945
JB		 7868}
7869
7870static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7871{
7872 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7873
7874 drm_framebuffer_cleanup(fb);
05394f39 7875 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7876
7877 kfree(intel_fb);
7878}
7879
7880static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7881 struct drm_file *file,
79e53945
JB		 7882 unsigned int *handle)
7883{
7884 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7885 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7886
05394f39 7887 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7888}
7889
7890static const struct drm_framebuffer_funcs intel_fb_funcs = {
7891 .destroy = intel_user_framebuffer_destroy,
7892 .create_handle = intel_user_framebuffer_create_handle,
7893};
7894
38651674
DA		 7895int intel_framebuffer_init(struct drm_device *dev,
7896 struct intel_framebuffer *intel_fb,
308e5bcb 7897 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7898 struct drm_i915_gem_object *obj)
79e53945 7899{
79e53945
JB		 7900 int ret;
7901
05394f39 7902 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7903 return -EINVAL;
7904
308e5bcb 7905 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7906 return -EINVAL;
7907
308e5bcb 7908 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7909 case DRM_FORMAT_RGB332:
7910 case DRM_FORMAT_RGB565:
7911 case DRM_FORMAT_XRGB8888:
7912 case DRM_FORMAT_ARGB8888:
7913 case DRM_FORMAT_XRGB2101010:
7914 case DRM_FORMAT_ARGB2101010:
308e5bcb 7915 /* RGB formats are common across chipsets */
b5626747 7916 break;
04b3924d
VS		 7917 case DRM_FORMAT_YUYV:
7918 case DRM_FORMAT_UYVY:
7919 case DRM_FORMAT_YVYU:
7920 case DRM_FORMAT_VYUY:
57cd6508
CW		 7921 break;
7922 default:
aca25848
ED		 7923 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7924 mode_cmd->pixel_format);
57cd6508
CW		 7925 return -EINVAL;
7926 }
7927
79e53945
JB		 7928 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7929 if (ret) {
7930 DRM_ERROR("framebuffer init failed %d\n", ret);
7931 return ret;
7932 }
7933
7934 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7935 intel_fb->obj = obj;
79e53945
JB		 7936 return 0;
7937}
7938
79e53945
JB		 7939static struct drm_framebuffer *
7940intel_user_framebuffer_create(struct drm_device *dev,
7941 struct drm_file *filp,
308e5bcb 7942 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7943{
05394f39 7944 struct drm_i915_gem_object *obj;
79e53945 7945
308e5bcb
JB		 7946 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7947 mode_cmd->handles[0]));
c8725226 7948 if (&obj->base == NULL)
cce13ff7 7949 return ERR_PTR(-ENOENT);
79e53945 7950
d2dff872 7951 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7952}
7953
79e53945 7954static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7955 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7956 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7957};
7958
05394f39 7959static struct drm_i915_gem_object *
aa40d6bb 7960intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7961{
05394f39 7962 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7963 int ret;
7964
2c34b850
BW		 7965 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7966
aa40d6bb
ZN		 7967 ctx = i915_gem_alloc_object(dev, 4096);
7968 if (!ctx) {
9ea8d059
CW		 7969 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7970 return NULL;
7971 }
7972
75e9e915 7973 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7974 if (ret) {
7975 DRM_ERROR("failed to pin power context: %d\n", ret);
7976 goto err_unref;
7977 }
7978
aa40d6bb 7979 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7980 if (ret) {
7981 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7982 goto err_unpin;
7983 }
9ea8d059 7984
aa40d6bb 7985 return ctx;
9ea8d059
CW		 7986
7987err_unpin:
aa40d6bb 7988 i915_gem_object_unpin(ctx);
9ea8d059 7989err_unref:
05394f39 7990 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7991 mutex_unlock(&dev->struct_mutex);
7992 return NULL;
7993}
7994
7648fa99
JB		 7995bool ironlake_set_drps(struct drm_device *dev, u8 val)
7996{
7997 struct drm_i915_private *dev_priv = dev->dev_private;
7998 u16 rgvswctl;
7999
8000 rgvswctl = I915_READ16(MEMSWCTL);
8001 if (rgvswctl & MEMCTL_CMD_STS) {
8002 DRM_DEBUG("gpu busy, RCS change rejected\n");
8003 return false; /* still busy with another command */
8004 }
8005
8006 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
8007 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
8008 I915_WRITE16(MEMSWCTL, rgvswctl);
8009 POSTING_READ16(MEMSWCTL);
8010
8011 rgvswctl |= MEMCTL_CMD_STS;
8012 I915_WRITE16(MEMSWCTL, rgvswctl);
8013
8014 return true;
8015}
8016
f97108d1
JB		 8017void ironlake_enable_drps(struct drm_device *dev)
8018{
8019 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8020 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 8021 u8 fmax, fmin, fstart, vstart;
f97108d1 8022
ea056c14
JB		 8023 /* Enable temp reporting */
8024 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8025 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8026
f97108d1
JB		 8027 /* 100ms RC evaluation intervals */
8028 I915_WRITE(RCUPEI, 100000);
8029 I915_WRITE(RCDNEI, 100000);
8030
8031 /* Set max/min thresholds to 90ms and 80ms respectively */
8032 I915_WRITE(RCBMAXAVG, 90000);
8033 I915_WRITE(RCBMINAVG, 80000);
8034
8035 I915_WRITE(MEMIHYST, 1);
8036
8037 /* Set up min, max, and cur for interrupt handling */
8038 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8039 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8040 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8041 MEMMODE_FSTART_SHIFT;
7648fa99 8042
f97108d1
JB		 8043 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8044 PXVFREQ_PX_SHIFT;
8045
80dbf4b7 8046 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 8047 dev_priv->fstart = fstart;
8048
80dbf4b7 8049 dev_priv->max_delay = fstart;
f97108d1
JB		 8050 dev_priv->min_delay = fmin;
8051 dev_priv->cur_delay = fstart;
8052
80dbf4b7
JB		 8053 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8054 fmax, fmin, fstart);
7648fa99 8055
f97108d1
JB		 8056 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8057
8058 /*
8059 * Interrupts will be enabled in ironlake_irq_postinstall
8060 */
8061
8062 I915_WRITE(VIDSTART, vstart);
8063 POSTING_READ(VIDSTART);
8064
8065 rgvmodectl |= MEMMODE_SWMODE_EN;
8066 I915_WRITE(MEMMODECTL, rgvmodectl);
8067
481b6af3 8068 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 8069 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 8070 msleep(1);
8071
7648fa99 8072 ironlake_set_drps(dev, fstart);
f97108d1 8073
7648fa99
JB		 8074 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8075 I915_READ(0x112e0);
8076 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8077 dev_priv->last_count2 = I915_READ(0x112f4);
8078 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 8079}
8080
8081void ironlake_disable_drps(struct drm_device *dev)
8082{
8083 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8084 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 8085
8086 /* Ack interrupts, disable EFC interrupt */
8087 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8088 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8089 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8090 I915_WRITE(DEIIR, DE_PCU_EVENT);
8091 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8092
8093 /* Go back to the starting frequency */
7648fa99 8094 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 8095 msleep(1);
8096 rgvswctl |= MEMCTL_CMD_STS;
8097 I915_WRITE(MEMSWCTL, rgvswctl);
8098 msleep(1);
8099
8100}
8101
3b8d8d91
JB		 8102void gen6_set_rps(struct drm_device *dev, u8 val)
8103{
8104 struct drm_i915_private *dev_priv = dev->dev_private;
8105 u32 swreq;
8106
8107 swreq = (val & 0x3ff) << 25;
8108 I915_WRITE(GEN6_RPNSWREQ, swreq);
8109}
8110
8111void gen6_disable_rps(struct drm_device *dev)
8112{
8113 struct drm_i915_private *dev_priv = dev->dev_private;
8114
8115 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8116 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8117 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 8118 /* Complete PM interrupt masking here doesn't race with the rps work
8119 * item again unmasking PM interrupts because that is using a different
8120 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8121 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 8122
8123 spin_lock_irq(&dev_priv->rps_lock);
8124 dev_priv->pm_iir = 0;
8125 spin_unlock_irq(&dev_priv->rps_lock);
8126
3b8d8d91
JB		 8127 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8128}
8129
7648fa99
JB		 8130static unsigned long intel_pxfreq(u32 vidfreq)
8131{
8132 unsigned long freq;
8133 int div = (vidfreq & 0x3f0000) >> 16;
8134 int post = (vidfreq & 0x3000) >> 12;
8135 int pre = (vidfreq & 0x7);
8136
8137 if (!pre)
8138 return 0;
8139
8140 freq = ((div * 133333) / ((1<<post) * pre));
8141
8142 return freq;
8143}
8144
8145void intel_init_emon(struct drm_device *dev)
8146{
8147 struct drm_i915_private *dev_priv = dev->dev_private;
8148 u32 lcfuse;
8149 u8 pxw[16];
8150 int i;
8151
8152 /* Disable to program */
8153 I915_WRITE(ECR, 0);
8154 POSTING_READ(ECR);
8155
8156 /* Program energy weights for various events */
8157 I915_WRITE(SDEW, 0x15040d00);
8158 I915_WRITE(CSIEW0, 0x007f0000);
8159 I915_WRITE(CSIEW1, 0x1e220004);
8160 I915_WRITE(CSIEW2, 0x04000004);
8161
8162 for (i = 0; i < 5; i++)
8163 I915_WRITE(PEW + (i * 4), 0);
8164 for (i = 0; i < 3; i++)
8165 I915_WRITE(DEW + (i * 4), 0);
8166
8167 /* Program P-state weights to account for frequency power adjustment */
8168 for (i = 0; i < 16; i++) {
8169 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8170 unsigned long freq = intel_pxfreq(pxvidfreq);
8171 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8172 PXVFREQ_PX_SHIFT;
8173 unsigned long val;
8174
8175 val = vid * vid;
8176 val *= (freq / 1000);
8177 val *= 255;
8178 val /= (127*127*900);
8179 if (val > 0xff)
8180 DRM_ERROR("bad pxval: %ld\n", val);
8181 pxw[i] = val;
8182 }
8183 /* Render standby states get 0 weight */
8184 pxw[14] = 0;
8185 pxw[15] = 0;
8186
8187 for (i = 0; i < 4; i++) {
8188 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8189 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8190 I915_WRITE(PXW + (i * 4), val);
8191 }
8192
8193 /* Adjust magic regs to magic values (more experimental results) */
8194 I915_WRITE(OGW0, 0);
8195 I915_WRITE(OGW1, 0);
8196 I915_WRITE(EG0, 0x00007f00);
8197 I915_WRITE(EG1, 0x0000000e);
8198 I915_WRITE(EG2, 0x000e0000);
8199 I915_WRITE(EG3, 0x68000300);
8200 I915_WRITE(EG4, 0x42000000);
8201 I915_WRITE(EG5, 0x00140031);
8202 I915_WRITE(EG6, 0);
8203 I915_WRITE(EG7, 0);
8204
8205 for (i = 0; i < 8; i++)
8206 I915_WRITE(PXWL + (i * 4), 0);
8207
8208 /* Enable PMON + select events */
8209 I915_WRITE(ECR, 0x80000019);
8210
8211 lcfuse = I915_READ(LCFUSE02);
8212
8213 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8214}
8215
c0f372b3
KP		 8216static bool intel_enable_rc6(struct drm_device *dev)
8217{
8218 /*
8219 * Respect the kernel parameter if it is set
8220 */
8221 if (i915_enable_rc6 >= 0)
8222 return i915_enable_rc6;
8223
8224 /*
8225 * Disable RC6 on Ironlake
8226 */
8227 if (INTEL_INFO(dev)->gen == 5)
8228 return 0;
8229
8230 /*
371de6e4 8231 * Disable rc6 on Sandybridge
c0f372b3
KP		 8232 */
8233 if (INTEL_INFO(dev)->gen == 6) {
371de6e4
KP		 8234 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8235 return 0;
c0f372b3
KP		 8236 }
8237 DRM_DEBUG_DRIVER("RC6 enabled\n");
8238 return 1;
8239}
8240
3b8d8d91 8241void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 8242{
a6044e23
JB		 8243 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8244 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 8245 u32 pcu_mbox, rc6_mask = 0;
dd202c6d 8246 u32 gtfifodbg;
a6044e23 8247 int cur_freq, min_freq, max_freq;
8fd26859
CW		 8248 int i;
8249
8250 /* Here begins a magic sequence of register writes to enable
8251 * auto-downclocking.
8252 *
8253 * Perhaps there might be some value in exposing these to
8254 * userspace...
8255 */
8256 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 8257 mutex_lock(&dev_priv->dev->struct_mutex);
dd202c6d
BW		 8258
8259 /* Clear the DBG now so we don't confuse earlier errors */
8260 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
8261 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
8262 I915_WRITE(GTFIFODBG, gtfifodbg);
8263 }
8264
fcca7926 8265 gen6_gt_force_wake_get(dev_priv);
8fd26859 8266
3b8d8d91 8267 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 8268 I915_WRITE(GEN6_RC_CONTROL, 0);
8269
8270 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8271 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8272 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8273 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8274 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8275
8276 for (i = 0; i < I915_NUM_RINGS; i++)
8277 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8278
8279 I915_WRITE(GEN6_RC_SLEEP, 0);
8280 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8281 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8282 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8283 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8284
c0f372b3 8285 if (intel_enable_rc6(dev_priv->dev))
7df8721b
JB		 8286 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8287 GEN6_RC_CTL_RC6_ENABLE;
8288
8fd26859 8289 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 8290 rc6_mask |
9c3d2f7f 8291 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 8292 GEN6_RC_CTL_HW_ENABLE);
8293
3b8d8d91 8294 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 8295 GEN6_FREQUENCY(10) |
8296 GEN6_OFFSET(0) |
8297 GEN6_AGGRESSIVE_TURBO);
8298 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8299 GEN6_FREQUENCY(12));
8300
8301 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8302 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8303 18 << 24 |
8304 6 << 16);
ccab5c82
JB		 8305 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8306 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 8307 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 8308 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 8309 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8310 I915_WRITE(GEN6_RP_CONTROL,
8311 GEN6_RP_MEDIA_TURBO |
6ed55ee7 8312 GEN6_RP_MEDIA_HW_MODE |
8fd26859
CW		 8313 GEN6_RP_MEDIA_IS_GFX |
8314 GEN6_RP_ENABLE |
ccab5c82
JB		 8315 GEN6_RP_UP_BUSY_AVG |
8316 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 8317
8318 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8319 500))
8320 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8321
8322 I915_WRITE(GEN6_PCODE_DATA, 0);
8323 I915_WRITE(GEN6_PCODE_MAILBOX,
8324 GEN6_PCODE_READY |
8325 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8326 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8327 500))
8328 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8329
a6044e23
JB		 8330 min_freq = (rp_state_cap & 0xff0000) >> 16;
8331 max_freq = rp_state_cap & 0xff;
8332 cur_freq = (gt_perf_status & 0xff00) >> 8;
8333
8334 /* Check for overclock support */
8335 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8336 500))
8337 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8338 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8339 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8340 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8341 500))
8342 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8343 if (pcu_mbox & (1<<31)) { /* OC supported */
8344 max_freq = pcu_mbox & 0xff;
e281fcaa 8345 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 8346 }
8347
8348 /* In units of 100MHz */
8349 dev_priv->max_delay = max_freq;
8350 dev_priv->min_delay = min_freq;
8351 dev_priv->cur_delay = cur_freq;
8352
8fd26859
CW		 8353 /* requires MSI enabled */
8354 I915_WRITE(GEN6_PMIER,
8355 GEN6_PM_MBOX_EVENT |
8356 GEN6_PM_THERMAL_EVENT |
8357 GEN6_PM_RP_DOWN_TIMEOUT |
8358 GEN6_PM_RP_UP_THRESHOLD |
8359 GEN6_PM_RP_DOWN_THRESHOLD |
8360 GEN6_PM_RP_UP_EI_EXPIRED |
8361 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 8362 spin_lock_irq(&dev_priv->rps_lock);
8363 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 8364 I915_WRITE(GEN6_PMIMR, 0);
4912d041 8365 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 8366 /* enable all PM interrupts */
8367 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 8368
fcca7926 8369 gen6_gt_force_wake_put(dev_priv);
d1ebd816 8370 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 8371}
8372
23b2f8bb
JB		 8373void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8374{
8375 int min_freq = 15;
8376 int gpu_freq, ia_freq, max_ia_freq;
8377 int scaling_factor = 180;
8378
8379 max_ia_freq = cpufreq_quick_get_max(0);
8380 /*
8381 * Default to measured freq if none found, PCU will ensure we don't go
8382 * over
8383 */
8384 if (!max_ia_freq)
8385 max_ia_freq = tsc_khz;
8386
8387 /* Convert from kHz to MHz */
8388 max_ia_freq /= 1000;
8389
8390 mutex_lock(&dev_priv->dev->struct_mutex);
8391
8392 /*
8393 * For each potential GPU frequency, load a ring frequency we'd like
8394 * to use for memory access. We do this by specifying the IA frequency
8395 * the PCU should use as a reference to determine the ring frequency.
8396 */
8397 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8398 gpu_freq--) {
8399 int diff = dev_priv->max_delay - gpu_freq;
8400
8401 /*
8402 * For GPU frequencies less than 750MHz, just use the lowest
8403 * ring freq.
8404 */
8405 if (gpu_freq < min_freq)
8406 ia_freq = 800;
8407 else
8408 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8409 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8410
8411 I915_WRITE(GEN6_PCODE_DATA,
8412 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8413 gpu_freq);
8414 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8415 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8416 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8417 GEN6_PCODE_READY) == 0, 10)) {
8418 DRM_ERROR("pcode write of freq table timed out\n");
8419 continue;
8420 }
8421 }
8422
8423 mutex_unlock(&dev_priv->dev->struct_mutex);
8424}
8425
6067aaea
JB		 8426static void ironlake_init_clock_gating(struct drm_device *dev)
8427{
8428 struct drm_i915_private *dev_priv = dev->dev_private;
8429 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8430
8431 /* Required for FBC */
8432 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8433 DPFCRUNIT_CLOCK_GATE_DISABLE |
8434 DPFDUNIT_CLOCK_GATE_DISABLE;
8435 /* Required for CxSR */
8436 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8437
8438 I915_WRITE(PCH_3DCGDIS0,
8439 MARIUNIT_CLOCK_GATE_DISABLE |
8440 SVSMUNIT_CLOCK_GATE_DISABLE);
8441 I915_WRITE(PCH_3DCGDIS1,
8442 VFMUNIT_CLOCK_GATE_DISABLE);
8443
8444 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8445
6067aaea
JB		 8446 /*
8447 * According to the spec the following bits should be set in
8448 * order to enable memory self-refresh
8449 * The bit 22/21 of 0x42004
8450 * The bit 5 of 0x42020
8451 * The bit 15 of 0x45000
8452 */
8453 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8454 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8455 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8456 I915_WRITE(ILK_DSPCLK_GATE,
8457 (I915_READ(ILK_DSPCLK_GATE) |
8458 ILK_DPARB_CLK_GATE));
8459 I915_WRITE(DISP_ARB_CTL,
8460 (I915_READ(DISP_ARB_CTL) |
8461 DISP_FBC_WM_DIS));
8462 I915_WRITE(WM3_LP_ILK, 0);
8463 I915_WRITE(WM2_LP_ILK, 0);
8464 I915_WRITE(WM1_LP_ILK, 0);
8465
8466 /*
8467 * Based on the document from hardware guys the following bits
8468 * should be set unconditionally in order to enable FBC.
8469 * The bit 22 of 0x42000
8470 * The bit 22 of 0x42004
8471 * The bit 7,8,9 of 0x42020.
8472 */
8473 if (IS_IRONLAKE_M(dev)) {
8474 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8475 I915_READ(ILK_DISPLAY_CHICKEN1) |
8476 ILK_FBCQ_DIS);
8477 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8478 I915_READ(ILK_DISPLAY_CHICKEN2) |
8479 ILK_DPARB_GATE);
8480 I915_WRITE(ILK_DSPCLK_GATE,
8481 I915_READ(ILK_DSPCLK_GATE) |
8482 ILK_DPFC_DIS1 |
8483 ILK_DPFC_DIS2 |
8484 ILK_CLK_FBC);
8485 }
8486
8487 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8488 I915_READ(ILK_DISPLAY_CHICKEN2) |
8489 ILK_ELPIN_409_SELECT);
8490 I915_WRITE(_3D_CHICKEN2,
8491 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8492 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8493}
8494
6067aaea 8495static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8496{
8497 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8498 int pipe;
6067aaea
JB		 8499 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8500
8501 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8502
6067aaea
JB		 8503 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8504 I915_READ(ILK_DISPLAY_CHICKEN2) |
8505 ILK_ELPIN_409_SELECT);
8956c8bb 8506
6067aaea
JB		 8507 I915_WRITE(WM3_LP_ILK, 0);
8508 I915_WRITE(WM2_LP_ILK, 0);
8509 I915_WRITE(WM1_LP_ILK, 0);
652c393a 8510
406478dc
EA		 8511 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8512 * gating disable must be set. Failure to set it results in
8513 * flickering pixels due to Z write ordering failures after
8514 * some amount of runtime in the Mesa "fire" demo, and Unigine
8515 * Sanctuary and Tropics, and apparently anything else with
8516 * alpha test or pixel discard.
9ca1d10d
EA		 8517 *
8518 * According to the spec, bit 11 (RCCUNIT) must also be set,
8519 * but we didn't debug actual testcases to find it out.
406478dc 8520 */
9ca1d10d
EA		 8521 I915_WRITE(GEN6_UCGCTL2,
8522 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8523 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
406478dc 8524
652c393a 8525 /*
6067aaea
JB		 8526 * According to the spec the following bits should be
8527 * set in order to enable memory self-refresh and fbc:
8528 * The bit21 and bit22 of 0x42000
8529 * The bit21 and bit22 of 0x42004
8530 * The bit5 and bit7 of 0x42020
8531 * The bit14 of 0x70180
8532 * The bit14 of 0x71180
652c393a 8533 */
6067aaea
JB		 8534 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8535 I915_READ(ILK_DISPLAY_CHICKEN1) |
8536 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8537 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8538 I915_READ(ILK_DISPLAY_CHICKEN2) |
8539 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8540 I915_WRITE(ILK_DSPCLK_GATE,
8541 I915_READ(ILK_DSPCLK_GATE) |
8542 ILK_DPARB_CLK_GATE |
8543 ILK_DPFD_CLK_GATE);
8956c8bb 8544
d74362c9 8545 for_each_pipe(pipe) {
6067aaea
JB		 8546 I915_WRITE(DSPCNTR(pipe),
8547 I915_READ(DSPCNTR(pipe)) |
8548 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8549 intel_flush_display_plane(dev_priv, pipe);
8550 }
6067aaea 8551}
8956c8bb 8552
28963a3e
JB		 8553static void ivybridge_init_clock_gating(struct drm_device *dev)
8554{
8555 struct drm_i915_private *dev_priv = dev->dev_private;
8556 int pipe;
8557 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8558
28963a3e 8559 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8560
28963a3e
JB		 8561 I915_WRITE(WM3_LP_ILK, 0);
8562 I915_WRITE(WM2_LP_ILK, 0);
8563 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8564
28963a3e 8565 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8566
116ac8d2
EA		 8567 I915_WRITE(IVB_CHICKEN3,
8568 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8569 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8570
d74362c9 8571 for_each_pipe(pipe) {
28963a3e
JB		 8572 I915_WRITE(DSPCNTR(pipe),
8573 I915_READ(DSPCNTR(pipe)) |
8574 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8575 intel_flush_display_plane(dev_priv, pipe);
8576 }
28963a3e
JB		 8577}
8578
6067aaea
JB		 8579static void g4x_init_clock_gating(struct drm_device *dev)
8580{
8581 struct drm_i915_private *dev_priv = dev->dev_private;
8582 uint32_t dspclk_gate;
8fd26859 8583
6067aaea
JB		 8584 I915_WRITE(RENCLK_GATE_D1, 0);
8585 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8586 GS_UNIT_CLOCK_GATE_DISABLE |
8587 CL_UNIT_CLOCK_GATE_DISABLE);
8588 I915_WRITE(RAMCLK_GATE_D, 0);
8589 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8590 OVRUNIT_CLOCK_GATE_DISABLE |
8591 OVCUNIT_CLOCK_GATE_DISABLE;
8592 if (IS_GM45(dev))
8593 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8594 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8595}
1398261a 8596
6067aaea
JB		 8597static void crestline_init_clock_gating(struct drm_device *dev)
8598{
8599 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8600
6067aaea
JB		 8601 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8602 I915_WRITE(RENCLK_GATE_D2, 0);
8603 I915_WRITE(DSPCLK_GATE_D, 0);
8604 I915_WRITE(RAMCLK_GATE_D, 0);
8605 I915_WRITE16(DEUC, 0);
8606}
652c393a 8607
6067aaea
JB		 8608static void broadwater_init_clock_gating(struct drm_device *dev)
8609{
8610 struct drm_i915_private *dev_priv = dev->dev_private;
8611
8612 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8613 I965_RCC_CLOCK_GATE_DISABLE |
8614 I965_RCPB_CLOCK_GATE_DISABLE |
8615 I965_ISC_CLOCK_GATE_DISABLE |
8616 I965_FBC_CLOCK_GATE_DISABLE);
8617 I915_WRITE(RENCLK_GATE_D2, 0);
8618}
8619
8620static void gen3_init_clock_gating(struct drm_device *dev)
8621{
8622 struct drm_i915_private *dev_priv = dev->dev_private;
8623 u32 dstate = I915_READ(D_STATE);
8624
8625 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8626 DSTATE_DOT_CLOCK_GATING;
8627 I915_WRITE(D_STATE, dstate);
8628}
8629
8630static void i85x_init_clock_gating(struct drm_device *dev)
8631{
8632 struct drm_i915_private *dev_priv = dev->dev_private;
8633
8634 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8635}
8636
8637static void i830_init_clock_gating(struct drm_device *dev)
8638{
8639 struct drm_i915_private *dev_priv = dev->dev_private;
8640
8641 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8642}
8643
645c62a5
JB		 8644static void ibx_init_clock_gating(struct drm_device *dev)
8645{
8646 struct drm_i915_private *dev_priv = dev->dev_private;
8647
8648 /*
8649 * On Ibex Peak and Cougar Point, we need to disable clock
8650 * gating for the panel power sequencer or it will fail to
8651 * start up when no ports are active.
8652 */
8653 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8654}
8655
8656static void cpt_init_clock_gating(struct drm_device *dev)
8657{
8658 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8659 int pipe;
645c62a5
JB		 8660
8661 /*
8662 * On Ibex Peak and Cougar Point, we need to disable clock
8663 * gating for the panel power sequencer or it will fail to
8664 * start up when no ports are active.
8665 */
8666 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8667 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8668 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8669 /* Without this, mode sets may fail silently on FDI */
8670 for_each_pipe(pipe)
8671 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8672}
8673
ac668088 8674static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8675{
8676 struct drm_i915_private *dev_priv = dev->dev_private;
8677
8678 if (dev_priv->renderctx) {
ac668088
CW		 8679 i915_gem_object_unpin(dev_priv->renderctx);
8680 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8681 dev_priv->renderctx = NULL;
8682 }
8683
8684 if (dev_priv->pwrctx) {
ac668088
CW		 8685 i915_gem_object_unpin(dev_priv->pwrctx);
8686 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8687 dev_priv->pwrctx = NULL;
8688 }
8689}
8690
8691static void ironlake_disable_rc6(struct drm_device *dev)
8692{
8693 struct drm_i915_private *dev_priv = dev->dev_private;
8694
8695 if (I915_READ(PWRCTXA)) {
8696 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8697 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8698 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8699 50);
0cdab21f
CW		 8700
8701 I915_WRITE(PWRCTXA, 0);
8702 POSTING_READ(PWRCTXA);
8703
ac668088
CW		 8704 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8705 POSTING_READ(RSTDBYCTL);
0cdab21f 8706 }
ac668088 8707
99507307 8708 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8709}
8710
ac668088 8711static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8712{
8713 struct drm_i915_private *dev_priv = dev->dev_private;
8714
ac668088
CW		 8715 if (dev_priv->renderctx == NULL)
8716 dev_priv->renderctx = intel_alloc_context_page(dev);
8717 if (!dev_priv->renderctx)
8718 return -ENOMEM;
8719
8720 if (dev_priv->pwrctx == NULL)
8721 dev_priv->pwrctx = intel_alloc_context_page(dev);
8722 if (!dev_priv->pwrctx) {
8723 ironlake_teardown_rc6(dev);
8724 return -ENOMEM;
8725 }
8726
8727 return 0;
d5bb081b
JB		 8728}
8729
8730void ironlake_enable_rc6(struct drm_device *dev)
8731{
8732 struct drm_i915_private *dev_priv = dev->dev_private;
8733 int ret;
8734
ac668088
CW		 8735 /* rc6 disabled by default due to repeated reports of hanging during
8736 * boot and resume.
8737 */
c0f372b3 8738 if (!intel_enable_rc6(dev))
ac668088
CW		 8739 return;
8740
2c34b850 8741 mutex_lock(&dev->struct_mutex);
ac668088 8742 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8743 if (ret) {
8744 mutex_unlock(&dev->struct_mutex);
ac668088 8745 return;
2c34b850 8746 }
ac668088 8747
d5bb081b
JB		 8748 /*
8749 * GPU can automatically power down the render unit if given a page
8750 * to save state.
8751 */
8752 ret = BEGIN_LP_RING(6);
8753 if (ret) {
ac668088 8754 ironlake_teardown_rc6(dev);
2c34b850 8755 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8756 return;
8757 }
ac668088 8758
d5bb081b
JB		 8759 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8760 OUT_RING(MI_SET_CONTEXT);
8761 OUT_RING(dev_priv->renderctx->gtt_offset |
8762 MI_MM_SPACE_GTT |
8763 MI_SAVE_EXT_STATE_EN |
8764 MI_RESTORE_EXT_STATE_EN |
8765 MI_RESTORE_INHIBIT);
8766 OUT_RING(MI_SUSPEND_FLUSH);
8767 OUT_RING(MI_NOOP);
8768 OUT_RING(MI_FLUSH);
8769 ADVANCE_LP_RING();
8770
4a246cfc
BW		 8771 /*
8772 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8773 * does an implicit flush, combined with MI_FLUSH above, it should be
8774 * safe to assume that renderctx is valid
8775 */
8776 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8777 if (ret) {
8778 DRM_ERROR("failed to enable ironlake power power savings\n");
8779 ironlake_teardown_rc6(dev);
8780 mutex_unlock(&dev->struct_mutex);
8781 return;
8782 }
8783
d5bb081b
JB		 8784 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8785 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8786 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8787}
8788
645c62a5
JB		 8789void intel_init_clock_gating(struct drm_device *dev)
8790{
8791 struct drm_i915_private *dev_priv = dev->dev_private;
8792
8793 dev_priv->display.init_clock_gating(dev);
8794
8795 if (dev_priv->display.init_pch_clock_gating)
8796 dev_priv->display.init_pch_clock_gating(dev);
8797}
ac668088 8798
e70236a8
JB		 8799/* Set up chip specific display functions */
8800static void intel_init_display(struct drm_device *dev)
8801{
8802 struct drm_i915_private *dev_priv = dev->dev_private;
8803
8804 /* We always want a DPMS function */
f564048e 8805 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8806 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8807 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8808 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8809 } else {
e70236a8 8810 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8811 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8812 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8813 }
e70236a8 8814
ee5382ae 8815 if (I915_HAS_FBC(dev)) {
9c04f015 8816 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8817 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8818 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8819 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8820 } else if (IS_GM45(dev)) {
74dff282
JB		 8821 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8822 dev_priv->display.enable_fbc = g4x_enable_fbc;
8823 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8824 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8825 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8826 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8827 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8828 }
74dff282 8829 /* 855GM needs testing */
e70236a8
JB		 8830 }
8831
8832 /* Returns the core display clock speed */
0206e353 8833 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8834 dev_priv->display.get_display_clock_speed =
8835 i945_get_display_clock_speed;
8836 else if (IS_I915G(dev))
8837 dev_priv->display.get_display_clock_speed =
8838 i915_get_display_clock_speed;
f2b115e6 8839 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8840 dev_priv->display.get_display_clock_speed =
8841 i9xx_misc_get_display_clock_speed;
8842 else if (IS_I915GM(dev))
8843 dev_priv->display.get_display_clock_speed =
8844 i915gm_get_display_clock_speed;
8845 else if (IS_I865G(dev))
8846 dev_priv->display.get_display_clock_speed =
8847 i865_get_display_clock_speed;
f0f8a9ce 8848 else if (IS_I85X(dev))
e70236a8
JB		 8849 dev_priv->display.get_display_clock_speed =
8850 i855_get_display_clock_speed;
8851 else /* 852, 830 */
8852 dev_priv->display.get_display_clock_speed =
8853 i830_get_display_clock_speed;
8854
8855 /* For FIFO watermark updates */
7f8a8569 8856 if (HAS_PCH_SPLIT(dev)) {
8d715f00
KP		 8857 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8858 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8859
8860 /* IVB configs may use multi-threaded forcewake */
8861 if (IS_IVYBRIDGE(dev)) {
8862 u32 ecobus;
8863
c7dffff7
KP		 8864 /* A small trick here - if the bios hasn't configured MT forcewake,
8865 * and if the device is in RC6, then force_wake_mt_get will not wake
8866 * the device and the ECOBUS read will return zero. Which will be
8867 * (correctly) interpreted by the test below as MT forcewake being
8868 * disabled.
8869 */
8d715f00
KP		 8870 mutex_lock(&dev->struct_mutex);
8871 __gen6_gt_force_wake_mt_get(dev_priv);
c7dffff7 8872 ecobus = I915_READ_NOTRACE(ECOBUS);
8d715f00
KP		 8873 __gen6_gt_force_wake_mt_put(dev_priv);
8874 mutex_unlock(&dev->struct_mutex);
8875
8876 if (ecobus & FORCEWAKE_MT_ENABLE) {
8877 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8878 dev_priv->display.force_wake_get =
8879 __gen6_gt_force_wake_mt_get;
8880 dev_priv->display.force_wake_put =
8881 __gen6_gt_force_wake_mt_put;
8882 }
8883 }
8884
645c62a5
JB		 8885 if (HAS_PCH_IBX(dev))
8886 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8887 else if (HAS_PCH_CPT(dev))
8888 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8889
f00a3ddf 8890 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8891 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8892 dev_priv->display.update_wm = ironlake_update_wm;
8893 else {
8894 DRM_DEBUG_KMS("Failed to get proper latency. "
8895 "Disable CxSR\n");
8896 dev_priv->display.update_wm = NULL;
1398261a 8897 }
674cf967 8898 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8899 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8900 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8901 } else if (IS_GEN6(dev)) {
8902 if (SNB_READ_WM0_LATENCY()) {
8903 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8904 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1398261a
YL		 8905 } else {
8906 DRM_DEBUG_KMS("Failed to read display plane latency. "
8907 "Disable CxSR\n");
8908 dev_priv->display.update_wm = NULL;
7f8a8569 8909 }
674cf967 8910 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8911 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8912 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8913 } else if (IS_IVYBRIDGE(dev)) {
8914 /* FIXME: detect B0+ stepping and use auto training */
8915 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8916 if (SNB_READ_WM0_LATENCY()) {
8917 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8918 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
fe100d4d
JB		 8919 } else {
8920 DRM_DEBUG_KMS("Failed to read display plane latency. "
8921 "Disable CxSR\n");
8922 dev_priv->display.update_wm = NULL;
8923 }
28963a3e 8924 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 8925 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 8926 } else
8927 dev_priv->display.update_wm = NULL;
8928 } else if (IS_PINEVIEW(dev)) {
d4294342 8929 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8930 dev_priv->is_ddr3,
d4294342
ZY		 8931 dev_priv->fsb_freq,
8932 dev_priv->mem_freq)) {
8933 DRM_INFO("failed to find known CxSR latency "
95534263 8934 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8935 "disabling CxSR\n",
0206e353 8936 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 8937 dev_priv->fsb_freq, dev_priv->mem_freq);
8938 /* Disable CxSR and never update its watermark again */
8939 pineview_disable_cxsr(dev);
8940 dev_priv->display.update_wm = NULL;
8941 } else
8942 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8943 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8944 } else if (IS_G4X(dev)) {
e0dac65e 8945 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8946 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8947 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8948 } else if (IS_GEN4(dev)) {
e70236a8 8949 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8950 if (IS_CRESTLINE(dev))
8951 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8952 else if (IS_BROADWATER(dev))
8953 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8954 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8955 dev_priv->display.update_wm = i9xx_update_wm;
8956 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8957 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8958 } else if (IS_I865G(dev)) {
8959 dev_priv->display.update_wm = i830_update_wm;
8960 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8961 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8962 } else if (IS_I85X(dev)) {
8963 dev_priv->display.update_wm = i9xx_update_wm;
8964 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8965 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8966 } else {
8f4695ed 8967 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8968 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8969 if (IS_845G(dev))
e70236a8
JB		 8970 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8971 else
8972 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8973 }
8c9f3aaf
JB		 8974
8975 /* Default just returns -ENODEV to indicate unsupported */
8976 dev_priv->display.queue_flip = intel_default_queue_flip;
8977
8978 switch (INTEL_INFO(dev)->gen) {
8979 case 2:
8980 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8981 break;
8982
8983 case 3:
8984 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8985 break;
8986
8987 case 4:
8988 case 5:
8989 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8990 break;
8991
8992 case 6:
8993 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8994 break;
7c9017e5
JB		 8995 case 7:
8996 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8997 break;
8c9f3aaf 8998 }
e70236a8
JB		 8999}
9000
b690e96c
JB		 9001/*
9002 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9003 * resume, or other times. This quirk makes sure that's the case for
9004 * affected systems.
9005 */
0206e353 9006static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9007{
9008 struct drm_i915_private *dev_priv = dev->dev_private;
9009
9010 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9011 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9012}
9013
435793df
KP		 9014/*
9015 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9016 */
9017static void quirk_ssc_force_disable(struct drm_device *dev)
9018{
9019 struct drm_i915_private *dev_priv = dev->dev_private;
9020 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9021}
9022
b690e96c
JB		 9023struct intel_quirk {
9024 int device;
9025 int subsystem_vendor;
9026 int subsystem_device;
9027 void (*hook)(struct drm_device *dev);
9028};
9029
9030struct intel_quirk intel_quirks[] = {
b690e96c 9031 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9032 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 9033
9034 /* Thinkpad R31 needs pipe A force quirk */
9035 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9036 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9037 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9038
9039 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9040 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9041 /* ThinkPad X40 needs pipe A force quirk */
9042
9043 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9044 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9045
9046 /* 855 & before need to leave pipe A & dpll A up */
9047 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9048 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9049
9050 /* Lenovo U160 cannot use SSC on LVDS */
9051 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9052
9053 /* Sony Vaio Y cannot use SSC on LVDS */
9054 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 9055};
9056
9057static void intel_init_quirks(struct drm_device *dev)
9058{
9059 struct pci_dev *d = dev->pdev;
9060 int i;
9061
9062 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9063 struct intel_quirk *q = &intel_quirks[i];
9064
9065 if (d->device == q->device &&
9066 (d->subsystem_vendor == q->subsystem_vendor ||
9067 q->subsystem_vendor == PCI_ANY_ID) &&
9068 (d->subsystem_device == q->subsystem_device ||
9069 q->subsystem_device == PCI_ANY_ID))
9070 q->hook(dev);
9071 }
9072}
9073
9cce37f4
JB		 9074/* Disable the VGA plane that we never use */
9075static void i915_disable_vga(struct drm_device *dev)
9076{
9077 struct drm_i915_private *dev_priv = dev->dev_private;
9078 u8 sr1;
9079 u32 vga_reg;
9080
9081 if (HAS_PCH_SPLIT(dev))
9082 vga_reg = CPU_VGACNTRL;
9083 else
9084 vga_reg = VGACNTRL;
9085
9086 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9087 outb(1, VGA_SR_INDEX);
9088 sr1 = inb(VGA_SR_DATA);
9089 outb(sr1 | 1<<5, VGA_SR_DATA);
9090 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9091 udelay(300);
9092
9093 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9094 POSTING_READ(vga_reg);
9095}
9096
79e53945
JB		 9097void intel_modeset_init(struct drm_device *dev)
9098{
652c393a 9099 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 9100 int i, ret;
79e53945
JB		 9101
9102 drm_mode_config_init(dev);
9103
9104 dev->mode_config.min_width = 0;
9105 dev->mode_config.min_height = 0;
9106
019d96cb
DA		 9107 dev->mode_config.preferred_depth = 24;
9108 dev->mode_config.prefer_shadow = 1;
9109
79e53945
JB		 9110 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9111
b690e96c
JB		 9112 intel_init_quirks(dev);
9113
e70236a8
JB		 9114 intel_init_display(dev);
9115
a6c45cf0
CW		 9116 if (IS_GEN2(dev)) {
9117 dev->mode_config.max_width = 2048;
9118 dev->mode_config.max_height = 2048;
9119 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9120 dev->mode_config.max_width = 4096;
9121 dev->mode_config.max_height = 4096;
79e53945 9122 } else {
a6c45cf0
CW		 9123 dev->mode_config.max_width = 8192;
9124 dev->mode_config.max_height = 8192;
79e53945 9125 }
35c3047a 9126 dev->mode_config.fb_base = dev->agp->base;
79e53945 9127
28c97730 9128 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 9129 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 9130
a3524f1b 9131 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 9132 intel_crtc_init(dev, i);
00c2064b
JB		 9133 ret = intel_plane_init(dev, i);
9134 if (ret)
9135 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 9136 }
9137
9cce37f4
JB		 9138 /* Just disable it once at startup */
9139 i915_disable_vga(dev);
79e53945 9140 intel_setup_outputs(dev);
652c393a 9141
645c62a5 9142 intel_init_clock_gating(dev);
9cce37f4 9143
7648fa99 9144 if (IS_IRONLAKE_M(dev)) {
f97108d1 9145 ironlake_enable_drps(dev);
7648fa99
JB		 9146 intel_init_emon(dev);
9147 }
f97108d1 9148
1c70c0ce 9149 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 9150 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 9151 gen6_update_ring_freq(dev_priv);
9152 }
3b8d8d91 9153
652c393a
JB		 9154 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9155 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9156 (unsigned long)dev);
2c7111db
CW		 9157}
9158
9159void intel_modeset_gem_init(struct drm_device *dev)
9160{
9161 if (IS_IRONLAKE_M(dev))
9162 ironlake_enable_rc6(dev);
02e792fb
DV		 9163
9164 intel_setup_overlay(dev);
79e53945
JB		 9165}
9166
9167void intel_modeset_cleanup(struct drm_device *dev)
9168{
652c393a
JB		 9169 struct drm_i915_private *dev_priv = dev->dev_private;
9170 struct drm_crtc *crtc;
9171 struct intel_crtc *intel_crtc;
9172
f87ea761 9173 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9174 mutex_lock(&dev->struct_mutex);
9175
723bfd70
JB		 9176 intel_unregister_dsm_handler();
9177
9178
652c393a
JB		 9179 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9180 /* Skip inactive CRTCs */
9181 if (!crtc->fb)
9182 continue;
9183
9184 intel_crtc = to_intel_crtc(crtc);
3dec0095 9185 intel_increase_pllclock(crtc);
652c393a
JB		 9186 }
9187
973d04f9 9188 intel_disable_fbc(dev);
e70236a8 9189
f97108d1
JB		 9190 if (IS_IRONLAKE_M(dev))
9191 ironlake_disable_drps(dev);
1c70c0ce 9192 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 9193 gen6_disable_rps(dev);
f97108d1 9194
d5bb081b
JB		 9195 if (IS_IRONLAKE_M(dev))
9196 ironlake_disable_rc6(dev);
0cdab21f 9197
69341a5e
KH		 9198 mutex_unlock(&dev->struct_mutex);
9199
6c0d9350
DV		 9200 /* Disable the irq before mode object teardown, for the irq might
9201 * enqueue unpin/hotplug work. */
9202 drm_irq_uninstall(dev);
9203 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 9204 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 9205
1630fe75
CW		 9206 /* flush any delayed tasks or pending work */
9207 flush_scheduled_work();
9208
3dec0095
DV		 9209 /* Shut off idle work before the crtcs get freed. */
9210 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9211 intel_crtc = to_intel_crtc(crtc);
9212 del_timer_sync(&intel_crtc->idle_timer);
9213 }
9214 del_timer_sync(&dev_priv->idle_timer);
9215 cancel_work_sync(&dev_priv->idle_work);
9216
79e53945
JB		 9217 drm_mode_config_cleanup(dev);
9218}
9219
f1c79df3
ZW		 9220/*
9221 * Return which encoder is currently attached for connector.
9222 */
df0e9248 9223struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9224{
df0e9248
CW		 9225 return &intel_attached_encoder(connector)->base;
9226}
f1c79df3 9227
df0e9248
CW		 9228void intel_connector_attach_encoder(struct intel_connector *connector,
9229 struct intel_encoder *encoder)
9230{
9231 connector->encoder = encoder;
9232 drm_mode_connector_attach_encoder(&connector->base,
9233 &encoder->base);
79e53945 9234}
28d52043
DA		 9235
9236/*
9237 * set vga decode state - true == enable VGA decode
9238 */
9239int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9240{
9241 struct drm_i915_private *dev_priv = dev->dev_private;
9242 u16 gmch_ctrl;
9243
9244 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9245 if (state)
9246 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9247 else
9248 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9249 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9250 return 0;
9251}
c4a1d9e4
CW		 9252
9253#ifdef CONFIG_DEBUG_FS
9254#include <linux/seq_file.h>
9255
9256struct intel_display_error_state {
9257 struct intel_cursor_error_state {
9258 u32 control;
9259 u32 position;
9260 u32 base;
9261 u32 size;
9262 } cursor[2];
9263
9264 struct intel_pipe_error_state {
9265 u32 conf;
9266 u32 source;
9267
9268 u32 htotal;
9269 u32 hblank;
9270 u32 hsync;
9271 u32 vtotal;
9272 u32 vblank;
9273 u32 vsync;
9274 } pipe[2];
9275
9276 struct intel_plane_error_state {
9277 u32 control;
9278 u32 stride;
9279 u32 size;
9280 u32 pos;
9281 u32 addr;
9282 u32 surface;
9283 u32 tile_offset;
9284 } plane[2];
9285};
9286
9287struct intel_display_error_state *
9288intel_display_capture_error_state(struct drm_device *dev)
9289{
0206e353 9290 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9291 struct intel_display_error_state *error;
9292 int i;
9293
9294 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9295 if (error == NULL)
9296 return NULL;
9297
9298 for (i = 0; i < 2; i++) {
9299 error->cursor[i].control = I915_READ(CURCNTR(i));
9300 error->cursor[i].position = I915_READ(CURPOS(i));
9301 error->cursor[i].base = I915_READ(CURBASE(i));
9302
9303 error->plane[i].control = I915_READ(DSPCNTR(i));
9304 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9305 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9306 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9307 error->plane[i].addr = I915_READ(DSPADDR(i));
9308 if (INTEL_INFO(dev)->gen >= 4) {
9309 error->plane[i].surface = I915_READ(DSPSURF(i));
9310 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9311 }
9312
9313 error->pipe[i].conf = I915_READ(PIPECONF(i));
9314 error->pipe[i].source = I915_READ(PIPESRC(i));
9315 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9316 error->pipe[i].hblank = I915_READ(HBLANK(i));
9317 error->pipe[i].hsync = I915_READ(HSYNC(i));
9318 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9319 error->pipe[i].vblank = I915_READ(VBLANK(i));
9320 error->pipe[i].vsync = I915_READ(VSYNC(i));
9321 }
9322
9323 return error;
9324}
9325
9326void
9327intel_display_print_error_state(struct seq_file *m,
9328 struct drm_device *dev,
9329 struct intel_display_error_state *error)
9330{
9331 int i;
9332
9333 for (i = 0; i < 2; i++) {
9334 seq_printf(m, "Pipe [%d]:\n", i);
9335 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9336 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9337 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9338 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9339 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9340 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9341 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9342 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9343
9344 seq_printf(m, "Plane [%d]:\n", i);
9345 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9346 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9347 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9348 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9349 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9350 if (INTEL_INFO(dev)->gen >= 4) {
9351 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9352 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9353 }
9354
9355 seq_printf(m, "Cursor [%d]:\n", i);
9356 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9357 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9358 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9359 }
9360}
9361#endif
Linux kernel - Deliverables
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