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drm/i915: extract i9xx_set_pipeconf
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
f4808ab8
VS		 74 /**
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
77 * @crtc: current CRTC
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
84 *
85 * Returns true on success, false on failure.
86 */
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
d4906093 92};
79e53945 93
2377b741
JB		 94/* FDI */
95#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
96
d2acd215
DV		 97int
98intel_pch_rawclk(struct drm_device *dev)
99{
100 struct drm_i915_private *dev_priv = dev->dev_private;
101
102 WARN_ON(!HAS_PCH_SPLIT(dev));
103
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
105}
106
d4906093
ML		 107static bool
108intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
d4906093
ML		 111static bool
112intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
79e53945 115
a4fc5ed6
KP		 116static bool
117intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
5eb08b69 120static bool
f2b115e6 121intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
a4fc5ed6 124
a0c4da24
JB		 125static bool
126intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
129
021357ac
CW		 130static inline u32 /* units of 100MHz */
131intel_fdi_link_freq(struct drm_device *dev)
132{
8b99e68c
CW		 133 if (IS_GEN5(dev)) {
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
136 } else
137 return 27;
021357ac
CW		 138}
139
e4b36699 140static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699 166};
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
d4906093 193 .find_pll = intel_find_best_PLL,
e4b36699
KP		 194};
195
273e27ca 196
e4b36699 197static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
207 .p2_slow = 10,
208 .p2_fast = 10
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
d4906093 224 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 225};
226
227static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
044c7c41 238 },
d4906093 239 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 240};
241
242static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
044c7c41 253 },
d4906093 254 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
273e27ca 267 .p2_slow = 10, .p2_fast = 10 },
0206e353 268 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
f2b115e6 287static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
6115707b 298 .find_pll = intel_find_best_PLL,
e4b36699
KP		 299};
300
273e27ca
EA		 301/* Ironlake / Sandybridge
302 *
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
305 */
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
4547668a 317 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 318};
319
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374 .find_pll = intel_g4x_find_best_PLL,
375};
376
377static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
273e27ca 387 .p2_slow = 10, .p2_fast = 10 },
0206e353 388 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 389};
390
a0c4da24
JB		 391static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 20000, .max = 165000 },
17dc9257 407 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
419static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 422 .n = { .min = 1, .max = 7 },
74a4dd2e 423 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 2, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
431};
432
57f350b6
JB		 433u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
434{
09153000 435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 436
57f350b6
JB		 437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
09153000 439 return 0;
57f350b6
JB		 440 }
441
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
444 DPIO_BYTE);
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
09153000 447 return 0;
57f350b6 448 }
57f350b6 449
09153000 450 return I915_READ(DPIO_DATA);
57f350b6
JB		 451}
452
a0c4da24
JB		 453static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
454 u32 val)
455{
09153000 456 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 457
a0c4da24
JB		 458 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
459 DRM_ERROR("DPIO idle wait timed out\n");
09153000 460 return;
a0c4da24
JB		 461 }
462
463 I915_WRITE(DPIO_DATA, val);
464 I915_WRITE(DPIO_REG, reg);
465 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 DPIO_BYTE);
467 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
468 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 469}
470
57f350b6
JB		 471static void vlv_init_dpio(struct drm_device *dev)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474
475 /* Reset the DPIO config */
476 I915_WRITE(DPIO_CTL, 0);
477 POSTING_READ(DPIO_CTL);
478 I915_WRITE(DPIO_CTL, 1);
479 POSTING_READ(DPIO_CTL);
480}
481
1b894b59
CW		 482static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
483 int refclk)
2c07245f 484{
b91ad0ec 485 struct drm_device *dev = crtc->dev;
2c07245f 486 const intel_limit_t *limit;
b91ad0ec
ZW		 487
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 489 if (intel_is_dual_link_lvds(dev)) {
1b894b59 490 if (refclk == 100000)
b91ad0ec
ZW		 491 limit = &intel_limits_ironlake_dual_lvds_100m;
492 else
493 limit = &intel_limits_ironlake_dual_lvds;
494 } else {
1b894b59 495 if (refclk == 100000)
b91ad0ec
ZW		 496 limit = &intel_limits_ironlake_single_lvds_100m;
497 else
498 limit = &intel_limits_ironlake_single_lvds;
499 }
500 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 501 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 502 limit = &intel_limits_ironlake_display_port;
2c07245f 503 else
b91ad0ec 504 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 505
506 return limit;
507}
508
044c7c41
ML		 509static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
044c7c41
ML		 512 const intel_limit_t *limit;
513
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 515 if (intel_is_dual_link_lvds(dev))
e4b36699 516 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 517 else
e4b36699 518 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 519 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
520 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 521 limit = &intel_limits_g4x_hdmi;
044c7c41 522 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 523 limit = &intel_limits_g4x_sdvo;
0206e353 524 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 525 limit = &intel_limits_g4x_display_port;
044c7c41 526 } else /* The option is for other outputs */
e4b36699 527 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 528
529 return limit;
530}
531
1b894b59 532static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 533{
534 struct drm_device *dev = crtc->dev;
535 const intel_limit_t *limit;
536
bad720ff 537 if (HAS_PCH_SPLIT(dev))
1b894b59 538 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 539 else if (IS_G4X(dev)) {
044c7c41 540 limit = intel_g4x_limit(crtc);
f2b115e6 541 } else if (IS_PINEVIEW(dev)) {
2177832f 542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 543 limit = &intel_limits_pineview_lvds;
2177832f 544 else
f2b115e6 545 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 546 } else if (IS_VALLEYVIEW(dev)) {
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
548 limit = &intel_limits_vlv_dac;
549 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
550 limit = &intel_limits_vlv_hdmi;
551 else
552 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 553 } else if (!IS_GEN2(dev)) {
554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
555 limit = &intel_limits_i9xx_lvds;
556 else
557 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 558 } else {
559 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 560 limit = &intel_limits_i8xx_lvds;
79e53945 561 else
e4b36699 562 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 563 }
564 return limit;
565}
566
f2b115e6
AJ		 567/* m1 is reserved as 0 in Pineview, n is a ring counter */
568static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 569{
2177832f
SL		 570 clock->m = clock->m2 + 2;
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / clock->n;
573 clock->dot = clock->vco / clock->p;
574}
575
576static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
577{
f2b115e6
AJ		 578 if (IS_PINEVIEW(dev)) {
579 pineview_clock(refclk, clock);
2177832f
SL		 580 return;
581 }
79e53945
JB		 582 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
583 clock->p = clock->p1 * clock->p2;
584 clock->vco = refclk * clock->m / (clock->n + 2);
585 clock->dot = clock->vco / clock->p;
586}
587
79e53945
JB		 588/**
589 * Returns whether any output on the specified pipe is of the specified type
590 */
4ef69c7a 591bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 592{
4ef69c7a 593 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 594 struct intel_encoder *encoder;
595
6c2b7c12
DV		 596 for_each_encoder_on_crtc(dev, crtc, encoder)
597 if (encoder->type == type)
4ef69c7a
CW		 598 return true;
599
600 return false;
79e53945
JB		 601}
602
7c04d1d9 603#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 604/**
605 * Returns whether the given set of divisors are valid for a given refclk with
606 * the given connectors.
607 */
608
1b894b59
CW		 609static bool intel_PLL_is_valid(struct drm_device *dev,
610 const intel_limit_t *limit,
611 const intel_clock_t *clock)
79e53945 612{
79e53945 613 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 614 INTELPllInvalid("p1 out of range\n");
79e53945 615 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 616 INTELPllInvalid("p out of range\n");
79e53945 617 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 618 INTELPllInvalid("m2 out of range\n");
79e53945 619 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 620 INTELPllInvalid("m1 out of range\n");
f2b115e6 621 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 622 INTELPllInvalid("m1 <= m2\n");
79e53945 623 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 624 INTELPllInvalid("m out of range\n");
79e53945 625 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 626 INTELPllInvalid("n out of range\n");
79e53945 627 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 628 INTELPllInvalid("vco out of range\n");
79e53945
JB		 629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
631 */
632 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 633 INTELPllInvalid("dot out of range\n");
79e53945
JB		 634
635 return true;
636}
637
d4906093
ML		 638static bool
639intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
d4906093 642
79e53945
JB		 643{
644 struct drm_device *dev = crtc->dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a210b028 648 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 671 /* m1 is always 0 in Pineview */
672 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 673 break;
674 for (clock.n = limit->n.min;
675 clock.n <= limit->n.max; clock.n++) {
676 for (clock.p1 = limit->p1.min;
677 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 678 int this_err;
679
2177832f 680 intel_clock(dev, refclk, &clock);
1b894b59
CW		 681 if (!intel_PLL_is_valid(dev, limit,
682 &clock))
79e53945 683 continue;
cec2f356
SP		 684 if (match_clock &&
685 clock.p != match_clock->p)
686 continue;
79e53945
JB		 687
688 this_err = abs(clock.dot - target);
689 if (this_err < err) {
690 *best_clock = clock;
691 err = this_err;
692 }
693 }
694 }
695 }
696 }
697
698 return (err != target);
699}
700
d4906093
ML		 701static bool
702intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
d4906093
ML		 705{
706 struct drm_device *dev = crtc->dev;
d4906093
ML		 707 intel_clock_t clock;
708 int max_n;
709 bool found;
6ba770dc
AJ		 710 /* approximately equals target * 0.00585 */
711 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 712 found = false;
713
714 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 715 int lvds_reg;
716
c619eed4 717 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 718 lvds_reg = PCH_LVDS;
719 else
720 lvds_reg = LVDS;
1974cad0 721 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
732 memset(best_clock, 0, sizeof(*best_clock));
733 max_n = limit->n.max;
f77f13e2 734 /* based on hardware requirement, prefer smaller n to precision */
d4906093 735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 736 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 737 for (clock.m1 = limit->m1.max;
738 clock.m1 >= limit->m1.min; clock.m1--) {
739 for (clock.m2 = limit->m2.max;
740 clock.m2 >= limit->m2.min; clock.m2--) {
741 for (clock.p1 = limit->p1.max;
742 clock.p1 >= limit->p1.min; clock.p1--) {
743 int this_err;
744
2177832f 745 intel_clock(dev, refclk, &clock);
1b894b59
CW		 746 if (!intel_PLL_is_valid(dev, limit,
747 &clock))
d4906093 748 continue;
cec2f356
SP		 749 if (match_clock &&
750 clock.p != match_clock->p)
751 continue;
1b894b59
CW		 752
753 this_err = abs(clock.dot - target);
d4906093
ML		 754 if (this_err < err_most) {
755 *best_clock = clock;
756 err_most = this_err;
757 max_n = clock.n;
758 found = true;
759 }
760 }
761 }
762 }
763 }
2c07245f
ZW		 764 return found;
765}
766
5eb08b69 767static bool
f2b115e6 768intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
5eb08b69
ZW		 771{
772 struct drm_device *dev = crtc->dev;
773 intel_clock_t clock;
4547668a 774
5eb08b69
ZW		 775 if (target < 200000) {
776 clock.n = 1;
777 clock.p1 = 2;
778 clock.p2 = 10;
779 clock.m1 = 12;
780 clock.m2 = 9;
781 } else {
782 clock.n = 2;
783 clock.p1 = 1;
784 clock.p2 = 10;
785 clock.m1 = 14;
786 clock.m2 = 8;
787 }
788 intel_clock(dev, refclk, &clock);
789 memcpy(best_clock, &clock, sizeof(intel_clock_t));
790 return true;
791}
792
a4fc5ed6
KP		 793/* DisplayPort has only two frequencies, 162MHz and 270MHz */
794static bool
795intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 796 int target, int refclk, intel_clock_t *match_clock,
797 intel_clock_t *best_clock)
a4fc5ed6 798{
5eddb70b
CW		 799 intel_clock_t clock;
800 if (target < 200000) {
801 clock.p1 = 2;
802 clock.p2 = 10;
803 clock.n = 2;
804 clock.m1 = 23;
805 clock.m2 = 8;
806 } else {
807 clock.p1 = 1;
808 clock.p2 = 10;
809 clock.n = 1;
810 clock.m1 = 14;
811 clock.m2 = 2;
812 }
813 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
814 clock.p = (clock.p1 * clock.p2);
815 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
816 clock.vco = 0;
817 memcpy(best_clock, &clock, sizeof(intel_clock_t));
818 return true;
a4fc5ed6 819}
a0c4da24
JB		 820static bool
821intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
822 int target, int refclk, intel_clock_t *match_clock,
823 intel_clock_t *best_clock)
824{
825 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
826 u32 m, n, fastclk;
827 u32 updrate, minupdate, fracbits, p;
828 unsigned long bestppm, ppm, absppm;
829 int dotclk, flag;
830
af447bd3 831 flag = 0;
a0c4da24
JB		 832 dotclk = target * 1000;
833 bestppm = 1000000;
834 ppm = absppm = 0;
835 fastclk = dotclk / (2*100);
836 updrate = 0;
837 minupdate = 19200;
838 fracbits = 1;
839 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
840 bestm1 = bestm2 = bestp1 = bestp2 = 0;
841
842 /* based on hardware requirement, prefer smaller n to precision */
843 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
844 updrate = refclk / n;
845 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
846 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
847 if (p2 > 10)
848 p2 = p2 - 1;
849 p = p1 * p2;
850 /* based on hardware requirement, prefer bigger m1,m2 values */
851 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
852 m2 = (((2*(fastclk * p * n / m1 )) +
853 refclk) / (2*refclk));
854 m = m1 * m2;
855 vco = updrate * m;
856 if (vco >= limit->vco.min && vco < limit->vco.max) {
857 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
858 absppm = (ppm > 0) ? ppm : (-ppm);
859 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
860 bestppm = 0;
861 flag = 1;
862 }
863 if (absppm < bestppm - 10) {
864 bestppm = absppm;
865 flag = 1;
866 }
867 if (flag) {
868 bestn = n;
869 bestm1 = m1;
870 bestm2 = m2;
871 bestp1 = p1;
872 bestp2 = p2;
873 flag = 0;
874 }
875 }
876 }
877 }
878 }
879 }
880 best_clock->n = bestn;
881 best_clock->m1 = bestm1;
882 best_clock->m2 = bestm2;
883 best_clock->p1 = bestp1;
884 best_clock->p2 = bestp2;
885
886 return true;
887}
a4fc5ed6 888
a5c961d1
PZ		 889enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
894
895 return intel_crtc->cpu_transcoder;
896}
897
a928d536
PZ		 898static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
899{
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 u32 frame, frame_reg = PIPEFRAME(pipe);
902
903 frame = I915_READ(frame_reg);
904
905 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
906 DRM_DEBUG_KMS("vblank wait timed out\n");
907}
908
9d0498a2
JB		 909/**
910 * intel_wait_for_vblank - wait for vblank on a given pipe
911 * @dev: drm device
912 * @pipe: pipe to wait for
913 *
914 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 * mode setting code.
916 */
917void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 918{
9d0498a2 919 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 920 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 921
a928d536
PZ		 922 if (INTEL_INFO(dev)->gen >= 5) {
923 ironlake_wait_for_vblank(dev, pipe);
924 return;
925 }
926
300387c0
CW		 927 /* Clear existing vblank status. Note this will clear any other
928 * sticky status fields as well.
929 *
930 * This races with i915_driver_irq_handler() with the result
931 * that either function could miss a vblank event. Here it is not
932 * fatal, as we will either wait upon the next vblank interrupt or
933 * timeout. Generally speaking intel_wait_for_vblank() is only
934 * called during modeset at which time the GPU should be idle and
935 * should *not* be performing page flips and thus not waiting on
936 * vblanks...
937 * Currently, the result of us stealing a vblank from the irq
938 * handler is that a single frame will be skipped during swapbuffers.
939 */
940 I915_WRITE(pipestat_reg,
941 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
942
9d0498a2 943 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 944 if (wait_for(I915_READ(pipestat_reg) &
945 PIPE_VBLANK_INTERRUPT_STATUS,
946 50))
9d0498a2
JB		 947 DRM_DEBUG_KMS("vblank wait timed out\n");
948}
949
ab7ad7f6
KP		 950/*
951 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 952 * @dev: drm device
953 * @pipe: pipe to wait for
954 *
955 * After disabling a pipe, we can't wait for vblank in the usual way,
956 * spinning on the vblank interrupt status bit, since we won't actually
957 * see an interrupt when the pipe is disabled.
958 *
ab7ad7f6
KP		 959 * On Gen4 and above:
960 * wait for the pipe register state bit to turn off
961 *
962 * Otherwise:
963 * wait for the display line value to settle (it usually
964 * ends up stopping at the start of the next frame).
58e10eb9 965 *
9d0498a2 966 */
58e10eb9 967void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 968{
969 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
ab7ad7f6
KP		 972
973 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 974 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 975
976 /* Wait for the Pipe State to go off */
58e10eb9
CW		 977 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
978 100))
284637d9 979 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 980 } else {
837ba00f 981 u32 last_line, line_mask;
58e10eb9 982 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 983 unsigned long timeout = jiffies + msecs_to_jiffies(100);
984
837ba00f
PZ		 985 if (IS_GEN2(dev))
986 line_mask = DSL_LINEMASK_GEN2;
987 else
988 line_mask = DSL_LINEMASK_GEN3;
989
ab7ad7f6
KP		 990 /* Wait for the display line to settle */
991 do {
837ba00f 992 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 993 mdelay(5);
837ba00f 994 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 995 time_after(timeout, jiffies));
996 if (time_after(jiffies, timeout))
284637d9 997 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 998 }
79e53945
JB		 999}
1000
b0ea7d37
DL		 1001/*
1002 * ibx_digital_port_connected - is the specified port connected?
1003 * @dev_priv: i915 private structure
1004 * @port: the port to test
1005 *
1006 * Returns true if @port is connected, false otherwise.
1007 */
1008bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1009 struct intel_digital_port *port)
1010{
1011 u32 bit;
1012
c36346e3
DL		 1013 if (HAS_PCH_IBX(dev_priv->dev)) {
1014 switch(port->port) {
1015 case PORT_B:
1016 bit = SDE_PORTB_HOTPLUG;
1017 break;
1018 case PORT_C:
1019 bit = SDE_PORTC_HOTPLUG;
1020 break;
1021 case PORT_D:
1022 bit = SDE_PORTD_HOTPLUG;
1023 break;
1024 default:
1025 return true;
1026 }
1027 } else {
1028 switch(port->port) {
1029 case PORT_B:
1030 bit = SDE_PORTB_HOTPLUG_CPT;
1031 break;
1032 case PORT_C:
1033 bit = SDE_PORTC_HOTPLUG_CPT;
1034 break;
1035 case PORT_D:
1036 bit = SDE_PORTD_HOTPLUG_CPT;
1037 break;
1038 default:
1039 return true;
1040 }
b0ea7d37
DL		 1041 }
1042
1043 return I915_READ(SDEISR) & bit;
1044}
1045
b24e7179
JB		 1046static const char *state_string(bool enabled)
1047{
1048 return enabled ? "on" : "off";
1049}
1050
1051/* Only for pre-ILK configs */
1052static void assert_pll(struct drm_i915_private *dev_priv,
1053 enum pipe pipe, bool state)
1054{
1055 int reg;
1056 u32 val;
1057 bool cur_state;
1058
1059 reg = DPLL(pipe);
1060 val = I915_READ(reg);
1061 cur_state = !!(val & DPLL_VCO_ENABLE);
1062 WARN(cur_state != state,
1063 "PLL state assertion failure (expected %s, current %s)\n",
1064 state_string(state), state_string(cur_state));
1065}
1066#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1067#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1068
040484af
JB		 1069/* For ILK+ */
1070static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1071 struct intel_pch_pll *pll,
1072 struct intel_crtc *crtc,
1073 bool state)
040484af 1074{
040484af
JB		 1075 u32 val;
1076 bool cur_state;
1077
9d82aa17
ED		 1078 if (HAS_PCH_LPT(dev_priv->dev)) {
1079 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1080 return;
1081 }
1082
92b27b08
CW		 1083 if (WARN (!pll,
1084 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1085 return;
ee7b9f93 1086
92b27b08
CW		 1087 val = I915_READ(pll->pll_reg);
1088 cur_state = !!(val & DPLL_VCO_ENABLE);
1089 WARN(cur_state != state,
1090 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1091 pll->pll_reg, state_string(state), state_string(cur_state), val);
1092
1093 /* Make sure the selected PLL is correctly attached to the transcoder */
1094 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1095 u32 pch_dpll;
1096
1097 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1098 cur_state = pll->pll_reg == _PCH_DPLL_B;
1099 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1100 "PLL[%d] not attached to this transcoder %d: %08x\n",
1101 cur_state, crtc->pipe, pch_dpll)) {
1102 cur_state = !!(val >> (4*crtc->pipe + 3));
1103 WARN(cur_state != state,
1104 "PLL[%d] not %s on this transcoder %d: %08x\n",
1105 pll->pll_reg == _PCH_DPLL_B,
1106 state_string(state),
1107 crtc->pipe,
1108 val);
1109 }
d3ccbe86 1110 }
040484af 1111}
92b27b08
CW		 1112#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1113#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1114
1115static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1116 enum pipe pipe, bool state)
1117{
1118 int reg;
1119 u32 val;
1120 bool cur_state;
ad80a810
PZ		 1121 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1122 pipe);
040484af 1123
affa9354
PZ		 1124 if (HAS_DDI(dev_priv->dev)) {
1125 /* DDI does not have a specific FDI_TX register */
ad80a810 1126 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1127 val = I915_READ(reg);
ad80a810 1128 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1129 } else {
1130 reg = FDI_TX_CTL(pipe);
1131 val = I915_READ(reg);
1132 cur_state = !!(val & FDI_TX_ENABLE);
1133 }
040484af
JB		 1134 WARN(cur_state != state,
1135 "FDI TX state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
1138#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1139#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1140
1141static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143{
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
d63fa0dc
PZ		 1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1151 WARN(cur_state != state,
1152 "FDI RX state assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154}
1155#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1156#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1157
1158static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1159 enum pipe pipe)
1160{
1161 int reg;
1162 u32 val;
1163
1164 /* ILK FDI PLL is always enabled */
1165 if (dev_priv->info->gen == 5)
1166 return;
1167
bf507ef7 1168 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1169 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1170 return;
1171
040484af
JB		 1172 reg = FDI_TX_CTL(pipe);
1173 val = I915_READ(reg);
1174 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1175}
1176
1177static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1178 enum pipe pipe)
1179{
1180 int reg;
1181 u32 val;
1182
1183 reg = FDI_RX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1186}
1187
ea0760cf
JB		 1188static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
0de3b485 1194 bool locked = true;
ea0760cf
JB		 1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1214 pipe_name(pipe));
ea0760cf
JB		 1215}
1216
b840d907
JB		 1217void assert_pipe(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
b24e7179
JB		 1219{
1220 int reg;
1221 u32 val;
63d7bbe9 1222 bool cur_state;
702e7a56
PZ		 1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
b24e7179 1225
8e636784
DV		 1226 /* if we need the pipe A quirk it must be always on */
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228 state = true;
1229
69310161
PZ		 1230 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1231 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
63d7bbe9
JB		 1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1241 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1242}
1243
931872fc
CW		 1244static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
b24e7179
JB		 1246{
1247 int reg;
1248 u32 val;
931872fc 1249 bool cur_state;
b24e7179
JB		 1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
931872fc
CW		 1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1257}
1258
931872fc
CW		 1259#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
b24e7179
JB		 1262static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264{
1265 int reg, i;
1266 u32 val;
1267 int cur_pipe;
1268
19ec1358 1269 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1270 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1271 reg = DSPCNTR(pipe);
1272 val = I915_READ(reg);
1273 WARN((val & DISPLAY_PLANE_ENABLE),
1274 "plane %c assertion failure, should be disabled but not\n",
1275 plane_name(pipe));
19ec1358 1276 return;
28c05794 1277 }
19ec1358 1278
b24e7179
JB		 1279 /* Need to check both planes against the pipe */
1280 for (i = 0; i < 2; i++) {
1281 reg = DSPCNTR(i);
1282 val = I915_READ(reg);
1283 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1284 DISPPLANE_SEL_PIPE_SHIFT;
1285 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1286 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1287 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1288 }
1289}
1290
19332d7a
JB		 1291static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg, i;
1295 u32 val;
1296
1297 if (!IS_VALLEYVIEW(dev_priv->dev))
1298 return;
1299
1300 /* Need to check both planes against the pipe */
1301 for (i = 0; i < dev_priv->num_plane; i++) {
1302 reg = SPCNTR(pipe, i);
1303 val = I915_READ(reg);
1304 WARN((val & SP_ENABLE),
1305 "sprite %d assertion failure, should be off on pipe %c but is still active\n",
1306 pipe * 2 + i, pipe_name(pipe));
1307 }
1308}
1309
92f2584a
JB		 1310static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1311{
1312 u32 val;
1313 bool enabled;
1314
9d82aa17
ED		 1315 if (HAS_PCH_LPT(dev_priv->dev)) {
1316 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1317 return;
1318 }
1319
92f2584a
JB		 1320 val = I915_READ(PCH_DREF_CONTROL);
1321 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1322 DREF_SUPERSPREAD_SOURCE_MASK));
1323 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1324}
1325
1326static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1327 enum pipe pipe)
1328{
1329 int reg;
1330 u32 val;
1331 bool enabled;
1332
1333 reg = TRANSCONF(pipe);
1334 val = I915_READ(reg);
1335 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1336 WARN(enabled,
1337 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1338 pipe_name(pipe));
92f2584a
JB		 1339}
1340
4e634389
KP		 1341static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1342 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1343{
1344 if ((val & DP_PORT_EN) == 0)
1345 return false;
1346
1347 if (HAS_PCH_CPT(dev_priv->dev)) {
1348 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1349 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1350 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1351 return false;
1352 } else {
1353 if ((val & DP_PIPE_MASK) != (pipe << 30))
1354 return false;
1355 }
1356 return true;
1357}
1358
1519b995
KP		 1359static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
dc0fa718 1362 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1363 return false;
1364
1365 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1366 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1367 return false;
1368 } else {
dc0fa718 1369 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1370 return false;
1371 }
1372 return true;
1373}
1374
1375static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1376 enum pipe pipe, u32 val)
1377{
1378 if ((val & LVDS_PORT_EN) == 0)
1379 return false;
1380
1381 if (HAS_PCH_CPT(dev_priv->dev)) {
1382 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1383 return false;
1384 } else {
1385 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1386 return false;
1387 }
1388 return true;
1389}
1390
1391static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393{
1394 if ((val & ADPA_DAC_ENABLE) == 0)
1395 return false;
1396 if (HAS_PCH_CPT(dev_priv->dev)) {
1397 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1398 return false;
1399 } else {
1400 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1401 return false;
1402 }
1403 return true;
1404}
1405
291906f1 1406static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1407 enum pipe pipe, int reg, u32 port_sel)
291906f1 1408{
47a05eca 1409 u32 val = I915_READ(reg);
4e634389 1410 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1411 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1412 reg, pipe_name(pipe));
de9a35ab 1413
75c5da27
DV		 1414 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1415 && (val & DP_PIPEB_SELECT),
de9a35ab 1416 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1417}
1418
1419static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, int reg)
1421{
47a05eca 1422 u32 val = I915_READ(reg);
b70ad586 1423 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1424 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1425 reg, pipe_name(pipe));
de9a35ab 1426
dc0fa718 1427 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1428 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1429 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1430}
1431
1432static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe)
1434{
1435 int reg;
1436 u32 val;
291906f1 1437
f0575e92
KP		 1438 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1441
1442 reg = PCH_ADPA;
1443 val = I915_READ(reg);
b70ad586 1444 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1445 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1446 pipe_name(pipe));
291906f1
JB		 1447
1448 reg = PCH_LVDS;
1449 val = I915_READ(reg);
b70ad586 1450 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1451 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1452 pipe_name(pipe));
291906f1 1453
e2debe91
PZ		 1454 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1457}
1458
63d7bbe9
JB		 1459/**
1460 * intel_enable_pll - enable a PLL
1461 * @dev_priv: i915 private structure
1462 * @pipe: pipe PLL to enable
1463 *
1464 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1465 * make sure the PLL reg is writable first though, since the panel write
1466 * protect mechanism may be enabled.
1467 *
1468 * Note! This is for pre-ILK only.
7434a255
TR		 1469 *
1470 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1471 */
1472static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* No really, not for ILK+ */
a0c4da24 1478 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1479
1480 /* PLL is protected by panel, make sure we can write it */
1481 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1482 assert_panel_unlocked(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val |= DPLL_VCO_ENABLE;
1487
1488 /* We do this three times for luck */
1489 I915_WRITE(reg, val);
1490 POSTING_READ(reg);
1491 udelay(150); /* wait for warmup */
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494 udelay(150); /* wait for warmup */
1495 I915_WRITE(reg, val);
1496 POSTING_READ(reg);
1497 udelay(150); /* wait for warmup */
1498}
1499
1500/**
1501 * intel_disable_pll - disable a PLL
1502 * @dev_priv: i915 private structure
1503 * @pipe: pipe PLL to disable
1504 *
1505 * Disable the PLL for @pipe, making sure the pipe is off first.
1506 *
1507 * Note! This is for pre-ILK only.
1508 */
1509static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1510{
1511 int reg;
1512 u32 val;
1513
1514 /* Don't disable pipe A or pipe A PLLs if needed */
1515 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1516 return;
1517
1518 /* Make sure the pipe isn't still relying on us */
1519 assert_pipe_disabled(dev_priv, pipe);
1520
1521 reg = DPLL(pipe);
1522 val = I915_READ(reg);
1523 val &= ~DPLL_VCO_ENABLE;
1524 I915_WRITE(reg, val);
1525 POSTING_READ(reg);
1526}
1527
a416edef
ED		 1528/* SBI access */
1529static void
988d6ee8
PZ		 1530intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1531 enum intel_sbi_destination destination)
a416edef 1532{
988d6ee8 1533 u32 tmp;
a416edef 1534
09153000 1535 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1536
39fb50f6 1537 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1538 100)) {
1539 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1540 return;
a416edef
ED		 1541 }
1542
988d6ee8
PZ		 1543 I915_WRITE(SBI_ADDR, (reg << 16));
1544 I915_WRITE(SBI_DATA, value);
1545
1546 if (destination == SBI_ICLK)
1547 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1548 else
1549 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1550 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1551
39fb50f6 1552 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1553 100)) {
1554 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1555 return;
a416edef 1556 }
a416edef
ED		 1557}
1558
1559static u32
988d6ee8
PZ		 1560intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1561 enum intel_sbi_destination destination)
a416edef 1562{
39fb50f6 1563 u32 value = 0;
09153000 1564 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1565
39fb50f6 1566 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1567 100)) {
1568 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1569 return 0;
a416edef
ED		 1570 }
1571
988d6ee8
PZ		 1572 I915_WRITE(SBI_ADDR, (reg << 16));
1573
1574 if (destination == SBI_ICLK)
1575 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1576 else
1577 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1578 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1579
39fb50f6 1580 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1581 100)) {
1582 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1583 return 0;
a416edef
ED		 1584 }
1585
09153000 1586 return I915_READ(SBI_DATA);
a416edef
ED		 1587}
1588
92f2584a 1589/**
b6b4e185 1590 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1591 * @dev_priv: i915 private structure
1592 * @pipe: pipe PLL to enable
1593 *
1594 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1595 * drives the transcoder clock.
1596 */
b6b4e185 1597static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1598{
ee7b9f93 1599 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1600 struct intel_pch_pll *pll;
92f2584a
JB		 1601 int reg;
1602 u32 val;
1603
48da64a8 1604 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1605 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1606 pll = intel_crtc->pch_pll;
1607 if (pll == NULL)
1608 return;
1609
1610 if (WARN_ON(pll->refcount == 0))
1611 return;
ee7b9f93
JB		 1612
1613 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1614 pll->pll_reg, pll->active, pll->on,
1615 intel_crtc->base.base.id);
92f2584a
JB		 1616
1617 /* PCH refclock must be enabled first */
1618 assert_pch_refclk_enabled(dev_priv);
1619
ee7b9f93 1620 if (pll->active++ && pll->on) {
92b27b08 1621 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1622 return;
1623 }
1624
1625 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1626
1627 reg = pll->pll_reg;
92f2584a
JB		 1628 val = I915_READ(reg);
1629 val |= DPLL_VCO_ENABLE;
1630 I915_WRITE(reg, val);
1631 POSTING_READ(reg);
1632 udelay(200);
ee7b9f93
JB		 1633
1634 pll->on = true;
92f2584a
JB		 1635}
1636
ee7b9f93 1637static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1638{
ee7b9f93
JB		 1639 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1640 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1641 int reg;
ee7b9f93 1642 u32 val;
4c609cb8 1643
92f2584a
JB		 1644 /* PCH only available on ILK+ */
1645 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1646 if (pll == NULL)
1647 return;
92f2584a 1648
48da64a8
CW		 1649 if (WARN_ON(pll->refcount == 0))
1650 return;
7a419866 1651
ee7b9f93
JB		 1652 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1653 pll->pll_reg, pll->active, pll->on,
1654 intel_crtc->base.base.id);
7a419866 1655
48da64a8 1656 if (WARN_ON(pll->active == 0)) {
92b27b08 1657 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1658 return;
1659 }
1660
ee7b9f93 1661 if (--pll->active) {
92b27b08 1662 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1663 return;
ee7b9f93
JB		 1664 }
1665
1666 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1667
1668 /* Make sure transcoder isn't still depending on us */
1669 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1670
ee7b9f93 1671 reg = pll->pll_reg;
92f2584a
JB		 1672 val = I915_READ(reg);
1673 val &= ~DPLL_VCO_ENABLE;
1674 I915_WRITE(reg, val);
1675 POSTING_READ(reg);
1676 udelay(200);
ee7b9f93
JB		 1677
1678 pll->on = false;
92f2584a
JB		 1679}
1680
b8a4f404
PZ		 1681static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1682 enum pipe pipe)
040484af 1683{
23670b32 1684 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1685 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1686 uint32_t reg, val, pipeconf_val;
040484af
JB		 1687
1688 /* PCH only available on ILK+ */
1689 BUG_ON(dev_priv->info->gen < 5);
1690
1691 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1692 assert_pch_pll_enabled(dev_priv,
1693 to_intel_crtc(crtc)->pch_pll,
1694 to_intel_crtc(crtc));
040484af
JB		 1695
1696 /* FDI must be feeding us bits for PCH ports */
1697 assert_fdi_tx_enabled(dev_priv, pipe);
1698 assert_fdi_rx_enabled(dev_priv, pipe);
1699
23670b32
DV		 1700 if (HAS_PCH_CPT(dev)) {
1701 /* Workaround: Set the timing override bit before enabling the
1702 * pch transcoder. */
1703 reg = TRANS_CHICKEN2(pipe);
1704 val = I915_READ(reg);
1705 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1706 I915_WRITE(reg, val);
59c859d6 1707 }
23670b32 1708
040484af
JB		 1709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
5f7f726d 1711 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1712
1713 if (HAS_PCH_IBX(dev_priv->dev)) {
1714 /*
1715 * make the BPC in transcoder be consistent with
1716 * that in pipeconf reg.
1717 */
dfd07d72
DV		 1718 val &= ~PIPECONF_BPC_MASK;
1719 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1720 }
5f7f726d
PZ		 1721
1722 val &= ~TRANS_INTERLACE_MASK;
1723 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1724 if (HAS_PCH_IBX(dev_priv->dev) &&
1725 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1726 val |= TRANS_LEGACY_INTERLACED_ILK;
1727 else
1728 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1729 else
1730 val |= TRANS_PROGRESSIVE;
1731
040484af
JB		 1732 I915_WRITE(reg, val | TRANS_ENABLE);
1733 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1734 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1735}
1736
8fb033d7 1737static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1738 enum transcoder cpu_transcoder)
040484af 1739{
8fb033d7 1740 u32 val, pipeconf_val;
8fb033d7
PZ		 1741
1742 /* PCH only available on ILK+ */
1743 BUG_ON(dev_priv->info->gen < 5);
1744
8fb033d7 1745 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1746 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1747 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1748
223a6fdf
PZ		 1749 /* Workaround: set timing override bit. */
1750 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1751 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1752 I915_WRITE(_TRANSA_CHICKEN2, val);
1753
25f3ef11 1754 val = TRANS_ENABLE;
937bb610 1755 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1756
9a76b1c6
PZ		 1757 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1758 PIPECONF_INTERLACED_ILK)
a35f2679 1759 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1760 else
1761 val |= TRANS_PROGRESSIVE;
1762
25f3ef11 1763 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1764 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1765 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1766}
1767
b8a4f404
PZ		 1768static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1769 enum pipe pipe)
040484af 1770{
23670b32
DV		 1771 struct drm_device *dev = dev_priv->dev;
1772 uint32_t reg, val;
040484af
JB		 1773
1774 /* FDI relies on the transcoder */
1775 assert_fdi_tx_disabled(dev_priv, pipe);
1776 assert_fdi_rx_disabled(dev_priv, pipe);
1777
291906f1
JB		 1778 /* Ports must be off as well */
1779 assert_pch_ports_disabled(dev_priv, pipe);
1780
040484af
JB		 1781 reg = TRANSCONF(pipe);
1782 val = I915_READ(reg);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(reg, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1787 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1788
1789 if (!HAS_PCH_IBX(dev)) {
1790 /* Workaround: Clear the timing override chicken bit again. */
1791 reg = TRANS_CHICKEN2(pipe);
1792 val = I915_READ(reg);
1793 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1794 I915_WRITE(reg, val);
1795 }
040484af
JB		 1796}
1797
ab4d966c 1798static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1799{
8fb033d7
PZ		 1800 u32 val;
1801
8a52fd9f 1802 val = I915_READ(_TRANSACONF);
8fb033d7 1803 val &= ~TRANS_ENABLE;
8a52fd9f 1804 I915_WRITE(_TRANSACONF, val);
8fb033d7 1805 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1806 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1807 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1808
1809 /* Workaround: clear timing override bit. */
1810 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1811 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1812 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1813}
1814
b24e7179 1815/**
309cfea8 1816 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1817 * @dev_priv: i915 private structure
1818 * @pipe: pipe to enable
040484af 1819 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1820 *
1821 * Enable @pipe, making sure that various hardware specific requirements
1822 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1823 *
1824 * @pipe should be %PIPE_A or %PIPE_B.
1825 *
1826 * Will wait until the pipe is actually running (i.e. first vblank) before
1827 * returning.
1828 */
040484af
JB		 1829static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1830 bool pch_port)
b24e7179 1831{
702e7a56
PZ		 1832 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1833 pipe);
1a240d4d 1834 enum pipe pch_transcoder;
b24e7179
JB		 1835 int reg;
1836 u32 val;
1837
681e5811 1838 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1839 pch_transcoder = TRANSCODER_A;
1840 else
1841 pch_transcoder = pipe;
1842
b24e7179
JB		 1843 /*
1844 * A pipe without a PLL won't actually be able to drive bits from
1845 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1846 * need the check.
1847 */
1848 if (!HAS_PCH_SPLIT(dev_priv->dev))
1849 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1850 else {
1851 if (pch_port) {
1852 /* if driving the PCH, we need FDI enabled */
cc391bbb 1853 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1854 assert_fdi_tx_pll_enabled(dev_priv,
1855 (enum pipe) cpu_transcoder);
040484af
JB		 1856 }
1857 /* FIXME: assert CPU port conditions for SNB+ */
1858 }
b24e7179 1859
702e7a56 1860 reg = PIPECONF(cpu_transcoder);
b24e7179 1861 val = I915_READ(reg);
00d70b15
CW		 1862 if (val & PIPECONF_ENABLE)
1863 return;
1864
1865 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1866 intel_wait_for_vblank(dev_priv->dev, pipe);
1867}
1868
1869/**
309cfea8 1870 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1871 * @dev_priv: i915 private structure
1872 * @pipe: pipe to disable
1873 *
1874 * Disable @pipe, making sure that various hardware specific requirements
1875 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1876 *
1877 * @pipe should be %PIPE_A or %PIPE_B.
1878 *
1879 * Will wait until the pipe has shut down before returning.
1880 */
1881static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1882 enum pipe pipe)
1883{
702e7a56
PZ		 1884 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1885 pipe);
b24e7179
JB		 1886 int reg;
1887 u32 val;
1888
1889 /*
1890 * Make sure planes won't keep trying to pump pixels to us,
1891 * or we might hang the display.
1892 */
1893 assert_planes_disabled(dev_priv, pipe);
19332d7a 1894 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1895
1896 /* Don't disable pipe A or pipe A PLLs if needed */
1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1898 return;
1899
702e7a56 1900 reg = PIPECONF(cpu_transcoder);
b24e7179 1901 val = I915_READ(reg);
00d70b15
CW		 1902 if ((val & PIPECONF_ENABLE) == 0)
1903 return;
1904
1905 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1906 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1907}
1908
d74362c9
KP		 1909/*
1910 * Plane regs are double buffered, going from enabled->disabled needs a
1911 * trigger in order to latch. The display address reg provides this.
1912 */
6f1d69b0 1913void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1914 enum plane plane)
1915{
14f86147
DL		 1916 if (dev_priv->info->gen >= 4)
1917 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1918 else
1919 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1920}
1921
b24e7179
JB		 1922/**
1923 * intel_enable_plane - enable a display plane on a given pipe
1924 * @dev_priv: i915 private structure
1925 * @plane: plane to enable
1926 * @pipe: pipe being fed
1927 *
1928 * Enable @plane on @pipe, making sure that @pipe is running first.
1929 */
1930static void intel_enable_plane(struct drm_i915_private *dev_priv,
1931 enum plane plane, enum pipe pipe)
1932{
1933 int reg;
1934 u32 val;
1935
1936 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1937 assert_pipe_enabled(dev_priv, pipe);
1938
1939 reg = DSPCNTR(plane);
1940 val = I915_READ(reg);
00d70b15
CW		 1941 if (val & DISPLAY_PLANE_ENABLE)
1942 return;
1943
1944 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1945 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1946 intel_wait_for_vblank(dev_priv->dev, pipe);
1947}
1948
b24e7179
JB		 1949/**
1950 * intel_disable_plane - disable a display plane
1951 * @dev_priv: i915 private structure
1952 * @plane: plane to disable
1953 * @pipe: pipe consuming the data
1954 *
1955 * Disable @plane; should be an independent operation.
1956 */
1957static void intel_disable_plane(struct drm_i915_private *dev_priv,
1958 enum plane plane, enum pipe pipe)
1959{
1960 int reg;
1961 u32 val;
1962
1963 reg = DSPCNTR(plane);
1964 val = I915_READ(reg);
00d70b15
CW		 1965 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1966 return;
1967
1968 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1969 intel_flush_display_plane(dev_priv, plane);
1970 intel_wait_for_vblank(dev_priv->dev, pipe);
1971}
1972
693db184
CW		 1973static bool need_vtd_wa(struct drm_device *dev)
1974{
1975#ifdef CONFIG_INTEL_IOMMU
1976 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1977 return true;
1978#endif
1979 return false;
1980}
1981
127bd2ac 1982int
48b956c5 1983intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1984 struct drm_i915_gem_object *obj,
919926ae 1985 struct intel_ring_buffer *pipelined)
6b95a207 1986{
ce453d81 1987 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1988 u32 alignment;
1989 int ret;
1990
05394f39 1991 switch (obj->tiling_mode) {
6b95a207 1992 case I915_TILING_NONE:
534843da
CW		 1993 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1994 alignment = 128 * 1024;
a6c45cf0 1995 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1996 alignment = 4 * 1024;
1997 else
1998 alignment = 64 * 1024;
6b95a207
KH		 1999 break;
2000 case I915_TILING_X:
2001 /* pin() will align the object as required by fence */
2002 alignment = 0;
2003 break;
2004 case I915_TILING_Y:
2005 /* FIXME: Is this true? */
2006 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2007 return -EINVAL;
2008 default:
2009 BUG();
2010 }
2011
693db184
CW		 2012 /* Note that the w/a also requires 64 PTE of padding following the
2013 * bo. We currently fill all unused PTE with the shadow page and so
2014 * we should always have valid PTE following the scanout preventing
2015 * the VT-d warning.
2016 */
2017 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2018 alignment = 256 * 1024;
2019
ce453d81 2020 dev_priv->mm.interruptible = false;
2da3b9b9 2021 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2022 if (ret)
ce453d81 2023 goto err_interruptible;
6b95a207
KH		 2024
2025 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2026 * fence, whereas 965+ only requires a fence if using
2027 * framebuffer compression. For simplicity, we always install
2028 * a fence as the cost is not that onerous.
2029 */
06d98131 2030 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2031 if (ret)
2032 goto err_unpin;
1690e1eb 2033
9a5a53b3 2034 i915_gem_object_pin_fence(obj);
6b95a207 2035
ce453d81 2036 dev_priv->mm.interruptible = true;
6b95a207 2037 return 0;
48b956c5
CW		 2038
2039err_unpin:
2040 i915_gem_object_unpin(obj);
ce453d81
CW		 2041err_interruptible:
2042 dev_priv->mm.interruptible = true;
48b956c5 2043 return ret;
6b95a207
KH		 2044}
2045
1690e1eb
CW		 2046void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2047{
2048 i915_gem_object_unpin_fence(obj);
2049 i915_gem_object_unpin(obj);
2050}
2051
c2c75131
DV		 2052/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2053 * is assumed to be a power-of-two. */
bc752862
CW		 2054unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2055 unsigned int tiling_mode,
2056 unsigned int cpp,
2057 unsigned int pitch)
c2c75131 2058{
bc752862
CW		 2059 if (tiling_mode != I915_TILING_NONE) {
2060 unsigned int tile_rows, tiles;
c2c75131 2061
bc752862
CW		 2062 tile_rows = *y / 8;
2063 *y %= 8;
c2c75131 2064
bc752862
CW		 2065 tiles = *x / (512/cpp);
2066 *x %= 512/cpp;
2067
2068 return tile_rows * pitch * 8 + tiles * 4096;
2069 } else {
2070 unsigned int offset;
2071
2072 offset = *y * pitch + *x * cpp;
2073 *y = 0;
2074 *x = (offset & 4095) / cpp;
2075 return offset & -4096;
2076 }
c2c75131
DV		 2077}
2078
17638cd6
JB		 2079static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2080 int x, int y)
81255565
JB		 2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
05394f39 2086 struct drm_i915_gem_object *obj;
81255565 2087 int plane = intel_crtc->plane;
e506a0c6 2088 unsigned long linear_offset;
81255565 2089 u32 dspcntr;
5eddb70b 2090 u32 reg;
81255565
JB		 2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
2095 break;
2096 default:
2097 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2098 return -EINVAL;
2099 }
2100
2101 intel_fb = to_intel_framebuffer(fb);
2102 obj = intel_fb->obj;
81255565 2103
5eddb70b
CW		 2104 reg = DSPCNTR(plane);
2105 dspcntr = I915_READ(reg);
81255565
JB		 2106 /* Mask out pixel format bits in case we change it */
2107 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2108 switch (fb->pixel_format) {
2109 case DRM_FORMAT_C8:
81255565
JB		 2110 dspcntr |= DISPPLANE_8BPP;
2111 break;
57779d06
VS		 2112 case DRM_FORMAT_XRGB1555:
2113 case DRM_FORMAT_ARGB1555:
2114 dspcntr |= DISPPLANE_BGRX555;
81255565 2115 break;
57779d06
VS		 2116 case DRM_FORMAT_RGB565:
2117 dspcntr |= DISPPLANE_BGRX565;
2118 break;
2119 case DRM_FORMAT_XRGB8888:
2120 case DRM_FORMAT_ARGB8888:
2121 dspcntr |= DISPPLANE_BGRX888;
2122 break;
2123 case DRM_FORMAT_XBGR8888:
2124 case DRM_FORMAT_ABGR8888:
2125 dspcntr |= DISPPLANE_RGBX888;
2126 break;
2127 case DRM_FORMAT_XRGB2101010:
2128 case DRM_FORMAT_ARGB2101010:
2129 dspcntr |= DISPPLANE_BGRX101010;
2130 break;
2131 case DRM_FORMAT_XBGR2101010:
2132 case DRM_FORMAT_ABGR2101010:
2133 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2134 break;
2135 default:
baba133a 2136 BUG();
81255565 2137 }
57779d06 2138
a6c45cf0 2139 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2140 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2141 dspcntr |= DISPPLANE_TILED;
2142 else
2143 dspcntr &= ~DISPPLANE_TILED;
2144 }
2145
5eddb70b 2146 I915_WRITE(reg, dspcntr);
81255565 2147
e506a0c6 2148 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2149
c2c75131
DV		 2150 if (INTEL_INFO(dev)->gen >= 4) {
2151 intel_crtc->dspaddr_offset =
bc752862
CW		 2152 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2153 fb->bits_per_pixel / 8,
2154 fb->pitches[0]);
c2c75131
DV		 2155 linear_offset -= intel_crtc->dspaddr_offset;
2156 } else {
e506a0c6 2157 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2158 }
e506a0c6
DV		 2159
2160 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2161 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2162 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2163 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2164 I915_MODIFY_DISPBASE(DSPSURF(plane),
2165 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2166 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2167 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2168 } else
e506a0c6 2169 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2170 POSTING_READ(reg);
81255565 2171
17638cd6
JB		 2172 return 0;
2173}
2174
2175static int ironlake_update_plane(struct drm_crtc *crtc,
2176 struct drm_framebuffer *fb, int x, int y)
2177{
2178 struct drm_device *dev = crtc->dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2181 struct intel_framebuffer *intel_fb;
2182 struct drm_i915_gem_object *obj;
2183 int plane = intel_crtc->plane;
e506a0c6 2184 unsigned long linear_offset;
17638cd6
JB		 2185 u32 dspcntr;
2186 u32 reg;
2187
2188 switch (plane) {
2189 case 0:
2190 case 1:
27f8227b 2191 case 2:
17638cd6
JB		 2192 break;
2193 default:
2194 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2195 return -EINVAL;
2196 }
2197
2198 intel_fb = to_intel_framebuffer(fb);
2199 obj = intel_fb->obj;
2200
2201 reg = DSPCNTR(plane);
2202 dspcntr = I915_READ(reg);
2203 /* Mask out pixel format bits in case we change it */
2204 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2205 switch (fb->pixel_format) {
2206 case DRM_FORMAT_C8:
17638cd6
JB		 2207 dspcntr |= DISPPLANE_8BPP;
2208 break;
57779d06
VS		 2209 case DRM_FORMAT_RGB565:
2210 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2211 break;
57779d06
VS		 2212 case DRM_FORMAT_XRGB8888:
2213 case DRM_FORMAT_ARGB8888:
2214 dspcntr |= DISPPLANE_BGRX888;
2215 break;
2216 case DRM_FORMAT_XBGR8888:
2217 case DRM_FORMAT_ABGR8888:
2218 dspcntr |= DISPPLANE_RGBX888;
2219 break;
2220 case DRM_FORMAT_XRGB2101010:
2221 case DRM_FORMAT_ARGB2101010:
2222 dspcntr |= DISPPLANE_BGRX101010;
2223 break;
2224 case DRM_FORMAT_XBGR2101010:
2225 case DRM_FORMAT_ABGR2101010:
2226 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2227 break;
2228 default:
baba133a 2229 BUG();
17638cd6
JB		 2230 }
2231
2232 if (obj->tiling_mode != I915_TILING_NONE)
2233 dspcntr |= DISPPLANE_TILED;
2234 else
2235 dspcntr &= ~DISPPLANE_TILED;
2236
2237 /* must disable */
2238 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2239
2240 I915_WRITE(reg, dspcntr);
2241
e506a0c6 2242 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2243 intel_crtc->dspaddr_offset =
bc752862
CW		 2244 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2245 fb->bits_per_pixel / 8,
2246 fb->pitches[0]);
c2c75131 2247 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2248
e506a0c6
DV		 2249 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2250 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2251 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2252 I915_MODIFY_DISPBASE(DSPSURF(plane),
2253 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2254 if (IS_HASWELL(dev)) {
2255 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2256 } else {
2257 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2258 I915_WRITE(DSPLINOFF(plane), linear_offset);
2259 }
17638cd6
JB		 2260 POSTING_READ(reg);
2261
2262 return 0;
2263}
2264
2265/* Assume fb object is pinned & idle & fenced and just update base pointers */
2266static int
2267intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2268 int x, int y, enum mode_set_atomic state)
2269{
2270 struct drm_device *dev = crtc->dev;
2271 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2272
6b8e6ed0
CW		 2273 if (dev_priv->display.disable_fbc)
2274 dev_priv->display.disable_fbc(dev);
3dec0095 2275 intel_increase_pllclock(crtc);
81255565 2276
6b8e6ed0 2277 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2278}
2279
96a02917
VS		 2280void intel_display_handle_reset(struct drm_device *dev)
2281{
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283 struct drm_crtc *crtc;
2284
2285 /*
2286 * Flips in the rings have been nuked by the reset,
2287 * so complete all pending flips so that user space
2288 * will get its events and not get stuck.
2289 *
2290 * Also update the base address of all primary
2291 * planes to the the last fb to make sure we're
2292 * showing the correct fb after a reset.
2293 *
2294 * Need to make two loops over the crtcs so that we
2295 * don't try to grab a crtc mutex before the
2296 * pending_flip_queue really got woken up.
2297 */
2298
2299 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2301 enum plane plane = intel_crtc->plane;
2302
2303 intel_prepare_page_flip(dev, plane);
2304 intel_finish_page_flip_plane(dev, plane);
2305 }
2306
2307 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309
2310 mutex_lock(&crtc->mutex);
2311 if (intel_crtc->active)
2312 dev_priv->display.update_plane(crtc, crtc->fb,
2313 crtc->x, crtc->y);
2314 mutex_unlock(&crtc->mutex);
2315 }
2316}
2317
14667a4b
CW		 2318static int
2319intel_finish_fb(struct drm_framebuffer *old_fb)
2320{
2321 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2322 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2323 bool was_interruptible = dev_priv->mm.interruptible;
2324 int ret;
2325
14667a4b
CW		 2326 /* Big Hammer, we also need to ensure that any pending
2327 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2328 * current scanout is retired before unpinning the old
2329 * framebuffer.
2330 *
2331 * This should only fail upon a hung GPU, in which case we
2332 * can safely continue.
2333 */
2334 dev_priv->mm.interruptible = false;
2335 ret = i915_gem_object_finish_gpu(obj);
2336 dev_priv->mm.interruptible = was_interruptible;
2337
2338 return ret;
2339}
2340
198598d0
VS		 2341static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2342{
2343 struct drm_device *dev = crtc->dev;
2344 struct drm_i915_master_private *master_priv;
2345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2346
2347 if (!dev->primary->master)
2348 return;
2349
2350 master_priv = dev->primary->master->driver_priv;
2351 if (!master_priv->sarea_priv)
2352 return;
2353
2354 switch (intel_crtc->pipe) {
2355 case 0:
2356 master_priv->sarea_priv->pipeA_x = x;
2357 master_priv->sarea_priv->pipeA_y = y;
2358 break;
2359 case 1:
2360 master_priv->sarea_priv->pipeB_x = x;
2361 master_priv->sarea_priv->pipeB_y = y;
2362 break;
2363 default:
2364 break;
2365 }
2366}
2367
5c3b82e2 2368static int
3c4fdcfb 2369intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2370 struct drm_framebuffer *fb)
79e53945
JB		 2371{
2372 struct drm_device *dev = crtc->dev;
6b8e6ed0 2373 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2375 struct drm_framebuffer *old_fb;
5c3b82e2 2376 int ret;
79e53945
JB		 2377
2378 /* no fb bound */
94352cf9 2379 if (!fb) {
a5071c2f 2380 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2381 return 0;
2382 }
2383
7eb552ae 2384 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
5826eca5
ED		 2385 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2386 intel_crtc->plane,
7eb552ae 2387 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2388 return -EINVAL;
79e53945
JB		 2389 }
2390
5c3b82e2 2391 mutex_lock(&dev->struct_mutex);
265db958 2392 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2393 to_intel_framebuffer(fb)->obj,
919926ae 2394 NULL);
5c3b82e2
CW		 2395 if (ret != 0) {
2396 mutex_unlock(&dev->struct_mutex);
a5071c2f 2397 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2398 return ret;
2399 }
79e53945 2400
94352cf9 2401 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2402 if (ret) {
94352cf9 2403 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2404 mutex_unlock(&dev->struct_mutex);
a5071c2f 2405 DRM_ERROR("failed to update base address\n");
4e6cfefc 2406 return ret;
79e53945 2407 }
3c4fdcfb 2408
94352cf9
DV		 2409 old_fb = crtc->fb;
2410 crtc->fb = fb;
6c4c86f5
DV		 2411 crtc->x = x;
2412 crtc->y = y;
94352cf9 2413
b7f1de28
CW		 2414 if (old_fb) {
2415 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2416 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2417 }
652c393a 2418
6b8e6ed0 2419 intel_update_fbc(dev);
5c3b82e2 2420 mutex_unlock(&dev->struct_mutex);
79e53945 2421
198598d0 2422 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2423
2424 return 0;
79e53945
JB		 2425}
2426
5e84e1a4
ZW		 2427static void intel_fdi_normal_train(struct drm_crtc *crtc)
2428{
2429 struct drm_device *dev = crtc->dev;
2430 struct drm_i915_private *dev_priv = dev->dev_private;
2431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2432 int pipe = intel_crtc->pipe;
2433 u32 reg, temp;
2434
2435 /* enable normal train */
2436 reg = FDI_TX_CTL(pipe);
2437 temp = I915_READ(reg);
61e499bf 2438 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2439 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2440 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2441 } else {
2442 temp &= ~FDI_LINK_TRAIN_NONE;
2443 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2444 }
5e84e1a4
ZW		 2445 I915_WRITE(reg, temp);
2446
2447 reg = FDI_RX_CTL(pipe);
2448 temp = I915_READ(reg);
2449 if (HAS_PCH_CPT(dev)) {
2450 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2451 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2452 } else {
2453 temp &= ~FDI_LINK_TRAIN_NONE;
2454 temp |= FDI_LINK_TRAIN_NONE;
2455 }
2456 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2457
2458 /* wait one idle pattern time */
2459 POSTING_READ(reg);
2460 udelay(1000);
357555c0
JB		 2461
2462 /* IVB wants error correction enabled */
2463 if (IS_IVYBRIDGE(dev))
2464 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2465 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2466}
2467
01a415fd
DV		 2468static void ivb_modeset_global_resources(struct drm_device *dev)
2469{
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *pipe_B_crtc =
2472 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2473 struct intel_crtc *pipe_C_crtc =
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2475 uint32_t temp;
2476
2477 /* When everything is off disable fdi C so that we could enable fdi B
2478 * with all lanes. XXX: This misses the case where a pipe is not using
2479 * any pch resources and so doesn't need any fdi lanes. */
2480 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2481 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2482 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2483
2484 temp = I915_READ(SOUTH_CHICKEN1);
2485 temp &= ~FDI_BC_BIFURCATION_SELECT;
2486 DRM_DEBUG_KMS("disabling fdi C rx\n");
2487 I915_WRITE(SOUTH_CHICKEN1, temp);
2488 }
2489}
2490
8db9d77b
ZW		 2491/* The FDI link training functions for ILK/Ibexpeak. */
2492static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2493{
2494 struct drm_device *dev = crtc->dev;
2495 struct drm_i915_private *dev_priv = dev->dev_private;
2496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2497 int pipe = intel_crtc->pipe;
0fc932b8 2498 int plane = intel_crtc->plane;
5eddb70b 2499 u32 reg, temp, tries;
8db9d77b 2500
0fc932b8
JB		 2501 /* FDI needs bits from pipe & plane first */
2502 assert_pipe_enabled(dev_priv, pipe);
2503 assert_plane_enabled(dev_priv, plane);
2504
e1a44743
AJ		 2505 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2506 for train result */
5eddb70b
CW		 2507 reg = FDI_RX_IMR(pipe);
2508 temp = I915_READ(reg);
e1a44743
AJ		 2509 temp &= ~FDI_RX_SYMBOL_LOCK;
2510 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2511 I915_WRITE(reg, temp);
2512 I915_READ(reg);
e1a44743
AJ		 2513 udelay(150);
2514
8db9d77b 2515 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
77ffb597
AJ		 2518 temp &= ~(7 << 19);
2519 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2520 temp &= ~FDI_LINK_TRAIN_NONE;
2521 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2522 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2523
5eddb70b
CW		 2524 reg = FDI_RX_CTL(pipe);
2525 temp = I915_READ(reg);
8db9d77b
ZW		 2526 temp &= ~FDI_LINK_TRAIN_NONE;
2527 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2528 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2529
2530 POSTING_READ(reg);
8db9d77b
ZW		 2531 udelay(150);
2532
5b2adf89 2533 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2534 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2535 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2536 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2537
5eddb70b 2538 reg = FDI_RX_IIR(pipe);
e1a44743 2539 for (tries = 0; tries < 5; tries++) {
5eddb70b 2540 temp = I915_READ(reg);
8db9d77b
ZW		 2541 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2542
2543 if ((temp & FDI_RX_BIT_LOCK)) {
2544 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2545 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2546 break;
2547 }
8db9d77b 2548 }
e1a44743 2549 if (tries == 5)
5eddb70b 2550 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2551
2552 /* Train 2 */
5eddb70b
CW		 2553 reg = FDI_TX_CTL(pipe);
2554 temp = I915_READ(reg);
8db9d77b
ZW		 2555 temp &= ~FDI_LINK_TRAIN_NONE;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2557 I915_WRITE(reg, temp);
8db9d77b 2558
5eddb70b
CW		 2559 reg = FDI_RX_CTL(pipe);
2560 temp = I915_READ(reg);
8db9d77b
ZW		 2561 temp &= ~FDI_LINK_TRAIN_NONE;
2562 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2563 I915_WRITE(reg, temp);
8db9d77b 2564
5eddb70b
CW		 2565 POSTING_READ(reg);
2566 udelay(150);
8db9d77b 2567
5eddb70b 2568 reg = FDI_RX_IIR(pipe);
e1a44743 2569 for (tries = 0; tries < 5; tries++) {
5eddb70b 2570 temp = I915_READ(reg);
8db9d77b
ZW		 2571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572
2573 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2574 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2575 DRM_DEBUG_KMS("FDI train 2 done.\n");
2576 break;
2577 }
8db9d77b 2578 }
e1a44743 2579 if (tries == 5)
5eddb70b 2580 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2581
2582 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2583
8db9d77b
ZW		 2584}
2585
0206e353 2586static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2587 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2588 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2589 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2590 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2591};
2592
2593/* The FDI link training functions for SNB/Cougarpoint. */
2594static void gen6_fdi_link_train(struct drm_crtc *crtc)
2595{
2596 struct drm_device *dev = crtc->dev;
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2599 int pipe = intel_crtc->pipe;
fa37d39e 2600 u32 reg, temp, i, retry;
8db9d77b 2601
e1a44743
AJ		 2602 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2603 for train result */
5eddb70b
CW		 2604 reg = FDI_RX_IMR(pipe);
2605 temp = I915_READ(reg);
e1a44743
AJ		 2606 temp &= ~FDI_RX_SYMBOL_LOCK;
2607 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2608 I915_WRITE(reg, temp);
2609
2610 POSTING_READ(reg);
e1a44743
AJ		 2611 udelay(150);
2612
8db9d77b 2613 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2614 reg = FDI_TX_CTL(pipe);
2615 temp = I915_READ(reg);
77ffb597
AJ		 2616 temp &= ~(7 << 19);
2617 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2618 temp &= ~FDI_LINK_TRAIN_NONE;
2619 temp |= FDI_LINK_TRAIN_PATTERN_1;
2620 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2621 /* SNB-B */
2622 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2623 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2624
d74cf324
DV		 2625 I915_WRITE(FDI_RX_MISC(pipe),
2626 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2627
5eddb70b
CW		 2628 reg = FDI_RX_CTL(pipe);
2629 temp = I915_READ(reg);
8db9d77b
ZW		 2630 if (HAS_PCH_CPT(dev)) {
2631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2633 } else {
2634 temp &= ~FDI_LINK_TRAIN_NONE;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1;
2636 }
5eddb70b
CW		 2637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639 POSTING_READ(reg);
8db9d77b
ZW		 2640 udelay(150);
2641
0206e353 2642 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
8db9d77b
ZW		 2645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
8db9d77b
ZW		 2650 udelay(500);
2651
fa37d39e
SP		 2652 for (retry = 0; retry < 5; retry++) {
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656 if (temp & FDI_RX_BIT_LOCK) {
2657 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2658 DRM_DEBUG_KMS("FDI train 1 done.\n");
2659 break;
2660 }
2661 udelay(50);
8db9d77b 2662 }
fa37d39e
SP		 2663 if (retry < 5)
2664 break;
8db9d77b
ZW		 2665 }
2666 if (i == 4)
5eddb70b 2667 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2668
2669 /* Train 2 */
5eddb70b
CW		 2670 reg = FDI_TX_CTL(pipe);
2671 temp = I915_READ(reg);
8db9d77b
ZW		 2672 temp &= ~FDI_LINK_TRAIN_NONE;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2;
2674 if (IS_GEN6(dev)) {
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 /* SNB-B */
2677 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2678 }
5eddb70b 2679 I915_WRITE(reg, temp);
8db9d77b 2680
5eddb70b
CW		 2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
8db9d77b
ZW		 2683 if (HAS_PCH_CPT(dev)) {
2684 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2685 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2686 } else {
2687 temp &= ~FDI_LINK_TRAIN_NONE;
2688 temp |= FDI_LINK_TRAIN_PATTERN_2;
2689 }
5eddb70b
CW		 2690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
8db9d77b
ZW		 2693 udelay(150);
2694
0206e353 2695 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
8db9d77b
ZW		 2698 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2700 I915_WRITE(reg, temp);
2701
2702 POSTING_READ(reg);
8db9d77b
ZW		 2703 udelay(500);
2704
fa37d39e
SP		 2705 for (retry = 0; retry < 5; retry++) {
2706 reg = FDI_RX_IIR(pipe);
2707 temp = I915_READ(reg);
2708 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709 if (temp & FDI_RX_SYMBOL_LOCK) {
2710 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711 DRM_DEBUG_KMS("FDI train 2 done.\n");
2712 break;
2713 }
2714 udelay(50);
8db9d77b 2715 }
fa37d39e
SP		 2716 if (retry < 5)
2717 break;
8db9d77b
ZW		 2718 }
2719 if (i == 4)
5eddb70b 2720 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2721
2722 DRM_DEBUG_KMS("FDI train done.\n");
2723}
2724
357555c0
JB		 2725/* Manual link training for Ivy Bridge A0 parts */
2726static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2727{
2728 struct drm_device *dev = crtc->dev;
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731 int pipe = intel_crtc->pipe;
2732 u32 reg, temp, i;
2733
2734 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2735 for train result */
2736 reg = FDI_RX_IMR(pipe);
2737 temp = I915_READ(reg);
2738 temp &= ~FDI_RX_SYMBOL_LOCK;
2739 temp &= ~FDI_RX_BIT_LOCK;
2740 I915_WRITE(reg, temp);
2741
2742 POSTING_READ(reg);
2743 udelay(150);
2744
01a415fd
DV		 2745 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2746 I915_READ(FDI_RX_IIR(pipe)));
2747
357555c0
JB		 2748 /* enable CPU FDI TX and PCH FDI RX */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~(7 << 19);
2752 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2753 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2754 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2755 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2756 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2757 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2758 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2759
d74cf324
DV		 2760 I915_WRITE(FDI_RX_MISC(pipe),
2761 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2762
357555c0
JB		 2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~FDI_LINK_TRAIN_AUTO;
2766 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2767 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2768 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2769 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2770
2771 POSTING_READ(reg);
2772 udelay(150);
2773
0206e353 2774 for (i = 0; i < 4; i++) {
357555c0
JB		 2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2778 temp |= snb_b_fdi_train_param[i];
2779 I915_WRITE(reg, temp);
2780
2781 POSTING_READ(reg);
2782 udelay(500);
2783
2784 reg = FDI_RX_IIR(pipe);
2785 temp = I915_READ(reg);
2786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2787
2788 if (temp & FDI_RX_BIT_LOCK ||
2789 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2790 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2791 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2792 break;
2793 }
2794 }
2795 if (i == 4)
2796 DRM_ERROR("FDI train 1 fail!\n");
2797
2798 /* Train 2 */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2802 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2803 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2804 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2805 I915_WRITE(reg, temp);
2806
2807 reg = FDI_RX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2811 I915_WRITE(reg, temp);
2812
2813 POSTING_READ(reg);
2814 udelay(150);
2815
0206e353 2816 for (i = 0; i < 4; i++) {
357555c0
JB		 2817 reg = FDI_TX_CTL(pipe);
2818 temp = I915_READ(reg);
2819 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2820 temp |= snb_b_fdi_train_param[i];
2821 I915_WRITE(reg, temp);
2822
2823 POSTING_READ(reg);
2824 udelay(500);
2825
2826 reg = FDI_RX_IIR(pipe);
2827 temp = I915_READ(reg);
2828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2829
2830 if (temp & FDI_RX_SYMBOL_LOCK) {
2831 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2832 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2833 break;
2834 }
2835 }
2836 if (i == 4)
2837 DRM_ERROR("FDI train 2 fail!\n");
2838
2839 DRM_DEBUG_KMS("FDI train done.\n");
2840}
2841
88cefb6c 2842static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2843{
88cefb6c 2844 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2845 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2846 int pipe = intel_crtc->pipe;
5eddb70b 2847 u32 reg, temp;
79e53945 2848
c64e311e 2849
c98e9dcf 2850 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2851 reg = FDI_RX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2854 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2855 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2856 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2857
2858 POSTING_READ(reg);
c98e9dcf
JB		 2859 udelay(200);
2860
2861 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2862 temp = I915_READ(reg);
2863 I915_WRITE(reg, temp | FDI_PCDCLK);
2864
2865 POSTING_READ(reg);
c98e9dcf
JB		 2866 udelay(200);
2867
20749730
PZ		 2868 /* Enable CPU FDI TX PLL, always on for Ironlake */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2872 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2873
20749730
PZ		 2874 POSTING_READ(reg);
2875 udelay(100);
6be4a607 2876 }
0e23b99d
JB		 2877}
2878
88cefb6c
DV		 2879static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2880{
2881 struct drm_device *dev = intel_crtc->base.dev;
2882 struct drm_i915_private *dev_priv = dev->dev_private;
2883 int pipe = intel_crtc->pipe;
2884 u32 reg, temp;
2885
2886 /* Switch from PCDclk to Rawclk */
2887 reg = FDI_RX_CTL(pipe);
2888 temp = I915_READ(reg);
2889 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2890
2891 /* Disable CPU FDI TX PLL */
2892 reg = FDI_TX_CTL(pipe);
2893 temp = I915_READ(reg);
2894 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2895
2896 POSTING_READ(reg);
2897 udelay(100);
2898
2899 reg = FDI_RX_CTL(pipe);
2900 temp = I915_READ(reg);
2901 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2902
2903 /* Wait for the clocks to turn off. */
2904 POSTING_READ(reg);
2905 udelay(100);
2906}
2907
0fc932b8
JB		 2908static void ironlake_fdi_disable(struct drm_crtc *crtc)
2909{
2910 struct drm_device *dev = crtc->dev;
2911 struct drm_i915_private *dev_priv = dev->dev_private;
2912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2913 int pipe = intel_crtc->pipe;
2914 u32 reg, temp;
2915
2916 /* disable CPU FDI tx and PCH FDI rx */
2917 reg = FDI_TX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2920 POSTING_READ(reg);
2921
2922 reg = FDI_RX_CTL(pipe);
2923 temp = I915_READ(reg);
2924 temp &= ~(0x7 << 16);
dfd07d72 2925 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2926 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2927
2928 POSTING_READ(reg);
2929 udelay(100);
2930
2931 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2932 if (HAS_PCH_IBX(dev)) {
2933 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2934 }
0fc932b8
JB		 2935
2936 /* still set train pattern 1 */
2937 reg = FDI_TX_CTL(pipe);
2938 temp = I915_READ(reg);
2939 temp &= ~FDI_LINK_TRAIN_NONE;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1;
2941 I915_WRITE(reg, temp);
2942
2943 reg = FDI_RX_CTL(pipe);
2944 temp = I915_READ(reg);
2945 if (HAS_PCH_CPT(dev)) {
2946 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2947 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2948 } else {
2949 temp &= ~FDI_LINK_TRAIN_NONE;
2950 temp |= FDI_LINK_TRAIN_PATTERN_1;
2951 }
2952 /* BPC in FDI rx is consistent with that in PIPECONF */
2953 temp &= ~(0x07 << 16);
dfd07d72 2954 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2955 I915_WRITE(reg, temp);
2956
2957 POSTING_READ(reg);
2958 udelay(100);
2959}
2960
5bb61643
CW		 2961static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2962{
2963 struct drm_device *dev = crtc->dev;
2964 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2966 unsigned long flags;
2967 bool pending;
2968
10d83730
VS		 2969 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2970 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2971 return false;
2972
2973 spin_lock_irqsave(&dev->event_lock, flags);
2974 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2975 spin_unlock_irqrestore(&dev->event_lock, flags);
2976
2977 return pending;
2978}
2979
e6c3a2a6
CW		 2980static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2981{
0f91128d 2982 struct drm_device *dev = crtc->dev;
5bb61643 2983 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2984
2985 if (crtc->fb == NULL)
2986 return;
2987
2c10d571
DV		 2988 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2989
5bb61643
CW		 2990 wait_event(dev_priv->pending_flip_queue,
2991 !intel_crtc_has_pending_flip(crtc));
2992
0f91128d
CW		 2993 mutex_lock(&dev->struct_mutex);
2994 intel_finish_fb(crtc->fb);
2995 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2996}
2997
e615efe4
ED		 2998/* Program iCLKIP clock to the desired frequency */
2999static void lpt_program_iclkip(struct drm_crtc *crtc)
3000{
3001 struct drm_device *dev = crtc->dev;
3002 struct drm_i915_private *dev_priv = dev->dev_private;
3003 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3004 u32 temp;
3005
09153000
DV		 3006 mutex_lock(&dev_priv->dpio_lock);
3007
e615efe4
ED		 3008 /* It is necessary to ungate the pixclk gate prior to programming
3009 * the divisors, and gate it back when it is done.
3010 */
3011 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3012
3013 /* Disable SSCCTL */
3014 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3015 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3016 SBI_SSCCTL_DISABLE,
3017 SBI_ICLK);
e615efe4
ED		 3018
3019 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3020 if (crtc->mode.clock == 20000) {
3021 auxdiv = 1;
3022 divsel = 0x41;
3023 phaseinc = 0x20;
3024 } else {
3025 /* The iCLK virtual clock root frequency is in MHz,
3026 * but the crtc->mode.clock in in KHz. To get the divisors,
3027 * it is necessary to divide one by another, so we
3028 * convert the virtual clock precision to KHz here for higher
3029 * precision.
3030 */
3031 u32 iclk_virtual_root_freq = 172800 * 1000;
3032 u32 iclk_pi_range = 64;
3033 u32 desired_divisor, msb_divisor_value, pi_value;
3034
3035 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3036 msb_divisor_value = desired_divisor / iclk_pi_range;
3037 pi_value = desired_divisor % iclk_pi_range;
3038
3039 auxdiv = 0;
3040 divsel = msb_divisor_value - 2;
3041 phaseinc = pi_value;
3042 }
3043
3044 /* This should not happen with any sane values */
3045 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3046 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3048 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3049
3050 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3051 crtc->mode.clock,
3052 auxdiv,
3053 divsel,
3054 phasedir,
3055 phaseinc);
3056
3057 /* Program SSCDIVINTPHASE6 */
988d6ee8 3058 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3059 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3060 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3061 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3062 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3063 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3064 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3065 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3066
3067 /* Program SSCAUXDIV */
988d6ee8 3068 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3069 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3070 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3071 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3072
3073 /* Enable modulator and associated divider */
988d6ee8 3074 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3075 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3076 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3077
3078 /* Wait for initialization time */
3079 udelay(24);
3080
3081 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3082
3083 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3084}
3085
f67a559d
JB		 3086/*
3087 * Enable PCH resources required for PCH ports:
3088 * - PCH PLLs
3089 * - FDI training & RX/TX
3090 * - update transcoder timings
3091 * - DP transcoding bits
3092 * - transcoder
3093 */
3094static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3095{
3096 struct drm_device *dev = crtc->dev;
3097 struct drm_i915_private *dev_priv = dev->dev_private;
3098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3099 int pipe = intel_crtc->pipe;
ee7b9f93 3100 u32 reg, temp;
2c07245f 3101
e7e164db
CW		 3102 assert_transcoder_disabled(dev_priv, pipe);
3103
cd986abb
DV		 3104 /* Write the TU size bits before fdi link training, so that error
3105 * detection works. */
3106 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3107 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3108
c98e9dcf 3109 /* For PCH output, training FDI link */
674cf967 3110 dev_priv->display.fdi_link_train(crtc);
2c07245f 3111
572deb37
DV		 3112 /* XXX: pch pll's can be enabled any time before we enable the PCH
3113 * transcoder, and we actually should do this to not upset any PCH
3114 * transcoder that already use the clock when we share it.
3115 *
3116 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3117 * unconditionally resets the pll - we need that to have the right LVDS
3118 * enable sequence. */
b6b4e185 3119 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3120
303b81e0 3121 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3122 u32 sel;
4b645f14 3123
c98e9dcf 3124 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3125 switch (pipe) {
3126 default:
3127 case 0:
3128 temp |= TRANSA_DPLL_ENABLE;
3129 sel = TRANSA_DPLLB_SEL;
3130 break;
3131 case 1:
3132 temp |= TRANSB_DPLL_ENABLE;
3133 sel = TRANSB_DPLLB_SEL;
3134 break;
3135 case 2:
3136 temp |= TRANSC_DPLL_ENABLE;
3137 sel = TRANSC_DPLLB_SEL;
3138 break;
d64311ab 3139 }
ee7b9f93
JB		 3140 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3141 temp |= sel;
3142 else
3143 temp &= ~sel;
c98e9dcf 3144 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3145 }
5eddb70b 3146
d9b6cb56
JB		 3147 /* set transcoder timing, panel must allow it */
3148 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3149 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3150 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3151 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3152
5eddb70b
CW		 3153 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3154 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3155 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3156 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3157
303b81e0 3158 intel_fdi_normal_train(crtc);
5e84e1a4 3159
c98e9dcf
JB		 3160 /* For PCH DP, enable TRANS_DP_CTL */
3161 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3162 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3163 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3164 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3165 reg = TRANS_DP_CTL(pipe);
3166 temp = I915_READ(reg);
3167 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3168 TRANS_DP_SYNC_MASK |
3169 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3170 temp |= (TRANS_DP_OUTPUT_ENABLE |
3171 TRANS_DP_ENH_FRAMING);
9325c9f0 3172 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3173
3174 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3175 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3176 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3177 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3178
3179 switch (intel_trans_dp_port_sel(crtc)) {
3180 case PCH_DP_B:
5eddb70b 3181 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3182 break;
3183 case PCH_DP_C:
5eddb70b 3184 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3185 break;
3186 case PCH_DP_D:
5eddb70b 3187 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3188 break;
3189 default:
e95d41e1 3190 BUG();
32f9d658 3191 }
2c07245f 3192
5eddb70b 3193 I915_WRITE(reg, temp);
6be4a607 3194 }
b52eb4dc 3195
b8a4f404 3196 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3197}
3198
1507e5bd
PZ		 3199static void lpt_pch_enable(struct drm_crtc *crtc)
3200{
3201 struct drm_device *dev = crtc->dev;
3202 struct drm_i915_private *dev_priv = dev->dev_private;
3203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3204 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3205
daed2dbb 3206 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3207
8c52b5e8 3208 lpt_program_iclkip(crtc);
1507e5bd 3209
0540e488 3210 /* Set transcoder timing. */
daed2dbb
PZ		 3211 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3212 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3213 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3214
daed2dbb
PZ		 3215 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3216 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3217 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3218 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3219
937bb610 3220 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3221}
3222
ee7b9f93
JB		 3223static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3224{
3225 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3226
3227 if (pll == NULL)
3228 return;
3229
3230 if (pll->refcount == 0) {
3231 WARN(1, "bad PCH PLL refcount\n");
3232 return;
3233 }
3234
3235 --pll->refcount;
3236 intel_crtc->pch_pll = NULL;
3237}
3238
3239static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3240{
3241 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3242 struct intel_pch_pll *pll;
3243 int i;
3244
3245 pll = intel_crtc->pch_pll;
3246 if (pll) {
3247 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3248 intel_crtc->base.base.id, pll->pll_reg);
3249 goto prepare;
3250 }
3251
98b6bd99
DV		 3252 if (HAS_PCH_IBX(dev_priv->dev)) {
3253 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3254 i = intel_crtc->pipe;
3255 pll = &dev_priv->pch_plls[i];
3256
3257 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3258 intel_crtc->base.base.id, pll->pll_reg);
3259
3260 goto found;
3261 }
3262
ee7b9f93
JB		 3263 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3264 pll = &dev_priv->pch_plls[i];
3265
3266 /* Only want to check enabled timings first */
3267 if (pll->refcount == 0)
3268 continue;
3269
3270 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3271 fp == I915_READ(pll->fp0_reg)) {
3272 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3273 intel_crtc->base.base.id,
3274 pll->pll_reg, pll->refcount, pll->active);
3275
3276 goto found;
3277 }
3278 }
3279
3280 /* Ok no matching timings, maybe there's a free one? */
3281 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3282 pll = &dev_priv->pch_plls[i];
3283 if (pll->refcount == 0) {
3284 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3285 intel_crtc->base.base.id, pll->pll_reg);
3286 goto found;
3287 }
3288 }
3289
3290 return NULL;
3291
3292found:
3293 intel_crtc->pch_pll = pll;
3294 pll->refcount++;
3295 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3296prepare: /* separate function? */
3297 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3298
e04c7350
CW		 3299 /* Wait for the clocks to stabilize before rewriting the regs */
3300 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3301 POSTING_READ(pll->pll_reg);
3302 udelay(150);
e04c7350
CW		 3303
3304 I915_WRITE(pll->fp0_reg, fp);
3305 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3306 pll->on = false;
3307 return pll;
3308}
3309
d4270e57
JB		 3310void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3311{
3312 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3313 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3314 u32 temp;
3315
3316 temp = I915_READ(dslreg);
3317 udelay(500);
3318 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3319 if (wait_for(I915_READ(dslreg) != temp, 5))
3320 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3321 }
3322}
3323
f67a559d
JB		 3324static void ironlake_crtc_enable(struct drm_crtc *crtc)
3325{
3326 struct drm_device *dev = crtc->dev;
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3329 struct intel_encoder *encoder;
f67a559d
JB		 3330 int pipe = intel_crtc->pipe;
3331 int plane = intel_crtc->plane;
3332 u32 temp;
f67a559d 3333
08a48469
DV		 3334 WARN_ON(!crtc->enabled);
3335
f67a559d
JB		 3336 if (intel_crtc->active)
3337 return;
3338
3339 intel_crtc->active = true;
3340 intel_update_watermarks(dev);
3341
3342 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3343 temp = I915_READ(PCH_LVDS);
3344 if ((temp & LVDS_PORT_EN) == 0)
3345 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3346 }
3347
f67a559d 3348
5bfe2ac0 3349 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3350 /* Note: FDI PLL enabling _must_ be done before we enable the
3351 * cpu pipes, hence this is separate from all the other fdi/pch
3352 * enabling. */
88cefb6c 3353 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3354 } else {
3355 assert_fdi_tx_disabled(dev_priv, pipe);
3356 assert_fdi_rx_disabled(dev_priv, pipe);
3357 }
f67a559d 3358
bf49ec8c
DV		 3359 for_each_encoder_on_crtc(dev, crtc, encoder)
3360 if (encoder->pre_enable)
3361 encoder->pre_enable(encoder);
f67a559d
JB		 3362
3363 /* Enable panel fitting for LVDS */
3364 if (dev_priv->pch_pf_size &&
547dc041
JN		 3365 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3366 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3367 /* Force use of hard-coded filter coefficients
3368 * as some pre-programmed values are broken,
3369 * e.g. x201.
3370 */
13888d78
PZ		 3371 if (IS_IVYBRIDGE(dev))
3372 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3373 PF_PIPE_SEL_IVB(pipe));
3374 else
3375 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3376 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3377 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3378 }
3379
9c54c0dd
JB		 3380 /*
3381 * On ILK+ LUT must be loaded before the pipe is running but with
3382 * clocks enabled
3383 */
3384 intel_crtc_load_lut(crtc);
3385
5bfe2ac0
DV		 3386 intel_enable_pipe(dev_priv, pipe,
3387 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3388 intel_enable_plane(dev_priv, plane, pipe);
3389
5bfe2ac0 3390 if (intel_crtc->config.has_pch_encoder)
f67a559d 3391 ironlake_pch_enable(crtc);
c98e9dcf 3392
d1ebd816 3393 mutex_lock(&dev->struct_mutex);
bed4a673 3394 intel_update_fbc(dev);
d1ebd816
BW		 3395 mutex_unlock(&dev->struct_mutex);
3396
6b383a7f 3397 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3398
fa5c73b1
DV		 3399 for_each_encoder_on_crtc(dev, crtc, encoder)
3400 encoder->enable(encoder);
61b77ddd
DV		 3401
3402 if (HAS_PCH_CPT(dev))
3403 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3404
3405 /*
3406 * There seems to be a race in PCH platform hw (at least on some
3407 * outputs) where an enabled pipe still completes any pageflip right
3408 * away (as if the pipe is off) instead of waiting for vblank. As soon
3409 * as the first vblank happend, everything works as expected. Hence just
3410 * wait for one vblank before returning to avoid strange things
3411 * happening.
3412 */
3413 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3414}
3415
4f771f10
PZ		 3416static void haswell_crtc_enable(struct drm_crtc *crtc)
3417{
3418 struct drm_device *dev = crtc->dev;
3419 struct drm_i915_private *dev_priv = dev->dev_private;
3420 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3421 struct intel_encoder *encoder;
3422 int pipe = intel_crtc->pipe;
3423 int plane = intel_crtc->plane;
4f771f10
PZ		 3424
3425 WARN_ON(!crtc->enabled);
3426
3427 if (intel_crtc->active)
3428 return;
3429
3430 intel_crtc->active = true;
3431 intel_update_watermarks(dev);
3432
5bfe2ac0 3433 if (intel_crtc->config.has_pch_encoder)
04945641 3434 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3435
3436 for_each_encoder_on_crtc(dev, crtc, encoder)
3437 if (encoder->pre_enable)
3438 encoder->pre_enable(encoder);
3439
1f544388 3440 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3441
1f544388 3442 /* Enable panel fitting for eDP */
547dc041
JN		 3443 if (dev_priv->pch_pf_size &&
3444 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3445 /* Force use of hard-coded filter coefficients
3446 * as some pre-programmed values are broken,
3447 * e.g. x201.
3448 */
54075a7d
PZ		 3449 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3450 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3451 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3452 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3453 }
3454
3455 /*
3456 * On ILK+ LUT must be loaded before the pipe is running but with
3457 * clocks enabled
3458 */
3459 intel_crtc_load_lut(crtc);
3460
1f544388 3461 intel_ddi_set_pipe_settings(crtc);
8228c251 3462 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3463
5bfe2ac0
DV		 3464 intel_enable_pipe(dev_priv, pipe,
3465 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3466 intel_enable_plane(dev_priv, plane, pipe);
3467
5bfe2ac0 3468 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3469 lpt_pch_enable(crtc);
4f771f10
PZ		 3470
3471 mutex_lock(&dev->struct_mutex);
3472 intel_update_fbc(dev);
3473 mutex_unlock(&dev->struct_mutex);
3474
3475 intel_crtc_update_cursor(crtc, true);
3476
3477 for_each_encoder_on_crtc(dev, crtc, encoder)
3478 encoder->enable(encoder);
3479
4f771f10
PZ		 3480 /*
3481 * There seems to be a race in PCH platform hw (at least on some
3482 * outputs) where an enabled pipe still completes any pageflip right
3483 * away (as if the pipe is off) instead of waiting for vblank. As soon
3484 * as the first vblank happend, everything works as expected. Hence just
3485 * wait for one vblank before returning to avoid strange things
3486 * happening.
3487 */
3488 intel_wait_for_vblank(dev, intel_crtc->pipe);
3489}
3490
6be4a607
JB		 3491static void ironlake_crtc_disable(struct drm_crtc *crtc)
3492{
3493 struct drm_device *dev = crtc->dev;
3494 struct drm_i915_private *dev_priv = dev->dev_private;
3495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3496 struct intel_encoder *encoder;
6be4a607
JB		 3497 int pipe = intel_crtc->pipe;
3498 int plane = intel_crtc->plane;
5eddb70b 3499 u32 reg, temp;
b52eb4dc 3500
ef9c3aee 3501
f7abfe8b
CW		 3502 if (!intel_crtc->active)
3503 return;
3504
ea9d758d
DV		 3505 for_each_encoder_on_crtc(dev, crtc, encoder)
3506 encoder->disable(encoder);
3507
e6c3a2a6 3508 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3509 drm_vblank_off(dev, pipe);
6b383a7f 3510 intel_crtc_update_cursor(crtc, false);
5eddb70b 3511
b24e7179 3512 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3513
973d04f9
CW		 3514 if (dev_priv->cfb_plane == plane)
3515 intel_disable_fbc(dev);
2c07245f 3516
b24e7179 3517 intel_disable_pipe(dev_priv, pipe);
32f9d658 3518
6be4a607 3519 /* Disable PF */
9db4a9c7
JB		 3520 I915_WRITE(PF_CTL(pipe), 0);
3521 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3522
bf49ec8c
DV		 3523 for_each_encoder_on_crtc(dev, crtc, encoder)
3524 if (encoder->post_disable)
3525 encoder->post_disable(encoder);
2c07245f 3526
0fc932b8 3527 ironlake_fdi_disable(crtc);
249c0e64 3528
b8a4f404 3529 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3530
6be4a607
JB		 3531 if (HAS_PCH_CPT(dev)) {
3532 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3533 reg = TRANS_DP_CTL(pipe);
3534 temp = I915_READ(reg);
3535 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3536 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3537 I915_WRITE(reg, temp);
6be4a607
JB		 3538
3539 /* disable DPLL_SEL */
3540 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3541 switch (pipe) {
3542 case 0:
d64311ab 3543 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3544 break;
3545 case 1:
6be4a607 3546 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3547 break;
3548 case 2:
4b645f14 3549 /* C shares PLL A or B */
d64311ab 3550 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3551 break;
3552 default:
3553 BUG(); /* wtf */
3554 }
6be4a607 3555 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3556 }
e3421a18 3557
6be4a607 3558 /* disable PCH DPLL */
ee7b9f93 3559 intel_disable_pch_pll(intel_crtc);
8db9d77b 3560
88cefb6c 3561 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3562
f7abfe8b 3563 intel_crtc->active = false;
6b383a7f 3564 intel_update_watermarks(dev);
d1ebd816
BW		 3565
3566 mutex_lock(&dev->struct_mutex);
6b383a7f 3567 intel_update_fbc(dev);
d1ebd816 3568 mutex_unlock(&dev->struct_mutex);
6be4a607 3569}
1b3c7a47 3570
4f771f10 3571static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3572{
4f771f10
PZ		 3573 struct drm_device *dev = crtc->dev;
3574 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3576 struct intel_encoder *encoder;
3577 int pipe = intel_crtc->pipe;
3578 int plane = intel_crtc->plane;
ad80a810 3579 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee7b9f93 3580
4f771f10
PZ		 3581 if (!intel_crtc->active)
3582 return;
3583
3584 for_each_encoder_on_crtc(dev, crtc, encoder)
3585 encoder->disable(encoder);
3586
3587 intel_crtc_wait_for_pending_flips(crtc);
3588 drm_vblank_off(dev, pipe);
3589 intel_crtc_update_cursor(crtc, false);
3590
3591 intel_disable_plane(dev_priv, plane, pipe);
3592
3593 if (dev_priv->cfb_plane == plane)
3594 intel_disable_fbc(dev);
3595
3596 intel_disable_pipe(dev_priv, pipe);
3597
ad80a810 3598 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3599
3600 /* Disable PF */
3601 I915_WRITE(PF_CTL(pipe), 0);
3602 I915_WRITE(PF_WIN_SZ(pipe), 0);
3603
1f544388 3604 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3605
3606 for_each_encoder_on_crtc(dev, crtc, encoder)
3607 if (encoder->post_disable)
3608 encoder->post_disable(encoder);
3609
88adfff1 3610 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3611 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3612 intel_ddi_fdi_disable(crtc);
83616634 3613 }
4f771f10
PZ		 3614
3615 intel_crtc->active = false;
3616 intel_update_watermarks(dev);
3617
3618 mutex_lock(&dev->struct_mutex);
3619 intel_update_fbc(dev);
3620 mutex_unlock(&dev->struct_mutex);
3621}
3622
ee7b9f93
JB		 3623static void ironlake_crtc_off(struct drm_crtc *crtc)
3624{
3625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3626 intel_put_pch_pll(intel_crtc);
3627}
3628
6441ab5f
PZ		 3629static void haswell_crtc_off(struct drm_crtc *crtc)
3630{
a5c961d1
PZ		 3631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3632
3633 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3634 * start using it. */
1a240d4d 3635 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3636
6441ab5f
PZ		 3637 intel_ddi_put_crtc_pll(crtc);
3638}
3639
02e792fb
DV		 3640static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3641{
02e792fb 3642 if (!enable && intel_crtc->overlay) {
23f09ce3 3643 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3644 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3645
23f09ce3 3646 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3647 dev_priv->mm.interruptible = false;
3648 (void) intel_overlay_switch_off(intel_crtc->overlay);
3649 dev_priv->mm.interruptible = true;
23f09ce3 3650 mutex_unlock(&dev->struct_mutex);
02e792fb 3651 }
02e792fb 3652
5dcdbcb0
CW		 3653 /* Let userspace switch the overlay on again. In most cases userspace
3654 * has to recompute where to put it anyway.
3655 */
02e792fb
DV		 3656}
3657
61bc95c1
EE		 3658/**
3659 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3660 * cursor plane briefly if not already running after enabling the display
3661 * plane.
3662 * This workaround avoids occasional blank screens when self refresh is
3663 * enabled.
3664 */
3665static void
3666g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3667{
3668 u32 cntl = I915_READ(CURCNTR(pipe));
3669
3670 if ((cntl & CURSOR_MODE) == 0) {
3671 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3672
3673 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3674 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3675 intel_wait_for_vblank(dev_priv->dev, pipe);
3676 I915_WRITE(CURCNTR(pipe), cntl);
3677 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3678 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3679 }
3680}
3681
0b8765c6 3682static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3683{
3684 struct drm_device *dev = crtc->dev;
79e53945
JB		 3685 struct drm_i915_private *dev_priv = dev->dev_private;
3686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3687 struct intel_encoder *encoder;
79e53945 3688 int pipe = intel_crtc->pipe;
80824003 3689 int plane = intel_crtc->plane;
79e53945 3690
08a48469
DV		 3691 WARN_ON(!crtc->enabled);
3692
f7abfe8b
CW		 3693 if (intel_crtc->active)
3694 return;
3695
3696 intel_crtc->active = true;
6b383a7f
CW		 3697 intel_update_watermarks(dev);
3698
63d7bbe9 3699 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3700
3701 for_each_encoder_on_crtc(dev, crtc, encoder)
3702 if (encoder->pre_enable)
3703 encoder->pre_enable(encoder);
3704
040484af 3705 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3706 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3707 if (IS_G4X(dev))
3708 g4x_fixup_plane(dev_priv, pipe);
79e53945 3709
0b8765c6 3710 intel_crtc_load_lut(crtc);
bed4a673 3711 intel_update_fbc(dev);
79e53945 3712
0b8765c6
JB		 3713 /* Give the overlay scaler a chance to enable if it's on this pipe */
3714 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3715 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3716
fa5c73b1
DV		 3717 for_each_encoder_on_crtc(dev, crtc, encoder)
3718 encoder->enable(encoder);
0b8765c6 3719}
79e53945 3720
0b8765c6
JB		 3721static void i9xx_crtc_disable(struct drm_crtc *crtc)
3722{
3723 struct drm_device *dev = crtc->dev;
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3726 struct intel_encoder *encoder;
0b8765c6
JB		 3727 int pipe = intel_crtc->pipe;
3728 int plane = intel_crtc->plane;
24a1f16d 3729 u32 pctl;
b690e96c 3730
ef9c3aee 3731
f7abfe8b
CW		 3732 if (!intel_crtc->active)
3733 return;
3734
ea9d758d
DV		 3735 for_each_encoder_on_crtc(dev, crtc, encoder)
3736 encoder->disable(encoder);
3737
0b8765c6 3738 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3739 intel_crtc_wait_for_pending_flips(crtc);
3740 drm_vblank_off(dev, pipe);
0b8765c6 3741 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3742 intel_crtc_update_cursor(crtc, false);
0b8765c6 3743
973d04f9
CW		 3744 if (dev_priv->cfb_plane == plane)
3745 intel_disable_fbc(dev);
79e53945 3746
b24e7179 3747 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3748 intel_disable_pipe(dev_priv, pipe);
24a1f16d
MK		 3749
3750 /* Disable pannel fitter if it is on this pipe. */
3751 pctl = I915_READ(PFIT_CONTROL);
3752 if ((pctl & PFIT_ENABLE) &&
3753 ((pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT) == pipe)
3754 I915_WRITE(PFIT_CONTROL, 0);
3755
63d7bbe9 3756 intel_disable_pll(dev_priv, pipe);
0b8765c6 3757
f7abfe8b 3758 intel_crtc->active = false;
6b383a7f
CW		 3759 intel_update_fbc(dev);
3760 intel_update_watermarks(dev);
0b8765c6
JB		 3761}
3762
ee7b9f93
JB		 3763static void i9xx_crtc_off(struct drm_crtc *crtc)
3764{
3765}
3766
976f8a20
DV		 3767static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3768 bool enabled)
2c07245f
ZW		 3769{
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_master_private *master_priv;
3772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3773 int pipe = intel_crtc->pipe;
79e53945
JB		 3774
3775 if (!dev->primary->master)
3776 return;
3777
3778 master_priv = dev->primary->master->driver_priv;
3779 if (!master_priv->sarea_priv)
3780 return;
3781
79e53945
JB		 3782 switch (pipe) {
3783 case 0:
3784 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3785 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3786 break;
3787 case 1:
3788 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3789 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3790 break;
3791 default:
9db4a9c7 3792 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3793 break;
3794 }
79e53945
JB		 3795}
3796
976f8a20
DV		 3797/**
3798 * Sets the power management mode of the pipe and plane.
3799 */
3800void intel_crtc_update_dpms(struct drm_crtc *crtc)
3801{
3802 struct drm_device *dev = crtc->dev;
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 struct intel_encoder *intel_encoder;
3805 bool enable = false;
3806
3807 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3808 enable |= intel_encoder->connectors_active;
3809
3810 if (enable)
3811 dev_priv->display.crtc_enable(crtc);
3812 else
3813 dev_priv->display.crtc_disable(crtc);
3814
3815 intel_crtc_update_sarea(crtc, enable);
3816}
3817
cdd59983
CW		 3818static void intel_crtc_disable(struct drm_crtc *crtc)
3819{
cdd59983 3820 struct drm_device *dev = crtc->dev;
976f8a20 3821 struct drm_connector *connector;
ee7b9f93 3822 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3823 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3824
976f8a20
DV		 3825 /* crtc should still be enabled when we disable it. */
3826 WARN_ON(!crtc->enabled);
3827
7b9f35a6 3828 intel_crtc->eld_vld = false;
976f8a20
DV		 3829 dev_priv->display.crtc_disable(crtc);
3830 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3831 dev_priv->display.off(crtc);
3832
931872fc
CW		 3833 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3834 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3835
3836 if (crtc->fb) {
3837 mutex_lock(&dev->struct_mutex);
1690e1eb 3838 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3839 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3840 crtc->fb = NULL;
3841 }
3842
3843 /* Update computed state. */
3844 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3845 if (!connector->encoder || !connector->encoder->crtc)
3846 continue;
3847
3848 if (connector->encoder->crtc != crtc)
3849 continue;
3850
3851 connector->dpms = DRM_MODE_DPMS_OFF;
3852 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3853 }
3854}
3855
a261b246 3856void intel_modeset_disable(struct drm_device *dev)
79e53945 3857{
a261b246
DV		 3858 struct drm_crtc *crtc;
3859
3860 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3861 if (crtc->enabled)
3862 intel_crtc_disable(crtc);
3863 }
79e53945
JB		 3864}
3865
ea5b213a 3866void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3867{
4ef69c7a 3868 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3869
ea5b213a
CW		 3870 drm_encoder_cleanup(encoder);
3871 kfree(intel_encoder);
7e7d76c3
JB		 3872}
3873
5ab432ef
DV		 3874/* Simple dpms helper for encodres with just one connector, no cloning and only
3875 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3876 * state of the entire output pipe. */
3877void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3878{
5ab432ef
DV		 3879 if (mode == DRM_MODE_DPMS_ON) {
3880 encoder->connectors_active = true;
3881
b2cabb0e 3882 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3883 } else {
3884 encoder->connectors_active = false;
3885
b2cabb0e 3886 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3887 }
79e53945
JB		 3888}
3889
0a91ca29
DV		 3890/* Cross check the actual hw state with our own modeset state tracking (and it's
3891 * internal consistency). */
b980514c 3892static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3893{
0a91ca29
DV		 3894 if (connector->get_hw_state(connector)) {
3895 struct intel_encoder *encoder = connector->encoder;
3896 struct drm_crtc *crtc;
3897 bool encoder_enabled;
3898 enum pipe pipe;
3899
3900 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3901 connector->base.base.id,
3902 drm_get_connector_name(&connector->base));
3903
3904 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3905 "wrong connector dpms state\n");
3906 WARN(connector->base.encoder != &encoder->base,
3907 "active connector not linked to encoder\n");
3908 WARN(!encoder->connectors_active,
3909 "encoder->connectors_active not set\n");
3910
3911 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3912 WARN(!encoder_enabled, "encoder not enabled\n");
3913 if (WARN_ON(!encoder->base.crtc))
3914 return;
3915
3916 crtc = encoder->base.crtc;
3917
3918 WARN(!crtc->enabled, "crtc not enabled\n");
3919 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3920 WARN(pipe != to_intel_crtc(crtc)->pipe,
3921 "encoder active on the wrong pipe\n");
3922 }
79e53945
JB		 3923}
3924
5ab432ef
DV		 3925/* Even simpler default implementation, if there's really no special case to
3926 * consider. */
3927void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3928{
5ab432ef 3929 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3930
5ab432ef
DV		 3931 /* All the simple cases only support two dpms states. */
3932 if (mode != DRM_MODE_DPMS_ON)
3933 mode = DRM_MODE_DPMS_OFF;
d4270e57 3934
5ab432ef
DV		 3935 if (mode == connector->dpms)
3936 return;
3937
3938 connector->dpms = mode;
3939
3940 /* Only need to change hw state when actually enabled */
3941 if (encoder->base.crtc)
3942 intel_encoder_dpms(encoder, mode);
3943 else
8af6cf88 3944 WARN_ON(encoder->connectors_active != false);
0a91ca29 3945
b980514c 3946 intel_modeset_check_state(connector->dev);
79e53945
JB		 3947}
3948
f0947c37
DV		 3949/* Simple connector->get_hw_state implementation for encoders that support only
3950 * one connector and no cloning and hence the encoder state determines the state
3951 * of the connector. */
3952bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3953{
24929352 3954 enum pipe pipe = 0;
f0947c37 3955 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3956
f0947c37 3957 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3958}
3959
b8cecdf5
DV		 3960static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3961 struct intel_crtc_config *pipe_config)
79e53945 3962{
2c07245f 3963 struct drm_device *dev = crtc->dev;
b8cecdf5 3964 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3965
bad720ff 3966 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3967 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3968 if (pipe_config->requested_mode.clock * 3
3969 > IRONLAKE_FDI_FREQ * 4)
2377b741 3970 return false;
2c07245f 3971 }
89749350 3972
f9bef081
DV		 3973 /* All interlaced capable intel hw wants timings in frames. Note though
3974 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3975 * timings, so we need to be careful not to clobber these.*/
7ae89233 3976 if (!pipe_config->timings_set)
f9bef081 3977 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3978
44f46b42
CW		 3979 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3980 * with a hsync front porch of 0.
3981 */
3982 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3983 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3984 return false;
3985
5d2d38dd
DV		 3986 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10) {
3987 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
3988 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8) {
3989 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
3990 * for lvds. */
3991 pipe_config->pipe_bpp = 8*3;
3992 }
3993
79e53945
JB		 3994 return true;
3995}
3996
25eb05fc
JB		 3997static int valleyview_get_display_clock_speed(struct drm_device *dev)
3998{
3999 return 400000; /* FIXME */
4000}
4001
e70236a8
JB		 4002static int i945_get_display_clock_speed(struct drm_device *dev)
4003{
4004 return 400000;
4005}
79e53945 4006
e70236a8 4007static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4008{
e70236a8
JB		 4009 return 333000;
4010}
79e53945 4011
e70236a8
JB		 4012static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4013{
4014 return 200000;
4015}
79e53945 4016
e70236a8
JB		 4017static int i915gm_get_display_clock_speed(struct drm_device *dev)
4018{
4019 u16 gcfgc = 0;
79e53945 4020
e70236a8
JB		 4021 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4022
4023 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4024 return 133000;
4025 else {
4026 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4027 case GC_DISPLAY_CLOCK_333_MHZ:
4028 return 333000;
4029 default:
4030 case GC_DISPLAY_CLOCK_190_200_MHZ:
4031 return 190000;
79e53945 4032 }
e70236a8
JB		 4033 }
4034}
4035
4036static int i865_get_display_clock_speed(struct drm_device *dev)
4037{
4038 return 266000;
4039}
4040
4041static int i855_get_display_clock_speed(struct drm_device *dev)
4042{
4043 u16 hpllcc = 0;
4044 /* Assume that the hardware is in the high speed state. This
4045 * should be the default.
4046 */
4047 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4048 case GC_CLOCK_133_200:
4049 case GC_CLOCK_100_200:
4050 return 200000;
4051 case GC_CLOCK_166_250:
4052 return 250000;
4053 case GC_CLOCK_100_133:
79e53945 4054 return 133000;
e70236a8 4055 }
79e53945 4056
e70236a8
JB		 4057 /* Shouldn't happen */
4058 return 0;
4059}
79e53945 4060
e70236a8
JB		 4061static int i830_get_display_clock_speed(struct drm_device *dev)
4062{
4063 return 133000;
79e53945
JB		 4064}
4065
2c07245f 4066static void
e69d0bc1 4067intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4068{
4069 while (*num > 0xffffff || *den > 0xffffff) {
4070 *num >>= 1;
4071 *den >>= 1;
4072 }
4073}
4074
e69d0bc1
DV		 4075void
4076intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4077 int pixel_clock, int link_clock,
4078 struct intel_link_m_n *m_n)
2c07245f 4079{
e69d0bc1 4080 m_n->tu = 64;
22ed1113
CW		 4081 m_n->gmch_m = bits_per_pixel * pixel_clock;
4082 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4083 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4084 m_n->link_m = pixel_clock;
4085 m_n->link_n = link_clock;
e69d0bc1 4086 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4087}
4088
a7615030
CW		 4089static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4090{
72bbe58c
KP		 4091 if (i915_panel_use_ssc >= 0)
4092 return i915_panel_use_ssc != 0;
4093 return dev_priv->lvds_use_ssc
435793df 4094 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4095}
4096
a0c4da24
JB		 4097static int vlv_get_refclk(struct drm_crtc *crtc)
4098{
4099 struct drm_device *dev = crtc->dev;
4100 struct drm_i915_private *dev_priv = dev->dev_private;
4101 int refclk = 27000; /* for DP & HDMI */
4102
4103 return 100000; /* only one validated so far */
4104
4105 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4106 refclk = 96000;
4107 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4108 if (intel_panel_use_ssc(dev_priv))
4109 refclk = 100000;
4110 else
4111 refclk = 96000;
4112 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4113 refclk = 100000;
4114 }
4115
4116 return refclk;
4117}
4118
c65d77d8
JB		 4119static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4120{
4121 struct drm_device *dev = crtc->dev;
4122 struct drm_i915_private *dev_priv = dev->dev_private;
4123 int refclk;
4124
a0c4da24
JB		 4125 if (IS_VALLEYVIEW(dev)) {
4126 refclk = vlv_get_refclk(crtc);
4127 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4128 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4129 refclk = dev_priv->lvds_ssc_freq * 1000;
4130 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4131 refclk / 1000);
4132 } else if (!IS_GEN2(dev)) {
4133 refclk = 96000;
4134 } else {
4135 refclk = 48000;
4136 }
4137
4138 return refclk;
4139}
4140
f47709a9 4141static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4142{
f47709a9
DV		 4143 unsigned dotclock = crtc->config.adjusted_mode.clock;
4144 struct dpll *clock = &crtc->config.dpll;
4145
c65d77d8
JB		 4146 /* SDVO TV has fixed PLL values depend on its clock range,
4147 this mirrors vbios setting. */
f47709a9 4148 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4149 clock->p1 = 2;
4150 clock->p2 = 10;
4151 clock->n = 3;
4152 clock->m1 = 16;
4153 clock->m2 = 8;
f47709a9 4154 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4155 clock->p1 = 1;
4156 clock->p2 = 10;
4157 clock->n = 6;
4158 clock->m1 = 12;
4159 clock->m2 = 8;
4160 }
f47709a9
DV		 4161
4162 crtc->config.clock_set = true;
c65d77d8
JB		 4163}
4164
f47709a9 4165static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4166 intel_clock_t *reduced_clock)
4167{
f47709a9 4168 struct drm_device *dev = crtc->base.dev;
a7516a05 4169 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4170 int pipe = crtc->pipe;
a7516a05 4171 u32 fp, fp2 = 0;
f47709a9 4172 struct dpll *clock = &crtc->config.dpll;
a7516a05
JB		 4173
4174 if (IS_PINEVIEW(dev)) {
4175 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4176 if (reduced_clock)
4177 fp2 = (1 << reduced_clock->n) << 16 |
4178 reduced_clock->m1 << 8 | reduced_clock->m2;
4179 } else {
4180 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4181 if (reduced_clock)
4182 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4183 reduced_clock->m2;
4184 }
4185
4186 I915_WRITE(FP0(pipe), fp);
4187
f47709a9
DV		 4188 crtc->lowfreq_avail = false;
4189 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4190 reduced_clock && i915_powersave) {
4191 I915_WRITE(FP1(pipe), fp2);
f47709a9 4192 crtc->lowfreq_avail = true;
a7516a05
JB		 4193 } else {
4194 I915_WRITE(FP1(pipe), fp);
4195 }
4196}
4197
03afc4a2
DV		 4198static void intel_dp_set_m_n(struct intel_crtc *crtc)
4199{
4200 if (crtc->config.has_pch_encoder)
4201 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4202 else
4203 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4204}
4205
f47709a9 4206static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4207{
f47709a9 4208 struct drm_device *dev = crtc->base.dev;
a0c4da24 4209 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4210 int pipe = crtc->pipe;
a0c4da24
JB		 4211 u32 dpll, mdiv, pdiv;
4212 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4213 bool is_sdvo;
4214 u32 temp;
a0c4da24 4215
09153000
DV		 4216 mutex_lock(&dev_priv->dpio_lock);
4217
f47709a9
DV		 4218 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4219 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4220
2a8f64ca
VP		 4221 dpll = DPLL_VGA_MODE_DIS;
4222 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4223 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4224 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4225
4226 I915_WRITE(DPLL(pipe), dpll);
4227 POSTING_READ(DPLL(pipe));
a0c4da24 4228
f47709a9
DV		 4229 bestn = crtc->config.dpll.n;
4230 bestm1 = crtc->config.dpll.m1;
4231 bestm2 = crtc->config.dpll.m2;
4232 bestp1 = crtc->config.dpll.p1;
4233 bestp2 = crtc->config.dpll.p2;
a0c4da24 4234
2a8f64ca
VP		 4235 /*
4236 * In Valleyview PLL and program lane counter registers are exposed
4237 * through DPIO interface
4238 */
a0c4da24
JB		 4239 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4240 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4241 mdiv |= ((bestn << DPIO_N_SHIFT));
4242 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4243 mdiv |= (1 << DPIO_K_SHIFT);
4244 mdiv |= DPIO_ENABLE_CALIBRATION;
4245 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4246
4247 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4248
2a8f64ca 4249 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4250 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4251 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4252 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4253 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4254
2a8f64ca 4255 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4256
4257 dpll |= DPLL_VCO_ENABLE;
4258 I915_WRITE(DPLL(pipe), dpll);
4259 POSTING_READ(DPLL(pipe));
4260 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4261 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4262
2a8f64ca
VP		 4263 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4264
f47709a9
DV		 4265 if (crtc->config.has_dp_encoder)
4266 intel_dp_set_m_n(crtc);
2a8f64ca
VP		 4267
4268 I915_WRITE(DPLL(pipe), dpll);
4269
4270 /* Wait for the clocks to stabilize. */
4271 POSTING_READ(DPLL(pipe));
4272 udelay(150);
a0c4da24 4273
2a8f64ca
VP		 4274 temp = 0;
4275 if (is_sdvo) {
6cc5f341 4276 temp = 0;
f47709a9
DV		 4277 if (crtc->config.pixel_multiplier > 1) {
4278 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4279 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4280 }
a0c4da24 4281 }
2a8f64ca
VP		 4282 I915_WRITE(DPLL_MD(pipe), temp);
4283 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4284
2a8f64ca 4285 /* Now program lane control registers */
f47709a9
DV		 4286 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)
4287 || intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
2a8f64ca
VP		 4288 temp = 0x1000C4;
4289 if(pipe == 1)
4290 temp |= (1 << 21);
4291 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4292 }
f47709a9
DV		 4293
4294 if(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
2a8f64ca
VP		 4295 temp = 0x1000C4;
4296 if(pipe == 1)
4297 temp |= (1 << 21);
4298 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4299 }
09153000
DV		 4300
4301 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4302}
4303
f47709a9
DV		 4304static void i9xx_update_pll(struct intel_crtc *crtc,
4305 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4306 int num_connectors)
4307{
f47709a9 4308 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4309 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4310 struct intel_encoder *encoder;
f47709a9 4311 int pipe = crtc->pipe;
eb1cbe48
DV		 4312 u32 dpll;
4313 bool is_sdvo;
f47709a9 4314 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4315
f47709a9 4316 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4317
f47709a9
DV		 4318 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4319 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4320
4321 dpll = DPLL_VGA_MODE_DIS;
4322
f47709a9 4323 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4324 dpll |= DPLLB_MODE_LVDS;
4325 else
4326 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4327
eb1cbe48 4328 if (is_sdvo) {
f47709a9 4329 if ((crtc->config.pixel_multiplier > 1) &&
6cc5f341 4330 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
f47709a9 4331 dpll |= (crtc->config.pixel_multiplier - 1)
6cc5f341 4332 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48
DV		 4333 }
4334 dpll |= DPLL_DVO_HIGH_SPEED;
4335 }
f47709a9 4336 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4337 dpll |= DPLL_DVO_HIGH_SPEED;
4338
4339 /* compute bitmask from p1 value */
4340 if (IS_PINEVIEW(dev))
4341 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4342 else {
4343 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4344 if (IS_G4X(dev) && reduced_clock)
4345 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4346 }
4347 switch (clock->p2) {
4348 case 5:
4349 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4350 break;
4351 case 7:
4352 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4353 break;
4354 case 10:
4355 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4356 break;
4357 case 14:
4358 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4359 break;
4360 }
4361 if (INTEL_INFO(dev)->gen >= 4)
4362 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4363
f47709a9 4364 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4365 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4366 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4367 /* XXX: just matching BIOS for now */
4368 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4369 dpll |= 3;
f47709a9 4370 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4371 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4372 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4373 else
4374 dpll |= PLL_REF_INPUT_DREFCLK;
4375
4376 dpll |= DPLL_VCO_ENABLE;
4377 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4378 POSTING_READ(DPLL(pipe));
4379 udelay(150);
4380
f47709a9 4381 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4382 if (encoder->pre_pll_enable)
4383 encoder->pre_pll_enable(encoder);
eb1cbe48 4384
f47709a9
DV		 4385 if (crtc->config.has_dp_encoder)
4386 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4387
4388 I915_WRITE(DPLL(pipe), dpll);
4389
4390 /* Wait for the clocks to stabilize. */
4391 POSTING_READ(DPLL(pipe));
4392 udelay(150);
4393
4394 if (INTEL_INFO(dev)->gen >= 4) {
4395 u32 temp = 0;
4396 if (is_sdvo) {
6cc5f341 4397 temp = 0;
f47709a9
DV		 4398 if (crtc->config.pixel_multiplier > 1) {
4399 temp = (crtc->config.pixel_multiplier - 1)
6cc5f341
DV		 4400 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4401 }
eb1cbe48
DV		 4402 }
4403 I915_WRITE(DPLL_MD(pipe), temp);
4404 } else {
4405 /* The pixel multiplier can only be updated once the
4406 * DPLL is enabled and the clocks are stable.
4407 *
4408 * So write it again.
4409 */
4410 I915_WRITE(DPLL(pipe), dpll);
4411 }
4412}
4413
f47709a9 4414static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4415 struct drm_display_mode *adjusted_mode,
f47709a9 4416 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4417 int num_connectors)
4418{
f47709a9 4419 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4420 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4421 struct intel_encoder *encoder;
f47709a9 4422 int pipe = crtc->pipe;
eb1cbe48 4423 u32 dpll;
f47709a9 4424 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4425
f47709a9 4426 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4427
eb1cbe48
DV		 4428 dpll = DPLL_VGA_MODE_DIS;
4429
f47709a9 4430 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4431 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4432 } else {
4433 if (clock->p1 == 2)
4434 dpll |= PLL_P1_DIVIDE_BY_TWO;
4435 else
4436 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4437 if (clock->p2 == 4)
4438 dpll |= PLL_P2_DIVIDE_BY_4;
4439 }
4440
f47709a9 4441 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4442 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4443 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4444 else
4445 dpll |= PLL_REF_INPUT_DREFCLK;
4446
4447 dpll |= DPLL_VCO_ENABLE;
4448 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4449 POSTING_READ(DPLL(pipe));
4450 udelay(150);
4451
f47709a9 4452 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4453 if (encoder->pre_pll_enable)
4454 encoder->pre_pll_enable(encoder);
eb1cbe48 4455
5b5896e4
DV		 4456 I915_WRITE(DPLL(pipe), dpll);
4457
4458 /* Wait for the clocks to stabilize. */
4459 POSTING_READ(DPLL(pipe));
4460 udelay(150);
4461
eb1cbe48
DV		 4462 /* The pixel multiplier can only be updated once the
4463 * DPLL is enabled and the clocks are stable.
4464 *
4465 * So write it again.
4466 */
4467 I915_WRITE(DPLL(pipe), dpll);
4468}
4469
b0e77b9c
PZ		 4470static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4471 struct drm_display_mode *mode,
4472 struct drm_display_mode *adjusted_mode)
4473{
4474 struct drm_device *dev = intel_crtc->base.dev;
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4477 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4478 uint32_t vsyncshift;
4479
4480 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4481 /* the chip adds 2 halflines automatically */
4482 adjusted_mode->crtc_vtotal -= 1;
4483 adjusted_mode->crtc_vblank_end -= 1;
4484 vsyncshift = adjusted_mode->crtc_hsync_start
4485 - adjusted_mode->crtc_htotal / 2;
4486 } else {
4487 vsyncshift = 0;
4488 }
4489
4490 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4491 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4492
fe2b8f9d 4493 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4494 (adjusted_mode->crtc_hdisplay - 1) |
4495 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4496 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4497 (adjusted_mode->crtc_hblank_start - 1) |
4498 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4499 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4500 (adjusted_mode->crtc_hsync_start - 1) |
4501 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4502
fe2b8f9d 4503 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4504 (adjusted_mode->crtc_vdisplay - 1) |
4505 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4506 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4507 (adjusted_mode->crtc_vblank_start - 1) |
4508 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4509 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4510 (adjusted_mode->crtc_vsync_start - 1) |
4511 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4512
b5e508d4
PZ		 4513 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4514 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4515 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4516 * bits. */
4517 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4518 (pipe == PIPE_B || pipe == PIPE_C))
4519 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4520
b0e77b9c
PZ		 4521 /* pipesrc controls the size that is scaled from, which should
4522 * always be the user's requested size.
4523 */
4524 I915_WRITE(PIPESRC(pipe),
4525 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4526}
4527
84b046f3
DV		 4528static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4529{
4530 struct drm_device *dev = intel_crtc->base.dev;
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532 uint32_t pipeconf;
4533
4534 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4535
4536 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4537 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4538 * core speed.
4539 *
4540 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4541 * pipe == 0 check?
4542 */
4543 if (intel_crtc->config.requested_mode.clock >
4544 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4545 pipeconf |= PIPECONF_DOUBLE_WIDE;
4546 else
4547 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4548 }
4549
4550 /* default to 8bpc */
4551 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4552 if (intel_crtc->config.has_dp_encoder) {
4553 if (intel_crtc->config.dither) {
4554 pipeconf |= PIPECONF_6BPC |
4555 PIPECONF_DITHER_EN |
4556 PIPECONF_DITHER_TYPE_SP;
4557 }
4558 }
4559
4560 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4561 INTEL_OUTPUT_EDP)) {
4562 if (intel_crtc->config.dither) {
4563 pipeconf |= PIPECONF_6BPC |
4564 PIPECONF_ENABLE |
4565 I965_PIPECONF_ACTIVE;
4566 }
4567 }
4568
4569 if (HAS_PIPE_CXSR(dev)) {
4570 if (intel_crtc->lowfreq_avail) {
4571 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4572 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4573 } else {
4574 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4575 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4576 }
4577 }
4578
4579 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4580 if (!IS_GEN2(dev) &&
4581 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4582 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4583 else
4584 pipeconf |= PIPECONF_PROGRESSIVE;
4585
4586 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4587 POSTING_READ(PIPECONF(intel_crtc->pipe));
4588}
4589
f564048e 4590static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4591 int x, int y,
94352cf9 4592 struct drm_framebuffer *fb)
79e53945
JB		 4593{
4594 struct drm_device *dev = crtc->dev;
4595 struct drm_i915_private *dev_priv = dev->dev_private;
4596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4597 struct drm_display_mode *adjusted_mode =
4598 &intel_crtc->config.adjusted_mode;
4599 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4600 int pipe = intel_crtc->pipe;
80824003 4601 int plane = intel_crtc->plane;
c751ce4f 4602 int refclk, num_connectors = 0;
652c393a 4603 intel_clock_t clock, reduced_clock;
84b046f3 4604 u32 dspcntr;
eb1cbe48 4605 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4606 bool is_lvds = false, is_tv = false;
5eddb70b 4607 struct intel_encoder *encoder;
d4906093 4608 const intel_limit_t *limit;
5c3b82e2 4609 int ret;
79e53945 4610
6c2b7c12 4611 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4612 switch (encoder->type) {
79e53945
JB		 4613 case INTEL_OUTPUT_LVDS:
4614 is_lvds = true;
4615 break;
4616 case INTEL_OUTPUT_SDVO:
7d57382e 4617 case INTEL_OUTPUT_HDMI:
79e53945 4618 is_sdvo = true;
5eddb70b 4619 if (encoder->needs_tv_clock)
e2f0ba97 4620 is_tv = true;
79e53945 4621 break;
79e53945
JB		 4622 case INTEL_OUTPUT_TVOUT:
4623 is_tv = true;
4624 break;
79e53945 4625 }
43565a06 4626
c751ce4f 4627 num_connectors++;
79e53945
JB		 4628 }
4629
c65d77d8 4630 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4631
d4906093
ML		 4632 /*
4633 * Returns a set of divisors for the desired target clock with the given
4634 * refclk, or FALSE. The returned values represent the clock equation:
4635 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4636 */
1b894b59 4637 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4638 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4639 &clock);
79e53945
JB		 4640 if (!ok) {
4641 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4642 return -EINVAL;
79e53945
JB		 4643 }
4644
cda4b7d3 4645 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4646 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4647
ddc9003c 4648 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4649 /*
4650 * Ensure we match the reduced clock's P to the target clock.
4651 * If the clocks don't match, we can't switch the display clock
4652 * by using the FP0/FP1. In such case we will disable the LVDS
4653 * downclock feature.
4654 */
ddc9003c 4655 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4656 dev_priv->lvds_downclock,
4657 refclk,
cec2f356 4658 &clock,
5eddb70b 4659 &reduced_clock);
7026d4ac 4660 }
f47709a9
DV		 4661 /* Compat-code for transition, will disappear. */
4662 if (!intel_crtc->config.clock_set) {
4663 intel_crtc->config.dpll.n = clock.n;
4664 intel_crtc->config.dpll.m1 = clock.m1;
4665 intel_crtc->config.dpll.m2 = clock.m2;
4666 intel_crtc->config.dpll.p1 = clock.p1;
4667 intel_crtc->config.dpll.p2 = clock.p2;
4668 }
7026d4ac 4669
c65d77d8 4670 if (is_sdvo && is_tv)
f47709a9 4671 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4672
eb1cbe48 4673 if (IS_GEN2(dev))
f47709a9 4674 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4675 has_reduced_clock ? &reduced_clock : NULL,
4676 num_connectors);
a0c4da24 4677 else if (IS_VALLEYVIEW(dev))
f47709a9 4678 vlv_update_pll(intel_crtc);
79e53945 4679 else
f47709a9 4680 i9xx_update_pll(intel_crtc,
eb1cbe48
DV		 4681 has_reduced_clock ? &reduced_clock : NULL,
4682 num_connectors);
79e53945 4683
79e53945
JB		 4684 /* Set up the display plane register */
4685 dspcntr = DISPPLANE_GAMMA_ENABLE;
4686
da6ecc5d
JB		 4687 if (!IS_VALLEYVIEW(dev)) {
4688 if (pipe == 0)
4689 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4690 else
4691 dspcntr |= DISPPLANE_SEL_PIPE_B;
4692 }
79e53945 4693
28c97730 4694 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4695 drm_mode_debug_printmodeline(mode);
4696
b0e77b9c 4697 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4698
4699 /* pipesrc and dspsize control the size that is scaled from,
4700 * which should always be the user's requested size.
79e53945 4701 */
929c77fb
EA		 4702 I915_WRITE(DSPSIZE(plane),
4703 ((mode->vdisplay - 1) << 16) |
4704 (mode->hdisplay - 1));
4705 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4706
84b046f3
DV		 4707 i9xx_set_pipeconf(intel_crtc);
4708
929c77fb 4709 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4710
4711 intel_wait_for_vblank(dev, pipe);
4712
f564048e
EA		 4713 I915_WRITE(DSPCNTR(plane), dspcntr);
4714 POSTING_READ(DSPCNTR(plane));
4715
94352cf9 4716 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4717
4718 intel_update_watermarks(dev);
4719
f564048e
EA		 4720 return ret;
4721}
4722
0e8ffe1b
DV		 4723static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4724 struct intel_crtc_config *pipe_config)
4725{
4726 struct drm_device *dev = crtc->base.dev;
4727 struct drm_i915_private *dev_priv = dev->dev_private;
4728 uint32_t tmp;
4729
4730 tmp = I915_READ(PIPECONF(crtc->pipe));
4731 if (!(tmp & PIPECONF_ENABLE))
4732 return false;
4733
4734 return true;
4735}
4736
dde86e2d 4737static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4738{
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4741 struct intel_encoder *encoder;
74cfd7ac 4742 u32 val, final;
13d83a67 4743 bool has_lvds = false;
199e5d79
KP		 4744 bool has_cpu_edp = false;
4745 bool has_pch_edp = false;
4746 bool has_panel = false;
99eb6a01
KP		 4747 bool has_ck505 = false;
4748 bool can_ssc = false;
13d83a67
JB		 4749
4750 /* We need to take the global config into account */
199e5d79
KP		 4751 list_for_each_entry(encoder, &mode_config->encoder_list,
4752 base.head) {
4753 switch (encoder->type) {
4754 case INTEL_OUTPUT_LVDS:
4755 has_panel = true;
4756 has_lvds = true;
4757 break;
4758 case INTEL_OUTPUT_EDP:
4759 has_panel = true;
4760 if (intel_encoder_is_pch_edp(&encoder->base))
4761 has_pch_edp = true;
4762 else
4763 has_cpu_edp = true;
4764 break;
13d83a67
JB		 4765 }
4766 }
4767
99eb6a01
KP		 4768 if (HAS_PCH_IBX(dev)) {
4769 has_ck505 = dev_priv->display_clock_mode;
4770 can_ssc = has_ck505;
4771 } else {
4772 has_ck505 = false;
4773 can_ssc = true;
4774 }
4775
4776 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4777 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4778 has_ck505);
13d83a67
JB		 4779
4780 /* Ironlake: try to setup display ref clock before DPLL
4781 * enabling. This is only under driver's control after
4782 * PCH B stepping, previous chipset stepping should be
4783 * ignoring this setting.
4784 */
74cfd7ac
CW		 4785 val = I915_READ(PCH_DREF_CONTROL);
4786
4787 /* As we must carefully and slowly disable/enable each source in turn,
4788 * compute the final state we want first and check if we need to
4789 * make any changes at all.
4790 */
4791 final = val;
4792 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4793 if (has_ck505)
4794 final |= DREF_NONSPREAD_CK505_ENABLE;
4795 else
4796 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4797
4798 final &= ~DREF_SSC_SOURCE_MASK;
4799 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4800 final &= ~DREF_SSC1_ENABLE;
4801
4802 if (has_panel) {
4803 final |= DREF_SSC_SOURCE_ENABLE;
4804
4805 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4806 final |= DREF_SSC1_ENABLE;
4807
4808 if (has_cpu_edp) {
4809 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4810 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4811 else
4812 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4813 } else
4814 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4815 } else {
4816 final |= DREF_SSC_SOURCE_DISABLE;
4817 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4818 }
4819
4820 if (final == val)
4821 return;
4822
13d83a67 4823 /* Always enable nonspread source */
74cfd7ac 4824 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4825
99eb6a01 4826 if (has_ck505)
74cfd7ac 4827 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4828 else
74cfd7ac 4829 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4830
199e5d79 4831 if (has_panel) {
74cfd7ac
CW		 4832 val &= ~DREF_SSC_SOURCE_MASK;
4833 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4834
199e5d79 4835 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4836 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4837 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4838 val |= DREF_SSC1_ENABLE;
e77166b5 4839 } else
74cfd7ac 4840 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4841
4842 /* Get SSC going before enabling the outputs */
74cfd7ac 4843 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4844 POSTING_READ(PCH_DREF_CONTROL);
4845 udelay(200);
4846
74cfd7ac 4847 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4848
4849 /* Enable CPU source on CPU attached eDP */
199e5d79 4850 if (has_cpu_edp) {
99eb6a01 4851 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4852 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4853 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4854 }
13d83a67 4855 else
74cfd7ac 4856 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4857 } else
74cfd7ac 4858 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4859
74cfd7ac 4860 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4861 POSTING_READ(PCH_DREF_CONTROL);
4862 udelay(200);
4863 } else {
4864 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4865
74cfd7ac 4866 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 4867
4868 /* Turn off CPU output */
74cfd7ac 4869 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4870
74cfd7ac 4871 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4872 POSTING_READ(PCH_DREF_CONTROL);
4873 udelay(200);
4874
4875 /* Turn off the SSC source */
74cfd7ac
CW		 4876 val &= ~DREF_SSC_SOURCE_MASK;
4877 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 4878
4879 /* Turn off SSC1 */
74cfd7ac 4880 val &= ~DREF_SSC1_ENABLE;
199e5d79 4881
74cfd7ac 4882 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 4883 POSTING_READ(PCH_DREF_CONTROL);
4884 udelay(200);
4885 }
74cfd7ac
CW		 4886
4887 BUG_ON(val != final);
13d83a67
JB		 4888}
4889
dde86e2d
PZ		 4890/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4891static void lpt_init_pch_refclk(struct drm_device *dev)
4892{
4893 struct drm_i915_private *dev_priv = dev->dev_private;
4894 struct drm_mode_config *mode_config = &dev->mode_config;
4895 struct intel_encoder *encoder;
4896 bool has_vga = false;
4897 bool is_sdv = false;
4898 u32 tmp;
4899
4900 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4901 switch (encoder->type) {
4902 case INTEL_OUTPUT_ANALOG:
4903 has_vga = true;
4904 break;
4905 }
4906 }
4907
4908 if (!has_vga)
4909 return;
4910
c00db246
DV		 4911 mutex_lock(&dev_priv->dpio_lock);
4912
dde86e2d
PZ		 4913 /* XXX: Rip out SDV support once Haswell ships for real. */
4914 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4915 is_sdv = true;
4916
4917 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4918 tmp &= ~SBI_SSCCTL_DISABLE;
4919 tmp |= SBI_SSCCTL_PATHALT;
4920 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4921
4922 udelay(24);
4923
4924 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4925 tmp &= ~SBI_SSCCTL_PATHALT;
4926 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4927
4928 if (!is_sdv) {
4929 tmp = I915_READ(SOUTH_CHICKEN2);
4930 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4931 I915_WRITE(SOUTH_CHICKEN2, tmp);
4932
4933 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4934 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4935 DRM_ERROR("FDI mPHY reset assert timeout\n");
4936
4937 tmp = I915_READ(SOUTH_CHICKEN2);
4938 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4939 I915_WRITE(SOUTH_CHICKEN2, tmp);
4940
4941 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4942 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4943 100))
4944 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4945 }
4946
4947 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4948 tmp &= ~(0xFF << 24);
4949 tmp |= (0x12 << 24);
4950 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4951
4952 if (!is_sdv) {
4953 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4954 tmp &= ~(0x3 << 6);
4955 tmp |= (1 << 6) | (1 << 0);
4956 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4957 }
4958
4959 if (is_sdv) {
4960 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4961 tmp |= 0x7FFF;
4962 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4963 }
4964
4965 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4966 tmp |= (1 << 11);
4967 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4968
4969 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4970 tmp |= (1 << 11);
4971 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4972
4973 if (is_sdv) {
4974 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4975 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4976 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4977
4978 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4979 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4980 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4981
4982 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4983 tmp |= (0x3F << 8);
4984 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4985
4986 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4987 tmp |= (0x3F << 8);
4988 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4989 }
4990
4991 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4992 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4993 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4994
4995 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4996 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4997 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4998
4999 if (!is_sdv) {
5000 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5001 tmp &= ~(7 << 13);
5002 tmp |= (5 << 13);
5003 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5004
5005 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5006 tmp &= ~(7 << 13);
5007 tmp |= (5 << 13);
5008 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5009 }
5010
5011 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5012 tmp &= ~0xFF;
5013 tmp |= 0x1C;
5014 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5015
5016 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5017 tmp &= ~0xFF;
5018 tmp |= 0x1C;
5019 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5020
5021 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5022 tmp &= ~(0xFF << 16);
5023 tmp |= (0x1C << 16);
5024 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5025
5026 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5027 tmp &= ~(0xFF << 16);
5028 tmp |= (0x1C << 16);
5029 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5030
5031 if (!is_sdv) {
5032 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5033 tmp |= (1 << 27);
5034 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5035
5036 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5037 tmp |= (1 << 27);
5038 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5039
5040 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5041 tmp &= ~(0xF << 28);
5042 tmp |= (4 << 28);
5043 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5044
5045 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5046 tmp &= ~(0xF << 28);
5047 tmp |= (4 << 28);
5048 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5049 }
5050
5051 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5052 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5053 tmp |= SBI_DBUFF0_ENABLE;
5054 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5055
5056 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5057}
5058
5059/*
5060 * Initialize reference clocks when the driver loads
5061 */
5062void intel_init_pch_refclk(struct drm_device *dev)
5063{
5064 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5065 ironlake_init_pch_refclk(dev);
5066 else if (HAS_PCH_LPT(dev))
5067 lpt_init_pch_refclk(dev);
5068}
5069
d9d444cb
JB		 5070static int ironlake_get_refclk(struct drm_crtc *crtc)
5071{
5072 struct drm_device *dev = crtc->dev;
5073 struct drm_i915_private *dev_priv = dev->dev_private;
5074 struct intel_encoder *encoder;
d9d444cb
JB		 5075 struct intel_encoder *edp_encoder = NULL;
5076 int num_connectors = 0;
5077 bool is_lvds = false;
5078
6c2b7c12 5079 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5080 switch (encoder->type) {
5081 case INTEL_OUTPUT_LVDS:
5082 is_lvds = true;
5083 break;
5084 case INTEL_OUTPUT_EDP:
5085 edp_encoder = encoder;
5086 break;
5087 }
5088 num_connectors++;
5089 }
5090
5091 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5092 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5093 dev_priv->lvds_ssc_freq);
5094 return dev_priv->lvds_ssc_freq * 1000;
5095 }
5096
5097 return 120000;
5098}
5099
c8203565 5100static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5101 struct drm_display_mode *adjusted_mode,
c8203565 5102 bool dither)
79e53945 5103{
c8203565 5104 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5106 int pipe = intel_crtc->pipe;
c8203565
PZ		 5107 uint32_t val;
5108
5109 val = I915_READ(PIPECONF(pipe));
5110
dfd07d72 5111 val &= ~PIPECONF_BPC_MASK;
965e0c48 5112 switch (intel_crtc->config.pipe_bpp) {
c8203565 5113 case 18:
dfd07d72 5114 val |= PIPECONF_6BPC;
c8203565
PZ		 5115 break;
5116 case 24:
dfd07d72 5117 val |= PIPECONF_8BPC;
c8203565
PZ		 5118 break;
5119 case 30:
dfd07d72 5120 val |= PIPECONF_10BPC;
c8203565
PZ		 5121 break;
5122 case 36:
dfd07d72 5123 val |= PIPECONF_12BPC;
c8203565
PZ		 5124 break;
5125 default:
cc769b62
PZ		 5126 /* Case prevented by intel_choose_pipe_bpp_dither. */
5127 BUG();
c8203565
PZ		 5128 }
5129
5130 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5131 if (dither)
5132 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5133
5134 val &= ~PIPECONF_INTERLACE_MASK;
5135 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5136 val |= PIPECONF_INTERLACED_ILK;
5137 else
5138 val |= PIPECONF_PROGRESSIVE;
5139
50f3b016 5140 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5141 val |= PIPECONF_COLOR_RANGE_SELECT;
5142 else
5143 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5144
c8203565
PZ		 5145 I915_WRITE(PIPECONF(pipe), val);
5146 POSTING_READ(PIPECONF(pipe));
5147}
5148
86d3efce
VS		 5149/*
5150 * Set up the pipe CSC unit.
5151 *
5152 * Currently only full range RGB to limited range RGB conversion
5153 * is supported, but eventually this should handle various
5154 * RGB<->YCbCr scenarios as well.
5155 */
50f3b016 5156static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5157{
5158 struct drm_device *dev = crtc->dev;
5159 struct drm_i915_private *dev_priv = dev->dev_private;
5160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5161 int pipe = intel_crtc->pipe;
5162 uint16_t coeff = 0x7800; /* 1.0 */
5163
5164 /*
5165 * TODO: Check what kind of values actually come out of the pipe
5166 * with these coeff/postoff values and adjust to get the best
5167 * accuracy. Perhaps we even need to take the bpc value into
5168 * consideration.
5169 */
5170
50f3b016 5171 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5172 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5173
5174 /*
5175 * GY/GU and RY/RU should be the other way around according
5176 * to BSpec, but reality doesn't agree. Just set them up in
5177 * a way that results in the correct picture.
5178 */
5179 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5180 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5181
5182 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5183 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5184
5185 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5186 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5187
5188 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5189 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5190 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5191
5192 if (INTEL_INFO(dev)->gen > 6) {
5193 uint16_t postoff = 0;
5194
50f3b016 5195 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5196 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5197
5198 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5199 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5200 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5201
5202 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5203 } else {
5204 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5205
50f3b016 5206 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5207 mode |= CSC_BLACK_SCREEN_OFFSET;
5208
5209 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5210 }
5211}
5212
ee2b0b38
PZ		 5213static void haswell_set_pipeconf(struct drm_crtc *crtc,
5214 struct drm_display_mode *adjusted_mode,
5215 bool dither)
5216{
5217 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5219 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5220 uint32_t val;
5221
702e7a56 5222 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5223
5224 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5225 if (dither)
5226 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5227
5228 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5229 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5230 val |= PIPECONF_INTERLACED_ILK;
5231 else
5232 val |= PIPECONF_PROGRESSIVE;
5233
702e7a56
PZ		 5234 I915_WRITE(PIPECONF(cpu_transcoder), val);
5235 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5236}
5237
6591c6e4
PZ		 5238static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5239 struct drm_display_mode *adjusted_mode,
5240 intel_clock_t *clock,
5241 bool *has_reduced_clock,
5242 intel_clock_t *reduced_clock)
5243{
5244 struct drm_device *dev = crtc->dev;
5245 struct drm_i915_private *dev_priv = dev->dev_private;
5246 struct intel_encoder *intel_encoder;
5247 int refclk;
d4906093 5248 const intel_limit_t *limit;
6591c6e4 5249 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5250
6591c6e4
PZ		 5251 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5252 switch (intel_encoder->type) {
79e53945
JB		 5253 case INTEL_OUTPUT_LVDS:
5254 is_lvds = true;
5255 break;
5256 case INTEL_OUTPUT_SDVO:
7d57382e 5257 case INTEL_OUTPUT_HDMI:
79e53945 5258 is_sdvo = true;
6591c6e4 5259 if (intel_encoder->needs_tv_clock)
e2f0ba97 5260 is_tv = true;
79e53945 5261 break;
79e53945
JB		 5262 case INTEL_OUTPUT_TVOUT:
5263 is_tv = true;
5264 break;
79e53945
JB		 5265 }
5266 }
5267
d9d444cb 5268 refclk = ironlake_get_refclk(crtc);
79e53945 5269
d4906093
ML		 5270 /*
5271 * Returns a set of divisors for the desired target clock with the given
5272 * refclk, or FALSE. The returned values represent the clock equation:
5273 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5274 */
1b894b59 5275 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5276 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5277 clock);
5278 if (!ret)
5279 return false;
cda4b7d3 5280
ddc9003c 5281 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5282 /*
5283 * Ensure we match the reduced clock's P to the target clock.
5284 * If the clocks don't match, we can't switch the display clock
5285 * by using the FP0/FP1. In such case we will disable the LVDS
5286 * downclock feature.
5287 */
6591c6e4
PZ		 5288 *has_reduced_clock = limit->find_pll(limit, crtc,
5289 dev_priv->lvds_downclock,
5290 refclk,
5291 clock,
5292 reduced_clock);
652c393a 5293 }
61e9653f
DV		 5294
5295 if (is_sdvo && is_tv)
f47709a9 5296 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5297
5298 return true;
5299}
5300
01a415fd
DV		 5301static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5302{
5303 struct drm_i915_private *dev_priv = dev->dev_private;
5304 uint32_t temp;
5305
5306 temp = I915_READ(SOUTH_CHICKEN1);
5307 if (temp & FDI_BC_BIFURCATION_SELECT)
5308 return;
5309
5310 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5311 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5312
5313 temp |= FDI_BC_BIFURCATION_SELECT;
5314 DRM_DEBUG_KMS("enabling fdi C rx\n");
5315 I915_WRITE(SOUTH_CHICKEN1, temp);
5316 POSTING_READ(SOUTH_CHICKEN1);
5317}
5318
5319static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5320{
5321 struct drm_device *dev = intel_crtc->base.dev;
5322 struct drm_i915_private *dev_priv = dev->dev_private;
5323 struct intel_crtc *pipe_B_crtc =
5324 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5325
5326 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5327 intel_crtc->pipe, intel_crtc->fdi_lanes);
5328 if (intel_crtc->fdi_lanes > 4) {
5329 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5330 intel_crtc->pipe, intel_crtc->fdi_lanes);
5331 /* Clamp lanes to avoid programming the hw with bogus values. */
5332 intel_crtc->fdi_lanes = 4;
5333
5334 return false;
5335 }
5336
7eb552ae 5337 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5338 return true;
5339
5340 switch (intel_crtc->pipe) {
5341 case PIPE_A:
5342 return true;
5343 case PIPE_B:
5344 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5345 intel_crtc->fdi_lanes > 2) {
5346 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5347 intel_crtc->pipe, intel_crtc->fdi_lanes);
5348 /* Clamp lanes to avoid programming the hw with bogus values. */
5349 intel_crtc->fdi_lanes = 2;
5350
5351 return false;
5352 }
5353
5354 if (intel_crtc->fdi_lanes > 2)
5355 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5356 else
5357 cpt_enable_fdi_bc_bifurcation(dev);
5358
5359 return true;
5360 case PIPE_C:
5361 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5362 if (intel_crtc->fdi_lanes > 2) {
5363 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5364 intel_crtc->pipe, intel_crtc->fdi_lanes);
5365 /* Clamp lanes to avoid programming the hw with bogus values. */
5366 intel_crtc->fdi_lanes = 2;
5367
5368 return false;
5369 }
5370 } else {
5371 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5372 return false;
5373 }
5374
5375 cpt_enable_fdi_bc_bifurcation(dev);
5376
5377 return true;
5378 default:
5379 BUG();
5380 }
5381}
5382
d4b1931c
PZ		 5383int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5384{
5385 /*
5386 * Account for spread spectrum to avoid
5387 * oversubscribing the link. Max center spread
5388 * is 2.5%; use 5% for safety's sake.
5389 */
5390 u32 bps = target_clock * bpp * 21 / 20;
5391 return bps / (link_bw * 8) + 1;
5392}
5393
6cf86a5e
DV		 5394void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5395 struct intel_link_m_n *m_n)
79e53945 5396{
6cf86a5e
DV		 5397 struct drm_device *dev = crtc->base.dev;
5398 struct drm_i915_private *dev_priv = dev->dev_private;
5399 int pipe = crtc->pipe;
5400
5401 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5402 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5403 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5404 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5405}
5406
5407void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5408 struct intel_link_m_n *m_n)
5409{
5410 struct drm_device *dev = crtc->base.dev;
79e53945 5411 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e
DV		 5412 int pipe = crtc->pipe;
5413 enum transcoder transcoder = crtc->cpu_transcoder;
5414
5415 if (INTEL_INFO(dev)->gen >= 5) {
5416 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5417 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5418 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5419 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5420 } else {
5421 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5422 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5423 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5424 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5425 }
5426}
5427
5428static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5429{
5430 struct drm_device *dev = crtc->dev;
79e53945 5431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5432 struct drm_display_mode *adjusted_mode =
5433 &intel_crtc->config.adjusted_mode;
e69d0bc1 5434 struct intel_link_m_n m_n = {0};
6cc5f341 5435 int target_clock, lane, link_bw;
61e9653f 5436
6cf86a5e
DV		 5437 /* FDI is a binary signal running at ~2.7GHz, encoding
5438 * each output octet as 10 bits. The actual frequency
5439 * is stored as a divider into a 100MHz clock, and the
5440 * mode pixel clock is stored in units of 1KHz.
5441 * Hence the bw of each lane in terms of the mode signal
5442 * is:
5443 */
5444 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5445
df92b1e6
DV		 5446 if (intel_crtc->config.pixel_target_clock)
5447 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5448 else
5449 target_clock = adjusted_mode->clock;
5450
6cf86a5e
DV		 5451 lane = ironlake_get_lanes_required(target_clock, link_bw,
5452 intel_crtc->config.pipe_bpp);
2c07245f 5453
8febb297
EA		 5454 intel_crtc->fdi_lanes = lane;
5455
6cc5f341
DV		 5456 if (intel_crtc->config.pixel_multiplier > 1)
5457 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5458 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5459 link_bw, &m_n);
8febb297 5460
6cf86a5e 5461 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5462}
5463
de13a2e3 5464static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
de13a2e3 5465 intel_clock_t *clock, u32 fp)
79e53945 5466{
de13a2e3 5467 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5468 struct drm_device *dev = crtc->dev;
5469 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5470 struct intel_encoder *intel_encoder;
5471 uint32_t dpll;
6cc5f341 5472 int factor, num_connectors = 0;
de13a2e3 5473 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5474
de13a2e3
PZ		 5475 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5476 switch (intel_encoder->type) {
79e53945
JB		 5477 case INTEL_OUTPUT_LVDS:
5478 is_lvds = true;
5479 break;
5480 case INTEL_OUTPUT_SDVO:
7d57382e 5481 case INTEL_OUTPUT_HDMI:
79e53945 5482 is_sdvo = true;
de13a2e3 5483 if (intel_encoder->needs_tv_clock)
e2f0ba97 5484 is_tv = true;
79e53945 5485 break;
79e53945
JB		 5486 case INTEL_OUTPUT_TVOUT:
5487 is_tv = true;
5488 break;
79e53945 5489 }
43565a06 5490
c751ce4f 5491 num_connectors++;
79e53945 5492 }
79e53945 5493
c1858123 5494 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5495 factor = 21;
5496 if (is_lvds) {
5497 if ((intel_panel_use_ssc(dev_priv) &&
5498 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5499 intel_is_dual_link_lvds(dev))
8febb297
EA		 5500 factor = 25;
5501 } else if (is_sdvo && is_tv)
5502 factor = 20;
c1858123 5503
de13a2e3 5504 if (clock->m < factor * clock->n)
8febb297 5505 fp |= FP_CB_TUNE;
2c07245f 5506
5eddb70b 5507 dpll = 0;
2c07245f 5508
a07d6787
EA		 5509 if (is_lvds)
5510 dpll |= DPLLB_MODE_LVDS;
5511 else
5512 dpll |= DPLLB_MODE_DAC_SERIAL;
5513 if (is_sdvo) {
6cc5f341
DV		 5514 if (intel_crtc->config.pixel_multiplier > 1) {
5515 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5516 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5517 }
a07d6787
EA		 5518 dpll |= DPLL_DVO_HIGH_SPEED;
5519 }
8b47047b
DV		 5520 if (intel_crtc->config.has_dp_encoder &&
5521 intel_crtc->config.has_pch_encoder)
a07d6787 5522 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5523
a07d6787 5524 /* compute bitmask from p1 value */
de13a2e3 5525 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5526 /* also FPA1 */
de13a2e3 5527 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5528
de13a2e3 5529 switch (clock->p2) {
a07d6787
EA		 5530 case 5:
5531 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5532 break;
5533 case 7:
5534 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5535 break;
5536 case 10:
5537 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5538 break;
5539 case 14:
5540 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5541 break;
79e53945
JB		 5542 }
5543
43565a06
KH		 5544 if (is_sdvo && is_tv)
5545 dpll |= PLL_REF_INPUT_TVCLKINBC;
5546 else if (is_tv)
79e53945 5547 /* XXX: just matching BIOS for now */
43565a06 5548 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5549 dpll |= 3;
a7615030 5550 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5551 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5552 else
5553 dpll |= PLL_REF_INPUT_DREFCLK;
5554
de13a2e3
PZ		 5555 return dpll;
5556}
5557
5558static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5559 int x, int y,
5560 struct drm_framebuffer *fb)
5561{
5562 struct drm_device *dev = crtc->dev;
5563 struct drm_i915_private *dev_priv = dev->dev_private;
5564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5565 struct drm_display_mode *adjusted_mode =
5566 &intel_crtc->config.adjusted_mode;
5567 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5568 int pipe = intel_crtc->pipe;
5569 int plane = intel_crtc->plane;
5570 int num_connectors = 0;
5571 intel_clock_t clock, reduced_clock;
5572 u32 dpll, fp = 0, fp2 = 0;
e2f12b07 5573 bool ok, has_reduced_clock = false;
8b47047b 5574 bool is_lvds = false;
de13a2e3 5575 struct intel_encoder *encoder;
de13a2e3 5576 int ret;
01a415fd 5577 bool dither, fdi_config_ok;
de13a2e3
PZ		 5578
5579 for_each_encoder_on_crtc(dev, crtc, encoder) {
5580 switch (encoder->type) {
5581 case INTEL_OUTPUT_LVDS:
5582 is_lvds = true;
5583 break;
de13a2e3
PZ		 5584 }
5585
5586 num_connectors++;
a07d6787 5587 }
79e53945 5588
5dc5298b
PZ		 5589 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5590 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5591
6cf86a5e
DV		 5592 intel_crtc->cpu_transcoder = pipe;
5593
de13a2e3
PZ		 5594 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5595 &has_reduced_clock, &reduced_clock);
5596 if (!ok) {
5597 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5598 return -EINVAL;
79e53945 5599 }
f47709a9
DV		 5600 /* Compat-code for transition, will disappear. */
5601 if (!intel_crtc->config.clock_set) {
5602 intel_crtc->config.dpll.n = clock.n;
5603 intel_crtc->config.dpll.m1 = clock.m1;
5604 intel_crtc->config.dpll.m2 = clock.m2;
5605 intel_crtc->config.dpll.p1 = clock.p1;
5606 intel_crtc->config.dpll.p2 = clock.p2;
5607 }
79e53945 5608
de13a2e3
PZ		 5609 /* Ensure that the cursor is valid for the new mode before changing... */
5610 intel_crtc_update_cursor(crtc, true);
5611
5612 /* determine panel color depth */
4e53c2e0 5613 dither = intel_crtc->config.dither;
de13a2e3
PZ		 5614 if (is_lvds && dev_priv->lvds_dither)
5615 dither = true;
5616
5617 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5618 if (has_reduced_clock)
5619 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5620 reduced_clock.m2;
5621
6cc5f341 5622 dpll = ironlake_compute_dpll(intel_crtc, &clock, fp);
79e53945 5623
f7cb34d4 5624 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5625 drm_mode_debug_printmodeline(mode);
5626
5dc5298b 5627 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5628 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5629 struct intel_pch_pll *pll;
4b645f14 5630
ee7b9f93
JB		 5631 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5632 if (pll == NULL) {
5633 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5634 pipe);
4b645f14
JB		 5635 return -EINVAL;
5636 }
ee7b9f93
JB		 5637 } else
5638 intel_put_pch_pll(intel_crtc);
79e53945 5639
03afc4a2
DV		 5640 if (intel_crtc->config.has_dp_encoder)
5641 intel_dp_set_m_n(intel_crtc);
79e53945 5642
dafd226c
DV		 5643 for_each_encoder_on_crtc(dev, crtc, encoder)
5644 if (encoder->pre_pll_enable)
5645 encoder->pre_pll_enable(encoder);
79e53945 5646
ee7b9f93
JB		 5647 if (intel_crtc->pch_pll) {
5648 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5649
32f9d658 5650 /* Wait for the clocks to stabilize. */
ee7b9f93 5651 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5652 udelay(150);
5653
8febb297
EA		 5654 /* The pixel multiplier can only be updated once the
5655 * DPLL is enabled and the clocks are stable.
5656 *
5657 * So write it again.
5658 */
ee7b9f93 5659 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5660 }
79e53945 5661
5eddb70b 5662 intel_crtc->lowfreq_avail = false;
ee7b9f93 5663 if (intel_crtc->pch_pll) {
4b645f14 5664 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5665 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5666 intel_crtc->lowfreq_avail = true;
4b645f14 5667 } else {
ee7b9f93 5668 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5669 }
5670 }
5671
b0e77b9c 5672 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5673
01a415fd
DV		 5674 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5675 * ironlake_check_fdi_lanes. */
6cf86a5e
DV		 5676 intel_crtc->fdi_lanes = 0;
5677 if (intel_crtc->config.has_pch_encoder)
5678 ironlake_fdi_set_m_n(crtc);
2c07245f 5679
01a415fd 5680 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5681
c8203565 5682 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5683
9d0498a2 5684 intel_wait_for_vblank(dev, pipe);
79e53945 5685
a1f9e77e
PZ		 5686 /* Set up the display plane register */
5687 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5688 POSTING_READ(DSPCNTR(plane));
79e53945 5689
94352cf9 5690 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5691
5692 intel_update_watermarks(dev);
5693
1f8eeabf
ED		 5694 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5695
01a415fd 5696 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5697}
5698
0e8ffe1b
DV		 5699static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5700 struct intel_crtc_config *pipe_config)
5701{
5702 struct drm_device *dev = crtc->base.dev;
5703 struct drm_i915_private *dev_priv = dev->dev_private;
5704 uint32_t tmp;
5705
5706 tmp = I915_READ(PIPECONF(crtc->pipe));
5707 if (!(tmp & PIPECONF_ENABLE))
5708 return false;
5709
88adfff1
DV		 5710 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5711 pipe_config->has_pch_encoder = true;
5712
0e8ffe1b
DV		 5713 return true;
5714}
5715
d6dd9eb1
DV		 5716static void haswell_modeset_global_resources(struct drm_device *dev)
5717{
5718 struct drm_i915_private *dev_priv = dev->dev_private;
5719 bool enable = false;
5720 struct intel_crtc *crtc;
5721 struct intel_encoder *encoder;
5722
5723 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5724 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5725 enable = true;
5726 /* XXX: Should check for edp transcoder here, but thanks to init
5727 * sequence that's not yet available. Just in case desktop eDP
5728 * on PORT D is possible on haswell, too. */
5729 }
5730
5731 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5732 base.head) {
5733 if (encoder->type != INTEL_OUTPUT_EDP &&
5734 encoder->connectors_active)
5735 enable = true;
5736 }
5737
5738 /* Even the eDP panel fitter is outside the always-on well. */
5739 if (dev_priv->pch_pf_size)
5740 enable = true;
5741
5742 intel_set_power_well(dev, enable);
5743}
5744
09b4ddf9 5745static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5746 int x, int y,
5747 struct drm_framebuffer *fb)
5748{
5749 struct drm_device *dev = crtc->dev;
5750 struct drm_i915_private *dev_priv = dev->dev_private;
5751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5752 struct drm_display_mode *adjusted_mode =
5753 &intel_crtc->config.adjusted_mode;
5754 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5755 int pipe = intel_crtc->pipe;
5756 int plane = intel_crtc->plane;
5757 int num_connectors = 0;
8b47047b 5758 bool is_cpu_edp = false;
09b4ddf9 5759 struct intel_encoder *encoder;
09b4ddf9
PZ		 5760 int ret;
5761 bool dither;
5762
5763 for_each_encoder_on_crtc(dev, crtc, encoder) {
5764 switch (encoder->type) {
09b4ddf9 5765 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5766 if (!intel_encoder_is_pch_edp(&encoder->base))
5767 is_cpu_edp = true;
5768 break;
5769 }
5770
5771 num_connectors++;
5772 }
5773
bba2181c
DV		 5774 if (is_cpu_edp)
5775 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5776 else
5777 intel_crtc->cpu_transcoder = pipe;
5778
5dc5298b
PZ		 5779 /* We are not sure yet this won't happen. */
5780 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5781 INTEL_PCH_TYPE(dev));
5782
5783 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5784 num_connectors, pipe_name(pipe));
5785
702e7a56 5786 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5787 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5788
5789 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5790
6441ab5f
PZ		 5791 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5792 return -EINVAL;
5793
09b4ddf9
PZ		 5794 /* Ensure that the cursor is valid for the new mode before changing... */
5795 intel_crtc_update_cursor(crtc, true);
5796
5797 /* determine panel color depth */
4e53c2e0 5798 dither = intel_crtc->config.dither;
09b4ddf9 5799
09b4ddf9
PZ		 5800 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5801 drm_mode_debug_printmodeline(mode);
5802
03afc4a2
DV		 5803 if (intel_crtc->config.has_dp_encoder)
5804 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5805
5806 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5807
5808 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5809
6cf86a5e
DV		 5810 if (intel_crtc->config.has_pch_encoder)
5811 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5812
ee2b0b38 5813 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5814
50f3b016 5815 intel_set_pipe_csc(crtc);
86d3efce 5816
09b4ddf9 5817 /* Set up the display plane register */
86d3efce 5818 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5819 POSTING_READ(DSPCNTR(plane));
5820
5821 ret = intel_pipe_set_base(crtc, x, y, fb);
5822
5823 intel_update_watermarks(dev);
5824
5825 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5826
1f803ee5 5827 return ret;
79e53945
JB		 5828}
5829
0e8ffe1b
DV		 5830static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5831 struct intel_crtc_config *pipe_config)
5832{
5833 struct drm_device *dev = crtc->base.dev;
5834 struct drm_i915_private *dev_priv = dev->dev_private;
5835 uint32_t tmp;
5836
5837 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
5838 if (!(tmp & PIPECONF_ENABLE))
5839 return false;
5840
88adfff1
DV		 5841 /*
5842 * aswell has only FDI/PCH transcoder A. It is which is connected to
5843 * DDI E. So just check whether this pipe is wired to DDI E and whether
5844 * the PCH transcoder is on.
5845 */
5846 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
5847 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5848 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5849 pipe_config->has_pch_encoder = true;
5850
5851
0e8ffe1b
DV		 5852 return true;
5853}
5854
f564048e 5855static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5856 int x, int y,
94352cf9 5857 struct drm_framebuffer *fb)
f564048e
EA		 5858{
5859 struct drm_device *dev = crtc->dev;
5860 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5861 struct drm_encoder_helper_funcs *encoder_funcs;
5862 struct intel_encoder *encoder;
0b701d27 5863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5864 struct drm_display_mode *adjusted_mode =
5865 &intel_crtc->config.adjusted_mode;
5866 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5867 int pipe = intel_crtc->pipe;
f564048e
EA		 5868 int ret;
5869
0b701d27 5870 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5871
b8cecdf5
DV		 5872 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5873
79e53945 5874 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5875
9256aa19
DV		 5876 if (ret != 0)
5877 return ret;
5878
5879 for_each_encoder_on_crtc(dev, crtc, encoder) {
5880 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5881 encoder->base.base.id,
5882 drm_get_encoder_name(&encoder->base),
5883 mode->base.id, mode->name);
6cc5f341
DV		 5884 if (encoder->mode_set) {
5885 encoder->mode_set(encoder);
5886 } else {
5887 encoder_funcs = encoder->base.helper_private;
5888 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5889 }
9256aa19
DV		 5890 }
5891
5892 return 0;
79e53945
JB		 5893}
5894
3a9627f4
WF		 5895static bool intel_eld_uptodate(struct drm_connector *connector,
5896 int reg_eldv, uint32_t bits_eldv,
5897 int reg_elda, uint32_t bits_elda,
5898 int reg_edid)
5899{
5900 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5901 uint8_t *eld = connector->eld;
5902 uint32_t i;
5903
5904 i = I915_READ(reg_eldv);
5905 i &= bits_eldv;
5906
5907 if (!eld[0])
5908 return !i;
5909
5910 if (!i)
5911 return false;
5912
5913 i = I915_READ(reg_elda);
5914 i &= ~bits_elda;
5915 I915_WRITE(reg_elda, i);
5916
5917 for (i = 0; i < eld[2]; i++)
5918 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5919 return false;
5920
5921 return true;
5922}
5923
e0dac65e
WF		 5924static void g4x_write_eld(struct drm_connector *connector,
5925 struct drm_crtc *crtc)
5926{
5927 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5928 uint8_t *eld = connector->eld;
5929 uint32_t eldv;
5930 uint32_t len;
5931 uint32_t i;
5932
5933 i = I915_READ(G4X_AUD_VID_DID);
5934
5935 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5936 eldv = G4X_ELDV_DEVCL_DEVBLC;
5937 else
5938 eldv = G4X_ELDV_DEVCTG;
5939
3a9627f4
WF		 5940 if (intel_eld_uptodate(connector,
5941 G4X_AUD_CNTL_ST, eldv,
5942 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5943 G4X_HDMIW_HDMIEDID))
5944 return;
5945
e0dac65e
WF		 5946 i = I915_READ(G4X_AUD_CNTL_ST);
5947 i &= ~(eldv | G4X_ELD_ADDR);
5948 len = (i >> 9) & 0x1f; /* ELD buffer size */
5949 I915_WRITE(G4X_AUD_CNTL_ST, i);
5950
5951 if (!eld[0])
5952 return;
5953
5954 len = min_t(uint8_t, eld[2], len);
5955 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5956 for (i = 0; i < len; i++)
5957 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5958
5959 i = I915_READ(G4X_AUD_CNTL_ST);
5960 i |= eldv;
5961 I915_WRITE(G4X_AUD_CNTL_ST, i);
5962}
5963
83358c85
WX		 5964static void haswell_write_eld(struct drm_connector *connector,
5965 struct drm_crtc *crtc)
5966{
5967 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5968 uint8_t *eld = connector->eld;
5969 struct drm_device *dev = crtc->dev;
7b9f35a6 5970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5971 uint32_t eldv;
5972 uint32_t i;
5973 int len;
5974 int pipe = to_intel_crtc(crtc)->pipe;
5975 int tmp;
5976
5977 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5978 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5979 int aud_config = HSW_AUD_CFG(pipe);
5980 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5981
5982
5983 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5984
5985 /* Audio output enable */
5986 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5987 tmp = I915_READ(aud_cntrl_st2);
5988 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5989 I915_WRITE(aud_cntrl_st2, tmp);
5990
5991 /* Wait for 1 vertical blank */
5992 intel_wait_for_vblank(dev, pipe);
5993
5994 /* Set ELD valid state */
5995 tmp = I915_READ(aud_cntrl_st2);
5996 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5997 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5998 I915_WRITE(aud_cntrl_st2, tmp);
5999 tmp = I915_READ(aud_cntrl_st2);
6000 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6001
6002 /* Enable HDMI mode */
6003 tmp = I915_READ(aud_config);
6004 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6005 /* clear N_programing_enable and N_value_index */
6006 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6007 I915_WRITE(aud_config, tmp);
6008
6009 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6010
6011 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6012 intel_crtc->eld_vld = true;
83358c85
WX		 6013
6014 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6015 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6016 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6017 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6018 } else
6019 I915_WRITE(aud_config, 0);
6020
6021 if (intel_eld_uptodate(connector,
6022 aud_cntrl_st2, eldv,
6023 aud_cntl_st, IBX_ELD_ADDRESS,
6024 hdmiw_hdmiedid))
6025 return;
6026
6027 i = I915_READ(aud_cntrl_st2);
6028 i &= ~eldv;
6029 I915_WRITE(aud_cntrl_st2, i);
6030
6031 if (!eld[0])
6032 return;
6033
6034 i = I915_READ(aud_cntl_st);
6035 i &= ~IBX_ELD_ADDRESS;
6036 I915_WRITE(aud_cntl_st, i);
6037 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6038 DRM_DEBUG_DRIVER("port num:%d\n", i);
6039
6040 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6041 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6042 for (i = 0; i < len; i++)
6043 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6044
6045 i = I915_READ(aud_cntrl_st2);
6046 i |= eldv;
6047 I915_WRITE(aud_cntrl_st2, i);
6048
6049}
6050
e0dac65e
WF		 6051static void ironlake_write_eld(struct drm_connector *connector,
6052 struct drm_crtc *crtc)
6053{
6054 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6055 uint8_t *eld = connector->eld;
6056 uint32_t eldv;
6057 uint32_t i;
6058 int len;
6059 int hdmiw_hdmiedid;
b6daa025 6060 int aud_config;
e0dac65e
WF		 6061 int aud_cntl_st;
6062 int aud_cntrl_st2;
9b138a83 6063 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6064
b3f33cbf 6065 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6066 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6067 aud_config = IBX_AUD_CFG(pipe);
6068 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6069 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6070 } else {
9b138a83
WX		 6071 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6072 aud_config = CPT_AUD_CFG(pipe);
6073 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6074 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6075 }
6076
9b138a83 6077 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6078
6079 i = I915_READ(aud_cntl_st);
9b138a83 6080 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6081 if (!i) {
6082 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6083 /* operate blindly on all ports */
1202b4c6
WF		 6084 eldv = IBX_ELD_VALIDB;
6085 eldv |= IBX_ELD_VALIDB << 4;
6086 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6087 } else {
6088 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6089 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6090 }
6091
3a9627f4
WF		 6092 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6093 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6094 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6095 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6096 } else
6097 I915_WRITE(aud_config, 0);
e0dac65e 6098
3a9627f4
WF		 6099 if (intel_eld_uptodate(connector,
6100 aud_cntrl_st2, eldv,
6101 aud_cntl_st, IBX_ELD_ADDRESS,
6102 hdmiw_hdmiedid))
6103 return;
6104
e0dac65e
WF		 6105 i = I915_READ(aud_cntrl_st2);
6106 i &= ~eldv;
6107 I915_WRITE(aud_cntrl_st2, i);
6108
6109 if (!eld[0])
6110 return;
6111
e0dac65e 6112 i = I915_READ(aud_cntl_st);
1202b4c6 6113 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6114 I915_WRITE(aud_cntl_st, i);
6115
6116 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6117 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6118 for (i = 0; i < len; i++)
6119 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6120
6121 i = I915_READ(aud_cntrl_st2);
6122 i |= eldv;
6123 I915_WRITE(aud_cntrl_st2, i);
6124}
6125
6126void intel_write_eld(struct drm_encoder *encoder,
6127 struct drm_display_mode *mode)
6128{
6129 struct drm_crtc *crtc = encoder->crtc;
6130 struct drm_connector *connector;
6131 struct drm_device *dev = encoder->dev;
6132 struct drm_i915_private *dev_priv = dev->dev_private;
6133
6134 connector = drm_select_eld(encoder, mode);
6135 if (!connector)
6136 return;
6137
6138 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6139 connector->base.id,
6140 drm_get_connector_name(connector),
6141 connector->encoder->base.id,
6142 drm_get_encoder_name(connector->encoder));
6143
6144 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6145
6146 if (dev_priv->display.write_eld)
6147 dev_priv->display.write_eld(connector, crtc);
6148}
6149
79e53945
JB		 6150/** Loads the palette/gamma unit for the CRTC with the prepared values */
6151void intel_crtc_load_lut(struct drm_crtc *crtc)
6152{
6153 struct drm_device *dev = crtc->dev;
6154 struct drm_i915_private *dev_priv = dev->dev_private;
6155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6156 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6157 int i;
6158
6159 /* The clocks have to be on to load the palette. */
aed3f09d 6160 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6161 return;
6162
f2b115e6 6163 /* use legacy palette for Ironlake */
bad720ff 6164 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6165 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6166
79e53945
JB		 6167 for (i = 0; i < 256; i++) {
6168 I915_WRITE(palreg + 4 * i,
6169 (intel_crtc->lut_r[i] << 16) |
6170 (intel_crtc->lut_g[i] << 8) |
6171 intel_crtc->lut_b[i]);
6172 }
6173}
6174
560b85bb
CW		 6175static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6176{
6177 struct drm_device *dev = crtc->dev;
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180 bool visible = base != 0;
6181 u32 cntl;
6182
6183 if (intel_crtc->cursor_visible == visible)
6184 return;
6185
9db4a9c7 6186 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6187 if (visible) {
6188 /* On these chipsets we can only modify the base whilst
6189 * the cursor is disabled.
6190 */
9db4a9c7 6191 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6192
6193 cntl &= ~(CURSOR_FORMAT_MASK);
6194 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6195 cntl |= CURSOR_ENABLE |
6196 CURSOR_GAMMA_ENABLE |
6197 CURSOR_FORMAT_ARGB;
6198 } else
6199 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6200 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6201
6202 intel_crtc->cursor_visible = visible;
6203}
6204
6205static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6206{
6207 struct drm_device *dev = crtc->dev;
6208 struct drm_i915_private *dev_priv = dev->dev_private;
6209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6210 int pipe = intel_crtc->pipe;
6211 bool visible = base != 0;
6212
6213 if (intel_crtc->cursor_visible != visible) {
548f245b 6214 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6215 if (base) {
6216 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6217 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6218 cntl |= pipe << 28; /* Connect to correct pipe */
6219 } else {
6220 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6221 cntl |= CURSOR_MODE_DISABLE;
6222 }
9db4a9c7 6223 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6224
6225 intel_crtc->cursor_visible = visible;
6226 }
6227 /* and commit changes on next vblank */
9db4a9c7 6228 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6229}
6230
65a21cd6
JB		 6231static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6232{
6233 struct drm_device *dev = crtc->dev;
6234 struct drm_i915_private *dev_priv = dev->dev_private;
6235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6236 int pipe = intel_crtc->pipe;
6237 bool visible = base != 0;
6238
6239 if (intel_crtc->cursor_visible != visible) {
6240 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6241 if (base) {
6242 cntl &= ~CURSOR_MODE;
6243 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6244 } else {
6245 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6246 cntl |= CURSOR_MODE_DISABLE;
6247 }
86d3efce
VS		 6248 if (IS_HASWELL(dev))
6249 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6250 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6251
6252 intel_crtc->cursor_visible = visible;
6253 }
6254 /* and commit changes on next vblank */
6255 I915_WRITE(CURBASE_IVB(pipe), base);
6256}
6257
cda4b7d3 6258/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6259static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6260 bool on)
cda4b7d3
CW		 6261{
6262 struct drm_device *dev = crtc->dev;
6263 struct drm_i915_private *dev_priv = dev->dev_private;
6264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6265 int pipe = intel_crtc->pipe;
6266 int x = intel_crtc->cursor_x;
6267 int y = intel_crtc->cursor_y;
560b85bb 6268 u32 base, pos;
cda4b7d3
CW		 6269 bool visible;
6270
6271 pos = 0;
6272
6b383a7f 6273 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6274 base = intel_crtc->cursor_addr;
6275 if (x > (int) crtc->fb->width)
6276 base = 0;
6277
6278 if (y > (int) crtc->fb->height)
6279 base = 0;
6280 } else
6281 base = 0;
6282
6283 if (x < 0) {
6284 if (x + intel_crtc->cursor_width < 0)
6285 base = 0;
6286
6287 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6288 x = -x;
6289 }
6290 pos |= x << CURSOR_X_SHIFT;
6291
6292 if (y < 0) {
6293 if (y + intel_crtc->cursor_height < 0)
6294 base = 0;
6295
6296 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6297 y = -y;
6298 }
6299 pos |= y << CURSOR_Y_SHIFT;
6300
6301 visible = base != 0;
560b85bb 6302 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6303 return;
6304
0cd83aa9 6305 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6306 I915_WRITE(CURPOS_IVB(pipe), pos);
6307 ivb_update_cursor(crtc, base);
6308 } else {
6309 I915_WRITE(CURPOS(pipe), pos);
6310 if (IS_845G(dev) || IS_I865G(dev))
6311 i845_update_cursor(crtc, base);
6312 else
6313 i9xx_update_cursor(crtc, base);
6314 }
cda4b7d3
CW		 6315}
6316
79e53945 6317static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6318 struct drm_file *file,
79e53945
JB		 6319 uint32_t handle,
6320 uint32_t width, uint32_t height)
6321{
6322 struct drm_device *dev = crtc->dev;
6323 struct drm_i915_private *dev_priv = dev->dev_private;
6324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6325 struct drm_i915_gem_object *obj;
cda4b7d3 6326 uint32_t addr;
3f8bc370 6327 int ret;
79e53945 6328
79e53945
JB		 6329 /* if we want to turn off the cursor ignore width and height */
6330 if (!handle) {
28c97730 6331 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6332 addr = 0;
05394f39 6333 obj = NULL;
5004417d 6334 mutex_lock(&dev->struct_mutex);
3f8bc370 6335 goto finish;
79e53945
JB		 6336 }
6337
6338 /* Currently we only support 64x64 cursors */
6339 if (width != 64 || height != 64) {
6340 DRM_ERROR("we currently only support 64x64 cursors\n");
6341 return -EINVAL;
6342 }
6343
05394f39 6344 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6345 if (&obj->base == NULL)
79e53945
JB		 6346 return -ENOENT;
6347
05394f39 6348 if (obj->base.size < width * height * 4) {
79e53945 6349 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6350 ret = -ENOMEM;
6351 goto fail;
79e53945
JB		 6352 }
6353
71acb5eb 6354 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6355 mutex_lock(&dev->struct_mutex);
b295d1b6 6356 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6357 unsigned alignment;
6358
d9e86c0e
CW		 6359 if (obj->tiling_mode) {
6360 DRM_ERROR("cursor cannot be tiled\n");
6361 ret = -EINVAL;
6362 goto fail_locked;
6363 }
6364
693db184
CW		 6365 /* Note that the w/a also requires 2 PTE of padding following
6366 * the bo. We currently fill all unused PTE with the shadow
6367 * page and so we should always have valid PTE following the
6368 * cursor preventing the VT-d warning.
6369 */
6370 alignment = 0;
6371 if (need_vtd_wa(dev))
6372 alignment = 64*1024;
6373
6374 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6375 if (ret) {
6376 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6377 goto fail_locked;
e7b526bb
CW		 6378 }
6379
d9e86c0e
CW		 6380 ret = i915_gem_object_put_fence(obj);
6381 if (ret) {
2da3b9b9 6382 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6383 goto fail_unpin;
6384 }
6385
05394f39 6386 addr = obj->gtt_offset;
71acb5eb 6387 } else {
6eeefaf3 6388 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6389 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6390 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6391 align);
71acb5eb
DA		 6392 if (ret) {
6393 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6394 goto fail_locked;
71acb5eb 6395 }
05394f39 6396 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6397 }
6398
a6c45cf0 6399 if (IS_GEN2(dev))
14b60391
JB		 6400 I915_WRITE(CURSIZE, (height << 12) | width);
6401
3f8bc370 6402 finish:
3f8bc370 6403 if (intel_crtc->cursor_bo) {
b295d1b6 6404 if (dev_priv->info->cursor_needs_physical) {
05394f39 6405 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6406 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6407 } else
6408 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6409 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6410 }
80824003 6411
7f9872e0 6412 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6413
6414 intel_crtc->cursor_addr = addr;
05394f39 6415 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6416 intel_crtc->cursor_width = width;
6417 intel_crtc->cursor_height = height;
6418
6b383a7f 6419 intel_crtc_update_cursor(crtc, true);
3f8bc370 6420
79e53945 6421 return 0;
e7b526bb 6422fail_unpin:
05394f39 6423 i915_gem_object_unpin(obj);
7f9872e0 6424fail_locked:
34b8686e 6425 mutex_unlock(&dev->struct_mutex);
bc9025bd 6426fail:
05394f39 6427 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6428 return ret;
79e53945
JB		 6429}
6430
6431static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6432{
79e53945 6433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6434
cda4b7d3
CW		 6435 intel_crtc->cursor_x = x;
6436 intel_crtc->cursor_y = y;
652c393a 6437
6b383a7f 6438 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6439
6440 return 0;
6441}
6442
6443/** Sets the color ramps on behalf of RandR */
6444void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6445 u16 blue, int regno)
6446{
6447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6448
6449 intel_crtc->lut_r[regno] = red >> 8;
6450 intel_crtc->lut_g[regno] = green >> 8;
6451 intel_crtc->lut_b[regno] = blue >> 8;
6452}
6453
b8c00ac5
DA		 6454void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6455 u16 *blue, int regno)
6456{
6457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6458
6459 *red = intel_crtc->lut_r[regno] << 8;
6460 *green = intel_crtc->lut_g[regno] << 8;
6461 *blue = intel_crtc->lut_b[regno] << 8;
6462}
6463
79e53945 6464static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6465 u16 *blue, uint32_t start, uint32_t size)
79e53945 6466{
7203425a 6467 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6469
7203425a 6470 for (i = start; i < end; i++) {
79e53945
JB		 6471 intel_crtc->lut_r[i] = red[i] >> 8;
6472 intel_crtc->lut_g[i] = green[i] >> 8;
6473 intel_crtc->lut_b[i] = blue[i] >> 8;
6474 }
6475
6476 intel_crtc_load_lut(crtc);
6477}
6478
79e53945
JB		 6479/* VESA 640x480x72Hz mode to set on the pipe */
6480static struct drm_display_mode load_detect_mode = {
6481 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6482 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6483};
6484
d2dff872
CW		 6485static struct drm_framebuffer *
6486intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6487 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6488 struct drm_i915_gem_object *obj)
6489{
6490 struct intel_framebuffer *intel_fb;
6491 int ret;
6492
6493 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6494 if (!intel_fb) {
6495 drm_gem_object_unreference_unlocked(&obj->base);
6496 return ERR_PTR(-ENOMEM);
6497 }
6498
6499 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6500 if (ret) {
6501 drm_gem_object_unreference_unlocked(&obj->base);
6502 kfree(intel_fb);
6503 return ERR_PTR(ret);
6504 }
6505
6506 return &intel_fb->base;
6507}
6508
6509static u32
6510intel_framebuffer_pitch_for_width(int width, int bpp)
6511{
6512 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6513 return ALIGN(pitch, 64);
6514}
6515
6516static u32
6517intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6518{
6519 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6520 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6521}
6522
6523static struct drm_framebuffer *
6524intel_framebuffer_create_for_mode(struct drm_device *dev,
6525 struct drm_display_mode *mode,
6526 int depth, int bpp)
6527{
6528 struct drm_i915_gem_object *obj;
0fed39bd 6529 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6530
6531 obj = i915_gem_alloc_object(dev,
6532 intel_framebuffer_size_for_mode(mode, bpp));
6533 if (obj == NULL)
6534 return ERR_PTR(-ENOMEM);
6535
6536 mode_cmd.width = mode->hdisplay;
6537 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6538 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6539 bpp);
5ca0c34a 6540 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6541
6542 return intel_framebuffer_create(dev, &mode_cmd, obj);
6543}
6544
6545static struct drm_framebuffer *
6546mode_fits_in_fbdev(struct drm_device *dev,
6547 struct drm_display_mode *mode)
6548{
6549 struct drm_i915_private *dev_priv = dev->dev_private;
6550 struct drm_i915_gem_object *obj;
6551 struct drm_framebuffer *fb;
6552
6553 if (dev_priv->fbdev == NULL)
6554 return NULL;
6555
6556 obj = dev_priv->fbdev->ifb.obj;
6557 if (obj == NULL)
6558 return NULL;
6559
6560 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6561 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6562 fb->bits_per_pixel))
d2dff872
CW		 6563 return NULL;
6564
01f2c773 6565 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6566 return NULL;
6567
6568 return fb;
6569}
6570
d2434ab7 6571bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6572 struct drm_display_mode *mode,
8261b191 6573 struct intel_load_detect_pipe *old)
79e53945
JB		 6574{
6575 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6576 struct intel_encoder *intel_encoder =
6577 intel_attached_encoder(connector);
79e53945 6578 struct drm_crtc *possible_crtc;
4ef69c7a 6579 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6580 struct drm_crtc *crtc = NULL;
6581 struct drm_device *dev = encoder->dev;
94352cf9 6582 struct drm_framebuffer *fb;
79e53945
JB		 6583 int i = -1;
6584
d2dff872
CW		 6585 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6586 connector->base.id, drm_get_connector_name(connector),
6587 encoder->base.id, drm_get_encoder_name(encoder));
6588
79e53945
JB		 6589 /*
6590 * Algorithm gets a little messy:
7a5e4805 6591 *
79e53945
JB		 6592 * - if the connector already has an assigned crtc, use it (but make
6593 * sure it's on first)
7a5e4805 6594 *
79e53945
JB		 6595 * - try to find the first unused crtc that can drive this connector,
6596 * and use that if we find one
79e53945
JB		 6597 */
6598
6599 /* See if we already have a CRTC for this connector */
6600 if (encoder->crtc) {
6601 crtc = encoder->crtc;
8261b191 6602
7b24056b
DV		 6603 mutex_lock(&crtc->mutex);
6604
24218aac 6605 old->dpms_mode = connector->dpms;
8261b191
CW		 6606 old->load_detect_temp = false;
6607
6608 /* Make sure the crtc and connector are running */
24218aac
DV		 6609 if (connector->dpms != DRM_MODE_DPMS_ON)
6610 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6611
7173188d 6612 return true;
79e53945
JB		 6613 }
6614
6615 /* Find an unused one (if possible) */
6616 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6617 i++;
6618 if (!(encoder->possible_crtcs & (1 << i)))
6619 continue;
6620 if (!possible_crtc->enabled) {
6621 crtc = possible_crtc;
6622 break;
6623 }
79e53945
JB		 6624 }
6625
6626 /*
6627 * If we didn't find an unused CRTC, don't use any.
6628 */
6629 if (!crtc) {
7173188d
CW		 6630 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6631 return false;
79e53945
JB		 6632 }
6633
7b24056b 6634 mutex_lock(&crtc->mutex);
fc303101
DV		 6635 intel_encoder->new_crtc = to_intel_crtc(crtc);
6636 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6637
6638 intel_crtc = to_intel_crtc(crtc);
24218aac 6639 old->dpms_mode = connector->dpms;
8261b191 6640 old->load_detect_temp = true;
d2dff872 6641 old->release_fb = NULL;
79e53945 6642
6492711d
CW		 6643 if (!mode)
6644 mode = &load_detect_mode;
79e53945 6645
d2dff872
CW		 6646 /* We need a framebuffer large enough to accommodate all accesses
6647 * that the plane may generate whilst we perform load detection.
6648 * We can not rely on the fbcon either being present (we get called
6649 * during its initialisation to detect all boot displays, or it may
6650 * not even exist) or that it is large enough to satisfy the
6651 * requested mode.
6652 */
94352cf9
DV		 6653 fb = mode_fits_in_fbdev(dev, mode);
6654 if (fb == NULL) {
d2dff872 6655 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6656 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6657 old->release_fb = fb;
d2dff872
CW		 6658 } else
6659 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6660 if (IS_ERR(fb)) {
d2dff872 6661 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6662 mutex_unlock(&crtc->mutex);
0e8b3d3e 6663 return false;
79e53945 6664 }
79e53945 6665
c0c36b94 6666 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6667 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6668 if (old->release_fb)
6669 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6670 mutex_unlock(&crtc->mutex);
0e8b3d3e 6671 return false;
79e53945 6672 }
7173188d 6673
79e53945 6674 /* let the connector get through one full cycle before testing */
9d0498a2 6675 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6676 return true;
79e53945
JB		 6677}
6678
d2434ab7 6679void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6680 struct intel_load_detect_pipe *old)
79e53945 6681{
d2434ab7
DV		 6682 struct intel_encoder *intel_encoder =
6683 intel_attached_encoder(connector);
4ef69c7a 6684 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6685 struct drm_crtc *crtc = encoder->crtc;
79e53945 6686
d2dff872
CW		 6687 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6688 connector->base.id, drm_get_connector_name(connector),
6689 encoder->base.id, drm_get_encoder_name(encoder));
6690
8261b191 6691 if (old->load_detect_temp) {
fc303101
DV		 6692 to_intel_connector(connector)->new_encoder = NULL;
6693 intel_encoder->new_crtc = NULL;
6694 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6695
36206361
DV		 6696 if (old->release_fb) {
6697 drm_framebuffer_unregister_private(old->release_fb);
6698 drm_framebuffer_unreference(old->release_fb);
6699 }
d2dff872 6700
67c96400 6701 mutex_unlock(&crtc->mutex);
0622a53c 6702 return;
79e53945
JB		 6703 }
6704
c751ce4f 6705 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6706 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6707 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6708
6709 mutex_unlock(&crtc->mutex);
79e53945
JB		 6710}
6711
6712/* Returns the clock of the currently programmed mode of the given pipe. */
6713static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6714{
6715 struct drm_i915_private *dev_priv = dev->dev_private;
6716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6717 int pipe = intel_crtc->pipe;
548f245b 6718 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6719 u32 fp;
6720 intel_clock_t clock;
6721
6722 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6723 fp = I915_READ(FP0(pipe));
79e53945 6724 else
39adb7a5 6725 fp = I915_READ(FP1(pipe));
79e53945
JB		 6726
6727 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6728 if (IS_PINEVIEW(dev)) {
6729 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6730 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6731 } else {
6732 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6733 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6734 }
6735
a6c45cf0 6736 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6737 if (IS_PINEVIEW(dev))
6738 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6739 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6740 else
6741 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6742 DPLL_FPA01_P1_POST_DIV_SHIFT);
6743
6744 switch (dpll & DPLL_MODE_MASK) {
6745 case DPLLB_MODE_DAC_SERIAL:
6746 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6747 5 : 10;
6748 break;
6749 case DPLLB_MODE_LVDS:
6750 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6751 7 : 14;
6752 break;
6753 default:
28c97730 6754 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6755 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6756 return 0;
6757 }
6758
6759 /* XXX: Handle the 100Mhz refclk */
2177832f 6760 intel_clock(dev, 96000, &clock);
79e53945
JB		 6761 } else {
6762 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6763
6764 if (is_lvds) {
6765 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6766 DPLL_FPA01_P1_POST_DIV_SHIFT);
6767 clock.p2 = 14;
6768
6769 if ((dpll & PLL_REF_INPUT_MASK) ==
6770 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6771 /* XXX: might not be 66MHz */
2177832f 6772 intel_clock(dev, 66000, &clock);
79e53945 6773 } else
2177832f 6774 intel_clock(dev, 48000, &clock);
79e53945
JB		 6775 } else {
6776 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6777 clock.p1 = 2;
6778 else {
6779 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6780 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6781 }
6782 if (dpll & PLL_P2_DIVIDE_BY_4)
6783 clock.p2 = 4;
6784 else
6785 clock.p2 = 2;
6786
2177832f 6787 intel_clock(dev, 48000, &clock);
79e53945
JB		 6788 }
6789 }
6790
6791 /* XXX: It would be nice to validate the clocks, but we can't reuse
6792 * i830PllIsValid() because it relies on the xf86_config connector
6793 * configuration being accurate, which it isn't necessarily.
6794 */
6795
6796 return clock.dot;
6797}
6798
6799/** Returns the currently programmed mode of the given pipe. */
6800struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6801 struct drm_crtc *crtc)
6802{
548f245b 6803 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6805 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6806 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6807 int htot = I915_READ(HTOTAL(cpu_transcoder));
6808 int hsync = I915_READ(HSYNC(cpu_transcoder));
6809 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6810 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6811
6812 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6813 if (!mode)
6814 return NULL;
6815
6816 mode->clock = intel_crtc_clock_get(dev, crtc);
6817 mode->hdisplay = (htot & 0xffff) + 1;
6818 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6819 mode->hsync_start = (hsync & 0xffff) + 1;
6820 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6821 mode->vdisplay = (vtot & 0xffff) + 1;
6822 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6823 mode->vsync_start = (vsync & 0xffff) + 1;
6824 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6825
6826 drm_mode_set_name(mode);
79e53945
JB		 6827
6828 return mode;
6829}
6830
3dec0095 6831static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6832{
6833 struct drm_device *dev = crtc->dev;
6834 drm_i915_private_t *dev_priv = dev->dev_private;
6835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6836 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6837 int dpll_reg = DPLL(pipe);
6838 int dpll;
652c393a 6839
bad720ff 6840 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6841 return;
6842
6843 if (!dev_priv->lvds_downclock_avail)
6844 return;
6845
dbdc6479 6846 dpll = I915_READ(dpll_reg);
652c393a 6847 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6848 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6849
8ac5a6d5 6850 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6851
6852 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6853 I915_WRITE(dpll_reg, dpll);
9d0498a2 6854 intel_wait_for_vblank(dev, pipe);
dbdc6479 6855
652c393a
JB		 6856 dpll = I915_READ(dpll_reg);
6857 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6858 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6859 }
652c393a
JB		 6860}
6861
6862static void intel_decrease_pllclock(struct drm_crtc *crtc)
6863{
6864 struct drm_device *dev = crtc->dev;
6865 drm_i915_private_t *dev_priv = dev->dev_private;
6866 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6867
bad720ff 6868 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6869 return;
6870
6871 if (!dev_priv->lvds_downclock_avail)
6872 return;
6873
6874 /*
6875 * Since this is called by a timer, we should never get here in
6876 * the manual case.
6877 */
6878 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6879 int pipe = intel_crtc->pipe;
6880 int dpll_reg = DPLL(pipe);
6881 int dpll;
f6e5b160 6882
44d98a61 6883 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6884
8ac5a6d5 6885 assert_panel_unlocked(dev_priv, pipe);
652c393a 6886
dc257cf1 6887 dpll = I915_READ(dpll_reg);
652c393a
JB		 6888 dpll |= DISPLAY_RATE_SELECT_FPA1;
6889 I915_WRITE(dpll_reg, dpll);
9d0498a2 6890 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6891 dpll = I915_READ(dpll_reg);
6892 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6893 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6894 }
6895
6896}
6897
f047e395
CW		 6898void intel_mark_busy(struct drm_device *dev)
6899{
f047e395
CW		 6900 i915_update_gfx_val(dev->dev_private);
6901}
6902
6903void intel_mark_idle(struct drm_device *dev)
652c393a 6904{
652c393a 6905 struct drm_crtc *crtc;
652c393a
JB		 6906
6907 if (!i915_powersave)
6908 return;
6909
652c393a 6910 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6911 if (!crtc->fb)
6912 continue;
6913
725a5b54 6914 intel_decrease_pllclock(crtc);
652c393a 6915 }
652c393a
JB		 6916}
6917
725a5b54 6918void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6919{
f047e395
CW		 6920 struct drm_device *dev = obj->base.dev;
6921 struct drm_crtc *crtc;
652c393a 6922
f047e395 6923 if (!i915_powersave)
acb87dfb
CW		 6924 return;
6925
652c393a
JB		 6926 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6927 if (!crtc->fb)
6928 continue;
6929
f047e395 6930 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6931 intel_increase_pllclock(crtc);
652c393a
JB		 6932 }
6933}
6934
79e53945
JB		 6935static void intel_crtc_destroy(struct drm_crtc *crtc)
6936{
6937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6938 struct drm_device *dev = crtc->dev;
6939 struct intel_unpin_work *work;
6940 unsigned long flags;
6941
6942 spin_lock_irqsave(&dev->event_lock, flags);
6943 work = intel_crtc->unpin_work;
6944 intel_crtc->unpin_work = NULL;
6945 spin_unlock_irqrestore(&dev->event_lock, flags);
6946
6947 if (work) {
6948 cancel_work_sync(&work->work);
6949 kfree(work);
6950 }
79e53945
JB		 6951
6952 drm_crtc_cleanup(crtc);
67e77c5a 6953
79e53945
JB		 6954 kfree(intel_crtc);
6955}
6956
6b95a207
KH		 6957static void intel_unpin_work_fn(struct work_struct *__work)
6958{
6959 struct intel_unpin_work *work =
6960 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6961 struct drm_device *dev = work->crtc->dev;
6b95a207 6962
b4a98e57 6963 mutex_lock(&dev->struct_mutex);
1690e1eb 6964 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6965 drm_gem_object_unreference(&work->pending_flip_obj->base);
6966 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6967
b4a98e57
CW		 6968 intel_update_fbc(dev);
6969 mutex_unlock(&dev->struct_mutex);
6970
6971 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6972 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6973
6b95a207
KH		 6974 kfree(work);
6975}
6976
1afe3e9d 6977static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6978 struct drm_crtc *crtc)
6b95a207
KH		 6979{
6980 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6982 struct intel_unpin_work *work;
6b95a207
KH		 6983 unsigned long flags;
6984
6985 /* Ignore early vblank irqs */
6986 if (intel_crtc == NULL)
6987 return;
6988
6989 spin_lock_irqsave(&dev->event_lock, flags);
6990 work = intel_crtc->unpin_work;
e7d841ca
CW		 6991
6992 /* Ensure we don't miss a work->pending update ... */
6993 smp_rmb();
6994
6995 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6996 spin_unlock_irqrestore(&dev->event_lock, flags);
6997 return;
6998 }
6999
e7d841ca
CW		 7000 /* and that the unpin work is consistent wrt ->pending. */
7001 smp_rmb();
7002
6b95a207 7003 intel_crtc->unpin_work = NULL;
6b95a207 7004
45a066eb
RC		 7005 if (work->event)
7006 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7007
0af7e4df
MK		 7008 drm_vblank_put(dev, intel_crtc->pipe);
7009
6b95a207
KH		 7010 spin_unlock_irqrestore(&dev->event_lock, flags);
7011
2c10d571 7012 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7013
7014 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7015
7016 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7017}
7018
1afe3e9d
JB		 7019void intel_finish_page_flip(struct drm_device *dev, int pipe)
7020{
7021 drm_i915_private_t *dev_priv = dev->dev_private;
7022 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7023
49b14a5c 7024 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7025}
7026
7027void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7028{
7029 drm_i915_private_t *dev_priv = dev->dev_private;
7030 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7031
49b14a5c 7032 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7033}
7034
6b95a207
KH		 7035void intel_prepare_page_flip(struct drm_device *dev, int plane)
7036{
7037 drm_i915_private_t *dev_priv = dev->dev_private;
7038 struct intel_crtc *intel_crtc =
7039 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7040 unsigned long flags;
7041
e7d841ca
CW		 7042 /* NB: An MMIO update of the plane base pointer will also
7043 * generate a page-flip completion irq, i.e. every modeset
7044 * is also accompanied by a spurious intel_prepare_page_flip().
7045 */
6b95a207 7046 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7047 if (intel_crtc->unpin_work)
7048 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7049 spin_unlock_irqrestore(&dev->event_lock, flags);
7050}
7051
e7d841ca
CW		 7052inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7053{
7054 /* Ensure that the work item is consistent when activating it ... */
7055 smp_wmb();
7056 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7057 /* and that it is marked active as soon as the irq could fire. */
7058 smp_wmb();
7059}
7060
8c9f3aaf
JB		 7061static int intel_gen2_queue_flip(struct drm_device *dev,
7062 struct drm_crtc *crtc,
7063 struct drm_framebuffer *fb,
7064 struct drm_i915_gem_object *obj)
7065{
7066 struct drm_i915_private *dev_priv = dev->dev_private;
7067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7068 u32 flip_mask;
6d90c952 7069 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7070 int ret;
7071
6d90c952 7072 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7073 if (ret)
83d4092b 7074 goto err;
8c9f3aaf 7075
6d90c952 7076 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7077 if (ret)
83d4092b 7078 goto err_unpin;
8c9f3aaf
JB		 7079
7080 /* Can't queue multiple flips, so wait for the previous
7081 * one to finish before executing the next.
7082 */
7083 if (intel_crtc->plane)
7084 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7085 else
7086 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7087 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7088 intel_ring_emit(ring, MI_NOOP);
7089 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7090 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7091 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7092 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7093 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7094
7095 intel_mark_page_flip_active(intel_crtc);
6d90c952 7096 intel_ring_advance(ring);
83d4092b
CW		 7097 return 0;
7098
7099err_unpin:
7100 intel_unpin_fb_obj(obj);
7101err:
8c9f3aaf
JB		 7102 return ret;
7103}
7104
7105static int intel_gen3_queue_flip(struct drm_device *dev,
7106 struct drm_crtc *crtc,
7107 struct drm_framebuffer *fb,
7108 struct drm_i915_gem_object *obj)
7109{
7110 struct drm_i915_private *dev_priv = dev->dev_private;
7111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7112 u32 flip_mask;
6d90c952 7113 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7114 int ret;
7115
6d90c952 7116 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7117 if (ret)
83d4092b 7118 goto err;
8c9f3aaf 7119
6d90c952 7120 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7121 if (ret)
83d4092b 7122 goto err_unpin;
8c9f3aaf
JB		 7123
7124 if (intel_crtc->plane)
7125 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7126 else
7127 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7128 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7129 intel_ring_emit(ring, MI_NOOP);
7130 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7131 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7132 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7133 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7134 intel_ring_emit(ring, MI_NOOP);
7135
e7d841ca 7136 intel_mark_page_flip_active(intel_crtc);
6d90c952 7137 intel_ring_advance(ring);
83d4092b
CW		 7138 return 0;
7139
7140err_unpin:
7141 intel_unpin_fb_obj(obj);
7142err:
8c9f3aaf
JB		 7143 return ret;
7144}
7145
7146static int intel_gen4_queue_flip(struct drm_device *dev,
7147 struct drm_crtc *crtc,
7148 struct drm_framebuffer *fb,
7149 struct drm_i915_gem_object *obj)
7150{
7151 struct drm_i915_private *dev_priv = dev->dev_private;
7152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7153 uint32_t pf, pipesrc;
6d90c952 7154 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7155 int ret;
7156
6d90c952 7157 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7158 if (ret)
83d4092b 7159 goto err;
8c9f3aaf 7160
6d90c952 7161 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7162 if (ret)
83d4092b 7163 goto err_unpin;
8c9f3aaf
JB		 7164
7165 /* i965+ uses the linear or tiled offsets from the
7166 * Display Registers (which do not change across a page-flip)
7167 * so we need only reprogram the base address.
7168 */
6d90c952
DV		 7169 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7170 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7171 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7172 intel_ring_emit(ring,
7173 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7174 obj->tiling_mode);
8c9f3aaf
JB		 7175
7176 /* XXX Enabling the panel-fitter across page-flip is so far
7177 * untested on non-native modes, so ignore it for now.
7178 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7179 */
7180 pf = 0;
7181 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7182 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7183
7184 intel_mark_page_flip_active(intel_crtc);
6d90c952 7185 intel_ring_advance(ring);
83d4092b
CW		 7186 return 0;
7187
7188err_unpin:
7189 intel_unpin_fb_obj(obj);
7190err:
8c9f3aaf
JB		 7191 return ret;
7192}
7193
7194static int intel_gen6_queue_flip(struct drm_device *dev,
7195 struct drm_crtc *crtc,
7196 struct drm_framebuffer *fb,
7197 struct drm_i915_gem_object *obj)
7198{
7199 struct drm_i915_private *dev_priv = dev->dev_private;
7200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7201 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7202 uint32_t pf, pipesrc;
7203 int ret;
7204
6d90c952 7205 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7206 if (ret)
83d4092b 7207 goto err;
8c9f3aaf 7208
6d90c952 7209 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7210 if (ret)
83d4092b 7211 goto err_unpin;
8c9f3aaf 7212
6d90c952
DV		 7213 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7214 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7215 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7216 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7217
dc257cf1
DV		 7218 /* Contrary to the suggestions in the documentation,
7219 * "Enable Panel Fitter" does not seem to be required when page
7220 * flipping with a non-native mode, and worse causes a normal
7221 * modeset to fail.
7222 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7223 */
7224 pf = 0;
8c9f3aaf 7225 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7226 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7227
7228 intel_mark_page_flip_active(intel_crtc);
6d90c952 7229 intel_ring_advance(ring);
83d4092b
CW		 7230 return 0;
7231
7232err_unpin:
7233 intel_unpin_fb_obj(obj);
7234err:
8c9f3aaf
JB		 7235 return ret;
7236}
7237
7c9017e5
JB		 7238/*
7239 * On gen7 we currently use the blit ring because (in early silicon at least)
7240 * the render ring doesn't give us interrpts for page flip completion, which
7241 * means clients will hang after the first flip is queued. Fortunately the
7242 * blit ring generates interrupts properly, so use it instead.
7243 */
7244static int intel_gen7_queue_flip(struct drm_device *dev,
7245 struct drm_crtc *crtc,
7246 struct drm_framebuffer *fb,
7247 struct drm_i915_gem_object *obj)
7248{
7249 struct drm_i915_private *dev_priv = dev->dev_private;
7250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7251 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7252 uint32_t plane_bit = 0;
7c9017e5
JB		 7253 int ret;
7254
7255 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7256 if (ret)
83d4092b 7257 goto err;
7c9017e5 7258
cb05d8de
DV		 7259 switch(intel_crtc->plane) {
7260 case PLANE_A:
7261 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7262 break;
7263 case PLANE_B:
7264 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7265 break;
7266 case PLANE_C:
7267 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7268 break;
7269 default:
7270 WARN_ONCE(1, "unknown plane in flip command\n");
7271 ret = -ENODEV;
ab3951eb 7272 goto err_unpin;
cb05d8de
DV		 7273 }
7274
7c9017e5
JB		 7275 ret = intel_ring_begin(ring, 4);
7276 if (ret)
83d4092b 7277 goto err_unpin;
7c9017e5 7278
cb05d8de 7279 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7280 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7281 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7282 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7283
7284 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7285 intel_ring_advance(ring);
83d4092b
CW		 7286 return 0;
7287
7288err_unpin:
7289 intel_unpin_fb_obj(obj);
7290err:
7c9017e5
JB		 7291 return ret;
7292}
7293
8c9f3aaf
JB		 7294static int intel_default_queue_flip(struct drm_device *dev,
7295 struct drm_crtc *crtc,
7296 struct drm_framebuffer *fb,
7297 struct drm_i915_gem_object *obj)
7298{
7299 return -ENODEV;
7300}
7301
6b95a207
KH		 7302static int intel_crtc_page_flip(struct drm_crtc *crtc,
7303 struct drm_framebuffer *fb,
7304 struct drm_pending_vblank_event *event)
7305{
7306 struct drm_device *dev = crtc->dev;
7307 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7308 struct drm_framebuffer *old_fb = crtc->fb;
7309 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7311 struct intel_unpin_work *work;
8c9f3aaf 7312 unsigned long flags;
52e68630 7313 int ret;
6b95a207 7314
e6a595d2
VS		 7315 /* Can't change pixel format via MI display flips. */
7316 if (fb->pixel_format != crtc->fb->pixel_format)
7317 return -EINVAL;
7318
7319 /*
7320 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7321 * Note that pitch changes could also affect these register.
7322 */
7323 if (INTEL_INFO(dev)->gen > 3 &&
7324 (fb->offsets[0] != crtc->fb->offsets[0] ||
7325 fb->pitches[0] != crtc->fb->pitches[0]))
7326 return -EINVAL;
7327
6b95a207
KH		 7328 work = kzalloc(sizeof *work, GFP_KERNEL);
7329 if (work == NULL)
7330 return -ENOMEM;
7331
6b95a207 7332 work->event = event;
b4a98e57 7333 work->crtc = crtc;
4a35f83b 7334 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7335 INIT_WORK(&work->work, intel_unpin_work_fn);
7336
7317c75e
JB		 7337 ret = drm_vblank_get(dev, intel_crtc->pipe);
7338 if (ret)
7339 goto free_work;
7340
6b95a207
KH		 7341 /* We borrow the event spin lock for protecting unpin_work */
7342 spin_lock_irqsave(&dev->event_lock, flags);
7343 if (intel_crtc->unpin_work) {
7344 spin_unlock_irqrestore(&dev->event_lock, flags);
7345 kfree(work);
7317c75e 7346 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7347
7348 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7349 return -EBUSY;
7350 }
7351 intel_crtc->unpin_work = work;
7352 spin_unlock_irqrestore(&dev->event_lock, flags);
7353
b4a98e57
CW		 7354 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7355 flush_workqueue(dev_priv->wq);
7356
79158103
CW		 7357 ret = i915_mutex_lock_interruptible(dev);
7358 if (ret)
7359 goto cleanup;
6b95a207 7360
75dfca80 7361 /* Reference the objects for the scheduled work. */
05394f39
CW		 7362 drm_gem_object_reference(&work->old_fb_obj->base);
7363 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7364
7365 crtc->fb = fb;
96b099fd 7366
e1f99ce6 7367 work->pending_flip_obj = obj;
e1f99ce6 7368
4e5359cd
SF		 7369 work->enable_stall_check = true;
7370
b4a98e57 7371 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7372 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7373
8c9f3aaf
JB		 7374 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7375 if (ret)
7376 goto cleanup_pending;
6b95a207 7377
7782de3b 7378 intel_disable_fbc(dev);
f047e395 7379 intel_mark_fb_busy(obj);
6b95a207
KH		 7380 mutex_unlock(&dev->struct_mutex);
7381
e5510fac
JB		 7382 trace_i915_flip_request(intel_crtc->plane, obj);
7383
6b95a207 7384 return 0;
96b099fd 7385
8c9f3aaf 7386cleanup_pending:
b4a98e57 7387 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7388 crtc->fb = old_fb;
05394f39
CW		 7389 drm_gem_object_unreference(&work->old_fb_obj->base);
7390 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7391 mutex_unlock(&dev->struct_mutex);
7392
79158103 7393cleanup:
96b099fd
CW		 7394 spin_lock_irqsave(&dev->event_lock, flags);
7395 intel_crtc->unpin_work = NULL;
7396 spin_unlock_irqrestore(&dev->event_lock, flags);
7397
7317c75e
JB		 7398 drm_vblank_put(dev, intel_crtc->pipe);
7399free_work:
96b099fd
CW		 7400 kfree(work);
7401
7402 return ret;
6b95a207
KH		 7403}
7404
f6e5b160 7405static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7406 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7407 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7408};
7409
6ed0f796 7410bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7411{
6ed0f796
DV		 7412 struct intel_encoder *other_encoder;
7413 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7414
6ed0f796
DV		 7415 if (WARN_ON(!crtc))
7416 return false;
7417
7418 list_for_each_entry(other_encoder,
7419 &crtc->dev->mode_config.encoder_list,
7420 base.head) {
7421
7422 if (&other_encoder->new_crtc->base != crtc ||
7423 encoder == other_encoder)
7424 continue;
7425 else
7426 return true;
f47166d2
CW		 7427 }
7428
6ed0f796
DV		 7429 return false;
7430}
47f1c6c9 7431
50f56119
DV		 7432static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7433 struct drm_crtc *crtc)
7434{
7435 struct drm_device *dev;
7436 struct drm_crtc *tmp;
7437 int crtc_mask = 1;
47f1c6c9 7438
50f56119 7439 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7440
50f56119 7441 dev = crtc->dev;
47f1c6c9 7442
50f56119
DV		 7443 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7444 if (tmp == crtc)
7445 break;
7446 crtc_mask <<= 1;
7447 }
47f1c6c9 7448
50f56119
DV		 7449 if (encoder->possible_crtcs & crtc_mask)
7450 return true;
7451 return false;
47f1c6c9 7452}
79e53945 7453
9a935856
DV		 7454/**
7455 * intel_modeset_update_staged_output_state
7456 *
7457 * Updates the staged output configuration state, e.g. after we've read out the
7458 * current hw state.
7459 */
7460static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7461{
9a935856
DV		 7462 struct intel_encoder *encoder;
7463 struct intel_connector *connector;
f6e5b160 7464
9a935856
DV		 7465 list_for_each_entry(connector, &dev->mode_config.connector_list,
7466 base.head) {
7467 connector->new_encoder =
7468 to_intel_encoder(connector->base.encoder);
7469 }
f6e5b160 7470
9a935856
DV		 7471 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7472 base.head) {
7473 encoder->new_crtc =
7474 to_intel_crtc(encoder->base.crtc);
7475 }
f6e5b160
CW		 7476}
7477
9a935856
DV		 7478/**
7479 * intel_modeset_commit_output_state
7480 *
7481 * This function copies the stage display pipe configuration to the real one.
7482 */
7483static void intel_modeset_commit_output_state(struct drm_device *dev)
7484{
7485 struct intel_encoder *encoder;
7486 struct intel_connector *connector;
f6e5b160 7487
9a935856
DV		 7488 list_for_each_entry(connector, &dev->mode_config.connector_list,
7489 base.head) {
7490 connector->base.encoder = &connector->new_encoder->base;
7491 }
f6e5b160 7492
9a935856
DV		 7493 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7494 base.head) {
7495 encoder->base.crtc = &encoder->new_crtc->base;
7496 }
7497}
7498
4e53c2e0
DV		 7499static int
7500pipe_config_set_bpp(struct drm_crtc *crtc,
7501 struct drm_framebuffer *fb,
7502 struct intel_crtc_config *pipe_config)
7503{
7504 struct drm_device *dev = crtc->dev;
7505 struct drm_connector *connector;
7506 int bpp;
7507
d42264b1
DV		 7508 switch (fb->pixel_format) {
7509 case DRM_FORMAT_C8:
4e53c2e0
DV		 7510 bpp = 8*3; /* since we go through a colormap */
7511 break;
d42264b1
DV		 7512 case DRM_FORMAT_XRGB1555:
7513 case DRM_FORMAT_ARGB1555:
7514 /* checked in intel_framebuffer_init already */
7515 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7516 return -EINVAL;
7517 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7518 bpp = 6*3; /* min is 18bpp */
7519 break;
d42264b1
DV		 7520 case DRM_FORMAT_XBGR8888:
7521 case DRM_FORMAT_ABGR8888:
7522 /* checked in intel_framebuffer_init already */
7523 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7524 return -EINVAL;
7525 case DRM_FORMAT_XRGB8888:
7526 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7527 bpp = 8*3;
7528 break;
d42264b1
DV		 7529 case DRM_FORMAT_XRGB2101010:
7530 case DRM_FORMAT_ARGB2101010:
7531 case DRM_FORMAT_XBGR2101010:
7532 case DRM_FORMAT_ABGR2101010:
7533 /* checked in intel_framebuffer_init already */
7534 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7535 return -EINVAL;
4e53c2e0
DV		 7536 bpp = 10*3;
7537 break;
baba133a 7538 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7539 default:
7540 DRM_DEBUG_KMS("unsupported depth\n");
7541 return -EINVAL;
7542 }
7543
4e53c2e0
DV		 7544 pipe_config->pipe_bpp = bpp;
7545
7546 /* Clamp display bpp to EDID value */
7547 list_for_each_entry(connector, &dev->mode_config.connector_list,
7548 head) {
7549 if (connector->encoder && connector->encoder->crtc != crtc)
7550 continue;
7551
7552 /* Don't use an invalid EDID bpc value */
7553 if (connector->display_info.bpc &&
7554 connector->display_info.bpc * 3 < bpp) {
7555 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7556 bpp, connector->display_info.bpc*3);
7557 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7558 }
7559 }
7560
7561 return bpp;
7562}
7563
b8cecdf5
DV		 7564static struct intel_crtc_config *
7565intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7566 struct drm_framebuffer *fb,
b8cecdf5 7567 struct drm_display_mode *mode)
ee7b9f93 7568{
7758a113 7569 struct drm_device *dev = crtc->dev;
7758a113
DV		 7570 struct drm_encoder_helper_funcs *encoder_funcs;
7571 struct intel_encoder *encoder;
b8cecdf5 7572 struct intel_crtc_config *pipe_config;
4e53c2e0 7573 int plane_bpp;
ee7b9f93 7574
b8cecdf5
DV		 7575 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7576 if (!pipe_config)
7758a113
DV		 7577 return ERR_PTR(-ENOMEM);
7578
b8cecdf5
DV		 7579 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7580 drm_mode_copy(&pipe_config->requested_mode, mode);
7581
4e53c2e0
DV		 7582 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7583 if (plane_bpp < 0)
7584 goto fail;
7585
7758a113
DV		 7586 /* Pass our mode to the connectors and the CRTC to give them a chance to
7587 * adjust it according to limitations or connector properties, and also
7588 * a chance to reject the mode entirely.
47f1c6c9 7589 */
7758a113
DV		 7590 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7591 base.head) {
47f1c6c9 7592
7758a113
DV		 7593 if (&encoder->new_crtc->base != crtc)
7594 continue;
7ae89233
DV		 7595
7596 if (encoder->compute_config) {
7597 if (!(encoder->compute_config(encoder, pipe_config))) {
7598 DRM_DEBUG_KMS("Encoder config failure\n");
7599 goto fail;
7600 }
7601
7602 continue;
7603 }
7604
7758a113 7605 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7606 if (!(encoder_funcs->mode_fixup(&encoder->base,
7607 &pipe_config->requested_mode,
7608 &pipe_config->adjusted_mode))) {
7758a113
DV		 7609 DRM_DEBUG_KMS("Encoder fixup failed\n");
7610 goto fail;
7611 }
ee7b9f93 7612 }
47f1c6c9 7613
b8cecdf5 7614 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7615 DRM_DEBUG_KMS("CRTC fixup failed\n");
7616 goto fail;
ee7b9f93 7617 }
7758a113 7618 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7619
4e53c2e0
DV		 7620 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7621 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7622 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7623
b8cecdf5 7624 return pipe_config;
7758a113 7625fail:
b8cecdf5 7626 kfree(pipe_config);
7758a113 7627 return ERR_PTR(-EINVAL);
ee7b9f93 7628}
47f1c6c9 7629
e2e1ed41
DV		 7630/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7631 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7632static void
7633intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7634 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7635{
7636 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7637 struct drm_device *dev = crtc->dev;
7638 struct intel_encoder *encoder;
7639 struct intel_connector *connector;
7640 struct drm_crtc *tmp_crtc;
79e53945 7641
e2e1ed41 7642 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7643
e2e1ed41
DV		 7644 /* Check which crtcs have changed outputs connected to them, these need
7645 * to be part of the prepare_pipes mask. We don't (yet) support global
7646 * modeset across multiple crtcs, so modeset_pipes will only have one
7647 * bit set at most. */
7648 list_for_each_entry(connector, &dev->mode_config.connector_list,
7649 base.head) {
7650 if (connector->base.encoder == &connector->new_encoder->base)
7651 continue;
79e53945 7652
e2e1ed41
DV		 7653 if (connector->base.encoder) {
7654 tmp_crtc = connector->base.encoder->crtc;
7655
7656 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7657 }
7658
7659 if (connector->new_encoder)
7660 *prepare_pipes |=
7661 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7662 }
7663
e2e1ed41
DV		 7664 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7665 base.head) {
7666 if (encoder->base.crtc == &encoder->new_crtc->base)
7667 continue;
7668
7669 if (encoder->base.crtc) {
7670 tmp_crtc = encoder->base.crtc;
7671
7672 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7673 }
7674
7675 if (encoder->new_crtc)
7676 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7677 }
7678
e2e1ed41
DV		 7679 /* Check for any pipes that will be fully disabled ... */
7680 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7681 base.head) {
7682 bool used = false;
22fd0fab 7683
e2e1ed41
DV		 7684 /* Don't try to disable disabled crtcs. */
7685 if (!intel_crtc->base.enabled)
7686 continue;
7e7d76c3 7687
e2e1ed41
DV		 7688 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7689 base.head) {
7690 if (encoder->new_crtc == intel_crtc)
7691 used = true;
7692 }
7693
7694 if (!used)
7695 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7696 }
7697
e2e1ed41
DV		 7698
7699 /* set_mode is also used to update properties on life display pipes. */
7700 intel_crtc = to_intel_crtc(crtc);
7701 if (crtc->enabled)
7702 *prepare_pipes |= 1 << intel_crtc->pipe;
7703
7704 /* We only support modeset on one single crtc, hence we need to do that
7705 * only for the passed in crtc iff we change anything else than just
7706 * disable crtcs.
7707 *
7708 * This is actually not true, to be fully compatible with the old crtc
7709 * helper we automatically disable _any_ output (i.e. doesn't need to be
7710 * connected to the crtc we're modesetting on) if it's disconnected.
7711 * Which is a rather nutty api (since changed the output configuration
7712 * without userspace's explicit request can lead to confusion), but
7713 * alas. Hence we currently need to modeset on all pipes we prepare. */
7714 if (*prepare_pipes)
7715 *modeset_pipes = *prepare_pipes;
7716
7717 /* ... and mask these out. */
7718 *modeset_pipes &= ~(*disable_pipes);
7719 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7720}
79e53945 7721
ea9d758d 7722static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7723{
ea9d758d 7724 struct drm_encoder *encoder;
f6e5b160 7725 struct drm_device *dev = crtc->dev;
f6e5b160 7726
ea9d758d
DV		 7727 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7728 if (encoder->crtc == crtc)
7729 return true;
7730
7731 return false;
7732}
7733
7734static void
7735intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7736{
7737 struct intel_encoder *intel_encoder;
7738 struct intel_crtc *intel_crtc;
7739 struct drm_connector *connector;
7740
7741 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7742 base.head) {
7743 if (!intel_encoder->base.crtc)
7744 continue;
7745
7746 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7747
7748 if (prepare_pipes & (1 << intel_crtc->pipe))
7749 intel_encoder->connectors_active = false;
7750 }
7751
7752 intel_modeset_commit_output_state(dev);
7753
7754 /* Update computed state. */
7755 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7756 base.head) {
7757 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7758 }
7759
7760 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7761 if (!connector->encoder || !connector->encoder->crtc)
7762 continue;
7763
7764 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7765
7766 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7767 struct drm_property *dpms_property =
7768 dev->mode_config.dpms_property;
7769
ea9d758d 7770 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7771 drm_object_property_set_value(&connector->base,
68d34720
DV		 7772 dpms_property,
7773 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7774
7775 intel_encoder = to_intel_encoder(connector->encoder);
7776 intel_encoder->connectors_active = true;
7777 }
7778 }
7779
7780}
7781
25c5b266
DV		 7782#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7783 list_for_each_entry((intel_crtc), \
7784 &(dev)->mode_config.crtc_list, \
7785 base.head) \
7786 if (mask & (1 <<(intel_crtc)->pipe)) \
7787
0e8ffe1b
DV		 7788static bool
7789intel_pipe_config_compare(struct intel_crtc_config *current_config,
7790 struct intel_crtc_config *pipe_config)
7791{
88adfff1
DV		 7792 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7793 DRM_ERROR("mismatch in has_pch_encoder "
7794 "(expected %i, found %i)\n",
7795 current_config->has_pch_encoder,
7796 pipe_config->has_pch_encoder);
7797 return false;
7798 }
7799
0e8ffe1b
DV		 7800 return true;
7801}
7802
b980514c 7803void
8af6cf88
DV		 7804intel_modeset_check_state(struct drm_device *dev)
7805{
0e8ffe1b 7806 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7807 struct intel_crtc *crtc;
7808 struct intel_encoder *encoder;
7809 struct intel_connector *connector;
0e8ffe1b 7810 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7811
7812 list_for_each_entry(connector, &dev->mode_config.connector_list,
7813 base.head) {
7814 /* This also checks the encoder/connector hw state with the
7815 * ->get_hw_state callbacks. */
7816 intel_connector_check_state(connector);
7817
7818 WARN(&connector->new_encoder->base != connector->base.encoder,
7819 "connector's staged encoder doesn't match current encoder\n");
7820 }
7821
7822 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7823 base.head) {
7824 bool enabled = false;
7825 bool active = false;
7826 enum pipe pipe, tracked_pipe;
7827
7828 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7829 encoder->base.base.id,
7830 drm_get_encoder_name(&encoder->base));
7831
7832 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7833 "encoder's stage crtc doesn't match current crtc\n");
7834 WARN(encoder->connectors_active && !encoder->base.crtc,
7835 "encoder's active_connectors set, but no crtc\n");
7836
7837 list_for_each_entry(connector, &dev->mode_config.connector_list,
7838 base.head) {
7839 if (connector->base.encoder != &encoder->base)
7840 continue;
7841 enabled = true;
7842 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7843 active = true;
7844 }
7845 WARN(!!encoder->base.crtc != enabled,
7846 "encoder's enabled state mismatch "
7847 "(expected %i, found %i)\n",
7848 !!encoder->base.crtc, enabled);
7849 WARN(active && !encoder->base.crtc,
7850 "active encoder with no crtc\n");
7851
7852 WARN(encoder->connectors_active != active,
7853 "encoder's computed active state doesn't match tracked active state "
7854 "(expected %i, found %i)\n", active, encoder->connectors_active);
7855
7856 active = encoder->get_hw_state(encoder, &pipe);
7857 WARN(active != encoder->connectors_active,
7858 "encoder's hw state doesn't match sw tracking "
7859 "(expected %i, found %i)\n",
7860 encoder->connectors_active, active);
7861
7862 if (!encoder->base.crtc)
7863 continue;
7864
7865 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7866 WARN(active && pipe != tracked_pipe,
7867 "active encoder's pipe doesn't match"
7868 "(expected %i, found %i)\n",
7869 tracked_pipe, pipe);
7870
7871 }
7872
7873 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7874 base.head) {
7875 bool enabled = false;
7876 bool active = false;
7877
7878 DRM_DEBUG_KMS("[CRTC:%d]\n",
7879 crtc->base.base.id);
7880
7881 WARN(crtc->active && !crtc->base.enabled,
7882 "active crtc, but not enabled in sw tracking\n");
7883
7884 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7885 base.head) {
7886 if (encoder->base.crtc != &crtc->base)
7887 continue;
7888 enabled = true;
7889 if (encoder->connectors_active)
7890 active = true;
7891 }
7892 WARN(active != crtc->active,
7893 "crtc's computed active state doesn't match tracked active state "
7894 "(expected %i, found %i)\n", active, crtc->active);
7895 WARN(enabled != crtc->base.enabled,
7896 "crtc's computed enabled state doesn't match tracked enabled state "
7897 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7898
88adfff1 7899 memset(&pipe_config, 0, sizeof(pipe_config));
0e8ffe1b
DV		 7900 active = dev_priv->display.get_pipe_config(crtc,
7901 &pipe_config);
7902 WARN(crtc->active != active,
7903 "crtc active state doesn't match with hw state "
7904 "(expected %i, found %i)\n", crtc->active, active);
7905
7906 WARN(active &&
7907 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7908 "pipe state doesn't match!\n");
8af6cf88
DV		 7909 }
7910}
7911
c0c36b94
CW		 7912int intel_set_mode(struct drm_crtc *crtc,
7913 struct drm_display_mode *mode,
7914 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7915{
7916 struct drm_device *dev = crtc->dev;
dbf2b54e 7917 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 7918 struct drm_display_mode *saved_mode, *saved_hwmode;
7919 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 7920 struct intel_crtc *intel_crtc;
7921 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7922 int ret = 0;
a6778b3c 7923
3ac18232 7924 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7925 if (!saved_mode)
7926 return -ENOMEM;
3ac18232 7927 saved_hwmode = saved_mode + 1;
a6778b3c 7928
e2e1ed41 7929 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7930 &prepare_pipes, &disable_pipes);
7931
3ac18232
TG		 7932 *saved_hwmode = crtc->hwmode;
7933 *saved_mode = crtc->mode;
a6778b3c 7934
25c5b266
DV		 7935 /* Hack: Because we don't (yet) support global modeset on multiple
7936 * crtcs, we don't keep track of the new mode for more than one crtc.
7937 * Hence simply check whether any bit is set in modeset_pipes in all the
7938 * pieces of code that are not yet converted to deal with mutliple crtcs
7939 * changing their mode at the same time. */
25c5b266 7940 if (modeset_pipes) {
4e53c2e0 7941 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 7942 if (IS_ERR(pipe_config)) {
7943 ret = PTR_ERR(pipe_config);
7944 pipe_config = NULL;
7945
3ac18232 7946 goto out;
25c5b266 7947 }
25c5b266 7948 }
a6778b3c 7949
460da916
DV		 7950 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7951 modeset_pipes, prepare_pipes, disable_pipes);
7952
7953 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7954 intel_crtc_disable(&intel_crtc->base);
7955
ea9d758d
DV		 7956 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7957 if (intel_crtc->base.enabled)
7958 dev_priv->display.crtc_disable(&intel_crtc->base);
7959 }
a6778b3c 7960
6c4c86f5
DV		 7961 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7962 * to set it here already despite that we pass it down the callchain.
f6e5b160 7963 */
b8cecdf5 7964 if (modeset_pipes) {
25c5b266 7965 crtc->mode = *mode;
b8cecdf5
DV		 7966 /* mode_set/enable/disable functions rely on a correct pipe
7967 * config. */
7968 to_intel_crtc(crtc)->config = *pipe_config;
7969 }
7758a113 7970
ea9d758d
DV		 7971 /* Only after disabling all output pipelines that will be changed can we
7972 * update the the output configuration. */
7973 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7974
47fab737
DV		 7975 if (dev_priv->display.modeset_global_resources)
7976 dev_priv->display.modeset_global_resources(dev);
7977
a6778b3c
DV		 7978 /* Set up the DPLL and any encoders state that needs to adjust or depend
7979 * on the DPLL.
f6e5b160 7980 */
25c5b266 7981 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 7982 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 7983 x, y, fb);
7984 if (ret)
7985 goto done;
a6778b3c
DV		 7986 }
7987
7988 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7989 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7990 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7991
25c5b266
DV		 7992 if (modeset_pipes) {
7993 /* Store real post-adjustment hardware mode. */
b8cecdf5 7994 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 7995
25c5b266
DV		 7996 /* Calculate and store various constants which
7997 * are later needed by vblank and swap-completion
7998 * timestamping. They are derived from true hwmode.
7999 */
8000 drm_calc_timestamping_constants(crtc);
8001 }
a6778b3c
DV		 8002
8003 /* FIXME: add subpixel order */
8004done:
c0c36b94 8005 if (ret && crtc->enabled) {
3ac18232
TG		 8006 crtc->hwmode = *saved_hwmode;
8007 crtc->mode = *saved_mode;
8af6cf88
DV		 8008 } else {
8009 intel_modeset_check_state(dev);
a6778b3c
DV		 8010 }
8011
3ac18232 8012out:
b8cecdf5 8013 kfree(pipe_config);
3ac18232 8014 kfree(saved_mode);
a6778b3c 8015 return ret;
f6e5b160
CW		 8016}
8017
c0c36b94
CW		 8018void intel_crtc_restore_mode(struct drm_crtc *crtc)
8019{
8020 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8021}
8022
25c5b266
DV		 8023#undef for_each_intel_crtc_masked
8024
d9e55608
DV		 8025static void intel_set_config_free(struct intel_set_config *config)
8026{
8027 if (!config)
8028 return;
8029
1aa4b628
DV		 8030 kfree(config->save_connector_encoders);
8031 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8032 kfree(config);
8033}
8034
85f9eb71
DV		 8035static int intel_set_config_save_state(struct drm_device *dev,
8036 struct intel_set_config *config)
8037{
85f9eb71
DV		 8038 struct drm_encoder *encoder;
8039 struct drm_connector *connector;
8040 int count;
8041
1aa4b628
DV		 8042 config->save_encoder_crtcs =
8043 kcalloc(dev->mode_config.num_encoder,
8044 sizeof(struct drm_crtc *), GFP_KERNEL);
8045 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8046 return -ENOMEM;
8047
1aa4b628
DV		 8048 config->save_connector_encoders =
8049 kcalloc(dev->mode_config.num_connector,
8050 sizeof(struct drm_encoder *), GFP_KERNEL);
8051 if (!config->save_connector_encoders)
85f9eb71
DV		 8052 return -ENOMEM;
8053
8054 /* Copy data. Note that driver private data is not affected.
8055 * Should anything bad happen only the expected state is
8056 * restored, not the drivers personal bookkeeping.
8057 */
85f9eb71
DV		 8058 count = 0;
8059 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8060 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8061 }
8062
8063 count = 0;
8064 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8065 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8066 }
8067
8068 return 0;
8069}
8070
8071static void intel_set_config_restore_state(struct drm_device *dev,
8072 struct intel_set_config *config)
8073{
9a935856
DV		 8074 struct intel_encoder *encoder;
8075 struct intel_connector *connector;
85f9eb71
DV		 8076 int count;
8077
85f9eb71 8078 count = 0;
9a935856
DV		 8079 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8080 encoder->new_crtc =
8081 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8082 }
8083
8084 count = 0;
9a935856
DV		 8085 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8086 connector->new_encoder =
8087 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8088 }
8089}
8090
5e2b584e
DV		 8091static void
8092intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8093 struct intel_set_config *config)
8094{
8095
8096 /* We should be able to check here if the fb has the same properties
8097 * and then just flip_or_move it */
8098 if (set->crtc->fb != set->fb) {
8099 /* If we have no fb then treat it as a full mode set */
8100 if (set->crtc->fb == NULL) {
8101 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8102 config->mode_changed = true;
8103 } else if (set->fb == NULL) {
8104 config->mode_changed = true;
72f4901e
DV		 8105 } else if (set->fb->pixel_format !=
8106 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8107 config->mode_changed = true;
8108 } else
8109 config->fb_changed = true;
8110 }
8111
835c5873 8112 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8113 config->fb_changed = true;
8114
8115 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8116 DRM_DEBUG_KMS("modes are different, full mode set\n");
8117 drm_mode_debug_printmodeline(&set->crtc->mode);
8118 drm_mode_debug_printmodeline(set->mode);
8119 config->mode_changed = true;
8120 }
8121}
8122
2e431051 8123static int
9a935856
DV		 8124intel_modeset_stage_output_state(struct drm_device *dev,
8125 struct drm_mode_set *set,
8126 struct intel_set_config *config)
50f56119 8127{
85f9eb71 8128 struct drm_crtc *new_crtc;
9a935856
DV		 8129 struct intel_connector *connector;
8130 struct intel_encoder *encoder;
2e431051 8131 int count, ro;
50f56119 8132
9abdda74 8133 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8134 * of connectors. For paranoia, double-check this. */
8135 WARN_ON(!set->fb && (set->num_connectors != 0));
8136 WARN_ON(set->fb && (set->num_connectors == 0));
8137
50f56119 8138 count = 0;
9a935856
DV		 8139 list_for_each_entry(connector, &dev->mode_config.connector_list,
8140 base.head) {
8141 /* Otherwise traverse passed in connector list and get encoders
8142 * for them. */
50f56119 8143 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8144 if (set->connectors[ro] == &connector->base) {
8145 connector->new_encoder = connector->encoder;
50f56119
DV		 8146 break;
8147 }
8148 }
8149
9a935856
DV		 8150 /* If we disable the crtc, disable all its connectors. Also, if
8151 * the connector is on the changing crtc but not on the new
8152 * connector list, disable it. */
8153 if ((!set->fb || ro == set->num_connectors) &&
8154 connector->base.encoder &&
8155 connector->base.encoder->crtc == set->crtc) {
8156 connector->new_encoder = NULL;
8157
8158 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8159 connector->base.base.id,
8160 drm_get_connector_name(&connector->base));
8161 }
8162
8163
8164 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8165 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8166 config->mode_changed = true;
50f56119
DV		 8167 }
8168 }
9a935856 8169 /* connector->new_encoder is now updated for all connectors. */
50f56119 8170
9a935856 8171 /* Update crtc of enabled connectors. */
50f56119 8172 count = 0;
9a935856
DV		 8173 list_for_each_entry(connector, &dev->mode_config.connector_list,
8174 base.head) {
8175 if (!connector->new_encoder)
50f56119
DV		 8176 continue;
8177
9a935856 8178 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8179
8180 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8181 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8182 new_crtc = set->crtc;
8183 }
8184
8185 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8186 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8187 new_crtc)) {
5e2b584e 8188 return -EINVAL;
50f56119 8189 }
9a935856
DV		 8190 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8191
8192 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8193 connector->base.base.id,
8194 drm_get_connector_name(&connector->base),
8195 new_crtc->base.id);
8196 }
8197
8198 /* Check for any encoders that needs to be disabled. */
8199 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8200 base.head) {
8201 list_for_each_entry(connector,
8202 &dev->mode_config.connector_list,
8203 base.head) {
8204 if (connector->new_encoder == encoder) {
8205 WARN_ON(!connector->new_encoder->new_crtc);
8206
8207 goto next_encoder;
8208 }
8209 }
8210 encoder->new_crtc = NULL;
8211next_encoder:
8212 /* Only now check for crtc changes so we don't miss encoders
8213 * that will be disabled. */
8214 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8215 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8216 config->mode_changed = true;
50f56119
DV		 8217 }
8218 }
9a935856 8219 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8220
2e431051
DV		 8221 return 0;
8222}
8223
8224static int intel_crtc_set_config(struct drm_mode_set *set)
8225{
8226 struct drm_device *dev;
2e431051
DV		 8227 struct drm_mode_set save_set;
8228 struct intel_set_config *config;
8229 int ret;
2e431051 8230
8d3e375e
DV		 8231 BUG_ON(!set);
8232 BUG_ON(!set->crtc);
8233 BUG_ON(!set->crtc->helper_private);
2e431051 8234
7e53f3a4
DV		 8235 /* Enforce sane interface api - has been abused by the fb helper. */
8236 BUG_ON(!set->mode && set->fb);
8237 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8238
2e431051
DV		 8239 if (set->fb) {
8240 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8241 set->crtc->base.id, set->fb->base.id,
8242 (int)set->num_connectors, set->x, set->y);
8243 } else {
8244 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8245 }
8246
8247 dev = set->crtc->dev;
8248
8249 ret = -ENOMEM;
8250 config = kzalloc(sizeof(*config), GFP_KERNEL);
8251 if (!config)
8252 goto out_config;
8253
8254 ret = intel_set_config_save_state(dev, config);
8255 if (ret)
8256 goto out_config;
8257
8258 save_set.crtc = set->crtc;
8259 save_set.mode = &set->crtc->mode;
8260 save_set.x = set->crtc->x;
8261 save_set.y = set->crtc->y;
8262 save_set.fb = set->crtc->fb;
8263
8264 /* Compute whether we need a full modeset, only an fb base update or no
8265 * change at all. In the future we might also check whether only the
8266 * mode changed, e.g. for LVDS where we only change the panel fitter in
8267 * such cases. */
8268 intel_set_config_compute_mode_changes(set, config);
8269
9a935856 8270 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8271 if (ret)
8272 goto fail;
8273
5e2b584e 8274 if (config->mode_changed) {
87f1faa6 8275 if (set->mode) {
50f56119
DV		 8276 DRM_DEBUG_KMS("attempting to set mode from"
8277 " userspace\n");
8278 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8279 }
8280
c0c36b94
CW		 8281 ret = intel_set_mode(set->crtc, set->mode,
8282 set->x, set->y, set->fb);
8283 if (ret) {
8284 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8285 set->crtc->base.id, ret);
87f1faa6
DV		 8286 goto fail;
8287 }
5e2b584e 8288 } else if (config->fb_changed) {
4878cae2
VS		 8289 intel_crtc_wait_for_pending_flips(set->crtc);
8290
4f660f49 8291 ret = intel_pipe_set_base(set->crtc,
94352cf9 8292 set->x, set->y, set->fb);
50f56119
DV		 8293 }
8294
d9e55608
DV		 8295 intel_set_config_free(config);
8296
50f56119
DV		 8297 return 0;
8298
8299fail:
85f9eb71 8300 intel_set_config_restore_state(dev, config);
50f56119
DV		 8301
8302 /* Try to restore the config */
5e2b584e 8303 if (config->mode_changed &&
c0c36b94
CW		 8304 intel_set_mode(save_set.crtc, save_set.mode,
8305 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8306 DRM_ERROR("failed to restore config after modeset failure\n");
8307
d9e55608
DV		 8308out_config:
8309 intel_set_config_free(config);
50f56119
DV		 8310 return ret;
8311}
f6e5b160
CW		 8312
8313static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8314 .cursor_set = intel_crtc_cursor_set,
8315 .cursor_move = intel_crtc_cursor_move,
8316 .gamma_set = intel_crtc_gamma_set,
50f56119 8317 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8318 .destroy = intel_crtc_destroy,
8319 .page_flip = intel_crtc_page_flip,
8320};
8321
79f689aa
PZ		 8322static void intel_cpu_pll_init(struct drm_device *dev)
8323{
affa9354 8324 if (HAS_DDI(dev))
79f689aa
PZ		 8325 intel_ddi_pll_init(dev);
8326}
8327
ee7b9f93
JB		 8328static void intel_pch_pll_init(struct drm_device *dev)
8329{
8330 drm_i915_private_t *dev_priv = dev->dev_private;
8331 int i;
8332
8333 if (dev_priv->num_pch_pll == 0) {
8334 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8335 return;
8336 }
8337
8338 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8339 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8340 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8341 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8342 }
8343}
8344
b358d0a6 8345static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8346{
22fd0fab 8347 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8348 struct intel_crtc *intel_crtc;
8349 int i;
8350
8351 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8352 if (intel_crtc == NULL)
8353 return;
8354
8355 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8356
8357 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8358 for (i = 0; i < 256; i++) {
8359 intel_crtc->lut_r[i] = i;
8360 intel_crtc->lut_g[i] = i;
8361 intel_crtc->lut_b[i] = i;
8362 }
8363
80824003
JB		 8364 /* Swap pipes & planes for FBC on pre-965 */
8365 intel_crtc->pipe = pipe;
8366 intel_crtc->plane = pipe;
a5c961d1 8367 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8368 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8369 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8370 intel_crtc->plane = !pipe;
80824003
JB		 8371 }
8372
22fd0fab
JB		 8373 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8374 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8375 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8376 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8377
79e53945 8378 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8379}
8380
08d7b3d1 8381int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8382 struct drm_file *file)
08d7b3d1 8383{
08d7b3d1 8384 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8385 struct drm_mode_object *drmmode_obj;
8386 struct intel_crtc *crtc;
08d7b3d1 8387
1cff8f6b
DV		 8388 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8389 return -ENODEV;
08d7b3d1 8390
c05422d5
DV		 8391 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8392 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8393
c05422d5 8394 if (!drmmode_obj) {
08d7b3d1
CW		 8395 DRM_ERROR("no such CRTC id\n");
8396 return -EINVAL;
8397 }
8398
c05422d5
DV		 8399 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8400 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8401
c05422d5 8402 return 0;
08d7b3d1
CW		 8403}
8404
66a9278e 8405static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8406{
66a9278e
DV		 8407 struct drm_device *dev = encoder->base.dev;
8408 struct intel_encoder *source_encoder;
79e53945 8409 int index_mask = 0;
79e53945
JB		 8410 int entry = 0;
8411
66a9278e
DV		 8412 list_for_each_entry(source_encoder,
8413 &dev->mode_config.encoder_list, base.head) {
8414
8415 if (encoder == source_encoder)
79e53945 8416 index_mask |= (1 << entry);
66a9278e
DV		 8417
8418 /* Intel hw has only one MUX where enocoders could be cloned. */
8419 if (encoder->cloneable && source_encoder->cloneable)
8420 index_mask |= (1 << entry);
8421
79e53945
JB		 8422 entry++;
8423 }
4ef69c7a 8424
79e53945
JB		 8425 return index_mask;
8426}
8427
4d302442
CW		 8428static bool has_edp_a(struct drm_device *dev)
8429{
8430 struct drm_i915_private *dev_priv = dev->dev_private;
8431
8432 if (!IS_MOBILE(dev))
8433 return false;
8434
8435 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8436 return false;
8437
8438 if (IS_GEN5(dev) &&
8439 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8440 return false;
8441
8442 return true;
8443}
8444
79e53945
JB		 8445static void intel_setup_outputs(struct drm_device *dev)
8446{
725e30ad 8447 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8448 struct intel_encoder *encoder;
cb0953d7 8449 bool dpd_is_edp = false;
f3cfcba6 8450 bool has_lvds;
79e53945 8451
f3cfcba6 8452 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8453 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8454 /* disable the panel fitter on everything but LVDS */
8455 I915_WRITE(PFIT_CONTROL, 0);
8456 }
79e53945 8457
affa9354 8458 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8459 intel_crt_init(dev);
cb0953d7 8460
affa9354 8461 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8462 int found;
8463
8464 /* Haswell uses DDI functions to detect digital outputs */
8465 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8466 /* DDI A only supports eDP */
8467 if (found)
8468 intel_ddi_init(dev, PORT_A);
8469
8470 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8471 * register */
8472 found = I915_READ(SFUSE_STRAP);
8473
8474 if (found & SFUSE_STRAP_DDIB_DETECTED)
8475 intel_ddi_init(dev, PORT_B);
8476 if (found & SFUSE_STRAP_DDIC_DETECTED)
8477 intel_ddi_init(dev, PORT_C);
8478 if (found & SFUSE_STRAP_DDID_DETECTED)
8479 intel_ddi_init(dev, PORT_D);
8480 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8481 int found;
270b3042
DV		 8482 dpd_is_edp = intel_dpd_is_edp(dev);
8483
8484 if (has_edp_a(dev))
8485 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8486
dc0fa718 8487 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8488 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8489 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8490 if (!found)
e2debe91 8491 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8492 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8493 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8494 }
8495
dc0fa718 8496 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8497 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8498
dc0fa718 8499 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8500 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8501
5eb08b69 8502 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8503 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8504
270b3042 8505 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8506 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8507 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8508 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8509 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8510 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8511
dc0fa718 8512 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8513 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8514 PORT_B);
67cfc203
VS		 8515 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8516 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8517 }
103a196f 8518 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8519 bool found = false;
7d57382e 8520
e2debe91 8521 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8522 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8523 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8524 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8525 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8526 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8527 }
27185ae1 8528
b01f2c3a
JB		 8529 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8530 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8531 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8532 }
725e30ad 8533 }
13520b05
KH		 8534
8535 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8536
e2debe91 8537 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8538 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8539 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8540 }
27185ae1 8541
e2debe91 8542 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8543
b01f2c3a
JB		 8544 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8545 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8546 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8547 }
8548 if (SUPPORTS_INTEGRATED_DP(dev)) {
8549 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8550 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8551 }
725e30ad 8552 }
27185ae1 8553
b01f2c3a
JB		 8554 if (SUPPORTS_INTEGRATED_DP(dev) &&
8555 (I915_READ(DP_D) & DP_DETECTED)) {
8556 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8557 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8558 }
bad720ff 8559 } else if (IS_GEN2(dev))
79e53945
JB		 8560 intel_dvo_init(dev);
8561
103a196f 8562 if (SUPPORTS_TV(dev))
79e53945
JB		 8563 intel_tv_init(dev);
8564
4ef69c7a
CW		 8565 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8566 encoder->base.possible_crtcs = encoder->crtc_mask;
8567 encoder->base.possible_clones =
66a9278e 8568 intel_encoder_clones(encoder);
79e53945 8569 }
47356eb6 8570
dde86e2d 8571 intel_init_pch_refclk(dev);
270b3042
DV		 8572
8573 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8574}
8575
8576static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8577{
8578 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8579
8580 drm_framebuffer_cleanup(fb);
05394f39 8581 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8582
8583 kfree(intel_fb);
8584}
8585
8586static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8587 struct drm_file *file,
79e53945
JB		 8588 unsigned int *handle)
8589{
8590 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8591 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8592
05394f39 8593 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8594}
8595
8596static const struct drm_framebuffer_funcs intel_fb_funcs = {
8597 .destroy = intel_user_framebuffer_destroy,
8598 .create_handle = intel_user_framebuffer_create_handle,
8599};
8600
38651674
DA		 8601int intel_framebuffer_init(struct drm_device *dev,
8602 struct intel_framebuffer *intel_fb,
308e5bcb 8603 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8604 struct drm_i915_gem_object *obj)
79e53945 8605{
79e53945
JB		 8606 int ret;
8607
c16ed4be
CW		 8608 if (obj->tiling_mode == I915_TILING_Y) {
8609 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8610 return -EINVAL;
c16ed4be 8611 }
57cd6508 8612
c16ed4be
CW		 8613 if (mode_cmd->pitches[0] & 63) {
8614 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8615 mode_cmd->pitches[0]);
57cd6508 8616 return -EINVAL;
c16ed4be 8617 }
57cd6508 8618
5d7bd705 8619 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8620 if (mode_cmd->pitches[0] > 32768) {
8621 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8622 mode_cmd->pitches[0]);
5d7bd705 8623 return -EINVAL;
c16ed4be 8624 }
5d7bd705
VS		 8625
8626 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8627 mode_cmd->pitches[0] != obj->stride) {
8628 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8629 mode_cmd->pitches[0], obj->stride);
5d7bd705 8630 return -EINVAL;
c16ed4be 8631 }
5d7bd705 8632
57779d06 8633 /* Reject formats not supported by any plane early. */
308e5bcb 8634 switch (mode_cmd->pixel_format) {
57779d06 8635 case DRM_FORMAT_C8:
04b3924d
VS		 8636 case DRM_FORMAT_RGB565:
8637 case DRM_FORMAT_XRGB8888:
8638 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8639 break;
8640 case DRM_FORMAT_XRGB1555:
8641 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8642 if (INTEL_INFO(dev)->gen > 3) {
8643 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8644 return -EINVAL;
c16ed4be 8645 }
57779d06
VS		 8646 break;
8647 case DRM_FORMAT_XBGR8888:
8648 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8649 case DRM_FORMAT_XRGB2101010:
8650 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8651 case DRM_FORMAT_XBGR2101010:
8652 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8653 if (INTEL_INFO(dev)->gen < 4) {
8654 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8655 return -EINVAL;
c16ed4be 8656 }
b5626747 8657 break;
04b3924d
VS		 8658 case DRM_FORMAT_YUYV:
8659 case DRM_FORMAT_UYVY:
8660 case DRM_FORMAT_YVYU:
8661 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8662 if (INTEL_INFO(dev)->gen < 5) {
8663 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8664 return -EINVAL;
c16ed4be 8665 }
57cd6508
CW		 8666 break;
8667 default:
c16ed4be 8668 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8669 return -EINVAL;
8670 }
8671
90f9a336
VS		 8672 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8673 if (mode_cmd->offsets[0] != 0)
8674 return -EINVAL;
8675
c7d73f6a
DV		 8676 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8677 intel_fb->obj = obj;
8678
79e53945
JB		 8679 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8680 if (ret) {
8681 DRM_ERROR("framebuffer init failed %d\n", ret);
8682 return ret;
8683 }
8684
79e53945
JB		 8685 return 0;
8686}
8687
79e53945
JB		 8688static struct drm_framebuffer *
8689intel_user_framebuffer_create(struct drm_device *dev,
8690 struct drm_file *filp,
308e5bcb 8691 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8692{
05394f39 8693 struct drm_i915_gem_object *obj;
79e53945 8694
308e5bcb
JB		 8695 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8696 mode_cmd->handles[0]));
c8725226 8697 if (&obj->base == NULL)
cce13ff7 8698 return ERR_PTR(-ENOENT);
79e53945 8699
d2dff872 8700 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8701}
8702
79e53945 8703static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8704 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8705 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8706};
8707
e70236a8
JB		 8708/* Set up chip specific display functions */
8709static void intel_init_display(struct drm_device *dev)
8710{
8711 struct drm_i915_private *dev_priv = dev->dev_private;
8712
affa9354 8713 if (HAS_DDI(dev)) {
0e8ffe1b 8714 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8715 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8716 dev_priv->display.crtc_enable = haswell_crtc_enable;
8717 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8718 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8719 dev_priv->display.update_plane = ironlake_update_plane;
8720 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8721 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8722 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8723 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8724 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8725 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8726 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8727 } else {
0e8ffe1b 8728 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8729 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8730 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8731 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8732 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8733 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8734 }
e70236a8 8735
e70236a8 8736 /* Returns the core display clock speed */
25eb05fc
JB		 8737 if (IS_VALLEYVIEW(dev))
8738 dev_priv->display.get_display_clock_speed =
8739 valleyview_get_display_clock_speed;
8740 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8741 dev_priv->display.get_display_clock_speed =
8742 i945_get_display_clock_speed;
8743 else if (IS_I915G(dev))
8744 dev_priv->display.get_display_clock_speed =
8745 i915_get_display_clock_speed;
f2b115e6 8746 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8747 dev_priv->display.get_display_clock_speed =
8748 i9xx_misc_get_display_clock_speed;
8749 else if (IS_I915GM(dev))
8750 dev_priv->display.get_display_clock_speed =
8751 i915gm_get_display_clock_speed;
8752 else if (IS_I865G(dev))
8753 dev_priv->display.get_display_clock_speed =
8754 i865_get_display_clock_speed;
f0f8a9ce 8755 else if (IS_I85X(dev))
e70236a8
JB		 8756 dev_priv->display.get_display_clock_speed =
8757 i855_get_display_clock_speed;
8758 else /* 852, 830 */
8759 dev_priv->display.get_display_clock_speed =
8760 i830_get_display_clock_speed;
8761
7f8a8569 8762 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8763 if (IS_GEN5(dev)) {
674cf967 8764 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8765 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8766 } else if (IS_GEN6(dev)) {
674cf967 8767 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8768 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8769 } else if (IS_IVYBRIDGE(dev)) {
8770 /* FIXME: detect B0+ stepping and use auto training */
8771 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8772 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8773 dev_priv->display.modeset_global_resources =
8774 ivb_modeset_global_resources;
c82e4d26
ED		 8775 } else if (IS_HASWELL(dev)) {
8776 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8777 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8778 dev_priv->display.modeset_global_resources =
8779 haswell_modeset_global_resources;
a0e63c22 8780 }
6067aaea 8781 } else if (IS_G4X(dev)) {
e0dac65e 8782 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8783 }
8c9f3aaf
JB		 8784
8785 /* Default just returns -ENODEV to indicate unsupported */
8786 dev_priv->display.queue_flip = intel_default_queue_flip;
8787
8788 switch (INTEL_INFO(dev)->gen) {
8789 case 2:
8790 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8791 break;
8792
8793 case 3:
8794 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8795 break;
8796
8797 case 4:
8798 case 5:
8799 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8800 break;
8801
8802 case 6:
8803 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8804 break;
7c9017e5
JB		 8805 case 7:
8806 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8807 break;
8c9f3aaf 8808 }
e70236a8
JB		 8809}
8810
b690e96c
JB		 8811/*
8812 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8813 * resume, or other times. This quirk makes sure that's the case for
8814 * affected systems.
8815 */
0206e353 8816static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8817{
8818 struct drm_i915_private *dev_priv = dev->dev_private;
8819
8820 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8821 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8822}
8823
435793df
KP		 8824/*
8825 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8826 */
8827static void quirk_ssc_force_disable(struct drm_device *dev)
8828{
8829 struct drm_i915_private *dev_priv = dev->dev_private;
8830 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8831 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8832}
8833
4dca20ef 8834/*
5a15ab5b
CE		 8835 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8836 * brightness value
4dca20ef
CE		 8837 */
8838static void quirk_invert_brightness(struct drm_device *dev)
8839{
8840 struct drm_i915_private *dev_priv = dev->dev_private;
8841 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8842 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8843}
8844
b690e96c
JB		 8845struct intel_quirk {
8846 int device;
8847 int subsystem_vendor;
8848 int subsystem_device;
8849 void (*hook)(struct drm_device *dev);
8850};
8851
5f85f176
EE		 8852/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8853struct intel_dmi_quirk {
8854 void (*hook)(struct drm_device *dev);
8855 const struct dmi_system_id (*dmi_id_list)[];
8856};
8857
8858static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8859{
8860 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8861 return 1;
8862}
8863
8864static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8865 {
8866 .dmi_id_list = &(const struct dmi_system_id[]) {
8867 {
8868 .callback = intel_dmi_reverse_brightness,
8869 .ident = "NCR Corporation",
8870 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8871 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8872 },
8873 },
8874 { } /* terminating entry */
8875 },
8876 .hook = quirk_invert_brightness,
8877 },
8878};
8879
c43b5634 8880static struct intel_quirk intel_quirks[] = {
b690e96c 8881 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8882 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8883
b690e96c
JB		 8884 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8885 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8886
b690e96c
JB		 8887 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8888 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8889
ccd0d36e 8890 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8891 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8892 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8893
8894 /* Lenovo U160 cannot use SSC on LVDS */
8895 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8896
8897 /* Sony Vaio Y cannot use SSC on LVDS */
8898 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8899
8900 /* Acer Aspire 5734Z must invert backlight brightness */
8901 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8902
8903 /* Acer/eMachines G725 */
8904 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8905
8906 /* Acer/eMachines e725 */
8907 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8908
8909 /* Acer/Packard Bell NCL20 */
8910 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 8911
8912 /* Acer Aspire 4736Z */
8913 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 8914};
8915
8916static void intel_init_quirks(struct drm_device *dev)
8917{
8918 struct pci_dev *d = dev->pdev;
8919 int i;
8920
8921 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8922 struct intel_quirk *q = &intel_quirks[i];
8923
8924 if (d->device == q->device &&
8925 (d->subsystem_vendor == q->subsystem_vendor ||
8926 q->subsystem_vendor == PCI_ANY_ID) &&
8927 (d->subsystem_device == q->subsystem_device ||
8928 q->subsystem_device == PCI_ANY_ID))
8929 q->hook(dev);
8930 }
5f85f176
EE		 8931 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8932 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8933 intel_dmi_quirks[i].hook(dev);
8934 }
b690e96c
JB		 8935}
8936
9cce37f4
JB		 8937/* Disable the VGA plane that we never use */
8938static void i915_disable_vga(struct drm_device *dev)
8939{
8940 struct drm_i915_private *dev_priv = dev->dev_private;
8941 u8 sr1;
766aa1c4 8942 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 8943
8944 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8945 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8946 sr1 = inb(VGA_SR_DATA);
8947 outb(sr1 | 1<<5, VGA_SR_DATA);
8948 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8949 udelay(300);
8950
8951 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8952 POSTING_READ(vga_reg);
8953}
8954
f817586c
DV		 8955void intel_modeset_init_hw(struct drm_device *dev)
8956{
fa42e23c 8957 intel_init_power_well(dev);
0232e927 8958
a8f78b58
ED		 8959 intel_prepare_ddi(dev);
8960
f817586c
DV		 8961 intel_init_clock_gating(dev);
8962
79f5b2c7 8963 mutex_lock(&dev->struct_mutex);
8090c6b9 8964 intel_enable_gt_powersave(dev);
79f5b2c7 8965 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8966}
8967
79e53945
JB		 8968void intel_modeset_init(struct drm_device *dev)
8969{
652c393a 8970 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 8971 int i, j, ret;
79e53945
JB		 8972
8973 drm_mode_config_init(dev);
8974
8975 dev->mode_config.min_width = 0;
8976 dev->mode_config.min_height = 0;
8977
019d96cb
DA		 8978 dev->mode_config.preferred_depth = 24;
8979 dev->mode_config.prefer_shadow = 1;
8980
e6ecefaa 8981 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8982
b690e96c
JB		 8983 intel_init_quirks(dev);
8984
1fa61106
ED		 8985 intel_init_pm(dev);
8986
e70236a8
JB		 8987 intel_init_display(dev);
8988
a6c45cf0
CW		 8989 if (IS_GEN2(dev)) {
8990 dev->mode_config.max_width = 2048;
8991 dev->mode_config.max_height = 2048;
8992 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8993 dev->mode_config.max_width = 4096;
8994 dev->mode_config.max_height = 4096;
79e53945 8995 } else {
a6c45cf0
CW		 8996 dev->mode_config.max_width = 8192;
8997 dev->mode_config.max_height = 8192;
79e53945 8998 }
5d4545ae 8999 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9000
28c97730 9001 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9002 INTEL_INFO(dev)->num_pipes,
9003 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9004
7eb552ae 9005 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9006 intel_crtc_init(dev, i);
7f1f3851
JB		 9007 for (j = 0; j < dev_priv->num_plane; j++) {
9008 ret = intel_plane_init(dev, i, j);
9009 if (ret)
9010 DRM_DEBUG_KMS("pipe %d plane %d init failed: %d\n",
9011 i, j, ret);
9012 }
79e53945
JB		 9013 }
9014
79f689aa 9015 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9016 intel_pch_pll_init(dev);
9017
9cce37f4
JB		 9018 /* Just disable it once at startup */
9019 i915_disable_vga(dev);
79e53945 9020 intel_setup_outputs(dev);
11be49eb
CW		 9021
9022 /* Just in case the BIOS is doing something questionable. */
9023 intel_disable_fbc(dev);
2c7111db
CW		 9024}
9025
24929352
DV		 9026static void
9027intel_connector_break_all_links(struct intel_connector *connector)
9028{
9029 connector->base.dpms = DRM_MODE_DPMS_OFF;
9030 connector->base.encoder = NULL;
9031 connector->encoder->connectors_active = false;
9032 connector->encoder->base.crtc = NULL;
9033}
9034
7fad798e
DV		 9035static void intel_enable_pipe_a(struct drm_device *dev)
9036{
9037 struct intel_connector *connector;
9038 struct drm_connector *crt = NULL;
9039 struct intel_load_detect_pipe load_detect_temp;
9040
9041 /* We can't just switch on the pipe A, we need to set things up with a
9042 * proper mode and output configuration. As a gross hack, enable pipe A
9043 * by enabling the load detect pipe once. */
9044 list_for_each_entry(connector,
9045 &dev->mode_config.connector_list,
9046 base.head) {
9047 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9048 crt = &connector->base;
9049 break;
9050 }
9051 }
9052
9053 if (!crt)
9054 return;
9055
9056 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9057 intel_release_load_detect_pipe(crt, &load_detect_temp);
9058
652c393a 9059
7fad798e
DV		 9060}
9061
fa555837
DV		 9062static bool
9063intel_check_plane_mapping(struct intel_crtc *crtc)
9064{
7eb552ae
BW		 9065 struct drm_device *dev = crtc->base.dev;
9066 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9067 u32 reg, val;
9068
7eb552ae 9069 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9070 return true;
9071
9072 reg = DSPCNTR(!crtc->plane);
9073 val = I915_READ(reg);
9074
9075 if ((val & DISPLAY_PLANE_ENABLE) &&
9076 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9077 return false;
9078
9079 return true;
9080}
9081
24929352
DV		 9082static void intel_sanitize_crtc(struct intel_crtc *crtc)
9083{
9084 struct drm_device *dev = crtc->base.dev;
9085 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9086 u32 reg;
24929352 9087
24929352 9088 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 9089 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 9090 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9091
9092 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9093 * disable the crtc (and hence change the state) if it is wrong. Note
9094 * that gen4+ has a fixed plane -> pipe mapping. */
9095 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9096 struct intel_connector *connector;
9097 bool plane;
9098
24929352
DV		 9099 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9100 crtc->base.base.id);
9101
9102 /* Pipe has the wrong plane attached and the plane is active.
9103 * Temporarily change the plane mapping and disable everything
9104 * ... */
9105 plane = crtc->plane;
9106 crtc->plane = !plane;
9107 dev_priv->display.crtc_disable(&crtc->base);
9108 crtc->plane = plane;
9109
9110 /* ... and break all links. */
9111 list_for_each_entry(connector, &dev->mode_config.connector_list,
9112 base.head) {
9113 if (connector->encoder->base.crtc != &crtc->base)
9114 continue;
9115
9116 intel_connector_break_all_links(connector);
9117 }
9118
9119 WARN_ON(crtc->active);
9120 crtc->base.enabled = false;
9121 }
24929352 9122
7fad798e
DV		 9123 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9124 crtc->pipe == PIPE_A && !crtc->active) {
9125 /* BIOS forgot to enable pipe A, this mostly happens after
9126 * resume. Force-enable the pipe to fix this, the update_dpms
9127 * call below we restore the pipe to the right state, but leave
9128 * the required bits on. */
9129 intel_enable_pipe_a(dev);
9130 }
9131
24929352
DV		 9132 /* Adjust the state of the output pipe according to whether we
9133 * have active connectors/encoders. */
9134 intel_crtc_update_dpms(&crtc->base);
9135
9136 if (crtc->active != crtc->base.enabled) {
9137 struct intel_encoder *encoder;
9138
9139 /* This can happen either due to bugs in the get_hw_state
9140 * functions or because the pipe is force-enabled due to the
9141 * pipe A quirk. */
9142 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9143 crtc->base.base.id,
9144 crtc->base.enabled ? "enabled" : "disabled",
9145 crtc->active ? "enabled" : "disabled");
9146
9147 crtc->base.enabled = crtc->active;
9148
9149 /* Because we only establish the connector -> encoder ->
9150 * crtc links if something is active, this means the
9151 * crtc is now deactivated. Break the links. connector
9152 * -> encoder links are only establish when things are
9153 * actually up, hence no need to break them. */
9154 WARN_ON(crtc->active);
9155
9156 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9157 WARN_ON(encoder->connectors_active);
9158 encoder->base.crtc = NULL;
9159 }
9160 }
9161}
9162
9163static void intel_sanitize_encoder(struct intel_encoder *encoder)
9164{
9165 struct intel_connector *connector;
9166 struct drm_device *dev = encoder->base.dev;
9167
9168 /* We need to check both for a crtc link (meaning that the
9169 * encoder is active and trying to read from a pipe) and the
9170 * pipe itself being active. */
9171 bool has_active_crtc = encoder->base.crtc &&
9172 to_intel_crtc(encoder->base.crtc)->active;
9173
9174 if (encoder->connectors_active && !has_active_crtc) {
9175 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9176 encoder->base.base.id,
9177 drm_get_encoder_name(&encoder->base));
9178
9179 /* Connector is active, but has no active pipe. This is
9180 * fallout from our resume register restoring. Disable
9181 * the encoder manually again. */
9182 if (encoder->base.crtc) {
9183 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9184 encoder->base.base.id,
9185 drm_get_encoder_name(&encoder->base));
9186 encoder->disable(encoder);
9187 }
9188
9189 /* Inconsistent output/port/pipe state happens presumably due to
9190 * a bug in one of the get_hw_state functions. Or someplace else
9191 * in our code, like the register restore mess on resume. Clamp
9192 * things to off as a safer default. */
9193 list_for_each_entry(connector,
9194 &dev->mode_config.connector_list,
9195 base.head) {
9196 if (connector->encoder != encoder)
9197 continue;
9198
9199 intel_connector_break_all_links(connector);
9200 }
9201 }
9202 /* Enabled encoders without active connectors will be fixed in
9203 * the crtc fixup. */
9204}
9205
44cec740 9206void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9207{
9208 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9209 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9210
9211 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9212 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9213 i915_disable_vga(dev);
0fde901f
KM		 9214 }
9215}
9216
24929352
DV		 9217/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9218 * and i915 state tracking structures. */
45e2b5f6
DV		 9219void intel_modeset_setup_hw_state(struct drm_device *dev,
9220 bool force_restore)
24929352
DV		 9221{
9222 struct drm_i915_private *dev_priv = dev->dev_private;
9223 enum pipe pipe;
9224 u32 tmp;
b5644d05 9225 struct drm_plane *plane;
24929352
DV		 9226 struct intel_crtc *crtc;
9227 struct intel_encoder *encoder;
9228 struct intel_connector *connector;
9229
affa9354 9230 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9231 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9232
9233 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9234 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9235 case TRANS_DDI_EDP_INPUT_A_ON:
9236 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9237 pipe = PIPE_A;
9238 break;
9239 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9240 pipe = PIPE_B;
9241 break;
9242 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9243 pipe = PIPE_C;
9244 break;
aaa148ec
DL		 9245 default:
9246 /* A bogus value has been programmed, disable
9247 * the transcoder */
9248 WARN(1, "Bogus eDP source %08x\n", tmp);
9249 intel_ddi_disable_transcoder_func(dev_priv,
9250 TRANSCODER_EDP);
9251 goto setup_pipes;
e28d54cb
PZ		 9252 }
9253
9254 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9255 crtc->cpu_transcoder = TRANSCODER_EDP;
9256
9257 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9258 pipe_name(pipe));
9259 }
9260 }
9261
aaa148ec 9262setup_pipes:
0e8ffe1b
DV		 9263 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9264 base.head) {
88adfff1 9265 memset(&crtc->config, 0, sizeof(crtc->config));
0e8ffe1b
DV		 9266 crtc->active = dev_priv->display.get_pipe_config(crtc,
9267 &crtc->config);
24929352
DV		 9268
9269 crtc->base.enabled = crtc->active;
9270
9271 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9272 crtc->base.base.id,
9273 crtc->active ? "enabled" : "disabled");
9274 }
9275
affa9354 9276 if (HAS_DDI(dev))
6441ab5f
PZ		 9277 intel_ddi_setup_hw_pll_state(dev);
9278
24929352
DV		 9279 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9280 base.head) {
9281 pipe = 0;
9282
9283 if (encoder->get_hw_state(encoder, &pipe)) {
9284 encoder->base.crtc =
9285 dev_priv->pipe_to_crtc_mapping[pipe];
9286 } else {
9287 encoder->base.crtc = NULL;
9288 }
9289
9290 encoder->connectors_active = false;
9291 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9292 encoder->base.base.id,
9293 drm_get_encoder_name(&encoder->base),
9294 encoder->base.crtc ? "enabled" : "disabled",
9295 pipe);
9296 }
9297
9298 list_for_each_entry(connector, &dev->mode_config.connector_list,
9299 base.head) {
9300 if (connector->get_hw_state(connector)) {
9301 connector->base.dpms = DRM_MODE_DPMS_ON;
9302 connector->encoder->connectors_active = true;
9303 connector->base.encoder = &connector->encoder->base;
9304 } else {
9305 connector->base.dpms = DRM_MODE_DPMS_OFF;
9306 connector->base.encoder = NULL;
9307 }
9308 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9309 connector->base.base.id,
9310 drm_get_connector_name(&connector->base),
9311 connector->base.encoder ? "enabled" : "disabled");
9312 }
9313
9314 /* HW state is read out, now we need to sanitize this mess. */
9315 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9316 base.head) {
9317 intel_sanitize_encoder(encoder);
9318 }
9319
9320 for_each_pipe(pipe) {
9321 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9322 intel_sanitize_crtc(crtc);
9323 }
9a935856 9324
45e2b5f6
DV		 9325 if (force_restore) {
9326 for_each_pipe(pipe) {
b5644d05
JB		 9327 struct drm_crtc *crtc =
9328 dev_priv->pipe_to_crtc_mapping[pipe];
9329 intel_crtc_restore_mode(crtc);
45e2b5f6 9330 }
b5644d05
JB		 9331 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9332 intel_plane_restore(plane);
0fde901f
KM		 9333
9334 i915_redisable_vga(dev);
45e2b5f6
DV		 9335 } else {
9336 intel_modeset_update_staged_output_state(dev);
9337 }
8af6cf88
DV		 9338
9339 intel_modeset_check_state(dev);
2e938892
DV		 9340
9341 drm_mode_config_reset(dev);
2c7111db
CW		 9342}
9343
9344void intel_modeset_gem_init(struct drm_device *dev)
9345{
1833b134 9346 intel_modeset_init_hw(dev);
02e792fb
DV		 9347
9348 intel_setup_overlay(dev);
24929352 9349
45e2b5f6 9350 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9351}
9352
9353void intel_modeset_cleanup(struct drm_device *dev)
9354{
652c393a
JB		 9355 struct drm_i915_private *dev_priv = dev->dev_private;
9356 struct drm_crtc *crtc;
9357 struct intel_crtc *intel_crtc;
9358
f87ea761 9359 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9360 mutex_lock(&dev->struct_mutex);
9361
723bfd70
JB		 9362 intel_unregister_dsm_handler();
9363
9364
652c393a
JB		 9365 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9366 /* Skip inactive CRTCs */
9367 if (!crtc->fb)
9368 continue;
9369
9370 intel_crtc = to_intel_crtc(crtc);
3dec0095 9371 intel_increase_pllclock(crtc);
652c393a
JB		 9372 }
9373
973d04f9 9374 intel_disable_fbc(dev);
e70236a8 9375
8090c6b9 9376 intel_disable_gt_powersave(dev);
0cdab21f 9377
930ebb46
DV		 9378 ironlake_teardown_rc6(dev);
9379
57f350b6
JB		 9380 if (IS_VALLEYVIEW(dev))
9381 vlv_init_dpio(dev);
9382
69341a5e
KH		 9383 mutex_unlock(&dev->struct_mutex);
9384
6c0d9350
DV		 9385 /* Disable the irq before mode object teardown, for the irq might
9386 * enqueue unpin/hotplug work. */
9387 drm_irq_uninstall(dev);
9388 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9389 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9390
1630fe75
CW		 9391 /* flush any delayed tasks or pending work */
9392 flush_scheduled_work();
9393
79e53945 9394 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9395
9396 intel_cleanup_overlay(dev);
79e53945
JB		 9397}
9398
f1c79df3
ZW		 9399/*
9400 * Return which encoder is currently attached for connector.
9401 */
df0e9248 9402struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9403{
df0e9248
CW		 9404 return &intel_attached_encoder(connector)->base;
9405}
f1c79df3 9406
df0e9248
CW		 9407void intel_connector_attach_encoder(struct intel_connector *connector,
9408 struct intel_encoder *encoder)
9409{
9410 connector->encoder = encoder;
9411 drm_mode_connector_attach_encoder(&connector->base,
9412 &encoder->base);
79e53945 9413}
28d52043
DA		 9414
9415/*
9416 * set vga decode state - true == enable VGA decode
9417 */
9418int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9419{
9420 struct drm_i915_private *dev_priv = dev->dev_private;
9421 u16 gmch_ctrl;
9422
9423 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9424 if (state)
9425 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9426 else
9427 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9428 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9429 return 0;
9430}
c4a1d9e4
CW		 9431
9432#ifdef CONFIG_DEBUG_FS
9433#include <linux/seq_file.h>
9434
9435struct intel_display_error_state {
9436 struct intel_cursor_error_state {
9437 u32 control;
9438 u32 position;
9439 u32 base;
9440 u32 size;
52331309 9441 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9442
9443 struct intel_pipe_error_state {
9444 u32 conf;
9445 u32 source;
9446
9447 u32 htotal;
9448 u32 hblank;
9449 u32 hsync;
9450 u32 vtotal;
9451 u32 vblank;
9452 u32 vsync;
52331309 9453 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9454
9455 struct intel_plane_error_state {
9456 u32 control;
9457 u32 stride;
9458 u32 size;
9459 u32 pos;
9460 u32 addr;
9461 u32 surface;
9462 u32 tile_offset;
52331309 9463 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9464};
9465
9466struct intel_display_error_state *
9467intel_display_capture_error_state(struct drm_device *dev)
9468{
0206e353 9469 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9470 struct intel_display_error_state *error;
702e7a56 9471 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9472 int i;
9473
9474 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9475 if (error == NULL)
9476 return NULL;
9477
52331309 9478 for_each_pipe(i) {
702e7a56
PZ		 9479 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9480
a18c4c3d
PZ		 9481 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9482 error->cursor[i].control = I915_READ(CURCNTR(i));
9483 error->cursor[i].position = I915_READ(CURPOS(i));
9484 error->cursor[i].base = I915_READ(CURBASE(i));
9485 } else {
9486 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9487 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9488 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9489 }
c4a1d9e4
CW		 9490
9491 error->plane[i].control = I915_READ(DSPCNTR(i));
9492 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9493 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9494 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9495 error->plane[i].pos = I915_READ(DSPPOS(i));
9496 }
ca291363
PZ		 9497 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9498 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9499 if (INTEL_INFO(dev)->gen >= 4) {
9500 error->plane[i].surface = I915_READ(DSPSURF(i));
9501 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9502 }
9503
702e7a56 9504 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9505 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9506 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9507 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9508 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9509 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9510 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9511 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9512 }
9513
9514 return error;
9515}
9516
9517void
9518intel_display_print_error_state(struct seq_file *m,
9519 struct drm_device *dev,
9520 struct intel_display_error_state *error)
9521{
9522 int i;
9523
7eb552ae 9524 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9525 for_each_pipe(i) {
c4a1d9e4
CW		 9526 seq_printf(m, "Pipe [%d]:\n", i);
9527 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9528 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9529 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9530 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9531 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9532 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9533 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9534 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9535
9536 seq_printf(m, "Plane [%d]:\n", i);
9537 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9538 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9539 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9540 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9541 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9542 }
4b71a570 9543 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9544 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9545 if (INTEL_INFO(dev)->gen >= 4) {
9546 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9547 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9548 }
9549
9550 seq_printf(m, "Cursor [%d]:\n", i);
9551 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9552 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9553 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9554 }
9555}
9556#endif
Linux kernel - Deliverables
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